commit 50f8791588f18f879ed7788d6974aced083d9a0f Author: Byron Lathi Date: Tue Apr 14 21:34:37 2026 -0700 initial commit diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..fa42509 --- /dev/null +++ b/.gitignore @@ -0,0 +1,6 @@ +outflow/ +work*/ +embedded_sw/ +sim_build +__pycache__ +.lock \ No newline at end of file diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..9baf7a2 --- /dev/null +++ b/.gitmodules @@ -0,0 +1,6 @@ +[submodule "sub/verilog-6502"] + path = sub/verilog-6502 + url = https://github.com/hoglet67/verilog-6502.git +[submodule "sub/taxi"] + path = sub/taxi + url = git@git.byronlathi.com:bslathi19/taxi.git \ No newline at end of file diff --git a/fpga/constraints.sdc b/fpga/constraints.sdc new file mode 100644 index 0000000..7e3647b --- /dev/null +++ b/fpga/constraints.sdc @@ -0,0 +1,369 @@ + +# Auto-generated by Interface Designer +# +# WARNING: Any manual changes made to this file will be lost when generating constraints. + +# Efinity Interface Designer SDC +# Version: 2024.M.98 +# Date: 2024-04-13 10:16 + +# Copyright (C) 2013 - 2024 Efinix Inc. All rights reserved. + +# Device: Ti375C529 +# Project: Ti375C529_devkit +# Timing Model: C4 (preliminary) +# NOTE: The timing data is not final + +# PLL Constraints +################# +create_clock -period 10.0000 io_sysFbClk +create_clock -period 5.0000 io_peripheralClk +create_clock -period 4.0000 io_ddrMasters_0_clk +create_clock -period 8.0000 io_cfuClk +create_clock -period 10.0000 sd_base_clk +create_clock -period 8.0000 rgmii_rxc +create_clock -waveform {2.0000 6.0000} -period 8.0000 io_tseClk_90 +create_clock -period 8.0000 io_tseClk + +set_clock_groups -exclusive -group {rgmii_rxc io_tseClk_90 io_tseClk} -group {sd_base_clk} -group {io_cfuClk} -group {io_peripheralClk} -group {io_ddrMasters_0_clk} + +# GPIO Constraints +#################### +set_output_delay -clock sd_base_clk -reference_pin [get_ports {sd_base_clk~CLKOUT~347~2}] -max 0.079 [get_ports {sd_clk_hi}] +set_output_delay -clock sd_base_clk -reference_pin [get_ports {sd_base_clk~CLKOUT~347~2}] -min -0.045 [get_ports {sd_clk_hi}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {io_gpio_sw_n}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {io_gpio_sw_n}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {system_uart_0_io_rxd}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {system_uart_0_io_rxd}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_uart_0_io_txd}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_uart_0_io_txd}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_read[1]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_read[1]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_write[1]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_write[1]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_writeEnable[1]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_writeEnable[1]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_read[2]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_read[2]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_write[2]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_write[2]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_writeEnable[2]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_writeEnable[2]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {system_i2c_0_io_scl_read}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {system_i2c_0_io_scl_read}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_i2c_0_io_scl_write}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_i2c_0_io_scl_write}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_i2c_0_io_scl_writeEnable}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_i2c_0_io_scl_writeEnable}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {system_i2c_0_io_sda_read}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {system_i2c_0_io_sda_read}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_i2c_0_io_sda_write}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_i2c_0_io_sda_write}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_i2c_0_io_sda_writeEnable}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_i2c_0_io_sda_writeEnable}] + +# JTAG Constraints +#################### +create_clock -period 100 [get_ports {jtagCtrl_tck}] +set_output_delay -clock jtagCtrl_tck -max 0.117 [get_ports {ut_jtagCtrl_tdo}] +set_output_delay -clock jtagCtrl_tck -min -0.075 [get_ports {ut_jtagCtrl_tdo}] +set_input_delay -clock_fall -clock jtagCtrl_tck -max 0.280 [get_ports {ut_jtagCtrl_capture}] +set_input_delay -clock_fall -clock jtagCtrl_tck -min 0.187 [get_ports {ut_jtagCtrl_capture}] +set_input_delay -clock_fall -clock jtagCtrl_tck -max 0.280 [get_ports {ut_jtagCtrl_reset}] +set_input_delay -clock_fall -clock jtagCtrl_tck -min 0.187 [get_ports {ut_jtagCtrl_reset}] +set_input_delay -clock_fall -clock jtagCtrl_tck -max 0.243 [get_ports {ut_jtagCtrl_enable}] +set_input_delay -clock_fall -clock jtagCtrl_tck -min 0.162 [get_ports {ut_jtagCtrl_enable}] +set_input_delay -clock_fall -clock jtagCtrl_tck -max 0.280 [get_ports {ut_jtagCtrl_update}] +set_input_delay -clock_fall -clock jtagCtrl_tck -min 0.187 [get_ports {ut_jtagCtrl_update}] +set_input_delay -clock_fall -clock jtagCtrl_tck -max 0.337 [get_ports {ut_jtagCtrl_shift}] +set_input_delay -clock_fall -clock jtagCtrl_tck -min 0.225 [get_ports {ut_jtagCtrl_shift}] +# JTAG Constraints (extra... not used by current Efinity debug tools) +# Create separate clock groups for JTAG clocks. Remove DRCK clock from the list below if it is not defined. +# set_clock_groups -asynchronous -group {jtagCtrl_tck} + +# HSIO GPIO Constraints +######################### +set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~391~964}] -max 0.414 [get_ports {rgmii_rx_ctl_LO rgmii_rx_ctl_HI}] +set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~391~964}] -min 0.276 [get_ports {rgmii_rx_ctl_LO rgmii_rx_ctl_HI}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {rgmii_rxc_phy}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {rgmii_rxc_phy}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {rgmii_rxc_slow}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {rgmii_rxc_slow}] +set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~395~964}] -max 0.414 [get_ports {rgmii_rxd_LO[0] rgmii_rxd_HI[0]}] +set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~395~964}] -min 0.276 [get_ports {rgmii_rxd_LO[0] rgmii_rxd_HI[0]}] +set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~397~964}] -max 0.414 [get_ports {rgmii_rxd_LO[1] rgmii_rxd_HI[1]}] +set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~397~964}] -min 0.276 [get_ports {rgmii_rxd_LO[1] rgmii_rxd_HI[1]}] +set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~408~964}] -max 0.414 [get_ports {rgmii_rxd_LO[2] rgmii_rxd_HI[2]}] +set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~408~964}] -min 0.276 [get_ports {rgmii_rxd_LO[2] rgmii_rxd_HI[2]}] +set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~412~963}] -max 0.414 [get_ports {rgmii_rxd_LO[3] rgmii_rxd_HI[3]}] +set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~412~963}] -min 0.276 [get_ports {rgmii_rxd_LO[3] rgmii_rxd_HI[3]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {sd_cd_n}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {sd_cd_n}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {io_ddrMasters_memCheck_pass}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {io_ddrMasters_memCheck_pass}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {phy_mdc}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {phy_mdc}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~352~963}] -max 0.263 [get_ports {rgmii_tx_ctl_LO rgmii_tx_ctl_HI}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~352~963}] -min -0.140 [get_ports {rgmii_tx_ctl_LO rgmii_tx_ctl_HI}] +set_output_delay -clock io_tseClk_90 -reference_pin [get_ports {io_tseClk_90~CLKOUT~359~964}] -max 0.263 [get_ports {rgmii_txc_LO rgmii_txc_HI}] +set_output_delay -clock io_tseClk_90 -reference_pin [get_ports {io_tseClk_90~CLKOUT~359~964}] -min -0.140 [get_ports {rgmii_txc_LO rgmii_txc_HI}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~358~963}] -max 0.263 [get_ports {rgmii_txd_LO[0] rgmii_txd_HI[0]}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~358~963}] -min -0.140 [get_ports {rgmii_txd_LO[0] rgmii_txd_HI[0]}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~364~963}] -max 0.263 [get_ports {rgmii_txd_LO[1] rgmii_txd_HI[1]}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~364~963}] -min -0.140 [get_ports {rgmii_txd_LO[1] rgmii_txd_HI[1]}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~365~964}] -max 0.263 [get_ports {rgmii_txd_LO[2] rgmii_txd_HI[2]}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~365~964}] -min -0.140 [get_ports {rgmii_txd_LO[2] rgmii_txd_HI[2]}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~376~964}] -max 0.263 [get_ports {rgmii_txd_LO[3] rgmii_txd_HI[3]}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~376~964}] -min -0.140 [get_ports {rgmii_txd_LO[3] rgmii_txd_HI[3]}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~418~2}] -max 0.263 [get_ports {system_spi_0_io_sclk_write}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~418~2}] -min -0.140 [get_ports {system_spi_0_io_sclk_write}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~407~2}] -max 0.263 [get_ports {system_spi_0_io_ss[0]}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~407~2}] -min -0.140 [get_ports {system_spi_0_io_ss[0]}] +set_input_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~381~964}] -max 0.414 [get_ports {phy_mdi}] +set_input_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~381~964}] -min 0.276 [get_ports {phy_mdi}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~384~964}] -max 0.263 [get_ports {phy_mdo}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~384~964}] -min -0.140 [get_ports {phy_mdo}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~384~964}] -max 0.263 [get_ports {phy_mdo_en}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~384~964}] -min -0.140 [get_ports {phy_mdo_en}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_read[0]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_read[0]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_write[0]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_write[0]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_writeEnable[0]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_writeEnable[0]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_read[3]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_read[3]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_write[3]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_write[3]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_writeEnable[3]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_writeEnable[3]}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~418~1}] -max 0.414 [get_ports {system_spi_0_io_data_0_read}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~418~1}] -min 0.276 [get_ports {system_spi_0_io_data_0_read}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~422~2}] -max 0.263 [get_ports {system_spi_0_io_data_0_write}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~422~2}] -min -0.140 [get_ports {system_spi_0_io_data_0_write}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~422~2}] -max 0.263 [get_ports {system_spi_0_io_data_0_writeEnable}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~422~2}] -min -0.140 [get_ports {system_spi_0_io_data_0_writeEnable}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~425~1}] -max 0.414 [get_ports {system_spi_0_io_data_1_read}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~425~1}] -min 0.276 [get_ports {system_spi_0_io_data_1_read}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~420~1}] -max 0.263 [get_ports {system_spi_0_io_data_1_write}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~420~1}] -min -0.140 [get_ports {system_spi_0_io_data_1_write}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~420~1}] -max 0.263 [get_ports {system_spi_0_io_data_1_writeEnable}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~420~1}] -min -0.140 [get_ports {system_spi_0_io_data_1_writeEnable}] + +# QCRV32 Constraints +####################### +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.701 [get_ports {io_ddrMasters_0_reset}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.340 [get_ports {io_ddrMasters_0_reset}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.196 [get_ports {io_ddrMasters_0_ar_payload_addr[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.071 [get_ports {io_ddrMasters_0_ar_payload_addr[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.217 [get_ports {io_ddrMasters_0_ar_payload_burst[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.034 [get_ports {io_ddrMasters_0_ar_payload_burst[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.222 [get_ports {io_ddrMasters_0_ar_payload_cache[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.020 [get_ports {io_ddrMasters_0_ar_payload_cache[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.247 [get_ports {io_ddrMasters_0_ar_payload_id[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.038 [get_ports {io_ddrMasters_0_ar_payload_id[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.251 [get_ports {io_ddrMasters_0_ar_payload_len[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.008 [get_ports {io_ddrMasters_0_ar_payload_len[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.226 [get_ports {io_ddrMasters_0_ar_payload_lock}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.054 [get_ports {io_ddrMasters_0_ar_payload_lock}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.265 [get_ports {io_ddrMasters_0_ar_payload_prot[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.006 [get_ports {io_ddrMasters_0_ar_payload_prot[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.191 [get_ports {io_ddrMasters_0_ar_payload_qos[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.013 [get_ports {io_ddrMasters_0_ar_payload_qos[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.259 [get_ports {io_ddrMasters_0_ar_payload_region[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.018 [get_ports {io_ddrMasters_0_ar_payload_region[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.219 [get_ports {io_ddrMasters_0_ar_payload_size[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.007 [get_ports {io_ddrMasters_0_ar_payload_size[*]}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 1.064 [get_ports {io_ddrMasters_0_ar_ready}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.544 [get_ports {io_ddrMasters_0_ar_ready}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.025 [get_ports {io_ddrMasters_0_ar_valid}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.051 [get_ports {io_ddrMasters_0_ar_valid}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 1.031 [get_ports {io_ddrMasters_0_r_payload_data[*]}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.347 [get_ports {io_ddrMasters_0_r_payload_data[*]}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.844 [get_ports {io_ddrMasters_0_r_payload_last}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.387 [get_ports {io_ddrMasters_0_r_payload_last}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.426 [get_ports {io_ddrMasters_0_r_ready}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.095 [get_ports {io_ddrMasters_0_r_ready}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.965 [get_ports {io_ddrMasters_0_r_valid}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.508 [get_ports {io_ddrMasters_0_r_valid}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.372 [get_ports {io_ddrMasters_0_aw_payload_addr[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.005 [get_ports {io_ddrMasters_0_aw_payload_addr[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.296 [get_ports {io_ddrMasters_0_aw_payload_allStrb}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.016 [get_ports {io_ddrMasters_0_aw_payload_allStrb}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.217 [get_ports {io_ddrMasters_0_aw_payload_burst[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.002 [get_ports {io_ddrMasters_0_aw_payload_burst[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.217 [get_ports {io_ddrMasters_0_aw_payload_cache[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.027 [get_ports {io_ddrMasters_0_aw_payload_cache[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.238 [get_ports {io_ddrMasters_0_aw_payload_id[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.001 [get_ports {io_ddrMasters_0_aw_payload_id[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.280 [get_ports {io_ddrMasters_0_aw_payload_len[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.003 [get_ports {io_ddrMasters_0_aw_payload_len[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.205 [get_ports {io_ddrMasters_0_aw_payload_lock}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.022 [get_ports {io_ddrMasters_0_aw_payload_lock}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.178 [get_ports {io_ddrMasters_0_aw_payload_prot[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.039 [get_ports {io_ddrMasters_0_aw_payload_prot[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.243 [get_ports {io_ddrMasters_0_aw_payload_qos[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.053 [get_ports {io_ddrMasters_0_aw_payload_qos[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.253 [get_ports {io_ddrMasters_0_aw_payload_region[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.008 [get_ports {io_ddrMasters_0_aw_payload_region[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.263 [get_ports {io_ddrMasters_0_aw_payload_size[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.007 [get_ports {io_ddrMasters_0_aw_payload_size[*]}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 1.213 [get_ports {io_ddrMasters_0_aw_ready}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.610 [get_ports {io_ddrMasters_0_aw_ready}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.294 [get_ports {io_ddrMasters_0_aw_valid}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.058 [get_ports {io_ddrMasters_0_aw_valid}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.289 [get_ports {io_ddrMasters_0_w_payload_data[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.105 [get_ports {io_ddrMasters_0_w_payload_data[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.042 [get_ports {io_ddrMasters_0_w_payload_last}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.053 [get_ports {io_ddrMasters_0_w_payload_last}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.130 [get_ports {io_ddrMasters_0_w_payload_strb[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.070 [get_ports {io_ddrMasters_0_w_payload_strb[*]}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 1.193 [get_ports {io_ddrMasters_0_w_ready}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.616 [get_ports {io_ddrMasters_0_w_ready}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.118 [get_ports {io_ddrMasters_0_w_valid}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.038 [get_ports {io_ddrMasters_0_w_valid}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.196 [get_ports {io_ddrMasters_0_b_ready}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.012 [get_ports {io_ddrMasters_0_b_ready}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.991 [get_ports {io_ddrMasters_0_b_valid}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.514 [get_ports {io_ddrMasters_0_b_valid}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.766 [get_ports {axiAInterrupt}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.322 [get_ports {axiAInterrupt}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 1.089 [get_ports {axiA_araddr[*]}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.425 [get_ports {axiA_araddr[*]}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 1.134 [get_ports {axiA_arlen[*]}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.484 [get_ports {axiA_arlen[*]}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.285 [get_ports {axiA_arready}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.074 [get_ports {axiA_arready}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.824 [get_ports {axiA_arvalid}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.444 [get_ports {axiA_arvalid}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.660 [get_ports {axiA_rdata[*]}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.018 [get_ports {axiA_rdata[*]}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.384 [get_ports {axiA_rlast}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.068 [get_ports {axiA_rlast}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 1.305 [get_ports {axiA_rready}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.647 [get_ports {axiA_rready}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.460 [get_ports {axiA_rresp[*]}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.113 [get_ports {axiA_rresp[*]}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.344 [get_ports {axiA_rvalid}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.071 [get_ports {axiA_rvalid}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.710 [get_ports {axiA_awaddr[*]}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.344 [get_ports {axiA_awaddr[*]}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.753 [get_ports {axiA_awlen[*]}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.363 [get_ports {axiA_awlen[*]}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.156 [get_ports {axiA_awready}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min -0.017 [get_ports {axiA_awready}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.674 [get_ports {axiA_awvalid}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.354 [get_ports {axiA_awvalid}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 1.000 [get_ports {axiA_wdata[*]}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.373 [get_ports {axiA_wdata[*]}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.933 [get_ports {axiA_wlast}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.494 [get_ports {axiA_wlast}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.155 [get_ports {axiA_wready}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min -0.018 [get_ports {axiA_wready}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 1.021 [get_ports {axiA_wstrb[*]}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.491 [get_ports {axiA_wstrb[*]}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.799 [get_ports {axiA_wvalid}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.414 [get_ports {axiA_wvalid}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.944 [get_ports {axiA_bready}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.494 [get_ports {axiA_bready}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.315 [get_ports {axiA_bresp[*]}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.064 [get_ports {axiA_bresp[*]}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.251 [get_ports {axiA_bvalid}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.052 [get_ports {axiA_bvalid}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.730 [get_ports {io_peripheralReset}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.386 [get_ports {io_peripheralReset}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.777 [get_ports {cpu0_customInstruction_cmd_ready}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.246 [get_ports {cpu0_customInstruction_cmd_ready}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.488 [get_ports {cpu0_customInstruction_cmd_valid}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.776 [get_ports {cpu0_customInstruction_cmd_valid}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.500 [get_ports {cpu0_customInstruction_function_id[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.637 [get_ports {cpu0_customInstruction_function_id[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.545 [get_ports {cpu0_customInstruction_inputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.612 [get_ports {cpu0_customInstruction_inputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.428 [get_ports {cpu0_customInstruction_inputs_1[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.625 [get_ports {cpu0_customInstruction_inputs_1[*]}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.844 [get_ports {cpu0_customInstruction_outputs_0[*]}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.147 [get_ports {cpu0_customInstruction_outputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.401 [get_ports {cpu0_customInstruction_rsp_ready}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.746 [get_ports {cpu0_customInstruction_rsp_ready}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.864 [get_ports {cpu0_customInstruction_rsp_valid}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.251 [get_ports {cpu0_customInstruction_rsp_valid}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.947 [get_ports {cpu1_customInstruction_cmd_ready}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.300 [get_ports {cpu1_customInstruction_cmd_ready}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.580 [get_ports {cpu1_customInstruction_cmd_valid}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.804 [get_ports {cpu1_customInstruction_cmd_valid}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.849 [get_ports {cpu1_customInstruction_function_id[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.720 [get_ports {cpu1_customInstruction_function_id[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.956 [get_ports {cpu1_customInstruction_inputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.752 [get_ports {cpu1_customInstruction_inputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.810 [get_ports {cpu1_customInstruction_inputs_1[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.748 [get_ports {cpu1_customInstruction_inputs_1[*]}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.052 [get_ports {cpu1_customInstruction_outputs_0[*]}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.169 [get_ports {cpu1_customInstruction_outputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.643 [get_ports {cpu1_customInstruction_rsp_ready}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.869 [get_ports {cpu1_customInstruction_rsp_ready}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.800 [get_ports {cpu1_customInstruction_rsp_valid}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.278 [get_ports {cpu1_customInstruction_rsp_valid}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.863 [get_ports {cpu2_customInstruction_cmd_ready}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.325 [get_ports {cpu2_customInstruction_cmd_ready}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.757 [get_ports {cpu2_customInstruction_cmd_valid}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.841 [get_ports {cpu2_customInstruction_cmd_valid}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.667 [get_ports {cpu2_customInstruction_function_id[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.801 [get_ports {cpu2_customInstruction_function_id[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.848 [get_ports {cpu2_customInstruction_inputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.750 [get_ports {cpu2_customInstruction_inputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.750 [get_ports {cpu2_customInstruction_inputs_1[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.762 [get_ports {cpu2_customInstruction_inputs_1[*]}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.950 [get_ports {cpu2_customInstruction_outputs_0[*]}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.234 [get_ports {cpu2_customInstruction_outputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.745 [get_ports {cpu2_customInstruction_rsp_ready}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.931 [get_ports {cpu2_customInstruction_rsp_ready}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.726 [get_ports {cpu2_customInstruction_rsp_valid}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.277 [get_ports {cpu2_customInstruction_rsp_valid}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.730 [get_ports {cpu3_customInstruction_cmd_ready}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.297 [get_ports {cpu3_customInstruction_cmd_ready}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.529 [get_ports {cpu3_customInstruction_cmd_valid}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.830 [get_ports {cpu3_customInstruction_cmd_valid}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.677 [get_ports {cpu3_customInstruction_function_id[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.788 [get_ports {cpu3_customInstruction_function_id[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.677 [get_ports {cpu3_customInstruction_inputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.770 [get_ports {cpu3_customInstruction_inputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.741 [get_ports {cpu3_customInstruction_inputs_1[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.769 [get_ports {cpu3_customInstruction_inputs_1[*]}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.074 [get_ports {cpu3_customInstruction_outputs_0[*]}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.200 [get_ports {cpu3_customInstruction_outputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.685 [get_ports {cpu3_customInstruction_rsp_ready}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.913 [get_ports {cpu3_customInstruction_rsp_ready}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.756 [get_ports {cpu3_customInstruction_rsp_valid}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.319 [get_ports {cpu3_customInstruction_rsp_valid}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 1.058 [get_ports {jtagCtrl_capture}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.420 [get_ports {jtagCtrl_capture}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 1.423 [get_ports {jtagCtrl_enable}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.374 [get_ports {jtagCtrl_enable}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 1.313 [get_ports {jtagCtrl_reset}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.436 [get_ports {jtagCtrl_reset}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 1.379 [get_ports {jtagCtrl_shift}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.399 [get_ports {jtagCtrl_shift}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 0.687 [get_ports {jtagCtrl_tdi}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.304 [get_ports {jtagCtrl_tdi}] +set_input_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 2.055 [get_ports {jtagCtrl_tdo}] +set_input_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.906 [get_ports {jtagCtrl_tdo}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 1.351 [get_ports {jtagCtrl_update}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.425 [get_ports {jtagCtrl_update}] + +# Clock Latency Constraints +############################ +# set_clock_latency -source -setup [get_ports {io_sysFbClk}] +# set_clock_latency -source -hold [get_ports {io_sysFbClk}] +# set_clock_latency -source -setup [get_ports {io_systemClk}] +# set_clock_latency -source -hold [get_ports {io_systemClk}] +# set_clock_latency -source -setup [get_ports {io_memoryClk}] +# set_clock_latency -source -hold [get_ports {io_memoryClk}] +# set_clock_latency -source -setup [get_ports {io_memFbClk}] +# set_clock_latency -source -hold [get_ports {io_memFbClk}] +# set_clock_latency -source -setup [get_ports {io_peripheralClk}] +# set_clock_latency -source -hold [get_ports {io_peripheralClk}] +# set_clock_latency -source -setup [get_ports {io_ddrMasters_0_clk}] +# set_clock_latency -source -hold [get_ports {io_ddrMasters_0_clk}] +# set_clock_latency -source -setup [get_ports {io_cfuClk}] +# set_clock_latency -source -hold [get_ports {io_cfuClk}] diff --git a/fpga/fpga6502.peri.xml b/fpga/fpga6502.peri.xml new file mode 100644 index 0000000..3d41495 --- /dev/null +++ b/fpga/fpga6502.peri.xml @@ -0,0 +1,852 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/fpga6502.xml b/fpga/fpga6502.xml new file mode 100644 index 0000000..e421b36 --- /dev/null +++ b/fpga/fpga6502.xml @@ -0,0 +1,150 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb.v b/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb.v new file mode 100644 index 0000000..80a2457 --- /dev/null +++ b/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb.v @@ -0,0 +1,8651 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 1.22.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _035069daf0ad4fb491e9c65d79bd2ddd +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module EfxSapphireHpSoc_slb +( + input io_peripheralClk, + input io_peripheralReset, + output io_asyncReset, + input io_gpio_sw_n, + input pll_peripheral_locked, + input pll_system_locked, + output jtagCtrl_capture, + output jtagCtrl_enable, + output jtagCtrl_reset, + output jtagCtrl_shift, + output jtagCtrl_tdi, + input jtagCtrl_tdo, + output jtagCtrl_update, + input ut_jtagCtrl_capture, + input ut_jtagCtrl_enable, + input ut_jtagCtrl_reset, + input ut_jtagCtrl_shift, + input ut_jtagCtrl_tdi, + output ut_jtagCtrl_tdo, + input ut_jtagCtrl_update, + input system_spi_0_io_data_0_read, + output system_spi_0_io_data_0_write, + output system_spi_0_io_data_0_writeEnable, + input system_spi_0_io_data_1_read, + output system_spi_0_io_data_1_write, + output system_spi_0_io_data_1_writeEnable, + input system_spi_0_io_data_2_read, + output system_spi_0_io_data_2_write, + output system_spi_0_io_data_2_writeEnable, + input system_spi_0_io_data_3_read, + output system_spi_0_io_data_3_write, + output system_spi_0_io_data_3_writeEnable, + output system_spi_0_io_sclk_write, + output [3:0] system_spi_0_io_ss, + input system_uart_0_io_rxd, + output system_uart_0_io_txd, + input system_i2c_0_io_scl_read, + output system_i2c_0_io_scl_write, + input system_i2c_0_io_sda_read, + input [3:0] system_gpio_0_io_read, + output [3:0] system_gpio_0_io_write, + output [3:0] system_gpio_0_io_writeEnable, + input cfg_done, + output cfg_start, + output cfg_sel, + output cfg_reset, + output axiAInterrupt, + input [31:0] axiA_awaddr, + input [7:0] axiA_awlen, + input [2:0] axiA_awsize, + input [1:0] axiA_awburst, + input axiA_awlock, + input [3:0] axiA_awcache, + input [2:0] axiA_awprot, + input [3:0] axiA_awqos, + input [3:0] axiA_awregion, + input axiA_awvalid, + output axiA_awready, + input [31:0] axiA_wdata, + input [3:0] axiA_wstrb, + input axiA_wvalid, + input axiA_wlast, + output axiA_wready, + output [1:0] axiA_bresp, + output axiA_bvalid, + input axiA_bready, + input [31:0] axiA_araddr, + input [7:0] axiA_arlen, + input [2:0] axiA_arsize, + input [1:0] axiA_arburst, + input axiA_arlock, + input [3:0] axiA_arcache, + input [2:0] axiA_arprot, + input [3:0] axiA_arqos, + input [3:0] axiA_arregion, + input axiA_arvalid, + output axiA_arready, + output [31:0] axiA_rdata, + output [1:0] axiA_rresp, + output axiA_rlast, + output axiA_rvalid, + input axiA_rready, + output userInterruptA, + output userInterruptB, + output userInterruptC, + output userInterruptD, + output userInterruptE, + output userInterruptF, + output [31:0] io_apbSlave_0_PADDR, + output io_apbSlave_0_PENABLE, + input [31:0] io_apbSlave_0_PRDATA, + input io_apbSlave_0_PREADY, + output io_apbSlave_0_PSEL, + input io_apbSlave_0_PSLVERROR, + output [31:0] io_apbSlave_0_PWDATA, + output io_apbSlave_0_PWRITE, + output system_i2c_0_io_sda_write, + output system_i2c_0_io_sda_writeEnable, + output system_i2c_0_io_scl_writeEnable, + output system_watchdog_hardPanic_reset +); +`IP_MODULE_NAME(Axi4Peripheral_wrapper) +#( + .PERI_FREQ (200) +) +u_Axi4Peripheral_wrapper +( + .io_peripheralClk ( io_peripheralClk ), + .io_peripheralReset ( io_peripheralReset ), + .io_asyncReset ( io_asyncReset ), + .io_gpio_sw_n ( io_gpio_sw_n ), + .pll_peripheral_locked ( pll_peripheral_locked ), + .pll_system_locked ( pll_system_locked ), + .jtagCtrl_capture ( jtagCtrl_capture ), + .jtagCtrl_enable ( jtagCtrl_enable ), + .jtagCtrl_reset ( jtagCtrl_reset ), + .jtagCtrl_shift ( jtagCtrl_shift ), + .jtagCtrl_tdi ( jtagCtrl_tdi ), + .jtagCtrl_tdo ( jtagCtrl_tdo ), + .jtagCtrl_update ( jtagCtrl_update ), + .ut_jtagCtrl_capture ( ut_jtagCtrl_capture ), + .ut_jtagCtrl_enable ( ut_jtagCtrl_enable ), + .ut_jtagCtrl_reset ( ut_jtagCtrl_reset ), + .ut_jtagCtrl_shift ( ut_jtagCtrl_shift ), + .ut_jtagCtrl_tdi ( ut_jtagCtrl_tdi ), + .ut_jtagCtrl_tdo ( ut_jtagCtrl_tdo ), + .ut_jtagCtrl_update ( ut_jtagCtrl_update ), + .system_spi_0_io_data_0_read ( system_spi_0_io_data_0_read ), + .system_spi_0_io_data_0_write ( system_spi_0_io_data_0_write ), + .system_spi_0_io_data_0_writeEnable ( system_spi_0_io_data_0_writeEnable ), + .system_spi_0_io_data_1_read ( system_spi_0_io_data_1_read ), + .system_spi_0_io_data_1_write ( system_spi_0_io_data_1_write ), + .system_spi_0_io_data_1_writeEnable ( system_spi_0_io_data_1_writeEnable ), + .system_spi_0_io_data_2_read ( system_spi_0_io_data_2_read ), + .system_spi_0_io_data_2_write ( system_spi_0_io_data_2_write ), + .system_spi_0_io_data_2_writeEnable ( system_spi_0_io_data_2_writeEnable ), + .system_spi_0_io_data_3_read ( system_spi_0_io_data_3_read ), + .system_spi_0_io_data_3_write ( system_spi_0_io_data_3_write ), + .system_spi_0_io_data_3_writeEnable ( system_spi_0_io_data_3_writeEnable ), + .system_spi_0_io_sclk_write ( system_spi_0_io_sclk_write ), + .system_spi_0_io_ss ( system_spi_0_io_ss ), + .system_uart_0_io_rxd ( system_uart_0_io_rxd ), + .system_uart_0_io_txd ( system_uart_0_io_txd ), + .system_i2c_0_io_scl_read ( system_i2c_0_io_scl_read ), + .system_i2c_0_io_scl_write ( system_i2c_0_io_scl_write ), + .system_i2c_0_io_sda_read ( system_i2c_0_io_sda_read ), + .system_gpio_0_io_read ( system_gpio_0_io_read ), + .system_gpio_0_io_write ( system_gpio_0_io_write ), + .system_gpio_0_io_writeEnable ( system_gpio_0_io_writeEnable ), + .cfg_done ( cfg_done ), + .cfg_start ( cfg_start ), + .cfg_sel ( cfg_sel ), + .cfg_reset ( cfg_reset ), + .axiAInterrupt ( axiAInterrupt ), + .axiA_awaddr ( axiA_awaddr ), + .axiA_awlen ( axiA_awlen ), + .axiA_awsize ( axiA_awsize ), + .axiA_awburst ( axiA_awburst ), + .axiA_awlock ( axiA_awlock ), + .axiA_awcache ( axiA_awcache ), + .axiA_awprot ( axiA_awprot ), + .axiA_awqos ( axiA_awqos ), + .axiA_awregion ( axiA_awregion ), + .axiA_awvalid ( axiA_awvalid ), + .axiA_awready ( axiA_awready ), + .axiA_wdata ( axiA_wdata ), + .axiA_wstrb ( axiA_wstrb ), + .axiA_wvalid ( axiA_wvalid ), + .axiA_wlast ( axiA_wlast ), + .axiA_wready ( axiA_wready ), + .axiA_bresp ( axiA_bresp ), + .axiA_bvalid ( axiA_bvalid ), + .axiA_bready ( axiA_bready ), + .axiA_araddr ( axiA_araddr ), + .axiA_arlen ( axiA_arlen ), + .axiA_arsize ( axiA_arsize ), + .axiA_arburst ( axiA_arburst ), + .axiA_arlock ( axiA_arlock ), + .axiA_arcache ( axiA_arcache ), + .axiA_arprot ( axiA_arprot ), + .axiA_arqos ( axiA_arqos ), + .axiA_arregion ( axiA_arregion ), + .axiA_arvalid ( axiA_arvalid ), + .axiA_arready ( axiA_arready ), + .axiA_rdata ( axiA_rdata ), + .axiA_rresp ( axiA_rresp ), + .axiA_rlast ( axiA_rlast ), + .axiA_rvalid ( axiA_rvalid ), + .axiA_rready ( axiA_rready ), + .userInterruptA ( userInterruptA ), + .userInterruptB ( userInterruptB ), + .userInterruptC ( userInterruptC ), + .userInterruptD ( userInterruptD ), + .userInterruptE ( userInterruptE ), + .userInterruptF ( userInterruptF ), + .io_apbSlave_0_PADDR ( io_apbSlave_0_PADDR ), + .io_apbSlave_0_PENABLE ( io_apbSlave_0_PENABLE ), + .io_apbSlave_0_PRDATA ( io_apbSlave_0_PRDATA ), + .io_apbSlave_0_PREADY ( io_apbSlave_0_PREADY ), + .io_apbSlave_0_PSEL ( io_apbSlave_0_PSEL ), + .io_apbSlave_0_PSLVERROR ( io_apbSlave_0_PSLVERROR ), + .io_apbSlave_0_PWDATA ( io_apbSlave_0_PWDATA ), + .io_apbSlave_0_PWRITE ( io_apbSlave_0_PWRITE ), + .system_i2c_0_io_sda_write ( system_i2c_0_io_sda_write ), + .system_i2c_0_io_sda_writeEnable ( system_i2c_0_io_sda_writeEnable ), + .system_i2c_0_io_scl_writeEnable ( system_i2c_0_io_scl_writeEnable ), + .system_watchdog_hardPanic_reset ( system_watchdog_hardPanic_reset ) +); +endmodule + +module `IP_MODULE_NAME(Axi4Peripheral_wrapper) #( +parameter PERI_FREQ=250 +)( +output system_i2c_0_io_sda_writeEnable, +output system_i2c_0_io_sda_write, +input system_i2c_0_io_sda_read, +output system_i2c_0_io_scl_writeEnable, +output system_i2c_0_io_scl_write, +input system_i2c_0_io_scl_read, +output userInterruptB, +input [3:0] system_gpio_0_io_read, +output [3:0] system_gpio_0_io_write, +output [3:0] system_gpio_0_io_writeEnable, +output userInterruptD, +output system_spi_0_io_sclk_write, +output system_spi_0_io_data_0_writeEnable, +input system_spi_0_io_data_0_read, +output system_spi_0_io_data_0_write, +output system_spi_0_io_data_1_writeEnable, +input system_spi_0_io_data_1_read, +output system_spi_0_io_data_1_write, +output system_spi_0_io_data_2_writeEnable, +input system_spi_0_io_data_2_read, +output system_spi_0_io_data_2_write, +output system_spi_0_io_data_3_writeEnable, +input system_spi_0_io_data_3_read, +output system_spi_0_io_data_3_write, +output [3:0] system_spi_0_io_ss, +output userInterruptE, +output userInterruptF, +output [15:0] io_apbSlave_0_PADDR, +output io_apbSlave_0_PSEL, +output io_apbSlave_0_PENABLE, +input io_apbSlave_0_PREADY, +output io_apbSlave_0_PWRITE, +output [31:0] io_apbSlave_0_PWDATA, +input [31:0] io_apbSlave_0_PRDATA, +input io_apbSlave_0_PSLVERROR, +output jtagCtrl_tdi, +input jtagCtrl_tdo, +output jtagCtrl_enable, +output jtagCtrl_capture, +output jtagCtrl_shift, +output jtagCtrl_update, +output jtagCtrl_reset, +input ut_jtagCtrl_tdi, +output ut_jtagCtrl_tdo, +input ut_jtagCtrl_enable, +input ut_jtagCtrl_capture, +input ut_jtagCtrl_shift, +input ut_jtagCtrl_update, +input ut_jtagCtrl_reset, +output system_uart_0_io_txd, +input system_uart_0_io_rxd, +output userInterruptA, +output userInterruptC, +output system_watchdog_hardPanic_reset, +input [31:0] axiA_awaddr, +input [7:0] axiA_awlen, +input [2:0] axiA_awsize, +input [1:0] axiA_awburst, +input axiA_awlock, +input [3:0] axiA_awcache, +input [2:0] axiA_awprot, +input [3:0] axiA_awqos, +input [3:0] axiA_awregion, +input axiA_awvalid, +output axiA_awready, +input [31:0] axiA_wdata, +input [3:0] axiA_wstrb, +input axiA_wvalid, +input axiA_wlast, +output axiA_wready, +output [1:0] axiA_bresp, +output axiA_bvalid, +input axiA_bready, +input [31:0] axiA_araddr, +input [7:0] axiA_arlen, +input [2:0] axiA_arsize, +input [1:0] axiA_arburst, +input axiA_arlock, +input [3:0] axiA_arcache, +input [2:0] axiA_arprot, +input [3:0] axiA_arqos, +input [3:0] axiA_arregion, +input axiA_arvalid, +output axiA_arready, +output [31:0] axiA_rdata, +output [1:0] axiA_rresp, +output axiA_rlast, +output axiA_rvalid, +input axiA_rready, +output axiAInterrupt, +input cfg_done, +output cfg_start, +output cfg_sel, +output cfg_reset, +input io_peripheralClk, +input io_peripheralReset, +output io_asyncReset, +input io_gpio_sw_n, +input pll_peripheral_locked, +input pll_system_locked +); + +wire flag_ok; +wire system_watchdog_softPanic_interrupt; +wire system_i2c_0_io_interrupt; +wire system_gpio_0_io_interrupt_0; +wire system_gpio_0_io_interrupt_1; +wire system_uart_0_io_interrupt; +wire system_spi_0_io_interrupt; + + +`IP_MODULE_NAME(lppdr4_init) u_lppdr4_init ( +.io_peripheralClk (io_peripheralClk), +.io_peripheralReset (io_peripheralReset), +.io_gpio_sw_n (io_gpio_sw_n), +.flag_ok (flag_ok), +.cfg_done (cfg_done), +.cfg_start (cfg_start), +.cfg_sel (cfg_sel), +.cfg_reset (cfg_reset) +); + +assign io_asyncReset = ~(io_gpio_sw_n & + pll_peripheral_locked & + pll_system_locked & + flag_ok); + +assign userInterruptA = system_uart_0_io_interrupt; +assign userInterruptB = system_spi_0_io_interrupt; +assign userInterruptC = system_i2c_0_io_interrupt; +assign userInterruptD = system_gpio_0_io_interrupt_0; +assign userInterruptE = system_gpio_0_io_interrupt_1; +assign userInterruptF = system_watchdog_softPanic_interrupt; + +assign jtagCtrl_capture = ut_jtagCtrl_capture; +assign jtagCtrl_enable = ut_jtagCtrl_enable; +assign jtagCtrl_reset = ut_jtagCtrl_reset; +assign jtagCtrl_shift = ut_jtagCtrl_shift; +assign jtagCtrl_tdi = ut_jtagCtrl_tdi; +assign jtagCtrl_update = ut_jtagCtrl_update; +assign ut_jtagCtrl_tdo = jtagCtrl_tdo; + + +assign system_i2c_0_io_sda_writeEnable=!system_i2c_0_io_sda_write; +assign system_i2c_0_io_scl_writeEnable=!system_i2c_0_io_scl_write; + + +//axi4 bridge to various I/O +Axi4PeripheralTop_035069daf0ad4fb491e9c65d79bd2ddd u_Axi4PeripheralTop( +.io_apbSlave_0_PADDR(io_apbSlave_0_PADDR), +.io_apbSlave_0_PSEL(io_apbSlave_0_PSEL), +.io_apbSlave_0_PENABLE(io_apbSlave_0_PENABLE), +.io_apbSlave_0_PREADY(io_apbSlave_0_PREADY), +.io_apbSlave_0_PWRITE(io_apbSlave_0_PWRITE), +.io_apbSlave_0_PWDATA(io_apbSlave_0_PWDATA), +.io_apbSlave_0_PRDATA(io_apbSlave_0_PRDATA), +.io_apbSlave_0_PSLVERROR(io_apbSlave_0_PSLVERROR), +.system_uart_0_io_interrupt(system_uart_0_io_interrupt), +.system_uart_0_io_txd(system_uart_0_io_txd), +.system_uart_0_io_rxd(system_uart_0_io_rxd), +.system_spi_0_io_interrupt(system_spi_0_io_interrupt), +.system_spi_0_io_sclk_write(system_spi_0_io_sclk_write), +.system_spi_0_io_data_0_writeEnable(system_spi_0_io_data_0_writeEnable), +.system_spi_0_io_data_0_read(system_spi_0_io_data_0_read), +.system_spi_0_io_data_0_write(system_spi_0_io_data_0_write), +.system_spi_0_io_data_1_writeEnable(system_spi_0_io_data_1_writeEnable), +.system_spi_0_io_data_1_read(system_spi_0_io_data_1_read), +.system_spi_0_io_data_1_write(system_spi_0_io_data_1_write), +.system_spi_0_io_data_2_writeEnable(system_spi_0_io_data_2_writeEnable), +.system_spi_0_io_data_2_read(system_spi_0_io_data_2_read), +.system_spi_0_io_data_2_write(system_spi_0_io_data_2_write), +.system_spi_0_io_data_3_writeEnable(system_spi_0_io_data_3_writeEnable), +.system_spi_0_io_data_3_read(system_spi_0_io_data_3_read), +.system_spi_0_io_data_3_write(system_spi_0_io_data_3_write), +.system_spi_0_io_ss(system_spi_0_io_ss), +.system_watchdog_hardPanic_reset(system_watchdog_hardPanic_reset), +.system_watchdog_logic_panics_0(system_watchdog_softPanic_interrupt), +.system_gpio_0_io_interrupts_0(system_gpio_0_io_interrupt_0), +.system_gpio_0_io_interrupts_1(system_gpio_0_io_interrupt_1), +.system_gpio_0_io_read(system_gpio_0_io_read), +.system_gpio_0_io_write(system_gpio_0_io_write), +.system_gpio_0_io_writeEnable(system_gpio_0_io_writeEnable), +.system_i2c_0_io_interrupt(system_i2c_0_io_interrupt), +.system_i2c_0_io_sda_write(system_i2c_0_io_sda_write), +.system_i2c_0_io_sda_read(system_i2c_0_io_sda_read), +.system_i2c_0_io_scl_write(system_i2c_0_io_scl_write), +.system_i2c_0_io_scl_read(system_i2c_0_io_scl_read), +.axi_awvalid(axiA_awvalid), +.axi_awready(axiA_awready), +.axi_awaddr(axiA_awaddr[23:0]), +.axi_awlen(axiA_awlen), +.axi_awsize(axiA_awsize), +.axi_awcache(axiA_awcache), +.axi_awprot(axiA_awprot), +.axi_wvalid(axiA_wvalid), +.axi_wready(axiA_wready), +.axi_wdata(axiA_wdata), +.axi_wstrb(axiA_wstrb), +.axi_wlast(axiA_wlast), +.axi_bvalid(axiA_bvalid), +.axi_bready(axiA_bready), +.axi_bresp(axiA_bresp), +.axi_arvalid(axiA_arvalid), +.axi_arready(axiA_arready), +.axi_araddr(axiA_araddr[23:0]), +.axi_arlen(axiA_arlen), +.axi_arsize(axiA_arsize), +.axi_arcache(axiA_arcache), +.axi_arprot(axiA_arprot), +.axi_rvalid(axiA_rvalid), +.axi_rready(axiA_rready), +.axi_rdata(axiA_rdata), +.axi_rresp(axiA_rresp), +.axi_rlast(axiA_rlast), +.clk(io_peripheralClk), +.reset(io_peripheralReset) +); +assign axiAInterrupt = 1'b0; + +endmodule + + +module `IP_MODULE_NAME(lppdr4_init) ( + input io_peripheralClk, + input io_peripheralReset, + input io_gpio_sw_n, + output reg flag_ok, + input cfg_done, + output cfg_start, + output cfg_sel, + output cfg_reset +); + +localparam [1:0] IDLE = 2'b00, + CFG_START = 2'b01, + CFG_DONE = 2'b11; + +reg [1:0] cfg_st, + cfg_next; +reg [7:0] cfg_count; +wire cfg_ok; +reg [1:0] buf_reset; +wire dmReset; + +always@(posedge io_peripheralClk) +begin + buf_reset[1] <= io_peripheralReset; + buf_reset[0] <= buf_reset[1]; +end + +assign dmReset = (~buf_reset[0] & buf_reset[1]); + +always@(posedge io_peripheralClk or negedge io_gpio_sw_n) +begin + if(!io_gpio_sw_n) + flag_ok <= 1'b0; + else + begin + if(cfg_st == CFG_DONE) + flag_ok <= 1'b1; + else + flag_ok <= flag_ok; + end +end + +always@(posedge io_peripheralClk or negedge io_gpio_sw_n) +begin + if(!io_gpio_sw_n || dmReset) + cfg_st <= IDLE; + else + cfg_st <= cfg_next; +end + +always@(*) +begin + cfg_next = cfg_st; + case(cfg_st) + IDLE: + begin + if(cfg_count == 'hff) + cfg_next = CFG_START; + else + cfg_next = IDLE; + end + CFG_START: + begin + if(cfg_done) + cfg_next = CFG_DONE; + else + cfg_next = CFG_START; + end + CFG_DONE: + cfg_next = CFG_DONE; + default: + cfg_next = IDLE; + endcase +end + +assign cfg_start = (cfg_st != IDLE); +assign cfg_ok = (cfg_st == CFG_DONE); +assign cfg_reset = (cfg_st == IDLE); +assign cfg_sel = 1'b0; + +always@(posedge io_peripheralClk) +begin + if(cfg_st == IDLE) + cfg_count <= cfg_count + 1'b1; + else + cfg_count <= 'h0; +end + +endmodule + + +// Generator : SpinalHDL dev git head : a69f4b9a329be784802c37cd8038b7dc9aec3094 +// Component : Axi4PeripheralTop_035069daf0ad4fb491e9c65d79bd2ddd +// Git hash : 176b956330f07bda5e095857b387c403a78f8448 + +`timescale 1ns/1ps + +module Axi4PeripheralTop_035069daf0ad4fb491e9c65d79bd2ddd ( + input wire axi_awvalid, + output wire axi_awready, + input wire [23:0] axi_awaddr, + input wire [7:0] axi_awlen, + input wire [2:0] axi_awsize, + input wire [3:0] axi_awcache, + input wire [2:0] axi_awprot, + input wire axi_wvalid, + output wire axi_wready, + input wire [31:0] axi_wdata, + input wire [3:0] axi_wstrb, + input wire axi_wlast, + output wire axi_bvalid, + input wire axi_bready, + output wire [1:0] axi_bresp, + input wire axi_arvalid, + output wire axi_arready, + input wire [23:0] axi_araddr, + input wire [7:0] axi_arlen, + input wire [2:0] axi_arsize, + input wire [3:0] axi_arcache, + input wire [2:0] axi_arprot, + output wire axi_rvalid, + input wire axi_rready, + output wire [31:0] axi_rdata, + output wire [1:0] axi_rresp, + output wire axi_rlast, + output wire system_uart_0_io_txd, + input wire system_uart_0_io_rxd, + output wire system_i2c_0_io_sda_write, + input wire system_i2c_0_io_sda_read, + output wire system_i2c_0_io_scl_write, + input wire system_i2c_0_io_scl_read, + input wire [3:0] system_gpio_0_io_read, + output wire [3:0] system_gpio_0_io_write, + output wire [3:0] system_gpio_0_io_writeEnable, + output wire [15:0] io_apbSlave_0_PADDR, + output wire [0:0] io_apbSlave_0_PSEL, + output wire io_apbSlave_0_PENABLE, + input wire io_apbSlave_0_PREADY, + output wire io_apbSlave_0_PWRITE, + output wire [31:0] io_apbSlave_0_PWDATA, + input wire [31:0] io_apbSlave_0_PRDATA, + input wire io_apbSlave_0_PSLVERROR, + output wire system_uart_0_io_interrupt, + output wire system_spi_0_io_interrupt, + output wire [0:0] system_spi_0_io_sclk_write, + output wire system_spi_0_io_data_0_writeEnable, + input wire [0:0] system_spi_0_io_data_0_read, + output wire [0:0] system_spi_0_io_data_0_write, + output wire system_spi_0_io_data_1_writeEnable, + input wire [0:0] system_spi_0_io_data_1_read, + output wire [0:0] system_spi_0_io_data_1_write, + output wire system_spi_0_io_data_2_writeEnable, + input wire [0:0] system_spi_0_io_data_2_read, + output wire [0:0] system_spi_0_io_data_2_write, + output wire system_spi_0_io_data_3_writeEnable, + input wire [0:0] system_spi_0_io_data_3_read, + output wire [0:0] system_spi_0_io_data_3_write, + output wire [3:0] system_spi_0_io_ss, + output wire system_i2c_0_io_interrupt, + output wire system_gpio_0_io_interrupts_0, + output wire system_gpio_0_io_interrupts_1, + output wire system_watchdog_logic_panics_0, + output wire system_watchdog_hardPanic_reset, + input wire clk, + input wire reset +); + + wire streamArbiter_io_inputs_0_ready; + wire streamArbiter_io_inputs_1_ready; + wire streamArbiter_io_output_valid; + wire [23:0] streamArbiter_io_output_payload_addr; + wire [7:0] streamArbiter_io_output_payload_len; + wire [2:0] streamArbiter_io_output_payload_size; + wire [3:0] streamArbiter_io_output_payload_cache; + wire [2:0] streamArbiter_io_output_payload_prot; + wire [0:0] streamArbiter_io_chosen; + wire [1:0] streamArbiter_io_chosenOH; + wire axiToBmb_io_axi_arw_ready; + wire axiToBmb_io_axi_w_ready; + wire axiToBmb_io_axi_b_valid; + wire [1:0] axiToBmb_io_axi_b_payload_resp; + wire axiToBmb_io_axi_r_valid; + wire [31:0] axiToBmb_io_axi_r_payload_data; + wire [1:0] axiToBmb_io_axi_r_payload_resp; + wire axiToBmb_io_axi_r_payload_last; + wire axiToBmb_io_bmb_cmd_valid; + wire axiToBmb_io_bmb_cmd_payload_last; + wire [0:0] axiToBmb_io_bmb_cmd_payload_fragment_source; + wire [0:0] axiToBmb_io_bmb_cmd_payload_fragment_opcode; + wire [23:0] axiToBmb_io_bmb_cmd_payload_fragment_address; + wire [9:0] axiToBmb_io_bmb_cmd_payload_fragment_length; + wire [31:0] axiToBmb_io_bmb_cmd_payload_fragment_data; + wire [3:0] axiToBmb_io_bmb_cmd_payload_fragment_mask; + wire axiToBmb_io_bmb_rsp_ready; + wire bmbHandle_decoder_io_input_cmd_ready; + wire bmbHandle_decoder_io_input_rsp_valid; + wire bmbHandle_decoder_io_input_rsp_payload_last; + wire [0:0] bmbHandle_decoder_io_input_rsp_payload_fragment_source; + wire [0:0] bmbHandle_decoder_io_input_rsp_payload_fragment_opcode; + wire [31:0] bmbHandle_decoder_io_input_rsp_payload_fragment_data; + wire bmbHandle_decoder_io_outputs_0_cmd_valid; + wire bmbHandle_decoder_io_outputs_0_cmd_payload_last; + wire [0:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_source; + wire [0:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_opcode; + wire [23:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_address; + wire [9:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_length; + wire [31:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_data; + wire [3:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_mask; + wire bmbHandle_decoder_io_outputs_0_rsp_ready; + wire bmbHandle_unburstify_io_input_cmd_ready; + wire bmbHandle_unburstify_io_input_rsp_valid; + wire bmbHandle_unburstify_io_input_rsp_payload_last; + wire [0:0] bmbHandle_unburstify_io_input_rsp_payload_fragment_source; + wire [0:0] bmbHandle_unburstify_io_input_rsp_payload_fragment_opcode; + wire [31:0] bmbHandle_unburstify_io_input_rsp_payload_fragment_data; + wire bmbHandle_unburstify_io_output_cmd_valid; + wire bmbHandle_unburstify_io_output_cmd_payload_last; + wire [0:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_opcode; + wire [23:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_address; + wire [1:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_length; + wire [31:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_data; + wire [3:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_mask; + wire [2:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_context; + wire bmbHandle_unburstify_io_output_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_input_cmd_ready; + wire bmbPeripheral_bmb_decoder_io_input_rsp_valid; + wire bmbPeripheral_bmb_decoder_io_input_rsp_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode; + wire [31:0] bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data; + wire [2:0] bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_outputs_5_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_5_rsp_ready; + wire system_uart_0_io_logic_io_bus_cmd_ready; + wire system_uart_0_io_logic_io_bus_rsp_valid; + wire system_uart_0_io_logic_io_bus_rsp_payload_last; + wire [0:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode; + wire [31:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_data; + wire [2:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_context; + wire system_uart_0_io_logic_io_uart_txd; + wire system_uart_0_io_logic_system_uart_0_io_interrupt_source; + wire system_spi_0_io_logic_io_ctrl_cmd_ready; + wire system_spi_0_io_logic_io_ctrl_rsp_valid; + wire system_spi_0_io_logic_io_ctrl_rsp_payload_last; + wire [0:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; + wire [31:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data; + wire [2:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context; + wire [0:0] system_spi_0_io_logic_io_spi_sclk_write; + wire [3:0] system_spi_0_io_logic_io_spi_ss; + wire [0:0] system_spi_0_io_logic_io_spi_data_0_write; + wire system_spi_0_io_logic_io_spi_data_0_writeEnable; + wire [0:0] system_spi_0_io_logic_io_spi_data_1_write; + wire system_spi_0_io_logic_io_spi_data_1_writeEnable; + wire [0:0] system_spi_0_io_logic_io_spi_data_2_write; + wire system_spi_0_io_logic_io_spi_data_2_writeEnable; + wire [0:0] system_spi_0_io_logic_io_spi_data_3_write; + wire system_spi_0_io_logic_io_spi_data_3_writeEnable; + wire system_spi_0_io_logic_system_spi_0_io_interrupt_source; + wire system_i2c_0_io_logic_io_ctrl_cmd_ready; + wire system_i2c_0_io_logic_io_ctrl_rsp_valid; + wire system_i2c_0_io_logic_io_ctrl_rsp_payload_last; + wire [0:0] system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; + wire [31:0] system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_data; + wire [2:0] system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_context; + wire system_i2c_0_io_logic_io_i2c_scl_write; + wire system_i2c_0_io_logic_io_i2c_sda_write; + wire system_i2c_0_io_logic_system_i2c_0_io_interrupt_source; + wire [3:0] system_gpio_0_io_logic_io_gpio_write; + wire [3:0] system_gpio_0_io_logic_io_gpio_writeEnable; + wire system_gpio_0_io_logic_io_bus_cmd_ready; + wire system_gpio_0_io_logic_io_bus_rsp_valid; + wire system_gpio_0_io_logic_io_bus_rsp_payload_last; + wire [0:0] system_gpio_0_io_logic_io_bus_rsp_payload_fragment_opcode; + wire [31:0] system_gpio_0_io_logic_io_bus_rsp_payload_fragment_data; + wire [2:0] system_gpio_0_io_logic_io_bus_rsp_payload_fragment_context; + wire [3:0] system_gpio_0_io_logic_io_interrupt; + wire system_watchdog_logic_logic_io_bus_cmd_ready; + wire system_watchdog_logic_logic_io_bus_rsp_valid; + wire system_watchdog_logic_logic_io_bus_rsp_payload_last; + wire [0:0] system_watchdog_logic_logic_io_bus_rsp_payload_fragment_opcode; + wire [31:0] system_watchdog_logic_logic_io_bus_rsp_payload_fragment_data; + wire [2:0] system_watchdog_logic_logic_io_bus_rsp_payload_fragment_context; + wire [1:0] system_watchdog_logic_logic_io_panics; + wire io_apbSlave_0_logic_io_input_cmd_ready; + wire io_apbSlave_0_logic_io_input_rsp_valid; + wire io_apbSlave_0_logic_io_input_rsp_payload_last; + wire [0:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode; + wire [31:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_data; + wire [2:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_context; + wire [15:0] io_apbSlave_0_logic_io_output_PADDR; + wire [0:0] io_apbSlave_0_logic_io_output_PSEL; + wire io_apbSlave_0_logic_io_output_PENABLE; + wire io_apbSlave_0_logic_io_output_PWRITE; + wire [31:0] io_apbSlave_0_logic_io_output_PWDATA; + wire _zz_axiShared_b_ready; + wire _zz_axiShared_r_ready; + wire axi_aw_halfPipe_valid; + wire axi_aw_halfPipe_ready; + wire [23:0] axi_aw_halfPipe_payload_addr; + wire [7:0] axi_aw_halfPipe_payload_len; + wire [2:0] axi_aw_halfPipe_payload_size; + wire [3:0] axi_aw_halfPipe_payload_cache; + wire [2:0] axi_aw_halfPipe_payload_prot; + reg axi_aw_rValid; + wire axi_aw_halfPipe_fire; + reg [23:0] axi_aw_rData_addr; + reg [7:0] axi_aw_rData_len; + reg [2:0] axi_aw_rData_size; + reg [3:0] axi_aw_rData_cache; + reg [2:0] axi_aw_rData_prot; + wire axi_w_halfPipe_valid; + wire axi_w_halfPipe_ready; + wire [31:0] axi_w_halfPipe_payload_data; + wire [3:0] axi_w_halfPipe_payload_strb; + wire axi_w_halfPipe_payload_last; + reg axi_w_rValid; + wire axi_w_halfPipe_fire; + reg [31:0] axi_w_rData_data; + reg [3:0] axi_w_rData_strb; + reg axi_w_rData_last; + wire _zz_axi_bvalid; + reg _zz_axi_bvalid_1; + reg [1:0] _zz_axi_bresp; + wire axi_ar_halfPipe_valid; + wire axi_ar_halfPipe_ready; + wire [23:0] axi_ar_halfPipe_payload_addr; + wire [7:0] axi_ar_halfPipe_payload_len; + wire [2:0] axi_ar_halfPipe_payload_size; + wire [3:0] axi_ar_halfPipe_payload_cache; + wire [2:0] axi_ar_halfPipe_payload_prot; + reg axi_ar_rValid; + wire axi_ar_halfPipe_fire; + reg [23:0] axi_ar_rData_addr; + reg [7:0] axi_ar_rData_len; + reg [2:0] axi_ar_rData_size; + reg [3:0] axi_ar_rData_cache; + reg [2:0] axi_ar_rData_prot; + wire _zz_axi_rvalid; + reg _zz_axi_rvalid_1; + reg [31:0] _zz_axi_rdata; + reg [1:0] _zz_axi_rresp; + reg _zz_axi_rlast; + wire axiShared_arw_valid; + wire axiShared_arw_ready; + wire [23:0] axiShared_arw_payload_addr; + wire [7:0] axiShared_arw_payload_len; + wire [2:0] axiShared_arw_payload_size; + wire [3:0] axiShared_arw_payload_cache; + wire [2:0] axiShared_arw_payload_prot; + wire axiShared_arw_payload_write; + wire axiShared_w_valid; + wire axiShared_w_ready; + wire [31:0] axiShared_w_payload_data; + wire [3:0] axiShared_w_payload_strb; + wire axiShared_w_payload_last; + wire axiShared_b_valid; + wire axiShared_b_ready; + wire [1:0] axiShared_b_payload_resp; + wire axiShared_r_valid; + wire axiShared_r_ready; + wire [31:0] axiShared_r_payload_data; + wire [1:0] axiShared_r_payload_resp; + wire axiShared_r_payload_last; + wire bmbPeripheral_bmb_cmd_valid; + wire bmbPeripheral_bmb_cmd_ready; + wire bmbPeripheral_bmb_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_rsp_valid; + wire bmbPeripheral_bmb_rsp_ready; + wire bmbPeripheral_bmb_rsp_payload_last; + wire [0:0] bmbPeripheral_bmb_rsp_payload_fragment_opcode; + wire [31:0] bmbPeripheral_bmb_rsp_payload_fragment_data; + wire [2:0] bmbPeripheral_bmb_rsp_payload_fragment_context; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_gpio_0_io_interrupts_0_source; + wire system_gpio_0_io_interrupts_1_source; + wire system_gpio_0_io_interrupts_2; + wire system_gpio_0_io_interrupts_3; + wire system_watchdog_logic_panics_0_source; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire _zz_io_bus_rsp_ready; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last; + wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode; + wire [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address; + wire [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length; + wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data; + wire [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context; + reg system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire; + reg system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + reg [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + reg [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + reg [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + reg [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + reg [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + wire _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + reg _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + reg _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + reg [0:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + reg [31:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + reg [2:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last; + wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode; + wire [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address; + wire [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length; + wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data; + wire [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context; + reg system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire; + reg system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + reg [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + reg [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + reg [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + reg [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + reg [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [7:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last; + wire [0:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode; + wire [7:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address; + wire [1:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length; + wire [31:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data; + wire [2:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context; + reg system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire; + reg system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + reg [0:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + reg [7:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + reg [1:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + reg [31:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + reg [2:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [7:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [7:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [15:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire bmbPeripheral_bmb_withoutMask_cmd_valid; + wire bmbPeripheral_bmb_withoutMask_cmd_ready; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_withoutMask_rsp_valid; + wire bmbPeripheral_bmb_withoutMask_rsp_ready; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context; + wire bmbPeripheral_bmb_withoutMask_cmd_valid_1; + wire bmbPeripheral_bmb_withoutMask_cmd_ready_1; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_1; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1; + wire bmbPeripheral_bmb_withoutMask_rsp_valid_1; + wire bmbPeripheral_bmb_withoutMask_rsp_ready_1; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_1; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1; + wire bmbPeripheral_bmb_withoutMask_cmd_valid_2; + wire bmbPeripheral_bmb_withoutMask_cmd_ready_2; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_2; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2; + wire bmbPeripheral_bmb_withoutMask_rsp_valid_2; + wire bmbPeripheral_bmb_withoutMask_rsp_ready_2; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_2; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2; + wire bmbPeripheral_bmb_withoutMask_cmd_valid_3; + wire bmbPeripheral_bmb_withoutMask_cmd_ready_3; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_3; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3; + wire bmbPeripheral_bmb_withoutMask_rsp_valid_3; + wire bmbPeripheral_bmb_withoutMask_rsp_ready_3; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_3; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3; + wire bmbPeripheral_bmb_withoutMask_cmd_valid_4; + wire bmbPeripheral_bmb_withoutMask_cmd_ready_4; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_4; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4; + wire bmbPeripheral_bmb_withoutMask_rsp_valid_4; + wire bmbPeripheral_bmb_withoutMask_rsp_ready_4; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_4; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4; + wire bmbPeripheral_bmb_withoutMask_cmd_valid_5; + wire bmbPeripheral_bmb_withoutMask_cmd_ready_5; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_5; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_5; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_5; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_5; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_5; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_5; + wire bmbPeripheral_bmb_withoutMask_rsp_valid_5; + wire bmbPeripheral_bmb_withoutMask_rsp_ready_5; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_5; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_5; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_5; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_5; + + Axi4PeripheralStreamArbiter_035069daf0ad4fb491e9c65d79bd2ddd streamArbiter ( + .io_inputs_0_valid (axi_ar_halfPipe_valid ), //i + .io_inputs_0_ready (streamArbiter_io_inputs_0_ready ), //o + .io_inputs_0_payload_addr (axi_ar_halfPipe_payload_addr[23:0] ), //i + .io_inputs_0_payload_len (axi_ar_halfPipe_payload_len[7:0] ), //i + .io_inputs_0_payload_size (axi_ar_halfPipe_payload_size[2:0] ), //i + .io_inputs_0_payload_cache (axi_ar_halfPipe_payload_cache[3:0] ), //i + .io_inputs_0_payload_prot (axi_ar_halfPipe_payload_prot[2:0] ), //i + .io_inputs_1_valid (axi_aw_halfPipe_valid ), //i + .io_inputs_1_ready (streamArbiter_io_inputs_1_ready ), //o + .io_inputs_1_payload_addr (axi_aw_halfPipe_payload_addr[23:0] ), //i + .io_inputs_1_payload_len (axi_aw_halfPipe_payload_len[7:0] ), //i + .io_inputs_1_payload_size (axi_aw_halfPipe_payload_size[2:0] ), //i + .io_inputs_1_payload_cache (axi_aw_halfPipe_payload_cache[3:0] ), //i + .io_inputs_1_payload_prot (axi_aw_halfPipe_payload_prot[2:0] ), //i + .io_output_valid (streamArbiter_io_output_valid ), //o + .io_output_ready (axiShared_arw_ready ), //i + .io_output_payload_addr (streamArbiter_io_output_payload_addr[23:0]), //o + .io_output_payload_len (streamArbiter_io_output_payload_len[7:0] ), //o + .io_output_payload_size (streamArbiter_io_output_payload_size[2:0] ), //o + .io_output_payload_cache (streamArbiter_io_output_payload_cache[3:0]), //o + .io_output_payload_prot (streamArbiter_io_output_payload_prot[2:0] ), //o + .io_chosen (streamArbiter_io_chosen ), //o + .io_chosenOH (streamArbiter_io_chosenOH[1:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralAxi4SharedToBmb_035069daf0ad4fb491e9c65d79bd2ddd axiToBmb ( + .io_axi_arw_valid (axiShared_arw_valid ), //i + .io_axi_arw_ready (axiToBmb_io_axi_arw_ready ), //o + .io_axi_arw_payload_addr (axiShared_arw_payload_addr[23:0] ), //i + .io_axi_arw_payload_len (axiShared_arw_payload_len[7:0] ), //i + .io_axi_arw_payload_size (axiShared_arw_payload_size[2:0] ), //i + .io_axi_arw_payload_cache (axiShared_arw_payload_cache[3:0] ), //i + .io_axi_arw_payload_prot (axiShared_arw_payload_prot[2:0] ), //i + .io_axi_arw_payload_write (axiShared_arw_payload_write ), //i + .io_axi_w_valid (axiShared_w_valid ), //i + .io_axi_w_ready (axiToBmb_io_axi_w_ready ), //o + .io_axi_w_payload_data (axiShared_w_payload_data[31:0] ), //i + .io_axi_w_payload_strb (axiShared_w_payload_strb[3:0] ), //i + .io_axi_w_payload_last (axiShared_w_payload_last ), //i + .io_axi_b_valid (axiToBmb_io_axi_b_valid ), //o + .io_axi_b_ready (axiShared_b_ready ), //i + .io_axi_b_payload_resp (axiToBmb_io_axi_b_payload_resp[1:0] ), //o + .io_axi_r_valid (axiToBmb_io_axi_r_valid ), //o + .io_axi_r_ready (axiShared_r_ready ), //i + .io_axi_r_payload_data (axiToBmb_io_axi_r_payload_data[31:0] ), //o + .io_axi_r_payload_resp (axiToBmb_io_axi_r_payload_resp[1:0] ), //o + .io_axi_r_payload_last (axiToBmb_io_axi_r_payload_last ), //o + .io_bmb_cmd_valid (axiToBmb_io_bmb_cmd_valid ), //o + .io_bmb_cmd_ready (bmbHandle_decoder_io_input_cmd_ready ), //i + .io_bmb_cmd_payload_last (axiToBmb_io_bmb_cmd_payload_last ), //o + .io_bmb_cmd_payload_fragment_source (axiToBmb_io_bmb_cmd_payload_fragment_source ), //o + .io_bmb_cmd_payload_fragment_opcode (axiToBmb_io_bmb_cmd_payload_fragment_opcode ), //o + .io_bmb_cmd_payload_fragment_address (axiToBmb_io_bmb_cmd_payload_fragment_address[23:0] ), //o + .io_bmb_cmd_payload_fragment_length (axiToBmb_io_bmb_cmd_payload_fragment_length[9:0] ), //o + .io_bmb_cmd_payload_fragment_data (axiToBmb_io_bmb_cmd_payload_fragment_data[31:0] ), //o + .io_bmb_cmd_payload_fragment_mask (axiToBmb_io_bmb_cmd_payload_fragment_mask[3:0] ), //o + .io_bmb_rsp_valid (bmbHandle_decoder_io_input_rsp_valid ), //i + .io_bmb_rsp_ready (axiToBmb_io_bmb_rsp_ready ), //o + .io_bmb_rsp_payload_last (bmbHandle_decoder_io_input_rsp_payload_last ), //i + .io_bmb_rsp_payload_fragment_source (bmbHandle_decoder_io_input_rsp_payload_fragment_source ), //i + .io_bmb_rsp_payload_fragment_opcode (bmbHandle_decoder_io_input_rsp_payload_fragment_opcode ), //i + .io_bmb_rsp_payload_fragment_data (bmbHandle_decoder_io_input_rsp_payload_fragment_data[31:0]) //i + ); + Axi4PeripheralBmbDecoder_035069daf0ad4fb491e9c65d79bd2ddd bmbHandle_decoder ( + .io_input_cmd_valid (axiToBmb_io_bmb_cmd_valid ), //i + .io_input_cmd_ready (bmbHandle_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (axiToBmb_io_bmb_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (axiToBmb_io_bmb_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (axiToBmb_io_bmb_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (axiToBmb_io_bmb_cmd_payload_fragment_address[23:0] ), //i + .io_input_cmd_payload_fragment_length (axiToBmb_io_bmb_cmd_payload_fragment_length[9:0] ), //i + .io_input_cmd_payload_fragment_data (axiToBmb_io_bmb_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (axiToBmb_io_bmb_cmd_payload_fragment_mask[3:0] ), //i + .io_input_rsp_valid (bmbHandle_decoder_io_input_rsp_valid ), //o + .io_input_rsp_ready (axiToBmb_io_bmb_rsp_ready ), //i + .io_input_rsp_payload_last (bmbHandle_decoder_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (bmbHandle_decoder_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (bmbHandle_decoder_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (bmbHandle_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_valid (bmbHandle_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (bmbHandle_unburstify_io_input_cmd_ready ), //i + .io_outputs_0_cmd_payload_last (bmbHandle_decoder_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_source (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_source ), //o + .io_outputs_0_cmd_payload_fragment_opcode (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_address[23:0]), //o + .io_outputs_0_cmd_payload_fragment_length (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_length[9:0] ), //o + .io_outputs_0_cmd_payload_fragment_data (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_mask (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_0_rsp_valid (bmbHandle_unburstify_io_input_rsp_valid ), //i + .io_outputs_0_rsp_ready (bmbHandle_decoder_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (bmbHandle_unburstify_io_input_rsp_payload_last ), //i + .io_outputs_0_rsp_payload_fragment_source (bmbHandle_unburstify_io_input_rsp_payload_fragment_source ), //i + .io_outputs_0_rsp_payload_fragment_opcode (bmbHandle_unburstify_io_input_rsp_payload_fragment_opcode ), //i + .io_outputs_0_rsp_payload_fragment_data (bmbHandle_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbUnburstify_035069daf0ad4fb491e9c65d79bd2ddd bmbHandle_unburstify ( + .io_input_cmd_valid (bmbHandle_decoder_io_outputs_0_cmd_valid ), //i + .io_input_cmd_ready (bmbHandle_unburstify_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (bmbHandle_decoder_io_outputs_0_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_address[23:0] ), //i + .io_input_cmd_payload_fragment_length (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_length[9:0] ), //i + .io_input_cmd_payload_fragment_data (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //i + .io_input_rsp_valid (bmbHandle_unburstify_io_input_rsp_valid ), //o + .io_input_rsp_ready (bmbHandle_decoder_io_outputs_0_rsp_ready ), //i + .io_input_rsp_payload_last (bmbHandle_unburstify_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (bmbHandle_unburstify_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (bmbHandle_unburstify_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (bmbHandle_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_output_cmd_valid (bmbHandle_unburstify_io_output_cmd_valid ), //o + .io_output_cmd_ready (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i + .io_output_cmd_payload_last (bmbHandle_unburstify_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (bmbHandle_unburstify_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (bmbHandle_unburstify_io_output_cmd_payload_fragment_address[23:0] ), //o + .io_output_cmd_payload_fragment_length (bmbHandle_unburstify_io_output_cmd_payload_fragment_length[1:0] ), //o + .io_output_cmd_payload_fragment_data (bmbHandle_unburstify_io_output_cmd_payload_fragment_data[31:0] ), //o + .io_output_cmd_payload_fragment_mask (bmbHandle_unburstify_io_output_cmd_payload_fragment_mask[3:0] ), //o + .io_output_cmd_payload_fragment_context (bmbHandle_unburstify_io_output_cmd_payload_fragment_context[2:0] ), //o + .io_output_rsp_valid (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i + .io_output_rsp_ready (bmbHandle_unburstify_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0] ), //i + .io_output_rsp_payload_fragment_context (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context[2:0]), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbDecoder_1_035069daf0ad4fb491e9c65d79bd2ddd bmbPeripheral_bmb_decoder ( + .io_input_cmd_valid (bmbPeripheral_bmb_cmd_valid ), //i + .io_input_cmd_ready (bmbPeripheral_bmb_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (bmbPeripheral_bmb_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (bmbPeripheral_bmb_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (bmbPeripheral_bmb_cmd_payload_fragment_address[23:0] ), //i + .io_input_cmd_payload_fragment_length (bmbPeripheral_bmb_cmd_payload_fragment_length[1:0] ), //i + .io_input_cmd_payload_fragment_data (bmbPeripheral_bmb_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (bmbPeripheral_bmb_cmd_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (bmbPeripheral_bmb_cmd_payload_fragment_context[2:0] ), //i + .io_input_rsp_valid (bmbPeripheral_bmb_decoder_io_input_rsp_valid ), //o + .io_input_rsp_ready (bmbPeripheral_bmb_rsp_ready ), //i + .io_input_rsp_payload_last (bmbPeripheral_bmb_decoder_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context[2:0] ), //o + .io_outputs_0_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready ), //i + .io_outputs_0_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[23:0]), //o + .io_outputs_0_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_0_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_0_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_0_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid ), //i + .io_outputs_0_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last ), //i + .io_outputs_0_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode ), //i + .io_outputs_0_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data[31:0] ), //i + .io_outputs_0_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context[2:0] ), //i + .io_outputs_1_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid ), //o + .io_outputs_1_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_1 ), //i + .io_outputs_1_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last ), //o + .io_outputs_1_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //o + .io_outputs_1_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[23:0]), //o + .io_outputs_1_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_1_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_1_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_1_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_1_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_1 ), //i + .io_outputs_1_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready ), //o + .io_outputs_1_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 ), //i + .io_outputs_1_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 ), //i + .io_outputs_1_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1[31:0] ), //i + .io_outputs_1_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1[2:0] ), //i + .io_outputs_2_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid ), //o + .io_outputs_2_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_2 ), //i + .io_outputs_2_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last ), //o + .io_outputs_2_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode ), //o + .io_outputs_2_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address[23:0]), //o + .io_outputs_2_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_2_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_2_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_2_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_2_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_2 ), //i + .io_outputs_2_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready ), //o + .io_outputs_2_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 ), //i + .io_outputs_2_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 ), //i + .io_outputs_2_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2[31:0] ), //i + .io_outputs_2_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2[2:0] ), //i + .io_outputs_3_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid ), //o + .io_outputs_3_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_3 ), //i + .io_outputs_3_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last ), //o + .io_outputs_3_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode ), //o + .io_outputs_3_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address[23:0]), //o + .io_outputs_3_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_3_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_3_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_3_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_3_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_3 ), //i + .io_outputs_3_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready ), //o + .io_outputs_3_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 ), //i + .io_outputs_3_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 ), //i + .io_outputs_3_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3[31:0] ), //i + .io_outputs_3_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3[2:0] ), //i + .io_outputs_4_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid ), //o + .io_outputs_4_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_4 ), //i + .io_outputs_4_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last ), //o + .io_outputs_4_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode ), //o + .io_outputs_4_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address[23:0]), //o + .io_outputs_4_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_4_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_4_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_4_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_4_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_4 ), //i + .io_outputs_4_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready ), //o + .io_outputs_4_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 ), //i + .io_outputs_4_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 ), //i + .io_outputs_4_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4[31:0] ), //i + .io_outputs_4_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4[2:0] ), //i + .io_outputs_5_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_valid ), //o + .io_outputs_5_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_5 ), //i + .io_outputs_5_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_last ), //o + .io_outputs_5_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_opcode ), //o + .io_outputs_5_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_address[23:0]), //o + .io_outputs_5_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_5_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_5_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_5_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_5_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_5 ), //i + .io_outputs_5_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_5_rsp_ready ), //o + .io_outputs_5_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_5 ), //i + .io_outputs_5_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_5 ), //i + .io_outputs_5_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_5[31:0] ), //i + .io_outputs_5_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_5[2:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbUartCtrl_035069daf0ad4fb491e9c65d79bd2ddd system_uart_0_io_logic ( + .io_bus_cmd_valid (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i + .io_bus_cmd_ready (system_uart_0_io_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[5:0]), //i + .io_bus_cmd_payload_fragment_length (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_context (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[2:0]), //i + .io_bus_rsp_valid (system_uart_0_io_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (_zz_io_bus_rsp_ready ), //i + .io_bus_rsp_payload_last (system_uart_0_io_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_uart_0_io_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_uart_0_io_logic_io_bus_rsp_payload_fragment_context[2:0] ), //o + .io_uart_txd (system_uart_0_io_logic_io_uart_txd ), //o + .io_uart_rxd (system_uart_0_io_rxd ), //i + .system_uart_0_io_interrupt_source (system_uart_0_io_logic_system_uart_0_io_interrupt_source ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbSpiXdrMasterCtrl_035069daf0ad4fb491e9c65d79bd2ddd system_spi_0_io_logic ( + .io_ctrl_cmd_valid (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i + .io_ctrl_cmd_ready (system_spi_0_io_logic_io_ctrl_cmd_ready ), //o + .io_ctrl_cmd_payload_last (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i + .io_ctrl_cmd_payload_fragment_opcode (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i + .io_ctrl_cmd_payload_fragment_address (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[11:0]), //i + .io_ctrl_cmd_payload_fragment_length (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i + .io_ctrl_cmd_payload_fragment_data (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i + .io_ctrl_cmd_payload_fragment_context (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[2:0] ), //i + .io_ctrl_rsp_valid (system_spi_0_io_logic_io_ctrl_rsp_valid ), //o + .io_ctrl_rsp_ready (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_ctrl_rsp_payload_last (system_spi_0_io_logic_io_ctrl_rsp_payload_last ), //o + .io_ctrl_rsp_payload_fragment_opcode (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode ), //o + .io_ctrl_rsp_payload_fragment_data (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data[31:0] ), //o + .io_ctrl_rsp_payload_fragment_context (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context[2:0] ), //o + .io_spi_sclk_write (system_spi_0_io_logic_io_spi_sclk_write ), //o + .io_spi_data_0_writeEnable (system_spi_0_io_logic_io_spi_data_0_writeEnable ), //o + .io_spi_data_0_read (system_spi_0_io_data_0_read ), //i + .io_spi_data_0_write (system_spi_0_io_logic_io_spi_data_0_write ), //o + .io_spi_data_1_writeEnable (system_spi_0_io_logic_io_spi_data_1_writeEnable ), //o + .io_spi_data_1_read (system_spi_0_io_data_1_read ), //i + .io_spi_data_1_write (system_spi_0_io_logic_io_spi_data_1_write ), //o + .io_spi_data_2_writeEnable (system_spi_0_io_logic_io_spi_data_2_writeEnable ), //o + .io_spi_data_2_read (system_spi_0_io_data_2_read ), //i + .io_spi_data_2_write (system_spi_0_io_logic_io_spi_data_2_write ), //o + .io_spi_data_3_writeEnable (system_spi_0_io_logic_io_spi_data_3_writeEnable ), //o + .io_spi_data_3_read (system_spi_0_io_data_3_read ), //i + .io_spi_data_3_write (system_spi_0_io_logic_io_spi_data_3_write ), //o + .io_spi_ss (system_spi_0_io_logic_io_spi_ss[3:0] ), //o + .system_spi_0_io_interrupt_source (system_spi_0_io_logic_system_spi_0_io_interrupt_source ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbI2cCtrl_035069daf0ad4fb491e9c65d79bd2ddd system_i2c_0_io_logic ( + .io_ctrl_cmd_valid (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i + .io_ctrl_cmd_ready (system_i2c_0_io_logic_io_ctrl_cmd_ready ), //o + .io_ctrl_cmd_payload_last (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i + .io_ctrl_cmd_payload_fragment_opcode (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i + .io_ctrl_cmd_payload_fragment_address (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[7:0]), //i + .io_ctrl_cmd_payload_fragment_length (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i + .io_ctrl_cmd_payload_fragment_data (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i + .io_ctrl_cmd_payload_fragment_context (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[2:0]), //i + .io_ctrl_rsp_valid (system_i2c_0_io_logic_io_ctrl_rsp_valid ), //o + .io_ctrl_rsp_ready (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_ctrl_rsp_payload_last (system_i2c_0_io_logic_io_ctrl_rsp_payload_last ), //o + .io_ctrl_rsp_payload_fragment_opcode (system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_opcode ), //o + .io_ctrl_rsp_payload_fragment_data (system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_data[31:0] ), //o + .io_ctrl_rsp_payload_fragment_context (system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_context[2:0] ), //o + .io_i2c_sda_write (system_i2c_0_io_logic_io_i2c_sda_write ), //o + .io_i2c_sda_read (system_i2c_0_io_sda_read ), //i + .io_i2c_scl_write (system_i2c_0_io_logic_io_i2c_scl_write ), //o + .io_i2c_scl_read (system_i2c_0_io_scl_read ), //i + .system_i2c_0_io_interrupt_source (system_i2c_0_io_logic_system_i2c_0_io_interrupt_source ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbGpio2_035069daf0ad4fb491e9c65d79bd2ddd system_gpio_0_io_logic ( + .io_gpio_read (system_gpio_0_io_read[3:0] ), //i + .io_gpio_write (system_gpio_0_io_logic_io_gpio_write[3:0] ), //o + .io_gpio_writeEnable (system_gpio_0_io_logic_io_gpio_writeEnable[3:0] ), //o + .io_bus_cmd_valid (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i + .io_bus_cmd_ready (system_gpio_0_io_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[7:0]), //i + .io_bus_cmd_payload_fragment_length (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_context (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[2:0]), //i + .io_bus_rsp_valid (system_gpio_0_io_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_bus_rsp_payload_last (system_gpio_0_io_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_gpio_0_io_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_gpio_0_io_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_gpio_0_io_logic_io_bus_rsp_payload_fragment_context[2:0] ), //o + .io_interrupt (system_gpio_0_io_logic_io_interrupt[3:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbWatchdog_035069daf0ad4fb491e9c65d79bd2ddd system_watchdog_logic_logic ( + .io_bus_cmd_valid (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i + .io_bus_cmd_ready (system_watchdog_logic_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[7:0]), //i + .io_bus_cmd_payload_fragment_length (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_context (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[2:0]), //i + .io_bus_rsp_valid (system_watchdog_logic_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_bus_rsp_payload_last (system_watchdog_logic_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_watchdog_logic_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_watchdog_logic_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_watchdog_logic_logic_io_bus_rsp_payload_fragment_context[2:0] ), //o + .io_panics (system_watchdog_logic_logic_io_panics[1:0] ), //o + .io_heartBeat (1'b0 ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbToApb3Bridge_035069daf0ad4fb491e9c65d79bd2ddd io_apbSlave_0_logic ( + .io_input_cmd_valid (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i + .io_input_cmd_ready (io_apbSlave_0_logic_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[15:0]), //i + .io_input_cmd_payload_fragment_length (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i + .io_input_cmd_payload_fragment_data (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_context (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[2:0] ), //i + .io_input_rsp_valid (io_apbSlave_0_logic_io_input_rsp_valid ), //o + .io_input_rsp_ready (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_input_rsp_payload_last (io_apbSlave_0_logic_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (io_apbSlave_0_logic_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (io_apbSlave_0_logic_io_input_rsp_payload_fragment_context[2:0] ), //o + .io_output_PADDR (io_apbSlave_0_logic_io_output_PADDR[15:0] ), //o + .io_output_PSEL (io_apbSlave_0_logic_io_output_PSEL ), //o + .io_output_PENABLE (io_apbSlave_0_logic_io_output_PENABLE ), //o + .io_output_PREADY (io_apbSlave_0_PREADY ), //i + .io_output_PWRITE (io_apbSlave_0_logic_io_output_PWRITE ), //o + .io_output_PWDATA (io_apbSlave_0_logic_io_output_PWDATA[31:0] ), //o + .io_output_PRDATA (io_apbSlave_0_PRDATA[31:0] ), //i + .io_output_PSLVERROR (io_apbSlave_0_PSLVERROR ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign axi_aw_halfPipe_fire = (axi_aw_halfPipe_valid && axi_aw_halfPipe_ready); + assign axi_awready = (! axi_aw_rValid); + assign axi_aw_halfPipe_valid = axi_aw_rValid; + assign axi_aw_halfPipe_payload_addr = axi_aw_rData_addr; + assign axi_aw_halfPipe_payload_len = axi_aw_rData_len; + assign axi_aw_halfPipe_payload_size = axi_aw_rData_size; + assign axi_aw_halfPipe_payload_cache = axi_aw_rData_cache; + assign axi_aw_halfPipe_payload_prot = axi_aw_rData_prot; + assign axi_aw_halfPipe_ready = streamArbiter_io_inputs_1_ready; + assign axi_w_halfPipe_fire = (axi_w_halfPipe_valid && axi_w_halfPipe_ready); + assign axi_wready = (! axi_w_rValid); + assign axi_w_halfPipe_valid = axi_w_rValid; + assign axi_w_halfPipe_payload_data = axi_w_rData_data; + assign axi_w_halfPipe_payload_strb = axi_w_rData_strb; + assign axi_w_halfPipe_payload_last = axi_w_rData_last; + assign axi_w_halfPipe_ready = axiShared_w_ready; + assign _zz_axiShared_b_ready = (! _zz_axi_bvalid_1); + assign _zz_axi_bvalid = _zz_axi_bvalid_1; + assign axi_bvalid = _zz_axi_bvalid; + assign axi_bresp = _zz_axi_bresp; + assign axi_ar_halfPipe_fire = (axi_ar_halfPipe_valid && axi_ar_halfPipe_ready); + assign axi_arready = (! axi_ar_rValid); + assign axi_ar_halfPipe_valid = axi_ar_rValid; + assign axi_ar_halfPipe_payload_addr = axi_ar_rData_addr; + assign axi_ar_halfPipe_payload_len = axi_ar_rData_len; + assign axi_ar_halfPipe_payload_size = axi_ar_rData_size; + assign axi_ar_halfPipe_payload_cache = axi_ar_rData_cache; + assign axi_ar_halfPipe_payload_prot = axi_ar_rData_prot; + assign axi_ar_halfPipe_ready = streamArbiter_io_inputs_0_ready; + assign _zz_axiShared_r_ready = (! _zz_axi_rvalid_1); + assign _zz_axi_rvalid = _zz_axi_rvalid_1; + assign axi_rvalid = _zz_axi_rvalid; + assign axi_rdata = _zz_axi_rdata; + assign axi_rresp = _zz_axi_rresp; + assign axi_rlast = _zz_axi_rlast; + assign axiShared_arw_valid = streamArbiter_io_output_valid; + assign axiShared_arw_payload_addr = streamArbiter_io_output_payload_addr; + assign axiShared_arw_payload_len = streamArbiter_io_output_payload_len; + assign axiShared_arw_payload_size = streamArbiter_io_output_payload_size; + assign axiShared_arw_payload_cache = streamArbiter_io_output_payload_cache; + assign axiShared_arw_payload_prot = streamArbiter_io_output_payload_prot; + assign axiShared_arw_payload_write = streamArbiter_io_chosenOH[1]; + assign axiShared_w_valid = axi_w_halfPipe_valid; + assign axiShared_w_payload_data = axi_w_halfPipe_payload_data; + assign axiShared_w_payload_strb = axi_w_halfPipe_payload_strb; + assign axiShared_w_payload_last = axi_w_halfPipe_payload_last; + assign axiShared_b_ready = _zz_axiShared_b_ready; + assign axiShared_r_ready = _zz_axiShared_r_ready; + assign axiShared_arw_ready = axiToBmb_io_axi_arw_ready; + assign axiShared_w_ready = axiToBmb_io_axi_w_ready; + assign axiShared_b_valid = axiToBmb_io_axi_b_valid; + assign axiShared_b_payload_resp = axiToBmb_io_axi_b_payload_resp; + assign axiShared_r_valid = axiToBmb_io_axi_r_valid; + assign axiShared_r_payload_data = axiToBmb_io_axi_r_payload_data; + assign axiShared_r_payload_last = axiToBmb_io_axi_r_payload_last; + assign axiShared_r_payload_resp = axiToBmb_io_axi_r_payload_resp; + assign bmbPeripheral_bmb_cmd_valid = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = bmbPeripheral_bmb_cmd_ready; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = bmbPeripheral_bmb_rsp_valid; + assign bmbPeripheral_bmb_rsp_ready = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign bmbPeripheral_bmb_cmd_payload_last = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = bmbPeripheral_bmb_rsp_payload_last; + assign bmbPeripheral_bmb_cmd_payload_fragment_opcode = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_cmd_payload_fragment_address = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_cmd_payload_fragment_length = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_cmd_payload_fragment_data = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_cmd_payload_fragment_mask = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign bmbPeripheral_bmb_cmd_payload_fragment_context = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = bmbPeripheral_bmb_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = bmbPeripheral_bmb_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = bmbPeripheral_bmb_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbHandle_unburstify_io_output_cmd_valid; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbHandle_unburstify_io_output_rsp_ready; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbHandle_unburstify_io_output_cmd_payload_last; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbHandle_unburstify_io_output_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbHandle_unburstify_io_output_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbHandle_unburstify_io_output_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbHandle_unburstify_io_output_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = bmbHandle_unburstify_io_output_cmd_payload_fragment_mask; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbHandle_unburstify_io_output_cmd_payload_fragment_context; + assign bmbPeripheral_bmb_cmd_ready = bmbPeripheral_bmb_decoder_io_input_cmd_ready; + assign bmbPeripheral_bmb_rsp_valid = bmbPeripheral_bmb_decoder_io_input_rsp_valid; + assign bmbPeripheral_bmb_rsp_payload_last = bmbPeripheral_bmb_decoder_io_input_rsp_payload_last; + assign bmbPeripheral_bmb_rsp_payload_fragment_opcode = bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_rsp_payload_fragment_data = bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_rsp_payload_fragment_context = bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context; + assign system_uart_0_io_txd = system_uart_0_io_logic_io_uart_txd; + assign system_i2c_0_io_sda_write = system_i2c_0_io_logic_io_i2c_sda_write; + assign system_i2c_0_io_scl_write = system_i2c_0_io_logic_io_i2c_scl_write; + assign system_gpio_0_io_write = system_gpio_0_io_logic_io_gpio_write; + assign system_gpio_0_io_writeEnable = system_gpio_0_io_logic_io_gpio_writeEnable; + assign system_gpio_0_io_interrupts_0_source = system_gpio_0_io_logic_io_interrupt[0]; + assign system_gpio_0_io_interrupts_1_source = system_gpio_0_io_logic_io_interrupt[1]; + assign system_gpio_0_io_interrupts_2 = system_gpio_0_io_logic_io_interrupt[2]; + assign system_gpio_0_io_interrupts_3 = system_gpio_0_io_logic_io_interrupt[3]; + assign system_watchdog_logic_panics_0_source = system_watchdog_logic_logic_io_panics[0]; + assign io_apbSlave_0_PADDR = io_apbSlave_0_logic_io_output_PADDR; + assign io_apbSlave_0_PSEL = io_apbSlave_0_logic_io_output_PSEL; + assign io_apbSlave_0_PENABLE = io_apbSlave_0_logic_io_output_PENABLE; + assign io_apbSlave_0_PWRITE = io_apbSlave_0_logic_io_output_PWRITE; + assign io_apbSlave_0_PWDATA = io_apbSlave_0_logic_io_output_PWDATA; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_uart_0_io_logic_io_bus_cmd_ready; + assign _zz_io_bus_rsp_ready = (! _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1); + assign _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_uart_0_io_interrupt = system_uart_0_io_logic_system_uart_0_io_interrupt_source; + assign system_spi_0_io_interrupt = system_spi_0_io_logic_system_spi_0_io_interrupt_source; + assign system_spi_0_io_sclk_write = system_spi_0_io_logic_io_spi_sclk_write; + assign system_spi_0_io_data_0_writeEnable = system_spi_0_io_logic_io_spi_data_0_writeEnable; + assign system_spi_0_io_data_0_write = system_spi_0_io_logic_io_spi_data_0_write; + assign system_spi_0_io_data_1_writeEnable = system_spi_0_io_logic_io_spi_data_1_writeEnable; + assign system_spi_0_io_data_1_write = system_spi_0_io_logic_io_spi_data_1_write; + assign system_spi_0_io_data_2_writeEnable = system_spi_0_io_logic_io_spi_data_2_writeEnable; + assign system_spi_0_io_data_2_write = system_spi_0_io_logic_io_spi_data_2_write; + assign system_spi_0_io_data_3_writeEnable = system_spi_0_io_logic_io_spi_data_3_writeEnable; + assign system_spi_0_io_data_3_write = system_spi_0_io_logic_io_spi_data_3_write; + assign system_spi_0_io_ss = system_spi_0_io_logic_io_spi_ss; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_spi_0_io_logic_io_ctrl_cmd_ready; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_spi_0_io_logic_io_ctrl_rsp_valid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_spi_0_io_logic_io_ctrl_rsp_payload_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_i2c_0_io_logic_io_ctrl_cmd_ready; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_i2c_0_io_logic_io_ctrl_rsp_valid; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_i2c_0_io_logic_io_ctrl_rsp_payload_last; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_data; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_context; + assign system_i2c_0_io_interrupt = system_i2c_0_io_logic_system_i2c_0_io_interrupt_source; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_gpio_0_io_logic_io_bus_cmd_ready; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_gpio_0_io_logic_io_bus_rsp_valid; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_gpio_0_io_logic_io_bus_rsp_payload_last; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_gpio_0_io_logic_io_bus_rsp_payload_fragment_opcode; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_gpio_0_io_logic_io_bus_rsp_payload_fragment_data; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_gpio_0_io_logic_io_bus_rsp_payload_fragment_context; + assign system_gpio_0_io_interrupts_0 = system_gpio_0_io_interrupts_0_source; + assign system_gpio_0_io_interrupts_1 = system_gpio_0_io_interrupts_1_source; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_watchdog_logic_logic_io_bus_cmd_ready; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_watchdog_logic_logic_io_bus_rsp_valid; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_watchdog_logic_logic_io_bus_rsp_payload_last; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_watchdog_logic_logic_io_bus_rsp_payload_fragment_opcode; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_watchdog_logic_logic_io_bus_rsp_payload_fragment_data; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_watchdog_logic_logic_io_bus_rsp_payload_fragment_context; + assign system_watchdog_logic_panics_0 = system_watchdog_logic_panics_0_source; + assign system_watchdog_hardPanic_reset = system_watchdog_logic_logic_io_panics[1]; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = io_apbSlave_0_logic_io_input_cmd_ready; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = io_apbSlave_0_logic_io_input_rsp_valid; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = io_apbSlave_0_logic_io_input_rsp_payload_last; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = io_apbSlave_0_logic_io_input_rsp_payload_fragment_data; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = io_apbSlave_0_logic_io_input_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready = bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_cmd_ready = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address[5:0]; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready_1 = bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_1; + assign bmbPeripheral_bmb_withoutMask_cmd_ready_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_1; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_1; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1[11:0]; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready_2 = bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_2; + assign bmbPeripheral_bmb_withoutMask_cmd_ready_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_2; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_2; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2[7:0]; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready_3 = bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_3; + assign bmbPeripheral_bmb_withoutMask_cmd_ready_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_3; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_3; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3[7:0]; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready_4 = bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_4; + assign bmbPeripheral_bmb_withoutMask_cmd_ready_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_4; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_4; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4[7:0]; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready_5 = bmbPeripheral_bmb_decoder_io_outputs_5_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_context; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_5; + assign bmbPeripheral_bmb_withoutMask_cmd_ready_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_5; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_5; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_5; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_5[15:0]; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_5; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_5; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_5; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + always @(posedge clk) begin + if(reset) begin + axi_aw_rValid <= 1'b0; + axi_w_rValid <= 1'b0; + _zz_axi_bvalid_1 <= 1'b0; + axi_ar_rValid <= 1'b0; + _zz_axi_rvalid_1 <= 1'b0; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end else begin + if(axi_awvalid) begin + axi_aw_rValid <= 1'b1; + end + if(axi_aw_halfPipe_fire) begin + axi_aw_rValid <= 1'b0; + end + if(axi_wvalid) begin + axi_w_rValid <= 1'b1; + end + if(axi_w_halfPipe_fire) begin + axi_w_rValid <= 1'b0; + end + if(axiShared_b_valid) begin + _zz_axi_bvalid_1 <= 1'b1; + end + if((_zz_axi_bvalid && axi_bready)) begin + _zz_axi_bvalid_1 <= 1'b0; + end + if(axi_arvalid) begin + axi_ar_rValid <= 1'b1; + end + if(axi_ar_halfPipe_fire) begin + axi_ar_rValid <= 1'b0; + end + if(axiShared_r_valid) begin + _zz_axi_rvalid_1 <= 1'b1; + end + if((_zz_axi_rvalid && axi_rready)) begin + _zz_axi_rvalid_1 <= 1'b0; + end + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + if(system_uart_0_io_logic_io_bus_rsp_valid) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b1; + end + if((_zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready)) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + if(system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + end + end + + always @(posedge clk) begin + if(axi_awready) begin + axi_aw_rData_addr <= axi_awaddr; + axi_aw_rData_len <= axi_awlen; + axi_aw_rData_size <= axi_awsize; + axi_aw_rData_cache <= axi_awcache; + axi_aw_rData_prot <= axi_awprot; + end + if(axi_wready) begin + axi_w_rData_data <= axi_wdata; + axi_w_rData_strb <= axi_wstrb; + axi_w_rData_last <= axi_wlast; + end + if(_zz_axiShared_b_ready) begin + _zz_axi_bresp <= axiShared_b_payload_resp; + end + if(axi_arready) begin + axi_ar_rData_addr <= axi_araddr; + axi_ar_rData_len <= axi_arlen; + axi_ar_rData_size <= axi_arsize; + axi_ar_rData_cache <= axi_arcache; + axi_ar_rData_prot <= axi_arprot; + end + if(_zz_axiShared_r_ready) begin + _zz_axi_rdata <= axiShared_r_payload_data; + _zz_axi_rresp <= axiShared_r_payload_resp; + _zz_axi_rlast <= axiShared_r_payload_last; + end + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + if(_zz_io_bus_rsp_ready) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_uart_0_io_logic_io_bus_rsp_payload_last; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_data; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_context; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + if(system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + end + + +endmodule + +module Axi4PeripheralBmbToApb3Bridge_035069daf0ad4fb491e9c65d79bd2ddd ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [15:0] io_input_cmd_payload_fragment_address, + input wire [1:0] io_input_cmd_payload_fragment_length, + input wire [31:0] io_input_cmd_payload_fragment_data, + input wire [2:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [31:0] io_input_rsp_payload_fragment_data, + output wire [2:0] io_input_rsp_payload_fragment_context, + output wire [15:0] io_output_PADDR, + output wire [0:0] io_output_PSEL, + output wire io_output_PENABLE, + input wire io_output_PREADY, + output wire io_output_PWRITE, + output wire [31:0] io_output_PWDATA, + input wire [31:0] io_output_PRDATA, + input wire io_output_PSLVERROR, + input wire clk, + input wire reset +); + + wire bmbBuffer_cmd_valid; + reg bmbBuffer_cmd_ready; + wire bmbBuffer_cmd_payload_last; + wire [0:0] bmbBuffer_cmd_payload_fragment_opcode; + wire [15:0] bmbBuffer_cmd_payload_fragment_address; + wire [1:0] bmbBuffer_cmd_payload_fragment_length; + wire [31:0] bmbBuffer_cmd_payload_fragment_data; + wire [2:0] bmbBuffer_cmd_payload_fragment_context; + reg bmbBuffer_rsp_valid; + reg bmbBuffer_rsp_ready; + wire bmbBuffer_rsp_payload_last; + reg [0:0] bmbBuffer_rsp_payload_fragment_opcode; + wire [31:0] bmbBuffer_rsp_payload_fragment_data; + wire [2:0] bmbBuffer_rsp_payload_fragment_context; + wire io_input_rsp_isStall; + wire _zz_io_input_cmd_ready; + wire bmbBuffer_rsp_m2sPipe_valid; + wire bmbBuffer_rsp_m2sPipe_ready; + wire bmbBuffer_rsp_m2sPipe_payload_last; + wire [0:0] bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; + wire [31:0] bmbBuffer_rsp_m2sPipe_payload_fragment_data; + wire [2:0] bmbBuffer_rsp_m2sPipe_payload_fragment_context; + reg bmbBuffer_rsp_rValid; + reg bmbBuffer_rsp_rData_last; + reg [0:0] bmbBuffer_rsp_rData_fragment_opcode; + reg [31:0] bmbBuffer_rsp_rData_fragment_data; + reg [2:0] bmbBuffer_rsp_rData_fragment_context; + wire when_Stream_l375; + reg state; + wire when_BmbToApb3Bridge_l46; + + assign io_input_rsp_isStall = (io_input_rsp_valid && (! io_input_rsp_ready)); + assign _zz_io_input_cmd_ready = (! io_input_rsp_isStall); + assign io_input_cmd_ready = (bmbBuffer_cmd_ready && _zz_io_input_cmd_ready); + assign bmbBuffer_cmd_valid = (io_input_cmd_valid && _zz_io_input_cmd_ready); + assign bmbBuffer_cmd_payload_last = io_input_cmd_payload_last; + assign bmbBuffer_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign bmbBuffer_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign bmbBuffer_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign bmbBuffer_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign bmbBuffer_cmd_payload_fragment_context = io_input_cmd_payload_fragment_context; + always @(*) begin + bmbBuffer_rsp_ready = bmbBuffer_rsp_m2sPipe_ready; + if(when_Stream_l375) begin + bmbBuffer_rsp_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! bmbBuffer_rsp_m2sPipe_valid); + assign bmbBuffer_rsp_m2sPipe_valid = bmbBuffer_rsp_rValid; + assign bmbBuffer_rsp_m2sPipe_payload_last = bmbBuffer_rsp_rData_last; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_opcode = bmbBuffer_rsp_rData_fragment_opcode; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_data = bmbBuffer_rsp_rData_fragment_data; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_context = bmbBuffer_rsp_rData_fragment_context; + assign io_input_rsp_valid = bmbBuffer_rsp_m2sPipe_valid; + assign bmbBuffer_rsp_m2sPipe_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = bmbBuffer_rsp_m2sPipe_payload_last; + assign io_input_rsp_payload_fragment_opcode = bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = bmbBuffer_rsp_m2sPipe_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = bmbBuffer_rsp_m2sPipe_payload_fragment_context; + always @(*) begin + bmbBuffer_cmd_ready = 1'b0; + if(!when_BmbToApb3Bridge_l46) begin + if(io_output_PREADY) begin + bmbBuffer_cmd_ready = 1'b1; + end + end + end + + assign io_output_PSEL[0] = bmbBuffer_cmd_valid; + assign io_output_PENABLE = state; + assign io_output_PWRITE = (bmbBuffer_cmd_payload_fragment_opcode == 1'b1); + assign io_output_PADDR = bmbBuffer_cmd_payload_fragment_address; + assign io_output_PWDATA = bmbBuffer_cmd_payload_fragment_data; + always @(*) begin + bmbBuffer_rsp_valid = 1'b0; + if(!when_BmbToApb3Bridge_l46) begin + if(io_output_PREADY) begin + bmbBuffer_rsp_valid = 1'b1; + end + end + end + + assign bmbBuffer_rsp_payload_fragment_data = io_output_PRDATA; + assign when_BmbToApb3Bridge_l46 = (! state); + assign bmbBuffer_rsp_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign bmbBuffer_rsp_payload_last = 1'b1; + always @(*) begin + bmbBuffer_rsp_payload_fragment_opcode = 1'b0; + if(io_output_PSLVERROR) begin + bmbBuffer_rsp_payload_fragment_opcode = 1'b1; + end + end + + always @(posedge clk) begin + if(reset) begin + bmbBuffer_rsp_rValid <= 1'b0; + state <= 1'b0; + end else begin + if(bmbBuffer_rsp_ready) begin + bmbBuffer_rsp_rValid <= bmbBuffer_rsp_valid; + end + if(when_BmbToApb3Bridge_l46) begin + state <= bmbBuffer_cmd_valid; + end else begin + if(io_output_PREADY) begin + state <= 1'b0; + end + end + end + end + + always @(posedge clk) begin + if(bmbBuffer_rsp_ready) begin + bmbBuffer_rsp_rData_last <= bmbBuffer_rsp_payload_last; + bmbBuffer_rsp_rData_fragment_opcode <= bmbBuffer_rsp_payload_fragment_opcode; + bmbBuffer_rsp_rData_fragment_data <= bmbBuffer_rsp_payload_fragment_data; + bmbBuffer_rsp_rData_fragment_context <= bmbBuffer_rsp_payload_fragment_context; + end + end + + +endmodule + +module Axi4PeripheralBmbWatchdog_035069daf0ad4fb491e9c65d79bd2ddd ( + input wire io_bus_cmd_valid, + output wire io_bus_cmd_ready, + input wire io_bus_cmd_payload_last, + input wire [0:0] io_bus_cmd_payload_fragment_opcode, + input wire [7:0] io_bus_cmd_payload_fragment_address, + input wire [1:0] io_bus_cmd_payload_fragment_length, + input wire [31:0] io_bus_cmd_payload_fragment_data, + input wire [2:0] io_bus_cmd_payload_fragment_context, + output wire io_bus_rsp_valid, + input wire io_bus_rsp_ready, + output wire io_bus_rsp_payload_last, + output wire [0:0] io_bus_rsp_payload_fragment_opcode, + output wire [31:0] io_bus_rsp_payload_fragment_data, + output wire [2:0] io_bus_rsp_payload_fragment_context, + output wire [1:0] io_panics, + input wire io_heartBeat, + input wire clk, + input wire reset +); + + wire wd_prescaler_io_clear; + wire wd_prescaler_io_overflow; + wire wd_counters_0_timer_io_full; + wire [15:0] wd_counters_0_timer_io_value; + wire wd_counters_1_timer_io_full; + wire [15:0] wd_counters_1_timer_io_value; + reg [1:0] wd_api_enables; + reg wd_api_heartbeat; + reg [1:0] wd_api_panics; + wire wd_counters_0_clear; + reg wd_counters_0_full; + wire wd_counters_1_clear; + reg wd_counters_1_full; + wire busCtrl_readErrorFlag; + wire busCtrl_writeErrorFlag; + wire busCtrl_readHaltTrigger; + wire busCtrl_writeHaltTrigger; + wire busCtrl_rsp_valid; + wire busCtrl_rsp_ready; + wire busCtrl_rsp_payload_last; + reg [0:0] busCtrl_rsp_payload_fragment_opcode; + reg [31:0] busCtrl_rsp_payload_fragment_data; + wire [2:0] busCtrl_rsp_payload_fragment_context; + wire _zz_busCtrl_rsp_ready; + reg _zz_busCtrl_rsp_ready_1; + wire _zz_io_bus_rsp_valid; + reg _zz_io_bus_rsp_valid_1; + reg _zz_io_bus_rsp_payload_last; + reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_bus_rsp_payload_fragment_data; + reg [2:0] _zz_io_bus_rsp_payload_fragment_context; + wire when_Stream_l375; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire io_bus_cmd_fire; + wire busCtrl_doWrite; + wire busCtrl_doRead; + wire when_BmbSlaveFactory_l33; + wire when_BmbSlaveFactory_l35; + reg driver_unlocked; + reg _zz_when_Watchdog_l42; + wire when_Watchdog_l42; + reg _zz_when_Watchdog_l43; + wire when_Watchdog_l43; + reg _zz_wd_api_heartbeat; + wire [1:0] _zz_when_Watchdog_l52; + reg _zz_when_Watchdog_l50; + wire when_Watchdog_l50; + wire when_Watchdog_l52; + wire when_Watchdog_l52_1; + reg _zz_when_Watchdog_l55; + wire when_Watchdog_l55; + wire when_Watchdog_l57; + wire when_Watchdog_l57_1; + reg [23:0] _zz_io_limit; + reg [15:0] _zz_io_limit_1; + reg [15:0] _zz_io_limit_2; + + Axi4PeripheralPrescaler_035069daf0ad4fb491e9c65d79bd2ddd wd_prescaler ( + .io_clear (wd_prescaler_io_clear ), //i + .io_limit (_zz_io_limit[23:0] ), //i + .io_overflow (wd_prescaler_io_overflow), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralTimer_035069daf0ad4fb491e9c65d79bd2ddd wd_counters_0_timer ( + .io_tick (wd_prescaler_io_overflow ), //i + .io_clear (wd_counters_0_clear ), //i + .io_limit (_zz_io_limit_1[15:0] ), //i + .io_full (wd_counters_0_timer_io_full ), //o + .io_value (wd_counters_0_timer_io_value[15:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralTimer_035069daf0ad4fb491e9c65d79bd2ddd wd_counters_1_timer ( + .io_tick (wd_prescaler_io_overflow ), //i + .io_clear (wd_counters_1_clear ), //i + .io_limit (_zz_io_limit_2[15:0] ), //i + .io_full (wd_counters_1_timer_io_full ), //o + .io_value (wd_counters_1_timer_io_value[15:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + assign wd_prescaler_io_clear = (wd_api_heartbeat || (wd_api_enables == 2'b00)); + assign wd_counters_0_clear = ((! wd_api_enables[0]) || wd_api_heartbeat); + always @(*) begin + wd_api_panics[0] = wd_counters_0_full; + wd_api_panics[1] = wd_counters_1_full; + end + + assign wd_counters_1_clear = ((! wd_api_enables[1]) || wd_api_heartbeat); + assign busCtrl_readErrorFlag = 1'b0; + assign busCtrl_writeErrorFlag = 1'b0; + assign busCtrl_readHaltTrigger = 1'b0; + assign busCtrl_writeHaltTrigger = 1'b0; + assign _zz_busCtrl_rsp_ready = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); + assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready_1 && _zz_busCtrl_rsp_ready); + always @(*) begin + _zz_busCtrl_rsp_ready_1 = io_bus_rsp_ready; + if(when_Stream_l375) begin + _zz_busCtrl_rsp_ready_1 = 1'b1; + end + end + + assign when_Stream_l375 = (! _zz_io_bus_rsp_valid); + assign _zz_io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; + assign io_bus_rsp_valid = _zz_io_bus_rsp_valid; + assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; + assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; + assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; + assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; + assign busCtrl_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign busCtrl_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_doRead = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign busCtrl_rsp_valid = io_bus_cmd_valid; + assign io_bus_cmd_ready = busCtrl_rsp_ready; + assign busCtrl_rsp_payload_last = 1'b1; + assign when_BmbSlaveFactory_l33 = (busCtrl_doWrite && busCtrl_writeErrorFlag); + always @(*) begin + if(when_BmbSlaveFactory_l33) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + if(when_BmbSlaveFactory_l35) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + busCtrl_rsp_payload_fragment_opcode = 1'b0; + end + end + end + + assign when_BmbSlaveFactory_l35 = (busCtrl_doRead && busCtrl_readErrorFlag); + always @(*) begin + busCtrl_rsp_payload_fragment_data = 32'h0; + case(io_bus_cmd_payload_fragment_address) + 8'hc0 : begin + busCtrl_rsp_payload_fragment_data[15 : 0] = wd_counters_0_timer_io_value; + end + 8'hc4 : begin + busCtrl_rsp_payload_fragment_data[15 : 0] = wd_counters_1_timer_io_value; + end + default : begin + end + endcase + end + + assign busCtrl_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; + always @(*) begin + _zz_when_Watchdog_l42 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 8'h0 : begin + if(busCtrl_doWrite) begin + _zz_when_Watchdog_l42 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_Watchdog_l42 = (_zz_when_Watchdog_l42 && (io_bus_cmd_payload_fragment_data[31 : 0] == 32'h3c21b925)); + always @(*) begin + _zz_when_Watchdog_l43 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 8'h0 : begin + if(busCtrl_doWrite) begin + _zz_when_Watchdog_l43 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_Watchdog_l43 = (_zz_when_Watchdog_l43 && (io_bus_cmd_payload_fragment_data[31 : 0] == 32'h3c21b924)); + always @(*) begin + _zz_wd_api_heartbeat = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 8'h0 : begin + if(busCtrl_doWrite) begin + _zz_wd_api_heartbeat = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + wd_api_heartbeat = (_zz_wd_api_heartbeat && (io_bus_cmd_payload_fragment_data[31 : 0] == 32'had68e70d)); + if(io_heartBeat) begin + wd_api_heartbeat = 1'b1; + end + end + + always @(*) begin + _zz_when_Watchdog_l50 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 8'h04 : begin + if(busCtrl_doWrite) begin + _zz_when_Watchdog_l50 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_Watchdog_l50 = (_zz_when_Watchdog_l50 && driver_unlocked); + assign when_Watchdog_l52 = _zz_when_Watchdog_l52[0]; + assign when_Watchdog_l52_1 = _zz_when_Watchdog_l52[1]; + always @(*) begin + _zz_when_Watchdog_l55 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 8'h08 : begin + if(busCtrl_doWrite) begin + _zz_when_Watchdog_l55 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_Watchdog_l55 = (_zz_when_Watchdog_l55 && driver_unlocked); + assign when_Watchdog_l57 = _zz_when_Watchdog_l52[0]; + assign when_Watchdog_l57_1 = _zz_when_Watchdog_l52[1]; + assign io_panics = wd_api_panics; + assign _zz_when_Watchdog_l52 = io_bus_cmd_payload_fragment_data[1 : 0]; + always @(posedge clk) begin + if(reset) begin + wd_counters_0_full <= 1'b0; + wd_counters_1_full <= 1'b0; + _zz_io_bus_rsp_valid_1 <= 1'b0; + driver_unlocked <= 1'b1; + wd_api_enables <= 2'b00; + _zz_io_limit <= 24'h0; + _zz_io_limit_1 <= 16'h0; + _zz_io_limit_2 <= 16'h0; + end else begin + if(wd_counters_0_timer_io_full) begin + wd_counters_0_full <= 1'b1; + end + if(wd_counters_0_clear) begin + wd_counters_0_full <= 1'b0; + end + if(wd_counters_1_timer_io_full) begin + wd_counters_1_full <= 1'b1; + end + if(wd_counters_1_clear) begin + wd_counters_1_full <= 1'b0; + end + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_bus_rsp_valid_1 <= (busCtrl_rsp_valid && _zz_busCtrl_rsp_ready); + end + if(when_Watchdog_l42) begin + driver_unlocked <= 1'b1; + end + if(when_Watchdog_l43) begin + driver_unlocked <= 1'b0; + end + if(when_Watchdog_l50) begin + if(when_Watchdog_l52) begin + wd_api_enables[0] <= 1'b1; + end + if(when_Watchdog_l52_1) begin + wd_api_enables[1] <= 1'b1; + end + end + if(when_Watchdog_l55) begin + if(when_Watchdog_l57) begin + wd_api_enables[0] <= 1'b0; + end + if(when_Watchdog_l57_1) begin + wd_api_enables[1] <= 1'b0; + end + end + case(io_bus_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + if(driver_unlocked) begin + _zz_io_limit <= io_bus_cmd_payload_fragment_data[23 : 0]; + end + end + end + 8'h80 : begin + if(busCtrl_doWrite) begin + if(driver_unlocked) begin + _zz_io_limit_1 <= io_bus_cmd_payload_fragment_data[15 : 0]; + end + end + end + 8'h84 : begin + if(busCtrl_doWrite) begin + if(driver_unlocked) begin + _zz_io_limit_2 <= io_bus_cmd_payload_fragment_data[15 : 0]; + end + end + end + default : begin + end + endcase + end + end + + always @(posedge clk) begin + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_bus_rsp_payload_last <= busCtrl_rsp_payload_last; + _zz_io_bus_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; + _zz_io_bus_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; + _zz_io_bus_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; + end + end + + +endmodule + +module Axi4PeripheralBmbGpio2_035069daf0ad4fb491e9c65d79bd2ddd ( + input wire [3:0] io_gpio_read, + output reg [3:0] io_gpio_write, + output reg [3:0] io_gpio_writeEnable, + input wire io_bus_cmd_valid, + output wire io_bus_cmd_ready, + input wire io_bus_cmd_payload_last, + input wire [0:0] io_bus_cmd_payload_fragment_opcode, + input wire [7:0] io_bus_cmd_payload_fragment_address, + input wire [1:0] io_bus_cmd_payload_fragment_length, + input wire [31:0] io_bus_cmd_payload_fragment_data, + input wire [2:0] io_bus_cmd_payload_fragment_context, + output wire io_bus_rsp_valid, + input wire io_bus_rsp_ready, + output wire io_bus_rsp_payload_last, + output wire [0:0] io_bus_rsp_payload_fragment_opcode, + output wire [31:0] io_bus_rsp_payload_fragment_data, + output wire [2:0] io_bus_rsp_payload_fragment_context, + output reg [3:0] io_interrupt, + input wire clk, + input wire reset +); + + wire mapper_readErrorFlag; + wire mapper_writeErrorFlag; + wire mapper_readHaltTrigger; + wire mapper_writeHaltTrigger; + wire mapper_rsp_valid; + wire mapper_rsp_ready; + wire mapper_rsp_payload_last; + reg [0:0] mapper_rsp_payload_fragment_opcode; + reg [31:0] mapper_rsp_payload_fragment_data; + wire [2:0] mapper_rsp_payload_fragment_context; + wire _zz_mapper_rsp_ready; + reg _zz_mapper_rsp_ready_1; + wire _zz_io_bus_rsp_valid; + reg _zz_io_bus_rsp_valid_1; + reg _zz_io_bus_rsp_payload_last; + reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_bus_rsp_payload_fragment_data; + reg [2:0] _zz_io_bus_rsp_payload_fragment_context; + wire when_Stream_l375; + wire mapper_askWrite; + wire mapper_askRead; + wire io_bus_cmd_fire; + wire mapper_doWrite; + wire mapper_doRead; + wire when_BmbSlaveFactory_l33; + wire when_BmbSlaveFactory_l35; + reg [3:0] io_gpio_read_delay_1; + reg [3:0] syncronized; + reg [3:0] last; + reg _zz_io_gpio_write; + reg _zz_io_gpio_writeEnable; + reg _zz_io_gpio_write_1; + reg _zz_io_gpio_writeEnable_1; + reg _zz_io_gpio_write_2; + reg _zz_io_gpio_writeEnable_2; + reg _zz_io_gpio_write_3; + reg _zz_io_gpio_writeEnable_3; + reg [3:0] interrupt_enable_high; + reg [3:0] interrupt_enable_low; + reg [3:0] interrupt_enable_rise; + reg [3:0] interrupt_enable_fall; + wire [3:0] interrupt_valid; + reg _zz_mapper_rsp_payload_fragment_data; + reg _zz_mapper_rsp_payload_fragment_data_1; + reg _zz_mapper_rsp_payload_fragment_data_2; + reg _zz_mapper_rsp_payload_fragment_data_3; + reg _zz_mapper_rsp_payload_fragment_data_4; + reg _zz_mapper_rsp_payload_fragment_data_5; + reg _zz_mapper_rsp_payload_fragment_data_6; + reg _zz_mapper_rsp_payload_fragment_data_7; + + assign mapper_readErrorFlag = 1'b0; + assign mapper_writeErrorFlag = 1'b0; + assign mapper_readHaltTrigger = 1'b0; + assign mapper_writeHaltTrigger = 1'b0; + assign _zz_mapper_rsp_ready = (! (mapper_readHaltTrigger || mapper_writeHaltTrigger)); + assign mapper_rsp_ready = (_zz_mapper_rsp_ready_1 && _zz_mapper_rsp_ready); + always @(*) begin + _zz_mapper_rsp_ready_1 = io_bus_rsp_ready; + if(when_Stream_l375) begin + _zz_mapper_rsp_ready_1 = 1'b1; + end + end + + assign when_Stream_l375 = (! _zz_io_bus_rsp_valid); + assign _zz_io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; + assign io_bus_rsp_valid = _zz_io_bus_rsp_valid; + assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; + assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; + assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; + assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; + assign mapper_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign mapper_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign mapper_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign mapper_doRead = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign mapper_rsp_valid = io_bus_cmd_valid; + assign io_bus_cmd_ready = mapper_rsp_ready; + assign mapper_rsp_payload_last = 1'b1; + assign when_BmbSlaveFactory_l33 = (mapper_doWrite && mapper_writeErrorFlag); + always @(*) begin + if(when_BmbSlaveFactory_l33) begin + mapper_rsp_payload_fragment_opcode = 1'b1; + end else begin + if(when_BmbSlaveFactory_l35) begin + mapper_rsp_payload_fragment_opcode = 1'b1; + end else begin + mapper_rsp_payload_fragment_opcode = 1'b0; + end + end + end + + assign when_BmbSlaveFactory_l35 = (mapper_doRead && mapper_readErrorFlag); + always @(*) begin + mapper_rsp_payload_fragment_data = 32'h0; + case(io_bus_cmd_payload_fragment_address) + 8'h0 : begin + mapper_rsp_payload_fragment_data[0 : 0] = syncronized[0]; + mapper_rsp_payload_fragment_data[1 : 1] = syncronized[1]; + mapper_rsp_payload_fragment_data[2 : 2] = syncronized[2]; + mapper_rsp_payload_fragment_data[3 : 3] = syncronized[3]; + end + 8'h04 : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_io_gpio_write; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_io_gpio_write_1; + mapper_rsp_payload_fragment_data[2 : 2] = _zz_io_gpio_write_2; + mapper_rsp_payload_fragment_data[3 : 3] = _zz_io_gpio_write_3; + end + 8'h08 : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_io_gpio_writeEnable; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_io_gpio_writeEnable_1; + mapper_rsp_payload_fragment_data[2 : 2] = _zz_io_gpio_writeEnable_2; + mapper_rsp_payload_fragment_data[3 : 3] = _zz_io_gpio_writeEnable_3; + end + 8'h20 : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_mapper_rsp_payload_fragment_data; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_mapper_rsp_payload_fragment_data_4; + end + 8'h24 : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_mapper_rsp_payload_fragment_data_1; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_mapper_rsp_payload_fragment_data_5; + end + 8'h28 : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_mapper_rsp_payload_fragment_data_2; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_mapper_rsp_payload_fragment_data_6; + end + 8'h2c : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_mapper_rsp_payload_fragment_data_3; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_mapper_rsp_payload_fragment_data_7; + end + default : begin + end + endcase + end + + assign mapper_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; + always @(*) begin + io_gpio_write[0] = _zz_io_gpio_write; + io_gpio_write[1] = _zz_io_gpio_write_1; + io_gpio_write[2] = _zz_io_gpio_write_2; + io_gpio_write[3] = _zz_io_gpio_write_3; + end + + always @(*) begin + io_gpio_writeEnable[0] = _zz_io_gpio_writeEnable; + io_gpio_writeEnable[1] = _zz_io_gpio_writeEnable_1; + io_gpio_writeEnable[2] = _zz_io_gpio_writeEnable_2; + io_gpio_writeEnable[3] = _zz_io_gpio_writeEnable_3; + end + + assign interrupt_valid = ((((interrupt_enable_high & syncronized) | (interrupt_enable_low & (~ syncronized))) | (interrupt_enable_rise & (syncronized & (~ last)))) | (interrupt_enable_fall & ((~ syncronized) & last))); + always @(*) begin + io_interrupt[0] = interrupt_valid[0]; + io_interrupt[1] = interrupt_valid[1]; + io_interrupt[2] = 1'b0; + io_interrupt[3] = 1'b0; + end + + always @(*) begin + interrupt_enable_rise[0] = _zz_mapper_rsp_payload_fragment_data; + interrupt_enable_rise[1] = _zz_mapper_rsp_payload_fragment_data_4; + interrupt_enable_rise[2] = 1'b0; + interrupt_enable_rise[3] = 1'b0; + end + + always @(*) begin + interrupt_enable_fall[0] = _zz_mapper_rsp_payload_fragment_data_1; + interrupt_enable_fall[1] = _zz_mapper_rsp_payload_fragment_data_5; + interrupt_enable_fall[2] = 1'b0; + interrupt_enable_fall[3] = 1'b0; + end + + always @(*) begin + interrupt_enable_high[0] = _zz_mapper_rsp_payload_fragment_data_2; + interrupt_enable_high[1] = _zz_mapper_rsp_payload_fragment_data_6; + interrupt_enable_high[2] = 1'b0; + interrupt_enable_high[3] = 1'b0; + end + + always @(*) begin + interrupt_enable_low[0] = _zz_mapper_rsp_payload_fragment_data_3; + interrupt_enable_low[1] = _zz_mapper_rsp_payload_fragment_data_7; + interrupt_enable_low[2] = 1'b0; + interrupt_enable_low[3] = 1'b0; + end + + always @(posedge clk) begin + if(reset) begin + _zz_io_bus_rsp_valid_1 <= 1'b0; + _zz_io_gpio_writeEnable <= 1'b0; + _zz_io_gpio_writeEnable_1 <= 1'b0; + _zz_io_gpio_writeEnable_2 <= 1'b0; + _zz_io_gpio_writeEnable_3 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_1 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_2 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_3 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_4 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_5 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_6 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_7 <= 1'b0; + end else begin + if(_zz_mapper_rsp_ready_1) begin + _zz_io_bus_rsp_valid_1 <= (mapper_rsp_valid && _zz_mapper_rsp_ready); + end + case(io_bus_cmd_payload_fragment_address) + 8'h08 : begin + if(mapper_doWrite) begin + _zz_io_gpio_writeEnable <= io_bus_cmd_payload_fragment_data[0]; + _zz_io_gpio_writeEnable_1 <= io_bus_cmd_payload_fragment_data[1]; + _zz_io_gpio_writeEnable_2 <= io_bus_cmd_payload_fragment_data[2]; + _zz_io_gpio_writeEnable_3 <= io_bus_cmd_payload_fragment_data[3]; + end + end + 8'h20 : begin + if(mapper_doWrite) begin + _zz_mapper_rsp_payload_fragment_data <= io_bus_cmd_payload_fragment_data[0]; + _zz_mapper_rsp_payload_fragment_data_4 <= io_bus_cmd_payload_fragment_data[1]; + end + end + 8'h24 : begin + if(mapper_doWrite) begin + _zz_mapper_rsp_payload_fragment_data_1 <= io_bus_cmd_payload_fragment_data[0]; + _zz_mapper_rsp_payload_fragment_data_5 <= io_bus_cmd_payload_fragment_data[1]; + end + end + 8'h28 : begin + if(mapper_doWrite) begin + _zz_mapper_rsp_payload_fragment_data_2 <= io_bus_cmd_payload_fragment_data[0]; + _zz_mapper_rsp_payload_fragment_data_6 <= io_bus_cmd_payload_fragment_data[1]; + end + end + 8'h2c : begin + if(mapper_doWrite) begin + _zz_mapper_rsp_payload_fragment_data_3 <= io_bus_cmd_payload_fragment_data[0]; + _zz_mapper_rsp_payload_fragment_data_7 <= io_bus_cmd_payload_fragment_data[1]; + end + end + default : begin + end + endcase + end + end + + always @(posedge clk) begin + if(_zz_mapper_rsp_ready_1) begin + _zz_io_bus_rsp_payload_last <= mapper_rsp_payload_last; + _zz_io_bus_rsp_payload_fragment_opcode <= mapper_rsp_payload_fragment_opcode; + _zz_io_bus_rsp_payload_fragment_data <= mapper_rsp_payload_fragment_data; + _zz_io_bus_rsp_payload_fragment_context <= mapper_rsp_payload_fragment_context; + end + io_gpio_read_delay_1 <= io_gpio_read; + syncronized <= io_gpio_read_delay_1; + last <= syncronized; + case(io_bus_cmd_payload_fragment_address) + 8'h04 : begin + if(mapper_doWrite) begin + _zz_io_gpio_write <= io_bus_cmd_payload_fragment_data[0]; + _zz_io_gpio_write_1 <= io_bus_cmd_payload_fragment_data[1]; + _zz_io_gpio_write_2 <= io_bus_cmd_payload_fragment_data[2]; + _zz_io_gpio_write_3 <= io_bus_cmd_payload_fragment_data[3]; + end + end + default : begin + end + endcase + end + + +endmodule + +module Axi4PeripheralBmbI2cCtrl_035069daf0ad4fb491e9c65d79bd2ddd ( + input wire io_ctrl_cmd_valid, + output wire io_ctrl_cmd_ready, + input wire io_ctrl_cmd_payload_last, + input wire [0:0] io_ctrl_cmd_payload_fragment_opcode, + input wire [7:0] io_ctrl_cmd_payload_fragment_address, + input wire [1:0] io_ctrl_cmd_payload_fragment_length, + input wire [31:0] io_ctrl_cmd_payload_fragment_data, + input wire [2:0] io_ctrl_cmd_payload_fragment_context, + output wire io_ctrl_rsp_valid, + input wire io_ctrl_rsp_ready, + output wire io_ctrl_rsp_payload_last, + output wire [0:0] io_ctrl_rsp_payload_fragment_opcode, + output wire [31:0] io_ctrl_rsp_payload_fragment_data, + output wire [2:0] io_ctrl_rsp_payload_fragment_context, + output wire io_i2c_sda_write, + input wire io_i2c_sda_read, + output wire io_i2c_scl_write, + input wire io_i2c_scl_read, + output wire system_i2c_0_io_interrupt_source, + input wire clk, + input wire reset +); + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT = 4'd0; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE = 4'd1; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 = 4'd2; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 = 4'd3; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 = 4'd4; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW = 4'd5; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH = 4'd6; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART = 4'd7; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 = 4'd8; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 = 4'd9; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 = 4'd10; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF = 4'd11; + localparam Axi4PeripheralI2cSlaveCmdMode_NONE = 3'd0; + localparam Axi4PeripheralI2cSlaveCmdMode_START = 3'd1; + localparam Axi4PeripheralI2cSlaveCmdMode_RESTART = 3'd2; + localparam Axi4PeripheralI2cSlaveCmdMode_STOP = 3'd3; + localparam Axi4PeripheralI2cSlaveCmdMode_DROP = 3'd4; + localparam Axi4PeripheralI2cSlaveCmdMode_DRIVE = 3'd5; + localparam Axi4PeripheralI2cSlaveCmdMode_READ = 3'd6; + + reg i2cCtrl_io_config_timeoutClear; + reg i2cCtrl_io_bus_rsp_valid; + reg i2cCtrl_io_bus_rsp_enable; + reg i2cCtrl_io_bus_rsp_data; + wire i2cCtrl_io_i2c_scl_write; + wire i2cCtrl_io_i2c_sda_write; + wire [2:0] i2cCtrl_io_bus_cmd_kind; + wire i2cCtrl_io_bus_cmd_data; + wire i2cCtrl_io_timeout; + wire i2cCtrl_io_internals_inFrame; + wire i2cCtrl_io_internals_sdaRead; + wire i2cCtrl_io_internals_sclRead; + wire [6:0] _zz_bridge_addressFilter_hits_0; + wire [6:0] _zz_bridge_addressFilter_hits_1; + wire [0:0] _zz_bridge_masterLogic_start; + wire [0:0] _zz_bridge_masterLogic_stop; + wire [0:0] _zz_bridge_masterLogic_drop; + wire [0:0] _zz_bridge_masterLogic_recover; + wire [11:0] _zz_bridge_masterLogic_timer_value; + wire [0:0] _zz_bridge_masterLogic_timer_value_1; + wire [0:0] _zz_bridge_masterLogic_fsm_dropped_start; + wire [0:0] _zz_bridge_masterLogic_fsm_dropped_stop; + wire [0:0] _zz_bridge_masterLogic_fsm_dropped_recover; + wire [2:0] _zz_io_bus_rsp_data; + wire [2:0] _zz_bridge_rxData_value; + wire [0:0] _zz_bridge_interruptCtrl_start_flag; + wire [0:0] _zz_bridge_interruptCtrl_restart_flag; + wire [0:0] _zz_bridge_interruptCtrl_end_flag; + wire [0:0] _zz_bridge_interruptCtrl_drop_flag; + wire [0:0] _zz_bridge_interruptCtrl_filterGen_flag; + wire [0:0] _zz_bridge_interruptCtrl_clockGenExit_flag; + wire [0:0] _zz_bridge_interruptCtrl_clockGenEnter_flag; + wire busCtrl_readErrorFlag; + wire busCtrl_writeErrorFlag; + wire busCtrl_readHaltTrigger; + wire busCtrl_writeHaltTrigger; + wire busCtrl_rsp_valid; + wire busCtrl_rsp_ready; + wire busCtrl_rsp_payload_last; + reg [0:0] busCtrl_rsp_payload_fragment_opcode; + reg [31:0] busCtrl_rsp_payload_fragment_data; + wire [2:0] busCtrl_rsp_payload_fragment_context; + wire _zz_busCtrl_rsp_ready; + reg _zz_busCtrl_rsp_ready_1; + wire _zz_io_ctrl_rsp_valid; + reg _zz_io_ctrl_rsp_valid_1; + reg _zz_io_ctrl_rsp_payload_last; + reg [0:0] _zz_io_ctrl_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_ctrl_rsp_payload_fragment_data; + reg [2:0] _zz_io_ctrl_rsp_payload_fragment_context; + wire when_Stream_l375; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire io_ctrl_cmd_fire; + wire busCtrl_doWrite; + wire busCtrl_doRead; + wire when_BmbSlaveFactory_l33; + wire when_BmbSlaveFactory_l35; + wire bridge_busCtrlWithOffset_readErrorFlag; + wire bridge_busCtrlWithOffset_writeErrorFlag; + reg bridge_frameReset; + reg bridge_i2cBuffer_sda_write; + wire bridge_i2cBuffer_sda_read; + reg bridge_i2cBuffer_scl_write; + wire bridge_i2cBuffer_scl_read; + reg bridge_rxData_event; + reg bridge_rxData_listen; + reg bridge_rxData_valid; + reg [7:0] bridge_rxData_value; + reg when_I2cCtrl_l224; + reg bridge_rxAck_listen; + reg bridge_rxAck_valid; + reg bridge_rxAck_value; + reg when_I2cCtrl_l237; + reg bridge_txData_valid; + reg bridge_txData_repeat; + reg bridge_txData_enable; + reg [7:0] bridge_txData_value; + reg bridge_txData_forceDisable; + reg bridge_txData_disableOnDataConflict; + reg bridge_txAck_valid; + reg bridge_txAck_repeat; + reg bridge_txAck_enable; + reg bridge_txAck_value; + reg bridge_txAck_forceAck; + reg bridge_txAck_disableOnDataConflict; + reg bridge_addressFilter_addresses_0_enable; + reg [9:0] bridge_addressFilter_addresses_0_value; + reg bridge_addressFilter_addresses_0_is10Bit; + reg bridge_addressFilter_addresses_1_enable; + reg [9:0] bridge_addressFilter_addresses_1_value; + reg bridge_addressFilter_addresses_1_is10Bit; + reg [1:0] bridge_addressFilter_state; + reg [7:0] bridge_addressFilter_byte0; + reg [7:0] bridge_addressFilter_byte1; + wire bridge_addressFilter_byte0Is10Bit; + wire bridge_addressFilter_hits_0; + wire bridge_addressFilter_hits_1; + wire when_I2cCtrl_l306; + wire _zz_when_I2cCtrl_l310; + reg _zz_when_I2cCtrl_l310_1; + wire when_I2cCtrl_l310; + reg bridge_masterLogic_start; + reg when_BusSlaveFactory_l377; + wire when_BusSlaveFactory_l379; + reg bridge_masterLogic_stop; + reg when_BusSlaveFactory_l377_1; + wire when_BusSlaveFactory_l379_1; + reg bridge_masterLogic_drop; + reg when_BusSlaveFactory_l377_2; + wire when_BusSlaveFactory_l379_2; + reg bridge_masterLogic_recover; + reg when_BusSlaveFactory_l377_3; + wire when_BusSlaveFactory_l379_3; + reg [11:0] bridge_masterLogic_timer_value; + reg [11:0] bridge_masterLogic_timer_tLow; + reg [11:0] bridge_masterLogic_timer_tHigh; + reg [11:0] bridge_masterLogic_timer_tBuf; + wire bridge_masterLogic_timer_done; + wire bridge_masterLogic_txReady; + wire bridge_masterLogic_fsm_wantExit; + reg bridge_masterLogic_fsm_wantStart; + wire bridge_masterLogic_fsm_wantKill; + reg bridge_masterLogic_fsm_dropped_start; + reg bridge_masterLogic_fsm_dropped_stop; + reg bridge_masterLogic_fsm_dropped_recover; + reg bridge_masterLogic_fsm_dropped_trigger; + reg bridge_masterLogic_fsm_inFrameLate; + wire when_I2cCtrl_l363; + wire when_I2cCtrl_l363_1; + wire bridge_masterLogic_fsm_outOfSync; + wire bridge_masterLogic_fsm_isBusy; + reg when_BusSlaveFactory_l341; + wire when_BusSlaveFactory_l347; + reg when_BusSlaveFactory_l341_1; + wire when_BusSlaveFactory_l347_1; + reg when_BusSlaveFactory_l341_2; + wire when_BusSlaveFactory_l347_2; + reg [2:0] bridge_dataCounter; + reg bridge_inAckState; + reg bridge_wasntAck; + wire when_I2cCtrl_l523; + wire when_I2cCtrl_l546; + wire when_I2cCtrl_l566; + wire when_I2cCtrl_l570; + wire when_I2cCtrl_l574; + wire when_I2cCtrl_l578; + wire when_I2cCtrl_l588; + wire when_I2cCtrl_l601; + reg bridge_interruptCtrl_rxDataEnable; + reg bridge_interruptCtrl_rxAckEnable; + reg bridge_interruptCtrl_txDataEnable; + reg bridge_interruptCtrl_txAckEnable; + reg bridge_interruptCtrl_interrupt; + wire when_I2cCtrl_l634; + reg bridge_interruptCtrl_start_enable; + reg bridge_interruptCtrl_start_flag; + wire when_I2cCtrl_l634_1; + reg when_BusSlaveFactory_l341_3; + wire when_BusSlaveFactory_l347_3; + wire when_I2cCtrl_l634_2; + reg bridge_interruptCtrl_restart_enable; + reg bridge_interruptCtrl_restart_flag; + wire when_I2cCtrl_l634_3; + reg when_BusSlaveFactory_l341_4; + wire when_BusSlaveFactory_l347_4; + wire when_I2cCtrl_l634_4; + reg bridge_interruptCtrl_end_enable; + reg bridge_interruptCtrl_end_flag; + wire when_I2cCtrl_l634_5; + reg when_BusSlaveFactory_l341_5; + wire when_BusSlaveFactory_l347_5; + wire when_I2cCtrl_l634_6; + reg bridge_interruptCtrl_drop_enable; + reg bridge_interruptCtrl_drop_flag; + wire when_I2cCtrl_l634_7; + reg when_BusSlaveFactory_l341_6; + wire when_BusSlaveFactory_l347_6; + wire _zz_when_I2cCtrl_l634; + reg _zz_when_I2cCtrl_l634_1; + wire when_I2cCtrl_l634_8; + reg bridge_interruptCtrl_filterGen_enable; + reg bridge_interruptCtrl_filterGen_flag; + wire when_I2cCtrl_l634_9; + reg when_BusSlaveFactory_l341_7; + wire when_BusSlaveFactory_l347_7; + reg bridge_masterLogic_fsm_isBusy_regNext; + wire when_I2cCtrl_l634_10; + reg bridge_interruptCtrl_clockGenExit_enable; + reg bridge_interruptCtrl_clockGenExit_flag; + wire when_I2cCtrl_l634_11; + reg when_BusSlaveFactory_l341_8; + wire when_BusSlaveFactory_l347_8; + reg bridge_masterLogic_fsm_isBusy_regNext_1; + wire when_I2cCtrl_l634_12; + reg bridge_interruptCtrl_clockGenEnter_enable; + reg bridge_interruptCtrl_clockGenEnter_flag; + wire when_I2cCtrl_l634_13; + reg when_BusSlaveFactory_l341_9; + wire when_BusSlaveFactory_l347_9; + reg [9:0] _zz_io_config_samplingClockDivider; + reg [19:0] _zz_io_config_timeout; + reg [5:0] _zz_io_config_tsuData; + reg bridge_timeoutClear; + wire when_I2cCtrl_l659; + reg [3:0] bridge_masterLogic_fsm_stateReg; + reg [3:0] bridge_masterLogic_fsm_stateNext; + reg i2cCtrl_io_internals_inFrame_regNext; + wire when_I2cCtrl_l367; + wire when_I2cCtrl_l369; + wire when_I2cCtrl_l380; + wire when_I2cCtrl_l392; + wire when_I2cCtrl_l418; + wire when_I2cCtrl_l422; + wire when_I2cCtrl_l442; + wire when_I2cCtrl_l450; + wire when_I2cCtrl_l474; + wire when_StateMachine_l253; + wire when_StateMachine_l253_1; + wire when_StateMachine_l253_2; + wire when_StateMachine_l253_3; + wire when_StateMachine_l253_4; + wire when_StateMachine_l253_5; + wire when_I2cCtrl_l350; + reg bridge_slaveOverride_sda; + reg bridge_slaveOverride_scl; + wire when_I2cCtrl_l673; + wire when_I2cCtrl_l674; + reg bridge_i2cBuffer_scl_write_regNext; + reg bridge_i2cBuffer_sda_write_regNext; + `ifndef SYNTHESIS + reg [55:0] bridge_masterLogic_fsm_stateReg_string; + reg [55:0] bridge_masterLogic_fsm_stateNext_string; + `endif + + + assign _zz_bridge_addressFilter_hits_0 = (bridge_addressFilter_byte0 >>> 1'd1); + assign _zz_bridge_addressFilter_hits_1 = (bridge_addressFilter_byte0 >>> 1'd1); + assign _zz_bridge_masterLogic_start = 1'b1; + assign _zz_bridge_masterLogic_stop = 1'b1; + assign _zz_bridge_masterLogic_drop = 1'b1; + assign _zz_bridge_masterLogic_recover = 1'b1; + assign _zz_bridge_masterLogic_timer_value_1 = (! bridge_masterLogic_timer_done); + assign _zz_bridge_masterLogic_timer_value = {11'd0, _zz_bridge_masterLogic_timer_value_1}; + assign _zz_bridge_masterLogic_fsm_dropped_start = 1'b0; + assign _zz_bridge_masterLogic_fsm_dropped_stop = 1'b0; + assign _zz_bridge_masterLogic_fsm_dropped_recover = 1'b0; + assign _zz_io_bus_rsp_data = (3'b111 - bridge_dataCounter); + assign _zz_bridge_rxData_value = (3'b111 - bridge_dataCounter); + assign _zz_bridge_interruptCtrl_start_flag = 1'b0; + assign _zz_bridge_interruptCtrl_restart_flag = 1'b0; + assign _zz_bridge_interruptCtrl_end_flag = 1'b0; + assign _zz_bridge_interruptCtrl_drop_flag = 1'b0; + assign _zz_bridge_interruptCtrl_filterGen_flag = 1'b0; + assign _zz_bridge_interruptCtrl_clockGenExit_flag = 1'b0; + assign _zz_bridge_interruptCtrl_clockGenEnter_flag = 1'b0; + Axi4PeripheralI2cSlave_035069daf0ad4fb491e9c65d79bd2ddd i2cCtrl ( + .io_i2c_sda_write (i2cCtrl_io_i2c_sda_write ), //o + .io_i2c_sda_read (bridge_i2cBuffer_sda_read ), //i + .io_i2c_scl_write (i2cCtrl_io_i2c_scl_write ), //o + .io_i2c_scl_read (bridge_i2cBuffer_scl_read ), //i + .io_config_samplingClockDivider (_zz_io_config_samplingClockDivider[9:0]), //i + .io_config_timeout (_zz_io_config_timeout[19:0] ), //i + .io_config_tsuData (_zz_io_config_tsuData[5:0] ), //i + .io_config_timeoutClear (i2cCtrl_io_config_timeoutClear ), //i + .io_bus_cmd_kind (i2cCtrl_io_bus_cmd_kind[2:0] ), //o + .io_bus_cmd_data (i2cCtrl_io_bus_cmd_data ), //o + .io_bus_rsp_valid (i2cCtrl_io_bus_rsp_valid ), //i + .io_bus_rsp_enable (i2cCtrl_io_bus_rsp_enable ), //i + .io_bus_rsp_data (i2cCtrl_io_bus_rsp_data ), //i + .io_timeout (i2cCtrl_io_timeout ), //o + .io_internals_inFrame (i2cCtrl_io_internals_inFrame ), //o + .io_internals_sdaRead (i2cCtrl_io_internals_sdaRead ), //o + .io_internals_sclRead (i2cCtrl_io_internals_sclRead ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + initial begin + `ifndef SYNTHESIS + _zz_io_config_timeout = {$urandom}; + _zz_io_config_tsuData = {$urandom}; + `endif + end + + `ifndef SYNTHESIS + always @(*) begin + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT : bridge_masterLogic_fsm_stateReg_string = "BOOT "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : bridge_masterLogic_fsm_stateReg_string = "IDLE "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : bridge_masterLogic_fsm_stateReg_string = "START1 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : bridge_masterLogic_fsm_stateReg_string = "START2 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : bridge_masterLogic_fsm_stateReg_string = "START3 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : bridge_masterLogic_fsm_stateReg_string = "LOW "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : bridge_masterLogic_fsm_stateReg_string = "HIGH "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : bridge_masterLogic_fsm_stateReg_string = "RESTART"; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : bridge_masterLogic_fsm_stateReg_string = "STOP1 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : bridge_masterLogic_fsm_stateReg_string = "STOP2 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : bridge_masterLogic_fsm_stateReg_string = "STOP3 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : bridge_masterLogic_fsm_stateReg_string = "TBUF "; + default : bridge_masterLogic_fsm_stateReg_string = "???????"; + endcase + end + always @(*) begin + case(bridge_masterLogic_fsm_stateNext) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT : bridge_masterLogic_fsm_stateNext_string = "BOOT "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : bridge_masterLogic_fsm_stateNext_string = "IDLE "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : bridge_masterLogic_fsm_stateNext_string = "START1 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : bridge_masterLogic_fsm_stateNext_string = "START2 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : bridge_masterLogic_fsm_stateNext_string = "START3 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : bridge_masterLogic_fsm_stateNext_string = "LOW "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : bridge_masterLogic_fsm_stateNext_string = "HIGH "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : bridge_masterLogic_fsm_stateNext_string = "RESTART"; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : bridge_masterLogic_fsm_stateNext_string = "STOP1 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : bridge_masterLogic_fsm_stateNext_string = "STOP2 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : bridge_masterLogic_fsm_stateNext_string = "STOP3 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : bridge_masterLogic_fsm_stateNext_string = "TBUF "; + default : bridge_masterLogic_fsm_stateNext_string = "???????"; + endcase + end + `endif + + assign busCtrl_readErrorFlag = 1'b0; + assign busCtrl_writeErrorFlag = 1'b0; + assign busCtrl_readHaltTrigger = 1'b0; + assign busCtrl_writeHaltTrigger = 1'b0; + assign _zz_busCtrl_rsp_ready = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); + assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready_1 && _zz_busCtrl_rsp_ready); + always @(*) begin + _zz_busCtrl_rsp_ready_1 = io_ctrl_rsp_ready; + if(when_Stream_l375) begin + _zz_busCtrl_rsp_ready_1 = 1'b1; + end + end + + assign when_Stream_l375 = (! _zz_io_ctrl_rsp_valid); + assign _zz_io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid_1; + assign io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid; + assign io_ctrl_rsp_payload_last = _zz_io_ctrl_rsp_payload_last; + assign io_ctrl_rsp_payload_fragment_opcode = _zz_io_ctrl_rsp_payload_fragment_opcode; + assign io_ctrl_rsp_payload_fragment_data = _zz_io_ctrl_rsp_payload_fragment_data; + assign io_ctrl_rsp_payload_fragment_context = _zz_io_ctrl_rsp_payload_fragment_context; + assign busCtrl_askWrite = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_askRead = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign io_ctrl_cmd_fire = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); + assign busCtrl_doWrite = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_doRead = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign busCtrl_rsp_valid = io_ctrl_cmd_valid; + assign io_ctrl_cmd_ready = busCtrl_rsp_ready; + assign busCtrl_rsp_payload_last = 1'b1; + assign when_BmbSlaveFactory_l33 = (busCtrl_doWrite && busCtrl_writeErrorFlag); + always @(*) begin + if(when_BmbSlaveFactory_l33) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + if(when_BmbSlaveFactory_l35) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + busCtrl_rsp_payload_fragment_opcode = 1'b0; + end + end + end + + assign when_BmbSlaveFactory_l35 = (busCtrl_doRead && busCtrl_readErrorFlag); + always @(*) begin + busCtrl_rsp_payload_fragment_data = 32'h0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h08 : begin + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_rxData_valid; + busCtrl_rsp_payload_fragment_data[7 : 0] = bridge_rxData_value; + end + 8'h0c : begin + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_rxAck_valid; + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_rxAck_value; + end + 8'h0 : begin + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_txData_valid; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_txData_enable; + end + 8'h04 : begin + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_txAck_valid; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_txAck_enable; + end + 8'h80 : begin + busCtrl_rsp_payload_fragment_data[1 : 0] = {bridge_addressFilter_hits_1,bridge_addressFilter_hits_0}; + end + 8'h84 : begin + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_addressFilter_byte0[0]; + end + 8'h40 : begin + busCtrl_rsp_payload_fragment_data[4 : 4] = bridge_masterLogic_start; + busCtrl_rsp_payload_fragment_data[5 : 5] = bridge_masterLogic_stop; + busCtrl_rsp_payload_fragment_data[6 : 6] = bridge_masterLogic_drop; + busCtrl_rsp_payload_fragment_data[7 : 7] = bridge_masterLogic_recover; + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_masterLogic_fsm_isBusy; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_masterLogic_fsm_dropped_start; + busCtrl_rsp_payload_fragment_data[10 : 10] = bridge_masterLogic_fsm_dropped_stop; + busCtrl_rsp_payload_fragment_data[11 : 11] = bridge_masterLogic_fsm_dropped_recover; + end + 8'h20 : begin + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_interruptCtrl_rxDataEnable; + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_interruptCtrl_rxAckEnable; + busCtrl_rsp_payload_fragment_data[2 : 2] = bridge_interruptCtrl_txDataEnable; + busCtrl_rsp_payload_fragment_data[3 : 3] = bridge_interruptCtrl_txAckEnable; + busCtrl_rsp_payload_fragment_data[4 : 4] = bridge_interruptCtrl_start_enable; + busCtrl_rsp_payload_fragment_data[5 : 5] = bridge_interruptCtrl_restart_enable; + busCtrl_rsp_payload_fragment_data[6 : 6] = bridge_interruptCtrl_end_enable; + busCtrl_rsp_payload_fragment_data[7 : 7] = bridge_interruptCtrl_drop_enable; + busCtrl_rsp_payload_fragment_data[17 : 17] = bridge_interruptCtrl_filterGen_enable; + busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_interruptCtrl_clockGenExit_enable; + busCtrl_rsp_payload_fragment_data[16 : 16] = bridge_interruptCtrl_clockGenEnter_enable; + end + 8'h24 : begin + busCtrl_rsp_payload_fragment_data[4 : 4] = bridge_interruptCtrl_start_flag; + busCtrl_rsp_payload_fragment_data[5 : 5] = bridge_interruptCtrl_restart_flag; + busCtrl_rsp_payload_fragment_data[6 : 6] = bridge_interruptCtrl_end_flag; + busCtrl_rsp_payload_fragment_data[7 : 7] = bridge_interruptCtrl_drop_flag; + busCtrl_rsp_payload_fragment_data[17 : 17] = bridge_interruptCtrl_filterGen_flag; + busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_interruptCtrl_clockGenExit_flag; + busCtrl_rsp_payload_fragment_data[16 : 16] = bridge_interruptCtrl_clockGenEnter_flag; + end + 8'h44 : begin + busCtrl_rsp_payload_fragment_data[0 : 0] = i2cCtrl_io_internals_inFrame; + busCtrl_rsp_payload_fragment_data[1 : 1] = i2cCtrl_io_internals_sdaRead; + busCtrl_rsp_payload_fragment_data[2 : 2] = i2cCtrl_io_internals_sclRead; + end + 8'h48 : begin + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_slaveOverride_sda; + busCtrl_rsp_payload_fragment_data[2 : 2] = bridge_slaveOverride_scl; + end + default : begin + end + endcase + end + + assign busCtrl_rsp_payload_fragment_context = io_ctrl_cmd_payload_fragment_context; + assign bridge_busCtrlWithOffset_readErrorFlag = 1'b0; + assign bridge_busCtrlWithOffset_writeErrorFlag = 1'b0; + always @(*) begin + bridge_frameReset = 1'b0; + case(i2cCtrl_io_bus_cmd_kind) + Axi4PeripheralI2cSlaveCmdMode_START : begin + bridge_frameReset = 1'b1; + end + Axi4PeripheralI2cSlaveCmdMode_RESTART : begin + bridge_frameReset = 1'b1; + end + Axi4PeripheralI2cSlaveCmdMode_STOP : begin + bridge_frameReset = 1'b1; + end + Axi4PeripheralI2cSlaveCmdMode_DROP : begin + bridge_frameReset = 1'b1; + end + default : begin + end + endcase + end + + always @(*) begin + bridge_i2cBuffer_sda_write = i2cCtrl_io_i2c_sda_write; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + bridge_i2cBuffer_sda_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + bridge_i2cBuffer_sda_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + bridge_i2cBuffer_sda_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + bridge_i2cBuffer_sda_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + end + endcase + if(when_I2cCtrl_l673) begin + bridge_i2cBuffer_sda_write = 1'b0; + end + end + + always @(*) begin + bridge_i2cBuffer_scl_write = i2cCtrl_io_i2c_scl_write; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + bridge_i2cBuffer_scl_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + if(bridge_masterLogic_timer_done) begin + if(when_I2cCtrl_l418) begin + bridge_i2cBuffer_scl_write = 1'b0; + end else begin + if(when_I2cCtrl_l422) begin + bridge_i2cBuffer_scl_write = 1'b0; + end + end + end else begin + bridge_i2cBuffer_scl_write = 1'b0; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + bridge_i2cBuffer_scl_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + end + endcase + if(when_I2cCtrl_l674) begin + bridge_i2cBuffer_scl_write = 1'b0; + end + end + + always @(*) begin + when_I2cCtrl_l224 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h08 : begin + if(busCtrl_doRead) begin + when_I2cCtrl_l224 = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + when_I2cCtrl_l237 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h0c : begin + if(busCtrl_doRead) begin + when_I2cCtrl_l237 = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + bridge_txData_forceDisable = 1'b0; + if(when_I2cCtrl_l601) begin + bridge_txData_forceDisable = 1'b0; + end + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + if(bridge_masterLogic_timer_done) begin + if(when_I2cCtrl_l418) begin + bridge_txData_forceDisable = 1'b1; + end else begin + if(when_I2cCtrl_l422) begin + bridge_txData_forceDisable = 1'b1; + end + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + end + endcase + end + + always @(*) begin + bridge_txAck_forceAck = 1'b0; + if(when_I2cCtrl_l306) begin + bridge_txAck_forceAck = 1'b1; + end + end + + assign bridge_addressFilter_byte0Is10Bit = (bridge_addressFilter_byte0[7 : 3] == 5'h1e); + assign bridge_addressFilter_hits_0 = (bridge_addressFilter_addresses_0_enable && ((! bridge_addressFilter_addresses_0_is10Bit) ? ((_zz_bridge_addressFilter_hits_0 == bridge_addressFilter_addresses_0_value[6 : 0]) && (bridge_addressFilter_state != 2'b00)) : (({bridge_addressFilter_byte0[2 : 1],bridge_addressFilter_byte1} == bridge_addressFilter_addresses_0_value) && (bridge_addressFilter_state == 2'b10)))); + assign bridge_addressFilter_hits_1 = (bridge_addressFilter_addresses_1_enable && ((! bridge_addressFilter_addresses_1_is10Bit) ? ((_zz_bridge_addressFilter_hits_1 == bridge_addressFilter_addresses_1_value[6 : 0]) && (bridge_addressFilter_state != 2'b00)) : (({bridge_addressFilter_byte0[2 : 1],bridge_addressFilter_byte1} == bridge_addressFilter_addresses_1_value) && (bridge_addressFilter_state == 2'b10)))); + assign when_I2cCtrl_l306 = ((bridge_addressFilter_byte0Is10Bit && (bridge_addressFilter_state == 2'b01)) && (|{((bridge_addressFilter_addresses_1_enable && bridge_addressFilter_addresses_1_is10Bit) && (bridge_addressFilter_byte0[2 : 1] == bridge_addressFilter_addresses_1_value[9 : 8])),((bridge_addressFilter_addresses_0_enable && bridge_addressFilter_addresses_0_is10Bit) && (bridge_addressFilter_byte0[2 : 1] == bridge_addressFilter_addresses_0_value[9 : 8]))})); + assign _zz_when_I2cCtrl_l310 = (|{bridge_addressFilter_hits_1,bridge_addressFilter_hits_0}); + assign when_I2cCtrl_l310 = (_zz_when_I2cCtrl_l310 && (! _zz_when_I2cCtrl_l310_1)); + always @(*) begin + when_BusSlaveFactory_l377 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l377 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379 = io_ctrl_cmd_payload_fragment_data[4]; + always @(*) begin + when_BusSlaveFactory_l377_1 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l377_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_1 = io_ctrl_cmd_payload_fragment_data[5]; + always @(*) begin + when_BusSlaveFactory_l377_2 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l377_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_2 = io_ctrl_cmd_payload_fragment_data[6]; + always @(*) begin + when_BusSlaveFactory_l377_3 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l377_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_3 = io_ctrl_cmd_payload_fragment_data[7]; + assign bridge_masterLogic_timer_done = (bridge_masterLogic_timer_value == 12'h0); + assign bridge_masterLogic_fsm_wantExit = 1'b0; + always @(*) begin + bridge_masterLogic_fsm_wantStart = 1'b0; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + bridge_masterLogic_fsm_wantStart = 1'b1; + end + endcase + end + + assign bridge_masterLogic_fsm_wantKill = 1'b0; + always @(*) begin + bridge_masterLogic_fsm_dropped_trigger = 1'b0; + if(when_I2cCtrl_l350) begin + bridge_masterLogic_fsm_dropped_trigger = 1'b1; + end + end + + assign when_I2cCtrl_l363 = (! i2cCtrl_io_internals_sclRead); + assign when_I2cCtrl_l363_1 = (! i2cCtrl_io_internals_inFrame); + assign bridge_masterLogic_fsm_outOfSync = ((! i2cCtrl_io_internals_inFrame) && ((! i2cCtrl_io_internals_sdaRead) || (! i2cCtrl_io_internals_sclRead))); + assign bridge_masterLogic_fsm_isBusy = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE)) && (! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF))); + always @(*) begin + when_BusSlaveFactory_l341 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347 = io_ctrl_cmd_payload_fragment_data[9]; + always @(*) begin + when_BusSlaveFactory_l341_1 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_1 = io_ctrl_cmd_payload_fragment_data[10]; + always @(*) begin + when_BusSlaveFactory_l341_2 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_2 = io_ctrl_cmd_payload_fragment_data[11]; + assign bridge_masterLogic_txReady = (bridge_inAckState ? bridge_txAck_valid : bridge_txData_valid); + assign when_I2cCtrl_l523 = (! bridge_inAckState); + always @(*) begin + if(when_I2cCtrl_l523) begin + i2cCtrl_io_bus_rsp_valid = ((bridge_txData_valid && (! (bridge_rxData_valid && bridge_rxData_listen))) && (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DRIVE)); + if(bridge_txData_forceDisable) begin + i2cCtrl_io_bus_rsp_valid = 1'b1; + end + end else begin + i2cCtrl_io_bus_rsp_valid = ((bridge_txAck_valid && (! (bridge_rxAck_valid && bridge_rxAck_listen))) && (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DRIVE)); + if(bridge_txAck_forceAck) begin + i2cCtrl_io_bus_rsp_valid = 1'b1; + end + end + if(when_I2cCtrl_l546) begin + i2cCtrl_io_bus_rsp_valid = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DRIVE); + end + end + + always @(*) begin + if(when_I2cCtrl_l523) begin + i2cCtrl_io_bus_rsp_enable = bridge_txData_enable; + if(bridge_txData_forceDisable) begin + i2cCtrl_io_bus_rsp_enable = 1'b0; + end + end else begin + i2cCtrl_io_bus_rsp_enable = bridge_txAck_enable; + if(bridge_txAck_forceAck) begin + i2cCtrl_io_bus_rsp_enable = 1'b1; + end + end + if(when_I2cCtrl_l546) begin + i2cCtrl_io_bus_rsp_enable = 1'b0; + end + end + + always @(*) begin + if(when_I2cCtrl_l523) begin + i2cCtrl_io_bus_rsp_data = bridge_txData_value[_zz_io_bus_rsp_data]; + end else begin + i2cCtrl_io_bus_rsp_data = bridge_txAck_value; + if(bridge_txAck_forceAck) begin + i2cCtrl_io_bus_rsp_data = 1'b0; + end + end + end + + assign when_I2cCtrl_l546 = (bridge_wasntAck && (! bridge_masterLogic_fsm_isBusy)); + assign when_I2cCtrl_l566 = (! bridge_inAckState); + assign when_I2cCtrl_l570 = (i2cCtrl_io_bus_rsp_data != i2cCtrl_io_bus_cmd_data); + assign when_I2cCtrl_l574 = (bridge_dataCounter == 3'b111); + assign when_I2cCtrl_l578 = (bridge_txData_valid && (! bridge_txData_repeat)); + assign when_I2cCtrl_l588 = (bridge_txAck_valid && (! bridge_txAck_repeat)); + assign when_I2cCtrl_l601 = ((i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_STOP) || (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DROP)); + always @(*) begin + bridge_interruptCtrl_interrupt = ((((bridge_interruptCtrl_rxDataEnable && bridge_rxData_valid) || (bridge_interruptCtrl_rxAckEnable && bridge_rxAck_valid)) || (bridge_interruptCtrl_txDataEnable && (! bridge_txData_valid))) || (bridge_interruptCtrl_txAckEnable && (! bridge_txAck_valid))); + if(bridge_interruptCtrl_start_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_restart_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_end_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_drop_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_filterGen_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_clockGenExit_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_clockGenEnter_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + end + + assign when_I2cCtrl_l634 = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_START); + assign when_I2cCtrl_l634_1 = (! bridge_interruptCtrl_start_enable); + always @(*) begin + when_BusSlaveFactory_l341_3 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_3 = io_ctrl_cmd_payload_fragment_data[4]; + assign when_I2cCtrl_l634_2 = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_RESTART); + assign when_I2cCtrl_l634_3 = (! bridge_interruptCtrl_restart_enable); + always @(*) begin + when_BusSlaveFactory_l341_4 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_4 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_4 = io_ctrl_cmd_payload_fragment_data[5]; + assign when_I2cCtrl_l634_4 = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_STOP); + assign when_I2cCtrl_l634_5 = (! bridge_interruptCtrl_end_enable); + always @(*) begin + when_BusSlaveFactory_l341_5 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_5 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_5 = io_ctrl_cmd_payload_fragment_data[6]; + assign when_I2cCtrl_l634_6 = ((i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DROP) || bridge_masterLogic_fsm_dropped_trigger); + assign when_I2cCtrl_l634_7 = (! bridge_interruptCtrl_drop_enable); + always @(*) begin + when_BusSlaveFactory_l341_6 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_6 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_6 = io_ctrl_cmd_payload_fragment_data[7]; + assign _zz_when_I2cCtrl_l634 = (|{bridge_addressFilter_hits_1,bridge_addressFilter_hits_0}); + assign when_I2cCtrl_l634_8 = (_zz_when_I2cCtrl_l634 && (! _zz_when_I2cCtrl_l634_1)); + assign when_I2cCtrl_l634_9 = (! bridge_interruptCtrl_filterGen_enable); + always @(*) begin + when_BusSlaveFactory_l341_7 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_7 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_7 = io_ctrl_cmd_payload_fragment_data[17]; + assign when_I2cCtrl_l634_10 = ((! bridge_masterLogic_fsm_isBusy) && bridge_masterLogic_fsm_isBusy_regNext); + assign when_I2cCtrl_l634_11 = (! bridge_interruptCtrl_clockGenExit_enable); + always @(*) begin + when_BusSlaveFactory_l341_8 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_8 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_8 = io_ctrl_cmd_payload_fragment_data[15]; + assign when_I2cCtrl_l634_12 = (bridge_masterLogic_fsm_isBusy && (! bridge_masterLogic_fsm_isBusy_regNext_1)); + assign when_I2cCtrl_l634_13 = (! bridge_interruptCtrl_clockGenEnter_enable); + always @(*) begin + when_BusSlaveFactory_l341_9 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_9 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_9 = io_ctrl_cmd_payload_fragment_data[16]; + always @(*) begin + i2cCtrl_io_config_timeoutClear = bridge_timeoutClear; + if(when_I2cCtrl_l659) begin + i2cCtrl_io_config_timeoutClear = 1'b1; + end + end + + assign when_I2cCtrl_l659 = ((! i2cCtrl_io_internals_inFrame) && (! bridge_masterLogic_fsm_isBusy)); + always @(*) begin + bridge_masterLogic_fsm_stateNext = bridge_masterLogic_fsm_stateReg; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + if(when_I2cCtrl_l367) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF; + end else begin + if(when_I2cCtrl_l369) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1; + end else begin + if(bridge_masterLogic_recover) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW; + end + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + if(when_I2cCtrl_l380) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + if(when_I2cCtrl_l392) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + if(bridge_masterLogic_timer_done) begin + if(when_I2cCtrl_l418) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1; + end else begin + if(when_I2cCtrl_l422) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART; + end else begin + if(i2cCtrl_io_internals_sclRead) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH; + end + end + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + if(when_I2cCtrl_l442) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + if(!when_I2cCtrl_l450) begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1; + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + if(!when_I2cCtrl_l474) begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3; + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + if(i2cCtrl_io_internals_sdaRead) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE; + end + end + default : begin + end + endcase + if(when_I2cCtrl_l350) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF; + end + if(bridge_masterLogic_fsm_wantStart) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE; + end + if(bridge_masterLogic_fsm_wantKill) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT; + end + end + + assign when_I2cCtrl_l367 = ((! i2cCtrl_io_internals_inFrame) && i2cCtrl_io_internals_inFrame_regNext); + assign when_I2cCtrl_l369 = (bridge_masterLogic_start && (! bridge_masterLogic_fsm_inFrameLate)); + assign when_I2cCtrl_l380 = (! bridge_masterLogic_fsm_outOfSync); + assign when_I2cCtrl_l392 = (bridge_masterLogic_timer_done || (! i2cCtrl_io_internals_sclRead)); + assign when_I2cCtrl_l418 = ((bridge_masterLogic_stop && (! bridge_inAckState)) || (bridge_masterLogic_recover && i2cCtrl_io_internals_sdaRead)); + assign when_I2cCtrl_l422 = (bridge_masterLogic_start && (! bridge_inAckState)); + assign when_I2cCtrl_l442 = (bridge_masterLogic_timer_done || (! i2cCtrl_io_internals_sclRead)); + assign when_I2cCtrl_l450 = (! i2cCtrl_io_internals_sclRead); + assign when_I2cCtrl_l474 = (! i2cCtrl_io_internals_sclRead); + assign when_StateMachine_l253 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2)); + assign when_StateMachine_l253_1 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3)); + assign when_StateMachine_l253_2 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW)); + assign when_StateMachine_l253_3 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH)); + assign when_StateMachine_l253_4 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1)); + assign when_StateMachine_l253_5 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF)); + assign when_I2cCtrl_l350 = (bridge_masterLogic_drop || ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE)) && ((i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DROP) || i2cCtrl_io_timeout))); + assign when_I2cCtrl_l673 = (! bridge_slaveOverride_sda); + assign when_I2cCtrl_l674 = (! bridge_slaveOverride_scl); + assign io_i2c_scl_write = bridge_i2cBuffer_scl_write_regNext; + assign io_i2c_sda_write = bridge_i2cBuffer_sda_write_regNext; + assign bridge_i2cBuffer_scl_read = io_i2c_scl_read; + assign bridge_i2cBuffer_sda_read = io_i2c_sda_read; + assign system_i2c_0_io_interrupt_source = bridge_interruptCtrl_interrupt; + always @(posedge clk) begin + if(reset) begin + _zz_io_ctrl_rsp_valid_1 <= 1'b0; + bridge_rxData_event <= 1'b0; + bridge_rxData_listen <= 1'b0; + bridge_rxData_valid <= 1'b0; + bridge_rxAck_listen <= 1'b0; + bridge_rxAck_valid <= 1'b0; + bridge_txData_valid <= 1'b1; + bridge_txData_repeat <= 1'b1; + bridge_txData_enable <= 1'b0; + bridge_txAck_valid <= 1'b1; + bridge_txAck_repeat <= 1'b1; + bridge_txAck_enable <= 1'b0; + bridge_addressFilter_addresses_0_enable <= 1'b0; + bridge_addressFilter_addresses_1_enable <= 1'b0; + bridge_addressFilter_state <= 2'b00; + bridge_masterLogic_start <= 1'b0; + bridge_masterLogic_stop <= 1'b0; + bridge_masterLogic_drop <= 1'b0; + bridge_masterLogic_recover <= 1'b0; + bridge_masterLogic_fsm_dropped_start <= 1'b0; + bridge_masterLogic_fsm_dropped_stop <= 1'b0; + bridge_masterLogic_fsm_dropped_recover <= 1'b0; + bridge_dataCounter <= 3'b000; + bridge_inAckState <= 1'b0; + bridge_wasntAck <= 1'b0; + bridge_interruptCtrl_rxDataEnable <= 1'b0; + bridge_interruptCtrl_rxAckEnable <= 1'b0; + bridge_interruptCtrl_txDataEnable <= 1'b0; + bridge_interruptCtrl_txAckEnable <= 1'b0; + bridge_interruptCtrl_start_enable <= 1'b0; + bridge_interruptCtrl_start_flag <= 1'b0; + bridge_interruptCtrl_restart_enable <= 1'b0; + bridge_interruptCtrl_restart_flag <= 1'b0; + bridge_interruptCtrl_end_enable <= 1'b0; + bridge_interruptCtrl_end_flag <= 1'b0; + bridge_interruptCtrl_drop_enable <= 1'b0; + bridge_interruptCtrl_drop_flag <= 1'b0; + bridge_interruptCtrl_filterGen_enable <= 1'b0; + bridge_interruptCtrl_filterGen_flag <= 1'b0; + bridge_interruptCtrl_clockGenExit_enable <= 1'b0; + bridge_interruptCtrl_clockGenExit_flag <= 1'b0; + bridge_interruptCtrl_clockGenEnter_enable <= 1'b0; + bridge_interruptCtrl_clockGenEnter_flag <= 1'b0; + _zz_io_config_samplingClockDivider <= 10'h0; + bridge_masterLogic_fsm_stateReg <= Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT; + bridge_slaveOverride_sda <= 1'b1; + bridge_slaveOverride_scl <= 1'b1; + bridge_i2cBuffer_scl_write_regNext <= 1'b1; + bridge_i2cBuffer_sda_write_regNext <= 1'b1; + end else begin + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_ctrl_rsp_valid_1 <= (busCtrl_rsp_valid && _zz_busCtrl_rsp_ready); + end + bridge_rxData_event <= 1'b0; + if(when_I2cCtrl_l224) begin + bridge_rxData_valid <= 1'b0; + end + if(when_I2cCtrl_l237) begin + bridge_rxAck_valid <= 1'b0; + end + if(bridge_rxData_event) begin + case(bridge_addressFilter_state) + 2'b00 : begin + bridge_addressFilter_state <= 2'b01; + end + 2'b01 : begin + bridge_addressFilter_state <= 2'b10; + end + default : begin + end + endcase + end + if(bridge_frameReset) begin + bridge_addressFilter_state <= 2'b00; + end + if(when_I2cCtrl_l310) begin + bridge_txAck_valid <= 1'b0; + end + if(when_BusSlaveFactory_l377) begin + if(when_BusSlaveFactory_l379) begin + bridge_masterLogic_start <= _zz_bridge_masterLogic_start[0]; + end + end + if(when_BusSlaveFactory_l377_1) begin + if(when_BusSlaveFactory_l379_1) begin + bridge_masterLogic_stop <= _zz_bridge_masterLogic_stop[0]; + end + end + if(when_BusSlaveFactory_l377_2) begin + if(when_BusSlaveFactory_l379_2) begin + bridge_masterLogic_drop <= _zz_bridge_masterLogic_drop[0]; + end + end + if(when_BusSlaveFactory_l377_3) begin + if(when_BusSlaveFactory_l379_3) begin + bridge_masterLogic_recover <= _zz_bridge_masterLogic_recover[0]; + end + end + if(when_BusSlaveFactory_l341) begin + if(when_BusSlaveFactory_l347) begin + bridge_masterLogic_fsm_dropped_start <= _zz_bridge_masterLogic_fsm_dropped_start[0]; + end + end + if(when_BusSlaveFactory_l341_1) begin + if(when_BusSlaveFactory_l347_1) begin + bridge_masterLogic_fsm_dropped_stop <= _zz_bridge_masterLogic_fsm_dropped_stop[0]; + end + end + if(when_BusSlaveFactory_l341_2) begin + if(when_BusSlaveFactory_l347_2) begin + bridge_masterLogic_fsm_dropped_recover <= _zz_bridge_masterLogic_fsm_dropped_recover[0]; + end + end + case(i2cCtrl_io_bus_cmd_kind) + Axi4PeripheralI2cSlaveCmdMode_READ : begin + if(when_I2cCtrl_l566) begin + bridge_dataCounter <= (bridge_dataCounter + 3'b001); + if(when_I2cCtrl_l570) begin + if(bridge_txData_disableOnDataConflict) begin + bridge_txData_enable <= 1'b0; + end + if(bridge_txAck_disableOnDataConflict) begin + bridge_txAck_enable <= 1'b0; + end + end + if(when_I2cCtrl_l574) begin + if(bridge_rxData_listen) begin + bridge_rxData_valid <= 1'b1; + end + bridge_rxData_event <= 1'b1; + bridge_inAckState <= 1'b1; + if(when_I2cCtrl_l578) begin + bridge_txData_valid <= 1'b0; + end + end + end else begin + if(bridge_rxAck_listen) begin + bridge_rxAck_valid <= 1'b1; + end + bridge_inAckState <= 1'b0; + bridge_wasntAck <= i2cCtrl_io_bus_cmd_data; + if(when_I2cCtrl_l588) begin + bridge_txAck_valid <= 1'b0; + end + end + end + default : begin + end + endcase + if(bridge_frameReset) begin + bridge_inAckState <= 1'b0; + bridge_dataCounter <= 3'b000; + bridge_wasntAck <= 1'b0; + end + if(when_I2cCtrl_l601) begin + bridge_txData_valid <= 1'b1; + bridge_txData_enable <= 1'b0; + bridge_txData_repeat <= 1'b1; + bridge_txAck_valid <= 1'b1; + bridge_txAck_enable <= 1'b0; + bridge_txAck_repeat <= 1'b1; + bridge_rxData_listen <= 1'b0; + bridge_rxAck_listen <= 1'b0; + end + if(when_I2cCtrl_l634) begin + bridge_interruptCtrl_start_flag <= 1'b1; + end + if(when_I2cCtrl_l634_1) begin + bridge_interruptCtrl_start_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_3) begin + if(when_BusSlaveFactory_l347_3) begin + bridge_interruptCtrl_start_flag <= _zz_bridge_interruptCtrl_start_flag[0]; + end + end + if(when_I2cCtrl_l634_2) begin + bridge_interruptCtrl_restart_flag <= 1'b1; + end + if(when_I2cCtrl_l634_3) begin + bridge_interruptCtrl_restart_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_4) begin + if(when_BusSlaveFactory_l347_4) begin + bridge_interruptCtrl_restart_flag <= _zz_bridge_interruptCtrl_restart_flag[0]; + end + end + if(when_I2cCtrl_l634_4) begin + bridge_interruptCtrl_end_flag <= 1'b1; + end + if(when_I2cCtrl_l634_5) begin + bridge_interruptCtrl_end_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_5) begin + if(when_BusSlaveFactory_l347_5) begin + bridge_interruptCtrl_end_flag <= _zz_bridge_interruptCtrl_end_flag[0]; + end + end + if(when_I2cCtrl_l634_6) begin + bridge_interruptCtrl_drop_flag <= 1'b1; + end + if(when_I2cCtrl_l634_7) begin + bridge_interruptCtrl_drop_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_6) begin + if(when_BusSlaveFactory_l347_6) begin + bridge_interruptCtrl_drop_flag <= _zz_bridge_interruptCtrl_drop_flag[0]; + end + end + if(when_I2cCtrl_l634_8) begin + bridge_interruptCtrl_filterGen_flag <= 1'b1; + end + if(when_I2cCtrl_l634_9) begin + bridge_interruptCtrl_filterGen_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_7) begin + if(when_BusSlaveFactory_l347_7) begin + bridge_interruptCtrl_filterGen_flag <= _zz_bridge_interruptCtrl_filterGen_flag[0]; + end + end + if(when_I2cCtrl_l634_10) begin + bridge_interruptCtrl_clockGenExit_flag <= 1'b1; + end + if(when_I2cCtrl_l634_11) begin + bridge_interruptCtrl_clockGenExit_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_8) begin + if(when_BusSlaveFactory_l347_8) begin + bridge_interruptCtrl_clockGenExit_flag <= _zz_bridge_interruptCtrl_clockGenExit_flag[0]; + end + end + if(when_I2cCtrl_l634_12) begin + bridge_interruptCtrl_clockGenEnter_flag <= 1'b1; + end + if(when_I2cCtrl_l634_13) begin + bridge_interruptCtrl_clockGenEnter_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_9) begin + if(when_BusSlaveFactory_l347_9) begin + bridge_interruptCtrl_clockGenEnter_flag <= _zz_bridge_interruptCtrl_clockGenEnter_flag[0]; + end + end + bridge_masterLogic_fsm_stateReg <= bridge_masterLogic_fsm_stateNext; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + if(!when_I2cCtrl_l367) begin + if(when_I2cCtrl_l369) begin + bridge_txData_valid <= 1'b0; + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_start <= 1'b0; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + if(i2cCtrl_io_internals_sdaRead) begin + bridge_masterLogic_stop <= 1'b0; + bridge_masterLogic_recover <= 1'b0; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + end + endcase + if(when_I2cCtrl_l350) begin + bridge_masterLogic_start <= 1'b0; + bridge_masterLogic_stop <= 1'b0; + bridge_masterLogic_drop <= 1'b0; + bridge_masterLogic_recover <= 1'b0; + if(bridge_masterLogic_start) begin + bridge_masterLogic_fsm_dropped_start <= 1'b1; + end + if(bridge_masterLogic_stop) begin + bridge_masterLogic_fsm_dropped_stop <= 1'b1; + end + end + bridge_i2cBuffer_scl_write_regNext <= bridge_i2cBuffer_scl_write; + bridge_i2cBuffer_sda_write_regNext <= bridge_i2cBuffer_sda_write; + case(io_ctrl_cmd_payload_fragment_address) + 8'h08 : begin + if(busCtrl_doWrite) begin + bridge_rxData_listen <= io_ctrl_cmd_payload_fragment_data[9]; + end + end + 8'h0c : begin + if(busCtrl_doWrite) begin + bridge_rxAck_listen <= io_ctrl_cmd_payload_fragment_data[9]; + end + end + 8'h0 : begin + if(busCtrl_doWrite) begin + bridge_txData_repeat <= io_ctrl_cmd_payload_fragment_data[10]; + bridge_txData_valid <= io_ctrl_cmd_payload_fragment_data[8]; + bridge_txData_enable <= io_ctrl_cmd_payload_fragment_data[9]; + end + end + 8'h04 : begin + if(busCtrl_doWrite) begin + bridge_txAck_repeat <= io_ctrl_cmd_payload_fragment_data[10]; + bridge_txAck_valid <= io_ctrl_cmd_payload_fragment_data[8]; + bridge_txAck_enable <= io_ctrl_cmd_payload_fragment_data[9]; + end + end + 8'h88 : begin + if(busCtrl_doWrite) begin + bridge_addressFilter_addresses_0_enable <= io_ctrl_cmd_payload_fragment_data[15]; + end + end + 8'h8c : begin + if(busCtrl_doWrite) begin + bridge_addressFilter_addresses_1_enable <= io_ctrl_cmd_payload_fragment_data[15]; + end + end + 8'h20 : begin + if(busCtrl_doWrite) begin + bridge_interruptCtrl_rxDataEnable <= io_ctrl_cmd_payload_fragment_data[0]; + bridge_interruptCtrl_rxAckEnable <= io_ctrl_cmd_payload_fragment_data[1]; + bridge_interruptCtrl_txDataEnable <= io_ctrl_cmd_payload_fragment_data[2]; + bridge_interruptCtrl_txAckEnable <= io_ctrl_cmd_payload_fragment_data[3]; + bridge_interruptCtrl_start_enable <= io_ctrl_cmd_payload_fragment_data[4]; + bridge_interruptCtrl_restart_enable <= io_ctrl_cmd_payload_fragment_data[5]; + bridge_interruptCtrl_end_enable <= io_ctrl_cmd_payload_fragment_data[6]; + bridge_interruptCtrl_drop_enable <= io_ctrl_cmd_payload_fragment_data[7]; + bridge_interruptCtrl_filterGen_enable <= io_ctrl_cmd_payload_fragment_data[17]; + bridge_interruptCtrl_clockGenExit_enable <= io_ctrl_cmd_payload_fragment_data[15]; + bridge_interruptCtrl_clockGenEnter_enable <= io_ctrl_cmd_payload_fragment_data[16]; + end + end + 8'h28 : begin + if(busCtrl_doWrite) begin + _zz_io_config_samplingClockDivider <= io_ctrl_cmd_payload_fragment_data[9 : 0]; + end + end + 8'h48 : begin + if(busCtrl_doWrite) begin + bridge_slaveOverride_sda <= io_ctrl_cmd_payload_fragment_data[1]; + bridge_slaveOverride_scl <= io_ctrl_cmd_payload_fragment_data[2]; + end + end + default : begin + end + endcase + end + end + + always @(posedge clk) begin + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_ctrl_rsp_payload_last <= busCtrl_rsp_payload_last; + _zz_io_ctrl_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; + _zz_io_ctrl_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; + _zz_io_ctrl_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; + end + if(bridge_rxData_event) begin + case(bridge_addressFilter_state) + 2'b00 : begin + bridge_addressFilter_byte0 <= bridge_rxData_value; + end + 2'b01 : begin + bridge_addressFilter_byte1 <= bridge_rxData_value; + end + default : begin + end + endcase + end + _zz_when_I2cCtrl_l310_1 <= _zz_when_I2cCtrl_l310; + bridge_masterLogic_timer_value <= (bridge_masterLogic_timer_value - _zz_bridge_masterLogic_timer_value); + if(when_I2cCtrl_l363) begin + bridge_masterLogic_fsm_inFrameLate <= 1'b1; + end + if(when_I2cCtrl_l363_1) begin + bridge_masterLogic_fsm_inFrameLate <= 1'b0; + end + case(i2cCtrl_io_bus_cmd_kind) + Axi4PeripheralI2cSlaveCmdMode_READ : begin + if(when_I2cCtrl_l566) begin + bridge_rxData_value[_zz_bridge_rxData_value] <= i2cCtrl_io_bus_cmd_data; + end else begin + bridge_rxAck_value <= i2cCtrl_io_bus_cmd_data; + end + end + default : begin + end + endcase + if(when_I2cCtrl_l601) begin + bridge_txData_disableOnDataConflict <= 1'b0; + bridge_txAck_disableOnDataConflict <= 1'b0; + end + _zz_when_I2cCtrl_l634_1 <= _zz_when_I2cCtrl_l634; + bridge_masterLogic_fsm_isBusy_regNext <= bridge_masterLogic_fsm_isBusy; + bridge_masterLogic_fsm_isBusy_regNext_1 <= bridge_masterLogic_fsm_isBusy; + bridge_timeoutClear <= 1'b0; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + if(when_I2cCtrl_l450) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + if(when_I2cCtrl_l474) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + end + endcase + if(when_StateMachine_l253) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; + end + if(when_StateMachine_l253_1) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tLow; + end + if(when_StateMachine_l253_2) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tLow; + end + if(when_StateMachine_l253_3) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; + end + if(when_StateMachine_l253_4) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; + end + if(when_StateMachine_l253_5) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tBuf; + end + case(io_ctrl_cmd_payload_fragment_address) + 8'h0 : begin + if(busCtrl_doWrite) begin + bridge_txData_value <= io_ctrl_cmd_payload_fragment_data[7 : 0]; + bridge_txData_disableOnDataConflict <= io_ctrl_cmd_payload_fragment_data[11]; + end + end + 8'h04 : begin + if(busCtrl_doWrite) begin + bridge_txAck_value <= io_ctrl_cmd_payload_fragment_data[0]; + bridge_txAck_disableOnDataConflict <= io_ctrl_cmd_payload_fragment_data[11]; + end + end + 8'h88 : begin + if(busCtrl_doWrite) begin + bridge_addressFilter_addresses_0_value <= io_ctrl_cmd_payload_fragment_data[9 : 0]; + bridge_addressFilter_addresses_0_is10Bit <= io_ctrl_cmd_payload_fragment_data[14]; + end + end + 8'h8c : begin + if(busCtrl_doWrite) begin + bridge_addressFilter_addresses_1_value <= io_ctrl_cmd_payload_fragment_data[9 : 0]; + bridge_addressFilter_addresses_1_is10Bit <= io_ctrl_cmd_payload_fragment_data[14]; + end + end + 8'h50 : begin + if(busCtrl_doWrite) begin + bridge_masterLogic_timer_tLow <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 8'h54 : begin + if(busCtrl_doWrite) begin + bridge_masterLogic_timer_tHigh <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 8'h58 : begin + if(busCtrl_doWrite) begin + bridge_masterLogic_timer_tBuf <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 8'h2c : begin + if(busCtrl_doWrite) begin + _zz_io_config_timeout <= io_ctrl_cmd_payload_fragment_data[19 : 0]; + bridge_timeoutClear <= 1'b1; + end + end + 8'h30 : begin + if(busCtrl_doWrite) begin + _zz_io_config_tsuData <= io_ctrl_cmd_payload_fragment_data[5 : 0]; + end + end + default : begin + end + endcase + end + + always @(posedge clk) begin + if(reset) begin + i2cCtrl_io_internals_inFrame_regNext <= 1'b0; + end else begin + i2cCtrl_io_internals_inFrame_regNext <= i2cCtrl_io_internals_inFrame; + end + end + + +endmodule + +module Axi4PeripheralBmbSpiXdrMasterCtrl_035069daf0ad4fb491e9c65d79bd2ddd ( + input wire io_ctrl_cmd_valid, + output wire io_ctrl_cmd_ready, + input wire io_ctrl_cmd_payload_last, + input wire [0:0] io_ctrl_cmd_payload_fragment_opcode, + input wire [11:0] io_ctrl_cmd_payload_fragment_address, + input wire [1:0] io_ctrl_cmd_payload_fragment_length, + input wire [31:0] io_ctrl_cmd_payload_fragment_data, + input wire [2:0] io_ctrl_cmd_payload_fragment_context, + output wire io_ctrl_rsp_valid, + input wire io_ctrl_rsp_ready, + output wire io_ctrl_rsp_payload_last, + output wire [0:0] io_ctrl_rsp_payload_fragment_opcode, + output wire [31:0] io_ctrl_rsp_payload_fragment_data, + output wire [2:0] io_ctrl_rsp_payload_fragment_context, + output wire [0:0] io_spi_sclk_write, + output wire io_spi_data_0_writeEnable, + input wire [0:0] io_spi_data_0_read, + output wire [0:0] io_spi_data_0_write, + output wire io_spi_data_1_writeEnable, + input wire [0:0] io_spi_data_1_read, + output wire [0:0] io_spi_data_1_write, + output wire io_spi_data_2_writeEnable, + input wire [0:0] io_spi_data_2_read, + output wire [0:0] io_spi_data_2_write, + output wire io_spi_data_3_writeEnable, + input wire [0:0] io_spi_data_3_read, + output wire [0:0] io_spi_data_3_write, + output wire [3:0] io_spi_ss, + output wire system_spi_0_io_interrupt_source, + input wire clk, + input wire reset +); + + wire ctrl_io_rsp_queueWithOccupancy_io_pop_ready; + wire ctrl_io_cmd_ready; + wire ctrl_io_rsp_valid; + wire [7:0] ctrl_io_rsp_payload_data; + wire [0:0] ctrl_io_spi_sclk_write; + wire [3:0] ctrl_io_spi_ss; + wire [0:0] ctrl_io_spi_data_0_write; + wire ctrl_io_spi_data_0_writeEnable; + wire [0:0] ctrl_io_spi_data_1_write; + wire ctrl_io_spi_data_1_writeEnable; + wire [0:0] ctrl_io_spi_data_2_write; + wire ctrl_io_spi_data_2_writeEnable; + wire [0:0] ctrl_io_spi_data_3_write; + wire ctrl_io_spi_data_3_writeEnable; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; + wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy; + wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; + wire ctrl_io_rsp_queueWithOccupancy_io_push_ready; + wire ctrl_io_rsp_queueWithOccupancy_io_pop_valid; + wire [7:0] ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_occupancy; + wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_availability; + wire factory_readErrorFlag; + wire factory_writeErrorFlag; + wire factory_readHaltTrigger; + wire factory_writeHaltTrigger; + wire factory_rsp_valid; + wire factory_rsp_ready; + wire factory_rsp_payload_last; + reg [0:0] factory_rsp_payload_fragment_opcode; + reg [31:0] factory_rsp_payload_fragment_data; + wire [2:0] factory_rsp_payload_fragment_context; + wire _zz_factory_rsp_ready; + reg _zz_factory_rsp_ready_1; + wire _zz_io_ctrl_rsp_valid; + reg _zz_io_ctrl_rsp_valid_1; + reg _zz_io_ctrl_rsp_payload_last; + reg [0:0] _zz_io_ctrl_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_ctrl_rsp_payload_fragment_data; + reg [2:0] _zz_io_ctrl_rsp_payload_fragment_context; + wire when_Stream_l375; + wire factory_askWrite; + wire factory_askRead; + wire io_ctrl_cmd_fire; + wire factory_doWrite; + wire factory_doRead; + wire when_BmbSlaveFactory_l33; + wire when_BmbSlaveFactory_l35; + wire [31:0] mapping_cmdLogic_writeData; + reg mapping_cmdLogic_doRegular; + reg mapping_cmdLogic_doWriteLarge; + reg mapping_cmdLogic_doReadWriteLarge; + wire mapping_cmdLogic_streamUnbuffered_valid; + wire mapping_cmdLogic_streamUnbuffered_ready; + wire mapping_cmdLogic_streamUnbuffered_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_payload_read; + wire mapping_cmdLogic_streamUnbuffered_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_payload_data; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write; + reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; + reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; + wire when_Stream_l375_1; + wire ctrl_io_rsp_toStream_valid; + wire ctrl_io_rsp_toStream_ready; + wire [7:0] ctrl_io_rsp_toStream_payload_data; + reg _zz_io_pop_ready; + reg _zz_io_pop_ready_1; + reg mapping_interruptCtrl_cmdIntEnable; + reg mapping_interruptCtrl_rspIntEnable; + wire mapping_interruptCtrl_cmdInt; + wire mapping_interruptCtrl_rspInt; + wire mapping_interruptCtrl_interrupt; + reg _zz_io_config_kind_cpol; + reg _zz_io_config_kind_cpha; + reg [1:0] _zz_io_config_mod; + reg [11:0] _zz_io_config_sclkToggle; + reg [11:0] _zz_io_config_ss_setup; + reg [11:0] _zz_io_config_ss_hold; + reg [11:0] _zz_io_config_ss_disable; + reg [3:0] _zz_io_config_ss_activeHigh; + wire [1:0] _zz_io_config_kind_cpol_1; + + Axi4PeripheralTopLevel_035069daf0ad4fb491e9c65d79bd2ddd ctrl ( + .io_config_kind_cpol (_zz_io_config_kind_cpol ), //i + .io_config_kind_cpha (_zz_io_config_kind_cpha ), //i + .io_config_sclkToggle (_zz_io_config_sclkToggle[11:0] ), //i + .io_config_mod (_zz_io_config_mod[1:0] ), //i + .io_config_ss_activeHigh (_zz_io_config_ss_activeHigh[3:0] ), //i + .io_config_ss_setup (_zz_io_config_ss_setup[11:0] ), //i + .io_config_ss_hold (_zz_io_config_ss_hold[11:0] ), //i + .io_config_ss_disable (_zz_io_config_ss_disable[11:0] ), //i + .io_cmd_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid ), //i + .io_cmd_ready (ctrl_io_cmd_ready ), //o + .io_cmd_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind ), //i + .io_cmd_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read ), //i + .io_cmd_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write ), //i + .io_cmd_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data[7:0]), //i + .io_rsp_valid (ctrl_io_rsp_valid ), //o + .io_rsp_payload_data (ctrl_io_rsp_payload_data[7:0] ), //o + .io_spi_sclk_write (ctrl_io_spi_sclk_write ), //o + .io_spi_data_0_writeEnable (ctrl_io_spi_data_0_writeEnable ), //o + .io_spi_data_0_read (io_spi_data_0_read ), //i + .io_spi_data_0_write (ctrl_io_spi_data_0_write ), //o + .io_spi_data_1_writeEnable (ctrl_io_spi_data_1_writeEnable ), //o + .io_spi_data_1_read (io_spi_data_1_read ), //i + .io_spi_data_1_write (ctrl_io_spi_data_1_write ), //o + .io_spi_data_2_writeEnable (ctrl_io_spi_data_2_writeEnable ), //o + .io_spi_data_2_read (io_spi_data_2_read ), //i + .io_spi_data_2_write (ctrl_io_spi_data_2_write ), //o + .io_spi_data_3_writeEnable (ctrl_io_spi_data_3_writeEnable ), //o + .io_spi_data_3_read (io_spi_data_3_read ), //i + .io_spi_data_3_write (ctrl_io_spi_data_3_write ), //o + .io_spi_ss (ctrl_io_spi_ss[3:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralStreamFifo_2_035069daf0ad4fb491e9c65d79bd2ddd mapping_cmdLogic_streamUnbuffered_queueWithAvailability ( + .io_push_valid (mapping_cmdLogic_streamUnbuffered_valid ), //i + .io_push_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready ), //o + .io_push_payload_kind (mapping_cmdLogic_streamUnbuffered_payload_kind ), //i + .io_push_payload_read (mapping_cmdLogic_streamUnbuffered_payload_read ), //i + .io_push_payload_write (mapping_cmdLogic_streamUnbuffered_payload_write ), //i + .io_push_payload_data (mapping_cmdLogic_streamUnbuffered_payload_data[7:0] ), //i + .io_pop_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid ), //o + .io_pop_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ), //i + .io_pop_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind ), //o + .io_pop_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read ), //o + .io_pop_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write ), //o + .io_pop_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data[7:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy[8:0] ), //o + .io_availability (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability[8:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralStreamFifo_3_035069daf0ad4fb491e9c65d79bd2ddd ctrl_io_rsp_queueWithOccupancy ( + .io_push_valid (ctrl_io_rsp_toStream_valid ), //i + .io_push_ready (ctrl_io_rsp_queueWithOccupancy_io_push_ready ), //o + .io_push_payload_data (ctrl_io_rsp_toStream_payload_data[7:0] ), //i + .io_pop_valid (ctrl_io_rsp_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (ctrl_io_rsp_queueWithOccupancy_io_pop_ready ), //i + .io_pop_payload_data (ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data[7:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (ctrl_io_rsp_queueWithOccupancy_io_occupancy[8:0] ), //o + .io_availability (ctrl_io_rsp_queueWithOccupancy_io_availability[8:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + assign factory_readErrorFlag = 1'b0; + assign factory_writeErrorFlag = 1'b0; + assign factory_readHaltTrigger = 1'b0; + assign factory_writeHaltTrigger = 1'b0; + assign _zz_factory_rsp_ready = (! (factory_readHaltTrigger || factory_writeHaltTrigger)); + assign factory_rsp_ready = (_zz_factory_rsp_ready_1 && _zz_factory_rsp_ready); + always @(*) begin + _zz_factory_rsp_ready_1 = io_ctrl_rsp_ready; + if(when_Stream_l375) begin + _zz_factory_rsp_ready_1 = 1'b1; + end + end + + assign when_Stream_l375 = (! _zz_io_ctrl_rsp_valid); + assign _zz_io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid_1; + assign io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid; + assign io_ctrl_rsp_payload_last = _zz_io_ctrl_rsp_payload_last; + assign io_ctrl_rsp_payload_fragment_opcode = _zz_io_ctrl_rsp_payload_fragment_opcode; + assign io_ctrl_rsp_payload_fragment_data = _zz_io_ctrl_rsp_payload_fragment_data; + assign io_ctrl_rsp_payload_fragment_context = _zz_io_ctrl_rsp_payload_fragment_context; + assign factory_askWrite = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign factory_askRead = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign io_ctrl_cmd_fire = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); + assign factory_doWrite = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign factory_doRead = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign factory_rsp_valid = io_ctrl_cmd_valid; + assign io_ctrl_cmd_ready = factory_rsp_ready; + assign factory_rsp_payload_last = 1'b1; + assign when_BmbSlaveFactory_l33 = (factory_doWrite && factory_writeErrorFlag); + always @(*) begin + if(when_BmbSlaveFactory_l33) begin + factory_rsp_payload_fragment_opcode = 1'b1; + end else begin + if(when_BmbSlaveFactory_l35) begin + factory_rsp_payload_fragment_opcode = 1'b1; + end else begin + factory_rsp_payload_fragment_opcode = 1'b0; + end + end + end + + assign when_BmbSlaveFactory_l35 = (factory_doRead && factory_readErrorFlag); + always @(*) begin + factory_rsp_payload_fragment_data = 32'h0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + factory_rsp_payload_fragment_data[31 : 31] = (! ctrl_io_rsp_queueWithOccupancy_io_pop_valid); + factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + end + 12'h004 : begin + factory_rsp_payload_fragment_data[8 : 0] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; + factory_rsp_payload_fragment_data[24 : 16] = ctrl_io_rsp_queueWithOccupancy_io_occupancy; + end + 12'h00c : begin + factory_rsp_payload_fragment_data[16 : 16] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; + factory_rsp_payload_fragment_data[0 : 0] = mapping_interruptCtrl_cmdIntEnable; + factory_rsp_payload_fragment_data[1 : 1] = mapping_interruptCtrl_rspIntEnable; + factory_rsp_payload_fragment_data[8 : 8] = mapping_interruptCtrl_cmdInt; + factory_rsp_payload_fragment_data[9 : 9] = mapping_interruptCtrl_rspInt; + end + 12'h058 : begin + factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + end + default : begin + end + endcase + end + + assign factory_rsp_payload_fragment_context = io_ctrl_cmd_payload_fragment_context; + always @(*) begin + mapping_cmdLogic_doRegular = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doRegular = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + mapping_cmdLogic_doWriteLarge = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h050 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doWriteLarge = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + mapping_cmdLogic_doReadWriteLarge = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h054 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doReadWriteLarge = 1'b1; + end + end + default : begin + end + endcase + end + + assign mapping_cmdLogic_streamUnbuffered_valid = ((mapping_cmdLogic_doRegular || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_write = (((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[8]) || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_read = ((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[9]) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_kind = (mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[11]); + assign mapping_cmdLogic_streamUnbuffered_payload_data = mapping_cmdLogic_writeData[7:0]; + assign mapping_cmdLogic_streamUnbuffered_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid || (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN)); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data); + always @(*) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; + if(when_Stream_l375_1) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375_1 = (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready = ctrl_io_cmd_ready; + assign ctrl_io_rsp_toStream_valid = ctrl_io_rsp_valid; + assign ctrl_io_rsp_toStream_payload_data = ctrl_io_rsp_payload_data; + assign ctrl_io_rsp_toStream_ready = ctrl_io_rsp_queueWithOccupancy_io_push_ready; + always @(*) begin + _zz_io_pop_ready = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + if(factory_doRead) begin + _zz_io_pop_ready = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + _zz_io_pop_ready_1 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h058 : begin + if(factory_doRead) begin + _zz_io_pop_ready_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign ctrl_io_rsp_queueWithOccupancy_io_pop_ready = (_zz_io_pop_ready || _zz_io_pop_ready_1); + assign mapping_interruptCtrl_cmdInt = (mapping_interruptCtrl_cmdIntEnable && (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid)); + assign mapping_interruptCtrl_rspInt = (mapping_interruptCtrl_rspIntEnable && ctrl_io_rsp_queueWithOccupancy_io_pop_valid); + assign mapping_interruptCtrl_interrupt = (mapping_interruptCtrl_rspInt || mapping_interruptCtrl_cmdInt); + assign io_spi_sclk_write = ctrl_io_spi_sclk_write; + assign io_spi_data_0_writeEnable = ctrl_io_spi_data_0_writeEnable; + assign io_spi_data_0_write = ctrl_io_spi_data_0_write; + assign io_spi_data_1_writeEnable = ctrl_io_spi_data_1_writeEnable; + assign io_spi_data_1_write = ctrl_io_spi_data_1_write; + assign io_spi_data_2_writeEnable = ctrl_io_spi_data_2_writeEnable; + assign io_spi_data_2_write = ctrl_io_spi_data_2_write; + assign io_spi_data_3_writeEnable = ctrl_io_spi_data_3_writeEnable; + assign io_spi_data_3_write = ctrl_io_spi_data_3_write; + assign io_spi_ss = ctrl_io_spi_ss; + assign system_spi_0_io_interrupt_source = mapping_interruptCtrl_interrupt; + assign mapping_cmdLogic_writeData = io_ctrl_cmd_payload_fragment_data[31 : 0]; + assign _zz_io_config_kind_cpol_1 = io_ctrl_cmd_payload_fragment_data[1 : 0]; + always @(posedge clk) begin + if(reset) begin + _zz_io_ctrl_rsp_valid_1 <= 1'b0; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN <= 1'b1; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= 1'b0; + mapping_interruptCtrl_cmdIntEnable <= 1'b0; + mapping_interruptCtrl_rspIntEnable <= 1'b0; + _zz_io_config_ss_activeHigh <= 4'b0000; + end else begin + if(_zz_factory_rsp_ready_1) begin + _zz_io_ctrl_rsp_valid_1 <= (factory_rsp_valid && _zz_factory_rsp_ready); + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN <= 1'b0; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN <= 1'b1; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; + end + case(io_ctrl_cmd_payload_fragment_address) + 12'h00c : begin + if(factory_doWrite) begin + mapping_interruptCtrl_cmdIntEnable <= io_ctrl_cmd_payload_fragment_data[0]; + mapping_interruptCtrl_rspIntEnable <= io_ctrl_cmd_payload_fragment_data[1]; + end + end + 12'h030 : begin + if(factory_doWrite) begin + _zz_io_config_ss_activeHigh <= io_ctrl_cmd_payload_fragment_data[3 : 0]; + end + end + default : begin + end + endcase + end + end + + always @(posedge clk) begin + if(_zz_factory_rsp_ready_1) begin + _zz_io_ctrl_rsp_payload_last <= factory_rsp_payload_last; + _zz_io_ctrl_rsp_payload_fragment_opcode <= factory_rsp_payload_fragment_opcode; + _zz_io_ctrl_rsp_payload_fragment_data <= factory_rsp_payload_fragment_data; + _zz_io_ctrl_rsp_payload_fragment_context <= factory_rsp_payload_fragment_context; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; + end + case(io_ctrl_cmd_payload_fragment_address) + 12'h008 : begin + if(factory_doWrite) begin + _zz_io_config_kind_cpol <= _zz_io_config_kind_cpol_1[0]; + _zz_io_config_kind_cpha <= _zz_io_config_kind_cpol_1[1]; + _zz_io_config_mod <= io_ctrl_cmd_payload_fragment_data[5 : 4]; + end + end + 12'h020 : begin + if(factory_doWrite) begin + _zz_io_config_sclkToggle <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h024 : begin + if(factory_doWrite) begin + _zz_io_config_ss_setup <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h028 : begin + if(factory_doWrite) begin + _zz_io_config_ss_hold <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h02c : begin + if(factory_doWrite) begin + _zz_io_config_ss_disable <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + default : begin + end + endcase + end + + +endmodule + +module Axi4PeripheralBmbUartCtrl_035069daf0ad4fb491e9c65d79bd2ddd ( + input wire io_bus_cmd_valid, + output wire io_bus_cmd_ready, + input wire io_bus_cmd_payload_last, + input wire [0:0] io_bus_cmd_payload_fragment_opcode, + input wire [5:0] io_bus_cmd_payload_fragment_address, + input wire [1:0] io_bus_cmd_payload_fragment_length, + input wire [31:0] io_bus_cmd_payload_fragment_data, + input wire [2:0] io_bus_cmd_payload_fragment_context, + output wire io_bus_rsp_valid, + input wire io_bus_rsp_ready, + output wire io_bus_rsp_payload_last, + output wire [0:0] io_bus_rsp_payload_fragment_opcode, + output wire [31:0] io_bus_rsp_payload_fragment_data, + output wire [2:0] io_bus_rsp_payload_fragment_context, + output wire io_uart_txd, + input wire io_uart_rxd, + output wire system_uart_0_io_interrupt_source, + input wire clk, + input wire reset +); + localparam Axi4PeripheralUartStopType_ONE = 1'd0; + localparam Axi4PeripheralUartStopType_TWO = 1'd1; + localparam Axi4PeripheralUartParityType_NONE = 2'd0; + localparam Axi4PeripheralUartParityType_EVEN = 2'd1; + localparam Axi4PeripheralUartParityType_ODD = 2'd2; + + reg uartCtrl_io_read_queueWithOccupancy_io_pop_ready; + wire uartCtrl_io_write_ready; + wire uartCtrl_io_read_valid; + wire [7:0] uartCtrl_io_read_payload; + wire uartCtrl_io_uart_txd; + wire uartCtrl_io_readError; + wire uartCtrl_io_readBreak; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_availability; + wire uartCtrl_io_read_queueWithOccupancy_io_push_ready; + wire uartCtrl_io_read_queueWithOccupancy_io_pop_valid; + wire [7:0] uartCtrl_io_read_queueWithOccupancy_io_pop_payload; + wire [7:0] uartCtrl_io_read_queueWithOccupancy_io_occupancy; + wire [7:0] uartCtrl_io_read_queueWithOccupancy_io_availability; + wire [0:0] _zz_bridge_misc_readError; + wire [0:0] _zz_bridge_misc_readOverflowError; + wire [0:0] _zz_bridge_misc_breakDetected; + wire [0:0] _zz_bridge_misc_doBreak; + wire [0:0] _zz_bridge_misc_doBreak_1; + wire [7:0] _zz_busCtrl_rsp_payload_fragment_data; + wire busCtrl_readErrorFlag; + wire busCtrl_writeErrorFlag; + wire busCtrl_readHaltTrigger; + wire busCtrl_writeHaltTrigger; + wire busCtrl_rsp_valid; + wire busCtrl_rsp_ready; + wire busCtrl_rsp_payload_last; + reg [0:0] busCtrl_rsp_payload_fragment_opcode; + reg [31:0] busCtrl_rsp_payload_fragment_data; + wire [2:0] busCtrl_rsp_payload_fragment_context; + wire _zz_busCtrl_rsp_ready; + reg _zz_busCtrl_rsp_ready_1; + wire _zz_io_bus_rsp_valid; + reg _zz_io_bus_rsp_valid_1; + reg _zz_io_bus_rsp_payload_last; + reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_bus_rsp_payload_fragment_data; + reg [2:0] _zz_io_bus_rsp_payload_fragment_context; + wire when_Stream_l375; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire io_bus_cmd_fire; + wire busCtrl_doWrite; + wire busCtrl_doRead; + wire when_BmbSlaveFactory_l33; + wire when_BmbSlaveFactory_l35; + wire bridge_busCtrlWrapped_readErrorFlag; + wire bridge_busCtrlWrapped_writeErrorFlag; + reg [2:0] bridge_uartConfigReg_frame_dataLength; + reg [0:0] bridge_uartConfigReg_frame_stop; + reg [1:0] bridge_uartConfigReg_frame_parity; + reg [19:0] bridge_uartConfigReg_clockDivider; + reg _zz_bridge_write_streamUnbuffered_valid; + wire bridge_write_streamUnbuffered_valid; + wire bridge_write_streamUnbuffered_ready; + wire [7:0] bridge_write_streamUnbuffered_payload; + reg bridge_read_streamBreaked_valid; + reg bridge_read_streamBreaked_ready; + wire [7:0] bridge_read_streamBreaked_payload; + reg bridge_interruptCtrl_writeIntEnable; + reg bridge_interruptCtrl_readIntEnable; + wire bridge_interruptCtrl_readInt; + wire bridge_interruptCtrl_writeInt; + wire bridge_interruptCtrl_interrupt; + reg bridge_misc_readError; + reg when_BusSlaveFactory_l341; + wire when_BusSlaveFactory_l347; + reg bridge_misc_readOverflowError; + reg when_BusSlaveFactory_l341_1; + wire when_BusSlaveFactory_l347_1; + wire uartCtrl_io_read_isStall; + reg bridge_misc_breakDetected; + reg uartCtrl_io_readBreak_regNext; + wire when_UartCtrl_l155; + reg when_BusSlaveFactory_l341_2; + wire when_BusSlaveFactory_l347_2; + reg bridge_misc_doBreak; + reg when_BusSlaveFactory_l377; + wire when_BusSlaveFactory_l379; + reg when_BusSlaveFactory_l341_3; + wire when_BusSlaveFactory_l347_3; + wire [1:0] _zz_bridge_uartConfigReg_frame_parity; + wire [0:0] _zz_bridge_uartConfigReg_frame_stop; + wire when_BmbSlaveFactory_l77; + `ifndef SYNTHESIS + reg [23:0] bridge_uartConfigReg_frame_stop_string; + reg [31:0] bridge_uartConfigReg_frame_parity_string; + reg [31:0] _zz_bridge_uartConfigReg_frame_parity_string; + reg [23:0] _zz_bridge_uartConfigReg_frame_stop_string; + `endif + + + assign _zz_bridge_misc_readError = 1'b0; + assign _zz_bridge_misc_readOverflowError = 1'b0; + assign _zz_bridge_misc_breakDetected = 1'b0; + assign _zz_bridge_misc_doBreak = 1'b1; + assign _zz_bridge_misc_doBreak_1 = 1'b0; + assign _zz_busCtrl_rsp_payload_fragment_data = (8'h80 - bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy); + Axi4PeripheralUartCtrl_035069daf0ad4fb491e9c65d79bd2ddd uartCtrl ( + .io_config_frame_dataLength (bridge_uartConfigReg_frame_dataLength[2:0] ), //i + .io_config_frame_stop (bridge_uartConfigReg_frame_stop ), //i + .io_config_frame_parity (bridge_uartConfigReg_frame_parity[1:0] ), //i + .io_config_clockDivider (bridge_uartConfigReg_clockDivider[19:0] ), //i + .io_write_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //i + .io_write_ready (uartCtrl_io_write_ready ), //o + .io_write_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0]), //i + .io_read_valid (uartCtrl_io_read_valid ), //o + .io_read_ready (uartCtrl_io_read_queueWithOccupancy_io_push_ready ), //i + .io_read_payload (uartCtrl_io_read_payload[7:0] ), //o + .io_uart_txd (uartCtrl_io_uart_txd ), //o + .io_uart_rxd (io_uart_rxd ), //i + .io_readError (uartCtrl_io_readError ), //o + .io_writeBreak (bridge_misc_doBreak ), //i + .io_readBreak (uartCtrl_io_readBreak ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralStreamFifo_035069daf0ad4fb491e9c65d79bd2ddd bridge_write_streamUnbuffered_queueWithOccupancy ( + .io_push_valid (bridge_write_streamUnbuffered_valid ), //i + .io_push_ready (bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready ), //o + .io_push_payload (bridge_write_streamUnbuffered_payload[7:0] ), //i + .io_pop_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (uartCtrl_io_write_ready ), //i + .io_pop_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy[7:0] ), //o + .io_availability (bridge_write_streamUnbuffered_queueWithOccupancy_io_availability[7:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralStreamFifo_035069daf0ad4fb491e9c65d79bd2ddd uartCtrl_io_read_queueWithOccupancy ( + .io_push_valid (uartCtrl_io_read_valid ), //i + .io_push_ready (uartCtrl_io_read_queueWithOccupancy_io_push_ready ), //o + .io_push_payload (uartCtrl_io_read_payload[7:0] ), //i + .io_pop_valid (uartCtrl_io_read_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (uartCtrl_io_read_queueWithOccupancy_io_pop_ready ), //i + .io_pop_payload (uartCtrl_io_read_queueWithOccupancy_io_pop_payload[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (uartCtrl_io_read_queueWithOccupancy_io_occupancy[7:0] ), //o + .io_availability (uartCtrl_io_read_queueWithOccupancy_io_availability[7:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(bridge_uartConfigReg_frame_stop) + Axi4PeripheralUartStopType_ONE : bridge_uartConfigReg_frame_stop_string = "ONE"; + Axi4PeripheralUartStopType_TWO : bridge_uartConfigReg_frame_stop_string = "TWO"; + default : bridge_uartConfigReg_frame_stop_string = "???"; + endcase + end + always @(*) begin + case(bridge_uartConfigReg_frame_parity) + Axi4PeripheralUartParityType_NONE : bridge_uartConfigReg_frame_parity_string = "NONE"; + Axi4PeripheralUartParityType_EVEN : bridge_uartConfigReg_frame_parity_string = "EVEN"; + Axi4PeripheralUartParityType_ODD : bridge_uartConfigReg_frame_parity_string = "ODD "; + default : bridge_uartConfigReg_frame_parity_string = "????"; + endcase + end + always @(*) begin + case(_zz_bridge_uartConfigReg_frame_parity) + Axi4PeripheralUartParityType_NONE : _zz_bridge_uartConfigReg_frame_parity_string = "NONE"; + Axi4PeripheralUartParityType_EVEN : _zz_bridge_uartConfigReg_frame_parity_string = "EVEN"; + Axi4PeripheralUartParityType_ODD : _zz_bridge_uartConfigReg_frame_parity_string = "ODD "; + default : _zz_bridge_uartConfigReg_frame_parity_string = "????"; + endcase + end + always @(*) begin + case(_zz_bridge_uartConfigReg_frame_stop) + Axi4PeripheralUartStopType_ONE : _zz_bridge_uartConfigReg_frame_stop_string = "ONE"; + Axi4PeripheralUartStopType_TWO : _zz_bridge_uartConfigReg_frame_stop_string = "TWO"; + default : _zz_bridge_uartConfigReg_frame_stop_string = "???"; + endcase + end + `endif + + assign io_uart_txd = uartCtrl_io_uart_txd; + assign busCtrl_readErrorFlag = 1'b0; + assign busCtrl_writeErrorFlag = 1'b0; + assign busCtrl_readHaltTrigger = 1'b0; + assign busCtrl_writeHaltTrigger = 1'b0; + assign _zz_busCtrl_rsp_ready = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); + assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready_1 && _zz_busCtrl_rsp_ready); + always @(*) begin + _zz_busCtrl_rsp_ready_1 = io_bus_rsp_ready; + if(when_Stream_l375) begin + _zz_busCtrl_rsp_ready_1 = 1'b1; + end + end + + assign when_Stream_l375 = (! _zz_io_bus_rsp_valid); + assign _zz_io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; + assign io_bus_rsp_valid = _zz_io_bus_rsp_valid; + assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; + assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; + assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; + assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; + assign busCtrl_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign busCtrl_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_doRead = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign busCtrl_rsp_valid = io_bus_cmd_valid; + assign io_bus_cmd_ready = busCtrl_rsp_ready; + assign busCtrl_rsp_payload_last = 1'b1; + assign when_BmbSlaveFactory_l33 = (busCtrl_doWrite && busCtrl_writeErrorFlag); + always @(*) begin + if(when_BmbSlaveFactory_l33) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + if(when_BmbSlaveFactory_l35) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + busCtrl_rsp_payload_fragment_opcode = 1'b0; + end + end + end + + assign when_BmbSlaveFactory_l35 = (busCtrl_doRead && busCtrl_readErrorFlag); + always @(*) begin + busCtrl_rsp_payload_fragment_data = 32'h0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + busCtrl_rsp_payload_fragment_data[16 : 16] = (bridge_read_streamBreaked_valid ^ 1'b0); + busCtrl_rsp_payload_fragment_data[7 : 0] = bridge_read_streamBreaked_payload; + end + 6'h04 : begin + busCtrl_rsp_payload_fragment_data[23 : 16] = _zz_busCtrl_rsp_payload_fragment_data; + busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; + busCtrl_rsp_payload_fragment_data[31 : 24] = uartCtrl_io_read_queueWithOccupancy_io_occupancy; + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_interruptCtrl_writeIntEnable; + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_interruptCtrl_readIntEnable; + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_interruptCtrl_writeInt; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_interruptCtrl_readInt; + end + 6'h10 : begin + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_misc_readError; + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_misc_readOverflowError; + busCtrl_rsp_payload_fragment_data[8 : 8] = uartCtrl_io_readBreak; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_misc_breakDetected; + end + default : begin + end + endcase + end + + assign busCtrl_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; + assign bridge_busCtrlWrapped_readErrorFlag = 1'b0; + assign bridge_busCtrlWrapped_writeErrorFlag = 1'b0; + always @(*) begin + _zz_bridge_write_streamUnbuffered_valid = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + if(busCtrl_doWrite) begin + _zz_bridge_write_streamUnbuffered_valid = 1'b1; + end + end + default : begin + end + endcase + end + + assign bridge_write_streamUnbuffered_valid = _zz_bridge_write_streamUnbuffered_valid; + assign bridge_write_streamUnbuffered_payload = io_bus_cmd_payload_fragment_data[7 : 0]; + assign bridge_write_streamUnbuffered_ready = bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + always @(*) begin + bridge_read_streamBreaked_valid = uartCtrl_io_read_queueWithOccupancy_io_pop_valid; + if(uartCtrl_io_readBreak) begin + bridge_read_streamBreaked_valid = 1'b0; + end + end + + always @(*) begin + uartCtrl_io_read_queueWithOccupancy_io_pop_ready = bridge_read_streamBreaked_ready; + if(uartCtrl_io_readBreak) begin + uartCtrl_io_read_queueWithOccupancy_io_pop_ready = 1'b1; + end + end + + assign bridge_read_streamBreaked_payload = uartCtrl_io_read_queueWithOccupancy_io_pop_payload; + always @(*) begin + bridge_read_streamBreaked_ready = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + if(busCtrl_doRead) begin + bridge_read_streamBreaked_ready = 1'b1; + end + end + default : begin + end + endcase + end + + assign bridge_interruptCtrl_readInt = (bridge_interruptCtrl_readIntEnable && bridge_read_streamBreaked_valid); + assign bridge_interruptCtrl_writeInt = (bridge_interruptCtrl_writeIntEnable && (! bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid)); + assign bridge_interruptCtrl_interrupt = (bridge_interruptCtrl_readInt || bridge_interruptCtrl_writeInt); + always @(*) begin + when_BusSlaveFactory_l341 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347 = io_bus_cmd_payload_fragment_data[0]; + always @(*) begin + when_BusSlaveFactory_l341_1 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_1 = io_bus_cmd_payload_fragment_data[1]; + assign uartCtrl_io_read_isStall = (uartCtrl_io_read_valid && (! uartCtrl_io_read_queueWithOccupancy_io_push_ready)); + assign when_UartCtrl_l155 = (uartCtrl_io_readBreak && (! uartCtrl_io_readBreak_regNext)); + always @(*) begin + when_BusSlaveFactory_l341_2 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_2 = io_bus_cmd_payload_fragment_data[9]; + always @(*) begin + when_BusSlaveFactory_l377 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l377 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379 = io_bus_cmd_payload_fragment_data[10]; + always @(*) begin + when_BusSlaveFactory_l341_3 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_3 = io_bus_cmd_payload_fragment_data[11]; + assign system_uart_0_io_interrupt_source = bridge_interruptCtrl_interrupt; + assign _zz_bridge_uartConfigReg_frame_parity = io_bus_cmd_payload_fragment_data[9 : 8]; + assign _zz_bridge_uartConfigReg_frame_stop = io_bus_cmd_payload_fragment_data[16 : 16]; + assign when_BmbSlaveFactory_l77 = ((io_bus_cmd_payload_fragment_address & (~ 6'h03)) == 6'h08); + always @(posedge clk) begin + if(reset) begin + _zz_io_bus_rsp_valid_1 <= 1'b0; + bridge_uartConfigReg_clockDivider <= 20'h0; + bridge_uartConfigReg_clockDivider <= 20'h000d8; + bridge_uartConfigReg_frame_dataLength <= 3'b111; + bridge_uartConfigReg_frame_parity <= Axi4PeripheralUartParityType_NONE; + bridge_uartConfigReg_frame_stop <= Axi4PeripheralUartStopType_ONE; + bridge_interruptCtrl_writeIntEnable <= 1'b0; + bridge_interruptCtrl_readIntEnable <= 1'b0; + bridge_misc_readError <= 1'b0; + bridge_misc_readOverflowError <= 1'b0; + bridge_misc_breakDetected <= 1'b0; + bridge_misc_doBreak <= 1'b0; + end else begin + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_bus_rsp_valid_1 <= (busCtrl_rsp_valid && _zz_busCtrl_rsp_ready); + end + if(when_BusSlaveFactory_l341) begin + if(when_BusSlaveFactory_l347) begin + bridge_misc_readError <= _zz_bridge_misc_readError[0]; + end + end + if(uartCtrl_io_readError) begin + bridge_misc_readError <= 1'b1; + end + if(when_BusSlaveFactory_l341_1) begin + if(when_BusSlaveFactory_l347_1) begin + bridge_misc_readOverflowError <= _zz_bridge_misc_readOverflowError[0]; + end + end + if(uartCtrl_io_read_isStall) begin + bridge_misc_readOverflowError <= 1'b1; + end + if(when_UartCtrl_l155) begin + bridge_misc_breakDetected <= 1'b1; + end + if(when_BusSlaveFactory_l341_2) begin + if(when_BusSlaveFactory_l347_2) begin + bridge_misc_breakDetected <= _zz_bridge_misc_breakDetected[0]; + end + end + if(when_BusSlaveFactory_l377) begin + if(when_BusSlaveFactory_l379) begin + bridge_misc_doBreak <= _zz_bridge_misc_doBreak[0]; + end + end + if(when_BusSlaveFactory_l341_3) begin + if(when_BusSlaveFactory_l347_3) begin + bridge_misc_doBreak <= _zz_bridge_misc_doBreak_1[0]; + end + end + case(io_bus_cmd_payload_fragment_address) + 6'h0c : begin + if(busCtrl_doWrite) begin + bridge_uartConfigReg_frame_dataLength <= io_bus_cmd_payload_fragment_data[2 : 0]; + bridge_uartConfigReg_frame_parity <= _zz_bridge_uartConfigReg_frame_parity; + bridge_uartConfigReg_frame_stop <= _zz_bridge_uartConfigReg_frame_stop; + end + end + 6'h04 : begin + if(busCtrl_doWrite) begin + bridge_interruptCtrl_writeIntEnable <= io_bus_cmd_payload_fragment_data[0]; + bridge_interruptCtrl_readIntEnable <= io_bus_cmd_payload_fragment_data[1]; + end + end + default : begin + end + endcase + if(when_BmbSlaveFactory_l77) begin + if(busCtrl_doWrite) begin + bridge_uartConfigReg_clockDivider[19 : 0] <= io_bus_cmd_payload_fragment_data[19 : 0]; + end + end + end + end + + always @(posedge clk) begin + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_bus_rsp_payload_last <= busCtrl_rsp_payload_last; + _zz_io_bus_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; + _zz_io_bus_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; + _zz_io_bus_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; + end + uartCtrl_io_readBreak_regNext <= uartCtrl_io_readBreak; + end + + +endmodule + +module Axi4PeripheralBmbDecoder_1_035069daf0ad4fb491e9c65d79bd2ddd ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [23:0] io_input_cmd_payload_fragment_address, + input wire [1:0] io_input_cmd_payload_fragment_length, + input wire [31:0] io_input_cmd_payload_fragment_data, + input wire [3:0] io_input_cmd_payload_fragment_mask, + input wire [2:0] io_input_cmd_payload_fragment_context, + output reg io_input_rsp_valid, + input wire io_input_rsp_ready, + output reg io_input_rsp_payload_last, + output reg [0:0] io_input_rsp_payload_fragment_opcode, + output wire [31:0] io_input_rsp_payload_fragment_data, + output reg [2:0] io_input_rsp_payload_fragment_context, + output reg io_outputs_0_cmd_valid, + input wire io_outputs_0_cmd_ready, + output wire io_outputs_0_cmd_payload_last, + output wire [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_0_cmd_payload_fragment_address, + output wire [1:0] io_outputs_0_cmd_payload_fragment_length, + output wire [31:0] io_outputs_0_cmd_payload_fragment_data, + output wire [3:0] io_outputs_0_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_0_cmd_payload_fragment_context, + input wire io_outputs_0_rsp_valid, + output wire io_outputs_0_rsp_ready, + input wire io_outputs_0_rsp_payload_last, + input wire [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_0_rsp_payload_fragment_data, + input wire [2:0] io_outputs_0_rsp_payload_fragment_context, + output reg io_outputs_1_cmd_valid, + input wire io_outputs_1_cmd_ready, + output wire io_outputs_1_cmd_payload_last, + output wire [0:0] io_outputs_1_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_1_cmd_payload_fragment_address, + output wire [1:0] io_outputs_1_cmd_payload_fragment_length, + output wire [31:0] io_outputs_1_cmd_payload_fragment_data, + output wire [3:0] io_outputs_1_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_1_cmd_payload_fragment_context, + input wire io_outputs_1_rsp_valid, + output wire io_outputs_1_rsp_ready, + input wire io_outputs_1_rsp_payload_last, + input wire [0:0] io_outputs_1_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_1_rsp_payload_fragment_data, + input wire [2:0] io_outputs_1_rsp_payload_fragment_context, + output reg io_outputs_2_cmd_valid, + input wire io_outputs_2_cmd_ready, + output wire io_outputs_2_cmd_payload_last, + output wire [0:0] io_outputs_2_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_2_cmd_payload_fragment_address, + output wire [1:0] io_outputs_2_cmd_payload_fragment_length, + output wire [31:0] io_outputs_2_cmd_payload_fragment_data, + output wire [3:0] io_outputs_2_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_2_cmd_payload_fragment_context, + input wire io_outputs_2_rsp_valid, + output wire io_outputs_2_rsp_ready, + input wire io_outputs_2_rsp_payload_last, + input wire [0:0] io_outputs_2_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_2_rsp_payload_fragment_data, + input wire [2:0] io_outputs_2_rsp_payload_fragment_context, + output reg io_outputs_3_cmd_valid, + input wire io_outputs_3_cmd_ready, + output wire io_outputs_3_cmd_payload_last, + output wire [0:0] io_outputs_3_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_3_cmd_payload_fragment_address, + output wire [1:0] io_outputs_3_cmd_payload_fragment_length, + output wire [31:0] io_outputs_3_cmd_payload_fragment_data, + output wire [3:0] io_outputs_3_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_3_cmd_payload_fragment_context, + input wire io_outputs_3_rsp_valid, + output wire io_outputs_3_rsp_ready, + input wire io_outputs_3_rsp_payload_last, + input wire [0:0] io_outputs_3_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_3_rsp_payload_fragment_data, + input wire [2:0] io_outputs_3_rsp_payload_fragment_context, + output reg io_outputs_4_cmd_valid, + input wire io_outputs_4_cmd_ready, + output wire io_outputs_4_cmd_payload_last, + output wire [0:0] io_outputs_4_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_4_cmd_payload_fragment_address, + output wire [1:0] io_outputs_4_cmd_payload_fragment_length, + output wire [31:0] io_outputs_4_cmd_payload_fragment_data, + output wire [3:0] io_outputs_4_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_4_cmd_payload_fragment_context, + input wire io_outputs_4_rsp_valid, + output wire io_outputs_4_rsp_ready, + input wire io_outputs_4_rsp_payload_last, + input wire [0:0] io_outputs_4_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_4_rsp_payload_fragment_data, + input wire [2:0] io_outputs_4_rsp_payload_fragment_context, + output reg io_outputs_5_cmd_valid, + input wire io_outputs_5_cmd_ready, + output wire io_outputs_5_cmd_payload_last, + output wire [0:0] io_outputs_5_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_5_cmd_payload_fragment_address, + output wire [1:0] io_outputs_5_cmd_payload_fragment_length, + output wire [31:0] io_outputs_5_cmd_payload_fragment_data, + output wire [3:0] io_outputs_5_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_5_cmd_payload_fragment_context, + input wire io_outputs_5_rsp_valid, + output wire io_outputs_5_rsp_ready, + input wire io_outputs_5_rsp_payload_last, + input wire [0:0] io_outputs_5_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_5_rsp_payload_fragment_data, + input wire [2:0] io_outputs_5_rsp_payload_fragment_context, + input wire clk, + input wire reset +); + + wire [6:0] _zz_logic_rspPendingCounter; + wire [6:0] _zz_logic_rspPendingCounter_1; + wire [0:0] _zz_logic_rspPendingCounter_2; + wire [6:0] _zz_logic_rspPendingCounter_3; + wire [0:0] _zz_logic_rspPendingCounter_4; + reg _zz_io_input_rsp_payload_last_4; + reg [0:0] _zz_io_input_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_input_rsp_payload_fragment_data; + reg [2:0] _zz_io_input_rsp_payload_fragment_context; + wire logic_input_valid; + reg logic_input_ready; + wire logic_input_payload_last; + wire [0:0] logic_input_payload_fragment_opcode; + wire [23:0] logic_input_payload_fragment_address; + wire [1:0] logic_input_payload_fragment_length; + wire [31:0] logic_input_payload_fragment_data; + wire [3:0] logic_input_payload_fragment_mask; + wire [2:0] logic_input_payload_fragment_context; + wire logic_hitsS0_0; + wire logic_hitsS0_1; + wire logic_hitsS0_2; + wire logic_hitsS0_3; + wire logic_hitsS0_4; + wire logic_hitsS0_5; + wire logic_noHitS0; + wire _zz_io_outputs_0_cmd_payload_last; + wire _zz_io_outputs_1_cmd_payload_last; + wire _zz_io_outputs_2_cmd_payload_last; + wire _zz_io_outputs_3_cmd_payload_last; + wire _zz_io_outputs_4_cmd_payload_last; + wire _zz_io_outputs_5_cmd_payload_last; + reg [6:0] logic_rspPendingCounter; + wire logic_input_fire; + wire io_input_rsp_fire; + wire logic_cmdWait; + wire when_BmbDecoder_l56; + reg logic_rspHits_0; + reg logic_rspHits_1; + reg logic_rspHits_2; + reg logic_rspHits_3; + reg logic_rspHits_4; + reg logic_rspHits_5; + wire logic_rspPending; + wire logic_rspNoHitValid; + reg logic_rspNoHit_doIt; + wire when_BmbDecoder_l60; + wire when_BmbDecoder_l60_1; + reg logic_rspNoHit_singleBeatRsp; + reg [2:0] logic_rspNoHit_context; + wire _zz_io_input_rsp_payload_last; + wire _zz_io_input_rsp_payload_last_1; + wire _zz_io_input_rsp_payload_last_2; + wire [2:0] _zz_io_input_rsp_payload_last_3; + + assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); + assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); + assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; + assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; + always @(*) begin + case(_zz_io_input_rsp_payload_last_3) + 3'b000 : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_0_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_0_rsp_payload_fragment_context; + end + 3'b001 : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_1_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_1_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_1_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_1_rsp_payload_fragment_context; + end + 3'b010 : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_2_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_2_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_2_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_2_rsp_payload_fragment_context; + end + 3'b011 : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_3_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_3_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_3_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_3_rsp_payload_fragment_context; + end + 3'b100 : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_4_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_4_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_4_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_4_rsp_payload_fragment_context; + end + default : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_5_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_5_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_5_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_5_rsp_payload_fragment_context; + end + endcase + end + + assign logic_input_valid = io_input_cmd_valid; + assign io_input_cmd_ready = logic_input_ready; + assign logic_input_payload_last = io_input_cmd_payload_last; + assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign logic_input_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign logic_noHitS0 = (! (|{logic_hitsS0_5,{logic_hitsS0_4,{logic_hitsS0_3,{logic_hitsS0_2,{logic_hitsS0_1,logic_hitsS0_0}}}}})); + assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 24'h00003f)) == 24'h010000); + always @(*) begin + io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); + if(logic_cmdWait) begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; + assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; + assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_0_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_1 = ((io_input_cmd_payload_fragment_address & (~ 24'h000fff)) == 24'h030000); + always @(*) begin + io_outputs_1_cmd_valid = (logic_input_valid && logic_hitsS0_1); + if(logic_cmdWait) begin + io_outputs_1_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_1_cmd_payload_last = logic_input_payload_last; + assign io_outputs_1_cmd_payload_last = _zz_io_outputs_1_cmd_payload_last; + assign io_outputs_1_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_1_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_1_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_1_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_1_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_1_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_2 = ((io_input_cmd_payload_fragment_address & (~ 24'h0000ff)) == 24'h020000); + always @(*) begin + io_outputs_2_cmd_valid = (logic_input_valid && logic_hitsS0_2); + if(logic_cmdWait) begin + io_outputs_2_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_2_cmd_payload_last = logic_input_payload_last; + assign io_outputs_2_cmd_payload_last = _zz_io_outputs_2_cmd_payload_last; + assign io_outputs_2_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_2_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_2_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_2_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_2_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_2_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_3 = ((io_input_cmd_payload_fragment_address & (~ 24'h0000ff)) == 24'h040000); + always @(*) begin + io_outputs_3_cmd_valid = (logic_input_valid && logic_hitsS0_3); + if(logic_cmdWait) begin + io_outputs_3_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_3_cmd_payload_last = logic_input_payload_last; + assign io_outputs_3_cmd_payload_last = _zz_io_outputs_3_cmd_payload_last; + assign io_outputs_3_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_3_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_3_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_3_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_3_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_3_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_4 = ((io_input_cmd_payload_fragment_address & (~ 24'h0000ff)) == 24'h050000); + always @(*) begin + io_outputs_4_cmd_valid = (logic_input_valid && logic_hitsS0_4); + if(logic_cmdWait) begin + io_outputs_4_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_4_cmd_payload_last = logic_input_payload_last; + assign io_outputs_4_cmd_payload_last = _zz_io_outputs_4_cmd_payload_last; + assign io_outputs_4_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_4_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_4_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_4_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_4_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_4_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_5 = ((io_input_cmd_payload_fragment_address & (~ 24'h00ffff)) == 24'h100000); + always @(*) begin + io_outputs_5_cmd_valid = (logic_input_valid && logic_hitsS0_5); + if(logic_cmdWait) begin + io_outputs_5_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_5_cmd_payload_last = logic_input_payload_last; + assign io_outputs_5_cmd_payload_last = _zz_io_outputs_5_cmd_payload_last; + assign io_outputs_5_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_5_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_5_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_5_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_5_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_5_cmd_payload_fragment_context = logic_input_payload_fragment_context; + always @(*) begin + logic_input_ready = ((|{(logic_hitsS0_5 && io_outputs_5_cmd_ready),{(logic_hitsS0_4 && io_outputs_4_cmd_ready),{(logic_hitsS0_3 && io_outputs_3_cmd_ready),{(logic_hitsS0_2 && io_outputs_2_cmd_ready),{(logic_hitsS0_1 && io_outputs_1_cmd_ready),(logic_hitsS0_0 && io_outputs_0_cmd_ready)}}}}}) || logic_noHitS0); + if(logic_cmdWait) begin + logic_input_ready = 1'b0; + end + end + + assign logic_input_fire = (logic_input_valid && logic_input_ready); + assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); + assign logic_rspPending = (logic_rspPendingCounter != 7'h0); + assign logic_rspNoHitValid = (! (|{logic_rspHits_5,{logic_rspHits_4,{logic_rspHits_3,{logic_rspHits_2,{logic_rspHits_1,logic_rspHits_0}}}}})); + assign when_BmbDecoder_l60 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign when_BmbDecoder_l60_1 = ((logic_input_fire && logic_noHitS0) && logic_input_payload_last); + always @(*) begin + io_input_rsp_valid = ((|{io_outputs_5_rsp_valid,{io_outputs_4_rsp_valid,{io_outputs_3_rsp_valid,{io_outputs_2_rsp_valid,{io_outputs_1_rsp_valid,io_outputs_0_rsp_valid}}}}}) || (logic_rspPending && logic_rspNoHitValid)); + if(logic_rspNoHit_doIt) begin + io_input_rsp_valid = 1'b1; + end + end + + assign _zz_io_input_rsp_payload_last = ((logic_rspHits_1 || logic_rspHits_3) || logic_rspHits_5); + assign _zz_io_input_rsp_payload_last_1 = (logic_rspHits_2 || logic_rspHits_3); + assign _zz_io_input_rsp_payload_last_2 = (logic_rspHits_4 || logic_rspHits_5); + assign _zz_io_input_rsp_payload_last_3 = {_zz_io_input_rsp_payload_last_2,{_zz_io_input_rsp_payload_last_1,_zz_io_input_rsp_payload_last}}; + always @(*) begin + io_input_rsp_payload_last = _zz_io_input_rsp_payload_last_4; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_last = 1'b1; + end + end + + always @(*) begin + io_input_rsp_payload_fragment_opcode = _zz_io_input_rsp_payload_fragment_opcode; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_opcode = 1'b1; + end + end + + assign io_input_rsp_payload_fragment_data = _zz_io_input_rsp_payload_fragment_data; + always @(*) begin + io_input_rsp_payload_fragment_context = _zz_io_input_rsp_payload_fragment_context; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_context = logic_rspNoHit_context; + end + end + + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign io_outputs_1_rsp_ready = io_input_rsp_ready; + assign io_outputs_2_rsp_ready = io_input_rsp_ready; + assign io_outputs_3_rsp_ready = io_input_rsp_ready; + assign io_outputs_4_rsp_ready = io_input_rsp_ready; + assign io_outputs_5_rsp_ready = io_input_rsp_ready; + assign logic_cmdWait = ((logic_rspPending && (((((((logic_hitsS0_0 != logic_rspHits_0) || (logic_hitsS0_1 != logic_rspHits_1)) || (logic_hitsS0_2 != logic_rspHits_2)) || (logic_hitsS0_3 != logic_rspHits_3)) || (logic_hitsS0_4 != logic_rspHits_4)) || (logic_hitsS0_5 != logic_rspHits_5)) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); + always @(posedge clk) begin + if(reset) begin + logic_rspPendingCounter <= 7'h0; + logic_rspNoHit_doIt <= 1'b0; + end else begin + logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); + if(when_BmbDecoder_l60) begin + logic_rspNoHit_doIt <= 1'b0; + end + if(when_BmbDecoder_l60_1) begin + logic_rspNoHit_doIt <= 1'b1; + end + end + end + + always @(posedge clk) begin + if(when_BmbDecoder_l56) begin + logic_rspHits_0 <= logic_hitsS0_0; + logic_rspHits_1 <= logic_hitsS0_1; + logic_rspHits_2 <= logic_hitsS0_2; + logic_rspHits_3 <= logic_hitsS0_3; + logic_rspHits_4 <= logic_hitsS0_4; + logic_rspHits_5 <= logic_hitsS0_5; + end + if(logic_input_fire) begin + logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); + end + if(logic_input_fire) begin + logic_rspNoHit_context <= logic_input_payload_fragment_context; + end + end + + +endmodule + +module Axi4PeripheralBmbUnburstify_035069daf0ad4fb491e9c65d79bd2ddd ( + input wire io_input_cmd_valid, + output reg io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_source, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [23:0] io_input_cmd_payload_fragment_address, + input wire [9:0] io_input_cmd_payload_fragment_length, + input wire [31:0] io_input_cmd_payload_fragment_data, + input wire [3:0] io_input_cmd_payload_fragment_mask, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_source, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [31:0] io_input_rsp_payload_fragment_data, + output reg io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output reg [0:0] io_output_cmd_payload_fragment_opcode, + output reg [23:0] io_output_cmd_payload_fragment_address, + output reg [1:0] io_output_cmd_payload_fragment_length, + output wire [31:0] io_output_cmd_payload_fragment_data, + output wire [3:0] io_output_cmd_payload_fragment_mask, + output wire [2:0] io_output_cmd_payload_fragment_context, + input wire io_output_rsp_valid, + output reg io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [31:0] io_output_rsp_payload_fragment_data, + input wire [2:0] io_output_rsp_payload_fragment_context, + input wire clk, + input wire reset +); + + wire [7:0] _zz_buffer_last; + wire [0:0] _zz_buffer_last_1; + wire [11:0] _zz_buffer_addressIncr; + wire doResult; + reg buffer_valid; + reg [0:0] buffer_opcode; + reg [0:0] buffer_source; + reg [23:0] buffer_address; + reg [7:0] buffer_beat; + wire buffer_last; + wire [23:0] buffer_addressIncr; + wire buffer_isWrite; + wire io_output_cmd_fire; + wire [7:0] cmdTransferBeatCount; + wire requireBuffer; + reg cmdContext_drop; + reg cmdContext_last; + reg [0:0] cmdContext_source; + wire rspContext_drop; + wire rspContext_last; + wire [0:0] rspContext_source; + wire [2:0] _zz_rspContext_drop; + wire when_Stream_l445; + reg io_output_rsp_thrown_valid; + wire io_output_rsp_thrown_ready; + wire io_output_rsp_thrown_payload_last; + wire [0:0] io_output_rsp_thrown_payload_fragment_opcode; + wire [31:0] io_output_rsp_thrown_payload_fragment_data; + wire [2:0] io_output_rsp_thrown_payload_fragment_context; + + assign _zz_buffer_last_1 = 1'b1; + assign _zz_buffer_last = {7'd0, _zz_buffer_last_1}; + assign _zz_buffer_addressIncr = (buffer_address[11 : 0] + 12'h004); + assign buffer_last = (buffer_beat == _zz_buffer_last); + assign buffer_addressIncr = {buffer_address[23 : 12],(_zz_buffer_addressIncr & (~ 12'h003))}; + assign buffer_isWrite = (buffer_opcode == 1'b1); + assign io_output_cmd_fire = (io_output_cmd_valid && io_output_cmd_ready); + assign cmdTransferBeatCount = io_input_cmd_payload_fragment_length[9 : 2]; + assign requireBuffer = (cmdTransferBeatCount != 8'h0); + assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign io_output_cmd_payload_last = 1'b1; + assign io_output_cmd_payload_fragment_context = {cmdContext_source,{cmdContext_last,cmdContext_drop}}; + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_address = buffer_addressIncr; + end else begin + io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + if(requireBuffer) begin + io_output_cmd_payload_fragment_address[1 : 0] = 2'b00; + end + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_opcode = buffer_opcode; + end else begin + io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_length = 2'b11; + end else begin + if(requireBuffer) begin + io_output_cmd_payload_fragment_length = 2'b11; + end else begin + io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length[1:0]; + end + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_source = buffer_source; + end else begin + cmdContext_source = io_input_cmd_payload_fragment_source; + end + end + + always @(*) begin + io_input_cmd_ready = 1'b0; + if(buffer_valid) begin + io_input_cmd_ready = (buffer_isWrite && io_output_cmd_ready); + end else begin + io_input_cmd_ready = io_output_cmd_ready; + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_valid = (! (buffer_isWrite && (! io_input_cmd_valid))); + end else begin + io_output_cmd_valid = io_input_cmd_valid; + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_last = buffer_last; + end else begin + cmdContext_last = (! requireBuffer); + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_drop = buffer_isWrite; + end else begin + cmdContext_drop = (io_input_cmd_payload_fragment_opcode == 1'b1); + end + end + + assign _zz_rspContext_drop = io_output_rsp_payload_fragment_context; + assign rspContext_drop = _zz_rspContext_drop[0]; + assign rspContext_last = _zz_rspContext_drop[1]; + assign rspContext_source = _zz_rspContext_drop[2 : 2]; + assign when_Stream_l445 = (! (rspContext_last || (! rspContext_drop))); + always @(*) begin + io_output_rsp_thrown_valid = io_output_rsp_valid; + if(when_Stream_l445) begin + io_output_rsp_thrown_valid = 1'b0; + end + end + + always @(*) begin + io_output_rsp_ready = io_output_rsp_thrown_ready; + if(when_Stream_l445) begin + io_output_rsp_ready = 1'b1; + end + end + + assign io_output_rsp_thrown_payload_last = io_output_rsp_payload_last; + assign io_output_rsp_thrown_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_output_rsp_thrown_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_output_rsp_thrown_payload_fragment_context = io_output_rsp_payload_fragment_context; + assign io_input_rsp_valid = io_output_rsp_thrown_valid; + assign io_output_rsp_thrown_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = rspContext_last; + assign io_input_rsp_payload_fragment_source = rspContext_source; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + always @(posedge clk) begin + if(reset) begin + buffer_valid <= 1'b0; + end else begin + if(io_output_cmd_fire) begin + if(buffer_last) begin + buffer_valid <= 1'b0; + end + end + if(!buffer_valid) begin + buffer_valid <= (requireBuffer && io_output_cmd_fire); + end + end + end + + always @(posedge clk) begin + if(io_output_cmd_fire) begin + buffer_beat <= (buffer_beat - 8'h01); + buffer_address[11 : 0] <= buffer_addressIncr[11 : 0]; + end + if(!buffer_valid) begin + buffer_opcode <= io_input_cmd_payload_fragment_opcode; + buffer_source <= io_input_cmd_payload_fragment_source; + buffer_address <= io_input_cmd_payload_fragment_address; + buffer_beat <= cmdTransferBeatCount; + end + end + + +endmodule + +module Axi4PeripheralBmbDecoder_035069daf0ad4fb491e9c65d79bd2ddd ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_source, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [23:0] io_input_cmd_payload_fragment_address, + input wire [9:0] io_input_cmd_payload_fragment_length, + input wire [31:0] io_input_cmd_payload_fragment_data, + input wire [3:0] io_input_cmd_payload_fragment_mask, + output reg io_input_rsp_valid, + input wire io_input_rsp_ready, + output reg io_input_rsp_payload_last, + output reg [0:0] io_input_rsp_payload_fragment_source, + output reg [0:0] io_input_rsp_payload_fragment_opcode, + output wire [31:0] io_input_rsp_payload_fragment_data, + output reg io_outputs_0_cmd_valid, + input wire io_outputs_0_cmd_ready, + output wire io_outputs_0_cmd_payload_last, + output wire [0:0] io_outputs_0_cmd_payload_fragment_source, + output wire [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_0_cmd_payload_fragment_address, + output wire [9:0] io_outputs_0_cmd_payload_fragment_length, + output wire [31:0] io_outputs_0_cmd_payload_fragment_data, + output wire [3:0] io_outputs_0_cmd_payload_fragment_mask, + input wire io_outputs_0_rsp_valid, + output wire io_outputs_0_rsp_ready, + input wire io_outputs_0_rsp_payload_last, + input wire [0:0] io_outputs_0_rsp_payload_fragment_source, + input wire [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_0_rsp_payload_fragment_data, + input wire clk, + input wire reset +); + + wire [6:0] _zz_logic_rspPendingCounter; + wire [6:0] _zz_logic_rspPendingCounter_1; + wire [0:0] _zz_logic_rspPendingCounter_2; + wire [6:0] _zz_logic_rspPendingCounter_3; + wire [0:0] _zz_logic_rspPendingCounter_4; + wire logic_input_valid; + reg logic_input_ready; + wire logic_input_payload_last; + wire [0:0] logic_input_payload_fragment_source; + wire [0:0] logic_input_payload_fragment_opcode; + wire [23:0] logic_input_payload_fragment_address; + wire [9:0] logic_input_payload_fragment_length; + wire [31:0] logic_input_payload_fragment_data; + wire [3:0] logic_input_payload_fragment_mask; + wire logic_hitsS0_0; + wire logic_noHitS0; + wire _zz_io_outputs_0_cmd_payload_last; + reg [6:0] logic_rspPendingCounter; + wire logic_input_fire; + wire io_input_rsp_fire; + wire logic_cmdWait; + wire when_BmbDecoder_l56; + reg logic_rspHits_0; + wire logic_rspPending; + wire logic_rspNoHitValid; + reg logic_rspNoHit_doIt; + wire when_BmbDecoder_l60; + wire when_BmbDecoder_l60_1; + reg logic_rspNoHit_singleBeatRsp; + reg [0:0] logic_rspNoHit_source; + reg [7:0] logic_rspNoHit_counter; + wire when_BmbDecoder_l81; + + assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); + assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); + assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; + assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; + assign logic_input_valid = io_input_cmd_valid; + assign io_input_cmd_ready = logic_input_ready; + assign logic_input_payload_last = io_input_cmd_payload_last; + assign logic_input_payload_fragment_source = io_input_cmd_payload_fragment_source; + assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign logic_noHitS0 = (! (|logic_hitsS0_0)); + assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 24'hffffff)) == 24'h0); + always @(*) begin + io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); + if(logic_cmdWait) begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; + assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; + assign io_outputs_0_cmd_payload_fragment_source = logic_input_payload_fragment_source; + assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + always @(*) begin + logic_input_ready = ((|(logic_hitsS0_0 && io_outputs_0_cmd_ready)) || logic_noHitS0); + if(logic_cmdWait) begin + logic_input_ready = 1'b0; + end + end + + assign logic_input_fire = (logic_input_valid && logic_input_ready); + assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); + assign logic_rspPending = (logic_rspPendingCounter != 7'h0); + assign logic_rspNoHitValid = (! (|logic_rspHits_0)); + assign when_BmbDecoder_l60 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign when_BmbDecoder_l60_1 = ((logic_input_fire && logic_noHitS0) && logic_input_payload_last); + always @(*) begin + io_input_rsp_valid = ((|io_outputs_0_rsp_valid) || (logic_rspPending && logic_rspNoHitValid)); + if(logic_rspNoHit_doIt) begin + io_input_rsp_valid = 1'b1; + end + end + + always @(*) begin + io_input_rsp_payload_last = io_outputs_0_rsp_payload_last; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_last = 1'b0; + if(when_BmbDecoder_l81) begin + io_input_rsp_payload_last = 1'b1; + end + if(logic_rspNoHit_singleBeatRsp) begin + io_input_rsp_payload_last = 1'b1; + end + end + end + + always @(*) begin + io_input_rsp_payload_fragment_source = io_outputs_0_rsp_payload_fragment_source; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_source = logic_rspNoHit_source; + end + end + + always @(*) begin + io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_opcode = 1'b1; + end + end + + assign io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + assign when_BmbDecoder_l81 = (logic_rspNoHit_counter == 8'h0); + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign logic_cmdWait = ((logic_rspPending && ((logic_hitsS0_0 != logic_rspHits_0) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); + always @(posedge clk) begin + if(reset) begin + logic_rspPendingCounter <= 7'h0; + logic_rspNoHit_doIt <= 1'b0; + end else begin + logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); + if(when_BmbDecoder_l60) begin + logic_rspNoHit_doIt <= 1'b0; + end + if(when_BmbDecoder_l60_1) begin + logic_rspNoHit_doIt <= 1'b1; + end + end + end + + always @(posedge clk) begin + if(when_BmbDecoder_l56) begin + logic_rspHits_0 <= logic_hitsS0_0; + end + if(logic_input_fire) begin + logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); + end + if(logic_input_fire) begin + logic_rspNoHit_source <= logic_input_payload_fragment_source; + end + if(logic_input_fire) begin + logic_rspNoHit_counter <= logic_input_payload_fragment_length[9 : 2]; + end + if(logic_rspNoHit_doIt) begin + if(io_input_rsp_fire) begin + logic_rspNoHit_counter <= (logic_rspNoHit_counter - 8'h01); + end + end + end + + +endmodule + +module Axi4PeripheralAxi4SharedToBmb_035069daf0ad4fb491e9c65d79bd2ddd ( + input wire io_axi_arw_valid, + output wire io_axi_arw_ready, + input wire [23:0] io_axi_arw_payload_addr, + input wire [7:0] io_axi_arw_payload_len, + input wire [2:0] io_axi_arw_payload_size, + input wire [3:0] io_axi_arw_payload_cache, + input wire [2:0] io_axi_arw_payload_prot, + input wire io_axi_arw_payload_write, + input wire io_axi_w_valid, + output wire io_axi_w_ready, + input wire [31:0] io_axi_w_payload_data, + input wire [3:0] io_axi_w_payload_strb, + input wire io_axi_w_payload_last, + output wire io_axi_b_valid, + input wire io_axi_b_ready, + output reg [1:0] io_axi_b_payload_resp, + output wire io_axi_r_valid, + input wire io_axi_r_ready, + output wire [31:0] io_axi_r_payload_data, + output reg [1:0] io_axi_r_payload_resp, + output wire io_axi_r_payload_last, + output wire io_bmb_cmd_valid, + input wire io_bmb_cmd_ready, + output wire io_bmb_cmd_payload_last, + output wire [0:0] io_bmb_cmd_payload_fragment_source, + output wire [0:0] io_bmb_cmd_payload_fragment_opcode, + output wire [23:0] io_bmb_cmd_payload_fragment_address, + output wire [9:0] io_bmb_cmd_payload_fragment_length, + output wire [31:0] io_bmb_cmd_payload_fragment_data, + output wire [3:0] io_bmb_cmd_payload_fragment_mask, + input wire io_bmb_rsp_valid, + output wire io_bmb_rsp_ready, + input wire io_bmb_rsp_payload_last, + input wire [0:0] io_bmb_rsp_payload_fragment_source, + input wire [0:0] io_bmb_rsp_payload_fragment_opcode, + input wire [31:0] io_bmb_rsp_payload_fragment_data +); + + wire [9:0] _zz_io_bmb_cmd_payload_fragment_length; + wire hazard; + wire io_bmb_cmd_fire; + wire rspIsWrite; + wire when_Axi4SharedToBmb_l42; + wire when_Axi4SharedToBmb_l49; + + assign _zz_io_bmb_cmd_payload_fragment_length = ({2'd0,io_axi_arw_payload_len} <<< 2'd2); + assign hazard = (io_axi_arw_payload_write && (! io_axi_w_valid)); + assign io_bmb_cmd_valid = (io_axi_arw_valid && (! hazard)); + assign io_bmb_cmd_payload_fragment_source = io_axi_arw_payload_write; + assign io_bmb_cmd_payload_fragment_opcode = io_axi_arw_payload_write; + assign io_bmb_cmd_payload_fragment_address = io_axi_arw_payload_addr; + assign io_bmb_cmd_payload_fragment_length = (_zz_io_bmb_cmd_payload_fragment_length | 10'h003); + assign io_bmb_cmd_payload_fragment_data = io_axi_w_payload_data; + assign io_bmb_cmd_payload_fragment_mask = io_axi_w_payload_strb; + assign io_bmb_cmd_payload_last = ((! io_axi_arw_payload_write) || io_axi_w_payload_last); + assign io_bmb_cmd_fire = (io_bmb_cmd_valid && io_bmb_cmd_ready); + assign io_axi_arw_ready = (io_bmb_cmd_fire && io_bmb_cmd_payload_last); + assign io_axi_w_ready = (io_bmb_cmd_fire && (io_bmb_cmd_payload_fragment_opcode == 1'b1)); + assign rspIsWrite = io_bmb_rsp_payload_fragment_source[0]; + assign io_axi_b_valid = (io_bmb_rsp_valid && rspIsWrite); + always @(*) begin + io_axi_b_payload_resp = 2'b00; + if(when_Axi4SharedToBmb_l42) begin + io_axi_b_payload_resp = 2'b11; + end + end + + assign when_Axi4SharedToBmb_l42 = (io_bmb_rsp_payload_fragment_opcode == 1'b1); + assign io_axi_r_valid = (io_bmb_rsp_valid && (! rspIsWrite)); + assign io_axi_r_payload_data = io_bmb_rsp_payload_fragment_data; + assign io_axi_r_payload_last = io_bmb_rsp_payload_last; + always @(*) begin + io_axi_r_payload_resp = 2'b00; + if(when_Axi4SharedToBmb_l49) begin + io_axi_r_payload_resp = 2'b11; + end + end + + assign when_Axi4SharedToBmb_l49 = (io_bmb_rsp_payload_fragment_opcode == 1'b1); + assign io_bmb_rsp_ready = (rspIsWrite ? io_axi_b_ready : io_axi_r_ready); + +endmodule + +module Axi4PeripheralStreamArbiter_035069daf0ad4fb491e9c65d79bd2ddd ( + input wire io_inputs_0_valid, + output wire io_inputs_0_ready, + input wire [23:0] io_inputs_0_payload_addr, + input wire [7:0] io_inputs_0_payload_len, + input wire [2:0] io_inputs_0_payload_size, + input wire [3:0] io_inputs_0_payload_cache, + input wire [2:0] io_inputs_0_payload_prot, + input wire io_inputs_1_valid, + output wire io_inputs_1_ready, + input wire [23:0] io_inputs_1_payload_addr, + input wire [7:0] io_inputs_1_payload_len, + input wire [2:0] io_inputs_1_payload_size, + input wire [3:0] io_inputs_1_payload_cache, + input wire [2:0] io_inputs_1_payload_prot, + output wire io_output_valid, + input wire io_output_ready, + output wire [23:0] io_output_payload_addr, + output wire [7:0] io_output_payload_len, + output wire [2:0] io_output_payload_size, + output wire [3:0] io_output_payload_cache, + output wire [2:0] io_output_payload_prot, + output wire [0:0] io_chosen, + output wire [1:0] io_chosenOH, + input wire clk, + input wire reset +); + + wire [3:0] _zz__zz_maskProposal_0_2; + wire [3:0] _zz__zz_maskProposal_0_2_1; + wire [1:0] _zz__zz_maskProposal_0_2_2; + reg locked; + wire maskProposal_0; + wire maskProposal_1; + reg maskLocked_0; + reg maskLocked_1; + wire maskRouted_0; + wire maskRouted_1; + wire [1:0] _zz_maskProposal_0; + wire [3:0] _zz_maskProposal_0_1; + wire [3:0] _zz_maskProposal_0_2; + wire [1:0] _zz_maskProposal_0_3; + wire io_output_fire; + wire _zz_io_chosen; + + assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); + assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; + assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; + assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); + assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); + assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; + assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; + assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); + assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); + assign maskProposal_0 = _zz_maskProposal_0_3[0]; + assign maskProposal_1 = _zz_maskProposal_0_3[1]; + assign io_output_fire = (io_output_valid && io_output_ready); + assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); + assign io_output_payload_addr = (maskRouted_0 ? io_inputs_0_payload_addr : io_inputs_1_payload_addr); + assign io_output_payload_len = (maskRouted_0 ? io_inputs_0_payload_len : io_inputs_1_payload_len); + assign io_output_payload_size = (maskRouted_0 ? io_inputs_0_payload_size : io_inputs_1_payload_size); + assign io_output_payload_cache = (maskRouted_0 ? io_inputs_0_payload_cache : io_inputs_1_payload_cache); + assign io_output_payload_prot = (maskRouted_0 ? io_inputs_0_payload_prot : io_inputs_1_payload_prot); + assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); + assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); + assign io_chosenOH = {maskRouted_1,maskRouted_0}; + assign _zz_io_chosen = io_chosenOH[1]; + assign io_chosen = _zz_io_chosen; + always @(posedge clk) begin + if(reset) begin + locked <= 1'b0; + maskLocked_0 <= 1'b0; + maskLocked_1 <= 1'b1; + end else begin + if(io_output_valid) begin + maskLocked_0 <= maskRouted_0; + maskLocked_1 <= maskRouted_1; + end + if(io_output_valid) begin + locked <= 1'b1; + end + if(io_output_fire) begin + locked <= 1'b0; + end + end + end + + +endmodule + +//Axi4PeripheralTimer_1 replaced by Axi4PeripheralTimer_035069daf0ad4fb491e9c65d79bd2ddd + +module Axi4PeripheralTimer_035069daf0ad4fb491e9c65d79bd2ddd ( + input wire io_tick, + input wire io_clear, + input wire [15:0] io_limit, + output wire io_full, + output wire [15:0] io_value, + input wire clk, + input wire reset +); + + wire [15:0] _zz_counter; + wire [0:0] _zz_counter_1; + reg [15:0] counter; + wire limitHit; + reg inhibitFull; + + assign _zz_counter_1 = (! limitHit); + assign _zz_counter = {15'd0, _zz_counter_1}; + assign limitHit = (counter == io_limit); + assign io_full = ((limitHit && io_tick) && (! inhibitFull)); + assign io_value = counter; + always @(posedge clk) begin + if(reset) begin + inhibitFull <= 1'b0; + end else begin + if(io_tick) begin + inhibitFull <= limitHit; + end + if(io_clear) begin + inhibitFull <= 1'b0; + end + end + end + + always @(posedge clk) begin + if(io_tick) begin + counter <= (counter + _zz_counter); + end + if(io_clear) begin + counter <= 16'h0; + end + end + + +endmodule + +module Axi4PeripheralPrescaler_035069daf0ad4fb491e9c65d79bd2ddd ( + input wire io_clear, + input wire [23:0] io_limit, + output wire io_overflow, + input wire clk, + input wire reset +); + + reg [23:0] counter; + wire when_Prescaler_l17; + + assign when_Prescaler_l17 = (io_clear || io_overflow); + assign io_overflow = (counter == io_limit); + always @(posedge clk) begin + counter <= (counter + 24'h000001); + if(when_Prescaler_l17) begin + counter <= 24'h0; + end + end + + +endmodule + +module Axi4PeripheralI2cSlave_035069daf0ad4fb491e9c65d79bd2ddd ( + output wire io_i2c_sda_write, + input wire io_i2c_sda_read, + output wire io_i2c_scl_write, + input wire io_i2c_scl_read, + input wire [9:0] io_config_samplingClockDivider, + input wire [19:0] io_config_timeout, + input wire [5:0] io_config_tsuData, + input wire io_config_timeoutClear, + output reg [2:0] io_bus_cmd_kind, + output wire io_bus_cmd_data, + input wire io_bus_rsp_valid, + input wire io_bus_rsp_enable, + input wire io_bus_rsp_data, + output wire io_timeout, + output wire io_internals_inFrame, + output wire io_internals_sdaRead, + output wire io_internals_sclRead, + input wire clk, + input wire reset +); + localparam Axi4PeripheralI2cSlaveCmdMode_NONE = 3'd0; + localparam Axi4PeripheralI2cSlaveCmdMode_START = 3'd1; + localparam Axi4PeripheralI2cSlaveCmdMode_RESTART = 3'd2; + localparam Axi4PeripheralI2cSlaveCmdMode_STOP = 3'd3; + localparam Axi4PeripheralI2cSlaveCmdMode_DROP = 3'd4; + localparam Axi4PeripheralI2cSlaveCmdMode_DRIVE = 3'd5; + localparam Axi4PeripheralI2cSlaveCmdMode_READ = 3'd6; + + wire io_i2c_scl_read_buffercc_io_dataOut; + wire io_i2c_sda_read_buffercc_io_dataOut; + reg [9:0] filter_timer_counter; + wire filter_timer_tick; + wire filter_sampler_sclSync; + wire filter_sampler_sdaSync; + wire filter_sampler_sclSamples_0; + wire filter_sampler_sclSamples_1; + wire filter_sampler_sclSamples_2; + wire _zz_filter_sampler_sclSamples_0; + reg _zz_filter_sampler_sclSamples_1; + reg _zz_filter_sampler_sclSamples_2; + wire filter_sampler_sdaSamples_0; + wire filter_sampler_sdaSamples_1; + wire filter_sampler_sdaSamples_2; + wire _zz_filter_sampler_sdaSamples_0; + reg _zz_filter_sampler_sdaSamples_1; + reg _zz_filter_sampler_sdaSamples_2; + reg filter_sda; + reg filter_scl; + wire when_Misc_l82; + wire when_Misc_l85; + wire sclEdge_rise; + wire sclEdge_fall; + wire sclEdge_toggle; + reg filter_scl_regNext; + wire sdaEdge_rise; + wire sdaEdge_fall; + wire sdaEdge_toggle; + reg filter_sda_regNext; + wire detector_start; + wire detector_stop; + reg [5:0] tsuData_counter; + wire tsuData_done; + reg tsuData_reset; + wire when_I2CSlave_l191; + reg ctrl_inFrame; + reg ctrl_inFrameData; + reg ctrl_sdaWrite; + reg ctrl_sclWrite; + wire ctrl_rspBufferIn_valid; + reg ctrl_rspBufferIn_ready; + wire ctrl_rspBufferIn_payload_enable; + wire ctrl_rspBufferIn_payload_data; + wire ctrl_rspBuffer_valid; + reg ctrl_rspBuffer_ready; + wire ctrl_rspBuffer_payload_enable; + wire ctrl_rspBuffer_payload_data; + reg ctrl_rspBufferIn_rValid; + reg ctrl_rspBufferIn_rData_enable; + reg ctrl_rspBufferIn_rData_data; + wire when_Stream_l375; + wire ctrl_rspAhead_valid; + wire ctrl_rspAhead_payload_enable; + wire ctrl_rspAhead_payload_data; + wire when_I2CSlave_l241; + wire when_I2CSlave_l245; + wire when_I2CSlave_l251; + wire [2:0] _zz_io_bus_cmd_kind; + reg timeout_enabled; + reg [19:0] timeout_counter; + wire timeout_tick; + wire when_I2CSlave_l270; + wire when_I2CSlave_l276; + wire [2:0] _zz_io_bus_cmd_kind_1; + `ifndef SYNTHESIS + reg [55:0] io_bus_cmd_kind_string; + reg [55:0] _zz_io_bus_cmd_kind_string; + reg [55:0] _zz_io_bus_cmd_kind_1_string; + `endif + + + (* keep_hierarchy = "TRUE" *) Axi4PeripheralBufferCC_1_035069daf0ad4fb491e9c65d79bd2ddd io_i2c_scl_read_buffercc ( + .io_dataIn (io_i2c_scl_read ), //i + .io_dataOut (io_i2c_scl_read_buffercc_io_dataOut), //o + .clk (clk ), //i + .reset (reset ) //i + ); + (* keep_hierarchy = "TRUE" *) Axi4PeripheralBufferCC_1_035069daf0ad4fb491e9c65d79bd2ddd io_i2c_sda_read_buffercc ( + .io_dataIn (io_i2c_sda_read ), //i + .io_dataOut (io_i2c_sda_read_buffercc_io_dataOut), //o + .clk (clk ), //i + .reset (reset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_bus_cmd_kind) + Axi4PeripheralI2cSlaveCmdMode_NONE : io_bus_cmd_kind_string = "NONE "; + Axi4PeripheralI2cSlaveCmdMode_START : io_bus_cmd_kind_string = "START "; + Axi4PeripheralI2cSlaveCmdMode_RESTART : io_bus_cmd_kind_string = "RESTART"; + Axi4PeripheralI2cSlaveCmdMode_STOP : io_bus_cmd_kind_string = "STOP "; + Axi4PeripheralI2cSlaveCmdMode_DROP : io_bus_cmd_kind_string = "DROP "; + Axi4PeripheralI2cSlaveCmdMode_DRIVE : io_bus_cmd_kind_string = "DRIVE "; + Axi4PeripheralI2cSlaveCmdMode_READ : io_bus_cmd_kind_string = "READ "; + default : io_bus_cmd_kind_string = "???????"; + endcase + end + always @(*) begin + case(_zz_io_bus_cmd_kind) + Axi4PeripheralI2cSlaveCmdMode_NONE : _zz_io_bus_cmd_kind_string = "NONE "; + Axi4PeripheralI2cSlaveCmdMode_START : _zz_io_bus_cmd_kind_string = "START "; + Axi4PeripheralI2cSlaveCmdMode_RESTART : _zz_io_bus_cmd_kind_string = "RESTART"; + Axi4PeripheralI2cSlaveCmdMode_STOP : _zz_io_bus_cmd_kind_string = "STOP "; + Axi4PeripheralI2cSlaveCmdMode_DROP : _zz_io_bus_cmd_kind_string = "DROP "; + Axi4PeripheralI2cSlaveCmdMode_DRIVE : _zz_io_bus_cmd_kind_string = "DRIVE "; + Axi4PeripheralI2cSlaveCmdMode_READ : _zz_io_bus_cmd_kind_string = "READ "; + default : _zz_io_bus_cmd_kind_string = "???????"; + endcase + end + always @(*) begin + case(_zz_io_bus_cmd_kind_1) + Axi4PeripheralI2cSlaveCmdMode_NONE : _zz_io_bus_cmd_kind_1_string = "NONE "; + Axi4PeripheralI2cSlaveCmdMode_START : _zz_io_bus_cmd_kind_1_string = "START "; + Axi4PeripheralI2cSlaveCmdMode_RESTART : _zz_io_bus_cmd_kind_1_string = "RESTART"; + Axi4PeripheralI2cSlaveCmdMode_STOP : _zz_io_bus_cmd_kind_1_string = "STOP "; + Axi4PeripheralI2cSlaveCmdMode_DROP : _zz_io_bus_cmd_kind_1_string = "DROP "; + Axi4PeripheralI2cSlaveCmdMode_DRIVE : _zz_io_bus_cmd_kind_1_string = "DRIVE "; + Axi4PeripheralI2cSlaveCmdMode_READ : _zz_io_bus_cmd_kind_1_string = "READ "; + default : _zz_io_bus_cmd_kind_1_string = "???????"; + endcase + end + `endif + + assign filter_timer_tick = (filter_timer_counter == 10'h0); + assign filter_sampler_sclSync = io_i2c_scl_read_buffercc_io_dataOut; + assign filter_sampler_sdaSync = io_i2c_sda_read_buffercc_io_dataOut; + assign _zz_filter_sampler_sclSamples_0 = filter_sampler_sclSync; + assign filter_sampler_sclSamples_0 = _zz_filter_sampler_sclSamples_0; + assign filter_sampler_sclSamples_1 = _zz_filter_sampler_sclSamples_1; + assign filter_sampler_sclSamples_2 = _zz_filter_sampler_sclSamples_2; + assign _zz_filter_sampler_sdaSamples_0 = filter_sampler_sdaSync; + assign filter_sampler_sdaSamples_0 = _zz_filter_sampler_sdaSamples_0; + assign filter_sampler_sdaSamples_1 = _zz_filter_sampler_sdaSamples_1; + assign filter_sampler_sdaSamples_2 = _zz_filter_sampler_sdaSamples_2; + assign when_Misc_l82 = (&{(filter_sampler_sdaSamples_2 != filter_sda),{(filter_sampler_sdaSamples_1 != filter_sda),(filter_sampler_sdaSamples_0 != filter_sda)}}); + assign when_Misc_l85 = (&{(filter_sampler_sclSamples_2 != filter_scl),{(filter_sampler_sclSamples_1 != filter_scl),(filter_sampler_sclSamples_0 != filter_scl)}}); + assign sclEdge_rise = ((! filter_scl_regNext) && filter_scl); + assign sclEdge_fall = (filter_scl_regNext && (! filter_scl)); + assign sclEdge_toggle = (filter_scl_regNext != filter_scl); + assign sdaEdge_rise = ((! filter_sda_regNext) && filter_sda); + assign sdaEdge_fall = (filter_sda_regNext && (! filter_sda)); + assign sdaEdge_toggle = (filter_sda_regNext != filter_sda); + assign detector_start = (filter_scl && sdaEdge_fall); + assign detector_stop = (filter_scl && sdaEdge_rise); + assign tsuData_done = (tsuData_counter == 6'h0); + always @(*) begin + tsuData_reset = 1'b0; + if(ctrl_inFrameData) begin + tsuData_reset = (! ctrl_rspAhead_valid); + end + end + + assign when_I2CSlave_l191 = (! tsuData_done); + always @(*) begin + ctrl_sdaWrite = 1'b1; + if(ctrl_inFrameData) begin + if(when_I2CSlave_l251) begin + ctrl_sdaWrite = ctrl_rspAhead_payload_data; + end + end + end + + always @(*) begin + ctrl_sclWrite = 1'b1; + if(ctrl_inFrameData) begin + if(when_I2CSlave_l245) begin + ctrl_sclWrite = 1'b0; + end + end + end + + always @(*) begin + ctrl_rspBufferIn_ready = ctrl_rspBuffer_ready; + if(when_Stream_l375) begin + ctrl_rspBufferIn_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! ctrl_rspBuffer_valid); + assign ctrl_rspBuffer_valid = ctrl_rspBufferIn_rValid; + assign ctrl_rspBuffer_payload_enable = ctrl_rspBufferIn_rData_enable; + assign ctrl_rspBuffer_payload_data = ctrl_rspBufferIn_rData_data; + assign ctrl_rspAhead_valid = (ctrl_rspBuffer_valid ? ctrl_rspBuffer_valid : ctrl_rspBufferIn_valid); + assign ctrl_rspAhead_payload_enable = (ctrl_rspBuffer_valid ? ctrl_rspBuffer_payload_enable : ctrl_rspBufferIn_payload_enable); + assign ctrl_rspAhead_payload_data = (ctrl_rspBuffer_valid ? ctrl_rspBuffer_payload_data : ctrl_rspBufferIn_payload_data); + assign ctrl_rspBufferIn_valid = io_bus_rsp_valid; + assign ctrl_rspBufferIn_payload_enable = io_bus_rsp_enable; + assign ctrl_rspBufferIn_payload_data = io_bus_rsp_data; + always @(*) begin + ctrl_rspBuffer_ready = 1'b0; + if(ctrl_inFrame) begin + if(sclEdge_fall) begin + ctrl_rspBuffer_ready = 1'b1; + end + end + end + + always @(*) begin + io_bus_cmd_kind = Axi4PeripheralI2cSlaveCmdMode_NONE; + if(ctrl_inFrame) begin + if(sclEdge_rise) begin + io_bus_cmd_kind = Axi4PeripheralI2cSlaveCmdMode_READ; + end + end + if(ctrl_inFrameData) begin + if(when_I2CSlave_l241) begin + io_bus_cmd_kind = Axi4PeripheralI2cSlaveCmdMode_DRIVE; + end + end + if(detector_start) begin + io_bus_cmd_kind = _zz_io_bus_cmd_kind; + end + if(when_I2CSlave_l276) begin + if(ctrl_inFrame) begin + io_bus_cmd_kind = _zz_io_bus_cmd_kind_1; + end + end + end + + assign io_bus_cmd_data = filter_sda; + assign when_I2CSlave_l241 = ((! ctrl_rspBuffer_valid) || ctrl_rspBuffer_ready); + assign when_I2CSlave_l245 = ((! ctrl_rspAhead_valid) || (ctrl_rspAhead_payload_enable && (! tsuData_done))); + assign when_I2CSlave_l251 = (ctrl_rspAhead_valid && ctrl_rspAhead_payload_enable); + assign _zz_io_bus_cmd_kind = (ctrl_inFrame ? Axi4PeripheralI2cSlaveCmdMode_RESTART : Axi4PeripheralI2cSlaveCmdMode_START); + assign timeout_tick = (timeout_enabled && (timeout_counter == 20'h0)); + assign when_I2CSlave_l270 = (((timeout_tick || sclEdge_toggle) || (((! ctrl_inFrame) && filter_scl) && filter_sda)) || io_config_timeoutClear); + assign io_timeout = timeout_tick; + assign when_I2CSlave_l276 = (detector_stop || timeout_tick); + assign _zz_io_bus_cmd_kind_1 = (timeout_tick ? Axi4PeripheralI2cSlaveCmdMode_DROP : Axi4PeripheralI2cSlaveCmdMode_STOP); + assign io_internals_inFrame = ctrl_inFrame; + assign io_internals_sdaRead = filter_sda; + assign io_internals_sclRead = filter_scl; + assign io_i2c_scl_write = ctrl_sclWrite; + assign io_i2c_sda_write = ctrl_sdaWrite; + always @(posedge clk) begin + if(reset) begin + filter_timer_counter <= 10'h0; + _zz_filter_sampler_sclSamples_1 <= 1'b1; + _zz_filter_sampler_sclSamples_2 <= 1'b1; + _zz_filter_sampler_sdaSamples_1 <= 1'b1; + _zz_filter_sampler_sdaSamples_2 <= 1'b1; + filter_sda <= 1'b1; + filter_scl <= 1'b1; + filter_scl_regNext <= 1'b1; + filter_sda_regNext <= 1'b1; + tsuData_counter <= 6'h0; + ctrl_inFrame <= 1'b0; + ctrl_inFrameData <= 1'b0; + ctrl_rspBufferIn_rValid <= 1'b0; + timeout_counter <= 20'h0; + end else begin + filter_timer_counter <= (filter_timer_counter - 10'h001); + if(filter_timer_tick) begin + filter_timer_counter <= io_config_samplingClockDivider; + end + if(filter_timer_tick) begin + _zz_filter_sampler_sclSamples_1 <= _zz_filter_sampler_sclSamples_0; + end + if(filter_timer_tick) begin + _zz_filter_sampler_sclSamples_2 <= _zz_filter_sampler_sclSamples_1; + end + if(filter_timer_tick) begin + _zz_filter_sampler_sdaSamples_1 <= _zz_filter_sampler_sdaSamples_0; + end + if(filter_timer_tick) begin + _zz_filter_sampler_sdaSamples_2 <= _zz_filter_sampler_sdaSamples_1; + end + if(filter_timer_tick) begin + if(when_Misc_l82) begin + filter_sda <= filter_sampler_sdaSamples_2; + end + if(when_Misc_l85) begin + filter_scl <= filter_sampler_sclSamples_2; + end + end + filter_scl_regNext <= filter_scl; + filter_sda_regNext <= filter_sda; + if(when_I2CSlave_l191) begin + tsuData_counter <= (tsuData_counter - 6'h01); + end + if(tsuData_reset) begin + tsuData_counter <= io_config_tsuData; + end + if(ctrl_rspBufferIn_ready) begin + ctrl_rspBufferIn_rValid <= ctrl_rspBufferIn_valid; + end + if(ctrl_inFrame) begin + if(sclEdge_fall) begin + ctrl_inFrameData <= 1'b1; + end + end + if(detector_start) begin + ctrl_inFrame <= 1'b1; + ctrl_inFrameData <= 1'b0; + end + timeout_counter <= (timeout_counter - 20'h00001); + if(when_I2CSlave_l270) begin + timeout_counter <= io_config_timeout; + end + if(when_I2CSlave_l276) begin + ctrl_inFrame <= 1'b0; + ctrl_inFrameData <= 1'b0; + end + end + end + + always @(posedge clk) begin + if(ctrl_rspBufferIn_ready) begin + ctrl_rspBufferIn_rData_enable <= ctrl_rspBufferIn_payload_enable; + ctrl_rspBufferIn_rData_data <= ctrl_rspBufferIn_payload_data; + end + timeout_enabled <= (io_config_timeout != 20'h0); + end + + +endmodule + +module Axi4PeripheralStreamFifo_3_035069daf0ad4fb491e9c65d79bd2ddd ( + input wire io_push_valid, + output wire io_push_ready, + input wire [7:0] io_push_payload_data, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [7:0] io_pop_payload_data, + input wire io_flush, + output wire [8:0] io_occupancy, + output wire [8:0] io_availability, + input wire clk, + input wire reset +); + + reg [7:0] logic_ram_spinal_port1; + reg _zz_1; + wire logic_ptr_doPush; + wire logic_ptr_doPop; + wire logic_ptr_full; + wire logic_ptr_empty; + reg [8:0] logic_ptr_push; + reg [8:0] logic_ptr_pop; + wire [8:0] logic_ptr_occupancy; + wire [8:0] logic_ptr_popOnIo; + wire when_Stream_l1248; + reg logic_ptr_wentUp; + wire io_push_fire; + wire logic_push_onRam_write_valid; + wire [7:0] logic_push_onRam_write_payload_address; + wire [7:0] logic_push_onRam_write_payload_data_data; + wire logic_pop_addressGen_valid; + reg logic_pop_addressGen_ready; + wire [7:0] logic_pop_addressGen_payload; + wire logic_pop_addressGen_fire; + wire logic_pop_sync_readArbitation_valid; + wire logic_pop_sync_readArbitation_ready; + wire [7:0] logic_pop_sync_readArbitation_payload; + reg logic_pop_addressGen_rValid; + reg [7:0] logic_pop_addressGen_rData; + wire when_Stream_l375; + wire logic_pop_sync_readPort_cmd_valid; + wire [7:0] logic_pop_sync_readPort_cmd_payload; + wire [7:0] logic_pop_sync_readPort_rsp_data; + wire logic_pop_sync_readArbitation_translated_valid; + wire logic_pop_sync_readArbitation_translated_ready; + wire [7:0] logic_pop_sync_readArbitation_translated_payload_data; + wire logic_pop_sync_readArbitation_fire; + reg [8:0] logic_pop_sync_popReg; + reg [7:0] logic_ram [0:255]; + + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data_data; + end + end + + always @(posedge clk) begin + if(logic_pop_sync_readPort_cmd_valid) begin + logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_push_onRam_write_valid) begin + _zz_1 = 1'b1; + end + end + + assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); + assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 9'h100) == 9'h0); + assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop); + assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo); + assign io_push_ready = (! logic_ptr_full); + assign io_push_fire = (io_push_valid && io_push_ready); + assign logic_ptr_doPush = io_push_fire; + assign logic_push_onRam_write_valid = io_push_fire; + assign logic_push_onRam_write_payload_address = logic_ptr_push[7:0]; + assign logic_push_onRam_write_payload_data_data = io_push_payload_data; + assign logic_pop_addressGen_valid = (! logic_ptr_empty); + assign logic_pop_addressGen_payload = logic_ptr_pop[7:0]; + assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); + assign logic_ptr_doPop = logic_pop_addressGen_fire; + always @(*) begin + logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; + if(when_Stream_l375) begin + logic_pop_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); + assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; + assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; + assign logic_pop_sync_readPort_rsp_data = logic_ram_spinal_port1[7 : 0]; + assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; + assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; + assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; + assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; + assign logic_pop_sync_readArbitation_translated_payload_data = logic_pop_sync_readPort_rsp_data; + assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; + assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_data = logic_pop_sync_readArbitation_translated_payload_data; + assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); + assign logic_ptr_popOnIo = logic_pop_sync_popReg; + assign io_occupancy = logic_ptr_occupancy; + assign io_availability = (9'h100 - logic_ptr_occupancy); + always @(posedge clk) begin + if(reset) begin + logic_ptr_push <= 9'h0; + logic_ptr_pop <= 9'h0; + logic_ptr_wentUp <= 1'b0; + logic_pop_addressGen_rValid <= 1'b0; + logic_pop_sync_popReg <= 9'h0; + end else begin + if(when_Stream_l1248) begin + logic_ptr_wentUp <= logic_ptr_doPush; + end + if(io_flush) begin + logic_ptr_wentUp <= 1'b0; + end + if(logic_ptr_doPush) begin + logic_ptr_push <= (logic_ptr_push + 9'h001); + end + if(logic_ptr_doPop) begin + logic_ptr_pop <= (logic_ptr_pop + 9'h001); + end + if(io_flush) begin + logic_ptr_push <= 9'h0; + logic_ptr_pop <= 9'h0; + end + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; + end + if(io_flush) begin + logic_pop_addressGen_rValid <= 1'b0; + end + if(logic_pop_sync_readArbitation_fire) begin + logic_pop_sync_popReg <= logic_ptr_pop; + end + if(io_flush) begin + logic_pop_sync_popReg <= 9'h0; + end + end + end + + always @(posedge clk) begin + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rData <= logic_pop_addressGen_payload; + end + end + + +endmodule + +module Axi4PeripheralStreamFifo_2_035069daf0ad4fb491e9c65d79bd2ddd ( + input wire io_push_valid, + output wire io_push_ready, + input wire io_push_payload_kind, + input wire io_push_payload_read, + input wire io_push_payload_write, + input wire [7:0] io_push_payload_data, + output wire io_pop_valid, + input wire io_pop_ready, + output wire io_pop_payload_kind, + output wire io_pop_payload_read, + output wire io_pop_payload_write, + output wire [7:0] io_pop_payload_data, + input wire io_flush, + output wire [8:0] io_occupancy, + output wire [8:0] io_availability, + input wire clk, + input wire reset +); + + reg [10:0] logic_ram_spinal_port1; + wire [10:0] _zz_logic_ram_port; + reg _zz_1; + wire logic_ptr_doPush; + wire logic_ptr_doPop; + wire logic_ptr_full; + wire logic_ptr_empty; + reg [8:0] logic_ptr_push; + reg [8:0] logic_ptr_pop; + wire [8:0] logic_ptr_occupancy; + wire [8:0] logic_ptr_popOnIo; + wire when_Stream_l1248; + reg logic_ptr_wentUp; + wire io_push_fire; + wire logic_push_onRam_write_valid; + wire [7:0] logic_push_onRam_write_payload_address; + wire logic_push_onRam_write_payload_data_kind; + wire logic_push_onRam_write_payload_data_read; + wire logic_push_onRam_write_payload_data_write; + wire [7:0] logic_push_onRam_write_payload_data_data; + wire logic_pop_addressGen_valid; + reg logic_pop_addressGen_ready; + wire [7:0] logic_pop_addressGen_payload; + wire logic_pop_addressGen_fire; + wire logic_pop_sync_readArbitation_valid; + wire logic_pop_sync_readArbitation_ready; + wire [7:0] logic_pop_sync_readArbitation_payload; + reg logic_pop_addressGen_rValid; + reg [7:0] logic_pop_addressGen_rData; + wire when_Stream_l375; + wire logic_pop_sync_readPort_cmd_valid; + wire [7:0] logic_pop_sync_readPort_cmd_payload; + wire logic_pop_sync_readPort_rsp_kind; + wire logic_pop_sync_readPort_rsp_read; + wire logic_pop_sync_readPort_rsp_write; + wire [7:0] logic_pop_sync_readPort_rsp_data; + wire [10:0] _zz_logic_pop_sync_readPort_rsp_kind; + wire logic_pop_sync_readArbitation_translated_valid; + wire logic_pop_sync_readArbitation_translated_ready; + wire logic_pop_sync_readArbitation_translated_payload_kind; + wire logic_pop_sync_readArbitation_translated_payload_read; + wire logic_pop_sync_readArbitation_translated_payload_write; + wire [7:0] logic_pop_sync_readArbitation_translated_payload_data; + wire logic_pop_sync_readArbitation_fire; + reg [8:0] logic_pop_sync_popReg; + reg [10:0] logic_ram [0:255]; + + assign _zz_logic_ram_port = {logic_push_onRam_write_payload_data_data,{logic_push_onRam_write_payload_data_write,{logic_push_onRam_write_payload_data_read,logic_push_onRam_write_payload_data_kind}}}; + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_push_onRam_write_payload_address] <= _zz_logic_ram_port; + end + end + + always @(posedge clk) begin + if(logic_pop_sync_readPort_cmd_valid) begin + logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_push_onRam_write_valid) begin + _zz_1 = 1'b1; + end + end + + assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); + assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 9'h100) == 9'h0); + assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop); + assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo); + assign io_push_ready = (! logic_ptr_full); + assign io_push_fire = (io_push_valid && io_push_ready); + assign logic_ptr_doPush = io_push_fire; + assign logic_push_onRam_write_valid = io_push_fire; + assign logic_push_onRam_write_payload_address = logic_ptr_push[7:0]; + assign logic_push_onRam_write_payload_data_kind = io_push_payload_kind; + assign logic_push_onRam_write_payload_data_read = io_push_payload_read; + assign logic_push_onRam_write_payload_data_write = io_push_payload_write; + assign logic_push_onRam_write_payload_data_data = io_push_payload_data; + assign logic_pop_addressGen_valid = (! logic_ptr_empty); + assign logic_pop_addressGen_payload = logic_ptr_pop[7:0]; + assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); + assign logic_ptr_doPop = logic_pop_addressGen_fire; + always @(*) begin + logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; + if(when_Stream_l375) begin + logic_pop_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); + assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; + assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; + assign _zz_logic_pop_sync_readPort_rsp_kind = logic_ram_spinal_port1; + assign logic_pop_sync_readPort_rsp_kind = _zz_logic_pop_sync_readPort_rsp_kind[0]; + assign logic_pop_sync_readPort_rsp_read = _zz_logic_pop_sync_readPort_rsp_kind[1]; + assign logic_pop_sync_readPort_rsp_write = _zz_logic_pop_sync_readPort_rsp_kind[2]; + assign logic_pop_sync_readPort_rsp_data = _zz_logic_pop_sync_readPort_rsp_kind[10 : 3]; + assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; + assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; + assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; + assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; + assign logic_pop_sync_readArbitation_translated_payload_kind = logic_pop_sync_readPort_rsp_kind; + assign logic_pop_sync_readArbitation_translated_payload_read = logic_pop_sync_readPort_rsp_read; + assign logic_pop_sync_readArbitation_translated_payload_write = logic_pop_sync_readPort_rsp_write; + assign logic_pop_sync_readArbitation_translated_payload_data = logic_pop_sync_readPort_rsp_data; + assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; + assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_kind = logic_pop_sync_readArbitation_translated_payload_kind; + assign io_pop_payload_read = logic_pop_sync_readArbitation_translated_payload_read; + assign io_pop_payload_write = logic_pop_sync_readArbitation_translated_payload_write; + assign io_pop_payload_data = logic_pop_sync_readArbitation_translated_payload_data; + assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); + assign logic_ptr_popOnIo = logic_pop_sync_popReg; + assign io_occupancy = logic_ptr_occupancy; + assign io_availability = (9'h100 - logic_ptr_occupancy); + always @(posedge clk) begin + if(reset) begin + logic_ptr_push <= 9'h0; + logic_ptr_pop <= 9'h0; + logic_ptr_wentUp <= 1'b0; + logic_pop_addressGen_rValid <= 1'b0; + logic_pop_sync_popReg <= 9'h0; + end else begin + if(when_Stream_l1248) begin + logic_ptr_wentUp <= logic_ptr_doPush; + end + if(io_flush) begin + logic_ptr_wentUp <= 1'b0; + end + if(logic_ptr_doPush) begin + logic_ptr_push <= (logic_ptr_push + 9'h001); + end + if(logic_ptr_doPop) begin + logic_ptr_pop <= (logic_ptr_pop + 9'h001); + end + if(io_flush) begin + logic_ptr_push <= 9'h0; + logic_ptr_pop <= 9'h0; + end + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; + end + if(io_flush) begin + logic_pop_addressGen_rValid <= 1'b0; + end + if(logic_pop_sync_readArbitation_fire) begin + logic_pop_sync_popReg <= logic_ptr_pop; + end + if(io_flush) begin + logic_pop_sync_popReg <= 9'h0; + end + end + end + + always @(posedge clk) begin + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rData <= logic_pop_addressGen_payload; + end + end + + +endmodule + +module Axi4PeripheralTopLevel_035069daf0ad4fb491e9c65d79bd2ddd ( + input wire io_config_kind_cpol, + input wire io_config_kind_cpha, + input wire [11:0] io_config_sclkToggle, + input wire [1:0] io_config_mod, + input wire [3:0] io_config_ss_activeHigh, + input wire [11:0] io_config_ss_setup, + input wire [11:0] io_config_ss_hold, + input wire [11:0] io_config_ss_disable, + input wire io_cmd_valid, + output reg io_cmd_ready, + input wire io_cmd_payload_kind, + input wire io_cmd_payload_read, + input wire io_cmd_payload_write, + input wire [7:0] io_cmd_payload_data, + output wire io_rsp_valid, + output wire [7:0] io_rsp_payload_data, + output wire [0:0] io_spi_sclk_write, + output reg io_spi_data_0_writeEnable, + input wire [0:0] io_spi_data_0_read, + output reg [0:0] io_spi_data_0_write, + output reg io_spi_data_1_writeEnable, + input wire [0:0] io_spi_data_1_read, + output reg [0:0] io_spi_data_1_write, + output reg io_spi_data_2_writeEnable, + input wire [0:0] io_spi_data_2_read, + output reg [0:0] io_spi_data_2_write, + output reg io_spi_data_3_writeEnable, + input wire [0:0] io_spi_data_3_read, + output reg [0:0] io_spi_data_3_write, + output wire [3:0] io_spi_ss, + input wire clk, + input wire reset +); + + reg [0:0] _zz_outputPhy_dataWrite_3; + wire [2:0] _zz_outputPhy_dataWrite_4; + reg [1:0] _zz_outputPhy_dataWrite_5; + wire [1:0] _zz_outputPhy_dataWrite_6; + wire [2:0] _zz_outputPhy_dataWrite_7; + reg [3:0] _zz_outputPhy_dataWrite_8; + wire [0:0] _zz_outputPhy_dataWrite_9; + wire [2:0] _zz_outputPhy_dataWrite_10; + wire [3:0] _zz_inputPhy_dataRead; + wire [3:0] _zz_inputPhy_dataRead_1; + wire [3:0] _zz_inputPhy_dataRead_2; + wire [3:0] _zz_inputPhy_dataRead_3; + wire [3:0] _zz_inputPhy_dataRead_4; + wire [3:0] _zz_inputPhy_dataRead_5; + wire [3:0] _zz_inputPhy_dataRead_6; + wire [8:0] _zz_inputPhy_bufferNext; + wire [10:0] _zz_inputPhy_bufferNext_1; + reg [11:0] timer_counter; + reg timer_reset; + wire timer_ss_setupHit; + wire timer_ss_holdHit; + wire timer_ss_disableHit; + wire timer_sclkToggleHit; + reg fsm_state; + reg [2:0] fsm_counter; + reg [2:0] _zz_fsm_counterPlus; + wire [2:0] fsm_counterPlus; + reg fsm_fastRate; + reg fsm_isDdr; + reg [2:0] fsm_counterMax; + reg fsm_lateSampling; + reg fsm_readFill; + reg fsm_readDone; + reg [3:0] fsm_ss; + wire when_SpiXdrMasterCtrl_l741; + wire when_SpiXdrMasterCtrl_l744; + wire when_SpiXdrMasterCtrl_l751; + wire when_SpiXdrMasterCtrl_l753; + wire when_SpiXdrMasterCtrl_l760; + wire when_SpiXdrMasterCtrl_l766; + wire when_SpiXdrMasterCtrl_l783; + reg [0:0] outputPhy_sclkWrite; + wire [0:0] _zz_io_spi_sclk_write; + wire when_SpiXdrMasterCtrl_l798; + reg [3:0] outputPhy_dataWrite; + reg [2:0] outputPhy_widthSel; + reg [2:0] outputPhy_offset; + wire [7:0] _zz_outputPhy_dataWrite; + wire [7:0] _zz_outputPhy_dataWrite_1; + wire [7:0] _zz_outputPhy_dataWrite_2; + wire when_SpiXdrMasterCtrl_l841; + wire when_SpiXdrMasterCtrl_l841_1; + reg [1:0] io_config_mod_delay_1; + reg [1:0] inputPhy_mod; + reg fsm_readFill_delay_1; + reg inputPhy_readFill; + reg fsm_readDone_delay_1; + reg inputPhy_readDone; + reg [6:0] inputPhy_buffer; + reg [7:0] inputPhy_bufferNext; + reg [2:0] inputPhy_widthSel; + wire [3:0] inputPhy_dataWrite; + reg [3:0] inputPhy_dataRead; + reg fsm_state_delay_1; + reg fsm_state_delay_2; + wire when_SpiXdrMasterCtrl_l863; + reg [3:0] inputPhy_dataReadBuffer; + + assign _zz_outputPhy_dataWrite_4 = (outputPhy_offset - fsm_counter); + assign _zz_outputPhy_dataWrite_6 = (_zz_outputPhy_dataWrite_7 >>> 1'd1); + assign _zz_outputPhy_dataWrite_7 = (outputPhy_offset - fsm_counter); + assign _zz_outputPhy_dataWrite_9 = (_zz_outputPhy_dataWrite_10 >>> 2'd2); + assign _zz_outputPhy_dataWrite_10 = (outputPhy_offset - fsm_counter); + assign _zz_inputPhy_dataRead = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_1 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_2 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_3 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_4 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_5 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_6 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[1 : 0]}; + assign _zz_inputPhy_bufferNext_1 = {inputPhy_buffer,inputPhy_dataRead[3 : 0]}; + always @(*) begin + case(_zz_outputPhy_dataWrite_4) + 3'b000 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[0 : 0]; + 3'b001 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[1 : 1]; + 3'b010 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[2 : 2]; + 3'b011 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[3 : 3]; + 3'b100 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[4 : 4]; + 3'b101 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[5 : 5]; + 3'b110 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[6 : 6]; + default : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[7 : 7]; + endcase + end + + always @(*) begin + case(_zz_outputPhy_dataWrite_6) + 2'b00 : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[1 : 0]; + 2'b01 : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[3 : 2]; + 2'b10 : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[5 : 4]; + default : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[7 : 6]; + endcase + end + + always @(*) begin + case(_zz_outputPhy_dataWrite_9) + 1'b0 : _zz_outputPhy_dataWrite_8 = _zz_outputPhy_dataWrite_2[3 : 0]; + default : _zz_outputPhy_dataWrite_8 = _zz_outputPhy_dataWrite_2[7 : 4]; + endcase + end + + always @(*) begin + timer_reset = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l741) begin + timer_reset = timer_sclkToggleHit; + end else begin + if(!when_SpiXdrMasterCtrl_l760) begin + if(when_SpiXdrMasterCtrl_l766) begin + if(timer_ss_holdHit) begin + timer_reset = 1'b1; + end + end + end + end + end + if(when_SpiXdrMasterCtrl_l783) begin + timer_reset = 1'b1; + end + end + + assign timer_ss_setupHit = (timer_counter == io_config_ss_setup); + assign timer_ss_holdHit = (timer_counter == io_config_ss_hold); + assign timer_ss_disableHit = (timer_counter == io_config_ss_disable); + assign timer_sclkToggleHit = (timer_counter == io_config_sclkToggle); + always @(*) begin + _zz_fsm_counterPlus = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + _zz_fsm_counterPlus = 3'b001; + end + 2'b01 : begin + _zz_fsm_counterPlus = 3'b010; + end + 2'b10 : begin + _zz_fsm_counterPlus = 3'b100; + end + default : begin + end + endcase + end + + assign fsm_counterPlus = (fsm_counter + _zz_fsm_counterPlus); + always @(*) begin + fsm_fastRate = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_fastRate = 1'b0; + end + 2'b01 : begin + fsm_fastRate = 1'b0; + end + 2'b10 : begin + fsm_fastRate = 1'b0; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_isDdr = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_isDdr = 1'b0; + end + 2'b01 : begin + fsm_isDdr = 1'b0; + end + 2'b10 : begin + fsm_isDdr = 1'b0; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_counterMax = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + fsm_counterMax = 3'b111; + end + 2'b01 : begin + fsm_counterMax = 3'b110; + end + 2'b10 : begin + fsm_counterMax = 3'b100; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_lateSampling = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_lateSampling = 1'b1; + end + 2'b01 : begin + fsm_lateSampling = 1'b1; + end + 2'b10 : begin + fsm_lateSampling = 1'b1; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_readFill = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l741) begin + if(when_SpiXdrMasterCtrl_l744) begin + fsm_readFill = 1'b1; + end + end + end + end + + always @(*) begin + fsm_readDone = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l741) begin + if(when_SpiXdrMasterCtrl_l744) begin + fsm_readDone = (io_cmd_payload_read && (fsm_counter == fsm_counterMax)); + end + end + end + end + + assign io_spi_ss = (~ (fsm_ss ^ io_config_ss_activeHigh)); + always @(*) begin + io_cmd_ready = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l741) begin + if(when_SpiXdrMasterCtrl_l751) begin + if(when_SpiXdrMasterCtrl_l753) begin + io_cmd_ready = 1'b1; + end + end + end else begin + if(when_SpiXdrMasterCtrl_l760) begin + if(timer_ss_setupHit) begin + io_cmd_ready = 1'b1; + end + end else begin + if(!when_SpiXdrMasterCtrl_l766) begin + if(timer_ss_disableHit) begin + io_cmd_ready = 1'b1; + end + end + end + end + end + end + + assign when_SpiXdrMasterCtrl_l741 = (! io_cmd_payload_kind); + assign when_SpiXdrMasterCtrl_l744 = ((timer_sclkToggleHit && (((! fsm_state) ^ fsm_lateSampling) || fsm_isDdr)) || fsm_fastRate); + assign when_SpiXdrMasterCtrl_l751 = ((timer_sclkToggleHit && (fsm_state || fsm_isDdr)) || fsm_fastRate); + assign when_SpiXdrMasterCtrl_l753 = (fsm_counter == fsm_counterMax); + assign when_SpiXdrMasterCtrl_l760 = io_cmd_payload_data[7]; + assign when_SpiXdrMasterCtrl_l766 = (! fsm_state); + assign when_SpiXdrMasterCtrl_l783 = ((! io_cmd_valid) || io_cmd_ready); + always @(*) begin + outputPhy_sclkWrite = 1'b0; + if(when_SpiXdrMasterCtrl_l798) begin + case(io_config_mod) + 2'b00 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + 2'b01 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + 2'b10 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + default : begin + end + endcase + end + end + + assign _zz_io_spi_sclk_write[0] = io_config_kind_cpol; + assign io_spi_sclk_write = (outputPhy_sclkWrite ^ _zz_io_spi_sclk_write); + assign when_SpiXdrMasterCtrl_l798 = (io_cmd_valid && (! io_cmd_payload_kind)); + always @(*) begin + outputPhy_widthSel = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + outputPhy_widthSel = 3'b000; + end + 2'b01 : begin + outputPhy_widthSel = 3'b001; + end + 2'b10 : begin + outputPhy_widthSel = 3'b010; + end + default : begin + end + endcase + end + + always @(*) begin + outputPhy_offset = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + outputPhy_offset = 3'b111; + end + 2'b01 : begin + outputPhy_offset = 3'b111; + end + 2'b10 : begin + outputPhy_offset = 3'b111; + end + default : begin + end + endcase + end + + always @(*) begin + outputPhy_dataWrite = 4'bxxxx; + case(outputPhy_widthSel) + 3'b000 : begin + outputPhy_dataWrite[0 : 0] = _zz_outputPhy_dataWrite_3; + end + 3'b001 : begin + outputPhy_dataWrite[1 : 0] = _zz_outputPhy_dataWrite_5; + end + 3'b010 : begin + outputPhy_dataWrite[3 : 0] = _zz_outputPhy_dataWrite_8; + end + default : begin + end + endcase + end + + assign _zz_outputPhy_dataWrite = io_cmd_payload_data; + assign _zz_outputPhy_dataWrite_1 = io_cmd_payload_data; + assign _zz_outputPhy_dataWrite_2 = io_cmd_payload_data; + always @(*) begin + io_spi_data_0_writeEnable = 1'b0; + case(io_config_mod) + 2'b00 : begin + io_spi_data_0_writeEnable = 1'b1; + end + 2'b01 : begin + if(when_SpiXdrMasterCtrl_l841) begin + io_spi_data_0_writeEnable = 1'b1; + end + end + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l841_1) begin + io_spi_data_0_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_1_writeEnable = 1'b0; + case(io_config_mod) + 2'b01 : begin + if(when_SpiXdrMasterCtrl_l841) begin + io_spi_data_1_writeEnable = 1'b1; + end + end + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l841_1) begin + io_spi_data_1_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_2_writeEnable = 1'b0; + case(io_config_mod) + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l841_1) begin + io_spi_data_2_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_3_writeEnable = 1'b0; + case(io_config_mod) + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l841_1) begin + io_spi_data_3_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_0_write = 1'bx; + case(io_config_mod) + 2'b00 : begin + io_spi_data_0_write[0] = (outputPhy_dataWrite[0] || (! (io_cmd_valid && io_cmd_payload_write))); + end + 2'b01 : begin + io_spi_data_0_write[0] = outputPhy_dataWrite[0]; + end + 2'b10 : begin + io_spi_data_0_write[0] = outputPhy_dataWrite[0]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_1_write = 1'bx; + case(io_config_mod) + 2'b01 : begin + io_spi_data_1_write[0] = outputPhy_dataWrite[1]; + end + 2'b10 : begin + io_spi_data_1_write[0] = outputPhy_dataWrite[1]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_2_write = 1'bx; + case(io_config_mod) + 2'b10 : begin + io_spi_data_2_write[0] = outputPhy_dataWrite[2]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_3_write = 1'bx; + case(io_config_mod) + 2'b10 : begin + io_spi_data_3_write[0] = outputPhy_dataWrite[3]; + end + default : begin + end + endcase + end + + assign when_SpiXdrMasterCtrl_l841 = (io_cmd_valid && io_cmd_payload_write); + assign when_SpiXdrMasterCtrl_l841_1 = (io_cmd_valid && io_cmd_payload_write); + always @(*) begin + inputPhy_bufferNext = 8'bxxxxxxxx; + case(inputPhy_widthSel) + 3'b000 : begin + inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[0 : 0]}; + end + 3'b001 : begin + inputPhy_bufferNext = _zz_inputPhy_bufferNext[7:0]; + end + 3'b010 : begin + inputPhy_bufferNext = _zz_inputPhy_bufferNext_1[7:0]; + end + default : begin + end + endcase + end + + always @(*) begin + inputPhy_widthSel = 3'bxxx; + case(inputPhy_mod) + 2'b00 : begin + inputPhy_widthSel = 3'b000; + end + 2'b01 : begin + inputPhy_widthSel = 3'b001; + end + 2'b10 : begin + inputPhy_widthSel = 3'b010; + end + default : begin + end + endcase + end + + assign when_SpiXdrMasterCtrl_l863 = (! fsm_state_delay_2); + always @(*) begin + inputPhy_dataRead = 4'bxxxx; + case(inputPhy_mod) + 2'b00 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead[1]; + end + 2'b01 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead_1[0]; + inputPhy_dataRead[1] = _zz_inputPhy_dataRead_2[1]; + end + 2'b10 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead_3[0]; + inputPhy_dataRead[1] = _zz_inputPhy_dataRead_4[1]; + inputPhy_dataRead[2] = _zz_inputPhy_dataRead_5[2]; + inputPhy_dataRead[3] = _zz_inputPhy_dataRead_6[3]; + end + default : begin + end + endcase + end + + assign io_rsp_valid = inputPhy_readDone; + assign io_rsp_payload_data = inputPhy_bufferNext; + always @(posedge clk) begin + timer_counter <= (timer_counter + 12'h001); + if(timer_reset) begin + timer_counter <= 12'h0; + end + io_config_mod_delay_1 <= io_config_mod; + inputPhy_mod <= io_config_mod_delay_1; + fsm_state_delay_1 <= fsm_state; + fsm_state_delay_2 <= fsm_state_delay_1; + if(when_SpiXdrMasterCtrl_l863) begin + inputPhy_dataReadBuffer <= {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + end + case(inputPhy_widthSel) + 3'b000 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + 3'b001 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + 3'b010 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + default : begin + end + endcase + end + + always @(posedge clk) begin + if(reset) begin + fsm_state <= 1'b0; + fsm_counter <= 3'b000; + fsm_ss <= 4'b0000; + fsm_readFill_delay_1 <= 1'b0; + inputPhy_readFill <= 1'b0; + fsm_readDone_delay_1 <= 1'b0; + inputPhy_readDone <= 1'b0; + end else begin + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l741) begin + if(timer_sclkToggleHit) begin + fsm_state <= (! fsm_state); + end + if(when_SpiXdrMasterCtrl_l751) begin + fsm_counter <= fsm_counterPlus; + if(when_SpiXdrMasterCtrl_l753) begin + fsm_state <= 1'b0; + end + end + end else begin + if(when_SpiXdrMasterCtrl_l760) begin + fsm_ss[io_cmd_payload_data[1 : 0]] <= 1'b1; + end else begin + if(when_SpiXdrMasterCtrl_l766) begin + if(timer_ss_holdHit) begin + fsm_state <= 1'b1; + end + end else begin + fsm_ss[io_cmd_payload_data[1 : 0]] <= 1'b0; + end + end + end + end + if(when_SpiXdrMasterCtrl_l783) begin + fsm_state <= 1'b0; + fsm_counter <= 3'b000; + end + fsm_readFill_delay_1 <= fsm_readFill; + inputPhy_readFill <= fsm_readFill_delay_1; + fsm_readDone_delay_1 <= fsm_readDone; + inputPhy_readDone <= fsm_readDone_delay_1; + end + end + + +endmodule + +//Axi4PeripheralStreamFifo_1 replaced by Axi4PeripheralStreamFifo_035069daf0ad4fb491e9c65d79bd2ddd + +module Axi4PeripheralStreamFifo_035069daf0ad4fb491e9c65d79bd2ddd ( + input wire io_push_valid, + output wire io_push_ready, + input wire [7:0] io_push_payload, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [7:0] io_pop_payload, + input wire io_flush, + output wire [7:0] io_occupancy, + output wire [7:0] io_availability, + input wire clk, + input wire reset +); + + reg [7:0] logic_ram_spinal_port1; + reg _zz_1; + wire logic_ptr_doPush; + wire logic_ptr_doPop; + wire logic_ptr_full; + wire logic_ptr_empty; + reg [7:0] logic_ptr_push; + reg [7:0] logic_ptr_pop; + wire [7:0] logic_ptr_occupancy; + wire [7:0] logic_ptr_popOnIo; + wire when_Stream_l1248; + reg logic_ptr_wentUp; + wire io_push_fire; + wire logic_push_onRam_write_valid; + wire [6:0] logic_push_onRam_write_payload_address; + wire [7:0] logic_push_onRam_write_payload_data; + wire logic_pop_addressGen_valid; + reg logic_pop_addressGen_ready; + wire [6:0] logic_pop_addressGen_payload; + wire logic_pop_addressGen_fire; + wire logic_pop_sync_readArbitation_valid; + wire logic_pop_sync_readArbitation_ready; + wire [6:0] logic_pop_sync_readArbitation_payload; + reg logic_pop_addressGen_rValid; + reg [6:0] logic_pop_addressGen_rData; + wire when_Stream_l375; + wire logic_pop_sync_readPort_cmd_valid; + wire [6:0] logic_pop_sync_readPort_cmd_payload; + wire [7:0] logic_pop_sync_readPort_rsp; + wire logic_pop_sync_readArbitation_translated_valid; + wire logic_pop_sync_readArbitation_translated_ready; + wire [7:0] logic_pop_sync_readArbitation_translated_payload; + wire logic_pop_sync_readArbitation_fire; + reg [7:0] logic_pop_sync_popReg; + reg [7:0] logic_ram [0:127]; + + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data; + end + end + + always @(posedge clk) begin + if(logic_pop_sync_readPort_cmd_valid) begin + logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_push_onRam_write_valid) begin + _zz_1 = 1'b1; + end + end + + assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); + assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 8'h80) == 8'h0); + assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop); + assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo); + assign io_push_ready = (! logic_ptr_full); + assign io_push_fire = (io_push_valid && io_push_ready); + assign logic_ptr_doPush = io_push_fire; + assign logic_push_onRam_write_valid = io_push_fire; + assign logic_push_onRam_write_payload_address = logic_ptr_push[6:0]; + assign logic_push_onRam_write_payload_data = io_push_payload; + assign logic_pop_addressGen_valid = (! logic_ptr_empty); + assign logic_pop_addressGen_payload = logic_ptr_pop[6:0]; + assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); + assign logic_ptr_doPop = logic_pop_addressGen_fire; + always @(*) begin + logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; + if(when_Stream_l375) begin + logic_pop_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); + assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; + assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; + assign logic_pop_sync_readPort_rsp = logic_ram_spinal_port1; + assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; + assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; + assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; + assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; + assign logic_pop_sync_readArbitation_translated_payload = logic_pop_sync_readPort_rsp; + assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; + assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload = logic_pop_sync_readArbitation_translated_payload; + assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); + assign logic_ptr_popOnIo = logic_pop_sync_popReg; + assign io_occupancy = logic_ptr_occupancy; + assign io_availability = (8'h80 - logic_ptr_occupancy); + always @(posedge clk) begin + if(reset) begin + logic_ptr_push <= 8'h0; + logic_ptr_pop <= 8'h0; + logic_ptr_wentUp <= 1'b0; + logic_pop_addressGen_rValid <= 1'b0; + logic_pop_sync_popReg <= 8'h0; + end else begin + if(when_Stream_l1248) begin + logic_ptr_wentUp <= logic_ptr_doPush; + end + if(io_flush) begin + logic_ptr_wentUp <= 1'b0; + end + if(logic_ptr_doPush) begin + logic_ptr_push <= (logic_ptr_push + 8'h01); + end + if(logic_ptr_doPop) begin + logic_ptr_pop <= (logic_ptr_pop + 8'h01); + end + if(io_flush) begin + logic_ptr_push <= 8'h0; + logic_ptr_pop <= 8'h0; + end + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; + end + if(io_flush) begin + logic_pop_addressGen_rValid <= 1'b0; + end + if(logic_pop_sync_readArbitation_fire) begin + logic_pop_sync_popReg <= logic_ptr_pop; + end + if(io_flush) begin + logic_pop_sync_popReg <= 8'h0; + end + end + end + + always @(posedge clk) begin + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rData <= logic_pop_addressGen_payload; + end + end + + +endmodule + +module Axi4PeripheralUartCtrl_035069daf0ad4fb491e9c65d79bd2ddd ( + input wire [2:0] io_config_frame_dataLength, + input wire [0:0] io_config_frame_stop, + input wire [1:0] io_config_frame_parity, + input wire [19:0] io_config_clockDivider, + input wire io_write_valid, + output reg io_write_ready, + input wire [7:0] io_write_payload, + output wire io_read_valid, + input wire io_read_ready, + output wire [7:0] io_read_payload, + output wire io_uart_txd, + input wire io_uart_rxd, + output wire io_readError, + input wire io_writeBreak, + output wire io_readBreak, + input wire clk, + input wire reset +); + localparam Axi4PeripheralUartStopType_ONE = 1'd0; + localparam Axi4PeripheralUartStopType_TWO = 1'd1; + localparam Axi4PeripheralUartParityType_NONE = 2'd0; + localparam Axi4PeripheralUartParityType_EVEN = 2'd1; + localparam Axi4PeripheralUartParityType_ODD = 2'd2; + + wire tx_io_write_ready; + wire tx_io_txd; + wire rx_io_read_valid; + wire [7:0] rx_io_read_payload; + wire rx_io_rts; + wire rx_io_error; + wire rx_io_break; + reg [19:0] clockDivider_counter; + wire clockDivider_tick; + reg clockDivider_tickReg; + reg io_write_thrown_valid; + wire io_write_thrown_ready; + wire [7:0] io_write_thrown_payload; + `ifndef SYNTHESIS + reg [23:0] io_config_frame_stop_string; + reg [31:0] io_config_frame_parity_string; + `endif + + + Axi4PeripheralUartCtrlTx_035069daf0ad4fb491e9c65d79bd2ddd tx ( + .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i + .io_configFrame_stop (io_config_frame_stop ), //i + .io_configFrame_parity (io_config_frame_parity[1:0] ), //i + .io_samplingTick (clockDivider_tickReg ), //i + .io_write_valid (io_write_thrown_valid ), //i + .io_write_ready (tx_io_write_ready ), //o + .io_write_payload (io_write_thrown_payload[7:0] ), //i + .io_cts (1'b0 ), //i + .io_txd (tx_io_txd ), //o + .io_break (io_writeBreak ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralUartCtrlRx_035069daf0ad4fb491e9c65d79bd2ddd rx ( + .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i + .io_configFrame_stop (io_config_frame_stop ), //i + .io_configFrame_parity (io_config_frame_parity[1:0] ), //i + .io_samplingTick (clockDivider_tickReg ), //i + .io_read_valid (rx_io_read_valid ), //o + .io_read_ready (io_read_ready ), //i + .io_read_payload (rx_io_read_payload[7:0] ), //o + .io_rxd (io_uart_rxd ), //i + .io_rts (rx_io_rts ), //o + .io_error (rx_io_error ), //o + .io_break (rx_io_break ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_config_frame_stop) + Axi4PeripheralUartStopType_ONE : io_config_frame_stop_string = "ONE"; + Axi4PeripheralUartStopType_TWO : io_config_frame_stop_string = "TWO"; + default : io_config_frame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_config_frame_parity) + Axi4PeripheralUartParityType_NONE : io_config_frame_parity_string = "NONE"; + Axi4PeripheralUartParityType_EVEN : io_config_frame_parity_string = "EVEN"; + Axi4PeripheralUartParityType_ODD : io_config_frame_parity_string = "ODD "; + default : io_config_frame_parity_string = "????"; + endcase + end + `endif + + assign clockDivider_tick = (clockDivider_counter == 20'h0); + always @(*) begin + io_write_thrown_valid = io_write_valid; + if(rx_io_break) begin + io_write_thrown_valid = 1'b0; + end + end + + always @(*) begin + io_write_ready = io_write_thrown_ready; + if(rx_io_break) begin + io_write_ready = 1'b1; + end + end + + assign io_write_thrown_payload = io_write_payload; + assign io_write_thrown_ready = tx_io_write_ready; + assign io_read_valid = rx_io_read_valid; + assign io_read_payload = rx_io_read_payload; + assign io_uart_txd = tx_io_txd; + assign io_readError = rx_io_error; + assign io_readBreak = rx_io_break; + always @(posedge clk) begin + if(reset) begin + clockDivider_counter <= 20'h0; + clockDivider_tickReg <= 1'b0; + end else begin + clockDivider_tickReg <= clockDivider_tick; + clockDivider_counter <= (clockDivider_counter - 20'h00001); + if(clockDivider_tick) begin + clockDivider_counter <= io_config_clockDivider; + end + end + end + + +endmodule + +//Axi4PeripheralBufferCC_2 replaced by Axi4PeripheralBufferCC_1_035069daf0ad4fb491e9c65d79bd2ddd + +module Axi4PeripheralBufferCC_1_035069daf0ad4fb491e9c65d79bd2ddd ( + input wire io_dataIn, + output wire io_dataOut, + input wire clk, + input wire reset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge clk) begin + if(reset) begin + buffers_0 <= 1'b1; + buffers_1 <= 1'b1; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module Axi4PeripheralUartCtrlRx_035069daf0ad4fb491e9c65d79bd2ddd ( + input wire [2:0] io_configFrame_dataLength, + input wire [0:0] io_configFrame_stop, + input wire [1:0] io_configFrame_parity, + input wire io_samplingTick, + output wire io_read_valid, + input wire io_read_ready, + output wire [7:0] io_read_payload, + input wire io_rxd, + output wire io_rts, + output reg io_error, + output wire io_break, + input wire clk, + input wire reset +); + localparam Axi4PeripheralUartStopType_ONE = 1'd0; + localparam Axi4PeripheralUartStopType_TWO = 1'd1; + localparam Axi4PeripheralUartParityType_NONE = 2'd0; + localparam Axi4PeripheralUartParityType_EVEN = 2'd1; + localparam Axi4PeripheralUartParityType_ODD = 2'd2; + localparam Axi4PeripheralUartCtrlRxState_IDLE = 3'd0; + localparam Axi4PeripheralUartCtrlRxState_START = 3'd1; + localparam Axi4PeripheralUartCtrlRxState_DATA = 3'd2; + localparam Axi4PeripheralUartCtrlRxState_PARITY = 3'd3; + localparam Axi4PeripheralUartCtrlRxState_STOP = 3'd4; + + wire io_rxd_buffercc_io_dataOut; + wire _zz_sampler_value; + wire _zz_sampler_value_1; + wire _zz_sampler_value_2; + wire _zz_sampler_value_3; + wire _zz_sampler_value_4; + wire _zz_sampler_value_5; + wire _zz_sampler_value_6; + wire [2:0] _zz_when_UartCtrlRx_l139; + wire [0:0] _zz_when_UartCtrlRx_l139_1; + reg _zz_io_rts; + wire sampler_synchroniser; + wire sampler_samples_0; + reg sampler_samples_1; + reg sampler_samples_2; + reg sampler_samples_3; + reg sampler_samples_4; + reg sampler_value; + reg sampler_tick; + reg [2:0] bitTimer_counter; + reg bitTimer_tick; + wire when_UartCtrlRx_l43; + reg [2:0] bitCounter_value; + reg [6:0] break_counter; + wire break_valid; + wire when_UartCtrlRx_l69; + reg [2:0] stateMachine_state; + reg stateMachine_parity; + reg [7:0] stateMachine_shifter; + reg stateMachine_validReg; + wire when_UartCtrlRx_l93; + wire when_UartCtrlRx_l103; + wire when_UartCtrlRx_l111; + wire when_UartCtrlRx_l113; + wire when_UartCtrlRx_l125; + wire when_UartCtrlRx_l136; + wire when_UartCtrlRx_l139; + `ifndef SYNTHESIS + reg [23:0] io_configFrame_stop_string; + reg [31:0] io_configFrame_parity_string; + reg [47:0] stateMachine_state_string; + `endif + + + assign _zz_when_UartCtrlRx_l139_1 = ((io_configFrame_stop == Axi4PeripheralUartStopType_ONE) ? 1'b0 : 1'b1); + assign _zz_when_UartCtrlRx_l139 = {2'd0, _zz_when_UartCtrlRx_l139_1}; + assign _zz_sampler_value = ((((1'b0 || ((_zz_sampler_value_1 && sampler_samples_1) && sampler_samples_2)) || (((_zz_sampler_value_2 && sampler_samples_0) && sampler_samples_1) && sampler_samples_3)) || (((1'b1 && sampler_samples_0) && sampler_samples_2) && sampler_samples_3)) || (((1'b1 && sampler_samples_1) && sampler_samples_2) && sampler_samples_3)); + assign _zz_sampler_value_3 = (((1'b1 && sampler_samples_0) && sampler_samples_1) && sampler_samples_4); + assign _zz_sampler_value_4 = ((1'b1 && sampler_samples_0) && sampler_samples_2); + assign _zz_sampler_value_5 = (1'b1 && sampler_samples_1); + assign _zz_sampler_value_6 = 1'b1; + assign _zz_sampler_value_1 = (1'b1 && sampler_samples_0); + assign _zz_sampler_value_2 = 1'b1; + (* keep_hierarchy = "TRUE" *) Axi4PeripheralBufferCC_035069daf0ad4fb491e9c65d79bd2ddd io_rxd_buffercc ( + .io_dataIn (io_rxd ), //i + .io_dataOut (io_rxd_buffercc_io_dataOut), //o + .clk (clk ), //i + .reset (reset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_configFrame_stop) + Axi4PeripheralUartStopType_ONE : io_configFrame_stop_string = "ONE"; + Axi4PeripheralUartStopType_TWO : io_configFrame_stop_string = "TWO"; + default : io_configFrame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_configFrame_parity) + Axi4PeripheralUartParityType_NONE : io_configFrame_parity_string = "NONE"; + Axi4PeripheralUartParityType_EVEN : io_configFrame_parity_string = "EVEN"; + Axi4PeripheralUartParityType_ODD : io_configFrame_parity_string = "ODD "; + default : io_configFrame_parity_string = "????"; + endcase + end + always @(*) begin + case(stateMachine_state) + Axi4PeripheralUartCtrlRxState_IDLE : stateMachine_state_string = "IDLE "; + Axi4PeripheralUartCtrlRxState_START : stateMachine_state_string = "START "; + Axi4PeripheralUartCtrlRxState_DATA : stateMachine_state_string = "DATA "; + Axi4PeripheralUartCtrlRxState_PARITY : stateMachine_state_string = "PARITY"; + Axi4PeripheralUartCtrlRxState_STOP : stateMachine_state_string = "STOP "; + default : stateMachine_state_string = "??????"; + endcase + end + `endif + + always @(*) begin + io_error = 1'b0; + case(stateMachine_state) + Axi4PeripheralUartCtrlRxState_IDLE : begin + end + Axi4PeripheralUartCtrlRxState_START : begin + end + Axi4PeripheralUartCtrlRxState_DATA : begin + end + Axi4PeripheralUartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + if(!when_UartCtrlRx_l125) begin + io_error = 1'b1; + end + end + end + default : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l136) begin + io_error = 1'b1; + end + end + end + endcase + end + + assign io_rts = _zz_io_rts; + assign sampler_synchroniser = io_rxd_buffercc_io_dataOut; + assign sampler_samples_0 = sampler_synchroniser; + always @(*) begin + bitTimer_tick = 1'b0; + if(sampler_tick) begin + if(when_UartCtrlRx_l43) begin + bitTimer_tick = 1'b1; + end + end + end + + assign when_UartCtrlRx_l43 = (bitTimer_counter == 3'b000); + assign break_valid = (break_counter == 7'h68); + assign when_UartCtrlRx_l69 = (io_samplingTick && (! break_valid)); + assign io_break = break_valid; + assign io_read_valid = stateMachine_validReg; + assign when_UartCtrlRx_l93 = ((sampler_tick && (! sampler_value)) && (! break_valid)); + assign when_UartCtrlRx_l103 = (sampler_value == 1'b1); + assign when_UartCtrlRx_l111 = (bitCounter_value == io_configFrame_dataLength); + assign when_UartCtrlRx_l113 = (io_configFrame_parity == Axi4PeripheralUartParityType_NONE); + assign when_UartCtrlRx_l125 = (stateMachine_parity == sampler_value); + assign when_UartCtrlRx_l136 = (! sampler_value); + assign when_UartCtrlRx_l139 = (bitCounter_value == _zz_when_UartCtrlRx_l139); + assign io_read_payload = stateMachine_shifter; + always @(posedge clk) begin + if(reset) begin + _zz_io_rts <= 1'b0; + sampler_samples_1 <= 1'b1; + sampler_samples_2 <= 1'b1; + sampler_samples_3 <= 1'b1; + sampler_samples_4 <= 1'b1; + sampler_value <= 1'b1; + sampler_tick <= 1'b0; + break_counter <= 7'h0; + stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; + stateMachine_validReg <= 1'b0; + end else begin + _zz_io_rts <= (! io_read_ready); + if(io_samplingTick) begin + sampler_samples_1 <= sampler_samples_0; + end + if(io_samplingTick) begin + sampler_samples_2 <= sampler_samples_1; + end + if(io_samplingTick) begin + sampler_samples_3 <= sampler_samples_2; + end + if(io_samplingTick) begin + sampler_samples_4 <= sampler_samples_3; + end + sampler_value <= ((((((_zz_sampler_value || _zz_sampler_value_3) || (_zz_sampler_value_4 && sampler_samples_4)) || ((_zz_sampler_value_5 && sampler_samples_2) && sampler_samples_4)) || (((_zz_sampler_value_6 && sampler_samples_0) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_1) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_2) && sampler_samples_3) && sampler_samples_4)); + sampler_tick <= io_samplingTick; + if(sampler_value) begin + break_counter <= 7'h0; + end else begin + if(when_UartCtrlRx_l69) begin + break_counter <= (break_counter + 7'h01); + end + end + stateMachine_validReg <= 1'b0; + case(stateMachine_state) + Axi4PeripheralUartCtrlRxState_IDLE : begin + if(when_UartCtrlRx_l93) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_START; + end + end + Axi4PeripheralUartCtrlRxState_START : begin + if(bitTimer_tick) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_DATA; + if(when_UartCtrlRx_l103) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; + end + end + end + Axi4PeripheralUartCtrlRxState_DATA : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l111) begin + if(when_UartCtrlRx_l113) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_STOP; + stateMachine_validReg <= 1'b1; + end else begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_PARITY; + end + end + end + end + Axi4PeripheralUartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l125) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_STOP; + stateMachine_validReg <= 1'b1; + end else begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; + end + end + end + default : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l136) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; + end else begin + if(when_UartCtrlRx_l139) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; + end + end + end + end + endcase + end + end + + always @(posedge clk) begin + if(sampler_tick) begin + bitTimer_counter <= (bitTimer_counter - 3'b001); + end + if(bitTimer_tick) begin + bitCounter_value <= (bitCounter_value + 3'b001); + end + if(bitTimer_tick) begin + stateMachine_parity <= (stateMachine_parity ^ sampler_value); + end + case(stateMachine_state) + Axi4PeripheralUartCtrlRxState_IDLE : begin + if(when_UartCtrlRx_l93) begin + bitTimer_counter <= 3'b010; + end + end + Axi4PeripheralUartCtrlRxState_START : begin + if(bitTimer_tick) begin + bitCounter_value <= 3'b000; + stateMachine_parity <= (io_configFrame_parity == Axi4PeripheralUartParityType_ODD); + end + end + Axi4PeripheralUartCtrlRxState_DATA : begin + if(bitTimer_tick) begin + stateMachine_shifter[bitCounter_value] <= sampler_value; + if(when_UartCtrlRx_l111) begin + bitCounter_value <= 3'b000; + end + end + end + Axi4PeripheralUartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + bitCounter_value <= 3'b000; + end + end + default : begin + end + endcase + end + + +endmodule + +module Axi4PeripheralUartCtrlTx_035069daf0ad4fb491e9c65d79bd2ddd ( + input wire [2:0] io_configFrame_dataLength, + input wire [0:0] io_configFrame_stop, + input wire [1:0] io_configFrame_parity, + input wire io_samplingTick, + input wire io_write_valid, + output reg io_write_ready, + input wire [7:0] io_write_payload, + input wire io_cts, + output wire io_txd, + input wire io_break, + input wire clk, + input wire reset +); + localparam Axi4PeripheralUartStopType_ONE = 1'd0; + localparam Axi4PeripheralUartStopType_TWO = 1'd1; + localparam Axi4PeripheralUartParityType_NONE = 2'd0; + localparam Axi4PeripheralUartParityType_EVEN = 2'd1; + localparam Axi4PeripheralUartParityType_ODD = 2'd2; + localparam Axi4PeripheralUartCtrlTxState_IDLE = 3'd0; + localparam Axi4PeripheralUartCtrlTxState_START = 3'd1; + localparam Axi4PeripheralUartCtrlTxState_DATA = 3'd2; + localparam Axi4PeripheralUartCtrlTxState_PARITY = 3'd3; + localparam Axi4PeripheralUartCtrlTxState_STOP = 3'd4; + + wire [2:0] _zz_clockDivider_counter_valueNext; + wire [0:0] _zz_clockDivider_counter_valueNext_1; + wire [2:0] _zz_when_UartCtrlTx_l93; + wire [0:0] _zz_when_UartCtrlTx_l93_1; + reg clockDivider_counter_willIncrement; + wire clockDivider_counter_willClear; + reg [2:0] clockDivider_counter_valueNext; + reg [2:0] clockDivider_counter_value; + wire clockDivider_counter_willOverflowIfInc; + wire clockDivider_counter_willOverflow; + reg [2:0] tickCounter_value; + reg [2:0] stateMachine_state; + reg stateMachine_parity; + reg stateMachine_txd; + wire when_UartCtrlTx_l58; + wire when_UartCtrlTx_l73; + wire when_UartCtrlTx_l76; + wire when_UartCtrlTx_l93; + wire [2:0] _zz_stateMachine_state; + reg _zz_io_txd; + `ifndef SYNTHESIS + reg [23:0] io_configFrame_stop_string; + reg [31:0] io_configFrame_parity_string; + reg [47:0] stateMachine_state_string; + reg [47:0] _zz_stateMachine_state_string; + `endif + + + assign _zz_clockDivider_counter_valueNext_1 = clockDivider_counter_willIncrement; + assign _zz_clockDivider_counter_valueNext = {2'd0, _zz_clockDivider_counter_valueNext_1}; + assign _zz_when_UartCtrlTx_l93_1 = ((io_configFrame_stop == Axi4PeripheralUartStopType_ONE) ? 1'b0 : 1'b1); + assign _zz_when_UartCtrlTx_l93 = {2'd0, _zz_when_UartCtrlTx_l93_1}; + `ifndef SYNTHESIS + always @(*) begin + case(io_configFrame_stop) + Axi4PeripheralUartStopType_ONE : io_configFrame_stop_string = "ONE"; + Axi4PeripheralUartStopType_TWO : io_configFrame_stop_string = "TWO"; + default : io_configFrame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_configFrame_parity) + Axi4PeripheralUartParityType_NONE : io_configFrame_parity_string = "NONE"; + Axi4PeripheralUartParityType_EVEN : io_configFrame_parity_string = "EVEN"; + Axi4PeripheralUartParityType_ODD : io_configFrame_parity_string = "ODD "; + default : io_configFrame_parity_string = "????"; + endcase + end + always @(*) begin + case(stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : stateMachine_state_string = "IDLE "; + Axi4PeripheralUartCtrlTxState_START : stateMachine_state_string = "START "; + Axi4PeripheralUartCtrlTxState_DATA : stateMachine_state_string = "DATA "; + Axi4PeripheralUartCtrlTxState_PARITY : stateMachine_state_string = "PARITY"; + Axi4PeripheralUartCtrlTxState_STOP : stateMachine_state_string = "STOP "; + default : stateMachine_state_string = "??????"; + endcase + end + always @(*) begin + case(_zz_stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : _zz_stateMachine_state_string = "IDLE "; + Axi4PeripheralUartCtrlTxState_START : _zz_stateMachine_state_string = "START "; + Axi4PeripheralUartCtrlTxState_DATA : _zz_stateMachine_state_string = "DATA "; + Axi4PeripheralUartCtrlTxState_PARITY : _zz_stateMachine_state_string = "PARITY"; + Axi4PeripheralUartCtrlTxState_STOP : _zz_stateMachine_state_string = "STOP "; + default : _zz_stateMachine_state_string = "??????"; + endcase + end + `endif + + always @(*) begin + clockDivider_counter_willIncrement = 1'b0; + if(io_samplingTick) begin + clockDivider_counter_willIncrement = 1'b1; + end + end + + assign clockDivider_counter_willClear = 1'b0; + assign clockDivider_counter_willOverflowIfInc = (clockDivider_counter_value == 3'b111); + assign clockDivider_counter_willOverflow = (clockDivider_counter_willOverflowIfInc && clockDivider_counter_willIncrement); + always @(*) begin + clockDivider_counter_valueNext = (clockDivider_counter_value + _zz_clockDivider_counter_valueNext); + if(clockDivider_counter_willClear) begin + clockDivider_counter_valueNext = 3'b000; + end + end + + always @(*) begin + stateMachine_txd = 1'b1; + case(stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : begin + end + Axi4PeripheralUartCtrlTxState_START : begin + stateMachine_txd = 1'b0; + end + Axi4PeripheralUartCtrlTxState_DATA : begin + stateMachine_txd = io_write_payload[tickCounter_value]; + end + Axi4PeripheralUartCtrlTxState_PARITY : begin + stateMachine_txd = stateMachine_parity; + end + default : begin + end + endcase + end + + always @(*) begin + io_write_ready = io_break; + case(stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : begin + end + Axi4PeripheralUartCtrlTxState_START : begin + end + Axi4PeripheralUartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + io_write_ready = 1'b1; + end + end + end + Axi4PeripheralUartCtrlTxState_PARITY : begin + end + default : begin + end + endcase + end + + assign when_UartCtrlTx_l58 = ((io_write_valid && (! io_cts)) && clockDivider_counter_willOverflow); + assign when_UartCtrlTx_l73 = (tickCounter_value == io_configFrame_dataLength); + assign when_UartCtrlTx_l76 = (io_configFrame_parity == Axi4PeripheralUartParityType_NONE); + assign when_UartCtrlTx_l93 = (tickCounter_value == _zz_when_UartCtrlTx_l93); + assign _zz_stateMachine_state = (io_write_valid ? Axi4PeripheralUartCtrlTxState_START : Axi4PeripheralUartCtrlTxState_IDLE); + assign io_txd = _zz_io_txd; + always @(posedge clk) begin + if(reset) begin + clockDivider_counter_value <= 3'b000; + stateMachine_state <= Axi4PeripheralUartCtrlTxState_IDLE; + _zz_io_txd <= 1'b1; + end else begin + clockDivider_counter_value <= clockDivider_counter_valueNext; + case(stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : begin + if(when_UartCtrlTx_l58) begin + stateMachine_state <= Axi4PeripheralUartCtrlTxState_START; + end + end + Axi4PeripheralUartCtrlTxState_START : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_state <= Axi4PeripheralUartCtrlTxState_DATA; + end + end + Axi4PeripheralUartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + if(when_UartCtrlTx_l76) begin + stateMachine_state <= Axi4PeripheralUartCtrlTxState_STOP; + end else begin + stateMachine_state <= Axi4PeripheralUartCtrlTxState_PARITY; + end + end + end + end + Axi4PeripheralUartCtrlTxState_PARITY : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_state <= Axi4PeripheralUartCtrlTxState_STOP; + end + end + default : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l93) begin + stateMachine_state <= _zz_stateMachine_state; + end + end + end + endcase + _zz_io_txd <= (stateMachine_txd && (! io_break)); + end + end + + always @(posedge clk) begin + if(clockDivider_counter_willOverflow) begin + tickCounter_value <= (tickCounter_value + 3'b001); + end + if(clockDivider_counter_willOverflow) begin + stateMachine_parity <= (stateMachine_parity ^ stateMachine_txd); + end + case(stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : begin + end + Axi4PeripheralUartCtrlTxState_START : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_parity <= (io_configFrame_parity == Axi4PeripheralUartParityType_ODD); + tickCounter_value <= 3'b000; + end + end + Axi4PeripheralUartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + tickCounter_value <= 3'b000; + end + end + end + Axi4PeripheralUartCtrlTxState_PARITY : begin + if(clockDivider_counter_willOverflow) begin + tickCounter_value <= 3'b000; + end + end + default : begin + end + endcase + end + + +endmodule + +module Axi4PeripheralBufferCC_035069daf0ad4fb491e9c65d79bd2ddd ( + input wire io_dataIn, + output wire io_dataOut, + input wire clk, + input wire reset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge clk) begin + if(reset) begin + buffers_0 <= 1'b0; + buffers_1 <= 1'b0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_define.vh b/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_define.vh new file mode 100644 index 0000000..bdfba5d --- /dev/null +++ b/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_define.vh @@ -0,0 +1,46 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 1.22.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam PERI_FREQ = 200; diff --git a/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.v b/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.v new file mode 100644 index 0000000..bf928f2 --- /dev/null +++ b/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.v @@ -0,0 +1,148 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 1.22.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +EfxSapphireHpSoc_slb u_EfxSapphireHpSoc_slb +( + .io_peripheralClk ( io_peripheralClk ), + .io_peripheralReset ( io_peripheralReset ), + .io_asyncReset ( io_asyncReset ), + .io_gpio_sw_n ( io_gpio_sw_n ), + .pll_peripheral_locked ( pll_peripheral_locked ), + .pll_system_locked ( pll_system_locked ), + .jtagCtrl_capture ( jtagCtrl_capture ), + .jtagCtrl_enable ( jtagCtrl_enable ), + .jtagCtrl_reset ( jtagCtrl_reset ), + .jtagCtrl_shift ( jtagCtrl_shift ), + .jtagCtrl_tdi ( jtagCtrl_tdi ), + .jtagCtrl_tdo ( jtagCtrl_tdo ), + .jtagCtrl_update ( jtagCtrl_update ), + .ut_jtagCtrl_capture ( ut_jtagCtrl_capture ), + .ut_jtagCtrl_enable ( ut_jtagCtrl_enable ), + .ut_jtagCtrl_reset ( ut_jtagCtrl_reset ), + .ut_jtagCtrl_shift ( ut_jtagCtrl_shift ), + .ut_jtagCtrl_tdi ( ut_jtagCtrl_tdi ), + .ut_jtagCtrl_tdo ( ut_jtagCtrl_tdo ), + .ut_jtagCtrl_update ( ut_jtagCtrl_update ), + .system_spi_0_io_data_0_read ( system_spi_0_io_data_0_read ), + .system_spi_0_io_data_0_write ( system_spi_0_io_data_0_write ), + .system_spi_0_io_data_0_writeEnable ( system_spi_0_io_data_0_writeEnable ), + .system_spi_0_io_data_1_read ( system_spi_0_io_data_1_read ), + .system_spi_0_io_data_1_write ( system_spi_0_io_data_1_write ), + .system_spi_0_io_data_1_writeEnable ( system_spi_0_io_data_1_writeEnable ), + .system_spi_0_io_data_2_read ( system_spi_0_io_data_2_read ), + .system_spi_0_io_data_2_write ( system_spi_0_io_data_2_write ), + .system_spi_0_io_data_2_writeEnable ( system_spi_0_io_data_2_writeEnable ), + .system_spi_0_io_data_3_read ( system_spi_0_io_data_3_read ), + .system_spi_0_io_data_3_write ( system_spi_0_io_data_3_write ), + .system_spi_0_io_data_3_writeEnable ( system_spi_0_io_data_3_writeEnable ), + .system_spi_0_io_sclk_write ( system_spi_0_io_sclk_write ), + .system_spi_0_io_ss ( system_spi_0_io_ss ), + .system_uart_0_io_rxd ( system_uart_0_io_rxd ), + .system_uart_0_io_txd ( system_uart_0_io_txd ), + .system_i2c_0_io_scl_read ( system_i2c_0_io_scl_read ), + .system_i2c_0_io_scl_write ( system_i2c_0_io_scl_write ), + .system_i2c_0_io_sda_read ( system_i2c_0_io_sda_read ), + .system_gpio_0_io_read ( system_gpio_0_io_read ), + .system_gpio_0_io_write ( system_gpio_0_io_write ), + .system_gpio_0_io_writeEnable ( system_gpio_0_io_writeEnable ), + .cfg_done ( cfg_done ), + .cfg_start ( cfg_start ), + .cfg_sel ( cfg_sel ), + .cfg_reset ( cfg_reset ), + .axiAInterrupt ( axiAInterrupt ), + .axiA_awaddr ( axiA_awaddr ), + .axiA_awlen ( axiA_awlen ), + .axiA_awsize ( axiA_awsize ), + .axiA_awburst ( axiA_awburst ), + .axiA_awlock ( axiA_awlock ), + .axiA_awcache ( axiA_awcache ), + .axiA_awprot ( axiA_awprot ), + .axiA_awqos ( axiA_awqos ), + .axiA_awregion ( axiA_awregion ), + .axiA_awvalid ( axiA_awvalid ), + .axiA_awready ( axiA_awready ), + .axiA_wdata ( axiA_wdata ), + .axiA_wstrb ( axiA_wstrb ), + .axiA_wvalid ( axiA_wvalid ), + .axiA_wlast ( axiA_wlast ), + .axiA_wready ( axiA_wready ), + .axiA_bresp ( axiA_bresp ), + .axiA_bvalid ( axiA_bvalid ), + .axiA_bready ( axiA_bready ), + .axiA_araddr ( axiA_araddr ), + .axiA_arlen ( axiA_arlen ), + .axiA_arsize ( axiA_arsize ), + .axiA_arburst ( axiA_arburst ), + .axiA_arlock ( axiA_arlock ), + .axiA_arcache ( axiA_arcache ), + .axiA_arprot ( axiA_arprot ), + .axiA_arqos ( axiA_arqos ), + .axiA_arregion ( axiA_arregion ), + .axiA_arvalid ( axiA_arvalid ), + .axiA_arready ( axiA_arready ), + .axiA_rdata ( axiA_rdata ), + .axiA_rresp ( axiA_rresp ), + .axiA_rlast ( axiA_rlast ), + .axiA_rvalid ( axiA_rvalid ), + .axiA_rready ( axiA_rready ), + .userInterruptA ( userInterruptA ), + .userInterruptB ( userInterruptB ), + .userInterruptC ( userInterruptC ), + .userInterruptD ( userInterruptD ), + .userInterruptE ( userInterruptE ), + .userInterruptF ( userInterruptF ), + .io_apbSlave_0_PADDR ( io_apbSlave_0_PADDR ), + .io_apbSlave_0_PENABLE ( io_apbSlave_0_PENABLE ), + .io_apbSlave_0_PRDATA ( io_apbSlave_0_PRDATA ), + .io_apbSlave_0_PREADY ( io_apbSlave_0_PREADY ), + .io_apbSlave_0_PSEL ( io_apbSlave_0_PSEL ), + .io_apbSlave_0_PSLVERROR ( io_apbSlave_0_PSLVERROR ), + .io_apbSlave_0_PWDATA ( io_apbSlave_0_PWDATA ), + .io_apbSlave_0_PWRITE ( io_apbSlave_0_PWRITE ), + .system_i2c_0_io_sda_write ( system_i2c_0_io_sda_write ), + .system_i2c_0_io_sda_writeEnable ( system_i2c_0_io_sda_writeEnable ), + .system_i2c_0_io_scl_writeEnable ( system_i2c_0_io_scl_writeEnable ), + .system_watchdog_hardPanic_reset ( system_watchdog_hardPanic_reset ) +); diff --git a/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.vhd b/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.vhd new file mode 100644 index 0000000..e161e0a --- /dev/null +++ b/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.vhd @@ -0,0 +1,251 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +component EfxSapphireHpSoc_slb is +port ( + io_peripheralClk : in std_logic; + io_peripheralReset : in std_logic; + io_asyncReset : out std_logic; + io_gpio_sw_n : in std_logic; + pll_peripheral_locked : in std_logic; + pll_system_locked : in std_logic; + jtagCtrl_capture : out std_logic; + jtagCtrl_enable : out std_logic; + jtagCtrl_reset : out std_logic; + jtagCtrl_shift : out std_logic; + jtagCtrl_tdi : out std_logic; + jtagCtrl_tdo : in std_logic; + jtagCtrl_update : out std_logic; + ut_jtagCtrl_capture : in std_logic; + ut_jtagCtrl_enable : in std_logic; + ut_jtagCtrl_reset : in std_logic; + ut_jtagCtrl_shift : in std_logic; + ut_jtagCtrl_tdi : in std_logic; + ut_jtagCtrl_tdo : out std_logic; + ut_jtagCtrl_update : in std_logic; + system_spi_0_io_data_0_read : in std_logic; + system_spi_0_io_data_0_write : out std_logic; + system_spi_0_io_data_0_writeEnable : out std_logic; + system_spi_0_io_data_1_read : in std_logic; + system_spi_0_io_data_1_write : out std_logic; + system_spi_0_io_data_1_writeEnable : out std_logic; + system_spi_0_io_data_2_read : in std_logic; + system_spi_0_io_data_2_write : out std_logic; + system_spi_0_io_data_2_writeEnable : out std_logic; + system_spi_0_io_data_3_read : in std_logic; + system_spi_0_io_data_3_write : out std_logic; + system_spi_0_io_data_3_writeEnable : out std_logic; + system_spi_0_io_sclk_write : out std_logic; + system_spi_0_io_ss : out std_logic_vector(3 downto 0); + system_uart_0_io_rxd : in std_logic; + system_uart_0_io_txd : out std_logic; + system_i2c_0_io_scl_read : in std_logic; + system_i2c_0_io_scl_write : out std_logic; + system_i2c_0_io_sda_read : in std_logic; + system_gpio_0_io_read : in std_logic_vector(3 downto 0); + system_gpio_0_io_write : out std_logic_vector(3 downto 0); + system_gpio_0_io_writeEnable : out std_logic_vector(3 downto 0); + cfg_done : in std_logic; + cfg_start : out std_logic; + cfg_sel : out std_logic; + cfg_reset : out std_logic; + axiAInterrupt : out std_logic; + axiA_awaddr : in std_logic_vector(31 downto 0); + axiA_awlen : in std_logic_vector(7 downto 0); + axiA_awsize : in std_logic_vector(2 downto 0); + axiA_awburst : in std_logic_vector(1 downto 0); + axiA_awlock : in std_logic; + axiA_awcache : in std_logic_vector(3 downto 0); + axiA_awprot : in std_logic_vector(2 downto 0); + axiA_awqos : in std_logic_vector(3 downto 0); + axiA_awregion : in std_logic_vector(3 downto 0); + axiA_awvalid : in std_logic; + axiA_awready : out std_logic; + axiA_wdata : in std_logic_vector(31 downto 0); + axiA_wstrb : in std_logic_vector(3 downto 0); + axiA_wvalid : in std_logic; + axiA_wlast : in std_logic; + axiA_wready : out std_logic; + axiA_bresp : out std_logic_vector(1 downto 0); + axiA_bvalid : out std_logic; + axiA_bready : in std_logic; + axiA_araddr : in std_logic_vector(31 downto 0); + axiA_arlen : in std_logic_vector(7 downto 0); + axiA_arsize : in std_logic_vector(2 downto 0); + axiA_arburst : in std_logic_vector(1 downto 0); + axiA_arlock : in std_logic; + axiA_arcache : in std_logic_vector(3 downto 0); + axiA_arprot : in std_logic_vector(2 downto 0); + axiA_arqos : in std_logic_vector(3 downto 0); + axiA_arregion : in std_logic_vector(3 downto 0); + axiA_arvalid : in std_logic; + axiA_arready : out std_logic; + axiA_rdata : out std_logic_vector(31 downto 0); + axiA_rresp : out std_logic_vector(1 downto 0); + axiA_rlast : out std_logic; + axiA_rvalid : out std_logic; + axiA_rready : in std_logic; + userInterruptA : out std_logic; + userInterruptB : out std_logic; + userInterruptC : out std_logic; + userInterruptD : out std_logic; + userInterruptE : out std_logic; + userInterruptF : out std_logic; + io_apbSlave_0_PADDR : out std_logic_vector(31 downto 0); + io_apbSlave_0_PENABLE : out std_logic; + io_apbSlave_0_PRDATA : in std_logic_vector(31 downto 0); + io_apbSlave_0_PREADY : in std_logic; + io_apbSlave_0_PSEL : out std_logic; + io_apbSlave_0_PSLVERROR : in std_logic; + io_apbSlave_0_PWDATA : out std_logic_vector(31 downto 0); + io_apbSlave_0_PWRITE : out std_logic; + system_i2c_0_io_sda_write : out std_logic; + system_i2c_0_io_sda_writeEnable : out std_logic; + system_i2c_0_io_scl_writeEnable : out std_logic; + system_watchdog_hardPanic_reset : out std_logic +); +end component EfxSapphireHpSoc_slb; + +---------------------- End COMPONENT Declaration ------------ +------------- Begin Cut here for INSTANTIATION Template ----- +u_EfxSapphireHpSoc_slb : EfxSapphireHpSoc_slb +port map ( + io_peripheralClk => io_peripheralClk, + io_peripheralReset => io_peripheralReset, + io_asyncReset => io_asyncReset, + io_gpio_sw_n => io_gpio_sw_n, + pll_peripheral_locked => pll_peripheral_locked, + pll_system_locked => pll_system_locked, + jtagCtrl_capture => jtagCtrl_capture, + jtagCtrl_enable => jtagCtrl_enable, + jtagCtrl_reset => jtagCtrl_reset, + jtagCtrl_shift => jtagCtrl_shift, + jtagCtrl_tdi => jtagCtrl_tdi, + jtagCtrl_tdo => jtagCtrl_tdo, + jtagCtrl_update => jtagCtrl_update, + ut_jtagCtrl_capture => ut_jtagCtrl_capture, + ut_jtagCtrl_enable => ut_jtagCtrl_enable, + ut_jtagCtrl_reset => ut_jtagCtrl_reset, + ut_jtagCtrl_shift => ut_jtagCtrl_shift, + ut_jtagCtrl_tdi => ut_jtagCtrl_tdi, + ut_jtagCtrl_tdo => ut_jtagCtrl_tdo, + ut_jtagCtrl_update => ut_jtagCtrl_update, + system_spi_0_io_data_0_read => system_spi_0_io_data_0_read, + system_spi_0_io_data_0_write => system_spi_0_io_data_0_write, + system_spi_0_io_data_0_writeEnable => system_spi_0_io_data_0_writeEnable, + system_spi_0_io_data_1_read => system_spi_0_io_data_1_read, + system_spi_0_io_data_1_write => system_spi_0_io_data_1_write, + system_spi_0_io_data_1_writeEnable => system_spi_0_io_data_1_writeEnable, + system_spi_0_io_data_2_read => system_spi_0_io_data_2_read, + system_spi_0_io_data_2_write => system_spi_0_io_data_2_write, + system_spi_0_io_data_2_writeEnable => system_spi_0_io_data_2_writeEnable, + system_spi_0_io_data_3_read => system_spi_0_io_data_3_read, + system_spi_0_io_data_3_write => system_spi_0_io_data_3_write, + system_spi_0_io_data_3_writeEnable => system_spi_0_io_data_3_writeEnable, + system_spi_0_io_sclk_write => system_spi_0_io_sclk_write, + system_spi_0_io_ss => system_spi_0_io_ss, + system_uart_0_io_rxd => system_uart_0_io_rxd, + system_uart_0_io_txd => system_uart_0_io_txd, + system_i2c_0_io_scl_read => system_i2c_0_io_scl_read, + system_i2c_0_io_scl_write => system_i2c_0_io_scl_write, + system_i2c_0_io_sda_read => system_i2c_0_io_sda_read, + system_gpio_0_io_read => system_gpio_0_io_read, + system_gpio_0_io_write => system_gpio_0_io_write, + system_gpio_0_io_writeEnable => system_gpio_0_io_writeEnable, + cfg_done => cfg_done, + cfg_start => cfg_start, + cfg_sel => cfg_sel, + cfg_reset => cfg_reset, + axiAInterrupt => axiAInterrupt, + axiA_awaddr => axiA_awaddr, + axiA_awlen => axiA_awlen, + axiA_awsize => axiA_awsize, + axiA_awburst => axiA_awburst, + axiA_awlock => axiA_awlock, + axiA_awcache => axiA_awcache, + axiA_awprot => axiA_awprot, + axiA_awqos => axiA_awqos, + axiA_awregion => axiA_awregion, + axiA_awvalid => axiA_awvalid, + axiA_awready => axiA_awready, + axiA_wdata => axiA_wdata, + axiA_wstrb => axiA_wstrb, + axiA_wvalid => axiA_wvalid, + axiA_wlast => axiA_wlast, + axiA_wready => axiA_wready, + axiA_bresp => axiA_bresp, + axiA_bvalid => axiA_bvalid, + axiA_bready => axiA_bready, + axiA_araddr => axiA_araddr, + axiA_arlen => axiA_arlen, + axiA_arsize => axiA_arsize, + axiA_arburst => axiA_arburst, + axiA_arlock => axiA_arlock, + axiA_arcache => axiA_arcache, + axiA_arprot => axiA_arprot, + axiA_arqos => axiA_arqos, + axiA_arregion => axiA_arregion, + axiA_arvalid => axiA_arvalid, + axiA_arready => axiA_arready, + axiA_rdata => axiA_rdata, + axiA_rresp => axiA_rresp, + axiA_rlast => axiA_rlast, + axiA_rvalid => axiA_rvalid, + axiA_rready => axiA_rready, + userInterruptA => userInterruptA, + userInterruptB => userInterruptB, + userInterruptC => userInterruptC, + userInterruptD => userInterruptD, + userInterruptE => userInterruptE, + userInterruptF => userInterruptF, + io_apbSlave_0_PADDR => io_apbSlave_0_PADDR, + io_apbSlave_0_PENABLE => io_apbSlave_0_PENABLE, + io_apbSlave_0_PRDATA => io_apbSlave_0_PRDATA, + io_apbSlave_0_PREADY => io_apbSlave_0_PREADY, + io_apbSlave_0_PSEL => io_apbSlave_0_PSEL, + io_apbSlave_0_PSLVERROR => io_apbSlave_0_PSLVERROR, + io_apbSlave_0_PWDATA => io_apbSlave_0_PWDATA, + io_apbSlave_0_PWRITE => io_apbSlave_0_PWRITE, + system_i2c_0_io_sda_write => system_i2c_0_io_sda_write, + system_i2c_0_io_sda_writeEnable => system_i2c_0_io_sda_writeEnable, + system_i2c_0_io_scl_writeEnable => system_i2c_0_io_scl_writeEnable, + system_watchdog_hardPanic_reset => system_watchdog_hardPanic_reset +); + +------------------------ End INSTANTIATION Template --------- diff --git a/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_wrapper.v b/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_wrapper.v new file mode 100644 index 0000000..dc09c96 --- /dev/null +++ b/fpga/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_wrapper.v @@ -0,0 +1,402 @@ +module EfxSapphireHpSoc_wrapper ( +input cpu0_customInstruction_cmd_valid, +output cpu0_customInstruction_cmd_ready, +input [9:0] cpu0_customInstruction_function_id, +input [31:0] cpu0_customInstruction_inputs_0, +input [31:0] cpu0_customInstruction_inputs_1, +output cpu0_customInstruction_rsp_valid, +input cpu0_customInstruction_rsp_ready, +output [31:0] cpu0_customInstruction_outputs_0, +output userInterruptB, +output userInterruptE, +input cpu2_customInstruction_cmd_valid, +output cpu2_customInstruction_cmd_ready, +input [9:0] cpu2_customInstruction_function_id, +input [31:0] cpu2_customInstruction_inputs_0, +input [31:0] cpu2_customInstruction_inputs_1, +output cpu2_customInstruction_rsp_valid, +input cpu2_customInstruction_rsp_ready, +output [31:0] cpu2_customInstruction_outputs_0, +input io_cfuClk, +input io_cfuReset, +output system_spi_0_io_sclk_write, +output system_spi_0_io_data_0_writeEnable, +input system_spi_0_io_data_0_read, +output system_spi_0_io_data_0_write, +output system_spi_0_io_data_1_writeEnable, +input system_spi_0_io_data_1_read, +output system_spi_0_io_data_1_write, +output system_spi_0_io_data_2_writeEnable, +input system_spi_0_io_data_2_read, +output system_spi_0_io_data_2_write, +output system_spi_0_io_data_3_writeEnable, +input system_spi_0_io_data_3_read, +output system_spi_0_io_data_3_write, +output [3:0] system_spi_0_io_ss, +output userInterruptC, +output userInterruptH, +input cpu1_customInstruction_cmd_valid, +output cpu1_customInstruction_cmd_ready, +input [9:0] cpu1_customInstruction_function_id, +input [31:0] cpu1_customInstruction_inputs_0, +input [31:0] cpu1_customInstruction_inputs_1, +output cpu1_customInstruction_rsp_valid, +input cpu1_customInstruction_rsp_ready, +output [31:0] cpu1_customInstruction_outputs_0, +output jtagCtrl_tdi, +input jtagCtrl_tdo, +output jtagCtrl_enable, +output jtagCtrl_capture, +output jtagCtrl_shift, +output jtagCtrl_update, +output jtagCtrl_reset, +input ut_jtagCtrl_tdi, +output ut_jtagCtrl_tdo, +input ut_jtagCtrl_enable, +input ut_jtagCtrl_capture, +input ut_jtagCtrl_shift, +input ut_jtagCtrl_update, +input ut_jtagCtrl_reset, +output system_uart_0_io_txd, +input system_uart_0_io_rxd, +output io_ddrMasters_0_aw_valid, +input io_ddrMasters_0_aw_ready, +output [31:0] io_ddrMasters_0_aw_payload_addr, +output [3:0] io_ddrMasters_0_aw_payload_id, +output [3:0] io_ddrMasters_0_aw_payload_region, +output [7:0] io_ddrMasters_0_aw_payload_len, +output [2:0] io_ddrMasters_0_aw_payload_size, +output [1:0] io_ddrMasters_0_aw_payload_burst, +output io_ddrMasters_0_aw_payload_lock, +output [3:0] io_ddrMasters_0_aw_payload_cache, +output [3:0] io_ddrMasters_0_aw_payload_qos, +output [2:0] io_ddrMasters_0_aw_payload_prot, +output io_ddrMasters_0_aw_payload_allStrb, +output io_ddrMasters_0_w_valid, +input io_ddrMasters_0_w_ready, +output [127:0] io_ddrMasters_0_w_payload_data, +output [15:0] io_ddrMasters_0_w_payload_strb, +output io_ddrMasters_0_w_payload_last, +input io_ddrMasters_0_b_valid, +output io_ddrMasters_0_b_ready, +input [3:0] io_ddrMasters_0_b_payload_id, +input [1:0] io_ddrMasters_0_b_payload_resp, +output io_ddrMasters_0_ar_valid, +input io_ddrMasters_0_ar_ready, +output [31:0] io_ddrMasters_0_ar_payload_addr, +output [3:0] io_ddrMasters_0_ar_payload_id, +output [3:0] io_ddrMasters_0_ar_payload_region, +output [7:0] io_ddrMasters_0_ar_payload_len, +output [2:0] io_ddrMasters_0_ar_payload_size, +output [1:0] io_ddrMasters_0_ar_payload_burst, +output io_ddrMasters_0_ar_payload_lock, +output [3:0] io_ddrMasters_0_ar_payload_cache, +output [3:0] io_ddrMasters_0_ar_payload_qos, +output [2:0] io_ddrMasters_0_ar_payload_prot, +input io_ddrMasters_0_r_valid, +output io_ddrMasters_0_r_ready, +input [127:0] io_ddrMasters_0_r_payload_data, +input [3:0] io_ddrMasters_0_r_payload_id, +input [1:0] io_ddrMasters_0_r_payload_resp, +input io_ddrMasters_0_r_payload_last, +input io_ddrMasters_0_clk, +input io_ddrMasters_0_reset, +output userInterruptF, +output userInterruptG, +output userInterruptA, +output system_i2c_0_io_sda_writeEnable, +output system_i2c_0_io_sda_write, +input system_i2c_0_io_sda_read, +output system_i2c_0_io_scl_writeEnable, +output system_i2c_0_io_scl_write, +input system_i2c_0_io_scl_read, +input [3:0] system_gpio_0_io_read, +output [3:0] system_gpio_0_io_write, +output [3:0] system_gpio_0_io_writeEnable, +output system_watchdog_hardPanic_reset, +output userInterruptI, +input cpu3_customInstruction_cmd_valid, +output cpu3_customInstruction_cmd_ready, +input [9:0] cpu3_customInstruction_function_id, +input [31:0] cpu3_customInstruction_inputs_0, +input [31:0] cpu3_customInstruction_inputs_1, +output cpu3_customInstruction_rsp_valid, +input cpu3_customInstruction_rsp_ready, +output [31:0] cpu3_customInstruction_outputs_0, +output userInterruptD, +input [31:0] axiA_awaddr, +input [7:0] axiA_awlen, +input [2:0] axiA_awsize, +input [1:0] axiA_awburst, +input axiA_awlock, +input [3:0] axiA_awcache, +input [2:0] axiA_awprot, +input [3:0] axiA_awqos, +input [3:0] axiA_awregion, +input axiA_awvalid, +output axiA_awready, +input [31:0] axiA_wdata, +input [3:0] axiA_wstrb, +input axiA_wvalid, +input axiA_wlast, +output axiA_wready, +output [1:0] axiA_bresp, +output axiA_bvalid, +input axiA_bready, +input [31:0] axiA_araddr, +input [7:0] axiA_arlen, +input [2:0] axiA_arsize, +input [1:0] axiA_arburst, +input axiA_arlock, +input [3:0] axiA_arcache, +input [2:0] axiA_arprot, +input [3:0] axiA_arqos, +input [3:0] axiA_arregion, +input axiA_arvalid, +output axiA_arready, +output [31:0] axiA_rdata, +output [1:0] axiA_rresp, +output axiA_rlast, +output axiA_rvalid, +input axiA_rready, +output axiAInterrupt, +input cfg_done, +output cfg_start, +output cfg_sel, +output cfg_reset, +input io_peripheralClk, +input io_peripheralReset, +output io_asyncReset, +input io_gpio_sw_n, +input pll_peripheral_locked, +input pll_system_locked +); + +wire [15:0] io_apbSlave_0_PADDR; +wire io_apbSlave_0_PSEL; +wire io_apbSlave_0_PENABLE; +wire io_apbSlave_0_PREADY; +wire io_apbSlave_0_PWRITE; +wire [31:0] io_apbSlave_0_PWDATA; +wire [31:0] io_apbSlave_0_PRDATA; +wire io_apbSlave_0_PSLVERROR; + + +assign userInterruptG = 1'b0; //USER TO MODIFY +assign userInterruptH = 1'b0; //USER TO MODIFY +assign userInterruptI = 1'b0; //USER TO MODIFY + +/**/ +/* INFO: USER TO MODIFY CODES BELOW */ +/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */ +/**/ +assign cpu3_customInstruction_cmd_ready = 1'b1; +assign cpu3_customInstruction_rsp_valid = 1'b0; +assign cpu3_customInstruction_outputs_0 = 32'd0; +//io_cfuClk +//io_cfyReset +//cpu3_customInstruction_rsp_ready +//cpu3_customInstruction_cmd_valid +//cpu3_customInstruction_function_id +//cpu3_customInstruction_inputs_0 +//cpu3_customInstruction_inputs_1 + +/**/ +/* INFO: USER TO MODIFY CODES BELOW */ +/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */ +/**/ +assign cpu0_customInstruction_cmd_ready = 1'b1; +assign cpu0_customInstruction_rsp_valid = 1'b0; +assign cpu0_customInstruction_outputs_0 = 32'd0; +//io_cfuClk +//io_cfyReset +//cpu0_customInstruction_rsp_ready +//cpu0_customInstruction_cmd_valid +//cpu0_customInstruction_function_id +//cpu0_customInstruction_inputs_0 +//cpu0_customInstruction_inputs_1 + +/**/ +/* INFO: USER TO MODIFY CODES BELOW */ +/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */ +/**/ +assign cpu1_customInstruction_cmd_ready = 1'b1; +assign cpu1_customInstruction_rsp_valid = 1'b0; +assign cpu1_customInstruction_outputs_0 = 32'd0; +//io_cfuClk +//io_cfyReset +//cpu1_customInstruction_rsp_ready +//cpu1_customInstruction_cmd_valid +//cpu1_customInstruction_function_id +//cpu1_customInstruction_inputs_0 +//cpu1_customInstruction_inputs_1 + +/**/ +/* INFO: USER TO MODIFY CODES BELOW */ +/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */ +/**/ +assign io_apbSlave_0_PREADY = 1'b1; +assign io_apbSlave_0_PRDATA = 32'd0; +//io_apbSlave_0_PADDR; +//io_apbSlave_0_PSEL; +//io_apbSlave_0_PENABLE; +//io_apbSlave_0_PWRITE; +//io_apbSlave_0_PWDATA; +//io_apbSlave_0_PSLVERROR; +/**/ +/* INFO: USER TO MODIFY CODES BELOW */ +/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */ +/**/ +assign cpu2_customInstruction_cmd_ready = 1'b1; +assign cpu2_customInstruction_rsp_valid = 1'b0; +assign cpu2_customInstruction_outputs_0 = 32'd0; +//io_cfuClk +//io_cfyReset +//cpu2_customInstruction_rsp_ready +//cpu2_customInstruction_cmd_valid +//cpu2_customInstruction_function_id +//cpu2_customInstruction_inputs_0 +//cpu2_customInstruction_inputs_1 + +/**/ +/* INFO: USER TO MODIFY CODES BELOW */ +/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */ +/**/ +assign io_ddrMasters_0_aw_payload_addr = 32'd0; +assign io_ddrMasters_0_aw_payload_id = 4'd0; +assign io_ddrMasters_0_aw_payload_region = 4'd0; +assign io_ddrMasters_0_aw_payload_len = 8'd0; +assign io_ddrMasters_0_aw_payload_size = 3'd0; +assign io_ddrMasters_0_aw_payload_burst = 2'd0; +assign io_ddrMasters_0_aw_payload_lock = 1'b0; +assign io_ddrMasters_0_aw_payload_cache = 4'd0; +assign io_ddrMasters_0_aw_payload_qos = 4'd0; +assign io_ddrMasters_0_aw_payload_prot = 3'd0; +assign io_ddrMasters_0_aw_payload_allStrb = 1'b0; +assign io_ddrMasters_0_w_valid = 1'b0; +//io_ddrMasters_0_w_ready +assign io_ddrMasters_0_w_payload_data = 128'd0; +assign io_ddrMasters_0_w_payload_strb = 16'd0; +assign io_ddrMasters_0_w_payload_last = 1'b0; +//io_ddrMasters_0_b_valid +assign io_ddrMasters_0_b_ready = 1'b1; +//io_ddrMasters_0_b_payload_id +//io_ddrMasters_0_b_payload_resp +assign io_ddrMasters_0_ar_valid = 1'b0; +//io_ddrMasters_0_ar_ready +assign io_ddrMasters_0_ar_payload_addr = 32'd0; +assign io_ddrMasters_0_ar_payload_id = 4'd0; +assign io_ddrMasters_0_ar_payload_region = 4'd0; +assign io_ddrMasters_0_ar_payload_len = 8'd0; +assign io_ddrMasters_0_ar_payload_size = 3'd0; +assign io_ddrMasters_0_ar_payload_burst = 2'd0; +assign io_ddrMasters_0_ar_payload_lock = 1'b0; +assign io_ddrMasters_0_ar_payload_cache = 4'd0; +assign io_ddrMasters_0_ar_payload_qos = 4'd0; +assign io_ddrMasters_0_ar_payload_pro = 3'd0; +//io_ddrMasters_0_r_valid +assign io_ddrMasters_0_r_ready = 1'b1; +//io_ddrMasters_0_r_payload_data +//io_ddrMasters_0_r_payload_id +//io_ddrMasters_0_r_payload_resp +//io_ddrMasters_0_r_payload_last + + + +//axi4 bridge to various I/O +EfxSapphireHpSoc_slb u_top_peripherals( +.userInterruptD(userInterruptD), +.userInterruptA(userInterruptA), +.system_watchdog_hardPanic_reset(system_watchdog_hardPanic_reset), +.system_uart_0_io_txd(system_uart_0_io_txd), +.system_uart_0_io_rxd(system_uart_0_io_rxd), +.system_spi_0_io_sclk_write(system_spi_0_io_sclk_write), +.system_spi_0_io_data_0_writeEnable(system_spi_0_io_data_0_writeEnable), +.system_spi_0_io_data_0_read(system_spi_0_io_data_0_read), +.system_spi_0_io_data_0_write(system_spi_0_io_data_0_write), +.system_spi_0_io_data_1_writeEnable(system_spi_0_io_data_1_writeEnable), +.system_spi_0_io_data_1_read(system_spi_0_io_data_1_read), +.system_spi_0_io_data_1_write(system_spi_0_io_data_1_write), +.system_spi_0_io_data_2_writeEnable(system_spi_0_io_data_2_writeEnable), +.system_spi_0_io_data_2_read(system_spi_0_io_data_2_read), +.system_spi_0_io_data_2_write(system_spi_0_io_data_2_write), +.system_spi_0_io_data_3_writeEnable(system_spi_0_io_data_3_writeEnable), +.system_spi_0_io_data_3_read(system_spi_0_io_data_3_read), +.system_spi_0_io_data_3_write(system_spi_0_io_data_3_write), +.system_spi_0_io_ss(system_spi_0_io_ss), +.system_gpio_0_io_read(system_gpio_0_io_read), +.system_gpio_0_io_write(system_gpio_0_io_write), +.system_gpio_0_io_writeEnable(system_gpio_0_io_writeEnable), +.userInterruptB(userInterruptB), +.userInterruptE(userInterruptE), +.io_apbSlave_0_PADDR(io_apbSlave_0_PADDR), +.io_apbSlave_0_PSEL(io_apbSlave_0_PSEL), +.io_apbSlave_0_PENABLE(io_apbSlave_0_PENABLE), +.io_apbSlave_0_PREADY(io_apbSlave_0_PREADY), +.io_apbSlave_0_PWRITE(io_apbSlave_0_PWRITE), +.io_apbSlave_0_PWDATA(io_apbSlave_0_PWDATA), +.io_apbSlave_0_PRDATA(io_apbSlave_0_PRDATA), +.io_apbSlave_0_PSLVERROR(io_apbSlave_0_PSLVERROR), +.system_i2c_0_io_sda_writeEnable(system_i2c_0_io_sda_writeEnable), +.system_i2c_0_io_sda_write(system_i2c_0_io_sda_write), +.system_i2c_0_io_sda_read(system_i2c_0_io_sda_read), +.system_i2c_0_io_scl_writeEnable(system_i2c_0_io_scl_writeEnable), +.system_i2c_0_io_scl_write(system_i2c_0_io_scl_write), +.system_i2c_0_io_scl_read(system_i2c_0_io_scl_read), +.userInterruptF(userInterruptF), +.jtagCtrl_tdi(jtagCtrl_tdi), +.jtagCtrl_tdo(jtagCtrl_tdo), +.jtagCtrl_enable(jtagCtrl_enable), +.jtagCtrl_capture(jtagCtrl_capture), +.jtagCtrl_shift(jtagCtrl_shift), +.jtagCtrl_update(jtagCtrl_update), +.jtagCtrl_reset(jtagCtrl_reset), +.ut_jtagCtrl_tdi(ut_jtagCtrl_tdi), +.ut_jtagCtrl_tdo(ut_jtagCtrl_tdo), +.ut_jtagCtrl_enable(ut_jtagCtrl_enable), +.ut_jtagCtrl_capture(ut_jtagCtrl_capture), +.ut_jtagCtrl_shift(ut_jtagCtrl_shift), +.ut_jtagCtrl_update(ut_jtagCtrl_update), +.ut_jtagCtrl_reset(ut_jtagCtrl_reset), +.userInterruptC(userInterruptC), +.axiA_awvalid(axiA_awvalid), +.axiA_awready(axiA_awready), +.axiA_awaddr(axiA_awaddr), +.axiA_awlen(axiA_awlen), +.axiA_awsize(axiA_awsize), +.axiA_awcache(axiA_awcache), +.axiA_awprot(axiA_awprot), +.axiA_wvalid(axiA_wvalid), +.axiA_wready(axiA_wready), +.axiA_wdata(axiA_wdata), +.axiA_wstrb(axiA_wstrb), +.axiA_wlast(axiA_wlast), +.axiA_bvalid(axiA_bvalid), +.axiA_bready(axiA_bready), +.axiA_bresp(axiA_bresp), +.axiA_arvalid(axiA_arvalid), +.axiA_arready(axiA_arready), +.axiA_araddr(axiA_araddr), +.axiA_arlen(axiA_arlen), +.axiA_arsize(axiA_arsize), +.axiA_arcache(axiA_arcache), +.axiA_arprot(axiA_arprot), +.axiA_rvalid(axiA_rvalid), +.axiA_rready(axiA_rready), +.axiA_rdata(axiA_rdata), +.axiA_rresp(axiA_rresp), +.axiA_rlast(axiA_rlast), +.axiAInterrupt(axiAInterrupt), +.cfg_done(cfg_done), +.cfg_start(cfg_start), +.cfg_sel(cfg_sel), +.cfg_reset(cfg_reset), +.io_peripheralClk(io_peripheralClk), +.io_peripheralReset(io_peripheralReset), +.io_asyncReset(io_asyncReset), +.io_gpio_sw_n(io_gpio_sw_n), +.pll_peripheral_locked(pll_peripheral_locked), +.pll_system_locked(pll_system_locked) +); + +endmodule diff --git a/fpga/ip/EfxSapphireHpSoc_slb/hard_ip_args.ini b/fpga/ip/EfxSapphireHpSoc_slb/hard_ip_args.ini new file mode 100644 index 0000000..5536035 --- /dev/null +++ b/fpga/ip/EfxSapphireHpSoc_slb/hard_ip_args.ini @@ -0,0 +1,224 @@ +[parameters] +pll_soc_sys_clk_name = soc_pll_sys_clk +hidden_min_freq = 0 +pll_soc_sys_clk_ref_freq_hidden = 100 +pll_soc_sys_clk_ref_freq = 100 +pll_soc_sys_clkout1_freq = 1000 +pll_soc_sys_clkout1_phase = 0 +pll_soc_sys_clkout2_freq = 250 +pll_soc_sys_clkout2_phase = 0 +pll_soc_mem_clk_name = soc_pll_peri_clk +pll_soc_mem_clk_ref_freq = 25 +pll_soc_mem_clkout1_freq = 250 +pll_soc_mem_clkout1_phase = 0 +pll_soc_mem_clkout2_freq = 250 +pll_soc_mem_clkout2_phase = 0 +pll_lpddr4_name = soc_ddr_pll +pll_lpddr4_ref_freq = 25 +pll_lpddr4_clkout0_freq = 100 +pll_lpddr4_clkout0_phase = 0 +pll_lpddr4_clkout3_freq = 533 +pll_lpddr4_clkout3_phase = 0 +ddr_data_width = 32 +ddr_memory_density = 8G +ddr_memory_type = LPDDR4x +ddr_physical_rank = 1 +ddr_pin_name = soc_ddr_inst1 +gpio_bus_name = system_gpio_0 +hard_jtag_inst_name = soc_jtag_inst1 +uart0_gpio_inst_name = system_uart_0 +spi0_gpio_inst_name = system_spi_0 +i2c0_gpio_inst_name = system_i2c_0 +jtag_gpio_inst_name = io_jtag +soc_pin_name = qcrv32_inst1 +intf_axim = 1 +intf_ci_0 = 1 +intf_ci_1 = 1 +intf_ci_2 = 1 +intf_ci_3 = 1 +co_debug = 0 +intf_jtag_type = 0 +intf_uintr = 9 +peri_spi_0 = 1 +peri_spi_1 = 0 +peri_spi_2 = 0 +peri_i2c_0 = 1 +peri_i2c_1 = 0 +peri_i2c_2 = 0 +peri_gpio_0 = 1 +peri_gpio_1 = 0 +peri_wdt_0 = 1 +peri_apb_0 = 1 +peri_apb_1 = 0 +peri_apb_2 = 0 +peri_apb_3 = 0 +peri_apb_4 = 0 +peri_gen = 1 +peri_uart_0 = 1 +peri_uart_1 = 0 +peri_uart_2 = 0 +peri_gpio_0_width = 4 +peri_gpio_1_width = 4 +peri_apb_0_size = 65536 +peri_apb_1_size = 4096 +peri_apb_2_size = 4096 +peri_apb_3_size = 4096 +peri_apb_4_size = 4096 +peri_freq = 200 +app_overwrite = 0 +app_overwrite_path = +peri_count = 6 +peri_tcount = 6 +intf_jtag_tap_sel = 8 +intf_axis = 1 +peri_pin_assign = 1 +pll_soc_mem_resource = PLL_TR0 +sys_freq = 1000 +sys_freq_hidden = 1000 +pll_soc_sys_clkout3_freq = 250 +pll_soc_sys_clkout3_phase = 0 +pll_soc_mem_clkout3_freq = 250 +pll_soc_mem_clkout3_phase = 0 +pll_soc_mem_clkout4_freq = 200 +pll_soc_mem_clkout4_phase = 0 +pll_soc_sys_resource = PLL_BL0 +pll_lpddr4_resource = PLL_BL2 +pll_res_assign = 0 +pll_soc_sys_clkout0_freq = 100 +pll_soc_sys_clkout0_phase = 0 +pll_soc_mem_clkout0_freq = 100 +pll_soc_mem_clkout0_phase = 0 +pll_lpddr4_clkout1_freq = 33 +pll_lpddr4_clkout1_phase = 0 +mem_freq = 250 +axim_freq = 250 +cfu_freq = 125 +ddr_freq = 800 +pll_res_assign_2 = 0 +ddr_res_assign = 0 +peri_res_assign = 0 +pll_soc_sys_ext_clk_src = 1 +pll_soc_mem_ext_clk_src = 0 +peri_sdhc = 0 +peri_tsemac = 0 +sw_ftdi_ch_num = 6011 +sw_app_size = 2044 +sw_app_size_custom = 0 +sw_stack_size = 8 +sw_stack_size_custom = 0 +sw_board = Ti375C529 Development Kit +sw_board_custom = +sw_ftdi_target_ch = 1 +sw_ftdi_ch_num_soft = 6011 +sw_ftdi_target_ch_soft = 0 +sw_frtos_app_size = 16380 +sw_frtos_app_size_custom = 0 +sw_frtos_stack_size = 4 +sw_frtos_stack_size_custom = 0 +package_type = 529 +family_type = TITANIUM +axi_pipeline = 0 +axi_write_buffer = 0 + +[ports] +io_peripheralclk = io_peripheralClk +io_peripheralreset = io_peripheralReset +io_asyncreset = io_asyncReset +io_gpio_sw_n = io_gpio_sw_n +pll_peripheral_locked = pll_peripheral_locked +pll_system_locked = pll_system_locked +jtagctrl_capture = jtagCtrl_capture +jtagctrl_enable = jtagCtrl_enable +jtagctrl_reset = jtagCtrl_reset +jtagctrl_shift = jtagCtrl_shift +jtagctrl_tdi = jtagCtrl_tdi +jtagctrl_tdo = jtagCtrl_tdo +jtagctrl_update = jtagCtrl_update +ut_jtagctrl_capture = ut_jtagCtrl_capture +ut_jtagctrl_enable = ut_jtagCtrl_enable +ut_jtagctrl_reset = ut_jtagCtrl_reset +ut_jtagctrl_shift = ut_jtagCtrl_shift +ut_jtagctrl_tdi = ut_jtagCtrl_tdi +ut_jtagctrl_tdo = ut_jtagCtrl_tdo +ut_jtagctrl_update = ut_jtagCtrl_update +system_spi_0_io_data_0_read = system_spi_0_io_data_0_read +system_spi_0_io_data_0_write = system_spi_0_io_data_0_write +system_spi_0_io_data_0_writeenable = system_spi_0_io_data_0_writeEnable +system_spi_0_io_data_1_read = system_spi_0_io_data_1_read +system_spi_0_io_data_1_write = system_spi_0_io_data_1_write +system_spi_0_io_data_1_writeenable = system_spi_0_io_data_1_writeEnable +system_spi_0_io_data_2_read = system_spi_0_io_data_2_read +system_spi_0_io_data_2_write = system_spi_0_io_data_2_write +system_spi_0_io_data_2_writeenable = system_spi_0_io_data_2_writeEnable +system_spi_0_io_data_3_read = system_spi_0_io_data_3_read +system_spi_0_io_data_3_write = system_spi_0_io_data_3_write +system_spi_0_io_data_3_writeenable = system_spi_0_io_data_3_writeEnable +system_spi_0_io_sclk_write = system_spi_0_io_sclk_write +system_spi_0_io_ss = system_spi_0_io_ss +system_uart_0_io_rxd = system_uart_0_io_rxd +system_uart_0_io_txd = system_uart_0_io_txd +system_i2c_0_io_scl_read = system_i2c_0_io_scl_read +system_i2c_0_io_scl_write = system_i2c_0_io_scl_write +system_i2c_0_io_sda_read = system_i2c_0_io_sda_read +system_gpio_0_io_read = system_gpio_0_io_read +system_gpio_0_io_write = system_gpio_0_io_write +system_gpio_0_io_writeenable = system_gpio_0_io_writeEnable +cfg_done = cfg_done +cfg_start = cfg_start +cfg_sel = cfg_sel +cfg_reset = cfg_reset +axiainterrupt = axiAInterrupt +axia_awaddr = axiA_awaddr +axia_awlen = axiA_awlen +axia_awsize = axiA_awsize +axia_awburst = axiA_awburst +axia_awlock = axiA_awlock +axia_awcache = axiA_awcache +axia_awprot = axiA_awprot +axia_awqos = axiA_awqos +axia_awregion = axiA_awregion +axia_awvalid = axiA_awvalid +axia_awready = axiA_awready +axia_wdata = axiA_wdata +axia_wstrb = axiA_wstrb +axia_wvalid = axiA_wvalid +axia_wlast = axiA_wlast +axia_wready = axiA_wready +axia_bresp = axiA_bresp +axia_bvalid = axiA_bvalid +axia_bready = axiA_bready +axia_araddr = axiA_araddr +axia_arlen = axiA_arlen +axia_arsize = axiA_arsize +axia_arburst = axiA_arburst +axia_arlock = axiA_arlock +axia_arcache = axiA_arcache +axia_arprot = axiA_arprot +axia_arqos = axiA_arqos +axia_arregion = axiA_arregion +axia_arvalid = axiA_arvalid +axia_arready = axiA_arready +axia_rdata = axiA_rdata +axia_rresp = axiA_rresp +axia_rlast = axiA_rlast +axia_rvalid = axiA_rvalid +axia_rready = axiA_rready +userinterrupta = userInterruptA +userinterruptb = userInterruptB +userinterruptc = userInterruptC +userinterruptd = userInterruptD +userinterrupte = userInterruptE +userinterruptf = userInterruptF +io_apbslave_0_paddr = io_apbSlave_0_PADDR +io_apbslave_0_penable = io_apbSlave_0_PENABLE +io_apbslave_0_prdata = io_apbSlave_0_PRDATA +io_apbslave_0_pready = io_apbSlave_0_PREADY +io_apbslave_0_psel = io_apbSlave_0_PSEL +io_apbslave_0_pslverror = io_apbSlave_0_PSLVERROR +io_apbslave_0_pwdata = io_apbSlave_0_PWDATA +io_apbslave_0_pwrite = io_apbSlave_0_PWRITE +system_i2c_0_io_sda_write = system_i2c_0_io_sda_write +system_i2c_0_io_sda_writeenable = system_i2c_0_io_sda_writeEnable +system_i2c_0_io_scl_writeenable = system_i2c_0_io_scl_writeEnable +system_watchdog_hardpanic_reset = system_watchdog_hardPanic_reset + diff --git a/fpga/ip/EfxSapphireHpSoc_slb/ipm/component.pickle b/fpga/ip/EfxSapphireHpSoc_slb/ipm/component.pickle new file mode 100644 index 0000000..f8b5aad Binary files /dev/null and b/fpga/ip/EfxSapphireHpSoc_slb/ipm/component.pickle differ diff --git a/fpga/ip/EfxSapphireHpSoc_slb/ipm/graph.pickle b/fpga/ip/EfxSapphireHpSoc_slb/ipm/graph.pickle new file mode 100644 index 0000000..0ac1fb4 Binary files /dev/null and b/fpga/ip/EfxSapphireHpSoc_slb/ipm/graph.pickle differ diff --git a/fpga/ip/EfxSapphireHpSoc_slb/ipm_pt_map.json b/fpga/ip/EfxSapphireHpSoc_slb/ipm_pt_map.json new file mode 100644 index 0000000..45a8436 --- /dev/null +++ b/fpga/ip/EfxSapphireHpSoc_slb/ipm_pt_map.json @@ -0,0 +1,20 @@ +{ + "PLL": {}, + "GPIO": { + "UART": [], + "SPI": [], + "I2C": [], + "JTAG": [], + "GPIO": [] + }, + "SOC": { + "SOC_PIN_NAME": { + "SOC_PIN_NAME": "qcrv32_inst1" + } + }, + "JTAG": { + "HARD_JTAG_INST_NAME": { + "HARD_JTAG_INST_NAME": "soc_jtag_inst1" + } + } +} \ No newline at end of file diff --git a/fpga/ip/EfxSapphireHpSoc_slb/settings.json b/fpga/ip/EfxSapphireHpSoc_slb/settings.json new file mode 100644 index 0000000..0b4da61 --- /dev/null +++ b/fpga/ip/EfxSapphireHpSoc_slb/settings.json @@ -0,0 +1,139 @@ +{ + "args": [ + "-o", + "EfxSapphireHpSoc_slb", + "--base_path", + "/projects/SSE/llching/repo/efx_IP_master/efx_IP/efx_hard_soc/fpga/Ti375C529_devkit/ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "soc", + "name": "efx_hard_soc", + "version": "1.22.0" + } + ], + "conf": { + "PLL_SOC_SYS_CLK_NAME": "\"soc_pll_sys_clk\"", + "PLL_SOC_SYS_CLK_REF_FREQ_HIDDEN": "\"100\"", + "PLL_SOC_SYS_CLK_REF_FREQ": "\"100\"", + "PLL_SOC_SYS_CLKOUT1_PHASE": "\"0\"", + "PLL_SOC_SYS_CLKOUT2_PHASE": "\"0\"", + "PLL_SOC_MEM_CLK_NAME": "\"soc_pll_peri_clk\"", + "PLL_SOC_MEM_CLK_REF_FREQ": "\"25\"", + "PLL_SOC_MEM_CLKOUT1_FREQ": "\"250\"", + "PLL_SOC_MEM_CLKOUT1_PHASE": "\"0\"", + "PLL_SOC_MEM_CLKOUT2_FREQ": "\"250\"", + "PLL_SOC_MEM_CLKOUT2_PHASE": "\"0\"", + "PLL_LPDDR4_NAME": "\"soc_ddr_pll\"", + "PLL_LPDDR4_REF_FREQ": "\"25\"", + "PLL_LPDDR4_CLKOUT0_FREQ": "\"100\"", + "PLL_LPDDR4_CLKOUT0_PHASE": "\"0\"", + "PLL_LPDDR4_CLKOUT3_FREQ": "\"533\"", + "PLL_LPDDR4_CLKOUT3_PHASE": "\"0\"", + "DDR_DATA_WIDTH": "32", + "DDR_MEMORY_DENSITY": "\"8G\"", + "DDR_MEMORY_TYPE": "\"LPDDR4x\"", + "DDR_PHYSICAL_RANK": "1", + "DDR_PIN_NAME": "\"soc_ddr_inst1\"", + "INTF_AXIM": "1'b1", + "INTF_CI_0": "1'b1", + "INTF_CI_1": "1'b1", + "INTF_CI_2": "1'b1", + "INTF_CI_3": "1'b1", + "CO_DEBUG": "1'b0", + "INTF_JTAG_TYPE": "0", + "INTF_UINTR": "9", + "PERI_SPI_0": "1'b1", + "PERI_SPI_1": "1'b0", + "PERI_SPI_2": "1'b0", + "PERI_I2C_0": "1'b1", + "PERI_I2C_1": "1'b0", + "PERI_I2C_2": "1'b0", + "PERI_GPIO_0": "1'b1", + "PERI_GPIO_1": "1'b0", + "PERI_WDT_0": "1'b1", + "PERI_APB_0": "1'b1", + "PERI_APB_1": "1'b0", + "PERI_APB_2": "1'b0", + "PERI_APB_3": "1'b0", + "PERI_APB_4": "1'b0", + "PERI_GEN": "1'b1", + "PERI_UART_0": "1'b1", + "PERI_UART_1": "1'b0", + "PERI_UART_2": "1'b0", + "PERI_GPIO_0_WIDTH": "4", + "PERI_GPIO_1_WIDTH": "4", + "PERI_APB_0_SIZE": "65536", + "PERI_APB_1_SIZE": "4096", + "PERI_APB_2_SIZE": "4096", + "PERI_APB_3_SIZE": "4096", + "PERI_APB_4_SIZE": "4096", + "PERI_FREQ": "200", + "APP_OVERWRITE": "1'b0", + "APP_OVERWRITE_PATH": "\"''\"", + "INTF_JTAG_TAP_SEL": "8", + "INTF_AXIS": "1'b1", + "PERI_PIN_ASSIGN": "1'b1", + "PLL_SOC_MEM_RESOURCE": "\"PLL_TR0\"", + "SYS_FREQ": "1000", + "SYS_FREQ_HIDDEN": "1000", + "PLL_SOC_SYS_CLKOUT3_FREQ": "\"250\"", + "PLL_SOC_SYS_CLKOUT3_PHASE": "\"0\"", + "PLL_SOC_MEM_CLKOUT3_FREQ": "\"250\"", + "PLL_SOC_MEM_CLKOUT3_PHASE": "\"0\"", + "PLL_SOC_MEM_CLKOUT4_PHASE": "\"0\"", + "PLL_SOC_SYS_RESOURCE": "\"PLL_BL0\"", + "PLL_LPDDR4_RESOURCE": "\"PLL_BL2\"", + "PLL_RES_ASSIGN": "1'b0", + "PLL_SOC_SYS_CLKOUT0_FREQ": "\"100\"", + "PLL_SOC_SYS_CLKOUT0_PHASE": "\"0\"", + "PLL_SOC_MEM_CLKOUT0_FREQ": "\"100\"", + "PLL_SOC_MEM_CLKOUT0_PHASE": "\"0\"", + "PLL_LPDDR4_CLKOUT1_FREQ": "\"33\"", + "PLL_LPDDR4_CLKOUT1_PHASE": "\"0\"", + "MEM_FREQ": "250", + "AXIM_FREQ": "250", + "CFU_FREQ": "125", + "DDR_FREQ": "800", + "PLL_RES_ASSIGN_2": "1'b0", + "DDR_RES_ASSIGN": "1'b0", + "PERI_RES_ASSIGN": "1'b0", + "PLL_SOC_SYS_EXT_CLK_SRC": "1", + "PLL_SOC_MEM_EXT_CLK_SRC": "0", + "PERI_SDHC": "1'b0", + "PERI_TSEMAC": "1'b0", + "SW_FTDI_CH_NUM": "6011", + "SW_APP_SIZE": "2044", + "SW_APP_SIZE_CUSTOM": "0", + "SW_STACK_SIZE": "8", + "SW_STACK_SIZE_CUSTOM": "0", + "SW_BOARD": "\"Ti375C529 Development Kit\"", + "SW_BOARD_CUSTOM": "\"\"", + "SW_FTDI_TARGET_CH": "1", + "SW_FTDI_CH_NUM_SOFT": "6011", + "SW_FTDI_TARGET_CH_SOFT": "0", + "SW_FRTOS_APP_SIZE": "16380", + "SW_FRTOS_APP_SIZE_CUSTOM": "0", + "SW_FRTOS_STACK_SIZE": "4", + "SW_FRTOS_STACK_SIZE_CUSTOM": "0", + "PACKAGE_TYPE": "\"529\"", + "FAMILY_TYPE": "\"TITANIUM\"", + "AXI_PIPELINE": "1'b0", + "AXI_WRITE_BUFFER": "1'b0" + }, + "output": { + "external_script_Peripheral_Generator": [], + "external_source_source": [ + "EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.vhd", + "EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.v", + "EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb.v", + "EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_define.vh" + ], + "external_script_PT_Configuration": [], + "external_script_Peripheral_Post_Script": [], + "external_script_Embedded_SW": [] + }, + "ooc_synthesis": {}, + "sw_version": "2025.2.272", + "generated_date": "2025-10-16T10:03:46.765007+00:00" +} \ No newline at end of file diff --git a/fpga/ip/EfxSapphireHpSoc_slb/source/Axi4PeripheralTop.v b/fpga/ip/EfxSapphireHpSoc_slb/source/Axi4PeripheralTop.v new file mode 100644 index 0000000..369dad0 --- /dev/null +++ b/fpga/ip/EfxSapphireHpSoc_slb/source/Axi4PeripheralTop.v @@ -0,0 +1,8070 @@ +// Generator : SpinalHDL dev git head : a69f4b9a329be784802c37cd8038b7dc9aec3094 +// Component : Axi4PeripheralTop +// Git hash : 176b956330f07bda5e095857b387c403a78f8448 + +`timescale 1ns/1ps + +module Axi4PeripheralTop ( + input wire axi_awvalid, + output wire axi_awready, + input wire [23:0] axi_awaddr, + input wire [7:0] axi_awlen, + input wire [2:0] axi_awsize, + input wire [3:0] axi_awcache, + input wire [2:0] axi_awprot, + input wire axi_wvalid, + output wire axi_wready, + input wire [31:0] axi_wdata, + input wire [3:0] axi_wstrb, + input wire axi_wlast, + output wire axi_bvalid, + input wire axi_bready, + output wire [1:0] axi_bresp, + input wire axi_arvalid, + output wire axi_arready, + input wire [23:0] axi_araddr, + input wire [7:0] axi_arlen, + input wire [2:0] axi_arsize, + input wire [3:0] axi_arcache, + input wire [2:0] axi_arprot, + output wire axi_rvalid, + input wire axi_rready, + output wire [31:0] axi_rdata, + output wire [1:0] axi_rresp, + output wire axi_rlast, + output wire system_uart_0_io_txd, + input wire system_uart_0_io_rxd, + output wire system_i2c_0_io_sda_write, + input wire system_i2c_0_io_sda_read, + output wire system_i2c_0_io_scl_write, + input wire system_i2c_0_io_scl_read, + input wire [3:0] system_gpio_0_io_read, + output wire [3:0] system_gpio_0_io_write, + output wire [3:0] system_gpio_0_io_writeEnable, + output wire [15:0] io_apbSlave_0_PADDR, + output wire [0:0] io_apbSlave_0_PSEL, + output wire io_apbSlave_0_PENABLE, + input wire io_apbSlave_0_PREADY, + output wire io_apbSlave_0_PWRITE, + output wire [31:0] io_apbSlave_0_PWDATA, + input wire [31:0] io_apbSlave_0_PRDATA, + input wire io_apbSlave_0_PSLVERROR, + output wire system_uart_0_io_interrupt, + output wire system_spi_0_io_interrupt, + output wire [0:0] system_spi_0_io_sclk_write, + output wire system_spi_0_io_data_0_writeEnable, + input wire [0:0] system_spi_0_io_data_0_read, + output wire [0:0] system_spi_0_io_data_0_write, + output wire system_spi_0_io_data_1_writeEnable, + input wire [0:0] system_spi_0_io_data_1_read, + output wire [0:0] system_spi_0_io_data_1_write, + output wire system_spi_0_io_data_2_writeEnable, + input wire [0:0] system_spi_0_io_data_2_read, + output wire [0:0] system_spi_0_io_data_2_write, + output wire system_spi_0_io_data_3_writeEnable, + input wire [0:0] system_spi_0_io_data_3_read, + output wire [0:0] system_spi_0_io_data_3_write, + output wire [3:0] system_spi_0_io_ss, + output wire system_i2c_0_io_interrupt, + output wire system_gpio_0_io_interrupts_0, + output wire system_gpio_0_io_interrupts_1, + output wire system_watchdog_logic_panics_0, + output wire system_watchdog_hardPanic_reset, + input wire clk, + input wire reset +); + + wire streamArbiter_io_inputs_0_ready; + wire streamArbiter_io_inputs_1_ready; + wire streamArbiter_io_output_valid; + wire [23:0] streamArbiter_io_output_payload_addr; + wire [7:0] streamArbiter_io_output_payload_len; + wire [2:0] streamArbiter_io_output_payload_size; + wire [3:0] streamArbiter_io_output_payload_cache; + wire [2:0] streamArbiter_io_output_payload_prot; + wire [0:0] streamArbiter_io_chosen; + wire [1:0] streamArbiter_io_chosenOH; + wire axiToBmb_io_axi_arw_ready; + wire axiToBmb_io_axi_w_ready; + wire axiToBmb_io_axi_b_valid; + wire [1:0] axiToBmb_io_axi_b_payload_resp; + wire axiToBmb_io_axi_r_valid; + wire [31:0] axiToBmb_io_axi_r_payload_data; + wire [1:0] axiToBmb_io_axi_r_payload_resp; + wire axiToBmb_io_axi_r_payload_last; + wire axiToBmb_io_bmb_cmd_valid; + wire axiToBmb_io_bmb_cmd_payload_last; + wire [0:0] axiToBmb_io_bmb_cmd_payload_fragment_source; + wire [0:0] axiToBmb_io_bmb_cmd_payload_fragment_opcode; + wire [23:0] axiToBmb_io_bmb_cmd_payload_fragment_address; + wire [9:0] axiToBmb_io_bmb_cmd_payload_fragment_length; + wire [31:0] axiToBmb_io_bmb_cmd_payload_fragment_data; + wire [3:0] axiToBmb_io_bmb_cmd_payload_fragment_mask; + wire axiToBmb_io_bmb_rsp_ready; + wire bmbHandle_decoder_io_input_cmd_ready; + wire bmbHandle_decoder_io_input_rsp_valid; + wire bmbHandle_decoder_io_input_rsp_payload_last; + wire [0:0] bmbHandle_decoder_io_input_rsp_payload_fragment_source; + wire [0:0] bmbHandle_decoder_io_input_rsp_payload_fragment_opcode; + wire [31:0] bmbHandle_decoder_io_input_rsp_payload_fragment_data; + wire bmbHandle_decoder_io_outputs_0_cmd_valid; + wire bmbHandle_decoder_io_outputs_0_cmd_payload_last; + wire [0:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_source; + wire [0:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_opcode; + wire [23:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_address; + wire [9:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_length; + wire [31:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_data; + wire [3:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_mask; + wire bmbHandle_decoder_io_outputs_0_rsp_ready; + wire bmbHandle_unburstify_io_input_cmd_ready; + wire bmbHandle_unburstify_io_input_rsp_valid; + wire bmbHandle_unburstify_io_input_rsp_payload_last; + wire [0:0] bmbHandle_unburstify_io_input_rsp_payload_fragment_source; + wire [0:0] bmbHandle_unburstify_io_input_rsp_payload_fragment_opcode; + wire [31:0] bmbHandle_unburstify_io_input_rsp_payload_fragment_data; + wire bmbHandle_unburstify_io_output_cmd_valid; + wire bmbHandle_unburstify_io_output_cmd_payload_last; + wire [0:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_opcode; + wire [23:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_address; + wire [1:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_length; + wire [31:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_data; + wire [3:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_mask; + wire [2:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_context; + wire bmbHandle_unburstify_io_output_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_input_cmd_ready; + wire bmbPeripheral_bmb_decoder_io_input_rsp_valid; + wire bmbPeripheral_bmb_decoder_io_input_rsp_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode; + wire [31:0] bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data; + wire [2:0] bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_outputs_5_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_5_rsp_ready; + wire system_uart_0_io_logic_io_bus_cmd_ready; + wire system_uart_0_io_logic_io_bus_rsp_valid; + wire system_uart_0_io_logic_io_bus_rsp_payload_last; + wire [0:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode; + wire [31:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_data; + wire [2:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_context; + wire system_uart_0_io_logic_io_uart_txd; + wire system_uart_0_io_logic_system_uart_0_io_interrupt_source; + wire system_spi_0_io_logic_io_ctrl_cmd_ready; + wire system_spi_0_io_logic_io_ctrl_rsp_valid; + wire system_spi_0_io_logic_io_ctrl_rsp_payload_last; + wire [0:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; + wire [31:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data; + wire [2:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context; + wire [0:0] system_spi_0_io_logic_io_spi_sclk_write; + wire [3:0] system_spi_0_io_logic_io_spi_ss; + wire [0:0] system_spi_0_io_logic_io_spi_data_0_write; + wire system_spi_0_io_logic_io_spi_data_0_writeEnable; + wire [0:0] system_spi_0_io_logic_io_spi_data_1_write; + wire system_spi_0_io_logic_io_spi_data_1_writeEnable; + wire [0:0] system_spi_0_io_logic_io_spi_data_2_write; + wire system_spi_0_io_logic_io_spi_data_2_writeEnable; + wire [0:0] system_spi_0_io_logic_io_spi_data_3_write; + wire system_spi_0_io_logic_io_spi_data_3_writeEnable; + wire system_spi_0_io_logic_system_spi_0_io_interrupt_source; + wire system_i2c_0_io_logic_io_ctrl_cmd_ready; + wire system_i2c_0_io_logic_io_ctrl_rsp_valid; + wire system_i2c_0_io_logic_io_ctrl_rsp_payload_last; + wire [0:0] system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; + wire [31:0] system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_data; + wire [2:0] system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_context; + wire system_i2c_0_io_logic_io_i2c_scl_write; + wire system_i2c_0_io_logic_io_i2c_sda_write; + wire system_i2c_0_io_logic_system_i2c_0_io_interrupt_source; + wire [3:0] system_gpio_0_io_logic_io_gpio_write; + wire [3:0] system_gpio_0_io_logic_io_gpio_writeEnable; + wire system_gpio_0_io_logic_io_bus_cmd_ready; + wire system_gpio_0_io_logic_io_bus_rsp_valid; + wire system_gpio_0_io_logic_io_bus_rsp_payload_last; + wire [0:0] system_gpio_0_io_logic_io_bus_rsp_payload_fragment_opcode; + wire [31:0] system_gpio_0_io_logic_io_bus_rsp_payload_fragment_data; + wire [2:0] system_gpio_0_io_logic_io_bus_rsp_payload_fragment_context; + wire [3:0] system_gpio_0_io_logic_io_interrupt; + wire system_watchdog_logic_logic_io_bus_cmd_ready; + wire system_watchdog_logic_logic_io_bus_rsp_valid; + wire system_watchdog_logic_logic_io_bus_rsp_payload_last; + wire [0:0] system_watchdog_logic_logic_io_bus_rsp_payload_fragment_opcode; + wire [31:0] system_watchdog_logic_logic_io_bus_rsp_payload_fragment_data; + wire [2:0] system_watchdog_logic_logic_io_bus_rsp_payload_fragment_context; + wire [1:0] system_watchdog_logic_logic_io_panics; + wire io_apbSlave_0_logic_io_input_cmd_ready; + wire io_apbSlave_0_logic_io_input_rsp_valid; + wire io_apbSlave_0_logic_io_input_rsp_payload_last; + wire [0:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode; + wire [31:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_data; + wire [2:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_context; + wire [15:0] io_apbSlave_0_logic_io_output_PADDR; + wire [0:0] io_apbSlave_0_logic_io_output_PSEL; + wire io_apbSlave_0_logic_io_output_PENABLE; + wire io_apbSlave_0_logic_io_output_PWRITE; + wire [31:0] io_apbSlave_0_logic_io_output_PWDATA; + wire _zz_axiShared_b_ready; + wire _zz_axiShared_r_ready; + wire axi_aw_halfPipe_valid; + wire axi_aw_halfPipe_ready; + wire [23:0] axi_aw_halfPipe_payload_addr; + wire [7:0] axi_aw_halfPipe_payload_len; + wire [2:0] axi_aw_halfPipe_payload_size; + wire [3:0] axi_aw_halfPipe_payload_cache; + wire [2:0] axi_aw_halfPipe_payload_prot; + reg axi_aw_rValid; + wire axi_aw_halfPipe_fire; + reg [23:0] axi_aw_rData_addr; + reg [7:0] axi_aw_rData_len; + reg [2:0] axi_aw_rData_size; + reg [3:0] axi_aw_rData_cache; + reg [2:0] axi_aw_rData_prot; + wire axi_w_halfPipe_valid; + wire axi_w_halfPipe_ready; + wire [31:0] axi_w_halfPipe_payload_data; + wire [3:0] axi_w_halfPipe_payload_strb; + wire axi_w_halfPipe_payload_last; + reg axi_w_rValid; + wire axi_w_halfPipe_fire; + reg [31:0] axi_w_rData_data; + reg [3:0] axi_w_rData_strb; + reg axi_w_rData_last; + wire _zz_axi_bvalid; + reg _zz_axi_bvalid_1; + reg [1:0] _zz_axi_bresp; + wire axi_ar_halfPipe_valid; + wire axi_ar_halfPipe_ready; + wire [23:0] axi_ar_halfPipe_payload_addr; + wire [7:0] axi_ar_halfPipe_payload_len; + wire [2:0] axi_ar_halfPipe_payload_size; + wire [3:0] axi_ar_halfPipe_payload_cache; + wire [2:0] axi_ar_halfPipe_payload_prot; + reg axi_ar_rValid; + wire axi_ar_halfPipe_fire; + reg [23:0] axi_ar_rData_addr; + reg [7:0] axi_ar_rData_len; + reg [2:0] axi_ar_rData_size; + reg [3:0] axi_ar_rData_cache; + reg [2:0] axi_ar_rData_prot; + wire _zz_axi_rvalid; + reg _zz_axi_rvalid_1; + reg [31:0] _zz_axi_rdata; + reg [1:0] _zz_axi_rresp; + reg _zz_axi_rlast; + wire axiShared_arw_valid; + wire axiShared_arw_ready; + wire [23:0] axiShared_arw_payload_addr; + wire [7:0] axiShared_arw_payload_len; + wire [2:0] axiShared_arw_payload_size; + wire [3:0] axiShared_arw_payload_cache; + wire [2:0] axiShared_arw_payload_prot; + wire axiShared_arw_payload_write; + wire axiShared_w_valid; + wire axiShared_w_ready; + wire [31:0] axiShared_w_payload_data; + wire [3:0] axiShared_w_payload_strb; + wire axiShared_w_payload_last; + wire axiShared_b_valid; + wire axiShared_b_ready; + wire [1:0] axiShared_b_payload_resp; + wire axiShared_r_valid; + wire axiShared_r_ready; + wire [31:0] axiShared_r_payload_data; + wire [1:0] axiShared_r_payload_resp; + wire axiShared_r_payload_last; + wire bmbPeripheral_bmb_cmd_valid; + wire bmbPeripheral_bmb_cmd_ready; + wire bmbPeripheral_bmb_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_rsp_valid; + wire bmbPeripheral_bmb_rsp_ready; + wire bmbPeripheral_bmb_rsp_payload_last; + wire [0:0] bmbPeripheral_bmb_rsp_payload_fragment_opcode; + wire [31:0] bmbPeripheral_bmb_rsp_payload_fragment_data; + wire [2:0] bmbPeripheral_bmb_rsp_payload_fragment_context; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_gpio_0_io_interrupts_0_source; + wire system_gpio_0_io_interrupts_1_source; + wire system_gpio_0_io_interrupts_2; + wire system_gpio_0_io_interrupts_3; + wire system_watchdog_logic_panics_0_source; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire _zz_io_bus_rsp_ready; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last; + wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode; + wire [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address; + wire [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length; + wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data; + wire [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context; + reg system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire; + reg system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + reg [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + reg [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + reg [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + reg [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + reg [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + wire _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + reg _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + reg _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + reg [0:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + reg [31:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + reg [2:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last; + wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode; + wire [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address; + wire [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length; + wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data; + wire [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context; + reg system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire; + reg system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + reg [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + reg [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + reg [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + reg [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + reg [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [7:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last; + wire [0:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode; + wire [7:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address; + wire [1:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length; + wire [31:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data; + wire [2:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context; + reg system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire; + reg system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + reg [0:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + reg [7:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + reg [1:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + reg [31:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + reg [2:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [7:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [7:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [15:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire bmbPeripheral_bmb_withoutMask_cmd_valid; + wire bmbPeripheral_bmb_withoutMask_cmd_ready; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_withoutMask_rsp_valid; + wire bmbPeripheral_bmb_withoutMask_rsp_ready; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context; + wire bmbPeripheral_bmb_withoutMask_cmd_valid_1; + wire bmbPeripheral_bmb_withoutMask_cmd_ready_1; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_1; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1; + wire bmbPeripheral_bmb_withoutMask_rsp_valid_1; + wire bmbPeripheral_bmb_withoutMask_rsp_ready_1; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_1; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1; + wire bmbPeripheral_bmb_withoutMask_cmd_valid_2; + wire bmbPeripheral_bmb_withoutMask_cmd_ready_2; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_2; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2; + wire bmbPeripheral_bmb_withoutMask_rsp_valid_2; + wire bmbPeripheral_bmb_withoutMask_rsp_ready_2; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_2; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2; + wire bmbPeripheral_bmb_withoutMask_cmd_valid_3; + wire bmbPeripheral_bmb_withoutMask_cmd_ready_3; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_3; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3; + wire bmbPeripheral_bmb_withoutMask_rsp_valid_3; + wire bmbPeripheral_bmb_withoutMask_rsp_ready_3; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_3; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3; + wire bmbPeripheral_bmb_withoutMask_cmd_valid_4; + wire bmbPeripheral_bmb_withoutMask_cmd_ready_4; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_4; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4; + wire bmbPeripheral_bmb_withoutMask_rsp_valid_4; + wire bmbPeripheral_bmb_withoutMask_rsp_ready_4; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_4; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4; + wire bmbPeripheral_bmb_withoutMask_cmd_valid_5; + wire bmbPeripheral_bmb_withoutMask_cmd_ready_5; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_5; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_5; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_5; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_5; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_5; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_5; + wire bmbPeripheral_bmb_withoutMask_rsp_valid_5; + wire bmbPeripheral_bmb_withoutMask_rsp_ready_5; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_5; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_5; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_5; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_5; + + Axi4PeripheralStreamArbiter streamArbiter ( + .io_inputs_0_valid (axi_ar_halfPipe_valid ), //i + .io_inputs_0_ready (streamArbiter_io_inputs_0_ready ), //o + .io_inputs_0_payload_addr (axi_ar_halfPipe_payload_addr[23:0] ), //i + .io_inputs_0_payload_len (axi_ar_halfPipe_payload_len[7:0] ), //i + .io_inputs_0_payload_size (axi_ar_halfPipe_payload_size[2:0] ), //i + .io_inputs_0_payload_cache (axi_ar_halfPipe_payload_cache[3:0] ), //i + .io_inputs_0_payload_prot (axi_ar_halfPipe_payload_prot[2:0] ), //i + .io_inputs_1_valid (axi_aw_halfPipe_valid ), //i + .io_inputs_1_ready (streamArbiter_io_inputs_1_ready ), //o + .io_inputs_1_payload_addr (axi_aw_halfPipe_payload_addr[23:0] ), //i + .io_inputs_1_payload_len (axi_aw_halfPipe_payload_len[7:0] ), //i + .io_inputs_1_payload_size (axi_aw_halfPipe_payload_size[2:0] ), //i + .io_inputs_1_payload_cache (axi_aw_halfPipe_payload_cache[3:0] ), //i + .io_inputs_1_payload_prot (axi_aw_halfPipe_payload_prot[2:0] ), //i + .io_output_valid (streamArbiter_io_output_valid ), //o + .io_output_ready (axiShared_arw_ready ), //i + .io_output_payload_addr (streamArbiter_io_output_payload_addr[23:0]), //o + .io_output_payload_len (streamArbiter_io_output_payload_len[7:0] ), //o + .io_output_payload_size (streamArbiter_io_output_payload_size[2:0] ), //o + .io_output_payload_cache (streamArbiter_io_output_payload_cache[3:0]), //o + .io_output_payload_prot (streamArbiter_io_output_payload_prot[2:0] ), //o + .io_chosen (streamArbiter_io_chosen ), //o + .io_chosenOH (streamArbiter_io_chosenOH[1:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralAxi4SharedToBmb axiToBmb ( + .io_axi_arw_valid (axiShared_arw_valid ), //i + .io_axi_arw_ready (axiToBmb_io_axi_arw_ready ), //o + .io_axi_arw_payload_addr (axiShared_arw_payload_addr[23:0] ), //i + .io_axi_arw_payload_len (axiShared_arw_payload_len[7:0] ), //i + .io_axi_arw_payload_size (axiShared_arw_payload_size[2:0] ), //i + .io_axi_arw_payload_cache (axiShared_arw_payload_cache[3:0] ), //i + .io_axi_arw_payload_prot (axiShared_arw_payload_prot[2:0] ), //i + .io_axi_arw_payload_write (axiShared_arw_payload_write ), //i + .io_axi_w_valid (axiShared_w_valid ), //i + .io_axi_w_ready (axiToBmb_io_axi_w_ready ), //o + .io_axi_w_payload_data (axiShared_w_payload_data[31:0] ), //i + .io_axi_w_payload_strb (axiShared_w_payload_strb[3:0] ), //i + .io_axi_w_payload_last (axiShared_w_payload_last ), //i + .io_axi_b_valid (axiToBmb_io_axi_b_valid ), //o + .io_axi_b_ready (axiShared_b_ready ), //i + .io_axi_b_payload_resp (axiToBmb_io_axi_b_payload_resp[1:0] ), //o + .io_axi_r_valid (axiToBmb_io_axi_r_valid ), //o + .io_axi_r_ready (axiShared_r_ready ), //i + .io_axi_r_payload_data (axiToBmb_io_axi_r_payload_data[31:0] ), //o + .io_axi_r_payload_resp (axiToBmb_io_axi_r_payload_resp[1:0] ), //o + .io_axi_r_payload_last (axiToBmb_io_axi_r_payload_last ), //o + .io_bmb_cmd_valid (axiToBmb_io_bmb_cmd_valid ), //o + .io_bmb_cmd_ready (bmbHandle_decoder_io_input_cmd_ready ), //i + .io_bmb_cmd_payload_last (axiToBmb_io_bmb_cmd_payload_last ), //o + .io_bmb_cmd_payload_fragment_source (axiToBmb_io_bmb_cmd_payload_fragment_source ), //o + .io_bmb_cmd_payload_fragment_opcode (axiToBmb_io_bmb_cmd_payload_fragment_opcode ), //o + .io_bmb_cmd_payload_fragment_address (axiToBmb_io_bmb_cmd_payload_fragment_address[23:0] ), //o + .io_bmb_cmd_payload_fragment_length (axiToBmb_io_bmb_cmd_payload_fragment_length[9:0] ), //o + .io_bmb_cmd_payload_fragment_data (axiToBmb_io_bmb_cmd_payload_fragment_data[31:0] ), //o + .io_bmb_cmd_payload_fragment_mask (axiToBmb_io_bmb_cmd_payload_fragment_mask[3:0] ), //o + .io_bmb_rsp_valid (bmbHandle_decoder_io_input_rsp_valid ), //i + .io_bmb_rsp_ready (axiToBmb_io_bmb_rsp_ready ), //o + .io_bmb_rsp_payload_last (bmbHandle_decoder_io_input_rsp_payload_last ), //i + .io_bmb_rsp_payload_fragment_source (bmbHandle_decoder_io_input_rsp_payload_fragment_source ), //i + .io_bmb_rsp_payload_fragment_opcode (bmbHandle_decoder_io_input_rsp_payload_fragment_opcode ), //i + .io_bmb_rsp_payload_fragment_data (bmbHandle_decoder_io_input_rsp_payload_fragment_data[31:0]) //i + ); + Axi4PeripheralBmbDecoder bmbHandle_decoder ( + .io_input_cmd_valid (axiToBmb_io_bmb_cmd_valid ), //i + .io_input_cmd_ready (bmbHandle_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (axiToBmb_io_bmb_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (axiToBmb_io_bmb_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (axiToBmb_io_bmb_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (axiToBmb_io_bmb_cmd_payload_fragment_address[23:0] ), //i + .io_input_cmd_payload_fragment_length (axiToBmb_io_bmb_cmd_payload_fragment_length[9:0] ), //i + .io_input_cmd_payload_fragment_data (axiToBmb_io_bmb_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (axiToBmb_io_bmb_cmd_payload_fragment_mask[3:0] ), //i + .io_input_rsp_valid (bmbHandle_decoder_io_input_rsp_valid ), //o + .io_input_rsp_ready (axiToBmb_io_bmb_rsp_ready ), //i + .io_input_rsp_payload_last (bmbHandle_decoder_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (bmbHandle_decoder_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (bmbHandle_decoder_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (bmbHandle_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_valid (bmbHandle_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (bmbHandle_unburstify_io_input_cmd_ready ), //i + .io_outputs_0_cmd_payload_last (bmbHandle_decoder_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_source (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_source ), //o + .io_outputs_0_cmd_payload_fragment_opcode (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_address[23:0]), //o + .io_outputs_0_cmd_payload_fragment_length (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_length[9:0] ), //o + .io_outputs_0_cmd_payload_fragment_data (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_mask (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_0_rsp_valid (bmbHandle_unburstify_io_input_rsp_valid ), //i + .io_outputs_0_rsp_ready (bmbHandle_decoder_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (bmbHandle_unburstify_io_input_rsp_payload_last ), //i + .io_outputs_0_rsp_payload_fragment_source (bmbHandle_unburstify_io_input_rsp_payload_fragment_source ), //i + .io_outputs_0_rsp_payload_fragment_opcode (bmbHandle_unburstify_io_input_rsp_payload_fragment_opcode ), //i + .io_outputs_0_rsp_payload_fragment_data (bmbHandle_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbUnburstify bmbHandle_unburstify ( + .io_input_cmd_valid (bmbHandle_decoder_io_outputs_0_cmd_valid ), //i + .io_input_cmd_ready (bmbHandle_unburstify_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (bmbHandle_decoder_io_outputs_0_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_address[23:0] ), //i + .io_input_cmd_payload_fragment_length (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_length[9:0] ), //i + .io_input_cmd_payload_fragment_data (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //i + .io_input_rsp_valid (bmbHandle_unburstify_io_input_rsp_valid ), //o + .io_input_rsp_ready (bmbHandle_decoder_io_outputs_0_rsp_ready ), //i + .io_input_rsp_payload_last (bmbHandle_unburstify_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (bmbHandle_unburstify_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (bmbHandle_unburstify_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (bmbHandle_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_output_cmd_valid (bmbHandle_unburstify_io_output_cmd_valid ), //o + .io_output_cmd_ready (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i + .io_output_cmd_payload_last (bmbHandle_unburstify_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (bmbHandle_unburstify_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (bmbHandle_unburstify_io_output_cmd_payload_fragment_address[23:0] ), //o + .io_output_cmd_payload_fragment_length (bmbHandle_unburstify_io_output_cmd_payload_fragment_length[1:0] ), //o + .io_output_cmd_payload_fragment_data (bmbHandle_unburstify_io_output_cmd_payload_fragment_data[31:0] ), //o + .io_output_cmd_payload_fragment_mask (bmbHandle_unburstify_io_output_cmd_payload_fragment_mask[3:0] ), //o + .io_output_cmd_payload_fragment_context (bmbHandle_unburstify_io_output_cmd_payload_fragment_context[2:0] ), //o + .io_output_rsp_valid (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i + .io_output_rsp_ready (bmbHandle_unburstify_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0] ), //i + .io_output_rsp_payload_fragment_context (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context[2:0]), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbDecoder_1 bmbPeripheral_bmb_decoder ( + .io_input_cmd_valid (bmbPeripheral_bmb_cmd_valid ), //i + .io_input_cmd_ready (bmbPeripheral_bmb_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (bmbPeripheral_bmb_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (bmbPeripheral_bmb_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (bmbPeripheral_bmb_cmd_payload_fragment_address[23:0] ), //i + .io_input_cmd_payload_fragment_length (bmbPeripheral_bmb_cmd_payload_fragment_length[1:0] ), //i + .io_input_cmd_payload_fragment_data (bmbPeripheral_bmb_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (bmbPeripheral_bmb_cmd_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (bmbPeripheral_bmb_cmd_payload_fragment_context[2:0] ), //i + .io_input_rsp_valid (bmbPeripheral_bmb_decoder_io_input_rsp_valid ), //o + .io_input_rsp_ready (bmbPeripheral_bmb_rsp_ready ), //i + .io_input_rsp_payload_last (bmbPeripheral_bmb_decoder_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context[2:0] ), //o + .io_outputs_0_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready ), //i + .io_outputs_0_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[23:0]), //o + .io_outputs_0_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_0_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_0_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_0_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid ), //i + .io_outputs_0_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last ), //i + .io_outputs_0_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode ), //i + .io_outputs_0_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data[31:0] ), //i + .io_outputs_0_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context[2:0] ), //i + .io_outputs_1_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid ), //o + .io_outputs_1_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_1 ), //i + .io_outputs_1_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last ), //o + .io_outputs_1_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //o + .io_outputs_1_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[23:0]), //o + .io_outputs_1_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_1_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_1_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_1_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_1_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_1 ), //i + .io_outputs_1_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready ), //o + .io_outputs_1_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 ), //i + .io_outputs_1_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 ), //i + .io_outputs_1_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1[31:0] ), //i + .io_outputs_1_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1[2:0] ), //i + .io_outputs_2_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid ), //o + .io_outputs_2_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_2 ), //i + .io_outputs_2_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last ), //o + .io_outputs_2_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode ), //o + .io_outputs_2_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address[23:0]), //o + .io_outputs_2_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_2_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_2_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_2_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_2_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_2 ), //i + .io_outputs_2_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready ), //o + .io_outputs_2_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 ), //i + .io_outputs_2_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 ), //i + .io_outputs_2_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2[31:0] ), //i + .io_outputs_2_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2[2:0] ), //i + .io_outputs_3_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid ), //o + .io_outputs_3_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_3 ), //i + .io_outputs_3_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last ), //o + .io_outputs_3_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode ), //o + .io_outputs_3_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address[23:0]), //o + .io_outputs_3_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_3_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_3_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_3_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_3_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_3 ), //i + .io_outputs_3_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready ), //o + .io_outputs_3_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 ), //i + .io_outputs_3_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 ), //i + .io_outputs_3_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3[31:0] ), //i + .io_outputs_3_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3[2:0] ), //i + .io_outputs_4_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid ), //o + .io_outputs_4_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_4 ), //i + .io_outputs_4_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last ), //o + .io_outputs_4_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode ), //o + .io_outputs_4_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address[23:0]), //o + .io_outputs_4_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_4_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_4_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_4_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_4_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_4 ), //i + .io_outputs_4_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready ), //o + .io_outputs_4_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 ), //i + .io_outputs_4_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 ), //i + .io_outputs_4_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4[31:0] ), //i + .io_outputs_4_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4[2:0] ), //i + .io_outputs_5_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_valid ), //o + .io_outputs_5_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_5 ), //i + .io_outputs_5_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_last ), //o + .io_outputs_5_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_opcode ), //o + .io_outputs_5_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_address[23:0]), //o + .io_outputs_5_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_5_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_5_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_5_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_5_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_5 ), //i + .io_outputs_5_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_5_rsp_ready ), //o + .io_outputs_5_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_5 ), //i + .io_outputs_5_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_5 ), //i + .io_outputs_5_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_5[31:0] ), //i + .io_outputs_5_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_5[2:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbUartCtrl system_uart_0_io_logic ( + .io_bus_cmd_valid (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i + .io_bus_cmd_ready (system_uart_0_io_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[5:0]), //i + .io_bus_cmd_payload_fragment_length (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_context (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[2:0]), //i + .io_bus_rsp_valid (system_uart_0_io_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (_zz_io_bus_rsp_ready ), //i + .io_bus_rsp_payload_last (system_uart_0_io_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_uart_0_io_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_uart_0_io_logic_io_bus_rsp_payload_fragment_context[2:0] ), //o + .io_uart_txd (system_uart_0_io_logic_io_uart_txd ), //o + .io_uart_rxd (system_uart_0_io_rxd ), //i + .system_uart_0_io_interrupt_source (system_uart_0_io_logic_system_uart_0_io_interrupt_source ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbSpiXdrMasterCtrl system_spi_0_io_logic ( + .io_ctrl_cmd_valid (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i + .io_ctrl_cmd_ready (system_spi_0_io_logic_io_ctrl_cmd_ready ), //o + .io_ctrl_cmd_payload_last (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i + .io_ctrl_cmd_payload_fragment_opcode (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i + .io_ctrl_cmd_payload_fragment_address (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[11:0]), //i + .io_ctrl_cmd_payload_fragment_length (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i + .io_ctrl_cmd_payload_fragment_data (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i + .io_ctrl_cmd_payload_fragment_context (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[2:0] ), //i + .io_ctrl_rsp_valid (system_spi_0_io_logic_io_ctrl_rsp_valid ), //o + .io_ctrl_rsp_ready (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_ctrl_rsp_payload_last (system_spi_0_io_logic_io_ctrl_rsp_payload_last ), //o + .io_ctrl_rsp_payload_fragment_opcode (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode ), //o + .io_ctrl_rsp_payload_fragment_data (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data[31:0] ), //o + .io_ctrl_rsp_payload_fragment_context (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context[2:0] ), //o + .io_spi_sclk_write (system_spi_0_io_logic_io_spi_sclk_write ), //o + .io_spi_data_0_writeEnable (system_spi_0_io_logic_io_spi_data_0_writeEnable ), //o + .io_spi_data_0_read (system_spi_0_io_data_0_read ), //i + .io_spi_data_0_write (system_spi_0_io_logic_io_spi_data_0_write ), //o + .io_spi_data_1_writeEnable (system_spi_0_io_logic_io_spi_data_1_writeEnable ), //o + .io_spi_data_1_read (system_spi_0_io_data_1_read ), //i + .io_spi_data_1_write (system_spi_0_io_logic_io_spi_data_1_write ), //o + .io_spi_data_2_writeEnable (system_spi_0_io_logic_io_spi_data_2_writeEnable ), //o + .io_spi_data_2_read (system_spi_0_io_data_2_read ), //i + .io_spi_data_2_write (system_spi_0_io_logic_io_spi_data_2_write ), //o + .io_spi_data_3_writeEnable (system_spi_0_io_logic_io_spi_data_3_writeEnable ), //o + .io_spi_data_3_read (system_spi_0_io_data_3_read ), //i + .io_spi_data_3_write (system_spi_0_io_logic_io_spi_data_3_write ), //o + .io_spi_ss (system_spi_0_io_logic_io_spi_ss[3:0] ), //o + .system_spi_0_io_interrupt_source (system_spi_0_io_logic_system_spi_0_io_interrupt_source ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbI2cCtrl system_i2c_0_io_logic ( + .io_ctrl_cmd_valid (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i + .io_ctrl_cmd_ready (system_i2c_0_io_logic_io_ctrl_cmd_ready ), //o + .io_ctrl_cmd_payload_last (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i + .io_ctrl_cmd_payload_fragment_opcode (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i + .io_ctrl_cmd_payload_fragment_address (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[7:0]), //i + .io_ctrl_cmd_payload_fragment_length (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i + .io_ctrl_cmd_payload_fragment_data (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i + .io_ctrl_cmd_payload_fragment_context (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[2:0]), //i + .io_ctrl_rsp_valid (system_i2c_0_io_logic_io_ctrl_rsp_valid ), //o + .io_ctrl_rsp_ready (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_ctrl_rsp_payload_last (system_i2c_0_io_logic_io_ctrl_rsp_payload_last ), //o + .io_ctrl_rsp_payload_fragment_opcode (system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_opcode ), //o + .io_ctrl_rsp_payload_fragment_data (system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_data[31:0] ), //o + .io_ctrl_rsp_payload_fragment_context (system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_context[2:0] ), //o + .io_i2c_sda_write (system_i2c_0_io_logic_io_i2c_sda_write ), //o + .io_i2c_sda_read (system_i2c_0_io_sda_read ), //i + .io_i2c_scl_write (system_i2c_0_io_logic_io_i2c_scl_write ), //o + .io_i2c_scl_read (system_i2c_0_io_scl_read ), //i + .system_i2c_0_io_interrupt_source (system_i2c_0_io_logic_system_i2c_0_io_interrupt_source ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbGpio2 system_gpio_0_io_logic ( + .io_gpio_read (system_gpio_0_io_read[3:0] ), //i + .io_gpio_write (system_gpio_0_io_logic_io_gpio_write[3:0] ), //o + .io_gpio_writeEnable (system_gpio_0_io_logic_io_gpio_writeEnable[3:0] ), //o + .io_bus_cmd_valid (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i + .io_bus_cmd_ready (system_gpio_0_io_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[7:0]), //i + .io_bus_cmd_payload_fragment_length (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_context (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[2:0]), //i + .io_bus_rsp_valid (system_gpio_0_io_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_bus_rsp_payload_last (system_gpio_0_io_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_gpio_0_io_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_gpio_0_io_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_gpio_0_io_logic_io_bus_rsp_payload_fragment_context[2:0] ), //o + .io_interrupt (system_gpio_0_io_logic_io_interrupt[3:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbWatchdog system_watchdog_logic_logic ( + .io_bus_cmd_valid (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i + .io_bus_cmd_ready (system_watchdog_logic_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[7:0]), //i + .io_bus_cmd_payload_fragment_length (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_context (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[2:0]), //i + .io_bus_rsp_valid (system_watchdog_logic_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_bus_rsp_payload_last (system_watchdog_logic_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_watchdog_logic_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_watchdog_logic_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_watchdog_logic_logic_io_bus_rsp_payload_fragment_context[2:0] ), //o + .io_panics (system_watchdog_logic_logic_io_panics[1:0] ), //o + .io_heartBeat (1'b0 ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbToApb3Bridge io_apbSlave_0_logic ( + .io_input_cmd_valid (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i + .io_input_cmd_ready (io_apbSlave_0_logic_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[15:0]), //i + .io_input_cmd_payload_fragment_length (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i + .io_input_cmd_payload_fragment_data (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_context (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[2:0] ), //i + .io_input_rsp_valid (io_apbSlave_0_logic_io_input_rsp_valid ), //o + .io_input_rsp_ready (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_input_rsp_payload_last (io_apbSlave_0_logic_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (io_apbSlave_0_logic_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (io_apbSlave_0_logic_io_input_rsp_payload_fragment_context[2:0] ), //o + .io_output_PADDR (io_apbSlave_0_logic_io_output_PADDR[15:0] ), //o + .io_output_PSEL (io_apbSlave_0_logic_io_output_PSEL ), //o + .io_output_PENABLE (io_apbSlave_0_logic_io_output_PENABLE ), //o + .io_output_PREADY (io_apbSlave_0_PREADY ), //i + .io_output_PWRITE (io_apbSlave_0_logic_io_output_PWRITE ), //o + .io_output_PWDATA (io_apbSlave_0_logic_io_output_PWDATA[31:0] ), //o + .io_output_PRDATA (io_apbSlave_0_PRDATA[31:0] ), //i + .io_output_PSLVERROR (io_apbSlave_0_PSLVERROR ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign axi_aw_halfPipe_fire = (axi_aw_halfPipe_valid && axi_aw_halfPipe_ready); + assign axi_awready = (! axi_aw_rValid); + assign axi_aw_halfPipe_valid = axi_aw_rValid; + assign axi_aw_halfPipe_payload_addr = axi_aw_rData_addr; + assign axi_aw_halfPipe_payload_len = axi_aw_rData_len; + assign axi_aw_halfPipe_payload_size = axi_aw_rData_size; + assign axi_aw_halfPipe_payload_cache = axi_aw_rData_cache; + assign axi_aw_halfPipe_payload_prot = axi_aw_rData_prot; + assign axi_aw_halfPipe_ready = streamArbiter_io_inputs_1_ready; + assign axi_w_halfPipe_fire = (axi_w_halfPipe_valid && axi_w_halfPipe_ready); + assign axi_wready = (! axi_w_rValid); + assign axi_w_halfPipe_valid = axi_w_rValid; + assign axi_w_halfPipe_payload_data = axi_w_rData_data; + assign axi_w_halfPipe_payload_strb = axi_w_rData_strb; + assign axi_w_halfPipe_payload_last = axi_w_rData_last; + assign axi_w_halfPipe_ready = axiShared_w_ready; + assign _zz_axiShared_b_ready = (! _zz_axi_bvalid_1); + assign _zz_axi_bvalid = _zz_axi_bvalid_1; + assign axi_bvalid = _zz_axi_bvalid; + assign axi_bresp = _zz_axi_bresp; + assign axi_ar_halfPipe_fire = (axi_ar_halfPipe_valid && axi_ar_halfPipe_ready); + assign axi_arready = (! axi_ar_rValid); + assign axi_ar_halfPipe_valid = axi_ar_rValid; + assign axi_ar_halfPipe_payload_addr = axi_ar_rData_addr; + assign axi_ar_halfPipe_payload_len = axi_ar_rData_len; + assign axi_ar_halfPipe_payload_size = axi_ar_rData_size; + assign axi_ar_halfPipe_payload_cache = axi_ar_rData_cache; + assign axi_ar_halfPipe_payload_prot = axi_ar_rData_prot; + assign axi_ar_halfPipe_ready = streamArbiter_io_inputs_0_ready; + assign _zz_axiShared_r_ready = (! _zz_axi_rvalid_1); + assign _zz_axi_rvalid = _zz_axi_rvalid_1; + assign axi_rvalid = _zz_axi_rvalid; + assign axi_rdata = _zz_axi_rdata; + assign axi_rresp = _zz_axi_rresp; + assign axi_rlast = _zz_axi_rlast; + assign axiShared_arw_valid = streamArbiter_io_output_valid; + assign axiShared_arw_payload_addr = streamArbiter_io_output_payload_addr; + assign axiShared_arw_payload_len = streamArbiter_io_output_payload_len; + assign axiShared_arw_payload_size = streamArbiter_io_output_payload_size; + assign axiShared_arw_payload_cache = streamArbiter_io_output_payload_cache; + assign axiShared_arw_payload_prot = streamArbiter_io_output_payload_prot; + assign axiShared_arw_payload_write = streamArbiter_io_chosenOH[1]; + assign axiShared_w_valid = axi_w_halfPipe_valid; + assign axiShared_w_payload_data = axi_w_halfPipe_payload_data; + assign axiShared_w_payload_strb = axi_w_halfPipe_payload_strb; + assign axiShared_w_payload_last = axi_w_halfPipe_payload_last; + assign axiShared_b_ready = _zz_axiShared_b_ready; + assign axiShared_r_ready = _zz_axiShared_r_ready; + assign axiShared_arw_ready = axiToBmb_io_axi_arw_ready; + assign axiShared_w_ready = axiToBmb_io_axi_w_ready; + assign axiShared_b_valid = axiToBmb_io_axi_b_valid; + assign axiShared_b_payload_resp = axiToBmb_io_axi_b_payload_resp; + assign axiShared_r_valid = axiToBmb_io_axi_r_valid; + assign axiShared_r_payload_data = axiToBmb_io_axi_r_payload_data; + assign axiShared_r_payload_last = axiToBmb_io_axi_r_payload_last; + assign axiShared_r_payload_resp = axiToBmb_io_axi_r_payload_resp; + assign bmbPeripheral_bmb_cmd_valid = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = bmbPeripheral_bmb_cmd_ready; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = bmbPeripheral_bmb_rsp_valid; + assign bmbPeripheral_bmb_rsp_ready = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign bmbPeripheral_bmb_cmd_payload_last = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = bmbPeripheral_bmb_rsp_payload_last; + assign bmbPeripheral_bmb_cmd_payload_fragment_opcode = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_cmd_payload_fragment_address = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_cmd_payload_fragment_length = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_cmd_payload_fragment_data = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_cmd_payload_fragment_mask = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign bmbPeripheral_bmb_cmd_payload_fragment_context = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = bmbPeripheral_bmb_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = bmbPeripheral_bmb_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = bmbPeripheral_bmb_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbHandle_unburstify_io_output_cmd_valid; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbHandle_unburstify_io_output_rsp_ready; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbHandle_unburstify_io_output_cmd_payload_last; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbHandle_unburstify_io_output_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbHandle_unburstify_io_output_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbHandle_unburstify_io_output_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbHandle_unburstify_io_output_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = bmbHandle_unburstify_io_output_cmd_payload_fragment_mask; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbHandle_unburstify_io_output_cmd_payload_fragment_context; + assign bmbPeripheral_bmb_cmd_ready = bmbPeripheral_bmb_decoder_io_input_cmd_ready; + assign bmbPeripheral_bmb_rsp_valid = bmbPeripheral_bmb_decoder_io_input_rsp_valid; + assign bmbPeripheral_bmb_rsp_payload_last = bmbPeripheral_bmb_decoder_io_input_rsp_payload_last; + assign bmbPeripheral_bmb_rsp_payload_fragment_opcode = bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_rsp_payload_fragment_data = bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_rsp_payload_fragment_context = bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context; + assign system_uart_0_io_txd = system_uart_0_io_logic_io_uart_txd; + assign system_i2c_0_io_sda_write = system_i2c_0_io_logic_io_i2c_sda_write; + assign system_i2c_0_io_scl_write = system_i2c_0_io_logic_io_i2c_scl_write; + assign system_gpio_0_io_write = system_gpio_0_io_logic_io_gpio_write; + assign system_gpio_0_io_writeEnable = system_gpio_0_io_logic_io_gpio_writeEnable; + assign system_gpio_0_io_interrupts_0_source = system_gpio_0_io_logic_io_interrupt[0]; + assign system_gpio_0_io_interrupts_1_source = system_gpio_0_io_logic_io_interrupt[1]; + assign system_gpio_0_io_interrupts_2 = system_gpio_0_io_logic_io_interrupt[2]; + assign system_gpio_0_io_interrupts_3 = system_gpio_0_io_logic_io_interrupt[3]; + assign system_watchdog_logic_panics_0_source = system_watchdog_logic_logic_io_panics[0]; + assign io_apbSlave_0_PADDR = io_apbSlave_0_logic_io_output_PADDR; + assign io_apbSlave_0_PSEL = io_apbSlave_0_logic_io_output_PSEL; + assign io_apbSlave_0_PENABLE = io_apbSlave_0_logic_io_output_PENABLE; + assign io_apbSlave_0_PWRITE = io_apbSlave_0_logic_io_output_PWRITE; + assign io_apbSlave_0_PWDATA = io_apbSlave_0_logic_io_output_PWDATA; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_uart_0_io_logic_io_bus_cmd_ready; + assign _zz_io_bus_rsp_ready = (! _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1); + assign _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_uart_0_io_interrupt = system_uart_0_io_logic_system_uart_0_io_interrupt_source; + assign system_spi_0_io_interrupt = system_spi_0_io_logic_system_spi_0_io_interrupt_source; + assign system_spi_0_io_sclk_write = system_spi_0_io_logic_io_spi_sclk_write; + assign system_spi_0_io_data_0_writeEnable = system_spi_0_io_logic_io_spi_data_0_writeEnable; + assign system_spi_0_io_data_0_write = system_spi_0_io_logic_io_spi_data_0_write; + assign system_spi_0_io_data_1_writeEnable = system_spi_0_io_logic_io_spi_data_1_writeEnable; + assign system_spi_0_io_data_1_write = system_spi_0_io_logic_io_spi_data_1_write; + assign system_spi_0_io_data_2_writeEnable = system_spi_0_io_logic_io_spi_data_2_writeEnable; + assign system_spi_0_io_data_2_write = system_spi_0_io_logic_io_spi_data_2_write; + assign system_spi_0_io_data_3_writeEnable = system_spi_0_io_logic_io_spi_data_3_writeEnable; + assign system_spi_0_io_data_3_write = system_spi_0_io_logic_io_spi_data_3_write; + assign system_spi_0_io_ss = system_spi_0_io_logic_io_spi_ss; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_spi_0_io_logic_io_ctrl_cmd_ready; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_spi_0_io_logic_io_ctrl_rsp_valid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_spi_0_io_logic_io_ctrl_rsp_payload_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_i2c_0_io_logic_io_ctrl_cmd_ready; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_i2c_0_io_logic_io_ctrl_rsp_valid; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_i2c_0_io_logic_io_ctrl_rsp_payload_last; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_data; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_context; + assign system_i2c_0_io_interrupt = system_i2c_0_io_logic_system_i2c_0_io_interrupt_source; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_gpio_0_io_logic_io_bus_cmd_ready; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_gpio_0_io_logic_io_bus_rsp_valid; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_gpio_0_io_logic_io_bus_rsp_payload_last; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_gpio_0_io_logic_io_bus_rsp_payload_fragment_opcode; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_gpio_0_io_logic_io_bus_rsp_payload_fragment_data; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_gpio_0_io_logic_io_bus_rsp_payload_fragment_context; + assign system_gpio_0_io_interrupts_0 = system_gpio_0_io_interrupts_0_source; + assign system_gpio_0_io_interrupts_1 = system_gpio_0_io_interrupts_1_source; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_watchdog_logic_logic_io_bus_cmd_ready; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_watchdog_logic_logic_io_bus_rsp_valid; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_watchdog_logic_logic_io_bus_rsp_payload_last; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_watchdog_logic_logic_io_bus_rsp_payload_fragment_opcode; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_watchdog_logic_logic_io_bus_rsp_payload_fragment_data; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_watchdog_logic_logic_io_bus_rsp_payload_fragment_context; + assign system_watchdog_logic_panics_0 = system_watchdog_logic_panics_0_source; + assign system_watchdog_hardPanic_reset = system_watchdog_logic_logic_io_panics[1]; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = io_apbSlave_0_logic_io_input_cmd_ready; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = io_apbSlave_0_logic_io_input_rsp_valid; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = io_apbSlave_0_logic_io_input_rsp_payload_last; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = io_apbSlave_0_logic_io_input_rsp_payload_fragment_data; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = io_apbSlave_0_logic_io_input_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready = bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_cmd_ready = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address[5:0]; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready_1 = bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_1; + assign bmbPeripheral_bmb_withoutMask_cmd_ready_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_1; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_1; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1[11:0]; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready_2 = bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_2; + assign bmbPeripheral_bmb_withoutMask_cmd_ready_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_2; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_2; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2[7:0]; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready_3 = bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_3; + assign bmbPeripheral_bmb_withoutMask_cmd_ready_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_3; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_3; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3[7:0]; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready_4 = bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_4; + assign bmbPeripheral_bmb_withoutMask_cmd_ready_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_4; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_4; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4[7:0]; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready_5 = bmbPeripheral_bmb_decoder_io_outputs_5_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_context; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_5; + assign bmbPeripheral_bmb_withoutMask_cmd_ready_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_5; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_5; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_5; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_5[15:0]; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_5; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_5; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_5; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + always @(posedge clk) begin + if(reset) begin + axi_aw_rValid <= 1'b0; + axi_w_rValid <= 1'b0; + _zz_axi_bvalid_1 <= 1'b0; + axi_ar_rValid <= 1'b0; + _zz_axi_rvalid_1 <= 1'b0; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end else begin + if(axi_awvalid) begin + axi_aw_rValid <= 1'b1; + end + if(axi_aw_halfPipe_fire) begin + axi_aw_rValid <= 1'b0; + end + if(axi_wvalid) begin + axi_w_rValid <= 1'b1; + end + if(axi_w_halfPipe_fire) begin + axi_w_rValid <= 1'b0; + end + if(axiShared_b_valid) begin + _zz_axi_bvalid_1 <= 1'b1; + end + if((_zz_axi_bvalid && axi_bready)) begin + _zz_axi_bvalid_1 <= 1'b0; + end + if(axi_arvalid) begin + axi_ar_rValid <= 1'b1; + end + if(axi_ar_halfPipe_fire) begin + axi_ar_rValid <= 1'b0; + end + if(axiShared_r_valid) begin + _zz_axi_rvalid_1 <= 1'b1; + end + if((_zz_axi_rvalid && axi_rready)) begin + _zz_axi_rvalid_1 <= 1'b0; + end + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + if(system_uart_0_io_logic_io_bus_rsp_valid) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b1; + end + if((_zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready)) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + if(system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + end + end + + always @(posedge clk) begin + if(axi_awready) begin + axi_aw_rData_addr <= axi_awaddr; + axi_aw_rData_len <= axi_awlen; + axi_aw_rData_size <= axi_awsize; + axi_aw_rData_cache <= axi_awcache; + axi_aw_rData_prot <= axi_awprot; + end + if(axi_wready) begin + axi_w_rData_data <= axi_wdata; + axi_w_rData_strb <= axi_wstrb; + axi_w_rData_last <= axi_wlast; + end + if(_zz_axiShared_b_ready) begin + _zz_axi_bresp <= axiShared_b_payload_resp; + end + if(axi_arready) begin + axi_ar_rData_addr <= axi_araddr; + axi_ar_rData_len <= axi_arlen; + axi_ar_rData_size <= axi_arsize; + axi_ar_rData_cache <= axi_arcache; + axi_ar_rData_prot <= axi_arprot; + end + if(_zz_axiShared_r_ready) begin + _zz_axi_rdata <= axiShared_r_payload_data; + _zz_axi_rresp <= axiShared_r_payload_resp; + _zz_axi_rlast <= axiShared_r_payload_last; + end + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + if(_zz_io_bus_rsp_ready) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_uart_0_io_logic_io_bus_rsp_payload_last; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_data; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_context; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + if(system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + end + + +endmodule + +module Axi4PeripheralBmbToApb3Bridge ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [15:0] io_input_cmd_payload_fragment_address, + input wire [1:0] io_input_cmd_payload_fragment_length, + input wire [31:0] io_input_cmd_payload_fragment_data, + input wire [2:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [31:0] io_input_rsp_payload_fragment_data, + output wire [2:0] io_input_rsp_payload_fragment_context, + output wire [15:0] io_output_PADDR, + output wire [0:0] io_output_PSEL, + output wire io_output_PENABLE, + input wire io_output_PREADY, + output wire io_output_PWRITE, + output wire [31:0] io_output_PWDATA, + input wire [31:0] io_output_PRDATA, + input wire io_output_PSLVERROR, + input wire clk, + input wire reset +); + + wire bmbBuffer_cmd_valid; + reg bmbBuffer_cmd_ready; + wire bmbBuffer_cmd_payload_last; + wire [0:0] bmbBuffer_cmd_payload_fragment_opcode; + wire [15:0] bmbBuffer_cmd_payload_fragment_address; + wire [1:0] bmbBuffer_cmd_payload_fragment_length; + wire [31:0] bmbBuffer_cmd_payload_fragment_data; + wire [2:0] bmbBuffer_cmd_payload_fragment_context; + reg bmbBuffer_rsp_valid; + reg bmbBuffer_rsp_ready; + wire bmbBuffer_rsp_payload_last; + reg [0:0] bmbBuffer_rsp_payload_fragment_opcode; + wire [31:0] bmbBuffer_rsp_payload_fragment_data; + wire [2:0] bmbBuffer_rsp_payload_fragment_context; + wire io_input_rsp_isStall; + wire _zz_io_input_cmd_ready; + wire bmbBuffer_rsp_m2sPipe_valid; + wire bmbBuffer_rsp_m2sPipe_ready; + wire bmbBuffer_rsp_m2sPipe_payload_last; + wire [0:0] bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; + wire [31:0] bmbBuffer_rsp_m2sPipe_payload_fragment_data; + wire [2:0] bmbBuffer_rsp_m2sPipe_payload_fragment_context; + reg bmbBuffer_rsp_rValid; + reg bmbBuffer_rsp_rData_last; + reg [0:0] bmbBuffer_rsp_rData_fragment_opcode; + reg [31:0] bmbBuffer_rsp_rData_fragment_data; + reg [2:0] bmbBuffer_rsp_rData_fragment_context; + wire when_Stream_l375; + reg state; + wire when_BmbToApb3Bridge_l46; + + assign io_input_rsp_isStall = (io_input_rsp_valid && (! io_input_rsp_ready)); + assign _zz_io_input_cmd_ready = (! io_input_rsp_isStall); + assign io_input_cmd_ready = (bmbBuffer_cmd_ready && _zz_io_input_cmd_ready); + assign bmbBuffer_cmd_valid = (io_input_cmd_valid && _zz_io_input_cmd_ready); + assign bmbBuffer_cmd_payload_last = io_input_cmd_payload_last; + assign bmbBuffer_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign bmbBuffer_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign bmbBuffer_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign bmbBuffer_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign bmbBuffer_cmd_payload_fragment_context = io_input_cmd_payload_fragment_context; + always @(*) begin + bmbBuffer_rsp_ready = bmbBuffer_rsp_m2sPipe_ready; + if(when_Stream_l375) begin + bmbBuffer_rsp_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! bmbBuffer_rsp_m2sPipe_valid); + assign bmbBuffer_rsp_m2sPipe_valid = bmbBuffer_rsp_rValid; + assign bmbBuffer_rsp_m2sPipe_payload_last = bmbBuffer_rsp_rData_last; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_opcode = bmbBuffer_rsp_rData_fragment_opcode; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_data = bmbBuffer_rsp_rData_fragment_data; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_context = bmbBuffer_rsp_rData_fragment_context; + assign io_input_rsp_valid = bmbBuffer_rsp_m2sPipe_valid; + assign bmbBuffer_rsp_m2sPipe_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = bmbBuffer_rsp_m2sPipe_payload_last; + assign io_input_rsp_payload_fragment_opcode = bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = bmbBuffer_rsp_m2sPipe_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = bmbBuffer_rsp_m2sPipe_payload_fragment_context; + always @(*) begin + bmbBuffer_cmd_ready = 1'b0; + if(!when_BmbToApb3Bridge_l46) begin + if(io_output_PREADY) begin + bmbBuffer_cmd_ready = 1'b1; + end + end + end + + assign io_output_PSEL[0] = bmbBuffer_cmd_valid; + assign io_output_PENABLE = state; + assign io_output_PWRITE = (bmbBuffer_cmd_payload_fragment_opcode == 1'b1); + assign io_output_PADDR = bmbBuffer_cmd_payload_fragment_address; + assign io_output_PWDATA = bmbBuffer_cmd_payload_fragment_data; + always @(*) begin + bmbBuffer_rsp_valid = 1'b0; + if(!when_BmbToApb3Bridge_l46) begin + if(io_output_PREADY) begin + bmbBuffer_rsp_valid = 1'b1; + end + end + end + + assign bmbBuffer_rsp_payload_fragment_data = io_output_PRDATA; + assign when_BmbToApb3Bridge_l46 = (! state); + assign bmbBuffer_rsp_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign bmbBuffer_rsp_payload_last = 1'b1; + always @(*) begin + bmbBuffer_rsp_payload_fragment_opcode = 1'b0; + if(io_output_PSLVERROR) begin + bmbBuffer_rsp_payload_fragment_opcode = 1'b1; + end + end + + always @(posedge clk) begin + if(reset) begin + bmbBuffer_rsp_rValid <= 1'b0; + state <= 1'b0; + end else begin + if(bmbBuffer_rsp_ready) begin + bmbBuffer_rsp_rValid <= bmbBuffer_rsp_valid; + end + if(when_BmbToApb3Bridge_l46) begin + state <= bmbBuffer_cmd_valid; + end else begin + if(io_output_PREADY) begin + state <= 1'b0; + end + end + end + end + + always @(posedge clk) begin + if(bmbBuffer_rsp_ready) begin + bmbBuffer_rsp_rData_last <= bmbBuffer_rsp_payload_last; + bmbBuffer_rsp_rData_fragment_opcode <= bmbBuffer_rsp_payload_fragment_opcode; + bmbBuffer_rsp_rData_fragment_data <= bmbBuffer_rsp_payload_fragment_data; + bmbBuffer_rsp_rData_fragment_context <= bmbBuffer_rsp_payload_fragment_context; + end + end + + +endmodule + +module Axi4PeripheralBmbWatchdog ( + input wire io_bus_cmd_valid, + output wire io_bus_cmd_ready, + input wire io_bus_cmd_payload_last, + input wire [0:0] io_bus_cmd_payload_fragment_opcode, + input wire [7:0] io_bus_cmd_payload_fragment_address, + input wire [1:0] io_bus_cmd_payload_fragment_length, + input wire [31:0] io_bus_cmd_payload_fragment_data, + input wire [2:0] io_bus_cmd_payload_fragment_context, + output wire io_bus_rsp_valid, + input wire io_bus_rsp_ready, + output wire io_bus_rsp_payload_last, + output wire [0:0] io_bus_rsp_payload_fragment_opcode, + output wire [31:0] io_bus_rsp_payload_fragment_data, + output wire [2:0] io_bus_rsp_payload_fragment_context, + output wire [1:0] io_panics, + input wire io_heartBeat, + input wire clk, + input wire reset +); + + wire wd_prescaler_io_clear; + wire wd_prescaler_io_overflow; + wire wd_counters_0_timer_io_full; + wire [15:0] wd_counters_0_timer_io_value; + wire wd_counters_1_timer_io_full; + wire [15:0] wd_counters_1_timer_io_value; + reg [1:0] wd_api_enables; + reg wd_api_heartbeat; + reg [1:0] wd_api_panics; + wire wd_counters_0_clear; + reg wd_counters_0_full; + wire wd_counters_1_clear; + reg wd_counters_1_full; + wire busCtrl_readErrorFlag; + wire busCtrl_writeErrorFlag; + wire busCtrl_readHaltTrigger; + wire busCtrl_writeHaltTrigger; + wire busCtrl_rsp_valid; + wire busCtrl_rsp_ready; + wire busCtrl_rsp_payload_last; + reg [0:0] busCtrl_rsp_payload_fragment_opcode; + reg [31:0] busCtrl_rsp_payload_fragment_data; + wire [2:0] busCtrl_rsp_payload_fragment_context; + wire _zz_busCtrl_rsp_ready; + reg _zz_busCtrl_rsp_ready_1; + wire _zz_io_bus_rsp_valid; + reg _zz_io_bus_rsp_valid_1; + reg _zz_io_bus_rsp_payload_last; + reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_bus_rsp_payload_fragment_data; + reg [2:0] _zz_io_bus_rsp_payload_fragment_context; + wire when_Stream_l375; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire io_bus_cmd_fire; + wire busCtrl_doWrite; + wire busCtrl_doRead; + wire when_BmbSlaveFactory_l33; + wire when_BmbSlaveFactory_l35; + reg driver_unlocked; + reg _zz_when_Watchdog_l42; + wire when_Watchdog_l42; + reg _zz_when_Watchdog_l43; + wire when_Watchdog_l43; + reg _zz_wd_api_heartbeat; + wire [1:0] _zz_when_Watchdog_l52; + reg _zz_when_Watchdog_l50; + wire when_Watchdog_l50; + wire when_Watchdog_l52; + wire when_Watchdog_l52_1; + reg _zz_when_Watchdog_l55; + wire when_Watchdog_l55; + wire when_Watchdog_l57; + wire when_Watchdog_l57_1; + reg [23:0] _zz_io_limit; + reg [15:0] _zz_io_limit_1; + reg [15:0] _zz_io_limit_2; + + Axi4PeripheralPrescaler wd_prescaler ( + .io_clear (wd_prescaler_io_clear ), //i + .io_limit (_zz_io_limit[23:0] ), //i + .io_overflow (wd_prescaler_io_overflow), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralTimer wd_counters_0_timer ( + .io_tick (wd_prescaler_io_overflow ), //i + .io_clear (wd_counters_0_clear ), //i + .io_limit (_zz_io_limit_1[15:0] ), //i + .io_full (wd_counters_0_timer_io_full ), //o + .io_value (wd_counters_0_timer_io_value[15:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralTimer wd_counters_1_timer ( + .io_tick (wd_prescaler_io_overflow ), //i + .io_clear (wd_counters_1_clear ), //i + .io_limit (_zz_io_limit_2[15:0] ), //i + .io_full (wd_counters_1_timer_io_full ), //o + .io_value (wd_counters_1_timer_io_value[15:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + assign wd_prescaler_io_clear = (wd_api_heartbeat || (wd_api_enables == 2'b00)); + assign wd_counters_0_clear = ((! wd_api_enables[0]) || wd_api_heartbeat); + always @(*) begin + wd_api_panics[0] = wd_counters_0_full; + wd_api_panics[1] = wd_counters_1_full; + end + + assign wd_counters_1_clear = ((! wd_api_enables[1]) || wd_api_heartbeat); + assign busCtrl_readErrorFlag = 1'b0; + assign busCtrl_writeErrorFlag = 1'b0; + assign busCtrl_readHaltTrigger = 1'b0; + assign busCtrl_writeHaltTrigger = 1'b0; + assign _zz_busCtrl_rsp_ready = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); + assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready_1 && _zz_busCtrl_rsp_ready); + always @(*) begin + _zz_busCtrl_rsp_ready_1 = io_bus_rsp_ready; + if(when_Stream_l375) begin + _zz_busCtrl_rsp_ready_1 = 1'b1; + end + end + + assign when_Stream_l375 = (! _zz_io_bus_rsp_valid); + assign _zz_io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; + assign io_bus_rsp_valid = _zz_io_bus_rsp_valid; + assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; + assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; + assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; + assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; + assign busCtrl_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign busCtrl_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_doRead = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign busCtrl_rsp_valid = io_bus_cmd_valid; + assign io_bus_cmd_ready = busCtrl_rsp_ready; + assign busCtrl_rsp_payload_last = 1'b1; + assign when_BmbSlaveFactory_l33 = (busCtrl_doWrite && busCtrl_writeErrorFlag); + always @(*) begin + if(when_BmbSlaveFactory_l33) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + if(when_BmbSlaveFactory_l35) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + busCtrl_rsp_payload_fragment_opcode = 1'b0; + end + end + end + + assign when_BmbSlaveFactory_l35 = (busCtrl_doRead && busCtrl_readErrorFlag); + always @(*) begin + busCtrl_rsp_payload_fragment_data = 32'h0; + case(io_bus_cmd_payload_fragment_address) + 8'hc0 : begin + busCtrl_rsp_payload_fragment_data[15 : 0] = wd_counters_0_timer_io_value; + end + 8'hc4 : begin + busCtrl_rsp_payload_fragment_data[15 : 0] = wd_counters_1_timer_io_value; + end + default : begin + end + endcase + end + + assign busCtrl_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; + always @(*) begin + _zz_when_Watchdog_l42 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 8'h0 : begin + if(busCtrl_doWrite) begin + _zz_when_Watchdog_l42 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_Watchdog_l42 = (_zz_when_Watchdog_l42 && (io_bus_cmd_payload_fragment_data[31 : 0] == 32'h3c21b925)); + always @(*) begin + _zz_when_Watchdog_l43 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 8'h0 : begin + if(busCtrl_doWrite) begin + _zz_when_Watchdog_l43 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_Watchdog_l43 = (_zz_when_Watchdog_l43 && (io_bus_cmd_payload_fragment_data[31 : 0] == 32'h3c21b924)); + always @(*) begin + _zz_wd_api_heartbeat = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 8'h0 : begin + if(busCtrl_doWrite) begin + _zz_wd_api_heartbeat = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + wd_api_heartbeat = (_zz_wd_api_heartbeat && (io_bus_cmd_payload_fragment_data[31 : 0] == 32'had68e70d)); + if(io_heartBeat) begin + wd_api_heartbeat = 1'b1; + end + end + + always @(*) begin + _zz_when_Watchdog_l50 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 8'h04 : begin + if(busCtrl_doWrite) begin + _zz_when_Watchdog_l50 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_Watchdog_l50 = (_zz_when_Watchdog_l50 && driver_unlocked); + assign when_Watchdog_l52 = _zz_when_Watchdog_l52[0]; + assign when_Watchdog_l52_1 = _zz_when_Watchdog_l52[1]; + always @(*) begin + _zz_when_Watchdog_l55 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 8'h08 : begin + if(busCtrl_doWrite) begin + _zz_when_Watchdog_l55 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_Watchdog_l55 = (_zz_when_Watchdog_l55 && driver_unlocked); + assign when_Watchdog_l57 = _zz_when_Watchdog_l52[0]; + assign when_Watchdog_l57_1 = _zz_when_Watchdog_l52[1]; + assign io_panics = wd_api_panics; + assign _zz_when_Watchdog_l52 = io_bus_cmd_payload_fragment_data[1 : 0]; + always @(posedge clk) begin + if(reset) begin + wd_counters_0_full <= 1'b0; + wd_counters_1_full <= 1'b0; + _zz_io_bus_rsp_valid_1 <= 1'b0; + driver_unlocked <= 1'b1; + wd_api_enables <= 2'b00; + _zz_io_limit <= 24'h0; + _zz_io_limit_1 <= 16'h0; + _zz_io_limit_2 <= 16'h0; + end else begin + if(wd_counters_0_timer_io_full) begin + wd_counters_0_full <= 1'b1; + end + if(wd_counters_0_clear) begin + wd_counters_0_full <= 1'b0; + end + if(wd_counters_1_timer_io_full) begin + wd_counters_1_full <= 1'b1; + end + if(wd_counters_1_clear) begin + wd_counters_1_full <= 1'b0; + end + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_bus_rsp_valid_1 <= (busCtrl_rsp_valid && _zz_busCtrl_rsp_ready); + end + if(when_Watchdog_l42) begin + driver_unlocked <= 1'b1; + end + if(when_Watchdog_l43) begin + driver_unlocked <= 1'b0; + end + if(when_Watchdog_l50) begin + if(when_Watchdog_l52) begin + wd_api_enables[0] <= 1'b1; + end + if(when_Watchdog_l52_1) begin + wd_api_enables[1] <= 1'b1; + end + end + if(when_Watchdog_l55) begin + if(when_Watchdog_l57) begin + wd_api_enables[0] <= 1'b0; + end + if(when_Watchdog_l57_1) begin + wd_api_enables[1] <= 1'b0; + end + end + case(io_bus_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + if(driver_unlocked) begin + _zz_io_limit <= io_bus_cmd_payload_fragment_data[23 : 0]; + end + end + end + 8'h80 : begin + if(busCtrl_doWrite) begin + if(driver_unlocked) begin + _zz_io_limit_1 <= io_bus_cmd_payload_fragment_data[15 : 0]; + end + end + end + 8'h84 : begin + if(busCtrl_doWrite) begin + if(driver_unlocked) begin + _zz_io_limit_2 <= io_bus_cmd_payload_fragment_data[15 : 0]; + end + end + end + default : begin + end + endcase + end + end + + always @(posedge clk) begin + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_bus_rsp_payload_last <= busCtrl_rsp_payload_last; + _zz_io_bus_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; + _zz_io_bus_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; + _zz_io_bus_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; + end + end + + +endmodule + +module Axi4PeripheralBmbGpio2 ( + input wire [3:0] io_gpio_read, + output reg [3:0] io_gpio_write, + output reg [3:0] io_gpio_writeEnable, + input wire io_bus_cmd_valid, + output wire io_bus_cmd_ready, + input wire io_bus_cmd_payload_last, + input wire [0:0] io_bus_cmd_payload_fragment_opcode, + input wire [7:0] io_bus_cmd_payload_fragment_address, + input wire [1:0] io_bus_cmd_payload_fragment_length, + input wire [31:0] io_bus_cmd_payload_fragment_data, + input wire [2:0] io_bus_cmd_payload_fragment_context, + output wire io_bus_rsp_valid, + input wire io_bus_rsp_ready, + output wire io_bus_rsp_payload_last, + output wire [0:0] io_bus_rsp_payload_fragment_opcode, + output wire [31:0] io_bus_rsp_payload_fragment_data, + output wire [2:0] io_bus_rsp_payload_fragment_context, + output reg [3:0] io_interrupt, + input wire clk, + input wire reset +); + + wire mapper_readErrorFlag; + wire mapper_writeErrorFlag; + wire mapper_readHaltTrigger; + wire mapper_writeHaltTrigger; + wire mapper_rsp_valid; + wire mapper_rsp_ready; + wire mapper_rsp_payload_last; + reg [0:0] mapper_rsp_payload_fragment_opcode; + reg [31:0] mapper_rsp_payload_fragment_data; + wire [2:0] mapper_rsp_payload_fragment_context; + wire _zz_mapper_rsp_ready; + reg _zz_mapper_rsp_ready_1; + wire _zz_io_bus_rsp_valid; + reg _zz_io_bus_rsp_valid_1; + reg _zz_io_bus_rsp_payload_last; + reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_bus_rsp_payload_fragment_data; + reg [2:0] _zz_io_bus_rsp_payload_fragment_context; + wire when_Stream_l375; + wire mapper_askWrite; + wire mapper_askRead; + wire io_bus_cmd_fire; + wire mapper_doWrite; + wire mapper_doRead; + wire when_BmbSlaveFactory_l33; + wire when_BmbSlaveFactory_l35; + reg [3:0] io_gpio_read_delay_1; + reg [3:0] syncronized; + reg [3:0] last; + reg _zz_io_gpio_write; + reg _zz_io_gpio_writeEnable; + reg _zz_io_gpio_write_1; + reg _zz_io_gpio_writeEnable_1; + reg _zz_io_gpio_write_2; + reg _zz_io_gpio_writeEnable_2; + reg _zz_io_gpio_write_3; + reg _zz_io_gpio_writeEnable_3; + reg [3:0] interrupt_enable_high; + reg [3:0] interrupt_enable_low; + reg [3:0] interrupt_enable_rise; + reg [3:0] interrupt_enable_fall; + wire [3:0] interrupt_valid; + reg _zz_mapper_rsp_payload_fragment_data; + reg _zz_mapper_rsp_payload_fragment_data_1; + reg _zz_mapper_rsp_payload_fragment_data_2; + reg _zz_mapper_rsp_payload_fragment_data_3; + reg _zz_mapper_rsp_payload_fragment_data_4; + reg _zz_mapper_rsp_payload_fragment_data_5; + reg _zz_mapper_rsp_payload_fragment_data_6; + reg _zz_mapper_rsp_payload_fragment_data_7; + + assign mapper_readErrorFlag = 1'b0; + assign mapper_writeErrorFlag = 1'b0; + assign mapper_readHaltTrigger = 1'b0; + assign mapper_writeHaltTrigger = 1'b0; + assign _zz_mapper_rsp_ready = (! (mapper_readHaltTrigger || mapper_writeHaltTrigger)); + assign mapper_rsp_ready = (_zz_mapper_rsp_ready_1 && _zz_mapper_rsp_ready); + always @(*) begin + _zz_mapper_rsp_ready_1 = io_bus_rsp_ready; + if(when_Stream_l375) begin + _zz_mapper_rsp_ready_1 = 1'b1; + end + end + + assign when_Stream_l375 = (! _zz_io_bus_rsp_valid); + assign _zz_io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; + assign io_bus_rsp_valid = _zz_io_bus_rsp_valid; + assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; + assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; + assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; + assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; + assign mapper_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign mapper_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign mapper_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign mapper_doRead = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign mapper_rsp_valid = io_bus_cmd_valid; + assign io_bus_cmd_ready = mapper_rsp_ready; + assign mapper_rsp_payload_last = 1'b1; + assign when_BmbSlaveFactory_l33 = (mapper_doWrite && mapper_writeErrorFlag); + always @(*) begin + if(when_BmbSlaveFactory_l33) begin + mapper_rsp_payload_fragment_opcode = 1'b1; + end else begin + if(when_BmbSlaveFactory_l35) begin + mapper_rsp_payload_fragment_opcode = 1'b1; + end else begin + mapper_rsp_payload_fragment_opcode = 1'b0; + end + end + end + + assign when_BmbSlaveFactory_l35 = (mapper_doRead && mapper_readErrorFlag); + always @(*) begin + mapper_rsp_payload_fragment_data = 32'h0; + case(io_bus_cmd_payload_fragment_address) + 8'h0 : begin + mapper_rsp_payload_fragment_data[0 : 0] = syncronized[0]; + mapper_rsp_payload_fragment_data[1 : 1] = syncronized[1]; + mapper_rsp_payload_fragment_data[2 : 2] = syncronized[2]; + mapper_rsp_payload_fragment_data[3 : 3] = syncronized[3]; + end + 8'h04 : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_io_gpio_write; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_io_gpio_write_1; + mapper_rsp_payload_fragment_data[2 : 2] = _zz_io_gpio_write_2; + mapper_rsp_payload_fragment_data[3 : 3] = _zz_io_gpio_write_3; + end + 8'h08 : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_io_gpio_writeEnable; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_io_gpio_writeEnable_1; + mapper_rsp_payload_fragment_data[2 : 2] = _zz_io_gpio_writeEnable_2; + mapper_rsp_payload_fragment_data[3 : 3] = _zz_io_gpio_writeEnable_3; + end + 8'h20 : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_mapper_rsp_payload_fragment_data; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_mapper_rsp_payload_fragment_data_4; + end + 8'h24 : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_mapper_rsp_payload_fragment_data_1; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_mapper_rsp_payload_fragment_data_5; + end + 8'h28 : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_mapper_rsp_payload_fragment_data_2; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_mapper_rsp_payload_fragment_data_6; + end + 8'h2c : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_mapper_rsp_payload_fragment_data_3; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_mapper_rsp_payload_fragment_data_7; + end + default : begin + end + endcase + end + + assign mapper_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; + always @(*) begin + io_gpio_write[0] = _zz_io_gpio_write; + io_gpio_write[1] = _zz_io_gpio_write_1; + io_gpio_write[2] = _zz_io_gpio_write_2; + io_gpio_write[3] = _zz_io_gpio_write_3; + end + + always @(*) begin + io_gpio_writeEnable[0] = _zz_io_gpio_writeEnable; + io_gpio_writeEnable[1] = _zz_io_gpio_writeEnable_1; + io_gpio_writeEnable[2] = _zz_io_gpio_writeEnable_2; + io_gpio_writeEnable[3] = _zz_io_gpio_writeEnable_3; + end + + assign interrupt_valid = ((((interrupt_enable_high & syncronized) | (interrupt_enable_low & (~ syncronized))) | (interrupt_enable_rise & (syncronized & (~ last)))) | (interrupt_enable_fall & ((~ syncronized) & last))); + always @(*) begin + io_interrupt[0] = interrupt_valid[0]; + io_interrupt[1] = interrupt_valid[1]; + io_interrupt[2] = 1'b0; + io_interrupt[3] = 1'b0; + end + + always @(*) begin + interrupt_enable_rise[0] = _zz_mapper_rsp_payload_fragment_data; + interrupt_enable_rise[1] = _zz_mapper_rsp_payload_fragment_data_4; + interrupt_enable_rise[2] = 1'b0; + interrupt_enable_rise[3] = 1'b0; + end + + always @(*) begin + interrupt_enable_fall[0] = _zz_mapper_rsp_payload_fragment_data_1; + interrupt_enable_fall[1] = _zz_mapper_rsp_payload_fragment_data_5; + interrupt_enable_fall[2] = 1'b0; + interrupt_enable_fall[3] = 1'b0; + end + + always @(*) begin + interrupt_enable_high[0] = _zz_mapper_rsp_payload_fragment_data_2; + interrupt_enable_high[1] = _zz_mapper_rsp_payload_fragment_data_6; + interrupt_enable_high[2] = 1'b0; + interrupt_enable_high[3] = 1'b0; + end + + always @(*) begin + interrupt_enable_low[0] = _zz_mapper_rsp_payload_fragment_data_3; + interrupt_enable_low[1] = _zz_mapper_rsp_payload_fragment_data_7; + interrupt_enable_low[2] = 1'b0; + interrupt_enable_low[3] = 1'b0; + end + + always @(posedge clk) begin + if(reset) begin + _zz_io_bus_rsp_valid_1 <= 1'b0; + _zz_io_gpio_writeEnable <= 1'b0; + _zz_io_gpio_writeEnable_1 <= 1'b0; + _zz_io_gpio_writeEnable_2 <= 1'b0; + _zz_io_gpio_writeEnable_3 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_1 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_2 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_3 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_4 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_5 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_6 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_7 <= 1'b0; + end else begin + if(_zz_mapper_rsp_ready_1) begin + _zz_io_bus_rsp_valid_1 <= (mapper_rsp_valid && _zz_mapper_rsp_ready); + end + case(io_bus_cmd_payload_fragment_address) + 8'h08 : begin + if(mapper_doWrite) begin + _zz_io_gpio_writeEnable <= io_bus_cmd_payload_fragment_data[0]; + _zz_io_gpio_writeEnable_1 <= io_bus_cmd_payload_fragment_data[1]; + _zz_io_gpio_writeEnable_2 <= io_bus_cmd_payload_fragment_data[2]; + _zz_io_gpio_writeEnable_3 <= io_bus_cmd_payload_fragment_data[3]; + end + end + 8'h20 : begin + if(mapper_doWrite) begin + _zz_mapper_rsp_payload_fragment_data <= io_bus_cmd_payload_fragment_data[0]; + _zz_mapper_rsp_payload_fragment_data_4 <= io_bus_cmd_payload_fragment_data[1]; + end + end + 8'h24 : begin + if(mapper_doWrite) begin + _zz_mapper_rsp_payload_fragment_data_1 <= io_bus_cmd_payload_fragment_data[0]; + _zz_mapper_rsp_payload_fragment_data_5 <= io_bus_cmd_payload_fragment_data[1]; + end + end + 8'h28 : begin + if(mapper_doWrite) begin + _zz_mapper_rsp_payload_fragment_data_2 <= io_bus_cmd_payload_fragment_data[0]; + _zz_mapper_rsp_payload_fragment_data_6 <= io_bus_cmd_payload_fragment_data[1]; + end + end + 8'h2c : begin + if(mapper_doWrite) begin + _zz_mapper_rsp_payload_fragment_data_3 <= io_bus_cmd_payload_fragment_data[0]; + _zz_mapper_rsp_payload_fragment_data_7 <= io_bus_cmd_payload_fragment_data[1]; + end + end + default : begin + end + endcase + end + end + + always @(posedge clk) begin + if(_zz_mapper_rsp_ready_1) begin + _zz_io_bus_rsp_payload_last <= mapper_rsp_payload_last; + _zz_io_bus_rsp_payload_fragment_opcode <= mapper_rsp_payload_fragment_opcode; + _zz_io_bus_rsp_payload_fragment_data <= mapper_rsp_payload_fragment_data; + _zz_io_bus_rsp_payload_fragment_context <= mapper_rsp_payload_fragment_context; + end + io_gpio_read_delay_1 <= io_gpio_read; + syncronized <= io_gpio_read_delay_1; + last <= syncronized; + case(io_bus_cmd_payload_fragment_address) + 8'h04 : begin + if(mapper_doWrite) begin + _zz_io_gpio_write <= io_bus_cmd_payload_fragment_data[0]; + _zz_io_gpio_write_1 <= io_bus_cmd_payload_fragment_data[1]; + _zz_io_gpio_write_2 <= io_bus_cmd_payload_fragment_data[2]; + _zz_io_gpio_write_3 <= io_bus_cmd_payload_fragment_data[3]; + end + end + default : begin + end + endcase + end + + +endmodule + +module Axi4PeripheralBmbI2cCtrl ( + input wire io_ctrl_cmd_valid, + output wire io_ctrl_cmd_ready, + input wire io_ctrl_cmd_payload_last, + input wire [0:0] io_ctrl_cmd_payload_fragment_opcode, + input wire [7:0] io_ctrl_cmd_payload_fragment_address, + input wire [1:0] io_ctrl_cmd_payload_fragment_length, + input wire [31:0] io_ctrl_cmd_payload_fragment_data, + input wire [2:0] io_ctrl_cmd_payload_fragment_context, + output wire io_ctrl_rsp_valid, + input wire io_ctrl_rsp_ready, + output wire io_ctrl_rsp_payload_last, + output wire [0:0] io_ctrl_rsp_payload_fragment_opcode, + output wire [31:0] io_ctrl_rsp_payload_fragment_data, + output wire [2:0] io_ctrl_rsp_payload_fragment_context, + output wire io_i2c_sda_write, + input wire io_i2c_sda_read, + output wire io_i2c_scl_write, + input wire io_i2c_scl_read, + output wire system_i2c_0_io_interrupt_source, + input wire clk, + input wire reset +); + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT = 4'd0; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE = 4'd1; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 = 4'd2; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 = 4'd3; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 = 4'd4; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW = 4'd5; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH = 4'd6; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART = 4'd7; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 = 4'd8; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 = 4'd9; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 = 4'd10; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF = 4'd11; + localparam Axi4PeripheralI2cSlaveCmdMode_NONE = 3'd0; + localparam Axi4PeripheralI2cSlaveCmdMode_START = 3'd1; + localparam Axi4PeripheralI2cSlaveCmdMode_RESTART = 3'd2; + localparam Axi4PeripheralI2cSlaveCmdMode_STOP = 3'd3; + localparam Axi4PeripheralI2cSlaveCmdMode_DROP = 3'd4; + localparam Axi4PeripheralI2cSlaveCmdMode_DRIVE = 3'd5; + localparam Axi4PeripheralI2cSlaveCmdMode_READ = 3'd6; + + reg i2cCtrl_io_config_timeoutClear; + reg i2cCtrl_io_bus_rsp_valid; + reg i2cCtrl_io_bus_rsp_enable; + reg i2cCtrl_io_bus_rsp_data; + wire i2cCtrl_io_i2c_scl_write; + wire i2cCtrl_io_i2c_sda_write; + wire [2:0] i2cCtrl_io_bus_cmd_kind; + wire i2cCtrl_io_bus_cmd_data; + wire i2cCtrl_io_timeout; + wire i2cCtrl_io_internals_inFrame; + wire i2cCtrl_io_internals_sdaRead; + wire i2cCtrl_io_internals_sclRead; + wire [6:0] _zz_bridge_addressFilter_hits_0; + wire [6:0] _zz_bridge_addressFilter_hits_1; + wire [0:0] _zz_bridge_masterLogic_start; + wire [0:0] _zz_bridge_masterLogic_stop; + wire [0:0] _zz_bridge_masterLogic_drop; + wire [0:0] _zz_bridge_masterLogic_recover; + wire [11:0] _zz_bridge_masterLogic_timer_value; + wire [0:0] _zz_bridge_masterLogic_timer_value_1; + wire [0:0] _zz_bridge_masterLogic_fsm_dropped_start; + wire [0:0] _zz_bridge_masterLogic_fsm_dropped_stop; + wire [0:0] _zz_bridge_masterLogic_fsm_dropped_recover; + wire [2:0] _zz_io_bus_rsp_data; + wire [2:0] _zz_bridge_rxData_value; + wire [0:0] _zz_bridge_interruptCtrl_start_flag; + wire [0:0] _zz_bridge_interruptCtrl_restart_flag; + wire [0:0] _zz_bridge_interruptCtrl_end_flag; + wire [0:0] _zz_bridge_interruptCtrl_drop_flag; + wire [0:0] _zz_bridge_interruptCtrl_filterGen_flag; + wire [0:0] _zz_bridge_interruptCtrl_clockGenExit_flag; + wire [0:0] _zz_bridge_interruptCtrl_clockGenEnter_flag; + wire busCtrl_readErrorFlag; + wire busCtrl_writeErrorFlag; + wire busCtrl_readHaltTrigger; + wire busCtrl_writeHaltTrigger; + wire busCtrl_rsp_valid; + wire busCtrl_rsp_ready; + wire busCtrl_rsp_payload_last; + reg [0:0] busCtrl_rsp_payload_fragment_opcode; + reg [31:0] busCtrl_rsp_payload_fragment_data; + wire [2:0] busCtrl_rsp_payload_fragment_context; + wire _zz_busCtrl_rsp_ready; + reg _zz_busCtrl_rsp_ready_1; + wire _zz_io_ctrl_rsp_valid; + reg _zz_io_ctrl_rsp_valid_1; + reg _zz_io_ctrl_rsp_payload_last; + reg [0:0] _zz_io_ctrl_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_ctrl_rsp_payload_fragment_data; + reg [2:0] _zz_io_ctrl_rsp_payload_fragment_context; + wire when_Stream_l375; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire io_ctrl_cmd_fire; + wire busCtrl_doWrite; + wire busCtrl_doRead; + wire when_BmbSlaveFactory_l33; + wire when_BmbSlaveFactory_l35; + wire bridge_busCtrlWithOffset_readErrorFlag; + wire bridge_busCtrlWithOffset_writeErrorFlag; + reg bridge_frameReset; + reg bridge_i2cBuffer_sda_write; + wire bridge_i2cBuffer_sda_read; + reg bridge_i2cBuffer_scl_write; + wire bridge_i2cBuffer_scl_read; + reg bridge_rxData_event; + reg bridge_rxData_listen; + reg bridge_rxData_valid; + reg [7:0] bridge_rxData_value; + reg when_I2cCtrl_l224; + reg bridge_rxAck_listen; + reg bridge_rxAck_valid; + reg bridge_rxAck_value; + reg when_I2cCtrl_l237; + reg bridge_txData_valid; + reg bridge_txData_repeat; + reg bridge_txData_enable; + reg [7:0] bridge_txData_value; + reg bridge_txData_forceDisable; + reg bridge_txData_disableOnDataConflict; + reg bridge_txAck_valid; + reg bridge_txAck_repeat; + reg bridge_txAck_enable; + reg bridge_txAck_value; + reg bridge_txAck_forceAck; + reg bridge_txAck_disableOnDataConflict; + reg bridge_addressFilter_addresses_0_enable; + reg [9:0] bridge_addressFilter_addresses_0_value; + reg bridge_addressFilter_addresses_0_is10Bit; + reg bridge_addressFilter_addresses_1_enable; + reg [9:0] bridge_addressFilter_addresses_1_value; + reg bridge_addressFilter_addresses_1_is10Bit; + reg [1:0] bridge_addressFilter_state; + reg [7:0] bridge_addressFilter_byte0; + reg [7:0] bridge_addressFilter_byte1; + wire bridge_addressFilter_byte0Is10Bit; + wire bridge_addressFilter_hits_0; + wire bridge_addressFilter_hits_1; + wire when_I2cCtrl_l306; + wire _zz_when_I2cCtrl_l310; + reg _zz_when_I2cCtrl_l310_1; + wire when_I2cCtrl_l310; + reg bridge_masterLogic_start; + reg when_BusSlaveFactory_l377; + wire when_BusSlaveFactory_l379; + reg bridge_masterLogic_stop; + reg when_BusSlaveFactory_l377_1; + wire when_BusSlaveFactory_l379_1; + reg bridge_masterLogic_drop; + reg when_BusSlaveFactory_l377_2; + wire when_BusSlaveFactory_l379_2; + reg bridge_masterLogic_recover; + reg when_BusSlaveFactory_l377_3; + wire when_BusSlaveFactory_l379_3; + reg [11:0] bridge_masterLogic_timer_value; + reg [11:0] bridge_masterLogic_timer_tLow; + reg [11:0] bridge_masterLogic_timer_tHigh; + reg [11:0] bridge_masterLogic_timer_tBuf; + wire bridge_masterLogic_timer_done; + wire bridge_masterLogic_txReady; + wire bridge_masterLogic_fsm_wantExit; + reg bridge_masterLogic_fsm_wantStart; + wire bridge_masterLogic_fsm_wantKill; + reg bridge_masterLogic_fsm_dropped_start; + reg bridge_masterLogic_fsm_dropped_stop; + reg bridge_masterLogic_fsm_dropped_recover; + reg bridge_masterLogic_fsm_dropped_trigger; + reg bridge_masterLogic_fsm_inFrameLate; + wire when_I2cCtrl_l363; + wire when_I2cCtrl_l363_1; + wire bridge_masterLogic_fsm_outOfSync; + wire bridge_masterLogic_fsm_isBusy; + reg when_BusSlaveFactory_l341; + wire when_BusSlaveFactory_l347; + reg when_BusSlaveFactory_l341_1; + wire when_BusSlaveFactory_l347_1; + reg when_BusSlaveFactory_l341_2; + wire when_BusSlaveFactory_l347_2; + reg [2:0] bridge_dataCounter; + reg bridge_inAckState; + reg bridge_wasntAck; + wire when_I2cCtrl_l523; + wire when_I2cCtrl_l546; + wire when_I2cCtrl_l566; + wire when_I2cCtrl_l570; + wire when_I2cCtrl_l574; + wire when_I2cCtrl_l578; + wire when_I2cCtrl_l588; + wire when_I2cCtrl_l601; + reg bridge_interruptCtrl_rxDataEnable; + reg bridge_interruptCtrl_rxAckEnable; + reg bridge_interruptCtrl_txDataEnable; + reg bridge_interruptCtrl_txAckEnable; + reg bridge_interruptCtrl_interrupt; + wire when_I2cCtrl_l634; + reg bridge_interruptCtrl_start_enable; + reg bridge_interruptCtrl_start_flag; + wire when_I2cCtrl_l634_1; + reg when_BusSlaveFactory_l341_3; + wire when_BusSlaveFactory_l347_3; + wire when_I2cCtrl_l634_2; + reg bridge_interruptCtrl_restart_enable; + reg bridge_interruptCtrl_restart_flag; + wire when_I2cCtrl_l634_3; + reg when_BusSlaveFactory_l341_4; + wire when_BusSlaveFactory_l347_4; + wire when_I2cCtrl_l634_4; + reg bridge_interruptCtrl_end_enable; + reg bridge_interruptCtrl_end_flag; + wire when_I2cCtrl_l634_5; + reg when_BusSlaveFactory_l341_5; + wire when_BusSlaveFactory_l347_5; + wire when_I2cCtrl_l634_6; + reg bridge_interruptCtrl_drop_enable; + reg bridge_interruptCtrl_drop_flag; + wire when_I2cCtrl_l634_7; + reg when_BusSlaveFactory_l341_6; + wire when_BusSlaveFactory_l347_6; + wire _zz_when_I2cCtrl_l634; + reg _zz_when_I2cCtrl_l634_1; + wire when_I2cCtrl_l634_8; + reg bridge_interruptCtrl_filterGen_enable; + reg bridge_interruptCtrl_filterGen_flag; + wire when_I2cCtrl_l634_9; + reg when_BusSlaveFactory_l341_7; + wire when_BusSlaveFactory_l347_7; + reg bridge_masterLogic_fsm_isBusy_regNext; + wire when_I2cCtrl_l634_10; + reg bridge_interruptCtrl_clockGenExit_enable; + reg bridge_interruptCtrl_clockGenExit_flag; + wire when_I2cCtrl_l634_11; + reg when_BusSlaveFactory_l341_8; + wire when_BusSlaveFactory_l347_8; + reg bridge_masterLogic_fsm_isBusy_regNext_1; + wire when_I2cCtrl_l634_12; + reg bridge_interruptCtrl_clockGenEnter_enable; + reg bridge_interruptCtrl_clockGenEnter_flag; + wire when_I2cCtrl_l634_13; + reg when_BusSlaveFactory_l341_9; + wire when_BusSlaveFactory_l347_9; + reg [9:0] _zz_io_config_samplingClockDivider; + reg [19:0] _zz_io_config_timeout; + reg [5:0] _zz_io_config_tsuData; + reg bridge_timeoutClear; + wire when_I2cCtrl_l659; + reg [3:0] bridge_masterLogic_fsm_stateReg; + reg [3:0] bridge_masterLogic_fsm_stateNext; + reg i2cCtrl_io_internals_inFrame_regNext; + wire when_I2cCtrl_l367; + wire when_I2cCtrl_l369; + wire when_I2cCtrl_l380; + wire when_I2cCtrl_l392; + wire when_I2cCtrl_l418; + wire when_I2cCtrl_l422; + wire when_I2cCtrl_l442; + wire when_I2cCtrl_l450; + wire when_I2cCtrl_l474; + wire when_StateMachine_l253; + wire when_StateMachine_l253_1; + wire when_StateMachine_l253_2; + wire when_StateMachine_l253_3; + wire when_StateMachine_l253_4; + wire when_StateMachine_l253_5; + wire when_I2cCtrl_l350; + reg bridge_slaveOverride_sda; + reg bridge_slaveOverride_scl; + wire when_I2cCtrl_l673; + wire when_I2cCtrl_l674; + reg bridge_i2cBuffer_scl_write_regNext; + reg bridge_i2cBuffer_sda_write_regNext; + `ifndef SYNTHESIS + reg [55:0] bridge_masterLogic_fsm_stateReg_string; + reg [55:0] bridge_masterLogic_fsm_stateNext_string; + `endif + + + assign _zz_bridge_addressFilter_hits_0 = (bridge_addressFilter_byte0 >>> 1'd1); + assign _zz_bridge_addressFilter_hits_1 = (bridge_addressFilter_byte0 >>> 1'd1); + assign _zz_bridge_masterLogic_start = 1'b1; + assign _zz_bridge_masterLogic_stop = 1'b1; + assign _zz_bridge_masterLogic_drop = 1'b1; + assign _zz_bridge_masterLogic_recover = 1'b1; + assign _zz_bridge_masterLogic_timer_value_1 = (! bridge_masterLogic_timer_done); + assign _zz_bridge_masterLogic_timer_value = {11'd0, _zz_bridge_masterLogic_timer_value_1}; + assign _zz_bridge_masterLogic_fsm_dropped_start = 1'b0; + assign _zz_bridge_masterLogic_fsm_dropped_stop = 1'b0; + assign _zz_bridge_masterLogic_fsm_dropped_recover = 1'b0; + assign _zz_io_bus_rsp_data = (3'b111 - bridge_dataCounter); + assign _zz_bridge_rxData_value = (3'b111 - bridge_dataCounter); + assign _zz_bridge_interruptCtrl_start_flag = 1'b0; + assign _zz_bridge_interruptCtrl_restart_flag = 1'b0; + assign _zz_bridge_interruptCtrl_end_flag = 1'b0; + assign _zz_bridge_interruptCtrl_drop_flag = 1'b0; + assign _zz_bridge_interruptCtrl_filterGen_flag = 1'b0; + assign _zz_bridge_interruptCtrl_clockGenExit_flag = 1'b0; + assign _zz_bridge_interruptCtrl_clockGenEnter_flag = 1'b0; + Axi4PeripheralI2cSlave i2cCtrl ( + .io_i2c_sda_write (i2cCtrl_io_i2c_sda_write ), //o + .io_i2c_sda_read (bridge_i2cBuffer_sda_read ), //i + .io_i2c_scl_write (i2cCtrl_io_i2c_scl_write ), //o + .io_i2c_scl_read (bridge_i2cBuffer_scl_read ), //i + .io_config_samplingClockDivider (_zz_io_config_samplingClockDivider[9:0]), //i + .io_config_timeout (_zz_io_config_timeout[19:0] ), //i + .io_config_tsuData (_zz_io_config_tsuData[5:0] ), //i + .io_config_timeoutClear (i2cCtrl_io_config_timeoutClear ), //i + .io_bus_cmd_kind (i2cCtrl_io_bus_cmd_kind[2:0] ), //o + .io_bus_cmd_data (i2cCtrl_io_bus_cmd_data ), //o + .io_bus_rsp_valid (i2cCtrl_io_bus_rsp_valid ), //i + .io_bus_rsp_enable (i2cCtrl_io_bus_rsp_enable ), //i + .io_bus_rsp_data (i2cCtrl_io_bus_rsp_data ), //i + .io_timeout (i2cCtrl_io_timeout ), //o + .io_internals_inFrame (i2cCtrl_io_internals_inFrame ), //o + .io_internals_sdaRead (i2cCtrl_io_internals_sdaRead ), //o + .io_internals_sclRead (i2cCtrl_io_internals_sclRead ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + initial begin + `ifndef SYNTHESIS + _zz_io_config_timeout = {$urandom}; + _zz_io_config_tsuData = {$urandom}; + `endif + end + + `ifndef SYNTHESIS + always @(*) begin + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT : bridge_masterLogic_fsm_stateReg_string = "BOOT "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : bridge_masterLogic_fsm_stateReg_string = "IDLE "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : bridge_masterLogic_fsm_stateReg_string = "START1 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : bridge_masterLogic_fsm_stateReg_string = "START2 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : bridge_masterLogic_fsm_stateReg_string = "START3 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : bridge_masterLogic_fsm_stateReg_string = "LOW "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : bridge_masterLogic_fsm_stateReg_string = "HIGH "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : bridge_masterLogic_fsm_stateReg_string = "RESTART"; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : bridge_masterLogic_fsm_stateReg_string = "STOP1 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : bridge_masterLogic_fsm_stateReg_string = "STOP2 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : bridge_masterLogic_fsm_stateReg_string = "STOP3 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : bridge_masterLogic_fsm_stateReg_string = "TBUF "; + default : bridge_masterLogic_fsm_stateReg_string = "???????"; + endcase + end + always @(*) begin + case(bridge_masterLogic_fsm_stateNext) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT : bridge_masterLogic_fsm_stateNext_string = "BOOT "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : bridge_masterLogic_fsm_stateNext_string = "IDLE "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : bridge_masterLogic_fsm_stateNext_string = "START1 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : bridge_masterLogic_fsm_stateNext_string = "START2 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : bridge_masterLogic_fsm_stateNext_string = "START3 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : bridge_masterLogic_fsm_stateNext_string = "LOW "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : bridge_masterLogic_fsm_stateNext_string = "HIGH "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : bridge_masterLogic_fsm_stateNext_string = "RESTART"; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : bridge_masterLogic_fsm_stateNext_string = "STOP1 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : bridge_masterLogic_fsm_stateNext_string = "STOP2 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : bridge_masterLogic_fsm_stateNext_string = "STOP3 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : bridge_masterLogic_fsm_stateNext_string = "TBUF "; + default : bridge_masterLogic_fsm_stateNext_string = "???????"; + endcase + end + `endif + + assign busCtrl_readErrorFlag = 1'b0; + assign busCtrl_writeErrorFlag = 1'b0; + assign busCtrl_readHaltTrigger = 1'b0; + assign busCtrl_writeHaltTrigger = 1'b0; + assign _zz_busCtrl_rsp_ready = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); + assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready_1 && _zz_busCtrl_rsp_ready); + always @(*) begin + _zz_busCtrl_rsp_ready_1 = io_ctrl_rsp_ready; + if(when_Stream_l375) begin + _zz_busCtrl_rsp_ready_1 = 1'b1; + end + end + + assign when_Stream_l375 = (! _zz_io_ctrl_rsp_valid); + assign _zz_io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid_1; + assign io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid; + assign io_ctrl_rsp_payload_last = _zz_io_ctrl_rsp_payload_last; + assign io_ctrl_rsp_payload_fragment_opcode = _zz_io_ctrl_rsp_payload_fragment_opcode; + assign io_ctrl_rsp_payload_fragment_data = _zz_io_ctrl_rsp_payload_fragment_data; + assign io_ctrl_rsp_payload_fragment_context = _zz_io_ctrl_rsp_payload_fragment_context; + assign busCtrl_askWrite = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_askRead = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign io_ctrl_cmd_fire = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); + assign busCtrl_doWrite = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_doRead = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign busCtrl_rsp_valid = io_ctrl_cmd_valid; + assign io_ctrl_cmd_ready = busCtrl_rsp_ready; + assign busCtrl_rsp_payload_last = 1'b1; + assign when_BmbSlaveFactory_l33 = (busCtrl_doWrite && busCtrl_writeErrorFlag); + always @(*) begin + if(when_BmbSlaveFactory_l33) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + if(when_BmbSlaveFactory_l35) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + busCtrl_rsp_payload_fragment_opcode = 1'b0; + end + end + end + + assign when_BmbSlaveFactory_l35 = (busCtrl_doRead && busCtrl_readErrorFlag); + always @(*) begin + busCtrl_rsp_payload_fragment_data = 32'h0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h08 : begin + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_rxData_valid; + busCtrl_rsp_payload_fragment_data[7 : 0] = bridge_rxData_value; + end + 8'h0c : begin + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_rxAck_valid; + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_rxAck_value; + end + 8'h0 : begin + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_txData_valid; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_txData_enable; + end + 8'h04 : begin + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_txAck_valid; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_txAck_enable; + end + 8'h80 : begin + busCtrl_rsp_payload_fragment_data[1 : 0] = {bridge_addressFilter_hits_1,bridge_addressFilter_hits_0}; + end + 8'h84 : begin + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_addressFilter_byte0[0]; + end + 8'h40 : begin + busCtrl_rsp_payload_fragment_data[4 : 4] = bridge_masterLogic_start; + busCtrl_rsp_payload_fragment_data[5 : 5] = bridge_masterLogic_stop; + busCtrl_rsp_payload_fragment_data[6 : 6] = bridge_masterLogic_drop; + busCtrl_rsp_payload_fragment_data[7 : 7] = bridge_masterLogic_recover; + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_masterLogic_fsm_isBusy; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_masterLogic_fsm_dropped_start; + busCtrl_rsp_payload_fragment_data[10 : 10] = bridge_masterLogic_fsm_dropped_stop; + busCtrl_rsp_payload_fragment_data[11 : 11] = bridge_masterLogic_fsm_dropped_recover; + end + 8'h20 : begin + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_interruptCtrl_rxDataEnable; + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_interruptCtrl_rxAckEnable; + busCtrl_rsp_payload_fragment_data[2 : 2] = bridge_interruptCtrl_txDataEnable; + busCtrl_rsp_payload_fragment_data[3 : 3] = bridge_interruptCtrl_txAckEnable; + busCtrl_rsp_payload_fragment_data[4 : 4] = bridge_interruptCtrl_start_enable; + busCtrl_rsp_payload_fragment_data[5 : 5] = bridge_interruptCtrl_restart_enable; + busCtrl_rsp_payload_fragment_data[6 : 6] = bridge_interruptCtrl_end_enable; + busCtrl_rsp_payload_fragment_data[7 : 7] = bridge_interruptCtrl_drop_enable; + busCtrl_rsp_payload_fragment_data[17 : 17] = bridge_interruptCtrl_filterGen_enable; + busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_interruptCtrl_clockGenExit_enable; + busCtrl_rsp_payload_fragment_data[16 : 16] = bridge_interruptCtrl_clockGenEnter_enable; + end + 8'h24 : begin + busCtrl_rsp_payload_fragment_data[4 : 4] = bridge_interruptCtrl_start_flag; + busCtrl_rsp_payload_fragment_data[5 : 5] = bridge_interruptCtrl_restart_flag; + busCtrl_rsp_payload_fragment_data[6 : 6] = bridge_interruptCtrl_end_flag; + busCtrl_rsp_payload_fragment_data[7 : 7] = bridge_interruptCtrl_drop_flag; + busCtrl_rsp_payload_fragment_data[17 : 17] = bridge_interruptCtrl_filterGen_flag; + busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_interruptCtrl_clockGenExit_flag; + busCtrl_rsp_payload_fragment_data[16 : 16] = bridge_interruptCtrl_clockGenEnter_flag; + end + 8'h44 : begin + busCtrl_rsp_payload_fragment_data[0 : 0] = i2cCtrl_io_internals_inFrame; + busCtrl_rsp_payload_fragment_data[1 : 1] = i2cCtrl_io_internals_sdaRead; + busCtrl_rsp_payload_fragment_data[2 : 2] = i2cCtrl_io_internals_sclRead; + end + 8'h48 : begin + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_slaveOverride_sda; + busCtrl_rsp_payload_fragment_data[2 : 2] = bridge_slaveOverride_scl; + end + default : begin + end + endcase + end + + assign busCtrl_rsp_payload_fragment_context = io_ctrl_cmd_payload_fragment_context; + assign bridge_busCtrlWithOffset_readErrorFlag = 1'b0; + assign bridge_busCtrlWithOffset_writeErrorFlag = 1'b0; + always @(*) begin + bridge_frameReset = 1'b0; + case(i2cCtrl_io_bus_cmd_kind) + Axi4PeripheralI2cSlaveCmdMode_START : begin + bridge_frameReset = 1'b1; + end + Axi4PeripheralI2cSlaveCmdMode_RESTART : begin + bridge_frameReset = 1'b1; + end + Axi4PeripheralI2cSlaveCmdMode_STOP : begin + bridge_frameReset = 1'b1; + end + Axi4PeripheralI2cSlaveCmdMode_DROP : begin + bridge_frameReset = 1'b1; + end + default : begin + end + endcase + end + + always @(*) begin + bridge_i2cBuffer_sda_write = i2cCtrl_io_i2c_sda_write; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + bridge_i2cBuffer_sda_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + bridge_i2cBuffer_sda_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + bridge_i2cBuffer_sda_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + bridge_i2cBuffer_sda_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + end + endcase + if(when_I2cCtrl_l673) begin + bridge_i2cBuffer_sda_write = 1'b0; + end + end + + always @(*) begin + bridge_i2cBuffer_scl_write = i2cCtrl_io_i2c_scl_write; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + bridge_i2cBuffer_scl_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + if(bridge_masterLogic_timer_done) begin + if(when_I2cCtrl_l418) begin + bridge_i2cBuffer_scl_write = 1'b0; + end else begin + if(when_I2cCtrl_l422) begin + bridge_i2cBuffer_scl_write = 1'b0; + end + end + end else begin + bridge_i2cBuffer_scl_write = 1'b0; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + bridge_i2cBuffer_scl_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + end + endcase + if(when_I2cCtrl_l674) begin + bridge_i2cBuffer_scl_write = 1'b0; + end + end + + always @(*) begin + when_I2cCtrl_l224 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h08 : begin + if(busCtrl_doRead) begin + when_I2cCtrl_l224 = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + when_I2cCtrl_l237 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h0c : begin + if(busCtrl_doRead) begin + when_I2cCtrl_l237 = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + bridge_txData_forceDisable = 1'b0; + if(when_I2cCtrl_l601) begin + bridge_txData_forceDisable = 1'b0; + end + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + if(bridge_masterLogic_timer_done) begin + if(when_I2cCtrl_l418) begin + bridge_txData_forceDisable = 1'b1; + end else begin + if(when_I2cCtrl_l422) begin + bridge_txData_forceDisable = 1'b1; + end + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + end + endcase + end + + always @(*) begin + bridge_txAck_forceAck = 1'b0; + if(when_I2cCtrl_l306) begin + bridge_txAck_forceAck = 1'b1; + end + end + + assign bridge_addressFilter_byte0Is10Bit = (bridge_addressFilter_byte0[7 : 3] == 5'h1e); + assign bridge_addressFilter_hits_0 = (bridge_addressFilter_addresses_0_enable && ((! bridge_addressFilter_addresses_0_is10Bit) ? ((_zz_bridge_addressFilter_hits_0 == bridge_addressFilter_addresses_0_value[6 : 0]) && (bridge_addressFilter_state != 2'b00)) : (({bridge_addressFilter_byte0[2 : 1],bridge_addressFilter_byte1} == bridge_addressFilter_addresses_0_value) && (bridge_addressFilter_state == 2'b10)))); + assign bridge_addressFilter_hits_1 = (bridge_addressFilter_addresses_1_enable && ((! bridge_addressFilter_addresses_1_is10Bit) ? ((_zz_bridge_addressFilter_hits_1 == bridge_addressFilter_addresses_1_value[6 : 0]) && (bridge_addressFilter_state != 2'b00)) : (({bridge_addressFilter_byte0[2 : 1],bridge_addressFilter_byte1} == bridge_addressFilter_addresses_1_value) && (bridge_addressFilter_state == 2'b10)))); + assign when_I2cCtrl_l306 = ((bridge_addressFilter_byte0Is10Bit && (bridge_addressFilter_state == 2'b01)) && (|{((bridge_addressFilter_addresses_1_enable && bridge_addressFilter_addresses_1_is10Bit) && (bridge_addressFilter_byte0[2 : 1] == bridge_addressFilter_addresses_1_value[9 : 8])),((bridge_addressFilter_addresses_0_enable && bridge_addressFilter_addresses_0_is10Bit) && (bridge_addressFilter_byte0[2 : 1] == bridge_addressFilter_addresses_0_value[9 : 8]))})); + assign _zz_when_I2cCtrl_l310 = (|{bridge_addressFilter_hits_1,bridge_addressFilter_hits_0}); + assign when_I2cCtrl_l310 = (_zz_when_I2cCtrl_l310 && (! _zz_when_I2cCtrl_l310_1)); + always @(*) begin + when_BusSlaveFactory_l377 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l377 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379 = io_ctrl_cmd_payload_fragment_data[4]; + always @(*) begin + when_BusSlaveFactory_l377_1 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l377_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_1 = io_ctrl_cmd_payload_fragment_data[5]; + always @(*) begin + when_BusSlaveFactory_l377_2 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l377_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_2 = io_ctrl_cmd_payload_fragment_data[6]; + always @(*) begin + when_BusSlaveFactory_l377_3 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l377_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_3 = io_ctrl_cmd_payload_fragment_data[7]; + assign bridge_masterLogic_timer_done = (bridge_masterLogic_timer_value == 12'h0); + assign bridge_masterLogic_fsm_wantExit = 1'b0; + always @(*) begin + bridge_masterLogic_fsm_wantStart = 1'b0; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + bridge_masterLogic_fsm_wantStart = 1'b1; + end + endcase + end + + assign bridge_masterLogic_fsm_wantKill = 1'b0; + always @(*) begin + bridge_masterLogic_fsm_dropped_trigger = 1'b0; + if(when_I2cCtrl_l350) begin + bridge_masterLogic_fsm_dropped_trigger = 1'b1; + end + end + + assign when_I2cCtrl_l363 = (! i2cCtrl_io_internals_sclRead); + assign when_I2cCtrl_l363_1 = (! i2cCtrl_io_internals_inFrame); + assign bridge_masterLogic_fsm_outOfSync = ((! i2cCtrl_io_internals_inFrame) && ((! i2cCtrl_io_internals_sdaRead) || (! i2cCtrl_io_internals_sclRead))); + assign bridge_masterLogic_fsm_isBusy = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE)) && (! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF))); + always @(*) begin + when_BusSlaveFactory_l341 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347 = io_ctrl_cmd_payload_fragment_data[9]; + always @(*) begin + when_BusSlaveFactory_l341_1 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_1 = io_ctrl_cmd_payload_fragment_data[10]; + always @(*) begin + when_BusSlaveFactory_l341_2 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_2 = io_ctrl_cmd_payload_fragment_data[11]; + assign bridge_masterLogic_txReady = (bridge_inAckState ? bridge_txAck_valid : bridge_txData_valid); + assign when_I2cCtrl_l523 = (! bridge_inAckState); + always @(*) begin + if(when_I2cCtrl_l523) begin + i2cCtrl_io_bus_rsp_valid = ((bridge_txData_valid && (! (bridge_rxData_valid && bridge_rxData_listen))) && (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DRIVE)); + if(bridge_txData_forceDisable) begin + i2cCtrl_io_bus_rsp_valid = 1'b1; + end + end else begin + i2cCtrl_io_bus_rsp_valid = ((bridge_txAck_valid && (! (bridge_rxAck_valid && bridge_rxAck_listen))) && (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DRIVE)); + if(bridge_txAck_forceAck) begin + i2cCtrl_io_bus_rsp_valid = 1'b1; + end + end + if(when_I2cCtrl_l546) begin + i2cCtrl_io_bus_rsp_valid = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DRIVE); + end + end + + always @(*) begin + if(when_I2cCtrl_l523) begin + i2cCtrl_io_bus_rsp_enable = bridge_txData_enable; + if(bridge_txData_forceDisable) begin + i2cCtrl_io_bus_rsp_enable = 1'b0; + end + end else begin + i2cCtrl_io_bus_rsp_enable = bridge_txAck_enable; + if(bridge_txAck_forceAck) begin + i2cCtrl_io_bus_rsp_enable = 1'b1; + end + end + if(when_I2cCtrl_l546) begin + i2cCtrl_io_bus_rsp_enable = 1'b0; + end + end + + always @(*) begin + if(when_I2cCtrl_l523) begin + i2cCtrl_io_bus_rsp_data = bridge_txData_value[_zz_io_bus_rsp_data]; + end else begin + i2cCtrl_io_bus_rsp_data = bridge_txAck_value; + if(bridge_txAck_forceAck) begin + i2cCtrl_io_bus_rsp_data = 1'b0; + end + end + end + + assign when_I2cCtrl_l546 = (bridge_wasntAck && (! bridge_masterLogic_fsm_isBusy)); + assign when_I2cCtrl_l566 = (! bridge_inAckState); + assign when_I2cCtrl_l570 = (i2cCtrl_io_bus_rsp_data != i2cCtrl_io_bus_cmd_data); + assign when_I2cCtrl_l574 = (bridge_dataCounter == 3'b111); + assign when_I2cCtrl_l578 = (bridge_txData_valid && (! bridge_txData_repeat)); + assign when_I2cCtrl_l588 = (bridge_txAck_valid && (! bridge_txAck_repeat)); + assign when_I2cCtrl_l601 = ((i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_STOP) || (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DROP)); + always @(*) begin + bridge_interruptCtrl_interrupt = ((((bridge_interruptCtrl_rxDataEnable && bridge_rxData_valid) || (bridge_interruptCtrl_rxAckEnable && bridge_rxAck_valid)) || (bridge_interruptCtrl_txDataEnable && (! bridge_txData_valid))) || (bridge_interruptCtrl_txAckEnable && (! bridge_txAck_valid))); + if(bridge_interruptCtrl_start_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_restart_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_end_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_drop_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_filterGen_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_clockGenExit_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_clockGenEnter_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + end + + assign when_I2cCtrl_l634 = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_START); + assign when_I2cCtrl_l634_1 = (! bridge_interruptCtrl_start_enable); + always @(*) begin + when_BusSlaveFactory_l341_3 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_3 = io_ctrl_cmd_payload_fragment_data[4]; + assign when_I2cCtrl_l634_2 = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_RESTART); + assign when_I2cCtrl_l634_3 = (! bridge_interruptCtrl_restart_enable); + always @(*) begin + when_BusSlaveFactory_l341_4 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_4 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_4 = io_ctrl_cmd_payload_fragment_data[5]; + assign when_I2cCtrl_l634_4 = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_STOP); + assign when_I2cCtrl_l634_5 = (! bridge_interruptCtrl_end_enable); + always @(*) begin + when_BusSlaveFactory_l341_5 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_5 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_5 = io_ctrl_cmd_payload_fragment_data[6]; + assign when_I2cCtrl_l634_6 = ((i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DROP) || bridge_masterLogic_fsm_dropped_trigger); + assign when_I2cCtrl_l634_7 = (! bridge_interruptCtrl_drop_enable); + always @(*) begin + when_BusSlaveFactory_l341_6 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_6 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_6 = io_ctrl_cmd_payload_fragment_data[7]; + assign _zz_when_I2cCtrl_l634 = (|{bridge_addressFilter_hits_1,bridge_addressFilter_hits_0}); + assign when_I2cCtrl_l634_8 = (_zz_when_I2cCtrl_l634 && (! _zz_when_I2cCtrl_l634_1)); + assign when_I2cCtrl_l634_9 = (! bridge_interruptCtrl_filterGen_enable); + always @(*) begin + when_BusSlaveFactory_l341_7 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_7 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_7 = io_ctrl_cmd_payload_fragment_data[17]; + assign when_I2cCtrl_l634_10 = ((! bridge_masterLogic_fsm_isBusy) && bridge_masterLogic_fsm_isBusy_regNext); + assign when_I2cCtrl_l634_11 = (! bridge_interruptCtrl_clockGenExit_enable); + always @(*) begin + when_BusSlaveFactory_l341_8 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_8 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_8 = io_ctrl_cmd_payload_fragment_data[15]; + assign when_I2cCtrl_l634_12 = (bridge_masterLogic_fsm_isBusy && (! bridge_masterLogic_fsm_isBusy_regNext_1)); + assign when_I2cCtrl_l634_13 = (! bridge_interruptCtrl_clockGenEnter_enable); + always @(*) begin + when_BusSlaveFactory_l341_9 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_9 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_9 = io_ctrl_cmd_payload_fragment_data[16]; + always @(*) begin + i2cCtrl_io_config_timeoutClear = bridge_timeoutClear; + if(when_I2cCtrl_l659) begin + i2cCtrl_io_config_timeoutClear = 1'b1; + end + end + + assign when_I2cCtrl_l659 = ((! i2cCtrl_io_internals_inFrame) && (! bridge_masterLogic_fsm_isBusy)); + always @(*) begin + bridge_masterLogic_fsm_stateNext = bridge_masterLogic_fsm_stateReg; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + if(when_I2cCtrl_l367) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF; + end else begin + if(when_I2cCtrl_l369) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1; + end else begin + if(bridge_masterLogic_recover) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW; + end + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + if(when_I2cCtrl_l380) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + if(when_I2cCtrl_l392) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + if(bridge_masterLogic_timer_done) begin + if(when_I2cCtrl_l418) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1; + end else begin + if(when_I2cCtrl_l422) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART; + end else begin + if(i2cCtrl_io_internals_sclRead) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH; + end + end + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + if(when_I2cCtrl_l442) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + if(!when_I2cCtrl_l450) begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1; + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + if(!when_I2cCtrl_l474) begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3; + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + if(i2cCtrl_io_internals_sdaRead) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE; + end + end + default : begin + end + endcase + if(when_I2cCtrl_l350) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF; + end + if(bridge_masterLogic_fsm_wantStart) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE; + end + if(bridge_masterLogic_fsm_wantKill) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT; + end + end + + assign when_I2cCtrl_l367 = ((! i2cCtrl_io_internals_inFrame) && i2cCtrl_io_internals_inFrame_regNext); + assign when_I2cCtrl_l369 = (bridge_masterLogic_start && (! bridge_masterLogic_fsm_inFrameLate)); + assign when_I2cCtrl_l380 = (! bridge_masterLogic_fsm_outOfSync); + assign when_I2cCtrl_l392 = (bridge_masterLogic_timer_done || (! i2cCtrl_io_internals_sclRead)); + assign when_I2cCtrl_l418 = ((bridge_masterLogic_stop && (! bridge_inAckState)) || (bridge_masterLogic_recover && i2cCtrl_io_internals_sdaRead)); + assign when_I2cCtrl_l422 = (bridge_masterLogic_start && (! bridge_inAckState)); + assign when_I2cCtrl_l442 = (bridge_masterLogic_timer_done || (! i2cCtrl_io_internals_sclRead)); + assign when_I2cCtrl_l450 = (! i2cCtrl_io_internals_sclRead); + assign when_I2cCtrl_l474 = (! i2cCtrl_io_internals_sclRead); + assign when_StateMachine_l253 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2)); + assign when_StateMachine_l253_1 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3)); + assign when_StateMachine_l253_2 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW)); + assign when_StateMachine_l253_3 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH)); + assign when_StateMachine_l253_4 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1)); + assign when_StateMachine_l253_5 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF)); + assign when_I2cCtrl_l350 = (bridge_masterLogic_drop || ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE)) && ((i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DROP) || i2cCtrl_io_timeout))); + assign when_I2cCtrl_l673 = (! bridge_slaveOverride_sda); + assign when_I2cCtrl_l674 = (! bridge_slaveOverride_scl); + assign io_i2c_scl_write = bridge_i2cBuffer_scl_write_regNext; + assign io_i2c_sda_write = bridge_i2cBuffer_sda_write_regNext; + assign bridge_i2cBuffer_scl_read = io_i2c_scl_read; + assign bridge_i2cBuffer_sda_read = io_i2c_sda_read; + assign system_i2c_0_io_interrupt_source = bridge_interruptCtrl_interrupt; + always @(posedge clk) begin + if(reset) begin + _zz_io_ctrl_rsp_valid_1 <= 1'b0; + bridge_rxData_event <= 1'b0; + bridge_rxData_listen <= 1'b0; + bridge_rxData_valid <= 1'b0; + bridge_rxAck_listen <= 1'b0; + bridge_rxAck_valid <= 1'b0; + bridge_txData_valid <= 1'b1; + bridge_txData_repeat <= 1'b1; + bridge_txData_enable <= 1'b0; + bridge_txAck_valid <= 1'b1; + bridge_txAck_repeat <= 1'b1; + bridge_txAck_enable <= 1'b0; + bridge_addressFilter_addresses_0_enable <= 1'b0; + bridge_addressFilter_addresses_1_enable <= 1'b0; + bridge_addressFilter_state <= 2'b00; + bridge_masterLogic_start <= 1'b0; + bridge_masterLogic_stop <= 1'b0; + bridge_masterLogic_drop <= 1'b0; + bridge_masterLogic_recover <= 1'b0; + bridge_masterLogic_fsm_dropped_start <= 1'b0; + bridge_masterLogic_fsm_dropped_stop <= 1'b0; + bridge_masterLogic_fsm_dropped_recover <= 1'b0; + bridge_dataCounter <= 3'b000; + bridge_inAckState <= 1'b0; + bridge_wasntAck <= 1'b0; + bridge_interruptCtrl_rxDataEnable <= 1'b0; + bridge_interruptCtrl_rxAckEnable <= 1'b0; + bridge_interruptCtrl_txDataEnable <= 1'b0; + bridge_interruptCtrl_txAckEnable <= 1'b0; + bridge_interruptCtrl_start_enable <= 1'b0; + bridge_interruptCtrl_start_flag <= 1'b0; + bridge_interruptCtrl_restart_enable <= 1'b0; + bridge_interruptCtrl_restart_flag <= 1'b0; + bridge_interruptCtrl_end_enable <= 1'b0; + bridge_interruptCtrl_end_flag <= 1'b0; + bridge_interruptCtrl_drop_enable <= 1'b0; + bridge_interruptCtrl_drop_flag <= 1'b0; + bridge_interruptCtrl_filterGen_enable <= 1'b0; + bridge_interruptCtrl_filterGen_flag <= 1'b0; + bridge_interruptCtrl_clockGenExit_enable <= 1'b0; + bridge_interruptCtrl_clockGenExit_flag <= 1'b0; + bridge_interruptCtrl_clockGenEnter_enable <= 1'b0; + bridge_interruptCtrl_clockGenEnter_flag <= 1'b0; + _zz_io_config_samplingClockDivider <= 10'h0; + bridge_masterLogic_fsm_stateReg <= Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT; + bridge_slaveOverride_sda <= 1'b1; + bridge_slaveOverride_scl <= 1'b1; + bridge_i2cBuffer_scl_write_regNext <= 1'b1; + bridge_i2cBuffer_sda_write_regNext <= 1'b1; + end else begin + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_ctrl_rsp_valid_1 <= (busCtrl_rsp_valid && _zz_busCtrl_rsp_ready); + end + bridge_rxData_event <= 1'b0; + if(when_I2cCtrl_l224) begin + bridge_rxData_valid <= 1'b0; + end + if(when_I2cCtrl_l237) begin + bridge_rxAck_valid <= 1'b0; + end + if(bridge_rxData_event) begin + case(bridge_addressFilter_state) + 2'b00 : begin + bridge_addressFilter_state <= 2'b01; + end + 2'b01 : begin + bridge_addressFilter_state <= 2'b10; + end + default : begin + end + endcase + end + if(bridge_frameReset) begin + bridge_addressFilter_state <= 2'b00; + end + if(when_I2cCtrl_l310) begin + bridge_txAck_valid <= 1'b0; + end + if(when_BusSlaveFactory_l377) begin + if(when_BusSlaveFactory_l379) begin + bridge_masterLogic_start <= _zz_bridge_masterLogic_start[0]; + end + end + if(when_BusSlaveFactory_l377_1) begin + if(when_BusSlaveFactory_l379_1) begin + bridge_masterLogic_stop <= _zz_bridge_masterLogic_stop[0]; + end + end + if(when_BusSlaveFactory_l377_2) begin + if(when_BusSlaveFactory_l379_2) begin + bridge_masterLogic_drop <= _zz_bridge_masterLogic_drop[0]; + end + end + if(when_BusSlaveFactory_l377_3) begin + if(when_BusSlaveFactory_l379_3) begin + bridge_masterLogic_recover <= _zz_bridge_masterLogic_recover[0]; + end + end + if(when_BusSlaveFactory_l341) begin + if(when_BusSlaveFactory_l347) begin + bridge_masterLogic_fsm_dropped_start <= _zz_bridge_masterLogic_fsm_dropped_start[0]; + end + end + if(when_BusSlaveFactory_l341_1) begin + if(when_BusSlaveFactory_l347_1) begin + bridge_masterLogic_fsm_dropped_stop <= _zz_bridge_masterLogic_fsm_dropped_stop[0]; + end + end + if(when_BusSlaveFactory_l341_2) begin + if(when_BusSlaveFactory_l347_2) begin + bridge_masterLogic_fsm_dropped_recover <= _zz_bridge_masterLogic_fsm_dropped_recover[0]; + end + end + case(i2cCtrl_io_bus_cmd_kind) + Axi4PeripheralI2cSlaveCmdMode_READ : begin + if(when_I2cCtrl_l566) begin + bridge_dataCounter <= (bridge_dataCounter + 3'b001); + if(when_I2cCtrl_l570) begin + if(bridge_txData_disableOnDataConflict) begin + bridge_txData_enable <= 1'b0; + end + if(bridge_txAck_disableOnDataConflict) begin + bridge_txAck_enable <= 1'b0; + end + end + if(when_I2cCtrl_l574) begin + if(bridge_rxData_listen) begin + bridge_rxData_valid <= 1'b1; + end + bridge_rxData_event <= 1'b1; + bridge_inAckState <= 1'b1; + if(when_I2cCtrl_l578) begin + bridge_txData_valid <= 1'b0; + end + end + end else begin + if(bridge_rxAck_listen) begin + bridge_rxAck_valid <= 1'b1; + end + bridge_inAckState <= 1'b0; + bridge_wasntAck <= i2cCtrl_io_bus_cmd_data; + if(when_I2cCtrl_l588) begin + bridge_txAck_valid <= 1'b0; + end + end + end + default : begin + end + endcase + if(bridge_frameReset) begin + bridge_inAckState <= 1'b0; + bridge_dataCounter <= 3'b000; + bridge_wasntAck <= 1'b0; + end + if(when_I2cCtrl_l601) begin + bridge_txData_valid <= 1'b1; + bridge_txData_enable <= 1'b0; + bridge_txData_repeat <= 1'b1; + bridge_txAck_valid <= 1'b1; + bridge_txAck_enable <= 1'b0; + bridge_txAck_repeat <= 1'b1; + bridge_rxData_listen <= 1'b0; + bridge_rxAck_listen <= 1'b0; + end + if(when_I2cCtrl_l634) begin + bridge_interruptCtrl_start_flag <= 1'b1; + end + if(when_I2cCtrl_l634_1) begin + bridge_interruptCtrl_start_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_3) begin + if(when_BusSlaveFactory_l347_3) begin + bridge_interruptCtrl_start_flag <= _zz_bridge_interruptCtrl_start_flag[0]; + end + end + if(when_I2cCtrl_l634_2) begin + bridge_interruptCtrl_restart_flag <= 1'b1; + end + if(when_I2cCtrl_l634_3) begin + bridge_interruptCtrl_restart_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_4) begin + if(when_BusSlaveFactory_l347_4) begin + bridge_interruptCtrl_restart_flag <= _zz_bridge_interruptCtrl_restart_flag[0]; + end + end + if(when_I2cCtrl_l634_4) begin + bridge_interruptCtrl_end_flag <= 1'b1; + end + if(when_I2cCtrl_l634_5) begin + bridge_interruptCtrl_end_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_5) begin + if(when_BusSlaveFactory_l347_5) begin + bridge_interruptCtrl_end_flag <= _zz_bridge_interruptCtrl_end_flag[0]; + end + end + if(when_I2cCtrl_l634_6) begin + bridge_interruptCtrl_drop_flag <= 1'b1; + end + if(when_I2cCtrl_l634_7) begin + bridge_interruptCtrl_drop_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_6) begin + if(when_BusSlaveFactory_l347_6) begin + bridge_interruptCtrl_drop_flag <= _zz_bridge_interruptCtrl_drop_flag[0]; + end + end + if(when_I2cCtrl_l634_8) begin + bridge_interruptCtrl_filterGen_flag <= 1'b1; + end + if(when_I2cCtrl_l634_9) begin + bridge_interruptCtrl_filterGen_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_7) begin + if(when_BusSlaveFactory_l347_7) begin + bridge_interruptCtrl_filterGen_flag <= _zz_bridge_interruptCtrl_filterGen_flag[0]; + end + end + if(when_I2cCtrl_l634_10) begin + bridge_interruptCtrl_clockGenExit_flag <= 1'b1; + end + if(when_I2cCtrl_l634_11) begin + bridge_interruptCtrl_clockGenExit_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_8) begin + if(when_BusSlaveFactory_l347_8) begin + bridge_interruptCtrl_clockGenExit_flag <= _zz_bridge_interruptCtrl_clockGenExit_flag[0]; + end + end + if(when_I2cCtrl_l634_12) begin + bridge_interruptCtrl_clockGenEnter_flag <= 1'b1; + end + if(when_I2cCtrl_l634_13) begin + bridge_interruptCtrl_clockGenEnter_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_9) begin + if(when_BusSlaveFactory_l347_9) begin + bridge_interruptCtrl_clockGenEnter_flag <= _zz_bridge_interruptCtrl_clockGenEnter_flag[0]; + end + end + bridge_masterLogic_fsm_stateReg <= bridge_masterLogic_fsm_stateNext; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + if(!when_I2cCtrl_l367) begin + if(when_I2cCtrl_l369) begin + bridge_txData_valid <= 1'b0; + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_start <= 1'b0; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + if(i2cCtrl_io_internals_sdaRead) begin + bridge_masterLogic_stop <= 1'b0; + bridge_masterLogic_recover <= 1'b0; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + end + endcase + if(when_I2cCtrl_l350) begin + bridge_masterLogic_start <= 1'b0; + bridge_masterLogic_stop <= 1'b0; + bridge_masterLogic_drop <= 1'b0; + bridge_masterLogic_recover <= 1'b0; + if(bridge_masterLogic_start) begin + bridge_masterLogic_fsm_dropped_start <= 1'b1; + end + if(bridge_masterLogic_stop) begin + bridge_masterLogic_fsm_dropped_stop <= 1'b1; + end + end + bridge_i2cBuffer_scl_write_regNext <= bridge_i2cBuffer_scl_write; + bridge_i2cBuffer_sda_write_regNext <= bridge_i2cBuffer_sda_write; + case(io_ctrl_cmd_payload_fragment_address) + 8'h08 : begin + if(busCtrl_doWrite) begin + bridge_rxData_listen <= io_ctrl_cmd_payload_fragment_data[9]; + end + end + 8'h0c : begin + if(busCtrl_doWrite) begin + bridge_rxAck_listen <= io_ctrl_cmd_payload_fragment_data[9]; + end + end + 8'h0 : begin + if(busCtrl_doWrite) begin + bridge_txData_repeat <= io_ctrl_cmd_payload_fragment_data[10]; + bridge_txData_valid <= io_ctrl_cmd_payload_fragment_data[8]; + bridge_txData_enable <= io_ctrl_cmd_payload_fragment_data[9]; + end + end + 8'h04 : begin + if(busCtrl_doWrite) begin + bridge_txAck_repeat <= io_ctrl_cmd_payload_fragment_data[10]; + bridge_txAck_valid <= io_ctrl_cmd_payload_fragment_data[8]; + bridge_txAck_enable <= io_ctrl_cmd_payload_fragment_data[9]; + end + end + 8'h88 : begin + if(busCtrl_doWrite) begin + bridge_addressFilter_addresses_0_enable <= io_ctrl_cmd_payload_fragment_data[15]; + end + end + 8'h8c : begin + if(busCtrl_doWrite) begin + bridge_addressFilter_addresses_1_enable <= io_ctrl_cmd_payload_fragment_data[15]; + end + end + 8'h20 : begin + if(busCtrl_doWrite) begin + bridge_interruptCtrl_rxDataEnable <= io_ctrl_cmd_payload_fragment_data[0]; + bridge_interruptCtrl_rxAckEnable <= io_ctrl_cmd_payload_fragment_data[1]; + bridge_interruptCtrl_txDataEnable <= io_ctrl_cmd_payload_fragment_data[2]; + bridge_interruptCtrl_txAckEnable <= io_ctrl_cmd_payload_fragment_data[3]; + bridge_interruptCtrl_start_enable <= io_ctrl_cmd_payload_fragment_data[4]; + bridge_interruptCtrl_restart_enable <= io_ctrl_cmd_payload_fragment_data[5]; + bridge_interruptCtrl_end_enable <= io_ctrl_cmd_payload_fragment_data[6]; + bridge_interruptCtrl_drop_enable <= io_ctrl_cmd_payload_fragment_data[7]; + bridge_interruptCtrl_filterGen_enable <= io_ctrl_cmd_payload_fragment_data[17]; + bridge_interruptCtrl_clockGenExit_enable <= io_ctrl_cmd_payload_fragment_data[15]; + bridge_interruptCtrl_clockGenEnter_enable <= io_ctrl_cmd_payload_fragment_data[16]; + end + end + 8'h28 : begin + if(busCtrl_doWrite) begin + _zz_io_config_samplingClockDivider <= io_ctrl_cmd_payload_fragment_data[9 : 0]; + end + end + 8'h48 : begin + if(busCtrl_doWrite) begin + bridge_slaveOverride_sda <= io_ctrl_cmd_payload_fragment_data[1]; + bridge_slaveOverride_scl <= io_ctrl_cmd_payload_fragment_data[2]; + end + end + default : begin + end + endcase + end + end + + always @(posedge clk) begin + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_ctrl_rsp_payload_last <= busCtrl_rsp_payload_last; + _zz_io_ctrl_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; + _zz_io_ctrl_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; + _zz_io_ctrl_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; + end + if(bridge_rxData_event) begin + case(bridge_addressFilter_state) + 2'b00 : begin + bridge_addressFilter_byte0 <= bridge_rxData_value; + end + 2'b01 : begin + bridge_addressFilter_byte1 <= bridge_rxData_value; + end + default : begin + end + endcase + end + _zz_when_I2cCtrl_l310_1 <= _zz_when_I2cCtrl_l310; + bridge_masterLogic_timer_value <= (bridge_masterLogic_timer_value - _zz_bridge_masterLogic_timer_value); + if(when_I2cCtrl_l363) begin + bridge_masterLogic_fsm_inFrameLate <= 1'b1; + end + if(when_I2cCtrl_l363_1) begin + bridge_masterLogic_fsm_inFrameLate <= 1'b0; + end + case(i2cCtrl_io_bus_cmd_kind) + Axi4PeripheralI2cSlaveCmdMode_READ : begin + if(when_I2cCtrl_l566) begin + bridge_rxData_value[_zz_bridge_rxData_value] <= i2cCtrl_io_bus_cmd_data; + end else begin + bridge_rxAck_value <= i2cCtrl_io_bus_cmd_data; + end + end + default : begin + end + endcase + if(when_I2cCtrl_l601) begin + bridge_txData_disableOnDataConflict <= 1'b0; + bridge_txAck_disableOnDataConflict <= 1'b0; + end + _zz_when_I2cCtrl_l634_1 <= _zz_when_I2cCtrl_l634; + bridge_masterLogic_fsm_isBusy_regNext <= bridge_masterLogic_fsm_isBusy; + bridge_masterLogic_fsm_isBusy_regNext_1 <= bridge_masterLogic_fsm_isBusy; + bridge_timeoutClear <= 1'b0; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + if(when_I2cCtrl_l450) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + if(when_I2cCtrl_l474) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + end + endcase + if(when_StateMachine_l253) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; + end + if(when_StateMachine_l253_1) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tLow; + end + if(when_StateMachine_l253_2) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tLow; + end + if(when_StateMachine_l253_3) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; + end + if(when_StateMachine_l253_4) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; + end + if(when_StateMachine_l253_5) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tBuf; + end + case(io_ctrl_cmd_payload_fragment_address) + 8'h0 : begin + if(busCtrl_doWrite) begin + bridge_txData_value <= io_ctrl_cmd_payload_fragment_data[7 : 0]; + bridge_txData_disableOnDataConflict <= io_ctrl_cmd_payload_fragment_data[11]; + end + end + 8'h04 : begin + if(busCtrl_doWrite) begin + bridge_txAck_value <= io_ctrl_cmd_payload_fragment_data[0]; + bridge_txAck_disableOnDataConflict <= io_ctrl_cmd_payload_fragment_data[11]; + end + end + 8'h88 : begin + if(busCtrl_doWrite) begin + bridge_addressFilter_addresses_0_value <= io_ctrl_cmd_payload_fragment_data[9 : 0]; + bridge_addressFilter_addresses_0_is10Bit <= io_ctrl_cmd_payload_fragment_data[14]; + end + end + 8'h8c : begin + if(busCtrl_doWrite) begin + bridge_addressFilter_addresses_1_value <= io_ctrl_cmd_payload_fragment_data[9 : 0]; + bridge_addressFilter_addresses_1_is10Bit <= io_ctrl_cmd_payload_fragment_data[14]; + end + end + 8'h50 : begin + if(busCtrl_doWrite) begin + bridge_masterLogic_timer_tLow <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 8'h54 : begin + if(busCtrl_doWrite) begin + bridge_masterLogic_timer_tHigh <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 8'h58 : begin + if(busCtrl_doWrite) begin + bridge_masterLogic_timer_tBuf <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 8'h2c : begin + if(busCtrl_doWrite) begin + _zz_io_config_timeout <= io_ctrl_cmd_payload_fragment_data[19 : 0]; + bridge_timeoutClear <= 1'b1; + end + end + 8'h30 : begin + if(busCtrl_doWrite) begin + _zz_io_config_tsuData <= io_ctrl_cmd_payload_fragment_data[5 : 0]; + end + end + default : begin + end + endcase + end + + always @(posedge clk) begin + if(reset) begin + i2cCtrl_io_internals_inFrame_regNext <= 1'b0; + end else begin + i2cCtrl_io_internals_inFrame_regNext <= i2cCtrl_io_internals_inFrame; + end + end + + +endmodule + +module Axi4PeripheralBmbSpiXdrMasterCtrl ( + input wire io_ctrl_cmd_valid, + output wire io_ctrl_cmd_ready, + input wire io_ctrl_cmd_payload_last, + input wire [0:0] io_ctrl_cmd_payload_fragment_opcode, + input wire [11:0] io_ctrl_cmd_payload_fragment_address, + input wire [1:0] io_ctrl_cmd_payload_fragment_length, + input wire [31:0] io_ctrl_cmd_payload_fragment_data, + input wire [2:0] io_ctrl_cmd_payload_fragment_context, + output wire io_ctrl_rsp_valid, + input wire io_ctrl_rsp_ready, + output wire io_ctrl_rsp_payload_last, + output wire [0:0] io_ctrl_rsp_payload_fragment_opcode, + output wire [31:0] io_ctrl_rsp_payload_fragment_data, + output wire [2:0] io_ctrl_rsp_payload_fragment_context, + output wire [0:0] io_spi_sclk_write, + output wire io_spi_data_0_writeEnable, + input wire [0:0] io_spi_data_0_read, + output wire [0:0] io_spi_data_0_write, + output wire io_spi_data_1_writeEnable, + input wire [0:0] io_spi_data_1_read, + output wire [0:0] io_spi_data_1_write, + output wire io_spi_data_2_writeEnable, + input wire [0:0] io_spi_data_2_read, + output wire [0:0] io_spi_data_2_write, + output wire io_spi_data_3_writeEnable, + input wire [0:0] io_spi_data_3_read, + output wire [0:0] io_spi_data_3_write, + output wire [3:0] io_spi_ss, + output wire system_spi_0_io_interrupt_source, + input wire clk, + input wire reset +); + + wire ctrl_io_rsp_queueWithOccupancy_io_pop_ready; + wire ctrl_io_cmd_ready; + wire ctrl_io_rsp_valid; + wire [7:0] ctrl_io_rsp_payload_data; + wire [0:0] ctrl_io_spi_sclk_write; + wire [3:0] ctrl_io_spi_ss; + wire [0:0] ctrl_io_spi_data_0_write; + wire ctrl_io_spi_data_0_writeEnable; + wire [0:0] ctrl_io_spi_data_1_write; + wire ctrl_io_spi_data_1_writeEnable; + wire [0:0] ctrl_io_spi_data_2_write; + wire ctrl_io_spi_data_2_writeEnable; + wire [0:0] ctrl_io_spi_data_3_write; + wire ctrl_io_spi_data_3_writeEnable; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; + wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy; + wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; + wire ctrl_io_rsp_queueWithOccupancy_io_push_ready; + wire ctrl_io_rsp_queueWithOccupancy_io_pop_valid; + wire [7:0] ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_occupancy; + wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_availability; + wire factory_readErrorFlag; + wire factory_writeErrorFlag; + wire factory_readHaltTrigger; + wire factory_writeHaltTrigger; + wire factory_rsp_valid; + wire factory_rsp_ready; + wire factory_rsp_payload_last; + reg [0:0] factory_rsp_payload_fragment_opcode; + reg [31:0] factory_rsp_payload_fragment_data; + wire [2:0] factory_rsp_payload_fragment_context; + wire _zz_factory_rsp_ready; + reg _zz_factory_rsp_ready_1; + wire _zz_io_ctrl_rsp_valid; + reg _zz_io_ctrl_rsp_valid_1; + reg _zz_io_ctrl_rsp_payload_last; + reg [0:0] _zz_io_ctrl_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_ctrl_rsp_payload_fragment_data; + reg [2:0] _zz_io_ctrl_rsp_payload_fragment_context; + wire when_Stream_l375; + wire factory_askWrite; + wire factory_askRead; + wire io_ctrl_cmd_fire; + wire factory_doWrite; + wire factory_doRead; + wire when_BmbSlaveFactory_l33; + wire when_BmbSlaveFactory_l35; + wire [31:0] mapping_cmdLogic_writeData; + reg mapping_cmdLogic_doRegular; + reg mapping_cmdLogic_doWriteLarge; + reg mapping_cmdLogic_doReadWriteLarge; + wire mapping_cmdLogic_streamUnbuffered_valid; + wire mapping_cmdLogic_streamUnbuffered_ready; + wire mapping_cmdLogic_streamUnbuffered_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_payload_read; + wire mapping_cmdLogic_streamUnbuffered_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_payload_data; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write; + reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; + reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; + wire when_Stream_l375_1; + wire ctrl_io_rsp_toStream_valid; + wire ctrl_io_rsp_toStream_ready; + wire [7:0] ctrl_io_rsp_toStream_payload_data; + reg _zz_io_pop_ready; + reg _zz_io_pop_ready_1; + reg mapping_interruptCtrl_cmdIntEnable; + reg mapping_interruptCtrl_rspIntEnable; + wire mapping_interruptCtrl_cmdInt; + wire mapping_interruptCtrl_rspInt; + wire mapping_interruptCtrl_interrupt; + reg _zz_io_config_kind_cpol; + reg _zz_io_config_kind_cpha; + reg [1:0] _zz_io_config_mod; + reg [11:0] _zz_io_config_sclkToggle; + reg [11:0] _zz_io_config_ss_setup; + reg [11:0] _zz_io_config_ss_hold; + reg [11:0] _zz_io_config_ss_disable; + reg [3:0] _zz_io_config_ss_activeHigh; + wire [1:0] _zz_io_config_kind_cpol_1; + + Axi4PeripheralTopLevel ctrl ( + .io_config_kind_cpol (_zz_io_config_kind_cpol ), //i + .io_config_kind_cpha (_zz_io_config_kind_cpha ), //i + .io_config_sclkToggle (_zz_io_config_sclkToggle[11:0] ), //i + .io_config_mod (_zz_io_config_mod[1:0] ), //i + .io_config_ss_activeHigh (_zz_io_config_ss_activeHigh[3:0] ), //i + .io_config_ss_setup (_zz_io_config_ss_setup[11:0] ), //i + .io_config_ss_hold (_zz_io_config_ss_hold[11:0] ), //i + .io_config_ss_disable (_zz_io_config_ss_disable[11:0] ), //i + .io_cmd_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid ), //i + .io_cmd_ready (ctrl_io_cmd_ready ), //o + .io_cmd_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind ), //i + .io_cmd_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read ), //i + .io_cmd_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write ), //i + .io_cmd_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data[7:0]), //i + .io_rsp_valid (ctrl_io_rsp_valid ), //o + .io_rsp_payload_data (ctrl_io_rsp_payload_data[7:0] ), //o + .io_spi_sclk_write (ctrl_io_spi_sclk_write ), //o + .io_spi_data_0_writeEnable (ctrl_io_spi_data_0_writeEnable ), //o + .io_spi_data_0_read (io_spi_data_0_read ), //i + .io_spi_data_0_write (ctrl_io_spi_data_0_write ), //o + .io_spi_data_1_writeEnable (ctrl_io_spi_data_1_writeEnable ), //o + .io_spi_data_1_read (io_spi_data_1_read ), //i + .io_spi_data_1_write (ctrl_io_spi_data_1_write ), //o + .io_spi_data_2_writeEnable (ctrl_io_spi_data_2_writeEnable ), //o + .io_spi_data_2_read (io_spi_data_2_read ), //i + .io_spi_data_2_write (ctrl_io_spi_data_2_write ), //o + .io_spi_data_3_writeEnable (ctrl_io_spi_data_3_writeEnable ), //o + .io_spi_data_3_read (io_spi_data_3_read ), //i + .io_spi_data_3_write (ctrl_io_spi_data_3_write ), //o + .io_spi_ss (ctrl_io_spi_ss[3:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralStreamFifo_2 mapping_cmdLogic_streamUnbuffered_queueWithAvailability ( + .io_push_valid (mapping_cmdLogic_streamUnbuffered_valid ), //i + .io_push_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready ), //o + .io_push_payload_kind (mapping_cmdLogic_streamUnbuffered_payload_kind ), //i + .io_push_payload_read (mapping_cmdLogic_streamUnbuffered_payload_read ), //i + .io_push_payload_write (mapping_cmdLogic_streamUnbuffered_payload_write ), //i + .io_push_payload_data (mapping_cmdLogic_streamUnbuffered_payload_data[7:0] ), //i + .io_pop_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid ), //o + .io_pop_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ), //i + .io_pop_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind ), //o + .io_pop_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read ), //o + .io_pop_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write ), //o + .io_pop_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data[7:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy[8:0] ), //o + .io_availability (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability[8:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralStreamFifo_3 ctrl_io_rsp_queueWithOccupancy ( + .io_push_valid (ctrl_io_rsp_toStream_valid ), //i + .io_push_ready (ctrl_io_rsp_queueWithOccupancy_io_push_ready ), //o + .io_push_payload_data (ctrl_io_rsp_toStream_payload_data[7:0] ), //i + .io_pop_valid (ctrl_io_rsp_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (ctrl_io_rsp_queueWithOccupancy_io_pop_ready ), //i + .io_pop_payload_data (ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data[7:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (ctrl_io_rsp_queueWithOccupancy_io_occupancy[8:0] ), //o + .io_availability (ctrl_io_rsp_queueWithOccupancy_io_availability[8:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + assign factory_readErrorFlag = 1'b0; + assign factory_writeErrorFlag = 1'b0; + assign factory_readHaltTrigger = 1'b0; + assign factory_writeHaltTrigger = 1'b0; + assign _zz_factory_rsp_ready = (! (factory_readHaltTrigger || factory_writeHaltTrigger)); + assign factory_rsp_ready = (_zz_factory_rsp_ready_1 && _zz_factory_rsp_ready); + always @(*) begin + _zz_factory_rsp_ready_1 = io_ctrl_rsp_ready; + if(when_Stream_l375) begin + _zz_factory_rsp_ready_1 = 1'b1; + end + end + + assign when_Stream_l375 = (! _zz_io_ctrl_rsp_valid); + assign _zz_io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid_1; + assign io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid; + assign io_ctrl_rsp_payload_last = _zz_io_ctrl_rsp_payload_last; + assign io_ctrl_rsp_payload_fragment_opcode = _zz_io_ctrl_rsp_payload_fragment_opcode; + assign io_ctrl_rsp_payload_fragment_data = _zz_io_ctrl_rsp_payload_fragment_data; + assign io_ctrl_rsp_payload_fragment_context = _zz_io_ctrl_rsp_payload_fragment_context; + assign factory_askWrite = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign factory_askRead = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign io_ctrl_cmd_fire = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); + assign factory_doWrite = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign factory_doRead = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign factory_rsp_valid = io_ctrl_cmd_valid; + assign io_ctrl_cmd_ready = factory_rsp_ready; + assign factory_rsp_payload_last = 1'b1; + assign when_BmbSlaveFactory_l33 = (factory_doWrite && factory_writeErrorFlag); + always @(*) begin + if(when_BmbSlaveFactory_l33) begin + factory_rsp_payload_fragment_opcode = 1'b1; + end else begin + if(when_BmbSlaveFactory_l35) begin + factory_rsp_payload_fragment_opcode = 1'b1; + end else begin + factory_rsp_payload_fragment_opcode = 1'b0; + end + end + end + + assign when_BmbSlaveFactory_l35 = (factory_doRead && factory_readErrorFlag); + always @(*) begin + factory_rsp_payload_fragment_data = 32'h0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + factory_rsp_payload_fragment_data[31 : 31] = (! ctrl_io_rsp_queueWithOccupancy_io_pop_valid); + factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + end + 12'h004 : begin + factory_rsp_payload_fragment_data[8 : 0] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; + factory_rsp_payload_fragment_data[24 : 16] = ctrl_io_rsp_queueWithOccupancy_io_occupancy; + end + 12'h00c : begin + factory_rsp_payload_fragment_data[16 : 16] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; + factory_rsp_payload_fragment_data[0 : 0] = mapping_interruptCtrl_cmdIntEnable; + factory_rsp_payload_fragment_data[1 : 1] = mapping_interruptCtrl_rspIntEnable; + factory_rsp_payload_fragment_data[8 : 8] = mapping_interruptCtrl_cmdInt; + factory_rsp_payload_fragment_data[9 : 9] = mapping_interruptCtrl_rspInt; + end + 12'h058 : begin + factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + end + default : begin + end + endcase + end + + assign factory_rsp_payload_fragment_context = io_ctrl_cmd_payload_fragment_context; + always @(*) begin + mapping_cmdLogic_doRegular = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doRegular = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + mapping_cmdLogic_doWriteLarge = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h050 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doWriteLarge = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + mapping_cmdLogic_doReadWriteLarge = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h054 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doReadWriteLarge = 1'b1; + end + end + default : begin + end + endcase + end + + assign mapping_cmdLogic_streamUnbuffered_valid = ((mapping_cmdLogic_doRegular || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_write = (((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[8]) || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_read = ((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[9]) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_kind = (mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[11]); + assign mapping_cmdLogic_streamUnbuffered_payload_data = mapping_cmdLogic_writeData[7:0]; + assign mapping_cmdLogic_streamUnbuffered_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid || (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN)); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data); + always @(*) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; + if(when_Stream_l375_1) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375_1 = (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready = ctrl_io_cmd_ready; + assign ctrl_io_rsp_toStream_valid = ctrl_io_rsp_valid; + assign ctrl_io_rsp_toStream_payload_data = ctrl_io_rsp_payload_data; + assign ctrl_io_rsp_toStream_ready = ctrl_io_rsp_queueWithOccupancy_io_push_ready; + always @(*) begin + _zz_io_pop_ready = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + if(factory_doRead) begin + _zz_io_pop_ready = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + _zz_io_pop_ready_1 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h058 : begin + if(factory_doRead) begin + _zz_io_pop_ready_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign ctrl_io_rsp_queueWithOccupancy_io_pop_ready = (_zz_io_pop_ready || _zz_io_pop_ready_1); + assign mapping_interruptCtrl_cmdInt = (mapping_interruptCtrl_cmdIntEnable && (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid)); + assign mapping_interruptCtrl_rspInt = (mapping_interruptCtrl_rspIntEnable && ctrl_io_rsp_queueWithOccupancy_io_pop_valid); + assign mapping_interruptCtrl_interrupt = (mapping_interruptCtrl_rspInt || mapping_interruptCtrl_cmdInt); + assign io_spi_sclk_write = ctrl_io_spi_sclk_write; + assign io_spi_data_0_writeEnable = ctrl_io_spi_data_0_writeEnable; + assign io_spi_data_0_write = ctrl_io_spi_data_0_write; + assign io_spi_data_1_writeEnable = ctrl_io_spi_data_1_writeEnable; + assign io_spi_data_1_write = ctrl_io_spi_data_1_write; + assign io_spi_data_2_writeEnable = ctrl_io_spi_data_2_writeEnable; + assign io_spi_data_2_write = ctrl_io_spi_data_2_write; + assign io_spi_data_3_writeEnable = ctrl_io_spi_data_3_writeEnable; + assign io_spi_data_3_write = ctrl_io_spi_data_3_write; + assign io_spi_ss = ctrl_io_spi_ss; + assign system_spi_0_io_interrupt_source = mapping_interruptCtrl_interrupt; + assign mapping_cmdLogic_writeData = io_ctrl_cmd_payload_fragment_data[31 : 0]; + assign _zz_io_config_kind_cpol_1 = io_ctrl_cmd_payload_fragment_data[1 : 0]; + always @(posedge clk) begin + if(reset) begin + _zz_io_ctrl_rsp_valid_1 <= 1'b0; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN <= 1'b1; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= 1'b0; + mapping_interruptCtrl_cmdIntEnable <= 1'b0; + mapping_interruptCtrl_rspIntEnable <= 1'b0; + _zz_io_config_ss_activeHigh <= 4'b0000; + end else begin + if(_zz_factory_rsp_ready_1) begin + _zz_io_ctrl_rsp_valid_1 <= (factory_rsp_valid && _zz_factory_rsp_ready); + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN <= 1'b0; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN <= 1'b1; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; + end + case(io_ctrl_cmd_payload_fragment_address) + 12'h00c : begin + if(factory_doWrite) begin + mapping_interruptCtrl_cmdIntEnable <= io_ctrl_cmd_payload_fragment_data[0]; + mapping_interruptCtrl_rspIntEnable <= io_ctrl_cmd_payload_fragment_data[1]; + end + end + 12'h030 : begin + if(factory_doWrite) begin + _zz_io_config_ss_activeHigh <= io_ctrl_cmd_payload_fragment_data[3 : 0]; + end + end + default : begin + end + endcase + end + end + + always @(posedge clk) begin + if(_zz_factory_rsp_ready_1) begin + _zz_io_ctrl_rsp_payload_last <= factory_rsp_payload_last; + _zz_io_ctrl_rsp_payload_fragment_opcode <= factory_rsp_payload_fragment_opcode; + _zz_io_ctrl_rsp_payload_fragment_data <= factory_rsp_payload_fragment_data; + _zz_io_ctrl_rsp_payload_fragment_context <= factory_rsp_payload_fragment_context; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; + end + case(io_ctrl_cmd_payload_fragment_address) + 12'h008 : begin + if(factory_doWrite) begin + _zz_io_config_kind_cpol <= _zz_io_config_kind_cpol_1[0]; + _zz_io_config_kind_cpha <= _zz_io_config_kind_cpol_1[1]; + _zz_io_config_mod <= io_ctrl_cmd_payload_fragment_data[5 : 4]; + end + end + 12'h020 : begin + if(factory_doWrite) begin + _zz_io_config_sclkToggle <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h024 : begin + if(factory_doWrite) begin + _zz_io_config_ss_setup <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h028 : begin + if(factory_doWrite) begin + _zz_io_config_ss_hold <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h02c : begin + if(factory_doWrite) begin + _zz_io_config_ss_disable <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + default : begin + end + endcase + end + + +endmodule + +module Axi4PeripheralBmbUartCtrl ( + input wire io_bus_cmd_valid, + output wire io_bus_cmd_ready, + input wire io_bus_cmd_payload_last, + input wire [0:0] io_bus_cmd_payload_fragment_opcode, + input wire [5:0] io_bus_cmd_payload_fragment_address, + input wire [1:0] io_bus_cmd_payload_fragment_length, + input wire [31:0] io_bus_cmd_payload_fragment_data, + input wire [2:0] io_bus_cmd_payload_fragment_context, + output wire io_bus_rsp_valid, + input wire io_bus_rsp_ready, + output wire io_bus_rsp_payload_last, + output wire [0:0] io_bus_rsp_payload_fragment_opcode, + output wire [31:0] io_bus_rsp_payload_fragment_data, + output wire [2:0] io_bus_rsp_payload_fragment_context, + output wire io_uart_txd, + input wire io_uart_rxd, + output wire system_uart_0_io_interrupt_source, + input wire clk, + input wire reset +); + localparam Axi4PeripheralUartStopType_ONE = 1'd0; + localparam Axi4PeripheralUartStopType_TWO = 1'd1; + localparam Axi4PeripheralUartParityType_NONE = 2'd0; + localparam Axi4PeripheralUartParityType_EVEN = 2'd1; + localparam Axi4PeripheralUartParityType_ODD = 2'd2; + + reg uartCtrl_io_read_queueWithOccupancy_io_pop_ready; + wire uartCtrl_io_write_ready; + wire uartCtrl_io_read_valid; + wire [7:0] uartCtrl_io_read_payload; + wire uartCtrl_io_uart_txd; + wire uartCtrl_io_readError; + wire uartCtrl_io_readBreak; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_availability; + wire uartCtrl_io_read_queueWithOccupancy_io_push_ready; + wire uartCtrl_io_read_queueWithOccupancy_io_pop_valid; + wire [7:0] uartCtrl_io_read_queueWithOccupancy_io_pop_payload; + wire [7:0] uartCtrl_io_read_queueWithOccupancy_io_occupancy; + wire [7:0] uartCtrl_io_read_queueWithOccupancy_io_availability; + wire [0:0] _zz_bridge_misc_readError; + wire [0:0] _zz_bridge_misc_readOverflowError; + wire [0:0] _zz_bridge_misc_breakDetected; + wire [0:0] _zz_bridge_misc_doBreak; + wire [0:0] _zz_bridge_misc_doBreak_1; + wire [7:0] _zz_busCtrl_rsp_payload_fragment_data; + wire busCtrl_readErrorFlag; + wire busCtrl_writeErrorFlag; + wire busCtrl_readHaltTrigger; + wire busCtrl_writeHaltTrigger; + wire busCtrl_rsp_valid; + wire busCtrl_rsp_ready; + wire busCtrl_rsp_payload_last; + reg [0:0] busCtrl_rsp_payload_fragment_opcode; + reg [31:0] busCtrl_rsp_payload_fragment_data; + wire [2:0] busCtrl_rsp_payload_fragment_context; + wire _zz_busCtrl_rsp_ready; + reg _zz_busCtrl_rsp_ready_1; + wire _zz_io_bus_rsp_valid; + reg _zz_io_bus_rsp_valid_1; + reg _zz_io_bus_rsp_payload_last; + reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_bus_rsp_payload_fragment_data; + reg [2:0] _zz_io_bus_rsp_payload_fragment_context; + wire when_Stream_l375; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire io_bus_cmd_fire; + wire busCtrl_doWrite; + wire busCtrl_doRead; + wire when_BmbSlaveFactory_l33; + wire when_BmbSlaveFactory_l35; + wire bridge_busCtrlWrapped_readErrorFlag; + wire bridge_busCtrlWrapped_writeErrorFlag; + reg [2:0] bridge_uartConfigReg_frame_dataLength; + reg [0:0] bridge_uartConfigReg_frame_stop; + reg [1:0] bridge_uartConfigReg_frame_parity; + reg [19:0] bridge_uartConfigReg_clockDivider; + reg _zz_bridge_write_streamUnbuffered_valid; + wire bridge_write_streamUnbuffered_valid; + wire bridge_write_streamUnbuffered_ready; + wire [7:0] bridge_write_streamUnbuffered_payload; + reg bridge_read_streamBreaked_valid; + reg bridge_read_streamBreaked_ready; + wire [7:0] bridge_read_streamBreaked_payload; + reg bridge_interruptCtrl_writeIntEnable; + reg bridge_interruptCtrl_readIntEnable; + wire bridge_interruptCtrl_readInt; + wire bridge_interruptCtrl_writeInt; + wire bridge_interruptCtrl_interrupt; + reg bridge_misc_readError; + reg when_BusSlaveFactory_l341; + wire when_BusSlaveFactory_l347; + reg bridge_misc_readOverflowError; + reg when_BusSlaveFactory_l341_1; + wire when_BusSlaveFactory_l347_1; + wire uartCtrl_io_read_isStall; + reg bridge_misc_breakDetected; + reg uartCtrl_io_readBreak_regNext; + wire when_UartCtrl_l155; + reg when_BusSlaveFactory_l341_2; + wire when_BusSlaveFactory_l347_2; + reg bridge_misc_doBreak; + reg when_BusSlaveFactory_l377; + wire when_BusSlaveFactory_l379; + reg when_BusSlaveFactory_l341_3; + wire when_BusSlaveFactory_l347_3; + wire [1:0] _zz_bridge_uartConfigReg_frame_parity; + wire [0:0] _zz_bridge_uartConfigReg_frame_stop; + wire when_BmbSlaveFactory_l77; + `ifndef SYNTHESIS + reg [23:0] bridge_uartConfigReg_frame_stop_string; + reg [31:0] bridge_uartConfigReg_frame_parity_string; + reg [31:0] _zz_bridge_uartConfigReg_frame_parity_string; + reg [23:0] _zz_bridge_uartConfigReg_frame_stop_string; + `endif + + + assign _zz_bridge_misc_readError = 1'b0; + assign _zz_bridge_misc_readOverflowError = 1'b0; + assign _zz_bridge_misc_breakDetected = 1'b0; + assign _zz_bridge_misc_doBreak = 1'b1; + assign _zz_bridge_misc_doBreak_1 = 1'b0; + assign _zz_busCtrl_rsp_payload_fragment_data = (8'h80 - bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy); + Axi4PeripheralUartCtrl uartCtrl ( + .io_config_frame_dataLength (bridge_uartConfigReg_frame_dataLength[2:0] ), //i + .io_config_frame_stop (bridge_uartConfigReg_frame_stop ), //i + .io_config_frame_parity (bridge_uartConfigReg_frame_parity[1:0] ), //i + .io_config_clockDivider (bridge_uartConfigReg_clockDivider[19:0] ), //i + .io_write_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //i + .io_write_ready (uartCtrl_io_write_ready ), //o + .io_write_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0]), //i + .io_read_valid (uartCtrl_io_read_valid ), //o + .io_read_ready (uartCtrl_io_read_queueWithOccupancy_io_push_ready ), //i + .io_read_payload (uartCtrl_io_read_payload[7:0] ), //o + .io_uart_txd (uartCtrl_io_uart_txd ), //o + .io_uart_rxd (io_uart_rxd ), //i + .io_readError (uartCtrl_io_readError ), //o + .io_writeBreak (bridge_misc_doBreak ), //i + .io_readBreak (uartCtrl_io_readBreak ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralStreamFifo bridge_write_streamUnbuffered_queueWithOccupancy ( + .io_push_valid (bridge_write_streamUnbuffered_valid ), //i + .io_push_ready (bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready ), //o + .io_push_payload (bridge_write_streamUnbuffered_payload[7:0] ), //i + .io_pop_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (uartCtrl_io_write_ready ), //i + .io_pop_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy[7:0] ), //o + .io_availability (bridge_write_streamUnbuffered_queueWithOccupancy_io_availability[7:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralStreamFifo uartCtrl_io_read_queueWithOccupancy ( + .io_push_valid (uartCtrl_io_read_valid ), //i + .io_push_ready (uartCtrl_io_read_queueWithOccupancy_io_push_ready ), //o + .io_push_payload (uartCtrl_io_read_payload[7:0] ), //i + .io_pop_valid (uartCtrl_io_read_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (uartCtrl_io_read_queueWithOccupancy_io_pop_ready ), //i + .io_pop_payload (uartCtrl_io_read_queueWithOccupancy_io_pop_payload[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (uartCtrl_io_read_queueWithOccupancy_io_occupancy[7:0] ), //o + .io_availability (uartCtrl_io_read_queueWithOccupancy_io_availability[7:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(bridge_uartConfigReg_frame_stop) + Axi4PeripheralUartStopType_ONE : bridge_uartConfigReg_frame_stop_string = "ONE"; + Axi4PeripheralUartStopType_TWO : bridge_uartConfigReg_frame_stop_string = "TWO"; + default : bridge_uartConfigReg_frame_stop_string = "???"; + endcase + end + always @(*) begin + case(bridge_uartConfigReg_frame_parity) + Axi4PeripheralUartParityType_NONE : bridge_uartConfigReg_frame_parity_string = "NONE"; + Axi4PeripheralUartParityType_EVEN : bridge_uartConfigReg_frame_parity_string = "EVEN"; + Axi4PeripheralUartParityType_ODD : bridge_uartConfigReg_frame_parity_string = "ODD "; + default : bridge_uartConfigReg_frame_parity_string = "????"; + endcase + end + always @(*) begin + case(_zz_bridge_uartConfigReg_frame_parity) + Axi4PeripheralUartParityType_NONE : _zz_bridge_uartConfigReg_frame_parity_string = "NONE"; + Axi4PeripheralUartParityType_EVEN : _zz_bridge_uartConfigReg_frame_parity_string = "EVEN"; + Axi4PeripheralUartParityType_ODD : _zz_bridge_uartConfigReg_frame_parity_string = "ODD "; + default : _zz_bridge_uartConfigReg_frame_parity_string = "????"; + endcase + end + always @(*) begin + case(_zz_bridge_uartConfigReg_frame_stop) + Axi4PeripheralUartStopType_ONE : _zz_bridge_uartConfigReg_frame_stop_string = "ONE"; + Axi4PeripheralUartStopType_TWO : _zz_bridge_uartConfigReg_frame_stop_string = "TWO"; + default : _zz_bridge_uartConfigReg_frame_stop_string = "???"; + endcase + end + `endif + + assign io_uart_txd = uartCtrl_io_uart_txd; + assign busCtrl_readErrorFlag = 1'b0; + assign busCtrl_writeErrorFlag = 1'b0; + assign busCtrl_readHaltTrigger = 1'b0; + assign busCtrl_writeHaltTrigger = 1'b0; + assign _zz_busCtrl_rsp_ready = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); + assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready_1 && _zz_busCtrl_rsp_ready); + always @(*) begin + _zz_busCtrl_rsp_ready_1 = io_bus_rsp_ready; + if(when_Stream_l375) begin + _zz_busCtrl_rsp_ready_1 = 1'b1; + end + end + + assign when_Stream_l375 = (! _zz_io_bus_rsp_valid); + assign _zz_io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; + assign io_bus_rsp_valid = _zz_io_bus_rsp_valid; + assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; + assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; + assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; + assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; + assign busCtrl_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign busCtrl_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_doRead = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign busCtrl_rsp_valid = io_bus_cmd_valid; + assign io_bus_cmd_ready = busCtrl_rsp_ready; + assign busCtrl_rsp_payload_last = 1'b1; + assign when_BmbSlaveFactory_l33 = (busCtrl_doWrite && busCtrl_writeErrorFlag); + always @(*) begin + if(when_BmbSlaveFactory_l33) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + if(when_BmbSlaveFactory_l35) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + busCtrl_rsp_payload_fragment_opcode = 1'b0; + end + end + end + + assign when_BmbSlaveFactory_l35 = (busCtrl_doRead && busCtrl_readErrorFlag); + always @(*) begin + busCtrl_rsp_payload_fragment_data = 32'h0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + busCtrl_rsp_payload_fragment_data[16 : 16] = (bridge_read_streamBreaked_valid ^ 1'b0); + busCtrl_rsp_payload_fragment_data[7 : 0] = bridge_read_streamBreaked_payload; + end + 6'h04 : begin + busCtrl_rsp_payload_fragment_data[23 : 16] = _zz_busCtrl_rsp_payload_fragment_data; + busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; + busCtrl_rsp_payload_fragment_data[31 : 24] = uartCtrl_io_read_queueWithOccupancy_io_occupancy; + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_interruptCtrl_writeIntEnable; + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_interruptCtrl_readIntEnable; + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_interruptCtrl_writeInt; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_interruptCtrl_readInt; + end + 6'h10 : begin + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_misc_readError; + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_misc_readOverflowError; + busCtrl_rsp_payload_fragment_data[8 : 8] = uartCtrl_io_readBreak; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_misc_breakDetected; + end + default : begin + end + endcase + end + + assign busCtrl_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; + assign bridge_busCtrlWrapped_readErrorFlag = 1'b0; + assign bridge_busCtrlWrapped_writeErrorFlag = 1'b0; + always @(*) begin + _zz_bridge_write_streamUnbuffered_valid = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + if(busCtrl_doWrite) begin + _zz_bridge_write_streamUnbuffered_valid = 1'b1; + end + end + default : begin + end + endcase + end + + assign bridge_write_streamUnbuffered_valid = _zz_bridge_write_streamUnbuffered_valid; + assign bridge_write_streamUnbuffered_payload = io_bus_cmd_payload_fragment_data[7 : 0]; + assign bridge_write_streamUnbuffered_ready = bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + always @(*) begin + bridge_read_streamBreaked_valid = uartCtrl_io_read_queueWithOccupancy_io_pop_valid; + if(uartCtrl_io_readBreak) begin + bridge_read_streamBreaked_valid = 1'b0; + end + end + + always @(*) begin + uartCtrl_io_read_queueWithOccupancy_io_pop_ready = bridge_read_streamBreaked_ready; + if(uartCtrl_io_readBreak) begin + uartCtrl_io_read_queueWithOccupancy_io_pop_ready = 1'b1; + end + end + + assign bridge_read_streamBreaked_payload = uartCtrl_io_read_queueWithOccupancy_io_pop_payload; + always @(*) begin + bridge_read_streamBreaked_ready = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + if(busCtrl_doRead) begin + bridge_read_streamBreaked_ready = 1'b1; + end + end + default : begin + end + endcase + end + + assign bridge_interruptCtrl_readInt = (bridge_interruptCtrl_readIntEnable && bridge_read_streamBreaked_valid); + assign bridge_interruptCtrl_writeInt = (bridge_interruptCtrl_writeIntEnable && (! bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid)); + assign bridge_interruptCtrl_interrupt = (bridge_interruptCtrl_readInt || bridge_interruptCtrl_writeInt); + always @(*) begin + when_BusSlaveFactory_l341 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347 = io_bus_cmd_payload_fragment_data[0]; + always @(*) begin + when_BusSlaveFactory_l341_1 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_1 = io_bus_cmd_payload_fragment_data[1]; + assign uartCtrl_io_read_isStall = (uartCtrl_io_read_valid && (! uartCtrl_io_read_queueWithOccupancy_io_push_ready)); + assign when_UartCtrl_l155 = (uartCtrl_io_readBreak && (! uartCtrl_io_readBreak_regNext)); + always @(*) begin + when_BusSlaveFactory_l341_2 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_2 = io_bus_cmd_payload_fragment_data[9]; + always @(*) begin + when_BusSlaveFactory_l377 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l377 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379 = io_bus_cmd_payload_fragment_data[10]; + always @(*) begin + when_BusSlaveFactory_l341_3 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_3 = io_bus_cmd_payload_fragment_data[11]; + assign system_uart_0_io_interrupt_source = bridge_interruptCtrl_interrupt; + assign _zz_bridge_uartConfigReg_frame_parity = io_bus_cmd_payload_fragment_data[9 : 8]; + assign _zz_bridge_uartConfigReg_frame_stop = io_bus_cmd_payload_fragment_data[16 : 16]; + assign when_BmbSlaveFactory_l77 = ((io_bus_cmd_payload_fragment_address & (~ 6'h03)) == 6'h08); + always @(posedge clk) begin + if(reset) begin + _zz_io_bus_rsp_valid_1 <= 1'b0; + bridge_uartConfigReg_clockDivider <= 20'h0; + bridge_uartConfigReg_clockDivider <= 20'h000d8; + bridge_uartConfigReg_frame_dataLength <= 3'b111; + bridge_uartConfigReg_frame_parity <= Axi4PeripheralUartParityType_NONE; + bridge_uartConfigReg_frame_stop <= Axi4PeripheralUartStopType_ONE; + bridge_interruptCtrl_writeIntEnable <= 1'b0; + bridge_interruptCtrl_readIntEnable <= 1'b0; + bridge_misc_readError <= 1'b0; + bridge_misc_readOverflowError <= 1'b0; + bridge_misc_breakDetected <= 1'b0; + bridge_misc_doBreak <= 1'b0; + end else begin + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_bus_rsp_valid_1 <= (busCtrl_rsp_valid && _zz_busCtrl_rsp_ready); + end + if(when_BusSlaveFactory_l341) begin + if(when_BusSlaveFactory_l347) begin + bridge_misc_readError <= _zz_bridge_misc_readError[0]; + end + end + if(uartCtrl_io_readError) begin + bridge_misc_readError <= 1'b1; + end + if(when_BusSlaveFactory_l341_1) begin + if(when_BusSlaveFactory_l347_1) begin + bridge_misc_readOverflowError <= _zz_bridge_misc_readOverflowError[0]; + end + end + if(uartCtrl_io_read_isStall) begin + bridge_misc_readOverflowError <= 1'b1; + end + if(when_UartCtrl_l155) begin + bridge_misc_breakDetected <= 1'b1; + end + if(when_BusSlaveFactory_l341_2) begin + if(when_BusSlaveFactory_l347_2) begin + bridge_misc_breakDetected <= _zz_bridge_misc_breakDetected[0]; + end + end + if(when_BusSlaveFactory_l377) begin + if(when_BusSlaveFactory_l379) begin + bridge_misc_doBreak <= _zz_bridge_misc_doBreak[0]; + end + end + if(when_BusSlaveFactory_l341_3) begin + if(when_BusSlaveFactory_l347_3) begin + bridge_misc_doBreak <= _zz_bridge_misc_doBreak_1[0]; + end + end + case(io_bus_cmd_payload_fragment_address) + 6'h0c : begin + if(busCtrl_doWrite) begin + bridge_uartConfigReg_frame_dataLength <= io_bus_cmd_payload_fragment_data[2 : 0]; + bridge_uartConfigReg_frame_parity <= _zz_bridge_uartConfigReg_frame_parity; + bridge_uartConfigReg_frame_stop <= _zz_bridge_uartConfigReg_frame_stop; + end + end + 6'h04 : begin + if(busCtrl_doWrite) begin + bridge_interruptCtrl_writeIntEnable <= io_bus_cmd_payload_fragment_data[0]; + bridge_interruptCtrl_readIntEnable <= io_bus_cmd_payload_fragment_data[1]; + end + end + default : begin + end + endcase + if(when_BmbSlaveFactory_l77) begin + if(busCtrl_doWrite) begin + bridge_uartConfigReg_clockDivider[19 : 0] <= io_bus_cmd_payload_fragment_data[19 : 0]; + end + end + end + end + + always @(posedge clk) begin + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_bus_rsp_payload_last <= busCtrl_rsp_payload_last; + _zz_io_bus_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; + _zz_io_bus_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; + _zz_io_bus_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; + end + uartCtrl_io_readBreak_regNext <= uartCtrl_io_readBreak; + end + + +endmodule + +module Axi4PeripheralBmbDecoder_1 ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [23:0] io_input_cmd_payload_fragment_address, + input wire [1:0] io_input_cmd_payload_fragment_length, + input wire [31:0] io_input_cmd_payload_fragment_data, + input wire [3:0] io_input_cmd_payload_fragment_mask, + input wire [2:0] io_input_cmd_payload_fragment_context, + output reg io_input_rsp_valid, + input wire io_input_rsp_ready, + output reg io_input_rsp_payload_last, + output reg [0:0] io_input_rsp_payload_fragment_opcode, + output wire [31:0] io_input_rsp_payload_fragment_data, + output reg [2:0] io_input_rsp_payload_fragment_context, + output reg io_outputs_0_cmd_valid, + input wire io_outputs_0_cmd_ready, + output wire io_outputs_0_cmd_payload_last, + output wire [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_0_cmd_payload_fragment_address, + output wire [1:0] io_outputs_0_cmd_payload_fragment_length, + output wire [31:0] io_outputs_0_cmd_payload_fragment_data, + output wire [3:0] io_outputs_0_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_0_cmd_payload_fragment_context, + input wire io_outputs_0_rsp_valid, + output wire io_outputs_0_rsp_ready, + input wire io_outputs_0_rsp_payload_last, + input wire [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_0_rsp_payload_fragment_data, + input wire [2:0] io_outputs_0_rsp_payload_fragment_context, + output reg io_outputs_1_cmd_valid, + input wire io_outputs_1_cmd_ready, + output wire io_outputs_1_cmd_payload_last, + output wire [0:0] io_outputs_1_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_1_cmd_payload_fragment_address, + output wire [1:0] io_outputs_1_cmd_payload_fragment_length, + output wire [31:0] io_outputs_1_cmd_payload_fragment_data, + output wire [3:0] io_outputs_1_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_1_cmd_payload_fragment_context, + input wire io_outputs_1_rsp_valid, + output wire io_outputs_1_rsp_ready, + input wire io_outputs_1_rsp_payload_last, + input wire [0:0] io_outputs_1_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_1_rsp_payload_fragment_data, + input wire [2:0] io_outputs_1_rsp_payload_fragment_context, + output reg io_outputs_2_cmd_valid, + input wire io_outputs_2_cmd_ready, + output wire io_outputs_2_cmd_payload_last, + output wire [0:0] io_outputs_2_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_2_cmd_payload_fragment_address, + output wire [1:0] io_outputs_2_cmd_payload_fragment_length, + output wire [31:0] io_outputs_2_cmd_payload_fragment_data, + output wire [3:0] io_outputs_2_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_2_cmd_payload_fragment_context, + input wire io_outputs_2_rsp_valid, + output wire io_outputs_2_rsp_ready, + input wire io_outputs_2_rsp_payload_last, + input wire [0:0] io_outputs_2_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_2_rsp_payload_fragment_data, + input wire [2:0] io_outputs_2_rsp_payload_fragment_context, + output reg io_outputs_3_cmd_valid, + input wire io_outputs_3_cmd_ready, + output wire io_outputs_3_cmd_payload_last, + output wire [0:0] io_outputs_3_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_3_cmd_payload_fragment_address, + output wire [1:0] io_outputs_3_cmd_payload_fragment_length, + output wire [31:0] io_outputs_3_cmd_payload_fragment_data, + output wire [3:0] io_outputs_3_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_3_cmd_payload_fragment_context, + input wire io_outputs_3_rsp_valid, + output wire io_outputs_3_rsp_ready, + input wire io_outputs_3_rsp_payload_last, + input wire [0:0] io_outputs_3_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_3_rsp_payload_fragment_data, + input wire [2:0] io_outputs_3_rsp_payload_fragment_context, + output reg io_outputs_4_cmd_valid, + input wire io_outputs_4_cmd_ready, + output wire io_outputs_4_cmd_payload_last, + output wire [0:0] io_outputs_4_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_4_cmd_payload_fragment_address, + output wire [1:0] io_outputs_4_cmd_payload_fragment_length, + output wire [31:0] io_outputs_4_cmd_payload_fragment_data, + output wire [3:0] io_outputs_4_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_4_cmd_payload_fragment_context, + input wire io_outputs_4_rsp_valid, + output wire io_outputs_4_rsp_ready, + input wire io_outputs_4_rsp_payload_last, + input wire [0:0] io_outputs_4_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_4_rsp_payload_fragment_data, + input wire [2:0] io_outputs_4_rsp_payload_fragment_context, + output reg io_outputs_5_cmd_valid, + input wire io_outputs_5_cmd_ready, + output wire io_outputs_5_cmd_payload_last, + output wire [0:0] io_outputs_5_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_5_cmd_payload_fragment_address, + output wire [1:0] io_outputs_5_cmd_payload_fragment_length, + output wire [31:0] io_outputs_5_cmd_payload_fragment_data, + output wire [3:0] io_outputs_5_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_5_cmd_payload_fragment_context, + input wire io_outputs_5_rsp_valid, + output wire io_outputs_5_rsp_ready, + input wire io_outputs_5_rsp_payload_last, + input wire [0:0] io_outputs_5_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_5_rsp_payload_fragment_data, + input wire [2:0] io_outputs_5_rsp_payload_fragment_context, + input wire clk, + input wire reset +); + + wire [6:0] _zz_logic_rspPendingCounter; + wire [6:0] _zz_logic_rspPendingCounter_1; + wire [0:0] _zz_logic_rspPendingCounter_2; + wire [6:0] _zz_logic_rspPendingCounter_3; + wire [0:0] _zz_logic_rspPendingCounter_4; + reg _zz_io_input_rsp_payload_last_4; + reg [0:0] _zz_io_input_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_input_rsp_payload_fragment_data; + reg [2:0] _zz_io_input_rsp_payload_fragment_context; + wire logic_input_valid; + reg logic_input_ready; + wire logic_input_payload_last; + wire [0:0] logic_input_payload_fragment_opcode; + wire [23:0] logic_input_payload_fragment_address; + wire [1:0] logic_input_payload_fragment_length; + wire [31:0] logic_input_payload_fragment_data; + wire [3:0] logic_input_payload_fragment_mask; + wire [2:0] logic_input_payload_fragment_context; + wire logic_hitsS0_0; + wire logic_hitsS0_1; + wire logic_hitsS0_2; + wire logic_hitsS0_3; + wire logic_hitsS0_4; + wire logic_hitsS0_5; + wire logic_noHitS0; + wire _zz_io_outputs_0_cmd_payload_last; + wire _zz_io_outputs_1_cmd_payload_last; + wire _zz_io_outputs_2_cmd_payload_last; + wire _zz_io_outputs_3_cmd_payload_last; + wire _zz_io_outputs_4_cmd_payload_last; + wire _zz_io_outputs_5_cmd_payload_last; + reg [6:0] logic_rspPendingCounter; + wire logic_input_fire; + wire io_input_rsp_fire; + wire logic_cmdWait; + wire when_BmbDecoder_l56; + reg logic_rspHits_0; + reg logic_rspHits_1; + reg logic_rspHits_2; + reg logic_rspHits_3; + reg logic_rspHits_4; + reg logic_rspHits_5; + wire logic_rspPending; + wire logic_rspNoHitValid; + reg logic_rspNoHit_doIt; + wire when_BmbDecoder_l60; + wire when_BmbDecoder_l60_1; + reg logic_rspNoHit_singleBeatRsp; + reg [2:0] logic_rspNoHit_context; + wire _zz_io_input_rsp_payload_last; + wire _zz_io_input_rsp_payload_last_1; + wire _zz_io_input_rsp_payload_last_2; + wire [2:0] _zz_io_input_rsp_payload_last_3; + + assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); + assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); + assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; + assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; + always @(*) begin + case(_zz_io_input_rsp_payload_last_3) + 3'b000 : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_0_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_0_rsp_payload_fragment_context; + end + 3'b001 : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_1_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_1_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_1_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_1_rsp_payload_fragment_context; + end + 3'b010 : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_2_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_2_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_2_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_2_rsp_payload_fragment_context; + end + 3'b011 : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_3_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_3_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_3_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_3_rsp_payload_fragment_context; + end + 3'b100 : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_4_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_4_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_4_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_4_rsp_payload_fragment_context; + end + default : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_5_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_5_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_5_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_5_rsp_payload_fragment_context; + end + endcase + end + + assign logic_input_valid = io_input_cmd_valid; + assign io_input_cmd_ready = logic_input_ready; + assign logic_input_payload_last = io_input_cmd_payload_last; + assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign logic_input_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign logic_noHitS0 = (! (|{logic_hitsS0_5,{logic_hitsS0_4,{logic_hitsS0_3,{logic_hitsS0_2,{logic_hitsS0_1,logic_hitsS0_0}}}}})); + assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 24'h00003f)) == 24'h010000); + always @(*) begin + io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); + if(logic_cmdWait) begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; + assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; + assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_0_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_1 = ((io_input_cmd_payload_fragment_address & (~ 24'h000fff)) == 24'h030000); + always @(*) begin + io_outputs_1_cmd_valid = (logic_input_valid && logic_hitsS0_1); + if(logic_cmdWait) begin + io_outputs_1_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_1_cmd_payload_last = logic_input_payload_last; + assign io_outputs_1_cmd_payload_last = _zz_io_outputs_1_cmd_payload_last; + assign io_outputs_1_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_1_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_1_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_1_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_1_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_1_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_2 = ((io_input_cmd_payload_fragment_address & (~ 24'h0000ff)) == 24'h020000); + always @(*) begin + io_outputs_2_cmd_valid = (logic_input_valid && logic_hitsS0_2); + if(logic_cmdWait) begin + io_outputs_2_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_2_cmd_payload_last = logic_input_payload_last; + assign io_outputs_2_cmd_payload_last = _zz_io_outputs_2_cmd_payload_last; + assign io_outputs_2_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_2_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_2_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_2_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_2_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_2_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_3 = ((io_input_cmd_payload_fragment_address & (~ 24'h0000ff)) == 24'h040000); + always @(*) begin + io_outputs_3_cmd_valid = (logic_input_valid && logic_hitsS0_3); + if(logic_cmdWait) begin + io_outputs_3_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_3_cmd_payload_last = logic_input_payload_last; + assign io_outputs_3_cmd_payload_last = _zz_io_outputs_3_cmd_payload_last; + assign io_outputs_3_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_3_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_3_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_3_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_3_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_3_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_4 = ((io_input_cmd_payload_fragment_address & (~ 24'h0000ff)) == 24'h050000); + always @(*) begin + io_outputs_4_cmd_valid = (logic_input_valid && logic_hitsS0_4); + if(logic_cmdWait) begin + io_outputs_4_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_4_cmd_payload_last = logic_input_payload_last; + assign io_outputs_4_cmd_payload_last = _zz_io_outputs_4_cmd_payload_last; + assign io_outputs_4_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_4_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_4_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_4_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_4_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_4_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_5 = ((io_input_cmd_payload_fragment_address & (~ 24'h00ffff)) == 24'h100000); + always @(*) begin + io_outputs_5_cmd_valid = (logic_input_valid && logic_hitsS0_5); + if(logic_cmdWait) begin + io_outputs_5_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_5_cmd_payload_last = logic_input_payload_last; + assign io_outputs_5_cmd_payload_last = _zz_io_outputs_5_cmd_payload_last; + assign io_outputs_5_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_5_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_5_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_5_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_5_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_5_cmd_payload_fragment_context = logic_input_payload_fragment_context; + always @(*) begin + logic_input_ready = ((|{(logic_hitsS0_5 && io_outputs_5_cmd_ready),{(logic_hitsS0_4 && io_outputs_4_cmd_ready),{(logic_hitsS0_3 && io_outputs_3_cmd_ready),{(logic_hitsS0_2 && io_outputs_2_cmd_ready),{(logic_hitsS0_1 && io_outputs_1_cmd_ready),(logic_hitsS0_0 && io_outputs_0_cmd_ready)}}}}}) || logic_noHitS0); + if(logic_cmdWait) begin + logic_input_ready = 1'b0; + end + end + + assign logic_input_fire = (logic_input_valid && logic_input_ready); + assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); + assign logic_rspPending = (logic_rspPendingCounter != 7'h0); + assign logic_rspNoHitValid = (! (|{logic_rspHits_5,{logic_rspHits_4,{logic_rspHits_3,{logic_rspHits_2,{logic_rspHits_1,logic_rspHits_0}}}}})); + assign when_BmbDecoder_l60 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign when_BmbDecoder_l60_1 = ((logic_input_fire && logic_noHitS0) && logic_input_payload_last); + always @(*) begin + io_input_rsp_valid = ((|{io_outputs_5_rsp_valid,{io_outputs_4_rsp_valid,{io_outputs_3_rsp_valid,{io_outputs_2_rsp_valid,{io_outputs_1_rsp_valid,io_outputs_0_rsp_valid}}}}}) || (logic_rspPending && logic_rspNoHitValid)); + if(logic_rspNoHit_doIt) begin + io_input_rsp_valid = 1'b1; + end + end + + assign _zz_io_input_rsp_payload_last = ((logic_rspHits_1 || logic_rspHits_3) || logic_rspHits_5); + assign _zz_io_input_rsp_payload_last_1 = (logic_rspHits_2 || logic_rspHits_3); + assign _zz_io_input_rsp_payload_last_2 = (logic_rspHits_4 || logic_rspHits_5); + assign _zz_io_input_rsp_payload_last_3 = {_zz_io_input_rsp_payload_last_2,{_zz_io_input_rsp_payload_last_1,_zz_io_input_rsp_payload_last}}; + always @(*) begin + io_input_rsp_payload_last = _zz_io_input_rsp_payload_last_4; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_last = 1'b1; + end + end + + always @(*) begin + io_input_rsp_payload_fragment_opcode = _zz_io_input_rsp_payload_fragment_opcode; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_opcode = 1'b1; + end + end + + assign io_input_rsp_payload_fragment_data = _zz_io_input_rsp_payload_fragment_data; + always @(*) begin + io_input_rsp_payload_fragment_context = _zz_io_input_rsp_payload_fragment_context; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_context = logic_rspNoHit_context; + end + end + + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign io_outputs_1_rsp_ready = io_input_rsp_ready; + assign io_outputs_2_rsp_ready = io_input_rsp_ready; + assign io_outputs_3_rsp_ready = io_input_rsp_ready; + assign io_outputs_4_rsp_ready = io_input_rsp_ready; + assign io_outputs_5_rsp_ready = io_input_rsp_ready; + assign logic_cmdWait = ((logic_rspPending && (((((((logic_hitsS0_0 != logic_rspHits_0) || (logic_hitsS0_1 != logic_rspHits_1)) || (logic_hitsS0_2 != logic_rspHits_2)) || (logic_hitsS0_3 != logic_rspHits_3)) || (logic_hitsS0_4 != logic_rspHits_4)) || (logic_hitsS0_5 != logic_rspHits_5)) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); + always @(posedge clk) begin + if(reset) begin + logic_rspPendingCounter <= 7'h0; + logic_rspNoHit_doIt <= 1'b0; + end else begin + logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); + if(when_BmbDecoder_l60) begin + logic_rspNoHit_doIt <= 1'b0; + end + if(when_BmbDecoder_l60_1) begin + logic_rspNoHit_doIt <= 1'b1; + end + end + end + + always @(posedge clk) begin + if(when_BmbDecoder_l56) begin + logic_rspHits_0 <= logic_hitsS0_0; + logic_rspHits_1 <= logic_hitsS0_1; + logic_rspHits_2 <= logic_hitsS0_2; + logic_rspHits_3 <= logic_hitsS0_3; + logic_rspHits_4 <= logic_hitsS0_4; + logic_rspHits_5 <= logic_hitsS0_5; + end + if(logic_input_fire) begin + logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); + end + if(logic_input_fire) begin + logic_rspNoHit_context <= logic_input_payload_fragment_context; + end + end + + +endmodule + +module Axi4PeripheralBmbUnburstify ( + input wire io_input_cmd_valid, + output reg io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_source, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [23:0] io_input_cmd_payload_fragment_address, + input wire [9:0] io_input_cmd_payload_fragment_length, + input wire [31:0] io_input_cmd_payload_fragment_data, + input wire [3:0] io_input_cmd_payload_fragment_mask, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_source, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [31:0] io_input_rsp_payload_fragment_data, + output reg io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output reg [0:0] io_output_cmd_payload_fragment_opcode, + output reg [23:0] io_output_cmd_payload_fragment_address, + output reg [1:0] io_output_cmd_payload_fragment_length, + output wire [31:0] io_output_cmd_payload_fragment_data, + output wire [3:0] io_output_cmd_payload_fragment_mask, + output wire [2:0] io_output_cmd_payload_fragment_context, + input wire io_output_rsp_valid, + output reg io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [31:0] io_output_rsp_payload_fragment_data, + input wire [2:0] io_output_rsp_payload_fragment_context, + input wire clk, + input wire reset +); + + wire [7:0] _zz_buffer_last; + wire [0:0] _zz_buffer_last_1; + wire [11:0] _zz_buffer_addressIncr; + wire doResult; + reg buffer_valid; + reg [0:0] buffer_opcode; + reg [0:0] buffer_source; + reg [23:0] buffer_address; + reg [7:0] buffer_beat; + wire buffer_last; + wire [23:0] buffer_addressIncr; + wire buffer_isWrite; + wire io_output_cmd_fire; + wire [7:0] cmdTransferBeatCount; + wire requireBuffer; + reg cmdContext_drop; + reg cmdContext_last; + reg [0:0] cmdContext_source; + wire rspContext_drop; + wire rspContext_last; + wire [0:0] rspContext_source; + wire [2:0] _zz_rspContext_drop; + wire when_Stream_l445; + reg io_output_rsp_thrown_valid; + wire io_output_rsp_thrown_ready; + wire io_output_rsp_thrown_payload_last; + wire [0:0] io_output_rsp_thrown_payload_fragment_opcode; + wire [31:0] io_output_rsp_thrown_payload_fragment_data; + wire [2:0] io_output_rsp_thrown_payload_fragment_context; + + assign _zz_buffer_last_1 = 1'b1; + assign _zz_buffer_last = {7'd0, _zz_buffer_last_1}; + assign _zz_buffer_addressIncr = (buffer_address[11 : 0] + 12'h004); + assign buffer_last = (buffer_beat == _zz_buffer_last); + assign buffer_addressIncr = {buffer_address[23 : 12],(_zz_buffer_addressIncr & (~ 12'h003))}; + assign buffer_isWrite = (buffer_opcode == 1'b1); + assign io_output_cmd_fire = (io_output_cmd_valid && io_output_cmd_ready); + assign cmdTransferBeatCount = io_input_cmd_payload_fragment_length[9 : 2]; + assign requireBuffer = (cmdTransferBeatCount != 8'h0); + assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign io_output_cmd_payload_last = 1'b1; + assign io_output_cmd_payload_fragment_context = {cmdContext_source,{cmdContext_last,cmdContext_drop}}; + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_address = buffer_addressIncr; + end else begin + io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + if(requireBuffer) begin + io_output_cmd_payload_fragment_address[1 : 0] = 2'b00; + end + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_opcode = buffer_opcode; + end else begin + io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_length = 2'b11; + end else begin + if(requireBuffer) begin + io_output_cmd_payload_fragment_length = 2'b11; + end else begin + io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length[1:0]; + end + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_source = buffer_source; + end else begin + cmdContext_source = io_input_cmd_payload_fragment_source; + end + end + + always @(*) begin + io_input_cmd_ready = 1'b0; + if(buffer_valid) begin + io_input_cmd_ready = (buffer_isWrite && io_output_cmd_ready); + end else begin + io_input_cmd_ready = io_output_cmd_ready; + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_valid = (! (buffer_isWrite && (! io_input_cmd_valid))); + end else begin + io_output_cmd_valid = io_input_cmd_valid; + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_last = buffer_last; + end else begin + cmdContext_last = (! requireBuffer); + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_drop = buffer_isWrite; + end else begin + cmdContext_drop = (io_input_cmd_payload_fragment_opcode == 1'b1); + end + end + + assign _zz_rspContext_drop = io_output_rsp_payload_fragment_context; + assign rspContext_drop = _zz_rspContext_drop[0]; + assign rspContext_last = _zz_rspContext_drop[1]; + assign rspContext_source = _zz_rspContext_drop[2 : 2]; + assign when_Stream_l445 = (! (rspContext_last || (! rspContext_drop))); + always @(*) begin + io_output_rsp_thrown_valid = io_output_rsp_valid; + if(when_Stream_l445) begin + io_output_rsp_thrown_valid = 1'b0; + end + end + + always @(*) begin + io_output_rsp_ready = io_output_rsp_thrown_ready; + if(when_Stream_l445) begin + io_output_rsp_ready = 1'b1; + end + end + + assign io_output_rsp_thrown_payload_last = io_output_rsp_payload_last; + assign io_output_rsp_thrown_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_output_rsp_thrown_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_output_rsp_thrown_payload_fragment_context = io_output_rsp_payload_fragment_context; + assign io_input_rsp_valid = io_output_rsp_thrown_valid; + assign io_output_rsp_thrown_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = rspContext_last; + assign io_input_rsp_payload_fragment_source = rspContext_source; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + always @(posedge clk) begin + if(reset) begin + buffer_valid <= 1'b0; + end else begin + if(io_output_cmd_fire) begin + if(buffer_last) begin + buffer_valid <= 1'b0; + end + end + if(!buffer_valid) begin + buffer_valid <= (requireBuffer && io_output_cmd_fire); + end + end + end + + always @(posedge clk) begin + if(io_output_cmd_fire) begin + buffer_beat <= (buffer_beat - 8'h01); + buffer_address[11 : 0] <= buffer_addressIncr[11 : 0]; + end + if(!buffer_valid) begin + buffer_opcode <= io_input_cmd_payload_fragment_opcode; + buffer_source <= io_input_cmd_payload_fragment_source; + buffer_address <= io_input_cmd_payload_fragment_address; + buffer_beat <= cmdTransferBeatCount; + end + end + + +endmodule + +module Axi4PeripheralBmbDecoder ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_source, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [23:0] io_input_cmd_payload_fragment_address, + input wire [9:0] io_input_cmd_payload_fragment_length, + input wire [31:0] io_input_cmd_payload_fragment_data, + input wire [3:0] io_input_cmd_payload_fragment_mask, + output reg io_input_rsp_valid, + input wire io_input_rsp_ready, + output reg io_input_rsp_payload_last, + output reg [0:0] io_input_rsp_payload_fragment_source, + output reg [0:0] io_input_rsp_payload_fragment_opcode, + output wire [31:0] io_input_rsp_payload_fragment_data, + output reg io_outputs_0_cmd_valid, + input wire io_outputs_0_cmd_ready, + output wire io_outputs_0_cmd_payload_last, + output wire [0:0] io_outputs_0_cmd_payload_fragment_source, + output wire [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_0_cmd_payload_fragment_address, + output wire [9:0] io_outputs_0_cmd_payload_fragment_length, + output wire [31:0] io_outputs_0_cmd_payload_fragment_data, + output wire [3:0] io_outputs_0_cmd_payload_fragment_mask, + input wire io_outputs_0_rsp_valid, + output wire io_outputs_0_rsp_ready, + input wire io_outputs_0_rsp_payload_last, + input wire [0:0] io_outputs_0_rsp_payload_fragment_source, + input wire [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_0_rsp_payload_fragment_data, + input wire clk, + input wire reset +); + + wire [6:0] _zz_logic_rspPendingCounter; + wire [6:0] _zz_logic_rspPendingCounter_1; + wire [0:0] _zz_logic_rspPendingCounter_2; + wire [6:0] _zz_logic_rspPendingCounter_3; + wire [0:0] _zz_logic_rspPendingCounter_4; + wire logic_input_valid; + reg logic_input_ready; + wire logic_input_payload_last; + wire [0:0] logic_input_payload_fragment_source; + wire [0:0] logic_input_payload_fragment_opcode; + wire [23:0] logic_input_payload_fragment_address; + wire [9:0] logic_input_payload_fragment_length; + wire [31:0] logic_input_payload_fragment_data; + wire [3:0] logic_input_payload_fragment_mask; + wire logic_hitsS0_0; + wire logic_noHitS0; + wire _zz_io_outputs_0_cmd_payload_last; + reg [6:0] logic_rspPendingCounter; + wire logic_input_fire; + wire io_input_rsp_fire; + wire logic_cmdWait; + wire when_BmbDecoder_l56; + reg logic_rspHits_0; + wire logic_rspPending; + wire logic_rspNoHitValid; + reg logic_rspNoHit_doIt; + wire when_BmbDecoder_l60; + wire when_BmbDecoder_l60_1; + reg logic_rspNoHit_singleBeatRsp; + reg [0:0] logic_rspNoHit_source; + reg [7:0] logic_rspNoHit_counter; + wire when_BmbDecoder_l81; + + assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); + assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); + assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; + assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; + assign logic_input_valid = io_input_cmd_valid; + assign io_input_cmd_ready = logic_input_ready; + assign logic_input_payload_last = io_input_cmd_payload_last; + assign logic_input_payload_fragment_source = io_input_cmd_payload_fragment_source; + assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign logic_noHitS0 = (! (|logic_hitsS0_0)); + assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 24'hffffff)) == 24'h0); + always @(*) begin + io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); + if(logic_cmdWait) begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; + assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; + assign io_outputs_0_cmd_payload_fragment_source = logic_input_payload_fragment_source; + assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + always @(*) begin + logic_input_ready = ((|(logic_hitsS0_0 && io_outputs_0_cmd_ready)) || logic_noHitS0); + if(logic_cmdWait) begin + logic_input_ready = 1'b0; + end + end + + assign logic_input_fire = (logic_input_valid && logic_input_ready); + assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); + assign logic_rspPending = (logic_rspPendingCounter != 7'h0); + assign logic_rspNoHitValid = (! (|logic_rspHits_0)); + assign when_BmbDecoder_l60 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign when_BmbDecoder_l60_1 = ((logic_input_fire && logic_noHitS0) && logic_input_payload_last); + always @(*) begin + io_input_rsp_valid = ((|io_outputs_0_rsp_valid) || (logic_rspPending && logic_rspNoHitValid)); + if(logic_rspNoHit_doIt) begin + io_input_rsp_valid = 1'b1; + end + end + + always @(*) begin + io_input_rsp_payload_last = io_outputs_0_rsp_payload_last; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_last = 1'b0; + if(when_BmbDecoder_l81) begin + io_input_rsp_payload_last = 1'b1; + end + if(logic_rspNoHit_singleBeatRsp) begin + io_input_rsp_payload_last = 1'b1; + end + end + end + + always @(*) begin + io_input_rsp_payload_fragment_source = io_outputs_0_rsp_payload_fragment_source; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_source = logic_rspNoHit_source; + end + end + + always @(*) begin + io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_opcode = 1'b1; + end + end + + assign io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + assign when_BmbDecoder_l81 = (logic_rspNoHit_counter == 8'h0); + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign logic_cmdWait = ((logic_rspPending && ((logic_hitsS0_0 != logic_rspHits_0) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); + always @(posedge clk) begin + if(reset) begin + logic_rspPendingCounter <= 7'h0; + logic_rspNoHit_doIt <= 1'b0; + end else begin + logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); + if(when_BmbDecoder_l60) begin + logic_rspNoHit_doIt <= 1'b0; + end + if(when_BmbDecoder_l60_1) begin + logic_rspNoHit_doIt <= 1'b1; + end + end + end + + always @(posedge clk) begin + if(when_BmbDecoder_l56) begin + logic_rspHits_0 <= logic_hitsS0_0; + end + if(logic_input_fire) begin + logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); + end + if(logic_input_fire) begin + logic_rspNoHit_source <= logic_input_payload_fragment_source; + end + if(logic_input_fire) begin + logic_rspNoHit_counter <= logic_input_payload_fragment_length[9 : 2]; + end + if(logic_rspNoHit_doIt) begin + if(io_input_rsp_fire) begin + logic_rspNoHit_counter <= (logic_rspNoHit_counter - 8'h01); + end + end + end + + +endmodule + +module Axi4PeripheralAxi4SharedToBmb ( + input wire io_axi_arw_valid, + output wire io_axi_arw_ready, + input wire [23:0] io_axi_arw_payload_addr, + input wire [7:0] io_axi_arw_payload_len, + input wire [2:0] io_axi_arw_payload_size, + input wire [3:0] io_axi_arw_payload_cache, + input wire [2:0] io_axi_arw_payload_prot, + input wire io_axi_arw_payload_write, + input wire io_axi_w_valid, + output wire io_axi_w_ready, + input wire [31:0] io_axi_w_payload_data, + input wire [3:0] io_axi_w_payload_strb, + input wire io_axi_w_payload_last, + output wire io_axi_b_valid, + input wire io_axi_b_ready, + output reg [1:0] io_axi_b_payload_resp, + output wire io_axi_r_valid, + input wire io_axi_r_ready, + output wire [31:0] io_axi_r_payload_data, + output reg [1:0] io_axi_r_payload_resp, + output wire io_axi_r_payload_last, + output wire io_bmb_cmd_valid, + input wire io_bmb_cmd_ready, + output wire io_bmb_cmd_payload_last, + output wire [0:0] io_bmb_cmd_payload_fragment_source, + output wire [0:0] io_bmb_cmd_payload_fragment_opcode, + output wire [23:0] io_bmb_cmd_payload_fragment_address, + output wire [9:0] io_bmb_cmd_payload_fragment_length, + output wire [31:0] io_bmb_cmd_payload_fragment_data, + output wire [3:0] io_bmb_cmd_payload_fragment_mask, + input wire io_bmb_rsp_valid, + output wire io_bmb_rsp_ready, + input wire io_bmb_rsp_payload_last, + input wire [0:0] io_bmb_rsp_payload_fragment_source, + input wire [0:0] io_bmb_rsp_payload_fragment_opcode, + input wire [31:0] io_bmb_rsp_payload_fragment_data +); + + wire [9:0] _zz_io_bmb_cmd_payload_fragment_length; + wire hazard; + wire io_bmb_cmd_fire; + wire rspIsWrite; + wire when_Axi4SharedToBmb_l42; + wire when_Axi4SharedToBmb_l49; + + assign _zz_io_bmb_cmd_payload_fragment_length = ({2'd0,io_axi_arw_payload_len} <<< 2'd2); + assign hazard = (io_axi_arw_payload_write && (! io_axi_w_valid)); + assign io_bmb_cmd_valid = (io_axi_arw_valid && (! hazard)); + assign io_bmb_cmd_payload_fragment_source = io_axi_arw_payload_write; + assign io_bmb_cmd_payload_fragment_opcode = io_axi_arw_payload_write; + assign io_bmb_cmd_payload_fragment_address = io_axi_arw_payload_addr; + assign io_bmb_cmd_payload_fragment_length = (_zz_io_bmb_cmd_payload_fragment_length | 10'h003); + assign io_bmb_cmd_payload_fragment_data = io_axi_w_payload_data; + assign io_bmb_cmd_payload_fragment_mask = io_axi_w_payload_strb; + assign io_bmb_cmd_payload_last = ((! io_axi_arw_payload_write) || io_axi_w_payload_last); + assign io_bmb_cmd_fire = (io_bmb_cmd_valid && io_bmb_cmd_ready); + assign io_axi_arw_ready = (io_bmb_cmd_fire && io_bmb_cmd_payload_last); + assign io_axi_w_ready = (io_bmb_cmd_fire && (io_bmb_cmd_payload_fragment_opcode == 1'b1)); + assign rspIsWrite = io_bmb_rsp_payload_fragment_source[0]; + assign io_axi_b_valid = (io_bmb_rsp_valid && rspIsWrite); + always @(*) begin + io_axi_b_payload_resp = 2'b00; + if(when_Axi4SharedToBmb_l42) begin + io_axi_b_payload_resp = 2'b11; + end + end + + assign when_Axi4SharedToBmb_l42 = (io_bmb_rsp_payload_fragment_opcode == 1'b1); + assign io_axi_r_valid = (io_bmb_rsp_valid && (! rspIsWrite)); + assign io_axi_r_payload_data = io_bmb_rsp_payload_fragment_data; + assign io_axi_r_payload_last = io_bmb_rsp_payload_last; + always @(*) begin + io_axi_r_payload_resp = 2'b00; + if(when_Axi4SharedToBmb_l49) begin + io_axi_r_payload_resp = 2'b11; + end + end + + assign when_Axi4SharedToBmb_l49 = (io_bmb_rsp_payload_fragment_opcode == 1'b1); + assign io_bmb_rsp_ready = (rspIsWrite ? io_axi_b_ready : io_axi_r_ready); + +endmodule + +module Axi4PeripheralStreamArbiter ( + input wire io_inputs_0_valid, + output wire io_inputs_0_ready, + input wire [23:0] io_inputs_0_payload_addr, + input wire [7:0] io_inputs_0_payload_len, + input wire [2:0] io_inputs_0_payload_size, + input wire [3:0] io_inputs_0_payload_cache, + input wire [2:0] io_inputs_0_payload_prot, + input wire io_inputs_1_valid, + output wire io_inputs_1_ready, + input wire [23:0] io_inputs_1_payload_addr, + input wire [7:0] io_inputs_1_payload_len, + input wire [2:0] io_inputs_1_payload_size, + input wire [3:0] io_inputs_1_payload_cache, + input wire [2:0] io_inputs_1_payload_prot, + output wire io_output_valid, + input wire io_output_ready, + output wire [23:0] io_output_payload_addr, + output wire [7:0] io_output_payload_len, + output wire [2:0] io_output_payload_size, + output wire [3:0] io_output_payload_cache, + output wire [2:0] io_output_payload_prot, + output wire [0:0] io_chosen, + output wire [1:0] io_chosenOH, + input wire clk, + input wire reset +); + + wire [3:0] _zz__zz_maskProposal_0_2; + wire [3:0] _zz__zz_maskProposal_0_2_1; + wire [1:0] _zz__zz_maskProposal_0_2_2; + reg locked; + wire maskProposal_0; + wire maskProposal_1; + reg maskLocked_0; + reg maskLocked_1; + wire maskRouted_0; + wire maskRouted_1; + wire [1:0] _zz_maskProposal_0; + wire [3:0] _zz_maskProposal_0_1; + wire [3:0] _zz_maskProposal_0_2; + wire [1:0] _zz_maskProposal_0_3; + wire io_output_fire; + wire _zz_io_chosen; + + assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); + assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; + assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; + assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); + assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); + assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; + assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; + assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); + assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); + assign maskProposal_0 = _zz_maskProposal_0_3[0]; + assign maskProposal_1 = _zz_maskProposal_0_3[1]; + assign io_output_fire = (io_output_valid && io_output_ready); + assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); + assign io_output_payload_addr = (maskRouted_0 ? io_inputs_0_payload_addr : io_inputs_1_payload_addr); + assign io_output_payload_len = (maskRouted_0 ? io_inputs_0_payload_len : io_inputs_1_payload_len); + assign io_output_payload_size = (maskRouted_0 ? io_inputs_0_payload_size : io_inputs_1_payload_size); + assign io_output_payload_cache = (maskRouted_0 ? io_inputs_0_payload_cache : io_inputs_1_payload_cache); + assign io_output_payload_prot = (maskRouted_0 ? io_inputs_0_payload_prot : io_inputs_1_payload_prot); + assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); + assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); + assign io_chosenOH = {maskRouted_1,maskRouted_0}; + assign _zz_io_chosen = io_chosenOH[1]; + assign io_chosen = _zz_io_chosen; + always @(posedge clk) begin + if(reset) begin + locked <= 1'b0; + maskLocked_0 <= 1'b0; + maskLocked_1 <= 1'b1; + end else begin + if(io_output_valid) begin + maskLocked_0 <= maskRouted_0; + maskLocked_1 <= maskRouted_1; + end + if(io_output_valid) begin + locked <= 1'b1; + end + if(io_output_fire) begin + locked <= 1'b0; + end + end + end + + +endmodule + +//Axi4PeripheralTimer_1 replaced by Axi4PeripheralTimer + +module Axi4PeripheralTimer ( + input wire io_tick, + input wire io_clear, + input wire [15:0] io_limit, + output wire io_full, + output wire [15:0] io_value, + input wire clk, + input wire reset +); + + wire [15:0] _zz_counter; + wire [0:0] _zz_counter_1; + reg [15:0] counter; + wire limitHit; + reg inhibitFull; + + assign _zz_counter_1 = (! limitHit); + assign _zz_counter = {15'd0, _zz_counter_1}; + assign limitHit = (counter == io_limit); + assign io_full = ((limitHit && io_tick) && (! inhibitFull)); + assign io_value = counter; + always @(posedge clk) begin + if(reset) begin + inhibitFull <= 1'b0; + end else begin + if(io_tick) begin + inhibitFull <= limitHit; + end + if(io_clear) begin + inhibitFull <= 1'b0; + end + end + end + + always @(posedge clk) begin + if(io_tick) begin + counter <= (counter + _zz_counter); + end + if(io_clear) begin + counter <= 16'h0; + end + end + + +endmodule + +module Axi4PeripheralPrescaler ( + input wire io_clear, + input wire [23:0] io_limit, + output wire io_overflow, + input wire clk, + input wire reset +); + + reg [23:0] counter; + wire when_Prescaler_l17; + + assign when_Prescaler_l17 = (io_clear || io_overflow); + assign io_overflow = (counter == io_limit); + always @(posedge clk) begin + counter <= (counter + 24'h000001); + if(when_Prescaler_l17) begin + counter <= 24'h0; + end + end + + +endmodule + +module Axi4PeripheralI2cSlave ( + output wire io_i2c_sda_write, + input wire io_i2c_sda_read, + output wire io_i2c_scl_write, + input wire io_i2c_scl_read, + input wire [9:0] io_config_samplingClockDivider, + input wire [19:0] io_config_timeout, + input wire [5:0] io_config_tsuData, + input wire io_config_timeoutClear, + output reg [2:0] io_bus_cmd_kind, + output wire io_bus_cmd_data, + input wire io_bus_rsp_valid, + input wire io_bus_rsp_enable, + input wire io_bus_rsp_data, + output wire io_timeout, + output wire io_internals_inFrame, + output wire io_internals_sdaRead, + output wire io_internals_sclRead, + input wire clk, + input wire reset +); + localparam Axi4PeripheralI2cSlaveCmdMode_NONE = 3'd0; + localparam Axi4PeripheralI2cSlaveCmdMode_START = 3'd1; + localparam Axi4PeripheralI2cSlaveCmdMode_RESTART = 3'd2; + localparam Axi4PeripheralI2cSlaveCmdMode_STOP = 3'd3; + localparam Axi4PeripheralI2cSlaveCmdMode_DROP = 3'd4; + localparam Axi4PeripheralI2cSlaveCmdMode_DRIVE = 3'd5; + localparam Axi4PeripheralI2cSlaveCmdMode_READ = 3'd6; + + wire io_i2c_scl_read_buffercc_io_dataOut; + wire io_i2c_sda_read_buffercc_io_dataOut; + reg [9:0] filter_timer_counter; + wire filter_timer_tick; + wire filter_sampler_sclSync; + wire filter_sampler_sdaSync; + wire filter_sampler_sclSamples_0; + wire filter_sampler_sclSamples_1; + wire filter_sampler_sclSamples_2; + wire _zz_filter_sampler_sclSamples_0; + reg _zz_filter_sampler_sclSamples_1; + reg _zz_filter_sampler_sclSamples_2; + wire filter_sampler_sdaSamples_0; + wire filter_sampler_sdaSamples_1; + wire filter_sampler_sdaSamples_2; + wire _zz_filter_sampler_sdaSamples_0; + reg _zz_filter_sampler_sdaSamples_1; + reg _zz_filter_sampler_sdaSamples_2; + reg filter_sda; + reg filter_scl; + wire when_Misc_l82; + wire when_Misc_l85; + wire sclEdge_rise; + wire sclEdge_fall; + wire sclEdge_toggle; + reg filter_scl_regNext; + wire sdaEdge_rise; + wire sdaEdge_fall; + wire sdaEdge_toggle; + reg filter_sda_regNext; + wire detector_start; + wire detector_stop; + reg [5:0] tsuData_counter; + wire tsuData_done; + reg tsuData_reset; + wire when_I2CSlave_l191; + reg ctrl_inFrame; + reg ctrl_inFrameData; + reg ctrl_sdaWrite; + reg ctrl_sclWrite; + wire ctrl_rspBufferIn_valid; + reg ctrl_rspBufferIn_ready; + wire ctrl_rspBufferIn_payload_enable; + wire ctrl_rspBufferIn_payload_data; + wire ctrl_rspBuffer_valid; + reg ctrl_rspBuffer_ready; + wire ctrl_rspBuffer_payload_enable; + wire ctrl_rspBuffer_payload_data; + reg ctrl_rspBufferIn_rValid; + reg ctrl_rspBufferIn_rData_enable; + reg ctrl_rspBufferIn_rData_data; + wire when_Stream_l375; + wire ctrl_rspAhead_valid; + wire ctrl_rspAhead_payload_enable; + wire ctrl_rspAhead_payload_data; + wire when_I2CSlave_l241; + wire when_I2CSlave_l245; + wire when_I2CSlave_l251; + wire [2:0] _zz_io_bus_cmd_kind; + reg timeout_enabled; + reg [19:0] timeout_counter; + wire timeout_tick; + wire when_I2CSlave_l270; + wire when_I2CSlave_l276; + wire [2:0] _zz_io_bus_cmd_kind_1; + `ifndef SYNTHESIS + reg [55:0] io_bus_cmd_kind_string; + reg [55:0] _zz_io_bus_cmd_kind_string; + reg [55:0] _zz_io_bus_cmd_kind_1_string; + `endif + + + (* keep_hierarchy = "TRUE" *) Axi4PeripheralBufferCC_1 io_i2c_scl_read_buffercc ( + .io_dataIn (io_i2c_scl_read ), //i + .io_dataOut (io_i2c_scl_read_buffercc_io_dataOut), //o + .clk (clk ), //i + .reset (reset ) //i + ); + (* keep_hierarchy = "TRUE" *) Axi4PeripheralBufferCC_1 io_i2c_sda_read_buffercc ( + .io_dataIn (io_i2c_sda_read ), //i + .io_dataOut (io_i2c_sda_read_buffercc_io_dataOut), //o + .clk (clk ), //i + .reset (reset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_bus_cmd_kind) + Axi4PeripheralI2cSlaveCmdMode_NONE : io_bus_cmd_kind_string = "NONE "; + Axi4PeripheralI2cSlaveCmdMode_START : io_bus_cmd_kind_string = "START "; + Axi4PeripheralI2cSlaveCmdMode_RESTART : io_bus_cmd_kind_string = "RESTART"; + Axi4PeripheralI2cSlaveCmdMode_STOP : io_bus_cmd_kind_string = "STOP "; + Axi4PeripheralI2cSlaveCmdMode_DROP : io_bus_cmd_kind_string = "DROP "; + Axi4PeripheralI2cSlaveCmdMode_DRIVE : io_bus_cmd_kind_string = "DRIVE "; + Axi4PeripheralI2cSlaveCmdMode_READ : io_bus_cmd_kind_string = "READ "; + default : io_bus_cmd_kind_string = "???????"; + endcase + end + always @(*) begin + case(_zz_io_bus_cmd_kind) + Axi4PeripheralI2cSlaveCmdMode_NONE : _zz_io_bus_cmd_kind_string = "NONE "; + Axi4PeripheralI2cSlaveCmdMode_START : _zz_io_bus_cmd_kind_string = "START "; + Axi4PeripheralI2cSlaveCmdMode_RESTART : _zz_io_bus_cmd_kind_string = "RESTART"; + Axi4PeripheralI2cSlaveCmdMode_STOP : _zz_io_bus_cmd_kind_string = "STOP "; + Axi4PeripheralI2cSlaveCmdMode_DROP : _zz_io_bus_cmd_kind_string = "DROP "; + Axi4PeripheralI2cSlaveCmdMode_DRIVE : _zz_io_bus_cmd_kind_string = "DRIVE "; + Axi4PeripheralI2cSlaveCmdMode_READ : _zz_io_bus_cmd_kind_string = "READ "; + default : _zz_io_bus_cmd_kind_string = "???????"; + endcase + end + always @(*) begin + case(_zz_io_bus_cmd_kind_1) + Axi4PeripheralI2cSlaveCmdMode_NONE : _zz_io_bus_cmd_kind_1_string = "NONE "; + Axi4PeripheralI2cSlaveCmdMode_START : _zz_io_bus_cmd_kind_1_string = "START "; + Axi4PeripheralI2cSlaveCmdMode_RESTART : _zz_io_bus_cmd_kind_1_string = "RESTART"; + Axi4PeripheralI2cSlaveCmdMode_STOP : _zz_io_bus_cmd_kind_1_string = "STOP "; + Axi4PeripheralI2cSlaveCmdMode_DROP : _zz_io_bus_cmd_kind_1_string = "DROP "; + Axi4PeripheralI2cSlaveCmdMode_DRIVE : _zz_io_bus_cmd_kind_1_string = "DRIVE "; + Axi4PeripheralI2cSlaveCmdMode_READ : _zz_io_bus_cmd_kind_1_string = "READ "; + default : _zz_io_bus_cmd_kind_1_string = "???????"; + endcase + end + `endif + + assign filter_timer_tick = (filter_timer_counter == 10'h0); + assign filter_sampler_sclSync = io_i2c_scl_read_buffercc_io_dataOut; + assign filter_sampler_sdaSync = io_i2c_sda_read_buffercc_io_dataOut; + assign _zz_filter_sampler_sclSamples_0 = filter_sampler_sclSync; + assign filter_sampler_sclSamples_0 = _zz_filter_sampler_sclSamples_0; + assign filter_sampler_sclSamples_1 = _zz_filter_sampler_sclSamples_1; + assign filter_sampler_sclSamples_2 = _zz_filter_sampler_sclSamples_2; + assign _zz_filter_sampler_sdaSamples_0 = filter_sampler_sdaSync; + assign filter_sampler_sdaSamples_0 = _zz_filter_sampler_sdaSamples_0; + assign filter_sampler_sdaSamples_1 = _zz_filter_sampler_sdaSamples_1; + assign filter_sampler_sdaSamples_2 = _zz_filter_sampler_sdaSamples_2; + assign when_Misc_l82 = (&{(filter_sampler_sdaSamples_2 != filter_sda),{(filter_sampler_sdaSamples_1 != filter_sda),(filter_sampler_sdaSamples_0 != filter_sda)}}); + assign when_Misc_l85 = (&{(filter_sampler_sclSamples_2 != filter_scl),{(filter_sampler_sclSamples_1 != filter_scl),(filter_sampler_sclSamples_0 != filter_scl)}}); + assign sclEdge_rise = ((! filter_scl_regNext) && filter_scl); + assign sclEdge_fall = (filter_scl_regNext && (! filter_scl)); + assign sclEdge_toggle = (filter_scl_regNext != filter_scl); + assign sdaEdge_rise = ((! filter_sda_regNext) && filter_sda); + assign sdaEdge_fall = (filter_sda_regNext && (! filter_sda)); + assign sdaEdge_toggle = (filter_sda_regNext != filter_sda); + assign detector_start = (filter_scl && sdaEdge_fall); + assign detector_stop = (filter_scl && sdaEdge_rise); + assign tsuData_done = (tsuData_counter == 6'h0); + always @(*) begin + tsuData_reset = 1'b0; + if(ctrl_inFrameData) begin + tsuData_reset = (! ctrl_rspAhead_valid); + end + end + + assign when_I2CSlave_l191 = (! tsuData_done); + always @(*) begin + ctrl_sdaWrite = 1'b1; + if(ctrl_inFrameData) begin + if(when_I2CSlave_l251) begin + ctrl_sdaWrite = ctrl_rspAhead_payload_data; + end + end + end + + always @(*) begin + ctrl_sclWrite = 1'b1; + if(ctrl_inFrameData) begin + if(when_I2CSlave_l245) begin + ctrl_sclWrite = 1'b0; + end + end + end + + always @(*) begin + ctrl_rspBufferIn_ready = ctrl_rspBuffer_ready; + if(when_Stream_l375) begin + ctrl_rspBufferIn_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! ctrl_rspBuffer_valid); + assign ctrl_rspBuffer_valid = ctrl_rspBufferIn_rValid; + assign ctrl_rspBuffer_payload_enable = ctrl_rspBufferIn_rData_enable; + assign ctrl_rspBuffer_payload_data = ctrl_rspBufferIn_rData_data; + assign ctrl_rspAhead_valid = (ctrl_rspBuffer_valid ? ctrl_rspBuffer_valid : ctrl_rspBufferIn_valid); + assign ctrl_rspAhead_payload_enable = (ctrl_rspBuffer_valid ? ctrl_rspBuffer_payload_enable : ctrl_rspBufferIn_payload_enable); + assign ctrl_rspAhead_payload_data = (ctrl_rspBuffer_valid ? ctrl_rspBuffer_payload_data : ctrl_rspBufferIn_payload_data); + assign ctrl_rspBufferIn_valid = io_bus_rsp_valid; + assign ctrl_rspBufferIn_payload_enable = io_bus_rsp_enable; + assign ctrl_rspBufferIn_payload_data = io_bus_rsp_data; + always @(*) begin + ctrl_rspBuffer_ready = 1'b0; + if(ctrl_inFrame) begin + if(sclEdge_fall) begin + ctrl_rspBuffer_ready = 1'b1; + end + end + end + + always @(*) begin + io_bus_cmd_kind = Axi4PeripheralI2cSlaveCmdMode_NONE; + if(ctrl_inFrame) begin + if(sclEdge_rise) begin + io_bus_cmd_kind = Axi4PeripheralI2cSlaveCmdMode_READ; + end + end + if(ctrl_inFrameData) begin + if(when_I2CSlave_l241) begin + io_bus_cmd_kind = Axi4PeripheralI2cSlaveCmdMode_DRIVE; + end + end + if(detector_start) begin + io_bus_cmd_kind = _zz_io_bus_cmd_kind; + end + if(when_I2CSlave_l276) begin + if(ctrl_inFrame) begin + io_bus_cmd_kind = _zz_io_bus_cmd_kind_1; + end + end + end + + assign io_bus_cmd_data = filter_sda; + assign when_I2CSlave_l241 = ((! ctrl_rspBuffer_valid) || ctrl_rspBuffer_ready); + assign when_I2CSlave_l245 = ((! ctrl_rspAhead_valid) || (ctrl_rspAhead_payload_enable && (! tsuData_done))); + assign when_I2CSlave_l251 = (ctrl_rspAhead_valid && ctrl_rspAhead_payload_enable); + assign _zz_io_bus_cmd_kind = (ctrl_inFrame ? Axi4PeripheralI2cSlaveCmdMode_RESTART : Axi4PeripheralI2cSlaveCmdMode_START); + assign timeout_tick = (timeout_enabled && (timeout_counter == 20'h0)); + assign when_I2CSlave_l270 = (((timeout_tick || sclEdge_toggle) || (((! ctrl_inFrame) && filter_scl) && filter_sda)) || io_config_timeoutClear); + assign io_timeout = timeout_tick; + assign when_I2CSlave_l276 = (detector_stop || timeout_tick); + assign _zz_io_bus_cmd_kind_1 = (timeout_tick ? Axi4PeripheralI2cSlaveCmdMode_DROP : Axi4PeripheralI2cSlaveCmdMode_STOP); + assign io_internals_inFrame = ctrl_inFrame; + assign io_internals_sdaRead = filter_sda; + assign io_internals_sclRead = filter_scl; + assign io_i2c_scl_write = ctrl_sclWrite; + assign io_i2c_sda_write = ctrl_sdaWrite; + always @(posedge clk) begin + if(reset) begin + filter_timer_counter <= 10'h0; + _zz_filter_sampler_sclSamples_1 <= 1'b1; + _zz_filter_sampler_sclSamples_2 <= 1'b1; + _zz_filter_sampler_sdaSamples_1 <= 1'b1; + _zz_filter_sampler_sdaSamples_2 <= 1'b1; + filter_sda <= 1'b1; + filter_scl <= 1'b1; + filter_scl_regNext <= 1'b1; + filter_sda_regNext <= 1'b1; + tsuData_counter <= 6'h0; + ctrl_inFrame <= 1'b0; + ctrl_inFrameData <= 1'b0; + ctrl_rspBufferIn_rValid <= 1'b0; + timeout_counter <= 20'h0; + end else begin + filter_timer_counter <= (filter_timer_counter - 10'h001); + if(filter_timer_tick) begin + filter_timer_counter <= io_config_samplingClockDivider; + end + if(filter_timer_tick) begin + _zz_filter_sampler_sclSamples_1 <= _zz_filter_sampler_sclSamples_0; + end + if(filter_timer_tick) begin + _zz_filter_sampler_sclSamples_2 <= _zz_filter_sampler_sclSamples_1; + end + if(filter_timer_tick) begin + _zz_filter_sampler_sdaSamples_1 <= _zz_filter_sampler_sdaSamples_0; + end + if(filter_timer_tick) begin + _zz_filter_sampler_sdaSamples_2 <= _zz_filter_sampler_sdaSamples_1; + end + if(filter_timer_tick) begin + if(when_Misc_l82) begin + filter_sda <= filter_sampler_sdaSamples_2; + end + if(when_Misc_l85) begin + filter_scl <= filter_sampler_sclSamples_2; + end + end + filter_scl_regNext <= filter_scl; + filter_sda_regNext <= filter_sda; + if(when_I2CSlave_l191) begin + tsuData_counter <= (tsuData_counter - 6'h01); + end + if(tsuData_reset) begin + tsuData_counter <= io_config_tsuData; + end + if(ctrl_rspBufferIn_ready) begin + ctrl_rspBufferIn_rValid <= ctrl_rspBufferIn_valid; + end + if(ctrl_inFrame) begin + if(sclEdge_fall) begin + ctrl_inFrameData <= 1'b1; + end + end + if(detector_start) begin + ctrl_inFrame <= 1'b1; + ctrl_inFrameData <= 1'b0; + end + timeout_counter <= (timeout_counter - 20'h00001); + if(when_I2CSlave_l270) begin + timeout_counter <= io_config_timeout; + end + if(when_I2CSlave_l276) begin + ctrl_inFrame <= 1'b0; + ctrl_inFrameData <= 1'b0; + end + end + end + + always @(posedge clk) begin + if(ctrl_rspBufferIn_ready) begin + ctrl_rspBufferIn_rData_enable <= ctrl_rspBufferIn_payload_enable; + ctrl_rspBufferIn_rData_data <= ctrl_rspBufferIn_payload_data; + end + timeout_enabled <= (io_config_timeout != 20'h0); + end + + +endmodule + +module Axi4PeripheralStreamFifo_3 ( + input wire io_push_valid, + output wire io_push_ready, + input wire [7:0] io_push_payload_data, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [7:0] io_pop_payload_data, + input wire io_flush, + output wire [8:0] io_occupancy, + output wire [8:0] io_availability, + input wire clk, + input wire reset +); + + reg [7:0] logic_ram_spinal_port1; + reg _zz_1; + wire logic_ptr_doPush; + wire logic_ptr_doPop; + wire logic_ptr_full; + wire logic_ptr_empty; + reg [8:0] logic_ptr_push; + reg [8:0] logic_ptr_pop; + wire [8:0] logic_ptr_occupancy; + wire [8:0] logic_ptr_popOnIo; + wire when_Stream_l1248; + reg logic_ptr_wentUp; + wire io_push_fire; + wire logic_push_onRam_write_valid; + wire [7:0] logic_push_onRam_write_payload_address; + wire [7:0] logic_push_onRam_write_payload_data_data; + wire logic_pop_addressGen_valid; + reg logic_pop_addressGen_ready; + wire [7:0] logic_pop_addressGen_payload; + wire logic_pop_addressGen_fire; + wire logic_pop_sync_readArbitation_valid; + wire logic_pop_sync_readArbitation_ready; + wire [7:0] logic_pop_sync_readArbitation_payload; + reg logic_pop_addressGen_rValid; + reg [7:0] logic_pop_addressGen_rData; + wire when_Stream_l375; + wire logic_pop_sync_readPort_cmd_valid; + wire [7:0] logic_pop_sync_readPort_cmd_payload; + wire [7:0] logic_pop_sync_readPort_rsp_data; + wire logic_pop_sync_readArbitation_translated_valid; + wire logic_pop_sync_readArbitation_translated_ready; + wire [7:0] logic_pop_sync_readArbitation_translated_payload_data; + wire logic_pop_sync_readArbitation_fire; + reg [8:0] logic_pop_sync_popReg; + reg [7:0] logic_ram [0:255]; + + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data_data; + end + end + + always @(posedge clk) begin + if(logic_pop_sync_readPort_cmd_valid) begin + logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_push_onRam_write_valid) begin + _zz_1 = 1'b1; + end + end + + assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); + assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 9'h100) == 9'h0); + assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop); + assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo); + assign io_push_ready = (! logic_ptr_full); + assign io_push_fire = (io_push_valid && io_push_ready); + assign logic_ptr_doPush = io_push_fire; + assign logic_push_onRam_write_valid = io_push_fire; + assign logic_push_onRam_write_payload_address = logic_ptr_push[7:0]; + assign logic_push_onRam_write_payload_data_data = io_push_payload_data; + assign logic_pop_addressGen_valid = (! logic_ptr_empty); + assign logic_pop_addressGen_payload = logic_ptr_pop[7:0]; + assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); + assign logic_ptr_doPop = logic_pop_addressGen_fire; + always @(*) begin + logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; + if(when_Stream_l375) begin + logic_pop_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); + assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; + assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; + assign logic_pop_sync_readPort_rsp_data = logic_ram_spinal_port1[7 : 0]; + assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; + assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; + assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; + assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; + assign logic_pop_sync_readArbitation_translated_payload_data = logic_pop_sync_readPort_rsp_data; + assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; + assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_data = logic_pop_sync_readArbitation_translated_payload_data; + assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); + assign logic_ptr_popOnIo = logic_pop_sync_popReg; + assign io_occupancy = logic_ptr_occupancy; + assign io_availability = (9'h100 - logic_ptr_occupancy); + always @(posedge clk) begin + if(reset) begin + logic_ptr_push <= 9'h0; + logic_ptr_pop <= 9'h0; + logic_ptr_wentUp <= 1'b0; + logic_pop_addressGen_rValid <= 1'b0; + logic_pop_sync_popReg <= 9'h0; + end else begin + if(when_Stream_l1248) begin + logic_ptr_wentUp <= logic_ptr_doPush; + end + if(io_flush) begin + logic_ptr_wentUp <= 1'b0; + end + if(logic_ptr_doPush) begin + logic_ptr_push <= (logic_ptr_push + 9'h001); + end + if(logic_ptr_doPop) begin + logic_ptr_pop <= (logic_ptr_pop + 9'h001); + end + if(io_flush) begin + logic_ptr_push <= 9'h0; + logic_ptr_pop <= 9'h0; + end + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; + end + if(io_flush) begin + logic_pop_addressGen_rValid <= 1'b0; + end + if(logic_pop_sync_readArbitation_fire) begin + logic_pop_sync_popReg <= logic_ptr_pop; + end + if(io_flush) begin + logic_pop_sync_popReg <= 9'h0; + end + end + end + + always @(posedge clk) begin + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rData <= logic_pop_addressGen_payload; + end + end + + +endmodule + +module Axi4PeripheralStreamFifo_2 ( + input wire io_push_valid, + output wire io_push_ready, + input wire io_push_payload_kind, + input wire io_push_payload_read, + input wire io_push_payload_write, + input wire [7:0] io_push_payload_data, + output wire io_pop_valid, + input wire io_pop_ready, + output wire io_pop_payload_kind, + output wire io_pop_payload_read, + output wire io_pop_payload_write, + output wire [7:0] io_pop_payload_data, + input wire io_flush, + output wire [8:0] io_occupancy, + output wire [8:0] io_availability, + input wire clk, + input wire reset +); + + reg [10:0] logic_ram_spinal_port1; + wire [10:0] _zz_logic_ram_port; + reg _zz_1; + wire logic_ptr_doPush; + wire logic_ptr_doPop; + wire logic_ptr_full; + wire logic_ptr_empty; + reg [8:0] logic_ptr_push; + reg [8:0] logic_ptr_pop; + wire [8:0] logic_ptr_occupancy; + wire [8:0] logic_ptr_popOnIo; + wire when_Stream_l1248; + reg logic_ptr_wentUp; + wire io_push_fire; + wire logic_push_onRam_write_valid; + wire [7:0] logic_push_onRam_write_payload_address; + wire logic_push_onRam_write_payload_data_kind; + wire logic_push_onRam_write_payload_data_read; + wire logic_push_onRam_write_payload_data_write; + wire [7:0] logic_push_onRam_write_payload_data_data; + wire logic_pop_addressGen_valid; + reg logic_pop_addressGen_ready; + wire [7:0] logic_pop_addressGen_payload; + wire logic_pop_addressGen_fire; + wire logic_pop_sync_readArbitation_valid; + wire logic_pop_sync_readArbitation_ready; + wire [7:0] logic_pop_sync_readArbitation_payload; + reg logic_pop_addressGen_rValid; + reg [7:0] logic_pop_addressGen_rData; + wire when_Stream_l375; + wire logic_pop_sync_readPort_cmd_valid; + wire [7:0] logic_pop_sync_readPort_cmd_payload; + wire logic_pop_sync_readPort_rsp_kind; + wire logic_pop_sync_readPort_rsp_read; + wire logic_pop_sync_readPort_rsp_write; + wire [7:0] logic_pop_sync_readPort_rsp_data; + wire [10:0] _zz_logic_pop_sync_readPort_rsp_kind; + wire logic_pop_sync_readArbitation_translated_valid; + wire logic_pop_sync_readArbitation_translated_ready; + wire logic_pop_sync_readArbitation_translated_payload_kind; + wire logic_pop_sync_readArbitation_translated_payload_read; + wire logic_pop_sync_readArbitation_translated_payload_write; + wire [7:0] logic_pop_sync_readArbitation_translated_payload_data; + wire logic_pop_sync_readArbitation_fire; + reg [8:0] logic_pop_sync_popReg; + reg [10:0] logic_ram [0:255]; + + assign _zz_logic_ram_port = {logic_push_onRam_write_payload_data_data,{logic_push_onRam_write_payload_data_write,{logic_push_onRam_write_payload_data_read,logic_push_onRam_write_payload_data_kind}}}; + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_push_onRam_write_payload_address] <= _zz_logic_ram_port; + end + end + + always @(posedge clk) begin + if(logic_pop_sync_readPort_cmd_valid) begin + logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_push_onRam_write_valid) begin + _zz_1 = 1'b1; + end + end + + assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); + assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 9'h100) == 9'h0); + assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop); + assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo); + assign io_push_ready = (! logic_ptr_full); + assign io_push_fire = (io_push_valid && io_push_ready); + assign logic_ptr_doPush = io_push_fire; + assign logic_push_onRam_write_valid = io_push_fire; + assign logic_push_onRam_write_payload_address = logic_ptr_push[7:0]; + assign logic_push_onRam_write_payload_data_kind = io_push_payload_kind; + assign logic_push_onRam_write_payload_data_read = io_push_payload_read; + assign logic_push_onRam_write_payload_data_write = io_push_payload_write; + assign logic_push_onRam_write_payload_data_data = io_push_payload_data; + assign logic_pop_addressGen_valid = (! logic_ptr_empty); + assign logic_pop_addressGen_payload = logic_ptr_pop[7:0]; + assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); + assign logic_ptr_doPop = logic_pop_addressGen_fire; + always @(*) begin + logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; + if(when_Stream_l375) begin + logic_pop_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); + assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; + assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; + assign _zz_logic_pop_sync_readPort_rsp_kind = logic_ram_spinal_port1; + assign logic_pop_sync_readPort_rsp_kind = _zz_logic_pop_sync_readPort_rsp_kind[0]; + assign logic_pop_sync_readPort_rsp_read = _zz_logic_pop_sync_readPort_rsp_kind[1]; + assign logic_pop_sync_readPort_rsp_write = _zz_logic_pop_sync_readPort_rsp_kind[2]; + assign logic_pop_sync_readPort_rsp_data = _zz_logic_pop_sync_readPort_rsp_kind[10 : 3]; + assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; + assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; + assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; + assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; + assign logic_pop_sync_readArbitation_translated_payload_kind = logic_pop_sync_readPort_rsp_kind; + assign logic_pop_sync_readArbitation_translated_payload_read = logic_pop_sync_readPort_rsp_read; + assign logic_pop_sync_readArbitation_translated_payload_write = logic_pop_sync_readPort_rsp_write; + assign logic_pop_sync_readArbitation_translated_payload_data = logic_pop_sync_readPort_rsp_data; + assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; + assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_kind = logic_pop_sync_readArbitation_translated_payload_kind; + assign io_pop_payload_read = logic_pop_sync_readArbitation_translated_payload_read; + assign io_pop_payload_write = logic_pop_sync_readArbitation_translated_payload_write; + assign io_pop_payload_data = logic_pop_sync_readArbitation_translated_payload_data; + assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); + assign logic_ptr_popOnIo = logic_pop_sync_popReg; + assign io_occupancy = logic_ptr_occupancy; + assign io_availability = (9'h100 - logic_ptr_occupancy); + always @(posedge clk) begin + if(reset) begin + logic_ptr_push <= 9'h0; + logic_ptr_pop <= 9'h0; + logic_ptr_wentUp <= 1'b0; + logic_pop_addressGen_rValid <= 1'b0; + logic_pop_sync_popReg <= 9'h0; + end else begin + if(when_Stream_l1248) begin + logic_ptr_wentUp <= logic_ptr_doPush; + end + if(io_flush) begin + logic_ptr_wentUp <= 1'b0; + end + if(logic_ptr_doPush) begin + logic_ptr_push <= (logic_ptr_push + 9'h001); + end + if(logic_ptr_doPop) begin + logic_ptr_pop <= (logic_ptr_pop + 9'h001); + end + if(io_flush) begin + logic_ptr_push <= 9'h0; + logic_ptr_pop <= 9'h0; + end + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; + end + if(io_flush) begin + logic_pop_addressGen_rValid <= 1'b0; + end + if(logic_pop_sync_readArbitation_fire) begin + logic_pop_sync_popReg <= logic_ptr_pop; + end + if(io_flush) begin + logic_pop_sync_popReg <= 9'h0; + end + end + end + + always @(posedge clk) begin + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rData <= logic_pop_addressGen_payload; + end + end + + +endmodule + +module Axi4PeripheralTopLevel ( + input wire io_config_kind_cpol, + input wire io_config_kind_cpha, + input wire [11:0] io_config_sclkToggle, + input wire [1:0] io_config_mod, + input wire [3:0] io_config_ss_activeHigh, + input wire [11:0] io_config_ss_setup, + input wire [11:0] io_config_ss_hold, + input wire [11:0] io_config_ss_disable, + input wire io_cmd_valid, + output reg io_cmd_ready, + input wire io_cmd_payload_kind, + input wire io_cmd_payload_read, + input wire io_cmd_payload_write, + input wire [7:0] io_cmd_payload_data, + output wire io_rsp_valid, + output wire [7:0] io_rsp_payload_data, + output wire [0:0] io_spi_sclk_write, + output reg io_spi_data_0_writeEnable, + input wire [0:0] io_spi_data_0_read, + output reg [0:0] io_spi_data_0_write, + output reg io_spi_data_1_writeEnable, + input wire [0:0] io_spi_data_1_read, + output reg [0:0] io_spi_data_1_write, + output reg io_spi_data_2_writeEnable, + input wire [0:0] io_spi_data_2_read, + output reg [0:0] io_spi_data_2_write, + output reg io_spi_data_3_writeEnable, + input wire [0:0] io_spi_data_3_read, + output reg [0:0] io_spi_data_3_write, + output wire [3:0] io_spi_ss, + input wire clk, + input wire reset +); + + reg [0:0] _zz_outputPhy_dataWrite_3; + wire [2:0] _zz_outputPhy_dataWrite_4; + reg [1:0] _zz_outputPhy_dataWrite_5; + wire [1:0] _zz_outputPhy_dataWrite_6; + wire [2:0] _zz_outputPhy_dataWrite_7; + reg [3:0] _zz_outputPhy_dataWrite_8; + wire [0:0] _zz_outputPhy_dataWrite_9; + wire [2:0] _zz_outputPhy_dataWrite_10; + wire [3:0] _zz_inputPhy_dataRead; + wire [3:0] _zz_inputPhy_dataRead_1; + wire [3:0] _zz_inputPhy_dataRead_2; + wire [3:0] _zz_inputPhy_dataRead_3; + wire [3:0] _zz_inputPhy_dataRead_4; + wire [3:0] _zz_inputPhy_dataRead_5; + wire [3:0] _zz_inputPhy_dataRead_6; + wire [8:0] _zz_inputPhy_bufferNext; + wire [10:0] _zz_inputPhy_bufferNext_1; + reg [11:0] timer_counter; + reg timer_reset; + wire timer_ss_setupHit; + wire timer_ss_holdHit; + wire timer_ss_disableHit; + wire timer_sclkToggleHit; + reg fsm_state; + reg [2:0] fsm_counter; + reg [2:0] _zz_fsm_counterPlus; + wire [2:0] fsm_counterPlus; + reg fsm_fastRate; + reg fsm_isDdr; + reg [2:0] fsm_counterMax; + reg fsm_lateSampling; + reg fsm_readFill; + reg fsm_readDone; + reg [3:0] fsm_ss; + wire when_SpiXdrMasterCtrl_l741; + wire when_SpiXdrMasterCtrl_l744; + wire when_SpiXdrMasterCtrl_l751; + wire when_SpiXdrMasterCtrl_l753; + wire when_SpiXdrMasterCtrl_l760; + wire when_SpiXdrMasterCtrl_l766; + wire when_SpiXdrMasterCtrl_l783; + reg [0:0] outputPhy_sclkWrite; + wire [0:0] _zz_io_spi_sclk_write; + wire when_SpiXdrMasterCtrl_l798; + reg [3:0] outputPhy_dataWrite; + reg [2:0] outputPhy_widthSel; + reg [2:0] outputPhy_offset; + wire [7:0] _zz_outputPhy_dataWrite; + wire [7:0] _zz_outputPhy_dataWrite_1; + wire [7:0] _zz_outputPhy_dataWrite_2; + wire when_SpiXdrMasterCtrl_l841; + wire when_SpiXdrMasterCtrl_l841_1; + reg [1:0] io_config_mod_delay_1; + reg [1:0] inputPhy_mod; + reg fsm_readFill_delay_1; + reg inputPhy_readFill; + reg fsm_readDone_delay_1; + reg inputPhy_readDone; + reg [6:0] inputPhy_buffer; + reg [7:0] inputPhy_bufferNext; + reg [2:0] inputPhy_widthSel; + wire [3:0] inputPhy_dataWrite; + reg [3:0] inputPhy_dataRead; + reg fsm_state_delay_1; + reg fsm_state_delay_2; + wire when_SpiXdrMasterCtrl_l863; + reg [3:0] inputPhy_dataReadBuffer; + + assign _zz_outputPhy_dataWrite_4 = (outputPhy_offset - fsm_counter); + assign _zz_outputPhy_dataWrite_6 = (_zz_outputPhy_dataWrite_7 >>> 1'd1); + assign _zz_outputPhy_dataWrite_7 = (outputPhy_offset - fsm_counter); + assign _zz_outputPhy_dataWrite_9 = (_zz_outputPhy_dataWrite_10 >>> 2'd2); + assign _zz_outputPhy_dataWrite_10 = (outputPhy_offset - fsm_counter); + assign _zz_inputPhy_dataRead = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_1 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_2 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_3 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_4 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_5 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_6 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[1 : 0]}; + assign _zz_inputPhy_bufferNext_1 = {inputPhy_buffer,inputPhy_dataRead[3 : 0]}; + always @(*) begin + case(_zz_outputPhy_dataWrite_4) + 3'b000 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[0 : 0]; + 3'b001 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[1 : 1]; + 3'b010 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[2 : 2]; + 3'b011 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[3 : 3]; + 3'b100 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[4 : 4]; + 3'b101 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[5 : 5]; + 3'b110 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[6 : 6]; + default : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[7 : 7]; + endcase + end + + always @(*) begin + case(_zz_outputPhy_dataWrite_6) + 2'b00 : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[1 : 0]; + 2'b01 : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[3 : 2]; + 2'b10 : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[5 : 4]; + default : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[7 : 6]; + endcase + end + + always @(*) begin + case(_zz_outputPhy_dataWrite_9) + 1'b0 : _zz_outputPhy_dataWrite_8 = _zz_outputPhy_dataWrite_2[3 : 0]; + default : _zz_outputPhy_dataWrite_8 = _zz_outputPhy_dataWrite_2[7 : 4]; + endcase + end + + always @(*) begin + timer_reset = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l741) begin + timer_reset = timer_sclkToggleHit; + end else begin + if(!when_SpiXdrMasterCtrl_l760) begin + if(when_SpiXdrMasterCtrl_l766) begin + if(timer_ss_holdHit) begin + timer_reset = 1'b1; + end + end + end + end + end + if(when_SpiXdrMasterCtrl_l783) begin + timer_reset = 1'b1; + end + end + + assign timer_ss_setupHit = (timer_counter == io_config_ss_setup); + assign timer_ss_holdHit = (timer_counter == io_config_ss_hold); + assign timer_ss_disableHit = (timer_counter == io_config_ss_disable); + assign timer_sclkToggleHit = (timer_counter == io_config_sclkToggle); + always @(*) begin + _zz_fsm_counterPlus = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + _zz_fsm_counterPlus = 3'b001; + end + 2'b01 : begin + _zz_fsm_counterPlus = 3'b010; + end + 2'b10 : begin + _zz_fsm_counterPlus = 3'b100; + end + default : begin + end + endcase + end + + assign fsm_counterPlus = (fsm_counter + _zz_fsm_counterPlus); + always @(*) begin + fsm_fastRate = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_fastRate = 1'b0; + end + 2'b01 : begin + fsm_fastRate = 1'b0; + end + 2'b10 : begin + fsm_fastRate = 1'b0; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_isDdr = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_isDdr = 1'b0; + end + 2'b01 : begin + fsm_isDdr = 1'b0; + end + 2'b10 : begin + fsm_isDdr = 1'b0; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_counterMax = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + fsm_counterMax = 3'b111; + end + 2'b01 : begin + fsm_counterMax = 3'b110; + end + 2'b10 : begin + fsm_counterMax = 3'b100; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_lateSampling = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_lateSampling = 1'b1; + end + 2'b01 : begin + fsm_lateSampling = 1'b1; + end + 2'b10 : begin + fsm_lateSampling = 1'b1; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_readFill = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l741) begin + if(when_SpiXdrMasterCtrl_l744) begin + fsm_readFill = 1'b1; + end + end + end + end + + always @(*) begin + fsm_readDone = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l741) begin + if(when_SpiXdrMasterCtrl_l744) begin + fsm_readDone = (io_cmd_payload_read && (fsm_counter == fsm_counterMax)); + end + end + end + end + + assign io_spi_ss = (~ (fsm_ss ^ io_config_ss_activeHigh)); + always @(*) begin + io_cmd_ready = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l741) begin + if(when_SpiXdrMasterCtrl_l751) begin + if(when_SpiXdrMasterCtrl_l753) begin + io_cmd_ready = 1'b1; + end + end + end else begin + if(when_SpiXdrMasterCtrl_l760) begin + if(timer_ss_setupHit) begin + io_cmd_ready = 1'b1; + end + end else begin + if(!when_SpiXdrMasterCtrl_l766) begin + if(timer_ss_disableHit) begin + io_cmd_ready = 1'b1; + end + end + end + end + end + end + + assign when_SpiXdrMasterCtrl_l741 = (! io_cmd_payload_kind); + assign when_SpiXdrMasterCtrl_l744 = ((timer_sclkToggleHit && (((! fsm_state) ^ fsm_lateSampling) || fsm_isDdr)) || fsm_fastRate); + assign when_SpiXdrMasterCtrl_l751 = ((timer_sclkToggleHit && (fsm_state || fsm_isDdr)) || fsm_fastRate); + assign when_SpiXdrMasterCtrl_l753 = (fsm_counter == fsm_counterMax); + assign when_SpiXdrMasterCtrl_l760 = io_cmd_payload_data[7]; + assign when_SpiXdrMasterCtrl_l766 = (! fsm_state); + assign when_SpiXdrMasterCtrl_l783 = ((! io_cmd_valid) || io_cmd_ready); + always @(*) begin + outputPhy_sclkWrite = 1'b0; + if(when_SpiXdrMasterCtrl_l798) begin + case(io_config_mod) + 2'b00 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + 2'b01 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + 2'b10 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + default : begin + end + endcase + end + end + + assign _zz_io_spi_sclk_write[0] = io_config_kind_cpol; + assign io_spi_sclk_write = (outputPhy_sclkWrite ^ _zz_io_spi_sclk_write); + assign when_SpiXdrMasterCtrl_l798 = (io_cmd_valid && (! io_cmd_payload_kind)); + always @(*) begin + outputPhy_widthSel = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + outputPhy_widthSel = 3'b000; + end + 2'b01 : begin + outputPhy_widthSel = 3'b001; + end + 2'b10 : begin + outputPhy_widthSel = 3'b010; + end + default : begin + end + endcase + end + + always @(*) begin + outputPhy_offset = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + outputPhy_offset = 3'b111; + end + 2'b01 : begin + outputPhy_offset = 3'b111; + end + 2'b10 : begin + outputPhy_offset = 3'b111; + end + default : begin + end + endcase + end + + always @(*) begin + outputPhy_dataWrite = 4'bxxxx; + case(outputPhy_widthSel) + 3'b000 : begin + outputPhy_dataWrite[0 : 0] = _zz_outputPhy_dataWrite_3; + end + 3'b001 : begin + outputPhy_dataWrite[1 : 0] = _zz_outputPhy_dataWrite_5; + end + 3'b010 : begin + outputPhy_dataWrite[3 : 0] = _zz_outputPhy_dataWrite_8; + end + default : begin + end + endcase + end + + assign _zz_outputPhy_dataWrite = io_cmd_payload_data; + assign _zz_outputPhy_dataWrite_1 = io_cmd_payload_data; + assign _zz_outputPhy_dataWrite_2 = io_cmd_payload_data; + always @(*) begin + io_spi_data_0_writeEnable = 1'b0; + case(io_config_mod) + 2'b00 : begin + io_spi_data_0_writeEnable = 1'b1; + end + 2'b01 : begin + if(when_SpiXdrMasterCtrl_l841) begin + io_spi_data_0_writeEnable = 1'b1; + end + end + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l841_1) begin + io_spi_data_0_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_1_writeEnable = 1'b0; + case(io_config_mod) + 2'b01 : begin + if(when_SpiXdrMasterCtrl_l841) begin + io_spi_data_1_writeEnable = 1'b1; + end + end + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l841_1) begin + io_spi_data_1_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_2_writeEnable = 1'b0; + case(io_config_mod) + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l841_1) begin + io_spi_data_2_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_3_writeEnable = 1'b0; + case(io_config_mod) + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l841_1) begin + io_spi_data_3_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_0_write = 1'bx; + case(io_config_mod) + 2'b00 : begin + io_spi_data_0_write[0] = (outputPhy_dataWrite[0] || (! (io_cmd_valid && io_cmd_payload_write))); + end + 2'b01 : begin + io_spi_data_0_write[0] = outputPhy_dataWrite[0]; + end + 2'b10 : begin + io_spi_data_0_write[0] = outputPhy_dataWrite[0]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_1_write = 1'bx; + case(io_config_mod) + 2'b01 : begin + io_spi_data_1_write[0] = outputPhy_dataWrite[1]; + end + 2'b10 : begin + io_spi_data_1_write[0] = outputPhy_dataWrite[1]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_2_write = 1'bx; + case(io_config_mod) + 2'b10 : begin + io_spi_data_2_write[0] = outputPhy_dataWrite[2]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_3_write = 1'bx; + case(io_config_mod) + 2'b10 : begin + io_spi_data_3_write[0] = outputPhy_dataWrite[3]; + end + default : begin + end + endcase + end + + assign when_SpiXdrMasterCtrl_l841 = (io_cmd_valid && io_cmd_payload_write); + assign when_SpiXdrMasterCtrl_l841_1 = (io_cmd_valid && io_cmd_payload_write); + always @(*) begin + inputPhy_bufferNext = 8'bxxxxxxxx; + case(inputPhy_widthSel) + 3'b000 : begin + inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[0 : 0]}; + end + 3'b001 : begin + inputPhy_bufferNext = _zz_inputPhy_bufferNext[7:0]; + end + 3'b010 : begin + inputPhy_bufferNext = _zz_inputPhy_bufferNext_1[7:0]; + end + default : begin + end + endcase + end + + always @(*) begin + inputPhy_widthSel = 3'bxxx; + case(inputPhy_mod) + 2'b00 : begin + inputPhy_widthSel = 3'b000; + end + 2'b01 : begin + inputPhy_widthSel = 3'b001; + end + 2'b10 : begin + inputPhy_widthSel = 3'b010; + end + default : begin + end + endcase + end + + assign when_SpiXdrMasterCtrl_l863 = (! fsm_state_delay_2); + always @(*) begin + inputPhy_dataRead = 4'bxxxx; + case(inputPhy_mod) + 2'b00 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead[1]; + end + 2'b01 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead_1[0]; + inputPhy_dataRead[1] = _zz_inputPhy_dataRead_2[1]; + end + 2'b10 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead_3[0]; + inputPhy_dataRead[1] = _zz_inputPhy_dataRead_4[1]; + inputPhy_dataRead[2] = _zz_inputPhy_dataRead_5[2]; + inputPhy_dataRead[3] = _zz_inputPhy_dataRead_6[3]; + end + default : begin + end + endcase + end + + assign io_rsp_valid = inputPhy_readDone; + assign io_rsp_payload_data = inputPhy_bufferNext; + always @(posedge clk) begin + timer_counter <= (timer_counter + 12'h001); + if(timer_reset) begin + timer_counter <= 12'h0; + end + io_config_mod_delay_1 <= io_config_mod; + inputPhy_mod <= io_config_mod_delay_1; + fsm_state_delay_1 <= fsm_state; + fsm_state_delay_2 <= fsm_state_delay_1; + if(when_SpiXdrMasterCtrl_l863) begin + inputPhy_dataReadBuffer <= {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + end + case(inputPhy_widthSel) + 3'b000 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + 3'b001 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + 3'b010 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + default : begin + end + endcase + end + + always @(posedge clk) begin + if(reset) begin + fsm_state <= 1'b0; + fsm_counter <= 3'b000; + fsm_ss <= 4'b0000; + fsm_readFill_delay_1 <= 1'b0; + inputPhy_readFill <= 1'b0; + fsm_readDone_delay_1 <= 1'b0; + inputPhy_readDone <= 1'b0; + end else begin + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l741) begin + if(timer_sclkToggleHit) begin + fsm_state <= (! fsm_state); + end + if(when_SpiXdrMasterCtrl_l751) begin + fsm_counter <= fsm_counterPlus; + if(when_SpiXdrMasterCtrl_l753) begin + fsm_state <= 1'b0; + end + end + end else begin + if(when_SpiXdrMasterCtrl_l760) begin + fsm_ss[io_cmd_payload_data[1 : 0]] <= 1'b1; + end else begin + if(when_SpiXdrMasterCtrl_l766) begin + if(timer_ss_holdHit) begin + fsm_state <= 1'b1; + end + end else begin + fsm_ss[io_cmd_payload_data[1 : 0]] <= 1'b0; + end + end + end + end + if(when_SpiXdrMasterCtrl_l783) begin + fsm_state <= 1'b0; + fsm_counter <= 3'b000; + end + fsm_readFill_delay_1 <= fsm_readFill; + inputPhy_readFill <= fsm_readFill_delay_1; + fsm_readDone_delay_1 <= fsm_readDone; + inputPhy_readDone <= fsm_readDone_delay_1; + end + end + + +endmodule + +//Axi4PeripheralStreamFifo_1 replaced by Axi4PeripheralStreamFifo + +module Axi4PeripheralStreamFifo ( + input wire io_push_valid, + output wire io_push_ready, + input wire [7:0] io_push_payload, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [7:0] io_pop_payload, + input wire io_flush, + output wire [7:0] io_occupancy, + output wire [7:0] io_availability, + input wire clk, + input wire reset +); + + reg [7:0] logic_ram_spinal_port1; + reg _zz_1; + wire logic_ptr_doPush; + wire logic_ptr_doPop; + wire logic_ptr_full; + wire logic_ptr_empty; + reg [7:0] logic_ptr_push; + reg [7:0] logic_ptr_pop; + wire [7:0] logic_ptr_occupancy; + wire [7:0] logic_ptr_popOnIo; + wire when_Stream_l1248; + reg logic_ptr_wentUp; + wire io_push_fire; + wire logic_push_onRam_write_valid; + wire [6:0] logic_push_onRam_write_payload_address; + wire [7:0] logic_push_onRam_write_payload_data; + wire logic_pop_addressGen_valid; + reg logic_pop_addressGen_ready; + wire [6:0] logic_pop_addressGen_payload; + wire logic_pop_addressGen_fire; + wire logic_pop_sync_readArbitation_valid; + wire logic_pop_sync_readArbitation_ready; + wire [6:0] logic_pop_sync_readArbitation_payload; + reg logic_pop_addressGen_rValid; + reg [6:0] logic_pop_addressGen_rData; + wire when_Stream_l375; + wire logic_pop_sync_readPort_cmd_valid; + wire [6:0] logic_pop_sync_readPort_cmd_payload; + wire [7:0] logic_pop_sync_readPort_rsp; + wire logic_pop_sync_readArbitation_translated_valid; + wire logic_pop_sync_readArbitation_translated_ready; + wire [7:0] logic_pop_sync_readArbitation_translated_payload; + wire logic_pop_sync_readArbitation_fire; + reg [7:0] logic_pop_sync_popReg; + reg [7:0] logic_ram [0:127]; + + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data; + end + end + + always @(posedge clk) begin + if(logic_pop_sync_readPort_cmd_valid) begin + logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_push_onRam_write_valid) begin + _zz_1 = 1'b1; + end + end + + assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); + assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 8'h80) == 8'h0); + assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop); + assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo); + assign io_push_ready = (! logic_ptr_full); + assign io_push_fire = (io_push_valid && io_push_ready); + assign logic_ptr_doPush = io_push_fire; + assign logic_push_onRam_write_valid = io_push_fire; + assign logic_push_onRam_write_payload_address = logic_ptr_push[6:0]; + assign logic_push_onRam_write_payload_data = io_push_payload; + assign logic_pop_addressGen_valid = (! logic_ptr_empty); + assign logic_pop_addressGen_payload = logic_ptr_pop[6:0]; + assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); + assign logic_ptr_doPop = logic_pop_addressGen_fire; + always @(*) begin + logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; + if(when_Stream_l375) begin + logic_pop_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); + assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; + assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; + assign logic_pop_sync_readPort_rsp = logic_ram_spinal_port1; + assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; + assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; + assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; + assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; + assign logic_pop_sync_readArbitation_translated_payload = logic_pop_sync_readPort_rsp; + assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; + assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload = logic_pop_sync_readArbitation_translated_payload; + assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); + assign logic_ptr_popOnIo = logic_pop_sync_popReg; + assign io_occupancy = logic_ptr_occupancy; + assign io_availability = (8'h80 - logic_ptr_occupancy); + always @(posedge clk) begin + if(reset) begin + logic_ptr_push <= 8'h0; + logic_ptr_pop <= 8'h0; + logic_ptr_wentUp <= 1'b0; + logic_pop_addressGen_rValid <= 1'b0; + logic_pop_sync_popReg <= 8'h0; + end else begin + if(when_Stream_l1248) begin + logic_ptr_wentUp <= logic_ptr_doPush; + end + if(io_flush) begin + logic_ptr_wentUp <= 1'b0; + end + if(logic_ptr_doPush) begin + logic_ptr_push <= (logic_ptr_push + 8'h01); + end + if(logic_ptr_doPop) begin + logic_ptr_pop <= (logic_ptr_pop + 8'h01); + end + if(io_flush) begin + logic_ptr_push <= 8'h0; + logic_ptr_pop <= 8'h0; + end + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; + end + if(io_flush) begin + logic_pop_addressGen_rValid <= 1'b0; + end + if(logic_pop_sync_readArbitation_fire) begin + logic_pop_sync_popReg <= logic_ptr_pop; + end + if(io_flush) begin + logic_pop_sync_popReg <= 8'h0; + end + end + end + + always @(posedge clk) begin + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rData <= logic_pop_addressGen_payload; + end + end + + +endmodule + +module Axi4PeripheralUartCtrl ( + input wire [2:0] io_config_frame_dataLength, + input wire [0:0] io_config_frame_stop, + input wire [1:0] io_config_frame_parity, + input wire [19:0] io_config_clockDivider, + input wire io_write_valid, + output reg io_write_ready, + input wire [7:0] io_write_payload, + output wire io_read_valid, + input wire io_read_ready, + output wire [7:0] io_read_payload, + output wire io_uart_txd, + input wire io_uart_rxd, + output wire io_readError, + input wire io_writeBreak, + output wire io_readBreak, + input wire clk, + input wire reset +); + localparam Axi4PeripheralUartStopType_ONE = 1'd0; + localparam Axi4PeripheralUartStopType_TWO = 1'd1; + localparam Axi4PeripheralUartParityType_NONE = 2'd0; + localparam Axi4PeripheralUartParityType_EVEN = 2'd1; + localparam Axi4PeripheralUartParityType_ODD = 2'd2; + + wire tx_io_write_ready; + wire tx_io_txd; + wire rx_io_read_valid; + wire [7:0] rx_io_read_payload; + wire rx_io_rts; + wire rx_io_error; + wire rx_io_break; + reg [19:0] clockDivider_counter; + wire clockDivider_tick; + reg clockDivider_tickReg; + reg io_write_thrown_valid; + wire io_write_thrown_ready; + wire [7:0] io_write_thrown_payload; + `ifndef SYNTHESIS + reg [23:0] io_config_frame_stop_string; + reg [31:0] io_config_frame_parity_string; + `endif + + + Axi4PeripheralUartCtrlTx tx ( + .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i + .io_configFrame_stop (io_config_frame_stop ), //i + .io_configFrame_parity (io_config_frame_parity[1:0] ), //i + .io_samplingTick (clockDivider_tickReg ), //i + .io_write_valid (io_write_thrown_valid ), //i + .io_write_ready (tx_io_write_ready ), //o + .io_write_payload (io_write_thrown_payload[7:0] ), //i + .io_cts (1'b0 ), //i + .io_txd (tx_io_txd ), //o + .io_break (io_writeBreak ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralUartCtrlRx rx ( + .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i + .io_configFrame_stop (io_config_frame_stop ), //i + .io_configFrame_parity (io_config_frame_parity[1:0] ), //i + .io_samplingTick (clockDivider_tickReg ), //i + .io_read_valid (rx_io_read_valid ), //o + .io_read_ready (io_read_ready ), //i + .io_read_payload (rx_io_read_payload[7:0] ), //o + .io_rxd (io_uart_rxd ), //i + .io_rts (rx_io_rts ), //o + .io_error (rx_io_error ), //o + .io_break (rx_io_break ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_config_frame_stop) + Axi4PeripheralUartStopType_ONE : io_config_frame_stop_string = "ONE"; + Axi4PeripheralUartStopType_TWO : io_config_frame_stop_string = "TWO"; + default : io_config_frame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_config_frame_parity) + Axi4PeripheralUartParityType_NONE : io_config_frame_parity_string = "NONE"; + Axi4PeripheralUartParityType_EVEN : io_config_frame_parity_string = "EVEN"; + Axi4PeripheralUartParityType_ODD : io_config_frame_parity_string = "ODD "; + default : io_config_frame_parity_string = "????"; + endcase + end + `endif + + assign clockDivider_tick = (clockDivider_counter == 20'h0); + always @(*) begin + io_write_thrown_valid = io_write_valid; + if(rx_io_break) begin + io_write_thrown_valid = 1'b0; + end + end + + always @(*) begin + io_write_ready = io_write_thrown_ready; + if(rx_io_break) begin + io_write_ready = 1'b1; + end + end + + assign io_write_thrown_payload = io_write_payload; + assign io_write_thrown_ready = tx_io_write_ready; + assign io_read_valid = rx_io_read_valid; + assign io_read_payload = rx_io_read_payload; + assign io_uart_txd = tx_io_txd; + assign io_readError = rx_io_error; + assign io_readBreak = rx_io_break; + always @(posedge clk) begin + if(reset) begin + clockDivider_counter <= 20'h0; + clockDivider_tickReg <= 1'b0; + end else begin + clockDivider_tickReg <= clockDivider_tick; + clockDivider_counter <= (clockDivider_counter - 20'h00001); + if(clockDivider_tick) begin + clockDivider_counter <= io_config_clockDivider; + end + end + end + + +endmodule + +//Axi4PeripheralBufferCC_2 replaced by Axi4PeripheralBufferCC_1 + +module Axi4PeripheralBufferCC_1 ( + input wire io_dataIn, + output wire io_dataOut, + input wire clk, + input wire reset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge clk) begin + if(reset) begin + buffers_0 <= 1'b1; + buffers_1 <= 1'b1; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module Axi4PeripheralUartCtrlRx ( + input wire [2:0] io_configFrame_dataLength, + input wire [0:0] io_configFrame_stop, + input wire [1:0] io_configFrame_parity, + input wire io_samplingTick, + output wire io_read_valid, + input wire io_read_ready, + output wire [7:0] io_read_payload, + input wire io_rxd, + output wire io_rts, + output reg io_error, + output wire io_break, + input wire clk, + input wire reset +); + localparam Axi4PeripheralUartStopType_ONE = 1'd0; + localparam Axi4PeripheralUartStopType_TWO = 1'd1; + localparam Axi4PeripheralUartParityType_NONE = 2'd0; + localparam Axi4PeripheralUartParityType_EVEN = 2'd1; + localparam Axi4PeripheralUartParityType_ODD = 2'd2; + localparam Axi4PeripheralUartCtrlRxState_IDLE = 3'd0; + localparam Axi4PeripheralUartCtrlRxState_START = 3'd1; + localparam Axi4PeripheralUartCtrlRxState_DATA = 3'd2; + localparam Axi4PeripheralUartCtrlRxState_PARITY = 3'd3; + localparam Axi4PeripheralUartCtrlRxState_STOP = 3'd4; + + wire io_rxd_buffercc_io_dataOut; + wire _zz_sampler_value; + wire _zz_sampler_value_1; + wire _zz_sampler_value_2; + wire _zz_sampler_value_3; + wire _zz_sampler_value_4; + wire _zz_sampler_value_5; + wire _zz_sampler_value_6; + wire [2:0] _zz_when_UartCtrlRx_l139; + wire [0:0] _zz_when_UartCtrlRx_l139_1; + reg _zz_io_rts; + wire sampler_synchroniser; + wire sampler_samples_0; + reg sampler_samples_1; + reg sampler_samples_2; + reg sampler_samples_3; + reg sampler_samples_4; + reg sampler_value; + reg sampler_tick; + reg [2:0] bitTimer_counter; + reg bitTimer_tick; + wire when_UartCtrlRx_l43; + reg [2:0] bitCounter_value; + reg [6:0] break_counter; + wire break_valid; + wire when_UartCtrlRx_l69; + reg [2:0] stateMachine_state; + reg stateMachine_parity; + reg [7:0] stateMachine_shifter; + reg stateMachine_validReg; + wire when_UartCtrlRx_l93; + wire when_UartCtrlRx_l103; + wire when_UartCtrlRx_l111; + wire when_UartCtrlRx_l113; + wire when_UartCtrlRx_l125; + wire when_UartCtrlRx_l136; + wire when_UartCtrlRx_l139; + `ifndef SYNTHESIS + reg [23:0] io_configFrame_stop_string; + reg [31:0] io_configFrame_parity_string; + reg [47:0] stateMachine_state_string; + `endif + + + assign _zz_when_UartCtrlRx_l139_1 = ((io_configFrame_stop == Axi4PeripheralUartStopType_ONE) ? 1'b0 : 1'b1); + assign _zz_when_UartCtrlRx_l139 = {2'd0, _zz_when_UartCtrlRx_l139_1}; + assign _zz_sampler_value = ((((1'b0 || ((_zz_sampler_value_1 && sampler_samples_1) && sampler_samples_2)) || (((_zz_sampler_value_2 && sampler_samples_0) && sampler_samples_1) && sampler_samples_3)) || (((1'b1 && sampler_samples_0) && sampler_samples_2) && sampler_samples_3)) || (((1'b1 && sampler_samples_1) && sampler_samples_2) && sampler_samples_3)); + assign _zz_sampler_value_3 = (((1'b1 && sampler_samples_0) && sampler_samples_1) && sampler_samples_4); + assign _zz_sampler_value_4 = ((1'b1 && sampler_samples_0) && sampler_samples_2); + assign _zz_sampler_value_5 = (1'b1 && sampler_samples_1); + assign _zz_sampler_value_6 = 1'b1; + assign _zz_sampler_value_1 = (1'b1 && sampler_samples_0); + assign _zz_sampler_value_2 = 1'b1; + (* keep_hierarchy = "TRUE" *) Axi4PeripheralBufferCC io_rxd_buffercc ( + .io_dataIn (io_rxd ), //i + .io_dataOut (io_rxd_buffercc_io_dataOut), //o + .clk (clk ), //i + .reset (reset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_configFrame_stop) + Axi4PeripheralUartStopType_ONE : io_configFrame_stop_string = "ONE"; + Axi4PeripheralUartStopType_TWO : io_configFrame_stop_string = "TWO"; + default : io_configFrame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_configFrame_parity) + Axi4PeripheralUartParityType_NONE : io_configFrame_parity_string = "NONE"; + Axi4PeripheralUartParityType_EVEN : io_configFrame_parity_string = "EVEN"; + Axi4PeripheralUartParityType_ODD : io_configFrame_parity_string = "ODD "; + default : io_configFrame_parity_string = "????"; + endcase + end + always @(*) begin + case(stateMachine_state) + Axi4PeripheralUartCtrlRxState_IDLE : stateMachine_state_string = "IDLE "; + Axi4PeripheralUartCtrlRxState_START : stateMachine_state_string = "START "; + Axi4PeripheralUartCtrlRxState_DATA : stateMachine_state_string = "DATA "; + Axi4PeripheralUartCtrlRxState_PARITY : stateMachine_state_string = "PARITY"; + Axi4PeripheralUartCtrlRxState_STOP : stateMachine_state_string = "STOP "; + default : stateMachine_state_string = "??????"; + endcase + end + `endif + + always @(*) begin + io_error = 1'b0; + case(stateMachine_state) + Axi4PeripheralUartCtrlRxState_IDLE : begin + end + Axi4PeripheralUartCtrlRxState_START : begin + end + Axi4PeripheralUartCtrlRxState_DATA : begin + end + Axi4PeripheralUartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + if(!when_UartCtrlRx_l125) begin + io_error = 1'b1; + end + end + end + default : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l136) begin + io_error = 1'b1; + end + end + end + endcase + end + + assign io_rts = _zz_io_rts; + assign sampler_synchroniser = io_rxd_buffercc_io_dataOut; + assign sampler_samples_0 = sampler_synchroniser; + always @(*) begin + bitTimer_tick = 1'b0; + if(sampler_tick) begin + if(when_UartCtrlRx_l43) begin + bitTimer_tick = 1'b1; + end + end + end + + assign when_UartCtrlRx_l43 = (bitTimer_counter == 3'b000); + assign break_valid = (break_counter == 7'h68); + assign when_UartCtrlRx_l69 = (io_samplingTick && (! break_valid)); + assign io_break = break_valid; + assign io_read_valid = stateMachine_validReg; + assign when_UartCtrlRx_l93 = ((sampler_tick && (! sampler_value)) && (! break_valid)); + assign when_UartCtrlRx_l103 = (sampler_value == 1'b1); + assign when_UartCtrlRx_l111 = (bitCounter_value == io_configFrame_dataLength); + assign when_UartCtrlRx_l113 = (io_configFrame_parity == Axi4PeripheralUartParityType_NONE); + assign when_UartCtrlRx_l125 = (stateMachine_parity == sampler_value); + assign when_UartCtrlRx_l136 = (! sampler_value); + assign when_UartCtrlRx_l139 = (bitCounter_value == _zz_when_UartCtrlRx_l139); + assign io_read_payload = stateMachine_shifter; + always @(posedge clk) begin + if(reset) begin + _zz_io_rts <= 1'b0; + sampler_samples_1 <= 1'b1; + sampler_samples_2 <= 1'b1; + sampler_samples_3 <= 1'b1; + sampler_samples_4 <= 1'b1; + sampler_value <= 1'b1; + sampler_tick <= 1'b0; + break_counter <= 7'h0; + stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; + stateMachine_validReg <= 1'b0; + end else begin + _zz_io_rts <= (! io_read_ready); + if(io_samplingTick) begin + sampler_samples_1 <= sampler_samples_0; + end + if(io_samplingTick) begin + sampler_samples_2 <= sampler_samples_1; + end + if(io_samplingTick) begin + sampler_samples_3 <= sampler_samples_2; + end + if(io_samplingTick) begin + sampler_samples_4 <= sampler_samples_3; + end + sampler_value <= ((((((_zz_sampler_value || _zz_sampler_value_3) || (_zz_sampler_value_4 && sampler_samples_4)) || ((_zz_sampler_value_5 && sampler_samples_2) && sampler_samples_4)) || (((_zz_sampler_value_6 && sampler_samples_0) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_1) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_2) && sampler_samples_3) && sampler_samples_4)); + sampler_tick <= io_samplingTick; + if(sampler_value) begin + break_counter <= 7'h0; + end else begin + if(when_UartCtrlRx_l69) begin + break_counter <= (break_counter + 7'h01); + end + end + stateMachine_validReg <= 1'b0; + case(stateMachine_state) + Axi4PeripheralUartCtrlRxState_IDLE : begin + if(when_UartCtrlRx_l93) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_START; + end + end + Axi4PeripheralUartCtrlRxState_START : begin + if(bitTimer_tick) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_DATA; + if(when_UartCtrlRx_l103) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; + end + end + end + Axi4PeripheralUartCtrlRxState_DATA : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l111) begin + if(when_UartCtrlRx_l113) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_STOP; + stateMachine_validReg <= 1'b1; + end else begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_PARITY; + end + end + end + end + Axi4PeripheralUartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l125) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_STOP; + stateMachine_validReg <= 1'b1; + end else begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; + end + end + end + default : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l136) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; + end else begin + if(when_UartCtrlRx_l139) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; + end + end + end + end + endcase + end + end + + always @(posedge clk) begin + if(sampler_tick) begin + bitTimer_counter <= (bitTimer_counter - 3'b001); + end + if(bitTimer_tick) begin + bitCounter_value <= (bitCounter_value + 3'b001); + end + if(bitTimer_tick) begin + stateMachine_parity <= (stateMachine_parity ^ sampler_value); + end + case(stateMachine_state) + Axi4PeripheralUartCtrlRxState_IDLE : begin + if(when_UartCtrlRx_l93) begin + bitTimer_counter <= 3'b010; + end + end + Axi4PeripheralUartCtrlRxState_START : begin + if(bitTimer_tick) begin + bitCounter_value <= 3'b000; + stateMachine_parity <= (io_configFrame_parity == Axi4PeripheralUartParityType_ODD); + end + end + Axi4PeripheralUartCtrlRxState_DATA : begin + if(bitTimer_tick) begin + stateMachine_shifter[bitCounter_value] <= sampler_value; + if(when_UartCtrlRx_l111) begin + bitCounter_value <= 3'b000; + end + end + end + Axi4PeripheralUartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + bitCounter_value <= 3'b000; + end + end + default : begin + end + endcase + end + + +endmodule + +module Axi4PeripheralUartCtrlTx ( + input wire [2:0] io_configFrame_dataLength, + input wire [0:0] io_configFrame_stop, + input wire [1:0] io_configFrame_parity, + input wire io_samplingTick, + input wire io_write_valid, + output reg io_write_ready, + input wire [7:0] io_write_payload, + input wire io_cts, + output wire io_txd, + input wire io_break, + input wire clk, + input wire reset +); + localparam Axi4PeripheralUartStopType_ONE = 1'd0; + localparam Axi4PeripheralUartStopType_TWO = 1'd1; + localparam Axi4PeripheralUartParityType_NONE = 2'd0; + localparam Axi4PeripheralUartParityType_EVEN = 2'd1; + localparam Axi4PeripheralUartParityType_ODD = 2'd2; + localparam Axi4PeripheralUartCtrlTxState_IDLE = 3'd0; + localparam Axi4PeripheralUartCtrlTxState_START = 3'd1; + localparam Axi4PeripheralUartCtrlTxState_DATA = 3'd2; + localparam Axi4PeripheralUartCtrlTxState_PARITY = 3'd3; + localparam Axi4PeripheralUartCtrlTxState_STOP = 3'd4; + + wire [2:0] _zz_clockDivider_counter_valueNext; + wire [0:0] _zz_clockDivider_counter_valueNext_1; + wire [2:0] _zz_when_UartCtrlTx_l93; + wire [0:0] _zz_when_UartCtrlTx_l93_1; + reg clockDivider_counter_willIncrement; + wire clockDivider_counter_willClear; + reg [2:0] clockDivider_counter_valueNext; + reg [2:0] clockDivider_counter_value; + wire clockDivider_counter_willOverflowIfInc; + wire clockDivider_counter_willOverflow; + reg [2:0] tickCounter_value; + reg [2:0] stateMachine_state; + reg stateMachine_parity; + reg stateMachine_txd; + wire when_UartCtrlTx_l58; + wire when_UartCtrlTx_l73; + wire when_UartCtrlTx_l76; + wire when_UartCtrlTx_l93; + wire [2:0] _zz_stateMachine_state; + reg _zz_io_txd; + `ifndef SYNTHESIS + reg [23:0] io_configFrame_stop_string; + reg [31:0] io_configFrame_parity_string; + reg [47:0] stateMachine_state_string; + reg [47:0] _zz_stateMachine_state_string; + `endif + + + assign _zz_clockDivider_counter_valueNext_1 = clockDivider_counter_willIncrement; + assign _zz_clockDivider_counter_valueNext = {2'd0, _zz_clockDivider_counter_valueNext_1}; + assign _zz_when_UartCtrlTx_l93_1 = ((io_configFrame_stop == Axi4PeripheralUartStopType_ONE) ? 1'b0 : 1'b1); + assign _zz_when_UartCtrlTx_l93 = {2'd0, _zz_when_UartCtrlTx_l93_1}; + `ifndef SYNTHESIS + always @(*) begin + case(io_configFrame_stop) + Axi4PeripheralUartStopType_ONE : io_configFrame_stop_string = "ONE"; + Axi4PeripheralUartStopType_TWO : io_configFrame_stop_string = "TWO"; + default : io_configFrame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_configFrame_parity) + Axi4PeripheralUartParityType_NONE : io_configFrame_parity_string = "NONE"; + Axi4PeripheralUartParityType_EVEN : io_configFrame_parity_string = "EVEN"; + Axi4PeripheralUartParityType_ODD : io_configFrame_parity_string = "ODD "; + default : io_configFrame_parity_string = "????"; + endcase + end + always @(*) begin + case(stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : stateMachine_state_string = "IDLE "; + Axi4PeripheralUartCtrlTxState_START : stateMachine_state_string = "START "; + Axi4PeripheralUartCtrlTxState_DATA : stateMachine_state_string = "DATA "; + Axi4PeripheralUartCtrlTxState_PARITY : stateMachine_state_string = "PARITY"; + Axi4PeripheralUartCtrlTxState_STOP : stateMachine_state_string = "STOP "; + default : stateMachine_state_string = "??????"; + endcase + end + always @(*) begin + case(_zz_stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : _zz_stateMachine_state_string = "IDLE "; + Axi4PeripheralUartCtrlTxState_START : _zz_stateMachine_state_string = "START "; + Axi4PeripheralUartCtrlTxState_DATA : _zz_stateMachine_state_string = "DATA "; + Axi4PeripheralUartCtrlTxState_PARITY : _zz_stateMachine_state_string = "PARITY"; + Axi4PeripheralUartCtrlTxState_STOP : _zz_stateMachine_state_string = "STOP "; + default : _zz_stateMachine_state_string = "??????"; + endcase + end + `endif + + always @(*) begin + clockDivider_counter_willIncrement = 1'b0; + if(io_samplingTick) begin + clockDivider_counter_willIncrement = 1'b1; + end + end + + assign clockDivider_counter_willClear = 1'b0; + assign clockDivider_counter_willOverflowIfInc = (clockDivider_counter_value == 3'b111); + assign clockDivider_counter_willOverflow = (clockDivider_counter_willOverflowIfInc && clockDivider_counter_willIncrement); + always @(*) begin + clockDivider_counter_valueNext = (clockDivider_counter_value + _zz_clockDivider_counter_valueNext); + if(clockDivider_counter_willClear) begin + clockDivider_counter_valueNext = 3'b000; + end + end + + always @(*) begin + stateMachine_txd = 1'b1; + case(stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : begin + end + Axi4PeripheralUartCtrlTxState_START : begin + stateMachine_txd = 1'b0; + end + Axi4PeripheralUartCtrlTxState_DATA : begin + stateMachine_txd = io_write_payload[tickCounter_value]; + end + Axi4PeripheralUartCtrlTxState_PARITY : begin + stateMachine_txd = stateMachine_parity; + end + default : begin + end + endcase + end + + always @(*) begin + io_write_ready = io_break; + case(stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : begin + end + Axi4PeripheralUartCtrlTxState_START : begin + end + Axi4PeripheralUartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + io_write_ready = 1'b1; + end + end + end + Axi4PeripheralUartCtrlTxState_PARITY : begin + end + default : begin + end + endcase + end + + assign when_UartCtrlTx_l58 = ((io_write_valid && (! io_cts)) && clockDivider_counter_willOverflow); + assign when_UartCtrlTx_l73 = (tickCounter_value == io_configFrame_dataLength); + assign when_UartCtrlTx_l76 = (io_configFrame_parity == Axi4PeripheralUartParityType_NONE); + assign when_UartCtrlTx_l93 = (tickCounter_value == _zz_when_UartCtrlTx_l93); + assign _zz_stateMachine_state = (io_write_valid ? Axi4PeripheralUartCtrlTxState_START : Axi4PeripheralUartCtrlTxState_IDLE); + assign io_txd = _zz_io_txd; + always @(posedge clk) begin + if(reset) begin + clockDivider_counter_value <= 3'b000; + stateMachine_state <= Axi4PeripheralUartCtrlTxState_IDLE; + _zz_io_txd <= 1'b1; + end else begin + clockDivider_counter_value <= clockDivider_counter_valueNext; + case(stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : begin + if(when_UartCtrlTx_l58) begin + stateMachine_state <= Axi4PeripheralUartCtrlTxState_START; + end + end + Axi4PeripheralUartCtrlTxState_START : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_state <= Axi4PeripheralUartCtrlTxState_DATA; + end + end + Axi4PeripheralUartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + if(when_UartCtrlTx_l76) begin + stateMachine_state <= Axi4PeripheralUartCtrlTxState_STOP; + end else begin + stateMachine_state <= Axi4PeripheralUartCtrlTxState_PARITY; + end + end + end + end + Axi4PeripheralUartCtrlTxState_PARITY : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_state <= Axi4PeripheralUartCtrlTxState_STOP; + end + end + default : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l93) begin + stateMachine_state <= _zz_stateMachine_state; + end + end + end + endcase + _zz_io_txd <= (stateMachine_txd && (! io_break)); + end + end + + always @(posedge clk) begin + if(clockDivider_counter_willOverflow) begin + tickCounter_value <= (tickCounter_value + 3'b001); + end + if(clockDivider_counter_willOverflow) begin + stateMachine_parity <= (stateMachine_parity ^ stateMachine_txd); + end + case(stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : begin + end + Axi4PeripheralUartCtrlTxState_START : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_parity <= (io_configFrame_parity == Axi4PeripheralUartParityType_ODD); + tickCounter_value <= 3'b000; + end + end + Axi4PeripheralUartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + tickCounter_value <= 3'b000; + end + end + end + Axi4PeripheralUartCtrlTxState_PARITY : begin + if(clockDivider_counter_willOverflow) begin + tickCounter_value <= 3'b000; + end + end + default : begin + end + endcase + end + + +endmodule + +module Axi4PeripheralBufferCC ( + input wire io_dataIn, + output wire io_dataOut, + input wire clk, + input wire reset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge clk) begin + if(reset) begin + buffers_0 <= 1'b0; + buffers_1 <= 1'b0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule diff --git a/fpga/ip/EfxSapphireHpSoc_slb/source/peri_config b/fpga/ip/EfxSapphireHpSoc_slb/source/peri_config new file mode 100644 index 0000000..c0743d8 --- /dev/null +++ b/fpga/ip/EfxSapphireHpSoc_slb/source/peri_config @@ -0,0 +1,8 @@ +--peripheralFrequency 200000000 +--PeripheralClock true +--uart name=system_uart_0_io,address=0x10000,interruptId=0 +--apbSlave name=io_apbSlave_0,address=0x100000,size=65536 +--watchdog name=system_watchdog,address=0x50000,interruptId=13,prescalerWidth=24,counters=2,countersWidth=16 +--gpio name=system_gpio_0_io,address=0x40000,width=4,interrupts="0->9;1->10" +--i2c name=system_i2c_0_io,address=0x20000,interruptId=6 +--spi name=system_spi_0_io,address=0x30000,interruptId=3,width=8,ssCount=4 diff --git a/fpga/ip/gAXIM_2to1_switch/axi_interconnect.vh b/fpga/ip/gAXIM_2to1_switch/axi_interconnect.vh new file mode 100644 index 0000000..cf9993c --- /dev/null +++ b/fpga/ip/gAXIM_2to1_switch/axi_interconnect.vh @@ -0,0 +1,2 @@ +localparam M_BASE_ADDR = {32'h41000000,32'h40000000,32'h30000000,32'h20000000,32'h11100000,32'h11000000,32'h10000000,32'h0}; +localparam M_ADDR_WIDTH = {32'd20,32'd24,32'd28,32'd28,32'd20,32'd12,32'd24,32'd32}; \ No newline at end of file diff --git a/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch.v b/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch.v new file mode 100644 index 0000000..e89ce24 --- /dev/null +++ b/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch.v @@ -0,0 +1,1349 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.1.95 +// IP Version: 5.4 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _f860ac11fa8043be8fa45e244a8a89a5 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module gAXIM_2to1_switch +( + input rst_n, + input clk, + input [1:0] s_axi_awvalid, + input [63:0] s_axi_awaddr, + input [3:0] s_axi_awlock, + output [1:0] s_axi_awready, + input [1:0] s_axi_arvalid, + input [63:0] s_axi_araddr, + input [3:0] s_axi_arlock, + output [1:0] s_axi_arready, + input [1:0] s_axi_wvalid, + input [1:0] s_axi_wlast, + input [15:0] s_axi_wid, + input [1:0] s_axi_bready, + output [3:0] s_axi_bresp, + input [1:0] s_axi_rready, + output [15:0] s_axi_bid, + output [15:0] s_axi_rid, + input [255:0] s_axi_wdata, + output [255:0] s_axi_rdata, + output [3:0] s_axi_rresp, + output [1:0] s_axi_bvalid, + output [1:0] s_axi_rvalid, + output [1:0] s_axi_rlast, + input [31:0] s_axi_wstrb, + output [0:0] m_axi_awvalid, + output [31:0] m_axi_awaddr, + output [1:0] m_axi_awlock, + input [0:0] m_axi_awready, + output [0:0] m_axi_arvalid, + output [31:0] m_axi_araddr, + output [1:0] m_axi_arlock, + input [0:0] m_axi_arready, + output [0:0] m_axi_wvalid, + output [0:0] m_axi_wlast, + output [0:0] m_axi_bready, + input [1:0] m_axi_bresp, + output [0:0] m_axi_rready, + input [7:0] m_axi_bid, + input [7:0] m_axi_rid, + output [127:0] m_axi_wdata, + input [127:0] m_axi_rdata, + input [1:0] m_axi_rresp, + input [0:0] m_axi_bvalid, + input [0:0] m_axi_rvalid, + input [0:0] m_axi_rlast, + output [15:0] m_axi_wstrb, + input [0:0] m_axi_wready, + output [1:0] s_axi_wready, + input [7:0] s_axi_awprot, + input [7:0] s_axi_awcache, + input [7:0] s_axi_awqos, + input [5:0] s_axi_awuser, + input [7:0] s_axi_arqos, + input [7:0] s_axi_arcache, + output [3:0] m_axi_awprot, + input [15:0] s_axi_arid, + input [5:0] s_axi_arsize, + input [15:0] s_axi_arlen, + input [3:0] s_axi_arburst, + input [7:0] s_axi_arprot, + input [15:0] s_axi_awid, + input [3:0] s_axi_awburst, + input [15:0] s_axi_awlen, + input [5:0] s_axi_awsize, + output [7:0] m_axi_awid, + output [1:0] m_axi_awburst, + output [7:0] m_axi_awlen, + output [2:0] m_axi_awsize, + output [3:0] m_axi_awcache, + output [3:0] m_axi_awqos, + output [2:0] m_axi_awuser, + output [3:0] m_axi_arprot, + output [1:0] m_axi_arburst, + output [7:0] m_axi_arlen, + output [2:0] m_axi_arsize, + output [3:0] m_axi_arcache, + output [3:0] m_axi_arqos, + output [2:0] m_axi_aruser, + output [3:0] m_axi_awregion, + output [3:0] m_axi_arregion, + output [7:0] m_axi_arid, + output [2:0] m_axi_wuser, + input [2:0] m_axi_ruser, + input [2:0] m_axi_buser, + input [5:0] s_axi_aruser, + input [5:0] s_axi_wuser, + output [5:0] s_axi_buser, + output [5:0] s_axi_ruser +); +`IP_MODULE_NAME(efx_axi_interconnect) +#( + .ARB_MODE ("ROUND_ROBIN_1"), + .S_PORTS (2), + .DATA_WIDTH (128), + .ADDR_WIDTH (32), + .M_PORTS (1), + .ID_WIDTH (8), + .USER_WIDTH (3), + .PROTOCOL ("AXI4") +) +u_efx_axi_interconnect +( + .rst_n ( rst_n ), + .clk ( clk ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awlock ( s_axi_awlock ), + .s_axi_awready ( s_axi_awready ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arlock ( s_axi_arlock ), + .s_axi_arready ( s_axi_arready ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_wlast ( s_axi_wlast ), + .s_axi_wid ( s_axi_wid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_rready ( s_axi_rready ), + .s_axi_bid ( s_axi_bid ), + .s_axi_rid ( s_axi_rid ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rlast ( s_axi_rlast ), + .s_axi_wstrb ( s_axi_wstrb ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awready ( m_axi_awready ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arready ( m_axi_arready ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_bready ( m_axi_bready ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_rready ( m_axi_rready ), + .m_axi_bid ( m_axi_bid ), + .m_axi_rid ( m_axi_rid ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_rdata ( m_axi_rdata ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_wready ( m_axi_wready ), + .s_axi_wready ( s_axi_wready ), + .s_axi_awprot ( s_axi_awprot ), + .s_axi_awcache ( s_axi_awcache ), + .s_axi_awqos ( s_axi_awqos ), + .s_axi_awuser ( s_axi_awuser ), + .s_axi_arqos ( s_axi_arqos ), + .s_axi_arcache ( s_axi_arcache ), + .m_axi_awprot ( m_axi_awprot ), + .s_axi_arid ( s_axi_arid ), + .s_axi_arsize ( s_axi_arsize ), + .s_axi_arlen ( s_axi_arlen ), + .s_axi_arburst ( s_axi_arburst ), + .s_axi_arprot ( s_axi_arprot ), + .s_axi_awid ( s_axi_awid ), + .s_axi_awburst ( s_axi_awburst ), + .s_axi_awlen ( s_axi_awlen ), + .s_axi_awsize ( s_axi_awsize ), + .m_axi_awid ( m_axi_awid ), + .m_axi_awburst ( m_axi_awburst ), + .m_axi_awlen ( m_axi_awlen ), + .m_axi_awsize ( m_axi_awsize ), + .m_axi_awcache ( m_axi_awcache ), + .m_axi_awqos ( m_axi_awqos ), + .m_axi_awuser ( m_axi_awuser ), + .m_axi_arprot ( m_axi_arprot ), + .m_axi_arburst ( m_axi_arburst ), + .m_axi_arlen ( m_axi_arlen ), + .m_axi_arsize ( m_axi_arsize ), + .m_axi_arcache ( m_axi_arcache ), + .m_axi_arqos ( m_axi_arqos ), + .m_axi_aruser ( m_axi_aruser ), + .m_axi_awregion ( m_axi_awregion ), + .m_axi_arregion ( m_axi_arregion ), + .m_axi_arid ( m_axi_arid ), + .m_axi_wuser ( m_axi_wuser ), + .m_axi_ruser ( m_axi_ruser ), + .m_axi_buser ( m_axi_buser ), + .s_axi_aruser ( s_axi_aruser ), + .s_axi_wuser ( s_axi_wuser ), + .s_axi_buser ( s_axi_buser ), + .s_axi_ruser ( s_axi_ruser ) +); +endmodule + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +k0MNGAL+siJuDYrFA58rRJscMTUE6hiuNEylu7uA+mdVk/vCPJpUprjqZIgJ75i6 +csRX146zVh4AUQABC09rbvto0kqPbqsZwZGmdOm1W8NmGZIXLCsG4MZs984TiToI +QMOSc+XFr9GVx1rFODfIQCsRVOla6WZCpHrBZzFjmFwY4t9fXFQCs5fSkNbGyG6v +8YDvdegFPMYp5Qu9ccfxeosyrpdCBompAmWscbYmzMrmyFiInvb8Y5dyqCuve1NW +jirl6fz1954ypdomnZDn+X9k8zTCJAxovyf9Qxk6Q+/Pf6e6yRqEYBxT7dtZhWRG +tEQdKP3bt5KBf+EuwdVLuQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 9552 ) +`pragma protect data_block +CosGYIkH0xBRxN95EJWx839RlT4VAi4LCJZ1mt3NitRA5g2pDgJLsvVh2D1y5BVA +pdFnLxJlKeO8VGxcbjdy9+FeBPs3Bo0hcGMo8L+LaJ0bVkv+6b77n30HN7W4KS8h +FD1Ep9sROiwLtXRFHJO89i05/tAaQLM8i1caOwWOyxnOkkN9uNWnXu8Q0YVHwDSo +6edwH6pDm7sUFDB7MkilS2mpOjdUBdlO7TGkRl9TuEENWQoMfIDEVtwj5ArywPyR +ABP441amQzUHEwhfDKcPN2iMoBL+T+S1wuWnJHqvzHEb6nVPARgwM2LxvxR9dJld +dNlxyS3zC6MHchUMEAThn6/mNnJEIrcrJfsvf1vvLfpUlQ5d+C8Gj2KcQl4cX+1i +y70cPd03g1gHtWhRfChJ+8u0hcEyphEmEnx9SLi2I4xYi+fTWMgPPM9PNN1YXNHq +otMqtc2ceQLlyCdlKJplKqKXkqQdhPcZ9wt1WckUoSV+ZeiA4t7bGUWN3kexbKDy +o/js6xWIxX0ryxN/pbXUzhaj+FMP84LHEs7BoUU3zxlGsUspgAysZAO14S2sGjNI +BGpe6bm0ONuesSHUY7+4NUAWlwtPlG6ulaAEIClApiB8gBOvDsTAQbDKVkunI6rz +9cfhmqP/A1djz1i+Lw6iytrG/0VEU8wOePUdJupVohofGQa/4y+YwGciqdf8bscN +y2H+LIZnDVF8FwQqxUMjnTJGvd0s9fHCJfhYvXMWorLOGLe2wW1l63PmZQoaNVXY +K/JSkYpZKe+1jeyKioBw1ecvAOFXmnHjUXoGGiAbTSgVf2c5qN+UOXty8BIpzXsg +rEi4GkhlmS9JOl4OQehZT8m8XUc6Gk4tOWOFI/Y04qqVeyyHXHoRK2YypFTeGvWZ +QWRGXrwLYJEsSZ4pSXjO2Y1sNzJSAy/LUfHn9ih9RN4pcPd2t5yJBs9i2YKdajDd +mMZ9cfbemdV3IUPvWQsy/p+aey0Cf+JLwgchg/lPfV4xgZIc4ZIqkBiIrOIkYCRT +43pSktGOK0XWBA1vaFIbC3cpTHkDm7LQWLF6LkVws9H+W9Ui7ZphPGJYQ2FZuPFI +x4JdlFgmbh8CKDphsgQ0S9wIPIiTxRywf2P0QWvDuaAPSf1ONlDVSLZTsMpwMhgp +JNkTIkZg82zj0VVndkAznUheBGdHU1LM7Ao8djstDoYkJyBKszFcpg5i+vych5sn +Y+FPaWBO8UY1afO/VO2H3aMYvPs8Ey4fLon6Ot+jqqE2QhWfWOyr6/Y2KpZ29Tn4 +yJFhBLEGx890JscKBgz/Pty/z4uI88ARA6quPcoynMcdIZ7KuZ3//NoLU+MW5Ji7 +VFYtef6sYztFjyVBej5iPcwEB/IFI1d4rEZ5trsKDNcBYtLv8P3uUTrAbkBUrkzI +yAmsEY5jaLeFXJdeT5qZFjyy9LTRuyOEdhKoHr8lsbIvJEP8fKGOyR71wt1P8vDh +baKkrSka1ND+doDAWaIksjVzpZtoOUJMCdyqduEGaSXMoEbOLzjwCwatyUAZnAfl +WwdgTbr+jMNDwm6ZJ1uUwd/AC+w2aunGMR1WHoMDyIK5icyVab5vg4cygOV/vkym +3aFkctiYHlucNCcL8phNpyLUKgGpY7wU7kLNA24HbnKJlqAwUOFuX/TToc7PQlcV +SY9tr2TMOFipbNlOu3jeaB0Vo6yseFq4QJYhA43C14lER0DuVgRveDhb4d+kcEl6 +bNUBGSkHWyh1txe8rFLTipxEBA9OvA4qfpJLdjdZ+y3lkqRQtHFTpuHTBJs691oX +Hut8P6qCvMQWHtqbc3rdk4Y3duWralCzKqrsCmziyZIJpOAC2sAyw8ISN+HX6FV4 +qfLqVX0UeSni7AgSkhblarOhtAnfYULYt5K77BFGy/3v2o9CPNOno8LSdA2CQ6Y4 +8oZYxxqrifzsGvCdSOAPCAmUtCHm/spRjVS3wwZr/JqiazytF1OksyJ3qY9H3Yy9 +cAOg1szShsdHmj4PNrZqE6mwktxWt51Th8QjPkjALxf1zO4f7PHlTl1NxGEZk3je +MQEv/NtiqEzeRmzB3GLiIAPNaq0pD4t6Bn/pUCW3WXfO9SsCw/fk57GZ/MCqIxfz +Wzv24NCpkA9CpffUL4DZ5pcSNGwbDVK8NhmPq3jq9aT9QiYkkv+Mc1G4gDL+NF9D +hbyD1Pr9TxJIKk+kFIFIdVJBMMIcVBOb/wo37185XNJQbJ8TB2axmGnkXjNOge9+ +arrvoVM2SERpIbo8+cbHNMy1fY8ywtiIA/N9+BybUe4qO24RtzrsJHoWJ1Rn1Rg9 +jsFzaIVI27UiFjAhQfsnzYfTKEnHZu4NnbUDGzZrPgFbQQCkbBiENyXRVX360gfC +hsfv5p6XFZfrWjLL55g2EmdV93K2ja+i6klL6yfb9+nyTLI35qz0QFKMIALNis8w +JKwyRM3ThTqe+K8+F25fyT0VqHp7Rk31IMEP2PIM8pkwn7q6CAdeRoPO+rln6Jaq +onLkSko+m25UxbrtdT/oiF5b1eR4oQfUAVJOnMFjMkuBrc/KmkiTotNCeFs47ViV +02JeMX2f8G8daHyES8qCv5R4a6DKb0lrNHoojbtef/gv1HFDUhxGn5xkqlDrApwi +AI2pXanHk96xQ3jzFuEI4oQ6KtHySDBFRby5u5Xrw85f1oSAeDDHvy7/Cw5emFoc +HDu3rpfebgG3sKM3ZrUH06lrR2Im3LbGXusrWI/isuwyYuYXyWMMpsJo8t9n8KpH +DYTSNXwIpbZ/rlm4yLEdyYPxNU1X93LpIY9+XJHBugTXrRpQWNr1NjX7xUD5NdhZ +no7eo1okylN6u2/9VzwwDxzpz6E2/ju3J32x4CYYhQisuP9BfA+GPp3vwp/f8JkF +wqKCtI6nkxCXWkDrPTmplKzKJxCSAN9iwYi0Yn15/oiBTA/l9NWgRb59/zARioB0 +xX3tdsXLlBZFuH57ePS6RcmU/DHKUkyChHupCu+IunhHfEC/EmHtGsjSHKrG5iyA +27M3fpB4Xd/LeuTYo+NaEYTlANaMYUeteH/Eb1PDwDgGF2bGhnriq4JmMd+EFZxL +4FiJpggUJYd/M135cC+ohSWsHT3WK+IIerSKyD72G/xVGexHeNPt0HXhdCrmgyH/ +00tTjTHdZQKdF4CvdjFeCT8+6Q9IQlP3CAaow27SaK9BibNtM6xbsHKlBW17PUbV +JDUZOiRAtSKcePPkEXirrqEFJWBUmBC1pJgAnn0IQE3ZmUSvJeiaxvyAHfP/IvBr +d7dr3MKhikrNMdgNklD4kU01G51cn7ehZQcSt7o1wjJ2bITWQAI4CN17Pa5BSi6x +M130n/O2tghSh4RMRXuM1uOqcMJlSdDaSSrNaXgMAO4ePH9mdquCwRLTFBdGhkej +mYrY6frqP29aFXcwtEaDxnzDmUML+UePGNeksngsXKyLW4NwfSYkwuct2paDGZ2n +l1mutyakT1UgcTYVtTym6xQjxp+fEQt9RWSaYw9my/H2vf7DJ3rgRmlnZ8VGHvsg +Q7vBtFvGEyU5LfD7czZT6ERpJCapbmEhOMibFy74sgIfFf2KYdcAr+ILpb26imPN +kASgszlpTJBiWkHVzM1hcGnYx07ltmPoEpfGnyP6w7idperxlYoUHzJa+QaXCQ4m +IoQUrcLW3olf2qD2dAHy+J7ew5IrXyg/FcEqkeoIvBM43fGKsr9BUlh2s5zm0qZN +PYg0Al3SMA2nVYA2BRPgVjfFL3iyjOFKjboMwEbHGEUMvVWE3YVgj5waDPrjRLIm +kejtSYej3CYAkQIw8DN9lhDSAg44hrdtYkk7EN9O+ASmQi/c9M9ROYv+Qh8S5Jj5 +aU1LWZY40pLJsnu1ihdw5QSHCIC/wsBAe3I+8+rEe8JqJbQ/OVOl2yqdOzJlUF9c +UnTwJIjcPj1/YZ+ouq+J52boVdYPIY03uzXfvh8/h0HS0sSBW+N9N4/qyhjwu498 +if9WWyX5QNldlEzADEOQJm9yvhTGUbOKsQHvLkq0L7ODUqfqh/4I4n3SVQBJLBgc +fJoHsaTB3UL233Itwlddl0RQZeZ44+2UurY6PPi9cs9PQHfBMGM4EEDIGczkfwrb +VXsQDl34cKlIl+ualZ8HO1RTQgonZpI3JpC67Li9mS00jWiYo+61yZ+tDOsKJpWH +rk5RAiDEgeEifE482FrBHyMs3Zi0M1ADm+CzchwS48zNJBS+Np1D9quxmCB1htEG +LpYnY4f5CukA3sRcAdKOBZiPqiZ8epunSri+QBGMzTlsy1jG+BVDiHw7qCnIjETO +uoYWsfqh1J0/Q3Ch1H17d8H75YtBWzWWaK87dTjLrHhu3IbA537Ey8THNaoKfpo6 +Q0aj4nLip/23JZzowTwMFjkdjIxaaUWG3BBwLysR00Ojci4rWhcJ3Kkl7X8mmTN0 +Q124nxpjDKCmoQG926wQYC31yHEVgDNyVILxcyV0zVb9FUIxojPKXlkmqzM6xfnz +fw2rDLAQt0aEZQ04G2P8ogq0Jm/S1PsqY4LoC9LSugckElDBF9jE2pTJbu8zejhN +H4f+b/A8yrlKWsTesVaXNrmTKFvEQErc8vi4UEaHdLvOJtJsA4Z/8zVimjWe+Z7E +RmOV1S53KXGzMg3Bs5Gom3YC9v+Vusuq4BX1Bhq1JkcGbq6TbDMG8rvG29UCt+2P +EplRUHVp9FSQ5aWP6T18iIJ4MSvhHH95hETsFAnkjnavR8q+REgqC+A2U+Gd3ibS +5fvK/B3n83x2SfyU4VcSf42zxVoleOLSYrTlIVVDY7UHQUyGCZhBZ08zXuncYYjF +40x7WtGXgFXhK5uHLyYRKCc67bdq+D7gCUnNhskDr0azpw2O7JrrdNoN0gZ0bSss +wOx+7CzZBb98+Kv8pOBrbU2pMKNFQwd70PBQWmRspVX1ib93hzuOh3uoyFCqHpDo +dkNAQR8AnBTO6wfLI1QLzYkV4XcuIl4YnivmZeWBGg3wCsE6wPJKRJtScC/i9Kq4 +PRalvjf4zDFcUpbLmF6AZ1UtSuExw4OYncihmxUpRcOGYovNufLqtmoC3q1TdExb +w0HGPIyJ/t5KEw1dXq7rd4KgLTIbgjUIDjWkXI5hfshqKBMcs+d51vLXaALHDwNz +VFU/iskzvUp+uE942PEpAH/hFlbSuZeDnKVDv3hfWSE6DnqrN2BvbxOOTSYShGEq +zjn8Xt1ZWmhPYYoBiaOAG/AFlV+tOsRI+g3KQjL+l3+iJ8yh4YwNm/A1t6BxNjgu +Rzr2KZsjDPa0qGRTrMEV4Nb5y2TxS77nDuyf+Efc424O/unlG7XwzpRJxvhYuArS +5yEuhUn+4OFq3XUJjgPeVEJH9fUxHlpKscpjAOMtsxu9lR3u3Krv37aZm9OwyEDG +3tU/l/nrzG4VEXdXExlGFP91lhygme0XJiPvLJAe8DAmTasKYMe5Rg6LNXyZ/4CL +xgjY9uYdSrEiv1J5aMGmdFDuYxfJZb1UxP0zjEGos2eCRUfR2KNwl09dCxRHOvMb +Z4n7HR1Lsqw5V2S9SxmZo/A1ju/rZML1EO1zDLkqe1on8dsPwyu774HfStaMhVGj +OfWr0AVe4DGr0jfajYwc6WE+RUAS85t27GtS9Fyu+Fz0Ifl6FdpzdUaMrJI34hU+ +i9XO8ofzPd68opcswPcO5AOaaL5w74Qfj4Q8xhdPpq+Tu/Ke9ZVLeJ2rFhUug2Ig +8iHhTJofPg8GATOdo7t7efZTS1J6CRk6AVotHvyJ0RCvHKr6i1qT+lCRu9EIuh8b +c5DJ51U1wh6y0k5ffYzFK0QsiujE5huyTFT1LNJrUwApeB8R27kVKSS1mSM6mz/4 +LhNC5nzo3JJ11XmH+ozwXTeXhsQS0NdFKyZJfW30fwgmqcw6UbbzbytJudUsG96L +dRmHzENmUnzRgVsSzB9z0tta/mIJ4aapzp2MPR8rmiiL2oDCOM7uZ7OYrmddzZEG +VsiMxJYOQb3s8MuxKfMIg3YMeKsTXYx016ZTW32L41w6HxqFFEFHIDi5qw2h3H5V +fsS6IIfvKlvfnWt95tO2k5LPmcYfl1Iq2QajQ/k9kgVyiOtAyF6pl6qPWKumZlli +pVcT9mTerAsGA02QLxeAesN8m3ojtpjQ7ZecB8QnN1lZArmeGkrYkGazFArgYJOc +Z9WOl87htK1txyN2ss2dAtgXRZcnDHm9G6NZTckni0CLYzPRXGqPg9Qhzjamx5O8 +RT4JZ9dERJ7nL8hT5uxmMFOgtm4/bfEeYZknj8uWjXP+yPdd96OH+PQ3mRaJSnPp +gmt3/SYLcyLjt2UF+k31JZ3v3y38zo/YhpP415VKsCcLerK7ULokgjgcr1H53Z91 +ss4huvMVNioD7eCutHG7VhRd4W/734DyorcglRWZDFQiGryyXMyhuBqv4z5xU1mW +ItulH01TTC5lPpPqvphq2MPOwMQ+b3QeCdmny98NSvIqy8FDfavqvuwWmIERgoge +QnOe6ytg+5qB7E14cRHWZo3OFGM7jTDvwvlQ/DYMpVMrG9FNr46ij3vTukx0bzDP +iiYU5ltHRny5B6LRyQXJXJi0Xp0UsAfDD7IxTFp7g0JsXxhRotnjqqmsRHID1cUt +9M29af7bU2mdNbhf2ESqjC97RA/1F2AG3ShxJxP/lf94Stc3VHbqi3fB0Nb7Z0rt +FBQk2c+uV1tD0QV8ho4vnUImlUXdPrwbNGamviPOtbGIMPR3Q2Fd3qj502Pi4OLp +Y9GhrZZz4PTDP13vlp7aF9q1vQtZALcOZrLT71PJB+uu3zCkg1e/Jz1UkD3Hpdot +vnX039fSPcJkyJsBzc9tnNlTL/Z8AJTq7NxaQ7NA+bdLBfV9zHhzMpaS7lSiF7lz +YzPwLB0oKTTKi3q4AE6Nm2WliNx4rf8rWW9VJ8IzO8zHgD/03cmdbmGPQBpPW36N +LwROtnLY8u1XRz6d04nrrYBdiG9rU+XzUCfI/QHskulQyMlZRa37gPLYNvcfF1zz +YbUkrCqxnHSn64xnPuQQZGjTk0kQORKuer5/mLjwqy7CYRZyULRinMASnzo47ow0 +Jx5Py6hznQFjAlNlO6NbGbfw7JgaI9kE9tCSZ9qXQtoZ/u5tgswL2R1CWBgHCFlv +tvTuqNwuq/1kG+48jFD+f5O0zWiB+R2tF1dzOaV8GNsynKgvHiLzhy1sMPs4P4U7 +JcQ6I1rV2mD6mKCNsPg5tLWFzi6vgfNkDw1xSaThZVwp5RgGryD6/SO8DSEE/h88 +n8LivWzhC/tLb5d+oXOI20PLwqKgI1qDbEo2/oZdpkHRgurHQ7pLzNPHmnAbjQvx +g0XQbnCPfZEJt5Jgo4fRO9xfXng8lTQbYTMQH1rJg1sGElIsdAZGNPNOP3dZezGq +dJTB6aMp5WUo6wWFvB/Fv5JEHKW1K5SxO+Y5KjnRSbdgpfVKyaoKAutYCcd7q9wJ +7wq8Ft0TT7UMeBPqGvknTXXm8w90V4MA789DdKbGXyx2VhCTLwFjVz2ysT42UJwM +BYbeELCuPhqp7EE0v0ysbT5MD8oPX80U/Dxeq39wdt9PFXAWz7gHae26N3KZdiKL +NCDN751mf3ccCJxy1qZCnQz17ToP6ZL2HWOQzZWBfYTjV+y0md2sNArb/C+GUmri +sISKA+Vp8Dk8/CUrUHV2q02iBFkRJ61QHNEWtqKNgX0pepYM9D6w8Ah9LgHgXgFx +5gJIng2rqOhaDfnUQToP82HdamOmHnCJ/gBNjaqMf+7bn9jVW+hjVY0ZPxCuQPAv +1uc3Sz3q+ZrNKVQmGh29KI7oZtTa9jxhK3VzoSpGNRCAS/anWSq6Hd4Dumm+oSQ+ +lHXUz9881/TiGnzog+eC5nc6O+Kc+wXbT7AmzsX9/5bjf/hrxsk6rEb/ixtHkB+i +GLu/cSBGVfFY01E/YTWetYSM2zUxrItaFaMSEVAkWnKnCLXVUQpB0Kz9qwEco+7U +Py/DFCDDPq/glDrxPTRPT+Bs05xxyx/2XHt+bpq+MsU44Ed3d545oXNyt6nEZKlM +HOAZ5hR7iRN9XTMHcw7N0Hj8w4irvXFIqQRN1R1gA4d57+//KLgVI3r2muMQiZq+ +gB95VPq23ELMxr3mW9TIQ4fq9srfL7AJ6hzLO/MWXkGwkthaudHThv22nioF6LF5 +tCyJUv3pc3xQd+G74SYee+s5YEbqoCzHmTvTz45mQm9qmLgk4ED7FC+8afzZrUWY +DZneOeh1qUIZqQgu7e/ftQc1kB0mY5qLngSaDlkUPHBplUlk0xcNVRqStxNYlyt6 ++egXrZOyty/+FX2wypnXy44ivJDKWIKpNjJKJFXthsSWtzyJBjGY0VttbNviX37j +yuoKGTphHdm7yZ1DRQvtUmr4WGTicaSfUC4oZttTtofEDAr2qipUF+LwUWGuGgWX +0ip/rhABZEM1UuOu6WNMCSf03YDPsXSBqg2ju1rexTk3z53VGM1cbU36G+EzTGim +S00BfgwxVQvdBJ8c0ORYmiZMNYt/IHd+dAFtWEEGaqi5na+rlrZ8qqy1rOufSZ4E +Lhgwp+mPd5p3ZNoMT2KVo/hwXvMhUpucwCT4WW8xKxPeNCTTww2i+yZxZUyLc8Pk +048Kzu9YjSoKUHk7r+hdEa0+CSnuWFARj5CUgscPrIse8Ty1lKKYWGPXQ+OoJC5p +phKW2nKPBeh5CDgRUqlFG/xj0O6dNq9telHYAWwBohz/6adUKI4xNUWlBY8FRTQ6 +hXKVB3iRnqlC+ln6f0fZ1KkT0rvkIBsiJF3tIVbOIGrGsa3pvqiGAP3iWF7BvOPF +5SY33+T7QbZQtrWpft43XUQomKj7RJNdoZpJmmIrVxU/JpesGd4n8Qghy5mRyV7H +aqnTd+JmRocf5aCjFjvYaHR8M67gylAm6h+JZSW9vDwyKv5KVBRPd8oaZpTaqqwz +VkNrrXv7fqDnSTEtoKetTp17kp+aF2tA0wamRKJW6X42SDtFKtinBnd1MFfmq6qR +Wtr+oDpNotRs4Cz5Ml/ETb9V+ctLISmAFpFZsXKMNEBf1l67EaVHhQHshFVo6MmE +gfaISipXVe57j7bJ1c1F2q+UPOTLK11kok5kuoZkZrSRdd0nY1O45diOkMe0f8SQ +s0PjcMXSCOVG5R+NhZHxF0GRm5GOusqh+luad3/HtsmjD2pBaT9TIORoUfo20Edy +hVQkeAWA8z0mjQv/kB/5N+qKVIlRuyz/cOV5MKmX0HFaBurRHbwv/AbS/5Uh5ZPX +F6m0+erd3l9ccqBuAvItaw4ouf/pr1a1kMDjez6R4CxmGRynS7E4al4djdLT7ZE/ +Cf4L5W55tyE3A4zGbYuwXxlvzB5otmjIARCVPaCJsDLQVvQEaS7/OFItoPSCuObn +w0w0h/4Gs7aqO2bsGPGLEr5fMFAjHsRiCiRxmmHUiezrEjiymz6RaZwzb4FFL3B3 +gpGoZRbffCIVaBgKnq1rifvnYtZbOZahg5UbCMALTRqj64lHxRKUaT+c507MBzcT +2A/xQaaMXd1unIp9AQPTmHGneDmpNpipbUwik4wZUVRBaaucrLWrG6LcGp4icVlK +QWwb+t0Ngh3nQgB8q4ywRv39xYJ+Ntu4vGsXz9Mt+hM4bjRSfzCFgdaaNQqqFNPB +c+dC2M7DsriTPTygks9wxwuQtzSECp7sgpkLEWJOGJLy4LVOCFyh4jdmMqdieiHb +BN1iscgTk91VwkG9+kQIgHStsiOsI+n81iz04jxiegCP8peldNSFvX5GYFHWotCO +ht0POQ1shkziTXdydE3F2umaRkAI72qYls5BhDPyfHP+Qf2ZsBACz5UId/nxPeD3 +5aWDupx7LBRLGH6oR2g34oj92Y/o/ph4b+Np1R+XmV+ahBA7RpnUVe6dsvN6UeSR +WglN7R4pTf2UTS+KD72r8aNQlcjwZ0DiDW14GW75OHxf3G5PZ+/KCoucxUfvZRNN +PeWX0pLfgCzN6d61NADCpGqzRaV8N5hfevJ7lWFXsU7hUXFMQd9d2YQsa6Isi2mB +rXHS3ReefPS4PBVhANGSzG2HuNTfc0XTeROebUTT8czFCvv1nRkph+eif5+w9e5Y +wpqZh64iUA5G1Lb68JAL5l96ntIzk+XHzfkF+bA+7E84hPgedhaTw2z4zzESxron +mWxB+8qJnZA1CXsD/PxASxJa3afR2iH0KkUDLyERtSBaZUV+ORUr0t18zpDlHE/0 +agC9ztwh4doxddnpKEXFBftpZaVbKsOypMu1vQFBxVPwwoKSgpcVcAbzUkWYnmJT +ZLX+04cd+Rh5lFe50K/JPYE7rw0EsiqzZFYja0GT/aY0i0sr7ggBv5PGox89DaPR +M+mwNkInkOXxi3MHyRrVITAGp2WcOXHmmzdXO6qpeExaBdhW6lBRDJorwAyOb1cQ +h4SZw5YdoducErUAzTrkd7VelUlhr/w1jZ/31NgyaSkRVOlOmJhTDTmxs83jfWTw +eZSGDO9ZvtDIgHBr4CLE/5SyxgW2lJdgs12MA8AmIFHbwTQRp67rKqD5tqjFON0Y +icTpZRXGj9+IXV/OlkjnMVKeIUjhVP7M9nzyCzQSr32foBsBoW8qEOEIe3Hp8v5N +jka1PWiaeVsORmiFSEJuNQBIbwKLWj8WpOQIU2WBsaSbwLgxZbAq6QeG+fWoHvOf +ZQsrr0aheaJ1sEjp+g7kcRz+OkkxiMLp+zqstbX3HepZcLcjE4sP9r3nffEF+jC0 +Lk6er739jGapdW5xc0mLBK8kUOlRUTOwGvfTMZv91gZkOwonaCOJcYnvoRnSZajJ +ITbUtQ5Ur/sIl/RJ48z0JlENCcZ5t1vwa7H3Iqh1SEDh3QEShy8erQMLb3uhogh1 +2PUTkyH2RVxTZrAjAmn/EZzsLf9st2rU4988fH/F+WN0fQ0pSzOjDOtT7Siie5l1 +LjFScPHYqlnLkl5CpaeHJ0bNu67frdavI9wj3kQzMRtsgTzycZJ0bvA0r2xRq804 +IYtaimeUwIRwg9NoGtcdYBL6k3beA6SMXeE5QJ5GZJcrOhcY40zgTMzcSKrkhSci +cVWK/y9yq20tFKRC95HuZMO1n1sCKpRCez+UluPrmyEhpj9i6SVFAyLhCa5/1T4Z +aIRK2609/+UWwhK/rFMYSAG+AMpFADC/G6hevSzwdq3nPYFNjaJEwuNqdgE08CfW +ZBUzJ7aBGw4QZS88aLrb2T5mdGqHWOCwD1F/0jpMDMwccTpwYqhcuixKy1IGDFsS +SxZrlEdxBAVpAlnWz3j6VGyRiLF2Th76uYHTwEeg5CwmofBk8mtQeHzyU1XelJPd +gT7yvnl9TUpDQ9uNnt5CWKAOy0jgC4lB+HILxpFgtlZ6+JawKnbbBmS5MyU9qsm5 +k+aQ4yQNdP5xyyXRTgyvSa21DiHvgzNv4xwNr2ClPh9xrsILpHGIviphv4ekwk8Q +pTFnZsWkl11LwNCbJZudB/3n+QXsla1k8zBe0oZoHDH/D7ao0GNmpuExKQohUuYm +Bkun4xAB77mhH9DoSaVs+zI5vJcDJK0J0LQNvZfdLek55LLkjLQTxvOKtb8IOHUa +R4PVGheykA4RribJ4gUmTrG4SxWRW6V6c8w/COxUBq6e9X3emTum0BXg2S97ddT/ +ugRqIye92Xu4glEuBKiEiSsYkCRRFRLfy33mg0Qh/wkn2YK6ymErHe3Va/xaHd53 +u4ZQNfZ2zwhyvScbaIIKwvMZglPNQTVKJoYdIRbSsFKAxyxhoiaeAS0e/PnTJrur +mmfNVhSaIcrbUmWrPtqsWn3ytCkkxdFXeDA1Mrr7npc+5MZeGWXYymgb22vn9u66 +VbgBe6JhB4LsFBymmlL78FBkH1Khl759XHwSqWBabZ78Nsma4wBoKqkNERIlTDFg +hM2GSRsibel4dwsBaKSh7XnXS1WialkaMX5jTQ8HgRMGL4Ieh+pBP14IyC8A2PgU +GZsHuiFP6gjnfiXafDlwsG2t85g1g3HW0nfk/lb9mPz9S0DrQpQgWE1hBizL4CN3 +c54o8MNUpj9kGITZ4R1NrkRWVKJGNeLGXMIy6MgmrAN6CjjyfID3jAe4CpIuUinu +F0uKdEsEMvl66AbaK2py4LZPaLpNpA+P6DKvQhVVBJjaOwuoG1zEvKavi+L8J045 +cuo6cLFe+aI+c+Fgl7dJrgLtCXnNojuOT/+/O3YbGWgGMJLq01mnSD2isOXdr1qw +zuL8aJHMRSJgY7p43KcdzyVbc0+0ala94PYpTuLaVVsYJGpyHHMCgHJhZFAgdXtg +Ux3K+QIeLnmphG+CLXWnBqNGzc+Y5h65JJ/Mo58vnrFb0gtG9qNf1y3lPp7iqFHj +j2D2AylIbNJ81RQmFx2cPoX2PKiIvKb0Fy6SD5IQ/2FLqRJqVOjnwg3Uu1AQ1NR+ +OAu6M+ioz+nfZk6rwKkJjrU28weaeNKuNtCQOwbaS39NwTHRNDybrXbAXbso3Izx +hHULq89G/WE7fXIJJ0uNZj/cmIVk3lVF6/9zsx2+nHv/XUIhJZx9EG5LfBBVc6qr +CfMjv+9oxgyUl/uPWDBsm26tkTV3DbbHeU//M/nf4KYRWNdwUirBLfeGqxXgdZFH +9mDPUQ4z6WmHHr3T8a0VqhMnAY9JZPZWtcaMhdhuEyEt5JTTJAmmO/m7cGRh+U9j +Oylxf2Mb1LOHffkW1XhJrQ3bDYFPbrrvddxJb7fYr43RlXkG/NtCA0CR7fzBlhtw +oML9Tv6EfavyLW/lnsOYIqZT3EexL37fh5q/U6iFfb2Fi4yP0ihSU9TcISR8bkn0 +`pragma protect end_protected + +//pragma protect end + + +module `IP_MODULE_NAME(efx_axi_interconnect) #( + parameter PROTOCOL = "AXI4", + parameter ARB_MODE = "PRIORITY", + parameter S_PORTS = 1, + parameter M_PORTS = 8, + parameter ID_WIDTH = 8, + parameter DATA_WIDTH = 32, + parameter USER_WIDTH = 3, + parameter ADDR_WIDTH = 32, + parameter M_REGIONS = 1, + parameter M_CONNECT_READ = {M_PORTS{{S_PORTS{1'b1}}}}, + parameter M_CONNECT_WRITE = {M_PORTS{{S_PORTS{1'b1}}}}, + parameter STRB_WIDTH = DATA_WIDTH/8 +) ( + input wire clk, + input wire rst_n, + input wire [S_PORTS-1:0] s_axi_awvalid, + input wire [S_PORTS*ADDR_WIDTH-1:0] s_axi_awaddr, + input wire [S_PORTS*3-1:0] s_axi_awprot, + input wire [S_PORTS*ID_WIDTH-1:0] s_axi_awid, + input wire [S_PORTS*2-1:0] s_axi_awburst, + input wire [S_PORTS*8-1:0] s_axi_awlen, + input wire [S_PORTS*3-1:0] s_axi_awsize, + input wire [S_PORTS*4-1:0] s_axi_awcache, + input wire [S_PORTS*4-1:0] s_axi_awqos, + input wire [S_PORTS*USER_WIDTH-1:0] s_axi_awuser, + input wire [S_PORTS*2-1:0] s_axi_awlock, + output reg [S_PORTS-1:0] s_axi_awready, + input wire [S_PORTS-1:0] s_axi_wvalid, + input wire [S_PORTS*DATA_WIDTH-1:0] s_axi_wdata, + input wire [S_PORTS*STRB_WIDTH-1:0] s_axi_wstrb, + input wire [S_PORTS-1:0] s_axi_wlast, + input wire [S_PORTS*USER_WIDTH-1:0] s_axi_wuser, + input wire [S_PORTS*ID_WIDTH-1:0] s_axi_wid, + output wire [S_PORTS-1:0] s_axi_wready, + input wire [S_PORTS-1:0] s_axi_bready, + output wire [S_PORTS*2-1:0] s_axi_bresp, + output reg [S_PORTS-1:0] s_axi_bvalid, + output wire [S_PORTS*ID_WIDTH-1:0] s_axi_bid, + output wire [S_PORTS*USER_WIDTH-1:0] s_axi_buser, + input wire [S_PORTS-1:0] s_axi_arvalid, + input wire [S_PORTS*ADDR_WIDTH-1:0] s_axi_araddr, + input wire [S_PORTS*3-1:0] s_axi_arprot, + input wire [S_PORTS*ID_WIDTH-1:0] s_axi_arid, + input wire [S_PORTS*2-1:0] s_axi_arburst, + input wire [S_PORTS*8-1:0] s_axi_arlen, + input wire [S_PORTS*3-1:0] s_axi_arsize, + input wire [S_PORTS*4-1:0] s_axi_arcache, + input wire [S_PORTS*4-1:0] s_axi_arqos, + input wire [S_PORTS*USER_WIDTH-1:0] s_axi_aruser, + input wire [S_PORTS*2-1:0] s_axi_arlock, + output reg [S_PORTS-1:0] s_axi_arready, + input wire [S_PORTS-1:0] s_axi_rready, + output wire [S_PORTS*ID_WIDTH-1:0] s_axi_rid, + output wire [S_PORTS*DATA_WIDTH-1:0] s_axi_rdata, + output wire [S_PORTS*2-1:0] s_axi_rresp, + output wire [S_PORTS-1:0] s_axi_rvalid, + output wire [S_PORTS-1:0] s_axi_rlast, + output wire [S_PORTS*USER_WIDTH-1:0] s_axi_ruser, + output reg [M_PORTS-1:0] m_axi_awvalid, + output wire [M_PORTS*ID_WIDTH-1:0] m_axi_awid, + output wire [M_PORTS*2-1:0] m_axi_awburst, + output wire [M_PORTS*8-1:0] m_axi_awlen, + output wire [M_PORTS*3-1:0] m_axi_awsize, + output wire [M_PORTS*4-1:0] m_axi_awcache, + output wire [M_PORTS*4-1:0] m_axi_awqos, + output wire [M_PORTS*4-1:0] m_axi_awregion, + output wire [M_PORTS*USER_WIDTH-1:0] m_axi_awuser, + output wire [M_PORTS*ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [M_PORTS*3-1:0] m_axi_awprot, + output wire [M_PORTS*2-1:0] m_axi_awlock, + input wire [M_PORTS-1:0] m_axi_awready, + output wire [M_PORTS*DATA_WIDTH-1:0] m_axi_wdata, + output wire [M_PORTS*STRB_WIDTH-1:0] m_axi_wstrb, + output wire [M_PORTS-1:0] m_axi_wvalid, + output wire [M_PORTS-1:0] m_axi_wlast, + output wire [M_PORTS*USER_WIDTH-1:0] m_axi_wuser, + output wire [M_PORTS*ID_WIDTH-1:0] m_axi_wid, + input wire [M_PORTS-1:0] m_axi_wready, + input wire [M_PORTS*2-1:0] m_axi_bresp, + input wire [M_PORTS-1:0] m_axi_bvalid, + input wire [M_PORTS*ID_WIDTH-1:0] m_axi_bid, + input wire [M_PORTS*USER_WIDTH-1:0] m_axi_buser, + output reg [M_PORTS-1:0] m_axi_bready, + output reg [M_PORTS-1:0] m_axi_arvalid, + output wire [M_PORTS*ID_WIDTH-1:0] m_axi_arid, + output wire [M_PORTS*2-1:0] m_axi_arburst, + output wire [M_PORTS*8-1:0] m_axi_arlen, + output wire [M_PORTS*3-1:0] m_axi_arsize, + output wire [M_PORTS*4-1:0] m_axi_arcache, + output wire [M_PORTS*4-1:0] m_axi_arqos, + output wire [M_PORTS*4-1:0] m_axi_arregion, + output wire [M_PORTS*USER_WIDTH-1:0] m_axi_aruser, + output wire [M_PORTS*ADDR_WIDTH-1:0] m_axi_araddr, + output wire [M_PORTS*3-1:0] m_axi_arprot, + output wire [M_PORTS*2-1:0] m_axi_arlock, + input wire [M_PORTS-1:0] m_axi_arready, + input wire [M_PORTS*ID_WIDTH-1:0] m_axi_rid, + input wire [M_PORTS*DATA_WIDTH-1:0] m_axi_rdata, + input wire [M_PORTS*2-1:0] m_axi_rresp, + input wire [M_PORTS-1:0] m_axi_rvalid, + input wire [M_PORTS-1:0] m_axi_rlast, + input wire [M_PORTS*USER_WIDTH-1:0] m_axi_ruser, + output wire [M_PORTS-1:0] m_axi_rready +); +`include "axi_interconnect.vh" +parameter S_PORTS_WIDTH = clog2(S_PORTS); +parameter M_PORTS_WIDTH = clog2(M_PORTS); +parameter M_BASE_ADDR_INT = M_BASE_ADDR ? M_BASE_ADDR : calcBaseAddrs(0); +parameter IDLE = 0, + PORT_GRANT = 1, + ADDR_DECODE = 2, + WR_FORWARD = 3, + WR_RESPONSE = 4, + RD_REQUEST = 5, + RD_RETURN = 6, + DRP_REQUEST = 7, + DRP_WAIT = 8, + END_WAIT = 9; +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +f0DVmU/kdU862C3ryhjQlDsM4c/0bG91GM/Tt0YfOziNIhVBbdZsoYW2RTSSEC81 +yNXUBt7tFmZq4YDopiOye7MWsFmf8WWRQEL3slo6DkYqzPlqCgnjys82AVws5Cco +WGW89TXAcQAYHJy7oG8Ae9oSMdLa3PIQNp7mSA6rz4RhAKHQyvxQU3wr0zXDmYKl +CeyI1ZIu155HAUZL2bXguauGtJWtwaTXIrQO4i5/hXied5l3pm8lCdXsKbM1Enxx +V3E/sk/RBAVETx2fmYxracwCdN363LHRvYHyP4b2qkmUndhj47mK2s4d6wc/G0IJ +HQRhooSUf5bQscVy4yyOxw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 24464 ) +`pragma protect data_block +VTq/qeL5rbYMXcLz0pVnq2QU7OySLW7WR1ySFBochA6uqctGyUZMjS/Pnq7DeDQA +s5ClOKMV4s33FMhzgVOQol94f7qpRytPtHwO4wJfN4F2g5QpANsEk5OSaLDZaL+T +9JNTHQOahODVVMjsEwLu3Hf3nxQqnUpY1Jq2hY3IPT9HQw+jYUbU1mwaaPtk3z/B +wfByi6gTuDXLRhTsDy9zF2v2hyVz2yDuu+x9TSJkxCf5Ivowir1LIvj5/3PTq70h +N6f3RfvSBCkVywuTW3T7/OhSi8wnLfdctcCOumE1svbUYFgxg4J2eKZs7MjC0kx9 +BSZcpQPmbuAEPr0X4s1LPhIA3vVVwZzzfsgimy/Xg5Jay4omrboBZMNf9zoz/upT +CWeKBGZMPg7uyDy+H3GpdRNVVeOleOFSVrU/4KbsSuM7/fgKqbwL1vbL3FoZihPh +ldxqCnYv2m//sJpbeK3FtM5xLVdzq8u7WgS2RNd0wbzqdcIbA5ahg4/wV5r22Zo3 +pDP2uVlZvB4LOCQM7VnNmxqVSUNOdZrdkfxscccugLwsZ/LRvxbuw3GVqzFEQGGl +FBnm83T00BwwWMh3yKaRmz9mYY8xXcUOaZ9cgJpRVvfKPq/yHCtnHgXpEEkbHFoC +p3eSX44fIQ/EIHBkJ6jvFyA61OKdjC0gsAj02XudRxsxq76JhRuRBETksNXiKo1k +txGlub+1WwXw3GYTDyjs23iROrf853eo1PTW2BocqDzdb6AFB8CkhQIM8lKkRJFe +Ud9XaZxwtPRYYuTWsJtwVM4GEj4CNvkOejnOgYU+YDJdHD8rTmdzTqQSwaPArCJj +kicLoihoJYPKvESIM+dRDHUXglXu0AWXSDZW7jhEcQaABvy+R6uR8NQoRwCnDWnW +9BuJ5yWg7tgdBHAcTw+zIT0yNPFPQ7yHxvcocbKDsAD2v5fA6rCKo04ExCwzGjvq +VPziGDSWQpMeyWZBl0bM8ImBRJ4NCkQLZGbWwqKCClyuTbIrl5vDQWa7RFLhz9sX +7UupGlRGTMLCeM14MqNak5fz19D/+5RGFM4HgBvzEteBpWetcsTRmDKh8dM2eCkF +q2H7nGtUT0YWjVcpkgPPJmcicdlBjkddEklWnmq9D6cnsaYNoZpNgd2vYsWUUuGC +OX1tPxXPrpLFmjWWv9S3YBktM3/bRdujZM5UsMrjh1IVZ1kIkM5NM0H0YVlE74ce +6+qAltkGjRI6dpaFA+9yuH3125i170IFrl13IiBVpBn0TX9ISHDm/IcTOvwZ6wrw ++Z7v/7ABM/hcfwOpdqUsmRl9OO7ZYHEVkzHf6lRJ4reYZ7PzXV1K95g5GWTttkBZ +oGsOAbke+u4OGduinSCSzl5voGmnEmgQ9Y+D7EEWDSS4D2B27QDHFVoJFIq+ftDe +leGgihAqC5W6p54JNbTrp1GmpIYTxgcgeVRzaNAPJ8brqHqyMSGtVIRZ59+wLNzR +GLResfaurHLA4yoUlWQwG8SQ/9m1x5Vvc6kW29v8l4MG/xAfKepI92NlD58wZAhb +iF38GP4nLgsMlWX4E6oF4fWEjoPEhMYC1fR0WCYhjQxdgKN1bHf1QfRICVqprKxS +jlP+XNEiN5RIGDKZZdbmfc7vyrfF83aWJU4joLW0m9+CMgqQIXgt6AhWfNWLVIJh +7oN/atW3Gk4rnvJTEa1NKo5e4GdAkjnd8sNku3c9tQrv7oLat7/6IzACnS7wPBr4 +kVbbEHMj+PmXbrkh/0sHfGHRwoweEGBK8lyXQfwoTzTxNDrSIUBz4+7ZsfkINpm9 +c6pI5Tv/jhvN3OC6CcZIcl1GYeKjsPKGBcmsxYNz7OKvvNz+0V6gCH5tXP+UonoM +jB/lYcsNyM2cqT/SwIlgWZguseIUmFR836ZLBqXkUVOX5vsDZryDrwZdW2qhHq6W +sqbaA0xn6pIZNo3ma6siY4TypA+UccgnQbIFxbAydrBt/ywzAhUFaCzTxv1JwG+S +MT8MoLI88wtpgGC+lbXNgS46D0Jy3uGZq6A5yBgLT5dwgYcP0M0HZjkThMozilEJ +xjRR80RUWZriVvU5QGBEd8/VgNnXdZuFHNF8HthIpgilAvF6kunsQMQe4yRGMO8u +FOp4ZXUQbuG00EM2vzEygce9HsiV6hIvpb+4M56JimSJgDP9ptsRuUI27VHqRVk4 +clLj3Vz78fgBb8TdKtkLn8mvcSgO8bWRFCBCnJ43AQry33aYGKs7KWUg3/eUrp0H +m8hey7U7tlD7nMmk9Dj2iMFv7nFOix5ISillo0soQXHWM1t2SAYSRYyichouZ7jR +ovIzBQ309elW0QQB7yQQLQ+XJ1EikMbvk7JLL+3ki5DHnerAGC0qZhfbYCoOZZ/+ +KLyQ0tsBmW6IyF2ey2NS/kMlp/5hub5DS+/SbamtpcxJnJ7Nr5VCISSSQzEtVAPI +MuJged9xjFdn0skx5Go2htScK3YatwWCbsK/lOQg5kZW2y+fObgmvLpSpdYKcE9o +jDrOIltzjsyW0Am2/mx9/90d+dehI5gKm/RqJrasmMTpmW5RIeXMutDy/HNAhNPv +lpEyQk5MFkL7x8+mtRQC2j8+p1JPzrJ0r7fJUb1muZQo866PI9Fe3L/48cruk2q4 +O7jAn2I/PFalXBGjFJVOt3MYb0GR/Qspdfqh1gCmMB4AbadW+702rfWcg6/uawog +InByisqiQi+Xrxl1XAqIOJn7SG1fOW3xGbIspRyODQuxY/+uPysZIacG7FrcYHzm +mTGm7bBoMMXdPjv1DZAkW2ZglGTWgjG0HXxfkHYoZb9ptYbeoEey6PrQR6eMSRe8 +ybn/GMG3r88pXpBK5h6hHA2+YScASRvBsEEUBL4J4OiseNY5JtjlRm2WEYCm7dSo +id+762nqI6ACttJpPIIVSFUYfDNpg0pAjEAcYkaBB1Zinxh4GS0yVIN8/4qjXbTX +PAQY+MkVoJDUoDVk1omrrZULwMs0DsSciSpczKBID950CnZSzlOISbSfEtDC9abX +P/SMOjA/DbIuD85OEKatfj4KsGnFbY6fNx6TE3eKVjdkH+K646mHzeE9vpmxrx5p +aHBcfsxn1C6w24vaLtCk2fZjIFpN9pMqYQE+BTlsGqTEzWOlqRd0rY+f5zltKtyF +Kxv5a9gnT3OgAfyEcofdRgkJvBAy0zi4A1pm6OHr7FctQShKq5NE9gnkGyy370et +X4xysoKnUb63dz5qHVbYiZOmDqnr4Xt8G/vhiUJlQTNnXPMz3juQrRKfPeJd63EZ +THahCZjcKdTCx1H7zKe4/FvEZsQda37M9sxU6IFiJY5cpt5qgSxJFh3ICwS+/ne/ +Iu14O4tQ2GbJ7mgaMYzGfCvuIgRw7Q2WpU9qTLDRwunZ63hD6p44PGnMVpJHNI5/ +/yR/yHinCR/vWA+W/hrQbu1Cqc4y7UxLLhxeefZevIflStb1fa0A9mzcFxEK7zes +vJRlE96crEI2V0nMOkRYiPEbgLEXqC805NbJjMIdVC0cC3epVKVFO+5gwzsmhjsW +ssKtEKDLvvdIYoOw0r/nXP+KKti5YmQyNvboR3A2fEUqnNmVe5OyUEDZIaWcv7e8 +PQv3RdCMTVNvluOJvG9selH/Hq529HdEbZ785AYjvsyq+tY3ymONM78uwprbnVW6 +U63pcADFtSXZSn7zWg61ziA08B7723CER2xhDSFYS+5xcmtnGTLZEHm+WHnsXKMB +4vBkyV3xLjETs6+I0wKHHcOPryjhLK+A0Pxt/TatVtWvTgoGg0JKhFwV60gsHqpt +Bv2VnchCPbxWjEm9oxXscgMtdZpd8EBc3qSxxB09Gbaf3sOczqq+MmJcT15GGvPo +16Otm32YxzzqBI0/V4HqBDztBvL1JHB0rmvB2G/9RRoSmeKms9d3pDy9+VbMXSX1 +r5/SQl9m2O9UgtZLBr5LmYJTHvkbq53bO6d8N1DDawV2ghF/MmzWG6uajMu5Rgor +8yAh1Qy/tVwtvH2HMS72NLRAs7Zts0qHzX8umxDV1Me7IW0tUA+VXalPh6GI+xfg ++FXEvK89laFrnXjbfDT47Z7fh2RcyOhRa8kcl+GvR3XeyCsaFGbIuyB5bfXMqCIa +SN9DRHk8xaoJj/Fw8fU6KEPtWXV8S6cPgk070FkIOHPM+IBOYeKgQjgvwocxCTka +dWv3n66qjLjYMGizvg3qIJ5+Wh9pYoPRdjawbX6gqwzrVxgOpJbMfZZy+hrEuE+W +RSTfsviAjKjBMvdHHPMzSwfJbuFBUzhwUL76GNQ7TQqeoBjilL/e7UpqEPXnAMIO +hIf6NqbZOo+hc0jkJc7H7kjrN8fG9hWehR/qr3AmdtT2QAB2eFy++TP5Y/8vUT3v +8CdXYU3vzRR842F9O4qEpp0QVYPJV4WLYUoj7Rln+4hcF8m3r+Cn5h+uVVC+67hq +d84x1PT+Y8klwk2EEJ0VXPTCwoAFiJ49Zf6nQ5/iojmUlT4huFlD+072Uh37fCzs +OBXGSQRVTRIeXRYCUNuWpclQF3ucc2due/MsOOgZB/jCsviZh9yztBhCjKDitH4v +/+E189WTtLhC0euW88xMHdI2sVOy99EgbklzlXkuSVfclhKD32C+VT73p/borAbz +E2G2oEsuRsN/VKRVRtUStQCPDlyrZjff4MndgdOsTONUwcTWVEQiyAVljs8xkHr4 +YoAVmlBUmCddw8YWmedfS8yAtNQ8hx7jyw5txM/6dCY3ggn3cblrA1xU0GxW9PVf +y/wGfUIE9/0M0OBtj/UvOK1R6ZLxahlctNdlR+7/KVN7S9O15NdD0ey2hYDPyrxH +BsPYzUm1AFJL8O5fhCKJWI3uVJjtPQRerrXGmVRzX52x6xaOGW/IkjetaIh91QDq +PRaz0afy/O84RtsoXEIn1VxxOInJ0wtOIOT7nbq7zE1usua9KG9wqHFb/Dlwz5pB +wpEkYN98cKg2VQcD2sc0MsBHtPkw2K9iZF5WtLbtYplElx3gGvkf7gjEJoxEyioj +i9S9uQuXy9yxTHBy+0nv6EQYcntasu+zJQ6so2bSUfRknjSdYknIt778lkycZ9B9 +n20iM1gHtSa9RNoekEsHbLzYaZx2GthK4vBLc6BMmp6L/hg3qlfeNULjUugI1QEO +M3Tp43ax6pV//6cYAwfNOVtnt9LRDtbMvRe72+GziXt516I0uhWba0M4gTcGWnEH +97pINk4TPzBX++2ukKHeFkayTdRMpiOPbjeSOJH93KwCR5hxY/ZAkBo4eOUx98lI +nlhS3MqdRzbd3eCPTXuDioQJddlkU95EPLXHxGKoJFhfFu3FSNQJWC9uRk02O9jH +cve4D5A2YfjhspJQg/v9IDiV8i9RK0oPt1x6M8z/JugROF0MRGIG2fRjS+6GM/xt +z/ILPxS7n8Q+ONg0NJmx4r1lXwAjtfTQi472EKloBzCM/U5wqLFR+ODHXniTqisM +OlEdHRSiVnX/kJPOf56LUmTS341cpWnHE0hcl5e+dtJoaz4jBnR+b2kA3OM+Quer +DFCVBxd2heZ60FyTFOp7SmnwtqMcA4n81KLjwluK2/2KHWPDDKMld5UWw8h0aaX5 +C/vmckob8m+tEUI4KvIJLvjLDlvkjVZxCTbw0Crzq+S3PA3uu74oaKOxXAOHLpSY +T/18dhYciR1FQC9tPRYRxSnxr1YBr3ZnY/II2PwcaoZc4d94fPPRWPL5x6WQp6fn +4dKL0rK/VBEQ4brinLAnYaE+OTsTFJpnzjQuaxohT6qFUoZjVEQuVWkGMrXTMI9N +Gw4jFRKK5B3+/UndWXPIc9gx8r6V8l93NippLEQ2tL5Ld+Rb83n7nSQKLxFQHaJV +Fg2Ramf6f1UUhIH98Z47a4iOjD5zfYsWiKkiQjIuLEo3VRGmgiixmfAOzfklurYQ +pA7QopglnZLJc8uQ1Q8VPP28QomPnEz522sW9irX186QJhgfEXGrif6JGI955SZw +Gzki2XZV9oNqAwB8K+Dr65Ae1weafkr1deROfiUHT7jX81s0mCOh1X3KmJaH7Vdq +qsGfj845Gq9aXJBy5I0vsZogtvafGUpF7r9QS8xS2UM/aUBZBEh2pwkD0OgEJjcH +rV1fTOLCw58ilXmj6dMxkvNqGZqyi/kMUmPtvTt8c5Z/TAdAkKfQnwMlgZoMr0zu +kOcvr70MdkDe7HiwMj3x3GPmcbRTfdu/lFwqCoo6DaXx6V6+ty6QoNALBtlEB0NL +y+1tSTuX3YMjZck/Wz4UB2XVH8iQ5iXFZH+rFGB2cKTeYMRfi7nN6dGvwQSyTTH6 +7slMZO5JQmqw0FKGOg4EqaRVd+NRQNRTTw2Oj8Pir4fuUkJMrJ/QSi7Sb7HD0jcM +Z2GMVsNZZy9MTbKACa1O0y9LF2pWKw1c0L86s6icApuLzr1CCM5PSY8TzuBLI5EB +/zPogXHR7yNeuKS5gtqbEUfOaZLXVQWX99+wmjD7dl6wqw5g8N3S+Jh5jWjyEVvE +D9AcBcu7XWtlzzSgBN1kQpi9zd3/2T8iuYA3globfEs2jkv+N0cINcpNQzspHLFV +bY2wTOk6detdQlkXR8TIh5CN1LaNkNpxrgVtq+n2MBkC3+Y53WjGeG7Shwt2gxtP +lv3mVCE6B0j8Zi8Qusd74JUl4sdwgG7IdxnOlbUh4JnmdlAXnmtj01LwVZTQCjJr +dl7JwlV9szhW7va8d9iBZwefCaZ6uJqu+Wu+6CWGam6xYy9DqnFB6ys2FKNjp8z+ +RBErmKvnAEEZc/r5/YBACuaVYGzr9ak0JtFigqI3EOXDgm6Q6kAFiT3DwILQKjB+ +XNOEDkUwv1qI1ozHH7FB2MCbKvXyBPselF57fTDfjsz1AftaUTyZ/67CrRnGks+z +GF/F9rsM5oSQUrRnHeowi2udmiW9D2B2vu3zBi/nkDRyQ517G3A55uA0Pgkqo6Vg +za/6c/4PWgn2GpMyFV5TU9kxQuZLfJrulnjBUxYlwWtdMr+cOVQ6sUJsY5GTdrj1 +qmitz5CI4xqj6+RIHPPIJo2RrxM+4hGHefEAdE/519YJuXRyvn7AwNDlbyR2023g +A5yAeHMVRIbyfSsUK+THe0judO9hHUxQJaXXpt/ROEKz4zS6kKb1DRIaeT/2BXkt +c8Z+hdCQTP+zwiihopr0U1dJYMaQwrBv7NqFjQ1snfPGDW3VFRDGfdQnTEsZVhyE +EPN5U9Kxt08C8moIxEodkxfl1I0pRZ6+SPngatBcfynJ2U9igp4Zg/rR0at/3WxJ +rZsFHAdDgEVkhOizM+4/6Vflyi2XQ7OtHTMkbc9Rb+ta7LPRtd/eSzm2r0ae6qHj +TyaTSB41QG4fpBpsfaEw1iy9B+KBNcgiU2S6tfKR+ZzaKgKOCgjCP6OChT1ZD63t +EJ08t5nPhPaBnGg6XJ0q4q4btfM+9PUOY8rYPx3a0RQm9s1VsFk1ldN2psrEiR+l +6l+W0he50lBg6Ov9CfAdOpwHJQnwbUEWqcbrULGO2TbUj25b3mghCWwyazzrHPi0 +yj8M4moWe0xJtSabkNcK/uHN+WAhblqSX06ldUij9+PxMiALfB4tvtGJe/6DJyio +E0sil9xIK/8tWcDVYIjYkFU19tlZGdDxJqo7MQjaDYOECiwX6DYRqbyKCszakypY +58i8Klxgojkwl2qkC1QL6ozvqwNHy6p5sUzScmACsk5qMD3He2SqGlsxKnWPtZOu +nLdQLvW0M0O8HrRamdjIOwgyj9ttDARrQkyLcHdWp0Rs2RsKrDYfMs+5gH8hVVlI +gkpfIWEuOdWM60nVvofgn36o16EN9iptow0tuEgTVcamTB5VZLxTAf1t+SW2TfAY +Vd5L1mbtNB2S491sN74jc8MqE7n55/lx7tXdP7KB/u6XA4FKsHm01YplT19YKE2i +//595NRPuurUdczfnnq2N0MvSOCCuOJZ1JVca1idZSEUQEc95nbAw/pioz6JP/mp +g45sO91YjcA5Hoxxrd7YYmaWdu0CdK7uPVdUkd4JATPFoV7Kbc2UGTaV1edC7GrP +d6bxGq9CO/17xu0T5UKS5HPZZ/EnvPD5l/GPA5n7scv6cfgKlMMQljooZfXMxnGV +o/PSoEFK/fhhy+85rkkPLaeP2az78T+alvfd9G4GOsPNlichIagz6aF0dP12LJuS +k5aKn+a3zqexr4Tcyv7I3QWXMh1irXfWznC7+APOdp/TTiHKtg11MT89Hti2r6rg +CviyLo9dvDvu/NhwFAT5lRT/5M9R67cMbx98Kk039bk+sStbKIWrYFxJdaVB7e0g +/b76mRqEUnsb8ixUtPzKCuQjkbnScc/tac1VN4emoVUVhJBwrUGcNv1VU7HRA9gq ++Z44uymsl957AhYc34bqrmbbAHDXmog8k5n93UlFwK83wDiweOOAxfGrzJU5h7Bl +uLRGtIc+SSNP7/xe1UijoYOSrIam/4P1RB58+0pUQtkzd5nqWXo2zEXrtn6qG8lu +r7om5uPdw92Y6W69P685KVav6U71t2NCtccSgF3NXCzRZ836YrufjoYzu+SFaYAE +SIX00EYlyn2UJuXzjOJmSQeFpDeGesFv5aaf5ecPGQlg63a+fAiJsz0uPf463K3Z +A/gA2MVuxTYhcRNYrq6221Y4uk2vDwATItHB2I/d7Rck2zGq+JnJTgs75bKNyIdx +ZKOoFddZQCwawdhoFGYPGw/1UBeCYlJd3UEXJv6/ZHL0I3rPFWSArSzYrrfoho0X +AxDgzkLgoKqIwsO+3pG4R9ntgWD18YBjnpTxrBDe1m44YsNwWvowGaX1lWvEfTPe +6wyFgyotpNFQu5iE9/n3UQ1S3niqHWgDXAYX9cAT409jK1CkwSjMh6GwnHXV+6ZP +SBoE0QMq20f66TNny3Mq7lbHjQIy2aLMdh1bF71Wi31tOtZd8ShwY7yF7WdwkbNR +rptvNdpypf6W7RYdI/bewh91pKDHQWRfF6rqDM+swkRAwXEMw3P1IF8uu4QBb1gl +hqR83c2ARzWF9DavjCMHENeDV05bA3PnkiqNFX0zJRZWlJLlc+eI4fiPTBv/ZE+D +9CaQ4h5CJzM+MlO7RvirC2q59AvJK9xH8YENv1eAe+PTJj6kwHJPKXvu4YRh6kc+ +5EPDmGGgElaAtZVda8HVVtgZF2vV2V/4LNFx5NKKG9PWLlVpHnqM1/kyBh8RT9Ww +WPkTpmln4xLraEp3dtIZJINvbxSXfo7tPRlRreTBQzZldFPC3nntD/SWEwH43SoY +QXi+8tnwyD5NQOst/RejpSW9+lxvuA4NeNmrjD+3NNn6IY3HgiMtO4jkAG+BjJO/ +0kcve+4eCjjoPID+Nkgi3MiABv6B+39tbBgWRYxYEJn8QHekr3X+Sn1y8GE1QjtX +VCrv27Wi7kcK91iiL42b1yH/U3q9DqW/vpB28DsUWUQBzrGGTBlQIwLyhxCrxjrv +dfsLom+y1ecpoxDy62iGGXNGqDylqBPDBDPYUmdcGFlXxzpLjqY7iBNSOtkdXoGl +LOXhBaBA/U7aThDUreSbrb0VFMGxFW+RNYy7IeOVdMru11xYPqJ2kTTQ49ezHM2r +B+K+2MBH5BsW1ho5TK365CS64BuAFqvoiojn0WTd954RynB+n46s+zq0niuY8UpY +NLjav5ZSmG+Evqx51lEXNVqALpU925chdx7bPBnmSSuX8d2XCeDWU7WmfUquLiZY +5IHKp3Ob2gC53V57IB/t4HOFhXyErIznwT8thhD92LFfDJDpMthmOcuCCuGbaiX0 +mC7K8Z2JexPu2dOs5fF471MPo3J6JC5zEungiQIeZ22PdJU7P/1qM7sOApQHBGVP +Q6okOaDrl86s6b85PJMLd/SMRhyRntp8ZxQ4Crrf48jx+Vm8myKRrlJdEIYIO7Zb +5udFlsnU5EX+Mb6ql7DasT2CP+zIVzQbmYajVwk6vp92ts/6mg8cElPSWmhFAFfP +OUWaSECIO7ar011Kd7ckwzT6y98Vw5Y+0V3bUJO0F076JA4AWUQdEo1t4TYfJfqn +yzlOsEkyCofnVVzSRh8DWHJzdjkAP2465/4alajYgGyUdmkKxcSIapXhKBuwcaDw +C8nCZocdvu2S8DMLXD/WeaSQWXmRO5S/so9cLarw486leQIUqacnfHcmhWUHXy0s +e6BLyFjpOuTDKG3St/gwePJ24ZL0CqeKCbV1E+i0ZCAQRm+G8N/0JpaZcb4P7ghr +Syprc0CcWUK3faCkzPm7oZEzIUtkKhWf8B7v2EAlOQqMF2tZLKSMxNYa2hmNVxYj +4hz2dw3NKjfIHBGKP/waPNlgt2RQMpznQWssL5CaoHo2B/dLgqH4KminZ1yzHkPa +XEEerrmCJpnFkA0h+olkjd6A9ZFxrcyFolp88sk95+eXH+hfjt6xdaw/AHaXtO+E +TWy6i+7AkO1EsOOEDQgPTvsL+GuKFBHcSz9TKX8jfZFlhtYdfWl2i/r+sBmbPiUo +7EqzuEMF0npkqb5BoLSMPthVz+QNYGhkfPnTKgX7e3rT9LiydzDdP94hQE9joLUp +cXND2mZulmenF3dSmBlEkjLTvxVKZXgWBxkjyJX+zgvZeg9L5rWxN7Fyqqy00JD6 +3bNgwu9A8yh5TD97Kg5QQ1Vt6/NcnKNHKYK16g6/PWGkIsAC5/AFVByhjO05YtyZ +TAOak0EMWMNQhKw8ootYfcDsDfkKQQOAW9ZcC+DGFkfrtbeTT3tidFxac3X9R4BW +KgSVJSO9BD6aYfMys906T2cQU7s/yVC3/4DZFqeq4sQWGs8Z4AsgEr4DNZLomqq6 +l512KarXXP6qrJZpbgu4Ht8+ysH+f3PfgHHz4lSYz0tsLYVa97MZ3aspn1hEHjE/ +Tk73oYtPquDuOqU+gCxluhfuQvdq0AI2uCl+RDrP/3IK33jv3mSxC6po8Gvds48/ +bSYE7bzQFKoYDx1RPZWiJK2WcmXGfSjLyP7D1sRpvlqdcm9SeUZmfrq1W7Moqwqp +6Lg3KPzr6jSQkW0hfvx1oQngzPlJtRuOeBX8HKzUTpvaySrXMVWn+kvC2hOh9XyA +Z/Pmp4mkJ4vV0FCOnMTQSnXYEbsB54LNls5FN9Ftunqmg5XlGtIokBlR5NkzA09r +nCFmCU1vYdQJAhOkMPVlqqyi+/IEsib7X5/6O2Qg9TO/I4psMZmfFYMAjGPUltXc +pmHHfdefTm0EhuTbTzQeSiENTrAa+/4G95XMz3B+BOPWg+BSWKth+5mgSLhHXHIv ++gwg/Omo0zP9saECTaELZpcoRQrA51R3zYCBCQIJKlg9Gi9DxeoOk87oUzlBaeqO +ljwYg9gcuaaaD2iyHNZIp32mHBiU6Krgx+aBKdiKrfDy8gm5LgNiLkwi7qzUyqdy +i8n03HaTLfSOOoK2Abygb70nzuQ8cHnJHWZNt12pGho1QRmOJH1ZcC0XQaCwNn0v +q6n+RO4h8QG+1HSMLYP7OGaxawED69gZktdDqdbDWtnbk/E4NVR5lB0OhWAtvCZ9 +zDEXZshScSU+6erzyukoXvVfWsKAKNTDQvngaNbkIO+r2J16R5MfyiTX3oUjzI8g +JC6byTRHwcBdJW2NzvzewKvFDnwrQzNE+DwOt43oiU13PVPLW3gAJ3xl4GiI5O1i +njVyIfP+ftzu4JMBgysK4g18M0sz3mWCxxMRQ7pqxlj5wUt4LHRG72oBjYG19xEK +mM9vgeB2oXaDxlFnBKoIJ3cdraczGyxqZajBI0SCcyTyXifdg1o6pM4FJjCSHBxT +7sgVqIIqwmvqOhOySu5Y8zswxttYxokcVOg6pegR0y+ZO2Z+/lHMFCbRjoIOtzuo +5PX2E94FrdjvCskaOZGwRnQRMosbBkrcFIxPMI3IqYTvPFEEY+VIg573vdr2Aic5 +QiONULjjFt2QFzkwOIFosxpHtoujpQqLNA2QMj1NObsfJnxVxtjdYxUhN1hBEAB/ +oTUTOXvASnjjX1zWZE10tnWrY7CQaAPlTnBdlZ60UfDaWC5317uoubV98IP7LsiO +bysdmfMylo6EUvGWKWs1uHMU6pKOWMGQGr7eKBkTd1GFRSvPcwCI/VBgNsFVKDON +5nuMYsgbvKEUw2ZU3JRlUuFkhbq3YZAKfw58zvrTrZqioV10frAE806FuoTsiKDK +8uKXUemT5nfY6ln1uGOUggdrHkFG0NMOc8LEju6dGg7lZGkb4DSDSsZ+qAejkYY8 +jnRt6FuaSceCLUq/J0ErevhmfHRD7XpUkkfH9Bt/7PrC/vJEYWXA+d5HyQBYiV92 +AREcRWxvrmzBJ6icmitCoiITq5uByRQR9Zon1hzcPUVf6yYlI9zpnYaQ89kMQpWp +AQwl9oCpeuXeX1h+2euhZdEYpxTeHEirTQSrgkO9hR+e4KGD5KirUrXWJXGcw01+ +F7RHFSk9OQtyRJJYRSN9wHa64oPfCOkr5SWu1ADPxaksYaRgw4DqBZbsv980Eyes +6wPqMmKMYfGVcW0VnMZEhg+aCN37Eai9gjR0ScKhbuhMUhgn41i3criLcBanbj8s +YIQGJaIUY7kXT3QmxdqierkW8f/STrHyfEMDVJieEWWSdeksbgg6D9WCLK0hLtVp +60YffjXUOW/UaZMcG0jWgoN251RNPRXQAmPHfEJBF52q3P7gyKez52R2jWIjtxpF +0VeyyzSnR+qwDYGroqgW0IsUZyUWwALNNVeajfbZDzA7EAXWrfYnOM8bbCnt2Er6 +EA0DboSOXPSSIOT+DPsBw7ef1+vRl7qf5CsKDEydUbX+kpAmEvksObiciTr2PlhV +VZtEwuVOpQcxS2kLUcDKixskft9THMzYxwUwp5Gg0TTQ5V+666bKXfmyMQukC9IT +MJklMKTNzuKMsp1SSqF9i+hJ82KRYnM7mps7HzDr8FbVhYWPnUUHYYESdI6m9bOt +TBbGmme/Cv0Xsz7Dek624Jyj6ATiA2r3dz8O2eSHBtnjtTzfVM5sEGm4y1b75jC6 +nGaN47Y/wq587xyXx/TO4eXWR3tFXKr0uiiYvgSyhEYTbjTO3s8WxWzV46eFYB/d ++tG4vSJ0otC47aEFqIb2EFjLg64SmAcyoZN8tDHN8DVTAhyaT/aUqp/N3ziYsQ/E +mRNfpYiSnkIpgJSnl6iIkYrtj4HczkNNvZu/ow2YHyJs/W00aYT4Ymo0l1Q0kmVj +hmIs6mJXDeCqM1EAzF2/6rvp2Et+h3yczObrS0spsGIb5bXdQJ8L1akQUx4keExs +OnYe+caH4SxaOOWKngYPUaRaGUydJ70Y8n/fNsZPpxQlr/X4U7B3rGD42RPz8POA +p/7NWH1Ipl7LAvV+VqUUrYHWh0osQOBU/rgS+M6d3YV1hlP+uYZ5NmMhVdhCTT4v +Yya3k3DXGKNwrDyBgF1xde+z3C6JkgXtKpKT9pt96mQEMRuC6hqM6IZ5DCVOZplq +u/Us0l+JYw/A6tSm8H8Vy8EaxdGwsqNz5UV/Hsj0oelhXJZFE4PGyR8kH+DEDFmr +9OJKmOtietVN+jwlG7GuedLvXjH6WOCSqPEIQJ+mAfeIHF32k5mU/L08yf0mVKcL +NES6kD1H+p4dK+KzdHPDoo/rJZWa78CwlWunn7Dhu9fpAYCjIwcLukhScmBeuQrR +aHMtc/OjgQAwjs9Q3bVfRjWvJaNJOjDzPrZEO4v0RR50onwKvN60BM5exRZpNu8W +ikNYAXsfS2cWvFqQC3CN3fblnWihYhYE8F0f5WexfttI13KRc+D6RllhYLTJI9l4 +RmrOBjF1d3+MzjHP3biUCFAR32w6NjSQq5KP07acF40YzaFD85A92nt+pTJ0RA5i +zOA+tOJbraGa9P/Soeu16riwpsx67LgX/RNt/kWlku857OK5FyuAlS62KYlxwwTW +K0WbZy4aReeoIdIty0EpAvL38wWm6PGSqj+w+J3fGNYQio8PmTljputWNRq8ho6l +PsEjqs3KQ718IY3/P+ae4rtWrBdW5NN1qVnQuZON1McXHNRbfVmLRtVyYSUxEERy +dy8ASUsTTzk97tgywQ5DZ5i8/vdaJiGZ1QnZinbQLaOd4q8dP8CGEIex2Gb+8OYk +fyXt6ef5Hsrd9LE/a1C4gyQDLcGoRlARVXNldzxCelfKeD5MZ9Ox5A5wNlbVkfi3 +rL/tS8KgW8gzLEr7xAKo4PVCn/98NeKmA/7enmlP9U5cAgTzu2w82YkGhldJKjT1 +tyeb6VyyL1TACTmMTppfiWzMKXsS7yxrXk+aHaqXzkDh1W7VnIUXsbGO+UDgUfkE +/SbEHCbPzMeE/JiojHTpgh6W03HiltnBWnjfi9PuBzpwO9pIKjzwWy3PEFbJemvt +Ritg1ludvlpE6sqAvDO6YVtSuhEtn2+vJRJzCPOHRjUhfcHu+sSUPOkBU4yPjRLd +6+7UyKAaVGfLLthO7r2xw8T0G2+/DU52YtZNzd4SFakMXGNVlyIhPA5zOuqxYGrP +FFIeche1YTgMCvFLmRjmURDgbT9dGE57FUrJnd/EQmoVoJN82i0r8zGLaPkgMbXt +gvoD3HgACf2FmOhV+05RWKxDspQCSgY98GtH0DCtRJyi51p4GbMRCilEMv/sCBHR +eyRYGrIX3Orm4yydHTeE20vCCich9ZoxQDu6ZKuWF0HN+rORbOKKgNgVRoEuRvnu +DdgTsYKLo4BMtDDHXE9J2xPDtXuro/+Jjd9/AnsJ/ZrbTVOlrdufRMPSer4o0Y0W +vwuqL7Xvm0fNBOc+BQ4aRzWajLBX5awYtF/riqkLgtNCuOiUQtipMVAQLewsmY64 +zGA5ICU1MaDUkDdRerGFX5VQP2l5kq7Z8zX3uLHlGieBXL9YOULzrEWmQf7m2zHa +p/Vp7BUhDLZrWjzC8hItRYTdaQdbQly7MzVBTvmeaKX2MmuB66q2cP4qSBmokzMG +U4ZMKU51YfWU0v+vSO9zvhIJMre2XeAPQWZPBtzK1QETVDNqvh0SAt08dLLT2YdI +Z7PbyBM6dmTMQdpb3xny72sE8c6fQ8UhFaVifwkHH28ELCYCC3DzNnlv5XdZGh2B +s72d2J5W12vZaqf3FZQJM0bZukC1fca3zJ8nU4svIr++JlNGTyqZxr6ATa5xeJ5S +fSrYYuVRo2+OZUPxm3s6tVdpcBLdQ9ydMOYNeACd4Ms5x628IDPW1DY3s/1CFgr4 +hhdTs7bGNIHAyK/1yNGvVfDQooHSH+8e80pVhg5fPmbXsmfK5S2Y5jCF9SQqPFFb +BSP/vihiws20UKgXYzEBBoGozzd3GF5qjmafkNeI/BMliHNBTSNgL87gF4rSjQbF +drM9uigPBsQxIhlDL6uPe0DKnX4yaoKfNqED20j/3qf6KLhUVO6TC5a19MtjsHfp +Y3JXXjucnYtw+78cFnvnU8QcKNxWK7OhHIxzCvULb3MRQ4F7677sznUaxFEyU8UL +HvJWJbP2pnXBZL6Pz+uHqbd5B5RESBggFMrXa9Sttvx+0IKKSsaP4UahRiBdeAsd +OmPFFSzjDzAkP13guDI2LuQJSow+k3rRGONQhGEK9yK9+tFEosTrCJmG26AAOTmK +0qwP8741XYaaZXRrmVx9sNVOBT1AHtdQP0nkxBIhmdj4rfhtLvgCSgBt1m8beHQd +6Qhlfyp0FCjRW08qtHYT7l/wT/f+HXqELEiX7I8qmJ7mV2ZekW/eqB84BTBFGLCF +kx4mJ0Vbjhc5kbGbWwy7TQNV6MQ7R8f0kce1UJ3ltLIdvbfMd6mgn8elpXlewJkk +Nj59s5pRwApEA3dV572R2u5zAG6r+G0uc1w3iISuYmPLpOUJ2FvLGOXOmmrLvIh9 +dVinZ8R9Vs2d6V+XJ0DNKANhpWIOv73kEDzQHCpHC0Dynm66dF+SqO7C78RZqnKA +wjZ1JtMKEuHOWcEFNfjkoRngQn2kVRgY/f2HN5iTGfAmoQbaG7Z0qjxwpqxBOg1+ +BbXloBg8X5SCJQC7q+u8TLfWFEyjeEvJvRr88g2OreWYqnTcMACWQ8O7KwFkykqD +Y9Dl/XC+viB2AjceAgy0GKraweQ74JOtPzbp8ibTYphvOWOvXlkwLReGRSzl0Ocu +VZw0bQ+b8di9tUoutn6wEdBP8vMvn4bFXxWP5g6HL5Vtr0NHjWNd2+/hFXJJ+XRm +7pt4T36/QK3u9qa3RyRfUHo+Xa1eMadFDgs4w9QiKNrR12ElgJ1s7m9kmWhUm+w3 +KA5E9vSb4B0iU5EBnuzgtHqjzrpM6Ii9IW3w1D0FMvKgXtsX5jriSR+7QHXJeuP/ +3bNV6ra6me5tqCbNbZzf8U6O2RXHQqq5sLFXXQ5pMo0oSmOPAenNz5iGRPNUBoMr +37kBw4taasAgE2JgYW1+gawHoQOI1pl3nO4bFvUsLtPWnLQziSN2z1zPo43xbX/5 +TRrm8THM6Wm0Vl1gzrHGgnoEDqvoQKANmVbP7A89lSFRPW543DuURkuFoNLWu5s+ +syHqT5oZaJf2fgIwxZCq6DxB8HWqlHwWLsdYOojgoBQy7vI9PKqtvgLm+zfKz0Br +Rbg7Tjfb1D9C6ecPPkrf+5UXWmNlumLHmG52o7c7vI8M7hmS0fQp9jPxrHI9TNe4 +w/b8XG1LlvHWCUEUSxCywmvy5ndiCNBWeA0IJ6JXnTTM1hr3gexfmOr3dKMJerBY +UfF5wuWaDA/RPagLfoq8EAT/Tb0xDgQhR8xql0zWDf/+suhChu+tRStBB/S+3A6k +Cbk394i2CiSDn6FmTFU41Khf+SPkdrWArHFSIfe3HG/WFwncQ08H0ga8ZbZst9LE +q7TKVLmMYI/o0EJruy+z6vkknp9NbkGhBDLWHTnssFs8pozVWoyoD4bOGVdQ2b9k +WhHF1i9e9q2sYvRZKzlJXEsVTjl/+Up9hVQwKVwDthPGs5idMpGyXS7lcC1tDj9N +2pimqHtAu5hZ7MWXPXgmmGITB7xjK0GP0BSbMwIKKgBDJrpI9lwK12HzqKGHzWGM +ShIh0+GMOsDszoUi0NmP0OFNL8hImk1GaRKXatPjFB0+7dSU6p6JcXpUOCHOcW1V +yI5UViNXRv++hRb9nGQs4kh3lnRSwVTs4KiMe0e3g3cl4LWLpl+an0M2Gka+hO6P +XdJoKZJ1mEUjX2uRJc+OWC1s9KvAjQNPpUdnuBZWe5bsfkf/fxyRzM1JxlxVz+3e +1DMajfNrAz3/4EPDKVM2gwF9TCL0CmP0xkCYrp83MbzwQzu6DRmCtag5z/nAApSK +19DRC5E/NcVh8cRQCxhxMMvUm2hCoL7KSp71ifejckQbpG0XaFSslGJvnN47HvVq +nofj0XnrBRzp7967WSSplkzrpgsneyYOY9D2BaGmNg1Uj/h8d3QR/WUx4k+Gvc6m +TKySdkCYCZ52LvFvsmZDUO892Bqqi8TKzVogwYgWHIIvTpgOp7NyCQOCDXf0QuV2 +s4+frVMOYb+N87RT3PqSvXec6R9rMFmksKUJd1UX/jVfnR6ifqUmwIyVp1Hb6/8c +zGLOyuMawHKFg1M10EpwUd4CRHkIRvEFrtWpQrjQQyIZBH58HYSiIrKefwHYCpZS +HH0as5Ex2BpOw2BWWrlPKm9IrBl1LLDrDrqJGKXZJ0UEBABXy7s9y9+dO1AVxHQH +EU35Y5r0cTFcbtw9UVwJHljs2iFkCRr/mE2j2Zw0hpFXI3T8ZaB1gua1KkJQEsMk +UM2Px4wDr9TL+CKAOO75jW/MIknB3xsCMFJ4wl/tSo36U0jn3aAmF5Me9/N8Gc63 +MAG6k/JP4YCZWksT979YpOlEIO5udEupzArkmEu5WWJJIPRYGMou9hSNx//eFLVp +0myXIgOvvUbuxycPwiAdFjhGu1F5EJBpwGlgtA8cuiL/7WGmgOLWrCKOXLD9WSZO +dDx7mSRHZYYyKtABNwzHqVN6B0dydwT3KR/EsaoR2GPOmzlWCXIhCBVx3YjxEA1S +wCT+siSMoLmfITEbSHi5Sg7ESUkK+Wk7cAciaWM2VTxmTLIyXO+WsIWoRwEdL2mZ +7VuzaHr02IPw3EhPYOhitOcKSvzQv/uT4Yit4/Q7AQeKVT1yt829FnBlPwvFB/W6 +HD/RqmTFPzxBZ5Anu4M4a+o+u/NkhU5LCE+VLffzmNL8GGS1eXyf12IJm1T62/W3 +XOX6127dnVAIIYqgEIf4M4XfPQAzMt++66W5EdQdkzI2T4wKTGm4iZP2Kp0Cbtr/ +4eKxdyAcdktYvBfgS7/70fc1lowbwCHu6R+k9UQgjidZPqdHSDbl7FIOR7ErxL8y +KEcFh+7P5GJBaegUH7n+ByK0BNYPQuZNQymZJxcVeTtqcs7ODPfePigwlShn8KJ0 +aEa/aV3CYabXEM9oCOlJQpfqeda020g+HhItAmYbM/ouCPAHBiq0GAU5rrC4fS/N +rT47gkRDoVE+6PurgBINQQJDSMi4FGLvar/Wvb37u2mb4iqUf0tIrIVsl58Qj/uj +XcCBuaHuuSeYFpcfQcIQjwGFZRfurZkbYUhNxtyM5VgMaQnaVD0W/4jVwSdwiEc8 +G+B+jGY6x9xMwEVwBo0ztuIvkLYDX9g5I6G/cobMEAAyanpZ7H1Tmp0FwqvjvPER +f6b67xTpGP4eycenzQJbHusj3HLu6GWx7cOAHlEWlj+OPeskODPDrsISZvazO/TK +yuUeI2t9DJKPz/5v6Qf0z2d9jnoUy5q1lgqa2o1sZxcpy/HOfFbIUkmo5A4QWqt0 +Q2J81LY+ZKrRz7vcwO9WWGuUA9Pg1xEPDny3PfFWsfgeK6lfIoGoehQBqvdc/7tK +AOQFl90rMlsZK4U5IV8Yo2lCKx6fTkEL3fEwKTXnfqa4ZP5n8o1lyidG7DCaDyqm +JWwWCP9Lv/AnMPnFJSOlEcFuEjfJBfXwO3TofseRSdQlpnD6yOw7J+yEQWKSucoV +1/mFTS/s+rzbtVDBcF8rk1EudFVXJw2eBvccP2E5EUFuTSmzcS/ERR46wu6YI04D +ZexQ9IUEBSqb6tCxyzYmKXfood5v+2RDsDIt90KQoXhtmiM3VPKUjRYyFy/daVrl +OjA/KiqUvvTK2o2lrapyS2BUobFqquD0onXM20gmXNTyozf7HSjf4Of3/6YdCMgK +8zoPx1qJjuxEddu7Qr429xo822nO11IUj3IdHfyLhAROfP31ATOcQlLaN1A9AdHy +QpFsNX7EDga6QNPA5AENETPD+rI/H4u86KkqSOQU8hHv7+KSJ5ltIBOJDKbH4YBd +DW35Z9d9Lhg9qbc13r/7rOit156t0XgSpb/r20fdUeC5xHcNeIJZSQ/SpfRDyJgs +mPQaIgwG64q14TUUdn3uE7vTh227l1jmG/idbiLm3ICGzavkg3OG1AZbkUA8YzDy +oVkK0TR8F+CUW/hJtpMeIFq6B3+1v3RgflydTspxyPQBOz02lUI5Z+aRn22k5fGM +HWFXFyK4FUHVMDVpBlgQ2aWAZm7dDUcPl3FSDksP88Vh0fIni27D8B0ZSwQbKBRt +Y502O4gVJxg38rTO1ArB9EGrggh1j0PHUWVZYyEAsXxtg6uslxOn1gOUx5YrDw73 +qytnzWedlLbXTRLL9brVYTeTGE3hS3zBtpFLpxt2MUzsPdFxV3plLZTAReGlDsEO +IyAA8WjJrMx7r/F/tMXqN/Q1cXm75lnN328MDXJBqRDnxUet0AGRQA5hyWm01Wfq +adIakStBmlqzO/idMwZO35p9AMexoSpWskDxIiSrnjOnkpC1RPCIDamUbIb//5zs +Gdcs8GuiiYas3pGHt/r7GYr4ZOdKVtEf18dtNa0NehyypOfyknuRR93d9dMEtyah +JY1LyXUR/RkODnDh2w1Dns6I8Dt6FFLBzWg3vNLtR9xdYYOOJjQGrmYMXR0eogd5 +h8MOALPchAaKr9GIuPWSgVMRvjVkd4+rTiktEp5MnPrQ5mGAgiDuKuUtBSoSXYj6 +LKapIdXUotfSq1ugB5tpOuEAVCYrN+oSbVOyhEH8sOLW0btFDMVb8Z2BaB2wWjHn +HHIzhJtluxrhP+IXLDgQEgVeU64iKyOieyaqJclU7VmhjZp4KWC5mnYRwzOcmwRO +ffpisHDU2xBZ+Af8ADb2Pf+HWw/doOmtdrTQ2QZqJOoWPBQkEaCvARG5IijPXLys +hra0Q7J62xQ3KHjHvOkla4EDdosQ8hSIsCD8O3N5BpPLZqs3HDeKglh0+8e24OIK +9H1BkAaPFILht84ON6lcdzWGEg3pKlZlXrGZXFJm8uSIR5nCGLbtT9ZBFESzOHRV +CAD7ZgCujlmjaMOb+5m6wp/sAtQXMKDMYk/9btdi8aq9GkWQFm8Tcw0pm1CqnlkI +n5+zrcOA6mJffNKns6/SXkLSvuXg4482TTbrEItw8QLsxFIfkTFypHGi7fAH2ndS +xi+VZOeWiY6oVm1UqOOI4+kEr4vbHYQaZGSGv+LAXqWEchGoSUQY0Cb5GH9g1o4F +F4tZVMUYN57qJcH54odhIenBU7PIIK6gpXy9VLnptpZ7yk2Mx9rrfYdzIZfJQz0Y +p8IFTegEaaILfuv0mZfghR76b4z38Ah8CH8spNENlCzB2DHHe2Q/fmPfJzfse89v +APEZgsmOpRK6/pNj1edKGm4kJGgtO+kW1Z3gysJlDvdsur04jwIStGBOir9HzoNA +HPq2ftJ/8mHQT1BR882Wfx5KE+D0cS99gRsLF+NKiBocyhNGm4TPq5qSEHMJTuoZ +1PWji5dB54aURQBdoFSAzZq4UMu3uyULGVm4czX9Ypc/QPF/dgQYO6pNKSDpAKCq +UIDmHFKJQf+xM19JR1yl0XgpF6429/XxvatcoDZF6Kuf0y46gslkzEexyF/AV2La +MElPLWVI1X9hbrEvQaFLt4nLczpMYT6r4r7gXm/q9IuIC2QgIbv2+Deol/iex8zm +VMn9+L3HphPe9vSJJKH/q6AuuPrFm3hK5AZD1MEb5vWEbxzcwgpSpgWUSd9L0q5+ +rJ/PoRXM3Cx+4/wjW5NBysgcMdHvH3jmTabJZjOgJC0pJDbYCdTV+FuRzriLPiLo +SK+UokJPpEIleWJQ+7ys6jP6eHiy91g+ih1I/It1ZlBZmQ2oPUluwhHVWGd6mMSM +K58F6reX0BNuimT4+RxqHhH+NQLxbCj+ETBmuwsZXvJJM/FZLR3OJSMYuvKiw+CM +mmUSpaqTrDh//gEqOKRdUojQa5npW10xmdv0WhXvVklISuO057bBFFA2W0k68ZRN +onF91GQNE72lqOjHkX2y04EDHAaA5cJtiKRtPUgttRAWyg5Ak4O/0GbBzrnhgNH1 +Dxuuagn26BUbBWYGdWP8f3URDHHCoZMwIyFkGL7SBk8hmUmwek8tkZ5TN/hnYL/d +7LPXnaaRL8VKZ9G9SYdCmFZgr70Pn9fzzKuR+oxICLc3RHJENnzOnVklmcihfauT +nzEie0F8pUzMXxX57aLEbowahrp+lyng+YEjTKZXO7t0o0SLIwnauS04SfE9oikV +R1wMuJHqWUK4kJbNC/HPGliFZDMtNn3k9UPkrVMI7YKC5H+71QmpYWZnpK6Yx8vc +ttnBlYi0myorMifNY7MlDQddBI9630zlXBXv8gpQffKLBIgH/UoFXY934BEi2vUj +62OdhyqoEHfrBRDM63IEPplui+Fmx4ppkogt4PQWTq3TJuFeA/AygXk58Dzpka34 +2hZQzjAjWKlPpXDpgNg0ag65fb95eZZh4bPj6O1pLSBMUm3nfXh9O4qPBejpP3iu +YCRpuw1Zfqx0cBDilL0X6nuXqlVBRBbqc7uN1VPzrGgdOKdxJ+y5ot/miBQwhclU +LcSIxYt+FEQdNBAo2C2tes8DTj+47lucdR5TQjoWqKd2scHmgnZgJcQDPMUz4VNf +nrFlt09vgEyarq8+Ys2+bwPBtxGg0KZwDzuKZqs4/p5m5vxL9axdUydqe2j5tC5K +nG1VTtPa8G5dDTd4jGvkAFBS94qbs7MHe5Sl+U/+7VMMQ4YLnqBv6xBZCA6vXBBu +9RgeRk67233dkVjpKgbO84SHH4vq7E0viu5mPXt4J3kQeOHr/9FtzjualbvIXiFs +Gi7cs4dcoTt8TB1egNJC8QBH50MnSVob+/yYQ8tgdZNkQxy96fdolGtrgWjdeVhG +uQuO+lTt8CjhCSkpzEF4YzhkDVZVUtwnvYzArsw/GEdB0/a7Wf3E9IHls8Xkvca3 +LHoVSlEceKJsiVce2kXW05Mep66x/2w2v3w4KCN73CPiYLxWDFcwSmT4Gex6EjDt +2oLHx8QlTtEIYi7yORRUsO4LXQTAVrjSMfaaebxOdKOJUoVbC7912OD65PtoRjiV +Mu3qoKJU5kiBCNfUdeiVx4LpdhyNnOWSk5uTl9p5JePp2Btl4Y65b2QvvgbfeI8r +g0UKEXPqsZusZhcxHCyFT5Y0uZV8YZA90EefA/JEACmdqlPeNMDS1KszLuAIR/ZV +Mt6ZtG0WH9ss2auBwAPKBf6t/xR9nma+ZmLP0kY03++uNomwvPtH877dzVlHTAvx +S/cFudDQG8t23C9gFhRNJ2iVe759ROQlMDub1bey7OXJNotEtYpdYpPgW8KojaYl +Dv8ayg2Vm9o4+UbhLJ89bOjPDyS31QjBgte4iV9hlbtHUm4E+KNH1lSiH93kUGQY +Zok2nG6rPRuNo1RvtB0rZmialRx+UtHxx9XaC5puUDOvxI35IVAT/EisMT1jAIpH +ShBFNI6DTNxlSiqZeDj3damW5U6SIDDphypK3+WC/BVHPU9KmvrwkSzPxmDL1ryw +bq5Fzbpr9yGLr5fv8BcCpJa+1NHcJ64ZqUNr70hZHd61qTJ8PrrGOh6sDmuE991p +nVlO/0+ImWlYqxC+arvBLdZPMxbSUNZdni9S29OrTR6EvCk+8iM3CVT+y9FpU0zZ +k0+ePG7ARx3I1cftYNDSzGbn2tMEoXszJqN540eJH6vpsRUF2iKDHrcLXn6gHAtQ +vL52ItOuhOq7IyPj9+IbQm3pud/DAxOJvWkUI3qC8Rs5LMfnRW1fRF4tQieW+r2K +hSOTyK6acUG6DUt/pcK/L6+NLjrg+86LdjgNr83RJ1ikJz3Wgu9UYFdAE6CwZIJu +9rReZmyPAKj0EH/ycPF0qZtp+VCMicme6LFl34VG7hRts1ZtnpDWqQ6aQhnAq4EG +eFz6t7p/+clQr+ADCjD5BBbhjMv+Kn4ySwdbmTWfdJb0U+zSorLZZlJF55E4simh +T3yjzjiFIMb858+wrbDYi4yKnkEeYntivYSLXqZffvik6hHBMiq7kUMme5gJFRUf +dM/s0e7gQBVR6cpLsnalO2L31TEVYKYq6WERxdBDeYk0AxrfQryqBRlCEhKgNfbR +yLtRGQU9+/X4EvvNJJ8qGloBzhPR2urWExO/DoW8aaxSWLMNJ5YiknLm7aN9vWMa +k6gKN7SFemG5IPoA+aHtL46eJJyR77UNxnipTMrccLyxV9cHdYCUPtKMArWRKvwU +0AjyvIUHgelShusC0ttYpGwPGaOTsJ+yC4hMU9gftnK3Y4QcHu7q5/Z1EN2a2fRK +w+lDHrYgvSKk5bHw3C3BEV/HRG89sThhYfIOFcCdtW3EWMZtCjoE/PZyaDHjvC56 +wZQC2MON6gvvk5In1v6TI7aoqloutrOBnEbbr07beBye38KW9MVcyuu2mdvbrsaU +btzVrE3KD5LOhOvkE6NJqahRWnXsedIxrtACYA9XdZfFeGJfz1tDFZuJfmvmC23d +0OqUsSR8TWb8jotNIU3Qm9U9XFNfnoonfOtze1HZyOKQCqWXO6WmbX4Aqz0UEcDT +LPzsb/FuKNIezJuUTt3mCitDOiQJa8wOhhcWnCDfDrXwm9DVMY0Mw8Kddg5pXhU4 +BPT0sPMa7OlEhAyKFqDaC7IM2XHFj+JGy4COMQtvKH6LQkNB6To9YF1PfZsXwqi3 +wkOlF6hopJOlDU76D4Iy8NyHqqfDY4ney6bZde60wt/KdVtaCVSnzXRFsToTKepe +UZ5BOLlz5aIsuJM8lI1+gGZkRBGRj+3IRXfGeIfQ6C8XyEs5jqV9BFNl9z7wOGXN +J5C+Zq+cNzhwHp7m63Yq2ytN5JunI13LuOdrG0l7EVW3a0TwcLXE3+Fq2AU9NmvY +DZbbMIziZ+wz+pMC/v4BwqShe4kYvosEzSOpDfbf1sLvbviBXe1OqHG6ZOwCANst +YHUsQlURFFd8HIy/rWBiM4mv895pQ93VUUWnYf9VMw09cDaLQ5V+6enp7aGrAHLI +jVYii7Mwsqwi8ofioW2jj9HuANh/dv6bvZA6rAbbgiHViiXIBrqAZ0Qx7tstOGW0 +W07DC9AoFqGKXM6wWBH2/roHH9KixHhlULTR1lRAUPun3FtKcorjJT2otrcS0P9/ +VRbZJ1KZR/z2869RbWX51vW116ZDYAg7DAnzDiSdAQF+dDpI9yXQ1Qz5PxyeGrYA +S9UGd5AZQ4Z2eLulLgj0Lp5LUR7N7YBu5tS2J+nePJk/32teGdowxaFb+ycjwllP +S4NeP8XYATQygxogte9l9iV+sHeeH3kbwY3hiXgaboNB/K7pnPh4f6kKA5TMeZ6b +67WGnA00Pc9t5JrFJfpj8sWfrlJbrR3pWoJu0H9MRbnYwRHMTXVHtOeAmBCkbuuF +0EJ3m3k25ruS4UEArp6HU7Fpm7yukhg9mDEqJ2s4nHX9W4WYrKG47Lq+8JmRuVai +Smlsdz3enuMlq4bwoJrvV+UQM7aVY3jzI7aK+2RxxWHERGmBJM1rMp0d9RPvWHwe +bZ87hzpQOfyzf+BrDn+MTvbwDsCFwibCjIuGpryTtWdXSkpXnd/BTCnDcsGZWuy6 +V7jHvPmjK4Cki2hIHBZT5fENzpAlhS1hxulpYnLj97rBoP8l1Iqs3mYw0JGAicRq +mnjv2FriCnEgxIphpXe38AT3U0Xx2zolDkjN2uQaF3UfzcWEalaApxicMKebXRNl +Q/tDa2LKWdiB9H6YqFEhhteej3ZzJqYFmkNtDL/BfHTT4k0ll6IveC/Y4jlT/lYl +AMKi1/w24+lPXWPW8j8m/mGhXfUtZN+XZOPzlCfDifMqQM8b9cFaCZo5/DYpCE3e +3soAtTlPeG4mIcsQZrUm6vp5Rk6Gyn/u1R+LR+5MiqB5SSiLcY4QSw0aGq3iP8S9 +CuAprbxsjMIFjfnhE2hYMIvkAzTHi/nEtmTswWeeuY1eCCoP+OZvGHdY3GywGGG+ +Rf6TTmFbvQjHAPJSk4MgjXVJ+9Fmij7kJa+hsXLq19fEHPdN3oD3FA3wBLi/1Ln5 +5707OW57H8FZ1lK8aKMFT9cfSEng2VAM6AAk+pKmWq5leACWh4CwPuy5VNOCQL5q +Q3Q7J2cEz0vSHrG/yZIcvH7Qfz+4TKrlCnLKD4OxWL+PYSFo9wu7aOw+JslVBMa3 +PSFZ32YRTUHc640KvDvn67g0sURA3UDeiRuM0UsICxitd9pfAsPJFavbeNtsG+5k +4CAEnJ4v40ZlAiriuDVCPc8jeaf30kYdwBtV1wFYqDWMKrYLM7d51PiVVGYyQxKf +adE/MwOIOJWjL2IG3tyY++jwUiElLAN/WW6dIiO6PtmbGHOTtKPicSVXsZ9nyfR0 +8eCLySc2N7Orzptd36YTP6Nwq/RvxsZCQXU9gjSYyVjD/2vu2i6rTHa7fD75+i4M +eDH4k5csQ7Sfd53ryouiHeBdHtEHbavD/ZMjm7h7ocgvgoSwISnORf7rYFsLDvbm +1+XoKYMGDZTFKfyOAyA2fzrj4fLkzvW/jTysYm69Yog6qPanGotfX681Ww7VTVI1 +I2BvdqiURa1qMAQ6/5iWDCx0VpvS3hCfzBs1VpisJxGHSt6XO1Rki4koq5pcsHEG +kQ/y2N0b5gTnjnN0D4CKJ+npX0uXpjs7apDBHNwsEZtKDSeSYWdqCGxOsZoHnCsA +lvoj/EoD6U86hh5mDfSMtiin6mBoIT0vg9omsSsyBXkl9hIB4SvnaUNZlS8gqQvn +ONaSw+V7j9UqnWI+DbTt4SRQT8kuiY60ZiRFzHtym6WchYkDUTM0aYVkxl2SKyeC +2PsBADMjYNbYl7GUEOe+pjNMSwWBIqErLl95ZTzEwjMxsg8pHeanSAo0B657CLjq +yxFe4kmSFzaZ34ebaXMm4F+2Eimxt5AOgaCbxyjG8NkfaLSZCK6tWamNzI2Nt7d3 +7OT7D03KQ5c3fKtQGQk11s7HOHEScZVZuoCNKKrChR/hl2xJFWoBCXRhTR2xXmQo +DwXbkUz5KR6fzRYCgzH0f6qKM8BwA7/N9hEK9+XxtyrUGrxLctPQv6iCHFByAdTL +hsGNcUBZZD157uCiBj73k9eQEgR3mCWRMZSTWU44q8om/r62TDJ1GjXmEuf5ybRW +TPjv5FZp5ZFnx9A7wSE9aifYg4GGhE0FI6TynyK0TCjHwTWW26mVYPwg/klsYe9t +rh3+Py4XU8uN5ACD9daSTNNTbBN8AriRUPrbTxhgGXWmUqGeoJ0Pebtj0tin5WGT +NvU4jpjJrigtxHWKZzPK7sKJK7BMtS1bokM+Rt1Z08pEK5M8pZjvOPTxlQq4L00Y +RTVl4OvlmNdcX4pwch3EQ626VfyAMjwNscxT9CoRcRTV+eAfuL7tK59dakITuYMf +RYV7NbHgFr7WlpRoM1aT0/0b5jR7pM6p/QBaEHDB59gFsN0jIA1Q6nj3DngrNZaE +Q1C5vrBxDpPpTs6BUg23PROT0fBkbvAAKt/lk9ES06hSZWezMudAA2YaYt22qVV5 +yqbyBhSgyLii5qCjnvG8Q+o0TiBZ/oTtX1gI1FDljM4skbKzBzL2DyhbMuBbx7j5 +GTjEmPQUeI7g6mQPPdvvC8kKWISsX0nGFdmr+5BUuA4891rFMo0m+T63YJQHmUUh +0hxYg4WQYxjXszRkranOYQgy7A1o8Xg8M7EBsyyeom+nc/lPE6eaR+R393OWKWDL +OdHUkrJGAgdpolFecAuHndW/rXGIfCWdvoBU4npwjz9N+2heuVY251erNjikzJG5 +zXIybYLOIjmhxtsDW+U6JekhFbMPrnZfQcA/JOw8A/EZChThnaX98R8Jg9Vqpx1g +S/5g6F3rB+OWIv7FzgxNwJ0W2EvQ2VBZVvkwLk9Upxyn47YJ0rk6mxuBTCqkhVXJ +Jhg9sXVWcke0+TvYQcT7lIQAJBmxGNUn8lqLDgduTynISiBzXMqTbN2epEDjzVLF +tyxx+rYBN5N9KAjqiT9l8IIpL2Lo59gedgU64KWJdpaeLg55OyetzlhDbWGBFk15 +EdRd++SoLD0UuHb9dYH8lORbxg84Rwn9gdFHstRSNT5ywic7y7iQHrL6dBSYwKDr +Mjf9PnhTbUcDKd/tF1fsLe5ZU1jtIDBfCgG2gQLdopeM0Euujp45ZyoHB9KdvE5n +Ow//d2VIg5YMyJFAFN7dKVKrDO/2xWcXBQCSFPjxJe3vQ+y34f1Jvz/q2gj/od45 +s3k7cV3GmXt4Rbzeqch0VAtLSkZ0e9NggDb9d/KQHlmtN1Nx1YKdvC4Bvoqo3h1c +DzgtLhMyC5vemhGnTAvGcxA46tFjSZBC0umJrnagPxuLNtUPqSFs4MX2HsdyHtDc +kLege0aPHf1BZXGvfilNaeLPWJx0/JPI5mvDB9Y/abY0EtPKs22LAoXuTawmPbky +O5XZtetolliZPNsx+8IqbjNvgn2oDJJ9qBBQ033fFok0POAxVC8MaUxej64fxFYd +i8zXmNJmpK5npBtPxkM37QlJD9AEtGGscFRfsQsm3VmdcE7VTANoWWM8QnewC3iz +44jZHf0t+bPsuieN6p/NL3hbeRKZ7XrQ0ajHBHWv76dpL5dxNsEZ57UY/9eTooeN +/E/uTGOFhhVm//SMXgscCHxtjf4fsF46I3M9RRXhYeNSZY5OxSgwqYdsv5rdYoP8 +ebu0Z4TJr3LsNVVZqdbpB83BmwwVXi2kUr20qB/1/IfxQDF6+JABN635e7jj2adj +6Vk1XnjYXBDUTQfqtpf8GUU7P8NqpYnG9Gk+U61Vq5JJKdZEZVV5d0DVaG1/sG3X +erSwQkkjuHto1L1Q7uvUhxYWsfvmx1CQ9q9nae+IfD/VYK9/nbcEOTgNWc2g33+c +Ej7UlOs23qisK+wPKiSY25zvt0+733YppBXmgjuQCuUgDL0Q4hK//+842xZY56bQ +OFHtOzU5xkwx+c2squqNs3HB2EXJDeJIPUjuqzJCM58cOv5GtHvhKafa7l/5wOCM +eJ86vu9bD4EvHiI7aWHw3Luwp5MCJaBtdAHdF3WOH3l6KSCfo7lU79yijNF+7nqo +ro9oN6zkWAulQ+UkAa52vjL1CtQsKa3kZ6aNOuFq2M4U3lWl/kGu+cwwrxEMLsFt +HviNcooX9Bd8GgMUIiUl0Mqae8pT60q+KHQI9DbC6Xcnk/1r0PBnn1hPtufA4Hi0 +tZpw+fgN9JxFe8O2OOnSImm0I5sq26j2OYWfdWT7o2mWi0HAce1YowCC/P4dyclW +zK7W54cLmNCrjpFc8VZIjxSVXxNEKcpVNrAAeUeP+w0kRvmn16YALcJRe+pVNfGL +M4nv7RSgrtnbCsb+mK51Vg4hW1PpkX3uvoLlJUHmBtlGRyPXiECppRnlEbuRWGxd +VYUcG81iAnZifnIMzJXrvQDvRgN1zIRC2KlzRKgBPX7nYL7i0nPevYkcGaiB4D/8 +ANdb59kTCT7BUlaYxJkm845k0CqhTjLAT+Hs8Uy6O6AghDHYNyFm7lWNB/a7NmGy +tLEV+K09H2lH98Jxn81xiDp9rx7JTzzOnTwJQamyipJZdHiHf3OaAoizt0gZITUf +5UUCJAR+RIAWx7dOkE9yPwA4PZ7W7pXGeslP2szGTnDk3FBRuzKewVWdpHkNS3s8 +sF/+OEs73dTsnmi7auLk6WgK0uJdMrZS1IL99Y5TsT8lk4VhEgtTXaXPDPDrHUGf +ifswzJeCdfoUUMbXLHpoNuzXyOStdKmUhfkcdpjGvc7KScNN2rGZw/j/G3fa7vel +CATHj0lO1FKSpRfaHzBD9bqUn9Sp4lRJ6YlWF6KPXGqkFj1r/J7GB2FI5ctLZUbR +rXeRh5kWZZvLshsZt/GMFJPr/TZASvLajBM1T9surQULTAjkwyyFRntkWl7WoAAK +GhQJq+MbmEggpqPyFRVZGausniYY3u5kyiZa15jj8Ga4tTXP77Yqakv0ePdLgxbx +XRnrl3FMzU4d+qJB+oRFg0+DF3S8f7IdWg0djTNDoxVmGDt9Aiowr2woFpld5J+R +HYjYXnqFZY5AA/vdREW1Iq0YjoiHBEgz2vtHcUs8zL3xYH159CR5QDyKcLCohV04 +9APC0U2rWLLIjsR0NNbrrC2BTXtsOGmo3l7FlUmOzpQBbMVUQPbC8OITpeprtKqe ++vgELZ5krH2cyOY4qwjo4XnMBBZX4seiJHxmaieMSS87PYyMAtsQXWpZINnEZfgo +b3X/qL/G4yo2dexZXd2WU040Mo1woKBGyIz02+MT63ehFQOiRtmz12BTkvNqmZpT +XuSVTTKTt11NSlUTsfthNzPLNGddTq2Z14z9OCCzIstrkJKWISPAKhdvNEG+tEB3 +IkUFc1cgoATGsra5aYYi28U+F2Bdz+OiyID/nRGZMOpBpBjPrHrqU45U6oSXTtEe +3L2AoC4MPuh9D1+ElFrWE0SRZG2HZr5XdGZqG1YPwZnYnCMWQYUJjxlBfk37dZgt +r5ExI1pGNSH9//Y/MGfi0YdGasyURchybzAFBqBPQncYoJJd59EuuFvDKe61vqnz +UwmT6hBjVltw3wo5ZO/zy2s7IrMTq0ZNJYlNgN8B8ZA1j7HuSq4/bthQuhm8gEZS +cEBEpVMB8POKzvB68i4w1+1P2TLDbdJsTG3HWvqKBmmgGhmAHGLDymLKh8UTu5ke +X3aA+skwxfifnzgVnv+xKdc9DEWimIE1fNU4LVR/4iiMSYDpQeQEEaHY/JbPxt9o +5ACEZkytoNFw9QqC2NrKI3kQ2q/kz2JsVFR/sPuBBCN5+JI6121bUy1O95B1JWjr +dbt6UQMAbXHqycQ86oOXPaqUJzqPRAcEGaK68OlhfxqUo1bgtLoiPkHNxAPQqKLi +W2Olki0g7Z9zVzaR5/cublzSgvh7JWA622Fj6WP5h9hj31H2rp+mkLwBBxDIWW6V +AUnm+fOWA/rYPabXn7kvoEj3h+tt4f6whrN3b+rLNBAgZN+YX+cGTJPTbfEo5RWv +DQvhAYU1uIOTF5KDtDjR/jOrRqV+eXmsgkhq5E4J93wKRY2XuMjSZPbLB0GeycY3 +bLh66SPgSabSAkWmBAGAZN1F7dY4MO9dw1pD0S6p9gGzYeoUpExc9r7mMDan26qm +LbNSMaUY0hoSQ961AiGdxsFbVyiBmdOBLBgcPnv6XknWUz0fKOs9wILctT0BX2k/ +kZf/9Rf1daeB/KsyaCiPYOPkX02a61xXAshEi42jlyaSAsul/47oYYso7HVVoqmw +mKmOBdbMjiJk40oj6GzQWrfPsnssygo9rIEMMRP2452xqWYBfEpaxxNlswnT/K/a +EUEnCk3Jhrifsq+nNy+5QfgAA8SY4uCoKAs29r71o4fEdsbemsnHMFcPvxx4SW7y +uTRODq+RN6LasiF4kuEaoVY3dpY2GZ66nLzfw4Qwil40dyiTymb//VVEVGmk05xo +Uk8NgeWE79/gaC/o8Qa/qu1KcTuCpe1hQoLWt2ynxTNqFr877AF8+r0teqM6dQKU +sMnZJyhRDWAK8UodSoddJO5EXv/lVPyA488s0BhIYieS/RsRjTg2PDCM3kFpWRiY +6Sgu3ZFqj8duLmBMTqJzlToqEpG7fEWwM7Fny6qnum/kpbgTTO/chlDhxrPC2zlm +JTIkg9TGQu9O0qUTDRoUnPzaeJDdeqDaoZyZBAw4k2BRxbFUaZo3tA7UQhfNuo2b +f3cV5sXXuzNfnp0ze9jMkbd/QlqcBoNB7hzLkHwhfYHIftcRCkBpb9QKJpZhEEdl +QT3oZFQTdOjruzXBgyP67mEfeyuQUgFkSn0w8KrtG9NRL6MbTGZPeNQQHQ+4jfCV +5+t9kr6D2ghD35b31kEGYayjMyb79CwVAlWly2D/RkLydSbvGuJ7/S2tUe+wbAA8 +48ZzwvsoEYAShvffELPQyQWUrej1Fbv9bApqnYdWhOwixsolF7sOQoW1SO/EzBdt +dbXRDBkjVAm5GvXvON5lPWYvSkdmaYfIPAQXRfuarloErf7TIklFTVEmKJovkiOg +mxBvBVgrAJZMATPlMz1Xdvf5CwIfPFm/PboaWS1Q7/mzlUSjBSIdPJQVZQ7S2BQw +qLGw9gKVLlwEiokuNvSL6AXYDlxd6nCSyOM+nb1QHyfmt7dMrFWor67PDTC0lwjU +9zcMAWrVQOFDeKWV3aa5LOzOvZBWml74NUoj3NLyWEarA0phv3WMltXyYBjNGB3f +TB1SgPqc6sfTPeiI9a1B4cve2J8zRA3KPoKO3KaXIrwOmDpgsC+2TJ2eEpmL032d +Yg6UJzltMqJ51MjVLlXXbr75yiwtL5CZ4o9OPMRCOdB4JERkq6rNpCcNHg6Qrmae +WxLl6ObOV53td0Axcqu7/1d/ywnObMzZwQueTEcDK+IoWkvyCFspoGQGJSTdrCln +9U/fwZ1Aw573Y8yV23mCoVz+46CizX1R0tt8RsiUUuJRedZuXpdgmloXHSwHqVir +4TeoeKbJ5TabI9wAUk5DudmB5BBA5WQUXbk863Vmp6ZrYuTLfrMjZIX9wugW7G99 +XjupmycimgGdDcwkPXsuhcn+y+kypAeSBT8BmORPoMB3GBQcBFCpksISgnzfj9Df +f88VaFEwPw6WYPsr5zD3qmYV2Wcsa1+AXMyVWEud3OibijB/ydovxfhoylxzubgq +c5dWawXZrm5RAj6OLUtonq8ExeCxZUVesAT41fPbsmxPMODfaNW5FbLVC3kqoKSR +/vBOG3e/0w29HIfCe3INg/hQVqRtqNawZuPB3U4eg6mkDZO0y9woSZUx+4YHiEnU +NTXJ5dCxVSwAc1bY/Ip6OLqp0SL7pbJLVLOZcdpgE5tqhkRt2TK3t44YBFUW+niA ++7vUO6hk9FiP9bQI/e7mVqrPotPqBtZ/BYUCVLnHL1JkdNsfhSH93PbRBOL30thr +a/CDhbsHwqYjqkrPHUZbNL6xs3s1Ebn/iXs+MoUC0UijkUhThusSGW3zplPE0G54 +0jWIUjvdB/4anXrEkP0+JFchB+2p29bDA6M6GqPIVL5rQWDi/hZj7Jo0GIXXkCmh +pvHuQ5Figaz8huMCbW3V2iIeCWQtEZCIlkqcyGu/srkMp8Qy6LofUqNL4sudqhPx +f4uyi9jp8NVnv5ItQ16FzQScH1btWx693lWnmb0+Z2LTNY3edWuP30Cn2zr10hQO +93mjE8j8xiqRmhLimsfa03ja3y1M5RFuYdaN/LBTd4fTOYAzlN0jlO+qU0fuEZpk +uQWrVWtrciib0QKfC1g20lTslFmwF9dosu8yjarIqZXr+RJVRJ+dXzaC9RXCMNZb +65UcvJNvzjdQOIPUdQcFIuSQwWUnMe5P8kikQsxEZuT+BErj9Pt17T+HPstvcsd4 +mLxzNtdOSZuENCu1k9eImFqEVVl2odtXcLBE6f8fS1rDtjNUupb+m5h+WR63QHid +eDln4z8ShnayiKhW6xp0jj2dUvWnOyhQwZWRP8m/EmfeFO7gYiIw1SxDD/ZqH364 +PzVEZruTbQ4jUKjpfHxf9WBgIVrEYTPTBjPjxaZbhfA= +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +gQ+VauIuH+g40FNOpVzoPSXPaSSXzZWh6rE+e4zt/Higof5lTVqndEO2y+vyS/HT +Uz3/xsHmLa5/hfJOzrQ2WAbWJcFOc0pzmbDqYnUgEw1W4IUS1qcjifpXTLdxvwfy +rSWd00QRecQN7v+pyLFb6xf5TELzzsB2PAr6/xlRVs03sGcC8jpFMP1gppLRrh+C +xnDjMIBVdGmu01tJ1gcEY/913addbws7HLgMcMDLft0U/4zTbjE/rrDoC7+eO+3k +z9ZPUNkRvEPxurfsVZfIuglJuZJSqyaB+Khmc5Q1nMDb9IswcttQUM3RtjEksR13 +Y4OcKLh/ejWsVorB6JLJeA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1312 ) +`pragma protect data_block +fo0JdXfIQsWgrENhFGo0RRW9s/IV4eGBK5upzSxFjRkxTj+wCit1QKkd15jJgDu4 +P06Rnw+P2/Cu/tkXRjH7RGfSCa1EZ08cwLiSykEmyb+qQo8wTkOBh8KIag5m0P1t +XTuNeK4lZP50EUwL/4wSSMPuRtdpIAF+0PAXjdoge2gwhduxtVQZpgPO12dwk0Wo +Qyfuxrm/7iyjiETt18QCBk/PXC9JLX6a9hmtr8ujb+7IKQJFj1S7F9WxCZ1yamDs +e1D+l34aYZ5r3sBbAysWrg65oN3fAAd6bhptfeU2+BDBA8oKIcTClBK2f3pBUPul +8YV5xUU0+FGat/Rjkm2ZmKKpm9JD+w7ufesbJ2fqRCCex08yynx+EuV6lNupQQk3 +UbxIK2+04eVmLtY7V87103cxyVnLFXqAQY3XaG0AWBpO2Ew1NwH6CU4yFpyUAC84 +Bjztc1mHKONeueopzONq61tRDqarI0ex6IhDy04D9/zAOhMyBrEHzeR0UozXtK6Y +TB/qqFBgJmagIMQWcL03s2FYWQgGUU3PRQ4JiB57ubJG6H64M9UJUMXI7VXW245F +S0oLuBSWchTwY4/6zvioNieoCZgdkxOTUqHNuV4Zf7Epcgh3IQIZRzjBSpah3skn +kQwLdkHYbh3EzBAN0L4lF8u4LE/8SqwLPpsl91D8Qck2jzgNTYnbsG+t2tsum6n8 +wYvw9H2G6SCXAimDrg2Qy66lpdDA8XQf+1Pu8sYKlEd3GH9lQyGX+l4gx3OLuOtR +fAlYbOhHnFRDXMNE9ZG/I8VKDFToJD1/SjoKUnrz4TdMcQZn3Asrj6LyXsw5CHgd +zhf60BREHK5nXIJRGkqTlV0OyCbaEe0yTgmpWapYbnUcpX4UNu07ijUdSbUBReil +f2PULQwchd1Nh+nj49FyRm0SU4twHeYIMoSC2sMtPiJkuqAZPugzpBpKZUPnKzDd +VmHxPV5Fl4haVbGLfQj4rfl6Mqpqk2DLOiPmwiXnf7CTAjpnwNQ07KsBw6SKxLAe +YS+1RZFe1JQTA73Dv+hAjOEby2uC1tz9V61abAakI4omdhXK1WBGS7AW7VIkOhsa +U2d43C1vqygKdJzTQVB3SVqswMzruIiClRGEypfl8F1L7BIegRA7y6KJYY2lQ69u +7eDX8XmDYmXDiWgXqtWRALbhHrDi8EwOCp5Tts6KK1q+HZNB6UjiGUrGZ2/EhU4H +rNhfbS8YD9wTQtEs/QCi40wIeLIYjIf429BBIRU8k3na6ZwzGLdfxJnqsRLJ6E7X +aCiJk8iag4Wfv0HsAb9J8vDUKzzLHS5OYlHmEss6CTswBAYs7u8/UF9rlfvXy8Mb +z5tfh7xCXqOQpY1gF85w0agvdFKLhhUzfB2Y/XiH+P9zw8608Q4B2irkUuj0fbhU +/VGCOg52ghhNNkaio6JDtzCj/4nMf3QJwdYnJNTiSWLmN/D4rgU8FE7RObm2foEA +5qemSiCt9nYnRGtaRQ0jFh1zieourorN3TI49Lfh/b++M/Hq8OUZh7Uxs5ni4scB +RqEGxATE+29gCCCJ1S3HVi7fcit9xh2mupZnT+m3qHM+Jt01sv59AUJ/UFx/cNYz +qo1oB/NkzOstxVDMlcp8bOO+elF1X4n4wKeC0g/eMM8C+ffQiVT7Rqh2mYLgXQA7 +BhBS+E0RB6UhkxYPnRFEgtk0VLL54VPEVDTINYlLs+L3ZsWwYJs39Gen6vvvepYy +bujDTnnouQqtvD9ok3pkbA== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +TpRHXtmr81JyoWaAtQOsoLu44jF5UvFDPdO5/CllOd3kdY7PwU2fkKx7bS6RlGe6 +282Wvc58pPBGh6uImNRfZkaAKTaspN+giuR1GHAo4nfIKi92dgY2DTW5JbEU67ml +1IGNiK4su606fm7n90PZ69MZadoZPNpUxZxzYbSs+I39eZWsgU+rtoUE2d35qjdW +UyorSD+O2F5Wv51CWlcWJyscNK886BFGFi72CtEY8IdYcolZ7hcONOhQT5jbhGWK +UFFTqjnMO6iVrEodujVvUgcUtFQSTl5/oHSkmacP7CSADA82+06uIHf+rByqHGTp +JNgtSAVN844IRP39n4T5EA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1200 ) +`pragma protect data_block +dW2N/rFxim9wkWiMqoV2KfFOb7ryaosiEjsKQ5d9XAY99bfh9dHXfxBwbIc/m/4e +C1jjMt+51lGF8ncrYuentPA6MwNEfk27Jwvqv9/Trdq+kOdiWuYmhbZxfJC2L3WJ +BzjhoC/o2ZNSFpgmDKLxln0/pf6iM8sUIldzujq1RDEv/fZvcQ9IXZ0c0cgbXEWf +SfOaD5E2qBGsljqkzqzIKjaiTPnGPsKJ6cZ41jLGbcm+AcbSk6th9Vdeim0hCA9t +HjX+E+Tq77j/ivdd5OuzAehdPAg3IiMJTQxdTNsI3km5GzvomnmxK+pG8L9aCaAh +o+hCsSXZD2QyVCRFZjVT4s0ltvRto5PgSDzzqm1N69eUDE/spFnroMx1TQCLbjBT +zS0w4mCeLkzFlxc0DJduqQlnRMlA8AnBFujD/Q2OAdVMSHQC7YscXbPzF31GPlqx +Eg2t/VyotaMLOGG0wG7ax43UokgdGbSuphzh14sCh3ZSbPueJQLw2MQwK5M2gcvg +/OCrpP6ZQDt10hFz8i/uLrgNIWA93ZzqujdUnYXBBCwUzRJEyHSLnlXX6Ko3rzE5 +ct8FuQPGV8vF+t6COL2nQ0qaq+23R5E5PuFtEMyRrDT+p8iXZasw8RECO0NyVnEE +YuX0T1i6imJS88oOkLq+ywGLgMFC+4O26DIlpPh4+UJ/fnt/pVOADhugk3UeF+QA +ZDR1sgxihCZe9rP7QzVpjm2tDiaPt+fklsKWPprWH2eAiuNaia9mSSHNYGF2x2lD +9h3FKeV/2LSUG5mOvvl3sgKhV2fY0MuldurIH+utuZSPbknY3sebf3BKCntClVOm +6zvNgcnFtvD2+A79A8sltui4gm5GYPS2b0YDfju51vT0iTsCH30p3LWNEG/zEtf2 +48bHsr15Z/CgHdw169NsY8B3V8RHxaJP+T6zbPLBjVmRFbuTftozxf/dv+m7Rgl2 +3kmwmDxauFLyklSGjQ352H678ASYS37eMG1wvn3akQjYEAsrQTdi1sxmk6SACmSb +Ko7v8gOZpn886AO3O4V3iIggxtfGIfRMtOXcoEIX6dRl5GdFkcASHigHwoV56yRO +tlfJEHrrKLKbmqhjLMjDz5jTptQZfwCjZGzki/PYImxPv0ay8+PTa/qXEaJEMsWZ +vWEGZGSO9zphfmPXEJI+qF22X0dYlKGn/U8rzBEsdcxIXyGWQwBJvbo+GhnPURiQ +i1MJHwfOEDztC3XemmsQeaMuSDWZFrnOKXuYkOBj7tD8ir7vJOor8isvwQUz9LGK +g5Vx+0HdaBgE32QEZ/NjYA1V6bM0iUHz9e9qzEVqN/kRww8HFXA6SnpD5lz6hyxy +jFVRtphwYQWmSzwLvFWa2AYQuI4xjU7tJKOCZRqxjD4hiIkjDK6/K/01Gk5QL/3K +12xoSmqSIZRHwxFGBoHiuBmy+wBhSdqqIOdJ/OsoBT+1OwzQ24l0CRjfAk+zBdVi +7A89GoA5JGSeX8OCJopZvuJ/kEWBUL+l+AU3S9Z4l0uVYybFXE7WXuTNCWRjCQFQ +DmofPA/+XPmyr1MT/3DpFQgnMN00C/jJ1eRmmSntrjCcYaPS0vX117igGa1YWfcD +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +TBCX5/gAT5S6xdVBuY05hYDsXmHLnm/0Yl4d4ayUlKrDe3IUWB3JcRtZJEwtIwhQ +wqO6qIYs21XvVt74eCxdt1SZXHRXXJiT196fD9q5vFrJxAQqeTDvH51bmshhKW+i +DwXpMTwZlLgBsT2BEP5C0RiiICy9chJTycHB7vHEh6lTXT6S/2H7bweTMlFCh6s6 +n5aHgBbfjk9BYIUSTuEvOxw9Yki0T44zjqGmjZ3qxkhk5Rae8iPLqCnjRTjNfqOE +zQtaoVQW+8NbATVUmZC4WlgxF/J03hq0TLeqLYfcuWR0uH9vLAWsUzHqlGMZvUSV +23zwmB8p0BqUeaj1cllyzw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1984 ) +`pragma protect data_block +2OvJlNYOCu/okutbEvWbuQI4X9C4wmVA84hW5XRuqc+R7lDXEYZ89g58fT3Wyd8M +ecpTY/f/5J++NaepFO9rZ71cRzxgXD7ZQypxrBwT8eXz6kwhomKLL8xgQuGMrD2h +002LEC5h770bZFbr2QDl94Kd8oWweGDIcwbbPgGtsgfsrwnZq107rvdgRLsvDJ6H +A9T68XpAsV83OJOA8hk5S1ytXOtMoD1vxUA9NgZ2d9BBiwxnfNC6r2DYa/TpgT+F +8Dlnu2u3Ch2T50E1FvIsU2NsOkKdsN8k6Nmhr7J+mWrK8q1RSElNbQt02yIshAzD +fz1m7maxuzNvKiofs7xTJYH5Zl3jsRgP4i3jUPcFIYQTdju0XGFuzz4tT0y3o98B +wJPQRdZzLdAIRwwOeqCGe94DNj6v4B0lCOW+L2I2xO/Zd85RIWk0KQ11TMBxIioX +lElgvMwoYdOobLmpseg4vchu9jvsSwd1ET14HpSefqoM8cHFSvGA3j0KpwHUHD6N +cAg2z8pkpvWyZBxPOnKrjjHml3gwE3q+X2mtD1ayi41L4xn6E8czI/znMUiRwwcz +u/UG8I65XcONtBswjX1cTAad9X9cP37rq7ly/mnCVaQ1fwdx50rBY6tOiF0jiVR5 +JjSBl4FkBYJu7kHqA7DcluE9ATZ1+D+BIfESxs4o+MIGiPbk2VMeafwTD7GkJFOt +pp85p5WDA/qQLIA+aQsaHfBRLInMjsajsBU1Nnr1Z2FuT4dNgRDU1JiEJoiGBh4S +RZzlhgVKqLQdDiC5KHU60BMuW3u1CxkP6BLofYO1/DTsIOzKRlb9s3+Bx2RBLO+X +LpI1kmPdmyjjLOe9xPxUuWAlk4Ona2bF7SOrCRKslzRwj5WK3kdfynnrqi6fyg/g +6RtRb5T19kv8xkX8Q0Nu2f6aIj9NFg8R8LJhXh6X45cptFvZzqgrDrKouB2qeqzv +r/ARvwCCrLhqU1Rwol3o14E8rmlZcjNTDxMVbtGHIC6f+FQD8Ge6dA7TLtOmbzhg +ADyiBfAGChDV8d6/1Hzt1ZCbp6C5hSA43mtpTQYEjZcGds4olsLWRMFlvn6SaE8U +/yc4f8I5aqNLijlkaO5yVtVndDXvrhyJK63yxQ2hv4wjwsq4K2PDQ4XYvUcmKPD/ +XlPlsS9Ze38WOmF18BNsWhFg/X1ZEsnJQZqQFknQ9z/lHiYTcq+HtWHD6JfZzOaM +E3UA8T88Db5hkBxdi+VdfTfF/tcJB9TVv94cA8SuyNnP6Q6AMPtj4AcaMmUbLwpN +6fOz+eRjs375gUjeGtSoPhbJZ6VvJjLK6xs1mDGS9ROACnxpeDCou3/Z35w98hvB ++vycfefBU/3Oz/FibzGZfGGRZxR88DoezSovO8xS1UTztbTV/E3Hf50BgcR927BL +NJGAapWYDd8JtV0BHG5wpaes7/XmU1ypZarztFE+5fUtgzp4AKZ9d8fLPqu7uHyy +VFSlknUG3lKAvV+aTv5kwTm6T24a0lpxxYWzaadSBxuqeJtU7FNijzCia9l+KD/j +MuWIX01bTZapbrnUlFm4fAAgbW5f3nA4jSdhRz4mKzYdZ4aMWDM8hBS+zHKdAxt+ +r3IOTmKOM53qQd6/AzPhoA0A+KC7CNCPEgYxWjHD9LvdybgmZ3XenDSbtLwQbD6Q +UwWAn1xKUS+VTfDL9VkVXP1CneqLQxZtc1Sc/vBPwSJ6+7jAYG5QfCsFKpYk6KVg +WWBjX/iaBk51jQZ/ISopM3fO5XEr5/3lYtazRsrg0f+S3e4Zzo8nxEOq9P5xVhSQ +O7JVUzPKxB+mq8b8+Trp0jpdlwATuoCmknWv7M7xGQxIxgYlBegfgpZNrb4ocJt1 +C2A5oMK874OASkTuFy/CZtTCSKDyyC2WSUJy/ybgFlZWnTyWBNaSIgYpaI2Gq/5N +W2sAGdn2IzwgLXJcE2TeXPkUP8I6D0EvyGS8UJ8WVt4jXlr/F3VEInfxr2Y6siXk +AHHFHgrTgDIGLtO8E808PqkxvLBmGkuPh75G6ryBOPonCZ0aT1e/GX3dbFPpEaEW +llXDZSgbk2fjRwniN+3OtnrHeVbQUlTC3iaVcpJd1hL8XMqXbPIDInH7Hno0Rp0/ +Voc9LaQvrTj/kEwf26rJMPkHP3A/gue3fawMlgP2mdiTeVrBYqtURRsKaMlxgKT3 +3O7Gyd/yxwB05GETZ6zA/3Z0q4ztIi5TZ5m+C2wW+NIXwkcYJdqHOodrO1fkRlTs +npvFlNq1Br3v3gImbnvFaouFkT+542lb5sOY50i4uwrifKPntqOl0n9+dE1pyipU +QURHoCbkL2QR65H1hYcDoLRvhJAfS/oEFf4DSf8HgiZITq5pSvnYcJn76jC0mNiX +9LRJqxBuOkHcdFIbmkvDuwIN0asrQmGQCAsYOOxVA6EpX0XWcJ8dVmRyWbGVZXNq +45wAMvGDj0F6Jm7b2sQ3quJFDXDWvD7hPWp8nLqRDN+P/s9tHqK5LMXPHFdcqMn4 +hKSmCVgEtnsVfWUGyjVJ0Yvh+jxdg3vECIO38UuFBuTGroD0egvsyd7iuwT3aOmn +5YaYW0vHuHERbtLy6AkO1sVVmg18jSH32tE036uQS+LCrj+G0cg6Mf5sU2CHJZA0 +9Jse9KsUSQdI7bnqvPdYIQ== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +eiP/26NloMbfJbEe1aU/cN+AkTVidxKZaNv824TVZXkpjf5L1zEVLf4buBzXwSr1 +MiO1FaB1qgL+ZgKHLwNzc4IiIP0d7qYOaGR46jDr8/k9N2BVxXC3V0wJJ6yhDom9 +O7B9d2Lcm+b0UifdEaFcX3luTwZzXAQW83Bggnm4eVP275Vqog3REHo5wgsstEU3 +AG6o+oVDnNjZTPDPyJ4uHq9bjFFyvY3ga+lOo2iVymecnhCiRtjy3AFtvWBJW0ek +uhj8QvNYf04TXkRXdhdRfq/HDLr3M6Qa7/Xn6vGE+drFyRTL1nmH9wkjBBbD3swn +58tiwvvx3ajgMOCJeXfrXQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1104 ) +`pragma protect data_block +z83CFN/6+XAqqlsaR10y0/0TRdqihm7Mln1SErDagYzHq/tf3472iVn71ufDnRwX +XjpfuAMiYkGYL+YySToA+S247ZqaWHze8oceixrYgRvhox5tY82fxq9Fl8kghDLv +SjC2MS3eD6cYQeQLFqzD1Mn0WKOQZFVCku3VAWFB2lduR5mhayfY/Fa3R/W72ABn +Z0d6Zn4ZBsgSyb/M70GpfeksPL4x3rnLEOyMOaWSU6+bpfwlHv6gwzh9HPzLZxVy +08g2U6/uxm0PBfE3o/LncY5k29GaWHkcOHv6VhXh/m8K01MJZqFeBphDIArYoxxq +PWDxAO8AUxxtI14Tgpa2V285dFMvK+4KnQioTwi0kMw0x+o+AprykzkXPkE/VVzK +KXd3WO23uskN1uRWHMVa+YBeVjuyFSDLn3GxfHH9tkFDow1kssYW0TqHWs0aqHah +qnNS7hoeJjqPZiowmyQrmDxNCJSTzH8quhzu6sXOHqjuy3hV/M2EY8gngXNAKKsb +WbOvs5QeFheEcLGYrod/Zfv9aZk0e3y0m11vKOyZVQVGFJQzc1uQ0fLjWrpSt7yG +qya4/JgJ8aoha2vBdN7gKSQ0jQBRSMhhOkv1iunq1iT+1ZETzOdrs32w7jLu65tq +rkZk2Z9PlyyFm4XlIu3ljYIH3Z1F+BdPGXiUKHiLhEHanApDED/zljh7BDGApCKl +t1zRJJjZMckJfWQclrLgdXSejbEhZFqHfgYNQe4ywo4o/SbWaqGvPgahhDBBVxZV +rvCFFNip8ka1YAIM4x0DqYw1pSFzn0sUmEm44Jl+Eo4D5chLPEJnYyAjsKm0nIFa +We3J6DKurh1q/PmPYqN51Vno2A5tlFLR8v6SH4m4qu3V3skZsRF0vR6BGx84VdVj +bN8BlLOwDEGmTO8UZpg5knVPN5bAfvf/kXvbSbr8KPR5NBZRqz3SXFeMxZYBPfbj +GI8S5ZZZeq5AvybyDwwt8BHWypNkKlsr+UxyAt+phMEA8F/U9gAt5r50llYjO4qu +5tLeotWmT7oFHBktGytHHC+gKwtWEMsJLm7+744JbDfnMvdHRr+AQgpYts9jdNY6 +guxuay2WoNBpjmE51Kq8M1xXeO6beJN3h1JAlESUfz7eFKkE8Vkr5Jg6ccn0KUsS +ZZmNyAaAta//k2mRELcX5bJmUCCHy7lAgQBjtv7XZBfyULC/eXy3RUO/ar8/VQKj +wwOLkv6PJN1DfDlpZ+oswIslScrN1ijU4t2buGKO8zI+cQCpYuC9FBN8V8chHOZw +//0ODvW7AEl6D/OUt8ZC6gUirNCSFRQjXz5x+MOrJPH54wUb0gmtQRPSsbnbcm8g +r+J90t6Fz+FSggPmyNbgv8Z+eWprb5Z3QuqJaQlTYxXGJYLXXwcTjZP3Sf58Vd4Q +9PV9zVG1BxTwV5hFTLJrTkIFGs6wyF+96e+3TnhJKuzZ4Qgf0XJPp9crAdiNtxfx +`pragma protect end_protected + +//pragma protect end + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_define.vh b/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_define.vh new file mode 100644 index 0000000..f49727e --- /dev/null +++ b/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_define.vh @@ -0,0 +1,53 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.1.95 +// IP Version: 5.4 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam ARB_MODE = "ROUND_ROBIN_1"; +localparam S_PORTS = 2; +localparam DATA_WIDTH = 128; +localparam ADDR_WIDTH = 32; +localparam M_PORTS = 1; +localparam ID_WIDTH = 8; +localparam USER_WIDTH = 3; +localparam PROTOCOL = "AXI4"; diff --git a/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_tmpl.v b/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_tmpl.v new file mode 100644 index 0000000..7c70e62 --- /dev/null +++ b/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_tmpl.v @@ -0,0 +1,137 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.1.95 +// IP Version: 5.4 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +gAXIM_2to1_switch u_gAXIM_2to1_switch +( + .rst_n ( rst_n ), + .clk ( clk ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awlock ( s_axi_awlock ), + .s_axi_awready ( s_axi_awready ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arlock ( s_axi_arlock ), + .s_axi_arready ( s_axi_arready ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_wlast ( s_axi_wlast ), + .s_axi_wid ( s_axi_wid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_rready ( s_axi_rready ), + .s_axi_bid ( s_axi_bid ), + .s_axi_rid ( s_axi_rid ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rlast ( s_axi_rlast ), + .s_axi_wstrb ( s_axi_wstrb ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awready ( m_axi_awready ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arready ( m_axi_arready ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_bready ( m_axi_bready ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_rready ( m_axi_rready ), + .m_axi_bid ( m_axi_bid ), + .m_axi_rid ( m_axi_rid ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_rdata ( m_axi_rdata ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_wready ( m_axi_wready ), + .s_axi_wready ( s_axi_wready ), + .s_axi_awprot ( s_axi_awprot ), + .s_axi_awcache ( s_axi_awcache ), + .s_axi_awqos ( s_axi_awqos ), + .s_axi_awuser ( s_axi_awuser ), + .s_axi_arqos ( s_axi_arqos ), + .s_axi_arcache ( s_axi_arcache ), + .m_axi_awprot ( m_axi_awprot ), + .s_axi_arid ( s_axi_arid ), + .s_axi_arsize ( s_axi_arsize ), + .s_axi_arlen ( s_axi_arlen ), + .s_axi_arburst ( s_axi_arburst ), + .s_axi_arprot ( s_axi_arprot ), + .s_axi_awid ( s_axi_awid ), + .s_axi_awburst ( s_axi_awburst ), + .s_axi_awlen ( s_axi_awlen ), + .s_axi_awsize ( s_axi_awsize ), + .m_axi_awid ( m_axi_awid ), + .m_axi_awburst ( m_axi_awburst ), + .m_axi_awlen ( m_axi_awlen ), + .m_axi_awsize ( m_axi_awsize ), + .m_axi_awcache ( m_axi_awcache ), + .m_axi_awqos ( m_axi_awqos ), + .m_axi_awuser ( m_axi_awuser ), + .m_axi_arprot ( m_axi_arprot ), + .m_axi_arburst ( m_axi_arburst ), + .m_axi_arlen ( m_axi_arlen ), + .m_axi_arsize ( m_axi_arsize ), + .m_axi_arcache ( m_axi_arcache ), + .m_axi_arqos ( m_axi_arqos ), + .m_axi_aruser ( m_axi_aruser ), + .m_axi_awregion ( m_axi_awregion ), + .m_axi_arregion ( m_axi_arregion ), + .m_axi_arid ( m_axi_arid ), + .m_axi_wuser ( m_axi_wuser ), + .m_axi_ruser ( m_axi_ruser ), + .m_axi_buser ( m_axi_buser ), + .s_axi_aruser ( s_axi_aruser ), + .s_axi_wuser ( s_axi_wuser ), + .s_axi_buser ( s_axi_buser ), + .s_axi_ruser ( s_axi_ruser ) +); diff --git a/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_tmpl.vhd b/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_tmpl.vhd new file mode 100644 index 0000000..9adec60 --- /dev/null +++ b/fpga/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_tmpl.vhd @@ -0,0 +1,229 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +component gAXIM_2to1_switch is +port ( + rst_n : in std_logic; + clk : in std_logic; + s_axi_awvalid : in std_logic_vector(1 downto 0); + s_axi_awaddr : in std_logic_vector(63 downto 0); + s_axi_awlock : in std_logic_vector(3 downto 0); + s_axi_awready : out std_logic_vector(1 downto 0); + s_axi_arvalid : in std_logic_vector(1 downto 0); + s_axi_araddr : in std_logic_vector(63 downto 0); + s_axi_arlock : in std_logic_vector(3 downto 0); + s_axi_arready : out std_logic_vector(1 downto 0); + s_axi_wvalid : in std_logic_vector(1 downto 0); + s_axi_wlast : in std_logic_vector(1 downto 0); + s_axi_wid : in std_logic_vector(15 downto 0); + s_axi_bready : in std_logic_vector(1 downto 0); + s_axi_bresp : out std_logic_vector(3 downto 0); + s_axi_rready : in std_logic_vector(1 downto 0); + s_axi_bid : out std_logic_vector(15 downto 0); + s_axi_rid : out std_logic_vector(15 downto 0); + s_axi_wdata : in std_logic_vector(255 downto 0); + s_axi_rdata : out std_logic_vector(255 downto 0); + s_axi_rresp : out std_logic_vector(3 downto 0); + s_axi_bvalid : out std_logic_vector(1 downto 0); + s_axi_rvalid : out std_logic_vector(1 downto 0); + s_axi_rlast : out std_logic_vector(1 downto 0); + s_axi_wstrb : in std_logic_vector(31 downto 0); + m_axi_awvalid : out std_logic_vector(0 to 0); + m_axi_awaddr : out std_logic_vector(31 downto 0); + m_axi_awlock : out std_logic_vector(1 downto 0); + m_axi_awready : in std_logic_vector(0 to 0); + m_axi_arvalid : out std_logic_vector(0 to 0); + m_axi_araddr : out std_logic_vector(31 downto 0); + m_axi_arlock : out std_logic_vector(1 downto 0); + m_axi_arready : in std_logic_vector(0 to 0); + m_axi_wvalid : out std_logic_vector(0 to 0); + m_axi_wlast : out std_logic_vector(0 to 0); + m_axi_bready : out std_logic_vector(0 to 0); + m_axi_bresp : in std_logic_vector(1 downto 0); + m_axi_rready : out std_logic_vector(0 to 0); + m_axi_bid : in std_logic_vector(7 downto 0); + m_axi_rid : in std_logic_vector(7 downto 0); + m_axi_wdata : out std_logic_vector(127 downto 0); + m_axi_rdata : in std_logic_vector(127 downto 0); + m_axi_rresp : in std_logic_vector(1 downto 0); + m_axi_bvalid : in std_logic_vector(0 to 0); + m_axi_rvalid : in std_logic_vector(0 to 0); + m_axi_rlast : in std_logic_vector(0 to 0); + m_axi_wstrb : out std_logic_vector(15 downto 0); + m_axi_wready : in std_logic_vector(0 to 0); + s_axi_wready : out std_logic_vector(1 downto 0); + s_axi_awprot : in std_logic_vector(7 downto 0); + s_axi_awcache : in std_logic_vector(7 downto 0); + s_axi_awqos : in std_logic_vector(7 downto 0); + s_axi_awuser : in std_logic_vector(5 downto 0); + s_axi_arqos : in std_logic_vector(7 downto 0); + s_axi_arcache : in std_logic_vector(7 downto 0); + m_axi_awprot : out std_logic_vector(3 downto 0); + s_axi_arid : in std_logic_vector(15 downto 0); + s_axi_arsize : in std_logic_vector(5 downto 0); + s_axi_arlen : in std_logic_vector(15 downto 0); + s_axi_arburst : in std_logic_vector(3 downto 0); + s_axi_arprot : in std_logic_vector(7 downto 0); + s_axi_awid : in std_logic_vector(15 downto 0); + s_axi_awburst : in std_logic_vector(3 downto 0); + s_axi_awlen : in std_logic_vector(15 downto 0); + s_axi_awsize : in std_logic_vector(5 downto 0); + m_axi_awid : out std_logic_vector(7 downto 0); + m_axi_awburst : out std_logic_vector(1 downto 0); + m_axi_awlen : out std_logic_vector(7 downto 0); + m_axi_awsize : out std_logic_vector(2 downto 0); + m_axi_awcache : out std_logic_vector(3 downto 0); + m_axi_awqos : out std_logic_vector(3 downto 0); + m_axi_awuser : out std_logic_vector(2 downto 0); + m_axi_arprot : out std_logic_vector(3 downto 0); + m_axi_arburst : out std_logic_vector(1 downto 0); + m_axi_arlen : out std_logic_vector(7 downto 0); + m_axi_arsize : out std_logic_vector(2 downto 0); + m_axi_arcache : out std_logic_vector(3 downto 0); + m_axi_arqos : out std_logic_vector(3 downto 0); + m_axi_aruser : out std_logic_vector(2 downto 0); + m_axi_awregion : out std_logic_vector(3 downto 0); + m_axi_arregion : out std_logic_vector(3 downto 0); + m_axi_arid : out std_logic_vector(7 downto 0); + m_axi_wuser : out std_logic_vector(2 downto 0); + m_axi_ruser : in std_logic_vector(2 downto 0); + m_axi_buser : in std_logic_vector(2 downto 0); + s_axi_aruser : in std_logic_vector(5 downto 0); + s_axi_wuser : in std_logic_vector(5 downto 0); + s_axi_buser : out std_logic_vector(5 downto 0); + s_axi_ruser : out std_logic_vector(5 downto 0) +); +end component gAXIM_2to1_switch; + +---------------------- End COMPONENT Declaration ------------ +------------- Begin Cut here for INSTANTIATION Template ----- +u_gAXIM_2to1_switch : gAXIM_2to1_switch +port map ( + rst_n => rst_n, + clk => clk, + s_axi_awvalid => s_axi_awvalid, + s_axi_awaddr => s_axi_awaddr, + s_axi_awlock => s_axi_awlock, + s_axi_awready => s_axi_awready, + s_axi_arvalid => s_axi_arvalid, + s_axi_araddr => s_axi_araddr, + s_axi_arlock => s_axi_arlock, + s_axi_arready => s_axi_arready, + s_axi_wvalid => s_axi_wvalid, + s_axi_wlast => s_axi_wlast, + s_axi_wid => s_axi_wid, + s_axi_bready => s_axi_bready, + s_axi_bresp => s_axi_bresp, + s_axi_rready => s_axi_rready, + s_axi_bid => s_axi_bid, + s_axi_rid => s_axi_rid, + s_axi_wdata => s_axi_wdata, + s_axi_rdata => s_axi_rdata, + s_axi_rresp => s_axi_rresp, + s_axi_bvalid => s_axi_bvalid, + s_axi_rvalid => s_axi_rvalid, + s_axi_rlast => s_axi_rlast, + s_axi_wstrb => s_axi_wstrb, + m_axi_awvalid => m_axi_awvalid, + m_axi_awaddr => m_axi_awaddr, + m_axi_awlock => m_axi_awlock, + m_axi_awready => m_axi_awready, + m_axi_arvalid => m_axi_arvalid, + m_axi_araddr => m_axi_araddr, + m_axi_arlock => m_axi_arlock, + m_axi_arready => m_axi_arready, + m_axi_wvalid => m_axi_wvalid, + m_axi_wlast => m_axi_wlast, + m_axi_bready => m_axi_bready, + m_axi_bresp => m_axi_bresp, + m_axi_rready => m_axi_rready, + m_axi_bid => m_axi_bid, + m_axi_rid => m_axi_rid, + m_axi_wdata => m_axi_wdata, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_rvalid => m_axi_rvalid, + m_axi_rlast => m_axi_rlast, + m_axi_wstrb => m_axi_wstrb, + m_axi_wready => m_axi_wready, + s_axi_wready => s_axi_wready, + s_axi_awprot => s_axi_awprot, + s_axi_awcache => s_axi_awcache, + s_axi_awqos => s_axi_awqos, + s_axi_awuser => s_axi_awuser, + s_axi_arqos => s_axi_arqos, + s_axi_arcache => s_axi_arcache, + m_axi_awprot => m_axi_awprot, + s_axi_arid => s_axi_arid, + s_axi_arsize => s_axi_arsize, + s_axi_arlen => s_axi_arlen, + s_axi_arburst => s_axi_arburst, + s_axi_arprot => s_axi_arprot, + s_axi_awid => s_axi_awid, + s_axi_awburst => s_axi_awburst, + s_axi_awlen => s_axi_awlen, + s_axi_awsize => s_axi_awsize, + m_axi_awid => m_axi_awid, + m_axi_awburst => m_axi_awburst, + m_axi_awlen => m_axi_awlen, + m_axi_awsize => m_axi_awsize, + m_axi_awcache => m_axi_awcache, + m_axi_awqos => m_axi_awqos, + m_axi_awuser => m_axi_awuser, + m_axi_arprot => m_axi_arprot, + m_axi_arburst => m_axi_arburst, + m_axi_arlen => m_axi_arlen, + m_axi_arsize => m_axi_arsize, + m_axi_arcache => m_axi_arcache, + m_axi_arqos => m_axi_arqos, + m_axi_aruser => m_axi_aruser, + m_axi_awregion => m_axi_awregion, + m_axi_arregion => m_axi_arregion, + m_axi_arid => m_axi_arid, + m_axi_wuser => m_axi_wuser, + m_axi_ruser => m_axi_ruser, + m_axi_buser => m_axi_buser, + s_axi_aruser => s_axi_aruser, + s_axi_wuser => s_axi_wuser, + s_axi_buser => s_axi_buser, + s_axi_ruser => s_axi_ruser +); + +------------------------ End INSTANTIATION Template --------- diff --git a/fpga/ip/gAXIM_2to1_switch/ipm/component.pickle b/fpga/ip/gAXIM_2to1_switch/ipm/component.pickle new file mode 100644 index 0000000..05edf35 Binary files /dev/null and b/fpga/ip/gAXIM_2to1_switch/ipm/component.pickle differ diff --git a/fpga/ip/gAXIM_2to1_switch/ipm/graph.pickle b/fpga/ip/gAXIM_2to1_switch/ipm/graph.pickle new file mode 100644 index 0000000..f915d4b Binary files /dev/null and b/fpga/ip/gAXIM_2to1_switch/ipm/graph.pickle differ diff --git a/fpga/ip/gAXIM_2to1_switch/settings.json b/fpga/ip/gAXIM_2to1_switch/settings.json new file mode 100644 index 0000000..ca90327 --- /dev/null +++ b/fpga/ip/gAXIM_2to1_switch/settings.json @@ -0,0 +1,96 @@ +{ + "args": [ + "-o", + "gAXIM_2to1_switch", + "--base_path", + "/home/cslau/Desktop/Workspace/efinity/2025.1.95/project/Example_Ti/ip/EfxSapphireHpSoc_slb/Ti375C529_devkit/ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "axi_infra", + "name": "efx_axi_interconnect", + "version": "5.4" + } + ], + "conf": { + "ARB_MODE": "\"ROUND_ROBIN_1\"", + "S_PORTS": "2", + "TABLE0_AXI_S0__MIN": "32'd0", + "TABLE0_AXI_S1__MIN": "32'd268435456", + "TABLE0_AXI_S2__MIN": "32'd285212672", + "TABLE0_AXI_S3__MIN": "32'd286261248", + "TABLE0_AXI_S4__MIN": "32'd536870912", + "TABLE0_AXI_S5__MIN": "32'd805306368", + "TABLE0_AXI_S6__MIN": "32'd1073741824", + "TABLE0_AXI_S7__MIN": "32'd1090519040", + "TABLE0_AXI_S0__MAX": "32'd32", + "TABLE0_AXI_S1__MAX": "32'd24", + "TABLE0_AXI_S2__MAX": "32'd12", + "TABLE0_AXI_S3__MAX": "32'd20", + "TABLE0_AXI_S4__MAX": "32'd28", + "TABLE0_AXI_S5__MAX": "32'd28", + "TABLE0_AXI_S6__MAX": "32'd24", + "TABLE0_AXI_S7__MAX": "32'd20", + "DATA_WIDTH": "128", + "ADDR_WIDTH": "32", + "M_PORTS": "1", + "ID_WIDTH": "8", + "USER_WIDTH": "3", + "PROTOCOL": "\"AXI4\"" + }, + "output": { + "external_script_generator": [], + "external_source_source": [ + "gAXIM_2to1_switch/gAXIM_2to1_switch.v", + "gAXIM_2to1_switch/gAXIM_2to1_switch_tmpl.vhd", + "gAXIM_2to1_switch/gAXIM_2to1_switch_define.vh", + "gAXIM_2to1_switch/gAXIM_2to1_switch_tmpl.v" + ], + "external_example_example": [ + "gAXIM_2to1_switch/Ti60F225_devkit/axi_interconnect_ed.xml", + "gAXIM_2to1_switch/Ti60F225_devkit/constraints.sdc", + "gAXIM_2to1_switch/Ti60F225_devkit/axi_interconnect_ed.peri.xml", + "gAXIM_2to1_switch/Ti60F225_devkit/efx_crc32.v", + "gAXIM_2to1_switch/Ti60F225_devkit/efx_custom_master_model.v", + "gAXIM_2to1_switch/Ti60F225_devkit/efx_custom_slave_model.v", + "gAXIM_2to1_switch/Ti60F225_devkit/top.v", + "gAXIM_2to1_switch/Ti60F225_devkit/efx_fifo_top.v", + "gAXIM_2to1_switch/Ti60F225_devkit/axi_interconnect.vh", + "gAXIM_2to1_switch/Ti60F225_devkit/gAXIM_2to1_switch.v", + "gAXIM_2to1_switch/Ti60F225_devkit/gAXIM_2to1_switch_define.vh" + ], + "external_testbench_synopsys": [ + "gAXIM_2to1_switch/Testbench/synopsys/gAXIM_2to1_switch.v" + ], + "external_testbench_modelsim": [ + "gAXIM_2to1_switch/Testbench/modelsim/gAXIM_2to1_switch.v" + ], + "external_testbench_ncsim": [ + "gAXIM_2to1_switch/Testbench/ncsim/gAXIM_2to1_switch.v" + ], + "external_testbench_aldec": [ + "gAXIM_2to1_switch/Testbench/aldec/gAXIM_2to1_switch.v" + ], + "external_testbench_testbench": [ + "gAXIM_2to1_switch/Testbench/modelsim.do", + "gAXIM_2to1_switch/Testbench/modelsim.sh", + "gAXIM_2to1_switch/Testbench/xrun.sh", + "gAXIM_2to1_switch/Testbench/axi_interconnect.vh", + "gAXIM_2to1_switch/Testbench/tb.v", + "gAXIM_2to1_switch/Testbench/top.v", + "gAXIM_2to1_switch/Testbench/efx_custom_slave_model.v", + "gAXIM_2to1_switch/Testbench/efx_crc32.v", + "gAXIM_2to1_switch/Testbench/efx_custom_master_model.v", + "gAXIM_2to1_switch/Testbench/efx_fifo_top.ncsim.v", + "gAXIM_2to1_switch/Testbench/efx_fifo_top.vcs.v", + "gAXIM_2to1_switch/Testbench/flist_ncsim", + "gAXIM_2to1_switch/Testbench/flist_modelsim", + "gAXIM_2to1_switch/Testbench/efx_fifo_top.modelsim.v", + "gAXIM_2to1_switch/Testbench/gAXIM_2to1_switch.v", + "gAXIM_2to1_switch/Testbench/gAXIM_2to1_switch_define.vh" + ] + }, + "ooc_synthesis": {}, + "sw_version": "2025.1.95", + "generated_date": "2025-04-14T02:18:07.620266+00:00" +} \ No newline at end of file diff --git a/fpga/ip/gAXIS_1to3_switch/axi_interconnect.vh b/fpga/ip/gAXIS_1to3_switch/axi_interconnect.vh new file mode 100644 index 0000000..9ccec85 --- /dev/null +++ b/fpga/ip/gAXIS_1to3_switch/axi_interconnect.vh @@ -0,0 +1,2 @@ +localparam M_BASE_ADDR = {32'h41000000,32'h40000000,32'h30000000,32'h20000000,32'h11100000,32'h1100000,32'h1000000,32'h0}; +localparam M_ADDR_WIDTH = {32'd20,32'd24,32'd28,32'd28,32'd20,32'd16,32'd16,32'd24}; \ No newline at end of file diff --git a/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch.v b/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch.v new file mode 100644 index 0000000..0040aec --- /dev/null +++ b/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch.v @@ -0,0 +1,1349 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.1.95 +// IP Version: 5.4 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _2bba7642b6c647e08f6a49c8c42e531c +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module gAXIS_1to3_switch +( + input rst_n, + input clk, + input [0:0] s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [1:0] s_axi_awlock, + output [0:0] s_axi_awready, + input [0:0] s_axi_arvalid, + input [31:0] s_axi_araddr, + input [1:0] s_axi_arlock, + output [0:0] s_axi_arready, + input [0:0] s_axi_wvalid, + input [0:0] s_axi_wlast, + input [7:0] s_axi_wid, + input [0:0] s_axi_bready, + output [1:0] s_axi_bresp, + input [0:0] s_axi_rready, + output [7:0] s_axi_bid, + output [7:0] s_axi_rid, + input [31:0] s_axi_wdata, + output [31:0] s_axi_rdata, + output [1:0] s_axi_rresp, + output [0:0] s_axi_bvalid, + output [0:0] s_axi_rvalid, + output [0:0] s_axi_rlast, + input [3:0] s_axi_wstrb, + output [2:0] m_axi_awvalid, + output [95:0] m_axi_awaddr, + output [5:0] m_axi_awlock, + input [2:0] m_axi_awready, + output [2:0] m_axi_arvalid, + output [95:0] m_axi_araddr, + output [5:0] m_axi_arlock, + input [2:0] m_axi_arready, + output [2:0] m_axi_wvalid, + output [2:0] m_axi_wlast, + output [2:0] m_axi_bready, + input [5:0] m_axi_bresp, + output [2:0] m_axi_rready, + input [23:0] m_axi_bid, + input [23:0] m_axi_rid, + output [95:0] m_axi_wdata, + input [95:0] m_axi_rdata, + input [5:0] m_axi_rresp, + input [2:0] m_axi_bvalid, + input [2:0] m_axi_rvalid, + input [2:0] m_axi_rlast, + output [11:0] m_axi_wstrb, + input [2:0] m_axi_wready, + output [0:0] s_axi_wready, + input [3:0] s_axi_awprot, + input [3:0] s_axi_awcache, + input [3:0] s_axi_awqos, + input [2:0] s_axi_awuser, + input [3:0] s_axi_arqos, + input [3:0] s_axi_arcache, + output [11:0] m_axi_awprot, + input [7:0] s_axi_arid, + input [2:0] s_axi_arsize, + input [7:0] s_axi_arlen, + input [1:0] s_axi_arburst, + input [3:0] s_axi_arprot, + input [7:0] s_axi_awid, + input [1:0] s_axi_awburst, + input [7:0] s_axi_awlen, + input [2:0] s_axi_awsize, + output [23:0] m_axi_awid, + output [5:0] m_axi_awburst, + output [23:0] m_axi_awlen, + output [8:0] m_axi_awsize, + output [11:0] m_axi_awcache, + output [11:0] m_axi_awqos, + output [8:0] m_axi_awuser, + output [11:0] m_axi_arprot, + output [5:0] m_axi_arburst, + output [23:0] m_axi_arlen, + output [8:0] m_axi_arsize, + output [11:0] m_axi_arcache, + output [11:0] m_axi_arqos, + output [8:0] m_axi_aruser, + output [11:0] m_axi_awregion, + output [11:0] m_axi_arregion, + output [23:0] m_axi_arid, + output [8:0] m_axi_wuser, + input [8:0] m_axi_ruser, + input [8:0] m_axi_buser, + input [2:0] s_axi_aruser, + input [2:0] s_axi_wuser, + output [2:0] s_axi_buser, + output [2:0] s_axi_ruser +); +`IP_MODULE_NAME(efx_axi_interconnect) +#( + .ARB_MODE ("ROUND_ROBIN_1"), + .S_PORTS (1), + .DATA_WIDTH (32), + .ADDR_WIDTH (32), + .M_PORTS (3), + .ID_WIDTH (8), + .USER_WIDTH (3), + .PROTOCOL ("AXI4") +) +u_efx_axi_interconnect +( + .rst_n ( rst_n ), + .clk ( clk ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awlock ( s_axi_awlock ), + .s_axi_awready ( s_axi_awready ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arlock ( s_axi_arlock ), + .s_axi_arready ( s_axi_arready ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_wlast ( s_axi_wlast ), + .s_axi_wid ( s_axi_wid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_rready ( s_axi_rready ), + .s_axi_bid ( s_axi_bid ), + .s_axi_rid ( s_axi_rid ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rlast ( s_axi_rlast ), + .s_axi_wstrb ( s_axi_wstrb ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awready ( m_axi_awready ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arready ( m_axi_arready ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_bready ( m_axi_bready ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_rready ( m_axi_rready ), + .m_axi_bid ( m_axi_bid ), + .m_axi_rid ( m_axi_rid ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_rdata ( m_axi_rdata ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_wready ( m_axi_wready ), + .s_axi_wready ( s_axi_wready ), + .s_axi_awprot ( s_axi_awprot ), + .s_axi_awcache ( s_axi_awcache ), + .s_axi_awqos ( s_axi_awqos ), + .s_axi_awuser ( s_axi_awuser ), + .s_axi_arqos ( s_axi_arqos ), + .s_axi_arcache ( s_axi_arcache ), + .m_axi_awprot ( m_axi_awprot ), + .s_axi_arid ( s_axi_arid ), + .s_axi_arsize ( s_axi_arsize ), + .s_axi_arlen ( s_axi_arlen ), + .s_axi_arburst ( s_axi_arburst ), + .s_axi_arprot ( s_axi_arprot ), + .s_axi_awid ( s_axi_awid ), + .s_axi_awburst ( s_axi_awburst ), + .s_axi_awlen ( s_axi_awlen ), + .s_axi_awsize ( s_axi_awsize ), + .m_axi_awid ( m_axi_awid ), + .m_axi_awburst ( m_axi_awburst ), + .m_axi_awlen ( m_axi_awlen ), + .m_axi_awsize ( m_axi_awsize ), + .m_axi_awcache ( m_axi_awcache ), + .m_axi_awqos ( m_axi_awqos ), + .m_axi_awuser ( m_axi_awuser ), + .m_axi_arprot ( m_axi_arprot ), + .m_axi_arburst ( m_axi_arburst ), + .m_axi_arlen ( m_axi_arlen ), + .m_axi_arsize ( m_axi_arsize ), + .m_axi_arcache ( m_axi_arcache ), + .m_axi_arqos ( m_axi_arqos ), + .m_axi_aruser ( m_axi_aruser ), + .m_axi_awregion ( m_axi_awregion ), + .m_axi_arregion ( m_axi_arregion ), + .m_axi_arid ( m_axi_arid ), + .m_axi_wuser ( m_axi_wuser ), + .m_axi_ruser ( m_axi_ruser ), + .m_axi_buser ( m_axi_buser ), + .s_axi_aruser ( s_axi_aruser ), + .s_axi_wuser ( s_axi_wuser ), + .s_axi_buser ( s_axi_buser ), + .s_axi_ruser ( s_axi_ruser ) +); +endmodule + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +k0MNGAL+siJuDYrFA58rRJscMTUE6hiuNEylu7uA+mdVk/vCPJpUprjqZIgJ75i6 +csRX146zVh4AUQABC09rbvto0kqPbqsZwZGmdOm1W8NmGZIXLCsG4MZs984TiToI +QMOSc+XFr9GVx1rFODfIQCsRVOla6WZCpHrBZzFjmFwY4t9fXFQCs5fSkNbGyG6v +8YDvdegFPMYp5Qu9ccfxeosyrpdCBompAmWscbYmzMrmyFiInvb8Y5dyqCuve1NW +jirl6fz1954ypdomnZDn+X9k8zTCJAxovyf9Qxk6Q+/Pf6e6yRqEYBxT7dtZhWRG +tEQdKP3bt5KBf+EuwdVLuQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 9552 ) +`pragma protect data_block +CosGYIkH0xBRxN95EJWx839RlT4VAi4LCJZ1mt3NitRA5g2pDgJLsvVh2D1y5BVA +pdFnLxJlKeO8VGxcbjdy9+FeBPs3Bo0hcGMo8L+LaJ0bVkv+6b77n30HN7W4KS8h +FD1Ep9sROiwLtXRFHJO89i05/tAaQLM8i1caOwWOyxnOkkN9uNWnXu8Q0YVHwDSo +6edwH6pDm7sUFDB7MkilS2mpOjdUBdlO7TGkRl9TuEENWQoMfIDEVtwj5ArywPyR +ABP441amQzUHEwhfDKcPN2iMoBL+T+S1wuWnJHqvzHEb6nVPARgwM2LxvxR9dJld +dNlxyS3zC6MHchUMEAThn6/mNnJEIrcrJfsvf1vvLfpUlQ5d+C8Gj2KcQl4cX+1i +y70cPd03g1gHtWhRfChJ+8u0hcEyphEmEnx9SLi2I4xYi+fTWMgPPM9PNN1YXNHq +otMqtc2ceQLlyCdlKJplKqKXkqQdhPcZ9wt1WckUoSV+ZeiA4t7bGUWN3kexbKDy +o/js6xWIxX0ryxN/pbXUzhaj+FMP84LHEs7BoUU3zxlGsUspgAysZAO14S2sGjNI +BGpe6bm0ONuesSHUY7+4NUAWlwtPlG6ulaAEIClApiB8gBOvDsTAQbDKVkunI6rz +9cfhmqP/A1djz1i+Lw6iytrG/0VEU8wOePUdJupVohofGQa/4y+YwGciqdf8bscN +y2H+LIZnDVF8FwQqxUMjnTJGvd0s9fHCJfhYvXMWorLOGLe2wW1l63PmZQoaNVXY +K/JSkYpZKe+1jeyKioBw1ecvAOFXmnHjUXoGGiAbTSgVf2c5qN+UOXty8BIpzXsg +rEi4GkhlmS9JOl4OQehZT8m8XUc6Gk4tOWOFI/Y04qqVeyyHXHoRK2YypFTeGvWZ +QWRGXrwLYJEsSZ4pSXjO2Y1sNzJSAy/LUfHn9ih9RN4pcPd2t5yJBs9i2YKdajDd +mMZ9cfbemdV3IUPvWQsy/p+aey0Cf+JLwgchg/lPfV4xgZIc4ZIqkBiIrOIkYCRT +43pSktGOK0XWBA1vaFIbC3cpTHkDm7LQWLF6LkVws9H+W9Ui7ZphPGJYQ2FZuPFI +x4JdlFgmbh8CKDphsgQ0S9wIPIiTxRywf2P0QWvDuaAPSf1ONlDVSLZTsMpwMhgp +JNkTIkZg82zj0VVndkAznUheBGdHU1LM7Ao8djstDoYkJyBKszFcpg5i+vych5sn +Y+FPaWBO8UY1afO/VO2H3aMYvPs8Ey4fLon6Ot+jqqE2QhWfWOyr6/Y2KpZ29Tn4 +yJFhBLEGx890JscKBgz/Pty/z4uI88ARA6quPcoynMcdIZ7KuZ3//NoLU+MW5Ji7 +VFYtef6sYztFjyVBej5iPcwEB/IFI1d4rEZ5trsKDNcBYtLv8P3uUTrAbkBUrkzI +yAmsEY5jaLeFXJdeT5qZFjyy9LTRuyOEdhKoHr8lsbIvJEP8fKGOyR71wt1P8vDh +baKkrSka1ND+doDAWaIksjVzpZtoOUJMCdyqduEGaSXMoEbOLzjwCwatyUAZnAfl +WwdgTbr+jMNDwm6ZJ1uUwd/AC+w2aunGMR1WHoMDyIK5icyVab5vg4cygOV/vkym +3aFkctiYHlucNCcL8phNpyLUKgGpY7wU7kLNA24HbnKJlqAwUOFuX/TToc7PQlcV +SY9tr2TMOFipbNlOu3jeaB0Vo6yseFq4QJYhA43C14lER0DuVgRveDhb4d+kcEl6 +bNUBGSkHWyh1txe8rFLTipxEBA9OvA4qfpJLdjdZ+y3lkqRQtHFTpuHTBJs691oX +Hut8P6qCvMQWHtqbc3rdk4Y3duWralCzKqrsCmziyZIJpOAC2sAyw8ISN+HX6FV4 +qfLqVX0UeSni7AgSkhblarOhtAnfYULYt5K77BFGy/3v2o9CPNOno8LSdA2CQ6Y4 +8oZYxxqrifzsGvCdSOAPCAmUtCHm/spRjVS3wwZr/JqiazytF1OksyJ3qY9H3Yy9 +cAOg1szShsdHmj4PNrZqE6mwktxWt51Th8QjPkjALxf1zO4f7PHlTl1NxGEZk3je +MQEv/NtiqEzeRmzB3GLiIAPNaq0pD4t6Bn/pUCW3WXfO9SsCw/fk57GZ/MCqIxfz +Wzv24NCpkA9CpffUL4DZ5pcSNGwbDVK8NhmPq3jq9aT9QiYkkv+Mc1G4gDL+NF9D +hbyD1Pr9TxJIKk+kFIFIdVJBMMIcVBOb/wo37185XNJQbJ8TB2axmGnkXjNOge9+ +arrvoVM2SERpIbo8+cbHNMy1fY8ywtiIA/N9+BybUe4qO24RtzrsJHoWJ1Rn1Rg9 +jsFzaIVI27UiFjAhQfsnzYfTKEnHZu4NnbUDGzZrPgFbQQCkbBiENyXRVX360gfC +hsfv5p6XFZfrWjLL55g2EmdV93K2ja+i6klL6yfb9+nyTLI35qz0QFKMIALNis8w +JKwyRM3ThTqe+K8+F25fyT0VqHp7Rk31IMEP2PIM8pkwn7q6CAdeRoPO+rln6Jaq +onLkSko+m25UxbrtdT/oiF5b1eR4oQfUAVJOnMFjMkuBrc/KmkiTotNCeFs47ViV +02JeMX2f8G8daHyES8qCv5R4a6DKb0lrNHoojbtef/gv1HFDUhxGn5xkqlDrApwi +AI2pXanHk96xQ3jzFuEI4oQ6KtHySDBFRby5u5Xrw85f1oSAeDDHvy7/Cw5emFoc +HDu3rpfebgG3sKM3ZrUH06lrR2Im3LbGXusrWI/isuwyYuYXyWMMpsJo8t9n8KpH +DYTSNXwIpbZ/rlm4yLEdyYPxNU1X93LpIY9+XJHBugTXrRpQWNr1NjX7xUD5NdhZ +no7eo1okylN6u2/9VzwwDxzpz6E2/ju3J32x4CYYhQisuP9BfA+GPp3vwp/f8JkF +wqKCtI6nkxCXWkDrPTmplKzKJxCSAN9iwYi0Yn15/oiBTA/l9NWgRb59/zARioB0 +xX3tdsXLlBZFuH57ePS6RcmU/DHKUkyChHupCu+IunhHfEC/EmHtGsjSHKrG5iyA +27M3fpB4Xd/LeuTYo+NaEYTlANaMYUeteH/Eb1PDwDgGF2bGhnriq4JmMd+EFZxL +4FiJpggUJYd/M135cC+ohSWsHT3WK+IIerSKyD72G/xVGexHeNPt0HXhdCrmgyH/ +00tTjTHdZQKdF4CvdjFeCT8+6Q9IQlP3CAaow27SaK9BibNtM6xbsHKlBW17PUbV +JDUZOiRAtSKcePPkEXirrqEFJWBUmBC1pJgAnn0IQE3ZmUSvJeiaxvyAHfP/IvBr +d7dr3MKhikrNMdgNklD4kU01G51cn7ehZQcSt7o1wjJ2bITWQAI4CN17Pa5BSi6x +M130n/O2tghSh4RMRXuM1uOqcMJlSdDaSSrNaXgMAO4ePH9mdquCwRLTFBdGhkej +mYrY6frqP29aFXcwtEaDxnzDmUML+UePGNeksngsXKyLW4NwfSYkwuct2paDGZ2n +l1mutyakT1UgcTYVtTym6xQjxp+fEQt9RWSaYw9my/H2vf7DJ3rgRmlnZ8VGHvsg +Q7vBtFvGEyU5LfD7czZT6ERpJCapbmEhOMibFy74sgIfFf2KYdcAr+ILpb26imPN +kASgszlpTJBiWkHVzM1hcGnYx07ltmPoEpfGnyP6w7idperxlYoUHzJa+QaXCQ4m +IoQUrcLW3olf2qD2dAHy+J7ew5IrXyg/FcEqkeoIvBM43fGKsr9BUlh2s5zm0qZN +PYg0Al3SMA2nVYA2BRPgVjfFL3iyjOFKjboMwEbHGEUMvVWE3YVgj5waDPrjRLIm +kejtSYej3CYAkQIw8DN9lhDSAg44hrdtYkk7EN9O+ASmQi/c9M9ROYv+Qh8S5Jj5 +aU1LWZY40pLJsnu1ihdw5QSHCIC/wsBAe3I+8+rEe8JqJbQ/OVOl2yqdOzJlUF9c +UnTwJIjcPj1/YZ+ouq+J52boVdYPIY03uzXfvh8/h0HS0sSBW+N9N4/qyhjwu498 +if9WWyX5QNldlEzADEOQJm9yvhTGUbOKsQHvLkq0L7ODUqfqh/4I4n3SVQBJLBgc +fJoHsaTB3UL233Itwlddl0RQZeZ44+2UurY6PPi9cs9PQHfBMGM4EEDIGczkfwrb +VXsQDl34cKlIl+ualZ8HO1RTQgonZpI3JpC67Li9mS00jWiYo+61yZ+tDOsKJpWH +rk5RAiDEgeEifE482FrBHyMs3Zi0M1ADm+CzchwS48zNJBS+Np1D9quxmCB1htEG +LpYnY4f5CukA3sRcAdKOBZiPqiZ8epunSri+QBGMzTlsy1jG+BVDiHw7qCnIjETO +uoYWsfqh1J0/Q3Ch1H17d8H75YtBWzWWaK87dTjLrHhu3IbA537Ey8THNaoKfpo6 +Q0aj4nLip/23JZzowTwMFjkdjIxaaUWG3BBwLysR00Ojci4rWhcJ3Kkl7X8mmTN0 +Q124nxpjDKCmoQG926wQYC31yHEVgDNyVILxcyV0zVb9FUIxojPKXlkmqzM6xfnz +fw2rDLAQt0aEZQ04G2P8ogq0Jm/S1PsqY4LoC9LSugckElDBF9jE2pTJbu8zejhN +H4f+b/A8yrlKWsTesVaXNrmTKFvEQErc8vi4UEaHdLvOJtJsA4Z/8zVimjWe+Z7E +RmOV1S53KXGzMg3Bs5Gom3YC9v+Vusuq4BX1Bhq1JkcGbq6TbDMG8rvG29UCt+2P +EplRUHVp9FSQ5aWP6T18iIJ4MSvhHH95hETsFAnkjnavR8q+REgqC+A2U+Gd3ibS +5fvK/B3n83x2SfyU4VcSf42zxVoleOLSYrTlIVVDY7UHQUyGCZhBZ08zXuncYYjF +40x7WtGXgFXhK5uHLyYRKCc67bdq+D7gCUnNhskDr0azpw2O7JrrdNoN0gZ0bSss +wOx+7CzZBb98+Kv8pOBrbU2pMKNFQwd70PBQWmRspVX1ib93hzuOh3uoyFCqHpDo +dkNAQR8AnBTO6wfLI1QLzYkV4XcuIl4YnivmZeWBGg3wCsE6wPJKRJtScC/i9Kq4 +PRalvjf4zDFcUpbLmF6AZ1UtSuExw4OYncihmxUpRcOGYovNufLqtmoC3q1TdExb +w0HGPIyJ/t5KEw1dXq7rd4KgLTIbgjUIDjWkXI5hfshqKBMcs+d51vLXaALHDwNz +VFU/iskzvUp+uE942PEpAH/hFlbSuZeDnKVDv3hfWSE6DnqrN2BvbxOOTSYShGEq +zjn8Xt1ZWmhPYYoBiaOAG/AFlV+tOsRI+g3KQjL+l3+iJ8yh4YwNm/A1t6BxNjgu +Rzr2KZsjDPa0qGRTrMEV4Nb5y2TxS77nDuyf+Efc424O/unlG7XwzpRJxvhYuArS +5yEuhUn+4OFq3XUJjgPeVEJH9fUxHlpKscpjAOMtsxu9lR3u3Krv37aZm9OwyEDG +3tU/l/nrzG4VEXdXExlGFP91lhygme0XJiPvLJAe8DAmTasKYMe5Rg6LNXyZ/4CL +xgjY9uYdSrEiv1J5aMGmdFDuYxfJZb1UxP0zjEGos2eCRUfR2KNwl09dCxRHOvMb +Z4n7HR1Lsqw5V2S9SxmZo/A1ju/rZML1EO1zDLkqe1on8dsPwyu774HfStaMhVGj +OfWr0AVe4DGr0jfajYwc6WE+RUAS85t27GtS9Fyu+Fz0Ifl6FdpzdUaMrJI34hU+ +i9XO8ofzPd68opcswPcO5AOaaL5w74Qfj4Q8xhdPpq+Tu/Ke9ZVLeJ2rFhUug2Ig +8iHhTJofPg8GATOdo7t7efZTS1J6CRk6AVotHvyJ0RCvHKr6i1qT+lCRu9EIuh8b +c5DJ51U1wh6y0k5ffYzFK0QsiujE5huyTFT1LNJrUwApeB8R27kVKSS1mSM6mz/4 +LhNC5nzo3JJ11XmH+ozwXTeXhsQS0NdFKyZJfW30fwgmqcw6UbbzbytJudUsG96L +dRmHzENmUnzRgVsSzB9z0tta/mIJ4aapzp2MPR8rmiiL2oDCOM7uZ7OYrmddzZEG +VsiMxJYOQb3s8MuxKfMIg3YMeKsTXYx016ZTW32L41w6HxqFFEFHIDi5qw2h3H5V +fsS6IIfvKlvfnWt95tO2k5LPmcYfl1Iq2QajQ/k9kgVyiOtAyF6pl6qPWKumZlli +pVcT9mTerAsGA02QLxeAesN8m3ojtpjQ7ZecB8QnN1lZArmeGkrYkGazFArgYJOc +Z9WOl87htK1txyN2ss2dAtgXRZcnDHm9G6NZTckni0CLYzPRXGqPg9Qhzjamx5O8 +RT4JZ9dERJ7nL8hT5uxmMFOgtm4/bfEeYZknj8uWjXP+yPdd96OH+PQ3mRaJSnPp +gmt3/SYLcyLjt2UF+k31JZ3v3y38zo/YhpP415VKsCcLerK7ULokgjgcr1H53Z91 +ss4huvMVNioD7eCutHG7VhRd4W/734DyorcglRWZDFQiGryyXMyhuBqv4z5xU1mW +ItulH01TTC5lPpPqvphq2MPOwMQ+b3QeCdmny98NSvIqy8FDfavqvuwWmIERgoge +QnOe6ytg+5qB7E14cRHWZo3OFGM7jTDvwvlQ/DYMpVMrG9FNr46ij3vTukx0bzDP +iiYU5ltHRny5B6LRyQXJXJi0Xp0UsAfDD7IxTFp7g0JsXxhRotnjqqmsRHID1cUt +9M29af7bU2mdNbhf2ESqjC97RA/1F2AG3ShxJxP/lf94Stc3VHbqi3fB0Nb7Z0rt +FBQk2c+uV1tD0QV8ho4vnUImlUXdPrwbNGamviPOtbGIMPR3Q2Fd3qj502Pi4OLp +Y9GhrZZz4PTDP13vlp7aF9q1vQtZALcOZrLT71PJB+uu3zCkg1e/Jz1UkD3Hpdot +vnX039fSPcJkyJsBzc9tnNlTL/Z8AJTq7NxaQ7NA+bdLBfV9zHhzMpaS7lSiF7lz +YzPwLB0oKTTKi3q4AE6Nm2WliNx4rf8rWW9VJ8IzO8zHgD/03cmdbmGPQBpPW36N +LwROtnLY8u1XRz6d04nrrYBdiG9rU+XzUCfI/QHskulQyMlZRa37gPLYNvcfF1zz +YbUkrCqxnHSn64xnPuQQZGjTk0kQORKuer5/mLjwqy7CYRZyULRinMASnzo47ow0 +Jx5Py6hznQFjAlNlO6NbGbfw7JgaI9kE9tCSZ9qXQtoZ/u5tgswL2R1CWBgHCFlv +tvTuqNwuq/1kG+48jFD+f5O0zWiB+R2tF1dzOaV8GNsynKgvHiLzhy1sMPs4P4U7 +JcQ6I1rV2mD6mKCNsPg5tLWFzi6vgfNkDw1xSaThZVwp5RgGryD6/SO8DSEE/h88 +n8LivWzhC/tLb5d+oXOI20PLwqKgI1qDbEo2/oZdpkHRgurHQ7pLzNPHmnAbjQvx +g0XQbnCPfZEJt5Jgo4fRO9xfXng8lTQbYTMQH1rJg1sGElIsdAZGNPNOP3dZezGq +dJTB6aMp5WUo6wWFvB/Fv5JEHKW1K5SxO+Y5KjnRSbdgpfVKyaoKAutYCcd7q9wJ +7wq8Ft0TT7UMeBPqGvknTXXm8w90V4MA789DdKbGXyx2VhCTLwFjVz2ysT42UJwM +BYbeELCuPhqp7EE0v0ysbT5MD8oPX80U/Dxeq39wdt9PFXAWz7gHae26N3KZdiKL +NCDN751mf3ccCJxy1qZCnQz17ToP6ZL2HWOQzZWBfYTjV+y0md2sNArb/C+GUmri +sISKA+Vp8Dk8/CUrUHV2q02iBFkRJ61QHNEWtqKNgX0pepYM9D6w8Ah9LgHgXgFx +5gJIng2rqOhaDfnUQToP82HdamOmHnCJ/gBNjaqMf+7bn9jVW+hjVY0ZPxCuQPAv +1uc3Sz3q+ZrNKVQmGh29KI7oZtTa9jxhK3VzoSpGNRCAS/anWSq6Hd4Dumm+oSQ+ +lHXUz9881/TiGnzog+eC5nc6O+Kc+wXbT7AmzsX9/5bjf/hrxsk6rEb/ixtHkB+i +GLu/cSBGVfFY01E/YTWetYSM2zUxrItaFaMSEVAkWnKnCLXVUQpB0Kz9qwEco+7U +Py/DFCDDPq/glDrxPTRPT+Bs05xxyx/2XHt+bpq+MsU44Ed3d545oXNyt6nEZKlM +HOAZ5hR7iRN9XTMHcw7N0Hj8w4irvXFIqQRN1R1gA4d57+//KLgVI3r2muMQiZq+ +gB95VPq23ELMxr3mW9TIQ4fq9srfL7AJ6hzLO/MWXkGwkthaudHThv22nioF6LF5 +tCyJUv3pc3xQd+G74SYee+s5YEbqoCzHmTvTz45mQm9qmLgk4ED7FC+8afzZrUWY +DZneOeh1qUIZqQgu7e/ftQc1kB0mY5qLngSaDlkUPHBplUlk0xcNVRqStxNYlyt6 ++egXrZOyty/+FX2wypnXy44ivJDKWIKpNjJKJFXthsSWtzyJBjGY0VttbNviX37j +yuoKGTphHdm7yZ1DRQvtUmr4WGTicaSfUC4oZttTtofEDAr2qipUF+LwUWGuGgWX +0ip/rhABZEM1UuOu6WNMCSf03YDPsXSBqg2ju1rexTk3z53VGM1cbU36G+EzTGim +S00BfgwxVQvdBJ8c0ORYmiZMNYt/IHd+dAFtWEEGaqi5na+rlrZ8qqy1rOufSZ4E +Lhgwp+mPd5p3ZNoMT2KVo/hwXvMhUpucwCT4WW8xKxPeNCTTww2i+yZxZUyLc8Pk +048Kzu9YjSoKUHk7r+hdEa0+CSnuWFARj5CUgscPrIse8Ty1lKKYWGPXQ+OoJC5p +phKW2nKPBeh5CDgRUqlFG/xj0O6dNq9telHYAWwBohz/6adUKI4xNUWlBY8FRTQ6 +hXKVB3iRnqlC+ln6f0fZ1KkT0rvkIBsiJF3tIVbOIGrGsa3pvqiGAP3iWF7BvOPF +5SY33+T7QbZQtrWpft43XUQomKj7RJNdoZpJmmIrVxU/JpesGd4n8Qghy5mRyV7H +aqnTd+JmRocf5aCjFjvYaHR8M67gylAm6h+JZSW9vDwyKv5KVBRPd8oaZpTaqqwz +VkNrrXv7fqDnSTEtoKetTp17kp+aF2tA0wamRKJW6X42SDtFKtinBnd1MFfmq6qR +Wtr+oDpNotRs4Cz5Ml/ETb9V+ctLISmAFpFZsXKMNEBf1l67EaVHhQHshFVo6MmE +gfaISipXVe57j7bJ1c1F2q+UPOTLK11kok5kuoZkZrSRdd0nY1O45diOkMe0f8SQ +s0PjcMXSCOVG5R+NhZHxF0GRm5GOusqh+luad3/HtsmjD2pBaT9TIORoUfo20Edy +hVQkeAWA8z0mjQv/kB/5N+qKVIlRuyz/cOV5MKmX0HFaBurRHbwv/AbS/5Uh5ZPX +F6m0+erd3l9ccqBuAvItaw4ouf/pr1a1kMDjez6R4CxmGRynS7E4al4djdLT7ZE/ +Cf4L5W55tyE3A4zGbYuwXxlvzB5otmjIARCVPaCJsDLQVvQEaS7/OFItoPSCuObn +w0w0h/4Gs7aqO2bsGPGLEr5fMFAjHsRiCiRxmmHUiezrEjiymz6RaZwzb4FFL3B3 +gpGoZRbffCIVaBgKnq1rifvnYtZbOZahg5UbCMALTRqj64lHxRKUaT+c507MBzcT +2A/xQaaMXd1unIp9AQPTmHGneDmpNpipbUwik4wZUVRBaaucrLWrG6LcGp4icVlK +QWwb+t0Ngh3nQgB8q4ywRv39xYJ+Ntu4vGsXz9Mt+hM4bjRSfzCFgdaaNQqqFNPB +c+dC2M7DsriTPTygks9wxwuQtzSECp7sgpkLEWJOGJLy4LVOCFyh4jdmMqdieiHb +BN1iscgTk91VwkG9+kQIgHStsiOsI+n81iz04jxiegCP8peldNSFvX5GYFHWotCO +ht0POQ1shkziTXdydE3F2umaRkAI72qYls5BhDPyfHP+Qf2ZsBACz5UId/nxPeD3 +5aWDupx7LBRLGH6oR2g34oj92Y/o/ph4b+Np1R+XmV+ahBA7RpnUVe6dsvN6UeSR +WglN7R4pTf2UTS+KD72r8aNQlcjwZ0DiDW14GW75OHxf3G5PZ+/KCoucxUfvZRNN +PeWX0pLfgCzN6d61NADCpGqzRaV8N5hfevJ7lWFXsU7hUXFMQd9d2YQsa6Isi2mB +rXHS3ReefPS4PBVhANGSzG2HuNTfc0XTeROebUTT8czFCvv1nRkph+eif5+w9e5Y +wpqZh64iUA5G1Lb68JAL5l96ntIzk+XHzfkF+bA+7E84hPgedhaTw2z4zzESxron +mWxB+8qJnZA1CXsD/PxASxJa3afR2iH0KkUDLyERtSBaZUV+ORUr0t18zpDlHE/0 +agC9ztwh4doxddnpKEXFBftpZaVbKsOypMu1vQFBxVPwwoKSgpcVcAbzUkWYnmJT +ZLX+04cd+Rh5lFe50K/JPYE7rw0EsiqzZFYja0GT/aY0i0sr7ggBv5PGox89DaPR +M+mwNkInkOXxi3MHyRrVITAGp2WcOXHmmzdXO6qpeExaBdhW6lBRDJorwAyOb1cQ +h4SZw5YdoducErUAzTrkd7VelUlhr/w1jZ/31NgyaSkRVOlOmJhTDTmxs83jfWTw +eZSGDO9ZvtDIgHBr4CLE/5SyxgW2lJdgs12MA8AmIFHbwTQRp67rKqD5tqjFON0Y +icTpZRXGj9+IXV/OlkjnMVKeIUjhVP7M9nzyCzQSr32foBsBoW8qEOEIe3Hp8v5N +jka1PWiaeVsORmiFSEJuNQBIbwKLWj8WpOQIU2WBsaSbwLgxZbAq6QeG+fWoHvOf +ZQsrr0aheaJ1sEjp+g7kcRz+OkkxiMLp+zqstbX3HepZcLcjE4sP9r3nffEF+jC0 +Lk6er739jGapdW5xc0mLBK8kUOlRUTOwGvfTMZv91gZkOwonaCOJcYnvoRnSZajJ +ITbUtQ5Ur/sIl/RJ48z0JlENCcZ5t1vwa7H3Iqh1SEDh3QEShy8erQMLb3uhogh1 +2PUTkyH2RVxTZrAjAmn/EZzsLf9st2rU4988fH/F+WN0fQ0pSzOjDOtT7Siie5l1 +LjFScPHYqlnLkl5CpaeHJ0bNu67frdavI9wj3kQzMRtsgTzycZJ0bvA0r2xRq804 +IYtaimeUwIRwg9NoGtcdYBL6k3beA6SMXeE5QJ5GZJcrOhcY40zgTMzcSKrkhSci +cVWK/y9yq20tFKRC95HuZMO1n1sCKpRCez+UluPrmyEhpj9i6SVFAyLhCa5/1T4Z +aIRK2609/+UWwhK/rFMYSAG+AMpFADC/G6hevSzwdq3nPYFNjaJEwuNqdgE08CfW +ZBUzJ7aBGw4QZS88aLrb2T5mdGqHWOCwD1F/0jpMDMwccTpwYqhcuixKy1IGDFsS +SxZrlEdxBAVpAlnWz3j6VGyRiLF2Th76uYHTwEeg5CwmofBk8mtQeHzyU1XelJPd +gT7yvnl9TUpDQ9uNnt5CWKAOy0jgC4lB+HILxpFgtlZ6+JawKnbbBmS5MyU9qsm5 +k+aQ4yQNdP5xyyXRTgyvSa21DiHvgzNv4xwNr2ClPh9xrsILpHGIviphv4ekwk8Q +pTFnZsWkl11LwNCbJZudB/3n+QXsla1k8zBe0oZoHDH/D7ao0GNmpuExKQohUuYm +Bkun4xAB77mhH9DoSaVs+zI5vJcDJK0J0LQNvZfdLek55LLkjLQTxvOKtb8IOHUa +R4PVGheykA4RribJ4gUmTrG4SxWRW6V6c8w/COxUBq6e9X3emTum0BXg2S97ddT/ +ugRqIye92Xu4glEuBKiEiSsYkCRRFRLfy33mg0Qh/wkn2YK6ymErHe3Va/xaHd53 +u4ZQNfZ2zwhyvScbaIIKwvMZglPNQTVKJoYdIRbSsFKAxyxhoiaeAS0e/PnTJrur +mmfNVhSaIcrbUmWrPtqsWn3ytCkkxdFXeDA1Mrr7npc+5MZeGWXYymgb22vn9u66 +VbgBe6JhB4LsFBymmlL78FBkH1Khl759XHwSqWBabZ78Nsma4wBoKqkNERIlTDFg +hM2GSRsibel4dwsBaKSh7XnXS1WialkaMX5jTQ8HgRMGL4Ieh+pBP14IyC8A2PgU +GZsHuiFP6gjnfiXafDlwsG2t85g1g3HW0nfk/lb9mPz9S0DrQpQgWE1hBizL4CN3 +c54o8MNUpj9kGITZ4R1NrkRWVKJGNeLGXMIy6MgmrAN6CjjyfID3jAe4CpIuUinu +F0uKdEsEMvl66AbaK2py4LZPaLpNpA+P6DKvQhVVBJjaOwuoG1zEvKavi+L8J045 +cuo6cLFe+aI+c+Fgl7dJrgLtCXnNojuOT/+/O3YbGWgGMJLq01mnSD2isOXdr1qw +zuL8aJHMRSJgY7p43KcdzyVbc0+0ala94PYpTuLaVVsYJGpyHHMCgHJhZFAgdXtg +Ux3K+QIeLnmphG+CLXWnBqNGzc+Y5h65JJ/Mo58vnrFb0gtG9qNf1y3lPp7iqFHj +j2D2AylIbNJ81RQmFx2cPoX2PKiIvKb0Fy6SD5IQ/2FLqRJqVOjnwg3Uu1AQ1NR+ +OAu6M+ioz+nfZk6rwKkJjrU28weaeNKuNtCQOwbaS39NwTHRNDybrXbAXbso3Izx +hHULq89G/WE7fXIJJ0uNZj/cmIVk3lVF6/9zsx2+nHv/XUIhJZx9EG5LfBBVc6qr +CfMjv+9oxgyUl/uPWDBsm26tkTV3DbbHeU//M/nf4KYRWNdwUirBLfeGqxXgdZFH +9mDPUQ4z6WmHHr3T8a0VqhMnAY9JZPZWtcaMhdhuEyEt5JTTJAmmO/m7cGRh+U9j +Oylxf2Mb1LOHffkW1XhJrQ3bDYFPbrrvddxJb7fYr43RlXkG/NtCA0CR7fzBlhtw +oML9Tv6EfavyLW/lnsOYIqZT3EexL37fh5q/U6iFfb2Fi4yP0ihSU9TcISR8bkn0 +`pragma protect end_protected + +//pragma protect end + + +module `IP_MODULE_NAME(efx_axi_interconnect) #( + parameter PROTOCOL = "AXI4", + parameter ARB_MODE = "PRIORITY", + parameter S_PORTS = 1, + parameter M_PORTS = 8, + parameter ID_WIDTH = 8, + parameter DATA_WIDTH = 32, + parameter USER_WIDTH = 3, + parameter ADDR_WIDTH = 32, + parameter M_REGIONS = 1, + parameter M_CONNECT_READ = {M_PORTS{{S_PORTS{1'b1}}}}, + parameter M_CONNECT_WRITE = {M_PORTS{{S_PORTS{1'b1}}}}, + parameter STRB_WIDTH = DATA_WIDTH/8 +) ( + input wire clk, + input wire rst_n, + input wire [S_PORTS-1:0] s_axi_awvalid, + input wire [S_PORTS*ADDR_WIDTH-1:0] s_axi_awaddr, + input wire [S_PORTS*3-1:0] s_axi_awprot, + input wire [S_PORTS*ID_WIDTH-1:0] s_axi_awid, + input wire [S_PORTS*2-1:0] s_axi_awburst, + input wire [S_PORTS*8-1:0] s_axi_awlen, + input wire [S_PORTS*3-1:0] s_axi_awsize, + input wire [S_PORTS*4-1:0] s_axi_awcache, + input wire [S_PORTS*4-1:0] s_axi_awqos, + input wire [S_PORTS*USER_WIDTH-1:0] s_axi_awuser, + input wire [S_PORTS*2-1:0] s_axi_awlock, + output reg [S_PORTS-1:0] s_axi_awready, + input wire [S_PORTS-1:0] s_axi_wvalid, + input wire [S_PORTS*DATA_WIDTH-1:0] s_axi_wdata, + input wire [S_PORTS*STRB_WIDTH-1:0] s_axi_wstrb, + input wire [S_PORTS-1:0] s_axi_wlast, + input wire [S_PORTS*USER_WIDTH-1:0] s_axi_wuser, + input wire [S_PORTS*ID_WIDTH-1:0] s_axi_wid, + output wire [S_PORTS-1:0] s_axi_wready, + input wire [S_PORTS-1:0] s_axi_bready, + output wire [S_PORTS*2-1:0] s_axi_bresp, + output reg [S_PORTS-1:0] s_axi_bvalid, + output wire [S_PORTS*ID_WIDTH-1:0] s_axi_bid, + output wire [S_PORTS*USER_WIDTH-1:0] s_axi_buser, + input wire [S_PORTS-1:0] s_axi_arvalid, + input wire [S_PORTS*ADDR_WIDTH-1:0] s_axi_araddr, + input wire [S_PORTS*3-1:0] s_axi_arprot, + input wire [S_PORTS*ID_WIDTH-1:0] s_axi_arid, + input wire [S_PORTS*2-1:0] s_axi_arburst, + input wire [S_PORTS*8-1:0] s_axi_arlen, + input wire [S_PORTS*3-1:0] s_axi_arsize, + input wire [S_PORTS*4-1:0] s_axi_arcache, + input wire [S_PORTS*4-1:0] s_axi_arqos, + input wire [S_PORTS*USER_WIDTH-1:0] s_axi_aruser, + input wire [S_PORTS*2-1:0] s_axi_arlock, + output reg [S_PORTS-1:0] s_axi_arready, + input wire [S_PORTS-1:0] s_axi_rready, + output wire [S_PORTS*ID_WIDTH-1:0] s_axi_rid, + output wire [S_PORTS*DATA_WIDTH-1:0] s_axi_rdata, + output wire [S_PORTS*2-1:0] s_axi_rresp, + output wire [S_PORTS-1:0] s_axi_rvalid, + output wire [S_PORTS-1:0] s_axi_rlast, + output wire [S_PORTS*USER_WIDTH-1:0] s_axi_ruser, + output reg [M_PORTS-1:0] m_axi_awvalid, + output wire [M_PORTS*ID_WIDTH-1:0] m_axi_awid, + output wire [M_PORTS*2-1:0] m_axi_awburst, + output wire [M_PORTS*8-1:0] m_axi_awlen, + output wire [M_PORTS*3-1:0] m_axi_awsize, + output wire [M_PORTS*4-1:0] m_axi_awcache, + output wire [M_PORTS*4-1:0] m_axi_awqos, + output wire [M_PORTS*4-1:0] m_axi_awregion, + output wire [M_PORTS*USER_WIDTH-1:0] m_axi_awuser, + output wire [M_PORTS*ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [M_PORTS*3-1:0] m_axi_awprot, + output wire [M_PORTS*2-1:0] m_axi_awlock, + input wire [M_PORTS-1:0] m_axi_awready, + output wire [M_PORTS*DATA_WIDTH-1:0] m_axi_wdata, + output wire [M_PORTS*STRB_WIDTH-1:0] m_axi_wstrb, + output wire [M_PORTS-1:0] m_axi_wvalid, + output wire [M_PORTS-1:0] m_axi_wlast, + output wire [M_PORTS*USER_WIDTH-1:0] m_axi_wuser, + output wire [M_PORTS*ID_WIDTH-1:0] m_axi_wid, + input wire [M_PORTS-1:0] m_axi_wready, + input wire [M_PORTS*2-1:0] m_axi_bresp, + input wire [M_PORTS-1:0] m_axi_bvalid, + input wire [M_PORTS*ID_WIDTH-1:0] m_axi_bid, + input wire [M_PORTS*USER_WIDTH-1:0] m_axi_buser, + output reg [M_PORTS-1:0] m_axi_bready, + output reg [M_PORTS-1:0] m_axi_arvalid, + output wire [M_PORTS*ID_WIDTH-1:0] m_axi_arid, + output wire [M_PORTS*2-1:0] m_axi_arburst, + output wire [M_PORTS*8-1:0] m_axi_arlen, + output wire [M_PORTS*3-1:0] m_axi_arsize, + output wire [M_PORTS*4-1:0] m_axi_arcache, + output wire [M_PORTS*4-1:0] m_axi_arqos, + output wire [M_PORTS*4-1:0] m_axi_arregion, + output wire [M_PORTS*USER_WIDTH-1:0] m_axi_aruser, + output wire [M_PORTS*ADDR_WIDTH-1:0] m_axi_araddr, + output wire [M_PORTS*3-1:0] m_axi_arprot, + output wire [M_PORTS*2-1:0] m_axi_arlock, + input wire [M_PORTS-1:0] m_axi_arready, + input wire [M_PORTS*ID_WIDTH-1:0] m_axi_rid, + input wire [M_PORTS*DATA_WIDTH-1:0] m_axi_rdata, + input wire [M_PORTS*2-1:0] m_axi_rresp, + input wire [M_PORTS-1:0] m_axi_rvalid, + input wire [M_PORTS-1:0] m_axi_rlast, + input wire [M_PORTS*USER_WIDTH-1:0] m_axi_ruser, + output wire [M_PORTS-1:0] m_axi_rready +); +`include "axi_interconnect.vh" +parameter S_PORTS_WIDTH = clog2(S_PORTS); +parameter M_PORTS_WIDTH = clog2(M_PORTS); +parameter M_BASE_ADDR_INT = M_BASE_ADDR ? M_BASE_ADDR : calcBaseAddrs(0); +parameter IDLE = 0, + PORT_GRANT = 1, + ADDR_DECODE = 2, + WR_FORWARD = 3, + WR_RESPONSE = 4, + RD_REQUEST = 5, + RD_RETURN = 6, + DRP_REQUEST = 7, + DRP_WAIT = 8, + END_WAIT = 9; +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +f0DVmU/kdU862C3ryhjQlDsM4c/0bG91GM/Tt0YfOziNIhVBbdZsoYW2RTSSEC81 +yNXUBt7tFmZq4YDopiOye7MWsFmf8WWRQEL3slo6DkYqzPlqCgnjys82AVws5Cco +WGW89TXAcQAYHJy7oG8Ae9oSMdLa3PIQNp7mSA6rz4RhAKHQyvxQU3wr0zXDmYKl +CeyI1ZIu155HAUZL2bXguauGtJWtwaTXIrQO4i5/hXied5l3pm8lCdXsKbM1Enxx +V3E/sk/RBAVETx2fmYxracwCdN363LHRvYHyP4b2qkmUndhj47mK2s4d6wc/G0IJ +HQRhooSUf5bQscVy4yyOxw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 24464 ) +`pragma protect data_block +VTq/qeL5rbYMXcLz0pVnq2QU7OySLW7WR1ySFBochA6uqctGyUZMjS/Pnq7DeDQA +s5ClOKMV4s33FMhzgVOQol94f7qpRytPtHwO4wJfN4F2g5QpANsEk5OSaLDZaL+T +9JNTHQOahODVVMjsEwLu3Hf3nxQqnUpY1Jq2hY3IPT9HQw+jYUbU1mwaaPtk3z/B +wfByi6gTuDXLRhTsDy9zF2v2hyVz2yDuu+x9TSJkxCf5Ivowir1LIvj5/3PTq70h +N6f3RfvSBCkVywuTW3T7/OhSi8wnLfdctcCOumE1svbUYFgxg4J2eKZs7MjC0kx9 +BSZcpQPmbuAEPr0X4s1LPhIA3vVVwZzzfsgimy/Xg5Jay4omrboBZMNf9zoz/upT +CWeKBGZMPg7uyDy+H3GpdRNVVeOleOFSVrU/4KbsSuM7/fgKqbwL1vbL3FoZihPh +ldxqCnYv2m//sJpbeK3FtM5xLVdzq8u7WgS2RNd0wbzqdcIbA5ahg4/wV5r22Zo3 +pDP2uVlZvB4LOCQM7VnNmxqVSUNOdZrdkfxscccugLwsZ/LRvxbuw3GVqzFEQGGl +FBnm83T00BwwWMh3yKaRmz9mYY8xXcUOaZ9cgJpRVvfKPq/yHCtnHgXpEEkbHFoC +p3eSX44fIQ/EIHBkJ6jvFyA61OKdjC0gsAj02XudRxsxq76JhRuRBETksNXiKo1k +txGlub+1WwXw3GYTDyjs23iROrf853eo1PTW2BocqDzdb6AFB8CkhQIM8lKkRJFe +Ud9XaZxwtPRYYuTWsJtwVM4GEj4CNvkOejnOgYU+YDJdHD8rTmdzTqQSwaPArCJj +kicLoihoJYPKvESIM+dRDHUXglXu0AWXSDZW7jhEcQaABvy+R6uR8NQoRwCnDWnW +9BuJ5yWg7tgdBHAcTw+zIT0yNPFPQ7yHxvcocbKDsAD2v5fA6rCKo04ExCwzGjvq +VPziGDSWQpMeyWZBl0bM8ImBRJ4NCkQLZGbWwqKCClyuTbIrl5vDQWa7RFLhz9sX +7UupGlRGTMLCeM14MqNak5fz19D/+5RGFM4HgBvzEteBpWetcsTRmDKh8dM2eCkF +q2H7nGtUT0YWjVcpkgPPJmcicdlBjkddEklWnmq9D6cnsaYNoZpNgd2vYsWUUuGC +OX1tPxXPrpLFmjWWv9S3YBktM3/bRdujZM5UsMrjh1IVZ1kIkM5NM0H0YVlE74ce +6+qAltkGjRI6dpaFA+9yuH3125i170IFrl13IiBVpBn0TX9ISHDm/IcTOvwZ6wrw ++Z7v/7ABM/hcfwOpdqUsmRl9OO7ZYHEVkzHf6lRJ4reYZ7PzXV1K95g5GWTttkBZ +oGsOAbke+u4OGduinSCSzl5voGmnEmgQ9Y+D7EEWDSS4D2B27QDHFVoJFIq+ftDe +leGgihAqC5W6p54JNbTrp1GmpIYTxgcgeVRzaNAPJ8brqHqyMSGtVIRZ59+wLNzR +GLResfaurHLA4yoUlWQwG8SQ/9m1x5Vvc6kW29v8l4MG/xAfKepI92NlD58wZAhb +iF38GP4nLgsMlWX4E6oF4fWEjoPEhMYC1fR0WCYhjQxdgKN1bHf1QfRICVqprKxS +jlP+XNEiN5RIGDKZZdbmfc7vyrfF83aWJU4joLW0m9+CMgqQIXgt6AhWfNWLVIJh +7oN/atW3Gk4rnvJTEa1NKo5e4GdAkjnd8sNku3c9tQrv7oLat7/6IzACnS7wPBr4 +kVbbEHMj+PmXbrkh/0sHfGHRwoweEGBK8lyXQfwoTzTxNDrSIUBz4+7ZsfkINpm9 +c6pI5Tv/jhvN3OC6CcZIcl1GYeKjsPKGBcmsxYNz7OKvvNz+0V6gCH5tXP+UonoM +jB/lYcsNyM2cqT/SwIlgWZguseIUmFR836ZLBqXkUVOX5vsDZryDrwZdW2qhHq6W +sqbaA0xn6pIZNo3ma6siY4TypA+UccgnQbIFxbAydrBt/ywzAhUFaCzTxv1JwG+S +MT8MoLI88wtpgGC+lbXNgS46D0Jy3uGZq6A5yBgLT5dwgYcP0M0HZjkThMozilEJ +xjRR80RUWZriVvU5QGBEd8/VgNnXdZuFHNF8HthIpgilAvF6kunsQMQe4yRGMO8u +FOp4ZXUQbuG00EM2vzEygce9HsiV6hIvpb+4M56JimSJgDP9ptsRuUI27VHqRVk4 +clLj3Vz78fgBb8TdKtkLn8mvcSgO8bWRFCBCnJ43AQry33aYGKs7KWUg3/eUrp0H +m8hey7U7tlD7nMmk9Dj2iMFv7nFOix5ISillo0soQXHWM1t2SAYSRYyichouZ7jR +ovIzBQ309elW0QQB7yQQLQ+XJ1EikMbvk7JLL+3ki5DHnerAGC0qZhfbYCoOZZ/+ +KLyQ0tsBmW6IyF2ey2NS/kMlp/5hub5DS+/SbamtpcxJnJ7Nr5VCISSSQzEtVAPI +MuJged9xjFdn0skx5Go2htScK3YatwWCbsK/lOQg5kZW2y+fObgmvLpSpdYKcE9o +jDrOIltzjsyW0Am2/mx9/90d+dehI5gKm/RqJrasmMTpmW5RIeXMutDy/HNAhNPv +lpEyQk5MFkL7x8+mtRQC2j8+p1JPzrJ0r7fJUb1muZQo866PI9Fe3L/48cruk2q4 +O7jAn2I/PFalXBGjFJVOt3MYb0GR/Qspdfqh1gCmMB4AbadW+702rfWcg6/uawog +InByisqiQi+Xrxl1XAqIOJn7SG1fOW3xGbIspRyODQuxY/+uPysZIacG7FrcYHzm +mTGm7bBoMMXdPjv1DZAkW2ZglGTWgjG0HXxfkHYoZb9ptYbeoEey6PrQR6eMSRe8 +ybn/GMG3r88pXpBK5h6hHA2+YScASRvBsEEUBL4J4OiseNY5JtjlRm2WEYCm7dSo +id+762nqI6ACttJpPIIVSFUYfDNpg0pAjEAcYkaBB1Zinxh4GS0yVIN8/4qjXbTX +PAQY+MkVoJDUoDVk1omrrZULwMs0DsSciSpczKBID950CnZSzlOISbSfEtDC9abX +P/SMOjA/DbIuD85OEKatfj4KsGnFbY6fNx6TE3eKVjdkH+K646mHzeE9vpmxrx5p +aHBcfsxn1C6w24vaLtCk2fZjIFpN9pMqYQE+BTlsGqTEzWOlqRd0rY+f5zltKtyF +Kxv5a9gnT3OgAfyEcofdRgkJvBAy0zi4A1pm6OHr7FctQShKq5NE9gnkGyy370et +X4xysoKnUb63dz5qHVbYiZOmDqnr4Xt8G/vhiUJlQTNnXPMz3juQrRKfPeJd63EZ +THahCZjcKdTCx1H7zKe4/FvEZsQda37M9sxU6IFiJY5cpt5qgSxJFh3ICwS+/ne/ +Iu14O4tQ2GbJ7mgaMYzGfCvuIgRw7Q2WpU9qTLDRwunZ63hD6p44PGnMVpJHNI5/ +/yR/yHinCR/vWA+W/hrQbu1Cqc4y7UxLLhxeefZevIflStb1fa0A9mzcFxEK7zes +vJRlE96crEI2V0nMOkRYiPEbgLEXqC805NbJjMIdVC0cC3epVKVFO+5gwzsmhjsW +ssKtEKDLvvdIYoOw0r/nXP+KKti5YmQyNvboR3A2fEUqnNmVe5OyUEDZIaWcv7e8 +PQv3RdCMTVNvluOJvG9selH/Hq529HdEbZ785AYjvsyq+tY3ymONM78uwprbnVW6 +U63pcADFtSXZSn7zWg61ziA08B7723CER2xhDSFYS+5xcmtnGTLZEHm+WHnsXKMB +4vBkyV3xLjETs6+I0wKHHcOPryjhLK+A0Pxt/TatVtWvTgoGg0JKhFwV60gsHqpt +Bv2VnchCPbxWjEm9oxXscgMtdZpd8EBc3qSxxB09Gbaf3sOczqq+MmJcT15GGvPo +16Otm32YxzzqBI0/V4HqBDztBvL1JHB0rmvB2G/9RRoSmeKms9d3pDy9+VbMXSX1 +r5/SQl9m2O9UgtZLBr5LmYJTHvkbq53bO6d8N1DDawV2ghF/MmzWG6uajMu5Rgor +8yAh1Qy/tVwtvH2HMS72NLRAs7Zts0qHzX8umxDV1Me7IW0tUA+VXalPh6GI+xfg ++FXEvK89laFrnXjbfDT47Z7fh2RcyOhRa8kcl+GvR3XeyCsaFGbIuyB5bfXMqCIa +SN9DRHk8xaoJj/Fw8fU6KEPtWXV8S6cPgk070FkIOHPM+IBOYeKgQjgvwocxCTka +dWv3n66qjLjYMGizvg3qIJ5+Wh9pYoPRdjawbX6gqwzrVxgOpJbMfZZy+hrEuE+W +RSTfsviAjKjBMvdHHPMzSwfJbuFBUzhwUL76GNQ7TQqeoBjilL/e7UpqEPXnAMIO +hIf6NqbZOo+hc0jkJc7H7kjrN8fG9hWehR/qr3AmdtT2QAB2eFy++TP5Y/8vUT3v +8CdXYU3vzRR842F9O4qEpp0QVYPJV4WLYUoj7Rln+4hcF8m3r+Cn5h+uVVC+67hq +d84x1PT+Y8klwk2EEJ0VXPTCwoAFiJ49Zf6nQ5/iojmUlT4huFlD+072Uh37fCzs +OBXGSQRVTRIeXRYCUNuWpclQF3ucc2due/MsOOgZB/jCsviZh9yztBhCjKDitH4v +/+E189WTtLhC0euW88xMHdI2sVOy99EgbklzlXkuSVfclhKD32C+VT73p/borAbz +E2G2oEsuRsN/VKRVRtUStQCPDlyrZjff4MndgdOsTONUwcTWVEQiyAVljs8xkHr4 +YoAVmlBUmCddw8YWmedfS8yAtNQ8hx7jyw5txM/6dCY3ggn3cblrA1xU0GxW9PVf +y/wGfUIE9/0M0OBtj/UvOK1R6ZLxahlctNdlR+7/KVN7S9O15NdD0ey2hYDPyrxH +BsPYzUm1AFJL8O5fhCKJWI3uVJjtPQRerrXGmVRzX52x6xaOGW/IkjetaIh91QDq +PRaz0afy/O84RtsoXEIn1VxxOInJ0wtOIOT7nbq7zE1usua9KG9wqHFb/Dlwz5pB +wpEkYN98cKg2VQcD2sc0MsBHtPkw2K9iZF5WtLbtYplElx3gGvkf7gjEJoxEyioj +i9S9uQuXy9yxTHBy+0nv6EQYcntasu+zJQ6so2bSUfRknjSdYknIt778lkycZ9B9 +n20iM1gHtSa9RNoekEsHbLzYaZx2GthK4vBLc6BMmp6L/hg3qlfeNULjUugI1QEO +M3Tp43ax6pV//6cYAwfNOVtnt9LRDtbMvRe72+GziXt516I0uhWba0M4gTcGWnEH +97pINk4TPzBX++2ukKHeFkayTdRMpiOPbjeSOJH93KwCR5hxY/ZAkBo4eOUx98lI +nlhS3MqdRzbd3eCPTXuDioQJddlkU95EPLXHxGKoJFhfFu3FSNQJWC9uRk02O9jH +cve4D5A2YfjhspJQg/v9IDiV8i9RK0oPt1x6M8z/JugROF0MRGIG2fRjS+6GM/xt +z/ILPxS7n8Q+ONg0NJmx4r1lXwAjtfTQi472EKloBzCM/U5wqLFR+ODHXniTqisM +OlEdHRSiVnX/kJPOf56LUmTS341cpWnHE0hcl5e+dtJoaz4jBnR+b2kA3OM+Quer +DFCVBxd2heZ60FyTFOp7SmnwtqMcA4n81KLjwluK2/2KHWPDDKMld5UWw8h0aaX5 +C/vmckob8m+tEUI4KvIJLvjLDlvkjVZxCTbw0Crzq+S3PA3uu74oaKOxXAOHLpSY +T/18dhYciR1FQC9tPRYRxSnxr1YBr3ZnY/II2PwcaoZc4d94fPPRWPL5x6WQp6fn +4dKL0rK/VBEQ4brinLAnYaE+OTsTFJpnzjQuaxohT6qFUoZjVEQuVWkGMrXTMI9N +Gw4jFRKK5B3+/UndWXPIc9gx8r6V8l93NippLEQ2tL5Ld+Rb83n7nSQKLxFQHaJV +Fg2Ramf6f1UUhIH98Z47a4iOjD5zfYsWiKkiQjIuLEo3VRGmgiixmfAOzfklurYQ +pA7QopglnZLJc8uQ1Q8VPP28QomPnEz522sW9irX186QJhgfEXGrif6JGI955SZw +Gzki2XZV9oNqAwB8K+Dr65Ae1weafkr1deROfiUHT7jX81s0mCOh1X3KmJaH7Vdq +qsGfj845Gq9aXJBy5I0vsZogtvafGUpF7r9QS8xS2UM/aUBZBEh2pwkD0OgEJjcH +rV1fTOLCw58ilXmj6dMxkvNqGZqyi/kMUmPtvTt8c5Z/TAdAkKfQnwMlgZoMr0zu +kOcvr70MdkDe7HiwMj3x3GPmcbRTfdu/lFwqCoo6DaXx6V6+ty6QoNALBtlEB0NL +y+1tSTuX3YMjZck/Wz4UB2XVH8iQ5iXFZH+rFGB2cKTeYMRfi7nN6dGvwQSyTTH6 +7slMZO5JQmqw0FKGOg4EqaRVd+NRQNRTTw2Oj8Pir4fuUkJMrJ/QSi7Sb7HD0jcM +Z2GMVsNZZy9MTbKACa1O0y9LF2pWKw1c0L86s6icApuLzr1CCM5PSY8TzuBLI5EB +/zPogXHR7yNeuKS5gtqbEUfOaZLXVQWX99+wmjD7dl6wqw5g8N3S+Jh5jWjyEVvE +D9AcBcu7XWtlzzSgBN1kQpi9zd3/2T8iuYA3globfEs2jkv+N0cINcpNQzspHLFV +bY2wTOk6detdQlkXR8TIh5CN1LaNkNpxrgVtq+n2MBkC3+Y53WjGeG7Shwt2gxtP +lv3mVCE6B0j8Zi8Qusd74JUl4sdwgG7IdxnOlbUh4JnmdlAXnmtj01LwVZTQCjJr +dl7JwlV9szhW7va8d9iBZwefCaZ6uJqu+Wu+6CWGam6xYy9DqnFB6ys2FKNjp8z+ +RBErmKvnAEEZc/r5/YBACuaVYGzr9ak0JtFigqI3EOXDgm6Q6kAFiT3DwILQKjB+ +XNOEDkUwv1qI1ozHH7FB2MCbKvXyBPselF57fTDfjsz1AftaUTyZ/67CrRnGks+z +GF/F9rsM5oSQUrRnHeowi2udmiW9D2B2vu3zBi/nkDRyQ517G3A55uA0Pgkqo6Vg +za/6c/4PWgn2GpMyFV5TU9kxQuZLfJrulnjBUxYlwWtdMr+cOVQ6sUJsY5GTdrj1 +qmitz5CI4xqj6+RIHPPIJo2RrxM+4hGHefEAdE/519YJuXRyvn7AwNDlbyR2023g +A5yAeHMVRIbyfSsUK+THe0judO9hHUxQJaXXpt/ROEKz4zS6kKb1DRIaeT/2BXkt +c8Z+hdCQTP+zwiihopr0U1dJYMaQwrBv7NqFjQ1snfPGDW3VFRDGfdQnTEsZVhyE +EPN5U9Kxt08C8moIxEodkxfl1I0pRZ6+SPngatBcfynJ2U9igp4Zg/rR0at/3WxJ +rZsFHAdDgEVkhOizM+4/6Vflyi2XQ7OtHTMkbc9Rb+ta7LPRtd/eSzm2r0ae6qHj +TyaTSB41QG4fpBpsfaEw1iy9B+KBNcgiU2S6tfKR+ZzaKgKOCgjCP6OChT1ZD63t +EJ08t5nPhPaBnGg6XJ0q4q4btfM+9PUOY8rYPx3a0RQm9s1VsFk1ldN2psrEiR+l +6l+W0he50lBg6Ov9CfAdOpwHJQnwbUEWqcbrULGO2TbUj25b3mghCWwyazzrHPi0 +yj8M4moWe0xJtSabkNcK/uHN+WAhblqSX06ldUij9+PxMiALfB4tvtGJe/6DJyio +E0sil9xIK/8tWcDVYIjYkFU19tlZGdDxJqo7MQjaDYOECiwX6DYRqbyKCszakypY +58i8Klxgojkwl2qkC1QL6ozvqwNHy6p5sUzScmACsk5qMD3He2SqGlsxKnWPtZOu +nLdQLvW0M0O8HrRamdjIOwgyj9ttDARrQkyLcHdWp0Rs2RsKrDYfMs+5gH8hVVlI +gkpfIWEuOdWM60nVvofgn36o16EN9iptow0tuEgTVcamTB5VZLxTAf1t+SW2TfAY +Vd5L1mbtNB2S491sN74jc8MqE7n55/lx7tXdP7KB/u6XA4FKsHm01YplT19YKE2i +//595NRPuurUdczfnnq2N0MvSOCCuOJZ1JVca1idZSEUQEc95nbAw/pioz6JP/mp +g45sO91YjcA5Hoxxrd7YYmaWdu0CdK7uPVdUkd4JATPFoV7Kbc2UGTaV1edC7GrP +d6bxGq9CO/17xu0T5UKS5HPZZ/EnvPD5l/GPA5n7scv6cfgKlMMQljooZfXMxnGV +o/PSoEFK/fhhy+85rkkPLaeP2az78T+alvfd9G4GOsPNlichIagz6aF0dP12LJuS +k5aKn+a3zqexr4Tcyv7I3QWXMh1irXfWznC7+APOdp/TTiHKtg11MT89Hti2r6rg +CviyLo9dvDvu/NhwFAT5lRT/5M9R67cMbx98Kk039bk+sStbKIWrYFxJdaVB7e0g +/b76mRqEUnsb8ixUtPzKCuQjkbnScc/tac1VN4emoVUVhJBwrUGcNv1VU7HRA9gq ++Z44uymsl957AhYc34bqrmbbAHDXmog8k5n93UlFwK83wDiweOOAxfGrzJU5h7Bl +uLRGtIc+SSNP7/xe1UijoYOSrIam/4P1RB58+0pUQtkzd5nqWXo2zEXrtn6qG8lu +r7om5uPdw92Y6W69P685KVav6U71t2NCtccSgF3NXCzRZ836YrufjoYzu+SFaYAE +SIX00EYlyn2UJuXzjOJmSQeFpDeGesFv5aaf5ecPGQlg63a+fAiJsz0uPf463K3Z +A/gA2MVuxTYhcRNYrq6221Y4uk2vDwATItHB2I/d7Rck2zGq+JnJTgs75bKNyIdx +ZKOoFddZQCwawdhoFGYPGw/1UBeCYlJd3UEXJv6/ZHL0I3rPFWSArSzYrrfoho0X +AxDgzkLgoKqIwsO+3pG4R9ntgWD18YBjnpTxrBDe1m44YsNwWvowGaX1lWvEfTPe +6wyFgyotpNFQu5iE9/n3UQ1S3niqHWgDXAYX9cAT409jK1CkwSjMh6GwnHXV+6ZP +SBoE0QMq20f66TNny3Mq7lbHjQIy2aLMdh1bF71Wi31tOtZd8ShwY7yF7WdwkbNR +rptvNdpypf6W7RYdI/bewh91pKDHQWRfF6rqDM+swkRAwXEMw3P1IF8uu4QBb1gl +hqR83c2ARzWF9DavjCMHENeDV05bA3PnkiqNFX0zJRZWlJLlc+eI4fiPTBv/ZE+D +9CaQ4h5CJzM+MlO7RvirC2q59AvJK9xH8YENv1eAe+PTJj6kwHJPKXvu4YRh6kc+ +5EPDmGGgElaAtZVda8HVVtgZF2vV2V/4LNFx5NKKG9PWLlVpHnqM1/kyBh8RT9Ww +WPkTpmln4xLraEp3dtIZJINvbxSXfo7tPRlRreTBQzZldFPC3nntD/SWEwH43SoY +QXi+8tnwyD5NQOst/RejpSW9+lxvuA4NeNmrjD+3NNn6IY3HgiMtO4jkAG+BjJO/ +0kcve+4eCjjoPID+Nkgi3MiABv6B+39tbBgWRYxYEJn8QHekr3X+Sn1y8GE1QjtX +VCrv27Wi7kcK91iiL42b1yH/U3q9DqW/vpB28DsUWUQBzrGGTBlQIwLyhxCrxjrv +dfsLom+y1ecpoxDy62iGGXNGqDylqBPDBDPYUmdcGFlXxzpLjqY7iBNSOtkdXoGl +LOXhBaBA/U7aThDUreSbrb0VFMGxFW+RNYy7IeOVdMru11xYPqJ2kTTQ49ezHM2r +B+K+2MBH5BsW1ho5TK365CS64BuAFqvoiojn0WTd954RynB+n46s+zq0niuY8UpY +NLjav5ZSmG+Evqx51lEXNVqALpU925chdx7bPBnmSSuX8d2XCeDWU7WmfUquLiZY +5IHKp3Ob2gC53V57IB/t4HOFhXyErIznwT8thhD92LFfDJDpMthmOcuCCuGbaiX0 +mC7K8Z2JexPu2dOs5fF471MPo3J6JC5zEungiQIeZ22PdJU7P/1qM7sOApQHBGVP +Q6okOaDrl86s6b85PJMLd/SMRhyRntp8ZxQ4Crrf48jx+Vm8myKRrlJdEIYIO7Zb +5udFlsnU5EX+Mb6ql7DasT2CP+zIVzQbmYajVwk6vp92ts/6mg8cElPSWmhFAFfP +OUWaSECIO7ar011Kd7ckwzT6y98Vw5Y+0V3bUJO0F076JA4AWUQdEo1t4TYfJfqn +yzlOsEkyCofnVVzSRh8DWHJzdjkAP2465/4alajYgGyUdmkKxcSIapXhKBuwcaDw +C8nCZocdvu2S8DMLXD/WeaSQWXmRO5S/so9cLarw486leQIUqacnfHcmhWUHXy0s +e6BLyFjpOuTDKG3St/gwePJ24ZL0CqeKCbV1E+i0ZCAQRm+G8N/0JpaZcb4P7ghr +Syprc0CcWUK3faCkzPm7oZEzIUtkKhWf8B7v2EAlOQqMF2tZLKSMxNYa2hmNVxYj +4hz2dw3NKjfIHBGKP/waPNlgt2RQMpznQWssL5CaoHo2B/dLgqH4KminZ1yzHkPa +XEEerrmCJpnFkA0h+olkjd6A9ZFxrcyFolp88sk95+eXH+hfjt6xdaw/AHaXtO+E +TWy6i+7AkO1EsOOEDQgPTvsL+GuKFBHcSz9TKX8jfZFlhtYdfWl2i/r+sBmbPiUo +7EqzuEMF0npkqb5BoLSMPthVz+QNYGhkfPnTKgX7e3rT9LiydzDdP94hQE9joLUp +cXND2mZulmenF3dSmBlEkjLTvxVKZXgWBxkjyJX+zgvZeg9L5rWxN7Fyqqy00JD6 +3bNgwu9A8yh5TD97Kg5QQ1Vt6/NcnKNHKYK16g6/PWGkIsAC5/AFVByhjO05YtyZ +TAOak0EMWMNQhKw8ootYfcDsDfkKQQOAW9ZcC+DGFkfrtbeTT3tidFxac3X9R4BW +KgSVJSO9BD6aYfMys906T2cQU7s/yVC3/4DZFqeq4sQWGs8Z4AsgEr4DNZLomqq6 +l512KarXXP6qrJZpbgu4Ht8+ysH+f3PfgHHz4lSYz0tsLYVa97MZ3aspn1hEHjE/ +Tk73oYtPquDuOqU+gCxluhfuQvdq0AI2uCl+RDrP/3IK33jv3mSxC6po8Gvds48/ +bSYE7bzQFKoYDx1RPZWiJK2WcmXGfSjLyP7D1sRpvlqdcm9SeUZmfrq1W7Moqwqp +6Lg3KPzr6jSQkW0hfvx1oQngzPlJtRuOeBX8HKzUTpvaySrXMVWn+kvC2hOh9XyA +Z/Pmp4mkJ4vV0FCOnMTQSnXYEbsB54LNls5FN9Ftunqmg5XlGtIokBlR5NkzA09r +nCFmCU1vYdQJAhOkMPVlqqyi+/IEsib7X5/6O2Qg9TO/I4psMZmfFYMAjGPUltXc +pmHHfdefTm0EhuTbTzQeSiENTrAa+/4G95XMz3B+BOPWg+BSWKth+5mgSLhHXHIv ++gwg/Omo0zP9saECTaELZpcoRQrA51R3zYCBCQIJKlg9Gi9DxeoOk87oUzlBaeqO +ljwYg9gcuaaaD2iyHNZIp32mHBiU6Krgx+aBKdiKrfDy8gm5LgNiLkwi7qzUyqdy +i8n03HaTLfSOOoK2Abygb70nzuQ8cHnJHWZNt12pGho1QRmOJH1ZcC0XQaCwNn0v +q6n+RO4h8QG+1HSMLYP7OGaxawED69gZktdDqdbDWtnbk/E4NVR5lB0OhWAtvCZ9 +zDEXZshScSU+6erzyukoXvVfWsKAKNTDQvngaNbkIO+r2J16R5MfyiTX3oUjzI8g +JC6byTRHwcBdJW2NzvzewKvFDnwrQzNE+DwOt43oiU13PVPLW3gAJ3xl4GiI5O1i +njVyIfP+ftzu4JMBgysK4g18M0sz3mWCxxMRQ7pqxlj5wUt4LHRG72oBjYG19xEK +mM9vgeB2oXaDxlFnBKoIJ3cdraczGyxqZajBI0SCcyTyXifdg1o6pM4FJjCSHBxT +7sgVqIIqwmvqOhOySu5Y8zswxttYxokcVOg6pegR0y+ZO2Z+/lHMFCbRjoIOtzuo +5PX2E94FrdjvCskaOZGwRnQRMosbBkrcFIxPMI3IqYTvPFEEY+VIg573vdr2Aic5 +QiONULjjFt2QFzkwOIFosxpHtoujpQqLNA2QMj1NObsfJnxVxtjdYxUhN1hBEAB/ +oTUTOXvASnjjX1zWZE10tnWrY7CQaAPlTnBdlZ60UfDaWC5317uoubV98IP7LsiO +bysdmfMylo6EUvGWKWs1uHMU6pKOWMGQGr7eKBkTd1GFRSvPcwCI/VBgNsFVKDON +5nuMYsgbvKEUw2ZU3JRlUuFkhbq3YZAKfw58zvrTrZqioV10frAE806FuoTsiKDK +8uKXUemT5nfY6ln1uGOUggdrHkFG0NMOc8LEju6dGg7lZGkb4DSDSsZ+qAejkYY8 +jnRt6FuaSceCLUq/J0ErevhmfHRD7XpUkkfH9Bt/7PrC/vJEYWXA+d5HyQBYiV92 +AREcRWxvrmzBJ6icmitCoiITq5uByRQR9Zon1hzcPUVf6yYlI9zpnYaQ89kMQpWp +AQwl9oCpeuXeX1h+2euhZdEYpxTeHEirTQSrgkO9hR+e4KGD5KirUrXWJXGcw01+ +F7RHFSk9OQtyRJJYRSN9wHa64oPfCOkr5SWu1ADPxaksYaRgw4DqBZbsv980Eyes +6wPqMmKMYfGVcW0VnMZEhg+aCN37Eai9gjR0ScKhbuhMUhgn41i3criLcBanbj8s +YIQGJaIUY7kXT3QmxdqierkW8f/STrHyfEMDVJieEWWSdeksbgg6D9WCLK0hLtVp +60YffjXUOW/UaZMcG0jWgoN251RNPRXQAmPHfEJBF52q3P7gyKez52R2jWIjtxpF +0VeyyzSnR+qwDYGroqgW0IsUZyUWwALNNVeajfbZDzA7EAXWrfYnOM8bbCnt2Er6 +EA0DboSOXPSSIOT+DPsBw7ef1+vRl7qf5CsKDEydUbX+kpAmEvksObiciTr2PlhV +VZtEwuVOpQcxS2kLUcDKixskft9THMzYxwUwp5Gg0TTQ5V+666bKXfmyMQukC9IT +MJklMKTNzuKMsp1SSqF9i+hJ82KRYnM7mps7HzDr8FbVhYWPnUUHYYESdI6m9bOt +TBbGmme/Cv0Xsz7Dek624Jyj6ATiA2r3dz8O2eSHBtnjtTzfVM5sEGm4y1b75jC6 +nGaN47Y/wq587xyXx/TO4eXWR3tFXKr0uiiYvgSyhEYTbjTO3s8WxWzV46eFYB/d ++tG4vSJ0otC47aEFqIb2EFjLg64SmAcyoZN8tDHN8DVTAhyaT/aUqp/N3ziYsQ/E +mRNfpYiSnkIpgJSnl6iIkYrtj4HczkNNvZu/ow2YHyJs/W00aYT4Ymo0l1Q0kmVj +hmIs6mJXDeCqM1EAzF2/6rvp2Et+h3yczObrS0spsGIb5bXdQJ8L1akQUx4keExs +OnYe+caH4SxaOOWKngYPUaRaGUydJ70Y8n/fNsZPpxQlr/X4U7B3rGD42RPz8POA +p/7NWH1Ipl7LAvV+VqUUrYHWh0osQOBU/rgS+M6d3YV1hlP+uYZ5NmMhVdhCTT4v +Yya3k3DXGKNwrDyBgF1xde+z3C6JkgXtKpKT9pt96mQEMRuC6hqM6IZ5DCVOZplq +u/Us0l+JYw/A6tSm8H8Vy8EaxdGwsqNz5UV/Hsj0oelhXJZFE4PGyR8kH+DEDFmr +9OJKmOtietVN+jwlG7GuedLvXjH6WOCSqPEIQJ+mAfeIHF32k5mU/L08yf0mVKcL +NES6kD1H+p4dK+KzdHPDoo/rJZWa78CwlWunn7Dhu9fpAYCjIwcLukhScmBeuQrR +aHMtc/OjgQAwjs9Q3bVfRjWvJaNJOjDzPrZEO4v0RR50onwKvN60BM5exRZpNu8W +ikNYAXsfS2cWvFqQC3CN3fblnWihYhYE8F0f5WexfttI13KRc+D6RllhYLTJI9l4 +RmrOBjF1d3+MzjHP3biUCFAR32w6NjSQq5KP07acF40YzaFD85A92nt+pTJ0RA5i +zOA+tOJbraGa9P/Soeu16riwpsx67LgX/RNt/kWlku857OK5FyuAlS62KYlxwwTW +K0WbZy4aReeoIdIty0EpAvL38wWm6PGSqj+w+J3fGNYQio8PmTljputWNRq8ho6l +PsEjqs3KQ718IY3/P+ae4rtWrBdW5NN1qVnQuZON1McXHNRbfVmLRtVyYSUxEERy +dy8ASUsTTzk97tgywQ5DZ5i8/vdaJiGZ1QnZinbQLaOd4q8dP8CGEIex2Gb+8OYk +fyXt6ef5Hsrd9LE/a1C4gyQDLcGoRlARVXNldzxCelfKeD5MZ9Ox5A5wNlbVkfi3 +rL/tS8KgW8gzLEr7xAKo4PVCn/98NeKmA/7enmlP9U5cAgTzu2w82YkGhldJKjT1 +tyeb6VyyL1TACTmMTppfiWzMKXsS7yxrXk+aHaqXzkDh1W7VnIUXsbGO+UDgUfkE +/SbEHCbPzMeE/JiojHTpgh6W03HiltnBWnjfi9PuBzpwO9pIKjzwWy3PEFbJemvt +Ritg1ludvlpE6sqAvDO6YVtSuhEtn2+vJRJzCPOHRjUhfcHu+sSUPOkBU4yPjRLd +6+7UyKAaVGfLLthO7r2xw8T0G2+/DU52YtZNzd4SFakMXGNVlyIhPA5zOuqxYGrP +FFIeche1YTgMCvFLmRjmURDgbT9dGE57FUrJnd/EQmoVoJN82i0r8zGLaPkgMbXt +gvoD3HgACf2FmOhV+05RWKxDspQCSgY98GtH0DCtRJyi51p4GbMRCilEMv/sCBHR +eyRYGrIX3Orm4yydHTeE20vCCich9ZoxQDu6ZKuWF0HN+rORbOKKgNgVRoEuRvnu +DdgTsYKLo4BMtDDHXE9J2xPDtXuro/+Jjd9/AnsJ/ZrbTVOlrdufRMPSer4o0Y0W +vwuqL7Xvm0fNBOc+BQ4aRzWajLBX5awYtF/riqkLgtNCuOiUQtipMVAQLewsmY64 +zGA5ICU1MaDUkDdRerGFX5VQP2l5kq7Z8zX3uLHlGieBXL9YOULzrEWmQf7m2zHa +p/Vp7BUhDLZrWjzC8hItRYTdaQdbQly7MzVBTvmeaKX2MmuB66q2cP4qSBmokzMG +U4ZMKU51YfWU0v+vSO9zvhIJMre2XeAPQWZPBtzK1QETVDNqvh0SAt08dLLT2YdI +Z7PbyBM6dmTMQdpb3xny72sE8c6fQ8UhFaVifwkHH28ELCYCC3DzNnlv5XdZGh2B +s72d2J5W12vZaqf3FZQJM0bZukC1fca3zJ8nU4svIr++JlNGTyqZxr6ATa5xeJ5S +fSrYYuVRo2+OZUPxm3s6tVdpcBLdQ9ydMOYNeACd4Ms5x628IDPW1DY3s/1CFgr4 +hhdTs7bGNIHAyK/1yNGvVfDQooHSH+8e80pVhg5fPmbXsmfK5S2Y5jCF9SQqPFFb +BSP/vihiws20UKgXYzEBBoGozzd3GF5qjmafkNeI/BMliHNBTSNgL87gF4rSjQbF +drM9uigPBsQxIhlDL6uPe0DKnX4yaoKfNqED20j/3qf6KLhUVO6TC5a19MtjsHfp +Y3JXXjucnYtw+78cFnvnU8QcKNxWK7OhHIxzCvULb3MRQ4F7677sznUaxFEyU8UL +HvJWJbP2pnXBZL6Pz+uHqbd5B5RESBggFMrXa9Sttvx+0IKKSsaP4UahRiBdeAsd +OmPFFSzjDzAkP13guDI2LuQJSow+k3rRGONQhGEK9yK9+tFEosTrCJmG26AAOTmK +0qwP8741XYaaZXRrmVx9sNVOBT1AHtdQP0nkxBIhmdj4rfhtLvgCSgBt1m8beHQd +6Qhlfyp0FCjRW08qtHYT7l/wT/f+HXqELEiX7I8qmJ7mV2ZekW/eqB84BTBFGLCF +kx4mJ0Vbjhc5kbGbWwy7TQNV6MQ7R8f0kce1UJ3ltLIdvbfMd6mgn8elpXlewJkk +Nj59s5pRwApEA3dV572R2u5zAG6r+G0uc1w3iISuYmPLpOUJ2FvLGOXOmmrLvIh9 +dVinZ8R9Vs2d6V+XJ0DNKANhpWIOv73kEDzQHCpHC0Dynm66dF+SqO7C78RZqnKA +wjZ1JtMKEuHOWcEFNfjkoRngQn2kVRgY/f2HN5iTGfAmoQbaG7Z0qjxwpqxBOg1+ +BbXloBg8X5SCJQC7q+u8TLfWFEyjeEvJvRr88g2OreWYqnTcMACWQ8O7KwFkykqD +Y9Dl/XC+viB2AjceAgy0GKraweQ74JOtPzbp8ibTYphvOWOvXlkwLReGRSzl0Ocu +VZw0bQ+b8di9tUoutn6wEdBP8vMvn4bFXxWP5g6HL5Vtr0NHjWNd2+/hFXJJ+XRm +7pt4T36/QK3u9qa3RyRfUHo+Xa1eMadFDgs4w9QiKNrR12ElgJ1s7m9kmWhUm+w3 +KA5E9vSb4B0iU5EBnuzgtHqjzrpM6Ii9IW3w1D0FMvKgXtsX5jriSR+7QHXJeuP/ +3bNV6ra6me5tqCbNbZzf8U6O2RXHQqq5sLFXXQ5pMo0oSmOPAenNz5iGRPNUBoMr +37kBw4taasAgE2JgYW1+gawHoQOI1pl3nO4bFvUsLtPWnLQziSN2z1zPo43xbX/5 +TRrm8THM6Wm0Vl1gzrHGgnoEDqvoQKANmVbP7A89lSFRPW543DuURkuFoNLWu5s+ +syHqT5oZaJf2fgIwxZCq6DxB8HWqlHwWLsdYOojgoBQy7vI9PKqtvgLm+zfKz0Br +Rbg7Tjfb1D9C6ecPPkrf+5UXWmNlumLHmG52o7c7vI8M7hmS0fQp9jPxrHI9TNe4 +w/b8XG1LlvHWCUEUSxCywmvy5ndiCNBWeA0IJ6JXnTTM1hr3gexfmOr3dKMJerBY +UfF5wuWaDA/RPagLfoq8EAT/Tb0xDgQhR8xql0zWDf/+suhChu+tRStBB/S+3A6k +Cbk394i2CiSDn6FmTFU41Khf+SPkdrWArHFSIfe3HG/WFwncQ08H0ga8ZbZst9LE +q7TKVLmMYI/o0EJruy+z6vkknp9NbkGhBDLWHTnssFs8pozVWoyoD4bOGVdQ2b9k +WhHF1i9e9q2sYvRZKzlJXEsVTjl/+Up9hVQwKVwDthPGs5idMpGyXS7lcC1tDj9N +2pimqHtAu5hZ7MWXPXgmmGITB7xjK0GP0BSbMwIKKgBDJrpI9lwK12HzqKGHzWGM +ShIh0+GMOsDszoUi0NmP0OFNL8hImk1GaRKXatPjFB0+7dSU6p6JcXpUOCHOcW1V +yI5UViNXRv++hRb9nGQs4kh3lnRSwVTs4KiMe0e3g3cl4LWLpl+an0M2Gka+hO6P +XdJoKZJ1mEUjX2uRJc+OWC1s9KvAjQNPpUdnuBZWe5bsfkf/fxyRzM1JxlxVz+3e +1DMajfNrAz3/4EPDKVM2gwF9TCL0CmP0xkCYrp83MbzwQzu6DRmCtag5z/nAApSK +19DRC5E/NcVh8cRQCxhxMMvUm2hCoL7KSp71ifejckQbpG0XaFSslGJvnN47HvVq +nofj0XnrBRzp7967WSSplkzrpgsneyYOY9D2BaGmNg1Uj/h8d3QR/WUx4k+Gvc6m +TKySdkCYCZ52LvFvsmZDUO892Bqqi8TKzVogwYgWHIIvTpgOp7NyCQOCDXf0QuV2 +s4+frVMOYb+N87RT3PqSvXec6R9rMFmksKUJd1UX/jVfnR6ifqUmwIyVp1Hb6/8c +zGLOyuMawHKFg1M10EpwUd4CRHkIRvEFrtWpQrjQQyIZBH58HYSiIrKefwHYCpZS +HH0as5Ex2BpOw2BWWrlPKm9IrBl1LLDrDrqJGKXZJ0UEBABXy7s9y9+dO1AVxHQH +EU35Y5r0cTFcbtw9UVwJHljs2iFkCRr/mE2j2Zw0hpFXI3T8ZaB1gua1KkJQEsMk +UM2Px4wDr9TL+CKAOO75jW/MIknB3xsCMFJ4wl/tSo36U0jn3aAmF5Me9/N8Gc63 +MAG6k/JP4YCZWksT979YpOlEIO5udEupzArkmEu5WWJJIPRYGMou9hSNx//eFLVp +0myXIgOvvUbuxycPwiAdFjhGu1F5EJBpwGlgtA8cuiL/7WGmgOLWrCKOXLD9WSZO +dDx7mSRHZYYyKtABNwzHqVN6B0dydwT3KR/EsaoR2GPOmzlWCXIhCBVx3YjxEA1S +wCT+siSMoLmfITEbSHi5Sg7ESUkK+Wk7cAciaWM2VTxmTLIyXO+WsIWoRwEdL2mZ +7VuzaHr02IPw3EhPYOhitOcKSvzQv/uT4Yit4/Q7AQeKVT1yt829FnBlPwvFB/W6 +HD/RqmTFPzxBZ5Anu4M4a+o+u/NkhU5LCE+VLffzmNL8GGS1eXyf12IJm1T62/W3 +XOX6127dnVAIIYqgEIf4M4XfPQAzMt++66W5EdQdkzI2T4wKTGm4iZP2Kp0Cbtr/ +4eKxdyAcdktYvBfgS7/70fc1lowbwCHu6R+k9UQgjidZPqdHSDbl7FIOR7ErxL8y +KEcFh+7P5GJBaegUH7n+ByK0BNYPQuZNQymZJxcVeTtqcs7ODPfePigwlShn8KJ0 +aEa/aV3CYabXEM9oCOlJQpfqeda020g+HhItAmYbM/ouCPAHBiq0GAU5rrC4fS/N +rT47gkRDoVE+6PurgBINQQJDSMi4FGLvar/Wvb37u2mb4iqUf0tIrIVsl58Qj/uj +XcCBuaHuuSeYFpcfQcIQjwGFZRfurZkbYUhNxtyM5VgMaQnaVD0W/4jVwSdwiEc8 +G+B+jGY6x9xMwEVwBo0ztuIvkLYDX9g5I6G/cobMEAAyanpZ7H1Tmp0FwqvjvPER +f6b67xTpGP4eycenzQJbHusj3HLu6GWx7cOAHlEWlj+OPeskODPDrsISZvazO/TK +yuUeI2t9DJKPz/5v6Qf0z2d9jnoUy5q1lgqa2o1sZxcpy/HOfFbIUkmo5A4QWqt0 +Q2J81LY+ZKrRz7vcwO9WWGuUA9Pg1xEPDny3PfFWsfgeK6lfIoGoehQBqvdc/7tK +AOQFl90rMlsZK4U5IV8Yo2lCKx6fTkEL3fEwKTXnfqa4ZP5n8o1lyidG7DCaDyqm +JWwWCP9Lv/AnMPnFJSOlEcFuEjfJBfXwO3TofseRSdQlpnD6yOw7J+yEQWKSucoV +1/mFTS/s+rzbtVDBcF8rk1EudFVXJw2eBvccP2E5EUFuTSmzcS/ERR46wu6YI04D +ZexQ9IUEBSqb6tCxyzYmKXfood5v+2RDsDIt90KQoXhtmiM3VPKUjRYyFy/daVrl +OjA/KiqUvvTK2o2lrapyS2BUobFqquD0onXM20gmXNTyozf7HSjf4Of3/6YdCMgK +8zoPx1qJjuxEddu7Qr429xo822nO11IUj3IdHfyLhAROfP31ATOcQlLaN1A9AdHy +QpFsNX7EDga6QNPA5AENETPD+rI/H4u86KkqSOQU8hHv7+KSJ5ltIBOJDKbH4YBd +DW35Z9d9Lhg9qbc13r/7rOit156t0XgSpb/r20fdUeC5xHcNeIJZSQ/SpfRDyJgs +mPQaIgwG64q14TUUdn3uE7vTh227l1jmG/idbiLm3ICGzavkg3OG1AZbkUA8YzDy +oVkK0TR8F+CUW/hJtpMeIFq6B3+1v3RgflydTspxyPQBOz02lUI5Z+aRn22k5fGM +HWFXFyK4FUHVMDVpBlgQ2aWAZm7dDUcPl3FSDksP88Vh0fIni27D8B0ZSwQbKBRt +Y502O4gVJxg38rTO1ArB9EGrggh1j0PHUWVZYyEAsXxtg6uslxOn1gOUx5YrDw73 +qytnzWedlLbXTRLL9brVYTeTGE3hS3zBtpFLpxt2MUzsPdFxV3plLZTAReGlDsEO +IyAA8WjJrMx7r/F/tMXqN/Q1cXm75lnN328MDXJBqRDnxUet0AGRQA5hyWm01Wfq +adIakStBmlqzO/idMwZO35p9AMexoSpWskDxIiSrnjOnkpC1RPCIDamUbIb//5zs +Gdcs8GuiiYas3pGHt/r7GYr4ZOdKVtEf18dtNa0NehyypOfyknuRR93d9dMEtyah +JY1LyXUR/RkODnDh2w1Dns6I8Dt6FFLBzWg3vNLtR9xdYYOOJjQGrmYMXR0eogd5 +h8MOALPchAaKr9GIuPWSgVMRvjVkd4+rTiktEp5MnPrQ5mGAgiDuKuUtBSoSXYj6 +LKapIdXUotfSq1ugB5tpOuEAVCYrN+oSbVOyhEH8sOLW0btFDMVb8Z2BaB2wWjHn +HHIzhJtluxrhP+IXLDgQEgVeU64iKyOieyaqJclU7VmhjZp4KWC5mnYRwzOcmwRO +ffpisHDU2xBZ+Af8ADb2Pf+HWw/doOmtdrTQ2QZqJOoWPBQkEaCvARG5IijPXLys +hra0Q7J62xQ3KHjHvOkla4EDdosQ8hSIsCD8O3N5BpPLZqs3HDeKglh0+8e24OIK +9H1BkAaPFILht84ON6lcdzWGEg3pKlZlXrGZXFJm8uSIR5nCGLbtT9ZBFESzOHRV +CAD7ZgCujlmjaMOb+5m6wp/sAtQXMKDMYk/9btdi8aq9GkWQFm8Tcw0pm1CqnlkI +n5+zrcOA6mJffNKns6/SXkLSvuXg4482TTbrEItw8QLsxFIfkTFypHGi7fAH2ndS +xi+VZOeWiY6oVm1UqOOI4+kEr4vbHYQaZGSGv+LAXqWEchGoSUQY0Cb5GH9g1o4F +F4tZVMUYN57qJcH54odhIenBU7PIIK6gpXy9VLnptpZ7yk2Mx9rrfYdzIZfJQz0Y +p8IFTegEaaILfuv0mZfghR76b4z38Ah8CH8spNENlCzB2DHHe2Q/fmPfJzfse89v +APEZgsmOpRK6/pNj1edKGm4kJGgtO+kW1Z3gysJlDvdsur04jwIStGBOir9HzoNA +HPq2ftJ/8mHQT1BR882Wfx5KE+D0cS99gRsLF+NKiBocyhNGm4TPq5qSEHMJTuoZ +1PWji5dB54aURQBdoFSAzZq4UMu3uyULGVm4czX9Ypc/QPF/dgQYO6pNKSDpAKCq +UIDmHFKJQf+xM19JR1yl0XgpF6429/XxvatcoDZF6Kuf0y46gslkzEexyF/AV2La +MElPLWVI1X9hbrEvQaFLt4nLczpMYT6r4r7gXm/q9IuIC2QgIbv2+Deol/iex8zm +VMn9+L3HphPe9vSJJKH/q6AuuPrFm3hK5AZD1MEb5vWEbxzcwgpSpgWUSd9L0q5+ +rJ/PoRXM3Cx+4/wjW5NBysgcMdHvH3jmTabJZjOgJC0pJDbYCdTV+FuRzriLPiLo +SK+UokJPpEIleWJQ+7ys6jP6eHiy91g+ih1I/It1ZlBZmQ2oPUluwhHVWGd6mMSM +K58F6reX0BNuimT4+RxqHhH+NQLxbCj+ETBmuwsZXvJJM/FZLR3OJSMYuvKiw+CM +mmUSpaqTrDh//gEqOKRdUojQa5npW10xmdv0WhXvVklISuO057bBFFA2W0k68ZRN +onF91GQNE72lqOjHkX2y04EDHAaA5cJtiKRtPUgttRAWyg5Ak4O/0GbBzrnhgNH1 +Dxuuagn26BUbBWYGdWP8f3URDHHCoZMwIyFkGL7SBk8hmUmwek8tkZ5TN/hnYL/d +7LPXnaaRL8VKZ9G9SYdCmFZgr70Pn9fzzKuR+oxICLc3RHJENnzOnVklmcihfauT +nzEie0F8pUzMXxX57aLEbowahrp+lyng+YEjTKZXO7t0o0SLIwnauS04SfE9oikV +R1wMuJHqWUK4kJbNC/HPGliFZDMtNn3k9UPkrVMI7YKC5H+71QmpYWZnpK6Yx8vc +ttnBlYi0myorMifNY7MlDQddBI9630zlXBXv8gpQffKLBIgH/UoFXY934BEi2vUj +62OdhyqoEHfrBRDM63IEPplui+Fmx4ppkogt4PQWTq3TJuFeA/AygXk58Dzpka34 +2hZQzjAjWKlPpXDpgNg0ag65fb95eZZh4bPj6O1pLSBMUm3nfXh9O4qPBejpP3iu +YCRpuw1Zfqx0cBDilL0X6nuXqlVBRBbqc7uN1VPzrGgdOKdxJ+y5ot/miBQwhclU +LcSIxYt+FEQdNBAo2C2tes8DTj+47lucdR5TQjoWqKd2scHmgnZgJcQDPMUz4VNf +nrFlt09vgEyarq8+Ys2+bwPBtxGg0KZwDzuKZqs4/p5m5vxL9axdUydqe2j5tC5K +nG1VTtPa8G5dDTd4jGvkAFBS94qbs7MHe5Sl+U/+7VMMQ4YLnqBv6xBZCA6vXBBu +9RgeRk67233dkVjpKgbO84SHH4vq7E0viu5mPXt4J3kQeOHr/9FtzjualbvIXiFs +Gi7cs4dcoTt8TB1egNJC8QBH50MnSVob+/yYQ8tgdZNkQxy96fdolGtrgWjdeVhG +uQuO+lTt8CjhCSkpzEF4YzhkDVZVUtwnvYzArsw/GEdB0/a7Wf3E9IHls8Xkvca3 +LHoVSlEceKJsiVce2kXW05Mep66x/2w2v3w4KCN73CPiYLxWDFcwSmT4Gex6EjDt +2oLHx8QlTtEIYi7yORRUsO4LXQTAVrjSMfaaebxOdKOJUoVbC7912OD65PtoRjiV +Mu3qoKJU5kiBCNfUdeiVx4LpdhyNnOWSk5uTl9p5JePp2Btl4Y65b2QvvgbfeI8r +g0UKEXPqsZusZhcxHCyFT5Y0uZV8YZA90EefA/JEACmdqlPeNMDS1KszLuAIR/ZV +Mt6ZtG0WH9ss2auBwAPKBf6t/xR9nma+ZmLP0kY03++uNomwvPtH877dzVlHTAvx +S/cFudDQG8t23C9gFhRNJ2iVe759ROQlMDub1bey7OXJNotEtYpdYpPgW8KojaYl +Dv8ayg2Vm9o4+UbhLJ89bOjPDyS31QjBgte4iV9hlbtHUm4E+KNH1lSiH93kUGQY +Zok2nG6rPRuNo1RvtB0rZmialRx+UtHxx9XaC5puUDOvxI35IVAT/EisMT1jAIpH +ShBFNI6DTNxlSiqZeDj3damW5U6SIDDphypK3+WC/BVHPU9KmvrwkSzPxmDL1ryw +bq5Fzbpr9yGLr5fv8BcCpJa+1NHcJ64ZqUNr70hZHd61qTJ8PrrGOh6sDmuE991p +nVlO/0+ImWlYqxC+arvBLdZPMxbSUNZdni9S29OrTR6EvCk+8iM3CVT+y9FpU0zZ +k0+ePG7ARx3I1cftYNDSzGbn2tMEoXszJqN540eJH6vpsRUF2iKDHrcLXn6gHAtQ +vL52ItOuhOq7IyPj9+IbQm3pud/DAxOJvWkUI3qC8Rs5LMfnRW1fRF4tQieW+r2K +hSOTyK6acUG6DUt/pcK/L6+NLjrg+86LdjgNr83RJ1ikJz3Wgu9UYFdAE6CwZIJu +9rReZmyPAKj0EH/ycPF0qZtp+VCMicme6LFl34VG7hRts1ZtnpDWqQ6aQhnAq4EG +eFz6t7p/+clQr+ADCjD5BBbhjMv+Kn4ySwdbmTWfdJb0U+zSorLZZlJF55E4simh +T3yjzjiFIMb858+wrbDYi4yKnkEeYntivYSLXqZffvik6hHBMiq7kUMme5gJFRUf +dM/s0e7gQBVR6cpLsnalO2L31TEVYKYq6WERxdBDeYk0AxrfQryqBRlCEhKgNfbR +yLtRGQU9+/X4EvvNJJ8qGloBzhPR2urWExO/DoW8aaxSWLMNJ5YiknLm7aN9vWMa +k6gKN7SFemG5IPoA+aHtL46eJJyR77UNxnipTMrccLyxV9cHdYCUPtKMArWRKvwU +0AjyvIUHgelShusC0ttYpGwPGaOTsJ+yC4hMU9gftnK3Y4QcHu7q5/Z1EN2a2fRK +w+lDHrYgvSKk5bHw3C3BEV/HRG89sThhYfIOFcCdtW3EWMZtCjoE/PZyaDHjvC56 +wZQC2MON6gvvk5In1v6TI7aoqloutrOBnEbbr07beBye38KW9MVcyuu2mdvbrsaU +btzVrE3KD5LOhOvkE6NJqahRWnXsedIxrtACYA9XdZfFeGJfz1tDFZuJfmvmC23d +0OqUsSR8TWb8jotNIU3Qm9U9XFNfnoonfOtze1HZyOKQCqWXO6WmbX4Aqz0UEcDT +LPzsb/FuKNIezJuUTt3mCitDOiQJa8wOhhcWnCDfDrXwm9DVMY0Mw8Kddg5pXhU4 +BPT0sPMa7OlEhAyKFqDaC7IM2XHFj+JGy4COMQtvKH6LQkNB6To9YF1PfZsXwqi3 +wkOlF6hopJOlDU76D4Iy8NyHqqfDY4ney6bZde60wt/KdVtaCVSnzXRFsToTKepe +UZ5BOLlz5aIsuJM8lI1+gGZkRBGRj+3IRXfGeIfQ6C8XyEs5jqV9BFNl9z7wOGXN +J5C+Zq+cNzhwHp7m63Yq2ytN5JunI13LuOdrG0l7EVW3a0TwcLXE3+Fq2AU9NmvY +DZbbMIziZ+wz+pMC/v4BwqShe4kYvosEzSOpDfbf1sLvbviBXe1OqHG6ZOwCANst +YHUsQlURFFd8HIy/rWBiM4mv895pQ93VUUWnYf9VMw09cDaLQ5V+6enp7aGrAHLI +jVYii7Mwsqwi8ofioW2jj9HuANh/dv6bvZA6rAbbgiHViiXIBrqAZ0Qx7tstOGW0 +W07DC9AoFqGKXM6wWBH2/roHH9KixHhlULTR1lRAUPun3FtKcorjJT2otrcS0P9/ +VRbZJ1KZR/z2869RbWX51vW116ZDYAg7DAnzDiSdAQF+dDpI9yXQ1Qz5PxyeGrYA +S9UGd5AZQ4Z2eLulLgj0Lp5LUR7N7YBu5tS2J+nePJk/32teGdowxaFb+ycjwllP +S4NeP8XYATQygxogte9l9iV+sHeeH3kbwY3hiXgaboNB/K7pnPh4f6kKA5TMeZ6b +67WGnA00Pc9t5JrFJfpj8sWfrlJbrR3pWoJu0H9MRbnYwRHMTXVHtOeAmBCkbuuF +0EJ3m3k25ruS4UEArp6HU7Fpm7yukhg9mDEqJ2s4nHX9W4WYrKG47Lq+8JmRuVai +Smlsdz3enuMlq4bwoJrvV+UQM7aVY3jzI7aK+2RxxWHERGmBJM1rMp0d9RPvWHwe +bZ87hzpQOfyzf+BrDn+MTvbwDsCFwibCjIuGpryTtWdXSkpXnd/BTCnDcsGZWuy6 +V7jHvPmjK4Cki2hIHBZT5fENzpAlhS1hxulpYnLj97rBoP8l1Iqs3mYw0JGAicRq +mnjv2FriCnEgxIphpXe38AT3U0Xx2zolDkjN2uQaF3UfzcWEalaApxicMKebXRNl +Q/tDa2LKWdiB9H6YqFEhhteej3ZzJqYFmkNtDL/BfHTT4k0ll6IveC/Y4jlT/lYl +AMKi1/w24+lPXWPW8j8m/mGhXfUtZN+XZOPzlCfDifMqQM8b9cFaCZo5/DYpCE3e +3soAtTlPeG4mIcsQZrUm6vp5Rk6Gyn/u1R+LR+5MiqB5SSiLcY4QSw0aGq3iP8S9 +CuAprbxsjMIFjfnhE2hYMIvkAzTHi/nEtmTswWeeuY1eCCoP+OZvGHdY3GywGGG+ +Rf6TTmFbvQjHAPJSk4MgjXVJ+9Fmij7kJa+hsXLq19fEHPdN3oD3FA3wBLi/1Ln5 +5707OW57H8FZ1lK8aKMFT9cfSEng2VAM6AAk+pKmWq5leACWh4CwPuy5VNOCQL5q +Q3Q7J2cEz0vSHrG/yZIcvH7Qfz+4TKrlCnLKD4OxWL+PYSFo9wu7aOw+JslVBMa3 +PSFZ32YRTUHc640KvDvn67g0sURA3UDeiRuM0UsICxitd9pfAsPJFavbeNtsG+5k +4CAEnJ4v40ZlAiriuDVCPc8jeaf30kYdwBtV1wFYqDWMKrYLM7d51PiVVGYyQxKf +adE/MwOIOJWjL2IG3tyY++jwUiElLAN/WW6dIiO6PtmbGHOTtKPicSVXsZ9nyfR0 +8eCLySc2N7Orzptd36YTP6Nwq/RvxsZCQXU9gjSYyVjD/2vu2i6rTHa7fD75+i4M +eDH4k5csQ7Sfd53ryouiHeBdHtEHbavD/ZMjm7h7ocgvgoSwISnORf7rYFsLDvbm +1+XoKYMGDZTFKfyOAyA2fzrj4fLkzvW/jTysYm69Yog6qPanGotfX681Ww7VTVI1 +I2BvdqiURa1qMAQ6/5iWDCx0VpvS3hCfzBs1VpisJxGHSt6XO1Rki4koq5pcsHEG +kQ/y2N0b5gTnjnN0D4CKJ+npX0uXpjs7apDBHNwsEZtKDSeSYWdqCGxOsZoHnCsA +lvoj/EoD6U86hh5mDfSMtiin6mBoIT0vg9omsSsyBXkl9hIB4SvnaUNZlS8gqQvn +ONaSw+V7j9UqnWI+DbTt4SRQT8kuiY60ZiRFzHtym6WchYkDUTM0aYVkxl2SKyeC +2PsBADMjYNbYl7GUEOe+pjNMSwWBIqErLl95ZTzEwjMxsg8pHeanSAo0B657CLjq +yxFe4kmSFzaZ34ebaXMm4F+2Eimxt5AOgaCbxyjG8NkfaLSZCK6tWamNzI2Nt7d3 +7OT7D03KQ5c3fKtQGQk11s7HOHEScZVZuoCNKKrChR/hl2xJFWoBCXRhTR2xXmQo +DwXbkUz5KR6fzRYCgzH0f6qKM8BwA7/N9hEK9+XxtyrUGrxLctPQv6iCHFByAdTL +hsGNcUBZZD157uCiBj73k9eQEgR3mCWRMZSTWU44q8om/r62TDJ1GjXmEuf5ybRW +TPjv5FZp5ZFnx9A7wSE9aifYg4GGhE0FI6TynyK0TCjHwTWW26mVYPwg/klsYe9t +rh3+Py4XU8uN5ACD9daSTNNTbBN8AriRUPrbTxhgGXWmUqGeoJ0Pebtj0tin5WGT +NvU4jpjJrigtxHWKZzPK7sKJK7BMtS1bokM+Rt1Z08pEK5M8pZjvOPTxlQq4L00Y +RTVl4OvlmNdcX4pwch3EQ626VfyAMjwNscxT9CoRcRTV+eAfuL7tK59dakITuYMf +RYV7NbHgFr7WlpRoM1aT0/0b5jR7pM6p/QBaEHDB59gFsN0jIA1Q6nj3DngrNZaE +Q1C5vrBxDpPpTs6BUg23PROT0fBkbvAAKt/lk9ES06hSZWezMudAA2YaYt22qVV5 +yqbyBhSgyLii5qCjnvG8Q+o0TiBZ/oTtX1gI1FDljM4skbKzBzL2DyhbMuBbx7j5 +GTjEmPQUeI7g6mQPPdvvC8kKWISsX0nGFdmr+5BUuA4891rFMo0m+T63YJQHmUUh +0hxYg4WQYxjXszRkranOYQgy7A1o8Xg8M7EBsyyeom+nc/lPE6eaR+R393OWKWDL +OdHUkrJGAgdpolFecAuHndW/rXGIfCWdvoBU4npwjz9N+2heuVY251erNjikzJG5 +zXIybYLOIjmhxtsDW+U6JekhFbMPrnZfQcA/JOw8A/EZChThnaX98R8Jg9Vqpx1g +S/5g6F3rB+OWIv7FzgxNwJ0W2EvQ2VBZVvkwLk9Upxyn47YJ0rk6mxuBTCqkhVXJ +Jhg9sXVWcke0+TvYQcT7lIQAJBmxGNUn8lqLDgduTynISiBzXMqTbN2epEDjzVLF +tyxx+rYBN5N9KAjqiT9l8IIpL2Lo59gedgU64KWJdpaeLg55OyetzlhDbWGBFk15 +EdRd++SoLD0UuHb9dYH8lORbxg84Rwn9gdFHstRSNT5ywic7y7iQHrL6dBSYwKDr +Mjf9PnhTbUcDKd/tF1fsLe5ZU1jtIDBfCgG2gQLdopeM0Euujp45ZyoHB9KdvE5n +Ow//d2VIg5YMyJFAFN7dKVKrDO/2xWcXBQCSFPjxJe3vQ+y34f1Jvz/q2gj/od45 +s3k7cV3GmXt4Rbzeqch0VAtLSkZ0e9NggDb9d/KQHlmtN1Nx1YKdvC4Bvoqo3h1c +DzgtLhMyC5vemhGnTAvGcxA46tFjSZBC0umJrnagPxuLNtUPqSFs4MX2HsdyHtDc +kLege0aPHf1BZXGvfilNaeLPWJx0/JPI5mvDB9Y/abY0EtPKs22LAoXuTawmPbky +O5XZtetolliZPNsx+8IqbjNvgn2oDJJ9qBBQ033fFok0POAxVC8MaUxej64fxFYd +i8zXmNJmpK5npBtPxkM37QlJD9AEtGGscFRfsQsm3VmdcE7VTANoWWM8QnewC3iz +44jZHf0t+bPsuieN6p/NL3hbeRKZ7XrQ0ajHBHWv76dpL5dxNsEZ57UY/9eTooeN +/E/uTGOFhhVm//SMXgscCHxtjf4fsF46I3M9RRXhYeNSZY5OxSgwqYdsv5rdYoP8 +ebu0Z4TJr3LsNVVZqdbpB83BmwwVXi2kUr20qB/1/IfxQDF6+JABN635e7jj2adj +6Vk1XnjYXBDUTQfqtpf8GUU7P8NqpYnG9Gk+U61Vq5JJKdZEZVV5d0DVaG1/sG3X +erSwQkkjuHto1L1Q7uvUhxYWsfvmx1CQ9q9nae+IfD/VYK9/nbcEOTgNWc2g33+c +Ej7UlOs23qisK+wPKiSY25zvt0+733YppBXmgjuQCuUgDL0Q4hK//+842xZY56bQ +OFHtOzU5xkwx+c2squqNs3HB2EXJDeJIPUjuqzJCM58cOv5GtHvhKafa7l/5wOCM +eJ86vu9bD4EvHiI7aWHw3Luwp5MCJaBtdAHdF3WOH3l6KSCfo7lU79yijNF+7nqo +ro9oN6zkWAulQ+UkAa52vjL1CtQsKa3kZ6aNOuFq2M4U3lWl/kGu+cwwrxEMLsFt +HviNcooX9Bd8GgMUIiUl0Mqae8pT60q+KHQI9DbC6Xcnk/1r0PBnn1hPtufA4Hi0 +tZpw+fgN9JxFe8O2OOnSImm0I5sq26j2OYWfdWT7o2mWi0HAce1YowCC/P4dyclW +zK7W54cLmNCrjpFc8VZIjxSVXxNEKcpVNrAAeUeP+w0kRvmn16YALcJRe+pVNfGL +M4nv7RSgrtnbCsb+mK51Vg4hW1PpkX3uvoLlJUHmBtlGRyPXiECppRnlEbuRWGxd +VYUcG81iAnZifnIMzJXrvQDvRgN1zIRC2KlzRKgBPX7nYL7i0nPevYkcGaiB4D/8 +ANdb59kTCT7BUlaYxJkm845k0CqhTjLAT+Hs8Uy6O6AghDHYNyFm7lWNB/a7NmGy +tLEV+K09H2lH98Jxn81xiDp9rx7JTzzOnTwJQamyipJZdHiHf3OaAoizt0gZITUf +5UUCJAR+RIAWx7dOkE9yPwA4PZ7W7pXGeslP2szGTnDk3FBRuzKewVWdpHkNS3s8 +sF/+OEs73dTsnmi7auLk6WgK0uJdMrZS1IL99Y5TsT8lk4VhEgtTXaXPDPDrHUGf +ifswzJeCdfoUUMbXLHpoNuzXyOStdKmUhfkcdpjGvc7KScNN2rGZw/j/G3fa7vel +CATHj0lO1FKSpRfaHzBD9bqUn9Sp4lRJ6YlWF6KPXGqkFj1r/J7GB2FI5ctLZUbR +rXeRh5kWZZvLshsZt/GMFJPr/TZASvLajBM1T9surQULTAjkwyyFRntkWl7WoAAK +GhQJq+MbmEggpqPyFRVZGausniYY3u5kyiZa15jj8Ga4tTXP77Yqakv0ePdLgxbx +XRnrl3FMzU4d+qJB+oRFg0+DF3S8f7IdWg0djTNDoxVmGDt9Aiowr2woFpld5J+R +HYjYXnqFZY5AA/vdREW1Iq0YjoiHBEgz2vtHcUs8zL3xYH159CR5QDyKcLCohV04 +9APC0U2rWLLIjsR0NNbrrC2BTXtsOGmo3l7FlUmOzpQBbMVUQPbC8OITpeprtKqe ++vgELZ5krH2cyOY4qwjo4XnMBBZX4seiJHxmaieMSS87PYyMAtsQXWpZINnEZfgo +b3X/qL/G4yo2dexZXd2WU040Mo1woKBGyIz02+MT63ehFQOiRtmz12BTkvNqmZpT +XuSVTTKTt11NSlUTsfthNzPLNGddTq2Z14z9OCCzIstrkJKWISPAKhdvNEG+tEB3 +IkUFc1cgoATGsra5aYYi28U+F2Bdz+OiyID/nRGZMOpBpBjPrHrqU45U6oSXTtEe +3L2AoC4MPuh9D1+ElFrWE0SRZG2HZr5XdGZqG1YPwZnYnCMWQYUJjxlBfk37dZgt +r5ExI1pGNSH9//Y/MGfi0YdGasyURchybzAFBqBPQncYoJJd59EuuFvDKe61vqnz +UwmT6hBjVltw3wo5ZO/zy2s7IrMTq0ZNJYlNgN8B8ZA1j7HuSq4/bthQuhm8gEZS +cEBEpVMB8POKzvB68i4w1+1P2TLDbdJsTG3HWvqKBmmgGhmAHGLDymLKh8UTu5ke +X3aA+skwxfifnzgVnv+xKdc9DEWimIE1fNU4LVR/4iiMSYDpQeQEEaHY/JbPxt9o +5ACEZkytoNFw9QqC2NrKI3kQ2q/kz2JsVFR/sPuBBCN5+JI6121bUy1O95B1JWjr +dbt6UQMAbXHqycQ86oOXPaqUJzqPRAcEGaK68OlhfxqUo1bgtLoiPkHNxAPQqKLi +W2Olki0g7Z9zVzaR5/cublzSgvh7JWA622Fj6WP5h9hj31H2rp+mkLwBBxDIWW6V +AUnm+fOWA/rYPabXn7kvoEj3h+tt4f6whrN3b+rLNBAgZN+YX+cGTJPTbfEo5RWv +DQvhAYU1uIOTF5KDtDjR/jOrRqV+eXmsgkhq5E4J93wKRY2XuMjSZPbLB0GeycY3 +bLh66SPgSabSAkWmBAGAZN1F7dY4MO9dw1pD0S6p9gGzYeoUpExc9r7mMDan26qm +LbNSMaUY0hoSQ961AiGdxsFbVyiBmdOBLBgcPnv6XknWUz0fKOs9wILctT0BX2k/ +kZf/9Rf1daeB/KsyaCiPYOPkX02a61xXAshEi42jlyaSAsul/47oYYso7HVVoqmw +mKmOBdbMjiJk40oj6GzQWrfPsnssygo9rIEMMRP2452xqWYBfEpaxxNlswnT/K/a +EUEnCk3Jhrifsq+nNy+5QfgAA8SY4uCoKAs29r71o4fEdsbemsnHMFcPvxx4SW7y +uTRODq+RN6LasiF4kuEaoVY3dpY2GZ66nLzfw4Qwil40dyiTymb//VVEVGmk05xo +Uk8NgeWE79/gaC/o8Qa/qu1KcTuCpe1hQoLWt2ynxTNqFr877AF8+r0teqM6dQKU +sMnZJyhRDWAK8UodSoddJO5EXv/lVPyA488s0BhIYieS/RsRjTg2PDCM3kFpWRiY +6Sgu3ZFqj8duLmBMTqJzlToqEpG7fEWwM7Fny6qnum/kpbgTTO/chlDhxrPC2zlm +JTIkg9TGQu9O0qUTDRoUnPzaeJDdeqDaoZyZBAw4k2BRxbFUaZo3tA7UQhfNuo2b +f3cV5sXXuzNfnp0ze9jMkbd/QlqcBoNB7hzLkHwhfYHIftcRCkBpb9QKJpZhEEdl +QT3oZFQTdOjruzXBgyP67mEfeyuQUgFkSn0w8KrtG9NRL6MbTGZPeNQQHQ+4jfCV +5+t9kr6D2ghD35b31kEGYayjMyb79CwVAlWly2D/RkLydSbvGuJ7/S2tUe+wbAA8 +48ZzwvsoEYAShvffELPQyQWUrej1Fbv9bApqnYdWhOwixsolF7sOQoW1SO/EzBdt +dbXRDBkjVAm5GvXvON5lPWYvSkdmaYfIPAQXRfuarloErf7TIklFTVEmKJovkiOg +mxBvBVgrAJZMATPlMz1Xdvf5CwIfPFm/PboaWS1Q7/mzlUSjBSIdPJQVZQ7S2BQw +qLGw9gKVLlwEiokuNvSL6AXYDlxd6nCSyOM+nb1QHyfmt7dMrFWor67PDTC0lwjU +9zcMAWrVQOFDeKWV3aa5LOzOvZBWml74NUoj3NLyWEarA0phv3WMltXyYBjNGB3f +TB1SgPqc6sfTPeiI9a1B4cve2J8zRA3KPoKO3KaXIrwOmDpgsC+2TJ2eEpmL032d +Yg6UJzltMqJ51MjVLlXXbr75yiwtL5CZ4o9OPMRCOdB4JERkq6rNpCcNHg6Qrmae +WxLl6ObOV53td0Axcqu7/1d/ywnObMzZwQueTEcDK+IoWkvyCFspoGQGJSTdrCln +9U/fwZ1Aw573Y8yV23mCoVz+46CizX1R0tt8RsiUUuJRedZuXpdgmloXHSwHqVir +4TeoeKbJ5TabI9wAUk5DudmB5BBA5WQUXbk863Vmp6ZrYuTLfrMjZIX9wugW7G99 +XjupmycimgGdDcwkPXsuhcn+y+kypAeSBT8BmORPoMB3GBQcBFCpksISgnzfj9Df +f88VaFEwPw6WYPsr5zD3qmYV2Wcsa1+AXMyVWEud3OibijB/ydovxfhoylxzubgq +c5dWawXZrm5RAj6OLUtonq8ExeCxZUVesAT41fPbsmxPMODfaNW5FbLVC3kqoKSR +/vBOG3e/0w29HIfCe3INg/hQVqRtqNawZuPB3U4eg6mkDZO0y9woSZUx+4YHiEnU +NTXJ5dCxVSwAc1bY/Ip6OLqp0SL7pbJLVLOZcdpgE5tqhkRt2TK3t44YBFUW+niA ++7vUO6hk9FiP9bQI/e7mVqrPotPqBtZ/BYUCVLnHL1JkdNsfhSH93PbRBOL30thr +a/CDhbsHwqYjqkrPHUZbNL6xs3s1Ebn/iXs+MoUC0UijkUhThusSGW3zplPE0G54 +0jWIUjvdB/4anXrEkP0+JFchB+2p29bDA6M6GqPIVL5rQWDi/hZj7Jo0GIXXkCmh +pvHuQ5Figaz8huMCbW3V2iIeCWQtEZCIlkqcyGu/srkMp8Qy6LofUqNL4sudqhPx +f4uyi9jp8NVnv5ItQ16FzQScH1btWx693lWnmb0+Z2LTNY3edWuP30Cn2zr10hQO +93mjE8j8xiqRmhLimsfa03ja3y1M5RFuYdaN/LBTd4fTOYAzlN0jlO+qU0fuEZpk +uQWrVWtrciib0QKfC1g20lTslFmwF9dosu8yjarIqZXr+RJVRJ+dXzaC9RXCMNZb +65UcvJNvzjdQOIPUdQcFIuSQwWUnMe5P8kikQsxEZuT+BErj9Pt17T+HPstvcsd4 +mLxzNtdOSZuENCu1k9eImFqEVVl2odtXcLBE6f8fS1rDtjNUupb+m5h+WR63QHid +eDln4z8ShnayiKhW6xp0jj2dUvWnOyhQwZWRP8m/EmfeFO7gYiIw1SxDD/ZqH364 +PzVEZruTbQ4jUKjpfHxf9WBgIVrEYTPTBjPjxaZbhfA= +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +gQ+VauIuH+g40FNOpVzoPSXPaSSXzZWh6rE+e4zt/Higof5lTVqndEO2y+vyS/HT +Uz3/xsHmLa5/hfJOzrQ2WAbWJcFOc0pzmbDqYnUgEw1W4IUS1qcjifpXTLdxvwfy +rSWd00QRecQN7v+pyLFb6xf5TELzzsB2PAr6/xlRVs03sGcC8jpFMP1gppLRrh+C +xnDjMIBVdGmu01tJ1gcEY/913addbws7HLgMcMDLft0U/4zTbjE/rrDoC7+eO+3k +z9ZPUNkRvEPxurfsVZfIuglJuZJSqyaB+Khmc5Q1nMDb9IswcttQUM3RtjEksR13 +Y4OcKLh/ejWsVorB6JLJeA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1312 ) +`pragma protect data_block +fo0JdXfIQsWgrENhFGo0RRW9s/IV4eGBK5upzSxFjRkxTj+wCit1QKkd15jJgDu4 +P06Rnw+P2/Cu/tkXRjH7RGfSCa1EZ08cwLiSykEmyb+qQo8wTkOBh8KIag5m0P1t +XTuNeK4lZP50EUwL/4wSSMPuRtdpIAF+0PAXjdoge2gwhduxtVQZpgPO12dwk0Wo +Qyfuxrm/7iyjiETt18QCBk/PXC9JLX6a9hmtr8ujb+7IKQJFj1S7F9WxCZ1yamDs +e1D+l34aYZ5r3sBbAysWrg65oN3fAAd6bhptfeU2+BDBA8oKIcTClBK2f3pBUPul +8YV5xUU0+FGat/Rjkm2ZmKKpm9JD+w7ufesbJ2fqRCCex08yynx+EuV6lNupQQk3 +UbxIK2+04eVmLtY7V87103cxyVnLFXqAQY3XaG0AWBpO2Ew1NwH6CU4yFpyUAC84 +Bjztc1mHKONeueopzONq61tRDqarI0ex6IhDy04D9/zAOhMyBrEHzeR0UozXtK6Y +TB/qqFBgJmagIMQWcL03s2FYWQgGUU3PRQ4JiB57ubJG6H64M9UJUMXI7VXW245F +S0oLuBSWchTwY4/6zvioNieoCZgdkxOTUqHNuV4Zf7Epcgh3IQIZRzjBSpah3skn +kQwLdkHYbh3EzBAN0L4lF8u4LE/8SqwLPpsl91D8Qck2jzgNTYnbsG+t2tsum6n8 +wYvw9H2G6SCXAimDrg2Qy66lpdDA8XQf+1Pu8sYKlEd3GH9lQyGX+l4gx3OLuOtR +fAlYbOhHnFRDXMNE9ZG/I8VKDFToJD1/SjoKUnrz4TdMcQZn3Asrj6LyXsw5CHgd +zhf60BREHK5nXIJRGkqTlV0OyCbaEe0yTgmpWapYbnUcpX4UNu07ijUdSbUBReil +f2PULQwchd1Nh+nj49FyRm0SU4twHeYIMoSC2sMtPiJkuqAZPugzpBpKZUPnKzDd +VmHxPV5Fl4haVbGLfQj4rfl6Mqpqk2DLOiPmwiXnf7CTAjpnwNQ07KsBw6SKxLAe +YS+1RZFe1JQTA73Dv+hAjOEby2uC1tz9V61abAakI4omdhXK1WBGS7AW7VIkOhsa +U2d43C1vqygKdJzTQVB3SVqswMzruIiClRGEypfl8F1L7BIegRA7y6KJYY2lQ69u +7eDX8XmDYmXDiWgXqtWRALbhHrDi8EwOCp5Tts6KK1q+HZNB6UjiGUrGZ2/EhU4H +rNhfbS8YD9wTQtEs/QCi40wIeLIYjIf429BBIRU8k3na6ZwzGLdfxJnqsRLJ6E7X +aCiJk8iag4Wfv0HsAb9J8vDUKzzLHS5OYlHmEss6CTswBAYs7u8/UF9rlfvXy8Mb +z5tfh7xCXqOQpY1gF85w0agvdFKLhhUzfB2Y/XiH+P9zw8608Q4B2irkUuj0fbhU +/VGCOg52ghhNNkaio6JDtzCj/4nMf3QJwdYnJNTiSWLmN/D4rgU8FE7RObm2foEA +5qemSiCt9nYnRGtaRQ0jFh1zieourorN3TI49Lfh/b++M/Hq8OUZh7Uxs5ni4scB +RqEGxATE+29gCCCJ1S3HVi7fcit9xh2mupZnT+m3qHM+Jt01sv59AUJ/UFx/cNYz +qo1oB/NkzOstxVDMlcp8bOO+elF1X4n4wKeC0g/eMM8C+ffQiVT7Rqh2mYLgXQA7 +BhBS+E0RB6UhkxYPnRFEgtk0VLL54VPEVDTINYlLs+L3ZsWwYJs39Gen6vvvepYy +bujDTnnouQqtvD9ok3pkbA== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +TpRHXtmr81JyoWaAtQOsoLu44jF5UvFDPdO5/CllOd3kdY7PwU2fkKx7bS6RlGe6 +282Wvc58pPBGh6uImNRfZkaAKTaspN+giuR1GHAo4nfIKi92dgY2DTW5JbEU67ml +1IGNiK4su606fm7n90PZ69MZadoZPNpUxZxzYbSs+I39eZWsgU+rtoUE2d35qjdW +UyorSD+O2F5Wv51CWlcWJyscNK886BFGFi72CtEY8IdYcolZ7hcONOhQT5jbhGWK +UFFTqjnMO6iVrEodujVvUgcUtFQSTl5/oHSkmacP7CSADA82+06uIHf+rByqHGTp +JNgtSAVN844IRP39n4T5EA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1200 ) +`pragma protect data_block +dW2N/rFxim9wkWiMqoV2KfFOb7ryaosiEjsKQ5d9XAY99bfh9dHXfxBwbIc/m/4e +C1jjMt+51lGF8ncrYuentPA6MwNEfk27Jwvqv9/Trdq+kOdiWuYmhbZxfJC2L3WJ +BzjhoC/o2ZNSFpgmDKLxln0/pf6iM8sUIldzujq1RDEv/fZvcQ9IXZ0c0cgbXEWf +SfOaD5E2qBGsljqkzqzIKjaiTPnGPsKJ6cZ41jLGbcm+AcbSk6th9Vdeim0hCA9t +HjX+E+Tq77j/ivdd5OuzAehdPAg3IiMJTQxdTNsI3km5GzvomnmxK+pG8L9aCaAh +o+hCsSXZD2QyVCRFZjVT4s0ltvRto5PgSDzzqm1N69eUDE/spFnroMx1TQCLbjBT +zS0w4mCeLkzFlxc0DJduqQlnRMlA8AnBFujD/Q2OAdVMSHQC7YscXbPzF31GPlqx +Eg2t/VyotaMLOGG0wG7ax43UokgdGbSuphzh14sCh3ZSbPueJQLw2MQwK5M2gcvg +/OCrpP6ZQDt10hFz8i/uLrgNIWA93ZzqujdUnYXBBCwUzRJEyHSLnlXX6Ko3rzE5 +ct8FuQPGV8vF+t6COL2nQ0qaq+23R5E5PuFtEMyRrDT+p8iXZasw8RECO0NyVnEE +YuX0T1i6imJS88oOkLq+ywGLgMFC+4O26DIlpPh4+UJ/fnt/pVOADhugk3UeF+QA +ZDR1sgxihCZe9rP7QzVpjm2tDiaPt+fklsKWPprWH2eAiuNaia9mSSHNYGF2x2lD +9h3FKeV/2LSUG5mOvvl3sgKhV2fY0MuldurIH+utuZSPbknY3sebf3BKCntClVOm +6zvNgcnFtvD2+A79A8sltui4gm5GYPS2b0YDfju51vT0iTsCH30p3LWNEG/zEtf2 +48bHsr15Z/CgHdw169NsY8B3V8RHxaJP+T6zbPLBjVmRFbuTftozxf/dv+m7Rgl2 +3kmwmDxauFLyklSGjQ352H678ASYS37eMG1wvn3akQjYEAsrQTdi1sxmk6SACmSb +Ko7v8gOZpn886AO3O4V3iIggxtfGIfRMtOXcoEIX6dRl5GdFkcASHigHwoV56yRO +tlfJEHrrKLKbmqhjLMjDz5jTptQZfwCjZGzki/PYImxPv0ay8+PTa/qXEaJEMsWZ +vWEGZGSO9zphfmPXEJI+qF22X0dYlKGn/U8rzBEsdcxIXyGWQwBJvbo+GhnPURiQ +i1MJHwfOEDztC3XemmsQeaMuSDWZFrnOKXuYkOBj7tD8ir7vJOor8isvwQUz9LGK +g5Vx+0HdaBgE32QEZ/NjYA1V6bM0iUHz9e9qzEVqN/kRww8HFXA6SnpD5lz6hyxy +jFVRtphwYQWmSzwLvFWa2AYQuI4xjU7tJKOCZRqxjD4hiIkjDK6/K/01Gk5QL/3K +12xoSmqSIZRHwxFGBoHiuBmy+wBhSdqqIOdJ/OsoBT+1OwzQ24l0CRjfAk+zBdVi +7A89GoA5JGSeX8OCJopZvuJ/kEWBUL+l+AU3S9Z4l0uVYybFXE7WXuTNCWRjCQFQ +DmofPA/+XPmyr1MT/3DpFQgnMN00C/jJ1eRmmSntrjCcYaPS0vX117igGa1YWfcD +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +TBCX5/gAT5S6xdVBuY05hYDsXmHLnm/0Yl4d4ayUlKrDe3IUWB3JcRtZJEwtIwhQ +wqO6qIYs21XvVt74eCxdt1SZXHRXXJiT196fD9q5vFrJxAQqeTDvH51bmshhKW+i +DwXpMTwZlLgBsT2BEP5C0RiiICy9chJTycHB7vHEh6lTXT6S/2H7bweTMlFCh6s6 +n5aHgBbfjk9BYIUSTuEvOxw9Yki0T44zjqGmjZ3qxkhk5Rae8iPLqCnjRTjNfqOE +zQtaoVQW+8NbATVUmZC4WlgxF/J03hq0TLeqLYfcuWR0uH9vLAWsUzHqlGMZvUSV +23zwmB8p0BqUeaj1cllyzw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1984 ) +`pragma protect data_block +2OvJlNYOCu/okutbEvWbuQI4X9C4wmVA84hW5XRuqc+R7lDXEYZ89g58fT3Wyd8M +ecpTY/f/5J++NaepFO9rZ71cRzxgXD7ZQypxrBwT8eXz6kwhomKLL8xgQuGMrD2h +002LEC5h770bZFbr2QDl94Kd8oWweGDIcwbbPgGtsgfsrwnZq107rvdgRLsvDJ6H +A9T68XpAsV83OJOA8hk5S1ytXOtMoD1vxUA9NgZ2d9BBiwxnfNC6r2DYa/TpgT+F +8Dlnu2u3Ch2T50E1FvIsU2NsOkKdsN8k6Nmhr7J+mWrK8q1RSElNbQt02yIshAzD +fz1m7maxuzNvKiofs7xTJYH5Zl3jsRgP4i3jUPcFIYQTdju0XGFuzz4tT0y3o98B +wJPQRdZzLdAIRwwOeqCGe94DNj6v4B0lCOW+L2I2xO/Zd85RIWk0KQ11TMBxIioX +lElgvMwoYdOobLmpseg4vchu9jvsSwd1ET14HpSefqoM8cHFSvGA3j0KpwHUHD6N +cAg2z8pkpvWyZBxPOnKrjjHml3gwE3q+X2mtD1ayi41L4xn6E8czI/znMUiRwwcz +u/UG8I65XcONtBswjX1cTAad9X9cP37rq7ly/mnCVaQ1fwdx50rBY6tOiF0jiVR5 +JjSBl4FkBYJu7kHqA7DcluE9ATZ1+D+BIfESxs4o+MIGiPbk2VMeafwTD7GkJFOt +pp85p5WDA/qQLIA+aQsaHfBRLInMjsajsBU1Nnr1Z2FuT4dNgRDU1JiEJoiGBh4S +RZzlhgVKqLQdDiC5KHU60BMuW3u1CxkP6BLofYO1/DTsIOzKRlb9s3+Bx2RBLO+X +LpI1kmPdmyjjLOe9xPxUuWAlk4Ona2bF7SOrCRKslzRwj5WK3kdfynnrqi6fyg/g +6RtRb5T19kv8xkX8Q0Nu2f6aIj9NFg8R8LJhXh6X45cptFvZzqgrDrKouB2qeqzv +r/ARvwCCrLhqU1Rwol3o14E8rmlZcjNTDxMVbtGHIC6f+FQD8Ge6dA7TLtOmbzhg +ADyiBfAGChDV8d6/1Hzt1ZCbp6C5hSA43mtpTQYEjZcGds4olsLWRMFlvn6SaE8U +/yc4f8I5aqNLijlkaO5yVtVndDXvrhyJK63yxQ2hv4wjwsq4K2PDQ4XYvUcmKPD/ +XlPlsS9Ze38WOmF18BNsWhFg/X1ZEsnJQZqQFknQ9z/lHiYTcq+HtWHD6JfZzOaM +E3UA8T88Db5hkBxdi+VdfTfF/tcJB9TVv94cA8SuyNnP6Q6AMPtj4AcaMmUbLwpN +6fOz+eRjs375gUjeGtSoPhbJZ6VvJjLK6xs1mDGS9ROACnxpeDCou3/Z35w98hvB ++vycfefBU/3Oz/FibzGZfGGRZxR88DoezSovO8xS1UTztbTV/E3Hf50BgcR927BL +NJGAapWYDd8JtV0BHG5wpaes7/XmU1ypZarztFE+5fUtgzp4AKZ9d8fLPqu7uHyy +VFSlknUG3lKAvV+aTv5kwTm6T24a0lpxxYWzaadSBxuqeJtU7FNijzCia9l+KD/j +MuWIX01bTZapbrnUlFm4fAAgbW5f3nA4jSdhRz4mKzYdZ4aMWDM8hBS+zHKdAxt+ +r3IOTmKOM53qQd6/AzPhoA0A+KC7CNCPEgYxWjHD9LvdybgmZ3XenDSbtLwQbD6Q +UwWAn1xKUS+VTfDL9VkVXP1CneqLQxZtc1Sc/vBPwSJ6+7jAYG5QfCsFKpYk6KVg +WWBjX/iaBk51jQZ/ISopM3fO5XEr5/3lYtazRsrg0f+S3e4Zzo8nxEOq9P5xVhSQ +O7JVUzPKxB+mq8b8+Trp0jpdlwATuoCmknWv7M7xGQxIxgYlBegfgpZNrb4ocJt1 +C2A5oMK874OASkTuFy/CZtTCSKDyyC2WSUJy/ybgFlZWnTyWBNaSIgYpaI2Gq/5N +W2sAGdn2IzwgLXJcE2TeXPkUP8I6D0EvyGS8UJ8WVt4jXlr/F3VEInfxr2Y6siXk +AHHFHgrTgDIGLtO8E808PqkxvLBmGkuPh75G6ryBOPonCZ0aT1e/GX3dbFPpEaEW +llXDZSgbk2fjRwniN+3OtnrHeVbQUlTC3iaVcpJd1hL8XMqXbPIDInH7Hno0Rp0/ +Voc9LaQvrTj/kEwf26rJMPkHP3A/gue3fawMlgP2mdiTeVrBYqtURRsKaMlxgKT3 +3O7Gyd/yxwB05GETZ6zA/3Z0q4ztIi5TZ5m+C2wW+NIXwkcYJdqHOodrO1fkRlTs +npvFlNq1Br3v3gImbnvFaouFkT+542lb5sOY50i4uwrifKPntqOl0n9+dE1pyipU +QURHoCbkL2QR65H1hYcDoLRvhJAfS/oEFf4DSf8HgiZITq5pSvnYcJn76jC0mNiX +9LRJqxBuOkHcdFIbmkvDuwIN0asrQmGQCAsYOOxVA6EpX0XWcJ8dVmRyWbGVZXNq +45wAMvGDj0F6Jm7b2sQ3quJFDXDWvD7hPWp8nLqRDN+P/s9tHqK5LMXPHFdcqMn4 +hKSmCVgEtnsVfWUGyjVJ0Yvh+jxdg3vECIO38UuFBuTGroD0egvsyd7iuwT3aOmn +5YaYW0vHuHERbtLy6AkO1sVVmg18jSH32tE036uQS+LCrj+G0cg6Mf5sU2CHJZA0 +9Jse9KsUSQdI7bnqvPdYIQ== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +eiP/26NloMbfJbEe1aU/cN+AkTVidxKZaNv824TVZXkpjf5L1zEVLf4buBzXwSr1 +MiO1FaB1qgL+ZgKHLwNzc4IiIP0d7qYOaGR46jDr8/k9N2BVxXC3V0wJJ6yhDom9 +O7B9d2Lcm+b0UifdEaFcX3luTwZzXAQW83Bggnm4eVP275Vqog3REHo5wgsstEU3 +AG6o+oVDnNjZTPDPyJ4uHq9bjFFyvY3ga+lOo2iVymecnhCiRtjy3AFtvWBJW0ek +uhj8QvNYf04TXkRXdhdRfq/HDLr3M6Qa7/Xn6vGE+drFyRTL1nmH9wkjBBbD3swn +58tiwvvx3ajgMOCJeXfrXQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1104 ) +`pragma protect data_block +z83CFN/6+XAqqlsaR10y0/0TRdqihm7Mln1SErDagYzHq/tf3472iVn71ufDnRwX +XjpfuAMiYkGYL+YySToA+S247ZqaWHze8oceixrYgRvhox5tY82fxq9Fl8kghDLv +SjC2MS3eD6cYQeQLFqzD1Mn0WKOQZFVCku3VAWFB2lduR5mhayfY/Fa3R/W72ABn +Z0d6Zn4ZBsgSyb/M70GpfeksPL4x3rnLEOyMOaWSU6+bpfwlHv6gwzh9HPzLZxVy +08g2U6/uxm0PBfE3o/LncY5k29GaWHkcOHv6VhXh/m8K01MJZqFeBphDIArYoxxq +PWDxAO8AUxxtI14Tgpa2V285dFMvK+4KnQioTwi0kMw0x+o+AprykzkXPkE/VVzK +KXd3WO23uskN1uRWHMVa+YBeVjuyFSDLn3GxfHH9tkFDow1kssYW0TqHWs0aqHah +qnNS7hoeJjqPZiowmyQrmDxNCJSTzH8quhzu6sXOHqjuy3hV/M2EY8gngXNAKKsb +WbOvs5QeFheEcLGYrod/Zfv9aZk0e3y0m11vKOyZVQVGFJQzc1uQ0fLjWrpSt7yG +qya4/JgJ8aoha2vBdN7gKSQ0jQBRSMhhOkv1iunq1iT+1ZETzOdrs32w7jLu65tq +rkZk2Z9PlyyFm4XlIu3ljYIH3Z1F+BdPGXiUKHiLhEHanApDED/zljh7BDGApCKl +t1zRJJjZMckJfWQclrLgdXSejbEhZFqHfgYNQe4ywo4o/SbWaqGvPgahhDBBVxZV +rvCFFNip8ka1YAIM4x0DqYw1pSFzn0sUmEm44Jl+Eo4D5chLPEJnYyAjsKm0nIFa +We3J6DKurh1q/PmPYqN51Vno2A5tlFLR8v6SH4m4qu3V3skZsRF0vR6BGx84VdVj +bN8BlLOwDEGmTO8UZpg5knVPN5bAfvf/kXvbSbr8KPR5NBZRqz3SXFeMxZYBPfbj +GI8S5ZZZeq5AvybyDwwt8BHWypNkKlsr+UxyAt+phMEA8F/U9gAt5r50llYjO4qu +5tLeotWmT7oFHBktGytHHC+gKwtWEMsJLm7+744JbDfnMvdHRr+AQgpYts9jdNY6 +guxuay2WoNBpjmE51Kq8M1xXeO6beJN3h1JAlESUfz7eFKkE8Vkr5Jg6ccn0KUsS +ZZmNyAaAta//k2mRELcX5bJmUCCHy7lAgQBjtv7XZBfyULC/eXy3RUO/ar8/VQKj +wwOLkv6PJN1DfDlpZ+oswIslScrN1ijU4t2buGKO8zI+cQCpYuC9FBN8V8chHOZw +//0ODvW7AEl6D/OUt8ZC6gUirNCSFRQjXz5x+MOrJPH54wUb0gmtQRPSsbnbcm8g +r+J90t6Fz+FSggPmyNbgv8Z+eWprb5Z3QuqJaQlTYxXGJYLXXwcTjZP3Sf58Vd4Q +9PV9zVG1BxTwV5hFTLJrTkIFGs6wyF+96e+3TnhJKuzZ4Qgf0XJPp9crAdiNtxfx +`pragma protect end_protected + +//pragma protect end + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_define.vh b/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_define.vh new file mode 100644 index 0000000..26709b4 --- /dev/null +++ b/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_define.vh @@ -0,0 +1,53 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.1.95 +// IP Version: 5.4 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam ARB_MODE = "ROUND_ROBIN_1"; +localparam S_PORTS = 1; +localparam DATA_WIDTH = 32; +localparam ADDR_WIDTH = 32; +localparam M_PORTS = 3; +localparam ID_WIDTH = 8; +localparam USER_WIDTH = 3; +localparam PROTOCOL = "AXI4"; diff --git a/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_tmpl.v b/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_tmpl.v new file mode 100644 index 0000000..00aa64f --- /dev/null +++ b/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_tmpl.v @@ -0,0 +1,137 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.1.95 +// IP Version: 5.4 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +gAXIS_1to3_switch u_gAXIS_1to3_switch +( + .rst_n ( rst_n ), + .clk ( clk ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awlock ( s_axi_awlock ), + .s_axi_awready ( s_axi_awready ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arlock ( s_axi_arlock ), + .s_axi_arready ( s_axi_arready ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_wlast ( s_axi_wlast ), + .s_axi_wid ( s_axi_wid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_rready ( s_axi_rready ), + .s_axi_bid ( s_axi_bid ), + .s_axi_rid ( s_axi_rid ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rlast ( s_axi_rlast ), + .s_axi_wstrb ( s_axi_wstrb ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awready ( m_axi_awready ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arready ( m_axi_arready ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_bready ( m_axi_bready ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_rready ( m_axi_rready ), + .m_axi_bid ( m_axi_bid ), + .m_axi_rid ( m_axi_rid ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_rdata ( m_axi_rdata ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_wready ( m_axi_wready ), + .s_axi_wready ( s_axi_wready ), + .s_axi_awprot ( s_axi_awprot ), + .s_axi_awcache ( s_axi_awcache ), + .s_axi_awqos ( s_axi_awqos ), + .s_axi_awuser ( s_axi_awuser ), + .s_axi_arqos ( s_axi_arqos ), + .s_axi_arcache ( s_axi_arcache ), + .m_axi_awprot ( m_axi_awprot ), + .s_axi_arid ( s_axi_arid ), + .s_axi_arsize ( s_axi_arsize ), + .s_axi_arlen ( s_axi_arlen ), + .s_axi_arburst ( s_axi_arburst ), + .s_axi_arprot ( s_axi_arprot ), + .s_axi_awid ( s_axi_awid ), + .s_axi_awburst ( s_axi_awburst ), + .s_axi_awlen ( s_axi_awlen ), + .s_axi_awsize ( s_axi_awsize ), + .m_axi_awid ( m_axi_awid ), + .m_axi_awburst ( m_axi_awburst ), + .m_axi_awlen ( m_axi_awlen ), + .m_axi_awsize ( m_axi_awsize ), + .m_axi_awcache ( m_axi_awcache ), + .m_axi_awqos ( m_axi_awqos ), + .m_axi_awuser ( m_axi_awuser ), + .m_axi_arprot ( m_axi_arprot ), + .m_axi_arburst ( m_axi_arburst ), + .m_axi_arlen ( m_axi_arlen ), + .m_axi_arsize ( m_axi_arsize ), + .m_axi_arcache ( m_axi_arcache ), + .m_axi_arqos ( m_axi_arqos ), + .m_axi_aruser ( m_axi_aruser ), + .m_axi_awregion ( m_axi_awregion ), + .m_axi_arregion ( m_axi_arregion ), + .m_axi_arid ( m_axi_arid ), + .m_axi_wuser ( m_axi_wuser ), + .m_axi_ruser ( m_axi_ruser ), + .m_axi_buser ( m_axi_buser ), + .s_axi_aruser ( s_axi_aruser ), + .s_axi_wuser ( s_axi_wuser ), + .s_axi_buser ( s_axi_buser ), + .s_axi_ruser ( s_axi_ruser ) +); diff --git a/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_tmpl.vhd b/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_tmpl.vhd new file mode 100644 index 0000000..9f59356 --- /dev/null +++ b/fpga/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_tmpl.vhd @@ -0,0 +1,229 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +component gAXIS_1to3_switch is +port ( + rst_n : in std_logic; + clk : in std_logic; + s_axi_awvalid : in std_logic_vector(0 to 0); + s_axi_awaddr : in std_logic_vector(31 downto 0); + s_axi_awlock : in std_logic_vector(1 downto 0); + s_axi_awready : out std_logic_vector(0 to 0); + s_axi_arvalid : in std_logic_vector(0 to 0); + s_axi_araddr : in std_logic_vector(31 downto 0); + s_axi_arlock : in std_logic_vector(1 downto 0); + s_axi_arready : out std_logic_vector(0 to 0); + s_axi_wvalid : in std_logic_vector(0 to 0); + s_axi_wlast : in std_logic_vector(0 to 0); + s_axi_wid : in std_logic_vector(7 downto 0); + s_axi_bready : in std_logic_vector(0 to 0); + s_axi_bresp : out std_logic_vector(1 downto 0); + s_axi_rready : in std_logic_vector(0 to 0); + s_axi_bid : out std_logic_vector(7 downto 0); + s_axi_rid : out std_logic_vector(7 downto 0); + s_axi_wdata : in std_logic_vector(31 downto 0); + s_axi_rdata : out std_logic_vector(31 downto 0); + s_axi_rresp : out std_logic_vector(1 downto 0); + s_axi_bvalid : out std_logic_vector(0 to 0); + s_axi_rvalid : out std_logic_vector(0 to 0); + s_axi_rlast : out std_logic_vector(0 to 0); + s_axi_wstrb : in std_logic_vector(3 downto 0); + m_axi_awvalid : out std_logic_vector(2 downto 0); + m_axi_awaddr : out std_logic_vector(95 downto 0); + m_axi_awlock : out std_logic_vector(5 downto 0); + m_axi_awready : in std_logic_vector(2 downto 0); + m_axi_arvalid : out std_logic_vector(2 downto 0); + m_axi_araddr : out std_logic_vector(95 downto 0); + m_axi_arlock : out std_logic_vector(5 downto 0); + m_axi_arready : in std_logic_vector(2 downto 0); + m_axi_wvalid : out std_logic_vector(2 downto 0); + m_axi_wlast : out std_logic_vector(2 downto 0); + m_axi_bready : out std_logic_vector(2 downto 0); + m_axi_bresp : in std_logic_vector(5 downto 0); + m_axi_rready : out std_logic_vector(2 downto 0); + m_axi_bid : in std_logic_vector(23 downto 0); + m_axi_rid : in std_logic_vector(23 downto 0); + m_axi_wdata : out std_logic_vector(95 downto 0); + m_axi_rdata : in std_logic_vector(95 downto 0); + m_axi_rresp : in std_logic_vector(5 downto 0); + m_axi_bvalid : in std_logic_vector(2 downto 0); + m_axi_rvalid : in std_logic_vector(2 downto 0); + m_axi_rlast : in std_logic_vector(2 downto 0); + m_axi_wstrb : out std_logic_vector(11 downto 0); + m_axi_wready : in std_logic_vector(2 downto 0); + s_axi_wready : out std_logic_vector(0 to 0); + s_axi_awprot : in std_logic_vector(3 downto 0); + s_axi_awcache : in std_logic_vector(3 downto 0); + s_axi_awqos : in std_logic_vector(3 downto 0); + s_axi_awuser : in std_logic_vector(2 downto 0); + s_axi_arqos : in std_logic_vector(3 downto 0); + s_axi_arcache : in std_logic_vector(3 downto 0); + m_axi_awprot : out std_logic_vector(11 downto 0); + s_axi_arid : in std_logic_vector(7 downto 0); + s_axi_arsize : in std_logic_vector(2 downto 0); + s_axi_arlen : in std_logic_vector(7 downto 0); + s_axi_arburst : in std_logic_vector(1 downto 0); + s_axi_arprot : in std_logic_vector(3 downto 0); + s_axi_awid : in std_logic_vector(7 downto 0); + s_axi_awburst : in std_logic_vector(1 downto 0); + s_axi_awlen : in std_logic_vector(7 downto 0); + s_axi_awsize : in std_logic_vector(2 downto 0); + m_axi_awid : out std_logic_vector(23 downto 0); + m_axi_awburst : out std_logic_vector(5 downto 0); + m_axi_awlen : out std_logic_vector(23 downto 0); + m_axi_awsize : out std_logic_vector(8 downto 0); + m_axi_awcache : out std_logic_vector(11 downto 0); + m_axi_awqos : out std_logic_vector(11 downto 0); + m_axi_awuser : out std_logic_vector(8 downto 0); + m_axi_arprot : out std_logic_vector(11 downto 0); + m_axi_arburst : out std_logic_vector(5 downto 0); + m_axi_arlen : out std_logic_vector(23 downto 0); + m_axi_arsize : out std_logic_vector(8 downto 0); + m_axi_arcache : out std_logic_vector(11 downto 0); + m_axi_arqos : out std_logic_vector(11 downto 0); + m_axi_aruser : out std_logic_vector(8 downto 0); + m_axi_awregion : out std_logic_vector(11 downto 0); + m_axi_arregion : out std_logic_vector(11 downto 0); + m_axi_arid : out std_logic_vector(23 downto 0); + m_axi_wuser : out std_logic_vector(8 downto 0); + m_axi_ruser : in std_logic_vector(8 downto 0); + m_axi_buser : in std_logic_vector(8 downto 0); + s_axi_aruser : in std_logic_vector(2 downto 0); + s_axi_wuser : in std_logic_vector(2 downto 0); + s_axi_buser : out std_logic_vector(2 downto 0); + s_axi_ruser : out std_logic_vector(2 downto 0) +); +end component gAXIS_1to3_switch; + +---------------------- End COMPONENT Declaration ------------ +------------- Begin Cut here for INSTANTIATION Template ----- +u_gAXIS_1to3_switch : gAXIS_1to3_switch +port map ( + rst_n => rst_n, + clk => clk, + s_axi_awvalid => s_axi_awvalid, + s_axi_awaddr => s_axi_awaddr, + s_axi_awlock => s_axi_awlock, + s_axi_awready => s_axi_awready, + s_axi_arvalid => s_axi_arvalid, + s_axi_araddr => s_axi_araddr, + s_axi_arlock => s_axi_arlock, + s_axi_arready => s_axi_arready, + s_axi_wvalid => s_axi_wvalid, + s_axi_wlast => s_axi_wlast, + s_axi_wid => s_axi_wid, + s_axi_bready => s_axi_bready, + s_axi_bresp => s_axi_bresp, + s_axi_rready => s_axi_rready, + s_axi_bid => s_axi_bid, + s_axi_rid => s_axi_rid, + s_axi_wdata => s_axi_wdata, + s_axi_rdata => s_axi_rdata, + s_axi_rresp => s_axi_rresp, + s_axi_bvalid => s_axi_bvalid, + s_axi_rvalid => s_axi_rvalid, + s_axi_rlast => s_axi_rlast, + s_axi_wstrb => s_axi_wstrb, + m_axi_awvalid => m_axi_awvalid, + m_axi_awaddr => m_axi_awaddr, + m_axi_awlock => m_axi_awlock, + m_axi_awready => m_axi_awready, + m_axi_arvalid => m_axi_arvalid, + m_axi_araddr => m_axi_araddr, + m_axi_arlock => m_axi_arlock, + m_axi_arready => m_axi_arready, + m_axi_wvalid => m_axi_wvalid, + m_axi_wlast => m_axi_wlast, + m_axi_bready => m_axi_bready, + m_axi_bresp => m_axi_bresp, + m_axi_rready => m_axi_rready, + m_axi_bid => m_axi_bid, + m_axi_rid => m_axi_rid, + m_axi_wdata => m_axi_wdata, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_rvalid => m_axi_rvalid, + m_axi_rlast => m_axi_rlast, + m_axi_wstrb => m_axi_wstrb, + m_axi_wready => m_axi_wready, + s_axi_wready => s_axi_wready, + s_axi_awprot => s_axi_awprot, + s_axi_awcache => s_axi_awcache, + s_axi_awqos => s_axi_awqos, + s_axi_awuser => s_axi_awuser, + s_axi_arqos => s_axi_arqos, + s_axi_arcache => s_axi_arcache, + m_axi_awprot => m_axi_awprot, + s_axi_arid => s_axi_arid, + s_axi_arsize => s_axi_arsize, + s_axi_arlen => s_axi_arlen, + s_axi_arburst => s_axi_arburst, + s_axi_arprot => s_axi_arprot, + s_axi_awid => s_axi_awid, + s_axi_awburst => s_axi_awburst, + s_axi_awlen => s_axi_awlen, + s_axi_awsize => s_axi_awsize, + m_axi_awid => m_axi_awid, + m_axi_awburst => m_axi_awburst, + m_axi_awlen => m_axi_awlen, + m_axi_awsize => m_axi_awsize, + m_axi_awcache => m_axi_awcache, + m_axi_awqos => m_axi_awqos, + m_axi_awuser => m_axi_awuser, + m_axi_arprot => m_axi_arprot, + m_axi_arburst => m_axi_arburst, + m_axi_arlen => m_axi_arlen, + m_axi_arsize => m_axi_arsize, + m_axi_arcache => m_axi_arcache, + m_axi_arqos => m_axi_arqos, + m_axi_aruser => m_axi_aruser, + m_axi_awregion => m_axi_awregion, + m_axi_arregion => m_axi_arregion, + m_axi_arid => m_axi_arid, + m_axi_wuser => m_axi_wuser, + m_axi_ruser => m_axi_ruser, + m_axi_buser => m_axi_buser, + s_axi_aruser => s_axi_aruser, + s_axi_wuser => s_axi_wuser, + s_axi_buser => s_axi_buser, + s_axi_ruser => s_axi_ruser +); + +------------------------ End INSTANTIATION Template --------- diff --git a/fpga/ip/gAXIS_1to3_switch/ipm/component.pickle b/fpga/ip/gAXIS_1to3_switch/ipm/component.pickle new file mode 100644 index 0000000..70cd9d2 Binary files /dev/null and b/fpga/ip/gAXIS_1to3_switch/ipm/component.pickle differ diff --git a/fpga/ip/gAXIS_1to3_switch/ipm/graph.pickle b/fpga/ip/gAXIS_1to3_switch/ipm/graph.pickle new file mode 100644 index 0000000..a254b5f Binary files /dev/null and b/fpga/ip/gAXIS_1to3_switch/ipm/graph.pickle differ diff --git a/fpga/ip/gAXIS_1to3_switch/settings.json b/fpga/ip/gAXIS_1to3_switch/settings.json new file mode 100644 index 0000000..f6219f9 --- /dev/null +++ b/fpga/ip/gAXIS_1to3_switch/settings.json @@ -0,0 +1,96 @@ +{ + "args": [ + "-o", + "gAXIS_1to3_switch", + "--base_path", + "/home/cslau/Desktop/Workspace/efinity/2025.1.95/project/Example_Ti/ip/EfxSapphireHpSoc_slb/Ti375C529_devkit/ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "axi_infra", + "name": "efx_axi_interconnect", + "version": "5.4" + } + ], + "conf": { + "ARB_MODE": "\"ROUND_ROBIN_1\"", + "S_PORTS": "1", + "TABLE0_AXI_S0__MIN": "32'd0", + "TABLE0_AXI_S1__MIN": "32'd16777216", + "TABLE0_AXI_S2__MIN": "32'd17825792", + "TABLE0_AXI_S3__MIN": "32'd286261248", + "TABLE0_AXI_S4__MIN": "32'd536870912", + "TABLE0_AXI_S5__MIN": "32'd805306368", + "TABLE0_AXI_S6__MIN": "32'd1073741824", + "TABLE0_AXI_S7__MIN": "32'd1090519040", + "TABLE0_AXI_S0__MAX": "32'd24", + "TABLE0_AXI_S1__MAX": "32'd16", + "TABLE0_AXI_S2__MAX": "32'd16", + "TABLE0_AXI_S3__MAX": "32'd20", + "TABLE0_AXI_S4__MAX": "32'd28", + "TABLE0_AXI_S5__MAX": "32'd28", + "TABLE0_AXI_S6__MAX": "32'd24", + "TABLE0_AXI_S7__MAX": "32'd20", + "DATA_WIDTH": "32", + "ADDR_WIDTH": "32", + "M_PORTS": "3", + "ID_WIDTH": "8", + "USER_WIDTH": "3", + "PROTOCOL": "\"AXI4\"" + }, + "output": { + "external_script_generator": [], + "external_source_source": [ + "gAXIS_1to3_switch/gAXIS_1to3_switch.v", + "gAXIS_1to3_switch/gAXIS_1to3_switch_tmpl.vhd", + "gAXIS_1to3_switch/gAXIS_1to3_switch_define.vh", + "gAXIS_1to3_switch/gAXIS_1to3_switch_tmpl.v" + ], + "external_example_example": [ + "gAXIS_1to3_switch/Ti60F225_devkit/axi_interconnect_ed.xml", + "gAXIS_1to3_switch/Ti60F225_devkit/constraints.sdc", + "gAXIS_1to3_switch/Ti60F225_devkit/axi_interconnect_ed.peri.xml", + "gAXIS_1to3_switch/Ti60F225_devkit/efx_crc32.v", + "gAXIS_1to3_switch/Ti60F225_devkit/efx_custom_master_model.v", + "gAXIS_1to3_switch/Ti60F225_devkit/efx_custom_slave_model.v", + "gAXIS_1to3_switch/Ti60F225_devkit/top.v", + "gAXIS_1to3_switch/Ti60F225_devkit/efx_fifo_top.v", + "gAXIS_1to3_switch/Ti60F225_devkit/axi_interconnect.vh", + "gAXIS_1to3_switch/Ti60F225_devkit/gAXIS_1to3_switch.v", + "gAXIS_1to3_switch/Ti60F225_devkit/gAXIS_1to3_switch_define.vh" + ], + "external_testbench_synopsys": [ + "gAXIS_1to3_switch/Testbench/synopsys/gAXIS_1to3_switch.v" + ], + "external_testbench_modelsim": [ + "gAXIS_1to3_switch/Testbench/modelsim/gAXIS_1to3_switch.v" + ], + "external_testbench_ncsim": [ + "gAXIS_1to3_switch/Testbench/ncsim/gAXIS_1to3_switch.v" + ], + "external_testbench_aldec": [ + "gAXIS_1to3_switch/Testbench/aldec/gAXIS_1to3_switch.v" + ], + "external_testbench_testbench": [ + "gAXIS_1to3_switch/Testbench/modelsim.do", + "gAXIS_1to3_switch/Testbench/modelsim.sh", + "gAXIS_1to3_switch/Testbench/xrun.sh", + "gAXIS_1to3_switch/Testbench/axi_interconnect.vh", + "gAXIS_1to3_switch/Testbench/tb.v", + "gAXIS_1to3_switch/Testbench/top.v", + "gAXIS_1to3_switch/Testbench/efx_custom_slave_model.v", + "gAXIS_1to3_switch/Testbench/efx_crc32.v", + "gAXIS_1to3_switch/Testbench/efx_custom_master_model.v", + "gAXIS_1to3_switch/Testbench/efx_fifo_top.ncsim.v", + "gAXIS_1to3_switch/Testbench/efx_fifo_top.vcs.v", + "gAXIS_1to3_switch/Testbench/flist_ncsim", + "gAXIS_1to3_switch/Testbench/flist_modelsim", + "gAXIS_1to3_switch/Testbench/efx_fifo_top.modelsim.v", + "gAXIS_1to3_switch/Testbench/gAXIS_1to3_switch.v", + "gAXIS_1to3_switch/Testbench/gAXIS_1to3_switch_define.vh" + ] + }, + "ooc_synthesis": {}, + "sw_version": "2025.1.95", + "generated_date": "2025-04-14T02:18:17.197392+00:00" +} \ No newline at end of file diff --git a/fpga/ip/gDMA/gDMA.v b/fpga/ip/gDMA/gDMA.v new file mode 100644 index 0000000..97c9922 --- /dev/null +++ b/fpga/ip/gDMA/gDMA.v @@ -0,0 +1,11641 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 6.4.2 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _a048ca8f51874147a1cd65d43e6523ef +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module gDMA +( + input clk, + input ctrl_reset, + input reset, + input ctrl_clk, + input [13:0] ctrl_PADDR, + output ctrl_PREADY, + input ctrl_PENABLE, + input ctrl_PSEL, + input ctrl_PWRITE, + input [31:0] ctrl_PWDATA, + output [31:0] ctrl_PRDATA, + output ctrl_PSLVERROR, + output [1:0] ctrl_interrupts, + output read_arvalid, + output [31:0] read_araddr, + input read_arready, + output [3:0] read_arregion, + output [7:0] read_arlen, + output [2:0] read_arsize, + output [1:0] read_arburst, + output read_arlock, + output [3:0] read_arcache, + output [3:0] read_arqos, + output [2:0] read_arprot, + output read_rready, + input read_rvalid, + input [127:0] read_rdata, + input read_rlast, + output write_awvalid, + input write_awready, + output [31:0] write_awaddr, + output [3:0] write_awregion, + output [7:0] write_awlen, + output [2:0] write_awsize, + output [1:0] write_awburst, + output write_awlock, + output [3:0] write_awcache, + output [3:0] write_awqos, + output [2:0] write_awprot, + output write_wvalid, + input write_wready, + output [127:0] write_wdata, + output [15:0] write_wstrb, + output write_wlast, + input write_bvalid, + output write_bready, + input [1:0] write_bresp, + output dat1_o_tvalid, + input dat1_o_tready, + output [7:0] dat1_o_tdata, + output [0:0] dat1_o_tkeep, + output [3:0] dat1_o_tdest, + output dat1_o_tlast, + output io_0_descriptorUpdate, + input dat1_o_clk, + input dat1_o_reset, + input dat0_i_clk, + input dat0_i_reset, + input dat0_i_tvalid, + output dat0_i_tready, + input [7:0] dat0_i_tdata, + input [0:0] dat0_i_tkeep, + input [3:0] dat0_i_tdest, + input dat0_i_tlast, + input [1:0] read_rresp, + output io_1_descriptorUpdate +); +`IP_MODULE_NAME(EfxDMA)u_EfxDMA +( + .clk ( clk ), + .ctrl_reset ( ctrl_reset ), + .reset ( reset ), + .ctrl_clk ( ctrl_clk ), + .ctrl_PADDR ( ctrl_PADDR ), + .ctrl_PREADY ( ctrl_PREADY ), + .ctrl_PENABLE ( ctrl_PENABLE ), + .ctrl_PSEL ( ctrl_PSEL ), + .ctrl_PWRITE ( ctrl_PWRITE ), + .ctrl_PWDATA ( ctrl_PWDATA ), + .ctrl_PRDATA ( ctrl_PRDATA ), + .ctrl_PSLVERROR ( ctrl_PSLVERROR ), + .ctrl_interrupts ( ctrl_interrupts ), + .read_arvalid ( read_arvalid ), + .read_araddr ( read_araddr ), + .read_arready ( read_arready ), + .read_arregion ( read_arregion ), + .read_arlen ( read_arlen ), + .read_arsize ( read_arsize ), + .read_arburst ( read_arburst ), + .read_arlock ( read_arlock ), + .read_arcache ( read_arcache ), + .read_arqos ( read_arqos ), + .read_arprot ( read_arprot ), + .read_rready ( read_rready ), + .read_rvalid ( read_rvalid ), + .read_rdata ( read_rdata ), + .read_rlast ( read_rlast ), + .write_awvalid ( write_awvalid ), + .write_awready ( write_awready ), + .write_awaddr ( write_awaddr ), + .write_awregion ( write_awregion ), + .write_awlen ( write_awlen ), + .write_awsize ( write_awsize ), + .write_awburst ( write_awburst ), + .write_awlock ( write_awlock ), + .write_awcache ( write_awcache ), + .write_awqos ( write_awqos ), + .write_awprot ( write_awprot ), + .write_wvalid ( write_wvalid ), + .write_wready ( write_wready ), + .write_wdata ( write_wdata ), + .write_wstrb ( write_wstrb ), + .write_wlast ( write_wlast ), + .write_bvalid ( write_bvalid ), + .write_bready ( write_bready ), + .write_bresp ( write_bresp ), + .dat1_o_tvalid ( dat1_o_tvalid ), + .dat1_o_tready ( dat1_o_tready ), + .dat1_o_tdata ( dat1_o_tdata ), + .dat1_o_tkeep ( dat1_o_tkeep ), + .dat1_o_tdest ( dat1_o_tdest ), + .dat1_o_tlast ( dat1_o_tlast ), + .io_0_descriptorUpdate ( io_0_descriptorUpdate ), + .dat1_o_clk ( dat1_o_clk ), + .dat1_o_reset ( dat1_o_reset ), + .dat0_i_clk ( dat0_i_clk ), + .dat0_i_reset ( dat0_i_reset ), + .dat0_i_tvalid ( dat0_i_tvalid ), + .dat0_i_tready ( dat0_i_tready ), + .dat0_i_tdata ( dat0_i_tdata ), + .dat0_i_tkeep ( dat0_i_tkeep ), + .dat0_i_tdest ( dat0_i_tdest ), + .dat0_i_tlast ( dat0_i_tlast ), + .read_rresp ( read_rresp ), + .io_1_descriptorUpdate ( io_1_descriptorUpdate ) +); +endmodule + +// Generator : SpinalHDL dev git head : a69f4b9a329be784802c37cd8038b7dc9aec3094 +// Component : EfxDMA_a048ca8f51874147a1cd65d43e6523ef + +`timescale 1ns/1ps + +module EfxDMA_a048ca8f51874147a1cd65d43e6523ef ( + input wire [13:0] ctrl_PADDR, + input wire [0:0] ctrl_PSEL, + input wire ctrl_PENABLE, + output wire ctrl_PREADY, + input wire ctrl_PWRITE, + input wire [31:0] ctrl_PWDATA, + output wire [31:0] ctrl_PRDATA, + output wire ctrl_PSLVERROR, + output wire [1:0] ctrl_interrupts, + output wire read_arvalid, + input wire read_arready, + output wire [31:0] read_araddr, + output wire [3:0] read_arregion, + output wire [7:0] read_arlen, + output wire [2:0] read_arsize, + output wire [1:0] read_arburst, + output wire [0:0] read_arlock, + output wire [3:0] read_arcache, + output wire [3:0] read_arqos, + output wire [2:0] read_arprot, + input wire read_rvalid, + output wire read_rready, + input wire [127:0] read_rdata, + input wire [1:0] read_rresp, + input wire read_rlast, + output wire write_awvalid, + input wire write_awready, + output wire [31:0] write_awaddr, + output wire [3:0] write_awregion, + output wire [7:0] write_awlen, + output wire [2:0] write_awsize, + output wire [1:0] write_awburst, + output wire [0:0] write_awlock, + output wire [3:0] write_awcache, + output wire [3:0] write_awqos, + output wire [2:0] write_awprot, + output wire write_wvalid, + input wire write_wready, + output wire [127:0] write_wdata, + output wire [15:0] write_wstrb, + output wire write_wlast, + input wire write_bvalid, + output wire write_bready, + input wire [1:0] write_bresp, + input wire dat0_i_tvalid, + output wire dat0_i_tready, + input wire [7:0] dat0_i_tdata, + input wire [0:0] dat0_i_tkeep, + input wire [3:0] dat0_i_tdest, + input wire dat0_i_tlast, + output wire dat1_o_tvalid, + input wire dat1_o_tready, + output wire [7:0] dat1_o_tdata, + output wire [0:0] dat1_o_tkeep, + output wire [3:0] dat1_o_tdest, + output wire dat1_o_tlast, + output wire io_0_descriptorUpdate, + output wire io_1_descriptorUpdate, + input wire clk, + input wire reset, + input wire ctrl_clk, + input wire ctrl_reset, + input wire dat0_i_clk, + input wire dat0_i_reset, + input wire dat1_o_clk, + input wire dat1_o_reset +); + + wire core_io_sgRead_cmd_valid; + wire core_io_sgRead_cmd_payload_last; + wire [0:0] core_io_sgRead_cmd_payload_fragment_opcode; + wire [31:0] core_io_sgRead_cmd_payload_fragment_address; + wire [4:0] core_io_sgRead_cmd_payload_fragment_length; + wire [0:0] core_io_sgRead_cmd_payload_fragment_context; + wire core_io_sgRead_rsp_ready; + wire core_io_sgWrite_cmd_valid; + wire core_io_sgWrite_cmd_payload_last; + wire [0:0] core_io_sgWrite_cmd_payload_fragment_opcode; + wire [31:0] core_io_sgWrite_cmd_payload_fragment_address; + wire [1:0] core_io_sgWrite_cmd_payload_fragment_length; + wire [127:0] core_io_sgWrite_cmd_payload_fragment_data; + wire [15:0] core_io_sgWrite_cmd_payload_fragment_mask; + wire [0:0] core_io_sgWrite_cmd_payload_fragment_context; + wire core_io_sgWrite_rsp_ready; + wire core_io_read_cmd_valid; + wire core_io_read_cmd_payload_last; + wire [0:0] core_io_read_cmd_payload_fragment_opcode; + wire [31:0] core_io_read_cmd_payload_fragment_address; + wire [11:0] core_io_read_cmd_payload_fragment_length; + wire [20:0] core_io_read_cmd_payload_fragment_context; + wire core_io_read_rsp_ready; + wire core_io_write_cmd_valid; + wire core_io_write_cmd_payload_last; + wire [0:0] core_io_write_cmd_payload_fragment_opcode; + wire [31:0] core_io_write_cmd_payload_fragment_address; + wire [11:0] core_io_write_cmd_payload_fragment_length; + wire [127:0] core_io_write_cmd_payload_fragment_data; + wire [15:0] core_io_write_cmd_payload_fragment_mask; + wire [12:0] core_io_write_cmd_payload_fragment_context; + wire core_io_write_rsp_ready; + wire core_io_outputs_0_valid; + wire [63:0] core_io_outputs_0_payload_data; + wire [7:0] core_io_outputs_0_payload_mask; + wire [3:0] core_io_outputs_0_payload_sink; + wire core_io_outputs_0_payload_last; + wire core_io_inputs_0_ready; + wire [1:0] core_io_interrupts; + wire core_io_ctrl_PREADY; + wire [31:0] core_io_ctrl_PRDATA; + wire core_io_ctrl_PSLVERROR; + wire core_ll_0_descriptorUpdate; + wire core_ll_1_descriptorUpdate; + wire withCtrlCc_apbCc_io_input_PREADY; + wire [31:0] withCtrlCc_apbCc_io_input_PRDATA; + wire withCtrlCc_apbCc_io_input_PSLVERROR; + wire [13:0] withCtrlCc_apbCc_io_output_PADDR; + wire [0:0] withCtrlCc_apbCc_io_output_PSEL; + wire withCtrlCc_apbCc_io_output_PENABLE; + wire withCtrlCc_apbCc_io_output_PWRITE; + wire [31:0] withCtrlCc_apbCc_io_output_PWDATA; + wire [1:0] io_interrupts_buffercc_io_dataOut; + wire readLogic_sourceRemover_io_input_cmd_ready; + wire readLogic_sourceRemover_io_input_rsp_valid; + wire readLogic_sourceRemover_io_input_rsp_payload_last; + wire [0:0] readLogic_sourceRemover_io_input_rsp_payload_fragment_source; + wire [0:0] readLogic_sourceRemover_io_input_rsp_payload_fragment_opcode; + wire [127:0] readLogic_sourceRemover_io_input_rsp_payload_fragment_data; + wire [20:0] readLogic_sourceRemover_io_input_rsp_payload_fragment_context; + wire readLogic_sourceRemover_io_output_cmd_valid; + wire readLogic_sourceRemover_io_output_cmd_payload_last; + wire [0:0] readLogic_sourceRemover_io_output_cmd_payload_fragment_opcode; + wire [31:0] readLogic_sourceRemover_io_output_cmd_payload_fragment_address; + wire [11:0] readLogic_sourceRemover_io_output_cmd_payload_fragment_length; + wire [21:0] readLogic_sourceRemover_io_output_cmd_payload_fragment_context; + wire readLogic_sourceRemover_io_output_rsp_ready; + wire readLogic_bridge_io_input_cmd_ready; + wire readLogic_bridge_io_input_rsp_valid; + wire readLogic_bridge_io_input_rsp_payload_last; + wire [0:0] readLogic_bridge_io_input_rsp_payload_fragment_opcode; + wire [127:0] readLogic_bridge_io_input_rsp_payload_fragment_data; + wire [21:0] readLogic_bridge_io_input_rsp_payload_fragment_context; + wire readLogic_bridge_io_output_ar_valid; + wire [31:0] readLogic_bridge_io_output_ar_payload_addr; + wire [7:0] readLogic_bridge_io_output_ar_payload_len; + wire [2:0] readLogic_bridge_io_output_ar_payload_size; + wire [3:0] readLogic_bridge_io_output_ar_payload_cache; + wire [2:0] readLogic_bridge_io_output_ar_payload_prot; + wire readLogic_bridge_io_output_r_ready; + wire writeLogic_sourceRemover_io_input_cmd_ready; + wire writeLogic_sourceRemover_io_input_rsp_valid; + wire writeLogic_sourceRemover_io_input_rsp_payload_last; + wire [0:0] writeLogic_sourceRemover_io_input_rsp_payload_fragment_source; + wire [0:0] writeLogic_sourceRemover_io_input_rsp_payload_fragment_opcode; + wire [12:0] writeLogic_sourceRemover_io_input_rsp_payload_fragment_context; + wire writeLogic_sourceRemover_io_output_cmd_valid; + wire writeLogic_sourceRemover_io_output_cmd_payload_last; + wire [0:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_opcode; + wire [31:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_address; + wire [11:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_length; + wire [127:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_data; + wire [15:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_mask; + wire [13:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_context; + wire writeLogic_sourceRemover_io_output_rsp_ready; + wire writeLogic_bridge_io_input_cmd_ready; + wire writeLogic_bridge_io_input_rsp_valid; + wire writeLogic_bridge_io_input_rsp_payload_last; + wire [0:0] writeLogic_bridge_io_input_rsp_payload_fragment_opcode; + wire [13:0] writeLogic_bridge_io_input_rsp_payload_fragment_context; + wire writeLogic_bridge_io_output_aw_valid; + wire [31:0] writeLogic_bridge_io_output_aw_payload_addr; + wire [7:0] writeLogic_bridge_io_output_aw_payload_len; + wire [2:0] writeLogic_bridge_io_output_aw_payload_size; + wire [3:0] writeLogic_bridge_io_output_aw_payload_cache; + wire [2:0] writeLogic_bridge_io_output_aw_payload_prot; + wire writeLogic_bridge_io_output_w_valid; + wire [127:0] writeLogic_bridge_io_output_w_payload_data; + wire [15:0] writeLogic_bridge_io_output_w_payload_strb; + wire writeLogic_bridge_io_output_w_payload_last; + wire writeLogic_bridge_io_output_b_ready; + wire inputsAdapter_0_upsizer_logic_io_input_ready; + wire inputsAdapter_0_upsizer_logic_io_output_valid; + wire [63:0] inputsAdapter_0_upsizer_logic_io_output_payload_data; + wire [7:0] inputsAdapter_0_upsizer_logic_io_output_payload_mask; + wire [3:0] inputsAdapter_0_upsizer_logic_io_output_payload_sink; + wire inputsAdapter_0_upsizer_logic_io_output_payload_last; + wire inputsAdapter_0_crossclock_fifo_io_push_ready; + wire inputsAdapter_0_crossclock_fifo_io_pop_valid; + wire [63:0] inputsAdapter_0_crossclock_fifo_io_pop_payload_data; + wire [7:0] inputsAdapter_0_crossclock_fifo_io_pop_payload_mask; + wire [3:0] inputsAdapter_0_crossclock_fifo_io_pop_payload_sink; + wire inputsAdapter_0_crossclock_fifo_io_pop_payload_last; + wire [4:0] inputsAdapter_0_crossclock_fifo_io_pushOccupancy; + wire [4:0] inputsAdapter_0_crossclock_fifo_io_popOccupancy; + wire outputsAdapter_0_crossclock_fifo_io_push_ready; + wire outputsAdapter_0_crossclock_fifo_io_pop_valid; + wire [63:0] outputsAdapter_0_crossclock_fifo_io_pop_payload_data; + wire [7:0] outputsAdapter_0_crossclock_fifo_io_pop_payload_mask; + wire [3:0] outputsAdapter_0_crossclock_fifo_io_pop_payload_sink; + wire outputsAdapter_0_crossclock_fifo_io_pop_payload_last; + wire [4:0] outputsAdapter_0_crossclock_fifo_io_pushOccupancy; + wire [4:0] outputsAdapter_0_crossclock_fifo_io_popOccupancy; + wire outputsAdapter_0_sparseDownsizer_logic_io_input_ready; + wire outputsAdapter_0_sparseDownsizer_logic_io_output_valid; + wire [7:0] outputsAdapter_0_sparseDownsizer_logic_io_output_payload_data; + wire [0:0] outputsAdapter_0_sparseDownsizer_logic_io_output_payload_mask; + wire [3:0] outputsAdapter_0_sparseDownsizer_logic_io_output_payload_sink; + wire outputsAdapter_0_sparseDownsizer_logic_io_output_payload_last; + wire interconnect_read_aggregated_arbiter_io_inputs_0_cmd_ready; + wire interconnect_read_aggregated_arbiter_io_inputs_0_rsp_valid; + wire interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_last; + wire [0:0] interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode; + wire [127:0] interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_data; + wire [0:0] interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context; + wire interconnect_read_aggregated_arbiter_io_inputs_1_cmd_ready; + wire interconnect_read_aggregated_arbiter_io_inputs_1_rsp_valid; + wire interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_last; + wire [0:0] interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode; + wire [127:0] interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_data; + wire [20:0] interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context; + wire interconnect_read_aggregated_arbiter_io_output_cmd_valid; + wire interconnect_read_aggregated_arbiter_io_output_cmd_payload_last; + wire [0:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_source; + wire [0:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_opcode; + wire [31:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_address; + wire [11:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_length; + wire [20:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_context; + wire interconnect_read_aggregated_arbiter_io_output_rsp_ready; + wire interconnect_write_aggregated_arbiter_io_inputs_0_cmd_ready; + wire interconnect_write_aggregated_arbiter_io_inputs_0_rsp_valid; + wire interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_last; + wire [0:0] interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode; + wire [0:0] interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context; + wire interconnect_write_aggregated_arbiter_io_inputs_1_cmd_ready; + wire interconnect_write_aggregated_arbiter_io_inputs_1_rsp_valid; + wire interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_last; + wire [0:0] interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode; + wire [12:0] interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context; + wire interconnect_write_aggregated_arbiter_io_output_cmd_valid; + wire interconnect_write_aggregated_arbiter_io_output_cmd_payload_last; + wire [0:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_source; + wire [0:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_opcode; + wire [31:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_address; + wire [11:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_length; + wire [127:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_data; + wire [15:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_mask; + wire [12:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_context; + wire interconnect_write_aggregated_arbiter_io_output_rsp_ready; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode; + wire [31:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address; + wire [11:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length; + wire [20:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode; + wire [127:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_data; + wire [20:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode; + wire [31:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address; + wire [4:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode; + wire [127:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode; + wire [31:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address; + wire [11:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length; + wire [127:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_data; + wire [15:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_mask; + wire [12:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode; + wire [12:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context; + wire io_write_cmd_s2mPipe_valid; + reg io_write_cmd_s2mPipe_ready; + wire io_write_cmd_s2mPipe_payload_last; + wire [0:0] io_write_cmd_s2mPipe_payload_fragment_opcode; + wire [31:0] io_write_cmd_s2mPipe_payload_fragment_address; + wire [11:0] io_write_cmd_s2mPipe_payload_fragment_length; + wire [127:0] io_write_cmd_s2mPipe_payload_fragment_data; + wire [15:0] io_write_cmd_s2mPipe_payload_fragment_mask; + wire [12:0] io_write_cmd_s2mPipe_payload_fragment_context; + reg io_write_cmd_rValidN; + reg io_write_cmd_rData_last; + reg [0:0] io_write_cmd_rData_fragment_opcode; + reg [31:0] io_write_cmd_rData_fragment_address; + reg [11:0] io_write_cmd_rData_fragment_length; + reg [127:0] io_write_cmd_rData_fragment_data; + reg [15:0] io_write_cmd_rData_fragment_mask; + reg [12:0] io_write_cmd_rData_fragment_context; + wire io_write_cmd_s2mPipe_m2sPipe_valid; + wire io_write_cmd_s2mPipe_m2sPipe_ready; + wire io_write_cmd_s2mPipe_m2sPipe_payload_last; + wire [0:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_opcode; + wire [31:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_address; + wire [11:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_length; + wire [127:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_data; + wire [15:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_mask; + wire [12:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_context; + reg io_write_cmd_s2mPipe_rValid; + reg io_write_cmd_s2mPipe_rData_last; + reg [0:0] io_write_cmd_s2mPipe_rData_fragment_opcode; + reg [31:0] io_write_cmd_s2mPipe_rData_fragment_address; + reg [11:0] io_write_cmd_s2mPipe_rData_fragment_length; + reg [127:0] io_write_cmd_s2mPipe_rData_fragment_data; + reg [15:0] io_write_cmd_s2mPipe_rData_fragment_mask; + reg [12:0] io_write_cmd_s2mPipe_rData_fragment_context; + wire when_Stream_l375; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode; + wire [31:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address; + wire [1:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length; + wire [127:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data; + wire [15:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context; + wire interconnect_read_aggregated_cmd_valid; + wire interconnect_read_aggregated_cmd_ready; + wire interconnect_read_aggregated_cmd_payload_last; + wire [0:0] interconnect_read_aggregated_cmd_payload_fragment_source; + wire [0:0] interconnect_read_aggregated_cmd_payload_fragment_opcode; + wire [31:0] interconnect_read_aggregated_cmd_payload_fragment_address; + wire [11:0] interconnect_read_aggregated_cmd_payload_fragment_length; + wire [20:0] interconnect_read_aggregated_cmd_payload_fragment_context; + wire interconnect_read_aggregated_rsp_valid; + wire interconnect_read_aggregated_rsp_ready; + wire interconnect_read_aggregated_rsp_payload_last; + wire [0:0] interconnect_read_aggregated_rsp_payload_fragment_source; + wire [0:0] interconnect_read_aggregated_rsp_payload_fragment_opcode; + wire [127:0] interconnect_read_aggregated_rsp_payload_fragment_data; + wire [20:0] interconnect_read_aggregated_rsp_payload_fragment_context; + wire interconnect_write_aggregated_cmd_valid; + reg interconnect_write_aggregated_cmd_ready; + wire interconnect_write_aggregated_cmd_payload_last; + wire [0:0] interconnect_write_aggregated_cmd_payload_fragment_source; + wire [0:0] interconnect_write_aggregated_cmd_payload_fragment_opcode; + wire [31:0] interconnect_write_aggregated_cmd_payload_fragment_address; + wire [11:0] interconnect_write_aggregated_cmd_payload_fragment_length; + wire [127:0] interconnect_write_aggregated_cmd_payload_fragment_data; + wire [15:0] interconnect_write_aggregated_cmd_payload_fragment_mask; + wire [12:0] interconnect_write_aggregated_cmd_payload_fragment_context; + wire interconnect_write_aggregated_rsp_valid; + wire interconnect_write_aggregated_rsp_ready; + wire interconnect_write_aggregated_rsp_payload_last; + wire [0:0] interconnect_write_aggregated_rsp_payload_fragment_source; + wire [0:0] interconnect_write_aggregated_rsp_payload_fragment_opcode; + wire [12:0] interconnect_write_aggregated_rsp_payload_fragment_context; + wire readLogic_resized_cmd_valid; + wire readLogic_resized_cmd_ready; + wire readLogic_resized_cmd_payload_last; + wire [0:0] readLogic_resized_cmd_payload_fragment_source; + wire [0:0] readLogic_resized_cmd_payload_fragment_opcode; + wire [31:0] readLogic_resized_cmd_payload_fragment_address; + wire [11:0] readLogic_resized_cmd_payload_fragment_length; + wire [20:0] readLogic_resized_cmd_payload_fragment_context; + wire readLogic_resized_rsp_valid; + wire readLogic_resized_rsp_ready; + wire readLogic_resized_rsp_payload_last; + wire [0:0] readLogic_resized_rsp_payload_fragment_source; + wire [0:0] readLogic_resized_rsp_payload_fragment_opcode; + wire [127:0] readLogic_resized_rsp_payload_fragment_data; + wire [20:0] readLogic_resized_rsp_payload_fragment_context; + wire interconnect_read_aggregated_cmd_halfPipe_valid; + wire interconnect_read_aggregated_cmd_halfPipe_ready; + wire interconnect_read_aggregated_cmd_halfPipe_payload_last; + wire [0:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_source; + wire [0:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_opcode; + wire [31:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_address; + wire [11:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_length; + wire [20:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_context; + reg interconnect_read_aggregated_cmd_rValid; + wire interconnect_read_aggregated_cmd_halfPipe_fire; + reg interconnect_read_aggregated_cmd_rData_last; + reg [0:0] interconnect_read_aggregated_cmd_rData_fragment_source; + reg [0:0] interconnect_read_aggregated_cmd_rData_fragment_opcode; + reg [31:0] interconnect_read_aggregated_cmd_rData_fragment_address; + reg [11:0] interconnect_read_aggregated_cmd_rData_fragment_length; + reg [20:0] interconnect_read_aggregated_cmd_rData_fragment_context; + wire readLogic_resized_rsp_combStage_valid; + wire readLogic_resized_rsp_combStage_ready; + wire readLogic_resized_rsp_combStage_payload_last; + wire [0:0] readLogic_resized_rsp_combStage_payload_fragment_source; + wire [0:0] readLogic_resized_rsp_combStage_payload_fragment_opcode; + wire [127:0] readLogic_resized_rsp_combStage_payload_fragment_data; + wire [20:0] readLogic_resized_rsp_combStage_payload_fragment_context; + wire readLogic_adapter_ar_valid; + wire readLogic_adapter_ar_ready; + wire [31:0] readLogic_adapter_ar_payload_addr; + wire [3:0] readLogic_adapter_ar_payload_region; + wire [7:0] readLogic_adapter_ar_payload_len; + wire [2:0] readLogic_adapter_ar_payload_size; + wire [1:0] readLogic_adapter_ar_payload_burst; + wire [0:0] readLogic_adapter_ar_payload_lock; + wire [3:0] readLogic_adapter_ar_payload_cache; + wire [3:0] readLogic_adapter_ar_payload_qos; + wire [2:0] readLogic_adapter_ar_payload_prot; + wire readLogic_adapter_r_valid; + wire readLogic_adapter_r_ready; + wire [127:0] readLogic_adapter_r_payload_data; + wire [1:0] readLogic_adapter_r_payload_resp; + wire readLogic_adapter_r_payload_last; + wire [3:0] _zz_readLogic_adapter_ar_payload_region; + wire readLogic_adapter_ar_halfPipe_valid; + wire readLogic_adapter_ar_halfPipe_ready; + wire [31:0] readLogic_adapter_ar_halfPipe_payload_addr; + wire [3:0] readLogic_adapter_ar_halfPipe_payload_region; + wire [7:0] readLogic_adapter_ar_halfPipe_payload_len; + wire [2:0] readLogic_adapter_ar_halfPipe_payload_size; + wire [1:0] readLogic_adapter_ar_halfPipe_payload_burst; + wire [0:0] readLogic_adapter_ar_halfPipe_payload_lock; + wire [3:0] readLogic_adapter_ar_halfPipe_payload_cache; + wire [3:0] readLogic_adapter_ar_halfPipe_payload_qos; + wire [2:0] readLogic_adapter_ar_halfPipe_payload_prot; + reg readLogic_adapter_ar_rValid; + wire readLogic_adapter_ar_halfPipe_fire; + reg [31:0] readLogic_adapter_ar_rData_addr; + reg [3:0] readLogic_adapter_ar_rData_region; + reg [7:0] readLogic_adapter_ar_rData_len; + reg [2:0] readLogic_adapter_ar_rData_size; + reg [1:0] readLogic_adapter_ar_rData_burst; + reg [0:0] readLogic_adapter_ar_rData_lock; + reg [3:0] readLogic_adapter_ar_rData_cache; + reg [3:0] readLogic_adapter_ar_rData_qos; + reg [2:0] readLogic_adapter_ar_rData_prot; + wire read_r_s2mPipe_valid; + reg read_r_s2mPipe_ready; + wire [127:0] read_r_s2mPipe_payload_data; + wire [1:0] read_r_s2mPipe_payload_resp; + wire read_r_s2mPipe_payload_last; + reg read_r_rValidN; + reg [127:0] read_r_rData_data; + reg [1:0] read_r_rData_resp; + reg read_r_rData_last; + wire readLogic_beforeQueue_valid; + wire readLogic_beforeQueue_ready; + wire [127:0] readLogic_beforeQueue_payload_data; + wire [1:0] readLogic_beforeQueue_payload_resp; + wire readLogic_beforeQueue_payload_last; + reg read_r_s2mPipe_rValid; + reg [127:0] read_r_s2mPipe_rData_data; + reg [1:0] read_r_s2mPipe_rData_resp; + reg read_r_s2mPipe_rData_last; + wire when_Stream_l375_1; + wire writeLogic_resized_cmd_valid; + wire writeLogic_resized_cmd_ready; + wire writeLogic_resized_cmd_payload_last; + wire [0:0] writeLogic_resized_cmd_payload_fragment_source; + wire [0:0] writeLogic_resized_cmd_payload_fragment_opcode; + wire [31:0] writeLogic_resized_cmd_payload_fragment_address; + wire [11:0] writeLogic_resized_cmd_payload_fragment_length; + wire [127:0] writeLogic_resized_cmd_payload_fragment_data; + wire [15:0] writeLogic_resized_cmd_payload_fragment_mask; + wire [12:0] writeLogic_resized_cmd_payload_fragment_context; + wire writeLogic_resized_rsp_valid; + wire writeLogic_resized_rsp_ready; + wire writeLogic_resized_rsp_payload_last; + wire [0:0] writeLogic_resized_rsp_payload_fragment_source; + wire [0:0] writeLogic_resized_rsp_payload_fragment_opcode; + wire [12:0] writeLogic_resized_rsp_payload_fragment_context; + wire interconnect_write_aggregated_cmd_m2sPipe_valid; + wire interconnect_write_aggregated_cmd_m2sPipe_ready; + wire interconnect_write_aggregated_cmd_m2sPipe_payload_last; + wire [0:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_source; + wire [0:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_opcode; + wire [31:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_address; + wire [11:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_length; + wire [127:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_data; + wire [15:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_mask; + wire [12:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_context; + reg interconnect_write_aggregated_cmd_rValid; + reg interconnect_write_aggregated_cmd_rData_last; + reg [0:0] interconnect_write_aggregated_cmd_rData_fragment_source; + reg [0:0] interconnect_write_aggregated_cmd_rData_fragment_opcode; + reg [31:0] interconnect_write_aggregated_cmd_rData_fragment_address; + reg [11:0] interconnect_write_aggregated_cmd_rData_fragment_length; + reg [127:0] interconnect_write_aggregated_cmd_rData_fragment_data; + reg [15:0] interconnect_write_aggregated_cmd_rData_fragment_mask; + reg [12:0] interconnect_write_aggregated_cmd_rData_fragment_context; + wire when_Stream_l375_2; + wire writeLogic_resized_rsp_combStage_valid; + wire writeLogic_resized_rsp_combStage_ready; + wire writeLogic_resized_rsp_combStage_payload_last; + wire [0:0] writeLogic_resized_rsp_combStage_payload_fragment_source; + wire [0:0] writeLogic_resized_rsp_combStage_payload_fragment_opcode; + wire [12:0] writeLogic_resized_rsp_combStage_payload_fragment_context; + wire writeLogic_adapter_aw_valid; + wire writeLogic_adapter_aw_ready; + wire [31:0] writeLogic_adapter_aw_payload_addr; + wire [3:0] writeLogic_adapter_aw_payload_region; + wire [7:0] writeLogic_adapter_aw_payload_len; + wire [2:0] writeLogic_adapter_aw_payload_size; + wire [1:0] writeLogic_adapter_aw_payload_burst; + wire [0:0] writeLogic_adapter_aw_payload_lock; + wire [3:0] writeLogic_adapter_aw_payload_cache; + wire [3:0] writeLogic_adapter_aw_payload_qos; + wire [2:0] writeLogic_adapter_aw_payload_prot; + wire writeLogic_adapter_w_valid; + wire writeLogic_adapter_w_ready; + wire [127:0] writeLogic_adapter_w_payload_data; + wire [15:0] writeLogic_adapter_w_payload_strb; + wire writeLogic_adapter_w_payload_last; + wire writeLogic_adapter_b_valid; + wire writeLogic_adapter_b_ready; + wire [1:0] writeLogic_adapter_b_payload_resp; + wire [3:0] _zz_writeLogic_adapter_aw_payload_region; + wire writeLogic_adapter_aw_halfPipe_valid; + wire writeLogic_adapter_aw_halfPipe_ready; + wire [31:0] writeLogic_adapter_aw_halfPipe_payload_addr; + wire [3:0] writeLogic_adapter_aw_halfPipe_payload_region; + wire [7:0] writeLogic_adapter_aw_halfPipe_payload_len; + wire [2:0] writeLogic_adapter_aw_halfPipe_payload_size; + wire [1:0] writeLogic_adapter_aw_halfPipe_payload_burst; + wire [0:0] writeLogic_adapter_aw_halfPipe_payload_lock; + wire [3:0] writeLogic_adapter_aw_halfPipe_payload_cache; + wire [3:0] writeLogic_adapter_aw_halfPipe_payload_qos; + wire [2:0] writeLogic_adapter_aw_halfPipe_payload_prot; + reg writeLogic_adapter_aw_rValid; + wire writeLogic_adapter_aw_halfPipe_fire; + reg [31:0] writeLogic_adapter_aw_rData_addr; + reg [3:0] writeLogic_adapter_aw_rData_region; + reg [7:0] writeLogic_adapter_aw_rData_len; + reg [2:0] writeLogic_adapter_aw_rData_size; + reg [1:0] writeLogic_adapter_aw_rData_burst; + reg [0:0] writeLogic_adapter_aw_rData_lock; + reg [3:0] writeLogic_adapter_aw_rData_cache; + reg [3:0] writeLogic_adapter_aw_rData_qos; + reg [2:0] writeLogic_adapter_aw_rData_prot; + wire writeLogic_adapter_w_s2mPipe_valid; + reg writeLogic_adapter_w_s2mPipe_ready; + wire [127:0] writeLogic_adapter_w_s2mPipe_payload_data; + wire [15:0] writeLogic_adapter_w_s2mPipe_payload_strb; + wire writeLogic_adapter_w_s2mPipe_payload_last; + reg writeLogic_adapter_w_rValidN; + reg [127:0] writeLogic_adapter_w_rData_data; + reg [15:0] writeLogic_adapter_w_rData_strb; + reg writeLogic_adapter_w_rData_last; + wire writeLogic_adapter_w_s2mPipe_m2sPipe_valid; + wire writeLogic_adapter_w_s2mPipe_m2sPipe_ready; + wire [127:0] writeLogic_adapter_w_s2mPipe_m2sPipe_payload_data; + wire [15:0] writeLogic_adapter_w_s2mPipe_m2sPipe_payload_strb; + wire writeLogic_adapter_w_s2mPipe_m2sPipe_payload_last; + reg writeLogic_adapter_w_s2mPipe_rValid; + reg [127:0] writeLogic_adapter_w_s2mPipe_rData_data; + reg [15:0] writeLogic_adapter_w_s2mPipe_rData_strb; + reg writeLogic_adapter_w_s2mPipe_rData_last; + wire when_Stream_l375_3; + wire write_b_halfPipe_valid; + wire write_b_halfPipe_ready; + wire [1:0] write_b_halfPipe_payload_resp; + reg write_b_rValid; + wire write_b_halfPipe_fire; + reg [1:0] write_b_rData_resp; + wire io_pop_s2mPipe_valid; + reg io_pop_s2mPipe_ready; + wire [63:0] io_pop_s2mPipe_payload_data; + wire [7:0] io_pop_s2mPipe_payload_mask; + wire [3:0] io_pop_s2mPipe_payload_sink; + wire io_pop_s2mPipe_payload_last; + reg io_pop_rValidN; + reg [63:0] io_pop_rData_data; + reg [7:0] io_pop_rData_mask; + reg [3:0] io_pop_rData_sink; + reg io_pop_rData_last; + wire io_pop_s2mPipe_m2sPipe_valid; + wire io_pop_s2mPipe_m2sPipe_ready; + wire [63:0] io_pop_s2mPipe_m2sPipe_payload_data; + wire [7:0] io_pop_s2mPipe_m2sPipe_payload_mask; + wire [3:0] io_pop_s2mPipe_m2sPipe_payload_sink; + wire io_pop_s2mPipe_m2sPipe_payload_last; + reg io_pop_s2mPipe_rValid; + reg [63:0] io_pop_s2mPipe_rData_data; + reg [7:0] io_pop_s2mPipe_rData_mask; + reg [3:0] io_pop_s2mPipe_rData_sink; + reg io_pop_s2mPipe_rData_last; + wire when_Stream_l375_4; + wire io_outputs_0_s2mPipe_valid; + reg io_outputs_0_s2mPipe_ready; + wire [63:0] io_outputs_0_s2mPipe_payload_data; + wire [7:0] io_outputs_0_s2mPipe_payload_mask; + wire [3:0] io_outputs_0_s2mPipe_payload_sink; + wire io_outputs_0_s2mPipe_payload_last; + reg io_outputs_0_rValidN; + reg [63:0] io_outputs_0_rData_data; + reg [7:0] io_outputs_0_rData_mask; + reg [3:0] io_outputs_0_rData_sink; + reg io_outputs_0_rData_last; + wire outputsAdapter_0_ptr_valid; + wire outputsAdapter_0_ptr_ready; + wire [63:0] outputsAdapter_0_ptr_payload_data; + wire [7:0] outputsAdapter_0_ptr_payload_mask; + wire [3:0] outputsAdapter_0_ptr_payload_sink; + wire outputsAdapter_0_ptr_payload_last; + reg io_outputs_0_s2mPipe_rValid; + reg [63:0] io_outputs_0_s2mPipe_rData_data; + reg [7:0] io_outputs_0_s2mPipe_rData_mask; + reg [3:0] io_outputs_0_s2mPipe_rData_sink; + reg io_outputs_0_s2mPipe_rData_last; + wire when_Stream_l375_5; + + EfxDMA_Core_a048ca8f51874147a1cd65d43e6523ef core ( + .io_sgRead_cmd_valid (core_io_sgRead_cmd_valid ), //o + .io_sgRead_cmd_ready (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready ), //i + .io_sgRead_cmd_payload_last (core_io_sgRead_cmd_payload_last ), //o + .io_sgRead_cmd_payload_fragment_opcode (core_io_sgRead_cmd_payload_fragment_opcode ), //o + .io_sgRead_cmd_payload_fragment_address (core_io_sgRead_cmd_payload_fragment_address[31:0] ), //o + .io_sgRead_cmd_payload_fragment_length (core_io_sgRead_cmd_payload_fragment_length[4:0] ), //o + .io_sgRead_cmd_payload_fragment_context (core_io_sgRead_cmd_payload_fragment_context ), //o + .io_sgRead_rsp_valid (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid ), //i + .io_sgRead_rsp_ready (core_io_sgRead_rsp_ready ), //o + .io_sgRead_rsp_payload_last (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last ), //i + .io_sgRead_rsp_payload_fragment_opcode (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode ), //i + .io_sgRead_rsp_payload_fragment_data (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data[127:0] ), //i + .io_sgRead_rsp_payload_fragment_context (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context ), //i + .io_sgWrite_cmd_valid (core_io_sgWrite_cmd_valid ), //o + .io_sgWrite_cmd_ready (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready ), //i + .io_sgWrite_cmd_payload_last (core_io_sgWrite_cmd_payload_last ), //o + .io_sgWrite_cmd_payload_fragment_opcode (core_io_sgWrite_cmd_payload_fragment_opcode ), //o + .io_sgWrite_cmd_payload_fragment_address (core_io_sgWrite_cmd_payload_fragment_address[31:0] ), //o + .io_sgWrite_cmd_payload_fragment_length (core_io_sgWrite_cmd_payload_fragment_length[1:0] ), //o + .io_sgWrite_cmd_payload_fragment_data (core_io_sgWrite_cmd_payload_fragment_data[127:0] ), //o + .io_sgWrite_cmd_payload_fragment_mask (core_io_sgWrite_cmd_payload_fragment_mask[15:0] ), //o + .io_sgWrite_cmd_payload_fragment_context (core_io_sgWrite_cmd_payload_fragment_context ), //o + .io_sgWrite_rsp_valid (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid ), //i + .io_sgWrite_rsp_ready (core_io_sgWrite_rsp_ready ), //o + .io_sgWrite_rsp_payload_last (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last ), //i + .io_sgWrite_rsp_payload_fragment_opcode (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode ), //i + .io_sgWrite_rsp_payload_fragment_context (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context ), //i + .io_read_cmd_valid (core_io_read_cmd_valid ), //o + .io_read_cmd_ready (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready ), //i + .io_read_cmd_payload_last (core_io_read_cmd_payload_last ), //o + .io_read_cmd_payload_fragment_opcode (core_io_read_cmd_payload_fragment_opcode ), //o + .io_read_cmd_payload_fragment_address (core_io_read_cmd_payload_fragment_address[31:0] ), //o + .io_read_cmd_payload_fragment_length (core_io_read_cmd_payload_fragment_length[11:0] ), //o + .io_read_cmd_payload_fragment_context (core_io_read_cmd_payload_fragment_context[20:0] ), //o + .io_read_rsp_valid (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid ), //i + .io_read_rsp_ready (core_io_read_rsp_ready ), //o + .io_read_rsp_payload_last (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last ), //i + .io_read_rsp_payload_fragment_opcode (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode ), //i + .io_read_rsp_payload_fragment_data (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_data[127:0] ), //i + .io_read_rsp_payload_fragment_context (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context[20:0] ), //i + .io_write_cmd_valid (core_io_write_cmd_valid ), //o + .io_write_cmd_ready (io_write_cmd_rValidN ), //i + .io_write_cmd_payload_last (core_io_write_cmd_payload_last ), //o + .io_write_cmd_payload_fragment_opcode (core_io_write_cmd_payload_fragment_opcode ), //o + .io_write_cmd_payload_fragment_address (core_io_write_cmd_payload_fragment_address[31:0] ), //o + .io_write_cmd_payload_fragment_length (core_io_write_cmd_payload_fragment_length[11:0] ), //o + .io_write_cmd_payload_fragment_data (core_io_write_cmd_payload_fragment_data[127:0] ), //o + .io_write_cmd_payload_fragment_mask (core_io_write_cmd_payload_fragment_mask[15:0] ), //o + .io_write_cmd_payload_fragment_context (core_io_write_cmd_payload_fragment_context[12:0] ), //o + .io_write_rsp_valid (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid ), //i + .io_write_rsp_ready (core_io_write_rsp_ready ), //o + .io_write_rsp_payload_last (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last ), //i + .io_write_rsp_payload_fragment_opcode (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode ), //i + .io_write_rsp_payload_fragment_context (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context[12:0]), //i + .io_outputs_0_valid (core_io_outputs_0_valid ), //o + .io_outputs_0_ready (io_outputs_0_rValidN ), //i + .io_outputs_0_payload_data (core_io_outputs_0_payload_data[63:0] ), //o + .io_outputs_0_payload_mask (core_io_outputs_0_payload_mask[7:0] ), //o + .io_outputs_0_payload_sink (core_io_outputs_0_payload_sink[3:0] ), //o + .io_outputs_0_payload_last (core_io_outputs_0_payload_last ), //o + .io_inputs_0_valid (io_pop_s2mPipe_m2sPipe_valid ), //i + .io_inputs_0_ready (core_io_inputs_0_ready ), //o + .io_inputs_0_payload_data (io_pop_s2mPipe_m2sPipe_payload_data[63:0] ), //i + .io_inputs_0_payload_mask (io_pop_s2mPipe_m2sPipe_payload_mask[7:0] ), //i + .io_inputs_0_payload_sink (io_pop_s2mPipe_m2sPipe_payload_sink[3:0] ), //i + .io_inputs_0_payload_last (io_pop_s2mPipe_m2sPipe_payload_last ), //i + .io_interrupts (core_io_interrupts[1:0] ), //o + .io_ctrl_PADDR (withCtrlCc_apbCc_io_output_PADDR[13:0] ), //i + .io_ctrl_PSEL (withCtrlCc_apbCc_io_output_PSEL ), //i + .io_ctrl_PENABLE (withCtrlCc_apbCc_io_output_PENABLE ), //i + .io_ctrl_PREADY (core_io_ctrl_PREADY ), //o + .io_ctrl_PWRITE (withCtrlCc_apbCc_io_output_PWRITE ), //i + .io_ctrl_PWDATA (withCtrlCc_apbCc_io_output_PWDATA[31:0] ), //i + .io_ctrl_PRDATA (core_io_ctrl_PRDATA[31:0] ), //o + .io_ctrl_PSLVERROR (core_io_ctrl_PSLVERROR ), //o + .ll_0_descriptorUpdate (core_ll_0_descriptorUpdate ), //o + .ll_1_descriptorUpdate (core_ll_1_descriptorUpdate ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_Apb3CC_a048ca8f51874147a1cd65d43e6523ef withCtrlCc_apbCc ( + .io_input_PADDR (ctrl_PADDR[13:0] ), //i + .io_input_PSEL (ctrl_PSEL ), //i + .io_input_PENABLE (ctrl_PENABLE ), //i + .io_input_PREADY (withCtrlCc_apbCc_io_input_PREADY ), //o + .io_input_PWRITE (ctrl_PWRITE ), //i + .io_input_PWDATA (ctrl_PWDATA[31:0] ), //i + .io_input_PRDATA (withCtrlCc_apbCc_io_input_PRDATA[31:0] ), //o + .io_input_PSLVERROR (withCtrlCc_apbCc_io_input_PSLVERROR ), //o + .io_output_PADDR (withCtrlCc_apbCc_io_output_PADDR[13:0] ), //o + .io_output_PSEL (withCtrlCc_apbCc_io_output_PSEL ), //o + .io_output_PENABLE (withCtrlCc_apbCc_io_output_PENABLE ), //o + .io_output_PREADY (core_io_ctrl_PREADY ), //i + .io_output_PWRITE (withCtrlCc_apbCc_io_output_PWRITE ), //o + .io_output_PWDATA (withCtrlCc_apbCc_io_output_PWDATA[31:0]), //o + .io_output_PRDATA (core_io_ctrl_PRDATA[31:0] ), //i + .io_output_PSLVERROR (core_io_ctrl_PSLVERROR ), //i + .ctrl_clk (ctrl_clk ), //i + .ctrl_reset (ctrl_reset ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_6_a048ca8f51874147a1cd65d43e6523ef io_interrupts_buffercc ( + .io_dataIn (core_io_interrupts[1:0] ), //i + .io_dataOut (io_interrupts_buffercc_io_dataOut[1:0]), //o + .ctrl_clk (ctrl_clk ), //i + .ctrl_reset (ctrl_reset ) //i + ); + EfxDMA_BmbSourceRemover_a048ca8f51874147a1cd65d43e6523ef readLogic_sourceRemover ( + .io_input_cmd_valid (readLogic_resized_cmd_valid ), //i + .io_input_cmd_ready (readLogic_sourceRemover_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (readLogic_resized_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (readLogic_resized_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (readLogic_resized_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (readLogic_resized_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (readLogic_resized_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_context (readLogic_resized_cmd_payload_fragment_context[20:0] ), //i + .io_input_rsp_valid (readLogic_sourceRemover_io_input_rsp_valid ), //o + .io_input_rsp_ready (readLogic_resized_rsp_ready ), //i + .io_input_rsp_payload_last (readLogic_sourceRemover_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (readLogic_sourceRemover_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (readLogic_sourceRemover_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (readLogic_sourceRemover_io_input_rsp_payload_fragment_data[127:0] ), //o + .io_input_rsp_payload_fragment_context (readLogic_sourceRemover_io_input_rsp_payload_fragment_context[20:0] ), //o + .io_output_cmd_valid (readLogic_sourceRemover_io_output_cmd_valid ), //o + .io_output_cmd_ready (readLogic_bridge_io_input_cmd_ready ), //i + .io_output_cmd_payload_last (readLogic_sourceRemover_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (readLogic_sourceRemover_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (readLogic_sourceRemover_io_output_cmd_payload_fragment_address[31:0]), //o + .io_output_cmd_payload_fragment_length (readLogic_sourceRemover_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_cmd_payload_fragment_context (readLogic_sourceRemover_io_output_cmd_payload_fragment_context[21:0]), //o + .io_output_rsp_valid (readLogic_bridge_io_input_rsp_valid ), //i + .io_output_rsp_ready (readLogic_sourceRemover_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (readLogic_bridge_io_input_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (readLogic_bridge_io_input_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (readLogic_bridge_io_input_rsp_payload_fragment_data[127:0] ), //i + .io_output_rsp_payload_fragment_context (readLogic_bridge_io_input_rsp_payload_fragment_context[21:0] ) //i + ); + EfxDMA_BmbToAxi4ReadOnlyBridge_a048ca8f51874147a1cd65d43e6523ef readLogic_bridge ( + .io_input_cmd_valid (readLogic_sourceRemover_io_output_cmd_valid ), //i + .io_input_cmd_ready (readLogic_bridge_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (readLogic_sourceRemover_io_output_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (readLogic_sourceRemover_io_output_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (readLogic_sourceRemover_io_output_cmd_payload_fragment_address[31:0]), //i + .io_input_cmd_payload_fragment_length (readLogic_sourceRemover_io_output_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_context (readLogic_sourceRemover_io_output_cmd_payload_fragment_context[21:0]), //i + .io_input_rsp_valid (readLogic_bridge_io_input_rsp_valid ), //o + .io_input_rsp_ready (readLogic_sourceRemover_io_output_rsp_ready ), //i + .io_input_rsp_payload_last (readLogic_bridge_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (readLogic_bridge_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (readLogic_bridge_io_input_rsp_payload_fragment_data[127:0] ), //o + .io_input_rsp_payload_fragment_context (readLogic_bridge_io_input_rsp_payload_fragment_context[21:0] ), //o + .io_output_ar_valid (readLogic_bridge_io_output_ar_valid ), //o + .io_output_ar_ready (readLogic_adapter_ar_ready ), //i + .io_output_ar_payload_addr (readLogic_bridge_io_output_ar_payload_addr[31:0] ), //o + .io_output_ar_payload_len (readLogic_bridge_io_output_ar_payload_len[7:0] ), //o + .io_output_ar_payload_size (readLogic_bridge_io_output_ar_payload_size[2:0] ), //o + .io_output_ar_payload_cache (readLogic_bridge_io_output_ar_payload_cache[3:0] ), //o + .io_output_ar_payload_prot (readLogic_bridge_io_output_ar_payload_prot[2:0] ), //o + .io_output_r_valid (readLogic_adapter_r_valid ), //i + .io_output_r_ready (readLogic_bridge_io_output_r_ready ), //o + .io_output_r_payload_data (readLogic_adapter_r_payload_data[127:0] ), //i + .io_output_r_payload_resp (readLogic_adapter_r_payload_resp[1:0] ), //i + .io_output_r_payload_last (readLogic_adapter_r_payload_last ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_BmbSourceRemover_1_a048ca8f51874147a1cd65d43e6523ef writeLogic_sourceRemover ( + .io_input_cmd_valid (writeLogic_resized_cmd_valid ), //i + .io_input_cmd_ready (writeLogic_sourceRemover_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (writeLogic_resized_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (writeLogic_resized_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (writeLogic_resized_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (writeLogic_resized_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (writeLogic_resized_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_data (writeLogic_resized_cmd_payload_fragment_data[127:0] ), //i + .io_input_cmd_payload_fragment_mask (writeLogic_resized_cmd_payload_fragment_mask[15:0] ), //i + .io_input_cmd_payload_fragment_context (writeLogic_resized_cmd_payload_fragment_context[12:0] ), //i + .io_input_rsp_valid (writeLogic_sourceRemover_io_input_rsp_valid ), //o + .io_input_rsp_ready (writeLogic_resized_rsp_ready ), //i + .io_input_rsp_payload_last (writeLogic_sourceRemover_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (writeLogic_sourceRemover_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (writeLogic_sourceRemover_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_context (writeLogic_sourceRemover_io_input_rsp_payload_fragment_context[12:0] ), //o + .io_output_cmd_valid (writeLogic_sourceRemover_io_output_cmd_valid ), //o + .io_output_cmd_ready (writeLogic_bridge_io_input_cmd_ready ), //i + .io_output_cmd_payload_last (writeLogic_sourceRemover_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (writeLogic_sourceRemover_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (writeLogic_sourceRemover_io_output_cmd_payload_fragment_address[31:0]), //o + .io_output_cmd_payload_fragment_length (writeLogic_sourceRemover_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_cmd_payload_fragment_data (writeLogic_sourceRemover_io_output_cmd_payload_fragment_data[127:0] ), //o + .io_output_cmd_payload_fragment_mask (writeLogic_sourceRemover_io_output_cmd_payload_fragment_mask[15:0] ), //o + .io_output_cmd_payload_fragment_context (writeLogic_sourceRemover_io_output_cmd_payload_fragment_context[13:0]), //o + .io_output_rsp_valid (writeLogic_bridge_io_input_rsp_valid ), //i + .io_output_rsp_ready (writeLogic_sourceRemover_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (writeLogic_bridge_io_input_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (writeLogic_bridge_io_input_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_context (writeLogic_bridge_io_input_rsp_payload_fragment_context[13:0] ) //i + ); + EfxDMA_BmbToAxi4WriteOnlyBridge_a048ca8f51874147a1cd65d43e6523ef writeLogic_bridge ( + .io_input_cmd_valid (writeLogic_sourceRemover_io_output_cmd_valid ), //i + .io_input_cmd_ready (writeLogic_bridge_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (writeLogic_sourceRemover_io_output_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (writeLogic_sourceRemover_io_output_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (writeLogic_sourceRemover_io_output_cmd_payload_fragment_address[31:0]), //i + .io_input_cmd_payload_fragment_length (writeLogic_sourceRemover_io_output_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_data (writeLogic_sourceRemover_io_output_cmd_payload_fragment_data[127:0] ), //i + .io_input_cmd_payload_fragment_mask (writeLogic_sourceRemover_io_output_cmd_payload_fragment_mask[15:0] ), //i + .io_input_cmd_payload_fragment_context (writeLogic_sourceRemover_io_output_cmd_payload_fragment_context[13:0]), //i + .io_input_rsp_valid (writeLogic_bridge_io_input_rsp_valid ), //o + .io_input_rsp_ready (writeLogic_sourceRemover_io_output_rsp_ready ), //i + .io_input_rsp_payload_last (writeLogic_bridge_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (writeLogic_bridge_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_context (writeLogic_bridge_io_input_rsp_payload_fragment_context[13:0] ), //o + .io_output_aw_valid (writeLogic_bridge_io_output_aw_valid ), //o + .io_output_aw_ready (writeLogic_adapter_aw_ready ), //i + .io_output_aw_payload_addr (writeLogic_bridge_io_output_aw_payload_addr[31:0] ), //o + .io_output_aw_payload_len (writeLogic_bridge_io_output_aw_payload_len[7:0] ), //o + .io_output_aw_payload_size (writeLogic_bridge_io_output_aw_payload_size[2:0] ), //o + .io_output_aw_payload_cache (writeLogic_bridge_io_output_aw_payload_cache[3:0] ), //o + .io_output_aw_payload_prot (writeLogic_bridge_io_output_aw_payload_prot[2:0] ), //o + .io_output_w_valid (writeLogic_bridge_io_output_w_valid ), //o + .io_output_w_ready (writeLogic_adapter_w_ready ), //i + .io_output_w_payload_data (writeLogic_bridge_io_output_w_payload_data[127:0] ), //o + .io_output_w_payload_strb (writeLogic_bridge_io_output_w_payload_strb[15:0] ), //o + .io_output_w_payload_last (writeLogic_bridge_io_output_w_payload_last ), //o + .io_output_b_valid (writeLogic_adapter_b_valid ), //i + .io_output_b_ready (writeLogic_bridge_io_output_b_ready ), //o + .io_output_b_payload_resp (writeLogic_adapter_b_payload_resp[1:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_BsbUpSizerDense_a048ca8f51874147a1cd65d43e6523ef inputsAdapter_0_upsizer_logic ( + .io_input_valid (dat0_i_tvalid ), //i + .io_input_ready (inputsAdapter_0_upsizer_logic_io_input_ready ), //o + .io_input_payload_data (dat0_i_tdata[7:0] ), //i + .io_input_payload_mask (dat0_i_tkeep ), //i + .io_input_payload_sink (dat0_i_tdest[3:0] ), //i + .io_input_payload_last (dat0_i_tlast ), //i + .io_output_valid (inputsAdapter_0_upsizer_logic_io_output_valid ), //o + .io_output_ready (inputsAdapter_0_crossclock_fifo_io_push_ready ), //i + .io_output_payload_data (inputsAdapter_0_upsizer_logic_io_output_payload_data[63:0]), //o + .io_output_payload_mask (inputsAdapter_0_upsizer_logic_io_output_payload_mask[7:0] ), //o + .io_output_payload_sink (inputsAdapter_0_upsizer_logic_io_output_payload_sink[3:0] ), //o + .io_output_payload_last (inputsAdapter_0_upsizer_logic_io_output_payload_last ), //o + .dat0_i_clk (dat0_i_clk ), //i + .dat0_i_reset (dat0_i_reset ) //i + ); + EfxDMA_StreamFifoCC_a048ca8f51874147a1cd65d43e6523ef inputsAdapter_0_crossclock_fifo ( + .io_push_valid (inputsAdapter_0_upsizer_logic_io_output_valid ), //i + .io_push_ready (inputsAdapter_0_crossclock_fifo_io_push_ready ), //o + .io_push_payload_data (inputsAdapter_0_upsizer_logic_io_output_payload_data[63:0]), //i + .io_push_payload_mask (inputsAdapter_0_upsizer_logic_io_output_payload_mask[7:0] ), //i + .io_push_payload_sink (inputsAdapter_0_upsizer_logic_io_output_payload_sink[3:0] ), //i + .io_push_payload_last (inputsAdapter_0_upsizer_logic_io_output_payload_last ), //i + .io_pop_valid (inputsAdapter_0_crossclock_fifo_io_pop_valid ), //o + .io_pop_ready (io_pop_rValidN ), //i + .io_pop_payload_data (inputsAdapter_0_crossclock_fifo_io_pop_payload_data[63:0] ), //o + .io_pop_payload_mask (inputsAdapter_0_crossclock_fifo_io_pop_payload_mask[7:0] ), //o + .io_pop_payload_sink (inputsAdapter_0_crossclock_fifo_io_pop_payload_sink[3:0] ), //o + .io_pop_payload_last (inputsAdapter_0_crossclock_fifo_io_pop_payload_last ), //o + .io_pushOccupancy (inputsAdapter_0_crossclock_fifo_io_pushOccupancy[4:0] ), //o + .io_popOccupancy (inputsAdapter_0_crossclock_fifo_io_popOccupancy[4:0] ), //o + .dat0_i_clk (dat0_i_clk ), //i + .dat0_i_reset (dat0_i_reset ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_StreamFifoCC_1_a048ca8f51874147a1cd65d43e6523ef outputsAdapter_0_crossclock_fifo ( + .io_push_valid (outputsAdapter_0_ptr_valid ), //i + .io_push_ready (outputsAdapter_0_crossclock_fifo_io_push_ready ), //o + .io_push_payload_data (outputsAdapter_0_ptr_payload_data[63:0] ), //i + .io_push_payload_mask (outputsAdapter_0_ptr_payload_mask[7:0] ), //i + .io_push_payload_sink (outputsAdapter_0_ptr_payload_sink[3:0] ), //i + .io_push_payload_last (outputsAdapter_0_ptr_payload_last ), //i + .io_pop_valid (outputsAdapter_0_crossclock_fifo_io_pop_valid ), //o + .io_pop_ready (outputsAdapter_0_sparseDownsizer_logic_io_input_ready ), //i + .io_pop_payload_data (outputsAdapter_0_crossclock_fifo_io_pop_payload_data[63:0]), //o + .io_pop_payload_mask (outputsAdapter_0_crossclock_fifo_io_pop_payload_mask[7:0] ), //o + .io_pop_payload_sink (outputsAdapter_0_crossclock_fifo_io_pop_payload_sink[3:0] ), //o + .io_pop_payload_last (outputsAdapter_0_crossclock_fifo_io_pop_payload_last ), //o + .io_pushOccupancy (outputsAdapter_0_crossclock_fifo_io_pushOccupancy[4:0] ), //o + .io_popOccupancy (outputsAdapter_0_crossclock_fifo_io_popOccupancy[4:0] ), //o + .clk (clk ), //i + .reset (reset ), //i + .dat1_o_clk (dat1_o_clk ), //i + .dat1_o_reset (dat1_o_reset ) //i + ); + EfxDMA_BsbDownSizerSparse_a048ca8f51874147a1cd65d43e6523ef outputsAdapter_0_sparseDownsizer_logic ( + .io_input_valid (outputsAdapter_0_crossclock_fifo_io_pop_valid ), //i + .io_input_ready (outputsAdapter_0_sparseDownsizer_logic_io_input_ready ), //o + .io_input_payload_data (outputsAdapter_0_crossclock_fifo_io_pop_payload_data[63:0] ), //i + .io_input_payload_mask (outputsAdapter_0_crossclock_fifo_io_pop_payload_mask[7:0] ), //i + .io_input_payload_sink (outputsAdapter_0_crossclock_fifo_io_pop_payload_sink[3:0] ), //i + .io_input_payload_last (outputsAdapter_0_crossclock_fifo_io_pop_payload_last ), //i + .io_output_valid (outputsAdapter_0_sparseDownsizer_logic_io_output_valid ), //o + .io_output_ready (dat1_o_tready ), //i + .io_output_payload_data (outputsAdapter_0_sparseDownsizer_logic_io_output_payload_data[7:0]), //o + .io_output_payload_mask (outputsAdapter_0_sparseDownsizer_logic_io_output_payload_mask ), //o + .io_output_payload_sink (outputsAdapter_0_sparseDownsizer_logic_io_output_payload_sink[3:0]), //o + .io_output_payload_last (outputsAdapter_0_sparseDownsizer_logic_io_output_payload_last ), //o + .dat1_o_clk (dat1_o_clk ), //i + .dat1_o_reset (dat1_o_reset ) //i + ); + EfxDMA_BmbArbiter_a048ca8f51874147a1cd65d43e6523ef interconnect_read_aggregated_arbiter ( + .io_inputs_0_cmd_valid (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid ), //i + .io_inputs_0_cmd_ready (interconnect_read_aggregated_arbiter_io_inputs_0_cmd_ready ), //o + .io_inputs_0_cmd_payload_last (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last ), //i + .io_inputs_0_cmd_payload_fragment_opcode (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode ), //i + .io_inputs_0_cmd_payload_fragment_address (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address[31:0]), //i + .io_inputs_0_cmd_payload_fragment_length (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length[4:0] ), //i + .io_inputs_0_cmd_payload_fragment_context (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context ), //i + .io_inputs_0_rsp_valid (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_valid ), //o + .io_inputs_0_rsp_ready (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready ), //i + .io_inputs_0_rsp_payload_last (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_last ), //o + .io_inputs_0_rsp_payload_fragment_opcode (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode ), //o + .io_inputs_0_rsp_payload_fragment_data (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_data[127:0] ), //o + .io_inputs_0_rsp_payload_fragment_context (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context ), //o + .io_inputs_1_cmd_valid (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid ), //i + .io_inputs_1_cmd_ready (interconnect_read_aggregated_arbiter_io_inputs_1_cmd_ready ), //o + .io_inputs_1_cmd_payload_last (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last ), //i + .io_inputs_1_cmd_payload_fragment_opcode (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode ), //i + .io_inputs_1_cmd_payload_fragment_address (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address[31:0]), //i + .io_inputs_1_cmd_payload_fragment_length (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length[11:0] ), //i + .io_inputs_1_cmd_payload_fragment_context (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context[20:0]), //i + .io_inputs_1_rsp_valid (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_valid ), //o + .io_inputs_1_rsp_ready (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready ), //i + .io_inputs_1_rsp_payload_last (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_last ), //o + .io_inputs_1_rsp_payload_fragment_opcode (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //o + .io_inputs_1_rsp_payload_fragment_data (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_data[127:0] ), //o + .io_inputs_1_rsp_payload_fragment_context (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context[20:0] ), //o + .io_output_cmd_valid (interconnect_read_aggregated_arbiter_io_output_cmd_valid ), //o + .io_output_cmd_ready (interconnect_read_aggregated_cmd_ready ), //i + .io_output_cmd_payload_last (interconnect_read_aggregated_arbiter_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_source (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_source ), //o + .io_output_cmd_payload_fragment_opcode (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_cmd_payload_fragment_context (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_context[20:0] ), //o + .io_output_rsp_valid (interconnect_read_aggregated_rsp_valid ), //i + .io_output_rsp_ready (interconnect_read_aggregated_arbiter_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (interconnect_read_aggregated_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_source (interconnect_read_aggregated_rsp_payload_fragment_source ), //i + .io_output_rsp_payload_fragment_opcode (interconnect_read_aggregated_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (interconnect_read_aggregated_rsp_payload_fragment_data[127:0] ), //i + .io_output_rsp_payload_fragment_context (interconnect_read_aggregated_rsp_payload_fragment_context[20:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_BmbArbiter_1_a048ca8f51874147a1cd65d43e6523ef interconnect_write_aggregated_arbiter ( + .io_inputs_0_cmd_valid (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid ), //i + .io_inputs_0_cmd_ready (interconnect_write_aggregated_arbiter_io_inputs_0_cmd_ready ), //o + .io_inputs_0_cmd_payload_last (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last ), //i + .io_inputs_0_cmd_payload_fragment_opcode (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode ), //i + .io_inputs_0_cmd_payload_fragment_address (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address[31:0]), //i + .io_inputs_0_cmd_payload_fragment_length (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length[1:0] ), //i + .io_inputs_0_cmd_payload_fragment_data (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data[127:0] ), //i + .io_inputs_0_cmd_payload_fragment_mask (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask[15:0] ), //i + .io_inputs_0_cmd_payload_fragment_context (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context ), //i + .io_inputs_0_rsp_valid (interconnect_write_aggregated_arbiter_io_inputs_0_rsp_valid ), //o + .io_inputs_0_rsp_ready (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready ), //i + .io_inputs_0_rsp_payload_last (interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_last ), //o + .io_inputs_0_rsp_payload_fragment_opcode (interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode ), //o + .io_inputs_0_rsp_payload_fragment_context (interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context ), //o + .io_inputs_1_cmd_valid (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid ), //i + .io_inputs_1_cmd_ready (interconnect_write_aggregated_arbiter_io_inputs_1_cmd_ready ), //o + .io_inputs_1_cmd_payload_last (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last ), //i + .io_inputs_1_cmd_payload_fragment_opcode (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode ), //i + .io_inputs_1_cmd_payload_fragment_address (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address[31:0]), //i + .io_inputs_1_cmd_payload_fragment_length (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length[11:0] ), //i + .io_inputs_1_cmd_payload_fragment_data (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_data[127:0] ), //i + .io_inputs_1_cmd_payload_fragment_mask (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_mask[15:0] ), //i + .io_inputs_1_cmd_payload_fragment_context (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context[12:0]), //i + .io_inputs_1_rsp_valid (interconnect_write_aggregated_arbiter_io_inputs_1_rsp_valid ), //o + .io_inputs_1_rsp_ready (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready ), //i + .io_inputs_1_rsp_payload_last (interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_last ), //o + .io_inputs_1_rsp_payload_fragment_opcode (interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //o + .io_inputs_1_rsp_payload_fragment_context (interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context[12:0] ), //o + .io_output_cmd_valid (interconnect_write_aggregated_arbiter_io_output_cmd_valid ), //o + .io_output_cmd_ready (interconnect_write_aggregated_cmd_ready ), //i + .io_output_cmd_payload_last (interconnect_write_aggregated_arbiter_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_source (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_source ), //o + .io_output_cmd_payload_fragment_opcode (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_cmd_payload_fragment_data (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_data[127:0] ), //o + .io_output_cmd_payload_fragment_mask (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_mask[15:0] ), //o + .io_output_cmd_payload_fragment_context (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_context[12:0] ), //o + .io_output_rsp_valid (interconnect_write_aggregated_rsp_valid ), //i + .io_output_rsp_ready (interconnect_write_aggregated_arbiter_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (interconnect_write_aggregated_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_source (interconnect_write_aggregated_rsp_payload_fragment_source ), //i + .io_output_rsp_payload_fragment_opcode (interconnect_write_aggregated_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_context (interconnect_write_aggregated_rsp_payload_fragment_context[12:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign io_0_descriptorUpdate = core_ll_0_descriptorUpdate; + assign io_1_descriptorUpdate = core_ll_1_descriptorUpdate; + assign ctrl_PREADY = withCtrlCc_apbCc_io_input_PREADY; + assign ctrl_PRDATA = withCtrlCc_apbCc_io_input_PRDATA; + assign ctrl_PSLVERROR = withCtrlCc_apbCc_io_input_PSLVERROR; + assign ctrl_interrupts = io_interrupts_buffercc_io_dataOut; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid = core_io_read_cmd_valid; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready = core_io_read_rsp_ready; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last = core_io_read_cmd_payload_last; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode = core_io_read_cmd_payload_fragment_opcode; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address = core_io_read_cmd_payload_fragment_address; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length = core_io_read_cmd_payload_fragment_length; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context = core_io_read_cmd_payload_fragment_context; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid = core_io_sgRead_cmd_valid; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready = core_io_sgRead_rsp_ready; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last = core_io_sgRead_cmd_payload_last; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode = core_io_sgRead_cmd_payload_fragment_opcode; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address = core_io_sgRead_cmd_payload_fragment_address; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length = core_io_sgRead_cmd_payload_fragment_length; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context = core_io_sgRead_cmd_payload_fragment_context; + assign io_write_cmd_s2mPipe_valid = (core_io_write_cmd_valid || (! io_write_cmd_rValidN)); + assign io_write_cmd_s2mPipe_payload_last = (io_write_cmd_rValidN ? core_io_write_cmd_payload_last : io_write_cmd_rData_last); + assign io_write_cmd_s2mPipe_payload_fragment_opcode = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_opcode : io_write_cmd_rData_fragment_opcode); + assign io_write_cmd_s2mPipe_payload_fragment_address = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_address : io_write_cmd_rData_fragment_address); + assign io_write_cmd_s2mPipe_payload_fragment_length = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_length : io_write_cmd_rData_fragment_length); + assign io_write_cmd_s2mPipe_payload_fragment_data = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_data : io_write_cmd_rData_fragment_data); + assign io_write_cmd_s2mPipe_payload_fragment_mask = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_mask : io_write_cmd_rData_fragment_mask); + assign io_write_cmd_s2mPipe_payload_fragment_context = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_context : io_write_cmd_rData_fragment_context); + always @(*) begin + io_write_cmd_s2mPipe_ready = io_write_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l375) begin + io_write_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! io_write_cmd_s2mPipe_m2sPipe_valid); + assign io_write_cmd_s2mPipe_m2sPipe_valid = io_write_cmd_s2mPipe_rValid; + assign io_write_cmd_s2mPipe_m2sPipe_payload_last = io_write_cmd_s2mPipe_rData_last; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_opcode = io_write_cmd_s2mPipe_rData_fragment_opcode; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_address = io_write_cmd_s2mPipe_rData_fragment_address; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_length = io_write_cmd_s2mPipe_rData_fragment_length; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_data = io_write_cmd_s2mPipe_rData_fragment_data; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_mask = io_write_cmd_s2mPipe_rData_fragment_mask; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_context = io_write_cmd_s2mPipe_rData_fragment_context; + assign io_write_cmd_s2mPipe_m2sPipe_ready = interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid = io_write_cmd_s2mPipe_m2sPipe_valid; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready = core_io_write_rsp_ready; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last = io_write_cmd_s2mPipe_m2sPipe_payload_last; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_opcode; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_address; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_length; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_data = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_data; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_mask = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_mask; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_context; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid = core_io_sgWrite_cmd_valid; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready = core_io_sgWrite_rsp_ready; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last = core_io_sgWrite_cmd_payload_last; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode = core_io_sgWrite_cmd_payload_fragment_opcode; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address = core_io_sgWrite_cmd_payload_fragment_address; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length = core_io_sgWrite_cmd_payload_fragment_length; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data = core_io_sgWrite_cmd_payload_fragment_data; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask = core_io_sgWrite_cmd_payload_fragment_mask; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context = core_io_sgWrite_cmd_payload_fragment_context; + assign interconnect_read_aggregated_cmd_halfPipe_fire = (interconnect_read_aggregated_cmd_halfPipe_valid && interconnect_read_aggregated_cmd_halfPipe_ready); + assign interconnect_read_aggregated_cmd_ready = (! interconnect_read_aggregated_cmd_rValid); + assign interconnect_read_aggregated_cmd_halfPipe_valid = interconnect_read_aggregated_cmd_rValid; + assign interconnect_read_aggregated_cmd_halfPipe_payload_last = interconnect_read_aggregated_cmd_rData_last; + assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_source = interconnect_read_aggregated_cmd_rData_fragment_source; + assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_opcode = interconnect_read_aggregated_cmd_rData_fragment_opcode; + assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_address = interconnect_read_aggregated_cmd_rData_fragment_address; + assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_length = interconnect_read_aggregated_cmd_rData_fragment_length; + assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_context = interconnect_read_aggregated_cmd_rData_fragment_context; + assign readLogic_resized_cmd_valid = interconnect_read_aggregated_cmd_halfPipe_valid; + assign interconnect_read_aggregated_cmd_halfPipe_ready = readLogic_resized_cmd_ready; + assign readLogic_resized_cmd_payload_last = interconnect_read_aggregated_cmd_halfPipe_payload_last; + assign readLogic_resized_cmd_payload_fragment_source = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_source; + assign readLogic_resized_cmd_payload_fragment_opcode = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_opcode; + assign readLogic_resized_cmd_payload_fragment_address = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_address; + assign readLogic_resized_cmd_payload_fragment_length = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_length; + assign readLogic_resized_cmd_payload_fragment_context = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_context; + assign readLogic_resized_rsp_combStage_valid = readLogic_resized_rsp_valid; + assign readLogic_resized_rsp_ready = readLogic_resized_rsp_combStage_ready; + assign readLogic_resized_rsp_combStage_payload_last = readLogic_resized_rsp_payload_last; + assign readLogic_resized_rsp_combStage_payload_fragment_source = readLogic_resized_rsp_payload_fragment_source; + assign readLogic_resized_rsp_combStage_payload_fragment_opcode = readLogic_resized_rsp_payload_fragment_opcode; + assign readLogic_resized_rsp_combStage_payload_fragment_data = readLogic_resized_rsp_payload_fragment_data; + assign readLogic_resized_rsp_combStage_payload_fragment_context = readLogic_resized_rsp_payload_fragment_context; + assign interconnect_read_aggregated_rsp_valid = readLogic_resized_rsp_combStage_valid; + assign readLogic_resized_rsp_combStage_ready = interconnect_read_aggregated_rsp_ready; + assign interconnect_read_aggregated_rsp_payload_last = readLogic_resized_rsp_combStage_payload_last; + assign interconnect_read_aggregated_rsp_payload_fragment_source = readLogic_resized_rsp_combStage_payload_fragment_source; + assign interconnect_read_aggregated_rsp_payload_fragment_opcode = readLogic_resized_rsp_combStage_payload_fragment_opcode; + assign interconnect_read_aggregated_rsp_payload_fragment_data = readLogic_resized_rsp_combStage_payload_fragment_data; + assign interconnect_read_aggregated_rsp_payload_fragment_context = readLogic_resized_rsp_combStage_payload_fragment_context; + assign readLogic_resized_cmd_ready = readLogic_sourceRemover_io_input_cmd_ready; + assign readLogic_resized_rsp_valid = readLogic_sourceRemover_io_input_rsp_valid; + assign readLogic_resized_rsp_payload_last = readLogic_sourceRemover_io_input_rsp_payload_last; + assign readLogic_resized_rsp_payload_fragment_source = readLogic_sourceRemover_io_input_rsp_payload_fragment_source; + assign readLogic_resized_rsp_payload_fragment_opcode = readLogic_sourceRemover_io_input_rsp_payload_fragment_opcode; + assign readLogic_resized_rsp_payload_fragment_data = readLogic_sourceRemover_io_input_rsp_payload_fragment_data; + assign readLogic_resized_rsp_payload_fragment_context = readLogic_sourceRemover_io_input_rsp_payload_fragment_context; + assign readLogic_adapter_ar_valid = readLogic_bridge_io_output_ar_valid; + assign readLogic_adapter_ar_payload_addr = readLogic_bridge_io_output_ar_payload_addr; + assign _zz_readLogic_adapter_ar_payload_region[3 : 0] = 4'b0000; + assign readLogic_adapter_ar_payload_region = _zz_readLogic_adapter_ar_payload_region; + assign readLogic_adapter_ar_payload_len = readLogic_bridge_io_output_ar_payload_len; + assign readLogic_adapter_ar_payload_size = readLogic_bridge_io_output_ar_payload_size; + assign readLogic_adapter_ar_payload_burst = 2'b01; + assign readLogic_adapter_ar_payload_lock = 1'b0; + assign readLogic_adapter_ar_payload_cache = readLogic_bridge_io_output_ar_payload_cache; + assign readLogic_adapter_ar_payload_qos = 4'b0000; + assign readLogic_adapter_ar_payload_prot = readLogic_bridge_io_output_ar_payload_prot; + assign readLogic_adapter_r_ready = readLogic_bridge_io_output_r_ready; + assign readLogic_adapter_ar_halfPipe_fire = (readLogic_adapter_ar_halfPipe_valid && readLogic_adapter_ar_halfPipe_ready); + assign readLogic_adapter_ar_ready = (! readLogic_adapter_ar_rValid); + assign readLogic_adapter_ar_halfPipe_valid = readLogic_adapter_ar_rValid; + assign readLogic_adapter_ar_halfPipe_payload_addr = readLogic_adapter_ar_rData_addr; + assign readLogic_adapter_ar_halfPipe_payload_region = readLogic_adapter_ar_rData_region; + assign readLogic_adapter_ar_halfPipe_payload_len = readLogic_adapter_ar_rData_len; + assign readLogic_adapter_ar_halfPipe_payload_size = readLogic_adapter_ar_rData_size; + assign readLogic_adapter_ar_halfPipe_payload_burst = readLogic_adapter_ar_rData_burst; + assign readLogic_adapter_ar_halfPipe_payload_lock = readLogic_adapter_ar_rData_lock; + assign readLogic_adapter_ar_halfPipe_payload_cache = readLogic_adapter_ar_rData_cache; + assign readLogic_adapter_ar_halfPipe_payload_qos = readLogic_adapter_ar_rData_qos; + assign readLogic_adapter_ar_halfPipe_payload_prot = readLogic_adapter_ar_rData_prot; + assign read_arvalid = readLogic_adapter_ar_halfPipe_valid; + assign readLogic_adapter_ar_halfPipe_ready = read_arready; + assign read_araddr = readLogic_adapter_ar_halfPipe_payload_addr; + assign read_arregion = readLogic_adapter_ar_halfPipe_payload_region; + assign read_arlen = readLogic_adapter_ar_halfPipe_payload_len; + assign read_arsize = readLogic_adapter_ar_halfPipe_payload_size; + assign read_arburst = readLogic_adapter_ar_halfPipe_payload_burst; + assign read_arlock = readLogic_adapter_ar_halfPipe_payload_lock; + assign read_arcache = readLogic_adapter_ar_halfPipe_payload_cache; + assign read_arqos = readLogic_adapter_ar_halfPipe_payload_qos; + assign read_arprot = readLogic_adapter_ar_halfPipe_payload_prot; + assign read_rready = read_r_rValidN; + assign read_r_s2mPipe_valid = (read_rvalid || (! read_r_rValidN)); + assign read_r_s2mPipe_payload_data = (read_r_rValidN ? read_rdata : read_r_rData_data); + assign read_r_s2mPipe_payload_resp = (read_r_rValidN ? read_rresp : read_r_rData_resp); + assign read_r_s2mPipe_payload_last = (read_r_rValidN ? read_rlast : read_r_rData_last); + always @(*) begin + read_r_s2mPipe_ready = readLogic_beforeQueue_ready; + if(when_Stream_l375_1) begin + read_r_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375_1 = (! readLogic_beforeQueue_valid); + assign readLogic_beforeQueue_valid = read_r_s2mPipe_rValid; + assign readLogic_beforeQueue_payload_data = read_r_s2mPipe_rData_data; + assign readLogic_beforeQueue_payload_resp = read_r_s2mPipe_rData_resp; + assign readLogic_beforeQueue_payload_last = read_r_s2mPipe_rData_last; + assign readLogic_adapter_r_valid = readLogic_beforeQueue_valid; + assign readLogic_beforeQueue_ready = readLogic_adapter_r_ready; + assign readLogic_adapter_r_payload_data = readLogic_beforeQueue_payload_data; + assign readLogic_adapter_r_payload_resp = readLogic_beforeQueue_payload_resp; + assign readLogic_adapter_r_payload_last = readLogic_beforeQueue_payload_last; + always @(*) begin + interconnect_write_aggregated_cmd_ready = interconnect_write_aggregated_cmd_m2sPipe_ready; + if(when_Stream_l375_2) begin + interconnect_write_aggregated_cmd_ready = 1'b1; + end + end + + assign when_Stream_l375_2 = (! interconnect_write_aggregated_cmd_m2sPipe_valid); + assign interconnect_write_aggregated_cmd_m2sPipe_valid = interconnect_write_aggregated_cmd_rValid; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_last = interconnect_write_aggregated_cmd_rData_last; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_source = interconnect_write_aggregated_cmd_rData_fragment_source; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_opcode = interconnect_write_aggregated_cmd_rData_fragment_opcode; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_address = interconnect_write_aggregated_cmd_rData_fragment_address; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_length = interconnect_write_aggregated_cmd_rData_fragment_length; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_data = interconnect_write_aggregated_cmd_rData_fragment_data; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_mask = interconnect_write_aggregated_cmd_rData_fragment_mask; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_context = interconnect_write_aggregated_cmd_rData_fragment_context; + assign writeLogic_resized_cmd_valid = interconnect_write_aggregated_cmd_m2sPipe_valid; + assign interconnect_write_aggregated_cmd_m2sPipe_ready = writeLogic_resized_cmd_ready; + assign writeLogic_resized_cmd_payload_last = interconnect_write_aggregated_cmd_m2sPipe_payload_last; + assign writeLogic_resized_cmd_payload_fragment_source = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_source; + assign writeLogic_resized_cmd_payload_fragment_opcode = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_opcode; + assign writeLogic_resized_cmd_payload_fragment_address = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_address; + assign writeLogic_resized_cmd_payload_fragment_length = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_length; + assign writeLogic_resized_cmd_payload_fragment_data = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_data; + assign writeLogic_resized_cmd_payload_fragment_mask = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_mask; + assign writeLogic_resized_cmd_payload_fragment_context = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_context; + assign writeLogic_resized_rsp_combStage_valid = writeLogic_resized_rsp_valid; + assign writeLogic_resized_rsp_ready = writeLogic_resized_rsp_combStage_ready; + assign writeLogic_resized_rsp_combStage_payload_last = writeLogic_resized_rsp_payload_last; + assign writeLogic_resized_rsp_combStage_payload_fragment_source = writeLogic_resized_rsp_payload_fragment_source; + assign writeLogic_resized_rsp_combStage_payload_fragment_opcode = writeLogic_resized_rsp_payload_fragment_opcode; + assign writeLogic_resized_rsp_combStage_payload_fragment_context = writeLogic_resized_rsp_payload_fragment_context; + assign interconnect_write_aggregated_rsp_valid = writeLogic_resized_rsp_combStage_valid; + assign writeLogic_resized_rsp_combStage_ready = interconnect_write_aggregated_rsp_ready; + assign interconnect_write_aggregated_rsp_payload_last = writeLogic_resized_rsp_combStage_payload_last; + assign interconnect_write_aggregated_rsp_payload_fragment_source = writeLogic_resized_rsp_combStage_payload_fragment_source; + assign interconnect_write_aggregated_rsp_payload_fragment_opcode = writeLogic_resized_rsp_combStage_payload_fragment_opcode; + assign interconnect_write_aggregated_rsp_payload_fragment_context = writeLogic_resized_rsp_combStage_payload_fragment_context; + assign writeLogic_resized_cmd_ready = writeLogic_sourceRemover_io_input_cmd_ready; + assign writeLogic_resized_rsp_valid = writeLogic_sourceRemover_io_input_rsp_valid; + assign writeLogic_resized_rsp_payload_last = writeLogic_sourceRemover_io_input_rsp_payload_last; + assign writeLogic_resized_rsp_payload_fragment_source = writeLogic_sourceRemover_io_input_rsp_payload_fragment_source; + assign writeLogic_resized_rsp_payload_fragment_opcode = writeLogic_sourceRemover_io_input_rsp_payload_fragment_opcode; + assign writeLogic_resized_rsp_payload_fragment_context = writeLogic_sourceRemover_io_input_rsp_payload_fragment_context; + assign writeLogic_adapter_aw_valid = writeLogic_bridge_io_output_aw_valid; + assign writeLogic_adapter_aw_payload_addr = writeLogic_bridge_io_output_aw_payload_addr; + assign _zz_writeLogic_adapter_aw_payload_region[3 : 0] = 4'b0000; + assign writeLogic_adapter_aw_payload_region = _zz_writeLogic_adapter_aw_payload_region; + assign writeLogic_adapter_aw_payload_len = writeLogic_bridge_io_output_aw_payload_len; + assign writeLogic_adapter_aw_payload_size = writeLogic_bridge_io_output_aw_payload_size; + assign writeLogic_adapter_aw_payload_burst = 2'b01; + assign writeLogic_adapter_aw_payload_lock = 1'b0; + assign writeLogic_adapter_aw_payload_cache = writeLogic_bridge_io_output_aw_payload_cache; + assign writeLogic_adapter_aw_payload_qos = 4'b0000; + assign writeLogic_adapter_aw_payload_prot = writeLogic_bridge_io_output_aw_payload_prot; + assign writeLogic_adapter_w_valid = writeLogic_bridge_io_output_w_valid; + assign writeLogic_adapter_w_payload_data = writeLogic_bridge_io_output_w_payload_data; + assign writeLogic_adapter_w_payload_strb = writeLogic_bridge_io_output_w_payload_strb; + assign writeLogic_adapter_w_payload_last = writeLogic_bridge_io_output_w_payload_last; + assign writeLogic_adapter_b_ready = writeLogic_bridge_io_output_b_ready; + assign writeLogic_adapter_aw_halfPipe_fire = (writeLogic_adapter_aw_halfPipe_valid && writeLogic_adapter_aw_halfPipe_ready); + assign writeLogic_adapter_aw_ready = (! writeLogic_adapter_aw_rValid); + assign writeLogic_adapter_aw_halfPipe_valid = writeLogic_adapter_aw_rValid; + assign writeLogic_adapter_aw_halfPipe_payload_addr = writeLogic_adapter_aw_rData_addr; + assign writeLogic_adapter_aw_halfPipe_payload_region = writeLogic_adapter_aw_rData_region; + assign writeLogic_adapter_aw_halfPipe_payload_len = writeLogic_adapter_aw_rData_len; + assign writeLogic_adapter_aw_halfPipe_payload_size = writeLogic_adapter_aw_rData_size; + assign writeLogic_adapter_aw_halfPipe_payload_burst = writeLogic_adapter_aw_rData_burst; + assign writeLogic_adapter_aw_halfPipe_payload_lock = writeLogic_adapter_aw_rData_lock; + assign writeLogic_adapter_aw_halfPipe_payload_cache = writeLogic_adapter_aw_rData_cache; + assign writeLogic_adapter_aw_halfPipe_payload_qos = writeLogic_adapter_aw_rData_qos; + assign writeLogic_adapter_aw_halfPipe_payload_prot = writeLogic_adapter_aw_rData_prot; + assign write_awvalid = writeLogic_adapter_aw_halfPipe_valid; + assign writeLogic_adapter_aw_halfPipe_ready = write_awready; + assign write_awaddr = writeLogic_adapter_aw_halfPipe_payload_addr; + assign write_awregion = writeLogic_adapter_aw_halfPipe_payload_region; + assign write_awlen = writeLogic_adapter_aw_halfPipe_payload_len; + assign write_awsize = writeLogic_adapter_aw_halfPipe_payload_size; + assign write_awburst = writeLogic_adapter_aw_halfPipe_payload_burst; + assign write_awlock = writeLogic_adapter_aw_halfPipe_payload_lock; + assign write_awcache = writeLogic_adapter_aw_halfPipe_payload_cache; + assign write_awqos = writeLogic_adapter_aw_halfPipe_payload_qos; + assign write_awprot = writeLogic_adapter_aw_halfPipe_payload_prot; + assign writeLogic_adapter_w_ready = writeLogic_adapter_w_rValidN; + assign writeLogic_adapter_w_s2mPipe_valid = (writeLogic_adapter_w_valid || (! writeLogic_adapter_w_rValidN)); + assign writeLogic_adapter_w_s2mPipe_payload_data = (writeLogic_adapter_w_rValidN ? writeLogic_adapter_w_payload_data : writeLogic_adapter_w_rData_data); + assign writeLogic_adapter_w_s2mPipe_payload_strb = (writeLogic_adapter_w_rValidN ? writeLogic_adapter_w_payload_strb : writeLogic_adapter_w_rData_strb); + assign writeLogic_adapter_w_s2mPipe_payload_last = (writeLogic_adapter_w_rValidN ? writeLogic_adapter_w_payload_last : writeLogic_adapter_w_rData_last); + always @(*) begin + writeLogic_adapter_w_s2mPipe_ready = writeLogic_adapter_w_s2mPipe_m2sPipe_ready; + if(when_Stream_l375_3) begin + writeLogic_adapter_w_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375_3 = (! writeLogic_adapter_w_s2mPipe_m2sPipe_valid); + assign writeLogic_adapter_w_s2mPipe_m2sPipe_valid = writeLogic_adapter_w_s2mPipe_rValid; + assign writeLogic_adapter_w_s2mPipe_m2sPipe_payload_data = writeLogic_adapter_w_s2mPipe_rData_data; + assign writeLogic_adapter_w_s2mPipe_m2sPipe_payload_strb = writeLogic_adapter_w_s2mPipe_rData_strb; + assign writeLogic_adapter_w_s2mPipe_m2sPipe_payload_last = writeLogic_adapter_w_s2mPipe_rData_last; + assign write_wvalid = writeLogic_adapter_w_s2mPipe_m2sPipe_valid; + assign writeLogic_adapter_w_s2mPipe_m2sPipe_ready = write_wready; + assign write_wdata = writeLogic_adapter_w_s2mPipe_m2sPipe_payload_data; + assign write_wstrb = writeLogic_adapter_w_s2mPipe_m2sPipe_payload_strb; + assign write_wlast = writeLogic_adapter_w_s2mPipe_m2sPipe_payload_last; + assign write_b_halfPipe_fire = (write_b_halfPipe_valid && write_b_halfPipe_ready); + assign write_bready = (! write_b_rValid); + assign write_b_halfPipe_valid = write_b_rValid; + assign write_b_halfPipe_payload_resp = write_b_rData_resp; + assign writeLogic_adapter_b_valid = write_b_halfPipe_valid; + assign write_b_halfPipe_ready = writeLogic_adapter_b_ready; + assign writeLogic_adapter_b_payload_resp = write_b_halfPipe_payload_resp; + assign dat0_i_tready = inputsAdapter_0_upsizer_logic_io_input_ready; + assign io_pop_s2mPipe_valid = (inputsAdapter_0_crossclock_fifo_io_pop_valid || (! io_pop_rValidN)); + assign io_pop_s2mPipe_payload_data = (io_pop_rValidN ? inputsAdapter_0_crossclock_fifo_io_pop_payload_data : io_pop_rData_data); + assign io_pop_s2mPipe_payload_mask = (io_pop_rValidN ? inputsAdapter_0_crossclock_fifo_io_pop_payload_mask : io_pop_rData_mask); + assign io_pop_s2mPipe_payload_sink = (io_pop_rValidN ? inputsAdapter_0_crossclock_fifo_io_pop_payload_sink : io_pop_rData_sink); + assign io_pop_s2mPipe_payload_last = (io_pop_rValidN ? inputsAdapter_0_crossclock_fifo_io_pop_payload_last : io_pop_rData_last); + always @(*) begin + io_pop_s2mPipe_ready = io_pop_s2mPipe_m2sPipe_ready; + if(when_Stream_l375_4) begin + io_pop_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375_4 = (! io_pop_s2mPipe_m2sPipe_valid); + assign io_pop_s2mPipe_m2sPipe_valid = io_pop_s2mPipe_rValid; + assign io_pop_s2mPipe_m2sPipe_payload_data = io_pop_s2mPipe_rData_data; + assign io_pop_s2mPipe_m2sPipe_payload_mask = io_pop_s2mPipe_rData_mask; + assign io_pop_s2mPipe_m2sPipe_payload_sink = io_pop_s2mPipe_rData_sink; + assign io_pop_s2mPipe_m2sPipe_payload_last = io_pop_s2mPipe_rData_last; + assign io_pop_s2mPipe_m2sPipe_ready = core_io_inputs_0_ready; + assign io_outputs_0_s2mPipe_valid = (core_io_outputs_0_valid || (! io_outputs_0_rValidN)); + assign io_outputs_0_s2mPipe_payload_data = (io_outputs_0_rValidN ? core_io_outputs_0_payload_data : io_outputs_0_rData_data); + assign io_outputs_0_s2mPipe_payload_mask = (io_outputs_0_rValidN ? core_io_outputs_0_payload_mask : io_outputs_0_rData_mask); + assign io_outputs_0_s2mPipe_payload_sink = (io_outputs_0_rValidN ? core_io_outputs_0_payload_sink : io_outputs_0_rData_sink); + assign io_outputs_0_s2mPipe_payload_last = (io_outputs_0_rValidN ? core_io_outputs_0_payload_last : io_outputs_0_rData_last); + always @(*) begin + io_outputs_0_s2mPipe_ready = outputsAdapter_0_ptr_ready; + if(when_Stream_l375_5) begin + io_outputs_0_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375_5 = (! outputsAdapter_0_ptr_valid); + assign outputsAdapter_0_ptr_valid = io_outputs_0_s2mPipe_rValid; + assign outputsAdapter_0_ptr_payload_data = io_outputs_0_s2mPipe_rData_data; + assign outputsAdapter_0_ptr_payload_mask = io_outputs_0_s2mPipe_rData_mask; + assign outputsAdapter_0_ptr_payload_sink = io_outputs_0_s2mPipe_rData_sink; + assign outputsAdapter_0_ptr_payload_last = io_outputs_0_s2mPipe_rData_last; + assign outputsAdapter_0_ptr_ready = outputsAdapter_0_crossclock_fifo_io_push_ready; + assign dat1_o_tvalid = outputsAdapter_0_sparseDownsizer_logic_io_output_valid; + assign dat1_o_tdata = outputsAdapter_0_sparseDownsizer_logic_io_output_payload_data; + assign dat1_o_tkeep = outputsAdapter_0_sparseDownsizer_logic_io_output_payload_mask; + assign dat1_o_tdest = outputsAdapter_0_sparseDownsizer_logic_io_output_payload_sink; + assign dat1_o_tlast = outputsAdapter_0_sparseDownsizer_logic_io_output_payload_last; + assign interconnect_read_aggregated_cmd_valid = interconnect_read_aggregated_arbiter_io_output_cmd_valid; + assign interconnect_read_aggregated_rsp_ready = interconnect_read_aggregated_arbiter_io_output_rsp_ready; + assign interconnect_read_aggregated_cmd_payload_last = interconnect_read_aggregated_arbiter_io_output_cmd_payload_last; + assign interconnect_read_aggregated_cmd_payload_fragment_source = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_source; + assign interconnect_read_aggregated_cmd_payload_fragment_opcode = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_opcode; + assign interconnect_read_aggregated_cmd_payload_fragment_address = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_address; + assign interconnect_read_aggregated_cmd_payload_fragment_length = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_length; + assign interconnect_read_aggregated_cmd_payload_fragment_context = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_context; + assign interconnect_write_aggregated_cmd_valid = interconnect_write_aggregated_arbiter_io_output_cmd_valid; + assign interconnect_write_aggregated_rsp_ready = interconnect_write_aggregated_arbiter_io_output_rsp_ready; + assign interconnect_write_aggregated_cmd_payload_last = interconnect_write_aggregated_arbiter_io_output_cmd_payload_last; + assign interconnect_write_aggregated_cmd_payload_fragment_source = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_source; + assign interconnect_write_aggregated_cmd_payload_fragment_opcode = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_opcode; + assign interconnect_write_aggregated_cmd_payload_fragment_address = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_address; + assign interconnect_write_aggregated_cmd_payload_fragment_length = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_length; + assign interconnect_write_aggregated_cmd_payload_fragment_data = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_data; + assign interconnect_write_aggregated_cmd_payload_fragment_mask = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_mask; + assign interconnect_write_aggregated_cmd_payload_fragment_context = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_context; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready = interconnect_read_aggregated_arbiter_io_inputs_0_cmd_ready; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_valid; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_last; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_data; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready = interconnect_read_aggregated_arbiter_io_inputs_1_cmd_ready; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_valid; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_last; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_data = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_data; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready = interconnect_write_aggregated_arbiter_io_inputs_0_cmd_ready; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid = interconnect_write_aggregated_arbiter_io_inputs_0_rsp_valid; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last = interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_last; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode = interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context = interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready = interconnect_write_aggregated_arbiter_io_inputs_1_cmd_ready; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid = interconnect_write_aggregated_arbiter_io_inputs_1_rsp_valid; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last = interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_last; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode = interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context = interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context; + always @(posedge clk) begin + if(reset) begin + io_write_cmd_rValidN <= 1'b1; + io_write_cmd_s2mPipe_rValid <= 1'b0; + interconnect_read_aggregated_cmd_rValid <= 1'b0; + readLogic_adapter_ar_rValid <= 1'b0; + read_r_rValidN <= 1'b1; + read_r_s2mPipe_rValid <= 1'b0; + interconnect_write_aggregated_cmd_rValid <= 1'b0; + writeLogic_adapter_aw_rValid <= 1'b0; + writeLogic_adapter_w_rValidN <= 1'b1; + writeLogic_adapter_w_s2mPipe_rValid <= 1'b0; + write_b_rValid <= 1'b0; + io_pop_rValidN <= 1'b1; + io_pop_s2mPipe_rValid <= 1'b0; + io_outputs_0_rValidN <= 1'b1; + io_outputs_0_s2mPipe_rValid <= 1'b0; + end else begin + if(core_io_write_cmd_valid) begin + io_write_cmd_rValidN <= 1'b0; + end + if(io_write_cmd_s2mPipe_ready) begin + io_write_cmd_rValidN <= 1'b1; + end + if(io_write_cmd_s2mPipe_ready) begin + io_write_cmd_s2mPipe_rValid <= io_write_cmd_s2mPipe_valid; + end + if(interconnect_read_aggregated_cmd_valid) begin + interconnect_read_aggregated_cmd_rValid <= 1'b1; + end + if(interconnect_read_aggregated_cmd_halfPipe_fire) begin + interconnect_read_aggregated_cmd_rValid <= 1'b0; + end + if(readLogic_adapter_ar_valid) begin + readLogic_adapter_ar_rValid <= 1'b1; + end + if(readLogic_adapter_ar_halfPipe_fire) begin + readLogic_adapter_ar_rValid <= 1'b0; + end + if(read_rvalid) begin + read_r_rValidN <= 1'b0; + end + if(read_r_s2mPipe_ready) begin + read_r_rValidN <= 1'b1; + end + if(read_r_s2mPipe_ready) begin + read_r_s2mPipe_rValid <= read_r_s2mPipe_valid; + end + if(interconnect_write_aggregated_cmd_ready) begin + interconnect_write_aggregated_cmd_rValid <= interconnect_write_aggregated_cmd_valid; + end + if(writeLogic_adapter_aw_valid) begin + writeLogic_adapter_aw_rValid <= 1'b1; + end + if(writeLogic_adapter_aw_halfPipe_fire) begin + writeLogic_adapter_aw_rValid <= 1'b0; + end + if(writeLogic_adapter_w_valid) begin + writeLogic_adapter_w_rValidN <= 1'b0; + end + if(writeLogic_adapter_w_s2mPipe_ready) begin + writeLogic_adapter_w_rValidN <= 1'b1; + end + if(writeLogic_adapter_w_s2mPipe_ready) begin + writeLogic_adapter_w_s2mPipe_rValid <= writeLogic_adapter_w_s2mPipe_valid; + end + if(write_bvalid) begin + write_b_rValid <= 1'b1; + end + if(write_b_halfPipe_fire) begin + write_b_rValid <= 1'b0; + end + if(inputsAdapter_0_crossclock_fifo_io_pop_valid) begin + io_pop_rValidN <= 1'b0; + end + if(io_pop_s2mPipe_ready) begin + io_pop_rValidN <= 1'b1; + end + if(io_pop_s2mPipe_ready) begin + io_pop_s2mPipe_rValid <= io_pop_s2mPipe_valid; + end + if(core_io_outputs_0_valid) begin + io_outputs_0_rValidN <= 1'b0; + end + if(io_outputs_0_s2mPipe_ready) begin + io_outputs_0_rValidN <= 1'b1; + end + if(io_outputs_0_s2mPipe_ready) begin + io_outputs_0_s2mPipe_rValid <= io_outputs_0_s2mPipe_valid; + end + end + end + + always @(posedge clk) begin + if(io_write_cmd_rValidN) begin + io_write_cmd_rData_last <= core_io_write_cmd_payload_last; + io_write_cmd_rData_fragment_opcode <= core_io_write_cmd_payload_fragment_opcode; + io_write_cmd_rData_fragment_address <= core_io_write_cmd_payload_fragment_address; + io_write_cmd_rData_fragment_length <= core_io_write_cmd_payload_fragment_length; + io_write_cmd_rData_fragment_data <= core_io_write_cmd_payload_fragment_data; + io_write_cmd_rData_fragment_mask <= core_io_write_cmd_payload_fragment_mask; + io_write_cmd_rData_fragment_context <= core_io_write_cmd_payload_fragment_context; + end + if(io_write_cmd_s2mPipe_ready) begin + io_write_cmd_s2mPipe_rData_last <= io_write_cmd_s2mPipe_payload_last; + io_write_cmd_s2mPipe_rData_fragment_opcode <= io_write_cmd_s2mPipe_payload_fragment_opcode; + io_write_cmd_s2mPipe_rData_fragment_address <= io_write_cmd_s2mPipe_payload_fragment_address; + io_write_cmd_s2mPipe_rData_fragment_length <= io_write_cmd_s2mPipe_payload_fragment_length; + io_write_cmd_s2mPipe_rData_fragment_data <= io_write_cmd_s2mPipe_payload_fragment_data; + io_write_cmd_s2mPipe_rData_fragment_mask <= io_write_cmd_s2mPipe_payload_fragment_mask; + io_write_cmd_s2mPipe_rData_fragment_context <= io_write_cmd_s2mPipe_payload_fragment_context; + end + if(interconnect_read_aggregated_cmd_ready) begin + interconnect_read_aggregated_cmd_rData_last <= interconnect_read_aggregated_cmd_payload_last; + interconnect_read_aggregated_cmd_rData_fragment_source <= interconnect_read_aggregated_cmd_payload_fragment_source; + interconnect_read_aggregated_cmd_rData_fragment_opcode <= interconnect_read_aggregated_cmd_payload_fragment_opcode; + interconnect_read_aggregated_cmd_rData_fragment_address <= interconnect_read_aggregated_cmd_payload_fragment_address; + interconnect_read_aggregated_cmd_rData_fragment_length <= interconnect_read_aggregated_cmd_payload_fragment_length; + interconnect_read_aggregated_cmd_rData_fragment_context <= interconnect_read_aggregated_cmd_payload_fragment_context; + end + if(readLogic_adapter_ar_ready) begin + readLogic_adapter_ar_rData_addr <= readLogic_adapter_ar_payload_addr; + readLogic_adapter_ar_rData_region <= readLogic_adapter_ar_payload_region; + readLogic_adapter_ar_rData_len <= readLogic_adapter_ar_payload_len; + readLogic_adapter_ar_rData_size <= readLogic_adapter_ar_payload_size; + readLogic_adapter_ar_rData_burst <= readLogic_adapter_ar_payload_burst; + readLogic_adapter_ar_rData_lock <= readLogic_adapter_ar_payload_lock; + readLogic_adapter_ar_rData_cache <= readLogic_adapter_ar_payload_cache; + readLogic_adapter_ar_rData_qos <= readLogic_adapter_ar_payload_qos; + readLogic_adapter_ar_rData_prot <= readLogic_adapter_ar_payload_prot; + end + if(read_rready) begin + read_r_rData_data <= read_rdata; + read_r_rData_resp <= read_rresp; + read_r_rData_last <= read_rlast; + end + if(read_r_s2mPipe_ready) begin + read_r_s2mPipe_rData_data <= read_r_s2mPipe_payload_data; + read_r_s2mPipe_rData_resp <= read_r_s2mPipe_payload_resp; + read_r_s2mPipe_rData_last <= read_r_s2mPipe_payload_last; + end + if(interconnect_write_aggregated_cmd_ready) begin + interconnect_write_aggregated_cmd_rData_last <= interconnect_write_aggregated_cmd_payload_last; + interconnect_write_aggregated_cmd_rData_fragment_source <= interconnect_write_aggregated_cmd_payload_fragment_source; + interconnect_write_aggregated_cmd_rData_fragment_opcode <= interconnect_write_aggregated_cmd_payload_fragment_opcode; + interconnect_write_aggregated_cmd_rData_fragment_address <= interconnect_write_aggregated_cmd_payload_fragment_address; + interconnect_write_aggregated_cmd_rData_fragment_length <= interconnect_write_aggregated_cmd_payload_fragment_length; + interconnect_write_aggregated_cmd_rData_fragment_data <= interconnect_write_aggregated_cmd_payload_fragment_data; + interconnect_write_aggregated_cmd_rData_fragment_mask <= interconnect_write_aggregated_cmd_payload_fragment_mask; + interconnect_write_aggregated_cmd_rData_fragment_context <= interconnect_write_aggregated_cmd_payload_fragment_context; + end + if(writeLogic_adapter_aw_ready) begin + writeLogic_adapter_aw_rData_addr <= writeLogic_adapter_aw_payload_addr; + writeLogic_adapter_aw_rData_region <= writeLogic_adapter_aw_payload_region; + writeLogic_adapter_aw_rData_len <= writeLogic_adapter_aw_payload_len; + writeLogic_adapter_aw_rData_size <= writeLogic_adapter_aw_payload_size; + writeLogic_adapter_aw_rData_burst <= writeLogic_adapter_aw_payload_burst; + writeLogic_adapter_aw_rData_lock <= writeLogic_adapter_aw_payload_lock; + writeLogic_adapter_aw_rData_cache <= writeLogic_adapter_aw_payload_cache; + writeLogic_adapter_aw_rData_qos <= writeLogic_adapter_aw_payload_qos; + writeLogic_adapter_aw_rData_prot <= writeLogic_adapter_aw_payload_prot; + end + if(writeLogic_adapter_w_ready) begin + writeLogic_adapter_w_rData_data <= writeLogic_adapter_w_payload_data; + writeLogic_adapter_w_rData_strb <= writeLogic_adapter_w_payload_strb; + writeLogic_adapter_w_rData_last <= writeLogic_adapter_w_payload_last; + end + if(writeLogic_adapter_w_s2mPipe_ready) begin + writeLogic_adapter_w_s2mPipe_rData_data <= writeLogic_adapter_w_s2mPipe_payload_data; + writeLogic_adapter_w_s2mPipe_rData_strb <= writeLogic_adapter_w_s2mPipe_payload_strb; + writeLogic_adapter_w_s2mPipe_rData_last <= writeLogic_adapter_w_s2mPipe_payload_last; + end + if(write_bready) begin + write_b_rData_resp <= write_bresp; + end + if(io_pop_rValidN) begin + io_pop_rData_data <= inputsAdapter_0_crossclock_fifo_io_pop_payload_data; + io_pop_rData_mask <= inputsAdapter_0_crossclock_fifo_io_pop_payload_mask; + io_pop_rData_sink <= inputsAdapter_0_crossclock_fifo_io_pop_payload_sink; + io_pop_rData_last <= inputsAdapter_0_crossclock_fifo_io_pop_payload_last; + end + if(io_pop_s2mPipe_ready) begin + io_pop_s2mPipe_rData_data <= io_pop_s2mPipe_payload_data; + io_pop_s2mPipe_rData_mask <= io_pop_s2mPipe_payload_mask; + io_pop_s2mPipe_rData_sink <= io_pop_s2mPipe_payload_sink; + io_pop_s2mPipe_rData_last <= io_pop_s2mPipe_payload_last; + end + if(io_outputs_0_rValidN) begin + io_outputs_0_rData_data <= core_io_outputs_0_payload_data; + io_outputs_0_rData_mask <= core_io_outputs_0_payload_mask; + io_outputs_0_rData_sink <= core_io_outputs_0_payload_sink; + io_outputs_0_rData_last <= core_io_outputs_0_payload_last; + end + if(io_outputs_0_s2mPipe_ready) begin + io_outputs_0_s2mPipe_rData_data <= io_outputs_0_s2mPipe_payload_data; + io_outputs_0_s2mPipe_rData_mask <= io_outputs_0_s2mPipe_payload_mask; + io_outputs_0_s2mPipe_rData_sink <= io_outputs_0_s2mPipe_payload_sink; + io_outputs_0_s2mPipe_rData_last <= io_outputs_0_s2mPipe_payload_last; + end + end + + +endmodule + +module EfxDMA_BmbArbiter_1_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_inputs_0_cmd_valid, + output wire io_inputs_0_cmd_ready, + input wire io_inputs_0_cmd_payload_last, + input wire [0:0] io_inputs_0_cmd_payload_fragment_opcode, + input wire [31:0] io_inputs_0_cmd_payload_fragment_address, + input wire [1:0] io_inputs_0_cmd_payload_fragment_length, + input wire [127:0] io_inputs_0_cmd_payload_fragment_data, + input wire [15:0] io_inputs_0_cmd_payload_fragment_mask, + input wire [0:0] io_inputs_0_cmd_payload_fragment_context, + output wire io_inputs_0_rsp_valid, + input wire io_inputs_0_rsp_ready, + output wire io_inputs_0_rsp_payload_last, + output wire [0:0] io_inputs_0_rsp_payload_fragment_opcode, + output wire [0:0] io_inputs_0_rsp_payload_fragment_context, + input wire io_inputs_1_cmd_valid, + output wire io_inputs_1_cmd_ready, + input wire io_inputs_1_cmd_payload_last, + input wire [0:0] io_inputs_1_cmd_payload_fragment_opcode, + input wire [31:0] io_inputs_1_cmd_payload_fragment_address, + input wire [11:0] io_inputs_1_cmd_payload_fragment_length, + input wire [127:0] io_inputs_1_cmd_payload_fragment_data, + input wire [15:0] io_inputs_1_cmd_payload_fragment_mask, + input wire [12:0] io_inputs_1_cmd_payload_fragment_context, + output wire io_inputs_1_rsp_valid, + input wire io_inputs_1_rsp_ready, + output wire io_inputs_1_rsp_payload_last, + output wire [0:0] io_inputs_1_rsp_payload_fragment_opcode, + output wire [12:0] io_inputs_1_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_source, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + output wire [127:0] io_output_cmd_payload_fragment_data, + output wire [15:0] io_output_cmd_payload_fragment_mask, + output wire [12:0] io_output_cmd_payload_fragment_context, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_source, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [12:0] io_output_rsp_payload_fragment_context, + input wire clk, + input wire reset +); + + wire [11:0] memory_arbiter_io_inputs_0_payload_fragment_length; + wire [12:0] memory_arbiter_io_inputs_0_payload_fragment_context; + wire memory_arbiter_io_inputs_0_ready; + wire memory_arbiter_io_inputs_1_ready; + wire memory_arbiter_io_output_valid; + wire memory_arbiter_io_output_payload_last; + wire [0:0] memory_arbiter_io_output_payload_fragment_source; + wire [0:0] memory_arbiter_io_output_payload_fragment_opcode; + wire [31:0] memory_arbiter_io_output_payload_fragment_address; + wire [11:0] memory_arbiter_io_output_payload_fragment_length; + wire [127:0] memory_arbiter_io_output_payload_fragment_data; + wire [15:0] memory_arbiter_io_output_payload_fragment_mask; + wire [12:0] memory_arbiter_io_output_payload_fragment_context; + wire [0:0] memory_arbiter_io_chosen; + wire [1:0] memory_arbiter_io_chosenOH; + wire [1:0] _zz_io_output_cmd_payload_fragment_source; + reg _zz_io_output_rsp_ready; + wire [0:0] memory_rspSel; + + assign _zz_io_output_cmd_payload_fragment_source = {memory_arbiter_io_output_payload_fragment_source,memory_arbiter_io_chosen}; + EfxDMA_StreamArbiter_1_a048ca8f51874147a1cd65d43e6523ef memory_arbiter ( + .io_inputs_0_valid (io_inputs_0_cmd_valid ), //i + .io_inputs_0_ready (memory_arbiter_io_inputs_0_ready ), //o + .io_inputs_0_payload_last (io_inputs_0_cmd_payload_last ), //i + .io_inputs_0_payload_fragment_source (1'b0 ), //i + .io_inputs_0_payload_fragment_opcode (io_inputs_0_cmd_payload_fragment_opcode ), //i + .io_inputs_0_payload_fragment_address (io_inputs_0_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_0_payload_fragment_length (memory_arbiter_io_inputs_0_payload_fragment_length[11:0] ), //i + .io_inputs_0_payload_fragment_data (io_inputs_0_cmd_payload_fragment_data[127:0] ), //i + .io_inputs_0_payload_fragment_mask (io_inputs_0_cmd_payload_fragment_mask[15:0] ), //i + .io_inputs_0_payload_fragment_context (memory_arbiter_io_inputs_0_payload_fragment_context[12:0]), //i + .io_inputs_1_valid (io_inputs_1_cmd_valid ), //i + .io_inputs_1_ready (memory_arbiter_io_inputs_1_ready ), //o + .io_inputs_1_payload_last (io_inputs_1_cmd_payload_last ), //i + .io_inputs_1_payload_fragment_source (1'b0 ), //i + .io_inputs_1_payload_fragment_opcode (io_inputs_1_cmd_payload_fragment_opcode ), //i + .io_inputs_1_payload_fragment_address (io_inputs_1_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_1_payload_fragment_length (io_inputs_1_cmd_payload_fragment_length[11:0] ), //i + .io_inputs_1_payload_fragment_data (io_inputs_1_cmd_payload_fragment_data[127:0] ), //i + .io_inputs_1_payload_fragment_mask (io_inputs_1_cmd_payload_fragment_mask[15:0] ), //i + .io_inputs_1_payload_fragment_context (io_inputs_1_cmd_payload_fragment_context[12:0] ), //i + .io_output_valid (memory_arbiter_io_output_valid ), //o + .io_output_ready (io_output_cmd_ready ), //i + .io_output_payload_last (memory_arbiter_io_output_payload_last ), //o + .io_output_payload_fragment_source (memory_arbiter_io_output_payload_fragment_source ), //o + .io_output_payload_fragment_opcode (memory_arbiter_io_output_payload_fragment_opcode ), //o + .io_output_payload_fragment_address (memory_arbiter_io_output_payload_fragment_address[31:0] ), //o + .io_output_payload_fragment_length (memory_arbiter_io_output_payload_fragment_length[11:0] ), //o + .io_output_payload_fragment_data (memory_arbiter_io_output_payload_fragment_data[127:0] ), //o + .io_output_payload_fragment_mask (memory_arbiter_io_output_payload_fragment_mask[15:0] ), //o + .io_output_payload_fragment_context (memory_arbiter_io_output_payload_fragment_context[12:0] ), //o + .io_chosen (memory_arbiter_io_chosen ), //o + .io_chosenOH (memory_arbiter_io_chosenOH[1:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(memory_rspSel) + 1'b0 : _zz_io_output_rsp_ready = io_inputs_0_rsp_ready; + default : _zz_io_output_rsp_ready = io_inputs_1_rsp_ready; + endcase + end + + assign io_inputs_0_cmd_ready = memory_arbiter_io_inputs_0_ready; + assign memory_arbiter_io_inputs_0_payload_fragment_length = {10'd0, io_inputs_0_cmd_payload_fragment_length}; + assign memory_arbiter_io_inputs_0_payload_fragment_context = {12'd0, io_inputs_0_cmd_payload_fragment_context}; + assign io_inputs_1_cmd_ready = memory_arbiter_io_inputs_1_ready; + assign io_output_cmd_valid = memory_arbiter_io_output_valid; + assign io_output_cmd_payload_last = memory_arbiter_io_output_payload_last; + assign io_output_cmd_payload_fragment_opcode = memory_arbiter_io_output_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = memory_arbiter_io_output_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = memory_arbiter_io_output_payload_fragment_length; + assign io_output_cmd_payload_fragment_data = memory_arbiter_io_output_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = memory_arbiter_io_output_payload_fragment_mask; + assign io_output_cmd_payload_fragment_context = memory_arbiter_io_output_payload_fragment_context; + assign io_output_cmd_payload_fragment_source = _zz_io_output_cmd_payload_fragment_source[0:0]; + assign memory_rspSel = io_output_rsp_payload_fragment_source[0 : 0]; + assign io_inputs_0_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b0)); + assign io_inputs_0_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_0_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_0_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context[0:0]; + assign io_inputs_1_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b1)); + assign io_inputs_1_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_1_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_1_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; + assign io_output_rsp_ready = _zz_io_output_rsp_ready; + +endmodule + +module EfxDMA_BmbArbiter_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_inputs_0_cmd_valid, + output wire io_inputs_0_cmd_ready, + input wire io_inputs_0_cmd_payload_last, + input wire [0:0] io_inputs_0_cmd_payload_fragment_opcode, + input wire [31:0] io_inputs_0_cmd_payload_fragment_address, + input wire [4:0] io_inputs_0_cmd_payload_fragment_length, + input wire [0:0] io_inputs_0_cmd_payload_fragment_context, + output wire io_inputs_0_rsp_valid, + input wire io_inputs_0_rsp_ready, + output wire io_inputs_0_rsp_payload_last, + output wire [0:0] io_inputs_0_rsp_payload_fragment_opcode, + output wire [127:0] io_inputs_0_rsp_payload_fragment_data, + output wire [0:0] io_inputs_0_rsp_payload_fragment_context, + input wire io_inputs_1_cmd_valid, + output wire io_inputs_1_cmd_ready, + input wire io_inputs_1_cmd_payload_last, + input wire [0:0] io_inputs_1_cmd_payload_fragment_opcode, + input wire [31:0] io_inputs_1_cmd_payload_fragment_address, + input wire [11:0] io_inputs_1_cmd_payload_fragment_length, + input wire [20:0] io_inputs_1_cmd_payload_fragment_context, + output wire io_inputs_1_rsp_valid, + input wire io_inputs_1_rsp_ready, + output wire io_inputs_1_rsp_payload_last, + output wire [0:0] io_inputs_1_rsp_payload_fragment_opcode, + output wire [127:0] io_inputs_1_rsp_payload_fragment_data, + output wire [20:0] io_inputs_1_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_source, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + output wire [20:0] io_output_cmd_payload_fragment_context, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_source, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [127:0] io_output_rsp_payload_fragment_data, + input wire [20:0] io_output_rsp_payload_fragment_context, + input wire clk, + input wire reset +); + + wire [11:0] memory_arbiter_io_inputs_0_payload_fragment_length; + wire [20:0] memory_arbiter_io_inputs_0_payload_fragment_context; + wire memory_arbiter_io_inputs_0_ready; + wire memory_arbiter_io_inputs_1_ready; + wire memory_arbiter_io_output_valid; + wire memory_arbiter_io_output_payload_last; + wire [0:0] memory_arbiter_io_output_payload_fragment_source; + wire [0:0] memory_arbiter_io_output_payload_fragment_opcode; + wire [31:0] memory_arbiter_io_output_payload_fragment_address; + wire [11:0] memory_arbiter_io_output_payload_fragment_length; + wire [20:0] memory_arbiter_io_output_payload_fragment_context; + wire [0:0] memory_arbiter_io_chosen; + wire [1:0] memory_arbiter_io_chosenOH; + wire [1:0] _zz_io_output_cmd_payload_fragment_source; + reg _zz_io_output_rsp_ready; + wire [0:0] memory_rspSel; + + assign _zz_io_output_cmd_payload_fragment_source = {memory_arbiter_io_output_payload_fragment_source,memory_arbiter_io_chosen}; + EfxDMA_StreamArbiter_a048ca8f51874147a1cd65d43e6523ef memory_arbiter ( + .io_inputs_0_valid (io_inputs_0_cmd_valid ), //i + .io_inputs_0_ready (memory_arbiter_io_inputs_0_ready ), //o + .io_inputs_0_payload_last (io_inputs_0_cmd_payload_last ), //i + .io_inputs_0_payload_fragment_source (1'b0 ), //i + .io_inputs_0_payload_fragment_opcode (io_inputs_0_cmd_payload_fragment_opcode ), //i + .io_inputs_0_payload_fragment_address (io_inputs_0_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_0_payload_fragment_length (memory_arbiter_io_inputs_0_payload_fragment_length[11:0] ), //i + .io_inputs_0_payload_fragment_context (memory_arbiter_io_inputs_0_payload_fragment_context[20:0]), //i + .io_inputs_1_valid (io_inputs_1_cmd_valid ), //i + .io_inputs_1_ready (memory_arbiter_io_inputs_1_ready ), //o + .io_inputs_1_payload_last (io_inputs_1_cmd_payload_last ), //i + .io_inputs_1_payload_fragment_source (1'b0 ), //i + .io_inputs_1_payload_fragment_opcode (io_inputs_1_cmd_payload_fragment_opcode ), //i + .io_inputs_1_payload_fragment_address (io_inputs_1_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_1_payload_fragment_length (io_inputs_1_cmd_payload_fragment_length[11:0] ), //i + .io_inputs_1_payload_fragment_context (io_inputs_1_cmd_payload_fragment_context[20:0] ), //i + .io_output_valid (memory_arbiter_io_output_valid ), //o + .io_output_ready (io_output_cmd_ready ), //i + .io_output_payload_last (memory_arbiter_io_output_payload_last ), //o + .io_output_payload_fragment_source (memory_arbiter_io_output_payload_fragment_source ), //o + .io_output_payload_fragment_opcode (memory_arbiter_io_output_payload_fragment_opcode ), //o + .io_output_payload_fragment_address (memory_arbiter_io_output_payload_fragment_address[31:0] ), //o + .io_output_payload_fragment_length (memory_arbiter_io_output_payload_fragment_length[11:0] ), //o + .io_output_payload_fragment_context (memory_arbiter_io_output_payload_fragment_context[20:0] ), //o + .io_chosen (memory_arbiter_io_chosen ), //o + .io_chosenOH (memory_arbiter_io_chosenOH[1:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(memory_rspSel) + 1'b0 : _zz_io_output_rsp_ready = io_inputs_0_rsp_ready; + default : _zz_io_output_rsp_ready = io_inputs_1_rsp_ready; + endcase + end + + assign io_inputs_0_cmd_ready = memory_arbiter_io_inputs_0_ready; + assign memory_arbiter_io_inputs_0_payload_fragment_length = {7'd0, io_inputs_0_cmd_payload_fragment_length}; + assign memory_arbiter_io_inputs_0_payload_fragment_context = {20'd0, io_inputs_0_cmd_payload_fragment_context}; + assign io_inputs_1_cmd_ready = memory_arbiter_io_inputs_1_ready; + assign io_output_cmd_valid = memory_arbiter_io_output_valid; + assign io_output_cmd_payload_last = memory_arbiter_io_output_payload_last; + assign io_output_cmd_payload_fragment_opcode = memory_arbiter_io_output_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = memory_arbiter_io_output_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = memory_arbiter_io_output_payload_fragment_length; + assign io_output_cmd_payload_fragment_context = memory_arbiter_io_output_payload_fragment_context; + assign io_output_cmd_payload_fragment_source = _zz_io_output_cmd_payload_fragment_source[0:0]; + assign memory_rspSel = io_output_rsp_payload_fragment_source[0 : 0]; + assign io_inputs_0_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b0)); + assign io_inputs_0_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_0_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_0_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_inputs_0_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context[0:0]; + assign io_inputs_1_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b1)); + assign io_inputs_1_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_1_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_1_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_inputs_1_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; + assign io_output_rsp_ready = _zz_io_output_rsp_ready; + +endmodule + +module EfxDMA_BsbDownSizerSparse_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_input_valid, + output wire io_input_ready, + input wire [63:0] io_input_payload_data, + input wire [7:0] io_input_payload_mask, + input wire [3:0] io_input_payload_sink, + input wire io_input_payload_last, + output wire io_output_valid, + input wire io_output_ready, + output wire [7:0] io_output_payload_data, + output wire [0:0] io_output_payload_mask, + output wire [3:0] io_output_payload_sink, + output wire io_output_payload_last, + input wire dat1_o_clk, + input wire dat1_o_reset +); + + reg [7:0] _zz_io_output_payload_data; + reg [0:0] _zz_io_output_payload_mask; + reg [2:0] counter; + wire end_1; + wire io_output_fire; + + always @(*) begin + case(counter) + 3'b000 : begin + _zz_io_output_payload_data = io_input_payload_data[7 : 0]; + _zz_io_output_payload_mask = io_input_payload_mask[0 : 0]; + end + 3'b001 : begin + _zz_io_output_payload_data = io_input_payload_data[15 : 8]; + _zz_io_output_payload_mask = io_input_payload_mask[1 : 1]; + end + 3'b010 : begin + _zz_io_output_payload_data = io_input_payload_data[23 : 16]; + _zz_io_output_payload_mask = io_input_payload_mask[2 : 2]; + end + 3'b011 : begin + _zz_io_output_payload_data = io_input_payload_data[31 : 24]; + _zz_io_output_payload_mask = io_input_payload_mask[3 : 3]; + end + 3'b100 : begin + _zz_io_output_payload_data = io_input_payload_data[39 : 32]; + _zz_io_output_payload_mask = io_input_payload_mask[4 : 4]; + end + 3'b101 : begin + _zz_io_output_payload_data = io_input_payload_data[47 : 40]; + _zz_io_output_payload_mask = io_input_payload_mask[5 : 5]; + end + 3'b110 : begin + _zz_io_output_payload_data = io_input_payload_data[55 : 48]; + _zz_io_output_payload_mask = io_input_payload_mask[6 : 6]; + end + default : begin + _zz_io_output_payload_data = io_input_payload_data[63 : 56]; + _zz_io_output_payload_mask = io_input_payload_mask[7 : 7]; + end + endcase + end + + assign end_1 = (counter == 3'b111); + assign io_output_fire = (io_output_valid && io_output_ready); + assign io_input_ready = (io_output_ready && end_1); + assign io_output_valid = io_input_valid; + assign io_output_payload_data = _zz_io_output_payload_data; + assign io_output_payload_mask = _zz_io_output_payload_mask; + assign io_output_payload_sink = io_input_payload_sink; + assign io_output_payload_last = (io_input_payload_last && end_1); + always @(posedge dat1_o_clk) begin + if(dat1_o_reset) begin + counter <= 3'b000; + end else begin + if(io_output_fire) begin + counter <= (counter + 3'b001); + end + end + end + + +endmodule + +module EfxDMA_StreamFifoCC_1_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_push_valid, + output wire io_push_ready, + input wire [63:0] io_push_payload_data, + input wire [7:0] io_push_payload_mask, + input wire [3:0] io_push_payload_sink, + input wire io_push_payload_last, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [63:0] io_pop_payload_data, + output wire [7:0] io_pop_payload_mask, + output wire [3:0] io_pop_payload_sink, + output wire io_pop_payload_last, + output wire [4:0] io_pushOccupancy, + output wire [4:0] io_popOccupancy, + input wire clk, + input wire reset, + input wire dat1_o_clk, + input wire dat1_o_reset +); + + reg [76:0] ram_spinal_port1; + wire [4:0] popToPushGray_buffercc_io_dataOut; + wire [4:0] pushToPopGray_buffercc_io_dataOut; + wire [4:0] _zz_pushCC_pushPtrGray; + wire [3:0] _zz_ram_port; + wire [76:0] _zz_ram_port_1; + wire [4:0] _zz_popCC_popPtrGray; + reg _zz_1; + wire [4:0] popToPushGray; + wire [4:0] pushToPopGray; + reg [4:0] pushCC_pushPtr; + wire [4:0] pushCC_pushPtrPlus; + wire io_push_fire; + reg [4:0] pushCC_pushPtrGray; + wire [4:0] pushCC_popPtrGray; + wire pushCC_full; + wire _zz_io_pushOccupancy; + wire _zz_io_pushOccupancy_1; + wire _zz_io_pushOccupancy_2; + wire _zz_io_pushOccupancy_3; + reg [4:0] popCC_popPtr; + (* keep , syn_keep *) wire [4:0] popCC_popPtrPlus /* synthesis syn_keep = 1 */ ; + wire [4:0] popCC_popPtrGray; + wire [4:0] popCC_pushPtrGray; + wire popCC_addressGen_valid; + reg popCC_addressGen_ready; + wire [3:0] popCC_addressGen_payload; + wire popCC_empty; + wire popCC_addressGen_fire; + wire popCC_readArbitation_valid; + wire popCC_readArbitation_ready; + wire [3:0] popCC_readArbitation_payload; + reg popCC_addressGen_rValid; + reg [3:0] popCC_addressGen_rData; + wire when_Stream_l375; + wire popCC_readPort_cmd_valid; + wire [3:0] popCC_readPort_cmd_payload; + wire [63:0] popCC_readPort_rsp_data; + wire [7:0] popCC_readPort_rsp_mask; + wire [3:0] popCC_readPort_rsp_sink; + wire popCC_readPort_rsp_last; + wire [76:0] _zz_popCC_readPort_rsp_data; + wire popCC_readArbitation_translated_valid; + wire popCC_readArbitation_translated_ready; + wire [63:0] popCC_readArbitation_translated_payload_data; + wire [7:0] popCC_readArbitation_translated_payload_mask; + wire [3:0] popCC_readArbitation_translated_payload_sink; + wire popCC_readArbitation_translated_payload_last; + wire popCC_readArbitation_fire; + reg [4:0] popCC_ptrToPush; + reg [4:0] popCC_ptrToOccupancy; + wire _zz_io_popOccupancy; + wire _zz_io_popOccupancy_1; + wire _zz_io_popOccupancy_2; + wire _zz_io_popOccupancy_3; + reg [76:0] ram [0:15]; + + assign _zz_pushCC_pushPtrGray = (pushCC_pushPtrPlus >>> 1'b1); + assign _zz_ram_port = pushCC_pushPtr[3:0]; + assign _zz_popCC_popPtrGray = (popCC_popPtr >>> 1'b1); + assign _zz_ram_port_1 = {io_push_payload_last,{io_push_payload_sink,{io_push_payload_mask,io_push_payload_data}}}; + always @(posedge clk) begin + if(_zz_1) begin + ram[_zz_ram_port] <= _zz_ram_port_1; + end + end + + always @(posedge dat1_o_clk) begin + if(popCC_readPort_cmd_valid) begin + ram_spinal_port1 <= ram[popCC_readPort_cmd_payload]; + end + end + + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_3_a048ca8f51874147a1cd65d43e6523ef popToPushGray_buffercc ( + .io_dataIn (popToPushGray[4:0] ), //i + .io_dataOut (popToPushGray_buffercc_io_dataOut[4:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_5_a048ca8f51874147a1cd65d43e6523ef pushToPopGray_buffercc ( + .io_dataIn (pushToPopGray[4:0] ), //i + .io_dataOut (pushToPopGray_buffercc_io_dataOut[4:0]), //o + .dat1_o_clk (dat1_o_clk ), //i + .dat1_o_reset (dat1_o_reset ) //i + ); + always @(*) begin + _zz_1 = 1'b0; + if(io_push_fire) begin + _zz_1 = 1'b1; + end + end + + assign pushCC_pushPtrPlus = (pushCC_pushPtr + 5'h01); + assign io_push_fire = (io_push_valid && io_push_ready); + assign pushCC_popPtrGray = popToPushGray_buffercc_io_dataOut; + assign pushCC_full = ((pushCC_pushPtrGray[4 : 3] == (~ pushCC_popPtrGray[4 : 3])) && (pushCC_pushPtrGray[2 : 0] == pushCC_popPtrGray[2 : 0])); + assign io_push_ready = (! pushCC_full); + assign _zz_io_pushOccupancy = (pushCC_popPtrGray[1] ^ _zz_io_pushOccupancy_1); + assign _zz_io_pushOccupancy_1 = (pushCC_popPtrGray[2] ^ _zz_io_pushOccupancy_2); + assign _zz_io_pushOccupancy_2 = (pushCC_popPtrGray[3] ^ _zz_io_pushOccupancy_3); + assign _zz_io_pushOccupancy_3 = pushCC_popPtrGray[4]; + assign io_pushOccupancy = (pushCC_pushPtr - {_zz_io_pushOccupancy_3,{_zz_io_pushOccupancy_2,{_zz_io_pushOccupancy_1,{_zz_io_pushOccupancy,(pushCC_popPtrGray[0] ^ _zz_io_pushOccupancy)}}}}); + assign popCC_popPtrPlus = (popCC_popPtr + 5'h01); + assign popCC_popPtrGray = (_zz_popCC_popPtrGray ^ popCC_popPtr); + assign popCC_pushPtrGray = pushToPopGray_buffercc_io_dataOut; + assign popCC_empty = (popCC_popPtrGray == popCC_pushPtrGray); + assign popCC_addressGen_valid = (! popCC_empty); + assign popCC_addressGen_payload = popCC_popPtr[3:0]; + assign popCC_addressGen_fire = (popCC_addressGen_valid && popCC_addressGen_ready); + always @(*) begin + popCC_addressGen_ready = popCC_readArbitation_ready; + if(when_Stream_l375) begin + popCC_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! popCC_readArbitation_valid); + assign popCC_readArbitation_valid = popCC_addressGen_rValid; + assign popCC_readArbitation_payload = popCC_addressGen_rData; + assign _zz_popCC_readPort_rsp_data = ram_spinal_port1; + assign popCC_readPort_rsp_data = _zz_popCC_readPort_rsp_data[63 : 0]; + assign popCC_readPort_rsp_mask = _zz_popCC_readPort_rsp_data[71 : 64]; + assign popCC_readPort_rsp_sink = _zz_popCC_readPort_rsp_data[75 : 72]; + assign popCC_readPort_rsp_last = _zz_popCC_readPort_rsp_data[76]; + assign popCC_readPort_cmd_valid = popCC_addressGen_fire; + assign popCC_readPort_cmd_payload = popCC_addressGen_payload; + assign popCC_readArbitation_translated_valid = popCC_readArbitation_valid; + assign popCC_readArbitation_ready = popCC_readArbitation_translated_ready; + assign popCC_readArbitation_translated_payload_data = popCC_readPort_rsp_data; + assign popCC_readArbitation_translated_payload_mask = popCC_readPort_rsp_mask; + assign popCC_readArbitation_translated_payload_sink = popCC_readPort_rsp_sink; + assign popCC_readArbitation_translated_payload_last = popCC_readPort_rsp_last; + assign io_pop_valid = popCC_readArbitation_translated_valid; + assign popCC_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_data = popCC_readArbitation_translated_payload_data; + assign io_pop_payload_mask = popCC_readArbitation_translated_payload_mask; + assign io_pop_payload_sink = popCC_readArbitation_translated_payload_sink; + assign io_pop_payload_last = popCC_readArbitation_translated_payload_last; + assign popCC_readArbitation_fire = (popCC_readArbitation_valid && popCC_readArbitation_ready); + assign _zz_io_popOccupancy = (popCC_pushPtrGray[1] ^ _zz_io_popOccupancy_1); + assign _zz_io_popOccupancy_1 = (popCC_pushPtrGray[2] ^ _zz_io_popOccupancy_2); + assign _zz_io_popOccupancy_2 = (popCC_pushPtrGray[3] ^ _zz_io_popOccupancy_3); + assign _zz_io_popOccupancy_3 = popCC_pushPtrGray[4]; + assign io_popOccupancy = ({_zz_io_popOccupancy_3,{_zz_io_popOccupancy_2,{_zz_io_popOccupancy_1,{_zz_io_popOccupancy,(popCC_pushPtrGray[0] ^ _zz_io_popOccupancy)}}}} - popCC_ptrToOccupancy); + assign pushToPopGray = pushCC_pushPtrGray; + assign popToPushGray = popCC_ptrToPush; + always @(posedge clk) begin + if(reset) begin + pushCC_pushPtr <= 5'h0; + pushCC_pushPtrGray <= 5'h0; + end else begin + if(io_push_fire) begin + pushCC_pushPtrGray <= (_zz_pushCC_pushPtrGray ^ pushCC_pushPtrPlus); + end + if(io_push_fire) begin + pushCC_pushPtr <= pushCC_pushPtrPlus; + end + end + end + + always @(posedge dat1_o_clk) begin + if(dat1_o_reset) begin + popCC_popPtr <= 5'h0; + popCC_addressGen_rValid <= 1'b0; + popCC_ptrToPush <= 5'h0; + popCC_ptrToOccupancy <= 5'h0; + end else begin + if(popCC_addressGen_fire) begin + popCC_popPtr <= popCC_popPtrPlus; + end + if(popCC_addressGen_ready) begin + popCC_addressGen_rValid <= popCC_addressGen_valid; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToPush <= popCC_popPtrGray; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToOccupancy <= popCC_popPtr; + end + end + end + + always @(posedge dat1_o_clk) begin + if(popCC_addressGen_ready) begin + popCC_addressGen_rData <= popCC_addressGen_payload; + end + end + + +endmodule + +module EfxDMA_StreamFifoCC_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_push_valid, + output wire io_push_ready, + input wire [63:0] io_push_payload_data, + input wire [7:0] io_push_payload_mask, + input wire [3:0] io_push_payload_sink, + input wire io_push_payload_last, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [63:0] io_pop_payload_data, + output wire [7:0] io_pop_payload_mask, + output wire [3:0] io_pop_payload_sink, + output wire io_pop_payload_last, + output wire [4:0] io_pushOccupancy, + output wire [4:0] io_popOccupancy, + input wire dat0_i_clk, + input wire dat0_i_reset, + input wire clk, + input wire reset +); + + reg [76:0] ram_spinal_port1; + wire [4:0] popToPushGray_buffercc_io_dataOut; + wire [4:0] pushToPopGray_buffercc_io_dataOut; + wire [4:0] _zz_pushCC_pushPtrGray; + wire [3:0] _zz_ram_port; + wire [76:0] _zz_ram_port_1; + wire [4:0] _zz_popCC_popPtrGray; + reg _zz_1; + wire [4:0] popToPushGray; + wire [4:0] pushToPopGray; + reg [4:0] pushCC_pushPtr; + wire [4:0] pushCC_pushPtrPlus; + wire io_push_fire; + reg [4:0] pushCC_pushPtrGray; + wire [4:0] pushCC_popPtrGray; + wire pushCC_full; + wire _zz_io_pushOccupancy; + wire _zz_io_pushOccupancy_1; + wire _zz_io_pushOccupancy_2; + wire _zz_io_pushOccupancy_3; + reg [4:0] popCC_popPtr; + (* keep , syn_keep *) wire [4:0] popCC_popPtrPlus /* synthesis syn_keep = 1 */ ; + wire [4:0] popCC_popPtrGray; + wire [4:0] popCC_pushPtrGray; + wire popCC_addressGen_valid; + reg popCC_addressGen_ready; + wire [3:0] popCC_addressGen_payload; + wire popCC_empty; + wire popCC_addressGen_fire; + wire popCC_readArbitation_valid; + wire popCC_readArbitation_ready; + wire [3:0] popCC_readArbitation_payload; + reg popCC_addressGen_rValid; + reg [3:0] popCC_addressGen_rData; + wire when_Stream_l375; + wire popCC_readPort_cmd_valid; + wire [3:0] popCC_readPort_cmd_payload; + wire [63:0] popCC_readPort_rsp_data; + wire [7:0] popCC_readPort_rsp_mask; + wire [3:0] popCC_readPort_rsp_sink; + wire popCC_readPort_rsp_last; + wire [76:0] _zz_popCC_readPort_rsp_data; + wire popCC_readArbitation_translated_valid; + wire popCC_readArbitation_translated_ready; + wire [63:0] popCC_readArbitation_translated_payload_data; + wire [7:0] popCC_readArbitation_translated_payload_mask; + wire [3:0] popCC_readArbitation_translated_payload_sink; + wire popCC_readArbitation_translated_payload_last; + wire popCC_readArbitation_fire; + reg [4:0] popCC_ptrToPush; + reg [4:0] popCC_ptrToOccupancy; + wire _zz_io_popOccupancy; + wire _zz_io_popOccupancy_1; + wire _zz_io_popOccupancy_2; + wire _zz_io_popOccupancy_3; + reg [76:0] ram [0:15]; + + assign _zz_pushCC_pushPtrGray = (pushCC_pushPtrPlus >>> 1'b1); + assign _zz_ram_port = pushCC_pushPtr[3:0]; + assign _zz_popCC_popPtrGray = (popCC_popPtr >>> 1'b1); + assign _zz_ram_port_1 = {io_push_payload_last,{io_push_payload_sink,{io_push_payload_mask,io_push_payload_data}}}; + always @(posedge dat0_i_clk) begin + if(_zz_1) begin + ram[_zz_ram_port] <= _zz_ram_port_1; + end + end + + always @(posedge clk) begin + if(popCC_readPort_cmd_valid) begin + ram_spinal_port1 <= ram[popCC_readPort_cmd_payload]; + end + end + + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_2_a048ca8f51874147a1cd65d43e6523ef popToPushGray_buffercc ( + .io_dataIn (popToPushGray[4:0] ), //i + .io_dataOut (popToPushGray_buffercc_io_dataOut[4:0]), //o + .dat0_i_clk (dat0_i_clk ), //i + .dat0_i_reset (dat0_i_reset ) //i + ); + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_3_a048ca8f51874147a1cd65d43e6523ef pushToPopGray_buffercc ( + .io_dataIn (pushToPopGray[4:0] ), //i + .io_dataOut (pushToPopGray_buffercc_io_dataOut[4:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + _zz_1 = 1'b0; + if(io_push_fire) begin + _zz_1 = 1'b1; + end + end + + assign pushCC_pushPtrPlus = (pushCC_pushPtr + 5'h01); + assign io_push_fire = (io_push_valid && io_push_ready); + assign pushCC_popPtrGray = popToPushGray_buffercc_io_dataOut; + assign pushCC_full = ((pushCC_pushPtrGray[4 : 3] == (~ pushCC_popPtrGray[4 : 3])) && (pushCC_pushPtrGray[2 : 0] == pushCC_popPtrGray[2 : 0])); + assign io_push_ready = (! pushCC_full); + assign _zz_io_pushOccupancy = (pushCC_popPtrGray[1] ^ _zz_io_pushOccupancy_1); + assign _zz_io_pushOccupancy_1 = (pushCC_popPtrGray[2] ^ _zz_io_pushOccupancy_2); + assign _zz_io_pushOccupancy_2 = (pushCC_popPtrGray[3] ^ _zz_io_pushOccupancy_3); + assign _zz_io_pushOccupancy_3 = pushCC_popPtrGray[4]; + assign io_pushOccupancy = (pushCC_pushPtr - {_zz_io_pushOccupancy_3,{_zz_io_pushOccupancy_2,{_zz_io_pushOccupancy_1,{_zz_io_pushOccupancy,(pushCC_popPtrGray[0] ^ _zz_io_pushOccupancy)}}}}); + assign popCC_popPtrPlus = (popCC_popPtr + 5'h01); + assign popCC_popPtrGray = (_zz_popCC_popPtrGray ^ popCC_popPtr); + assign popCC_pushPtrGray = pushToPopGray_buffercc_io_dataOut; + assign popCC_empty = (popCC_popPtrGray == popCC_pushPtrGray); + assign popCC_addressGen_valid = (! popCC_empty); + assign popCC_addressGen_payload = popCC_popPtr[3:0]; + assign popCC_addressGen_fire = (popCC_addressGen_valid && popCC_addressGen_ready); + always @(*) begin + popCC_addressGen_ready = popCC_readArbitation_ready; + if(when_Stream_l375) begin + popCC_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! popCC_readArbitation_valid); + assign popCC_readArbitation_valid = popCC_addressGen_rValid; + assign popCC_readArbitation_payload = popCC_addressGen_rData; + assign _zz_popCC_readPort_rsp_data = ram_spinal_port1; + assign popCC_readPort_rsp_data = _zz_popCC_readPort_rsp_data[63 : 0]; + assign popCC_readPort_rsp_mask = _zz_popCC_readPort_rsp_data[71 : 64]; + assign popCC_readPort_rsp_sink = _zz_popCC_readPort_rsp_data[75 : 72]; + assign popCC_readPort_rsp_last = _zz_popCC_readPort_rsp_data[76]; + assign popCC_readPort_cmd_valid = popCC_addressGen_fire; + assign popCC_readPort_cmd_payload = popCC_addressGen_payload; + assign popCC_readArbitation_translated_valid = popCC_readArbitation_valid; + assign popCC_readArbitation_ready = popCC_readArbitation_translated_ready; + assign popCC_readArbitation_translated_payload_data = popCC_readPort_rsp_data; + assign popCC_readArbitation_translated_payload_mask = popCC_readPort_rsp_mask; + assign popCC_readArbitation_translated_payload_sink = popCC_readPort_rsp_sink; + assign popCC_readArbitation_translated_payload_last = popCC_readPort_rsp_last; + assign io_pop_valid = popCC_readArbitation_translated_valid; + assign popCC_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_data = popCC_readArbitation_translated_payload_data; + assign io_pop_payload_mask = popCC_readArbitation_translated_payload_mask; + assign io_pop_payload_sink = popCC_readArbitation_translated_payload_sink; + assign io_pop_payload_last = popCC_readArbitation_translated_payload_last; + assign popCC_readArbitation_fire = (popCC_readArbitation_valid && popCC_readArbitation_ready); + assign _zz_io_popOccupancy = (popCC_pushPtrGray[1] ^ _zz_io_popOccupancy_1); + assign _zz_io_popOccupancy_1 = (popCC_pushPtrGray[2] ^ _zz_io_popOccupancy_2); + assign _zz_io_popOccupancy_2 = (popCC_pushPtrGray[3] ^ _zz_io_popOccupancy_3); + assign _zz_io_popOccupancy_3 = popCC_pushPtrGray[4]; + assign io_popOccupancy = ({_zz_io_popOccupancy_3,{_zz_io_popOccupancy_2,{_zz_io_popOccupancy_1,{_zz_io_popOccupancy,(popCC_pushPtrGray[0] ^ _zz_io_popOccupancy)}}}} - popCC_ptrToOccupancy); + assign pushToPopGray = pushCC_pushPtrGray; + assign popToPushGray = popCC_ptrToPush; + always @(posedge dat0_i_clk) begin + if(dat0_i_reset) begin + pushCC_pushPtr <= 5'h0; + pushCC_pushPtrGray <= 5'h0; + end else begin + if(io_push_fire) begin + pushCC_pushPtrGray <= (_zz_pushCC_pushPtrGray ^ pushCC_pushPtrPlus); + end + if(io_push_fire) begin + pushCC_pushPtr <= pushCC_pushPtrPlus; + end + end + end + + always @(posedge clk) begin + if(reset) begin + popCC_popPtr <= 5'h0; + popCC_addressGen_rValid <= 1'b0; + popCC_ptrToPush <= 5'h0; + popCC_ptrToOccupancy <= 5'h0; + end else begin + if(popCC_addressGen_fire) begin + popCC_popPtr <= popCC_popPtrPlus; + end + if(popCC_addressGen_ready) begin + popCC_addressGen_rValid <= popCC_addressGen_valid; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToPush <= popCC_popPtrGray; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToOccupancy <= popCC_popPtr; + end + end + end + + always @(posedge clk) begin + if(popCC_addressGen_ready) begin + popCC_addressGen_rData <= popCC_addressGen_payload; + end + end + + +endmodule + +module EfxDMA_BsbUpSizerDense_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_input_valid, + output wire io_input_ready, + input wire [7:0] io_input_payload_data, + input wire [0:0] io_input_payload_mask, + input wire [3:0] io_input_payload_sink, + input wire io_input_payload_last, + output wire io_output_valid, + input wire io_output_ready, + output wire [63:0] io_output_payload_data, + output wire [7:0] io_output_payload_mask, + output wire [3:0] io_output_payload_sink, + output wire io_output_payload_last, + input wire dat0_i_clk, + input wire dat0_i_reset +); + + reg valid; + reg [2:0] counter; + reg [63:0] buffer_data; + reg [7:0] buffer_mask; + reg [3:0] buffer_sink; + reg buffer_last; + wire full; + wire canAggregate; + wire onOutput; + wire [2:0] counterSample; + wire io_output_fire; + wire io_input_fire; + wire [7:0] _zz_1; + wire [7:0] _zz_2; + + assign full = ((counter == 3'b000) || buffer_last); + assign canAggregate = ((((valid && (! buffer_last)) && (! full)) && 1'b1) && (buffer_sink == io_input_payload_sink)); + assign counterSample = (canAggregate ? counter : 3'b000); + assign io_output_fire = (io_output_valid && io_output_ready); + assign io_input_fire = (io_input_valid && io_input_ready); + assign _zz_1 = ({7'd0,1'b1} <<< counterSample); + assign _zz_2 = ({7'd0,1'b1} <<< counterSample); + assign io_output_valid = (valid && ((valid && full) || (io_input_valid && (! canAggregate)))); + assign io_output_payload_data = buffer_data; + assign io_output_payload_mask = buffer_mask; + assign io_output_payload_sink = buffer_sink; + assign io_output_payload_last = buffer_last; + assign io_input_ready = (((! valid) || canAggregate) || io_output_ready); + always @(posedge dat0_i_clk) begin + if(dat0_i_reset) begin + valid <= 1'b0; + counter <= 3'b000; + buffer_last <= 1'b0; + buffer_mask <= 8'h0; + end else begin + if(io_output_fire) begin + valid <= 1'b0; + buffer_mask <= 8'h0; + end + if(io_input_fire) begin + valid <= 1'b1; + if(_zz_2[0]) begin + buffer_mask[0 : 0] <= io_input_payload_mask; + end + if(_zz_2[1]) begin + buffer_mask[1 : 1] <= io_input_payload_mask; + end + if(_zz_2[2]) begin + buffer_mask[2 : 2] <= io_input_payload_mask; + end + if(_zz_2[3]) begin + buffer_mask[3 : 3] <= io_input_payload_mask; + end + if(_zz_2[4]) begin + buffer_mask[4 : 4] <= io_input_payload_mask; + end + if(_zz_2[5]) begin + buffer_mask[5 : 5] <= io_input_payload_mask; + end + if(_zz_2[6]) begin + buffer_mask[6 : 6] <= io_input_payload_mask; + end + if(_zz_2[7]) begin + buffer_mask[7 : 7] <= io_input_payload_mask; + end + buffer_last <= io_input_payload_last; + counter <= (counterSample + 3'b001); + end + end + end + + always @(posedge dat0_i_clk) begin + if(io_input_fire) begin + buffer_sink <= io_input_payload_sink; + if(_zz_1[0]) begin + buffer_data[7 : 0] <= io_input_payload_data; + end + if(_zz_1[1]) begin + buffer_data[15 : 8] <= io_input_payload_data; + end + if(_zz_1[2]) begin + buffer_data[23 : 16] <= io_input_payload_data; + end + if(_zz_1[3]) begin + buffer_data[31 : 24] <= io_input_payload_data; + end + if(_zz_1[4]) begin + buffer_data[39 : 32] <= io_input_payload_data; + end + if(_zz_1[5]) begin + buffer_data[47 : 40] <= io_input_payload_data; + end + if(_zz_1[6]) begin + buffer_data[55 : 48] <= io_input_payload_data; + end + if(_zz_1[7]) begin + buffer_data[63 : 56] <= io_input_payload_data; + end + end + end + + +endmodule + +module EfxDMA_BmbToAxi4WriteOnlyBridge_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [127:0] io_input_cmd_payload_fragment_data, + input wire [15:0] io_input_cmd_payload_fragment_mask, + input wire [13:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [13:0] io_input_rsp_payload_fragment_context, + output wire io_output_aw_valid, + input wire io_output_aw_ready, + output wire [31:0] io_output_aw_payload_addr, + output wire [7:0] io_output_aw_payload_len, + output wire [2:0] io_output_aw_payload_size, + output wire [3:0] io_output_aw_payload_cache, + output wire [2:0] io_output_aw_payload_prot, + output wire io_output_w_valid, + input wire io_output_w_ready, + output wire [127:0] io_output_w_payload_data, + output wire [15:0] io_output_w_payload_strb, + output wire io_output_w_payload_last, + input wire io_output_b_valid, + output wire io_output_b_ready, + input wire [1:0] io_output_b_payload_resp, + input wire clk, + input wire reset +); + + reg contextRemover_io_output_cmd_ready; + reg [0:0] contextRemover_io_output_rsp_payload_fragment_opcode; + wire contextRemover_io_input_cmd_ready; + wire contextRemover_io_input_rsp_valid; + wire contextRemover_io_input_rsp_payload_last; + wire [0:0] contextRemover_io_input_rsp_payload_fragment_opcode; + wire [13:0] contextRemover_io_input_rsp_payload_fragment_context; + wire contextRemover_io_output_cmd_valid; + wire contextRemover_io_output_cmd_payload_last; + wire [0:0] contextRemover_io_output_cmd_payload_fragment_opcode; + wire [31:0] contextRemover_io_output_cmd_payload_fragment_address; + wire [11:0] contextRemover_io_output_cmd_payload_fragment_length; + wire [127:0] contextRemover_io_output_cmd_payload_fragment_data; + wire [15:0] contextRemover_io_output_cmd_payload_fragment_mask; + wire contextRemover_io_output_rsp_ready; + wire [8:0] _zz_io_output_aw_payload_len; + wire [12:0] _zz_io_output_aw_payload_len_1; + wire [12:0] _zz_io_output_aw_payload_len_2; + wire [3:0] _zz_io_output_aw_payload_len_3; + wire cmdFork_valid; + reg cmdFork_ready; + wire cmdFork_payload_last; + wire [0:0] cmdFork_payload_fragment_opcode; + wire [31:0] cmdFork_payload_fragment_address; + wire [11:0] cmdFork_payload_fragment_length; + wire [127:0] cmdFork_payload_fragment_data; + wire [15:0] cmdFork_payload_fragment_mask; + wire dataFork_valid; + wire dataFork_ready; + wire dataFork_payload_last; + wire [0:0] dataFork_payload_fragment_opcode; + wire [31:0] dataFork_payload_fragment_address; + wire [11:0] dataFork_payload_fragment_length; + wire [127:0] dataFork_payload_fragment_data; + wire [15:0] dataFork_payload_fragment_mask; + reg contextRemover_io_output_cmd_fork2_logic_linkEnable_0; + reg contextRemover_io_output_cmd_fork2_logic_linkEnable_1; + wire when_Stream_l1063; + wire when_Stream_l1063_1; + wire cmdFork_fire; + wire dataFork_fire; + wire contextRemover_io_output_cmd_fire; + reg contextRemover_io_output_cmd_payload_first; + wire when_Stream_l445; + reg cmdStage_valid; + wire cmdStage_ready; + wire cmdStage_payload_last; + wire [0:0] cmdStage_payload_fragment_opcode; + wire [31:0] cmdStage_payload_fragment_address; + wire [11:0] cmdStage_payload_fragment_length; + wire [127:0] cmdStage_payload_fragment_data; + wire [15:0] cmdStage_payload_fragment_mask; + wire when_BmbToAxi4Bridge_l297; + + assign _zz_io_output_aw_payload_len = _zz_io_output_aw_payload_len_1[12 : 4]; + assign _zz_io_output_aw_payload_len_1 = ({1'b0,cmdStage_payload_fragment_length} + _zz_io_output_aw_payload_len_2); + assign _zz_io_output_aw_payload_len_3 = cmdStage_payload_fragment_address[3 : 0]; + assign _zz_io_output_aw_payload_len_2 = {9'd0, _zz_io_output_aw_payload_len_3}; + EfxDMA_BmbContextRemover_1_a048ca8f51874147a1cd65d43e6523ef contextRemover ( + .io_input_cmd_valid (io_input_cmd_valid ), //i + .io_input_cmd_ready (contextRemover_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (io_input_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (io_input_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (io_input_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (io_input_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_data (io_input_cmd_payload_fragment_data[127:0] ), //i + .io_input_cmd_payload_fragment_mask (io_input_cmd_payload_fragment_mask[15:0] ), //i + .io_input_cmd_payload_fragment_context (io_input_cmd_payload_fragment_context[13:0] ), //i + .io_input_rsp_valid (contextRemover_io_input_rsp_valid ), //o + .io_input_rsp_ready (io_input_rsp_ready ), //i + .io_input_rsp_payload_last (contextRemover_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (contextRemover_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_context (contextRemover_io_input_rsp_payload_fragment_context[13:0] ), //o + .io_output_cmd_valid (contextRemover_io_output_cmd_valid ), //o + .io_output_cmd_ready (contextRemover_io_output_cmd_ready ), //i + .io_output_cmd_payload_last (contextRemover_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (contextRemover_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (contextRemover_io_output_cmd_payload_fragment_address[31:0]), //o + .io_output_cmd_payload_fragment_length (contextRemover_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_cmd_payload_fragment_data (contextRemover_io_output_cmd_payload_fragment_data[127:0] ), //o + .io_output_cmd_payload_fragment_mask (contextRemover_io_output_cmd_payload_fragment_mask[15:0] ), //o + .io_output_rsp_valid (io_output_b_valid ), //i + .io_output_rsp_ready (contextRemover_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (1'b1 ), //i + .io_output_rsp_payload_fragment_opcode (contextRemover_io_output_rsp_payload_fragment_opcode ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign io_input_cmd_ready = contextRemover_io_input_cmd_ready; + assign io_input_rsp_valid = contextRemover_io_input_rsp_valid; + assign io_input_rsp_payload_last = contextRemover_io_input_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = contextRemover_io_input_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_context = contextRemover_io_input_rsp_payload_fragment_context; + always @(*) begin + contextRemover_io_output_cmd_ready = 1'b1; + if(when_Stream_l1063) begin + contextRemover_io_output_cmd_ready = 1'b0; + end + if(when_Stream_l1063_1) begin + contextRemover_io_output_cmd_ready = 1'b0; + end + end + + assign when_Stream_l1063 = ((! cmdFork_ready) && contextRemover_io_output_cmd_fork2_logic_linkEnable_0); + assign when_Stream_l1063_1 = ((! dataFork_ready) && contextRemover_io_output_cmd_fork2_logic_linkEnable_1); + assign cmdFork_valid = (contextRemover_io_output_cmd_valid && contextRemover_io_output_cmd_fork2_logic_linkEnable_0); + assign cmdFork_payload_last = contextRemover_io_output_cmd_payload_last; + assign cmdFork_payload_fragment_opcode = contextRemover_io_output_cmd_payload_fragment_opcode; + assign cmdFork_payload_fragment_address = contextRemover_io_output_cmd_payload_fragment_address; + assign cmdFork_payload_fragment_length = contextRemover_io_output_cmd_payload_fragment_length; + assign cmdFork_payload_fragment_data = contextRemover_io_output_cmd_payload_fragment_data; + assign cmdFork_payload_fragment_mask = contextRemover_io_output_cmd_payload_fragment_mask; + assign cmdFork_fire = (cmdFork_valid && cmdFork_ready); + assign dataFork_valid = (contextRemover_io_output_cmd_valid && contextRemover_io_output_cmd_fork2_logic_linkEnable_1); + assign dataFork_payload_last = contextRemover_io_output_cmd_payload_last; + assign dataFork_payload_fragment_opcode = contextRemover_io_output_cmd_payload_fragment_opcode; + assign dataFork_payload_fragment_address = contextRemover_io_output_cmd_payload_fragment_address; + assign dataFork_payload_fragment_length = contextRemover_io_output_cmd_payload_fragment_length; + assign dataFork_payload_fragment_data = contextRemover_io_output_cmd_payload_fragment_data; + assign dataFork_payload_fragment_mask = contextRemover_io_output_cmd_payload_fragment_mask; + assign dataFork_fire = (dataFork_valid && dataFork_ready); + assign contextRemover_io_output_cmd_fire = (contextRemover_io_output_cmd_valid && contextRemover_io_output_cmd_ready); + assign when_Stream_l445 = (! contextRemover_io_output_cmd_payload_first); + always @(*) begin + cmdStage_valid = cmdFork_valid; + if(when_Stream_l445) begin + cmdStage_valid = 1'b0; + end + end + + always @(*) begin + cmdFork_ready = cmdStage_ready; + if(when_Stream_l445) begin + cmdFork_ready = 1'b1; + end + end + + assign cmdStage_payload_last = cmdFork_payload_last; + assign cmdStage_payload_fragment_opcode = cmdFork_payload_fragment_opcode; + assign cmdStage_payload_fragment_address = cmdFork_payload_fragment_address; + assign cmdStage_payload_fragment_length = cmdFork_payload_fragment_length; + assign cmdStage_payload_fragment_data = cmdFork_payload_fragment_data; + assign cmdStage_payload_fragment_mask = cmdFork_payload_fragment_mask; + assign io_output_aw_valid = cmdStage_valid; + assign cmdStage_ready = io_output_aw_ready; + assign io_output_aw_payload_addr = cmdStage_payload_fragment_address; + assign io_output_aw_payload_len = _zz_io_output_aw_payload_len[7:0]; + assign io_output_aw_payload_size = 3'b100; + assign io_output_aw_payload_prot = 3'b010; + assign io_output_aw_payload_cache = 4'b1111; + assign io_output_w_valid = dataFork_valid; + assign dataFork_ready = io_output_w_ready; + assign io_output_w_payload_data = dataFork_payload_fragment_data; + assign io_output_w_payload_strb = dataFork_payload_fragment_mask; + assign io_output_w_payload_last = dataFork_payload_last; + assign io_output_b_ready = contextRemover_io_output_rsp_ready; + assign when_BmbToAxi4Bridge_l297 = (io_output_b_payload_resp == 2'b00); + always @(*) begin + if(when_BmbToAxi4Bridge_l297) begin + contextRemover_io_output_rsp_payload_fragment_opcode = 1'b0; + end else begin + contextRemover_io_output_rsp_payload_fragment_opcode = 1'b1; + end + end + + always @(posedge clk) begin + if(reset) begin + contextRemover_io_output_cmd_fork2_logic_linkEnable_0 <= 1'b1; + contextRemover_io_output_cmd_fork2_logic_linkEnable_1 <= 1'b1; + contextRemover_io_output_cmd_payload_first <= 1'b1; + end else begin + if(cmdFork_fire) begin + contextRemover_io_output_cmd_fork2_logic_linkEnable_0 <= 1'b0; + end + if(dataFork_fire) begin + contextRemover_io_output_cmd_fork2_logic_linkEnable_1 <= 1'b0; + end + if(contextRemover_io_output_cmd_ready) begin + contextRemover_io_output_cmd_fork2_logic_linkEnable_0 <= 1'b1; + contextRemover_io_output_cmd_fork2_logic_linkEnable_1 <= 1'b1; + end + if(contextRemover_io_output_cmd_fire) begin + contextRemover_io_output_cmd_payload_first <= contextRemover_io_output_cmd_payload_last; + end + end + end + + +endmodule + +module EfxDMA_BmbSourceRemover_1_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_source, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [127:0] io_input_cmd_payload_fragment_data, + input wire [15:0] io_input_cmd_payload_fragment_mask, + input wire [12:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_source, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [12:0] io_input_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + output wire [127:0] io_output_cmd_payload_fragment_data, + output wire [15:0] io_output_cmd_payload_fragment_mask, + output wire [13:0] io_output_cmd_payload_fragment_context, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [13:0] io_output_rsp_payload_fragment_context +); + + wire [0:0] cmdContext_source; + wire [12:0] cmdContext_context; + wire [0:0] rspContext_source; + wire [12:0] rspContext_context; + wire [13:0] _zz_rspContext_source; + + assign cmdContext_source = io_input_cmd_payload_fragment_source; + assign cmdContext_context = io_input_cmd_payload_fragment_context; + assign io_output_cmd_valid = io_input_cmd_valid; + assign io_input_cmd_ready = io_output_cmd_ready; + assign io_output_cmd_payload_last = io_input_cmd_payload_last; + assign io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign io_output_cmd_payload_fragment_context = {cmdContext_context,cmdContext_source}; + assign _zz_rspContext_source = io_output_rsp_payload_fragment_context; + assign rspContext_source = _zz_rspContext_source[0 : 0]; + assign rspContext_context = _zz_rspContext_source[13 : 1]; + assign io_input_rsp_valid = io_output_rsp_valid; + assign io_output_rsp_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = io_output_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_source = rspContext_source; + assign io_input_rsp_payload_fragment_context = rspContext_context; + +endmodule + +module EfxDMA_BmbToAxi4ReadOnlyBridge_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [21:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [127:0] io_input_rsp_payload_fragment_data, + output wire [21:0] io_input_rsp_payload_fragment_context, + output wire io_output_ar_valid, + input wire io_output_ar_ready, + output wire [31:0] io_output_ar_payload_addr, + output wire [7:0] io_output_ar_payload_len, + output wire [2:0] io_output_ar_payload_size, + output wire [3:0] io_output_ar_payload_cache, + output wire [2:0] io_output_ar_payload_prot, + input wire io_output_r_valid, + output wire io_output_r_ready, + input wire [127:0] io_output_r_payload_data, + input wire [1:0] io_output_r_payload_resp, + input wire io_output_r_payload_last, + input wire clk, + input wire reset +); + + reg [0:0] contextRemover_io_output_rsp_payload_fragment_opcode; + wire contextRemover_io_input_cmd_ready; + wire contextRemover_io_input_rsp_valid; + wire contextRemover_io_input_rsp_payload_last; + wire [0:0] contextRemover_io_input_rsp_payload_fragment_opcode; + wire [127:0] contextRemover_io_input_rsp_payload_fragment_data; + wire [21:0] contextRemover_io_input_rsp_payload_fragment_context; + wire contextRemover_io_output_cmd_valid; + wire contextRemover_io_output_cmd_payload_last; + wire [0:0] contextRemover_io_output_cmd_payload_fragment_opcode; + wire [31:0] contextRemover_io_output_cmd_payload_fragment_address; + wire [11:0] contextRemover_io_output_cmd_payload_fragment_length; + wire contextRemover_io_output_rsp_ready; + wire [8:0] _zz_io_output_ar_payload_len; + wire [12:0] _zz_io_output_ar_payload_len_1; + wire [12:0] _zz_io_output_ar_payload_len_2; + wire [3:0] _zz_io_output_ar_payload_len_3; + wire when_BmbToAxi4Bridge_l243; + + assign _zz_io_output_ar_payload_len = _zz_io_output_ar_payload_len_1[12 : 4]; + assign _zz_io_output_ar_payload_len_1 = ({1'b0,contextRemover_io_output_cmd_payload_fragment_length} + _zz_io_output_ar_payload_len_2); + assign _zz_io_output_ar_payload_len_3 = contextRemover_io_output_cmd_payload_fragment_address[3 : 0]; + assign _zz_io_output_ar_payload_len_2 = {9'd0, _zz_io_output_ar_payload_len_3}; + EfxDMA_BmbContextRemover_a048ca8f51874147a1cd65d43e6523ef contextRemover ( + .io_input_cmd_valid (io_input_cmd_valid ), //i + .io_input_cmd_ready (contextRemover_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (io_input_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (io_input_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (io_input_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (io_input_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_context (io_input_cmd_payload_fragment_context[21:0] ), //i + .io_input_rsp_valid (contextRemover_io_input_rsp_valid ), //o + .io_input_rsp_ready (io_input_rsp_ready ), //i + .io_input_rsp_payload_last (contextRemover_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (contextRemover_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (contextRemover_io_input_rsp_payload_fragment_data[127:0] ), //o + .io_input_rsp_payload_fragment_context (contextRemover_io_input_rsp_payload_fragment_context[21:0] ), //o + .io_output_cmd_valid (contextRemover_io_output_cmd_valid ), //o + .io_output_cmd_ready (io_output_ar_ready ), //i + .io_output_cmd_payload_last (contextRemover_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (contextRemover_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (contextRemover_io_output_cmd_payload_fragment_address[31:0]), //o + .io_output_cmd_payload_fragment_length (contextRemover_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_rsp_valid (io_output_r_valid ), //i + .io_output_rsp_ready (contextRemover_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (io_output_r_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (contextRemover_io_output_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (io_output_r_payload_data[127:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign io_input_cmd_ready = contextRemover_io_input_cmd_ready; + assign io_input_rsp_valid = contextRemover_io_input_rsp_valid; + assign io_input_rsp_payload_last = contextRemover_io_input_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = contextRemover_io_input_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = contextRemover_io_input_rsp_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = contextRemover_io_input_rsp_payload_fragment_context; + assign io_output_ar_valid = contextRemover_io_output_cmd_valid; + assign io_output_ar_payload_addr = contextRemover_io_output_cmd_payload_fragment_address; + assign io_output_ar_payload_len = _zz_io_output_ar_payload_len[7:0]; + assign io_output_ar_payload_size = 3'b100; + assign io_output_ar_payload_prot = 3'b010; + assign io_output_ar_payload_cache = 4'b1111; + assign io_output_r_ready = contextRemover_io_output_rsp_ready; + assign when_BmbToAxi4Bridge_l243 = (io_output_r_payload_resp == 2'b00); + always @(*) begin + if(when_BmbToAxi4Bridge_l243) begin + contextRemover_io_output_rsp_payload_fragment_opcode = 1'b0; + end else begin + contextRemover_io_output_rsp_payload_fragment_opcode = 1'b1; + end + end + + +endmodule + +module EfxDMA_BmbSourceRemover_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_source, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [20:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_source, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [127:0] io_input_rsp_payload_fragment_data, + output wire [20:0] io_input_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + output wire [21:0] io_output_cmd_payload_fragment_context, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [127:0] io_output_rsp_payload_fragment_data, + input wire [21:0] io_output_rsp_payload_fragment_context +); + + wire [0:0] cmdContext_source; + wire [20:0] cmdContext_context; + wire [0:0] rspContext_source; + wire [20:0] rspContext_context; + wire [21:0] _zz_rspContext_source; + + assign cmdContext_source = io_input_cmd_payload_fragment_source; + assign cmdContext_context = io_input_cmd_payload_fragment_context; + assign io_output_cmd_valid = io_input_cmd_valid; + assign io_input_cmd_ready = io_output_cmd_ready; + assign io_output_cmd_payload_last = io_input_cmd_payload_last; + assign io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign io_output_cmd_payload_fragment_context = {cmdContext_context,cmdContext_source}; + assign _zz_rspContext_source = io_output_rsp_payload_fragment_context; + assign rspContext_source = _zz_rspContext_source[0 : 0]; + assign rspContext_context = _zz_rspContext_source[21 : 1]; + assign io_input_rsp_valid = io_output_rsp_valid; + assign io_output_rsp_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = io_output_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_input_rsp_payload_fragment_source = rspContext_source; + assign io_input_rsp_payload_fragment_context = rspContext_context; + +endmodule + +module EfxDMA_BufferCC_6_a048ca8f51874147a1cd65d43e6523ef ( + input wire [1:0] io_dataIn, + output wire [1:0] io_dataOut, + input wire ctrl_clk, + input wire ctrl_reset +); + + (* async_reg = "true" *) reg [1:0] buffers_0; + (* async_reg = "true" *) reg [1:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge ctrl_clk) begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + + +endmodule + +module EfxDMA_Apb3CC_a048ca8f51874147a1cd65d43e6523ef ( + input wire [13:0] io_input_PADDR, + input wire [0:0] io_input_PSEL, + input wire io_input_PENABLE, + output wire io_input_PREADY, + input wire io_input_PWRITE, + input wire [31:0] io_input_PWDATA, + output wire [31:0] io_input_PRDATA, + output wire io_input_PSLVERROR, + output wire [13:0] io_output_PADDR, + output reg [0:0] io_output_PSEL, + output reg io_output_PENABLE, + input wire io_output_PREADY, + output wire io_output_PWRITE, + output wire [31:0] io_output_PWDATA, + input wire [31:0] io_output_PRDATA, + input wire io_output_PSLVERROR, + input wire ctrl_clk, + input wire ctrl_reset, + input wire clk, + input wire reset +); + + wire flowCCUnsafeByToggle_io_output_valid; + wire [13:0] flowCCUnsafeByToggle_io_output_payload_PADDR; + wire flowCCUnsafeByToggle_io_output_payload_PWRITE; + wire [31:0] flowCCUnsafeByToggle_io_output_payload_PWDATA; + wire flowCCUnsafeByToggle_1_io_output_valid; + wire [31:0] flowCCUnsafeByToggle_1_io_output_payload_PRDATA; + wire flowCCUnsafeByToggle_1_io_output_payload_PSLVERROR; + wire inputLogic_inputCmd_valid; + wire [13:0] inputLogic_inputCmd_payload_PADDR; + wire inputLogic_inputCmd_payload_PWRITE; + wire [31:0] inputLogic_inputCmd_payload_PWDATA; + wire inputLogic_inputRsp_valid; + wire [31:0] inputLogic_inputRsp_payload_PRDATA; + wire inputLogic_inputRsp_payload_PSLVERROR; + reg inputLogic_state; + wire flowCCUnsafeByToggle_io_output_toStream_valid; + reg flowCCUnsafeByToggle_io_output_toStream_ready; + wire [13:0] flowCCUnsafeByToggle_io_output_toStream_payload_PADDR; + wire flowCCUnsafeByToggle_io_output_toStream_payload_PWRITE; + wire [31:0] flowCCUnsafeByToggle_io_output_toStream_payload_PWDATA; + wire outputLogic_outputCmd_valid; + reg outputLogic_outputCmd_ready; + wire [13:0] outputLogic_outputCmd_payload_PADDR; + wire outputLogic_outputCmd_payload_PWRITE; + wire [31:0] outputLogic_outputCmd_payload_PWDATA; + reg flowCCUnsafeByToggle_io_output_toStream_rValid; + wire flowCCUnsafeByToggle_io_output_toStream_fire; + (* async_reg = "true" *) reg [13:0] flowCCUnsafeByToggle_io_output_toStream_rData_PADDR; + (* async_reg = "true" *) reg flowCCUnsafeByToggle_io_output_toStream_rData_PWRITE; + (* async_reg = "true" *) reg [31:0] flowCCUnsafeByToggle_io_output_toStream_rData_PWDATA; + wire when_Stream_l375; + reg outputLogic_state; + wire when_Apb3CCToggle_l81; + wire outputLogic_outputRsp_valid; + wire [31:0] outputLogic_outputRsp_payload_PRDATA; + wire outputLogic_outputRsp_payload_PSLVERROR; + wire outputLogic_outputCmd_fire; + + EfxDMA_FlowCCUnsafeByToggle_a048ca8f51874147a1cd65d43e6523ef flowCCUnsafeByToggle ( + .io_input_valid (inputLogic_inputCmd_valid ), //i + .io_input_payload_PADDR (inputLogic_inputCmd_payload_PADDR[13:0] ), //i + .io_input_payload_PWRITE (inputLogic_inputCmd_payload_PWRITE ), //i + .io_input_payload_PWDATA (inputLogic_inputCmd_payload_PWDATA[31:0] ), //i + .io_output_valid (flowCCUnsafeByToggle_io_output_valid ), //o + .io_output_payload_PADDR (flowCCUnsafeByToggle_io_output_payload_PADDR[13:0] ), //o + .io_output_payload_PWRITE (flowCCUnsafeByToggle_io_output_payload_PWRITE ), //o + .io_output_payload_PWDATA (flowCCUnsafeByToggle_io_output_payload_PWDATA[31:0]), //o + .ctrl_clk (ctrl_clk ), //i + .ctrl_reset (ctrl_reset ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_FlowCCUnsafeByToggle_1_a048ca8f51874147a1cd65d43e6523ef flowCCUnsafeByToggle_1 ( + .io_input_valid (outputLogic_outputRsp_valid ), //i + .io_input_payload_PRDATA (outputLogic_outputRsp_payload_PRDATA[31:0] ), //i + .io_input_payload_PSLVERROR (outputLogic_outputRsp_payload_PSLVERROR ), //i + .io_output_valid (flowCCUnsafeByToggle_1_io_output_valid ), //o + .io_output_payload_PRDATA (flowCCUnsafeByToggle_1_io_output_payload_PRDATA[31:0]), //o + .io_output_payload_PSLVERROR (flowCCUnsafeByToggle_1_io_output_payload_PSLVERROR ), //o + .clk (clk ), //i + .reset (reset ), //i + .ctrl_clk (ctrl_clk ), //i + .ctrl_reset (ctrl_reset ) //i + ); + assign inputLogic_inputCmd_valid = ((io_input_PSEL[0] && io_input_PENABLE) && (! inputLogic_state)); + assign inputLogic_inputCmd_payload_PADDR = io_input_PADDR; + assign inputLogic_inputCmd_payload_PWRITE = io_input_PWRITE; + assign inputLogic_inputCmd_payload_PWDATA = io_input_PWDATA; + assign io_input_PREADY = inputLogic_inputRsp_valid; + assign io_input_PRDATA = inputLogic_inputRsp_payload_PRDATA; + assign io_input_PSLVERROR = inputLogic_inputRsp_payload_PSLVERROR; + assign flowCCUnsafeByToggle_io_output_toStream_valid = flowCCUnsafeByToggle_io_output_valid; + assign flowCCUnsafeByToggle_io_output_toStream_payload_PADDR = flowCCUnsafeByToggle_io_output_payload_PADDR; + assign flowCCUnsafeByToggle_io_output_toStream_payload_PWRITE = flowCCUnsafeByToggle_io_output_payload_PWRITE; + assign flowCCUnsafeByToggle_io_output_toStream_payload_PWDATA = flowCCUnsafeByToggle_io_output_payload_PWDATA; + assign flowCCUnsafeByToggle_io_output_toStream_fire = (flowCCUnsafeByToggle_io_output_toStream_valid && flowCCUnsafeByToggle_io_output_toStream_ready); + always @(*) begin + flowCCUnsafeByToggle_io_output_toStream_ready = outputLogic_outputCmd_ready; + if(when_Stream_l375) begin + flowCCUnsafeByToggle_io_output_toStream_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! outputLogic_outputCmd_valid); + assign outputLogic_outputCmd_valid = flowCCUnsafeByToggle_io_output_toStream_rValid; + assign outputLogic_outputCmd_payload_PADDR = flowCCUnsafeByToggle_io_output_toStream_rData_PADDR; + assign outputLogic_outputCmd_payload_PWRITE = flowCCUnsafeByToggle_io_output_toStream_rData_PWRITE; + assign outputLogic_outputCmd_payload_PWDATA = flowCCUnsafeByToggle_io_output_toStream_rData_PWDATA; + always @(*) begin + io_output_PENABLE = 1'b0; + if(outputLogic_outputCmd_valid) begin + if(when_Apb3CCToggle_l81) begin + io_output_PENABLE = 1'b0; + end else begin + io_output_PENABLE = 1'b1; + end + end + end + + always @(*) begin + io_output_PSEL = 1'b0; + if(outputLogic_outputCmd_valid) begin + io_output_PSEL = 1'b1; + end + end + + assign io_output_PADDR = outputLogic_outputCmd_payload_PADDR; + assign io_output_PWDATA = outputLogic_outputCmd_payload_PWDATA; + assign io_output_PWRITE = outputLogic_outputCmd_payload_PWRITE; + always @(*) begin + outputLogic_outputCmd_ready = 1'b0; + if(outputLogic_outputCmd_valid) begin + if(!when_Apb3CCToggle_l81) begin + if(io_output_PREADY) begin + outputLogic_outputCmd_ready = 1'b1; + end + end + end + end + + assign when_Apb3CCToggle_l81 = (! outputLogic_state); + assign outputLogic_outputCmd_fire = (outputLogic_outputCmd_valid && outputLogic_outputCmd_ready); + assign outputLogic_outputRsp_valid = outputLogic_outputCmd_fire; + assign outputLogic_outputRsp_payload_PRDATA = io_output_PRDATA; + assign outputLogic_outputRsp_payload_PSLVERROR = io_output_PSLVERROR; + assign inputLogic_inputRsp_valid = flowCCUnsafeByToggle_1_io_output_valid; + assign inputLogic_inputRsp_payload_PRDATA = flowCCUnsafeByToggle_1_io_output_payload_PRDATA; + assign inputLogic_inputRsp_payload_PSLVERROR = flowCCUnsafeByToggle_1_io_output_payload_PSLVERROR; + always @(posedge ctrl_clk) begin + if(ctrl_reset) begin + inputLogic_state <= 1'b0; + end else begin + if(inputLogic_inputCmd_valid) begin + inputLogic_state <= 1'b1; + end + if(inputLogic_inputRsp_valid) begin + inputLogic_state <= 1'b0; + end + end + end + + always @(posedge clk) begin + if(reset) begin + flowCCUnsafeByToggle_io_output_toStream_rValid <= 1'b0; + outputLogic_state <= 1'b0; + end else begin + if(flowCCUnsafeByToggle_io_output_toStream_ready) begin + flowCCUnsafeByToggle_io_output_toStream_rValid <= flowCCUnsafeByToggle_io_output_toStream_valid; + end + if(outputLogic_outputCmd_valid) begin + if(when_Apb3CCToggle_l81) begin + outputLogic_state <= 1'b1; + end else begin + if(io_output_PREADY) begin + outputLogic_state <= 1'b0; + end + end + end + end + end + + always @(posedge clk) begin + if(flowCCUnsafeByToggle_io_output_toStream_fire) begin + flowCCUnsafeByToggle_io_output_toStream_rData_PADDR <= flowCCUnsafeByToggle_io_output_toStream_payload_PADDR; + flowCCUnsafeByToggle_io_output_toStream_rData_PWRITE <= flowCCUnsafeByToggle_io_output_toStream_payload_PWRITE; + flowCCUnsafeByToggle_io_output_toStream_rData_PWDATA <= flowCCUnsafeByToggle_io_output_toStream_payload_PWDATA; + end + end + + +endmodule + +module EfxDMA_Core_a048ca8f51874147a1cd65d43e6523ef ( + output wire io_sgRead_cmd_valid, + input wire io_sgRead_cmd_ready, + output wire io_sgRead_cmd_payload_last, + output wire [0:0] io_sgRead_cmd_payload_fragment_opcode, + output wire [31:0] io_sgRead_cmd_payload_fragment_address, + output wire [4:0] io_sgRead_cmd_payload_fragment_length, + output wire [0:0] io_sgRead_cmd_payload_fragment_context, + input wire io_sgRead_rsp_valid, + output wire io_sgRead_rsp_ready, + input wire io_sgRead_rsp_payload_last, + input wire [0:0] io_sgRead_rsp_payload_fragment_opcode, + input wire [127:0] io_sgRead_rsp_payload_fragment_data, + input wire [0:0] io_sgRead_rsp_payload_fragment_context, + output wire io_sgWrite_cmd_valid, + input wire io_sgWrite_cmd_ready, + output wire io_sgWrite_cmd_payload_last, + output wire [0:0] io_sgWrite_cmd_payload_fragment_opcode, + output wire [31:0] io_sgWrite_cmd_payload_fragment_address, + output wire [1:0] io_sgWrite_cmd_payload_fragment_length, + output reg [127:0] io_sgWrite_cmd_payload_fragment_data, + output reg [15:0] io_sgWrite_cmd_payload_fragment_mask, + output wire [0:0] io_sgWrite_cmd_payload_fragment_context, + input wire io_sgWrite_rsp_valid, + output wire io_sgWrite_rsp_ready, + input wire io_sgWrite_rsp_payload_last, + input wire [0:0] io_sgWrite_rsp_payload_fragment_opcode, + input wire [0:0] io_sgWrite_rsp_payload_fragment_context, + output reg io_read_cmd_valid, + input wire io_read_cmd_ready, + output wire io_read_cmd_payload_last, + output wire [0:0] io_read_cmd_payload_fragment_opcode, + output wire [31:0] io_read_cmd_payload_fragment_address, + output wire [11:0] io_read_cmd_payload_fragment_length, + output wire [20:0] io_read_cmd_payload_fragment_context, + input wire io_read_rsp_valid, + output wire io_read_rsp_ready, + input wire io_read_rsp_payload_last, + input wire [0:0] io_read_rsp_payload_fragment_opcode, + input wire [127:0] io_read_rsp_payload_fragment_data, + input wire [20:0] io_read_rsp_payload_fragment_context, + output wire io_write_cmd_valid, + input wire io_write_cmd_ready, + output wire io_write_cmd_payload_last, + output wire [0:0] io_write_cmd_payload_fragment_opcode, + output wire [31:0] io_write_cmd_payload_fragment_address, + output wire [11:0] io_write_cmd_payload_fragment_length, + output wire [127:0] io_write_cmd_payload_fragment_data, + output wire [15:0] io_write_cmd_payload_fragment_mask, + output wire [12:0] io_write_cmd_payload_fragment_context, + input wire io_write_rsp_valid, + output wire io_write_rsp_ready, + input wire io_write_rsp_payload_last, + input wire [0:0] io_write_rsp_payload_fragment_opcode, + input wire [12:0] io_write_rsp_payload_fragment_context, + output wire io_outputs_0_valid, + input wire io_outputs_0_ready, + output wire [63:0] io_outputs_0_payload_data, + output wire [7:0] io_outputs_0_payload_mask, + output wire [3:0] io_outputs_0_payload_sink, + output wire io_outputs_0_payload_last, + input wire io_inputs_0_valid, + output reg io_inputs_0_ready, + input wire [63:0] io_inputs_0_payload_data, + input wire [7:0] io_inputs_0_payload_mask, + input wire [3:0] io_inputs_0_payload_sink, + input wire io_inputs_0_payload_last, + output reg [1:0] io_interrupts, + input wire [13:0] io_ctrl_PADDR, + input wire [0:0] io_ctrl_PSEL, + input wire io_ctrl_PENABLE, + output wire io_ctrl_PREADY, + input wire io_ctrl_PWRITE, + input wire [31:0] io_ctrl_PWDATA, + output reg [31:0] io_ctrl_PRDATA, + output wire io_ctrl_PSLVERROR, + output wire ll_0_descriptorUpdate, + output wire ll_1_descriptorUpdate, + input wire clk, + input wire reset +); + + wire [9:0] memory_core_io_writes_0_cmd_payload_address; + wire [6:0] memory_core_io_writes_0_cmd_payload_context; + wire [9:0] memory_core_io_writes_1_cmd_payload_address; + reg [15:0] memory_core_io_writes_1_cmd_payload_mask; + wire [6:0] memory_core_io_writes_1_cmd_payload_context; + wire memory_core_io_reads_0_cmd_valid; + wire [9:0] memory_core_io_reads_0_cmd_payload_address; + wire [2:0] memory_core_io_reads_0_cmd_payload_context; + wire [9:0] memory_core_io_reads_1_cmd_payload_address; + wire [11:0] memory_core_io_reads_1_cmd_payload_context; + wire [15:0] b2m_fsm_aggregate_engine_io_input_payload_mask; + wire b2m_fsm_aggregate_engine_io_flush; + wire [3:0] b2m_fsm_aggregate_engine_io_offset; + wire memory_core_io_writes_0_cmd_ready; + wire memory_core_io_writes_0_rsp_valid; + wire [6:0] memory_core_io_writes_0_rsp_payload_context; + wire memory_core_io_writes_1_cmd_ready; + wire memory_core_io_writes_1_rsp_valid; + wire [6:0] memory_core_io_writes_1_rsp_payload_context; + wire memory_core_io_reads_0_cmd_ready; + wire memory_core_io_reads_0_rsp_valid; + wire [63:0] memory_core_io_reads_0_rsp_payload_data; + wire [7:0] memory_core_io_reads_0_rsp_payload_mask; + wire [2:0] memory_core_io_reads_0_rsp_payload_context; + wire memory_core_io_reads_1_cmd_ready; + wire memory_core_io_reads_1_rsp_valid; + wire [127:0] memory_core_io_reads_1_rsp_payload_data; + wire [15:0] memory_core_io_reads_1_rsp_payload_mask; + wire [11:0] memory_core_io_reads_1_rsp_payload_context; + wire b2m_fsm_aggregate_engine_io_input_ready; + wire [127:0] b2m_fsm_aggregate_engine_io_output_data; + wire [15:0] b2m_fsm_aggregate_engine_io_output_mask; + wire b2m_fsm_aggregate_engine_io_output_consumed; + wire [3:0] b2m_fsm_aggregate_engine_io_output_usedUntil; + wire [26:0] _zz_channels_0_bytesProbe_value; + wire [26:0] _zz_channels_0_bytesProbe_value_1; + wire [13:0] _zz_channels_0_fifo_pop_withOverride_backupNext; + wire [13:0] _zz_channels_0_fifo_pop_withOverride_exposed; + wire [26:0] _zz_channels_0_pop_b2m_selfFlush; + wire [13:0] _zz_channels_0_pop_b2m_request; + wire [10:0] _zz_channels_0_pop_b2m_request_1; + wire [9:0] _zz_channels_0_pop_b2m_request_2; + wire [3:0] _zz_channels_0_pop_b2m_memPending; + wire [3:0] _zz_channels_0_pop_b2m_memPending_1; + wire [0:0] _zz_channels_0_pop_b2m_memPending_2; + wire [3:0] _zz_channels_0_pop_b2m_memPending_3; + wire [0:0] _zz_channels_0_pop_b2m_memPending_4; + wire [10:0] _zz_channels_0_fifo_push_available; + wire [26:0] _zz_channels_1_bytesProbe_value; + wire [26:0] _zz_channels_1_bytesProbe_value_1; + wire [13:0] _zz_channels_1_fifo_pop_withoutOverride_exposed; + wire [3:0] _zz_channels_1_push_m2b_memPending; + wire [3:0] _zz_channels_1_push_m2b_memPending_1; + wire [0:0] _zz_channels_1_push_m2b_memPending_2; + wire [3:0] _zz_channels_1_push_m2b_memPending_3; + wire [0:0] _zz_channels_1_push_m2b_memPending_4; + wire [10:0] _zz_channels_1_push_m2b_loadRequest; + wire [8:0] _zz_channels_1_push_m2b_loadRequest_1; + wire [25:0] _zz_when_DmaSg_l486; + wire [10:0] _zz_channels_1_fifo_push_available; + wire [0:0] _zz_s2b_0_cmd_firsts; + wire [4:0] _zz_s2b_0_cmd_firsts_1; + wire [3:0] _zz_s2b_0_cmd_byteCount_8; + reg [3:0] _zz_s2b_0_cmd_byteCount_9; + wire [2:0] _zz_s2b_0_cmd_byteCount_10; + reg [3:0] _zz_s2b_0_cmd_byteCount_11; + wire [2:0] _zz_s2b_0_cmd_byteCount_12; + reg [3:0] _zz_s2b_0_cmd_byteCount_13; + wire [2:0] _zz_s2b_0_cmd_byteCount_14; + wire [1:0] _zz_s2b_0_cmd_byteCount_15; + wire [1:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2; + wire [1:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2_1; + wire [0:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2_2; + reg [0:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3; + wire [25:0] _zz_m2b_cmd_s0_length; + wire [25:0] _zz_m2b_cmd_s0_length_1; + wire [25:0] _zz_m2b_cmd_s0_length_2; + wire [25:0] _zz_m2b_cmd_s0_lastBurst; + wire [31:0] _zz_m2b_cmd_s1_context_stop; + wire [31:0] _zz_m2b_cmd_s1_context_stop_1; + wire [31:0] _zz_m2b_cmd_s1_addressNext; + wire [31:0] _zz_m2b_cmd_s1_addressNext_1; + wire [25:0] _zz_m2b_cmd_s1_byteLeftNext; + wire [25:0] _zz_m2b_cmd_s1_byteLeftNext_1; + wire [12:0] _zz_m2b_cmd_s1_fifoPushDecr; + wire [11:0] _zz_m2b_cmd_s1_fifoPushDecr_1; + wire [11:0] _zz_m2b_cmd_s1_fifoPushDecr_2; + wire [3:0] _zz_m2b_cmd_s1_fifoPushDecr_3; + wire [12:0] _zz_m2b_cmd_s1_fifoPushDecr_4; + wire [1:0] _zz_m2b_cmd_s1_fifoPushDecr_5; + wire [1:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2; + wire [1:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_1; + wire [0:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_2; + reg [0:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3; + wire [0:0] _zz_when; + wire [12:0] _zz_b2m_fsm_bytesInBurstP1; + wire [1:0] _zz_b2m_fsm_bytesInBurstP1_1; + wire [31:0] _zz_b2m_fsm_addressNext; + wire [26:0] _zz_b2m_fsm_bytesLeftNext; + wire [13:0] _zz_b2m_fsm_bytesLeftNext_1; + wire [25:0] _zz__zz_b2m_fsm_sel_bytesInBurst_1; + wire [25:0] _zz__zz_b2m_fsm_sel_bytesInBurst_1_1; + wire [11:0] _zz__zz_b2m_fsm_sel_bytesInBurst_2; + wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_3; + wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_4; + wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_5; + wire [13:0] _zz_b2m_fsm_fifoCompletion; + wire [13:0] _zz_b2m_fsm_fifoCompletion_1; + wire [11:0] _zz_b2m_fsm_beatCounter; + wire [11:0] _zz_b2m_fsm_beatCounter_1; + wire [3:0] _zz_b2m_fsm_beatCounter_2; + wire [10:0] _zz_b2m_fsm_sel_ptr; + wire [3:0] _zz_b2m_fsm_aggregate_bytesToSkipMask; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_1; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_2; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_3; + wire [0:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_4; + wire [9:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_5; + wire [3:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_6; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_7; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_8; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_9; + wire [0:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_10; + wire [3:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_11; + wire [3:0] _zz_b2m_fsm_cmd_maskLastTriggerComb; + wire [3:0] _zz_b2m_fsm_cmd_maskLast; + wire _zz_b2m_fsm_cmd_maskLast_1; + wire [0:0] _zz_b2m_fsm_cmd_maskLast_2; + wire [7:0] _zz_b2m_fsm_cmd_maskLast_3; + wire [3:0] _zz_b2m_fsm_cmd_maskLast_4; + wire [3:0] _zz_b2m_fsm_cmd_maskLast_5; + wire [3:0] _zz_b2m_fsm_cmd_maskFirst; + wire _zz_b2m_fsm_cmd_maskFirst_1; + wire [0:0] _zz_b2m_fsm_cmd_maskFirst_2; + wire [7:0] _zz_b2m_fsm_cmd_maskFirst_3; + wire [3:0] _zz_b2m_fsm_cmd_maskFirst_4; + wire [3:0] _zz_b2m_fsm_cmd_maskFirst_5; + wire [0:0] _zz_when_1; + wire [0:0] _zz_when_2; + wire [1:0] _zz__zz_ll_arbiter_head_1; + wire [1:0] _zz__zz_ll_arbiter_head_1_1; + wire [1:0] _zz_ll_arbiter_head_2; + wire [1:0] _zz_ll_arbiter_isJustASink; + wire [1:0] _zz_ll_arbiter_doDescriptorStall; + wire [1:0] _zz_ll_arbiter_onSgStream; + wire [1:0] _zz_ll_cmd_ptr; + wire [1:0] _zz_ll_cmd_ptrNext; + wire [1:0] _zz_ll_cmd_endOfPacket; + wire [0:0] _zz_channels_0_channelStart; + wire [0:0] _zz_channels_0_ctrl_kick; + wire [0:0] _zz_channels_0_channelStart_1; + wire [0:0] _zz_channels_0_ll_sgStart; + wire [0:0] _zz_channels_0_interrupts_completion_valid; + wire [0:0] _zz_channels_0_interrupts_onChannelCompletion_valid; + wire [0:0] _zz_channels_0_interrupts_onLinkedListUpdate_valid; + wire [0:0] _zz_channels_0_interrupts_s2mPacket_valid; + wire [0:0] _zz_channels_1_channelStart; + wire [0:0] _zz_channels_1_ctrl_kick; + wire [0:0] _zz_channels_1_channelStart_1; + wire [0:0] _zz_channels_1_ll_sgStart; + wire [0:0] _zz_channels_1_interrupts_completion_valid; + wire [0:0] _zz_channels_1_interrupts_onChannelCompletion_valid; + wire [0:0] _zz_channels_1_interrupts_onLinkedListUpdate_valid; + wire [31:0] _zz_io_ctrl_PRDATA; + wire [31:0] _zz_io_ctrl_PRDATA_1; + wire [10:0] _zz_channels_0_fifo_push_ptrIncr_value; + wire [0:0] _zz_channels_0_fifo_push_ptrIncr_value_1; + wire [13:0] _zz_channels_0_fifo_pop_bytesIncr_value_1; + wire [3:0] _zz_channels_0_fifo_pop_bytesIncr_value_2; + wire [10:0] _zz_channels_0_fifo_pop_ptrIncr_value; + wire [1:0] _zz_channels_0_fifo_pop_ptrIncr_value_1; + wire [10:0] _zz_channels_1_fifo_push_ptrIncr_value_1; + wire [1:0] _zz_channels_1_fifo_push_ptrIncr_value_2; + wire [13:0] _zz_channels_1_fifo_pop_bytesIncr_value_1; + wire [4:0] _zz_channels_1_fifo_pop_bytesIncr_value_2; + wire [4:0] _zz_channels_1_fifo_pop_bytesIncr_value_3; + wire [10:0] _zz_channels_1_fifo_pop_ptrIncr_value; + wire [0:0] _zz_channels_1_fifo_pop_ptrIncr_value_1; + wire ctrl_readErrorFlag; + wire ctrl_writeErrorFlag; + wire ctrl_askWrite; + wire ctrl_askRead; + wire ctrl_doWrite; + wire ctrl_doRead; + reg channels_0_channelStart; + reg channels_0_channelStop; + reg channels_0_channelCompletion; + reg channels_0_channelValid; + reg channels_0_descriptorStart; + reg channels_0_descriptorCompletion; + reg channels_0_descriptorValid; + reg [25:0] channels_0_bytes; + reg [1:0] channels_0_priority; + reg [1:0] channels_0_weight; + reg channels_0_readyToStop; + reg [26:0] channels_0_bytesProbe_value; + reg channels_0_bytesProbe_incr_valid; + reg [11:0] channels_0_bytesProbe_incr_payload; + reg channels_0_ctrl_kick; + reg channels_0_ll_sgStart; + reg channels_0_ll_valid; + reg channels_0_ll_onSgStream; + reg channels_0_ll_head; + reg channels_0_ll_justASync; + reg channels_0_ll_waitDone; + reg channels_0_ll_readDone; + reg channels_0_ll_writeDone; + reg channels_0_ll_gotDescriptorStall; + reg channels_0_ll_controlNoCompletion; + reg channels_0_ll_packet; + reg channels_0_ll_requireSync; + reg [31:0] channels_0_ll_ptr; + reg [31:0] channels_0_ll_ptrNext; + wire channels_0_ll_requestLl; + reg channels_0_ll_descriptorUpdated; + wire when_DmaSg_l318; + wire when_DmaSg_l320; + wire when_DmaSg_l322; + wire when_DmaSg_l328; + wire [10:0] channels_0_fifo_base; + wire [10:0] channels_0_fifo_words; + reg [10:0] channels_0_fifo_push_available; + wire [10:0] channels_0_fifo_push_availableDecr; + reg [10:0] channels_0_fifo_push_ptr; + wire [10:0] channels_0_fifo_push_ptrWithBase; + wire [10:0] channels_0_fifo_push_ptrIncr_value; + reg [10:0] channels_0_fifo_pop_ptr; + wire [13:0] channels_0_fifo_pop_bytes; + wire [10:0] channels_0_fifo_pop_ptrWithBase; + wire [13:0] channels_0_fifo_pop_bytesIncr_value; + wire [13:0] channels_0_fifo_pop_bytesDecr_value; + wire channels_0_fifo_pop_empty; + wire [10:0] channels_0_fifo_pop_ptrIncr_value; + reg [13:0] channels_0_fifo_pop_withOverride_backup; + wire [13:0] channels_0_fifo_pop_withOverride_backupNext; + reg channels_0_fifo_pop_withOverride_load; + reg channels_0_fifo_pop_withOverride_unload; + reg [13:0] channels_0_fifo_pop_withOverride_exposed; + reg channels_0_fifo_pop_withOverride_valid; + wire when_DmaSg_l409; + wire channels_0_fifo_empty; + reg channels_0_push_memory; + reg channels_0_push_s2b_completionOnLast; + reg channels_0_push_s2b_packetEvent; + reg channels_0_push_s2b_packetLock; + reg channels_0_push_s2b_waitFirst; + wire when_DmaSg_l457; + reg channels_0_pop_memory; + wire [11:0] channels_0_pop_b2m_bytePerBurst; + reg channels_0_pop_b2m_fire; + reg channels_0_pop_b2m_waitFinalRsp; + reg channels_0_pop_b2m_flush; + reg channels_0_pop_b2m_packetSync; + reg channels_0_pop_b2m_packet; + wire when_DmaSg_l505; + reg channels_0_pop_b2m_memRsp; + reg [3:0] channels_0_pop_b2m_memPending; + reg [31:0] channels_0_pop_b2m_address; + reg [26:0] channels_0_pop_b2m_bytesLeft; + wire channels_0_pop_b2m_selfFlush; + wire channels_0_pop_b2m_request; + reg [3:0] channels_0_pop_b2m_bytesToSkip; + reg [13:0] channels_0_pop_b2m_decrBytes; + reg channels_0_pop_b2m_memPendingInc; + wire when_DmaSg_l523; + wire when_DmaSg_l532; + wire when_DmaSg_l536; + wire when_DmaSg_l547; + wire when_DmaSg_l563; + wire channels_0_readyForChannelCompletion; + wire when_DmaSg_l575; + reg _zz_when_DmaSg_l593; + wire when_DmaSg_l593; + wire channels_0_s2b_full; + reg [10:0] channels_0_fifo_pop_ptrIncr_value_regNext; + wire when_DmaSg_l255; + reg channels_0_interrupts_completion_enable; + reg channels_0_interrupts_completion_valid; + wire when_DmaSg_l255_1; + wire when_DmaSg_l255_2; + reg channels_0_interrupts_onChannelCompletion_enable; + reg channels_0_interrupts_onChannelCompletion_valid; + wire when_DmaSg_l255_3; + reg channels_0_interrupts_onLinkedListUpdate_enable; + reg channels_0_interrupts_onLinkedListUpdate_valid; + wire when_DmaSg_l255_4; + reg channels_0_interrupts_s2mPacket_enable; + reg channels_0_interrupts_s2mPacket_valid; + wire when_DmaSg_l255_5; + wire when_DmaSg_l625; + reg channels_1_channelStart; + reg channels_1_channelStop; + reg channels_1_channelCompletion; + reg channels_1_channelValid; + reg channels_1_descriptorStart; + reg channels_1_descriptorCompletion; + reg channels_1_descriptorValid; + reg [25:0] channels_1_bytes; + reg [1:0] channels_1_priority; + reg [1:0] channels_1_weight; + reg channels_1_readyToStop; + reg [26:0] channels_1_bytesProbe_value; + reg channels_1_bytesProbe_incr_valid; + reg [11:0] channels_1_bytesProbe_incr_payload; + reg channels_1_ctrl_kick; + reg channels_1_ll_sgStart; + reg channels_1_ll_valid; + reg channels_1_ll_onSgStream; + reg channels_1_ll_head; + reg channels_1_ll_justASync; + reg channels_1_ll_waitDone; + reg channels_1_ll_readDone; + reg channels_1_ll_writeDone; + reg channels_1_ll_gotDescriptorStall; + reg channels_1_ll_controlNoCompletion; + reg channels_1_ll_packet; + reg channels_1_ll_requireSync; + reg [31:0] channels_1_ll_ptr; + reg [31:0] channels_1_ll_ptrNext; + wire channels_1_ll_requestLl; + reg channels_1_ll_descriptorUpdated; + wire when_DmaSg_l318_1; + wire when_DmaSg_l320_1; + wire when_DmaSg_l322_1; + wire when_DmaSg_l328_1; + wire [10:0] channels_1_fifo_base; + wire [10:0] channels_1_fifo_words; + reg [10:0] channels_1_fifo_push_available; + reg [10:0] channels_1_fifo_push_availableDecr; + reg [10:0] channels_1_fifo_push_ptr; + wire [10:0] channels_1_fifo_push_ptrWithBase; + wire [10:0] channels_1_fifo_push_ptrIncr_value; + reg [10:0] channels_1_fifo_pop_ptr; + wire [13:0] channels_1_fifo_pop_bytes; + wire [10:0] channels_1_fifo_pop_ptrWithBase; + wire [13:0] channels_1_fifo_pop_bytesIncr_value; + wire [13:0] channels_1_fifo_pop_bytesDecr_value; + wire channels_1_fifo_pop_empty; + wire [10:0] channels_1_fifo_pop_ptrIncr_value; + reg [13:0] channels_1_fifo_pop_withoutOverride_exposed; + wire channels_1_fifo_empty; + reg channels_1_push_memory; + reg [31:0] channels_1_push_m2b_address; + wire [11:0] channels_1_push_m2b_bytePerBurst; + reg channels_1_push_m2b_loadDone; + reg [25:0] channels_1_push_m2b_bytesLeft; + reg [3:0] channels_1_push_m2b_memPending; + reg channels_1_push_m2b_memPendingIncr; + reg channels_1_push_m2b_memPendingDecr; + reg channels_1_push_m2b_loadRequest; + reg channels_1_pop_memory; + reg channels_1_pop_b2s_last; + reg [3:0] channels_1_pop_b2s_sinkId; + reg channels_1_pop_b2s_veryLastTrigger; + reg channels_1_pop_b2s_veryLastValid; + wire when_DmaSg_l474; + reg [10:0] channels_1_pop_b2s_veryLastPtr; + reg channels_1_pop_b2s_veryLastEndPacket; + wire when_DmaSg_l483; + wire when_DmaSg_l486; + wire when_DmaSg_l562; + reg channels_1_readyForChannelCompletion; + wire when_DmaSg_l566; + wire when_DmaSg_l575_1; + reg _zz_when_DmaSg_l593_1; + wire when_DmaSg_l593_1; + wire channels_1_s2b_full; + reg [10:0] channels_1_fifo_pop_ptrIncr_value_regNext; + wire when_DmaSg_l255_6; + reg channels_1_interrupts_completion_enable; + reg channels_1_interrupts_completion_valid; + wire when_DmaSg_l255_7; + wire when_DmaSg_l255_8; + reg channels_1_interrupts_onChannelCompletion_enable; + reg channels_1_interrupts_onChannelCompletion_valid; + wire when_DmaSg_l255_9; + reg channels_1_interrupts_onLinkedListUpdate_enable; + reg channels_1_interrupts_onLinkedListUpdate_valid; + wire when_DmaSg_l255_10; + wire when_DmaSg_l625_1; + wire io_inputs_0_fire; + wire when_package_l12; + reg io_inputs_0_payload_last_regNextWhen; + wire when_package_l12_1; + reg io_inputs_0_payload_last_regNextWhen_1; + wire when_package_l12_2; + reg io_inputs_0_payload_last_regNextWhen_2; + wire when_package_l12_3; + reg io_inputs_0_payload_last_regNextWhen_3; + wire when_package_l12_4; + reg io_inputs_0_payload_last_regNextWhen_4; + wire when_package_l12_5; + reg io_inputs_0_payload_last_regNextWhen_5; + wire when_package_l12_6; + reg io_inputs_0_payload_last_regNextWhen_6; + wire when_package_l12_7; + reg io_inputs_0_payload_last_regNextWhen_7; + wire when_package_l12_8; + reg io_inputs_0_payload_last_regNextWhen_8; + wire when_package_l12_9; + reg io_inputs_0_payload_last_regNextWhen_9; + wire when_package_l12_10; + reg io_inputs_0_payload_last_regNextWhen_10; + wire when_package_l12_11; + reg io_inputs_0_payload_last_regNextWhen_11; + wire when_package_l12_12; + reg io_inputs_0_payload_last_regNextWhen_12; + wire when_package_l12_13; + reg io_inputs_0_payload_last_regNextWhen_13; + wire when_package_l12_14; + reg io_inputs_0_payload_last_regNextWhen_14; + wire when_package_l12_15; + reg io_inputs_0_payload_last_regNextWhen_15; + wire [15:0] s2b_0_cmd_firsts; + wire s2b_0_cmd_first; + wire [0:0] s2b_0_cmd_channelsOh; + wire s2b_0_cmd_noHit; + wire [0:0] s2b_0_cmd_channelsFull; + reg io_inputs_0_thrown_valid; + wire io_inputs_0_thrown_ready; + wire [63:0] io_inputs_0_thrown_payload_data; + wire [7:0] io_inputs_0_thrown_payload_mask; + wire [3:0] io_inputs_0_thrown_payload_sink; + wire io_inputs_0_thrown_payload_last; + wire _zz_io_inputs_0_thrown_ready; + wire s2b_0_cmd_sinkHalted_valid; + wire s2b_0_cmd_sinkHalted_ready; + wire [63:0] s2b_0_cmd_sinkHalted_payload_data; + wire [7:0] s2b_0_cmd_sinkHalted_payload_mask; + wire [3:0] s2b_0_cmd_sinkHalted_payload_sink; + wire s2b_0_cmd_sinkHalted_payload_last; + wire [3:0] _zz_s2b_0_cmd_byteCount; + wire [3:0] _zz_s2b_0_cmd_byteCount_1; + wire [3:0] _zz_s2b_0_cmd_byteCount_2; + wire [3:0] _zz_s2b_0_cmd_byteCount_3; + wire [3:0] _zz_s2b_0_cmd_byteCount_4; + wire [3:0] _zz_s2b_0_cmd_byteCount_5; + wire [3:0] _zz_s2b_0_cmd_byteCount_6; + wire [3:0] _zz_s2b_0_cmd_byteCount_7; + wire [3:0] s2b_0_cmd_byteCount; + wire [0:0] s2b_0_cmd_context_channel; + wire [3:0] s2b_0_cmd_context_bytes; + wire s2b_0_cmd_context_flush; + wire s2b_0_cmd_context_packet; + wire memory_core_io_writes_0_cmd_fire; + wire when_DmaSg_l665; + wire [0:0] s2b_0_rsp_context_channel; + wire [3:0] s2b_0_rsp_context_bytes; + wire s2b_0_rsp_context_flush; + wire s2b_0_rsp_context_packet; + wire [6:0] _zz_s2b_0_rsp_context_channel; + wire _zz_channels_0_fifo_pop_bytesIncr_value; + wire when_DmaSg_l679; + wire when_DmaSg_l681; + wire when_DmaSg_l682; + wire [0:0] b2s_0_cmd_channelsOh; + wire [0:0] b2s_0_cmd_context_channel; + wire b2s_0_cmd_context_veryLast; + wire b2s_0_cmd_context_endPacket; + wire [10:0] b2s_0_cmd_veryLastPtr; + wire [10:0] b2s_0_cmd_address; + wire [0:0] b2s_0_rsp_context_channel; + wire b2s_0_rsp_context_veryLast; + wire b2s_0_rsp_context_endPacket; + wire [2:0] _zz_b2s_0_rsp_context_channel; + wire io_outputs_0_fire; + wire when_DmaSg_l725; + wire when_DmaSg_l726; + reg m2b_cmd_s0_valid; + wire [1:0] _zz_m2b_cmd_s0_priority_masked; + wire [0:0] m2b_cmd_s0_priority_masked; + reg [0:0] m2b_cmd_s0_priority_roundRobins_0; + reg [0:0] m2b_cmd_s0_priority_roundRobins_1; + reg [0:0] m2b_cmd_s0_priority_roundRobins_2; + reg [0:0] m2b_cmd_s0_priority_roundRobins_3; + reg [1:0] m2b_cmd_s0_priority_counter; + wire [0:0] _zz_m2b_cmd_s0_priority_chosenOh; + wire [1:0] _zz_m2b_cmd_s0_priority_chosenOh_1; + wire [1:0] _zz_m2b_cmd_s0_priority_chosenOh_2; + wire [0:0] m2b_cmd_s0_priority_chosenOh; + wire m2b_cmd_s0_priority_weightLast; + wire [0:0] m2b_cmd_s0_priority_contextNext; + wire when_DmaSg_l758; + wire when_DmaSg_l760; + wire when_DmaSg_l763; + wire when_DmaSg_l763_1; + wire when_DmaSg_l763_2; + wire when_DmaSg_l763_3; + wire when_DmaSg_l773; + wire [31:0] m2b_cmd_s0_address; + wire [25:0] m2b_cmd_s0_bytesLeft; + wire [11:0] m2b_cmd_s0_readAddressBurstRange; + wire [11:0] m2b_cmd_s0_lengthHead; + wire [11:0] m2b_cmd_s0_length; + wire m2b_cmd_s0_lastBurst; + reg m2b_cmd_s1_valid; + reg [31:0] m2b_cmd_s1_address; + reg [11:0] m2b_cmd_s1_length; + reg m2b_cmd_s1_lastBurst; + reg [25:0] m2b_cmd_s1_bytesLeft; + wire [3:0] m2b_cmd_s1_context_start; + wire [3:0] m2b_cmd_s1_context_stop; + wire [11:0] m2b_cmd_s1_context_length; + wire m2b_cmd_s1_context_last; + wire [31:0] m2b_cmd_s1_addressNext; + wire [25:0] m2b_cmd_s1_byteLeftNext; + wire [9:0] m2b_cmd_s1_fifoPushDecr; + wire when_DmaSg_l828; + wire [3:0] m2b_rsp_context_start; + wire [3:0] m2b_rsp_context_stop; + wire [11:0] m2b_rsp_context_length; + wire m2b_rsp_context_last; + wire [20:0] _zz_m2b_rsp_context_start; + wire m2b_rsp_veryLast; + wire io_read_rsp_fire; + wire when_DmaSg_l847; + wire when_DmaSg_l848; + reg m2b_rsp_first; + wire m2b_rsp_writeContext_last; + wire m2b_rsp_writeContext_lastOfBurst; + wire [4:0] m2b_rsp_writeContext_loadByteInNextBeat; + wire memory_core_io_writes_1_cmd_fire; + wire _zz_channels_1_fifo_push_ptrIncr_value; + wire when_DmaSg_l874; + wire m2b_writeRsp_context_last; + wire m2b_writeRsp_context_lastOfBurst; + wire [4:0] m2b_writeRsp_context_loadByteInNextBeat; + wire [6:0] _zz_m2b_writeRsp_context_last; + wire _zz_channels_1_fifo_pop_bytesIncr_value; + wire when_DmaSg_l893; + reg b2m_fsm_sel_valid; + reg b2m_fsm_sel_ready; + reg [11:0] b2m_fsm_sel_bytePerBurst; + reg [11:0] b2m_fsm_sel_bytesInBurst; + reg [13:0] b2m_fsm_sel_bytesInFifo; + reg [31:0] b2m_fsm_sel_address; + reg [10:0] b2m_fsm_sel_ptr; + reg [10:0] b2m_fsm_sel_ptrMask; + reg b2m_fsm_sel_flush; + reg b2m_fsm_sel_packet; + reg [25:0] b2m_fsm_sel_bytesLeft; + reg b2m_fsm_arbiter_logic_valid; + wire [1:0] _zz_b2m_fsm_arbiter_logic_priority_masked; + wire [0:0] b2m_fsm_arbiter_logic_priority_masked; + reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_0; + reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_1; + reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_2; + reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_3; + reg [1:0] b2m_fsm_arbiter_logic_priority_counter; + wire [0:0] _zz_b2m_fsm_arbiter_logic_priority_chosenOh; + wire [1:0] _zz_b2m_fsm_arbiter_logic_priority_chosenOh_1; + wire [1:0] _zz_b2m_fsm_arbiter_logic_priority_chosenOh_2; + wire [0:0] b2m_fsm_arbiter_logic_priority_chosenOh; + wire b2m_fsm_arbiter_logic_priority_weightLast; + wire [0:0] b2m_fsm_arbiter_logic_priority_contextNext; + wire when_DmaSg_l758_1; + wire when_DmaSg_l760_1; + wire when_DmaSg_l763_4; + wire when_DmaSg_l763_5; + wire when_DmaSg_l763_6; + wire when_DmaSg_l763_7; + wire when_DmaSg_l773_1; + wire when_DmaSg_l935; + wire [12:0] b2m_fsm_bytesInBurstP1; + wire [31:0] b2m_fsm_addressNext; + wire [26:0] b2m_fsm_bytesLeftNext; + wire b2m_fsm_isFinalCmd; + reg [7:0] b2m_fsm_beatCounter; + reg b2m_fsm_sel_valid_regNext; + wire b2m_fsm_s0; + reg b2m_fsm_s1; + reg b2m_fsm_s2; + wire when_DmaSg_l986; + wire [13:0] _zz_b2m_fsm_sel_bytesInBurst; + wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_1; + wire [11:0] _zz_b2m_fsm_sel_bytesInBurst_2; + wire b2m_fsm_fifoCompletion; + wire when_DmaSg_l996; + wire when_DmaSg_l1001; + reg b2m_fsm_toggle; + wire when_DmaSg_l1013; + wire [10:0] b2m_fsm_fetch_context_ptr; + wire b2m_fsm_fetch_context_toggle; + wire when_DmaSg_l1033; + wire [10:0] b2m_fsm_aggregate_context_ptr; + wire b2m_fsm_aggregate_context_toggle; + wire [11:0] _zz_b2m_fsm_aggregate_context_ptr; + wire memory_core_io_reads_1_rsp_s2mPipe_valid; + reg memory_core_io_reads_1_rsp_s2mPipe_ready; + wire [127:0] memory_core_io_reads_1_rsp_s2mPipe_payload_data; + wire [15:0] memory_core_io_reads_1_rsp_s2mPipe_payload_mask; + wire [11:0] memory_core_io_reads_1_rsp_s2mPipe_payload_context; + reg memory_core_io_reads_1_rsp_rValidN; + reg [127:0] memory_core_io_reads_1_rsp_rData_data; + reg [15:0] memory_core_io_reads_1_rsp_rData_mask; + reg [11:0] memory_core_io_reads_1_rsp_rData_context; + wire when_Stream_l445; + reg b2m_fsm_aggregate_memoryPort_valid; + wire b2m_fsm_aggregate_memoryPort_ready; + wire [127:0] b2m_fsm_aggregate_memoryPort_payload_data; + wire [15:0] b2m_fsm_aggregate_memoryPort_payload_mask; + wire [11:0] b2m_fsm_aggregate_memoryPort_payload_context; + reg b2m_fsm_aggregate_first; + wire b2m_fsm_aggregate_memoryPort_fire; + wire when_DmaSg_l1050; + wire [3:0] b2m_fsm_aggregate_bytesToSkip; + wire [15:0] b2m_fsm_aggregate_bytesToSkipMask; + reg _zz_io_flush; + wire [3:0] b2m_fsm_cmd_maskFirstTrigger; + wire [3:0] b2m_fsm_cmd_maskLastTriggerComb; + reg [3:0] b2m_fsm_cmd_maskLastTriggerReg; + reg [15:0] b2m_fsm_cmd_maskLast; + wire [15:0] b2m_fsm_cmd_maskFirst; + wire b2m_fsm_cmd_enoughAggregation; + wire io_write_cmd_fire; + reg io_write_cmd_payload_first; + wire b2m_fsm_cmd_doPtrIncr; + wire [11:0] b2m_fsm_cmd_context_length; + wire b2m_fsm_cmd_context_doPacketSync; + wire when_DmaSg_l1102; + wire [11:0] b2m_rsp_context_length; + wire b2m_rsp_context_doPacketSync; + wire [12:0] _zz_b2m_rsp_context_length; + wire io_write_rsp_fire; + wire when_DmaSg_l1116; + wire [1:0] _zz_ll_arbiter_head; + wire _zz_ll_arbiter_head_1; + wire ll_arbiter_head; + wire ll_arbiter_isJustASink; + wire ll_arbiter_doDescriptorStall; + wire ll_arbiter_onSgStream; + reg ll_cmd_valid; + wire when_DmaSg_l1149; + reg ll_cmd_oh_0; + reg ll_cmd_oh_1; + wire when_DmaSg_l1148; + reg [31:0] ll_cmd_ptr; + wire when_DmaSg_l1148_1; + reg [31:0] ll_cmd_ptrNext; + wire when_DmaSg_l1148_2; + reg [26:0] ll_cmd_bytesDone; + wire when_DmaSg_l1148_3; + reg ll_cmd_endOfPacket; + wire when_DmaSg_l1154; + reg ll_cmd_isJustASink; + wire when_DmaSg_l1155; + reg ll_cmd_doDescriptorStall; + wire when_DmaSg_l1156; + reg ll_cmd_onSgStream; + reg ll_cmd_readFired; + reg ll_cmd_writeFired; + wire when_DmaSg_l1160; + wire when_DmaSg_l1161; + wire when_DmaSg_l1169; + wire when_DmaSg_l1169_1; + wire when_DmaSg_l1177; + wire [0:0] ll_cmd_context_channel; + wire [3:0] ll_cmd_writeMaskSplit_0; + wire [3:0] ll_cmd_writeMaskSplit_1; + wire [3:0] ll_cmd_writeMaskSplit_2; + wire [3:0] ll_cmd_writeMaskSplit_3; + wire [31:0] ll_cmd_writeDataSplit_0; + wire [31:0] ll_cmd_writeDataSplit_1; + wire [31:0] ll_cmd_writeDataSplit_2; + wire [31:0] ll_cmd_writeDataSplit_3; + wire io_sgRead_cmd_fire; + wire io_sgWrite_cmd_fire; + wire [0:0] ll_readRsp_context_channel; + wire [1:0] _zz_ll_readRsp_oh_0; + wire ll_readRsp_oh_0; + wire ll_readRsp_oh_1; + reg [0:0] ll_readRsp_beatCounter; + reg ll_readRsp_completed; + wire io_sgRead_rsp_fire; + wire when_DmaSg_l1248; + wire when_DmaSg_l1248_1; + wire when_DmaSg_l1248_2; + wire when_DmaSg_l1248_3; + wire when_DmaSg_l1248_4; + wire when_DmaSg_l1248_5; + wire when_DmaSg_l1248_6; + wire when_DmaSg_l1271; + wire [0:0] ll_writeRsp_context_channel; + wire [1:0] _zz_ll_writeRsp_oh_0; + wire ll_writeRsp_oh_0; + wire ll_writeRsp_oh_1; + wire io_sgWrite_rsp_fire; + reg when_BusSlaveFactory_l377; + wire when_BusSlaveFactory_l379; + reg when_BusSlaveFactory_l377_1; + wire when_BusSlaveFactory_l379_1; + reg when_BusSlaveFactory_l377_2; + wire when_BusSlaveFactory_l379_2; + reg when_BusSlaveFactory_l377_3; + wire when_BusSlaveFactory_l379_3; + reg when_BusSlaveFactory_l341; + wire when_BusSlaveFactory_l347; + reg when_BusSlaveFactory_l341_1; + wire when_BusSlaveFactory_l347_1; + reg when_BusSlaveFactory_l341_2; + wire when_BusSlaveFactory_l347_2; + reg when_BusSlaveFactory_l341_3; + wire when_BusSlaveFactory_l347_3; + reg when_BusSlaveFactory_l377_4; + wire when_BusSlaveFactory_l379_4; + reg when_BusSlaveFactory_l377_5; + wire when_BusSlaveFactory_l379_5; + reg when_BusSlaveFactory_l377_6; + wire when_BusSlaveFactory_l379_6; + reg when_BusSlaveFactory_l377_7; + wire when_BusSlaveFactory_l379_7; + reg when_BusSlaveFactory_l341_4; + wire when_BusSlaveFactory_l347_4; + reg when_BusSlaveFactory_l341_5; + wire when_BusSlaveFactory_l347_5; + reg when_BusSlaveFactory_l341_6; + wire when_BusSlaveFactory_l347_6; + wire when_Apb3SlaveFactory_l81; + wire when_Apb3SlaveFactory_l81_1; + wire when_Apb3SlaveFactory_l81_2; + wire when_Apb3SlaveFactory_l81_3; + function [15:0] zz_io_sgWrite_cmd_payload_fragment_mask(input dummy); + begin + zz_io_sgWrite_cmd_payload_fragment_mask[7 : 4] = 4'b0000; + zz_io_sgWrite_cmd_payload_fragment_mask[11 : 8] = 4'b0000; + zz_io_sgWrite_cmd_payload_fragment_mask[15 : 12] = 4'b0000; + zz_io_sgWrite_cmd_payload_fragment_mask[3 : 0] = 4'b1111; + end + endfunction + wire [15:0] _zz_1; + + assign _zz_channels_0_bytesProbe_value = (channels_0_bytesProbe_value + _zz_channels_0_bytesProbe_value_1); + assign _zz_channels_0_bytesProbe_value_1 = {15'd0, channels_0_bytesProbe_incr_payload}; + assign _zz_channels_0_fifo_pop_withOverride_backupNext = (channels_0_fifo_pop_withOverride_backup + channels_0_fifo_pop_bytesIncr_value); + assign _zz_channels_0_fifo_pop_withOverride_exposed = (channels_0_fifo_pop_withOverride_exposed - channels_0_fifo_pop_bytesDecr_value); + assign _zz_channels_0_pop_b2m_selfFlush = {13'd0, channels_0_fifo_pop_bytes}; + assign _zz_channels_0_pop_b2m_request = {2'd0, channels_0_pop_b2m_bytePerBurst}; + assign _zz_channels_0_pop_b2m_request_2 = (channels_0_fifo_words >>> 1'd1); + assign _zz_channels_0_pop_b2m_request_1 = {1'd0, _zz_channels_0_pop_b2m_request_2}; + assign _zz_channels_0_pop_b2m_memPending = (channels_0_pop_b2m_memPending + _zz_channels_0_pop_b2m_memPending_1); + assign _zz_channels_0_pop_b2m_memPending_2 = channels_0_pop_b2m_memPendingInc; + assign _zz_channels_0_pop_b2m_memPending_1 = {3'd0, _zz_channels_0_pop_b2m_memPending_2}; + assign _zz_channels_0_pop_b2m_memPending_4 = channels_0_pop_b2m_memRsp; + assign _zz_channels_0_pop_b2m_memPending_3 = {3'd0, _zz_channels_0_pop_b2m_memPending_4}; + assign _zz_channels_0_fifo_push_available = (channels_0_fifo_push_available + channels_0_fifo_pop_ptrIncr_value_regNext); + assign _zz_channels_1_bytesProbe_value = (channels_1_bytesProbe_value + _zz_channels_1_bytesProbe_value_1); + assign _zz_channels_1_bytesProbe_value_1 = {15'd0, channels_1_bytesProbe_incr_payload}; + assign _zz_channels_1_fifo_pop_withoutOverride_exposed = (channels_1_fifo_pop_withoutOverride_exposed + channels_1_fifo_pop_bytesIncr_value); + assign _zz_channels_1_push_m2b_memPending = (channels_1_push_m2b_memPending + _zz_channels_1_push_m2b_memPending_1); + assign _zz_channels_1_push_m2b_memPending_2 = channels_1_push_m2b_memPendingIncr; + assign _zz_channels_1_push_m2b_memPending_1 = {3'd0, _zz_channels_1_push_m2b_memPending_2}; + assign _zz_channels_1_push_m2b_memPending_4 = channels_1_push_m2b_memPendingDecr; + assign _zz_channels_1_push_m2b_memPending_3 = {3'd0, _zz_channels_1_push_m2b_memPending_4}; + assign _zz_channels_1_push_m2b_loadRequest_1 = (channels_1_push_m2b_bytePerBurst >>> 2'd3); + assign _zz_channels_1_push_m2b_loadRequest = {2'd0, _zz_channels_1_push_m2b_loadRequest_1}; + assign _zz_when_DmaSg_l486 = {14'd0, channels_1_push_m2b_bytePerBurst}; + assign _zz_channels_1_fifo_push_available = (channels_1_fifo_push_available + channels_1_fifo_pop_ptrIncr_value_regNext); + assign _zz_s2b_0_cmd_byteCount_8 = (_zz_s2b_0_cmd_byteCount_9 + _zz_s2b_0_cmd_byteCount_11); + assign _zz_s2b_0_cmd_byteCount_15 = {s2b_0_cmd_sinkHalted_payload_mask[7],s2b_0_cmd_sinkHalted_payload_mask[6]}; + assign _zz_s2b_0_cmd_byteCount_14 = {1'd0, _zz_s2b_0_cmd_byteCount_15}; + assign _zz__zz_m2b_cmd_s0_priority_chosenOh_2 = (_zz_m2b_cmd_s0_priority_chosenOh_1 - _zz__zz_m2b_cmd_s0_priority_chosenOh_2_1); + assign _zz__zz_m2b_cmd_s0_priority_chosenOh_2_2 = _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3; + assign _zz__zz_m2b_cmd_s0_priority_chosenOh_2_1 = {1'd0, _zz__zz_m2b_cmd_s0_priority_chosenOh_2_2}; + assign _zz_m2b_cmd_s0_length = ((_zz_m2b_cmd_s0_length_1 < m2b_cmd_s0_bytesLeft) ? _zz_m2b_cmd_s0_length_2 : m2b_cmd_s0_bytesLeft); + assign _zz_m2b_cmd_s0_length_1 = {14'd0, m2b_cmd_s0_lengthHead}; + assign _zz_m2b_cmd_s0_length_2 = {14'd0, m2b_cmd_s0_lengthHead}; + assign _zz_m2b_cmd_s0_lastBurst = {14'd0, m2b_cmd_s0_length}; + assign _zz_m2b_cmd_s1_context_stop = (m2b_cmd_s1_address + _zz_m2b_cmd_s1_context_stop_1); + assign _zz_m2b_cmd_s1_context_stop_1 = {20'd0, m2b_cmd_s1_length}; + assign _zz_m2b_cmd_s1_addressNext = (m2b_cmd_s1_address + _zz_m2b_cmd_s1_addressNext_1); + assign _zz_m2b_cmd_s1_addressNext_1 = {20'd0, m2b_cmd_s1_length}; + assign _zz_m2b_cmd_s1_byteLeftNext = (m2b_cmd_s1_bytesLeft - _zz_m2b_cmd_s1_byteLeftNext_1); + assign _zz_m2b_cmd_s1_byteLeftNext_1 = {14'd0, m2b_cmd_s1_length}; + assign _zz_m2b_cmd_s1_fifoPushDecr = ({1'b0,(_zz_m2b_cmd_s1_fifoPushDecr_1 | 12'h00f)} + _zz_m2b_cmd_s1_fifoPushDecr_4); + assign _zz_m2b_cmd_s1_fifoPushDecr_1 = (_zz_m2b_cmd_s1_fifoPushDecr_2 + io_read_cmd_payload_fragment_length); + assign _zz_m2b_cmd_s1_fifoPushDecr_3 = m2b_cmd_s1_address[3 : 0]; + assign _zz_m2b_cmd_s1_fifoPushDecr_2 = {8'd0, _zz_m2b_cmd_s1_fifoPushDecr_3}; + assign _zz_m2b_cmd_s1_fifoPushDecr_5 = {1'b0,1'b1}; + assign _zz_m2b_cmd_s1_fifoPushDecr_4 = {11'd0, _zz_m2b_cmd_s1_fifoPushDecr_5}; + assign _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2 = (_zz_b2m_fsm_arbiter_logic_priority_chosenOh_1 - _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_1); + assign _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_2 = _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3; + assign _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_1 = {1'd0, _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_2}; + assign _zz_when = 1'b1; + assign _zz_b2m_fsm_bytesInBurstP1_1 = {1'b0,1'b1}; + assign _zz_b2m_fsm_bytesInBurstP1 = {11'd0, _zz_b2m_fsm_bytesInBurstP1_1}; + assign _zz_b2m_fsm_addressNext = {19'd0, b2m_fsm_bytesInBurstP1}; + assign _zz_b2m_fsm_bytesLeftNext_1 = {1'b0,b2m_fsm_bytesInBurstP1}; + assign _zz_b2m_fsm_bytesLeftNext = {13'd0, _zz_b2m_fsm_bytesLeftNext_1}; + assign _zz__zz_b2m_fsm_sel_bytesInBurst_1 = {12'd0, _zz_b2m_fsm_sel_bytesInBurst}; + assign _zz__zz_b2m_fsm_sel_bytesInBurst_1_1 = {12'd0, _zz_b2m_fsm_sel_bytesInBurst}; + assign _zz__zz_b2m_fsm_sel_bytesInBurst_2 = b2m_fsm_sel_address[11:0]; + assign _zz_b2m_fsm_sel_bytesInBurst_3 = ((_zz_b2m_fsm_sel_bytesInBurst_1 < _zz_b2m_fsm_sel_bytesInBurst_4) ? _zz_b2m_fsm_sel_bytesInBurst_1 : _zz_b2m_fsm_sel_bytesInBurst_5); + assign _zz_b2m_fsm_sel_bytesInBurst_4 = {14'd0, _zz_b2m_fsm_sel_bytesInBurst_2}; + assign _zz_b2m_fsm_sel_bytesInBurst_5 = {14'd0, _zz_b2m_fsm_sel_bytesInBurst_2}; + assign _zz_b2m_fsm_fifoCompletion = {2'd0, b2m_fsm_sel_bytesInBurst}; + assign _zz_b2m_fsm_fifoCompletion_1 = (b2m_fsm_sel_bytesInFifo - 14'h0001); + assign _zz_b2m_fsm_beatCounter = (_zz_b2m_fsm_beatCounter_1 + b2m_fsm_sel_bytesInBurst); + assign _zz_b2m_fsm_beatCounter_2 = b2m_fsm_sel_address[3 : 0]; + assign _zz_b2m_fsm_beatCounter_1 = {8'd0, _zz_b2m_fsm_beatCounter_2}; + assign _zz_b2m_fsm_sel_ptr = (b2m_fsm_sel_ptr + 11'h002); + assign _zz_b2m_fsm_cmd_maskLastTriggerComb = b2m_fsm_sel_bytesInBurst[3:0]; + assign _zz_when_1 = 1'b1; + assign _zz_when_2 = 1'b1; + assign _zz__zz_ll_arbiter_head_1 = (_zz_ll_arbiter_head & (~ _zz__zz_ll_arbiter_head_1_1)); + assign _zz__zz_ll_arbiter_head_1_1 = (_zz_ll_arbiter_head - 2'b01); + assign _zz_ll_arbiter_head_2 = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_arbiter_isJustASink = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_arbiter_doDescriptorStall = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_arbiter_onSgStream = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_cmd_ptr = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_cmd_ptrNext = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_cmd_endOfPacket = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_channels_0_channelStart = 1'b1; + assign _zz_channels_0_ctrl_kick = 1'b1; + assign _zz_channels_0_channelStart_1 = 1'b1; + assign _zz_channels_0_ll_sgStart = 1'b1; + assign _zz_channels_0_interrupts_completion_valid = 1'b0; + assign _zz_channels_0_interrupts_onChannelCompletion_valid = 1'b0; + assign _zz_channels_0_interrupts_onLinkedListUpdate_valid = 1'b0; + assign _zz_channels_0_interrupts_s2mPacket_valid = 1'b0; + assign _zz_channels_1_channelStart = 1'b1; + assign _zz_channels_1_ctrl_kick = 1'b1; + assign _zz_channels_1_channelStart_1 = 1'b1; + assign _zz_channels_1_ll_sgStart = 1'b1; + assign _zz_channels_1_interrupts_completion_valid = 1'b0; + assign _zz_channels_1_interrupts_onChannelCompletion_valid = 1'b0; + assign _zz_channels_1_interrupts_onLinkedListUpdate_valid = 1'b0; + assign _zz_io_ctrl_PRDATA = channels_0_ll_ptr; + assign _zz_io_ctrl_PRDATA_1 = channels_1_ll_ptr; + assign _zz_channels_0_fifo_push_ptrIncr_value_1 = ((when_DmaSg_l665 && (|s2b_0_cmd_sinkHalted_payload_mask)) ? 1'b1 : 1'b0); + assign _zz_channels_0_fifo_push_ptrIncr_value = {10'd0, _zz_channels_0_fifo_push_ptrIncr_value_1}; + assign _zz_channels_0_fifo_pop_bytesIncr_value_2 = (_zz_channels_0_fifo_pop_bytesIncr_value ? s2b_0_rsp_context_bytes : 4'b0000); + assign _zz_channels_0_fifo_pop_bytesIncr_value_1 = {10'd0, _zz_channels_0_fifo_pop_bytesIncr_value_2}; + assign _zz_channels_0_fifo_pop_ptrIncr_value_1 = ((b2m_fsm_cmd_doPtrIncr && 1'b1) ? 2'b10 : 2'b00); + assign _zz_channels_0_fifo_pop_ptrIncr_value = {9'd0, _zz_channels_0_fifo_pop_ptrIncr_value_1}; + assign _zz_channels_1_fifo_push_ptrIncr_value_2 = (_zz_channels_1_fifo_push_ptrIncr_value ? 2'b10 : 2'b00); + assign _zz_channels_1_fifo_push_ptrIncr_value_1 = {9'd0, _zz_channels_1_fifo_push_ptrIncr_value_2}; + assign _zz_channels_1_fifo_pop_bytesIncr_value_2 = (_zz_channels_1_fifo_pop_bytesIncr_value ? _zz_channels_1_fifo_pop_bytesIncr_value_3 : 5'h0); + assign _zz_channels_1_fifo_pop_bytesIncr_value_1 = {9'd0, _zz_channels_1_fifo_pop_bytesIncr_value_2}; + assign _zz_channels_1_fifo_pop_bytesIncr_value_3 = (m2b_writeRsp_context_loadByteInNextBeat + 5'h01); + assign _zz_channels_1_fifo_pop_ptrIncr_value_1 = ((b2s_0_cmd_channelsOh[0] && memory_core_io_reads_0_cmd_ready) ? 1'b1 : 1'b0); + assign _zz_channels_1_fifo_pop_ptrIncr_value = {10'd0, _zz_channels_1_fifo_pop_ptrIncr_value_1}; + assign _zz_s2b_0_cmd_byteCount_10 = {s2b_0_cmd_sinkHalted_payload_mask[2],{s2b_0_cmd_sinkHalted_payload_mask[1],s2b_0_cmd_sinkHalted_payload_mask[0]}}; + assign _zz_s2b_0_cmd_byteCount_12 = {s2b_0_cmd_sinkHalted_payload_mask[5],{s2b_0_cmd_sinkHalted_payload_mask[4],s2b_0_cmd_sinkHalted_payload_mask[3]}}; + assign _zz_s2b_0_cmd_firsts = io_inputs_0_payload_last_regNextWhen_5; + assign _zz_s2b_0_cmd_firsts_1 = {io_inputs_0_payload_last_regNextWhen_4,{io_inputs_0_payload_last_regNextWhen_3,{io_inputs_0_payload_last_regNextWhen_2,{io_inputs_0_payload_last_regNextWhen_1,io_inputs_0_payload_last_regNextWhen}}}}; + assign _zz_b2m_fsm_aggregate_bytesToSkipMask = 4'b1101; + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_1 = (! b2m_fsm_aggregate_first); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_2 = (b2m_fsm_aggregate_bytesToSkip <= 4'b1100); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_3 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1011)); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_4 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1010)); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_5 = {((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1001)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1000)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= _zz_b2m_fsm_aggregate_bytesToSkipMask_6)),{(_zz_b2m_fsm_aggregate_bytesToSkipMask_7 || _zz_b2m_fsm_aggregate_bytesToSkipMask_8),{_zz_b2m_fsm_aggregate_bytesToSkipMask_9,{_zz_b2m_fsm_aggregate_bytesToSkipMask_10,_zz_b2m_fsm_aggregate_bytesToSkipMask_11}}}}}}; + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_6 = 4'b0111; + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_7 = (! b2m_fsm_aggregate_first); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_8 = (b2m_fsm_aggregate_bytesToSkip <= 4'b0110); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_9 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0101)); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_10 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0100)); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_11 = {((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0011)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0010)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0001)),((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0000))}}}; + assign _zz_b2m_fsm_cmd_maskLast = 4'b1010; + assign _zz_b2m_fsm_cmd_maskLast_1 = (4'b1001 <= b2m_fsm_cmd_maskLastTriggerComb); + assign _zz_b2m_fsm_cmd_maskLast_2 = (4'b1000 <= b2m_fsm_cmd_maskLastTriggerComb); + assign _zz_b2m_fsm_cmd_maskLast_3 = {(4'b0111 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0110 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0101 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0100 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0011 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0010 <= b2m_fsm_cmd_maskLastTriggerComb),{(_zz_b2m_fsm_cmd_maskLast_4 <= b2m_fsm_cmd_maskLastTriggerComb),(_zz_b2m_fsm_cmd_maskLast_5 <= b2m_fsm_cmd_maskLastTriggerComb)}}}}}}}; + assign _zz_b2m_fsm_cmd_maskLast_4 = 4'b0001; + assign _zz_b2m_fsm_cmd_maskLast_5 = 4'b0000; + assign _zz_b2m_fsm_cmd_maskFirst = 4'b1010; + assign _zz_b2m_fsm_cmd_maskFirst_1 = (b2m_fsm_cmd_maskFirstTrigger <= 4'b1001); + assign _zz_b2m_fsm_cmd_maskFirst_2 = (b2m_fsm_cmd_maskFirstTrigger <= 4'b1000); + assign _zz_b2m_fsm_cmd_maskFirst_3 = {(b2m_fsm_cmd_maskFirstTrigger <= 4'b0111),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0110),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0101),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0100),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0011),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0010),{(b2m_fsm_cmd_maskFirstTrigger <= _zz_b2m_fsm_cmd_maskFirst_4),(b2m_fsm_cmd_maskFirstTrigger <= _zz_b2m_fsm_cmd_maskFirst_5)}}}}}}}; + assign _zz_b2m_fsm_cmd_maskFirst_4 = 4'b0001; + assign _zz_b2m_fsm_cmd_maskFirst_5 = 4'b0000; + EfxDMA_DmaMemoryCore_a048ca8f51874147a1cd65d43e6523ef memory_core ( + .io_writes_0_cmd_valid (s2b_0_cmd_sinkHalted_valid ), //i + .io_writes_0_cmd_ready (memory_core_io_writes_0_cmd_ready ), //o + .io_writes_0_cmd_payload_address (memory_core_io_writes_0_cmd_payload_address[9:0]), //i + .io_writes_0_cmd_payload_data (s2b_0_cmd_sinkHalted_payload_data[63:0] ), //i + .io_writes_0_cmd_payload_mask (s2b_0_cmd_sinkHalted_payload_mask[7:0] ), //i + .io_writes_0_cmd_payload_priority (channels_0_priority[1:0] ), //i + .io_writes_0_cmd_payload_context (memory_core_io_writes_0_cmd_payload_context[6:0]), //i + .io_writes_0_rsp_valid (memory_core_io_writes_0_rsp_valid ), //o + .io_writes_0_rsp_payload_context (memory_core_io_writes_0_rsp_payload_context[6:0]), //o + .io_writes_1_cmd_valid (io_read_rsp_valid ), //i + .io_writes_1_cmd_ready (memory_core_io_writes_1_cmd_ready ), //o + .io_writes_1_cmd_payload_address (memory_core_io_writes_1_cmd_payload_address[9:0]), //i + .io_writes_1_cmd_payload_data (io_read_rsp_payload_fragment_data[127:0] ), //i + .io_writes_1_cmd_payload_mask (memory_core_io_writes_1_cmd_payload_mask[15:0] ), //i + .io_writes_1_cmd_payload_context (memory_core_io_writes_1_cmd_payload_context[6:0]), //i + .io_writes_1_rsp_valid (memory_core_io_writes_1_rsp_valid ), //o + .io_writes_1_rsp_payload_context (memory_core_io_writes_1_rsp_payload_context[6:0]), //o + .io_reads_0_cmd_valid (memory_core_io_reads_0_cmd_valid ), //i + .io_reads_0_cmd_ready (memory_core_io_reads_0_cmd_ready ), //o + .io_reads_0_cmd_payload_address (memory_core_io_reads_0_cmd_payload_address[9:0] ), //i + .io_reads_0_cmd_payload_priority (channels_1_priority[1:0] ), //i + .io_reads_0_cmd_payload_context (memory_core_io_reads_0_cmd_payload_context[2:0] ), //i + .io_reads_0_rsp_valid (memory_core_io_reads_0_rsp_valid ), //o + .io_reads_0_rsp_ready (io_outputs_0_ready ), //i + .io_reads_0_rsp_payload_data (memory_core_io_reads_0_rsp_payload_data[63:0] ), //o + .io_reads_0_rsp_payload_mask (memory_core_io_reads_0_rsp_payload_mask[7:0] ), //o + .io_reads_0_rsp_payload_context (memory_core_io_reads_0_rsp_payload_context[2:0] ), //o + .io_reads_1_cmd_valid (b2m_fsm_sel_valid ), //i + .io_reads_1_cmd_ready (memory_core_io_reads_1_cmd_ready ), //o + .io_reads_1_cmd_payload_address (memory_core_io_reads_1_cmd_payload_address[9:0] ), //i + .io_reads_1_cmd_payload_context (memory_core_io_reads_1_cmd_payload_context[11:0]), //i + .io_reads_1_rsp_valid (memory_core_io_reads_1_rsp_valid ), //o + .io_reads_1_rsp_ready (memory_core_io_reads_1_rsp_rValidN ), //i + .io_reads_1_rsp_payload_data (memory_core_io_reads_1_rsp_payload_data[127:0] ), //o + .io_reads_1_rsp_payload_mask (memory_core_io_reads_1_rsp_payload_mask[15:0] ), //o + .io_reads_1_rsp_payload_context (memory_core_io_reads_1_rsp_payload_context[11:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_Aggregator_a048ca8f51874147a1cd65d43e6523ef b2m_fsm_aggregate_engine ( + .io_input_valid (b2m_fsm_aggregate_memoryPort_valid ), //i + .io_input_ready (b2m_fsm_aggregate_engine_io_input_ready ), //o + .io_input_payload_data (b2m_fsm_aggregate_memoryPort_payload_data[127:0] ), //i + .io_input_payload_mask (b2m_fsm_aggregate_engine_io_input_payload_mask[15:0]), //i + .io_output_data (b2m_fsm_aggregate_engine_io_output_data[127:0] ), //o + .io_output_mask (b2m_fsm_aggregate_engine_io_output_mask[15:0] ), //o + .io_output_enough (b2m_fsm_cmd_enoughAggregation ), //i + .io_output_consume (io_write_cmd_fire ), //i + .io_output_consumed (b2m_fsm_aggregate_engine_io_output_consumed ), //o + .io_output_lastByteUsed (b2m_fsm_cmd_maskLastTriggerReg[3:0] ), //i + .io_output_usedUntil (b2m_fsm_aggregate_engine_io_output_usedUntil[3:0] ), //o + .io_flush (b2m_fsm_aggregate_engine_io_flush ), //i + .io_offset (b2m_fsm_aggregate_engine_io_offset[3:0] ), //i + .io_burstLength (b2m_fsm_sel_bytesInBurst[11:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_s2b_0_cmd_byteCount_10) + 3'b000 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount; + 3'b001 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_1; + 3'b010 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_2; + 3'b011 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_3; + 3'b100 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_4; + 3'b101 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_5; + 3'b110 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_6; + default : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_7; + endcase + end + + always @(*) begin + case(_zz_s2b_0_cmd_byteCount_12) + 3'b000 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount; + 3'b001 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_1; + 3'b010 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_2; + 3'b011 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_3; + 3'b100 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_4; + 3'b101 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_5; + 3'b110 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_6; + default : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_7; + endcase + end + + always @(*) begin + case(_zz_s2b_0_cmd_byteCount_14) + 3'b000 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount; + 3'b001 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_1; + 3'b010 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_2; + 3'b011 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_3; + 3'b100 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_4; + 3'b101 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_5; + 3'b110 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_6; + default : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_7; + endcase + end + + always @(*) begin + case(_zz_m2b_cmd_s0_priority_masked) + 2'b00 : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_0; + 2'b01 : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_1; + 2'b10 : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_2; + default : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_3; + endcase + end + + always @(*) begin + case(_zz_b2m_fsm_arbiter_logic_priority_masked) + 2'b00 : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_0; + 2'b01 : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_1; + 2'b10 : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_2; + default : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_3; + endcase + end + + assign ctrl_readErrorFlag = 1'b0; + assign ctrl_writeErrorFlag = 1'b0; + assign io_ctrl_PREADY = 1'b1; + always @(*) begin + io_ctrl_PRDATA = 32'h0; + case(io_ctrl_PADDR) + 14'h002c : begin + io_ctrl_PRDATA[0 : 0] = channels_0_channelValid; + end + 14'h0054 : begin + io_ctrl_PRDATA[0 : 0] = channels_0_interrupts_completion_valid; + io_ctrl_PRDATA[2 : 2] = channels_0_interrupts_onChannelCompletion_valid; + io_ctrl_PRDATA[3 : 3] = channels_0_interrupts_onLinkedListUpdate_valid; + io_ctrl_PRDATA[4 : 4] = channels_0_interrupts_s2mPacket_valid; + end + 14'h0060 : begin + io_ctrl_PRDATA[26 : 0] = channels_0_bytesProbe_value; + end + 14'h00ac : begin + io_ctrl_PRDATA[0 : 0] = channels_1_channelValid; + end + 14'h00d4 : begin + io_ctrl_PRDATA[0 : 0] = channels_1_interrupts_completion_valid; + io_ctrl_PRDATA[2 : 2] = channels_1_interrupts_onChannelCompletion_valid; + io_ctrl_PRDATA[3 : 3] = channels_1_interrupts_onLinkedListUpdate_valid; + end + 14'h00e0 : begin + io_ctrl_PRDATA[26 : 0] = channels_1_bytesProbe_value; + end + default : begin + end + endcase + if(when_Apb3SlaveFactory_l81_1) begin + io_ctrl_PRDATA[31 : 0] = _zz_io_ctrl_PRDATA[31 : 0]; + end + if(when_Apb3SlaveFactory_l81_3) begin + io_ctrl_PRDATA[31 : 0] = _zz_io_ctrl_PRDATA_1[31 : 0]; + end + end + + assign ctrl_askWrite = ((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && io_ctrl_PWRITE); + assign ctrl_askRead = ((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && (! io_ctrl_PWRITE)); + assign ctrl_doWrite = (((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && io_ctrl_PREADY) && io_ctrl_PWRITE); + assign ctrl_doRead = (((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && io_ctrl_PREADY) && (! io_ctrl_PWRITE)); + assign io_ctrl_PSLVERROR = ((ctrl_doWrite && ctrl_writeErrorFlag) || (ctrl_doRead && ctrl_readErrorFlag)); + always @(*) begin + channels_0_channelStart = 1'b0; + if(when_BusSlaveFactory_l377) begin + if(when_BusSlaveFactory_l379) begin + channels_0_channelStart = _zz_channels_0_channelStart[0]; + end + end + if(when_BusSlaveFactory_l377_2) begin + if(when_BusSlaveFactory_l379_2) begin + channels_0_channelStart = _zz_channels_0_channelStart_1[0]; + end + end + end + + always @(*) begin + channels_0_channelCompletion = 1'b0; + if(channels_0_channelValid) begin + if(channels_0_channelStop) begin + if(channels_0_readyToStop) begin + channels_0_channelCompletion = 1'b1; + end + end + end + end + + always @(*) begin + channels_0_descriptorStart = 1'b0; + if(channels_0_ctrl_kick) begin + channels_0_descriptorStart = 1'b1; + end + if(when_DmaSg_l318) begin + if(when_DmaSg_l320) begin + if(when_DmaSg_l322) begin + channels_0_descriptorStart = 1'b1; + end + end + end + end + + always @(*) begin + channels_0_descriptorCompletion = 1'b0; + if(channels_0_pop_b2m_packetSync) begin + if(when_DmaSg_l532) begin + if(channels_0_push_s2b_completionOnLast) begin + channels_0_descriptorCompletion = 1'b1; + end + end + end + if(when_DmaSg_l547) begin + channels_0_descriptorCompletion = 1'b1; + end + if(channels_0_channelValid) begin + if(channels_0_channelStop) begin + if(channels_0_readyToStop) begin + channels_0_descriptorCompletion = 1'b1; + end + end + end + end + + always @(*) begin + channels_0_readyToStop = 1'b1; + if(channels_0_ll_waitDone) begin + channels_0_readyToStop = 1'b0; + end + if(when_DmaSg_l563) begin + channels_0_readyToStop = 1'b0; + end + end + + always @(*) begin + channels_0_bytesProbe_incr_valid = 1'b0; + if(io_write_rsp_fire) begin + if(when_DmaSg_l1116) begin + channels_0_bytesProbe_incr_valid = 1'b1; + end + end + end + + always @(*) begin + channels_0_bytesProbe_incr_payload = 12'bxxxxxxxxxxxx; + if(io_write_rsp_fire) begin + if(when_DmaSg_l1116) begin + channels_0_bytesProbe_incr_payload = b2m_rsp_context_length; + end + end + end + + always @(*) begin + channels_0_ll_sgStart = 1'b0; + if(when_BusSlaveFactory_l377_3) begin + if(when_BusSlaveFactory_l379_3) begin + channels_0_ll_sgStart = _zz_channels_0_ll_sgStart[0]; + end + end + end + + assign channels_0_ll_requestLl = ((((channels_0_channelValid && channels_0_ll_valid) && (! channels_0_channelStop)) && (! channels_0_ll_waitDone)) && ((! channels_0_descriptorValid) || channels_0_ll_requireSync)); + always @(*) begin + channels_0_ll_descriptorUpdated = 1'b0; + if(when_DmaSg_l318) begin + if(when_DmaSg_l328) begin + channels_0_ll_descriptorUpdated = 1'b1; + end + end + end + + assign when_DmaSg_l318 = (((channels_0_ll_valid && channels_0_ll_waitDone) && channels_0_ll_writeDone) && channels_0_ll_readDone); + assign when_DmaSg_l320 = (! channels_0_ll_justASync); + assign when_DmaSg_l322 = (! channels_0_ll_gotDescriptorStall); + assign when_DmaSg_l328 = (! channels_0_ll_head); + assign channels_0_fifo_base = 11'h0; + assign channels_0_fifo_words = 11'h1ff; + assign channels_0_fifo_push_availableDecr = 11'h0; + assign channels_0_fifo_push_ptrWithBase = ((channels_0_fifo_base & (~ channels_0_fifo_words)) | (channels_0_fifo_push_ptr & channels_0_fifo_words)); + assign channels_0_fifo_pop_ptrWithBase = ((channels_0_fifo_base & (~ channels_0_fifo_words)) | (channels_0_fifo_pop_ptr & channels_0_fifo_words)); + assign channels_0_fifo_pop_empty = (channels_0_fifo_pop_ptr == channels_0_fifo_push_ptr); + assign channels_0_fifo_pop_withOverride_backupNext = (_zz_channels_0_fifo_pop_withOverride_backupNext - channels_0_fifo_pop_bytesDecr_value); + always @(*) begin + channels_0_fifo_pop_withOverride_load = 1'b0; + if(when_DmaSg_l457) begin + channels_0_fifo_pop_withOverride_load = 1'b1; + end + end + + always @(*) begin + channels_0_fifo_pop_withOverride_unload = 1'b0; + if(channels_0_pop_b2m_packetSync) begin + channels_0_fifo_pop_withOverride_unload = 1'b1; + end + end + + assign when_DmaSg_l409 = (channels_0_channelStart || channels_0_fifo_pop_withOverride_unload); + assign channels_0_fifo_pop_bytes = channels_0_fifo_pop_withOverride_exposed; + assign channels_0_fifo_empty = (channels_0_fifo_push_ptr == channels_0_fifo_pop_ptr); + always @(*) begin + channels_0_push_s2b_packetEvent = 1'b0; + if(when_DmaSg_l679) begin + channels_0_push_s2b_packetEvent = 1'b1; + end + end + + assign when_DmaSg_l457 = (channels_0_push_s2b_packetEvent && channels_0_push_s2b_completionOnLast); + assign channels_0_pop_b2m_bytePerBurst = 12'h3ff; + always @(*) begin + channels_0_pop_b2m_fire = 1'b0; + if(when_DmaSg_l935) begin + if(_zz_when[0]) begin + channels_0_pop_b2m_fire = 1'b1; + end + end + end + + always @(*) begin + channels_0_pop_b2m_packetSync = 1'b0; + if(when_DmaSg_l523) begin + if(channels_0_pop_b2m_packet) begin + channels_0_pop_b2m_packetSync = 1'b1; + end + end + if(io_write_rsp_fire) begin + if(when_DmaSg_l1116) begin + if(b2m_rsp_context_doPacketSync) begin + channels_0_pop_b2m_packetSync = 1'b1; + end + end + end + end + + assign when_DmaSg_l505 = (channels_0_channelStart || channels_0_pop_b2m_fire); + always @(*) begin + channels_0_pop_b2m_memRsp = 1'b0; + if(io_write_rsp_fire) begin + if(_zz_when_2[0]) begin + channels_0_pop_b2m_memRsp = 1'b1; + end + end + end + + assign channels_0_pop_b2m_selfFlush = (channels_0_pop_b2m_bytesLeft < _zz_channels_0_pop_b2m_selfFlush); + assign channels_0_pop_b2m_request = ((((((channels_0_descriptorValid && (! channels_0_channelStop)) && (! channels_0_pop_b2m_waitFinalRsp)) && channels_0_pop_memory) && ((_zz_channels_0_pop_b2m_request < channels_0_fifo_pop_bytes) || (((channels_0_fifo_push_available < _zz_channels_0_pop_b2m_request_1) || channels_0_pop_b2m_flush) || channels_0_pop_b2m_selfFlush))) && (channels_0_fifo_pop_bytes != 14'h0)) && (channels_0_pop_b2m_memPending != 4'b1111)); + always @(*) begin + channels_0_pop_b2m_memPendingInc = 1'b0; + if(when_DmaSg_l758_1) begin + if(when_DmaSg_l773_1) begin + channels_0_pop_b2m_memPendingInc = 1'b1; + end + end + end + + always @(*) begin + channels_0_pop_b2m_decrBytes = 14'h0; + if(b2m_fsm_s1) begin + if(when_DmaSg_l996) begin + channels_0_pop_b2m_decrBytes = {1'd0, b2m_fsm_bytesInBurstP1}; + end + end + end + + assign when_DmaSg_l523 = ((channels_0_pop_b2m_memPending == 4'b0000) && (channels_0_fifo_pop_bytes == 14'h0)); + assign when_DmaSg_l532 = (channels_0_descriptorValid && (! channels_0_push_memory)); + assign when_DmaSg_l536 = (! channels_0_pop_b2m_waitFinalRsp); + assign when_DmaSg_l547 = ((channels_0_descriptorValid && (channels_0_pop_b2m_memPending == 4'b0000)) && channels_0_pop_b2m_waitFinalRsp); + assign when_DmaSg_l563 = (channels_0_pop_b2m_memPending != 4'b0000); + assign channels_0_readyForChannelCompletion = 1'b1; + assign when_DmaSg_l575 = (! channels_0_descriptorValid); + always @(*) begin + _zz_when_DmaSg_l593 = 1'b1; + if(channels_0_ctrl_kick) begin + _zz_when_DmaSg_l593 = 1'b0; + end + if(channels_0_ll_valid) begin + _zz_when_DmaSg_l593 = 1'b0; + end + end + + assign when_DmaSg_l593 = (_zz_when_DmaSg_l593 && channels_0_readyForChannelCompletion); + assign channels_0_s2b_full = (channels_0_fifo_push_available < 11'h002); + assign when_DmaSg_l255 = (channels_0_descriptorValid && channels_0_descriptorCompletion); + assign when_DmaSg_l255_1 = (! channels_0_interrupts_completion_enable); + assign when_DmaSg_l255_2 = (channels_0_channelValid && channels_0_channelCompletion); + assign when_DmaSg_l255_3 = (! channels_0_interrupts_onChannelCompletion_enable); + assign when_DmaSg_l255_4 = (! channels_0_interrupts_onLinkedListUpdate_enable); + assign when_DmaSg_l255_5 = (! channels_0_interrupts_s2mPacket_enable); + assign when_DmaSg_l625 = (channels_0_channelStart || channels_0_descriptorStart); + always @(*) begin + channels_1_channelStart = 1'b0; + if(when_BusSlaveFactory_l377_4) begin + if(when_BusSlaveFactory_l379_4) begin + channels_1_channelStart = _zz_channels_1_channelStart[0]; + end + end + if(when_BusSlaveFactory_l377_6) begin + if(when_BusSlaveFactory_l379_6) begin + channels_1_channelStart = _zz_channels_1_channelStart_1[0]; + end + end + end + + always @(*) begin + channels_1_channelCompletion = 1'b0; + if(channels_1_channelValid) begin + if(channels_1_channelStop) begin + if(channels_1_readyToStop) begin + channels_1_channelCompletion = 1'b1; + end + end + end + end + + always @(*) begin + channels_1_descriptorStart = 1'b0; + if(channels_1_ctrl_kick) begin + channels_1_descriptorStart = 1'b1; + end + if(when_DmaSg_l318_1) begin + if(when_DmaSg_l320_1) begin + if(when_DmaSg_l322_1) begin + channels_1_descriptorStart = 1'b1; + end + end + end + end + + always @(*) begin + channels_1_descriptorCompletion = 1'b0; + if(when_DmaSg_l483) begin + channels_1_descriptorCompletion = 1'b1; + end + if(channels_1_channelValid) begin + if(channels_1_channelStop) begin + if(channels_1_readyToStop) begin + channels_1_descriptorCompletion = 1'b1; + end + end + end + end + + always @(*) begin + channels_1_readyToStop = 1'b1; + if(channels_1_ll_waitDone) begin + channels_1_readyToStop = 1'b0; + end + if(when_DmaSg_l562) begin + channels_1_readyToStop = 1'b0; + end + end + + always @(*) begin + channels_1_bytesProbe_incr_valid = 1'b0; + if(when_DmaSg_l874) begin + channels_1_bytesProbe_incr_valid = 1'b1; + end + end + + always @(*) begin + channels_1_bytesProbe_incr_payload = 12'bxxxxxxxxxxxx; + if(when_DmaSg_l874) begin + channels_1_bytesProbe_incr_payload = m2b_rsp_context_length; + end + end + + always @(*) begin + channels_1_ll_sgStart = 1'b0; + if(when_BusSlaveFactory_l377_7) begin + if(when_BusSlaveFactory_l379_7) begin + channels_1_ll_sgStart = _zz_channels_1_ll_sgStart[0]; + end + end + end + + assign channels_1_ll_requestLl = ((((channels_1_channelValid && channels_1_ll_valid) && (! channels_1_channelStop)) && (! channels_1_ll_waitDone)) && ((! channels_1_descriptorValid) || channels_1_ll_requireSync)); + always @(*) begin + channels_1_ll_descriptorUpdated = 1'b0; + if(when_DmaSg_l318_1) begin + if(when_DmaSg_l328_1) begin + channels_1_ll_descriptorUpdated = 1'b1; + end + end + end + + assign when_DmaSg_l318_1 = (((channels_1_ll_valid && channels_1_ll_waitDone) && channels_1_ll_writeDone) && channels_1_ll_readDone); + assign when_DmaSg_l320_1 = (! channels_1_ll_justASync); + assign when_DmaSg_l322_1 = (! channels_1_ll_gotDescriptorStall); + assign when_DmaSg_l328_1 = (! channels_1_ll_head); + assign channels_1_fifo_base = 11'h200; + assign channels_1_fifo_words = 11'h1ff; + always @(*) begin + channels_1_fifo_push_availableDecr = 11'h0; + if(m2b_cmd_s1_valid) begin + if(io_read_cmd_ready) begin + if(when_DmaSg_l828) begin + channels_1_fifo_push_availableDecr = {1'd0, m2b_cmd_s1_fifoPushDecr}; + end + end + end + end + + assign channels_1_fifo_push_ptrWithBase = ((channels_1_fifo_base & (~ channels_1_fifo_words)) | (channels_1_fifo_push_ptr & channels_1_fifo_words)); + assign channels_1_fifo_pop_ptrWithBase = ((channels_1_fifo_base & (~ channels_1_fifo_words)) | (channels_1_fifo_pop_ptr & channels_1_fifo_words)); + assign channels_1_fifo_pop_empty = (channels_1_fifo_pop_ptr == channels_1_fifo_push_ptr); + assign channels_1_fifo_pop_bytes = channels_1_fifo_pop_withoutOverride_exposed; + assign channels_1_fifo_empty = (channels_1_fifo_push_ptr == channels_1_fifo_pop_ptr); + assign channels_1_push_m2b_bytePerBurst = 12'h3ff; + always @(*) begin + channels_1_push_m2b_memPendingIncr = 1'b0; + if(when_DmaSg_l758) begin + if(when_DmaSg_l773) begin + channels_1_push_m2b_memPendingIncr = 1'b1; + end + end + end + + always @(*) begin + channels_1_push_m2b_memPendingDecr = 1'b0; + if(when_DmaSg_l893) begin + channels_1_push_m2b_memPendingDecr = 1'b1; + end + end + + always @(*) begin + channels_1_push_m2b_loadRequest = (((((channels_1_descriptorValid && (! channels_1_channelStop)) && (! channels_1_push_m2b_loadDone)) && channels_1_push_memory) && (_zz_channels_1_push_m2b_loadRequest < channels_1_fifo_push_available)) && (channels_1_push_m2b_memPending != 4'b1111)); + if(when_DmaSg_l486) begin + channels_1_push_m2b_loadRequest = 1'b0; + end + end + + always @(*) begin + channels_1_pop_b2s_veryLastTrigger = 1'b0; + if(when_DmaSg_l847) begin + if(when_DmaSg_l848) begin + channels_1_pop_b2s_veryLastTrigger = 1'b1; + end + end + end + + assign when_DmaSg_l474 = (channels_1_pop_b2s_veryLastTrigger && channels_1_pop_b2s_last); + assign when_DmaSg_l483 = ((((channels_1_descriptorValid && (! channels_1_pop_memory)) && channels_1_push_memory) && channels_1_push_m2b_loadDone) && (channels_1_push_m2b_memPending == 4'b0000)); + assign when_DmaSg_l486 = (((! channels_1_pop_memory) && channels_1_pop_b2s_veryLastValid) && (channels_1_push_m2b_bytesLeft <= _zz_when_DmaSg_l486)); + assign when_DmaSg_l562 = (channels_1_push_m2b_memPending != 4'b0000); + always @(*) begin + channels_1_readyForChannelCompletion = 1'b1; + if(when_DmaSg_l566) begin + channels_1_readyForChannelCompletion = 1'b0; + end + end + + assign when_DmaSg_l566 = ((! channels_1_pop_memory) && (! channels_1_fifo_pop_empty)); + assign when_DmaSg_l575_1 = (! channels_1_descriptorValid); + always @(*) begin + _zz_when_DmaSg_l593_1 = 1'b1; + if(channels_1_ctrl_kick) begin + _zz_when_DmaSg_l593_1 = 1'b0; + end + if(channels_1_ll_valid) begin + _zz_when_DmaSg_l593_1 = 1'b0; + end + end + + assign when_DmaSg_l593_1 = (_zz_when_DmaSg_l593_1 && channels_1_readyForChannelCompletion); + assign channels_1_s2b_full = (channels_1_fifo_push_available < 11'h002); + assign when_DmaSg_l255_6 = (channels_1_descriptorValid && channels_1_descriptorCompletion); + assign when_DmaSg_l255_7 = (! channels_1_interrupts_completion_enable); + assign when_DmaSg_l255_8 = (channels_1_channelValid && channels_1_channelCompletion); + assign when_DmaSg_l255_9 = (! channels_1_interrupts_onChannelCompletion_enable); + assign when_DmaSg_l255_10 = (! channels_1_interrupts_onLinkedListUpdate_enable); + assign when_DmaSg_l625_1 = (channels_1_channelStart || channels_1_descriptorStart); + assign io_inputs_0_fire = (io_inputs_0_valid && io_inputs_0_ready); + assign when_package_l12 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0000)); + assign when_package_l12_1 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0001)); + assign when_package_l12_2 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0010)); + assign when_package_l12_3 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0011)); + assign when_package_l12_4 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0100)); + assign when_package_l12_5 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0101)); + assign when_package_l12_6 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0110)); + assign when_package_l12_7 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0111)); + assign when_package_l12_8 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1000)); + assign when_package_l12_9 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1001)); + assign when_package_l12_10 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1010)); + assign when_package_l12_11 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1011)); + assign when_package_l12_12 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1100)); + assign when_package_l12_13 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1101)); + assign when_package_l12_14 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1110)); + assign when_package_l12_15 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1111)); + assign s2b_0_cmd_firsts = {io_inputs_0_payload_last_regNextWhen_15,{io_inputs_0_payload_last_regNextWhen_14,{io_inputs_0_payload_last_regNextWhen_13,{io_inputs_0_payload_last_regNextWhen_12,{io_inputs_0_payload_last_regNextWhen_11,{io_inputs_0_payload_last_regNextWhen_10,{io_inputs_0_payload_last_regNextWhen_9,{io_inputs_0_payload_last_regNextWhen_8,{io_inputs_0_payload_last_regNextWhen_7,{io_inputs_0_payload_last_regNextWhen_6,{_zz_s2b_0_cmd_firsts,_zz_s2b_0_cmd_firsts_1}}}}}}}}}}}; + assign s2b_0_cmd_first = s2b_0_cmd_firsts[io_inputs_0_payload_sink]; + assign s2b_0_cmd_channelsOh = ((((channels_0_channelValid && (s2b_0_cmd_first || (! channels_0_push_s2b_waitFirst))) && (! channels_0_push_memory)) && 1'b1) && (io_inputs_0_payload_sink == 4'b0000)); + assign s2b_0_cmd_noHit = (! (|s2b_0_cmd_channelsOh)); + assign s2b_0_cmd_channelsFull = (channels_0_s2b_full || (channels_0_push_s2b_packetLock && io_inputs_0_payload_last)); + always @(*) begin + io_inputs_0_thrown_valid = io_inputs_0_valid; + if(s2b_0_cmd_noHit) begin + io_inputs_0_thrown_valid = 1'b0; + end + end + + always @(*) begin + io_inputs_0_ready = io_inputs_0_thrown_ready; + if(s2b_0_cmd_noHit) begin + io_inputs_0_ready = 1'b1; + end + end + + assign io_inputs_0_thrown_payload_data = io_inputs_0_payload_data; + assign io_inputs_0_thrown_payload_mask = io_inputs_0_payload_mask; + assign io_inputs_0_thrown_payload_sink = io_inputs_0_payload_sink; + assign io_inputs_0_thrown_payload_last = io_inputs_0_payload_last; + assign _zz_io_inputs_0_thrown_ready = (! (|(s2b_0_cmd_channelsOh & s2b_0_cmd_channelsFull))); + assign s2b_0_cmd_sinkHalted_valid = (io_inputs_0_thrown_valid && _zz_io_inputs_0_thrown_ready); + assign io_inputs_0_thrown_ready = (s2b_0_cmd_sinkHalted_ready && _zz_io_inputs_0_thrown_ready); + assign s2b_0_cmd_sinkHalted_payload_data = io_inputs_0_thrown_payload_data; + assign s2b_0_cmd_sinkHalted_payload_mask = io_inputs_0_thrown_payload_mask; + assign s2b_0_cmd_sinkHalted_payload_sink = io_inputs_0_thrown_payload_sink; + assign s2b_0_cmd_sinkHalted_payload_last = io_inputs_0_thrown_payload_last; + assign _zz_s2b_0_cmd_byteCount = 4'b0000; + assign _zz_s2b_0_cmd_byteCount_1 = 4'b0001; + assign _zz_s2b_0_cmd_byteCount_2 = 4'b0001; + assign _zz_s2b_0_cmd_byteCount_3 = 4'b0010; + assign _zz_s2b_0_cmd_byteCount_4 = 4'b0001; + assign _zz_s2b_0_cmd_byteCount_5 = 4'b0010; + assign _zz_s2b_0_cmd_byteCount_6 = 4'b0010; + assign _zz_s2b_0_cmd_byteCount_7 = 4'b0011; + assign s2b_0_cmd_byteCount = (_zz_s2b_0_cmd_byteCount_8 + _zz_s2b_0_cmd_byteCount_13); + assign s2b_0_cmd_context_channel = s2b_0_cmd_channelsOh; + assign s2b_0_cmd_context_bytes = s2b_0_cmd_byteCount; + assign s2b_0_cmd_context_flush = io_inputs_0_payload_last; + assign s2b_0_cmd_context_packet = io_inputs_0_payload_last; + assign s2b_0_cmd_sinkHalted_ready = memory_core_io_writes_0_cmd_ready; + assign memory_core_io_writes_0_cmd_payload_address = channels_0_fifo_push_ptrWithBase[9:0]; + assign memory_core_io_writes_0_cmd_payload_context = {s2b_0_cmd_context_packet,{s2b_0_cmd_context_flush,{s2b_0_cmd_context_bytes,s2b_0_cmd_context_channel}}}; + assign memory_core_io_writes_0_cmd_fire = (s2b_0_cmd_sinkHalted_valid && memory_core_io_writes_0_cmd_ready); + assign when_DmaSg_l665 = (s2b_0_cmd_channelsOh[0] && memory_core_io_writes_0_cmd_fire); + assign _zz_s2b_0_rsp_context_channel = memory_core_io_writes_0_rsp_payload_context; + assign s2b_0_rsp_context_channel = _zz_s2b_0_rsp_context_channel[0 : 0]; + assign s2b_0_rsp_context_bytes = _zz_s2b_0_rsp_context_channel[4 : 1]; + assign s2b_0_rsp_context_flush = _zz_s2b_0_rsp_context_channel[5]; + assign s2b_0_rsp_context_packet = _zz_s2b_0_rsp_context_channel[6]; + assign _zz_channels_0_fifo_pop_bytesIncr_value = (memory_core_io_writes_0_rsp_valid && s2b_0_rsp_context_channel[0]); + assign when_DmaSg_l679 = (_zz_channels_0_fifo_pop_bytesIncr_value && s2b_0_rsp_context_packet); + assign when_DmaSg_l681 = (_zz_channels_0_fifo_pop_bytesIncr_value && s2b_0_rsp_context_flush); + assign when_DmaSg_l682 = (_zz_channels_0_fifo_pop_bytesIncr_value && s2b_0_rsp_context_packet); + assign b2s_0_cmd_channelsOh = (((channels_1_channelValid && (! channels_1_pop_memory)) && 1'b1) && (! channels_1_fifo_pop_empty)); + assign b2s_0_cmd_veryLastPtr = channels_1_pop_b2s_veryLastPtr; + assign b2s_0_cmd_address = channels_1_fifo_pop_ptrWithBase; + assign b2s_0_cmd_context_channel = b2s_0_cmd_channelsOh; + assign b2s_0_cmd_context_veryLast = ((channels_1_pop_b2s_veryLastValid && (b2s_0_cmd_address[10 : 1] == b2s_0_cmd_veryLastPtr[10 : 1])) && (b2s_0_cmd_address[0 : 0] == 1'b1)); + assign b2s_0_cmd_context_endPacket = channels_1_pop_b2s_veryLastEndPacket; + assign memory_core_io_reads_0_cmd_valid = (|b2s_0_cmd_channelsOh); + assign memory_core_io_reads_0_cmd_payload_address = b2s_0_cmd_address[9:0]; + assign memory_core_io_reads_0_cmd_payload_context = {b2s_0_cmd_context_endPacket,{b2s_0_cmd_context_veryLast,b2s_0_cmd_context_channel}}; + assign _zz_b2s_0_rsp_context_channel = memory_core_io_reads_0_rsp_payload_context; + assign b2s_0_rsp_context_channel = _zz_b2s_0_rsp_context_channel[0 : 0]; + assign b2s_0_rsp_context_veryLast = _zz_b2s_0_rsp_context_channel[1]; + assign b2s_0_rsp_context_endPacket = _zz_b2s_0_rsp_context_channel[2]; + assign io_outputs_0_valid = memory_core_io_reads_0_rsp_valid; + assign io_outputs_0_payload_data = memory_core_io_reads_0_rsp_payload_data; + assign io_outputs_0_payload_mask = memory_core_io_reads_0_rsp_payload_mask; + assign io_outputs_0_payload_sink = channels_1_pop_b2s_sinkId; + assign io_outputs_0_payload_last = (b2s_0_rsp_context_veryLast && b2s_0_rsp_context_endPacket); + assign io_outputs_0_fire = (io_outputs_0_valid && io_outputs_0_ready); + assign when_DmaSg_l725 = (io_outputs_0_fire && b2s_0_rsp_context_veryLast); + assign when_DmaSg_l726 = b2s_0_rsp_context_channel[0]; + assign _zz_m2b_cmd_s0_priority_masked = channels_1_priority; + assign m2b_cmd_s0_priority_masked = (channels_1_push_m2b_loadRequest && (channels_1_priority == _zz_m2b_cmd_s0_priority_masked)); + assign _zz_m2b_cmd_s0_priority_chosenOh = m2b_cmd_s0_priority_masked; + assign _zz_m2b_cmd_s0_priority_chosenOh_1 = {_zz_m2b_cmd_s0_priority_chosenOh,_zz_m2b_cmd_s0_priority_chosenOh}; + assign _zz_m2b_cmd_s0_priority_chosenOh_2 = (_zz_m2b_cmd_s0_priority_chosenOh_1 & (~ _zz__zz_m2b_cmd_s0_priority_chosenOh_2)); + assign m2b_cmd_s0_priority_chosenOh = (_zz_m2b_cmd_s0_priority_chosenOh_2[1 : 1] | _zz_m2b_cmd_s0_priority_chosenOh_2[0 : 0]); + assign m2b_cmd_s0_priority_weightLast = (channels_1_weight == m2b_cmd_s0_priority_counter); + assign m2b_cmd_s0_priority_contextNext = (m2b_cmd_s0_priority_weightLast ? m2b_cmd_s0_priority_chosenOh[0 : 0] : m2b_cmd_s0_priority_chosenOh); + assign when_DmaSg_l758 = (! m2b_cmd_s0_valid); + assign when_DmaSg_l760 = (|channels_1_push_m2b_loadRequest); + assign when_DmaSg_l763 = (2'b00 == _zz_m2b_cmd_s0_priority_masked); + assign when_DmaSg_l763_1 = (2'b01 == _zz_m2b_cmd_s0_priority_masked); + assign when_DmaSg_l763_2 = (2'b10 == _zz_m2b_cmd_s0_priority_masked); + assign when_DmaSg_l763_3 = (2'b11 == _zz_m2b_cmd_s0_priority_masked); + assign when_DmaSg_l773 = (channels_1_push_m2b_loadRequest && m2b_cmd_s0_priority_chosenOh[0]); + assign m2b_cmd_s0_address = channels_1_push_m2b_address; + assign m2b_cmd_s0_bytesLeft = channels_1_push_m2b_bytesLeft; + assign m2b_cmd_s0_readAddressBurstRange = m2b_cmd_s0_address[11 : 0]; + assign m2b_cmd_s0_lengthHead = ((~ m2b_cmd_s0_readAddressBurstRange) & channels_1_push_m2b_bytePerBurst); + assign m2b_cmd_s0_length = _zz_m2b_cmd_s0_length[11:0]; + assign m2b_cmd_s0_lastBurst = (m2b_cmd_s0_bytesLeft == _zz_m2b_cmd_s0_lastBurst); + assign m2b_cmd_s1_context_start = m2b_cmd_s1_address[3:0]; + assign m2b_cmd_s1_context_stop = _zz_m2b_cmd_s1_context_stop[3:0]; + assign m2b_cmd_s1_context_last = m2b_cmd_s1_lastBurst; + assign m2b_cmd_s1_context_length = m2b_cmd_s1_length; + always @(*) begin + io_read_cmd_valid = 1'b0; + if(m2b_cmd_s1_valid) begin + io_read_cmd_valid = 1'b1; + end + end + + assign io_read_cmd_payload_last = 1'b1; + assign io_read_cmd_payload_fragment_opcode = 1'b0; + assign io_read_cmd_payload_fragment_address = m2b_cmd_s1_address; + assign io_read_cmd_payload_fragment_length = m2b_cmd_s1_length; + assign io_read_cmd_payload_fragment_context = {m2b_cmd_s1_context_last,{m2b_cmd_s1_context_length,{m2b_cmd_s1_context_stop,m2b_cmd_s1_context_start}}}; + assign m2b_cmd_s1_addressNext = (_zz_m2b_cmd_s1_addressNext + 32'h00000001); + assign m2b_cmd_s1_byteLeftNext = (_zz_m2b_cmd_s1_byteLeftNext - 26'h0000001); + assign m2b_cmd_s1_fifoPushDecr = (_zz_m2b_cmd_s1_fifoPushDecr >>> 2'd3); + assign when_DmaSg_l828 = 1'b1; + assign _zz_m2b_rsp_context_start = io_read_rsp_payload_fragment_context; + assign m2b_rsp_context_start = _zz_m2b_rsp_context_start[3 : 0]; + assign m2b_rsp_context_stop = _zz_m2b_rsp_context_start[7 : 4]; + assign m2b_rsp_context_length = _zz_m2b_rsp_context_start[19 : 8]; + assign m2b_rsp_context_last = _zz_m2b_rsp_context_start[20]; + assign m2b_rsp_veryLast = (m2b_rsp_context_last && io_read_rsp_payload_last); + assign io_read_rsp_fire = (io_read_rsp_valid && io_read_rsp_ready); + assign when_DmaSg_l847 = (io_read_rsp_fire && m2b_rsp_veryLast); + assign when_DmaSg_l848 = 1'b1; + always @(*) begin + memory_core_io_writes_1_cmd_payload_mask[0] = ((! (m2b_rsp_first && (4'b0000 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0000)))); + memory_core_io_writes_1_cmd_payload_mask[1] = ((! (m2b_rsp_first && (4'b0001 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0001)))); + memory_core_io_writes_1_cmd_payload_mask[2] = ((! (m2b_rsp_first && (4'b0010 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0010)))); + memory_core_io_writes_1_cmd_payload_mask[3] = ((! (m2b_rsp_first && (4'b0011 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0011)))); + memory_core_io_writes_1_cmd_payload_mask[4] = ((! (m2b_rsp_first && (4'b0100 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0100)))); + memory_core_io_writes_1_cmd_payload_mask[5] = ((! (m2b_rsp_first && (4'b0101 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0101)))); + memory_core_io_writes_1_cmd_payload_mask[6] = ((! (m2b_rsp_first && (4'b0110 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0110)))); + memory_core_io_writes_1_cmd_payload_mask[7] = ((! (m2b_rsp_first && (4'b0111 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0111)))); + memory_core_io_writes_1_cmd_payload_mask[8] = ((! (m2b_rsp_first && (4'b1000 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1000)))); + memory_core_io_writes_1_cmd_payload_mask[9] = ((! (m2b_rsp_first && (4'b1001 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1001)))); + memory_core_io_writes_1_cmd_payload_mask[10] = ((! (m2b_rsp_first && (4'b1010 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1010)))); + memory_core_io_writes_1_cmd_payload_mask[11] = ((! (m2b_rsp_first && (4'b1011 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1011)))); + memory_core_io_writes_1_cmd_payload_mask[12] = ((! (m2b_rsp_first && (4'b1100 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1100)))); + memory_core_io_writes_1_cmd_payload_mask[13] = ((! (m2b_rsp_first && (4'b1101 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1101)))); + memory_core_io_writes_1_cmd_payload_mask[14] = ((! (m2b_rsp_first && (4'b1110 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1110)))); + memory_core_io_writes_1_cmd_payload_mask[15] = ((! (m2b_rsp_first && (4'b1111 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1111)))); + end + + assign m2b_rsp_writeContext_last = m2b_rsp_veryLast; + assign m2b_rsp_writeContext_lastOfBurst = io_read_rsp_payload_last; + assign m2b_rsp_writeContext_loadByteInNextBeat = ({1'b0,(io_read_rsp_payload_last ? m2b_rsp_context_stop : 4'b1111)} - {1'b0,(m2b_rsp_first ? m2b_rsp_context_start : 4'b0000)}); + assign memory_core_io_writes_1_cmd_payload_address = channels_1_fifo_push_ptrWithBase[9:0]; + assign io_read_rsp_ready = memory_core_io_writes_1_cmd_ready; + assign memory_core_io_writes_1_cmd_payload_context = {m2b_rsp_writeContext_loadByteInNextBeat,{m2b_rsp_writeContext_lastOfBurst,m2b_rsp_writeContext_last}}; + assign memory_core_io_writes_1_cmd_fire = (io_read_rsp_valid && memory_core_io_writes_1_cmd_ready); + assign _zz_channels_1_fifo_push_ptrIncr_value = (memory_core_io_writes_1_cmd_fire && 1'b1); + assign when_DmaSg_l874 = (_zz_channels_1_fifo_push_ptrIncr_value && io_read_rsp_payload_last); + assign _zz_m2b_writeRsp_context_last = memory_core_io_writes_1_rsp_payload_context; + assign m2b_writeRsp_context_last = _zz_m2b_writeRsp_context_last[0]; + assign m2b_writeRsp_context_lastOfBurst = _zz_m2b_writeRsp_context_last[1]; + assign m2b_writeRsp_context_loadByteInNextBeat = _zz_m2b_writeRsp_context_last[6 : 2]; + assign _zz_channels_1_fifo_pop_bytesIncr_value = (memory_core_io_writes_1_rsp_valid && 1'b1); + assign when_DmaSg_l893 = (_zz_channels_1_fifo_pop_bytesIncr_value && m2b_writeRsp_context_lastOfBurst); + assign _zz_b2m_fsm_arbiter_logic_priority_masked = channels_0_priority; + assign b2m_fsm_arbiter_logic_priority_masked = (channels_0_pop_b2m_request && (channels_0_priority == _zz_b2m_fsm_arbiter_logic_priority_masked)); + assign _zz_b2m_fsm_arbiter_logic_priority_chosenOh = b2m_fsm_arbiter_logic_priority_masked; + assign _zz_b2m_fsm_arbiter_logic_priority_chosenOh_1 = {_zz_b2m_fsm_arbiter_logic_priority_chosenOh,_zz_b2m_fsm_arbiter_logic_priority_chosenOh}; + assign _zz_b2m_fsm_arbiter_logic_priority_chosenOh_2 = (_zz_b2m_fsm_arbiter_logic_priority_chosenOh_1 & (~ _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2)); + assign b2m_fsm_arbiter_logic_priority_chosenOh = (_zz_b2m_fsm_arbiter_logic_priority_chosenOh_2[1 : 1] | _zz_b2m_fsm_arbiter_logic_priority_chosenOh_2[0 : 0]); + assign b2m_fsm_arbiter_logic_priority_weightLast = (channels_0_weight == b2m_fsm_arbiter_logic_priority_counter); + assign b2m_fsm_arbiter_logic_priority_contextNext = (b2m_fsm_arbiter_logic_priority_weightLast ? b2m_fsm_arbiter_logic_priority_chosenOh[0 : 0] : b2m_fsm_arbiter_logic_priority_chosenOh); + assign when_DmaSg_l758_1 = (! b2m_fsm_arbiter_logic_valid); + assign when_DmaSg_l760_1 = (|channels_0_pop_b2m_request); + assign when_DmaSg_l763_4 = (2'b00 == _zz_b2m_fsm_arbiter_logic_priority_masked); + assign when_DmaSg_l763_5 = (2'b01 == _zz_b2m_fsm_arbiter_logic_priority_masked); + assign when_DmaSg_l763_6 = (2'b10 == _zz_b2m_fsm_arbiter_logic_priority_masked); + assign when_DmaSg_l763_7 = (2'b11 == _zz_b2m_fsm_arbiter_logic_priority_masked); + assign when_DmaSg_l773_1 = (channels_0_pop_b2m_request && b2m_fsm_arbiter_logic_priority_chosenOh[0]); + assign when_DmaSg_l935 = ((! b2m_fsm_sel_valid) && b2m_fsm_arbiter_logic_valid); + assign b2m_fsm_bytesInBurstP1 = ({1'b0,b2m_fsm_sel_bytesInBurst} + _zz_b2m_fsm_bytesInBurstP1); + assign b2m_fsm_addressNext = (b2m_fsm_sel_address + _zz_b2m_fsm_addressNext); + assign b2m_fsm_bytesLeftNext = ({1'b0,b2m_fsm_sel_bytesLeft} - _zz_b2m_fsm_bytesLeftNext); + assign b2m_fsm_isFinalCmd = b2m_fsm_bytesLeftNext[26]; + assign b2m_fsm_s0 = (b2m_fsm_sel_valid && (! b2m_fsm_sel_valid_regNext)); + assign when_DmaSg_l986 = (! b2m_fsm_sel_valid); + assign _zz_b2m_fsm_sel_bytesInBurst = (b2m_fsm_sel_bytesInFifo - 14'h0001); + assign _zz_b2m_fsm_sel_bytesInBurst_1 = ((_zz__zz_b2m_fsm_sel_bytesInBurst_1 < b2m_fsm_sel_bytesLeft) ? _zz__zz_b2m_fsm_sel_bytesInBurst_1_1 : b2m_fsm_sel_bytesLeft); + assign _zz_b2m_fsm_sel_bytesInBurst_2 = (b2m_fsm_sel_bytePerBurst - (_zz__zz_b2m_fsm_sel_bytesInBurst_2 & b2m_fsm_sel_bytePerBurst)); + assign b2m_fsm_fifoCompletion = (_zz_b2m_fsm_fifoCompletion == _zz_b2m_fsm_fifoCompletion_1); + assign when_DmaSg_l996 = 1'b1; + assign when_DmaSg_l1001 = (! b2m_fsm_fifoCompletion); + assign when_DmaSg_l1013 = (b2m_fsm_sel_valid && b2m_fsm_sel_ready); + always @(*) begin + b2m_fsm_sel_ready = 1'b0; + if(when_DmaSg_l1102) begin + b2m_fsm_sel_ready = 1'b1; + end + end + + assign b2m_fsm_fetch_context_ptr = channels_0_fifo_pop_ptr; + assign b2m_fsm_fetch_context_toggle = b2m_fsm_toggle; + assign memory_core_io_reads_1_cmd_payload_address = b2m_fsm_sel_ptr[9:0]; + assign memory_core_io_reads_1_cmd_payload_context = {b2m_fsm_fetch_context_toggle,b2m_fsm_fetch_context_ptr}; + assign when_DmaSg_l1033 = (b2m_fsm_sel_valid && memory_core_io_reads_1_cmd_ready); + assign _zz_b2m_fsm_aggregate_context_ptr = memory_core_io_reads_1_rsp_payload_context; + assign b2m_fsm_aggregate_context_ptr = _zz_b2m_fsm_aggregate_context_ptr[10 : 0]; + assign b2m_fsm_aggregate_context_toggle = _zz_b2m_fsm_aggregate_context_ptr[11]; + assign memory_core_io_reads_1_rsp_s2mPipe_valid = (memory_core_io_reads_1_rsp_valid || (! memory_core_io_reads_1_rsp_rValidN)); + assign memory_core_io_reads_1_rsp_s2mPipe_payload_data = (memory_core_io_reads_1_rsp_rValidN ? memory_core_io_reads_1_rsp_payload_data : memory_core_io_reads_1_rsp_rData_data); + assign memory_core_io_reads_1_rsp_s2mPipe_payload_mask = (memory_core_io_reads_1_rsp_rValidN ? memory_core_io_reads_1_rsp_payload_mask : memory_core_io_reads_1_rsp_rData_mask); + assign memory_core_io_reads_1_rsp_s2mPipe_payload_context = (memory_core_io_reads_1_rsp_rValidN ? memory_core_io_reads_1_rsp_payload_context : memory_core_io_reads_1_rsp_rData_context); + assign when_Stream_l445 = (b2m_fsm_aggregate_context_toggle != b2m_fsm_toggle); + always @(*) begin + b2m_fsm_aggregate_memoryPort_valid = memory_core_io_reads_1_rsp_s2mPipe_valid; + if(when_Stream_l445) begin + b2m_fsm_aggregate_memoryPort_valid = 1'b0; + end + end + + always @(*) begin + memory_core_io_reads_1_rsp_s2mPipe_ready = b2m_fsm_aggregate_memoryPort_ready; + if(when_Stream_l445) begin + memory_core_io_reads_1_rsp_s2mPipe_ready = 1'b1; + end + end + + assign b2m_fsm_aggregate_memoryPort_payload_data = memory_core_io_reads_1_rsp_s2mPipe_payload_data; + assign b2m_fsm_aggregate_memoryPort_payload_mask = memory_core_io_reads_1_rsp_s2mPipe_payload_mask; + assign b2m_fsm_aggregate_memoryPort_payload_context = memory_core_io_reads_1_rsp_s2mPipe_payload_context; + assign b2m_fsm_aggregate_memoryPort_fire = (b2m_fsm_aggregate_memoryPort_valid && b2m_fsm_aggregate_memoryPort_ready); + assign when_DmaSg_l1050 = (! (b2m_fsm_sel_valid && (! b2m_fsm_sel_ready))); + assign b2m_fsm_aggregate_bytesToSkip = channels_0_pop_b2m_bytesToSkip; + assign b2m_fsm_aggregate_bytesToSkipMask = {((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1111)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1110)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= _zz_b2m_fsm_aggregate_bytesToSkipMask)),{(_zz_b2m_fsm_aggregate_bytesToSkipMask_1 || _zz_b2m_fsm_aggregate_bytesToSkipMask_2),{_zz_b2m_fsm_aggregate_bytesToSkipMask_3,{_zz_b2m_fsm_aggregate_bytesToSkipMask_4,_zz_b2m_fsm_aggregate_bytesToSkipMask_5}}}}}}; + assign b2m_fsm_aggregate_memoryPort_ready = b2m_fsm_aggregate_engine_io_input_ready; + assign b2m_fsm_aggregate_engine_io_input_payload_mask = (b2m_fsm_aggregate_memoryPort_payload_mask & b2m_fsm_aggregate_bytesToSkipMask); + assign b2m_fsm_aggregate_engine_io_offset = b2m_fsm_sel_address[3:0]; + assign b2m_fsm_aggregate_engine_io_flush = (! _zz_io_flush); + assign b2m_fsm_cmd_maskFirstTrigger = b2m_fsm_sel_address[3:0]; + assign b2m_fsm_cmd_maskLastTriggerComb = (b2m_fsm_cmd_maskFirstTrigger + _zz_b2m_fsm_cmd_maskLastTriggerComb); + assign b2m_fsm_cmd_maskFirst = {(b2m_fsm_cmd_maskFirstTrigger <= 4'b1111),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1110),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1101),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1100),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1011),{(b2m_fsm_cmd_maskFirstTrigger <= _zz_b2m_fsm_cmd_maskFirst),{_zz_b2m_fsm_cmd_maskFirst_1,{_zz_b2m_fsm_cmd_maskFirst_2,_zz_b2m_fsm_cmd_maskFirst_3}}}}}}}}; + assign b2m_fsm_cmd_enoughAggregation = (((b2m_fsm_s2 && b2m_fsm_sel_valid) && (! b2m_fsm_aggregate_engine_io_flush)) && (io_write_cmd_payload_last ? ((b2m_fsm_aggregate_engine_io_output_mask & b2m_fsm_cmd_maskLast) == b2m_fsm_cmd_maskLast) : (&b2m_fsm_aggregate_engine_io_output_mask))); + assign io_write_cmd_fire = (io_write_cmd_valid && io_write_cmd_ready); + assign io_write_cmd_valid = b2m_fsm_cmd_enoughAggregation; + assign io_write_cmd_payload_last = (b2m_fsm_beatCounter == 8'h0); + assign io_write_cmd_payload_fragment_address = b2m_fsm_sel_address; + assign io_write_cmd_payload_fragment_opcode = 1'b1; + assign io_write_cmd_payload_fragment_data = b2m_fsm_aggregate_engine_io_output_data; + assign io_write_cmd_payload_fragment_mask = (~ ((io_write_cmd_payload_first ? (~ b2m_fsm_cmd_maskFirst) : 16'h0) | (io_write_cmd_payload_last ? (~ b2m_fsm_cmd_maskLast) : 16'h0))); + assign io_write_cmd_payload_fragment_length = b2m_fsm_sel_bytesInBurst; + assign b2m_fsm_cmd_doPtrIncr = (b2m_fsm_sel_valid && (b2m_fsm_aggregate_engine_io_output_consumed || ((io_write_cmd_fire && io_write_cmd_payload_last) && (b2m_fsm_aggregate_engine_io_output_usedUntil == 4'b1111)))); + assign b2m_fsm_cmd_context_length = b2m_fsm_sel_bytesInBurst; + assign b2m_fsm_cmd_context_doPacketSync = (b2m_fsm_sel_packet && b2m_fsm_fifoCompletion); + assign io_write_cmd_payload_fragment_context = {b2m_fsm_cmd_context_doPacketSync,b2m_fsm_cmd_context_length}; + assign when_DmaSg_l1102 = (io_write_cmd_fire && io_write_cmd_payload_last); + assign io_write_rsp_ready = 1'b1; + assign _zz_b2m_rsp_context_length = io_write_rsp_payload_fragment_context; + assign b2m_rsp_context_length = _zz_b2m_rsp_context_length[11 : 0]; + assign b2m_rsp_context_doPacketSync = _zz_b2m_rsp_context_length[12]; + assign io_write_rsp_fire = (io_write_rsp_valid && io_write_rsp_ready); + assign when_DmaSg_l1116 = 1'b1; + assign _zz_ll_arbiter_head = {channels_1_ll_requestLl,channels_0_ll_requestLl}; + assign _zz_ll_arbiter_head_1 = _zz__zz_ll_arbiter_head_1[1]; + assign ll_arbiter_head = (_zz_ll_arbiter_head_2[0] ? channels_0_ll_head : channels_1_ll_head); + assign ll_arbiter_isJustASink = (_zz_ll_arbiter_isJustASink[0] ? channels_0_descriptorValid : channels_1_descriptorValid); + assign ll_arbiter_doDescriptorStall = (_zz_ll_arbiter_doDescriptorStall[0] ? ((! channels_0_ll_controlNoCompletion) || channels_0_ll_gotDescriptorStall) : ((! channels_1_ll_controlNoCompletion) || channels_1_ll_gotDescriptorStall)); + assign ll_arbiter_onSgStream = (_zz_ll_arbiter_onSgStream[0] ? channels_0_ll_onSgStream : channels_1_ll_onSgStream); + assign when_DmaSg_l1149 = (! ll_cmd_valid); + assign when_DmaSg_l1148 = (! ll_cmd_valid); + assign when_DmaSg_l1148_1 = (! ll_cmd_valid); + assign when_DmaSg_l1148_2 = (! ll_cmd_valid); + assign when_DmaSg_l1148_3 = (! ll_cmd_valid); + assign when_DmaSg_l1154 = (! ll_cmd_valid); + assign when_DmaSg_l1155 = (! ll_cmd_valid); + assign when_DmaSg_l1156 = (! ll_cmd_valid); + assign when_DmaSg_l1160 = (! ll_cmd_valid); + assign when_DmaSg_l1161 = (|{_zz_ll_arbiter_head_1,channels_0_ll_requestLl}); + assign when_DmaSg_l1169 = (! ll_arbiter_isJustASink); + assign when_DmaSg_l1169_1 = (! ll_arbiter_isJustASink); + assign when_DmaSg_l1177 = (ll_cmd_writeFired && ll_cmd_readFired); + assign ll_cmd_context_channel = ll_cmd_oh_1; + assign io_sgRead_cmd_valid = ((ll_cmd_valid && (! ll_cmd_readFired)) && (! ll_cmd_onSgStream)); + assign io_sgRead_cmd_payload_last = 1'b1; + assign io_sgRead_cmd_payload_fragment_address = {ll_cmd_ptrNext[31 : 5],5'h0}; + assign io_sgRead_cmd_payload_fragment_length = 5'h1f; + assign io_sgRead_cmd_payload_fragment_opcode = 1'b0; + assign io_sgRead_cmd_payload_fragment_context = ll_cmd_context_channel; + assign io_sgWrite_cmd_valid = ((ll_cmd_valid && (! ll_cmd_writeFired)) && (! ll_cmd_onSgStream)); + assign io_sgWrite_cmd_payload_last = 1'b1; + assign io_sgWrite_cmd_payload_fragment_address = {ll_cmd_ptr[31 : 5],5'h0}; + assign io_sgWrite_cmd_payload_fragment_length = 2'b11; + assign io_sgWrite_cmd_payload_fragment_opcode = 1'b1; + assign io_sgWrite_cmd_payload_fragment_context = ll_cmd_context_channel; + assign ll_cmd_writeMaskSplit_0 = io_sgWrite_cmd_payload_fragment_mask[3 : 0]; + assign ll_cmd_writeMaskSplit_1 = io_sgWrite_cmd_payload_fragment_mask[7 : 4]; + assign ll_cmd_writeMaskSplit_2 = io_sgWrite_cmd_payload_fragment_mask[11 : 8]; + assign ll_cmd_writeMaskSplit_3 = io_sgWrite_cmd_payload_fragment_mask[15 : 12]; + assign ll_cmd_writeDataSplit_0 = io_sgWrite_cmd_payload_fragment_data[31 : 0]; + assign ll_cmd_writeDataSplit_1 = io_sgWrite_cmd_payload_fragment_data[63 : 32]; + assign ll_cmd_writeDataSplit_2 = io_sgWrite_cmd_payload_fragment_data[95 : 64]; + assign ll_cmd_writeDataSplit_3 = io_sgWrite_cmd_payload_fragment_data[127 : 96]; + assign _zz_1 = zz_io_sgWrite_cmd_payload_fragment_mask(1'b0); + always @(*) io_sgWrite_cmd_payload_fragment_mask = _zz_1; + always @(*) begin + io_sgWrite_cmd_payload_fragment_data[63 : 32] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + io_sgWrite_cmd_payload_fragment_data[95 : 64] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + io_sgWrite_cmd_payload_fragment_data[127 : 96] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + io_sgWrite_cmd_payload_fragment_data[31 : 0] = 32'h0; + io_sgWrite_cmd_payload_fragment_data[26 : 0] = ll_cmd_bytesDone; + io_sgWrite_cmd_payload_fragment_data[30] = ll_cmd_endOfPacket; + io_sgWrite_cmd_payload_fragment_data[31] = ((! ll_cmd_isJustASink) && ll_cmd_doDescriptorStall); + end + + assign io_sgRead_cmd_fire = (io_sgRead_cmd_valid && io_sgRead_cmd_ready); + assign io_sgWrite_cmd_fire = (io_sgWrite_cmd_valid && io_sgWrite_cmd_ready); + assign ll_readRsp_context_channel = io_sgRead_rsp_payload_fragment_context[0 : 0]; + assign _zz_ll_readRsp_oh_0 = (2'b01 <<< ll_readRsp_context_channel); + assign ll_readRsp_oh_0 = _zz_ll_readRsp_oh_0[0]; + assign ll_readRsp_oh_1 = _zz_ll_readRsp_oh_0[1]; + assign io_sgRead_rsp_ready = 1'b1; + assign io_sgRead_rsp_fire = (io_sgRead_rsp_valid && io_sgRead_rsp_ready); + assign when_DmaSg_l1248 = (1'b0 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_1 = (1'b1 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_2 = (1'b1 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_3 = (1'b0 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_4 = (1'b0 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_5 = (1'b0 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_6 = (1'b0 == ll_readRsp_beatCounter); + assign when_DmaSg_l1271 = (io_sgRead_rsp_fire && io_sgRead_rsp_payload_last); + assign ll_writeRsp_context_channel = io_sgWrite_rsp_payload_fragment_context[0 : 0]; + assign _zz_ll_writeRsp_oh_0 = (2'b01 <<< ll_writeRsp_context_channel); + assign ll_writeRsp_oh_0 = _zz_ll_writeRsp_oh_0[0]; + assign ll_writeRsp_oh_1 = _zz_ll_writeRsp_oh_0[1]; + assign io_sgWrite_rsp_ready = 1'b1; + assign io_sgWrite_rsp_fire = (io_sgWrite_rsp_valid && io_sgWrite_rsp_ready); + always @(*) begin + io_interrupts = 2'b00; + if(channels_0_interrupts_completion_valid) begin + io_interrupts[0] = 1'b1; + end + if(channels_0_interrupts_onChannelCompletion_valid) begin + io_interrupts[0] = 1'b1; + end + if(channels_0_interrupts_onLinkedListUpdate_valid) begin + io_interrupts[0] = 1'b1; + end + if(channels_0_interrupts_s2mPacket_valid) begin + io_interrupts[0] = 1'b1; + end + if(channels_1_interrupts_completion_valid) begin + io_interrupts[1] = 1'b1; + end + if(channels_1_interrupts_onChannelCompletion_valid) begin + io_interrupts[1] = 1'b1; + end + if(channels_1_interrupts_onLinkedListUpdate_valid) begin + io_interrupts[1] = 1'b1; + end + end + + always @(*) begin + when_BusSlaveFactory_l377 = 1'b0; + case(io_ctrl_PADDR) + 14'h002c : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l377_1 = 1'b0; + case(io_ctrl_PADDR) + 14'h002c : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_1 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l377_2 = 1'b0; + case(io_ctrl_PADDR) + 14'h002c : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_2 = io_ctrl_PWDATA[4]; + always @(*) begin + when_BusSlaveFactory_l377_3 = 1'b0; + case(io_ctrl_PADDR) + 14'h002c : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_3 = io_ctrl_PWDATA[4]; + always @(*) begin + when_BusSlaveFactory_l341 = 1'b0; + case(io_ctrl_PADDR) + 14'h0054 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l341_1 = 1'b0; + case(io_ctrl_PADDR) + 14'h0054 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_1 = io_ctrl_PWDATA[2]; + always @(*) begin + when_BusSlaveFactory_l341_2 = 1'b0; + case(io_ctrl_PADDR) + 14'h0054 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_2 = io_ctrl_PWDATA[3]; + always @(*) begin + when_BusSlaveFactory_l341_3 = 1'b0; + case(io_ctrl_PADDR) + 14'h0054 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_3 = io_ctrl_PWDATA[4]; + always @(*) begin + when_BusSlaveFactory_l377_4 = 1'b0; + case(io_ctrl_PADDR) + 14'h00ac : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_4 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_4 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l377_5 = 1'b0; + case(io_ctrl_PADDR) + 14'h00ac : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_5 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_5 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l377_6 = 1'b0; + case(io_ctrl_PADDR) + 14'h00ac : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_6 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_6 = io_ctrl_PWDATA[4]; + always @(*) begin + when_BusSlaveFactory_l377_7 = 1'b0; + case(io_ctrl_PADDR) + 14'h00ac : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_7 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_7 = io_ctrl_PWDATA[4]; + always @(*) begin + when_BusSlaveFactory_l341_4 = 1'b0; + case(io_ctrl_PADDR) + 14'h00d4 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_4 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_4 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l341_5 = 1'b0; + case(io_ctrl_PADDR) + 14'h00d4 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_5 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_5 = io_ctrl_PWDATA[2]; + always @(*) begin + when_BusSlaveFactory_l341_6 = 1'b0; + case(io_ctrl_PADDR) + 14'h00d4 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_6 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_6 = io_ctrl_PWDATA[3]; + assign when_Apb3SlaveFactory_l81 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h0010); + assign when_Apb3SlaveFactory_l81_1 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h0070); + assign when_Apb3SlaveFactory_l81_2 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h0080); + assign when_Apb3SlaveFactory_l81_3 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h00f0); + assign channels_0_fifo_push_ptrIncr_value = _zz_channels_0_fifo_push_ptrIncr_value; + assign channels_0_fifo_pop_bytesIncr_value = _zz_channels_0_fifo_pop_bytesIncr_value_1; + assign channels_0_fifo_pop_bytesDecr_value = channels_0_pop_b2m_decrBytes; + assign channels_0_fifo_pop_ptrIncr_value = _zz_channels_0_fifo_pop_ptrIncr_value; + assign channels_1_fifo_push_ptrIncr_value = _zz_channels_1_fifo_push_ptrIncr_value_1; + assign channels_1_fifo_pop_bytesIncr_value = _zz_channels_1_fifo_pop_bytesIncr_value_1; + assign channels_1_fifo_pop_bytesDecr_value = 14'h0; + assign channels_1_fifo_pop_ptrIncr_value = _zz_channels_1_fifo_pop_ptrIncr_value; + assign ll_0_descriptorUpdate = (channels_0_ll_descriptorUpdated && (! channels_0_ll_gotDescriptorStall)); + assign ll_1_descriptorUpdate = (channels_1_ll_descriptorUpdated && (! channels_1_ll_gotDescriptorStall)); + always @(posedge clk) begin + if(reset) begin + channels_0_channelValid <= 1'b0; + channels_0_descriptorValid <= 1'b0; + channels_0_priority <= 2'b00; + channels_0_weight <= 2'b00; + channels_0_ctrl_kick <= 1'b0; + channels_0_ll_valid <= 1'b0; + channels_0_ll_onSgStream <= 1'b0; + channels_0_pop_b2m_memPending <= 4'b0000; + channels_0_interrupts_completion_enable <= 1'b0; + channels_0_interrupts_completion_valid <= 1'b0; + channels_0_interrupts_onChannelCompletion_enable <= 1'b0; + channels_0_interrupts_onChannelCompletion_valid <= 1'b0; + channels_0_interrupts_onLinkedListUpdate_enable <= 1'b0; + channels_0_interrupts_onLinkedListUpdate_valid <= 1'b0; + channels_0_interrupts_s2mPacket_enable <= 1'b0; + channels_0_interrupts_s2mPacket_valid <= 1'b0; + channels_1_channelValid <= 1'b0; + channels_1_descriptorValid <= 1'b0; + channels_1_priority <= 2'b00; + channels_1_weight <= 2'b00; + channels_1_ctrl_kick <= 1'b0; + channels_1_ll_valid <= 1'b0; + channels_1_ll_onSgStream <= 1'b0; + channels_1_push_m2b_loadDone <= 1'b1; + channels_1_push_m2b_memPending <= 4'b0000; + channels_1_interrupts_completion_enable <= 1'b0; + channels_1_interrupts_completion_valid <= 1'b0; + channels_1_interrupts_onChannelCompletion_enable <= 1'b0; + channels_1_interrupts_onChannelCompletion_valid <= 1'b0; + channels_1_interrupts_onLinkedListUpdate_enable <= 1'b0; + channels_1_interrupts_onLinkedListUpdate_valid <= 1'b0; + io_inputs_0_payload_last_regNextWhen <= 1'b1; + io_inputs_0_payload_last_regNextWhen_1 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_2 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_3 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_4 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_5 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_6 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_7 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_8 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_9 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_10 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_11 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_12 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_13 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_14 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_15 <= 1'b1; + m2b_cmd_s0_valid <= 1'b0; + m2b_cmd_s0_priority_roundRobins_0 <= 1'b1; + m2b_cmd_s0_priority_roundRobins_1 <= 1'b1; + m2b_cmd_s0_priority_roundRobins_2 <= 1'b1; + m2b_cmd_s0_priority_roundRobins_3 <= 1'b1; + m2b_cmd_s0_priority_counter <= 2'b00; + m2b_cmd_s1_valid <= 1'b0; + m2b_rsp_first <= 1'b1; + b2m_fsm_sel_valid <= 1'b0; + b2m_fsm_arbiter_logic_valid <= 1'b0; + b2m_fsm_arbiter_logic_priority_roundRobins_0 <= 1'b1; + b2m_fsm_arbiter_logic_priority_roundRobins_1 <= 1'b1; + b2m_fsm_arbiter_logic_priority_roundRobins_2 <= 1'b1; + b2m_fsm_arbiter_logic_priority_roundRobins_3 <= 1'b1; + b2m_fsm_arbiter_logic_priority_counter <= 2'b00; + b2m_fsm_sel_valid_regNext <= 1'b0; + b2m_fsm_s1 <= 1'b0; + b2m_fsm_s2 <= 1'b0; + b2m_fsm_toggle <= 1'b0; + memory_core_io_reads_1_rsp_rValidN <= 1'b1; + _zz_io_flush <= 1'b0; + io_write_cmd_payload_first <= 1'b1; + ll_cmd_valid <= 1'b0; + ll_readRsp_beatCounter <= 1'b0; + end else begin + if(channels_0_channelStart) begin + channels_0_channelValid <= 1'b1; + end + if(channels_0_channelCompletion) begin + channels_0_channelValid <= 1'b0; + end + if(channels_0_descriptorStart) begin + channels_0_descriptorValid <= 1'b1; + end + if(channels_0_descriptorCompletion) begin + channels_0_descriptorValid <= 1'b0; + end + channels_0_ctrl_kick <= 1'b0; + if(channels_0_channelCompletion) begin + channels_0_ctrl_kick <= 1'b0; + end + if(when_DmaSg_l318) begin + if(when_DmaSg_l320) begin + if(!when_DmaSg_l322) begin + channels_0_ll_valid <= 1'b0; + end + end + end + if(channels_0_ll_sgStart) begin + channels_0_ll_valid <= 1'b1; + end + if(channels_0_channelCompletion) begin + channels_0_ll_valid <= 1'b0; + end + channels_0_pop_b2m_memPending <= (_zz_channels_0_pop_b2m_memPending - _zz_channels_0_pop_b2m_memPending_3); + if(when_DmaSg_l255) begin + channels_0_interrupts_completion_valid <= 1'b1; + end + if(when_DmaSg_l255_1) begin + channels_0_interrupts_completion_valid <= 1'b0; + end + if(when_DmaSg_l255_2) begin + channels_0_interrupts_onChannelCompletion_valid <= 1'b1; + end + if(when_DmaSg_l255_3) begin + channels_0_interrupts_onChannelCompletion_valid <= 1'b0; + end + if(channels_0_ll_descriptorUpdated) begin + channels_0_interrupts_onLinkedListUpdate_valid <= 1'b1; + end + if(when_DmaSg_l255_4) begin + channels_0_interrupts_onLinkedListUpdate_valid <= 1'b0; + end + if(channels_0_pop_b2m_packetSync) begin + channels_0_interrupts_s2mPacket_valid <= 1'b1; + end + if(when_DmaSg_l255_5) begin + channels_0_interrupts_s2mPacket_valid <= 1'b0; + end + if(channels_1_channelStart) begin + channels_1_channelValid <= 1'b1; + end + if(channels_1_channelCompletion) begin + channels_1_channelValid <= 1'b0; + end + if(channels_1_descriptorStart) begin + channels_1_descriptorValid <= 1'b1; + end + if(channels_1_descriptorCompletion) begin + channels_1_descriptorValid <= 1'b0; + end + channels_1_ctrl_kick <= 1'b0; + if(channels_1_channelCompletion) begin + channels_1_ctrl_kick <= 1'b0; + end + if(when_DmaSg_l318_1) begin + if(when_DmaSg_l320_1) begin + if(!when_DmaSg_l322_1) begin + channels_1_ll_valid <= 1'b0; + end + end + end + if(channels_1_ll_sgStart) begin + channels_1_ll_valid <= 1'b1; + end + if(channels_1_channelCompletion) begin + channels_1_ll_valid <= 1'b0; + end + channels_1_push_m2b_memPending <= (_zz_channels_1_push_m2b_memPending - _zz_channels_1_push_m2b_memPending_3); + if(channels_1_descriptorStart) begin + channels_1_push_m2b_loadDone <= 1'b0; + end + if(when_DmaSg_l255_6) begin + channels_1_interrupts_completion_valid <= 1'b1; + end + if(when_DmaSg_l255_7) begin + channels_1_interrupts_completion_valid <= 1'b0; + end + if(when_DmaSg_l255_8) begin + channels_1_interrupts_onChannelCompletion_valid <= 1'b1; + end + if(when_DmaSg_l255_9) begin + channels_1_interrupts_onChannelCompletion_valid <= 1'b0; + end + if(channels_1_ll_descriptorUpdated) begin + channels_1_interrupts_onLinkedListUpdate_valid <= 1'b1; + end + if(when_DmaSg_l255_10) begin + channels_1_interrupts_onLinkedListUpdate_valid <= 1'b0; + end + if(when_package_l12) begin + io_inputs_0_payload_last_regNextWhen <= io_inputs_0_payload_last; + end + if(when_package_l12_1) begin + io_inputs_0_payload_last_regNextWhen_1 <= io_inputs_0_payload_last; + end + if(when_package_l12_2) begin + io_inputs_0_payload_last_regNextWhen_2 <= io_inputs_0_payload_last; + end + if(when_package_l12_3) begin + io_inputs_0_payload_last_regNextWhen_3 <= io_inputs_0_payload_last; + end + if(when_package_l12_4) begin + io_inputs_0_payload_last_regNextWhen_4 <= io_inputs_0_payload_last; + end + if(when_package_l12_5) begin + io_inputs_0_payload_last_regNextWhen_5 <= io_inputs_0_payload_last; + end + if(when_package_l12_6) begin + io_inputs_0_payload_last_regNextWhen_6 <= io_inputs_0_payload_last; + end + if(when_package_l12_7) begin + io_inputs_0_payload_last_regNextWhen_7 <= io_inputs_0_payload_last; + end + if(when_package_l12_8) begin + io_inputs_0_payload_last_regNextWhen_8 <= io_inputs_0_payload_last; + end + if(when_package_l12_9) begin + io_inputs_0_payload_last_regNextWhen_9 <= io_inputs_0_payload_last; + end + if(when_package_l12_10) begin + io_inputs_0_payload_last_regNextWhen_10 <= io_inputs_0_payload_last; + end + if(when_package_l12_11) begin + io_inputs_0_payload_last_regNextWhen_11 <= io_inputs_0_payload_last; + end + if(when_package_l12_12) begin + io_inputs_0_payload_last_regNextWhen_12 <= io_inputs_0_payload_last; + end + if(when_package_l12_13) begin + io_inputs_0_payload_last_regNextWhen_13 <= io_inputs_0_payload_last; + end + if(when_package_l12_14) begin + io_inputs_0_payload_last_regNextWhen_14 <= io_inputs_0_payload_last; + end + if(when_package_l12_15) begin + io_inputs_0_payload_last_regNextWhen_15 <= io_inputs_0_payload_last; + end + if(when_DmaSg_l758) begin + if(when_DmaSg_l760) begin + m2b_cmd_s0_valid <= 1'b1; + if(when_DmaSg_l763) begin + m2b_cmd_s0_priority_roundRobins_0 <= m2b_cmd_s0_priority_contextNext; + end + if(when_DmaSg_l763_1) begin + m2b_cmd_s0_priority_roundRobins_1 <= m2b_cmd_s0_priority_contextNext; + end + if(when_DmaSg_l763_2) begin + m2b_cmd_s0_priority_roundRobins_2 <= m2b_cmd_s0_priority_contextNext; + end + if(when_DmaSg_l763_3) begin + m2b_cmd_s0_priority_roundRobins_3 <= m2b_cmd_s0_priority_contextNext; + end + m2b_cmd_s0_priority_counter <= (m2b_cmd_s0_priority_counter + 2'b01); + if(m2b_cmd_s0_priority_weightLast) begin + m2b_cmd_s0_priority_counter <= 2'b00; + end + end + end + if(m2b_cmd_s0_valid) begin + m2b_cmd_s1_valid <= 1'b1; + end + if(m2b_cmd_s1_valid) begin + if(io_read_cmd_ready) begin + m2b_cmd_s0_valid <= 1'b0; + m2b_cmd_s1_valid <= 1'b0; + if(when_DmaSg_l828) begin + if(m2b_cmd_s1_lastBurst) begin + channels_1_push_m2b_loadDone <= 1'b1; + end + end + end + end + if(io_read_rsp_fire) begin + m2b_rsp_first <= io_read_rsp_payload_last; + end + if(when_DmaSg_l758_1) begin + if(when_DmaSg_l760_1) begin + b2m_fsm_arbiter_logic_valid <= 1'b1; + if(when_DmaSg_l763_4) begin + b2m_fsm_arbiter_logic_priority_roundRobins_0 <= b2m_fsm_arbiter_logic_priority_contextNext; + end + if(when_DmaSg_l763_5) begin + b2m_fsm_arbiter_logic_priority_roundRobins_1 <= b2m_fsm_arbiter_logic_priority_contextNext; + end + if(when_DmaSg_l763_6) begin + b2m_fsm_arbiter_logic_priority_roundRobins_2 <= b2m_fsm_arbiter_logic_priority_contextNext; + end + if(when_DmaSg_l763_7) begin + b2m_fsm_arbiter_logic_priority_roundRobins_3 <= b2m_fsm_arbiter_logic_priority_contextNext; + end + b2m_fsm_arbiter_logic_priority_counter <= (b2m_fsm_arbiter_logic_priority_counter + 2'b01); + if(b2m_fsm_arbiter_logic_priority_weightLast) begin + b2m_fsm_arbiter_logic_priority_counter <= 2'b00; + end + end + end + if(b2m_fsm_sel_ready) begin + b2m_fsm_sel_valid <= 1'b0; + if(b2m_fsm_sel_valid) begin + b2m_fsm_arbiter_logic_valid <= 1'b0; + end + end + if(when_DmaSg_l935) begin + b2m_fsm_sel_valid <= 1'b1; + end + b2m_fsm_sel_valid_regNext <= b2m_fsm_sel_valid; + b2m_fsm_s1 <= b2m_fsm_s0; + if(b2m_fsm_s1) begin + b2m_fsm_s2 <= 1'b1; + end + if(when_DmaSg_l986) begin + b2m_fsm_s2 <= 1'b0; + end + if(when_DmaSg_l1013) begin + b2m_fsm_toggle <= (! b2m_fsm_toggle); + end + if(memory_core_io_reads_1_rsp_valid) begin + memory_core_io_reads_1_rsp_rValidN <= 1'b0; + end + if(memory_core_io_reads_1_rsp_s2mPipe_ready) begin + memory_core_io_reads_1_rsp_rValidN <= 1'b1; + end + _zz_io_flush <= (b2m_fsm_sel_valid && (! b2m_fsm_sel_ready)); + if(io_write_cmd_fire) begin + io_write_cmd_payload_first <= io_write_cmd_payload_last; + end + if(when_DmaSg_l1160) begin + if(when_DmaSg_l1161) begin + ll_cmd_valid <= 1'b1; + end + end else begin + if(when_DmaSg_l1177) begin + ll_cmd_valid <= 1'b0; + end + end + if(io_sgRead_rsp_fire) begin + ll_readRsp_beatCounter <= (ll_readRsp_beatCounter + 1'b1); + end + if(when_BusSlaveFactory_l377_1) begin + if(when_BusSlaveFactory_l379_1) begin + channels_0_ctrl_kick <= _zz_channels_0_ctrl_kick[0]; + end + end + if(when_BusSlaveFactory_l341) begin + if(when_BusSlaveFactory_l347) begin + channels_0_interrupts_completion_valid <= _zz_channels_0_interrupts_completion_valid[0]; + end + end + if(when_BusSlaveFactory_l341_1) begin + if(when_BusSlaveFactory_l347_1) begin + channels_0_interrupts_onChannelCompletion_valid <= _zz_channels_0_interrupts_onChannelCompletion_valid[0]; + end + end + if(when_BusSlaveFactory_l341_2) begin + if(when_BusSlaveFactory_l347_2) begin + channels_0_interrupts_onLinkedListUpdate_valid <= _zz_channels_0_interrupts_onLinkedListUpdate_valid[0]; + end + end + if(when_BusSlaveFactory_l341_3) begin + if(when_BusSlaveFactory_l347_3) begin + channels_0_interrupts_s2mPacket_valid <= _zz_channels_0_interrupts_s2mPacket_valid[0]; + end + end + if(when_BusSlaveFactory_l377_5) begin + if(when_BusSlaveFactory_l379_5) begin + channels_1_ctrl_kick <= _zz_channels_1_ctrl_kick[0]; + end + end + if(when_BusSlaveFactory_l341_4) begin + if(when_BusSlaveFactory_l347_4) begin + channels_1_interrupts_completion_valid <= _zz_channels_1_interrupts_completion_valid[0]; + end + end + if(when_BusSlaveFactory_l341_5) begin + if(when_BusSlaveFactory_l347_5) begin + channels_1_interrupts_onChannelCompletion_valid <= _zz_channels_1_interrupts_onChannelCompletion_valid[0]; + end + end + if(when_BusSlaveFactory_l341_6) begin + if(when_BusSlaveFactory_l347_6) begin + channels_1_interrupts_onLinkedListUpdate_valid <= _zz_channels_1_interrupts_onLinkedListUpdate_valid[0]; + end + end + case(io_ctrl_PADDR) + 14'h0078 : begin + if(ctrl_doWrite) begin + channels_0_ll_onSgStream <= io_ctrl_PWDATA[0]; + end + end + 14'h0044 : begin + if(ctrl_doWrite) begin + channels_0_priority <= io_ctrl_PWDATA[1 : 0]; + channels_0_weight <= io_ctrl_PWDATA[9 : 8]; + end + end + 14'h0050 : begin + if(ctrl_doWrite) begin + channels_0_interrupts_completion_enable <= io_ctrl_PWDATA[0]; + channels_0_interrupts_onChannelCompletion_enable <= io_ctrl_PWDATA[2]; + channels_0_interrupts_onLinkedListUpdate_enable <= io_ctrl_PWDATA[3]; + channels_0_interrupts_s2mPacket_enable <= io_ctrl_PWDATA[4]; + end + end + 14'h00f8 : begin + if(ctrl_doWrite) begin + channels_1_ll_onSgStream <= io_ctrl_PWDATA[0]; + end + end + 14'h00c4 : begin + if(ctrl_doWrite) begin + channels_1_priority <= io_ctrl_PWDATA[1 : 0]; + channels_1_weight <= io_ctrl_PWDATA[9 : 8]; + end + end + 14'h00d0 : begin + if(ctrl_doWrite) begin + channels_1_interrupts_completion_enable <= io_ctrl_PWDATA[0]; + channels_1_interrupts_onChannelCompletion_enable <= io_ctrl_PWDATA[2]; + channels_1_interrupts_onLinkedListUpdate_enable <= io_ctrl_PWDATA[3]; + end + end + default : begin + end + endcase + end + end + + always @(posedge clk) begin + if(channels_0_bytesProbe_incr_valid) begin + channels_0_bytesProbe_value <= (_zz_channels_0_bytesProbe_value + 27'h0000001); + end + if(channels_0_descriptorStart) begin + channels_0_ll_packet <= 1'b0; + end + if(channels_0_descriptorStart) begin + channels_0_ll_requireSync <= 1'b0; + end + if(when_DmaSg_l318) begin + channels_0_ll_waitDone <= 1'b0; + if(when_DmaSg_l320) begin + channels_0_ll_head <= 1'b0; + end + end + if(channels_0_channelStart) begin + channels_0_ll_waitDone <= 1'b0; + channels_0_ll_head <= 1'b1; + end + channels_0_fifo_push_ptr <= (channels_0_fifo_push_ptr + channels_0_fifo_push_ptrIncr_value); + if(channels_0_channelStart) begin + channels_0_fifo_push_ptr <= 11'h0; + end + channels_0_fifo_pop_ptr <= (channels_0_fifo_pop_ptr + channels_0_fifo_pop_ptrIncr_value); + channels_0_fifo_pop_withOverride_backup <= channels_0_fifo_pop_withOverride_backupNext; + if(when_DmaSg_l409) begin + channels_0_fifo_pop_withOverride_valid <= 1'b0; + end + if(channels_0_fifo_pop_withOverride_load) begin + channels_0_fifo_pop_withOverride_valid <= 1'b1; + end + channels_0_fifo_pop_withOverride_exposed <= ((! channels_0_fifo_pop_withOverride_valid) ? channels_0_fifo_pop_withOverride_backupNext : _zz_channels_0_fifo_pop_withOverride_exposed); + if(channels_0_channelStart) begin + channels_0_fifo_pop_withOverride_backup <= 14'h0; + channels_0_fifo_pop_withOverride_valid <= 1'b0; + end + if(channels_0_channelStart) begin + channels_0_push_s2b_packetLock <= 1'b0; + end + if(channels_0_pop_b2m_fire) begin + channels_0_pop_b2m_flush <= 1'b0; + end + if(when_DmaSg_l505) begin + channels_0_pop_b2m_packet <= 1'b0; + end + if(when_DmaSg_l523) begin + channels_0_pop_b2m_flush <= 1'b0; + channels_0_pop_b2m_packet <= 1'b0; + end + if(channels_0_pop_b2m_packetSync) begin + channels_0_push_s2b_packetLock <= 1'b0; + if(when_DmaSg_l532) begin + if(!channels_0_push_s2b_completionOnLast) begin + if(when_DmaSg_l536) begin + channels_0_ll_requireSync <= 1'b1; + end + end + channels_0_ll_packet <= 1'b1; + end + end + if(channels_0_channelStart) begin + channels_0_pop_b2m_bytesToSkip <= 4'b0000; + channels_0_pop_b2m_flush <= 1'b0; + end + if(channels_0_descriptorStart) begin + channels_0_pop_b2m_bytesLeft <= {1'd0, channels_0_bytes}; + channels_0_pop_b2m_waitFinalRsp <= 1'b0; + end + if(channels_0_channelValid) begin + if(!channels_0_channelStop) begin + if(when_DmaSg_l575) begin + if(when_DmaSg_l593) begin + channels_0_channelStop <= 1'b1; + end + end + end + end + channels_0_fifo_pop_ptrIncr_value_regNext <= channels_0_fifo_pop_ptrIncr_value; + channels_0_fifo_push_available <= (_zz_channels_0_fifo_push_available - (channels_0_push_memory ? channels_0_fifo_push_availableDecr : channels_0_fifo_push_ptrIncr_value)); + if(channels_0_channelStart) begin + channels_0_fifo_push_ptr <= 11'h0; + channels_0_fifo_push_available <= (channels_0_fifo_words + 11'h001); + channels_0_fifo_pop_ptr <= 11'h0; + end + if(when_DmaSg_l625) begin + channels_0_bytesProbe_value <= 27'h0; + end + if(channels_1_bytesProbe_incr_valid) begin + channels_1_bytesProbe_value <= (_zz_channels_1_bytesProbe_value + 27'h0000001); + end + if(channels_1_descriptorStart) begin + channels_1_ll_packet <= 1'b0; + end + if(channels_1_descriptorStart) begin + channels_1_ll_requireSync <= 1'b0; + end + if(when_DmaSg_l318_1) begin + channels_1_ll_waitDone <= 1'b0; + if(when_DmaSg_l320_1) begin + channels_1_ll_head <= 1'b0; + end + end + if(channels_1_channelStart) begin + channels_1_ll_waitDone <= 1'b0; + channels_1_ll_head <= 1'b1; + end + channels_1_fifo_push_ptr <= (channels_1_fifo_push_ptr + channels_1_fifo_push_ptrIncr_value); + if(channels_1_channelStart) begin + channels_1_fifo_push_ptr <= 11'h0; + end + channels_1_fifo_pop_ptr <= (channels_1_fifo_pop_ptr + channels_1_fifo_pop_ptrIncr_value); + channels_1_fifo_pop_withoutOverride_exposed <= (_zz_channels_1_fifo_pop_withoutOverride_exposed - channels_1_fifo_pop_bytesDecr_value); + if(channels_1_channelStart) begin + channels_1_fifo_pop_withoutOverride_exposed <= 14'h0; + end + if(channels_1_descriptorStart) begin + channels_1_push_m2b_bytesLeft <= channels_1_bytes; + end + if(when_DmaSg_l474) begin + channels_1_pop_b2s_veryLastValid <= 1'b1; + end + if(channels_1_pop_b2s_veryLastTrigger) begin + channels_1_pop_b2s_veryLastPtr <= channels_1_fifo_push_ptrWithBase; + channels_1_pop_b2s_veryLastEndPacket <= channels_1_pop_b2s_last; + end + if(channels_1_channelStart) begin + channels_1_pop_b2s_veryLastValid <= 1'b0; + end + if(channels_1_channelValid) begin + if(!channels_1_channelStop) begin + if(when_DmaSg_l575_1) begin + if(when_DmaSg_l593_1) begin + channels_1_channelStop <= 1'b1; + end + end + end + end + channels_1_fifo_pop_ptrIncr_value_regNext <= channels_1_fifo_pop_ptrIncr_value; + channels_1_fifo_push_available <= (_zz_channels_1_fifo_push_available - (channels_1_push_memory ? channels_1_fifo_push_availableDecr : channels_1_fifo_push_ptrIncr_value)); + if(channels_1_channelStart) begin + channels_1_fifo_push_ptr <= 11'h0; + channels_1_fifo_push_available <= (channels_1_fifo_words + 11'h001); + channels_1_fifo_pop_ptr <= 11'h0; + end + if(when_DmaSg_l625_1) begin + channels_1_bytesProbe_value <= 27'h0; + end + if(when_DmaSg_l665) begin + channels_0_push_s2b_waitFirst <= 1'b0; + if(io_inputs_0_payload_last) begin + channels_0_push_s2b_packetLock <= 1'b1; + end + end + if(when_DmaSg_l681) begin + channels_0_pop_b2m_flush <= 1'b1; + end + if(when_DmaSg_l682) begin + channels_0_pop_b2m_packet <= 1'b1; + end + if(when_DmaSg_l725) begin + if(when_DmaSg_l726) begin + channels_1_pop_b2s_veryLastValid <= 1'b0; + end + end + m2b_cmd_s1_address <= m2b_cmd_s0_address; + m2b_cmd_s1_length <= m2b_cmd_s0_length; + m2b_cmd_s1_lastBurst <= m2b_cmd_s0_lastBurst; + m2b_cmd_s1_bytesLeft <= m2b_cmd_s0_bytesLeft; + if(m2b_cmd_s1_valid) begin + if(io_read_cmd_ready) begin + if(when_DmaSg_l828) begin + channels_1_push_m2b_address <= m2b_cmd_s1_addressNext; + channels_1_push_m2b_bytesLeft <= m2b_cmd_s1_byteLeftNext; + end + end + end + if(when_DmaSg_l935) begin + b2m_fsm_sel_address <= channels_0_pop_b2m_address; + b2m_fsm_sel_ptr <= channels_0_fifo_pop_ptrWithBase; + b2m_fsm_sel_ptrMask <= channels_0_fifo_words; + b2m_fsm_sel_bytePerBurst <= channels_0_pop_b2m_bytePerBurst; + b2m_fsm_sel_bytesInFifo <= channels_0_fifo_pop_bytes; + b2m_fsm_sel_flush <= channels_0_pop_b2m_flush; + b2m_fsm_sel_packet <= channels_0_pop_b2m_packet; + b2m_fsm_sel_bytesLeft <= channels_0_pop_b2m_bytesLeft[25:0]; + end + if(b2m_fsm_s0) begin + b2m_fsm_sel_bytesInBurst <= _zz_b2m_fsm_sel_bytesInBurst_3[11:0]; + end + if(b2m_fsm_s1) begin + b2m_fsm_beatCounter <= (_zz_b2m_fsm_beatCounter >>> 3'd4); + if(when_DmaSg_l996) begin + channels_0_pop_b2m_address <= b2m_fsm_addressNext; + channels_0_pop_b2m_bytesLeft <= b2m_fsm_bytesLeftNext; + if(b2m_fsm_isFinalCmd) begin + channels_0_pop_b2m_waitFinalRsp <= 1'b1; + end + if(when_DmaSg_l1001) begin + if(b2m_fsm_sel_flush) begin + channels_0_pop_b2m_flush <= 1'b1; + end + if(b2m_fsm_sel_packet) begin + channels_0_pop_b2m_packet <= 1'b1; + end + end + end + end + if(when_DmaSg_l1033) begin + b2m_fsm_sel_ptr <= ((b2m_fsm_sel_ptr & (~ b2m_fsm_sel_ptrMask)) | (_zz_b2m_fsm_sel_ptr & b2m_fsm_sel_ptrMask)); + end + if(memory_core_io_reads_1_rsp_rValidN) begin + memory_core_io_reads_1_rsp_rData_data <= memory_core_io_reads_1_rsp_payload_data; + memory_core_io_reads_1_rsp_rData_mask <= memory_core_io_reads_1_rsp_payload_mask; + memory_core_io_reads_1_rsp_rData_context <= memory_core_io_reads_1_rsp_payload_context; + end + if(b2m_fsm_aggregate_memoryPort_fire) begin + b2m_fsm_aggregate_first <= 1'b0; + end + if(when_DmaSg_l1050) begin + b2m_fsm_aggregate_first <= 1'b1; + end + b2m_fsm_cmd_maskLastTriggerReg <= b2m_fsm_cmd_maskLastTriggerComb; + b2m_fsm_cmd_maskLast <= {(4'b1111 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1110 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1101 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1100 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1011 <= b2m_fsm_cmd_maskLastTriggerComb),{(_zz_b2m_fsm_cmd_maskLast <= b2m_fsm_cmd_maskLastTriggerComb),{_zz_b2m_fsm_cmd_maskLast_1,{_zz_b2m_fsm_cmd_maskLast_2,_zz_b2m_fsm_cmd_maskLast_3}}}}}}}}; + if(io_write_cmd_fire) begin + b2m_fsm_beatCounter <= (b2m_fsm_beatCounter - 8'h01); + end + if(when_DmaSg_l1102) begin + if(_zz_when_1[0]) begin + channels_0_pop_b2m_bytesToSkip <= (b2m_fsm_aggregate_engine_io_output_usedUntil + 4'b0001); + end + end + if(when_DmaSg_l1149) begin + ll_cmd_oh_0 <= channels_0_ll_requestLl; + ll_cmd_oh_1 <= _zz_ll_arbiter_head_1; + end + if(when_DmaSg_l1148) begin + ll_cmd_ptr <= (_zz_ll_cmd_ptr[0] ? channels_0_ll_ptr : channels_1_ll_ptr); + end + if(when_DmaSg_l1148_1) begin + ll_cmd_ptrNext <= (_zz_ll_cmd_ptrNext[0] ? channels_0_ll_ptrNext : channels_1_ll_ptrNext); + end + if(when_DmaSg_l1148_2) begin + ll_cmd_bytesDone <= channels_0_bytesProbe_value; + end + if(when_DmaSg_l1148_3) begin + ll_cmd_endOfPacket <= (_zz_ll_cmd_endOfPacket[0] ? channels_0_ll_packet : channels_1_ll_packet); + end + if(when_DmaSg_l1154) begin + ll_cmd_isJustASink <= ll_arbiter_isJustASink; + end + if(when_DmaSg_l1155) begin + ll_cmd_doDescriptorStall <= ll_arbiter_doDescriptorStall; + end + if(when_DmaSg_l1156) begin + ll_cmd_onSgStream <= ll_arbiter_onSgStream; + end + if(when_DmaSg_l1160) begin + ll_cmd_oh_0 <= channels_0_ll_requestLl; + ll_cmd_oh_1 <= _zz_ll_arbiter_head_1; + if(channels_0_ll_requestLl) begin + channels_0_ll_waitDone <= 1'b1; + channels_0_ll_writeDone <= ll_arbiter_head; + channels_0_ll_justASync <= ll_arbiter_isJustASink; + channels_0_ll_packet <= 1'b0; + channels_0_ll_requireSync <= 1'b0; + if(when_DmaSg_l1169) begin + channels_0_ll_ptr <= channels_0_ll_ptrNext; + end + channels_0_ll_readDone <= ll_arbiter_isJustASink; + end + if(_zz_ll_arbiter_head_1) begin + channels_1_ll_waitDone <= 1'b1; + channels_1_ll_writeDone <= ll_arbiter_head; + channels_1_ll_justASync <= ll_arbiter_isJustASink; + channels_1_ll_packet <= 1'b0; + channels_1_ll_requireSync <= 1'b0; + if(when_DmaSg_l1169_1) begin + channels_1_ll_ptr <= channels_1_ll_ptrNext; + end + channels_1_ll_readDone <= ll_arbiter_isJustASink; + end + ll_cmd_readFired <= ll_arbiter_isJustASink; + ll_cmd_writeFired <= ll_arbiter_head; + end + if(io_sgRead_cmd_fire) begin + ll_cmd_readFired <= 1'b1; + end + if(io_sgWrite_cmd_fire) begin + ll_cmd_writeFired <= 1'b1; + end + if(io_sgRead_rsp_fire) begin + if(when_DmaSg_l1248) begin + if(ll_readRsp_oh_1) begin + channels_1_push_m2b_address <= io_sgRead_rsp_payload_fragment_data[95 : 64]; + end + end + if(when_DmaSg_l1248_1) begin + if(ll_readRsp_oh_0) begin + channels_0_pop_b2m_address <= io_sgRead_rsp_payload_fragment_data[31 : 0]; + end + end + if(when_DmaSg_l1248_2) begin + if(ll_readRsp_oh_0) begin + channels_0_ll_ptrNext <= io_sgRead_rsp_payload_fragment_data[95 : 64]; + end + if(ll_readRsp_oh_1) begin + channels_1_ll_ptrNext <= io_sgRead_rsp_payload_fragment_data[95 : 64]; + end + end + if(when_DmaSg_l1248_3) begin + if(ll_readRsp_oh_0) begin + channels_0_bytes <= io_sgRead_rsp_payload_fragment_data[57 : 32]; + end + if(ll_readRsp_oh_1) begin + channels_1_bytes <= io_sgRead_rsp_payload_fragment_data[57 : 32]; + end + end + if(when_DmaSg_l1248_4) begin + if(ll_readRsp_oh_0) begin + channels_0_ll_controlNoCompletion <= io_sgRead_rsp_payload_fragment_data[63]; + end + if(ll_readRsp_oh_1) begin + channels_1_ll_controlNoCompletion <= io_sgRead_rsp_payload_fragment_data[63]; + end + end + if(when_DmaSg_l1248_5) begin + if(ll_readRsp_oh_1) begin + channels_1_pop_b2s_last <= io_sgRead_rsp_payload_fragment_data[62]; + end + end + if(when_DmaSg_l1248_6) begin + if(ll_readRsp_oh_0) begin + channels_0_ll_gotDescriptorStall <= io_sgRead_rsp_payload_fragment_data[31]; + end + if(ll_readRsp_oh_1) begin + channels_1_ll_gotDescriptorStall <= io_sgRead_rsp_payload_fragment_data[31]; + end + end + if(when_DmaSg_l1271) begin + if(ll_readRsp_oh_0) begin + channels_0_ll_readDone <= 1'b1; + end + if(ll_readRsp_oh_1) begin + channels_1_ll_readDone <= 1'b1; + end + end + end + if(io_sgWrite_rsp_fire) begin + if(ll_writeRsp_oh_0) begin + channels_0_ll_writeDone <= 1'b1; + end + if(ll_writeRsp_oh_1) begin + channels_1_ll_writeDone <= 1'b1; + end + end + case(io_ctrl_PADDR) + 14'h000c : begin + if(ctrl_doWrite) begin + channels_0_push_memory <= io_ctrl_PWDATA[12]; + channels_0_push_s2b_completionOnLast <= io_ctrl_PWDATA[13]; + channels_0_push_s2b_waitFirst <= io_ctrl_PWDATA[14]; + end + end + 14'h001c : begin + if(ctrl_doWrite) begin + channels_0_pop_memory <= io_ctrl_PWDATA[12]; + end + end + 14'h002c : begin + if(ctrl_doWrite) begin + channels_0_channelStop <= io_ctrl_PWDATA[2]; + end + end + 14'h0020 : begin + if(ctrl_doWrite) begin + channels_0_bytes <= io_ctrl_PWDATA[25 : 0]; + end + end + 14'h008c : begin + if(ctrl_doWrite) begin + channels_1_push_memory <= io_ctrl_PWDATA[12]; + end + end + 14'h0098 : begin + if(ctrl_doWrite) begin + channels_1_pop_b2s_sinkId <= io_ctrl_PWDATA[19 : 16]; + end + end + 14'h009c : begin + if(ctrl_doWrite) begin + channels_1_pop_memory <= io_ctrl_PWDATA[12]; + channels_1_pop_b2s_last <= io_ctrl_PWDATA[13]; + end + end + 14'h00ac : begin + if(ctrl_doWrite) begin + channels_1_channelStop <= io_ctrl_PWDATA[2]; + end + end + 14'h00a0 : begin + if(ctrl_doWrite) begin + channels_1_bytes <= io_ctrl_PWDATA[25 : 0]; + end + end + default : begin + end + endcase + if(when_Apb3SlaveFactory_l81) begin + if(ctrl_doWrite) begin + channels_0_pop_b2m_address[31 : 0] <= io_ctrl_PWDATA[31 : 0]; + end + end + if(when_Apb3SlaveFactory_l81_1) begin + if(ctrl_doWrite) begin + channels_0_ll_ptrNext[31 : 0] <= io_ctrl_PWDATA[31 : 0]; + end + end + if(when_Apb3SlaveFactory_l81_2) begin + if(ctrl_doWrite) begin + channels_1_push_m2b_address[31 : 0] <= io_ctrl_PWDATA[31 : 0]; + end + end + if(when_Apb3SlaveFactory_l81_3) begin + if(ctrl_doWrite) begin + channels_1_ll_ptrNext[31 : 0] <= io_ctrl_PWDATA[31 : 0]; + end + end + end + + +endmodule + +module EfxDMA_StreamArbiter_1_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_inputs_0_valid, + output wire io_inputs_0_ready, + input wire io_inputs_0_payload_last, + input wire [0:0] io_inputs_0_payload_fragment_source, + input wire [0:0] io_inputs_0_payload_fragment_opcode, + input wire [31:0] io_inputs_0_payload_fragment_address, + input wire [11:0] io_inputs_0_payload_fragment_length, + input wire [127:0] io_inputs_0_payload_fragment_data, + input wire [15:0] io_inputs_0_payload_fragment_mask, + input wire [12:0] io_inputs_0_payload_fragment_context, + input wire io_inputs_1_valid, + output wire io_inputs_1_ready, + input wire io_inputs_1_payload_last, + input wire [0:0] io_inputs_1_payload_fragment_source, + input wire [0:0] io_inputs_1_payload_fragment_opcode, + input wire [31:0] io_inputs_1_payload_fragment_address, + input wire [11:0] io_inputs_1_payload_fragment_length, + input wire [127:0] io_inputs_1_payload_fragment_data, + input wire [15:0] io_inputs_1_payload_fragment_mask, + input wire [12:0] io_inputs_1_payload_fragment_context, + output wire io_output_valid, + input wire io_output_ready, + output wire io_output_payload_last, + output wire [0:0] io_output_payload_fragment_source, + output wire [0:0] io_output_payload_fragment_opcode, + output wire [31:0] io_output_payload_fragment_address, + output wire [11:0] io_output_payload_fragment_length, + output wire [127:0] io_output_payload_fragment_data, + output wire [15:0] io_output_payload_fragment_mask, + output wire [12:0] io_output_payload_fragment_context, + output wire [0:0] io_chosen, + output wire [1:0] io_chosenOH, + input wire clk, + input wire reset +); + + wire [3:0] _zz__zz_maskProposal_0_2; + wire [3:0] _zz__zz_maskProposal_0_2_1; + wire [1:0] _zz__zz_maskProposal_0_2_2; + reg locked; + wire maskProposal_0; + wire maskProposal_1; + reg maskLocked_0; + reg maskLocked_1; + wire maskRouted_0; + wire maskRouted_1; + wire [1:0] _zz_maskProposal_0; + wire [3:0] _zz_maskProposal_0_1; + wire [3:0] _zz_maskProposal_0_2; + wire [1:0] _zz_maskProposal_0_3; + wire io_output_fire; + wire when_Stream_l683; + wire _zz_io_chosen; + + assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); + assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; + assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; + assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); + assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); + assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; + assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; + assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); + assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); + assign maskProposal_0 = _zz_maskProposal_0_3[0]; + assign maskProposal_1 = _zz_maskProposal_0_3[1]; + assign io_output_fire = (io_output_valid && io_output_ready); + assign when_Stream_l683 = (io_output_fire && io_output_payload_last); + assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); + assign io_output_payload_last = (maskRouted_0 ? io_inputs_0_payload_last : io_inputs_1_payload_last); + assign io_output_payload_fragment_source = (maskRouted_0 ? io_inputs_0_payload_fragment_source : io_inputs_1_payload_fragment_source); + assign io_output_payload_fragment_opcode = (maskRouted_0 ? io_inputs_0_payload_fragment_opcode : io_inputs_1_payload_fragment_opcode); + assign io_output_payload_fragment_address = (maskRouted_0 ? io_inputs_0_payload_fragment_address : io_inputs_1_payload_fragment_address); + assign io_output_payload_fragment_length = (maskRouted_0 ? io_inputs_0_payload_fragment_length : io_inputs_1_payload_fragment_length); + assign io_output_payload_fragment_data = (maskRouted_0 ? io_inputs_0_payload_fragment_data : io_inputs_1_payload_fragment_data); + assign io_output_payload_fragment_mask = (maskRouted_0 ? io_inputs_0_payload_fragment_mask : io_inputs_1_payload_fragment_mask); + assign io_output_payload_fragment_context = (maskRouted_0 ? io_inputs_0_payload_fragment_context : io_inputs_1_payload_fragment_context); + assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); + assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); + assign io_chosenOH = {maskRouted_1,maskRouted_0}; + assign _zz_io_chosen = io_chosenOH[1]; + assign io_chosen = _zz_io_chosen; + always @(posedge clk) begin + if(reset) begin + locked <= 1'b0; + maskLocked_0 <= 1'b0; + maskLocked_1 <= 1'b1; + end else begin + if(io_output_valid) begin + maskLocked_0 <= maskRouted_0; + maskLocked_1 <= maskRouted_1; + end + if(io_output_valid) begin + locked <= 1'b1; + end + if(when_Stream_l683) begin + locked <= 1'b0; + end + end + end + + +endmodule + +module EfxDMA_StreamArbiter_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_inputs_0_valid, + output wire io_inputs_0_ready, + input wire io_inputs_0_payload_last, + input wire [0:0] io_inputs_0_payload_fragment_source, + input wire [0:0] io_inputs_0_payload_fragment_opcode, + input wire [31:0] io_inputs_0_payload_fragment_address, + input wire [11:0] io_inputs_0_payload_fragment_length, + input wire [20:0] io_inputs_0_payload_fragment_context, + input wire io_inputs_1_valid, + output wire io_inputs_1_ready, + input wire io_inputs_1_payload_last, + input wire [0:0] io_inputs_1_payload_fragment_source, + input wire [0:0] io_inputs_1_payload_fragment_opcode, + input wire [31:0] io_inputs_1_payload_fragment_address, + input wire [11:0] io_inputs_1_payload_fragment_length, + input wire [20:0] io_inputs_1_payload_fragment_context, + output wire io_output_valid, + input wire io_output_ready, + output wire io_output_payload_last, + output wire [0:0] io_output_payload_fragment_source, + output wire [0:0] io_output_payload_fragment_opcode, + output wire [31:0] io_output_payload_fragment_address, + output wire [11:0] io_output_payload_fragment_length, + output wire [20:0] io_output_payload_fragment_context, + output wire [0:0] io_chosen, + output wire [1:0] io_chosenOH, + input wire clk, + input wire reset +); + + wire [3:0] _zz__zz_maskProposal_0_2; + wire [3:0] _zz__zz_maskProposal_0_2_1; + wire [1:0] _zz__zz_maskProposal_0_2_2; + reg locked; + wire maskProposal_0; + wire maskProposal_1; + reg maskLocked_0; + reg maskLocked_1; + wire maskRouted_0; + wire maskRouted_1; + wire [1:0] _zz_maskProposal_0; + wire [3:0] _zz_maskProposal_0_1; + wire [3:0] _zz_maskProposal_0_2; + wire [1:0] _zz_maskProposal_0_3; + wire io_output_fire; + wire when_Stream_l683; + wire _zz_io_chosen; + + assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); + assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; + assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; + assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); + assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); + assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; + assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; + assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); + assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); + assign maskProposal_0 = _zz_maskProposal_0_3[0]; + assign maskProposal_1 = _zz_maskProposal_0_3[1]; + assign io_output_fire = (io_output_valid && io_output_ready); + assign when_Stream_l683 = (io_output_fire && io_output_payload_last); + assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); + assign io_output_payload_last = (maskRouted_0 ? io_inputs_0_payload_last : io_inputs_1_payload_last); + assign io_output_payload_fragment_source = (maskRouted_0 ? io_inputs_0_payload_fragment_source : io_inputs_1_payload_fragment_source); + assign io_output_payload_fragment_opcode = (maskRouted_0 ? io_inputs_0_payload_fragment_opcode : io_inputs_1_payload_fragment_opcode); + assign io_output_payload_fragment_address = (maskRouted_0 ? io_inputs_0_payload_fragment_address : io_inputs_1_payload_fragment_address); + assign io_output_payload_fragment_length = (maskRouted_0 ? io_inputs_0_payload_fragment_length : io_inputs_1_payload_fragment_length); + assign io_output_payload_fragment_context = (maskRouted_0 ? io_inputs_0_payload_fragment_context : io_inputs_1_payload_fragment_context); + assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); + assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); + assign io_chosenOH = {maskRouted_1,maskRouted_0}; + assign _zz_io_chosen = io_chosenOH[1]; + assign io_chosen = _zz_io_chosen; + always @(posedge clk) begin + if(reset) begin + locked <= 1'b0; + maskLocked_0 <= 1'b0; + maskLocked_1 <= 1'b1; + end else begin + if(io_output_valid) begin + maskLocked_0 <= maskRouted_0; + maskLocked_1 <= maskRouted_1; + end + if(io_output_valid) begin + locked <= 1'b1; + end + if(when_Stream_l683) begin + locked <= 1'b0; + end + end + end + + +endmodule + +module EfxDMA_BufferCC_5_a048ca8f51874147a1cd65d43e6523ef ( + input wire [4:0] io_dataIn, + output wire [4:0] io_dataOut, + input wire dat1_o_clk, + input wire dat1_o_reset +); + + (* async_reg = "true" *) reg [4:0] buffers_0; + (* async_reg = "true" *) reg [4:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge dat1_o_clk) begin + if(dat1_o_reset) begin + buffers_0 <= 5'h0; + buffers_1 <= 5'h0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +//EfxDMA_BufferCC_4 replaced by EfxDMA_BufferCC_3_a048ca8f51874147a1cd65d43e6523ef + +module EfxDMA_BufferCC_3_a048ca8f51874147a1cd65d43e6523ef ( + input wire [4:0] io_dataIn, + output wire [4:0] io_dataOut, + input wire clk, + input wire reset +); + + (* async_reg = "true" *) reg [4:0] buffers_0; + (* async_reg = "true" *) reg [4:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge clk) begin + if(reset) begin + buffers_0 <= 5'h0; + buffers_1 <= 5'h0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module EfxDMA_BufferCC_2_a048ca8f51874147a1cd65d43e6523ef ( + input wire [4:0] io_dataIn, + output wire [4:0] io_dataOut, + input wire dat0_i_clk, + input wire dat0_i_reset +); + + (* async_reg = "true" *) reg [4:0] buffers_0; + (* async_reg = "true" *) reg [4:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge dat0_i_clk) begin + if(dat0_i_reset) begin + buffers_0 <= 5'h0; + buffers_1 <= 5'h0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module EfxDMA_BmbContextRemover_1_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_input_cmd_valid, + output reg io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [127:0] io_input_cmd_payload_fragment_data, + input wire [15:0] io_input_cmd_payload_fragment_mask, + input wire [13:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [13:0] io_input_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + output wire [127:0] io_output_cmd_payload_fragment_data, + output wire [15:0] io_output_cmd_payload_fragment_mask, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire clk, + input wire reset +); + + reg fifoFork_thrown_translated_fifo_io_pop_ready; + wire fifoFork_thrown_translated_fifo_io_push_ready; + wire fifoFork_thrown_translated_fifo_io_pop_valid; + wire [13:0] fifoFork_thrown_translated_fifo_io_pop_payload_context; + wire [2:0] fifoFork_thrown_translated_fifo_io_occupancy; + wire [2:0] fifoFork_thrown_translated_fifo_io_availability; + wire fifoFork_valid; + reg fifoFork_ready; + wire fifoFork_payload_last; + wire [0:0] fifoFork_payload_fragment_opcode; + wire [31:0] fifoFork_payload_fragment_address; + wire [11:0] fifoFork_payload_fragment_length; + wire [127:0] fifoFork_payload_fragment_data; + wire [15:0] fifoFork_payload_fragment_mask; + wire [13:0] fifoFork_payload_fragment_context; + wire cmdFork_valid; + wire cmdFork_ready; + wire cmdFork_payload_last; + wire [0:0] cmdFork_payload_fragment_opcode; + wire [31:0] cmdFork_payload_fragment_address; + wire [11:0] cmdFork_payload_fragment_length; + wire [127:0] cmdFork_payload_fragment_data; + wire [15:0] cmdFork_payload_fragment_mask; + wire [13:0] cmdFork_payload_fragment_context; + reg io_input_cmd_fork2_logic_linkEnable_0; + reg io_input_cmd_fork2_logic_linkEnable_1; + wire when_Stream_l1063; + wire when_Stream_l1063_1; + wire fifoFork_fire; + wire cmdFork_fire; + wire [13:0] pushCtx_context; + reg fifoFork_payload_first; + wire when_Stream_l445; + reg fifoFork_thrown_valid; + wire fifoFork_thrown_ready; + wire fifoFork_thrown_payload_last; + wire [0:0] fifoFork_thrown_payload_fragment_opcode; + wire [31:0] fifoFork_thrown_payload_fragment_address; + wire [11:0] fifoFork_thrown_payload_fragment_length; + wire [127:0] fifoFork_thrown_payload_fragment_data; + wire [15:0] fifoFork_thrown_payload_fragment_mask; + wire [13:0] fifoFork_thrown_payload_fragment_context; + wire fifoFork_thrown_translated_valid; + wire fifoFork_thrown_translated_ready; + wire [13:0] fifoFork_thrown_translated_payload_context; + wire popCtx_valid; + wire popCtx_ready; + wire [13:0] popCtx_payload_context; + reg fifoFork_thrown_translated_fifo_io_pop_rValid; + reg [13:0] fifoFork_thrown_translated_fifo_io_pop_rData_context; + wire when_Stream_l375; + wire _zz_io_input_rsp_valid; + + EfxDMA_StreamFifo_1_a048ca8f51874147a1cd65d43e6523ef fifoFork_thrown_translated_fifo ( + .io_push_valid (fifoFork_thrown_translated_valid ), //i + .io_push_ready (fifoFork_thrown_translated_fifo_io_push_ready ), //o + .io_push_payload_context (fifoFork_thrown_translated_payload_context[13:0] ), //i + .io_pop_valid (fifoFork_thrown_translated_fifo_io_pop_valid ), //o + .io_pop_ready (fifoFork_thrown_translated_fifo_io_pop_ready ), //i + .io_pop_payload_context (fifoFork_thrown_translated_fifo_io_pop_payload_context[13:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (fifoFork_thrown_translated_fifo_io_occupancy[2:0] ), //o + .io_availability (fifoFork_thrown_translated_fifo_io_availability[2:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + io_input_cmd_ready = 1'b1; + if(when_Stream_l1063) begin + io_input_cmd_ready = 1'b0; + end + if(when_Stream_l1063_1) begin + io_input_cmd_ready = 1'b0; + end + end + + assign when_Stream_l1063 = ((! fifoFork_ready) && io_input_cmd_fork2_logic_linkEnable_0); + assign when_Stream_l1063_1 = ((! cmdFork_ready) && io_input_cmd_fork2_logic_linkEnable_1); + assign fifoFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_0); + assign fifoFork_payload_last = io_input_cmd_payload_last; + assign fifoFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign fifoFork_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign fifoFork_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign fifoFork_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign fifoFork_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign fifoFork_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign fifoFork_fire = (fifoFork_valid && fifoFork_ready); + assign cmdFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_1); + assign cmdFork_payload_last = io_input_cmd_payload_last; + assign cmdFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign cmdFork_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign cmdFork_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign cmdFork_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign cmdFork_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign cmdFork_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign cmdFork_fire = (cmdFork_valid && cmdFork_ready); + assign io_output_cmd_valid = cmdFork_valid; + assign cmdFork_ready = io_output_cmd_ready; + assign io_output_cmd_payload_last = cmdFork_payload_last; + assign io_output_cmd_payload_fragment_opcode = cmdFork_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = cmdFork_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = cmdFork_payload_fragment_length; + assign io_output_cmd_payload_fragment_data = cmdFork_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = cmdFork_payload_fragment_mask; + assign pushCtx_context = fifoFork_payload_fragment_context; + assign when_Stream_l445 = (! fifoFork_payload_first); + always @(*) begin + fifoFork_thrown_valid = fifoFork_valid; + if(when_Stream_l445) begin + fifoFork_thrown_valid = 1'b0; + end + end + + always @(*) begin + fifoFork_ready = fifoFork_thrown_ready; + if(when_Stream_l445) begin + fifoFork_ready = 1'b1; + end + end + + assign fifoFork_thrown_payload_last = fifoFork_payload_last; + assign fifoFork_thrown_payload_fragment_opcode = fifoFork_payload_fragment_opcode; + assign fifoFork_thrown_payload_fragment_address = fifoFork_payload_fragment_address; + assign fifoFork_thrown_payload_fragment_length = fifoFork_payload_fragment_length; + assign fifoFork_thrown_payload_fragment_data = fifoFork_payload_fragment_data; + assign fifoFork_thrown_payload_fragment_mask = fifoFork_payload_fragment_mask; + assign fifoFork_thrown_payload_fragment_context = fifoFork_payload_fragment_context; + assign fifoFork_thrown_translated_valid = fifoFork_thrown_valid; + assign fifoFork_thrown_ready = fifoFork_thrown_translated_ready; + assign fifoFork_thrown_translated_payload_context = pushCtx_context; + assign fifoFork_thrown_translated_ready = fifoFork_thrown_translated_fifo_io_push_ready; + always @(*) begin + fifoFork_thrown_translated_fifo_io_pop_ready = popCtx_ready; + if(when_Stream_l375) begin + fifoFork_thrown_translated_fifo_io_pop_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! popCtx_valid); + assign popCtx_valid = fifoFork_thrown_translated_fifo_io_pop_rValid; + assign popCtx_payload_context = fifoFork_thrown_translated_fifo_io_pop_rData_context; + assign popCtx_ready = ((io_output_rsp_valid && io_output_rsp_payload_last) && io_input_rsp_ready); + assign _zz_io_input_rsp_valid = (! (! popCtx_valid)); + assign io_output_rsp_ready = (io_input_rsp_ready && _zz_io_input_rsp_valid); + assign io_input_rsp_valid = (io_output_rsp_valid && _zz_io_input_rsp_valid); + assign io_input_rsp_payload_last = io_output_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_context = popCtx_payload_context; + always @(posedge clk) begin + if(reset) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; + fifoFork_payload_first <= 1'b1; + fifoFork_thrown_translated_fifo_io_pop_rValid <= 1'b0; + end else begin + if(fifoFork_fire) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdFork_fire) begin + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_cmd_ready) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; + end + if(fifoFork_fire) begin + fifoFork_payload_first <= fifoFork_payload_last; + end + if(fifoFork_thrown_translated_fifo_io_pop_ready) begin + fifoFork_thrown_translated_fifo_io_pop_rValid <= fifoFork_thrown_translated_fifo_io_pop_valid; + end + end + end + + always @(posedge clk) begin + if(fifoFork_thrown_translated_fifo_io_pop_ready) begin + fifoFork_thrown_translated_fifo_io_pop_rData_context <= fifoFork_thrown_translated_fifo_io_pop_payload_context; + end + end + + +endmodule + +module EfxDMA_BmbContextRemover_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_input_cmd_valid, + output reg io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [21:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [127:0] io_input_rsp_payload_fragment_data, + output wire [21:0] io_input_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [127:0] io_output_rsp_payload_fragment_data, + input wire clk, + input wire reset +); + + reg fifoFork_thrown_translated_fifo_io_pop_ready; + wire fifoFork_thrown_translated_fifo_io_push_ready; + wire fifoFork_thrown_translated_fifo_io_pop_valid; + wire [21:0] fifoFork_thrown_translated_fifo_io_pop_payload_context; + wire [2:0] fifoFork_thrown_translated_fifo_io_occupancy; + wire [2:0] fifoFork_thrown_translated_fifo_io_availability; + wire fifoFork_valid; + reg fifoFork_ready; + wire fifoFork_payload_last; + wire [0:0] fifoFork_payload_fragment_opcode; + wire [31:0] fifoFork_payload_fragment_address; + wire [11:0] fifoFork_payload_fragment_length; + wire [21:0] fifoFork_payload_fragment_context; + wire cmdFork_valid; + wire cmdFork_ready; + wire cmdFork_payload_last; + wire [0:0] cmdFork_payload_fragment_opcode; + wire [31:0] cmdFork_payload_fragment_address; + wire [11:0] cmdFork_payload_fragment_length; + wire [21:0] cmdFork_payload_fragment_context; + reg io_input_cmd_fork2_logic_linkEnable_0; + reg io_input_cmd_fork2_logic_linkEnable_1; + wire when_Stream_l1063; + wire when_Stream_l1063_1; + wire fifoFork_fire; + wire cmdFork_fire; + wire [21:0] pushCtx_context; + reg fifoFork_payload_first; + wire when_Stream_l445; + reg fifoFork_thrown_valid; + wire fifoFork_thrown_ready; + wire fifoFork_thrown_payload_last; + wire [0:0] fifoFork_thrown_payload_fragment_opcode; + wire [31:0] fifoFork_thrown_payload_fragment_address; + wire [11:0] fifoFork_thrown_payload_fragment_length; + wire [21:0] fifoFork_thrown_payload_fragment_context; + wire fifoFork_thrown_translated_valid; + wire fifoFork_thrown_translated_ready; + wire [21:0] fifoFork_thrown_translated_payload_context; + wire popCtx_valid; + wire popCtx_ready; + wire [21:0] popCtx_payload_context; + reg fifoFork_thrown_translated_fifo_io_pop_rValid; + reg [21:0] fifoFork_thrown_translated_fifo_io_pop_rData_context; + wire when_Stream_l375; + wire _zz_io_input_rsp_valid; + + EfxDMA_StreamFifo_a048ca8f51874147a1cd65d43e6523ef fifoFork_thrown_translated_fifo ( + .io_push_valid (fifoFork_thrown_translated_valid ), //i + .io_push_ready (fifoFork_thrown_translated_fifo_io_push_ready ), //o + .io_push_payload_context (fifoFork_thrown_translated_payload_context[21:0] ), //i + .io_pop_valid (fifoFork_thrown_translated_fifo_io_pop_valid ), //o + .io_pop_ready (fifoFork_thrown_translated_fifo_io_pop_ready ), //i + .io_pop_payload_context (fifoFork_thrown_translated_fifo_io_pop_payload_context[21:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (fifoFork_thrown_translated_fifo_io_occupancy[2:0] ), //o + .io_availability (fifoFork_thrown_translated_fifo_io_availability[2:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + io_input_cmd_ready = 1'b1; + if(when_Stream_l1063) begin + io_input_cmd_ready = 1'b0; + end + if(when_Stream_l1063_1) begin + io_input_cmd_ready = 1'b0; + end + end + + assign when_Stream_l1063 = ((! fifoFork_ready) && io_input_cmd_fork2_logic_linkEnable_0); + assign when_Stream_l1063_1 = ((! cmdFork_ready) && io_input_cmd_fork2_logic_linkEnable_1); + assign fifoFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_0); + assign fifoFork_payload_last = io_input_cmd_payload_last; + assign fifoFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign fifoFork_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign fifoFork_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign fifoFork_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign fifoFork_fire = (fifoFork_valid && fifoFork_ready); + assign cmdFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_1); + assign cmdFork_payload_last = io_input_cmd_payload_last; + assign cmdFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign cmdFork_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign cmdFork_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign cmdFork_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign cmdFork_fire = (cmdFork_valid && cmdFork_ready); + assign io_output_cmd_valid = cmdFork_valid; + assign cmdFork_ready = io_output_cmd_ready; + assign io_output_cmd_payload_last = cmdFork_payload_last; + assign io_output_cmd_payload_fragment_opcode = cmdFork_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = cmdFork_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = cmdFork_payload_fragment_length; + assign pushCtx_context = fifoFork_payload_fragment_context; + assign when_Stream_l445 = (! fifoFork_payload_first); + always @(*) begin + fifoFork_thrown_valid = fifoFork_valid; + if(when_Stream_l445) begin + fifoFork_thrown_valid = 1'b0; + end + end + + always @(*) begin + fifoFork_ready = fifoFork_thrown_ready; + if(when_Stream_l445) begin + fifoFork_ready = 1'b1; + end + end + + assign fifoFork_thrown_payload_last = fifoFork_payload_last; + assign fifoFork_thrown_payload_fragment_opcode = fifoFork_payload_fragment_opcode; + assign fifoFork_thrown_payload_fragment_address = fifoFork_payload_fragment_address; + assign fifoFork_thrown_payload_fragment_length = fifoFork_payload_fragment_length; + assign fifoFork_thrown_payload_fragment_context = fifoFork_payload_fragment_context; + assign fifoFork_thrown_translated_valid = fifoFork_thrown_valid; + assign fifoFork_thrown_ready = fifoFork_thrown_translated_ready; + assign fifoFork_thrown_translated_payload_context = pushCtx_context; + assign fifoFork_thrown_translated_ready = fifoFork_thrown_translated_fifo_io_push_ready; + always @(*) begin + fifoFork_thrown_translated_fifo_io_pop_ready = popCtx_ready; + if(when_Stream_l375) begin + fifoFork_thrown_translated_fifo_io_pop_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! popCtx_valid); + assign popCtx_valid = fifoFork_thrown_translated_fifo_io_pop_rValid; + assign popCtx_payload_context = fifoFork_thrown_translated_fifo_io_pop_rData_context; + assign popCtx_ready = ((io_output_rsp_valid && io_output_rsp_payload_last) && io_input_rsp_ready); + assign _zz_io_input_rsp_valid = (! (! popCtx_valid)); + assign io_output_rsp_ready = (io_input_rsp_ready && _zz_io_input_rsp_valid); + assign io_input_rsp_valid = (io_output_rsp_valid && _zz_io_input_rsp_valid); + assign io_input_rsp_payload_last = io_output_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = popCtx_payload_context; + always @(posedge clk) begin + if(reset) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; + fifoFork_payload_first <= 1'b1; + fifoFork_thrown_translated_fifo_io_pop_rValid <= 1'b0; + end else begin + if(fifoFork_fire) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdFork_fire) begin + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_cmd_ready) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; + end + if(fifoFork_fire) begin + fifoFork_payload_first <= fifoFork_payload_last; + end + if(fifoFork_thrown_translated_fifo_io_pop_ready) begin + fifoFork_thrown_translated_fifo_io_pop_rValid <= fifoFork_thrown_translated_fifo_io_pop_valid; + end + end + end + + always @(posedge clk) begin + if(fifoFork_thrown_translated_fifo_io_pop_ready) begin + fifoFork_thrown_translated_fifo_io_pop_rData_context <= fifoFork_thrown_translated_fifo_io_pop_payload_context; + end + end + + +endmodule + +module EfxDMA_FlowCCUnsafeByToggle_1_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_input_valid, + input wire [31:0] io_input_payload_PRDATA, + input wire io_input_payload_PSLVERROR, + output wire io_output_valid, + output wire [31:0] io_output_payload_PRDATA, + output wire io_output_payload_PSLVERROR, + input wire clk, + input wire reset, + input wire ctrl_clk, + input wire ctrl_reset +); + + wire inputArea_target_buffercc_io_dataOut; + reg inputArea_target; + reg [31:0] inputArea_data_PRDATA; + reg inputArea_data_PSLVERROR; + wire outputArea_target; + reg outputArea_hit; + wire outputArea_flow_valid; + wire [31:0] outputArea_flow_payload_PRDATA; + wire outputArea_flow_payload_PSLVERROR; + reg outputArea_flow_m2sPipe_valid; + (* async_reg = "true" *) reg [31:0] outputArea_flow_m2sPipe_payload_PRDATA; + (* async_reg = "true" *) reg outputArea_flow_m2sPipe_payload_PSLVERROR; + + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_1_a048ca8f51874147a1cd65d43e6523ef inputArea_target_buffercc ( + .io_dataIn (inputArea_target ), //i + .io_dataOut (inputArea_target_buffercc_io_dataOut), //o + .ctrl_clk (ctrl_clk ), //i + .ctrl_reset (ctrl_reset ) //i + ); + assign outputArea_target = inputArea_target_buffercc_io_dataOut; + assign outputArea_flow_valid = (outputArea_target != outputArea_hit); + assign outputArea_flow_payload_PRDATA = inputArea_data_PRDATA; + assign outputArea_flow_payload_PSLVERROR = inputArea_data_PSLVERROR; + assign io_output_valid = outputArea_flow_m2sPipe_valid; + assign io_output_payload_PRDATA = outputArea_flow_m2sPipe_payload_PRDATA; + assign io_output_payload_PSLVERROR = outputArea_flow_m2sPipe_payload_PSLVERROR; + always @(posedge clk) begin + if(reset) begin + inputArea_target <= 1'b0; + end else begin + if(io_input_valid) begin + inputArea_target <= (! inputArea_target); + end + end + end + + always @(posedge clk) begin + if(io_input_valid) begin + inputArea_data_PRDATA <= io_input_payload_PRDATA; + inputArea_data_PSLVERROR <= io_input_payload_PSLVERROR; + end + end + + always @(posedge ctrl_clk) begin + if(ctrl_reset) begin + outputArea_flow_m2sPipe_valid <= 1'b0; + outputArea_hit <= 1'b0; + end else begin + outputArea_hit <= outputArea_target; + outputArea_flow_m2sPipe_valid <= outputArea_flow_valid; + end + end + + always @(posedge ctrl_clk) begin + if(outputArea_flow_valid) begin + outputArea_flow_m2sPipe_payload_PRDATA <= outputArea_flow_payload_PRDATA; + outputArea_flow_m2sPipe_payload_PSLVERROR <= outputArea_flow_payload_PSLVERROR; + end + end + + +endmodule + +module EfxDMA_FlowCCUnsafeByToggle_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_input_valid, + input wire [13:0] io_input_payload_PADDR, + input wire io_input_payload_PWRITE, + input wire [31:0] io_input_payload_PWDATA, + output wire io_output_valid, + output wire [13:0] io_output_payload_PADDR, + output wire io_output_payload_PWRITE, + output wire [31:0] io_output_payload_PWDATA, + input wire ctrl_clk, + input wire ctrl_reset, + input wire clk, + input wire reset +); + + wire inputArea_target_buffercc_io_dataOut; + reg inputArea_target; + reg [13:0] inputArea_data_PADDR; + reg inputArea_data_PWRITE; + reg [31:0] inputArea_data_PWDATA; + wire outputArea_target; + reg outputArea_hit; + wire outputArea_flow_valid; + wire [13:0] outputArea_flow_payload_PADDR; + wire outputArea_flow_payload_PWRITE; + wire [31:0] outputArea_flow_payload_PWDATA; + + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_a048ca8f51874147a1cd65d43e6523ef inputArea_target_buffercc ( + .io_dataIn (inputArea_target ), //i + .io_dataOut (inputArea_target_buffercc_io_dataOut), //o + .clk (clk ), //i + .reset (reset ) //i + ); + assign outputArea_target = inputArea_target_buffercc_io_dataOut; + assign outputArea_flow_valid = (outputArea_target != outputArea_hit); + assign outputArea_flow_payload_PADDR = inputArea_data_PADDR; + assign outputArea_flow_payload_PWRITE = inputArea_data_PWRITE; + assign outputArea_flow_payload_PWDATA = inputArea_data_PWDATA; + assign io_output_valid = outputArea_flow_valid; + assign io_output_payload_PADDR = outputArea_flow_payload_PADDR; + assign io_output_payload_PWRITE = outputArea_flow_payload_PWRITE; + assign io_output_payload_PWDATA = outputArea_flow_payload_PWDATA; + always @(posedge ctrl_clk) begin + if(ctrl_reset) begin + inputArea_target <= 1'b0; + end else begin + if(io_input_valid) begin + inputArea_target <= (! inputArea_target); + end + end + end + + always @(posedge ctrl_clk) begin + if(io_input_valid) begin + inputArea_data_PADDR <= io_input_payload_PADDR; + inputArea_data_PWRITE <= io_input_payload_PWRITE; + inputArea_data_PWDATA <= io_input_payload_PWDATA; + end + end + + always @(posedge clk) begin + if(reset) begin + outputArea_hit <= 1'b0; + end else begin + outputArea_hit <= outputArea_target; + end + end + + +endmodule + +module EfxDMA_Aggregator_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_input_valid, + output reg io_input_ready, + input wire [127:0] io_input_payload_data, + input wire [15:0] io_input_payload_mask, + output reg [127:0] io_output_data, + output reg [15:0] io_output_mask, + input wire io_output_enough, + input wire io_output_consume, + output wire io_output_consumed, + input wire [3:0] io_output_lastByteUsed, + output wire [3:0] io_output_usedUntil, + input wire io_flush, + input wire [3:0] io_offset, + input wire [11:0] io_burstLength, + input wire clk, + input wire reset +); + + reg [0:0] _zz_s0_countOnesLogic_0_1; + wire [0:0] _zz_s0_countOnesLogic_0_2; + reg [1:0] _zz_s0_countOnesLogic_1_1; + wire [1:0] _zz_s0_countOnesLogic_1_2; + reg [1:0] _zz_s0_countOnesLogic_2_1; + wire [2:0] _zz_s0_countOnesLogic_2_2; + reg [2:0] _zz_s0_countOnesLogic_3_9; + wire [2:0] _zz_s0_countOnesLogic_3_10; + reg [2:0] _zz_s0_countOnesLogic_3_11; + wire [2:0] _zz_s0_countOnesLogic_3_12; + wire [0:0] _zz_s0_countOnesLogic_3_13; + reg [2:0] _zz_s0_countOnesLogic_4_9; + wire [2:0] _zz_s0_countOnesLogic_4_10; + reg [2:0] _zz_s0_countOnesLogic_4_11; + wire [2:0] _zz_s0_countOnesLogic_4_12; + wire [1:0] _zz_s0_countOnesLogic_4_13; + reg [2:0] _zz_s0_countOnesLogic_5_9; + wire [2:0] _zz_s0_countOnesLogic_5_10; + reg [2:0] _zz_s0_countOnesLogic_5_11; + wire [2:0] _zz_s0_countOnesLogic_5_12; + wire [2:0] _zz_s0_countOnesLogic_6_9; + reg [2:0] _zz_s0_countOnesLogic_6_10; + wire [2:0] _zz_s0_countOnesLogic_6_11; + reg [2:0] _zz_s0_countOnesLogic_6_12; + wire [2:0] _zz_s0_countOnesLogic_6_13; + reg [2:0] _zz_s0_countOnesLogic_6_14; + wire [2:0] _zz_s0_countOnesLogic_6_15; + wire [0:0] _zz_s0_countOnesLogic_6_16; + wire [3:0] _zz_s0_countOnesLogic_7_9; + reg [3:0] _zz_s0_countOnesLogic_7_10; + wire [2:0] _zz_s0_countOnesLogic_7_11; + reg [3:0] _zz_s0_countOnesLogic_7_12; + wire [2:0] _zz_s0_countOnesLogic_7_13; + reg [3:0] _zz_s0_countOnesLogic_7_14; + wire [2:0] _zz_s0_countOnesLogic_7_15; + wire [1:0] _zz_s0_countOnesLogic_7_16; + wire [3:0] _zz_s0_countOnesLogic_8_9; + reg [3:0] _zz_s0_countOnesLogic_8_10; + wire [2:0] _zz_s0_countOnesLogic_8_11; + reg [3:0] _zz_s0_countOnesLogic_8_12; + wire [2:0] _zz_s0_countOnesLogic_8_13; + reg [3:0] _zz_s0_countOnesLogic_8_14; + wire [2:0] _zz_s0_countOnesLogic_8_15; + wire [3:0] _zz_s0_countOnesLogic_9_9; + reg [3:0] _zz_s0_countOnesLogic_9_10; + wire [2:0] _zz_s0_countOnesLogic_9_11; + reg [3:0] _zz_s0_countOnesLogic_9_12; + wire [2:0] _zz_s0_countOnesLogic_9_13; + wire [3:0] _zz_s0_countOnesLogic_9_14; + reg [3:0] _zz_s0_countOnesLogic_9_15; + wire [2:0] _zz_s0_countOnesLogic_9_16; + reg [3:0] _zz_s0_countOnesLogic_9_17; + wire [2:0] _zz_s0_countOnesLogic_9_18; + wire [0:0] _zz_s0_countOnesLogic_9_19; + wire [3:0] _zz_s0_countOnesLogic_10_9; + reg [3:0] _zz_s0_countOnesLogic_10_10; + wire [2:0] _zz_s0_countOnesLogic_10_11; + reg [3:0] _zz_s0_countOnesLogic_10_12; + wire [2:0] _zz_s0_countOnesLogic_10_13; + wire [3:0] _zz_s0_countOnesLogic_10_14; + reg [3:0] _zz_s0_countOnesLogic_10_15; + wire [2:0] _zz_s0_countOnesLogic_10_16; + reg [3:0] _zz_s0_countOnesLogic_10_17; + wire [2:0] _zz_s0_countOnesLogic_10_18; + wire [1:0] _zz_s0_countOnesLogic_10_19; + wire [3:0] _zz_s0_countOnesLogic_11_9; + reg [3:0] _zz_s0_countOnesLogic_11_10; + wire [2:0] _zz_s0_countOnesLogic_11_11; + reg [3:0] _zz_s0_countOnesLogic_11_12; + wire [2:0] _zz_s0_countOnesLogic_11_13; + wire [3:0] _zz_s0_countOnesLogic_11_14; + reg [3:0] _zz_s0_countOnesLogic_11_15; + wire [2:0] _zz_s0_countOnesLogic_11_16; + reg [3:0] _zz_s0_countOnesLogic_11_17; + wire [2:0] _zz_s0_countOnesLogic_11_18; + wire [3:0] _zz_s0_countOnesLogic_12_9; + wire [3:0] _zz_s0_countOnesLogic_12_10; + reg [3:0] _zz_s0_countOnesLogic_12_11; + wire [2:0] _zz_s0_countOnesLogic_12_12; + reg [3:0] _zz_s0_countOnesLogic_12_13; + wire [2:0] _zz_s0_countOnesLogic_12_14; + wire [3:0] _zz_s0_countOnesLogic_12_15; + reg [3:0] _zz_s0_countOnesLogic_12_16; + wire [2:0] _zz_s0_countOnesLogic_12_17; + reg [3:0] _zz_s0_countOnesLogic_12_18; + wire [2:0] _zz_s0_countOnesLogic_12_19; + reg [3:0] _zz_s0_countOnesLogic_12_20; + wire [2:0] _zz_s0_countOnesLogic_12_21; + wire [0:0] _zz_s0_countOnesLogic_12_22; + wire [3:0] _zz_s0_countOnesLogic_13_9; + wire [3:0] _zz_s0_countOnesLogic_13_10; + reg [3:0] _zz_s0_countOnesLogic_13_11; + wire [2:0] _zz_s0_countOnesLogic_13_12; + reg [3:0] _zz_s0_countOnesLogic_13_13; + wire [2:0] _zz_s0_countOnesLogic_13_14; + wire [3:0] _zz_s0_countOnesLogic_13_15; + reg [3:0] _zz_s0_countOnesLogic_13_16; + wire [2:0] _zz_s0_countOnesLogic_13_17; + reg [3:0] _zz_s0_countOnesLogic_13_18; + wire [2:0] _zz_s0_countOnesLogic_13_19; + reg [3:0] _zz_s0_countOnesLogic_13_20; + wire [2:0] _zz_s0_countOnesLogic_13_21; + wire [1:0] _zz_s0_countOnesLogic_13_22; + wire [3:0] _zz_s0_countOnesLogic_14_9; + wire [3:0] _zz_s0_countOnesLogic_14_10; + reg [3:0] _zz_s0_countOnesLogic_14_11; + wire [2:0] _zz_s0_countOnesLogic_14_12; + reg [3:0] _zz_s0_countOnesLogic_14_13; + wire [2:0] _zz_s0_countOnesLogic_14_14; + wire [3:0] _zz_s0_countOnesLogic_14_15; + reg [3:0] _zz_s0_countOnesLogic_14_16; + wire [2:0] _zz_s0_countOnesLogic_14_17; + reg [3:0] _zz_s0_countOnesLogic_14_18; + wire [2:0] _zz_s0_countOnesLogic_14_19; + reg [3:0] _zz_s0_countOnesLogic_14_20; + wire [2:0] _zz_s0_countOnesLogic_14_21; + wire [4:0] _zz_s0_countOnesLogic_15_8; + wire [4:0] _zz_s0_countOnesLogic_15_9; + reg [4:0] _zz_s0_countOnesLogic_15_10; + wire [2:0] _zz_s0_countOnesLogic_15_11; + reg [4:0] _zz_s0_countOnesLogic_15_12; + wire [2:0] _zz_s0_countOnesLogic_15_13; + wire [4:0] _zz_s0_countOnesLogic_15_14; + reg [4:0] _zz_s0_countOnesLogic_15_15; + wire [2:0] _zz_s0_countOnesLogic_15_16; + reg [4:0] _zz_s0_countOnesLogic_15_17; + wire [2:0] _zz_s0_countOnesLogic_15_18; + wire [4:0] _zz_s0_countOnesLogic_15_19; + reg [4:0] _zz_s0_countOnesLogic_15_20; + wire [2:0] _zz_s0_countOnesLogic_15_21; + reg [4:0] _zz_s0_countOnesLogic_15_22; + wire [2:0] _zz_s0_countOnesLogic_15_23; + wire [0:0] _zz_s0_countOnesLogic_15_24; + wire [4:0] _zz_s1_offsetNext; + wire [12:0] _zz_s1_byteCounter; + wire [3:0] _zz_s1_inputIndexes_1; + wire [3:0] _zz_s1_inputIndexes_2; + wire [3:0] _zz_s1_inputIndexes_3; + wire [3:0] _zz_s1_inputIndexes_4; + wire [3:0] _zz_s1_inputIndexes_5; + wire [3:0] _zz_s1_inputIndexes_6; + wire [3:0] _zz_s1_inputIndexes_7; + wire [0:0] _zz_s1_outputPayload_selValid_240; + wire [6:0] _zz_s1_outputPayload_selValid_241; + wire [0:0] _zz_s1_outputPayload_selValid_242; + wire [6:0] _zz_s1_outputPayload_selValid_243; + wire [0:0] _zz_s1_outputPayload_selValid_244; + wire [6:0] _zz_s1_outputPayload_selValid_245; + wire [0:0] _zz_s1_outputPayload_selValid_246; + wire [6:0] _zz_s1_outputPayload_selValid_247; + wire [0:0] _zz_s1_outputPayload_selValid_248; + wire [6:0] _zz_s1_outputPayload_selValid_249; + wire [0:0] _zz_s1_outputPayload_selValid_250; + wire [6:0] _zz_s1_outputPayload_selValid_251; + wire [0:0] _zz_s1_outputPayload_selValid_252; + wire [6:0] _zz_s1_outputPayload_selValid_253; + wire [0:0] _zz_s1_outputPayload_selValid_254; + wire [6:0] _zz_s1_outputPayload_selValid_255; + wire [0:0] _zz_s1_outputPayload_selValid_256; + wire [6:0] _zz_s1_outputPayload_selValid_257; + wire [0:0] _zz_s1_outputPayload_selValid_258; + wire [6:0] _zz_s1_outputPayload_selValid_259; + wire [0:0] _zz_s1_outputPayload_selValid_260; + wire [6:0] _zz_s1_outputPayload_selValid_261; + wire [0:0] _zz_s1_outputPayload_selValid_262; + wire [6:0] _zz_s1_outputPayload_selValid_263; + wire [0:0] _zz_s1_outputPayload_selValid_264; + wire [6:0] _zz_s1_outputPayload_selValid_265; + wire [0:0] _zz_s1_outputPayload_selValid_266; + wire [6:0] _zz_s1_outputPayload_selValid_267; + wire [0:0] _zz_s1_outputPayload_selValid_268; + wire [6:0] _zz_s1_outputPayload_selValid_269; + wire [0:0] _zz_s1_outputPayload_selValid_270; + wire [6:0] _zz_s1_outputPayload_selValid_271; + wire [12:0] _zz_when_DmaSg_l1464; + reg [7:0] _zz_s2_byteLogic_0_inputData; + reg [7:0] _zz_s2_byteLogic_1_inputData; + reg [7:0] _zz_s2_byteLogic_2_inputData; + reg [7:0] _zz_s2_byteLogic_3_inputData; + reg [7:0] _zz_s2_byteLogic_4_inputData; + reg [7:0] _zz_s2_byteLogic_5_inputData; + reg [7:0] _zz_s2_byteLogic_6_inputData; + reg [7:0] _zz_s2_byteLogic_7_inputData; + reg [7:0] _zz_s2_byteLogic_8_inputData; + reg [7:0] _zz_s2_byteLogic_9_inputData; + reg [7:0] _zz_s2_byteLogic_10_inputData; + reg [7:0] _zz_s2_byteLogic_11_inputData; + reg [7:0] _zz_s2_byteLogic_12_inputData; + reg [7:0] _zz_s2_byteLogic_13_inputData; + reg [7:0] _zz_s2_byteLogic_14_inputData; + reg [7:0] _zz_s2_byteLogic_15_inputData; + reg [3:0] _zz_io_output_usedUntil_4; + wire [3:0] _zz_io_output_usedUntil_5; + wire s0_input_valid; + wire s0_input_ready; + wire [127:0] s0_input_payload_data; + wire [15:0] s0_input_payload_mask; + reg io_input_rValid; + reg [127:0] io_input_rData_data; + reg [15:0] io_input_rData_mask; + wire when_Stream_l375; + wire _zz_s0_countOnesLogic_0; + wire _zz_s0_countOnesLogic_1; + wire _zz_s0_countOnesLogic_2; + wire _zz_s0_countOnesLogic_3; + wire _zz_s0_countOnesLogic_4; + wire _zz_s0_countOnesLogic_5; + wire _zz_s0_countOnesLogic_6; + wire _zz_s0_countOnesLogic_7; + wire _zz_s0_countOnesLogic_8; + wire _zz_s0_countOnesLogic_9; + wire _zz_s0_countOnesLogic_10; + wire _zz_s0_countOnesLogic_11; + wire _zz_s0_countOnesLogic_12; + wire _zz_s0_countOnesLogic_13; + wire _zz_s0_countOnesLogic_14; + wire [0:0] s0_countOnesLogic_0; + wire [1:0] s0_countOnesLogic_1; + wire [1:0] s0_countOnesLogic_2; + wire [2:0] _zz_s0_countOnesLogic_3_1; + wire [2:0] _zz_s0_countOnesLogic_3_2; + wire [2:0] _zz_s0_countOnesLogic_3_3; + wire [2:0] _zz_s0_countOnesLogic_3_4; + wire [2:0] _zz_s0_countOnesLogic_3_5; + wire [2:0] _zz_s0_countOnesLogic_3_6; + wire [2:0] _zz_s0_countOnesLogic_3_7; + wire [2:0] _zz_s0_countOnesLogic_3_8; + wire [2:0] s0_countOnesLogic_3; + wire [2:0] _zz_s0_countOnesLogic_4_1; + wire [2:0] _zz_s0_countOnesLogic_4_2; + wire [2:0] _zz_s0_countOnesLogic_4_3; + wire [2:0] _zz_s0_countOnesLogic_4_4; + wire [2:0] _zz_s0_countOnesLogic_4_5; + wire [2:0] _zz_s0_countOnesLogic_4_6; + wire [2:0] _zz_s0_countOnesLogic_4_7; + wire [2:0] _zz_s0_countOnesLogic_4_8; + wire [2:0] s0_countOnesLogic_4; + wire [2:0] _zz_s0_countOnesLogic_5_1; + wire [2:0] _zz_s0_countOnesLogic_5_2; + wire [2:0] _zz_s0_countOnesLogic_5_3; + wire [2:0] _zz_s0_countOnesLogic_5_4; + wire [2:0] _zz_s0_countOnesLogic_5_5; + wire [2:0] _zz_s0_countOnesLogic_5_6; + wire [2:0] _zz_s0_countOnesLogic_5_7; + wire [2:0] _zz_s0_countOnesLogic_5_8; + wire [2:0] s0_countOnesLogic_5; + wire [2:0] _zz_s0_countOnesLogic_6_1; + wire [2:0] _zz_s0_countOnesLogic_6_2; + wire [2:0] _zz_s0_countOnesLogic_6_3; + wire [2:0] _zz_s0_countOnesLogic_6_4; + wire [2:0] _zz_s0_countOnesLogic_6_5; + wire [2:0] _zz_s0_countOnesLogic_6_6; + wire [2:0] _zz_s0_countOnesLogic_6_7; + wire [2:0] _zz_s0_countOnesLogic_6_8; + wire [2:0] s0_countOnesLogic_6; + wire [3:0] _zz_s0_countOnesLogic_7_1; + wire [3:0] _zz_s0_countOnesLogic_7_2; + wire [3:0] _zz_s0_countOnesLogic_7_3; + wire [3:0] _zz_s0_countOnesLogic_7_4; + wire [3:0] _zz_s0_countOnesLogic_7_5; + wire [3:0] _zz_s0_countOnesLogic_7_6; + wire [3:0] _zz_s0_countOnesLogic_7_7; + wire [3:0] _zz_s0_countOnesLogic_7_8; + wire [3:0] s0_countOnesLogic_7; + wire [3:0] _zz_s0_countOnesLogic_8_1; + wire [3:0] _zz_s0_countOnesLogic_8_2; + wire [3:0] _zz_s0_countOnesLogic_8_3; + wire [3:0] _zz_s0_countOnesLogic_8_4; + wire [3:0] _zz_s0_countOnesLogic_8_5; + wire [3:0] _zz_s0_countOnesLogic_8_6; + wire [3:0] _zz_s0_countOnesLogic_8_7; + wire [3:0] _zz_s0_countOnesLogic_8_8; + wire [3:0] s0_countOnesLogic_8; + wire [3:0] _zz_s0_countOnesLogic_9_1; + wire [3:0] _zz_s0_countOnesLogic_9_2; + wire [3:0] _zz_s0_countOnesLogic_9_3; + wire [3:0] _zz_s0_countOnesLogic_9_4; + wire [3:0] _zz_s0_countOnesLogic_9_5; + wire [3:0] _zz_s0_countOnesLogic_9_6; + wire [3:0] _zz_s0_countOnesLogic_9_7; + wire [3:0] _zz_s0_countOnesLogic_9_8; + wire [3:0] s0_countOnesLogic_9; + wire [3:0] _zz_s0_countOnesLogic_10_1; + wire [3:0] _zz_s0_countOnesLogic_10_2; + wire [3:0] _zz_s0_countOnesLogic_10_3; + wire [3:0] _zz_s0_countOnesLogic_10_4; + wire [3:0] _zz_s0_countOnesLogic_10_5; + wire [3:0] _zz_s0_countOnesLogic_10_6; + wire [3:0] _zz_s0_countOnesLogic_10_7; + wire [3:0] _zz_s0_countOnesLogic_10_8; + wire [3:0] s0_countOnesLogic_10; + wire [3:0] _zz_s0_countOnesLogic_11_1; + wire [3:0] _zz_s0_countOnesLogic_11_2; + wire [3:0] _zz_s0_countOnesLogic_11_3; + wire [3:0] _zz_s0_countOnesLogic_11_4; + wire [3:0] _zz_s0_countOnesLogic_11_5; + wire [3:0] _zz_s0_countOnesLogic_11_6; + wire [3:0] _zz_s0_countOnesLogic_11_7; + wire [3:0] _zz_s0_countOnesLogic_11_8; + wire [3:0] s0_countOnesLogic_11; + wire [3:0] _zz_s0_countOnesLogic_12_1; + wire [3:0] _zz_s0_countOnesLogic_12_2; + wire [3:0] _zz_s0_countOnesLogic_12_3; + wire [3:0] _zz_s0_countOnesLogic_12_4; + wire [3:0] _zz_s0_countOnesLogic_12_5; + wire [3:0] _zz_s0_countOnesLogic_12_6; + wire [3:0] _zz_s0_countOnesLogic_12_7; + wire [3:0] _zz_s0_countOnesLogic_12_8; + wire [3:0] s0_countOnesLogic_12; + wire [3:0] _zz_s0_countOnesLogic_13_1; + wire [3:0] _zz_s0_countOnesLogic_13_2; + wire [3:0] _zz_s0_countOnesLogic_13_3; + wire [3:0] _zz_s0_countOnesLogic_13_4; + wire [3:0] _zz_s0_countOnesLogic_13_5; + wire [3:0] _zz_s0_countOnesLogic_13_6; + wire [3:0] _zz_s0_countOnesLogic_13_7; + wire [3:0] _zz_s0_countOnesLogic_13_8; + wire [3:0] s0_countOnesLogic_13; + wire [3:0] _zz_s0_countOnesLogic_14_1; + wire [3:0] _zz_s0_countOnesLogic_14_2; + wire [3:0] _zz_s0_countOnesLogic_14_3; + wire [3:0] _zz_s0_countOnesLogic_14_4; + wire [3:0] _zz_s0_countOnesLogic_14_5; + wire [3:0] _zz_s0_countOnesLogic_14_6; + wire [3:0] _zz_s0_countOnesLogic_14_7; + wire [3:0] _zz_s0_countOnesLogic_14_8; + wire [3:0] s0_countOnesLogic_14; + wire [4:0] _zz_s0_countOnesLogic_15; + wire [4:0] _zz_s0_countOnesLogic_15_1; + wire [4:0] _zz_s0_countOnesLogic_15_2; + wire [4:0] _zz_s0_countOnesLogic_15_3; + wire [4:0] _zz_s0_countOnesLogic_15_4; + wire [4:0] _zz_s0_countOnesLogic_15_5; + wire [4:0] _zz_s0_countOnesLogic_15_6; + wire [4:0] _zz_s0_countOnesLogic_15_7; + wire [4:0] s0_countOnesLogic_15; + wire [127:0] s0_outputPayload_cmd_data; + wire [15:0] s0_outputPayload_cmd_mask; + wire [0:0] s0_outputPayload_countOnes_0; + wire [1:0] s0_outputPayload_countOnes_1; + wire [1:0] s0_outputPayload_countOnes_2; + wire [2:0] s0_outputPayload_countOnes_3; + wire [2:0] s0_outputPayload_countOnes_4; + wire [2:0] s0_outputPayload_countOnes_5; + wire [2:0] s0_outputPayload_countOnes_6; + wire [3:0] s0_outputPayload_countOnes_7; + wire [3:0] s0_outputPayload_countOnes_8; + wire [3:0] s0_outputPayload_countOnes_9; + wire [3:0] s0_outputPayload_countOnes_10; + wire [3:0] s0_outputPayload_countOnes_11; + wire [3:0] s0_outputPayload_countOnes_12; + wire [3:0] s0_outputPayload_countOnes_13; + wire [3:0] s0_outputPayload_countOnes_14; + wire [4:0] s0_outputPayload_countOnes_15; + wire s0_output_valid; + reg s0_output_ready; + wire [127:0] s0_output_payload_cmd_data; + wire [15:0] s0_output_payload_cmd_mask; + wire [0:0] s0_output_payload_countOnes_0; + wire [1:0] s0_output_payload_countOnes_1; + wire [1:0] s0_output_payload_countOnes_2; + wire [2:0] s0_output_payload_countOnes_3; + wire [2:0] s0_output_payload_countOnes_4; + wire [2:0] s0_output_payload_countOnes_5; + wire [2:0] s0_output_payload_countOnes_6; + wire [3:0] s0_output_payload_countOnes_7; + wire [3:0] s0_output_payload_countOnes_8; + wire [3:0] s0_output_payload_countOnes_9; + wire [3:0] s0_output_payload_countOnes_10; + wire [3:0] s0_output_payload_countOnes_11; + wire [3:0] s0_output_payload_countOnes_12; + wire [3:0] s0_output_payload_countOnes_13; + wire [3:0] s0_output_payload_countOnes_14; + wire [4:0] s0_output_payload_countOnes_15; + wire s1_input_valid; + wire s1_input_ready; + wire [127:0] s1_input_payload_cmd_data; + wire [15:0] s1_input_payload_cmd_mask; + wire [0:0] s1_input_payload_countOnes_0; + wire [1:0] s1_input_payload_countOnes_1; + wire [1:0] s1_input_payload_countOnes_2; + wire [2:0] s1_input_payload_countOnes_3; + wire [2:0] s1_input_payload_countOnes_4; + wire [2:0] s1_input_payload_countOnes_5; + wire [2:0] s1_input_payload_countOnes_6; + wire [3:0] s1_input_payload_countOnes_7; + wire [3:0] s1_input_payload_countOnes_8; + wire [3:0] s1_input_payload_countOnes_9; + wire [3:0] s1_input_payload_countOnes_10; + wire [3:0] s1_input_payload_countOnes_11; + wire [3:0] s1_input_payload_countOnes_12; + wire [3:0] s1_input_payload_countOnes_13; + wire [3:0] s1_input_payload_countOnes_14; + wire [4:0] s1_input_payload_countOnes_15; + reg s0_output_rValid; + reg [127:0] s0_output_rData_cmd_data; + reg [15:0] s0_output_rData_cmd_mask; + reg [0:0] s0_output_rData_countOnes_0; + reg [1:0] s0_output_rData_countOnes_1; + reg [1:0] s0_output_rData_countOnes_2; + reg [2:0] s0_output_rData_countOnes_3; + reg [2:0] s0_output_rData_countOnes_4; + reg [2:0] s0_output_rData_countOnes_5; + reg [2:0] s0_output_rData_countOnes_6; + reg [3:0] s0_output_rData_countOnes_7; + reg [3:0] s0_output_rData_countOnes_8; + reg [3:0] s0_output_rData_countOnes_9; + reg [3:0] s0_output_rData_countOnes_10; + reg [3:0] s0_output_rData_countOnes_11; + reg [3:0] s0_output_rData_countOnes_12; + reg [3:0] s0_output_rData_countOnes_13; + reg [3:0] s0_output_rData_countOnes_14; + reg [4:0] s0_output_rData_countOnes_15; + wire when_Stream_l375_1; + reg [3:0] s1_offset; + wire [4:0] s1_offsetNext; + wire s1_input_fire; + reg [12:0] s1_byteCounter; + wire [3:0] s1_inputIndexes_0; + wire [3:0] s1_inputIndexes_1; + wire [3:0] s1_inputIndexes_2; + wire [3:0] s1_inputIndexes_3; + wire [3:0] s1_inputIndexes_4; + wire [3:0] s1_inputIndexes_5; + wire [3:0] s1_inputIndexes_6; + wire [3:0] s1_inputIndexes_7; + wire [3:0] s1_inputIndexes_8; + wire [3:0] s1_inputIndexes_9; + wire [3:0] s1_inputIndexes_10; + wire [3:0] s1_inputIndexes_11; + wire [3:0] s1_inputIndexes_12; + wire [3:0] s1_inputIndexes_13; + wire [3:0] s1_inputIndexes_14; + wire [3:0] s1_inputIndexes_15; + wire [127:0] s1_outputPayload_cmd_data; + wire [15:0] s1_outputPayload_cmd_mask; + wire [3:0] s1_outputPayload_index_0; + wire [3:0] s1_outputPayload_index_1; + wire [3:0] s1_outputPayload_index_2; + wire [3:0] s1_outputPayload_index_3; + wire [3:0] s1_outputPayload_index_4; + wire [3:0] s1_outputPayload_index_5; + wire [3:0] s1_outputPayload_index_6; + wire [3:0] s1_outputPayload_index_7; + wire [3:0] s1_outputPayload_index_8; + wire [3:0] s1_outputPayload_index_9; + wire [3:0] s1_outputPayload_index_10; + wire [3:0] s1_outputPayload_index_11; + wire [3:0] s1_outputPayload_index_12; + wire [3:0] s1_outputPayload_index_13; + wire [3:0] s1_outputPayload_index_14; + wire [3:0] s1_outputPayload_index_15; + wire s1_outputPayload_last; + wire [3:0] s1_outputPayload_sel_0; + wire [3:0] s1_outputPayload_sel_1; + wire [3:0] s1_outputPayload_sel_2; + wire [3:0] s1_outputPayload_sel_3; + wire [3:0] s1_outputPayload_sel_4; + wire [3:0] s1_outputPayload_sel_5; + wire [3:0] s1_outputPayload_sel_6; + wire [3:0] s1_outputPayload_sel_7; + wire [3:0] s1_outputPayload_sel_8; + wire [3:0] s1_outputPayload_sel_9; + wire [3:0] s1_outputPayload_sel_10; + wire [3:0] s1_outputPayload_sel_11; + wire [3:0] s1_outputPayload_sel_12; + wire [3:0] s1_outputPayload_sel_13; + wire [3:0] s1_outputPayload_sel_14; + wire [3:0] s1_outputPayload_sel_15; + reg [15:0] s1_outputPayload_selValid; + wire _zz_s1_outputPayload_selValid; + wire _zz_s1_outputPayload_selValid_1; + wire _zz_s1_outputPayload_selValid_2; + wire _zz_s1_outputPayload_selValid_3; + wire _zz_s1_outputPayload_selValid_4; + wire _zz_s1_outputPayload_selValid_5; + wire _zz_s1_outputPayload_selValid_6; + wire _zz_s1_outputPayload_selValid_7; + wire _zz_s1_outputPayload_selValid_8; + wire _zz_s1_outputPayload_selValid_9; + wire _zz_s1_outputPayload_selValid_10; + wire _zz_s1_outputPayload_selValid_11; + wire _zz_s1_outputPayload_selValid_12; + wire _zz_s1_outputPayload_selValid_13; + wire _zz_s1_outputPayload_selValid_14; + wire _zz_s1_outputPayload_sel_0; + wire _zz_s1_outputPayload_sel_0_1; + wire _zz_s1_outputPayload_sel_0_2; + wire _zz_s1_outputPayload_sel_0_3; + wire _zz_s1_outputPayload_selValid_15; + wire _zz_s1_outputPayload_selValid_16; + wire _zz_s1_outputPayload_selValid_17; + wire _zz_s1_outputPayload_selValid_18; + wire _zz_s1_outputPayload_selValid_19; + wire _zz_s1_outputPayload_selValid_20; + wire _zz_s1_outputPayload_selValid_21; + wire _zz_s1_outputPayload_selValid_22; + wire _zz_s1_outputPayload_selValid_23; + wire _zz_s1_outputPayload_selValid_24; + wire _zz_s1_outputPayload_selValid_25; + wire _zz_s1_outputPayload_selValid_26; + wire _zz_s1_outputPayload_selValid_27; + wire _zz_s1_outputPayload_selValid_28; + wire _zz_s1_outputPayload_selValid_29; + wire _zz_s1_outputPayload_sel_1; + wire _zz_s1_outputPayload_sel_1_1; + wire _zz_s1_outputPayload_sel_1_2; + wire _zz_s1_outputPayload_sel_1_3; + wire _zz_s1_outputPayload_selValid_30; + wire _zz_s1_outputPayload_selValid_31; + wire _zz_s1_outputPayload_selValid_32; + wire _zz_s1_outputPayload_selValid_33; + wire _zz_s1_outputPayload_selValid_34; + wire _zz_s1_outputPayload_selValid_35; + wire _zz_s1_outputPayload_selValid_36; + wire _zz_s1_outputPayload_selValid_37; + wire _zz_s1_outputPayload_selValid_38; + wire _zz_s1_outputPayload_selValid_39; + wire _zz_s1_outputPayload_selValid_40; + wire _zz_s1_outputPayload_selValid_41; + wire _zz_s1_outputPayload_selValid_42; + wire _zz_s1_outputPayload_selValid_43; + wire _zz_s1_outputPayload_selValid_44; + wire _zz_s1_outputPayload_sel_2; + wire _zz_s1_outputPayload_sel_2_1; + wire _zz_s1_outputPayload_sel_2_2; + wire _zz_s1_outputPayload_sel_2_3; + wire _zz_s1_outputPayload_selValid_45; + wire _zz_s1_outputPayload_selValid_46; + wire _zz_s1_outputPayload_selValid_47; + wire _zz_s1_outputPayload_selValid_48; + wire _zz_s1_outputPayload_selValid_49; + wire _zz_s1_outputPayload_selValid_50; + wire _zz_s1_outputPayload_selValid_51; + wire _zz_s1_outputPayload_selValid_52; + wire _zz_s1_outputPayload_selValid_53; + wire _zz_s1_outputPayload_selValid_54; + wire _zz_s1_outputPayload_selValid_55; + wire _zz_s1_outputPayload_selValid_56; + wire _zz_s1_outputPayload_selValid_57; + wire _zz_s1_outputPayload_selValid_58; + wire _zz_s1_outputPayload_selValid_59; + wire _zz_s1_outputPayload_sel_3; + wire _zz_s1_outputPayload_sel_3_1; + wire _zz_s1_outputPayload_sel_3_2; + wire _zz_s1_outputPayload_sel_3_3; + wire _zz_s1_outputPayload_selValid_60; + wire _zz_s1_outputPayload_selValid_61; + wire _zz_s1_outputPayload_selValid_62; + wire _zz_s1_outputPayload_selValid_63; + wire _zz_s1_outputPayload_selValid_64; + wire _zz_s1_outputPayload_selValid_65; + wire _zz_s1_outputPayload_selValid_66; + wire _zz_s1_outputPayload_selValid_67; + wire _zz_s1_outputPayload_selValid_68; + wire _zz_s1_outputPayload_selValid_69; + wire _zz_s1_outputPayload_selValid_70; + wire _zz_s1_outputPayload_selValid_71; + wire _zz_s1_outputPayload_selValid_72; + wire _zz_s1_outputPayload_selValid_73; + wire _zz_s1_outputPayload_selValid_74; + wire _zz_s1_outputPayload_sel_4; + wire _zz_s1_outputPayload_sel_4_1; + wire _zz_s1_outputPayload_sel_4_2; + wire _zz_s1_outputPayload_sel_4_3; + wire _zz_s1_outputPayload_selValid_75; + wire _zz_s1_outputPayload_selValid_76; + wire _zz_s1_outputPayload_selValid_77; + wire _zz_s1_outputPayload_selValid_78; + wire _zz_s1_outputPayload_selValid_79; + wire _zz_s1_outputPayload_selValid_80; + wire _zz_s1_outputPayload_selValid_81; + wire _zz_s1_outputPayload_selValid_82; + wire _zz_s1_outputPayload_selValid_83; + wire _zz_s1_outputPayload_selValid_84; + wire _zz_s1_outputPayload_selValid_85; + wire _zz_s1_outputPayload_selValid_86; + wire _zz_s1_outputPayload_selValid_87; + wire _zz_s1_outputPayload_selValid_88; + wire _zz_s1_outputPayload_selValid_89; + wire _zz_s1_outputPayload_sel_5; + wire _zz_s1_outputPayload_sel_5_1; + wire _zz_s1_outputPayload_sel_5_2; + wire _zz_s1_outputPayload_sel_5_3; + wire _zz_s1_outputPayload_selValid_90; + wire _zz_s1_outputPayload_selValid_91; + wire _zz_s1_outputPayload_selValid_92; + wire _zz_s1_outputPayload_selValid_93; + wire _zz_s1_outputPayload_selValid_94; + wire _zz_s1_outputPayload_selValid_95; + wire _zz_s1_outputPayload_selValid_96; + wire _zz_s1_outputPayload_selValid_97; + wire _zz_s1_outputPayload_selValid_98; + wire _zz_s1_outputPayload_selValid_99; + wire _zz_s1_outputPayload_selValid_100; + wire _zz_s1_outputPayload_selValid_101; + wire _zz_s1_outputPayload_selValid_102; + wire _zz_s1_outputPayload_selValid_103; + wire _zz_s1_outputPayload_selValid_104; + wire _zz_s1_outputPayload_sel_6; + wire _zz_s1_outputPayload_sel_6_1; + wire _zz_s1_outputPayload_sel_6_2; + wire _zz_s1_outputPayload_sel_6_3; + wire _zz_s1_outputPayload_selValid_105; + wire _zz_s1_outputPayload_selValid_106; + wire _zz_s1_outputPayload_selValid_107; + wire _zz_s1_outputPayload_selValid_108; + wire _zz_s1_outputPayload_selValid_109; + wire _zz_s1_outputPayload_selValid_110; + wire _zz_s1_outputPayload_selValid_111; + wire _zz_s1_outputPayload_selValid_112; + wire _zz_s1_outputPayload_selValid_113; + wire _zz_s1_outputPayload_selValid_114; + wire _zz_s1_outputPayload_selValid_115; + wire _zz_s1_outputPayload_selValid_116; + wire _zz_s1_outputPayload_selValid_117; + wire _zz_s1_outputPayload_selValid_118; + wire _zz_s1_outputPayload_selValid_119; + wire _zz_s1_outputPayload_sel_7; + wire _zz_s1_outputPayload_sel_7_1; + wire _zz_s1_outputPayload_sel_7_2; + wire _zz_s1_outputPayload_sel_7_3; + wire _zz_s1_outputPayload_selValid_120; + wire _zz_s1_outputPayload_selValid_121; + wire _zz_s1_outputPayload_selValid_122; + wire _zz_s1_outputPayload_selValid_123; + wire _zz_s1_outputPayload_selValid_124; + wire _zz_s1_outputPayload_selValid_125; + wire _zz_s1_outputPayload_selValid_126; + wire _zz_s1_outputPayload_selValid_127; + wire _zz_s1_outputPayload_selValid_128; + wire _zz_s1_outputPayload_selValid_129; + wire _zz_s1_outputPayload_selValid_130; + wire _zz_s1_outputPayload_selValid_131; + wire _zz_s1_outputPayload_selValid_132; + wire _zz_s1_outputPayload_selValid_133; + wire _zz_s1_outputPayload_selValid_134; + wire _zz_s1_outputPayload_sel_8; + wire _zz_s1_outputPayload_sel_8_1; + wire _zz_s1_outputPayload_sel_8_2; + wire _zz_s1_outputPayload_sel_8_3; + wire _zz_s1_outputPayload_selValid_135; + wire _zz_s1_outputPayload_selValid_136; + wire _zz_s1_outputPayload_selValid_137; + wire _zz_s1_outputPayload_selValid_138; + wire _zz_s1_outputPayload_selValid_139; + wire _zz_s1_outputPayload_selValid_140; + wire _zz_s1_outputPayload_selValid_141; + wire _zz_s1_outputPayload_selValid_142; + wire _zz_s1_outputPayload_selValid_143; + wire _zz_s1_outputPayload_selValid_144; + wire _zz_s1_outputPayload_selValid_145; + wire _zz_s1_outputPayload_selValid_146; + wire _zz_s1_outputPayload_selValid_147; + wire _zz_s1_outputPayload_selValid_148; + wire _zz_s1_outputPayload_selValid_149; + wire _zz_s1_outputPayload_sel_9; + wire _zz_s1_outputPayload_sel_9_1; + wire _zz_s1_outputPayload_sel_9_2; + wire _zz_s1_outputPayload_sel_9_3; + wire _zz_s1_outputPayload_selValid_150; + wire _zz_s1_outputPayload_selValid_151; + wire _zz_s1_outputPayload_selValid_152; + wire _zz_s1_outputPayload_selValid_153; + wire _zz_s1_outputPayload_selValid_154; + wire _zz_s1_outputPayload_selValid_155; + wire _zz_s1_outputPayload_selValid_156; + wire _zz_s1_outputPayload_selValid_157; + wire _zz_s1_outputPayload_selValid_158; + wire _zz_s1_outputPayload_selValid_159; + wire _zz_s1_outputPayload_selValid_160; + wire _zz_s1_outputPayload_selValid_161; + wire _zz_s1_outputPayload_selValid_162; + wire _zz_s1_outputPayload_selValid_163; + wire _zz_s1_outputPayload_selValid_164; + wire _zz_s1_outputPayload_sel_10; + wire _zz_s1_outputPayload_sel_10_1; + wire _zz_s1_outputPayload_sel_10_2; + wire _zz_s1_outputPayload_sel_10_3; + wire _zz_s1_outputPayload_selValid_165; + wire _zz_s1_outputPayload_selValid_166; + wire _zz_s1_outputPayload_selValid_167; + wire _zz_s1_outputPayload_selValid_168; + wire _zz_s1_outputPayload_selValid_169; + wire _zz_s1_outputPayload_selValid_170; + wire _zz_s1_outputPayload_selValid_171; + wire _zz_s1_outputPayload_selValid_172; + wire _zz_s1_outputPayload_selValid_173; + wire _zz_s1_outputPayload_selValid_174; + wire _zz_s1_outputPayload_selValid_175; + wire _zz_s1_outputPayload_selValid_176; + wire _zz_s1_outputPayload_selValid_177; + wire _zz_s1_outputPayload_selValid_178; + wire _zz_s1_outputPayload_selValid_179; + wire _zz_s1_outputPayload_sel_11; + wire _zz_s1_outputPayload_sel_11_1; + wire _zz_s1_outputPayload_sel_11_2; + wire _zz_s1_outputPayload_sel_11_3; + wire _zz_s1_outputPayload_selValid_180; + wire _zz_s1_outputPayload_selValid_181; + wire _zz_s1_outputPayload_selValid_182; + wire _zz_s1_outputPayload_selValid_183; + wire _zz_s1_outputPayload_selValid_184; + wire _zz_s1_outputPayload_selValid_185; + wire _zz_s1_outputPayload_selValid_186; + wire _zz_s1_outputPayload_selValid_187; + wire _zz_s1_outputPayload_selValid_188; + wire _zz_s1_outputPayload_selValid_189; + wire _zz_s1_outputPayload_selValid_190; + wire _zz_s1_outputPayload_selValid_191; + wire _zz_s1_outputPayload_selValid_192; + wire _zz_s1_outputPayload_selValid_193; + wire _zz_s1_outputPayload_selValid_194; + wire _zz_s1_outputPayload_sel_12; + wire _zz_s1_outputPayload_sel_12_1; + wire _zz_s1_outputPayload_sel_12_2; + wire _zz_s1_outputPayload_sel_12_3; + wire _zz_s1_outputPayload_selValid_195; + wire _zz_s1_outputPayload_selValid_196; + wire _zz_s1_outputPayload_selValid_197; + wire _zz_s1_outputPayload_selValid_198; + wire _zz_s1_outputPayload_selValid_199; + wire _zz_s1_outputPayload_selValid_200; + wire _zz_s1_outputPayload_selValid_201; + wire _zz_s1_outputPayload_selValid_202; + wire _zz_s1_outputPayload_selValid_203; + wire _zz_s1_outputPayload_selValid_204; + wire _zz_s1_outputPayload_selValid_205; + wire _zz_s1_outputPayload_selValid_206; + wire _zz_s1_outputPayload_selValid_207; + wire _zz_s1_outputPayload_selValid_208; + wire _zz_s1_outputPayload_selValid_209; + wire _zz_s1_outputPayload_sel_13; + wire _zz_s1_outputPayload_sel_13_1; + wire _zz_s1_outputPayload_sel_13_2; + wire _zz_s1_outputPayload_sel_13_3; + wire _zz_s1_outputPayload_selValid_210; + wire _zz_s1_outputPayload_selValid_211; + wire _zz_s1_outputPayload_selValid_212; + wire _zz_s1_outputPayload_selValid_213; + wire _zz_s1_outputPayload_selValid_214; + wire _zz_s1_outputPayload_selValid_215; + wire _zz_s1_outputPayload_selValid_216; + wire _zz_s1_outputPayload_selValid_217; + wire _zz_s1_outputPayload_selValid_218; + wire _zz_s1_outputPayload_selValid_219; + wire _zz_s1_outputPayload_selValid_220; + wire _zz_s1_outputPayload_selValid_221; + wire _zz_s1_outputPayload_selValid_222; + wire _zz_s1_outputPayload_selValid_223; + wire _zz_s1_outputPayload_selValid_224; + wire _zz_s1_outputPayload_sel_14; + wire _zz_s1_outputPayload_sel_14_1; + wire _zz_s1_outputPayload_sel_14_2; + wire _zz_s1_outputPayload_sel_14_3; + wire _zz_s1_outputPayload_selValid_225; + wire _zz_s1_outputPayload_selValid_226; + wire _zz_s1_outputPayload_selValid_227; + wire _zz_s1_outputPayload_selValid_228; + wire _zz_s1_outputPayload_selValid_229; + wire _zz_s1_outputPayload_selValid_230; + wire _zz_s1_outputPayload_selValid_231; + wire _zz_s1_outputPayload_selValid_232; + wire _zz_s1_outputPayload_selValid_233; + wire _zz_s1_outputPayload_selValid_234; + wire _zz_s1_outputPayload_selValid_235; + wire _zz_s1_outputPayload_selValid_236; + wire _zz_s1_outputPayload_selValid_237; + wire _zz_s1_outputPayload_selValid_238; + wire _zz_s1_outputPayload_selValid_239; + wire _zz_s1_outputPayload_sel_15; + wire _zz_s1_outputPayload_sel_15_1; + wire _zz_s1_outputPayload_sel_15_2; + wire _zz_s1_outputPayload_sel_15_3; + wire s1_output_valid; + reg s1_output_ready; + wire [127:0] s1_output_payload_cmd_data; + wire [15:0] s1_output_payload_cmd_mask; + wire [3:0] s1_output_payload_index_0; + wire [3:0] s1_output_payload_index_1; + wire [3:0] s1_output_payload_index_2; + wire [3:0] s1_output_payload_index_3; + wire [3:0] s1_output_payload_index_4; + wire [3:0] s1_output_payload_index_5; + wire [3:0] s1_output_payload_index_6; + wire [3:0] s1_output_payload_index_7; + wire [3:0] s1_output_payload_index_8; + wire [3:0] s1_output_payload_index_9; + wire [3:0] s1_output_payload_index_10; + wire [3:0] s1_output_payload_index_11; + wire [3:0] s1_output_payload_index_12; + wire [3:0] s1_output_payload_index_13; + wire [3:0] s1_output_payload_index_14; + wire [3:0] s1_output_payload_index_15; + wire s1_output_payload_last; + wire [3:0] s1_output_payload_sel_0; + wire [3:0] s1_output_payload_sel_1; + wire [3:0] s1_output_payload_sel_2; + wire [3:0] s1_output_payload_sel_3; + wire [3:0] s1_output_payload_sel_4; + wire [3:0] s1_output_payload_sel_5; + wire [3:0] s1_output_payload_sel_6; + wire [3:0] s1_output_payload_sel_7; + wire [3:0] s1_output_payload_sel_8; + wire [3:0] s1_output_payload_sel_9; + wire [3:0] s1_output_payload_sel_10; + wire [3:0] s1_output_payload_sel_11; + wire [3:0] s1_output_payload_sel_12; + wire [3:0] s1_output_payload_sel_13; + wire [3:0] s1_output_payload_sel_14; + wire [3:0] s1_output_payload_sel_15; + wire [15:0] s1_output_payload_selValid; + wire s2_input_valid; + reg s2_input_ready; + wire [127:0] s2_input_payload_cmd_data; + wire [15:0] s2_input_payload_cmd_mask; + wire [3:0] s2_input_payload_index_0; + wire [3:0] s2_input_payload_index_1; + wire [3:0] s2_input_payload_index_2; + wire [3:0] s2_input_payload_index_3; + wire [3:0] s2_input_payload_index_4; + wire [3:0] s2_input_payload_index_5; + wire [3:0] s2_input_payload_index_6; + wire [3:0] s2_input_payload_index_7; + wire [3:0] s2_input_payload_index_8; + wire [3:0] s2_input_payload_index_9; + wire [3:0] s2_input_payload_index_10; + wire [3:0] s2_input_payload_index_11; + wire [3:0] s2_input_payload_index_12; + wire [3:0] s2_input_payload_index_13; + wire [3:0] s2_input_payload_index_14; + wire [3:0] s2_input_payload_index_15; + wire s2_input_payload_last; + wire [3:0] s2_input_payload_sel_0; + wire [3:0] s2_input_payload_sel_1; + wire [3:0] s2_input_payload_sel_2; + wire [3:0] s2_input_payload_sel_3; + wire [3:0] s2_input_payload_sel_4; + wire [3:0] s2_input_payload_sel_5; + wire [3:0] s2_input_payload_sel_6; + wire [3:0] s2_input_payload_sel_7; + wire [3:0] s2_input_payload_sel_8; + wire [3:0] s2_input_payload_sel_9; + wire [3:0] s2_input_payload_sel_10; + wire [3:0] s2_input_payload_sel_11; + wire [3:0] s2_input_payload_sel_12; + wire [3:0] s2_input_payload_sel_13; + wire [3:0] s2_input_payload_sel_14; + wire [3:0] s2_input_payload_sel_15; + wire [15:0] s2_input_payload_selValid; + reg s1_output_rValid; + reg [127:0] s1_output_rData_cmd_data; + reg [15:0] s1_output_rData_cmd_mask; + reg [3:0] s1_output_rData_index_0; + reg [3:0] s1_output_rData_index_1; + reg [3:0] s1_output_rData_index_2; + reg [3:0] s1_output_rData_index_3; + reg [3:0] s1_output_rData_index_4; + reg [3:0] s1_output_rData_index_5; + reg [3:0] s1_output_rData_index_6; + reg [3:0] s1_output_rData_index_7; + reg [3:0] s1_output_rData_index_8; + reg [3:0] s1_output_rData_index_9; + reg [3:0] s1_output_rData_index_10; + reg [3:0] s1_output_rData_index_11; + reg [3:0] s1_output_rData_index_12; + reg [3:0] s1_output_rData_index_13; + reg [3:0] s1_output_rData_index_14; + reg [3:0] s1_output_rData_index_15; + reg s1_output_rData_last; + reg [3:0] s1_output_rData_sel_0; + reg [3:0] s1_output_rData_sel_1; + reg [3:0] s1_output_rData_sel_2; + reg [3:0] s1_output_rData_sel_3; + reg [3:0] s1_output_rData_sel_4; + reg [3:0] s1_output_rData_sel_5; + reg [3:0] s1_output_rData_sel_6; + reg [3:0] s1_output_rData_sel_7; + reg [3:0] s1_output_rData_sel_8; + reg [3:0] s1_output_rData_sel_9; + reg [3:0] s1_output_rData_sel_10; + reg [3:0] s1_output_rData_sel_11; + reg [3:0] s1_output_rData_sel_12; + reg [3:0] s1_output_rData_sel_13; + reg [3:0] s1_output_rData_sel_14; + reg [3:0] s1_output_rData_sel_15; + reg [15:0] s1_output_rData_selValid; + wire when_Stream_l375_2; + wire when_DmaSg_l1464; + wire s2_input_fire; + wire [7:0] s2_inputDataBytes_0; + wire [7:0] s2_inputDataBytes_1; + wire [7:0] s2_inputDataBytes_2; + wire [7:0] s2_inputDataBytes_3; + wire [7:0] s2_inputDataBytes_4; + wire [7:0] s2_inputDataBytes_5; + wire [7:0] s2_inputDataBytes_6; + wire [7:0] s2_inputDataBytes_7; + wire [7:0] s2_inputDataBytes_8; + wire [7:0] s2_inputDataBytes_9; + wire [7:0] s2_inputDataBytes_10; + wire [7:0] s2_inputDataBytes_11; + wire [7:0] s2_inputDataBytes_12; + wire [7:0] s2_inputDataBytes_13; + wire [7:0] s2_inputDataBytes_14; + wire [7:0] s2_inputDataBytes_15; + reg s2_byteLogic_0_buffer_valid; + reg [7:0] s2_byteLogic_0_buffer_data; + wire s2_byteLogic_0_lastUsed; + wire s2_byteLogic_0_inputMask; + wire [7:0] s2_byteLogic_0_inputData; + wire s2_byteLogic_0_outputMask; + wire [7:0] s2_byteLogic_0_outputData; + wire when_DmaSg_l1493; + reg s2_byteLogic_1_buffer_valid; + reg [7:0] s2_byteLogic_1_buffer_data; + wire s2_byteLogic_1_lastUsed; + wire s2_byteLogic_1_inputMask; + wire [7:0] s2_byteLogic_1_inputData; + wire s2_byteLogic_1_outputMask; + wire [7:0] s2_byteLogic_1_outputData; + wire when_DmaSg_l1493_1; + reg s2_byteLogic_2_buffer_valid; + reg [7:0] s2_byteLogic_2_buffer_data; + wire s2_byteLogic_2_lastUsed; + wire s2_byteLogic_2_inputMask; + wire [7:0] s2_byteLogic_2_inputData; + wire s2_byteLogic_2_outputMask; + wire [7:0] s2_byteLogic_2_outputData; + wire when_DmaSg_l1493_2; + reg s2_byteLogic_3_buffer_valid; + reg [7:0] s2_byteLogic_3_buffer_data; + wire s2_byteLogic_3_lastUsed; + wire s2_byteLogic_3_inputMask; + wire [7:0] s2_byteLogic_3_inputData; + wire s2_byteLogic_3_outputMask; + wire [7:0] s2_byteLogic_3_outputData; + wire when_DmaSg_l1493_3; + reg s2_byteLogic_4_buffer_valid; + reg [7:0] s2_byteLogic_4_buffer_data; + wire s2_byteLogic_4_lastUsed; + wire s2_byteLogic_4_inputMask; + wire [7:0] s2_byteLogic_4_inputData; + wire s2_byteLogic_4_outputMask; + wire [7:0] s2_byteLogic_4_outputData; + wire when_DmaSg_l1493_4; + reg s2_byteLogic_5_buffer_valid; + reg [7:0] s2_byteLogic_5_buffer_data; + wire s2_byteLogic_5_lastUsed; + wire s2_byteLogic_5_inputMask; + wire [7:0] s2_byteLogic_5_inputData; + wire s2_byteLogic_5_outputMask; + wire [7:0] s2_byteLogic_5_outputData; + wire when_DmaSg_l1493_5; + reg s2_byteLogic_6_buffer_valid; + reg [7:0] s2_byteLogic_6_buffer_data; + wire s2_byteLogic_6_lastUsed; + wire s2_byteLogic_6_inputMask; + wire [7:0] s2_byteLogic_6_inputData; + wire s2_byteLogic_6_outputMask; + wire [7:0] s2_byteLogic_6_outputData; + wire when_DmaSg_l1493_6; + reg s2_byteLogic_7_buffer_valid; + reg [7:0] s2_byteLogic_7_buffer_data; + wire s2_byteLogic_7_lastUsed; + wire s2_byteLogic_7_inputMask; + wire [7:0] s2_byteLogic_7_inputData; + wire s2_byteLogic_7_outputMask; + wire [7:0] s2_byteLogic_7_outputData; + wire when_DmaSg_l1493_7; + reg s2_byteLogic_8_buffer_valid; + reg [7:0] s2_byteLogic_8_buffer_data; + wire s2_byteLogic_8_lastUsed; + wire s2_byteLogic_8_inputMask; + wire [7:0] s2_byteLogic_8_inputData; + wire s2_byteLogic_8_outputMask; + wire [7:0] s2_byteLogic_8_outputData; + wire when_DmaSg_l1493_8; + reg s2_byteLogic_9_buffer_valid; + reg [7:0] s2_byteLogic_9_buffer_data; + wire s2_byteLogic_9_lastUsed; + wire s2_byteLogic_9_inputMask; + wire [7:0] s2_byteLogic_9_inputData; + wire s2_byteLogic_9_outputMask; + wire [7:0] s2_byteLogic_9_outputData; + wire when_DmaSg_l1493_9; + reg s2_byteLogic_10_buffer_valid; + reg [7:0] s2_byteLogic_10_buffer_data; + wire s2_byteLogic_10_lastUsed; + wire s2_byteLogic_10_inputMask; + wire [7:0] s2_byteLogic_10_inputData; + wire s2_byteLogic_10_outputMask; + wire [7:0] s2_byteLogic_10_outputData; + wire when_DmaSg_l1493_10; + reg s2_byteLogic_11_buffer_valid; + reg [7:0] s2_byteLogic_11_buffer_data; + wire s2_byteLogic_11_lastUsed; + wire s2_byteLogic_11_inputMask; + wire [7:0] s2_byteLogic_11_inputData; + wire s2_byteLogic_11_outputMask; + wire [7:0] s2_byteLogic_11_outputData; + wire when_DmaSg_l1493_11; + reg s2_byteLogic_12_buffer_valid; + reg [7:0] s2_byteLogic_12_buffer_data; + wire s2_byteLogic_12_lastUsed; + wire s2_byteLogic_12_inputMask; + wire [7:0] s2_byteLogic_12_inputData; + wire s2_byteLogic_12_outputMask; + wire [7:0] s2_byteLogic_12_outputData; + wire when_DmaSg_l1493_12; + reg s2_byteLogic_13_buffer_valid; + reg [7:0] s2_byteLogic_13_buffer_data; + wire s2_byteLogic_13_lastUsed; + wire s2_byteLogic_13_inputMask; + wire [7:0] s2_byteLogic_13_inputData; + wire s2_byteLogic_13_outputMask; + wire [7:0] s2_byteLogic_13_outputData; + wire when_DmaSg_l1493_13; + reg s2_byteLogic_14_buffer_valid; + reg [7:0] s2_byteLogic_14_buffer_data; + wire s2_byteLogic_14_lastUsed; + wire s2_byteLogic_14_inputMask; + wire [7:0] s2_byteLogic_14_inputData; + wire s2_byteLogic_14_outputMask; + wire [7:0] s2_byteLogic_14_outputData; + wire when_DmaSg_l1493_14; + reg s2_byteLogic_15_buffer_valid; + reg [7:0] s2_byteLogic_15_buffer_data; + wire s2_byteLogic_15_lastUsed; + wire s2_byteLogic_15_inputMask; + wire [7:0] s2_byteLogic_15_inputData; + wire s2_byteLogic_15_outputMask; + wire [7:0] s2_byteLogic_15_outputData; + wire when_DmaSg_l1493_15; + wire _zz_io_output_usedUntil; + wire _zz_io_output_usedUntil_1; + wire _zz_io_output_usedUntil_2; + wire _zz_io_output_usedUntil_3; + + assign _zz_s0_countOnesLogic_3_13 = _zz_s0_countOnesLogic_3; + assign _zz_s0_countOnesLogic_3_12 = {2'd0, _zz_s0_countOnesLogic_3_13}; + assign _zz_s0_countOnesLogic_4_13 = {_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}; + assign _zz_s0_countOnesLogic_4_12 = {1'd0, _zz_s0_countOnesLogic_4_13}; + assign _zz_s0_countOnesLogic_6_9 = (_zz_s0_countOnesLogic_6_10 + _zz_s0_countOnesLogic_6_12); + assign _zz_s0_countOnesLogic_6_16 = _zz_s0_countOnesLogic_6; + assign _zz_s0_countOnesLogic_6_15 = {2'd0, _zz_s0_countOnesLogic_6_16}; + assign _zz_s0_countOnesLogic_7_9 = (_zz_s0_countOnesLogic_7_10 + _zz_s0_countOnesLogic_7_12); + assign _zz_s0_countOnesLogic_7_16 = {_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}; + assign _zz_s0_countOnesLogic_7_15 = {1'd0, _zz_s0_countOnesLogic_7_16}; + assign _zz_s0_countOnesLogic_8_9 = (_zz_s0_countOnesLogic_8_10 + _zz_s0_countOnesLogic_8_12); + assign _zz_s0_countOnesLogic_9_9 = (_zz_s0_countOnesLogic_9_10 + _zz_s0_countOnesLogic_9_12); + assign _zz_s0_countOnesLogic_9_14 = (_zz_s0_countOnesLogic_9_15 + _zz_s0_countOnesLogic_9_17); + assign _zz_s0_countOnesLogic_9_19 = _zz_s0_countOnesLogic_9; + assign _zz_s0_countOnesLogic_9_18 = {2'd0, _zz_s0_countOnesLogic_9_19}; + assign _zz_s0_countOnesLogic_10_9 = (_zz_s0_countOnesLogic_10_10 + _zz_s0_countOnesLogic_10_12); + assign _zz_s0_countOnesLogic_10_14 = (_zz_s0_countOnesLogic_10_15 + _zz_s0_countOnesLogic_10_17); + assign _zz_s0_countOnesLogic_10_19 = {_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}; + assign _zz_s0_countOnesLogic_10_18 = {1'd0, _zz_s0_countOnesLogic_10_19}; + assign _zz_s0_countOnesLogic_11_9 = (_zz_s0_countOnesLogic_11_10 + _zz_s0_countOnesLogic_11_12); + assign _zz_s0_countOnesLogic_11_14 = (_zz_s0_countOnesLogic_11_15 + _zz_s0_countOnesLogic_11_17); + assign _zz_s0_countOnesLogic_12_9 = (_zz_s0_countOnesLogic_12_10 + _zz_s0_countOnesLogic_12_15); + assign _zz_s0_countOnesLogic_12_10 = (_zz_s0_countOnesLogic_12_11 + _zz_s0_countOnesLogic_12_13); + assign _zz_s0_countOnesLogic_12_15 = (_zz_s0_countOnesLogic_12_16 + _zz_s0_countOnesLogic_12_18); + assign _zz_s0_countOnesLogic_12_22 = _zz_s0_countOnesLogic_12; + assign _zz_s0_countOnesLogic_12_21 = {2'd0, _zz_s0_countOnesLogic_12_22}; + assign _zz_s0_countOnesLogic_13_9 = (_zz_s0_countOnesLogic_13_10 + _zz_s0_countOnesLogic_13_15); + assign _zz_s0_countOnesLogic_13_10 = (_zz_s0_countOnesLogic_13_11 + _zz_s0_countOnesLogic_13_13); + assign _zz_s0_countOnesLogic_13_15 = (_zz_s0_countOnesLogic_13_16 + _zz_s0_countOnesLogic_13_18); + assign _zz_s0_countOnesLogic_13_22 = {_zz_s0_countOnesLogic_13,_zz_s0_countOnesLogic_12}; + assign _zz_s0_countOnesLogic_13_21 = {1'd0, _zz_s0_countOnesLogic_13_22}; + assign _zz_s0_countOnesLogic_14_9 = (_zz_s0_countOnesLogic_14_10 + _zz_s0_countOnesLogic_14_15); + assign _zz_s0_countOnesLogic_14_10 = (_zz_s0_countOnesLogic_14_11 + _zz_s0_countOnesLogic_14_13); + assign _zz_s0_countOnesLogic_14_15 = (_zz_s0_countOnesLogic_14_16 + _zz_s0_countOnesLogic_14_18); + assign _zz_s0_countOnesLogic_15_8 = (_zz_s0_countOnesLogic_15_9 + _zz_s0_countOnesLogic_15_14); + assign _zz_s0_countOnesLogic_15_9 = (_zz_s0_countOnesLogic_15_10 + _zz_s0_countOnesLogic_15_12); + assign _zz_s0_countOnesLogic_15_14 = (_zz_s0_countOnesLogic_15_15 + _zz_s0_countOnesLogic_15_17); + assign _zz_s0_countOnesLogic_15_19 = (_zz_s0_countOnesLogic_15_20 + _zz_s0_countOnesLogic_15_22); + assign _zz_s0_countOnesLogic_15_24 = s0_input_payload_mask[15]; + assign _zz_s0_countOnesLogic_15_23 = {2'd0, _zz_s0_countOnesLogic_15_24}; + assign _zz_s1_offsetNext = {1'd0, s1_offset}; + assign _zz_s1_byteCounter = {8'd0, s1_input_payload_countOnes_15}; + assign _zz_s1_inputIndexes_1 = {3'd0, s1_input_payload_countOnes_0}; + assign _zz_s1_inputIndexes_2 = {2'd0, s1_input_payload_countOnes_1}; + assign _zz_s1_inputIndexes_3 = {2'd0, s1_input_payload_countOnes_2}; + assign _zz_s1_inputIndexes_4 = {1'd0, s1_input_payload_countOnes_3}; + assign _zz_s1_inputIndexes_5 = {1'd0, s1_input_payload_countOnes_4}; + assign _zz_s1_inputIndexes_6 = {1'd0, s1_input_payload_countOnes_5}; + assign _zz_s1_inputIndexes_7 = {1'd0, s1_input_payload_countOnes_6}; + assign _zz_when_DmaSg_l1464 = {1'd0, io_burstLength}; + assign _zz_s0_countOnesLogic_0_2 = _zz_s0_countOnesLogic_0; + assign _zz_s0_countOnesLogic_1_2 = {_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}; + assign _zz_s0_countOnesLogic_2_2 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_3_10 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_4_10 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_5_10 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_5_12 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_6_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_6_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_7_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_7_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_8_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_8_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_8_15 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_9_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_9_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_9_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_10_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_10_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_10_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_11_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_11_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_11_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_11_18 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; + assign _zz_s0_countOnesLogic_12_12 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_12_14 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_12_17 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_12_19 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; + assign _zz_s0_countOnesLogic_13_12 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_13_14 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_13_17 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_13_19 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; + assign _zz_s0_countOnesLogic_14_12 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_14_14 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_14_17 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_14_19 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; + assign _zz_s0_countOnesLogic_14_21 = {_zz_s0_countOnesLogic_14,{_zz_s0_countOnesLogic_13,_zz_s0_countOnesLogic_12}}; + assign _zz_s0_countOnesLogic_15_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_15_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_15_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_15_18 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; + assign _zz_s0_countOnesLogic_15_21 = {_zz_s0_countOnesLogic_14,{_zz_s0_countOnesLogic_13,_zz_s0_countOnesLogic_12}}; + assign _zz_io_output_usedUntil_5 = {_zz_io_output_usedUntil_3,{_zz_io_output_usedUntil_2,{_zz_io_output_usedUntil_1,_zz_io_output_usedUntil}}}; + assign _zz_s1_outputPayload_selValid_240 = _zz_s1_outputPayload_selValid_6; + assign _zz_s1_outputPayload_selValid_241 = {_zz_s1_outputPayload_selValid_5,{_zz_s1_outputPayload_selValid_4,{_zz_s1_outputPayload_selValid_3,{_zz_s1_outputPayload_selValid_2,{_zz_s1_outputPayload_selValid_1,{_zz_s1_outputPayload_selValid,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0000))}}}}}}; + assign _zz_s1_outputPayload_selValid_242 = _zz_s1_outputPayload_selValid_21; + assign _zz_s1_outputPayload_selValid_243 = {_zz_s1_outputPayload_selValid_20,{_zz_s1_outputPayload_selValid_19,{_zz_s1_outputPayload_selValid_18,{_zz_s1_outputPayload_selValid_17,{_zz_s1_outputPayload_selValid_16,{_zz_s1_outputPayload_selValid_15,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0001))}}}}}}; + assign _zz_s1_outputPayload_selValid_244 = _zz_s1_outputPayload_selValid_36; + assign _zz_s1_outputPayload_selValid_245 = {_zz_s1_outputPayload_selValid_35,{_zz_s1_outputPayload_selValid_34,{_zz_s1_outputPayload_selValid_33,{_zz_s1_outputPayload_selValid_32,{_zz_s1_outputPayload_selValid_31,{_zz_s1_outputPayload_selValid_30,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0010))}}}}}}; + assign _zz_s1_outputPayload_selValid_246 = _zz_s1_outputPayload_selValid_51; + assign _zz_s1_outputPayload_selValid_247 = {_zz_s1_outputPayload_selValid_50,{_zz_s1_outputPayload_selValid_49,{_zz_s1_outputPayload_selValid_48,{_zz_s1_outputPayload_selValid_47,{_zz_s1_outputPayload_selValid_46,{_zz_s1_outputPayload_selValid_45,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0011))}}}}}}; + assign _zz_s1_outputPayload_selValid_248 = _zz_s1_outputPayload_selValid_66; + assign _zz_s1_outputPayload_selValid_249 = {_zz_s1_outputPayload_selValid_65,{_zz_s1_outputPayload_selValid_64,{_zz_s1_outputPayload_selValid_63,{_zz_s1_outputPayload_selValid_62,{_zz_s1_outputPayload_selValid_61,{_zz_s1_outputPayload_selValid_60,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0100))}}}}}}; + assign _zz_s1_outputPayload_selValid_250 = _zz_s1_outputPayload_selValid_81; + assign _zz_s1_outputPayload_selValid_251 = {_zz_s1_outputPayload_selValid_80,{_zz_s1_outputPayload_selValid_79,{_zz_s1_outputPayload_selValid_78,{_zz_s1_outputPayload_selValid_77,{_zz_s1_outputPayload_selValid_76,{_zz_s1_outputPayload_selValid_75,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0101))}}}}}}; + assign _zz_s1_outputPayload_selValid_252 = _zz_s1_outputPayload_selValid_96; + assign _zz_s1_outputPayload_selValid_253 = {_zz_s1_outputPayload_selValid_95,{_zz_s1_outputPayload_selValid_94,{_zz_s1_outputPayload_selValid_93,{_zz_s1_outputPayload_selValid_92,{_zz_s1_outputPayload_selValid_91,{_zz_s1_outputPayload_selValid_90,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0110))}}}}}}; + assign _zz_s1_outputPayload_selValid_254 = _zz_s1_outputPayload_selValid_111; + assign _zz_s1_outputPayload_selValid_255 = {_zz_s1_outputPayload_selValid_110,{_zz_s1_outputPayload_selValid_109,{_zz_s1_outputPayload_selValid_108,{_zz_s1_outputPayload_selValid_107,{_zz_s1_outputPayload_selValid_106,{_zz_s1_outputPayload_selValid_105,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0111))}}}}}}; + assign _zz_s1_outputPayload_selValid_256 = _zz_s1_outputPayload_selValid_126; + assign _zz_s1_outputPayload_selValid_257 = {_zz_s1_outputPayload_selValid_125,{_zz_s1_outputPayload_selValid_124,{_zz_s1_outputPayload_selValid_123,{_zz_s1_outputPayload_selValid_122,{_zz_s1_outputPayload_selValid_121,{_zz_s1_outputPayload_selValid_120,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1000))}}}}}}; + assign _zz_s1_outputPayload_selValid_258 = _zz_s1_outputPayload_selValid_141; + assign _zz_s1_outputPayload_selValid_259 = {_zz_s1_outputPayload_selValid_140,{_zz_s1_outputPayload_selValid_139,{_zz_s1_outputPayload_selValid_138,{_zz_s1_outputPayload_selValid_137,{_zz_s1_outputPayload_selValid_136,{_zz_s1_outputPayload_selValid_135,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1001))}}}}}}; + assign _zz_s1_outputPayload_selValid_260 = _zz_s1_outputPayload_selValid_156; + assign _zz_s1_outputPayload_selValid_261 = {_zz_s1_outputPayload_selValid_155,{_zz_s1_outputPayload_selValid_154,{_zz_s1_outputPayload_selValid_153,{_zz_s1_outputPayload_selValid_152,{_zz_s1_outputPayload_selValid_151,{_zz_s1_outputPayload_selValid_150,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1010))}}}}}}; + assign _zz_s1_outputPayload_selValid_262 = _zz_s1_outputPayload_selValid_171; + assign _zz_s1_outputPayload_selValid_263 = {_zz_s1_outputPayload_selValid_170,{_zz_s1_outputPayload_selValid_169,{_zz_s1_outputPayload_selValid_168,{_zz_s1_outputPayload_selValid_167,{_zz_s1_outputPayload_selValid_166,{_zz_s1_outputPayload_selValid_165,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1011))}}}}}}; + assign _zz_s1_outputPayload_selValid_264 = _zz_s1_outputPayload_selValid_186; + assign _zz_s1_outputPayload_selValid_265 = {_zz_s1_outputPayload_selValid_185,{_zz_s1_outputPayload_selValid_184,{_zz_s1_outputPayload_selValid_183,{_zz_s1_outputPayload_selValid_182,{_zz_s1_outputPayload_selValid_181,{_zz_s1_outputPayload_selValid_180,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1100))}}}}}}; + assign _zz_s1_outputPayload_selValid_266 = _zz_s1_outputPayload_selValid_201; + assign _zz_s1_outputPayload_selValid_267 = {_zz_s1_outputPayload_selValid_200,{_zz_s1_outputPayload_selValid_199,{_zz_s1_outputPayload_selValid_198,{_zz_s1_outputPayload_selValid_197,{_zz_s1_outputPayload_selValid_196,{_zz_s1_outputPayload_selValid_195,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1101))}}}}}}; + assign _zz_s1_outputPayload_selValid_268 = _zz_s1_outputPayload_selValid_216; + assign _zz_s1_outputPayload_selValid_269 = {_zz_s1_outputPayload_selValid_215,{_zz_s1_outputPayload_selValid_214,{_zz_s1_outputPayload_selValid_213,{_zz_s1_outputPayload_selValid_212,{_zz_s1_outputPayload_selValid_211,{_zz_s1_outputPayload_selValid_210,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1110))}}}}}}; + assign _zz_s1_outputPayload_selValid_270 = _zz_s1_outputPayload_selValid_231; + assign _zz_s1_outputPayload_selValid_271 = {_zz_s1_outputPayload_selValid_230,{_zz_s1_outputPayload_selValid_229,{_zz_s1_outputPayload_selValid_228,{_zz_s1_outputPayload_selValid_227,{_zz_s1_outputPayload_selValid_226,{_zz_s1_outputPayload_selValid_225,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1111))}}}}}}; + always @(*) begin + case(_zz_s0_countOnesLogic_0_2) + 1'b0 : _zz_s0_countOnesLogic_0_1 = 1'b0; + default : _zz_s0_countOnesLogic_0_1 = 1'b1; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_1_2) + 2'b00 : _zz_s0_countOnesLogic_1_1 = 2'b00; + 2'b01 : _zz_s0_countOnesLogic_1_1 = 2'b01; + 2'b10 : _zz_s0_countOnesLogic_1_1 = 2'b01; + default : _zz_s0_countOnesLogic_1_1 = 2'b10; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_2_2) + 3'b000 : _zz_s0_countOnesLogic_2_1 = 2'b00; + 3'b001 : _zz_s0_countOnesLogic_2_1 = 2'b01; + 3'b010 : _zz_s0_countOnesLogic_2_1 = 2'b01; + 3'b011 : _zz_s0_countOnesLogic_2_1 = 2'b10; + 3'b100 : _zz_s0_countOnesLogic_2_1 = 2'b01; + 3'b101 : _zz_s0_countOnesLogic_2_1 = 2'b10; + 3'b110 : _zz_s0_countOnesLogic_2_1 = 2'b10; + default : _zz_s0_countOnesLogic_2_1 = 2'b11; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_3_10) + 3'b000 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_1; + 3'b001 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_2; + 3'b010 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_3; + 3'b011 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_4; + 3'b100 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_5; + 3'b101 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_6; + 3'b110 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_7; + default : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_3_12) + 3'b000 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_1; + 3'b001 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_2; + 3'b010 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_3; + 3'b011 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_4; + 3'b100 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_5; + 3'b101 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_6; + 3'b110 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_7; + default : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_4_10) + 3'b000 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_1; + 3'b001 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_2; + 3'b010 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_3; + 3'b011 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_4; + 3'b100 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_5; + 3'b101 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_6; + 3'b110 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_7; + default : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_4_12) + 3'b000 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_1; + 3'b001 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_2; + 3'b010 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_3; + 3'b011 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_4; + 3'b100 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_5; + 3'b101 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_6; + 3'b110 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_7; + default : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_5_10) + 3'b000 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_1; + 3'b001 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_2; + 3'b010 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_3; + 3'b011 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_4; + 3'b100 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_5; + 3'b101 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_6; + 3'b110 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_7; + default : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_5_12) + 3'b000 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_1; + 3'b001 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_2; + 3'b010 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_3; + 3'b011 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_4; + 3'b100 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_5; + 3'b101 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_6; + 3'b110 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_7; + default : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_6_11) + 3'b000 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_1; + 3'b001 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_2; + 3'b010 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_3; + 3'b011 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_4; + 3'b100 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_5; + 3'b101 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_6; + 3'b110 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_7; + default : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_6_13) + 3'b000 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_1; + 3'b001 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_2; + 3'b010 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_3; + 3'b011 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_4; + 3'b100 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_5; + 3'b101 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_6; + 3'b110 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_7; + default : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_6_15) + 3'b000 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_1; + 3'b001 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_2; + 3'b010 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_3; + 3'b011 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_4; + 3'b100 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_5; + 3'b101 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_6; + 3'b110 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_7; + default : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_7_11) + 3'b000 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_1; + 3'b001 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_2; + 3'b010 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_3; + 3'b011 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_4; + 3'b100 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_5; + 3'b101 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_6; + 3'b110 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_7; + default : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_7_13) + 3'b000 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_1; + 3'b001 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_2; + 3'b010 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_3; + 3'b011 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_4; + 3'b100 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_5; + 3'b101 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_6; + 3'b110 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_7; + default : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_7_15) + 3'b000 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_1; + 3'b001 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_2; + 3'b010 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_3; + 3'b011 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_4; + 3'b100 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_5; + 3'b101 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_6; + 3'b110 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_7; + default : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_8_11) + 3'b000 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_1; + 3'b001 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_2; + 3'b010 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_3; + 3'b011 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_4; + 3'b100 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_5; + 3'b101 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_6; + 3'b110 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_7; + default : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_8_13) + 3'b000 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_1; + 3'b001 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_2; + 3'b010 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_3; + 3'b011 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_4; + 3'b100 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_5; + 3'b101 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_6; + 3'b110 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_7; + default : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_8_15) + 3'b000 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_1; + 3'b001 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_2; + 3'b010 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_3; + 3'b011 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_4; + 3'b100 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_5; + 3'b101 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_6; + 3'b110 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_7; + default : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_9_11) + 3'b000 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_1; + 3'b001 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_2; + 3'b010 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_3; + 3'b011 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_4; + 3'b100 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_5; + 3'b101 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_6; + 3'b110 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_7; + default : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_9_13) + 3'b000 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_1; + 3'b001 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_2; + 3'b010 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_3; + 3'b011 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_4; + 3'b100 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_5; + 3'b101 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_6; + 3'b110 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_7; + default : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_9_16) + 3'b000 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_1; + 3'b001 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_2; + 3'b010 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_3; + 3'b011 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_4; + 3'b100 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_5; + 3'b101 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_6; + 3'b110 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_7; + default : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_9_18) + 3'b000 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_1; + 3'b001 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_2; + 3'b010 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_3; + 3'b011 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_4; + 3'b100 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_5; + 3'b101 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_6; + 3'b110 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_7; + default : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_10_11) + 3'b000 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_1; + 3'b001 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_2; + 3'b010 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_3; + 3'b011 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_4; + 3'b100 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_5; + 3'b101 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_6; + 3'b110 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_7; + default : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_10_13) + 3'b000 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_1; + 3'b001 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_2; + 3'b010 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_3; + 3'b011 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_4; + 3'b100 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_5; + 3'b101 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_6; + 3'b110 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_7; + default : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_10_16) + 3'b000 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_1; + 3'b001 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_2; + 3'b010 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_3; + 3'b011 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_4; + 3'b100 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_5; + 3'b101 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_6; + 3'b110 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_7; + default : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_10_18) + 3'b000 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_1; + 3'b001 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_2; + 3'b010 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_3; + 3'b011 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_4; + 3'b100 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_5; + 3'b101 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_6; + 3'b110 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_7; + default : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_11_11) + 3'b000 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_1; + 3'b001 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_2; + 3'b010 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_3; + 3'b011 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_4; + 3'b100 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_5; + 3'b101 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_6; + 3'b110 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_7; + default : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_11_13) + 3'b000 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_1; + 3'b001 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_2; + 3'b010 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_3; + 3'b011 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_4; + 3'b100 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_5; + 3'b101 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_6; + 3'b110 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_7; + default : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_11_16) + 3'b000 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_1; + 3'b001 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_2; + 3'b010 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_3; + 3'b011 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_4; + 3'b100 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_5; + 3'b101 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_6; + 3'b110 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_7; + default : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_11_18) + 3'b000 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_1; + 3'b001 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_2; + 3'b010 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_3; + 3'b011 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_4; + 3'b100 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_5; + 3'b101 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_6; + 3'b110 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_7; + default : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_12_12) + 3'b000 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_1; + 3'b001 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_2; + 3'b010 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_3; + 3'b011 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_4; + 3'b100 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_5; + 3'b101 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_6; + 3'b110 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_7; + default : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_12_14) + 3'b000 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_1; + 3'b001 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_2; + 3'b010 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_3; + 3'b011 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_4; + 3'b100 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_5; + 3'b101 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_6; + 3'b110 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_7; + default : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_12_17) + 3'b000 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_1; + 3'b001 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_2; + 3'b010 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_3; + 3'b011 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_4; + 3'b100 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_5; + 3'b101 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_6; + 3'b110 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_7; + default : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_12_19) + 3'b000 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_1; + 3'b001 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_2; + 3'b010 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_3; + 3'b011 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_4; + 3'b100 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_5; + 3'b101 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_6; + 3'b110 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_7; + default : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_12_21) + 3'b000 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_1; + 3'b001 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_2; + 3'b010 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_3; + 3'b011 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_4; + 3'b100 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_5; + 3'b101 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_6; + 3'b110 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_7; + default : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_13_12) + 3'b000 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_1; + 3'b001 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_2; + 3'b010 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_3; + 3'b011 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_4; + 3'b100 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_5; + 3'b101 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_6; + 3'b110 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_7; + default : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_13_14) + 3'b000 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_1; + 3'b001 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_2; + 3'b010 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_3; + 3'b011 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_4; + 3'b100 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_5; + 3'b101 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_6; + 3'b110 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_7; + default : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_13_17) + 3'b000 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_1; + 3'b001 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_2; + 3'b010 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_3; + 3'b011 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_4; + 3'b100 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_5; + 3'b101 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_6; + 3'b110 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_7; + default : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_13_19) + 3'b000 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_1; + 3'b001 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_2; + 3'b010 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_3; + 3'b011 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_4; + 3'b100 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_5; + 3'b101 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_6; + 3'b110 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_7; + default : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_13_21) + 3'b000 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_1; + 3'b001 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_2; + 3'b010 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_3; + 3'b011 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_4; + 3'b100 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_5; + 3'b101 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_6; + 3'b110 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_7; + default : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_14_12) + 3'b000 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_1; + 3'b001 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_2; + 3'b010 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_3; + 3'b011 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_4; + 3'b100 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_5; + 3'b101 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_6; + 3'b110 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_7; + default : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_14_14) + 3'b000 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_1; + 3'b001 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_2; + 3'b010 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_3; + 3'b011 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_4; + 3'b100 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_5; + 3'b101 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_6; + 3'b110 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_7; + default : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_14_17) + 3'b000 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_1; + 3'b001 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_2; + 3'b010 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_3; + 3'b011 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_4; + 3'b100 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_5; + 3'b101 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_6; + 3'b110 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_7; + default : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_14_19) + 3'b000 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_1; + 3'b001 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_2; + 3'b010 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_3; + 3'b011 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_4; + 3'b100 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_5; + 3'b101 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_6; + 3'b110 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_7; + default : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_14_21) + 3'b000 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_1; + 3'b001 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_2; + 3'b010 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_3; + 3'b011 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_4; + 3'b100 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_5; + 3'b101 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_6; + 3'b110 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_7; + default : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_11) + 3'b000 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_13) + 3'b000 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_16) + 3'b000 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_18) + 3'b000 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_21) + 3'b000 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_23) + 3'b000 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_0) + 4'b0000 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_1) + 4'b0000 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_2) + 4'b0000 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_3) + 4'b0000 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_4) + 4'b0000 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_5) + 4'b0000 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_6) + 4'b0000 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_7) + 4'b0000 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_8) + 4'b0000 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_9) + 4'b0000 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_10) + 4'b0000 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_11) + 4'b0000 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_12) + 4'b0000 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_13) + 4'b0000 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_14) + 4'b0000 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_15) + 4'b0000 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(_zz_io_output_usedUntil_5) + 4'b0000 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_0; + 4'b0001 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_1; + 4'b0010 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_2; + 4'b0011 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_3; + 4'b0100 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_4; + 4'b0101 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_5; + 4'b0110 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_6; + 4'b0111 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_7; + 4'b1000 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_8; + 4'b1001 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_9; + 4'b1010 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_10; + 4'b1011 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_11; + 4'b1100 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_12; + 4'b1101 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_13; + 4'b1110 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_14; + default : _zz_io_output_usedUntil_4 = s2_input_payload_sel_15; + endcase + end + + always @(*) begin + io_input_ready = s0_input_ready; + if(when_Stream_l375) begin + io_input_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! s0_input_valid); + assign s0_input_valid = io_input_rValid; + assign s0_input_payload_data = io_input_rData_data; + assign s0_input_payload_mask = io_input_rData_mask; + assign _zz_s0_countOnesLogic_0 = s0_input_payload_mask[0]; + assign _zz_s0_countOnesLogic_1 = s0_input_payload_mask[1]; + assign _zz_s0_countOnesLogic_2 = s0_input_payload_mask[2]; + assign _zz_s0_countOnesLogic_3 = s0_input_payload_mask[3]; + assign _zz_s0_countOnesLogic_4 = s0_input_payload_mask[4]; + assign _zz_s0_countOnesLogic_5 = s0_input_payload_mask[5]; + assign _zz_s0_countOnesLogic_6 = s0_input_payload_mask[6]; + assign _zz_s0_countOnesLogic_7 = s0_input_payload_mask[7]; + assign _zz_s0_countOnesLogic_8 = s0_input_payload_mask[8]; + assign _zz_s0_countOnesLogic_9 = s0_input_payload_mask[9]; + assign _zz_s0_countOnesLogic_10 = s0_input_payload_mask[10]; + assign _zz_s0_countOnesLogic_11 = s0_input_payload_mask[11]; + assign _zz_s0_countOnesLogic_12 = s0_input_payload_mask[12]; + assign _zz_s0_countOnesLogic_13 = s0_input_payload_mask[13]; + assign _zz_s0_countOnesLogic_14 = s0_input_payload_mask[14]; + assign s0_countOnesLogic_0 = _zz_s0_countOnesLogic_0_1; + assign s0_countOnesLogic_1 = _zz_s0_countOnesLogic_1_1; + assign s0_countOnesLogic_2 = _zz_s0_countOnesLogic_2_1; + assign _zz_s0_countOnesLogic_3_1 = 3'b000; + assign _zz_s0_countOnesLogic_3_2 = 3'b001; + assign _zz_s0_countOnesLogic_3_3 = 3'b001; + assign _zz_s0_countOnesLogic_3_4 = 3'b010; + assign _zz_s0_countOnesLogic_3_5 = 3'b001; + assign _zz_s0_countOnesLogic_3_6 = 3'b010; + assign _zz_s0_countOnesLogic_3_7 = 3'b010; + assign _zz_s0_countOnesLogic_3_8 = 3'b011; + assign s0_countOnesLogic_3 = (_zz_s0_countOnesLogic_3_9 + _zz_s0_countOnesLogic_3_11); + assign _zz_s0_countOnesLogic_4_1 = 3'b000; + assign _zz_s0_countOnesLogic_4_2 = 3'b001; + assign _zz_s0_countOnesLogic_4_3 = 3'b001; + assign _zz_s0_countOnesLogic_4_4 = 3'b010; + assign _zz_s0_countOnesLogic_4_5 = 3'b001; + assign _zz_s0_countOnesLogic_4_6 = 3'b010; + assign _zz_s0_countOnesLogic_4_7 = 3'b010; + assign _zz_s0_countOnesLogic_4_8 = 3'b011; + assign s0_countOnesLogic_4 = (_zz_s0_countOnesLogic_4_9 + _zz_s0_countOnesLogic_4_11); + assign _zz_s0_countOnesLogic_5_1 = 3'b000; + assign _zz_s0_countOnesLogic_5_2 = 3'b001; + assign _zz_s0_countOnesLogic_5_3 = 3'b001; + assign _zz_s0_countOnesLogic_5_4 = 3'b010; + assign _zz_s0_countOnesLogic_5_5 = 3'b001; + assign _zz_s0_countOnesLogic_5_6 = 3'b010; + assign _zz_s0_countOnesLogic_5_7 = 3'b010; + assign _zz_s0_countOnesLogic_5_8 = 3'b011; + assign s0_countOnesLogic_5 = (_zz_s0_countOnesLogic_5_9 + _zz_s0_countOnesLogic_5_11); + assign _zz_s0_countOnesLogic_6_1 = 3'b000; + assign _zz_s0_countOnesLogic_6_2 = 3'b001; + assign _zz_s0_countOnesLogic_6_3 = 3'b001; + assign _zz_s0_countOnesLogic_6_4 = 3'b010; + assign _zz_s0_countOnesLogic_6_5 = 3'b001; + assign _zz_s0_countOnesLogic_6_6 = 3'b010; + assign _zz_s0_countOnesLogic_6_7 = 3'b010; + assign _zz_s0_countOnesLogic_6_8 = 3'b011; + assign s0_countOnesLogic_6 = (_zz_s0_countOnesLogic_6_9 + _zz_s0_countOnesLogic_6_14); + assign _zz_s0_countOnesLogic_7_1 = 4'b0000; + assign _zz_s0_countOnesLogic_7_2 = 4'b0001; + assign _zz_s0_countOnesLogic_7_3 = 4'b0001; + assign _zz_s0_countOnesLogic_7_4 = 4'b0010; + assign _zz_s0_countOnesLogic_7_5 = 4'b0001; + assign _zz_s0_countOnesLogic_7_6 = 4'b0010; + assign _zz_s0_countOnesLogic_7_7 = 4'b0010; + assign _zz_s0_countOnesLogic_7_8 = 4'b0011; + assign s0_countOnesLogic_7 = (_zz_s0_countOnesLogic_7_9 + _zz_s0_countOnesLogic_7_14); + assign _zz_s0_countOnesLogic_8_1 = 4'b0000; + assign _zz_s0_countOnesLogic_8_2 = 4'b0001; + assign _zz_s0_countOnesLogic_8_3 = 4'b0001; + assign _zz_s0_countOnesLogic_8_4 = 4'b0010; + assign _zz_s0_countOnesLogic_8_5 = 4'b0001; + assign _zz_s0_countOnesLogic_8_6 = 4'b0010; + assign _zz_s0_countOnesLogic_8_7 = 4'b0010; + assign _zz_s0_countOnesLogic_8_8 = 4'b0011; + assign s0_countOnesLogic_8 = (_zz_s0_countOnesLogic_8_9 + _zz_s0_countOnesLogic_8_14); + assign _zz_s0_countOnesLogic_9_1 = 4'b0000; + assign _zz_s0_countOnesLogic_9_2 = 4'b0001; + assign _zz_s0_countOnesLogic_9_3 = 4'b0001; + assign _zz_s0_countOnesLogic_9_4 = 4'b0010; + assign _zz_s0_countOnesLogic_9_5 = 4'b0001; + assign _zz_s0_countOnesLogic_9_6 = 4'b0010; + assign _zz_s0_countOnesLogic_9_7 = 4'b0010; + assign _zz_s0_countOnesLogic_9_8 = 4'b0011; + assign s0_countOnesLogic_9 = (_zz_s0_countOnesLogic_9_9 + _zz_s0_countOnesLogic_9_14); + assign _zz_s0_countOnesLogic_10_1 = 4'b0000; + assign _zz_s0_countOnesLogic_10_2 = 4'b0001; + assign _zz_s0_countOnesLogic_10_3 = 4'b0001; + assign _zz_s0_countOnesLogic_10_4 = 4'b0010; + assign _zz_s0_countOnesLogic_10_5 = 4'b0001; + assign _zz_s0_countOnesLogic_10_6 = 4'b0010; + assign _zz_s0_countOnesLogic_10_7 = 4'b0010; + assign _zz_s0_countOnesLogic_10_8 = 4'b0011; + assign s0_countOnesLogic_10 = (_zz_s0_countOnesLogic_10_9 + _zz_s0_countOnesLogic_10_14); + assign _zz_s0_countOnesLogic_11_1 = 4'b0000; + assign _zz_s0_countOnesLogic_11_2 = 4'b0001; + assign _zz_s0_countOnesLogic_11_3 = 4'b0001; + assign _zz_s0_countOnesLogic_11_4 = 4'b0010; + assign _zz_s0_countOnesLogic_11_5 = 4'b0001; + assign _zz_s0_countOnesLogic_11_6 = 4'b0010; + assign _zz_s0_countOnesLogic_11_7 = 4'b0010; + assign _zz_s0_countOnesLogic_11_8 = 4'b0011; + assign s0_countOnesLogic_11 = (_zz_s0_countOnesLogic_11_9 + _zz_s0_countOnesLogic_11_14); + assign _zz_s0_countOnesLogic_12_1 = 4'b0000; + assign _zz_s0_countOnesLogic_12_2 = 4'b0001; + assign _zz_s0_countOnesLogic_12_3 = 4'b0001; + assign _zz_s0_countOnesLogic_12_4 = 4'b0010; + assign _zz_s0_countOnesLogic_12_5 = 4'b0001; + assign _zz_s0_countOnesLogic_12_6 = 4'b0010; + assign _zz_s0_countOnesLogic_12_7 = 4'b0010; + assign _zz_s0_countOnesLogic_12_8 = 4'b0011; + assign s0_countOnesLogic_12 = (_zz_s0_countOnesLogic_12_9 + _zz_s0_countOnesLogic_12_20); + assign _zz_s0_countOnesLogic_13_1 = 4'b0000; + assign _zz_s0_countOnesLogic_13_2 = 4'b0001; + assign _zz_s0_countOnesLogic_13_3 = 4'b0001; + assign _zz_s0_countOnesLogic_13_4 = 4'b0010; + assign _zz_s0_countOnesLogic_13_5 = 4'b0001; + assign _zz_s0_countOnesLogic_13_6 = 4'b0010; + assign _zz_s0_countOnesLogic_13_7 = 4'b0010; + assign _zz_s0_countOnesLogic_13_8 = 4'b0011; + assign s0_countOnesLogic_13 = (_zz_s0_countOnesLogic_13_9 + _zz_s0_countOnesLogic_13_20); + assign _zz_s0_countOnesLogic_14_1 = 4'b0000; + assign _zz_s0_countOnesLogic_14_2 = 4'b0001; + assign _zz_s0_countOnesLogic_14_3 = 4'b0001; + assign _zz_s0_countOnesLogic_14_4 = 4'b0010; + assign _zz_s0_countOnesLogic_14_5 = 4'b0001; + assign _zz_s0_countOnesLogic_14_6 = 4'b0010; + assign _zz_s0_countOnesLogic_14_7 = 4'b0010; + assign _zz_s0_countOnesLogic_14_8 = 4'b0011; + assign s0_countOnesLogic_14 = (_zz_s0_countOnesLogic_14_9 + _zz_s0_countOnesLogic_14_20); + assign _zz_s0_countOnesLogic_15 = 5'h0; + assign _zz_s0_countOnesLogic_15_1 = 5'h01; + assign _zz_s0_countOnesLogic_15_2 = 5'h01; + assign _zz_s0_countOnesLogic_15_3 = 5'h02; + assign _zz_s0_countOnesLogic_15_4 = 5'h01; + assign _zz_s0_countOnesLogic_15_5 = 5'h02; + assign _zz_s0_countOnesLogic_15_6 = 5'h02; + assign _zz_s0_countOnesLogic_15_7 = 5'h03; + assign s0_countOnesLogic_15 = (_zz_s0_countOnesLogic_15_8 + _zz_s0_countOnesLogic_15_19); + assign s0_outputPayload_cmd_data = s0_input_payload_data; + assign s0_outputPayload_cmd_mask = s0_input_payload_mask; + assign s0_outputPayload_countOnes_0 = s0_countOnesLogic_0; + assign s0_outputPayload_countOnes_1 = s0_countOnesLogic_1; + assign s0_outputPayload_countOnes_2 = s0_countOnesLogic_2; + assign s0_outputPayload_countOnes_3 = s0_countOnesLogic_3; + assign s0_outputPayload_countOnes_4 = s0_countOnesLogic_4; + assign s0_outputPayload_countOnes_5 = s0_countOnesLogic_5; + assign s0_outputPayload_countOnes_6 = s0_countOnesLogic_6; + assign s0_outputPayload_countOnes_7 = s0_countOnesLogic_7; + assign s0_outputPayload_countOnes_8 = s0_countOnesLogic_8; + assign s0_outputPayload_countOnes_9 = s0_countOnesLogic_9; + assign s0_outputPayload_countOnes_10 = s0_countOnesLogic_10; + assign s0_outputPayload_countOnes_11 = s0_countOnesLogic_11; + assign s0_outputPayload_countOnes_12 = s0_countOnesLogic_12; + assign s0_outputPayload_countOnes_13 = s0_countOnesLogic_13; + assign s0_outputPayload_countOnes_14 = s0_countOnesLogic_14; + assign s0_outputPayload_countOnes_15 = s0_countOnesLogic_15; + assign s0_output_valid = s0_input_valid; + assign s0_input_ready = s0_output_ready; + assign s0_output_payload_cmd_data = s0_outputPayload_cmd_data; + assign s0_output_payload_cmd_mask = s0_outputPayload_cmd_mask; + assign s0_output_payload_countOnes_0 = s0_outputPayload_countOnes_0; + assign s0_output_payload_countOnes_1 = s0_outputPayload_countOnes_1; + assign s0_output_payload_countOnes_2 = s0_outputPayload_countOnes_2; + assign s0_output_payload_countOnes_3 = s0_outputPayload_countOnes_3; + assign s0_output_payload_countOnes_4 = s0_outputPayload_countOnes_4; + assign s0_output_payload_countOnes_5 = s0_outputPayload_countOnes_5; + assign s0_output_payload_countOnes_6 = s0_outputPayload_countOnes_6; + assign s0_output_payload_countOnes_7 = s0_outputPayload_countOnes_7; + assign s0_output_payload_countOnes_8 = s0_outputPayload_countOnes_8; + assign s0_output_payload_countOnes_9 = s0_outputPayload_countOnes_9; + assign s0_output_payload_countOnes_10 = s0_outputPayload_countOnes_10; + assign s0_output_payload_countOnes_11 = s0_outputPayload_countOnes_11; + assign s0_output_payload_countOnes_12 = s0_outputPayload_countOnes_12; + assign s0_output_payload_countOnes_13 = s0_outputPayload_countOnes_13; + assign s0_output_payload_countOnes_14 = s0_outputPayload_countOnes_14; + assign s0_output_payload_countOnes_15 = s0_outputPayload_countOnes_15; + always @(*) begin + s0_output_ready = s1_input_ready; + if(when_Stream_l375_1) begin + s0_output_ready = 1'b1; + end + end + + assign when_Stream_l375_1 = (! s1_input_valid); + assign s1_input_valid = s0_output_rValid; + assign s1_input_payload_cmd_data = s0_output_rData_cmd_data; + assign s1_input_payload_cmd_mask = s0_output_rData_cmd_mask; + assign s1_input_payload_countOnes_0 = s0_output_rData_countOnes_0; + assign s1_input_payload_countOnes_1 = s0_output_rData_countOnes_1; + assign s1_input_payload_countOnes_2 = s0_output_rData_countOnes_2; + assign s1_input_payload_countOnes_3 = s0_output_rData_countOnes_3; + assign s1_input_payload_countOnes_4 = s0_output_rData_countOnes_4; + assign s1_input_payload_countOnes_5 = s0_output_rData_countOnes_5; + assign s1_input_payload_countOnes_6 = s0_output_rData_countOnes_6; + assign s1_input_payload_countOnes_7 = s0_output_rData_countOnes_7; + assign s1_input_payload_countOnes_8 = s0_output_rData_countOnes_8; + assign s1_input_payload_countOnes_9 = s0_output_rData_countOnes_9; + assign s1_input_payload_countOnes_10 = s0_output_rData_countOnes_10; + assign s1_input_payload_countOnes_11 = s0_output_rData_countOnes_11; + assign s1_input_payload_countOnes_12 = s0_output_rData_countOnes_12; + assign s1_input_payload_countOnes_13 = s0_output_rData_countOnes_13; + assign s1_input_payload_countOnes_14 = s0_output_rData_countOnes_14; + assign s1_input_payload_countOnes_15 = s0_output_rData_countOnes_15; + assign s1_offsetNext = (_zz_s1_offsetNext + s1_input_payload_countOnes_15); + assign s1_input_fire = (s1_input_valid && s1_input_ready); + assign s1_inputIndexes_0 = (4'b0000 + s1_offset); + assign s1_inputIndexes_1 = (_zz_s1_inputIndexes_1 + s1_offset); + assign s1_inputIndexes_2 = (_zz_s1_inputIndexes_2 + s1_offset); + assign s1_inputIndexes_3 = (_zz_s1_inputIndexes_3 + s1_offset); + assign s1_inputIndexes_4 = (_zz_s1_inputIndexes_4 + s1_offset); + assign s1_inputIndexes_5 = (_zz_s1_inputIndexes_5 + s1_offset); + assign s1_inputIndexes_6 = (_zz_s1_inputIndexes_6 + s1_offset); + assign s1_inputIndexes_7 = (_zz_s1_inputIndexes_7 + s1_offset); + assign s1_inputIndexes_8 = (s1_input_payload_countOnes_7 + s1_offset); + assign s1_inputIndexes_9 = (s1_input_payload_countOnes_8 + s1_offset); + assign s1_inputIndexes_10 = (s1_input_payload_countOnes_9 + s1_offset); + assign s1_inputIndexes_11 = (s1_input_payload_countOnes_10 + s1_offset); + assign s1_inputIndexes_12 = (s1_input_payload_countOnes_11 + s1_offset); + assign s1_inputIndexes_13 = (s1_input_payload_countOnes_12 + s1_offset); + assign s1_inputIndexes_14 = (s1_input_payload_countOnes_13 + s1_offset); + assign s1_inputIndexes_15 = (s1_input_payload_countOnes_14 + s1_offset); + assign s1_outputPayload_cmd_data = s1_input_payload_cmd_data; + assign s1_outputPayload_cmd_mask = s1_input_payload_cmd_mask; + assign s1_outputPayload_index_0 = s1_inputIndexes_0; + assign s1_outputPayload_index_1 = s1_inputIndexes_1; + assign s1_outputPayload_index_2 = s1_inputIndexes_2; + assign s1_outputPayload_index_3 = s1_inputIndexes_3; + assign s1_outputPayload_index_4 = s1_inputIndexes_4; + assign s1_outputPayload_index_5 = s1_inputIndexes_5; + assign s1_outputPayload_index_6 = s1_inputIndexes_6; + assign s1_outputPayload_index_7 = s1_inputIndexes_7; + assign s1_outputPayload_index_8 = s1_inputIndexes_8; + assign s1_outputPayload_index_9 = s1_inputIndexes_9; + assign s1_outputPayload_index_10 = s1_inputIndexes_10; + assign s1_outputPayload_index_11 = s1_inputIndexes_11; + assign s1_outputPayload_index_12 = s1_inputIndexes_12; + assign s1_outputPayload_index_13 = s1_inputIndexes_13; + assign s1_outputPayload_index_14 = s1_inputIndexes_14; + assign s1_outputPayload_index_15 = s1_inputIndexes_15; + assign s1_outputPayload_last = s1_offsetNext[4]; + assign _zz_s1_outputPayload_selValid = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_1 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_2 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_3 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_4 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_5 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_6 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_7 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_8 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_9 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_10 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_11 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_12 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_13 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_14 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0000)); + assign _zz_s1_outputPayload_sel_0 = (((((((_zz_s1_outputPayload_selValid || _zz_s1_outputPayload_selValid_2) || _zz_s1_outputPayload_selValid_4) || _zz_s1_outputPayload_selValid_6) || _zz_s1_outputPayload_selValid_8) || _zz_s1_outputPayload_selValid_10) || _zz_s1_outputPayload_selValid_12) || _zz_s1_outputPayload_selValid_14); + assign _zz_s1_outputPayload_sel_0_1 = (((((((_zz_s1_outputPayload_selValid_1 || _zz_s1_outputPayload_selValid_2) || _zz_s1_outputPayload_selValid_5) || _zz_s1_outputPayload_selValid_6) || _zz_s1_outputPayload_selValid_9) || _zz_s1_outputPayload_selValid_10) || _zz_s1_outputPayload_selValid_13) || _zz_s1_outputPayload_selValid_14); + assign _zz_s1_outputPayload_sel_0_2 = (((((((_zz_s1_outputPayload_selValid_3 || _zz_s1_outputPayload_selValid_4) || _zz_s1_outputPayload_selValid_5) || _zz_s1_outputPayload_selValid_6) || _zz_s1_outputPayload_selValid_11) || _zz_s1_outputPayload_selValid_12) || _zz_s1_outputPayload_selValid_13) || _zz_s1_outputPayload_selValid_14); + assign _zz_s1_outputPayload_sel_0_3 = (((((((_zz_s1_outputPayload_selValid_7 || _zz_s1_outputPayload_selValid_8) || _zz_s1_outputPayload_selValid_9) || _zz_s1_outputPayload_selValid_10) || _zz_s1_outputPayload_selValid_11) || _zz_s1_outputPayload_selValid_12) || _zz_s1_outputPayload_selValid_13) || _zz_s1_outputPayload_selValid_14); + assign s1_outputPayload_sel_0 = {_zz_s1_outputPayload_sel_0_3,{_zz_s1_outputPayload_sel_0_2,{_zz_s1_outputPayload_sel_0_1,_zz_s1_outputPayload_sel_0}}}; + always @(*) begin + s1_outputPayload_selValid[0] = ((|{_zz_s1_outputPayload_selValid_14,{_zz_s1_outputPayload_selValid_13,{_zz_s1_outputPayload_selValid_12,{_zz_s1_outputPayload_selValid_11,{_zz_s1_outputPayload_selValid_10,{_zz_s1_outputPayload_selValid_9,{_zz_s1_outputPayload_selValid_8,{_zz_s1_outputPayload_selValid_7,{_zz_s1_outputPayload_selValid_240,_zz_s1_outputPayload_selValid_241}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_0]); + s1_outputPayload_selValid[1] = ((|{_zz_s1_outputPayload_selValid_29,{_zz_s1_outputPayload_selValid_28,{_zz_s1_outputPayload_selValid_27,{_zz_s1_outputPayload_selValid_26,{_zz_s1_outputPayload_selValid_25,{_zz_s1_outputPayload_selValid_24,{_zz_s1_outputPayload_selValid_23,{_zz_s1_outputPayload_selValid_22,{_zz_s1_outputPayload_selValid_242,_zz_s1_outputPayload_selValid_243}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_1]); + s1_outputPayload_selValid[2] = ((|{_zz_s1_outputPayload_selValid_44,{_zz_s1_outputPayload_selValid_43,{_zz_s1_outputPayload_selValid_42,{_zz_s1_outputPayload_selValid_41,{_zz_s1_outputPayload_selValid_40,{_zz_s1_outputPayload_selValid_39,{_zz_s1_outputPayload_selValid_38,{_zz_s1_outputPayload_selValid_37,{_zz_s1_outputPayload_selValid_244,_zz_s1_outputPayload_selValid_245}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_2]); + s1_outputPayload_selValid[3] = ((|{_zz_s1_outputPayload_selValid_59,{_zz_s1_outputPayload_selValid_58,{_zz_s1_outputPayload_selValid_57,{_zz_s1_outputPayload_selValid_56,{_zz_s1_outputPayload_selValid_55,{_zz_s1_outputPayload_selValid_54,{_zz_s1_outputPayload_selValid_53,{_zz_s1_outputPayload_selValid_52,{_zz_s1_outputPayload_selValid_246,_zz_s1_outputPayload_selValid_247}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_3]); + s1_outputPayload_selValid[4] = ((|{_zz_s1_outputPayload_selValid_74,{_zz_s1_outputPayload_selValid_73,{_zz_s1_outputPayload_selValid_72,{_zz_s1_outputPayload_selValid_71,{_zz_s1_outputPayload_selValid_70,{_zz_s1_outputPayload_selValid_69,{_zz_s1_outputPayload_selValid_68,{_zz_s1_outputPayload_selValid_67,{_zz_s1_outputPayload_selValid_248,_zz_s1_outputPayload_selValid_249}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_4]); + s1_outputPayload_selValid[5] = ((|{_zz_s1_outputPayload_selValid_89,{_zz_s1_outputPayload_selValid_88,{_zz_s1_outputPayload_selValid_87,{_zz_s1_outputPayload_selValid_86,{_zz_s1_outputPayload_selValid_85,{_zz_s1_outputPayload_selValid_84,{_zz_s1_outputPayload_selValid_83,{_zz_s1_outputPayload_selValid_82,{_zz_s1_outputPayload_selValid_250,_zz_s1_outputPayload_selValid_251}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_5]); + s1_outputPayload_selValid[6] = ((|{_zz_s1_outputPayload_selValid_104,{_zz_s1_outputPayload_selValid_103,{_zz_s1_outputPayload_selValid_102,{_zz_s1_outputPayload_selValid_101,{_zz_s1_outputPayload_selValid_100,{_zz_s1_outputPayload_selValid_99,{_zz_s1_outputPayload_selValid_98,{_zz_s1_outputPayload_selValid_97,{_zz_s1_outputPayload_selValid_252,_zz_s1_outputPayload_selValid_253}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_6]); + s1_outputPayload_selValid[7] = ((|{_zz_s1_outputPayload_selValid_119,{_zz_s1_outputPayload_selValid_118,{_zz_s1_outputPayload_selValid_117,{_zz_s1_outputPayload_selValid_116,{_zz_s1_outputPayload_selValid_115,{_zz_s1_outputPayload_selValid_114,{_zz_s1_outputPayload_selValid_113,{_zz_s1_outputPayload_selValid_112,{_zz_s1_outputPayload_selValid_254,_zz_s1_outputPayload_selValid_255}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_7]); + s1_outputPayload_selValid[8] = ((|{_zz_s1_outputPayload_selValid_134,{_zz_s1_outputPayload_selValid_133,{_zz_s1_outputPayload_selValid_132,{_zz_s1_outputPayload_selValid_131,{_zz_s1_outputPayload_selValid_130,{_zz_s1_outputPayload_selValid_129,{_zz_s1_outputPayload_selValid_128,{_zz_s1_outputPayload_selValid_127,{_zz_s1_outputPayload_selValid_256,_zz_s1_outputPayload_selValid_257}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_8]); + s1_outputPayload_selValid[9] = ((|{_zz_s1_outputPayload_selValid_149,{_zz_s1_outputPayload_selValid_148,{_zz_s1_outputPayload_selValid_147,{_zz_s1_outputPayload_selValid_146,{_zz_s1_outputPayload_selValid_145,{_zz_s1_outputPayload_selValid_144,{_zz_s1_outputPayload_selValid_143,{_zz_s1_outputPayload_selValid_142,{_zz_s1_outputPayload_selValid_258,_zz_s1_outputPayload_selValid_259}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_9]); + s1_outputPayload_selValid[10] = ((|{_zz_s1_outputPayload_selValid_164,{_zz_s1_outputPayload_selValid_163,{_zz_s1_outputPayload_selValid_162,{_zz_s1_outputPayload_selValid_161,{_zz_s1_outputPayload_selValid_160,{_zz_s1_outputPayload_selValid_159,{_zz_s1_outputPayload_selValid_158,{_zz_s1_outputPayload_selValid_157,{_zz_s1_outputPayload_selValid_260,_zz_s1_outputPayload_selValid_261}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_10]); + s1_outputPayload_selValid[11] = ((|{_zz_s1_outputPayload_selValid_179,{_zz_s1_outputPayload_selValid_178,{_zz_s1_outputPayload_selValid_177,{_zz_s1_outputPayload_selValid_176,{_zz_s1_outputPayload_selValid_175,{_zz_s1_outputPayload_selValid_174,{_zz_s1_outputPayload_selValid_173,{_zz_s1_outputPayload_selValid_172,{_zz_s1_outputPayload_selValid_262,_zz_s1_outputPayload_selValid_263}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_11]); + s1_outputPayload_selValid[12] = ((|{_zz_s1_outputPayload_selValid_194,{_zz_s1_outputPayload_selValid_193,{_zz_s1_outputPayload_selValid_192,{_zz_s1_outputPayload_selValid_191,{_zz_s1_outputPayload_selValid_190,{_zz_s1_outputPayload_selValid_189,{_zz_s1_outputPayload_selValid_188,{_zz_s1_outputPayload_selValid_187,{_zz_s1_outputPayload_selValid_264,_zz_s1_outputPayload_selValid_265}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_12]); + s1_outputPayload_selValid[13] = ((|{_zz_s1_outputPayload_selValid_209,{_zz_s1_outputPayload_selValid_208,{_zz_s1_outputPayload_selValid_207,{_zz_s1_outputPayload_selValid_206,{_zz_s1_outputPayload_selValid_205,{_zz_s1_outputPayload_selValid_204,{_zz_s1_outputPayload_selValid_203,{_zz_s1_outputPayload_selValid_202,{_zz_s1_outputPayload_selValid_266,_zz_s1_outputPayload_selValid_267}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_13]); + s1_outputPayload_selValid[14] = ((|{_zz_s1_outputPayload_selValid_224,{_zz_s1_outputPayload_selValid_223,{_zz_s1_outputPayload_selValid_222,{_zz_s1_outputPayload_selValid_221,{_zz_s1_outputPayload_selValid_220,{_zz_s1_outputPayload_selValid_219,{_zz_s1_outputPayload_selValid_218,{_zz_s1_outputPayload_selValid_217,{_zz_s1_outputPayload_selValid_268,_zz_s1_outputPayload_selValid_269}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_14]); + s1_outputPayload_selValid[15] = ((|{_zz_s1_outputPayload_selValid_239,{_zz_s1_outputPayload_selValid_238,{_zz_s1_outputPayload_selValid_237,{_zz_s1_outputPayload_selValid_236,{_zz_s1_outputPayload_selValid_235,{_zz_s1_outputPayload_selValid_234,{_zz_s1_outputPayload_selValid_233,{_zz_s1_outputPayload_selValid_232,{_zz_s1_outputPayload_selValid_270,_zz_s1_outputPayload_selValid_271}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_15]); + end + + assign _zz_s1_outputPayload_selValid_15 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_16 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_17 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_18 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_19 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_20 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_21 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_22 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_23 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_24 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_25 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_26 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_27 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_28 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_29 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0001)); + assign _zz_s1_outputPayload_sel_1 = (((((((_zz_s1_outputPayload_selValid_15 || _zz_s1_outputPayload_selValid_17) || _zz_s1_outputPayload_selValid_19) || _zz_s1_outputPayload_selValid_21) || _zz_s1_outputPayload_selValid_23) || _zz_s1_outputPayload_selValid_25) || _zz_s1_outputPayload_selValid_27) || _zz_s1_outputPayload_selValid_29); + assign _zz_s1_outputPayload_sel_1_1 = (((((((_zz_s1_outputPayload_selValid_16 || _zz_s1_outputPayload_selValid_17) || _zz_s1_outputPayload_selValid_20) || _zz_s1_outputPayload_selValid_21) || _zz_s1_outputPayload_selValid_24) || _zz_s1_outputPayload_selValid_25) || _zz_s1_outputPayload_selValid_28) || _zz_s1_outputPayload_selValid_29); + assign _zz_s1_outputPayload_sel_1_2 = (((((((_zz_s1_outputPayload_selValid_18 || _zz_s1_outputPayload_selValid_19) || _zz_s1_outputPayload_selValid_20) || _zz_s1_outputPayload_selValid_21) || _zz_s1_outputPayload_selValid_26) || _zz_s1_outputPayload_selValid_27) || _zz_s1_outputPayload_selValid_28) || _zz_s1_outputPayload_selValid_29); + assign _zz_s1_outputPayload_sel_1_3 = (((((((_zz_s1_outputPayload_selValid_22 || _zz_s1_outputPayload_selValid_23) || _zz_s1_outputPayload_selValid_24) || _zz_s1_outputPayload_selValid_25) || _zz_s1_outputPayload_selValid_26) || _zz_s1_outputPayload_selValid_27) || _zz_s1_outputPayload_selValid_28) || _zz_s1_outputPayload_selValid_29); + assign s1_outputPayload_sel_1 = {_zz_s1_outputPayload_sel_1_3,{_zz_s1_outputPayload_sel_1_2,{_zz_s1_outputPayload_sel_1_1,_zz_s1_outputPayload_sel_1}}}; + assign _zz_s1_outputPayload_selValid_30 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_31 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_32 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_33 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_34 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_35 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_36 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_37 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_38 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_39 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_40 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_41 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_42 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_43 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_44 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0010)); + assign _zz_s1_outputPayload_sel_2 = (((((((_zz_s1_outputPayload_selValid_30 || _zz_s1_outputPayload_selValid_32) || _zz_s1_outputPayload_selValid_34) || _zz_s1_outputPayload_selValid_36) || _zz_s1_outputPayload_selValid_38) || _zz_s1_outputPayload_selValid_40) || _zz_s1_outputPayload_selValid_42) || _zz_s1_outputPayload_selValid_44); + assign _zz_s1_outputPayload_sel_2_1 = (((((((_zz_s1_outputPayload_selValid_31 || _zz_s1_outputPayload_selValid_32) || _zz_s1_outputPayload_selValid_35) || _zz_s1_outputPayload_selValid_36) || _zz_s1_outputPayload_selValid_39) || _zz_s1_outputPayload_selValid_40) || _zz_s1_outputPayload_selValid_43) || _zz_s1_outputPayload_selValid_44); + assign _zz_s1_outputPayload_sel_2_2 = (((((((_zz_s1_outputPayload_selValid_33 || _zz_s1_outputPayload_selValid_34) || _zz_s1_outputPayload_selValid_35) || _zz_s1_outputPayload_selValid_36) || _zz_s1_outputPayload_selValid_41) || _zz_s1_outputPayload_selValid_42) || _zz_s1_outputPayload_selValid_43) || _zz_s1_outputPayload_selValid_44); + assign _zz_s1_outputPayload_sel_2_3 = (((((((_zz_s1_outputPayload_selValid_37 || _zz_s1_outputPayload_selValid_38) || _zz_s1_outputPayload_selValid_39) || _zz_s1_outputPayload_selValid_40) || _zz_s1_outputPayload_selValid_41) || _zz_s1_outputPayload_selValid_42) || _zz_s1_outputPayload_selValid_43) || _zz_s1_outputPayload_selValid_44); + assign s1_outputPayload_sel_2 = {_zz_s1_outputPayload_sel_2_3,{_zz_s1_outputPayload_sel_2_2,{_zz_s1_outputPayload_sel_2_1,_zz_s1_outputPayload_sel_2}}}; + assign _zz_s1_outputPayload_selValid_45 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_46 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_47 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_48 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_49 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_50 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_51 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_52 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_53 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_54 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_55 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_56 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_57 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_58 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_59 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0011)); + assign _zz_s1_outputPayload_sel_3 = (((((((_zz_s1_outputPayload_selValid_45 || _zz_s1_outputPayload_selValid_47) || _zz_s1_outputPayload_selValid_49) || _zz_s1_outputPayload_selValid_51) || _zz_s1_outputPayload_selValid_53) || _zz_s1_outputPayload_selValid_55) || _zz_s1_outputPayload_selValid_57) || _zz_s1_outputPayload_selValid_59); + assign _zz_s1_outputPayload_sel_3_1 = (((((((_zz_s1_outputPayload_selValid_46 || _zz_s1_outputPayload_selValid_47) || _zz_s1_outputPayload_selValid_50) || _zz_s1_outputPayload_selValid_51) || _zz_s1_outputPayload_selValid_54) || _zz_s1_outputPayload_selValid_55) || _zz_s1_outputPayload_selValid_58) || _zz_s1_outputPayload_selValid_59); + assign _zz_s1_outputPayload_sel_3_2 = (((((((_zz_s1_outputPayload_selValid_48 || _zz_s1_outputPayload_selValid_49) || _zz_s1_outputPayload_selValid_50) || _zz_s1_outputPayload_selValid_51) || _zz_s1_outputPayload_selValid_56) || _zz_s1_outputPayload_selValid_57) || _zz_s1_outputPayload_selValid_58) || _zz_s1_outputPayload_selValid_59); + assign _zz_s1_outputPayload_sel_3_3 = (((((((_zz_s1_outputPayload_selValid_52 || _zz_s1_outputPayload_selValid_53) || _zz_s1_outputPayload_selValid_54) || _zz_s1_outputPayload_selValid_55) || _zz_s1_outputPayload_selValid_56) || _zz_s1_outputPayload_selValid_57) || _zz_s1_outputPayload_selValid_58) || _zz_s1_outputPayload_selValid_59); + assign s1_outputPayload_sel_3 = {_zz_s1_outputPayload_sel_3_3,{_zz_s1_outputPayload_sel_3_2,{_zz_s1_outputPayload_sel_3_1,_zz_s1_outputPayload_sel_3}}}; + assign _zz_s1_outputPayload_selValid_60 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_61 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_62 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_63 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_64 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_65 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_66 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_67 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_68 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_69 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_70 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_71 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_72 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_73 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_74 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0100)); + assign _zz_s1_outputPayload_sel_4 = (((((((_zz_s1_outputPayload_selValid_60 || _zz_s1_outputPayload_selValid_62) || _zz_s1_outputPayload_selValid_64) || _zz_s1_outputPayload_selValid_66) || _zz_s1_outputPayload_selValid_68) || _zz_s1_outputPayload_selValid_70) || _zz_s1_outputPayload_selValid_72) || _zz_s1_outputPayload_selValid_74); + assign _zz_s1_outputPayload_sel_4_1 = (((((((_zz_s1_outputPayload_selValid_61 || _zz_s1_outputPayload_selValid_62) || _zz_s1_outputPayload_selValid_65) || _zz_s1_outputPayload_selValid_66) || _zz_s1_outputPayload_selValid_69) || _zz_s1_outputPayload_selValid_70) || _zz_s1_outputPayload_selValid_73) || _zz_s1_outputPayload_selValid_74); + assign _zz_s1_outputPayload_sel_4_2 = (((((((_zz_s1_outputPayload_selValid_63 || _zz_s1_outputPayload_selValid_64) || _zz_s1_outputPayload_selValid_65) || _zz_s1_outputPayload_selValid_66) || _zz_s1_outputPayload_selValid_71) || _zz_s1_outputPayload_selValid_72) || _zz_s1_outputPayload_selValid_73) || _zz_s1_outputPayload_selValid_74); + assign _zz_s1_outputPayload_sel_4_3 = (((((((_zz_s1_outputPayload_selValid_67 || _zz_s1_outputPayload_selValid_68) || _zz_s1_outputPayload_selValid_69) || _zz_s1_outputPayload_selValid_70) || _zz_s1_outputPayload_selValid_71) || _zz_s1_outputPayload_selValid_72) || _zz_s1_outputPayload_selValid_73) || _zz_s1_outputPayload_selValid_74); + assign s1_outputPayload_sel_4 = {_zz_s1_outputPayload_sel_4_3,{_zz_s1_outputPayload_sel_4_2,{_zz_s1_outputPayload_sel_4_1,_zz_s1_outputPayload_sel_4}}}; + assign _zz_s1_outputPayload_selValid_75 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_76 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_77 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_78 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_79 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_80 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_81 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_82 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_83 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_84 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_85 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_86 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_87 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_88 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_89 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0101)); + assign _zz_s1_outputPayload_sel_5 = (((((((_zz_s1_outputPayload_selValid_75 || _zz_s1_outputPayload_selValid_77) || _zz_s1_outputPayload_selValid_79) || _zz_s1_outputPayload_selValid_81) || _zz_s1_outputPayload_selValid_83) || _zz_s1_outputPayload_selValid_85) || _zz_s1_outputPayload_selValid_87) || _zz_s1_outputPayload_selValid_89); + assign _zz_s1_outputPayload_sel_5_1 = (((((((_zz_s1_outputPayload_selValid_76 || _zz_s1_outputPayload_selValid_77) || _zz_s1_outputPayload_selValid_80) || _zz_s1_outputPayload_selValid_81) || _zz_s1_outputPayload_selValid_84) || _zz_s1_outputPayload_selValid_85) || _zz_s1_outputPayload_selValid_88) || _zz_s1_outputPayload_selValid_89); + assign _zz_s1_outputPayload_sel_5_2 = (((((((_zz_s1_outputPayload_selValid_78 || _zz_s1_outputPayload_selValid_79) || _zz_s1_outputPayload_selValid_80) || _zz_s1_outputPayload_selValid_81) || _zz_s1_outputPayload_selValid_86) || _zz_s1_outputPayload_selValid_87) || _zz_s1_outputPayload_selValid_88) || _zz_s1_outputPayload_selValid_89); + assign _zz_s1_outputPayload_sel_5_3 = (((((((_zz_s1_outputPayload_selValid_82 || _zz_s1_outputPayload_selValid_83) || _zz_s1_outputPayload_selValid_84) || _zz_s1_outputPayload_selValid_85) || _zz_s1_outputPayload_selValid_86) || _zz_s1_outputPayload_selValid_87) || _zz_s1_outputPayload_selValid_88) || _zz_s1_outputPayload_selValid_89); + assign s1_outputPayload_sel_5 = {_zz_s1_outputPayload_sel_5_3,{_zz_s1_outputPayload_sel_5_2,{_zz_s1_outputPayload_sel_5_1,_zz_s1_outputPayload_sel_5}}}; + assign _zz_s1_outputPayload_selValid_90 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_91 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_92 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_93 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_94 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_95 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_96 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_97 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_98 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_99 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_100 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_101 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_102 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_103 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_104 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0110)); + assign _zz_s1_outputPayload_sel_6 = (((((((_zz_s1_outputPayload_selValid_90 || _zz_s1_outputPayload_selValid_92) || _zz_s1_outputPayload_selValid_94) || _zz_s1_outputPayload_selValid_96) || _zz_s1_outputPayload_selValid_98) || _zz_s1_outputPayload_selValid_100) || _zz_s1_outputPayload_selValid_102) || _zz_s1_outputPayload_selValid_104); + assign _zz_s1_outputPayload_sel_6_1 = (((((((_zz_s1_outputPayload_selValid_91 || _zz_s1_outputPayload_selValid_92) || _zz_s1_outputPayload_selValid_95) || _zz_s1_outputPayload_selValid_96) || _zz_s1_outputPayload_selValid_99) || _zz_s1_outputPayload_selValid_100) || _zz_s1_outputPayload_selValid_103) || _zz_s1_outputPayload_selValid_104); + assign _zz_s1_outputPayload_sel_6_2 = (((((((_zz_s1_outputPayload_selValid_93 || _zz_s1_outputPayload_selValid_94) || _zz_s1_outputPayload_selValid_95) || _zz_s1_outputPayload_selValid_96) || _zz_s1_outputPayload_selValid_101) || _zz_s1_outputPayload_selValid_102) || _zz_s1_outputPayload_selValid_103) || _zz_s1_outputPayload_selValid_104); + assign _zz_s1_outputPayload_sel_6_3 = (((((((_zz_s1_outputPayload_selValid_97 || _zz_s1_outputPayload_selValid_98) || _zz_s1_outputPayload_selValid_99) || _zz_s1_outputPayload_selValid_100) || _zz_s1_outputPayload_selValid_101) || _zz_s1_outputPayload_selValid_102) || _zz_s1_outputPayload_selValid_103) || _zz_s1_outputPayload_selValid_104); + assign s1_outputPayload_sel_6 = {_zz_s1_outputPayload_sel_6_3,{_zz_s1_outputPayload_sel_6_2,{_zz_s1_outputPayload_sel_6_1,_zz_s1_outputPayload_sel_6}}}; + assign _zz_s1_outputPayload_selValid_105 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_106 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_107 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_108 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_109 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_110 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_111 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_112 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_113 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_114 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_115 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_116 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_117 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_118 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_119 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0111)); + assign _zz_s1_outputPayload_sel_7 = (((((((_zz_s1_outputPayload_selValid_105 || _zz_s1_outputPayload_selValid_107) || _zz_s1_outputPayload_selValid_109) || _zz_s1_outputPayload_selValid_111) || _zz_s1_outputPayload_selValid_113) || _zz_s1_outputPayload_selValid_115) || _zz_s1_outputPayload_selValid_117) || _zz_s1_outputPayload_selValid_119); + assign _zz_s1_outputPayload_sel_7_1 = (((((((_zz_s1_outputPayload_selValid_106 || _zz_s1_outputPayload_selValid_107) || _zz_s1_outputPayload_selValid_110) || _zz_s1_outputPayload_selValid_111) || _zz_s1_outputPayload_selValid_114) || _zz_s1_outputPayload_selValid_115) || _zz_s1_outputPayload_selValid_118) || _zz_s1_outputPayload_selValid_119); + assign _zz_s1_outputPayload_sel_7_2 = (((((((_zz_s1_outputPayload_selValid_108 || _zz_s1_outputPayload_selValid_109) || _zz_s1_outputPayload_selValid_110) || _zz_s1_outputPayload_selValid_111) || _zz_s1_outputPayload_selValid_116) || _zz_s1_outputPayload_selValid_117) || _zz_s1_outputPayload_selValid_118) || _zz_s1_outputPayload_selValid_119); + assign _zz_s1_outputPayload_sel_7_3 = (((((((_zz_s1_outputPayload_selValid_112 || _zz_s1_outputPayload_selValid_113) || _zz_s1_outputPayload_selValid_114) || _zz_s1_outputPayload_selValid_115) || _zz_s1_outputPayload_selValid_116) || _zz_s1_outputPayload_selValid_117) || _zz_s1_outputPayload_selValid_118) || _zz_s1_outputPayload_selValid_119); + assign s1_outputPayload_sel_7 = {_zz_s1_outputPayload_sel_7_3,{_zz_s1_outputPayload_sel_7_2,{_zz_s1_outputPayload_sel_7_1,_zz_s1_outputPayload_sel_7}}}; + assign _zz_s1_outputPayload_selValid_120 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_121 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_122 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_123 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_124 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_125 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_126 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_127 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_128 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_129 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_130 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_131 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_132 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_133 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_134 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1000)); + assign _zz_s1_outputPayload_sel_8 = (((((((_zz_s1_outputPayload_selValid_120 || _zz_s1_outputPayload_selValid_122) || _zz_s1_outputPayload_selValid_124) || _zz_s1_outputPayload_selValid_126) || _zz_s1_outputPayload_selValid_128) || _zz_s1_outputPayload_selValid_130) || _zz_s1_outputPayload_selValid_132) || _zz_s1_outputPayload_selValid_134); + assign _zz_s1_outputPayload_sel_8_1 = (((((((_zz_s1_outputPayload_selValid_121 || _zz_s1_outputPayload_selValid_122) || _zz_s1_outputPayload_selValid_125) || _zz_s1_outputPayload_selValid_126) || _zz_s1_outputPayload_selValid_129) || _zz_s1_outputPayload_selValid_130) || _zz_s1_outputPayload_selValid_133) || _zz_s1_outputPayload_selValid_134); + assign _zz_s1_outputPayload_sel_8_2 = (((((((_zz_s1_outputPayload_selValid_123 || _zz_s1_outputPayload_selValid_124) || _zz_s1_outputPayload_selValid_125) || _zz_s1_outputPayload_selValid_126) || _zz_s1_outputPayload_selValid_131) || _zz_s1_outputPayload_selValid_132) || _zz_s1_outputPayload_selValid_133) || _zz_s1_outputPayload_selValid_134); + assign _zz_s1_outputPayload_sel_8_3 = (((((((_zz_s1_outputPayload_selValid_127 || _zz_s1_outputPayload_selValid_128) || _zz_s1_outputPayload_selValid_129) || _zz_s1_outputPayload_selValid_130) || _zz_s1_outputPayload_selValid_131) || _zz_s1_outputPayload_selValid_132) || _zz_s1_outputPayload_selValid_133) || _zz_s1_outputPayload_selValid_134); + assign s1_outputPayload_sel_8 = {_zz_s1_outputPayload_sel_8_3,{_zz_s1_outputPayload_sel_8_2,{_zz_s1_outputPayload_sel_8_1,_zz_s1_outputPayload_sel_8}}}; + assign _zz_s1_outputPayload_selValid_135 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_136 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_137 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_138 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_139 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_140 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_141 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_142 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_143 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_144 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_145 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_146 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_147 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_148 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_149 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1001)); + assign _zz_s1_outputPayload_sel_9 = (((((((_zz_s1_outputPayload_selValid_135 || _zz_s1_outputPayload_selValid_137) || _zz_s1_outputPayload_selValid_139) || _zz_s1_outputPayload_selValid_141) || _zz_s1_outputPayload_selValid_143) || _zz_s1_outputPayload_selValid_145) || _zz_s1_outputPayload_selValid_147) || _zz_s1_outputPayload_selValid_149); + assign _zz_s1_outputPayload_sel_9_1 = (((((((_zz_s1_outputPayload_selValid_136 || _zz_s1_outputPayload_selValid_137) || _zz_s1_outputPayload_selValid_140) || _zz_s1_outputPayload_selValid_141) || _zz_s1_outputPayload_selValid_144) || _zz_s1_outputPayload_selValid_145) || _zz_s1_outputPayload_selValid_148) || _zz_s1_outputPayload_selValid_149); + assign _zz_s1_outputPayload_sel_9_2 = (((((((_zz_s1_outputPayload_selValid_138 || _zz_s1_outputPayload_selValid_139) || _zz_s1_outputPayload_selValid_140) || _zz_s1_outputPayload_selValid_141) || _zz_s1_outputPayload_selValid_146) || _zz_s1_outputPayload_selValid_147) || _zz_s1_outputPayload_selValid_148) || _zz_s1_outputPayload_selValid_149); + assign _zz_s1_outputPayload_sel_9_3 = (((((((_zz_s1_outputPayload_selValid_142 || _zz_s1_outputPayload_selValid_143) || _zz_s1_outputPayload_selValid_144) || _zz_s1_outputPayload_selValid_145) || _zz_s1_outputPayload_selValid_146) || _zz_s1_outputPayload_selValid_147) || _zz_s1_outputPayload_selValid_148) || _zz_s1_outputPayload_selValid_149); + assign s1_outputPayload_sel_9 = {_zz_s1_outputPayload_sel_9_3,{_zz_s1_outputPayload_sel_9_2,{_zz_s1_outputPayload_sel_9_1,_zz_s1_outputPayload_sel_9}}}; + assign _zz_s1_outputPayload_selValid_150 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_151 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_152 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_153 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_154 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_155 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_156 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_157 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_158 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_159 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_160 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_161 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_162 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_163 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_164 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1010)); + assign _zz_s1_outputPayload_sel_10 = (((((((_zz_s1_outputPayload_selValid_150 || _zz_s1_outputPayload_selValid_152) || _zz_s1_outputPayload_selValid_154) || _zz_s1_outputPayload_selValid_156) || _zz_s1_outputPayload_selValid_158) || _zz_s1_outputPayload_selValid_160) || _zz_s1_outputPayload_selValid_162) || _zz_s1_outputPayload_selValid_164); + assign _zz_s1_outputPayload_sel_10_1 = (((((((_zz_s1_outputPayload_selValid_151 || _zz_s1_outputPayload_selValid_152) || _zz_s1_outputPayload_selValid_155) || _zz_s1_outputPayload_selValid_156) || _zz_s1_outputPayload_selValid_159) || _zz_s1_outputPayload_selValid_160) || _zz_s1_outputPayload_selValid_163) || _zz_s1_outputPayload_selValid_164); + assign _zz_s1_outputPayload_sel_10_2 = (((((((_zz_s1_outputPayload_selValid_153 || _zz_s1_outputPayload_selValid_154) || _zz_s1_outputPayload_selValid_155) || _zz_s1_outputPayload_selValid_156) || _zz_s1_outputPayload_selValid_161) || _zz_s1_outputPayload_selValid_162) || _zz_s1_outputPayload_selValid_163) || _zz_s1_outputPayload_selValid_164); + assign _zz_s1_outputPayload_sel_10_3 = (((((((_zz_s1_outputPayload_selValid_157 || _zz_s1_outputPayload_selValid_158) || _zz_s1_outputPayload_selValid_159) || _zz_s1_outputPayload_selValid_160) || _zz_s1_outputPayload_selValid_161) || _zz_s1_outputPayload_selValid_162) || _zz_s1_outputPayload_selValid_163) || _zz_s1_outputPayload_selValid_164); + assign s1_outputPayload_sel_10 = {_zz_s1_outputPayload_sel_10_3,{_zz_s1_outputPayload_sel_10_2,{_zz_s1_outputPayload_sel_10_1,_zz_s1_outputPayload_sel_10}}}; + assign _zz_s1_outputPayload_selValid_165 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_166 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_167 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_168 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_169 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_170 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_171 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_172 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_173 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_174 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_175 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_176 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_177 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_178 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_179 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1011)); + assign _zz_s1_outputPayload_sel_11 = (((((((_zz_s1_outputPayload_selValid_165 || _zz_s1_outputPayload_selValid_167) || _zz_s1_outputPayload_selValid_169) || _zz_s1_outputPayload_selValid_171) || _zz_s1_outputPayload_selValid_173) || _zz_s1_outputPayload_selValid_175) || _zz_s1_outputPayload_selValid_177) || _zz_s1_outputPayload_selValid_179); + assign _zz_s1_outputPayload_sel_11_1 = (((((((_zz_s1_outputPayload_selValid_166 || _zz_s1_outputPayload_selValid_167) || _zz_s1_outputPayload_selValid_170) || _zz_s1_outputPayload_selValid_171) || _zz_s1_outputPayload_selValid_174) || _zz_s1_outputPayload_selValid_175) || _zz_s1_outputPayload_selValid_178) || _zz_s1_outputPayload_selValid_179); + assign _zz_s1_outputPayload_sel_11_2 = (((((((_zz_s1_outputPayload_selValid_168 || _zz_s1_outputPayload_selValid_169) || _zz_s1_outputPayload_selValid_170) || _zz_s1_outputPayload_selValid_171) || _zz_s1_outputPayload_selValid_176) || _zz_s1_outputPayload_selValid_177) || _zz_s1_outputPayload_selValid_178) || _zz_s1_outputPayload_selValid_179); + assign _zz_s1_outputPayload_sel_11_3 = (((((((_zz_s1_outputPayload_selValid_172 || _zz_s1_outputPayload_selValid_173) || _zz_s1_outputPayload_selValid_174) || _zz_s1_outputPayload_selValid_175) || _zz_s1_outputPayload_selValid_176) || _zz_s1_outputPayload_selValid_177) || _zz_s1_outputPayload_selValid_178) || _zz_s1_outputPayload_selValid_179); + assign s1_outputPayload_sel_11 = {_zz_s1_outputPayload_sel_11_3,{_zz_s1_outputPayload_sel_11_2,{_zz_s1_outputPayload_sel_11_1,_zz_s1_outputPayload_sel_11}}}; + assign _zz_s1_outputPayload_selValid_180 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_181 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_182 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_183 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_184 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_185 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_186 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_187 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_188 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_189 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_190 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_191 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_192 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_193 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_194 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1100)); + assign _zz_s1_outputPayload_sel_12 = (((((((_zz_s1_outputPayload_selValid_180 || _zz_s1_outputPayload_selValid_182) || _zz_s1_outputPayload_selValid_184) || _zz_s1_outputPayload_selValid_186) || _zz_s1_outputPayload_selValid_188) || _zz_s1_outputPayload_selValid_190) || _zz_s1_outputPayload_selValid_192) || _zz_s1_outputPayload_selValid_194); + assign _zz_s1_outputPayload_sel_12_1 = (((((((_zz_s1_outputPayload_selValid_181 || _zz_s1_outputPayload_selValid_182) || _zz_s1_outputPayload_selValid_185) || _zz_s1_outputPayload_selValid_186) || _zz_s1_outputPayload_selValid_189) || _zz_s1_outputPayload_selValid_190) || _zz_s1_outputPayload_selValid_193) || _zz_s1_outputPayload_selValid_194); + assign _zz_s1_outputPayload_sel_12_2 = (((((((_zz_s1_outputPayload_selValid_183 || _zz_s1_outputPayload_selValid_184) || _zz_s1_outputPayload_selValid_185) || _zz_s1_outputPayload_selValid_186) || _zz_s1_outputPayload_selValid_191) || _zz_s1_outputPayload_selValid_192) || _zz_s1_outputPayload_selValid_193) || _zz_s1_outputPayload_selValid_194); + assign _zz_s1_outputPayload_sel_12_3 = (((((((_zz_s1_outputPayload_selValid_187 || _zz_s1_outputPayload_selValid_188) || _zz_s1_outputPayload_selValid_189) || _zz_s1_outputPayload_selValid_190) || _zz_s1_outputPayload_selValid_191) || _zz_s1_outputPayload_selValid_192) || _zz_s1_outputPayload_selValid_193) || _zz_s1_outputPayload_selValid_194); + assign s1_outputPayload_sel_12 = {_zz_s1_outputPayload_sel_12_3,{_zz_s1_outputPayload_sel_12_2,{_zz_s1_outputPayload_sel_12_1,_zz_s1_outputPayload_sel_12}}}; + assign _zz_s1_outputPayload_selValid_195 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_196 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_197 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_198 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_199 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_200 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_201 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_202 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_203 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_204 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_205 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_206 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_207 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_208 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_209 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1101)); + assign _zz_s1_outputPayload_sel_13 = (((((((_zz_s1_outputPayload_selValid_195 || _zz_s1_outputPayload_selValid_197) || _zz_s1_outputPayload_selValid_199) || _zz_s1_outputPayload_selValid_201) || _zz_s1_outputPayload_selValid_203) || _zz_s1_outputPayload_selValid_205) || _zz_s1_outputPayload_selValid_207) || _zz_s1_outputPayload_selValid_209); + assign _zz_s1_outputPayload_sel_13_1 = (((((((_zz_s1_outputPayload_selValid_196 || _zz_s1_outputPayload_selValid_197) || _zz_s1_outputPayload_selValid_200) || _zz_s1_outputPayload_selValid_201) || _zz_s1_outputPayload_selValid_204) || _zz_s1_outputPayload_selValid_205) || _zz_s1_outputPayload_selValid_208) || _zz_s1_outputPayload_selValid_209); + assign _zz_s1_outputPayload_sel_13_2 = (((((((_zz_s1_outputPayload_selValid_198 || _zz_s1_outputPayload_selValid_199) || _zz_s1_outputPayload_selValid_200) || _zz_s1_outputPayload_selValid_201) || _zz_s1_outputPayload_selValid_206) || _zz_s1_outputPayload_selValid_207) || _zz_s1_outputPayload_selValid_208) || _zz_s1_outputPayload_selValid_209); + assign _zz_s1_outputPayload_sel_13_3 = (((((((_zz_s1_outputPayload_selValid_202 || _zz_s1_outputPayload_selValid_203) || _zz_s1_outputPayload_selValid_204) || _zz_s1_outputPayload_selValid_205) || _zz_s1_outputPayload_selValid_206) || _zz_s1_outputPayload_selValid_207) || _zz_s1_outputPayload_selValid_208) || _zz_s1_outputPayload_selValid_209); + assign s1_outputPayload_sel_13 = {_zz_s1_outputPayload_sel_13_3,{_zz_s1_outputPayload_sel_13_2,{_zz_s1_outputPayload_sel_13_1,_zz_s1_outputPayload_sel_13}}}; + assign _zz_s1_outputPayload_selValid_210 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_211 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_212 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_213 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_214 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_215 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_216 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_217 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_218 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_219 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_220 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_221 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_222 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_223 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_224 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1110)); + assign _zz_s1_outputPayload_sel_14 = (((((((_zz_s1_outputPayload_selValid_210 || _zz_s1_outputPayload_selValid_212) || _zz_s1_outputPayload_selValid_214) || _zz_s1_outputPayload_selValid_216) || _zz_s1_outputPayload_selValid_218) || _zz_s1_outputPayload_selValid_220) || _zz_s1_outputPayload_selValid_222) || _zz_s1_outputPayload_selValid_224); + assign _zz_s1_outputPayload_sel_14_1 = (((((((_zz_s1_outputPayload_selValid_211 || _zz_s1_outputPayload_selValid_212) || _zz_s1_outputPayload_selValid_215) || _zz_s1_outputPayload_selValid_216) || _zz_s1_outputPayload_selValid_219) || _zz_s1_outputPayload_selValid_220) || _zz_s1_outputPayload_selValid_223) || _zz_s1_outputPayload_selValid_224); + assign _zz_s1_outputPayload_sel_14_2 = (((((((_zz_s1_outputPayload_selValid_213 || _zz_s1_outputPayload_selValid_214) || _zz_s1_outputPayload_selValid_215) || _zz_s1_outputPayload_selValid_216) || _zz_s1_outputPayload_selValid_221) || _zz_s1_outputPayload_selValid_222) || _zz_s1_outputPayload_selValid_223) || _zz_s1_outputPayload_selValid_224); + assign _zz_s1_outputPayload_sel_14_3 = (((((((_zz_s1_outputPayload_selValid_217 || _zz_s1_outputPayload_selValid_218) || _zz_s1_outputPayload_selValid_219) || _zz_s1_outputPayload_selValid_220) || _zz_s1_outputPayload_selValid_221) || _zz_s1_outputPayload_selValid_222) || _zz_s1_outputPayload_selValid_223) || _zz_s1_outputPayload_selValid_224); + assign s1_outputPayload_sel_14 = {_zz_s1_outputPayload_sel_14_3,{_zz_s1_outputPayload_sel_14_2,{_zz_s1_outputPayload_sel_14_1,_zz_s1_outputPayload_sel_14}}}; + assign _zz_s1_outputPayload_selValid_225 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_226 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_227 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_228 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_229 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_230 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_231 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_232 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_233 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_234 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_235 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_236 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_237 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_238 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_239 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1111)); + assign _zz_s1_outputPayload_sel_15 = (((((((_zz_s1_outputPayload_selValid_225 || _zz_s1_outputPayload_selValid_227) || _zz_s1_outputPayload_selValid_229) || _zz_s1_outputPayload_selValid_231) || _zz_s1_outputPayload_selValid_233) || _zz_s1_outputPayload_selValid_235) || _zz_s1_outputPayload_selValid_237) || _zz_s1_outputPayload_selValid_239); + assign _zz_s1_outputPayload_sel_15_1 = (((((((_zz_s1_outputPayload_selValid_226 || _zz_s1_outputPayload_selValid_227) || _zz_s1_outputPayload_selValid_230) || _zz_s1_outputPayload_selValid_231) || _zz_s1_outputPayload_selValid_234) || _zz_s1_outputPayload_selValid_235) || _zz_s1_outputPayload_selValid_238) || _zz_s1_outputPayload_selValid_239); + assign _zz_s1_outputPayload_sel_15_2 = (((((((_zz_s1_outputPayload_selValid_228 || _zz_s1_outputPayload_selValid_229) || _zz_s1_outputPayload_selValid_230) || _zz_s1_outputPayload_selValid_231) || _zz_s1_outputPayload_selValid_236) || _zz_s1_outputPayload_selValid_237) || _zz_s1_outputPayload_selValid_238) || _zz_s1_outputPayload_selValid_239); + assign _zz_s1_outputPayload_sel_15_3 = (((((((_zz_s1_outputPayload_selValid_232 || _zz_s1_outputPayload_selValid_233) || _zz_s1_outputPayload_selValid_234) || _zz_s1_outputPayload_selValid_235) || _zz_s1_outputPayload_selValid_236) || _zz_s1_outputPayload_selValid_237) || _zz_s1_outputPayload_selValid_238) || _zz_s1_outputPayload_selValid_239); + assign s1_outputPayload_sel_15 = {_zz_s1_outputPayload_sel_15_3,{_zz_s1_outputPayload_sel_15_2,{_zz_s1_outputPayload_sel_15_1,_zz_s1_outputPayload_sel_15}}}; + assign s1_output_valid = s1_input_valid; + assign s1_input_ready = s1_output_ready; + assign s1_output_payload_cmd_data = s1_outputPayload_cmd_data; + assign s1_output_payload_cmd_mask = s1_outputPayload_cmd_mask; + assign s1_output_payload_index_0 = s1_outputPayload_index_0; + assign s1_output_payload_index_1 = s1_outputPayload_index_1; + assign s1_output_payload_index_2 = s1_outputPayload_index_2; + assign s1_output_payload_index_3 = s1_outputPayload_index_3; + assign s1_output_payload_index_4 = s1_outputPayload_index_4; + assign s1_output_payload_index_5 = s1_outputPayload_index_5; + assign s1_output_payload_index_6 = s1_outputPayload_index_6; + assign s1_output_payload_index_7 = s1_outputPayload_index_7; + assign s1_output_payload_index_8 = s1_outputPayload_index_8; + assign s1_output_payload_index_9 = s1_outputPayload_index_9; + assign s1_output_payload_index_10 = s1_outputPayload_index_10; + assign s1_output_payload_index_11 = s1_outputPayload_index_11; + assign s1_output_payload_index_12 = s1_outputPayload_index_12; + assign s1_output_payload_index_13 = s1_outputPayload_index_13; + assign s1_output_payload_index_14 = s1_outputPayload_index_14; + assign s1_output_payload_index_15 = s1_outputPayload_index_15; + assign s1_output_payload_last = s1_outputPayload_last; + assign s1_output_payload_sel_0 = s1_outputPayload_sel_0; + assign s1_output_payload_sel_1 = s1_outputPayload_sel_1; + assign s1_output_payload_sel_2 = s1_outputPayload_sel_2; + assign s1_output_payload_sel_3 = s1_outputPayload_sel_3; + assign s1_output_payload_sel_4 = s1_outputPayload_sel_4; + assign s1_output_payload_sel_5 = s1_outputPayload_sel_5; + assign s1_output_payload_sel_6 = s1_outputPayload_sel_6; + assign s1_output_payload_sel_7 = s1_outputPayload_sel_7; + assign s1_output_payload_sel_8 = s1_outputPayload_sel_8; + assign s1_output_payload_sel_9 = s1_outputPayload_sel_9; + assign s1_output_payload_sel_10 = s1_outputPayload_sel_10; + assign s1_output_payload_sel_11 = s1_outputPayload_sel_11; + assign s1_output_payload_sel_12 = s1_outputPayload_sel_12; + assign s1_output_payload_sel_13 = s1_outputPayload_sel_13; + assign s1_output_payload_sel_14 = s1_outputPayload_sel_14; + assign s1_output_payload_sel_15 = s1_outputPayload_sel_15; + assign s1_output_payload_selValid = s1_outputPayload_selValid; + always @(*) begin + s1_output_ready = s2_input_ready; + if(when_Stream_l375_2) begin + s1_output_ready = 1'b1; + end + end + + assign when_Stream_l375_2 = (! s2_input_valid); + assign s2_input_valid = s1_output_rValid; + assign s2_input_payload_cmd_data = s1_output_rData_cmd_data; + assign s2_input_payload_cmd_mask = s1_output_rData_cmd_mask; + assign s2_input_payload_index_0 = s1_output_rData_index_0; + assign s2_input_payload_index_1 = s1_output_rData_index_1; + assign s2_input_payload_index_2 = s1_output_rData_index_2; + assign s2_input_payload_index_3 = s1_output_rData_index_3; + assign s2_input_payload_index_4 = s1_output_rData_index_4; + assign s2_input_payload_index_5 = s1_output_rData_index_5; + assign s2_input_payload_index_6 = s1_output_rData_index_6; + assign s2_input_payload_index_7 = s1_output_rData_index_7; + assign s2_input_payload_index_8 = s1_output_rData_index_8; + assign s2_input_payload_index_9 = s1_output_rData_index_9; + assign s2_input_payload_index_10 = s1_output_rData_index_10; + assign s2_input_payload_index_11 = s1_output_rData_index_11; + assign s2_input_payload_index_12 = s1_output_rData_index_12; + assign s2_input_payload_index_13 = s1_output_rData_index_13; + assign s2_input_payload_index_14 = s1_output_rData_index_14; + assign s2_input_payload_index_15 = s1_output_rData_index_15; + assign s2_input_payload_last = s1_output_rData_last; + assign s2_input_payload_sel_0 = s1_output_rData_sel_0; + assign s2_input_payload_sel_1 = s1_output_rData_sel_1; + assign s2_input_payload_sel_2 = s1_output_rData_sel_2; + assign s2_input_payload_sel_3 = s1_output_rData_sel_3; + assign s2_input_payload_sel_4 = s1_output_rData_sel_4; + assign s2_input_payload_sel_5 = s1_output_rData_sel_5; + assign s2_input_payload_sel_6 = s1_output_rData_sel_6; + assign s2_input_payload_sel_7 = s1_output_rData_sel_7; + assign s2_input_payload_sel_8 = s1_output_rData_sel_8; + assign s2_input_payload_sel_9 = s1_output_rData_sel_9; + assign s2_input_payload_sel_10 = s1_output_rData_sel_10; + assign s2_input_payload_sel_11 = s1_output_rData_sel_11; + assign s2_input_payload_sel_12 = s1_output_rData_sel_12; + assign s2_input_payload_sel_13 = s1_output_rData_sel_13; + assign s2_input_payload_sel_14 = s1_output_rData_sel_14; + assign s2_input_payload_sel_15 = s1_output_rData_sel_15; + assign s2_input_payload_selValid = s1_output_rData_selValid; + always @(*) begin + s2_input_ready = ((! io_output_enough) || io_output_consume); + if(when_DmaSg_l1464) begin + s2_input_ready = 1'b0; + end + end + + assign when_DmaSg_l1464 = (_zz_when_DmaSg_l1464 < s1_byteCounter); + assign s2_input_fire = (s2_input_valid && s2_input_ready); + assign io_output_consumed = s2_input_fire; + assign s2_inputDataBytes_0 = s2_input_payload_cmd_data[7 : 0]; + assign s2_inputDataBytes_1 = s2_input_payload_cmd_data[15 : 8]; + assign s2_inputDataBytes_2 = s2_input_payload_cmd_data[23 : 16]; + assign s2_inputDataBytes_3 = s2_input_payload_cmd_data[31 : 24]; + assign s2_inputDataBytes_4 = s2_input_payload_cmd_data[39 : 32]; + assign s2_inputDataBytes_5 = s2_input_payload_cmd_data[47 : 40]; + assign s2_inputDataBytes_6 = s2_input_payload_cmd_data[55 : 48]; + assign s2_inputDataBytes_7 = s2_input_payload_cmd_data[63 : 56]; + assign s2_inputDataBytes_8 = s2_input_payload_cmd_data[71 : 64]; + assign s2_inputDataBytes_9 = s2_input_payload_cmd_data[79 : 72]; + assign s2_inputDataBytes_10 = s2_input_payload_cmd_data[87 : 80]; + assign s2_inputDataBytes_11 = s2_input_payload_cmd_data[95 : 88]; + assign s2_inputDataBytes_12 = s2_input_payload_cmd_data[103 : 96]; + assign s2_inputDataBytes_13 = s2_input_payload_cmd_data[111 : 104]; + assign s2_inputDataBytes_14 = s2_input_payload_cmd_data[119 : 112]; + assign s2_inputDataBytes_15 = s2_input_payload_cmd_data[127 : 120]; + assign s2_byteLogic_0_lastUsed = (4'b0000 == io_output_lastByteUsed); + assign s2_byteLogic_0_inputMask = s2_input_payload_selValid[0]; + assign s2_byteLogic_0_inputData = _zz_s2_byteLogic_0_inputData; + assign s2_byteLogic_0_outputMask = (s2_byteLogic_0_buffer_valid || (s2_input_valid && s2_byteLogic_0_inputMask)); + assign s2_byteLogic_0_outputData = (s2_byteLogic_0_buffer_valid ? s2_byteLogic_0_buffer_data : s2_byteLogic_0_inputData); + always @(*) begin + io_output_mask[0] = s2_byteLogic_0_outputMask; + io_output_mask[1] = s2_byteLogic_1_outputMask; + io_output_mask[2] = s2_byteLogic_2_outputMask; + io_output_mask[3] = s2_byteLogic_3_outputMask; + io_output_mask[4] = s2_byteLogic_4_outputMask; + io_output_mask[5] = s2_byteLogic_5_outputMask; + io_output_mask[6] = s2_byteLogic_6_outputMask; + io_output_mask[7] = s2_byteLogic_7_outputMask; + io_output_mask[8] = s2_byteLogic_8_outputMask; + io_output_mask[9] = s2_byteLogic_9_outputMask; + io_output_mask[10] = s2_byteLogic_10_outputMask; + io_output_mask[11] = s2_byteLogic_11_outputMask; + io_output_mask[12] = s2_byteLogic_12_outputMask; + io_output_mask[13] = s2_byteLogic_13_outputMask; + io_output_mask[14] = s2_byteLogic_14_outputMask; + io_output_mask[15] = s2_byteLogic_15_outputMask; + end + + always @(*) begin + io_output_data[7 : 0] = s2_byteLogic_0_outputData; + io_output_data[15 : 8] = s2_byteLogic_1_outputData; + io_output_data[23 : 16] = s2_byteLogic_2_outputData; + io_output_data[31 : 24] = s2_byteLogic_3_outputData; + io_output_data[39 : 32] = s2_byteLogic_4_outputData; + io_output_data[47 : 40] = s2_byteLogic_5_outputData; + io_output_data[55 : 48] = s2_byteLogic_6_outputData; + io_output_data[63 : 56] = s2_byteLogic_7_outputData; + io_output_data[71 : 64] = s2_byteLogic_8_outputData; + io_output_data[79 : 72] = s2_byteLogic_9_outputData; + io_output_data[87 : 80] = s2_byteLogic_10_outputData; + io_output_data[95 : 88] = s2_byteLogic_11_outputData; + io_output_data[103 : 96] = s2_byteLogic_12_outputData; + io_output_data[111 : 104] = s2_byteLogic_13_outputData; + io_output_data[119 : 112] = s2_byteLogic_14_outputData; + io_output_data[127 : 120] = s2_byteLogic_15_outputData; + end + + assign when_DmaSg_l1493 = (s2_byteLogic_0_inputMask && ((! io_output_consume) || s2_byteLogic_0_buffer_valid)); + assign s2_byteLogic_1_lastUsed = (4'b0001 == io_output_lastByteUsed); + assign s2_byteLogic_1_inputMask = s2_input_payload_selValid[1]; + assign s2_byteLogic_1_inputData = _zz_s2_byteLogic_1_inputData; + assign s2_byteLogic_1_outputMask = (s2_byteLogic_1_buffer_valid || (s2_input_valid && s2_byteLogic_1_inputMask)); + assign s2_byteLogic_1_outputData = (s2_byteLogic_1_buffer_valid ? s2_byteLogic_1_buffer_data : s2_byteLogic_1_inputData); + assign when_DmaSg_l1493_1 = (s2_byteLogic_1_inputMask && ((! io_output_consume) || s2_byteLogic_1_buffer_valid)); + assign s2_byteLogic_2_lastUsed = (4'b0010 == io_output_lastByteUsed); + assign s2_byteLogic_2_inputMask = s2_input_payload_selValid[2]; + assign s2_byteLogic_2_inputData = _zz_s2_byteLogic_2_inputData; + assign s2_byteLogic_2_outputMask = (s2_byteLogic_2_buffer_valid || (s2_input_valid && s2_byteLogic_2_inputMask)); + assign s2_byteLogic_2_outputData = (s2_byteLogic_2_buffer_valid ? s2_byteLogic_2_buffer_data : s2_byteLogic_2_inputData); + assign when_DmaSg_l1493_2 = (s2_byteLogic_2_inputMask && ((! io_output_consume) || s2_byteLogic_2_buffer_valid)); + assign s2_byteLogic_3_lastUsed = (4'b0011 == io_output_lastByteUsed); + assign s2_byteLogic_3_inputMask = s2_input_payload_selValid[3]; + assign s2_byteLogic_3_inputData = _zz_s2_byteLogic_3_inputData; + assign s2_byteLogic_3_outputMask = (s2_byteLogic_3_buffer_valid || (s2_input_valid && s2_byteLogic_3_inputMask)); + assign s2_byteLogic_3_outputData = (s2_byteLogic_3_buffer_valid ? s2_byteLogic_3_buffer_data : s2_byteLogic_3_inputData); + assign when_DmaSg_l1493_3 = (s2_byteLogic_3_inputMask && ((! io_output_consume) || s2_byteLogic_3_buffer_valid)); + assign s2_byteLogic_4_lastUsed = (4'b0100 == io_output_lastByteUsed); + assign s2_byteLogic_4_inputMask = s2_input_payload_selValid[4]; + assign s2_byteLogic_4_inputData = _zz_s2_byteLogic_4_inputData; + assign s2_byteLogic_4_outputMask = (s2_byteLogic_4_buffer_valid || (s2_input_valid && s2_byteLogic_4_inputMask)); + assign s2_byteLogic_4_outputData = (s2_byteLogic_4_buffer_valid ? s2_byteLogic_4_buffer_data : s2_byteLogic_4_inputData); + assign when_DmaSg_l1493_4 = (s2_byteLogic_4_inputMask && ((! io_output_consume) || s2_byteLogic_4_buffer_valid)); + assign s2_byteLogic_5_lastUsed = (4'b0101 == io_output_lastByteUsed); + assign s2_byteLogic_5_inputMask = s2_input_payload_selValid[5]; + assign s2_byteLogic_5_inputData = _zz_s2_byteLogic_5_inputData; + assign s2_byteLogic_5_outputMask = (s2_byteLogic_5_buffer_valid || (s2_input_valid && s2_byteLogic_5_inputMask)); + assign s2_byteLogic_5_outputData = (s2_byteLogic_5_buffer_valid ? s2_byteLogic_5_buffer_data : s2_byteLogic_5_inputData); + assign when_DmaSg_l1493_5 = (s2_byteLogic_5_inputMask && ((! io_output_consume) || s2_byteLogic_5_buffer_valid)); + assign s2_byteLogic_6_lastUsed = (4'b0110 == io_output_lastByteUsed); + assign s2_byteLogic_6_inputMask = s2_input_payload_selValid[6]; + assign s2_byteLogic_6_inputData = _zz_s2_byteLogic_6_inputData; + assign s2_byteLogic_6_outputMask = (s2_byteLogic_6_buffer_valid || (s2_input_valid && s2_byteLogic_6_inputMask)); + assign s2_byteLogic_6_outputData = (s2_byteLogic_6_buffer_valid ? s2_byteLogic_6_buffer_data : s2_byteLogic_6_inputData); + assign when_DmaSg_l1493_6 = (s2_byteLogic_6_inputMask && ((! io_output_consume) || s2_byteLogic_6_buffer_valid)); + assign s2_byteLogic_7_lastUsed = (4'b0111 == io_output_lastByteUsed); + assign s2_byteLogic_7_inputMask = s2_input_payload_selValid[7]; + assign s2_byteLogic_7_inputData = _zz_s2_byteLogic_7_inputData; + assign s2_byteLogic_7_outputMask = (s2_byteLogic_7_buffer_valid || (s2_input_valid && s2_byteLogic_7_inputMask)); + assign s2_byteLogic_7_outputData = (s2_byteLogic_7_buffer_valid ? s2_byteLogic_7_buffer_data : s2_byteLogic_7_inputData); + assign when_DmaSg_l1493_7 = (s2_byteLogic_7_inputMask && ((! io_output_consume) || s2_byteLogic_7_buffer_valid)); + assign s2_byteLogic_8_lastUsed = (4'b1000 == io_output_lastByteUsed); + assign s2_byteLogic_8_inputMask = s2_input_payload_selValid[8]; + assign s2_byteLogic_8_inputData = _zz_s2_byteLogic_8_inputData; + assign s2_byteLogic_8_outputMask = (s2_byteLogic_8_buffer_valid || (s2_input_valid && s2_byteLogic_8_inputMask)); + assign s2_byteLogic_8_outputData = (s2_byteLogic_8_buffer_valid ? s2_byteLogic_8_buffer_data : s2_byteLogic_8_inputData); + assign when_DmaSg_l1493_8 = (s2_byteLogic_8_inputMask && ((! io_output_consume) || s2_byteLogic_8_buffer_valid)); + assign s2_byteLogic_9_lastUsed = (4'b1001 == io_output_lastByteUsed); + assign s2_byteLogic_9_inputMask = s2_input_payload_selValid[9]; + assign s2_byteLogic_9_inputData = _zz_s2_byteLogic_9_inputData; + assign s2_byteLogic_9_outputMask = (s2_byteLogic_9_buffer_valid || (s2_input_valid && s2_byteLogic_9_inputMask)); + assign s2_byteLogic_9_outputData = (s2_byteLogic_9_buffer_valid ? s2_byteLogic_9_buffer_data : s2_byteLogic_9_inputData); + assign when_DmaSg_l1493_9 = (s2_byteLogic_9_inputMask && ((! io_output_consume) || s2_byteLogic_9_buffer_valid)); + assign s2_byteLogic_10_lastUsed = (4'b1010 == io_output_lastByteUsed); + assign s2_byteLogic_10_inputMask = s2_input_payload_selValid[10]; + assign s2_byteLogic_10_inputData = _zz_s2_byteLogic_10_inputData; + assign s2_byteLogic_10_outputMask = (s2_byteLogic_10_buffer_valid || (s2_input_valid && s2_byteLogic_10_inputMask)); + assign s2_byteLogic_10_outputData = (s2_byteLogic_10_buffer_valid ? s2_byteLogic_10_buffer_data : s2_byteLogic_10_inputData); + assign when_DmaSg_l1493_10 = (s2_byteLogic_10_inputMask && ((! io_output_consume) || s2_byteLogic_10_buffer_valid)); + assign s2_byteLogic_11_lastUsed = (4'b1011 == io_output_lastByteUsed); + assign s2_byteLogic_11_inputMask = s2_input_payload_selValid[11]; + assign s2_byteLogic_11_inputData = _zz_s2_byteLogic_11_inputData; + assign s2_byteLogic_11_outputMask = (s2_byteLogic_11_buffer_valid || (s2_input_valid && s2_byteLogic_11_inputMask)); + assign s2_byteLogic_11_outputData = (s2_byteLogic_11_buffer_valid ? s2_byteLogic_11_buffer_data : s2_byteLogic_11_inputData); + assign when_DmaSg_l1493_11 = (s2_byteLogic_11_inputMask && ((! io_output_consume) || s2_byteLogic_11_buffer_valid)); + assign s2_byteLogic_12_lastUsed = (4'b1100 == io_output_lastByteUsed); + assign s2_byteLogic_12_inputMask = s2_input_payload_selValid[12]; + assign s2_byteLogic_12_inputData = _zz_s2_byteLogic_12_inputData; + assign s2_byteLogic_12_outputMask = (s2_byteLogic_12_buffer_valid || (s2_input_valid && s2_byteLogic_12_inputMask)); + assign s2_byteLogic_12_outputData = (s2_byteLogic_12_buffer_valid ? s2_byteLogic_12_buffer_data : s2_byteLogic_12_inputData); + assign when_DmaSg_l1493_12 = (s2_byteLogic_12_inputMask && ((! io_output_consume) || s2_byteLogic_12_buffer_valid)); + assign s2_byteLogic_13_lastUsed = (4'b1101 == io_output_lastByteUsed); + assign s2_byteLogic_13_inputMask = s2_input_payload_selValid[13]; + assign s2_byteLogic_13_inputData = _zz_s2_byteLogic_13_inputData; + assign s2_byteLogic_13_outputMask = (s2_byteLogic_13_buffer_valid || (s2_input_valid && s2_byteLogic_13_inputMask)); + assign s2_byteLogic_13_outputData = (s2_byteLogic_13_buffer_valid ? s2_byteLogic_13_buffer_data : s2_byteLogic_13_inputData); + assign when_DmaSg_l1493_13 = (s2_byteLogic_13_inputMask && ((! io_output_consume) || s2_byteLogic_13_buffer_valid)); + assign s2_byteLogic_14_lastUsed = (4'b1110 == io_output_lastByteUsed); + assign s2_byteLogic_14_inputMask = s2_input_payload_selValid[14]; + assign s2_byteLogic_14_inputData = _zz_s2_byteLogic_14_inputData; + assign s2_byteLogic_14_outputMask = (s2_byteLogic_14_buffer_valid || (s2_input_valid && s2_byteLogic_14_inputMask)); + assign s2_byteLogic_14_outputData = (s2_byteLogic_14_buffer_valid ? s2_byteLogic_14_buffer_data : s2_byteLogic_14_inputData); + assign when_DmaSg_l1493_14 = (s2_byteLogic_14_inputMask && ((! io_output_consume) || s2_byteLogic_14_buffer_valid)); + assign s2_byteLogic_15_lastUsed = (4'b1111 == io_output_lastByteUsed); + assign s2_byteLogic_15_inputMask = s2_input_payload_selValid[15]; + assign s2_byteLogic_15_inputData = _zz_s2_byteLogic_15_inputData; + assign s2_byteLogic_15_outputMask = (s2_byteLogic_15_buffer_valid || (s2_input_valid && s2_byteLogic_15_inputMask)); + assign s2_byteLogic_15_outputData = (s2_byteLogic_15_buffer_valid ? s2_byteLogic_15_buffer_data : s2_byteLogic_15_inputData); + assign when_DmaSg_l1493_15 = (s2_byteLogic_15_inputMask && ((! io_output_consume) || s2_byteLogic_15_buffer_valid)); + assign _zz_io_output_usedUntil = (((((((s2_byteLogic_1_lastUsed || s2_byteLogic_3_lastUsed) || s2_byteLogic_5_lastUsed) || s2_byteLogic_7_lastUsed) || s2_byteLogic_9_lastUsed) || s2_byteLogic_11_lastUsed) || s2_byteLogic_13_lastUsed) || s2_byteLogic_15_lastUsed); + assign _zz_io_output_usedUntil_1 = (((((((s2_byteLogic_2_lastUsed || s2_byteLogic_3_lastUsed) || s2_byteLogic_6_lastUsed) || s2_byteLogic_7_lastUsed) || s2_byteLogic_10_lastUsed) || s2_byteLogic_11_lastUsed) || s2_byteLogic_14_lastUsed) || s2_byteLogic_15_lastUsed); + assign _zz_io_output_usedUntil_2 = (((((((s2_byteLogic_4_lastUsed || s2_byteLogic_5_lastUsed) || s2_byteLogic_6_lastUsed) || s2_byteLogic_7_lastUsed) || s2_byteLogic_12_lastUsed) || s2_byteLogic_13_lastUsed) || s2_byteLogic_14_lastUsed) || s2_byteLogic_15_lastUsed); + assign _zz_io_output_usedUntil_3 = (((((((s2_byteLogic_8_lastUsed || s2_byteLogic_9_lastUsed) || s2_byteLogic_10_lastUsed) || s2_byteLogic_11_lastUsed) || s2_byteLogic_12_lastUsed) || s2_byteLogic_13_lastUsed) || s2_byteLogic_14_lastUsed) || s2_byteLogic_15_lastUsed); + assign io_output_usedUntil = _zz_io_output_usedUntil_4; + always @(posedge clk) begin + if(reset) begin + io_input_rValid <= 1'b0; + s0_output_rValid <= 1'b0; + s1_output_rValid <= 1'b0; + end else begin + if(io_input_ready) begin + io_input_rValid <= io_input_valid; + end + if(io_flush) begin + io_input_rValid <= 1'b0; + end + if(s0_output_ready) begin + s0_output_rValid <= s0_output_valid; + end + if(io_flush) begin + s0_output_rValid <= 1'b0; + end + if(s1_output_ready) begin + s1_output_rValid <= s1_output_valid; + end + if(io_flush) begin + s1_output_rValid <= 1'b0; + end + end + end + + always @(posedge clk) begin + if(io_input_ready) begin + io_input_rData_data <= io_input_payload_data; + io_input_rData_mask <= io_input_payload_mask; + end + if(s0_output_ready) begin + s0_output_rData_cmd_data <= s0_output_payload_cmd_data; + s0_output_rData_cmd_mask <= s0_output_payload_cmd_mask; + s0_output_rData_countOnes_0 <= s0_output_payload_countOnes_0; + s0_output_rData_countOnes_1 <= s0_output_payload_countOnes_1; + s0_output_rData_countOnes_2 <= s0_output_payload_countOnes_2; + s0_output_rData_countOnes_3 <= s0_output_payload_countOnes_3; + s0_output_rData_countOnes_4 <= s0_output_payload_countOnes_4; + s0_output_rData_countOnes_5 <= s0_output_payload_countOnes_5; + s0_output_rData_countOnes_6 <= s0_output_payload_countOnes_6; + s0_output_rData_countOnes_7 <= s0_output_payload_countOnes_7; + s0_output_rData_countOnes_8 <= s0_output_payload_countOnes_8; + s0_output_rData_countOnes_9 <= s0_output_payload_countOnes_9; + s0_output_rData_countOnes_10 <= s0_output_payload_countOnes_10; + s0_output_rData_countOnes_11 <= s0_output_payload_countOnes_11; + s0_output_rData_countOnes_12 <= s0_output_payload_countOnes_12; + s0_output_rData_countOnes_13 <= s0_output_payload_countOnes_13; + s0_output_rData_countOnes_14 <= s0_output_payload_countOnes_14; + s0_output_rData_countOnes_15 <= s0_output_payload_countOnes_15; + end + if(s1_input_fire) begin + s1_offset <= s1_offsetNext[3:0]; + end + if(io_flush) begin + s1_offset <= io_offset; + end + if(s1_input_fire) begin + s1_byteCounter <= (s1_byteCounter + _zz_s1_byteCounter); + end + if(io_flush) begin + s1_byteCounter <= 13'h0; + end + if(s1_output_ready) begin + s1_output_rData_cmd_data <= s1_output_payload_cmd_data; + s1_output_rData_cmd_mask <= s1_output_payload_cmd_mask; + s1_output_rData_index_0 <= s1_output_payload_index_0; + s1_output_rData_index_1 <= s1_output_payload_index_1; + s1_output_rData_index_2 <= s1_output_payload_index_2; + s1_output_rData_index_3 <= s1_output_payload_index_3; + s1_output_rData_index_4 <= s1_output_payload_index_4; + s1_output_rData_index_5 <= s1_output_payload_index_5; + s1_output_rData_index_6 <= s1_output_payload_index_6; + s1_output_rData_index_7 <= s1_output_payload_index_7; + s1_output_rData_index_8 <= s1_output_payload_index_8; + s1_output_rData_index_9 <= s1_output_payload_index_9; + s1_output_rData_index_10 <= s1_output_payload_index_10; + s1_output_rData_index_11 <= s1_output_payload_index_11; + s1_output_rData_index_12 <= s1_output_payload_index_12; + s1_output_rData_index_13 <= s1_output_payload_index_13; + s1_output_rData_index_14 <= s1_output_payload_index_14; + s1_output_rData_index_15 <= s1_output_payload_index_15; + s1_output_rData_last <= s1_output_payload_last; + s1_output_rData_sel_0 <= s1_output_payload_sel_0; + s1_output_rData_sel_1 <= s1_output_payload_sel_1; + s1_output_rData_sel_2 <= s1_output_payload_sel_2; + s1_output_rData_sel_3 <= s1_output_payload_sel_3; + s1_output_rData_sel_4 <= s1_output_payload_sel_4; + s1_output_rData_sel_5 <= s1_output_payload_sel_5; + s1_output_rData_sel_6 <= s1_output_payload_sel_6; + s1_output_rData_sel_7 <= s1_output_payload_sel_7; + s1_output_rData_sel_8 <= s1_output_payload_sel_8; + s1_output_rData_sel_9 <= s1_output_payload_sel_9; + s1_output_rData_sel_10 <= s1_output_payload_sel_10; + s1_output_rData_sel_11 <= s1_output_payload_sel_11; + s1_output_rData_sel_12 <= s1_output_payload_sel_12; + s1_output_rData_sel_13 <= s1_output_payload_sel_13; + s1_output_rData_sel_14 <= s1_output_payload_sel_14; + s1_output_rData_sel_15 <= s1_output_payload_sel_15; + s1_output_rData_selValid <= s1_output_payload_selValid; + end + if(io_output_consume) begin + s2_byteLogic_0_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_0_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493) begin + s2_byteLogic_0_buffer_valid <= 1'b1; + s2_byteLogic_0_buffer_data <= s2_byteLogic_0_inputData; + end + end + if(io_flush) begin + s2_byteLogic_0_buffer_valid <= (4'b0000 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_1_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_1_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_1) begin + s2_byteLogic_1_buffer_valid <= 1'b1; + s2_byteLogic_1_buffer_data <= s2_byteLogic_1_inputData; + end + end + if(io_flush) begin + s2_byteLogic_1_buffer_valid <= (4'b0001 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_2_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_2_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_2) begin + s2_byteLogic_2_buffer_valid <= 1'b1; + s2_byteLogic_2_buffer_data <= s2_byteLogic_2_inputData; + end + end + if(io_flush) begin + s2_byteLogic_2_buffer_valid <= (4'b0010 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_3_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_3_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_3) begin + s2_byteLogic_3_buffer_valid <= 1'b1; + s2_byteLogic_3_buffer_data <= s2_byteLogic_3_inputData; + end + end + if(io_flush) begin + s2_byteLogic_3_buffer_valid <= (4'b0011 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_4_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_4_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_4) begin + s2_byteLogic_4_buffer_valid <= 1'b1; + s2_byteLogic_4_buffer_data <= s2_byteLogic_4_inputData; + end + end + if(io_flush) begin + s2_byteLogic_4_buffer_valid <= (4'b0100 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_5_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_5_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_5) begin + s2_byteLogic_5_buffer_valid <= 1'b1; + s2_byteLogic_5_buffer_data <= s2_byteLogic_5_inputData; + end + end + if(io_flush) begin + s2_byteLogic_5_buffer_valid <= (4'b0101 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_6_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_6_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_6) begin + s2_byteLogic_6_buffer_valid <= 1'b1; + s2_byteLogic_6_buffer_data <= s2_byteLogic_6_inputData; + end + end + if(io_flush) begin + s2_byteLogic_6_buffer_valid <= (4'b0110 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_7_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_7_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_7) begin + s2_byteLogic_7_buffer_valid <= 1'b1; + s2_byteLogic_7_buffer_data <= s2_byteLogic_7_inputData; + end + end + if(io_flush) begin + s2_byteLogic_7_buffer_valid <= (4'b0111 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_8_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_8_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_8) begin + s2_byteLogic_8_buffer_valid <= 1'b1; + s2_byteLogic_8_buffer_data <= s2_byteLogic_8_inputData; + end + end + if(io_flush) begin + s2_byteLogic_8_buffer_valid <= (4'b1000 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_9_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_9_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_9) begin + s2_byteLogic_9_buffer_valid <= 1'b1; + s2_byteLogic_9_buffer_data <= s2_byteLogic_9_inputData; + end + end + if(io_flush) begin + s2_byteLogic_9_buffer_valid <= (4'b1001 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_10_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_10_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_10) begin + s2_byteLogic_10_buffer_valid <= 1'b1; + s2_byteLogic_10_buffer_data <= s2_byteLogic_10_inputData; + end + end + if(io_flush) begin + s2_byteLogic_10_buffer_valid <= (4'b1010 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_11_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_11_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_11) begin + s2_byteLogic_11_buffer_valid <= 1'b1; + s2_byteLogic_11_buffer_data <= s2_byteLogic_11_inputData; + end + end + if(io_flush) begin + s2_byteLogic_11_buffer_valid <= (4'b1011 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_12_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_12_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_12) begin + s2_byteLogic_12_buffer_valid <= 1'b1; + s2_byteLogic_12_buffer_data <= s2_byteLogic_12_inputData; + end + end + if(io_flush) begin + s2_byteLogic_12_buffer_valid <= (4'b1100 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_13_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_13_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_13) begin + s2_byteLogic_13_buffer_valid <= 1'b1; + s2_byteLogic_13_buffer_data <= s2_byteLogic_13_inputData; + end + end + if(io_flush) begin + s2_byteLogic_13_buffer_valid <= (4'b1101 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_14_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_14_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_14) begin + s2_byteLogic_14_buffer_valid <= 1'b1; + s2_byteLogic_14_buffer_data <= s2_byteLogic_14_inputData; + end + end + if(io_flush) begin + s2_byteLogic_14_buffer_valid <= (4'b1110 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_15_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_15_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_15) begin + s2_byteLogic_15_buffer_valid <= 1'b1; + s2_byteLogic_15_buffer_data <= s2_byteLogic_15_inputData; + end + end + if(io_flush) begin + s2_byteLogic_15_buffer_valid <= (4'b1111 < io_offset); + end + end + + +endmodule + +module EfxDMA_DmaMemoryCore_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_writes_0_cmd_valid, + output wire io_writes_0_cmd_ready, + input wire [9:0] io_writes_0_cmd_payload_address, + input wire [63:0] io_writes_0_cmd_payload_data, + input wire [7:0] io_writes_0_cmd_payload_mask, + input wire [1:0] io_writes_0_cmd_payload_priority, + input wire [6:0] io_writes_0_cmd_payload_context, + output wire io_writes_0_rsp_valid, + output wire [6:0] io_writes_0_rsp_payload_context, + input wire io_writes_1_cmd_valid, + output wire io_writes_1_cmd_ready, + input wire [9:0] io_writes_1_cmd_payload_address, + input wire [127:0] io_writes_1_cmd_payload_data, + input wire [15:0] io_writes_1_cmd_payload_mask, + input wire [6:0] io_writes_1_cmd_payload_context, + output wire io_writes_1_rsp_valid, + output wire [6:0] io_writes_1_rsp_payload_context, + input wire io_reads_0_cmd_valid, + output wire io_reads_0_cmd_ready, + input wire [9:0] io_reads_0_cmd_payload_address, + input wire [1:0] io_reads_0_cmd_payload_priority, + input wire [2:0] io_reads_0_cmd_payload_context, + output wire io_reads_0_rsp_valid, + input wire io_reads_0_rsp_ready, + output wire [63:0] io_reads_0_rsp_payload_data, + output wire [7:0] io_reads_0_rsp_payload_mask, + output wire [2:0] io_reads_0_rsp_payload_context, + input wire io_reads_1_cmd_valid, + output wire io_reads_1_cmd_ready, + input wire [9:0] io_reads_1_cmd_payload_address, + input wire [11:0] io_reads_1_cmd_payload_context, + output wire io_reads_1_rsp_valid, + input wire io_reads_1_rsp_ready, + output wire [127:0] io_reads_1_rsp_payload_data, + output wire [15:0] io_reads_1_rsp_payload_mask, + output wire [11:0] io_reads_1_rsp_payload_context, + input wire clk, + input wire reset +); + + reg [71:0] banks_0_ram_spinal_port1; + reg [71:0] banks_1_ram_spinal_port1; + wire [71:0] _zz_banks_0_ram_port; + wire [71:0] _zz_banks_1_ram_port; + wire [3:0] _zz_write_ports_0_priority_value; + wire [9:0] _zz_when_MemoryCore_l136; + wire [9:0] _zz_when_MemoryCore_l136_1; + reg [63:0] _zz_read_ports_0_buffer_bufferIn_payload_data; + reg [7:0] _zz_read_ports_0_buffer_bufferIn_payload_mask; + wire [3:0] _zz_read_ports_0_priority_value; + wire [9:0] _zz_when_MemoryCore_l221; + wire [9:0] _zz_when_MemoryCore_l221_1; + reg _zz_1; + reg _zz_2; + reg banks_0_write_valid; + reg [8:0] banks_0_write_payload_address; + reg [63:0] banks_0_write_payload_data_data; + reg [7:0] banks_0_write_payload_data_mask; + wire banks_0_read_cmd_valid; + wire [8:0] banks_0_read_cmd_payload; + wire [63:0] banks_0_read_rsp_data; + wire [7:0] banks_0_read_rsp_mask; + wire [71:0] _zz_banks_0_read_rsp_data; + wire banks_0_writeOr_value_valid; + wire [8:0] banks_0_writeOr_value_payload_address; + wire [63:0] banks_0_writeOr_value_payload_data_data; + wire [7:0] banks_0_writeOr_value_payload_data_mask; + wire banks_0_readOr_value_valid; + wire [8:0] banks_0_readOr_value_payload; + reg banks_1_write_valid; + reg [8:0] banks_1_write_payload_address; + reg [63:0] banks_1_write_payload_data_data; + reg [7:0] banks_1_write_payload_data_mask; + wire banks_1_read_cmd_valid; + wire [8:0] banks_1_read_cmd_payload; + wire [63:0] banks_1_read_rsp_data; + wire [7:0] banks_1_read_rsp_mask; + wire [71:0] _zz_banks_1_read_rsp_data; + wire banks_1_writeOr_value_valid; + wire [8:0] banks_1_writeOr_value_payload_address; + wire [63:0] banks_1_writeOr_value_payload_data_data; + wire [7:0] banks_1_writeOr_value_payload_data_mask; + wire banks_1_readOr_value_valid; + wire [8:0] banks_1_readOr_value_payload; + reg [3:0] write_ports_0_priority_value; + wire write_nodes_0_0_priority; + wire write_nodes_0_0_conflict; + wire write_nodes_0_1_priority; + wire write_nodes_0_1_conflict; + wire write_nodes_1_0_priority; + wire write_nodes_1_0_conflict; + wire write_nodes_1_1_priority; + wire write_nodes_1_1_conflict; + wire [0:0] write_arbiter_0_losedAgainst; + reg write_arbiter_0_doIt; + reg _zz_banks_0_writeOr_value_valid; + reg [8:0] _zz_banks_0_writeOr_value_valid_1; + reg [63:0] _zz_banks_0_writeOr_value_valid_2; + reg [7:0] _zz_banks_0_writeOr_value_valid_3; + wire when_MemoryCore_l136; + reg _zz_banks_1_writeOr_value_valid; + reg [8:0] _zz_banks_1_writeOr_value_valid_1; + reg [63:0] _zz_banks_1_writeOr_value_valid_2; + reg [7:0] _zz_banks_1_writeOr_value_valid_3; + wire when_MemoryCore_l136_1; + reg write_arbiter_0_doIt_regNext; + reg [6:0] io_writes_0_cmd_payload_context_regNext; + wire [0:0] write_arbiter_1_losedAgainst; + reg write_arbiter_1_doIt; + reg _zz_banks_0_writeOr_value_valid_4; + reg [8:0] _zz_banks_0_writeOr_value_valid_5; + reg [63:0] _zz_banks_0_writeOr_value_valid_6; + reg [7:0] _zz_banks_0_writeOr_value_valid_7; + wire when_MemoryCore_l136_2; + reg _zz_banks_1_writeOr_value_valid_4; + reg [8:0] _zz_banks_1_writeOr_value_valid_5; + reg [63:0] _zz_banks_1_writeOr_value_valid_6; + reg [7:0] _zz_banks_1_writeOr_value_valid_7; + wire when_MemoryCore_l136_3; + reg write_arbiter_1_doIt_regNext; + reg [6:0] io_writes_1_cmd_payload_context_regNext; + wire read_ports_0_buffer_s0_valid; + wire [2:0] read_ports_0_buffer_s0_payload_context; + wire [9:0] read_ports_0_buffer_s0_payload_address; + reg read_ports_0_buffer_s1_valid; + reg [2:0] read_ports_0_buffer_s1_payload_context; + reg [9:0] read_ports_0_buffer_s1_payload_address; + wire [0:0] read_ports_0_buffer_groupSel; + wire read_ports_0_buffer_bufferIn_valid; + wire read_ports_0_buffer_bufferIn_ready; + wire [63:0] read_ports_0_buffer_bufferIn_payload_data; + wire [7:0] read_ports_0_buffer_bufferIn_payload_mask; + wire [2:0] read_ports_0_buffer_bufferIn_payload_context; + wire read_ports_0_buffer_bufferOut_valid; + wire read_ports_0_buffer_bufferOut_ready; + wire [63:0] read_ports_0_buffer_bufferOut_payload_data; + wire [7:0] read_ports_0_buffer_bufferOut_payload_mask; + wire [2:0] read_ports_0_buffer_bufferOut_payload_context; + reg read_ports_0_buffer_bufferIn_rValidN; + reg [63:0] read_ports_0_buffer_bufferIn_rData_data; + reg [7:0] read_ports_0_buffer_bufferIn_rData_mask; + reg [2:0] read_ports_0_buffer_bufferIn_rData_context; + wire read_ports_0_buffer_full; + wire _zz_io_reads_0_cmd_ready; + wire read_ports_0_cmd_valid; + wire read_ports_0_cmd_ready; + wire [9:0] read_ports_0_cmd_payload_address; + wire [1:0] read_ports_0_cmd_payload_priority; + wire [2:0] read_ports_0_cmd_payload_context; + reg [3:0] read_ports_0_priority_value; + wire read_ports_1_buffer_s0_valid; + wire [11:0] read_ports_1_buffer_s0_payload_context; + wire [9:0] read_ports_1_buffer_s0_payload_address; + reg read_ports_1_buffer_s1_valid; + reg [11:0] read_ports_1_buffer_s1_payload_context; + reg [9:0] read_ports_1_buffer_s1_payload_address; + wire read_ports_1_buffer_bufferIn_valid; + wire read_ports_1_buffer_bufferIn_ready; + wire [127:0] read_ports_1_buffer_bufferIn_payload_data; + wire [15:0] read_ports_1_buffer_bufferIn_payload_mask; + wire [11:0] read_ports_1_buffer_bufferIn_payload_context; + wire read_ports_1_buffer_bufferOut_valid; + wire read_ports_1_buffer_bufferOut_ready; + wire [127:0] read_ports_1_buffer_bufferOut_payload_data; + wire [15:0] read_ports_1_buffer_bufferOut_payload_mask; + wire [11:0] read_ports_1_buffer_bufferOut_payload_context; + reg read_ports_1_buffer_bufferIn_rValidN; + reg [127:0] read_ports_1_buffer_bufferIn_rData_data; + reg [15:0] read_ports_1_buffer_bufferIn_rData_mask; + reg [11:0] read_ports_1_buffer_bufferIn_rData_context; + wire read_ports_1_buffer_full; + wire _zz_io_reads_1_cmd_ready; + wire read_ports_1_cmd_valid; + wire read_ports_1_cmd_ready; + wire [9:0] read_ports_1_cmd_payload_address; + wire [11:0] read_ports_1_cmd_payload_context; + wire read_nodes_0_0_priority; + wire read_nodes_0_0_conflict; + wire read_nodes_0_1_priority; + wire read_nodes_0_1_conflict; + wire read_nodes_1_0_priority; + wire read_nodes_1_0_conflict; + wire read_nodes_1_1_priority; + wire read_nodes_1_1_conflict; + wire [0:0] read_arbiter_0_losedAgainst; + wire read_arbiter_0_doIt; + reg _zz_banks_0_readOr_value_valid; + reg [8:0] _zz_banks_0_readOr_value_valid_1; + wire when_MemoryCore_l221; + reg _zz_banks_1_readOr_value_valid; + reg [8:0] _zz_banks_1_readOr_value_valid_1; + wire when_MemoryCore_l221_1; + wire [0:0] read_arbiter_1_losedAgainst; + wire read_arbiter_1_doIt; + reg _zz_banks_0_readOr_value_valid_2; + reg [8:0] _zz_banks_0_readOr_value_valid_3; + wire when_MemoryCore_l221_2; + reg _zz_banks_1_readOr_value_valid_2; + reg [8:0] _zz_banks_1_readOr_value_valid_3; + wire when_MemoryCore_l221_3; + reg [9:0] initialiser_counter; + wire initialiser_done; + wire when_MemoryCore_l239; + wire [71:0] _zz_banks_0_write_payload_data_data; + wire [71:0] _zz_banks_1_write_payload_data_data; + wire [81:0] _zz_banks_0_writeOr_value_valid_8; + wire [80:0] _zz_banks_0_writeOr_value_payload_address; + wire [71:0] _zz_banks_0_writeOr_value_payload_data_data; + wire [9:0] _zz_banks_0_readOr_value_valid_4; + wire [81:0] _zz_banks_1_writeOr_value_valid_8; + wire [80:0] _zz_banks_1_writeOr_value_payload_address; + wire [71:0] _zz_banks_1_writeOr_value_payload_data_data; + wire [9:0] _zz_banks_1_readOr_value_valid_4; + (* ram_style = "block" *) reg [71:0] banks_0_ram [0:511]; + (* ram_style = "block" *) reg [71:0] banks_1_ram [0:511]; + + assign _zz_write_ports_0_priority_value = {2'd0, io_writes_0_cmd_payload_priority}; + assign _zz_when_MemoryCore_l136 = (io_writes_0_cmd_payload_address ^ 10'h0); + assign _zz_when_MemoryCore_l136_1 = (io_writes_0_cmd_payload_address ^ 10'h001); + assign _zz_read_ports_0_priority_value = {2'd0, read_ports_0_cmd_payload_priority}; + assign _zz_when_MemoryCore_l221 = (read_ports_0_cmd_payload_address ^ 10'h0); + assign _zz_when_MemoryCore_l221_1 = (read_ports_0_cmd_payload_address ^ 10'h001); + assign _zz_banks_0_ram_port = {banks_0_write_payload_data_mask,banks_0_write_payload_data_data}; + assign _zz_banks_1_ram_port = {banks_1_write_payload_data_mask,banks_1_write_payload_data_data}; + always @(posedge clk) begin + if(_zz_2) begin + banks_0_ram[banks_0_write_payload_address] <= _zz_banks_0_ram_port; + end + end + + always @(posedge clk) begin + if(banks_0_read_cmd_valid) begin + banks_0_ram_spinal_port1 <= banks_0_ram[banks_0_read_cmd_payload]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin + banks_1_ram[banks_1_write_payload_address] <= _zz_banks_1_ram_port; + end + end + + always @(posedge clk) begin + if(banks_1_read_cmd_valid) begin + banks_1_ram_spinal_port1 <= banks_1_ram[banks_1_read_cmd_payload]; + end + end + + initial begin + `ifndef SYNTHESIS + write_ports_0_priority_value = {$urandom}; + read_ports_0_priority_value = {$urandom}; + `endif + end + + always @(*) begin + case(read_ports_0_buffer_groupSel) + 1'b0 : begin + _zz_read_ports_0_buffer_bufferIn_payload_data = banks_0_read_rsp_data; + _zz_read_ports_0_buffer_bufferIn_payload_mask = banks_0_read_rsp_mask; + end + default : begin + _zz_read_ports_0_buffer_bufferIn_payload_data = banks_1_read_rsp_data; + _zz_read_ports_0_buffer_bufferIn_payload_mask = banks_1_read_rsp_mask; + end + endcase + end + + always @(*) begin + _zz_1 = 1'b0; + if(banks_1_write_valid) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + _zz_2 = 1'b0; + if(banks_0_write_valid) begin + _zz_2 = 1'b1; + end + end + + assign _zz_banks_0_read_rsp_data = banks_0_ram_spinal_port1; + assign banks_0_read_rsp_data = _zz_banks_0_read_rsp_data[63 : 0]; + assign banks_0_read_rsp_mask = _zz_banks_0_read_rsp_data[71 : 64]; + always @(*) begin + banks_0_write_valid = banks_0_writeOr_value_valid; + if(when_MemoryCore_l239) begin + banks_0_write_valid = 1'b1; + end + end + + always @(*) begin + banks_0_write_payload_address = banks_0_writeOr_value_payload_address; + if(when_MemoryCore_l239) begin + banks_0_write_payload_address = initialiser_counter[8:0]; + end + end + + always @(*) begin + banks_0_write_payload_data_data = banks_0_writeOr_value_payload_data_data; + if(when_MemoryCore_l239) begin + banks_0_write_payload_data_data = _zz_banks_0_write_payload_data_data[63 : 0]; + end + end + + always @(*) begin + banks_0_write_payload_data_mask = banks_0_writeOr_value_payload_data_mask; + if(when_MemoryCore_l239) begin + banks_0_write_payload_data_mask = _zz_banks_0_write_payload_data_data[71 : 64]; + end + end + + assign banks_0_read_cmd_valid = banks_0_readOr_value_valid; + assign banks_0_read_cmd_payload = banks_0_readOr_value_payload; + assign _zz_banks_1_read_rsp_data = banks_1_ram_spinal_port1; + assign banks_1_read_rsp_data = _zz_banks_1_read_rsp_data[63 : 0]; + assign banks_1_read_rsp_mask = _zz_banks_1_read_rsp_data[71 : 64]; + always @(*) begin + banks_1_write_valid = banks_1_writeOr_value_valid; + if(when_MemoryCore_l239) begin + banks_1_write_valid = 1'b1; + end + end + + always @(*) begin + banks_1_write_payload_address = banks_1_writeOr_value_payload_address; + if(when_MemoryCore_l239) begin + banks_1_write_payload_address = initialiser_counter[8:0]; + end + end + + always @(*) begin + banks_1_write_payload_data_data = banks_1_writeOr_value_payload_data_data; + if(when_MemoryCore_l239) begin + banks_1_write_payload_data_data = _zz_banks_1_write_payload_data_data[63 : 0]; + end + end + + always @(*) begin + banks_1_write_payload_data_mask = banks_1_writeOr_value_payload_data_mask; + if(when_MemoryCore_l239) begin + banks_1_write_payload_data_mask = _zz_banks_1_write_payload_data_data[71 : 64]; + end + end + + assign banks_1_read_cmd_valid = banks_1_readOr_value_valid; + assign banks_1_read_cmd_payload = banks_1_readOr_value_payload; + assign write_nodes_0_1_priority = 1'b0; + assign write_nodes_1_0_priority = 1'b1; + assign write_nodes_0_1_conflict = ((io_writes_0_cmd_valid && io_writes_1_cmd_valid) && (((io_writes_0_cmd_payload_address ^ io_writes_1_cmd_payload_address) & 10'h0) == 10'h0)); + assign write_nodes_1_0_conflict = write_nodes_0_1_conflict; + assign write_arbiter_0_losedAgainst = (write_nodes_0_1_conflict && (! write_nodes_0_1_priority)); + always @(*) begin + write_arbiter_0_doIt = (io_writes_0_cmd_valid && (write_arbiter_0_losedAgainst == 1'b0)); + if(when_MemoryCore_l239) begin + write_arbiter_0_doIt = 1'b0; + end + end + + assign when_MemoryCore_l136 = (write_arbiter_0_doIt && (_zz_when_MemoryCore_l136[0 : 0] == 1'b0)); + always @(*) begin + if(when_MemoryCore_l136) begin + _zz_banks_0_writeOr_value_valid = 1'b1; + end else begin + _zz_banks_0_writeOr_value_valid = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l136) begin + _zz_banks_0_writeOr_value_valid_1 = (io_writes_0_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_0_writeOr_value_valid_1 = 9'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136) begin + _zz_banks_0_writeOr_value_valid_2 = io_writes_0_cmd_payload_data[63 : 0]; + end else begin + _zz_banks_0_writeOr_value_valid_2 = 64'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136) begin + _zz_banks_0_writeOr_value_valid_3 = io_writes_0_cmd_payload_mask[7 : 0]; + end else begin + _zz_banks_0_writeOr_value_valid_3 = 8'h0; + end + end + + assign when_MemoryCore_l136_1 = (write_arbiter_0_doIt && (_zz_when_MemoryCore_l136_1[0 : 0] == 1'b0)); + always @(*) begin + if(when_MemoryCore_l136_1) begin + _zz_banks_1_writeOr_value_valid = 1'b1; + end else begin + _zz_banks_1_writeOr_value_valid = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_1) begin + _zz_banks_1_writeOr_value_valid_1 = (io_writes_0_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_1_writeOr_value_valid_1 = 9'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_1) begin + _zz_banks_1_writeOr_value_valid_2 = io_writes_0_cmd_payload_data[63 : 0]; + end else begin + _zz_banks_1_writeOr_value_valid_2 = 64'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_1) begin + _zz_banks_1_writeOr_value_valid_3 = io_writes_0_cmd_payload_mask[7 : 0]; + end else begin + _zz_banks_1_writeOr_value_valid_3 = 8'h0; + end + end + + assign io_writes_0_cmd_ready = write_arbiter_0_doIt; + assign io_writes_0_rsp_valid = write_arbiter_0_doIt_regNext; + assign io_writes_0_rsp_payload_context = io_writes_0_cmd_payload_context_regNext; + assign write_arbiter_1_losedAgainst = (write_nodes_1_0_conflict && (! write_nodes_1_0_priority)); + always @(*) begin + write_arbiter_1_doIt = (io_writes_1_cmd_valid && (write_arbiter_1_losedAgainst == 1'b0)); + if(when_MemoryCore_l239) begin + write_arbiter_1_doIt = 1'b0; + end + end + + assign when_MemoryCore_l136_2 = (write_arbiter_1_doIt && 1'b1); + always @(*) begin + if(when_MemoryCore_l136_2) begin + _zz_banks_0_writeOr_value_valid_4 = 1'b1; + end else begin + _zz_banks_0_writeOr_value_valid_4 = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_2) begin + _zz_banks_0_writeOr_value_valid_5 = (io_writes_1_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_0_writeOr_value_valid_5 = 9'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_2) begin + _zz_banks_0_writeOr_value_valid_6 = io_writes_1_cmd_payload_data[63 : 0]; + end else begin + _zz_banks_0_writeOr_value_valid_6 = 64'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_2) begin + _zz_banks_0_writeOr_value_valid_7 = io_writes_1_cmd_payload_mask[7 : 0]; + end else begin + _zz_banks_0_writeOr_value_valid_7 = 8'h0; + end + end + + assign when_MemoryCore_l136_3 = (write_arbiter_1_doIt && 1'b1); + always @(*) begin + if(when_MemoryCore_l136_3) begin + _zz_banks_1_writeOr_value_valid_4 = 1'b1; + end else begin + _zz_banks_1_writeOr_value_valid_4 = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_3) begin + _zz_banks_1_writeOr_value_valid_5 = (io_writes_1_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_1_writeOr_value_valid_5 = 9'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_3) begin + _zz_banks_1_writeOr_value_valid_6 = io_writes_1_cmd_payload_data[127 : 64]; + end else begin + _zz_banks_1_writeOr_value_valid_6 = 64'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_3) begin + _zz_banks_1_writeOr_value_valid_7 = io_writes_1_cmd_payload_mask[15 : 8]; + end else begin + _zz_banks_1_writeOr_value_valid_7 = 8'h0; + end + end + + assign io_writes_1_cmd_ready = write_arbiter_1_doIt; + assign io_writes_1_rsp_valid = write_arbiter_1_doIt_regNext; + assign io_writes_1_rsp_payload_context = io_writes_1_cmd_payload_context_regNext; + assign read_ports_0_buffer_groupSel = read_ports_0_buffer_s1_payload_address[0 : 0]; + assign read_ports_0_buffer_bufferIn_valid = read_ports_0_buffer_s1_valid; + assign read_ports_0_buffer_bufferIn_payload_context = read_ports_0_buffer_s1_payload_context; + assign read_ports_0_buffer_bufferIn_payload_data = _zz_read_ports_0_buffer_bufferIn_payload_data; + assign read_ports_0_buffer_bufferIn_payload_mask = _zz_read_ports_0_buffer_bufferIn_payload_mask; + assign read_ports_0_buffer_bufferIn_ready = read_ports_0_buffer_bufferIn_rValidN; + assign read_ports_0_buffer_bufferOut_valid = (read_ports_0_buffer_bufferIn_valid || (! read_ports_0_buffer_bufferIn_rValidN)); + assign read_ports_0_buffer_bufferOut_payload_data = (read_ports_0_buffer_bufferIn_rValidN ? read_ports_0_buffer_bufferIn_payload_data : read_ports_0_buffer_bufferIn_rData_data); + assign read_ports_0_buffer_bufferOut_payload_mask = (read_ports_0_buffer_bufferIn_rValidN ? read_ports_0_buffer_bufferIn_payload_mask : read_ports_0_buffer_bufferIn_rData_mask); + assign read_ports_0_buffer_bufferOut_payload_context = (read_ports_0_buffer_bufferIn_rValidN ? read_ports_0_buffer_bufferIn_payload_context : read_ports_0_buffer_bufferIn_rData_context); + assign io_reads_0_rsp_valid = read_ports_0_buffer_bufferOut_valid; + assign read_ports_0_buffer_bufferOut_ready = io_reads_0_rsp_ready; + assign io_reads_0_rsp_payload_data = read_ports_0_buffer_bufferOut_payload_data; + assign io_reads_0_rsp_payload_mask = read_ports_0_buffer_bufferOut_payload_mask; + assign io_reads_0_rsp_payload_context = read_ports_0_buffer_bufferOut_payload_context; + assign read_ports_0_buffer_full = (read_ports_0_buffer_bufferOut_valid && (! read_ports_0_buffer_bufferOut_ready)); + assign _zz_io_reads_0_cmd_ready = (! read_ports_0_buffer_full); + assign read_ports_0_cmd_valid = (io_reads_0_cmd_valid && _zz_io_reads_0_cmd_ready); + assign io_reads_0_cmd_ready = (read_ports_0_cmd_ready && _zz_io_reads_0_cmd_ready); + assign read_ports_0_cmd_payload_address = io_reads_0_cmd_payload_address; + assign read_ports_0_cmd_payload_priority = io_reads_0_cmd_payload_priority; + assign read_ports_0_cmd_payload_context = io_reads_0_cmd_payload_context; + assign read_ports_1_buffer_bufferIn_valid = read_ports_1_buffer_s1_valid; + assign read_ports_1_buffer_bufferIn_payload_context = read_ports_1_buffer_s1_payload_context; + assign read_ports_1_buffer_bufferIn_payload_data = {banks_1_read_rsp_data,banks_0_read_rsp_data}; + assign read_ports_1_buffer_bufferIn_payload_mask = {banks_1_read_rsp_mask,banks_0_read_rsp_mask}; + assign read_ports_1_buffer_bufferIn_ready = read_ports_1_buffer_bufferIn_rValidN; + assign read_ports_1_buffer_bufferOut_valid = (read_ports_1_buffer_bufferIn_valid || (! read_ports_1_buffer_bufferIn_rValidN)); + assign read_ports_1_buffer_bufferOut_payload_data = (read_ports_1_buffer_bufferIn_rValidN ? read_ports_1_buffer_bufferIn_payload_data : read_ports_1_buffer_bufferIn_rData_data); + assign read_ports_1_buffer_bufferOut_payload_mask = (read_ports_1_buffer_bufferIn_rValidN ? read_ports_1_buffer_bufferIn_payload_mask : read_ports_1_buffer_bufferIn_rData_mask); + assign read_ports_1_buffer_bufferOut_payload_context = (read_ports_1_buffer_bufferIn_rValidN ? read_ports_1_buffer_bufferIn_payload_context : read_ports_1_buffer_bufferIn_rData_context); + assign io_reads_1_rsp_valid = read_ports_1_buffer_bufferOut_valid; + assign read_ports_1_buffer_bufferOut_ready = io_reads_1_rsp_ready; + assign io_reads_1_rsp_payload_data = read_ports_1_buffer_bufferOut_payload_data; + assign io_reads_1_rsp_payload_mask = read_ports_1_buffer_bufferOut_payload_mask; + assign io_reads_1_rsp_payload_context = read_ports_1_buffer_bufferOut_payload_context; + assign read_ports_1_buffer_full = (read_ports_1_buffer_bufferOut_valid && (! read_ports_1_buffer_bufferOut_ready)); + assign _zz_io_reads_1_cmd_ready = (! read_ports_1_buffer_full); + assign read_ports_1_cmd_valid = (io_reads_1_cmd_valid && _zz_io_reads_1_cmd_ready); + assign io_reads_1_cmd_ready = (read_ports_1_cmd_ready && _zz_io_reads_1_cmd_ready); + assign read_ports_1_cmd_payload_address = io_reads_1_cmd_payload_address; + assign read_ports_1_cmd_payload_context = io_reads_1_cmd_payload_context; + assign read_nodes_0_1_priority = 1'b0; + assign read_nodes_1_0_priority = 1'b1; + assign read_nodes_0_1_conflict = ((read_ports_0_cmd_valid && read_ports_1_cmd_valid) && (((read_ports_0_cmd_payload_address ^ io_reads_1_cmd_payload_address) & 10'h0) == 10'h0)); + assign read_nodes_1_0_conflict = read_nodes_0_1_conflict; + assign read_arbiter_0_losedAgainst = (read_nodes_0_1_conflict && (! read_nodes_0_1_priority)); + assign read_arbiter_0_doIt = (read_ports_0_cmd_valid && (read_arbiter_0_losedAgainst == 1'b0)); + assign when_MemoryCore_l221 = (read_arbiter_0_doIt && (_zz_when_MemoryCore_l221[0 : 0] == 1'b0)); + always @(*) begin + if(when_MemoryCore_l221) begin + _zz_banks_0_readOr_value_valid = 1'b1; + end else begin + _zz_banks_0_readOr_value_valid = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l221) begin + _zz_banks_0_readOr_value_valid_1 = (read_ports_0_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_0_readOr_value_valid_1 = 9'h0; + end + end + + assign when_MemoryCore_l221_1 = (read_arbiter_0_doIt && (_zz_when_MemoryCore_l221_1[0 : 0] == 1'b0)); + always @(*) begin + if(when_MemoryCore_l221_1) begin + _zz_banks_1_readOr_value_valid = 1'b1; + end else begin + _zz_banks_1_readOr_value_valid = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l221_1) begin + _zz_banks_1_readOr_value_valid_1 = (read_ports_0_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_1_readOr_value_valid_1 = 9'h0; + end + end + + assign read_ports_0_cmd_ready = read_arbiter_0_doIt; + assign read_ports_0_buffer_s0_valid = read_arbiter_0_doIt; + assign read_ports_0_buffer_s0_payload_context = read_ports_0_cmd_payload_context; + assign read_ports_0_buffer_s0_payload_address = read_ports_0_cmd_payload_address; + assign read_arbiter_1_losedAgainst = (read_nodes_1_0_conflict && (! read_nodes_1_0_priority)); + assign read_arbiter_1_doIt = (read_ports_1_cmd_valid && (read_arbiter_1_losedAgainst == 1'b0)); + assign when_MemoryCore_l221_2 = (read_arbiter_1_doIt && 1'b1); + always @(*) begin + if(when_MemoryCore_l221_2) begin + _zz_banks_0_readOr_value_valid_2 = 1'b1; + end else begin + _zz_banks_0_readOr_value_valid_2 = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l221_2) begin + _zz_banks_0_readOr_value_valid_3 = (read_ports_1_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_0_readOr_value_valid_3 = 9'h0; + end + end + + assign when_MemoryCore_l221_3 = (read_arbiter_1_doIt && 1'b1); + always @(*) begin + if(when_MemoryCore_l221_3) begin + _zz_banks_1_readOr_value_valid_2 = 1'b1; + end else begin + _zz_banks_1_readOr_value_valid_2 = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l221_3) begin + _zz_banks_1_readOr_value_valid_3 = (read_ports_1_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_1_readOr_value_valid_3 = 9'h0; + end + end + + assign read_ports_1_cmd_ready = read_arbiter_1_doIt; + assign read_ports_1_buffer_s0_valid = read_arbiter_1_doIt; + assign read_ports_1_buffer_s0_payload_context = read_ports_1_cmd_payload_context; + assign read_ports_1_buffer_s0_payload_address = read_ports_1_cmd_payload_address; + assign initialiser_done = initialiser_counter[9]; + assign when_MemoryCore_l239 = (! initialiser_done); + assign _zz_banks_0_write_payload_data_data = 72'h0; + assign _zz_banks_1_write_payload_data_data = 72'h0; + assign _zz_banks_0_writeOr_value_valid_8 = ({{{_zz_banks_0_writeOr_value_valid_3,_zz_banks_0_writeOr_value_valid_2},_zz_banks_0_writeOr_value_valid_1},_zz_banks_0_writeOr_value_valid} | {{{_zz_banks_0_writeOr_value_valid_7,_zz_banks_0_writeOr_value_valid_6},_zz_banks_0_writeOr_value_valid_5},_zz_banks_0_writeOr_value_valid_4}); + assign banks_0_writeOr_value_valid = _zz_banks_0_writeOr_value_valid_8[0]; + assign _zz_banks_0_writeOr_value_payload_address = _zz_banks_0_writeOr_value_valid_8[81 : 1]; + assign banks_0_writeOr_value_payload_address = _zz_banks_0_writeOr_value_payload_address[8 : 0]; + assign _zz_banks_0_writeOr_value_payload_data_data = _zz_banks_0_writeOr_value_payload_address[80 : 9]; + assign banks_0_writeOr_value_payload_data_data = _zz_banks_0_writeOr_value_payload_data_data[63 : 0]; + assign banks_0_writeOr_value_payload_data_mask = _zz_banks_0_writeOr_value_payload_data_data[71 : 64]; + assign _zz_banks_0_readOr_value_valid_4 = ({_zz_banks_0_readOr_value_valid_1,_zz_banks_0_readOr_value_valid} | {_zz_banks_0_readOr_value_valid_3,_zz_banks_0_readOr_value_valid_2}); + assign banks_0_readOr_value_valid = _zz_banks_0_readOr_value_valid_4[0]; + assign banks_0_readOr_value_payload = _zz_banks_0_readOr_value_valid_4[9 : 1]; + assign _zz_banks_1_writeOr_value_valid_8 = ({{{_zz_banks_1_writeOr_value_valid_3,_zz_banks_1_writeOr_value_valid_2},_zz_banks_1_writeOr_value_valid_1},_zz_banks_1_writeOr_value_valid} | {{{_zz_banks_1_writeOr_value_valid_7,_zz_banks_1_writeOr_value_valid_6},_zz_banks_1_writeOr_value_valid_5},_zz_banks_1_writeOr_value_valid_4}); + assign banks_1_writeOr_value_valid = _zz_banks_1_writeOr_value_valid_8[0]; + assign _zz_banks_1_writeOr_value_payload_address = _zz_banks_1_writeOr_value_valid_8[81 : 1]; + assign banks_1_writeOr_value_payload_address = _zz_banks_1_writeOr_value_payload_address[8 : 0]; + assign _zz_banks_1_writeOr_value_payload_data_data = _zz_banks_1_writeOr_value_payload_address[80 : 9]; + assign banks_1_writeOr_value_payload_data_data = _zz_banks_1_writeOr_value_payload_data_data[63 : 0]; + assign banks_1_writeOr_value_payload_data_mask = _zz_banks_1_writeOr_value_payload_data_data[71 : 64]; + assign _zz_banks_1_readOr_value_valid_4 = ({_zz_banks_1_readOr_value_valid_1,_zz_banks_1_readOr_value_valid} | {_zz_banks_1_readOr_value_valid_3,_zz_banks_1_readOr_value_valid_2}); + assign banks_1_readOr_value_valid = _zz_banks_1_readOr_value_valid_4[0]; + assign banks_1_readOr_value_payload = _zz_banks_1_readOr_value_valid_4[9 : 1]; + always @(posedge clk) begin + if(io_writes_0_cmd_valid) begin + write_ports_0_priority_value <= (write_ports_0_priority_value + _zz_write_ports_0_priority_value); + if(io_writes_0_cmd_ready) begin + write_ports_0_priority_value <= 4'b0000; + end + end + io_writes_0_cmd_payload_context_regNext <= io_writes_0_cmd_payload_context; + io_writes_1_cmd_payload_context_regNext <= io_writes_1_cmd_payload_context; + read_ports_0_buffer_s1_payload_context <= read_ports_0_buffer_s0_payload_context; + read_ports_0_buffer_s1_payload_address <= read_ports_0_buffer_s0_payload_address; + if(read_ports_0_buffer_bufferIn_ready) begin + read_ports_0_buffer_bufferIn_rData_data <= read_ports_0_buffer_bufferIn_payload_data; + read_ports_0_buffer_bufferIn_rData_mask <= read_ports_0_buffer_bufferIn_payload_mask; + read_ports_0_buffer_bufferIn_rData_context <= read_ports_0_buffer_bufferIn_payload_context; + end + if(read_ports_0_cmd_valid) begin + read_ports_0_priority_value <= (read_ports_0_priority_value + _zz_read_ports_0_priority_value); + if(read_ports_0_cmd_ready) begin + read_ports_0_priority_value <= 4'b0000; + end + end + read_ports_1_buffer_s1_payload_context <= read_ports_1_buffer_s0_payload_context; + read_ports_1_buffer_s1_payload_address <= read_ports_1_buffer_s0_payload_address; + if(read_ports_1_buffer_bufferIn_ready) begin + read_ports_1_buffer_bufferIn_rData_data <= read_ports_1_buffer_bufferIn_payload_data; + read_ports_1_buffer_bufferIn_rData_mask <= read_ports_1_buffer_bufferIn_payload_mask; + read_ports_1_buffer_bufferIn_rData_context <= read_ports_1_buffer_bufferIn_payload_context; + end + end + + always @(posedge clk) begin + if(reset) begin + write_arbiter_0_doIt_regNext <= 1'b0; + write_arbiter_1_doIt_regNext <= 1'b0; + read_ports_0_buffer_s1_valid <= 1'b0; + read_ports_0_buffer_bufferIn_rValidN <= 1'b1; + read_ports_1_buffer_s1_valid <= 1'b0; + read_ports_1_buffer_bufferIn_rValidN <= 1'b1; + initialiser_counter <= 10'h0; + end else begin + write_arbiter_0_doIt_regNext <= write_arbiter_0_doIt; + write_arbiter_1_doIt_regNext <= write_arbiter_1_doIt; + read_ports_0_buffer_s1_valid <= read_ports_0_buffer_s0_valid; + if(read_ports_0_buffer_bufferIn_valid) begin + read_ports_0_buffer_bufferIn_rValidN <= 1'b0; + end + if(read_ports_0_buffer_bufferOut_ready) begin + read_ports_0_buffer_bufferIn_rValidN <= 1'b1; + end + read_ports_1_buffer_s1_valid <= read_ports_1_buffer_s0_valid; + if(read_ports_1_buffer_bufferIn_valid) begin + read_ports_1_buffer_bufferIn_rValidN <= 1'b0; + end + if(read_ports_1_buffer_bufferOut_ready) begin + read_ports_1_buffer_bufferIn_rValidN <= 1'b1; + end + if(when_MemoryCore_l239) begin + initialiser_counter <= (initialiser_counter + 10'h001); + end + end + end + + +endmodule + +module EfxDMA_StreamFifo_1_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_push_valid, + output wire io_push_ready, + input wire [13:0] io_push_payload_context, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [13:0] io_pop_payload_context, + input wire io_flush, + output wire [2:0] io_occupancy, + output wire [2:0] io_availability, + input wire clk, + input wire reset +); + + reg [13:0] logic_ram_spinal_port1; + wire [2:0] _zz_logic_ptr_notPow2_counter; + wire [2:0] _zz_logic_ptr_notPow2_counter_1; + wire [0:0] _zz_logic_ptr_notPow2_counter_2; + wire [2:0] _zz_logic_ptr_notPow2_counter_3; + wire [0:0] _zz_logic_ptr_notPow2_counter_4; + reg _zz_1; + wire logic_ptr_doPush; + wire logic_ptr_doPop; + wire logic_ptr_full; + wire logic_ptr_empty; + reg [2:0] logic_ptr_push; + reg [2:0] logic_ptr_pop; + wire [2:0] logic_ptr_occupancy; + wire [2:0] logic_ptr_popOnIo; + wire when_Stream_l1248; + reg logic_ptr_wentUp; + wire when_Stream_l1283; + wire when_Stream_l1287; + reg [2:0] logic_ptr_notPow2_counter; + wire io_push_fire; + wire io_pop_fire; + wire logic_push_onRam_write_valid; + wire [2:0] logic_push_onRam_write_payload_address; + wire [13:0] logic_push_onRam_write_payload_data_context; + wire logic_pop_addressGen_valid; + reg logic_pop_addressGen_ready; + wire [2:0] logic_pop_addressGen_payload; + wire logic_pop_addressGen_fire; + wire logic_pop_sync_readArbitation_valid; + wire logic_pop_sync_readArbitation_ready; + wire [2:0] logic_pop_sync_readArbitation_payload; + reg logic_pop_addressGen_rValid; + reg [2:0] logic_pop_addressGen_rData; + wire when_Stream_l375; + wire logic_pop_sync_readPort_cmd_valid; + wire [2:0] logic_pop_sync_readPort_cmd_payload; + wire [13:0] logic_pop_sync_readPort_rsp_context; + wire logic_pop_sync_readArbitation_translated_valid; + wire logic_pop_sync_readArbitation_translated_ready; + wire [13:0] logic_pop_sync_readArbitation_translated_payload_context; + wire logic_pop_sync_readArbitation_fire; + reg [2:0] logic_pop_sync_popReg; + reg [13:0] logic_ram [0:6]; + + assign _zz_logic_ptr_notPow2_counter = (logic_ptr_notPow2_counter + _zz_logic_ptr_notPow2_counter_1); + assign _zz_logic_ptr_notPow2_counter_2 = io_push_fire; + assign _zz_logic_ptr_notPow2_counter_1 = {2'd0, _zz_logic_ptr_notPow2_counter_2}; + assign _zz_logic_ptr_notPow2_counter_4 = io_pop_fire; + assign _zz_logic_ptr_notPow2_counter_3 = {2'd0, _zz_logic_ptr_notPow2_counter_4}; + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data_context; + end + end + + always @(posedge clk) begin + if(logic_pop_sync_readPort_cmd_valid) begin + logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_push_onRam_write_valid) begin + _zz_1 = 1'b1; + end + end + + assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); + assign logic_ptr_full = ((logic_ptr_push == logic_ptr_popOnIo) && logic_ptr_wentUp); + assign logic_ptr_empty = ((logic_ptr_push == logic_ptr_pop) && (! logic_ptr_wentUp)); + assign when_Stream_l1283 = (logic_ptr_push == 3'b110); + assign when_Stream_l1287 = (logic_ptr_pop == 3'b110); + assign io_push_fire = (io_push_valid && io_push_ready); + assign io_pop_fire = (io_pop_valid && io_pop_ready); + assign logic_ptr_occupancy = logic_ptr_notPow2_counter; + assign io_push_ready = (! logic_ptr_full); + assign logic_ptr_doPush = io_push_fire; + assign logic_push_onRam_write_valid = io_push_fire; + assign logic_push_onRam_write_payload_address = logic_ptr_push; + assign logic_push_onRam_write_payload_data_context = io_push_payload_context; + assign logic_pop_addressGen_valid = (! logic_ptr_empty); + assign logic_pop_addressGen_payload = logic_ptr_pop; + assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); + assign logic_ptr_doPop = logic_pop_addressGen_fire; + always @(*) begin + logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; + if(when_Stream_l375) begin + logic_pop_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); + assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; + assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; + assign logic_pop_sync_readPort_rsp_context = logic_ram_spinal_port1[13 : 0]; + assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; + assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; + assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; + assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; + assign logic_pop_sync_readArbitation_translated_payload_context = logic_pop_sync_readPort_rsp_context; + assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; + assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_context = logic_pop_sync_readArbitation_translated_payload_context; + assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); + assign logic_ptr_popOnIo = logic_pop_sync_popReg; + assign io_occupancy = logic_ptr_occupancy; + assign io_availability = (3'b111 - logic_ptr_occupancy); + always @(posedge clk) begin + if(reset) begin + logic_ptr_push <= 3'b000; + logic_ptr_pop <= 3'b000; + logic_ptr_wentUp <= 1'b0; + logic_ptr_notPow2_counter <= 3'b000; + logic_pop_addressGen_rValid <= 1'b0; + logic_pop_sync_popReg <= 3'b000; + end else begin + if(when_Stream_l1248) begin + logic_ptr_wentUp <= logic_ptr_doPush; + end + if(io_flush) begin + logic_ptr_wentUp <= 1'b0; + end + if(logic_ptr_doPush) begin + logic_ptr_push <= (logic_ptr_push + 3'b001); + if(when_Stream_l1283) begin + logic_ptr_push <= 3'b000; + end + end + if(logic_ptr_doPop) begin + logic_ptr_pop <= (logic_ptr_pop + 3'b001); + if(when_Stream_l1287) begin + logic_ptr_pop <= 3'b000; + end + end + if(io_flush) begin + logic_ptr_push <= 3'b000; + logic_ptr_pop <= 3'b000; + end + logic_ptr_notPow2_counter <= (_zz_logic_ptr_notPow2_counter - _zz_logic_ptr_notPow2_counter_3); + if(io_flush) begin + logic_ptr_notPow2_counter <= 3'b000; + end + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; + end + if(io_flush) begin + logic_pop_addressGen_rValid <= 1'b0; + end + if(logic_pop_sync_readArbitation_fire) begin + logic_pop_sync_popReg <= logic_ptr_pop; + end + if(io_flush) begin + logic_pop_sync_popReg <= 3'b000; + end + end + end + + always @(posedge clk) begin + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rData <= logic_pop_addressGen_payload; + end + end + + +endmodule + +module EfxDMA_StreamFifo_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_push_valid, + output wire io_push_ready, + input wire [21:0] io_push_payload_context, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [21:0] io_pop_payload_context, + input wire io_flush, + output wire [2:0] io_occupancy, + output wire [2:0] io_availability, + input wire clk, + input wire reset +); + + reg [21:0] logic_ram_spinal_port1; + wire [2:0] _zz_logic_ptr_notPow2_counter; + wire [2:0] _zz_logic_ptr_notPow2_counter_1; + wire [0:0] _zz_logic_ptr_notPow2_counter_2; + wire [2:0] _zz_logic_ptr_notPow2_counter_3; + wire [0:0] _zz_logic_ptr_notPow2_counter_4; + reg _zz_1; + wire logic_ptr_doPush; + wire logic_ptr_doPop; + wire logic_ptr_full; + wire logic_ptr_empty; + reg [2:0] logic_ptr_push; + reg [2:0] logic_ptr_pop; + wire [2:0] logic_ptr_occupancy; + wire [2:0] logic_ptr_popOnIo; + wire when_Stream_l1248; + reg logic_ptr_wentUp; + wire when_Stream_l1283; + wire when_Stream_l1287; + reg [2:0] logic_ptr_notPow2_counter; + wire io_push_fire; + wire io_pop_fire; + wire logic_push_onRam_write_valid; + wire [2:0] logic_push_onRam_write_payload_address; + wire [21:0] logic_push_onRam_write_payload_data_context; + wire logic_pop_addressGen_valid; + reg logic_pop_addressGen_ready; + wire [2:0] logic_pop_addressGen_payload; + wire logic_pop_addressGen_fire; + wire logic_pop_sync_readArbitation_valid; + wire logic_pop_sync_readArbitation_ready; + wire [2:0] logic_pop_sync_readArbitation_payload; + reg logic_pop_addressGen_rValid; + reg [2:0] logic_pop_addressGen_rData; + wire when_Stream_l375; + wire logic_pop_sync_readPort_cmd_valid; + wire [2:0] logic_pop_sync_readPort_cmd_payload; + wire [21:0] logic_pop_sync_readPort_rsp_context; + wire logic_pop_sync_readArbitation_translated_valid; + wire logic_pop_sync_readArbitation_translated_ready; + wire [21:0] logic_pop_sync_readArbitation_translated_payload_context; + wire logic_pop_sync_readArbitation_fire; + reg [2:0] logic_pop_sync_popReg; + reg [21:0] logic_ram [0:6]; + + assign _zz_logic_ptr_notPow2_counter = (logic_ptr_notPow2_counter + _zz_logic_ptr_notPow2_counter_1); + assign _zz_logic_ptr_notPow2_counter_2 = io_push_fire; + assign _zz_logic_ptr_notPow2_counter_1 = {2'd0, _zz_logic_ptr_notPow2_counter_2}; + assign _zz_logic_ptr_notPow2_counter_4 = io_pop_fire; + assign _zz_logic_ptr_notPow2_counter_3 = {2'd0, _zz_logic_ptr_notPow2_counter_4}; + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data_context; + end + end + + always @(posedge clk) begin + if(logic_pop_sync_readPort_cmd_valid) begin + logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_push_onRam_write_valid) begin + _zz_1 = 1'b1; + end + end + + assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); + assign logic_ptr_full = ((logic_ptr_push == logic_ptr_popOnIo) && logic_ptr_wentUp); + assign logic_ptr_empty = ((logic_ptr_push == logic_ptr_pop) && (! logic_ptr_wentUp)); + assign when_Stream_l1283 = (logic_ptr_push == 3'b110); + assign when_Stream_l1287 = (logic_ptr_pop == 3'b110); + assign io_push_fire = (io_push_valid && io_push_ready); + assign io_pop_fire = (io_pop_valid && io_pop_ready); + assign logic_ptr_occupancy = logic_ptr_notPow2_counter; + assign io_push_ready = (! logic_ptr_full); + assign logic_ptr_doPush = io_push_fire; + assign logic_push_onRam_write_valid = io_push_fire; + assign logic_push_onRam_write_payload_address = logic_ptr_push; + assign logic_push_onRam_write_payload_data_context = io_push_payload_context; + assign logic_pop_addressGen_valid = (! logic_ptr_empty); + assign logic_pop_addressGen_payload = logic_ptr_pop; + assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); + assign logic_ptr_doPop = logic_pop_addressGen_fire; + always @(*) begin + logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; + if(when_Stream_l375) begin + logic_pop_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); + assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; + assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; + assign logic_pop_sync_readPort_rsp_context = logic_ram_spinal_port1[21 : 0]; + assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; + assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; + assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; + assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; + assign logic_pop_sync_readArbitation_translated_payload_context = logic_pop_sync_readPort_rsp_context; + assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; + assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_context = logic_pop_sync_readArbitation_translated_payload_context; + assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); + assign logic_ptr_popOnIo = logic_pop_sync_popReg; + assign io_occupancy = logic_ptr_occupancy; + assign io_availability = (3'b111 - logic_ptr_occupancy); + always @(posedge clk) begin + if(reset) begin + logic_ptr_push <= 3'b000; + logic_ptr_pop <= 3'b000; + logic_ptr_wentUp <= 1'b0; + logic_ptr_notPow2_counter <= 3'b000; + logic_pop_addressGen_rValid <= 1'b0; + logic_pop_sync_popReg <= 3'b000; + end else begin + if(when_Stream_l1248) begin + logic_ptr_wentUp <= logic_ptr_doPush; + end + if(io_flush) begin + logic_ptr_wentUp <= 1'b0; + end + if(logic_ptr_doPush) begin + logic_ptr_push <= (logic_ptr_push + 3'b001); + if(when_Stream_l1283) begin + logic_ptr_push <= 3'b000; + end + end + if(logic_ptr_doPop) begin + logic_ptr_pop <= (logic_ptr_pop + 3'b001); + if(when_Stream_l1287) begin + logic_ptr_pop <= 3'b000; + end + end + if(io_flush) begin + logic_ptr_push <= 3'b000; + logic_ptr_pop <= 3'b000; + end + logic_ptr_notPow2_counter <= (_zz_logic_ptr_notPow2_counter - _zz_logic_ptr_notPow2_counter_3); + if(io_flush) begin + logic_ptr_notPow2_counter <= 3'b000; + end + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; + end + if(io_flush) begin + logic_pop_addressGen_rValid <= 1'b0; + end + if(logic_pop_sync_readArbitation_fire) begin + logic_pop_sync_popReg <= logic_ptr_pop; + end + if(io_flush) begin + logic_pop_sync_popReg <= 3'b000; + end + end + end + + always @(posedge clk) begin + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rData <= logic_pop_addressGen_payload; + end + end + + +endmodule + +module EfxDMA_BufferCC_1_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_dataIn, + output wire io_dataOut, + input wire ctrl_clk, + input wire ctrl_reset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge ctrl_clk) begin + if(ctrl_reset) begin + buffers_0 <= 1'b0; + buffers_1 <= 1'b0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module EfxDMA_BufferCC_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_dataIn, + output wire io_dataOut, + input wire clk, + input wire reset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge clk) begin + if(reset) begin + buffers_0 <= 1'b0; + buffers_1 <= 1'b0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/fpga/ip/gDMA/gDMA_define.vh b/fpga/ip/gDMA/gDMA_define.vh new file mode 100644 index 0000000..9ddbd8e --- /dev/null +++ b/fpga/ip/gDMA/gDMA_define.vh @@ -0,0 +1,45 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 6.4.2 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + diff --git a/fpga/ip/gDMA/gDMA_tmpl.v b/fpga/ip/gDMA/gDMA_tmpl.v new file mode 100644 index 0000000..a24f50a --- /dev/null +++ b/fpga/ip/gDMA/gDMA_tmpl.v @@ -0,0 +1,114 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 6.4.2 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +gDMA u_gDMA +( + .clk ( clk ), + .ctrl_reset ( ctrl_reset ), + .reset ( reset ), + .ctrl_clk ( ctrl_clk ), + .ctrl_PADDR ( ctrl_PADDR ), + .ctrl_PREADY ( ctrl_PREADY ), + .ctrl_PENABLE ( ctrl_PENABLE ), + .ctrl_PSEL ( ctrl_PSEL ), + .ctrl_PWRITE ( ctrl_PWRITE ), + .ctrl_PWDATA ( ctrl_PWDATA ), + .ctrl_PRDATA ( ctrl_PRDATA ), + .ctrl_PSLVERROR ( ctrl_PSLVERROR ), + .ctrl_interrupts ( ctrl_interrupts ), + .read_arvalid ( read_arvalid ), + .read_araddr ( read_araddr ), + .read_arready ( read_arready ), + .read_arregion ( read_arregion ), + .read_arlen ( read_arlen ), + .read_arsize ( read_arsize ), + .read_arburst ( read_arburst ), + .read_arlock ( read_arlock ), + .read_arcache ( read_arcache ), + .read_arqos ( read_arqos ), + .read_arprot ( read_arprot ), + .read_rready ( read_rready ), + .read_rvalid ( read_rvalid ), + .read_rdata ( read_rdata ), + .read_rlast ( read_rlast ), + .write_awvalid ( write_awvalid ), + .write_awready ( write_awready ), + .write_awaddr ( write_awaddr ), + .write_awregion ( write_awregion ), + .write_awlen ( write_awlen ), + .write_awsize ( write_awsize ), + .write_awburst ( write_awburst ), + .write_awlock ( write_awlock ), + .write_awcache ( write_awcache ), + .write_awqos ( write_awqos ), + .write_awprot ( write_awprot ), + .write_wvalid ( write_wvalid ), + .write_wready ( write_wready ), + .write_wdata ( write_wdata ), + .write_wstrb ( write_wstrb ), + .write_wlast ( write_wlast ), + .write_bvalid ( write_bvalid ), + .write_bready ( write_bready ), + .write_bresp ( write_bresp ), + .dat1_o_tvalid ( dat1_o_tvalid ), + .dat1_o_tready ( dat1_o_tready ), + .dat1_o_tdata ( dat1_o_tdata ), + .dat1_o_tkeep ( dat1_o_tkeep ), + .dat1_o_tdest ( dat1_o_tdest ), + .dat1_o_tlast ( dat1_o_tlast ), + .io_0_descriptorUpdate ( io_0_descriptorUpdate ), + .dat1_o_clk ( dat1_o_clk ), + .dat1_o_reset ( dat1_o_reset ), + .dat0_i_clk ( dat0_i_clk ), + .dat0_i_reset ( dat0_i_reset ), + .dat0_i_tvalid ( dat0_i_tvalid ), + .dat0_i_tready ( dat0_i_tready ), + .dat0_i_tdata ( dat0_i_tdata ), + .dat0_i_tkeep ( dat0_i_tkeep ), + .dat0_i_tdest ( dat0_i_tdest ), + .dat0_i_tlast ( dat0_i_tlast ), + .read_rresp ( read_rresp ), + .io_1_descriptorUpdate ( io_1_descriptorUpdate ) +); diff --git a/fpga/ip/gDMA/gDMA_tmpl.vhd b/fpga/ip/gDMA/gDMA_tmpl.vhd new file mode 100644 index 0000000..3f0c81e --- /dev/null +++ b/fpga/ip/gDMA/gDMA_tmpl.vhd @@ -0,0 +1,183 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +component gDMA is +port ( + clk : in std_logic; + ctrl_reset : in std_logic; + reset : in std_logic; + ctrl_clk : in std_logic; + ctrl_PADDR : in std_logic_vector(13 downto 0); + ctrl_PREADY : out std_logic; + ctrl_PENABLE : in std_logic; + ctrl_PSEL : in std_logic; + ctrl_PWRITE : in std_logic; + ctrl_PWDATA : in std_logic_vector(31 downto 0); + ctrl_PRDATA : out std_logic_vector(31 downto 0); + ctrl_PSLVERROR : out std_logic; + ctrl_interrupts : out std_logic_vector(1 downto 0); + read_arvalid : out std_logic; + read_araddr : out std_logic_vector(31 downto 0); + read_arready : in std_logic; + read_arregion : out std_logic_vector(3 downto 0); + read_arlen : out std_logic_vector(7 downto 0); + read_arsize : out std_logic_vector(2 downto 0); + read_arburst : out std_logic_vector(1 downto 0); + read_arlock : out std_logic; + read_arcache : out std_logic_vector(3 downto 0); + read_arqos : out std_logic_vector(3 downto 0); + read_arprot : out std_logic_vector(2 downto 0); + read_rready : out std_logic; + read_rvalid : in std_logic; + read_rdata : in std_logic_vector(127 downto 0); + read_rlast : in std_logic; + write_awvalid : out std_logic; + write_awready : in std_logic; + write_awaddr : out std_logic_vector(31 downto 0); + write_awregion : out std_logic_vector(3 downto 0); + write_awlen : out std_logic_vector(7 downto 0); + write_awsize : out std_logic_vector(2 downto 0); + write_awburst : out std_logic_vector(1 downto 0); + write_awlock : out std_logic; + write_awcache : out std_logic_vector(3 downto 0); + write_awqos : out std_logic_vector(3 downto 0); + write_awprot : out std_logic_vector(2 downto 0); + write_wvalid : out std_logic; + write_wready : in std_logic; + write_wdata : out std_logic_vector(127 downto 0); + write_wstrb : out std_logic_vector(15 downto 0); + write_wlast : out std_logic; + write_bvalid : in std_logic; + write_bready : out std_logic; + write_bresp : in std_logic_vector(1 downto 0); + dat1_o_tvalid : out std_logic; + dat1_o_tready : in std_logic; + dat1_o_tdata : out std_logic_vector(7 downto 0); + dat1_o_tkeep : out std_logic_vector(0 to 0); + dat1_o_tdest : out std_logic_vector(3 downto 0); + dat1_o_tlast : out std_logic; + io_0_descriptorUpdate : out std_logic; + dat1_o_clk : in std_logic; + dat1_o_reset : in std_logic; + dat0_i_clk : in std_logic; + dat0_i_reset : in std_logic; + dat0_i_tvalid : in std_logic; + dat0_i_tready : out std_logic; + dat0_i_tdata : in std_logic_vector(7 downto 0); + dat0_i_tkeep : in std_logic_vector(0 to 0); + dat0_i_tdest : in std_logic_vector(3 downto 0); + dat0_i_tlast : in std_logic; + read_rresp : in std_logic_vector(1 downto 0); + io_1_descriptorUpdate : out std_logic +); +end component gDMA; + +---------------------- End COMPONENT Declaration ------------ +------------- Begin Cut here for INSTANTIATION Template ----- +u_gDMA : gDMA +port map ( + clk => clk, + ctrl_reset => ctrl_reset, + reset => reset, + ctrl_clk => ctrl_clk, + ctrl_PADDR => ctrl_PADDR, + ctrl_PREADY => ctrl_PREADY, + ctrl_PENABLE => ctrl_PENABLE, + ctrl_PSEL => ctrl_PSEL, + ctrl_PWRITE => ctrl_PWRITE, + ctrl_PWDATA => ctrl_PWDATA, + ctrl_PRDATA => ctrl_PRDATA, + ctrl_PSLVERROR => ctrl_PSLVERROR, + ctrl_interrupts => ctrl_interrupts, + read_arvalid => read_arvalid, + read_araddr => read_araddr, + read_arready => read_arready, + read_arregion => read_arregion, + read_arlen => read_arlen, + read_arsize => read_arsize, + read_arburst => read_arburst, + read_arlock => read_arlock, + read_arcache => read_arcache, + read_arqos => read_arqos, + read_arprot => read_arprot, + read_rready => read_rready, + read_rvalid => read_rvalid, + read_rdata => read_rdata, + read_rlast => read_rlast, + write_awvalid => write_awvalid, + write_awready => write_awready, + write_awaddr => write_awaddr, + write_awregion => write_awregion, + write_awlen => write_awlen, + write_awsize => write_awsize, + write_awburst => write_awburst, + write_awlock => write_awlock, + write_awcache => write_awcache, + write_awqos => write_awqos, + write_awprot => write_awprot, + write_wvalid => write_wvalid, + write_wready => write_wready, + write_wdata => write_wdata, + write_wstrb => write_wstrb, + write_wlast => write_wlast, + write_bvalid => write_bvalid, + write_bready => write_bready, + write_bresp => write_bresp, + dat1_o_tvalid => dat1_o_tvalid, + dat1_o_tready => dat1_o_tready, + dat1_o_tdata => dat1_o_tdata, + dat1_o_tkeep => dat1_o_tkeep, + dat1_o_tdest => dat1_o_tdest, + dat1_o_tlast => dat1_o_tlast, + io_0_descriptorUpdate => io_0_descriptorUpdate, + dat1_o_clk => dat1_o_clk, + dat1_o_reset => dat1_o_reset, + dat0_i_clk => dat0_i_clk, + dat0_i_reset => dat0_i_reset, + dat0_i_tvalid => dat0_i_tvalid, + dat0_i_tready => dat0_i_tready, + dat0_i_tdata => dat0_i_tdata, + dat0_i_tkeep => dat0_i_tkeep, + dat0_i_tdest => dat0_i_tdest, + dat0_i_tlast => dat0_i_tlast, + read_rresp => read_rresp, + io_1_descriptorUpdate => io_1_descriptorUpdate +); + +------------------------ End INSTANTIATION Template --------- diff --git a/fpga/ip/gDMA/ipm/component.pickle b/fpga/ip/gDMA/ipm/component.pickle new file mode 100644 index 0000000..d3113f8 Binary files /dev/null and b/fpga/ip/gDMA/ipm/component.pickle differ diff --git a/fpga/ip/gDMA/ipm/graph.pickle b/fpga/ip/gDMA/ipm/graph.pickle new file mode 100644 index 0000000..5031dee Binary files /dev/null and b/fpga/ip/gDMA/ipm/graph.pickle differ diff --git a/fpga/ip/gDMA/settings.json b/fpga/ip/gDMA/settings.json new file mode 100644 index 0000000..7d11253 --- /dev/null +++ b/fpga/ip/gDMA/settings.json @@ -0,0 +1,126 @@ +{ + "args": [ + "-o", + "gDMA", + "--base_path", + "/projects/SSE/llching/repo/efx_IP_master/efx_IP/efx_hard_soc/fpga/Ti375C529_devkit/ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "bridges_and_adaptors", + "name": "efx_dma", + "version": "6.4.2" + } + ], + "conf": { + "PriorityEncode": "1'b0", + "WrQueue": "1'b0", + "CTRL_ASYNC_MODE": "1'b1", + "EfinixDDR": "1'b0", + "RdQueue": "1'b0", + "BufferWidth": "64", + "BufferWords": "512", + "MemExtWidth": "128", + "CH0_SGMode": "1'b1", + "CH0_Output": "1'b0", + "CH0_Input": "1'b1", + "CH4_Input": "1'b1", + "CH4_Width": "32", + "CH4_Output": "1'b1", + "CH4_SGMode": "1'b0", + "CH4_SR": "1'b0", + "CH5_BurstSize": "64", + "CH5_BufferSize": "1024", + "CH5_SR": "1'b0", + "CH6_Output": "1'b1", + "CH6_SGMode": "1'b0", + "CH6_SR": "1'b0", + "CH7_Output": "1'b1", + "CH7_SGMode": "1'b0", + "CH7_SR": "1'b0", + "CH7_Input": "1'b1", + "CH7_Width": "32", + "CH7_BurstSize": "64", + "CH7_BufferSize": "1024", + "CH6_Width": "32", + "CH6_Input": "1'b1", + "CH6_BurstSize": "64", + "CH6_BufferSize": "1024", + "CH5_Width": "32", + "CH5_Output": "1'b1", + "CH5_SGMode": "1'b0", + "CH5_Input": "1'b1", + "CH4_BurstSize": "64", + "CH4_BufferSize": "1024", + "CH3_SR": "1'b0", + "CH3_SGMode": "1'b0", + "CH3_Output": "1'b1", + "CH3_Width": "32", + "CH3_Input": "1'b1", + "CH3_BufferSize": "1024", + "CH3_BurstSize": "64", + "BufferCount": "2", + "CH0_Enable": "1'b1", + "CH1_Enable": "1'b1", + "CH1_AsyncMode": "1'b1", + "CH6_AsyncMode": "1'b0", + "CH5_AsyncMode": "1'b0", + "CH7_AsyncMode": "1'b0", + "CH0_AsyncMode": "1'b1", + "CH3_AsyncMode": "1'b0", + "CH2_AsyncMode": "1'b0", + "CH4_AsyncMode": "1'b0", + "CH0_BufferSize": "4096", + "CH0_BurstSize": "1024", + "CH0_SR": "1'b0", + "CH0_Width": "8", + "CH1_Input": "1'b0", + "CH1_Width": "8", + "CH1_Output": "1'b1", + "CH1_SGMode": "1'b1", + "CH1_SR": "1'b0", + "CH2_BufferSize": "1024", + "CH2_BurstSize": "64", + "CH2_Width": "32", + "CH2_SR": "1'b0", + "CH2_SGMode": "1'b0", + "CH2_Output": "1'b1", + "CH2_Input": "1'b1", + "CH1_BufferSize": "4096", + "CH1_BurstSize": "1024", + "CH2_Enable_user": "1'b0", + "CH2_Enable_default": "1'b0", + "CH3_Enable_default": "1'b0", + "CH3_Enable_user": "1'b0", + "CH4_Enable_default": "1'b0", + "CH4_Enable_user": "1'b0", + "CH5_Enable_user": "1'b0", + "CH5_Enable_default": "1'b0", + "CH6_Enable_user": "1'b0", + "CH6_Enable_default": "1'b0", + "CH7_Enable_user": "1'b0", + "CH7_Enable_default": "1'b0", + "CustomSGBus": "1'b0", + "CH0_MemMode": "1'b0", + "CH1_MemMode": "1'b0", + "CH2_MemMode": "1'b0", + "CH3_MemMode": "1'b0", + "CH4_MemMode": "1'b0", + "CH5_MemMode": "1'b0", + "CH6_MemMode": "1'b0", + "CH7_MemMode": "1'b0" + }, + "output": { + "external_script_generator": [], + "external_source_source": [ + "gDMA/gDMA_define.vh", + "gDMA/gDMA.v", + "gDMA/gDMA_tmpl.v", + "gDMA/gDMA_tmpl.vhd" + ], + "external_script_script": [] + }, + "ooc_synthesis": {}, + "sw_version": "2025.2.272", + "generated_date": "2025-10-16T09:35:15.778966+00:00" +} \ No newline at end of file diff --git a/fpga/ip/gDMA/source/EfxDMA.v b/fpga/ip/gDMA/source/EfxDMA.v new file mode 100644 index 0000000..c77644c --- /dev/null +++ b/fpga/ip/gDMA/source/EfxDMA.v @@ -0,0 +1,11449 @@ +// Generator : SpinalHDL dev git head : a69f4b9a329be784802c37cd8038b7dc9aec3094 +// Component : EfxDMA + +`timescale 1ns/1ps + +module EfxDMA ( + input wire [13:0] ctrl_PADDR, + input wire [0:0] ctrl_PSEL, + input wire ctrl_PENABLE, + output wire ctrl_PREADY, + input wire ctrl_PWRITE, + input wire [31:0] ctrl_PWDATA, + output wire [31:0] ctrl_PRDATA, + output wire ctrl_PSLVERROR, + output wire [1:0] ctrl_interrupts, + output wire read_arvalid, + input wire read_arready, + output wire [31:0] read_araddr, + output wire [3:0] read_arregion, + output wire [7:0] read_arlen, + output wire [2:0] read_arsize, + output wire [1:0] read_arburst, + output wire [0:0] read_arlock, + output wire [3:0] read_arcache, + output wire [3:0] read_arqos, + output wire [2:0] read_arprot, + input wire read_rvalid, + output wire read_rready, + input wire [127:0] read_rdata, + input wire [1:0] read_rresp, + input wire read_rlast, + output wire write_awvalid, + input wire write_awready, + output wire [31:0] write_awaddr, + output wire [3:0] write_awregion, + output wire [7:0] write_awlen, + output wire [2:0] write_awsize, + output wire [1:0] write_awburst, + output wire [0:0] write_awlock, + output wire [3:0] write_awcache, + output wire [3:0] write_awqos, + output wire [2:0] write_awprot, + output wire write_wvalid, + input wire write_wready, + output wire [127:0] write_wdata, + output wire [15:0] write_wstrb, + output wire write_wlast, + input wire write_bvalid, + output wire write_bready, + input wire [1:0] write_bresp, + input wire dat0_i_tvalid, + output wire dat0_i_tready, + input wire [7:0] dat0_i_tdata, + input wire [0:0] dat0_i_tkeep, + input wire [3:0] dat0_i_tdest, + input wire dat0_i_tlast, + output wire dat1_o_tvalid, + input wire dat1_o_tready, + output wire [7:0] dat1_o_tdata, + output wire [0:0] dat1_o_tkeep, + output wire [3:0] dat1_o_tdest, + output wire dat1_o_tlast, + output wire io_0_descriptorUpdate, + output wire io_1_descriptorUpdate, + input wire clk, + input wire reset, + input wire ctrl_clk, + input wire ctrl_reset, + input wire dat0_i_clk, + input wire dat0_i_reset, + input wire dat1_o_clk, + input wire dat1_o_reset +); + + wire core_io_sgRead_cmd_valid; + wire core_io_sgRead_cmd_payload_last; + wire [0:0] core_io_sgRead_cmd_payload_fragment_opcode; + wire [31:0] core_io_sgRead_cmd_payload_fragment_address; + wire [4:0] core_io_sgRead_cmd_payload_fragment_length; + wire [0:0] core_io_sgRead_cmd_payload_fragment_context; + wire core_io_sgRead_rsp_ready; + wire core_io_sgWrite_cmd_valid; + wire core_io_sgWrite_cmd_payload_last; + wire [0:0] core_io_sgWrite_cmd_payload_fragment_opcode; + wire [31:0] core_io_sgWrite_cmd_payload_fragment_address; + wire [1:0] core_io_sgWrite_cmd_payload_fragment_length; + wire [127:0] core_io_sgWrite_cmd_payload_fragment_data; + wire [15:0] core_io_sgWrite_cmd_payload_fragment_mask; + wire [0:0] core_io_sgWrite_cmd_payload_fragment_context; + wire core_io_sgWrite_rsp_ready; + wire core_io_read_cmd_valid; + wire core_io_read_cmd_payload_last; + wire [0:0] core_io_read_cmd_payload_fragment_opcode; + wire [31:0] core_io_read_cmd_payload_fragment_address; + wire [11:0] core_io_read_cmd_payload_fragment_length; + wire [20:0] core_io_read_cmd_payload_fragment_context; + wire core_io_read_rsp_ready; + wire core_io_write_cmd_valid; + wire core_io_write_cmd_payload_last; + wire [0:0] core_io_write_cmd_payload_fragment_opcode; + wire [31:0] core_io_write_cmd_payload_fragment_address; + wire [11:0] core_io_write_cmd_payload_fragment_length; + wire [127:0] core_io_write_cmd_payload_fragment_data; + wire [15:0] core_io_write_cmd_payload_fragment_mask; + wire [12:0] core_io_write_cmd_payload_fragment_context; + wire core_io_write_rsp_ready; + wire core_io_outputs_0_valid; + wire [63:0] core_io_outputs_0_payload_data; + wire [7:0] core_io_outputs_0_payload_mask; + wire [3:0] core_io_outputs_0_payload_sink; + wire core_io_outputs_0_payload_last; + wire core_io_inputs_0_ready; + wire [1:0] core_io_interrupts; + wire core_io_ctrl_PREADY; + wire [31:0] core_io_ctrl_PRDATA; + wire core_io_ctrl_PSLVERROR; + wire core_ll_0_descriptorUpdate; + wire core_ll_1_descriptorUpdate; + wire withCtrlCc_apbCc_io_input_PREADY; + wire [31:0] withCtrlCc_apbCc_io_input_PRDATA; + wire withCtrlCc_apbCc_io_input_PSLVERROR; + wire [13:0] withCtrlCc_apbCc_io_output_PADDR; + wire [0:0] withCtrlCc_apbCc_io_output_PSEL; + wire withCtrlCc_apbCc_io_output_PENABLE; + wire withCtrlCc_apbCc_io_output_PWRITE; + wire [31:0] withCtrlCc_apbCc_io_output_PWDATA; + wire [1:0] io_interrupts_buffercc_io_dataOut; + wire readLogic_sourceRemover_io_input_cmd_ready; + wire readLogic_sourceRemover_io_input_rsp_valid; + wire readLogic_sourceRemover_io_input_rsp_payload_last; + wire [0:0] readLogic_sourceRemover_io_input_rsp_payload_fragment_source; + wire [0:0] readLogic_sourceRemover_io_input_rsp_payload_fragment_opcode; + wire [127:0] readLogic_sourceRemover_io_input_rsp_payload_fragment_data; + wire [20:0] readLogic_sourceRemover_io_input_rsp_payload_fragment_context; + wire readLogic_sourceRemover_io_output_cmd_valid; + wire readLogic_sourceRemover_io_output_cmd_payload_last; + wire [0:0] readLogic_sourceRemover_io_output_cmd_payload_fragment_opcode; + wire [31:0] readLogic_sourceRemover_io_output_cmd_payload_fragment_address; + wire [11:0] readLogic_sourceRemover_io_output_cmd_payload_fragment_length; + wire [21:0] readLogic_sourceRemover_io_output_cmd_payload_fragment_context; + wire readLogic_sourceRemover_io_output_rsp_ready; + wire readLogic_bridge_io_input_cmd_ready; + wire readLogic_bridge_io_input_rsp_valid; + wire readLogic_bridge_io_input_rsp_payload_last; + wire [0:0] readLogic_bridge_io_input_rsp_payload_fragment_opcode; + wire [127:0] readLogic_bridge_io_input_rsp_payload_fragment_data; + wire [21:0] readLogic_bridge_io_input_rsp_payload_fragment_context; + wire readLogic_bridge_io_output_ar_valid; + wire [31:0] readLogic_bridge_io_output_ar_payload_addr; + wire [7:0] readLogic_bridge_io_output_ar_payload_len; + wire [2:0] readLogic_bridge_io_output_ar_payload_size; + wire [3:0] readLogic_bridge_io_output_ar_payload_cache; + wire [2:0] readLogic_bridge_io_output_ar_payload_prot; + wire readLogic_bridge_io_output_r_ready; + wire writeLogic_sourceRemover_io_input_cmd_ready; + wire writeLogic_sourceRemover_io_input_rsp_valid; + wire writeLogic_sourceRemover_io_input_rsp_payload_last; + wire [0:0] writeLogic_sourceRemover_io_input_rsp_payload_fragment_source; + wire [0:0] writeLogic_sourceRemover_io_input_rsp_payload_fragment_opcode; + wire [12:0] writeLogic_sourceRemover_io_input_rsp_payload_fragment_context; + wire writeLogic_sourceRemover_io_output_cmd_valid; + wire writeLogic_sourceRemover_io_output_cmd_payload_last; + wire [0:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_opcode; + wire [31:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_address; + wire [11:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_length; + wire [127:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_data; + wire [15:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_mask; + wire [13:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_context; + wire writeLogic_sourceRemover_io_output_rsp_ready; + wire writeLogic_bridge_io_input_cmd_ready; + wire writeLogic_bridge_io_input_rsp_valid; + wire writeLogic_bridge_io_input_rsp_payload_last; + wire [0:0] writeLogic_bridge_io_input_rsp_payload_fragment_opcode; + wire [13:0] writeLogic_bridge_io_input_rsp_payload_fragment_context; + wire writeLogic_bridge_io_output_aw_valid; + wire [31:0] writeLogic_bridge_io_output_aw_payload_addr; + wire [7:0] writeLogic_bridge_io_output_aw_payload_len; + wire [2:0] writeLogic_bridge_io_output_aw_payload_size; + wire [3:0] writeLogic_bridge_io_output_aw_payload_cache; + wire [2:0] writeLogic_bridge_io_output_aw_payload_prot; + wire writeLogic_bridge_io_output_w_valid; + wire [127:0] writeLogic_bridge_io_output_w_payload_data; + wire [15:0] writeLogic_bridge_io_output_w_payload_strb; + wire writeLogic_bridge_io_output_w_payload_last; + wire writeLogic_bridge_io_output_b_ready; + wire inputsAdapter_0_upsizer_logic_io_input_ready; + wire inputsAdapter_0_upsizer_logic_io_output_valid; + wire [63:0] inputsAdapter_0_upsizer_logic_io_output_payload_data; + wire [7:0] inputsAdapter_0_upsizer_logic_io_output_payload_mask; + wire [3:0] inputsAdapter_0_upsizer_logic_io_output_payload_sink; + wire inputsAdapter_0_upsizer_logic_io_output_payload_last; + wire inputsAdapter_0_crossclock_fifo_io_push_ready; + wire inputsAdapter_0_crossclock_fifo_io_pop_valid; + wire [63:0] inputsAdapter_0_crossclock_fifo_io_pop_payload_data; + wire [7:0] inputsAdapter_0_crossclock_fifo_io_pop_payload_mask; + wire [3:0] inputsAdapter_0_crossclock_fifo_io_pop_payload_sink; + wire inputsAdapter_0_crossclock_fifo_io_pop_payload_last; + wire [4:0] inputsAdapter_0_crossclock_fifo_io_pushOccupancy; + wire [4:0] inputsAdapter_0_crossclock_fifo_io_popOccupancy; + wire outputsAdapter_0_crossclock_fifo_io_push_ready; + wire outputsAdapter_0_crossclock_fifo_io_pop_valid; + wire [63:0] outputsAdapter_0_crossclock_fifo_io_pop_payload_data; + wire [7:0] outputsAdapter_0_crossclock_fifo_io_pop_payload_mask; + wire [3:0] outputsAdapter_0_crossclock_fifo_io_pop_payload_sink; + wire outputsAdapter_0_crossclock_fifo_io_pop_payload_last; + wire [4:0] outputsAdapter_0_crossclock_fifo_io_pushOccupancy; + wire [4:0] outputsAdapter_0_crossclock_fifo_io_popOccupancy; + wire outputsAdapter_0_sparseDownsizer_logic_io_input_ready; + wire outputsAdapter_0_sparseDownsizer_logic_io_output_valid; + wire [7:0] outputsAdapter_0_sparseDownsizer_logic_io_output_payload_data; + wire [0:0] outputsAdapter_0_sparseDownsizer_logic_io_output_payload_mask; + wire [3:0] outputsAdapter_0_sparseDownsizer_logic_io_output_payload_sink; + wire outputsAdapter_0_sparseDownsizer_logic_io_output_payload_last; + wire interconnect_read_aggregated_arbiter_io_inputs_0_cmd_ready; + wire interconnect_read_aggregated_arbiter_io_inputs_0_rsp_valid; + wire interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_last; + wire [0:0] interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode; + wire [127:0] interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_data; + wire [0:0] interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context; + wire interconnect_read_aggregated_arbiter_io_inputs_1_cmd_ready; + wire interconnect_read_aggregated_arbiter_io_inputs_1_rsp_valid; + wire interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_last; + wire [0:0] interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode; + wire [127:0] interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_data; + wire [20:0] interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context; + wire interconnect_read_aggregated_arbiter_io_output_cmd_valid; + wire interconnect_read_aggregated_arbiter_io_output_cmd_payload_last; + wire [0:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_source; + wire [0:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_opcode; + wire [31:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_address; + wire [11:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_length; + wire [20:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_context; + wire interconnect_read_aggregated_arbiter_io_output_rsp_ready; + wire interconnect_write_aggregated_arbiter_io_inputs_0_cmd_ready; + wire interconnect_write_aggregated_arbiter_io_inputs_0_rsp_valid; + wire interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_last; + wire [0:0] interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode; + wire [0:0] interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context; + wire interconnect_write_aggregated_arbiter_io_inputs_1_cmd_ready; + wire interconnect_write_aggregated_arbiter_io_inputs_1_rsp_valid; + wire interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_last; + wire [0:0] interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode; + wire [12:0] interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context; + wire interconnect_write_aggregated_arbiter_io_output_cmd_valid; + wire interconnect_write_aggregated_arbiter_io_output_cmd_payload_last; + wire [0:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_source; + wire [0:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_opcode; + wire [31:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_address; + wire [11:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_length; + wire [127:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_data; + wire [15:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_mask; + wire [12:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_context; + wire interconnect_write_aggregated_arbiter_io_output_rsp_ready; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode; + wire [31:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address; + wire [11:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length; + wire [20:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode; + wire [127:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_data; + wire [20:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode; + wire [31:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address; + wire [4:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode; + wire [127:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode; + wire [31:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address; + wire [11:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length; + wire [127:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_data; + wire [15:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_mask; + wire [12:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode; + wire [12:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context; + wire io_write_cmd_s2mPipe_valid; + reg io_write_cmd_s2mPipe_ready; + wire io_write_cmd_s2mPipe_payload_last; + wire [0:0] io_write_cmd_s2mPipe_payload_fragment_opcode; + wire [31:0] io_write_cmd_s2mPipe_payload_fragment_address; + wire [11:0] io_write_cmd_s2mPipe_payload_fragment_length; + wire [127:0] io_write_cmd_s2mPipe_payload_fragment_data; + wire [15:0] io_write_cmd_s2mPipe_payload_fragment_mask; + wire [12:0] io_write_cmd_s2mPipe_payload_fragment_context; + reg io_write_cmd_rValidN; + reg io_write_cmd_rData_last; + reg [0:0] io_write_cmd_rData_fragment_opcode; + reg [31:0] io_write_cmd_rData_fragment_address; + reg [11:0] io_write_cmd_rData_fragment_length; + reg [127:0] io_write_cmd_rData_fragment_data; + reg [15:0] io_write_cmd_rData_fragment_mask; + reg [12:0] io_write_cmd_rData_fragment_context; + wire io_write_cmd_s2mPipe_m2sPipe_valid; + wire io_write_cmd_s2mPipe_m2sPipe_ready; + wire io_write_cmd_s2mPipe_m2sPipe_payload_last; + wire [0:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_opcode; + wire [31:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_address; + wire [11:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_length; + wire [127:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_data; + wire [15:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_mask; + wire [12:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_context; + reg io_write_cmd_s2mPipe_rValid; + reg io_write_cmd_s2mPipe_rData_last; + reg [0:0] io_write_cmd_s2mPipe_rData_fragment_opcode; + reg [31:0] io_write_cmd_s2mPipe_rData_fragment_address; + reg [11:0] io_write_cmd_s2mPipe_rData_fragment_length; + reg [127:0] io_write_cmd_s2mPipe_rData_fragment_data; + reg [15:0] io_write_cmd_s2mPipe_rData_fragment_mask; + reg [12:0] io_write_cmd_s2mPipe_rData_fragment_context; + wire when_Stream_l375; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode; + wire [31:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address; + wire [1:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length; + wire [127:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data; + wire [15:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context; + wire interconnect_read_aggregated_cmd_valid; + wire interconnect_read_aggregated_cmd_ready; + wire interconnect_read_aggregated_cmd_payload_last; + wire [0:0] interconnect_read_aggregated_cmd_payload_fragment_source; + wire [0:0] interconnect_read_aggregated_cmd_payload_fragment_opcode; + wire [31:0] interconnect_read_aggregated_cmd_payload_fragment_address; + wire [11:0] interconnect_read_aggregated_cmd_payload_fragment_length; + wire [20:0] interconnect_read_aggregated_cmd_payload_fragment_context; + wire interconnect_read_aggregated_rsp_valid; + wire interconnect_read_aggregated_rsp_ready; + wire interconnect_read_aggregated_rsp_payload_last; + wire [0:0] interconnect_read_aggregated_rsp_payload_fragment_source; + wire [0:0] interconnect_read_aggregated_rsp_payload_fragment_opcode; + wire [127:0] interconnect_read_aggregated_rsp_payload_fragment_data; + wire [20:0] interconnect_read_aggregated_rsp_payload_fragment_context; + wire interconnect_write_aggregated_cmd_valid; + reg interconnect_write_aggregated_cmd_ready; + wire interconnect_write_aggregated_cmd_payload_last; + wire [0:0] interconnect_write_aggregated_cmd_payload_fragment_source; + wire [0:0] interconnect_write_aggregated_cmd_payload_fragment_opcode; + wire [31:0] interconnect_write_aggregated_cmd_payload_fragment_address; + wire [11:0] interconnect_write_aggregated_cmd_payload_fragment_length; + wire [127:0] interconnect_write_aggregated_cmd_payload_fragment_data; + wire [15:0] interconnect_write_aggregated_cmd_payload_fragment_mask; + wire [12:0] interconnect_write_aggregated_cmd_payload_fragment_context; + wire interconnect_write_aggregated_rsp_valid; + wire interconnect_write_aggregated_rsp_ready; + wire interconnect_write_aggregated_rsp_payload_last; + wire [0:0] interconnect_write_aggregated_rsp_payload_fragment_source; + wire [0:0] interconnect_write_aggregated_rsp_payload_fragment_opcode; + wire [12:0] interconnect_write_aggregated_rsp_payload_fragment_context; + wire readLogic_resized_cmd_valid; + wire readLogic_resized_cmd_ready; + wire readLogic_resized_cmd_payload_last; + wire [0:0] readLogic_resized_cmd_payload_fragment_source; + wire [0:0] readLogic_resized_cmd_payload_fragment_opcode; + wire [31:0] readLogic_resized_cmd_payload_fragment_address; + wire [11:0] readLogic_resized_cmd_payload_fragment_length; + wire [20:0] readLogic_resized_cmd_payload_fragment_context; + wire readLogic_resized_rsp_valid; + wire readLogic_resized_rsp_ready; + wire readLogic_resized_rsp_payload_last; + wire [0:0] readLogic_resized_rsp_payload_fragment_source; + wire [0:0] readLogic_resized_rsp_payload_fragment_opcode; + wire [127:0] readLogic_resized_rsp_payload_fragment_data; + wire [20:0] readLogic_resized_rsp_payload_fragment_context; + wire interconnect_read_aggregated_cmd_halfPipe_valid; + wire interconnect_read_aggregated_cmd_halfPipe_ready; + wire interconnect_read_aggregated_cmd_halfPipe_payload_last; + wire [0:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_source; + wire [0:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_opcode; + wire [31:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_address; + wire [11:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_length; + wire [20:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_context; + reg interconnect_read_aggregated_cmd_rValid; + wire interconnect_read_aggregated_cmd_halfPipe_fire; + reg interconnect_read_aggregated_cmd_rData_last; + reg [0:0] interconnect_read_aggregated_cmd_rData_fragment_source; + reg [0:0] interconnect_read_aggregated_cmd_rData_fragment_opcode; + reg [31:0] interconnect_read_aggregated_cmd_rData_fragment_address; + reg [11:0] interconnect_read_aggregated_cmd_rData_fragment_length; + reg [20:0] interconnect_read_aggregated_cmd_rData_fragment_context; + wire readLogic_resized_rsp_combStage_valid; + wire readLogic_resized_rsp_combStage_ready; + wire readLogic_resized_rsp_combStage_payload_last; + wire [0:0] readLogic_resized_rsp_combStage_payload_fragment_source; + wire [0:0] readLogic_resized_rsp_combStage_payload_fragment_opcode; + wire [127:0] readLogic_resized_rsp_combStage_payload_fragment_data; + wire [20:0] readLogic_resized_rsp_combStage_payload_fragment_context; + wire readLogic_adapter_ar_valid; + wire readLogic_adapter_ar_ready; + wire [31:0] readLogic_adapter_ar_payload_addr; + wire [3:0] readLogic_adapter_ar_payload_region; + wire [7:0] readLogic_adapter_ar_payload_len; + wire [2:0] readLogic_adapter_ar_payload_size; + wire [1:0] readLogic_adapter_ar_payload_burst; + wire [0:0] readLogic_adapter_ar_payload_lock; + wire [3:0] readLogic_adapter_ar_payload_cache; + wire [3:0] readLogic_adapter_ar_payload_qos; + wire [2:0] readLogic_adapter_ar_payload_prot; + wire readLogic_adapter_r_valid; + wire readLogic_adapter_r_ready; + wire [127:0] readLogic_adapter_r_payload_data; + wire [1:0] readLogic_adapter_r_payload_resp; + wire readLogic_adapter_r_payload_last; + wire [3:0] _zz_readLogic_adapter_ar_payload_region; + wire readLogic_adapter_ar_halfPipe_valid; + wire readLogic_adapter_ar_halfPipe_ready; + wire [31:0] readLogic_adapter_ar_halfPipe_payload_addr; + wire [3:0] readLogic_adapter_ar_halfPipe_payload_region; + wire [7:0] readLogic_adapter_ar_halfPipe_payload_len; + wire [2:0] readLogic_adapter_ar_halfPipe_payload_size; + wire [1:0] readLogic_adapter_ar_halfPipe_payload_burst; + wire [0:0] readLogic_adapter_ar_halfPipe_payload_lock; + wire [3:0] readLogic_adapter_ar_halfPipe_payload_cache; + wire [3:0] readLogic_adapter_ar_halfPipe_payload_qos; + wire [2:0] readLogic_adapter_ar_halfPipe_payload_prot; + reg readLogic_adapter_ar_rValid; + wire readLogic_adapter_ar_halfPipe_fire; + reg [31:0] readLogic_adapter_ar_rData_addr; + reg [3:0] readLogic_adapter_ar_rData_region; + reg [7:0] readLogic_adapter_ar_rData_len; + reg [2:0] readLogic_adapter_ar_rData_size; + reg [1:0] readLogic_adapter_ar_rData_burst; + reg [0:0] readLogic_adapter_ar_rData_lock; + reg [3:0] readLogic_adapter_ar_rData_cache; + reg [3:0] readLogic_adapter_ar_rData_qos; + reg [2:0] readLogic_adapter_ar_rData_prot; + wire read_r_s2mPipe_valid; + reg read_r_s2mPipe_ready; + wire [127:0] read_r_s2mPipe_payload_data; + wire [1:0] read_r_s2mPipe_payload_resp; + wire read_r_s2mPipe_payload_last; + reg read_r_rValidN; + reg [127:0] read_r_rData_data; + reg [1:0] read_r_rData_resp; + reg read_r_rData_last; + wire readLogic_beforeQueue_valid; + wire readLogic_beforeQueue_ready; + wire [127:0] readLogic_beforeQueue_payload_data; + wire [1:0] readLogic_beforeQueue_payload_resp; + wire readLogic_beforeQueue_payload_last; + reg read_r_s2mPipe_rValid; + reg [127:0] read_r_s2mPipe_rData_data; + reg [1:0] read_r_s2mPipe_rData_resp; + reg read_r_s2mPipe_rData_last; + wire when_Stream_l375_1; + wire writeLogic_resized_cmd_valid; + wire writeLogic_resized_cmd_ready; + wire writeLogic_resized_cmd_payload_last; + wire [0:0] writeLogic_resized_cmd_payload_fragment_source; + wire [0:0] writeLogic_resized_cmd_payload_fragment_opcode; + wire [31:0] writeLogic_resized_cmd_payload_fragment_address; + wire [11:0] writeLogic_resized_cmd_payload_fragment_length; + wire [127:0] writeLogic_resized_cmd_payload_fragment_data; + wire [15:0] writeLogic_resized_cmd_payload_fragment_mask; + wire [12:0] writeLogic_resized_cmd_payload_fragment_context; + wire writeLogic_resized_rsp_valid; + wire writeLogic_resized_rsp_ready; + wire writeLogic_resized_rsp_payload_last; + wire [0:0] writeLogic_resized_rsp_payload_fragment_source; + wire [0:0] writeLogic_resized_rsp_payload_fragment_opcode; + wire [12:0] writeLogic_resized_rsp_payload_fragment_context; + wire interconnect_write_aggregated_cmd_m2sPipe_valid; + wire interconnect_write_aggregated_cmd_m2sPipe_ready; + wire interconnect_write_aggregated_cmd_m2sPipe_payload_last; + wire [0:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_source; + wire [0:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_opcode; + wire [31:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_address; + wire [11:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_length; + wire [127:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_data; + wire [15:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_mask; + wire [12:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_context; + reg interconnect_write_aggregated_cmd_rValid; + reg interconnect_write_aggregated_cmd_rData_last; + reg [0:0] interconnect_write_aggregated_cmd_rData_fragment_source; + reg [0:0] interconnect_write_aggregated_cmd_rData_fragment_opcode; + reg [31:0] interconnect_write_aggregated_cmd_rData_fragment_address; + reg [11:0] interconnect_write_aggregated_cmd_rData_fragment_length; + reg [127:0] interconnect_write_aggregated_cmd_rData_fragment_data; + reg [15:0] interconnect_write_aggregated_cmd_rData_fragment_mask; + reg [12:0] interconnect_write_aggregated_cmd_rData_fragment_context; + wire when_Stream_l375_2; + wire writeLogic_resized_rsp_combStage_valid; + wire writeLogic_resized_rsp_combStage_ready; + wire writeLogic_resized_rsp_combStage_payload_last; + wire [0:0] writeLogic_resized_rsp_combStage_payload_fragment_source; + wire [0:0] writeLogic_resized_rsp_combStage_payload_fragment_opcode; + wire [12:0] writeLogic_resized_rsp_combStage_payload_fragment_context; + wire writeLogic_adapter_aw_valid; + wire writeLogic_adapter_aw_ready; + wire [31:0] writeLogic_adapter_aw_payload_addr; + wire [3:0] writeLogic_adapter_aw_payload_region; + wire [7:0] writeLogic_adapter_aw_payload_len; + wire [2:0] writeLogic_adapter_aw_payload_size; + wire [1:0] writeLogic_adapter_aw_payload_burst; + wire [0:0] writeLogic_adapter_aw_payload_lock; + wire [3:0] writeLogic_adapter_aw_payload_cache; + wire [3:0] writeLogic_adapter_aw_payload_qos; + wire [2:0] writeLogic_adapter_aw_payload_prot; + wire writeLogic_adapter_w_valid; + wire writeLogic_adapter_w_ready; + wire [127:0] writeLogic_adapter_w_payload_data; + wire [15:0] writeLogic_adapter_w_payload_strb; + wire writeLogic_adapter_w_payload_last; + wire writeLogic_adapter_b_valid; + wire writeLogic_adapter_b_ready; + wire [1:0] writeLogic_adapter_b_payload_resp; + wire [3:0] _zz_writeLogic_adapter_aw_payload_region; + wire writeLogic_adapter_aw_halfPipe_valid; + wire writeLogic_adapter_aw_halfPipe_ready; + wire [31:0] writeLogic_adapter_aw_halfPipe_payload_addr; + wire [3:0] writeLogic_adapter_aw_halfPipe_payload_region; + wire [7:0] writeLogic_adapter_aw_halfPipe_payload_len; + wire [2:0] writeLogic_adapter_aw_halfPipe_payload_size; + wire [1:0] writeLogic_adapter_aw_halfPipe_payload_burst; + wire [0:0] writeLogic_adapter_aw_halfPipe_payload_lock; + wire [3:0] writeLogic_adapter_aw_halfPipe_payload_cache; + wire [3:0] writeLogic_adapter_aw_halfPipe_payload_qos; + wire [2:0] writeLogic_adapter_aw_halfPipe_payload_prot; + reg writeLogic_adapter_aw_rValid; + wire writeLogic_adapter_aw_halfPipe_fire; + reg [31:0] writeLogic_adapter_aw_rData_addr; + reg [3:0] writeLogic_adapter_aw_rData_region; + reg [7:0] writeLogic_adapter_aw_rData_len; + reg [2:0] writeLogic_adapter_aw_rData_size; + reg [1:0] writeLogic_adapter_aw_rData_burst; + reg [0:0] writeLogic_adapter_aw_rData_lock; + reg [3:0] writeLogic_adapter_aw_rData_cache; + reg [3:0] writeLogic_adapter_aw_rData_qos; + reg [2:0] writeLogic_adapter_aw_rData_prot; + wire writeLogic_adapter_w_s2mPipe_valid; + reg writeLogic_adapter_w_s2mPipe_ready; + wire [127:0] writeLogic_adapter_w_s2mPipe_payload_data; + wire [15:0] writeLogic_adapter_w_s2mPipe_payload_strb; + wire writeLogic_adapter_w_s2mPipe_payload_last; + reg writeLogic_adapter_w_rValidN; + reg [127:0] writeLogic_adapter_w_rData_data; + reg [15:0] writeLogic_adapter_w_rData_strb; + reg writeLogic_adapter_w_rData_last; + wire writeLogic_adapter_w_s2mPipe_m2sPipe_valid; + wire writeLogic_adapter_w_s2mPipe_m2sPipe_ready; + wire [127:0] writeLogic_adapter_w_s2mPipe_m2sPipe_payload_data; + wire [15:0] writeLogic_adapter_w_s2mPipe_m2sPipe_payload_strb; + wire writeLogic_adapter_w_s2mPipe_m2sPipe_payload_last; + reg writeLogic_adapter_w_s2mPipe_rValid; + reg [127:0] writeLogic_adapter_w_s2mPipe_rData_data; + reg [15:0] writeLogic_adapter_w_s2mPipe_rData_strb; + reg writeLogic_adapter_w_s2mPipe_rData_last; + wire when_Stream_l375_3; + wire write_b_halfPipe_valid; + wire write_b_halfPipe_ready; + wire [1:0] write_b_halfPipe_payload_resp; + reg write_b_rValid; + wire write_b_halfPipe_fire; + reg [1:0] write_b_rData_resp; + wire io_pop_s2mPipe_valid; + reg io_pop_s2mPipe_ready; + wire [63:0] io_pop_s2mPipe_payload_data; + wire [7:0] io_pop_s2mPipe_payload_mask; + wire [3:0] io_pop_s2mPipe_payload_sink; + wire io_pop_s2mPipe_payload_last; + reg io_pop_rValidN; + reg [63:0] io_pop_rData_data; + reg [7:0] io_pop_rData_mask; + reg [3:0] io_pop_rData_sink; + reg io_pop_rData_last; + wire io_pop_s2mPipe_m2sPipe_valid; + wire io_pop_s2mPipe_m2sPipe_ready; + wire [63:0] io_pop_s2mPipe_m2sPipe_payload_data; + wire [7:0] io_pop_s2mPipe_m2sPipe_payload_mask; + wire [3:0] io_pop_s2mPipe_m2sPipe_payload_sink; + wire io_pop_s2mPipe_m2sPipe_payload_last; + reg io_pop_s2mPipe_rValid; + reg [63:0] io_pop_s2mPipe_rData_data; + reg [7:0] io_pop_s2mPipe_rData_mask; + reg [3:0] io_pop_s2mPipe_rData_sink; + reg io_pop_s2mPipe_rData_last; + wire when_Stream_l375_4; + wire io_outputs_0_s2mPipe_valid; + reg io_outputs_0_s2mPipe_ready; + wire [63:0] io_outputs_0_s2mPipe_payload_data; + wire [7:0] io_outputs_0_s2mPipe_payload_mask; + wire [3:0] io_outputs_0_s2mPipe_payload_sink; + wire io_outputs_0_s2mPipe_payload_last; + reg io_outputs_0_rValidN; + reg [63:0] io_outputs_0_rData_data; + reg [7:0] io_outputs_0_rData_mask; + reg [3:0] io_outputs_0_rData_sink; + reg io_outputs_0_rData_last; + wire outputsAdapter_0_ptr_valid; + wire outputsAdapter_0_ptr_ready; + wire [63:0] outputsAdapter_0_ptr_payload_data; + wire [7:0] outputsAdapter_0_ptr_payload_mask; + wire [3:0] outputsAdapter_0_ptr_payload_sink; + wire outputsAdapter_0_ptr_payload_last; + reg io_outputs_0_s2mPipe_rValid; + reg [63:0] io_outputs_0_s2mPipe_rData_data; + reg [7:0] io_outputs_0_s2mPipe_rData_mask; + reg [3:0] io_outputs_0_s2mPipe_rData_sink; + reg io_outputs_0_s2mPipe_rData_last; + wire when_Stream_l375_5; + + EfxDMA_Core core ( + .io_sgRead_cmd_valid (core_io_sgRead_cmd_valid ), //o + .io_sgRead_cmd_ready (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready ), //i + .io_sgRead_cmd_payload_last (core_io_sgRead_cmd_payload_last ), //o + .io_sgRead_cmd_payload_fragment_opcode (core_io_sgRead_cmd_payload_fragment_opcode ), //o + .io_sgRead_cmd_payload_fragment_address (core_io_sgRead_cmd_payload_fragment_address[31:0] ), //o + .io_sgRead_cmd_payload_fragment_length (core_io_sgRead_cmd_payload_fragment_length[4:0] ), //o + .io_sgRead_cmd_payload_fragment_context (core_io_sgRead_cmd_payload_fragment_context ), //o + .io_sgRead_rsp_valid (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid ), //i + .io_sgRead_rsp_ready (core_io_sgRead_rsp_ready ), //o + .io_sgRead_rsp_payload_last (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last ), //i + .io_sgRead_rsp_payload_fragment_opcode (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode ), //i + .io_sgRead_rsp_payload_fragment_data (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data[127:0] ), //i + .io_sgRead_rsp_payload_fragment_context (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context ), //i + .io_sgWrite_cmd_valid (core_io_sgWrite_cmd_valid ), //o + .io_sgWrite_cmd_ready (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready ), //i + .io_sgWrite_cmd_payload_last (core_io_sgWrite_cmd_payload_last ), //o + .io_sgWrite_cmd_payload_fragment_opcode (core_io_sgWrite_cmd_payload_fragment_opcode ), //o + .io_sgWrite_cmd_payload_fragment_address (core_io_sgWrite_cmd_payload_fragment_address[31:0] ), //o + .io_sgWrite_cmd_payload_fragment_length (core_io_sgWrite_cmd_payload_fragment_length[1:0] ), //o + .io_sgWrite_cmd_payload_fragment_data (core_io_sgWrite_cmd_payload_fragment_data[127:0] ), //o + .io_sgWrite_cmd_payload_fragment_mask (core_io_sgWrite_cmd_payload_fragment_mask[15:0] ), //o + .io_sgWrite_cmd_payload_fragment_context (core_io_sgWrite_cmd_payload_fragment_context ), //o + .io_sgWrite_rsp_valid (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid ), //i + .io_sgWrite_rsp_ready (core_io_sgWrite_rsp_ready ), //o + .io_sgWrite_rsp_payload_last (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last ), //i + .io_sgWrite_rsp_payload_fragment_opcode (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode ), //i + .io_sgWrite_rsp_payload_fragment_context (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context ), //i + .io_read_cmd_valid (core_io_read_cmd_valid ), //o + .io_read_cmd_ready (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready ), //i + .io_read_cmd_payload_last (core_io_read_cmd_payload_last ), //o + .io_read_cmd_payload_fragment_opcode (core_io_read_cmd_payload_fragment_opcode ), //o + .io_read_cmd_payload_fragment_address (core_io_read_cmd_payload_fragment_address[31:0] ), //o + .io_read_cmd_payload_fragment_length (core_io_read_cmd_payload_fragment_length[11:0] ), //o + .io_read_cmd_payload_fragment_context (core_io_read_cmd_payload_fragment_context[20:0] ), //o + .io_read_rsp_valid (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid ), //i + .io_read_rsp_ready (core_io_read_rsp_ready ), //o + .io_read_rsp_payload_last (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last ), //i + .io_read_rsp_payload_fragment_opcode (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode ), //i + .io_read_rsp_payload_fragment_data (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_data[127:0] ), //i + .io_read_rsp_payload_fragment_context (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context[20:0] ), //i + .io_write_cmd_valid (core_io_write_cmd_valid ), //o + .io_write_cmd_ready (io_write_cmd_rValidN ), //i + .io_write_cmd_payload_last (core_io_write_cmd_payload_last ), //o + .io_write_cmd_payload_fragment_opcode (core_io_write_cmd_payload_fragment_opcode ), //o + .io_write_cmd_payload_fragment_address (core_io_write_cmd_payload_fragment_address[31:0] ), //o + .io_write_cmd_payload_fragment_length (core_io_write_cmd_payload_fragment_length[11:0] ), //o + .io_write_cmd_payload_fragment_data (core_io_write_cmd_payload_fragment_data[127:0] ), //o + .io_write_cmd_payload_fragment_mask (core_io_write_cmd_payload_fragment_mask[15:0] ), //o + .io_write_cmd_payload_fragment_context (core_io_write_cmd_payload_fragment_context[12:0] ), //o + .io_write_rsp_valid (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid ), //i + .io_write_rsp_ready (core_io_write_rsp_ready ), //o + .io_write_rsp_payload_last (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last ), //i + .io_write_rsp_payload_fragment_opcode (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode ), //i + .io_write_rsp_payload_fragment_context (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context[12:0]), //i + .io_outputs_0_valid (core_io_outputs_0_valid ), //o + .io_outputs_0_ready (io_outputs_0_rValidN ), //i + .io_outputs_0_payload_data (core_io_outputs_0_payload_data[63:0] ), //o + .io_outputs_0_payload_mask (core_io_outputs_0_payload_mask[7:0] ), //o + .io_outputs_0_payload_sink (core_io_outputs_0_payload_sink[3:0] ), //o + .io_outputs_0_payload_last (core_io_outputs_0_payload_last ), //o + .io_inputs_0_valid (io_pop_s2mPipe_m2sPipe_valid ), //i + .io_inputs_0_ready (core_io_inputs_0_ready ), //o + .io_inputs_0_payload_data (io_pop_s2mPipe_m2sPipe_payload_data[63:0] ), //i + .io_inputs_0_payload_mask (io_pop_s2mPipe_m2sPipe_payload_mask[7:0] ), //i + .io_inputs_0_payload_sink (io_pop_s2mPipe_m2sPipe_payload_sink[3:0] ), //i + .io_inputs_0_payload_last (io_pop_s2mPipe_m2sPipe_payload_last ), //i + .io_interrupts (core_io_interrupts[1:0] ), //o + .io_ctrl_PADDR (withCtrlCc_apbCc_io_output_PADDR[13:0] ), //i + .io_ctrl_PSEL (withCtrlCc_apbCc_io_output_PSEL ), //i + .io_ctrl_PENABLE (withCtrlCc_apbCc_io_output_PENABLE ), //i + .io_ctrl_PREADY (core_io_ctrl_PREADY ), //o + .io_ctrl_PWRITE (withCtrlCc_apbCc_io_output_PWRITE ), //i + .io_ctrl_PWDATA (withCtrlCc_apbCc_io_output_PWDATA[31:0] ), //i + .io_ctrl_PRDATA (core_io_ctrl_PRDATA[31:0] ), //o + .io_ctrl_PSLVERROR (core_io_ctrl_PSLVERROR ), //o + .ll_0_descriptorUpdate (core_ll_0_descriptorUpdate ), //o + .ll_1_descriptorUpdate (core_ll_1_descriptorUpdate ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_Apb3CC withCtrlCc_apbCc ( + .io_input_PADDR (ctrl_PADDR[13:0] ), //i + .io_input_PSEL (ctrl_PSEL ), //i + .io_input_PENABLE (ctrl_PENABLE ), //i + .io_input_PREADY (withCtrlCc_apbCc_io_input_PREADY ), //o + .io_input_PWRITE (ctrl_PWRITE ), //i + .io_input_PWDATA (ctrl_PWDATA[31:0] ), //i + .io_input_PRDATA (withCtrlCc_apbCc_io_input_PRDATA[31:0] ), //o + .io_input_PSLVERROR (withCtrlCc_apbCc_io_input_PSLVERROR ), //o + .io_output_PADDR (withCtrlCc_apbCc_io_output_PADDR[13:0] ), //o + .io_output_PSEL (withCtrlCc_apbCc_io_output_PSEL ), //o + .io_output_PENABLE (withCtrlCc_apbCc_io_output_PENABLE ), //o + .io_output_PREADY (core_io_ctrl_PREADY ), //i + .io_output_PWRITE (withCtrlCc_apbCc_io_output_PWRITE ), //o + .io_output_PWDATA (withCtrlCc_apbCc_io_output_PWDATA[31:0]), //o + .io_output_PRDATA (core_io_ctrl_PRDATA[31:0] ), //i + .io_output_PSLVERROR (core_io_ctrl_PSLVERROR ), //i + .ctrl_clk (ctrl_clk ), //i + .ctrl_reset (ctrl_reset ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_6 io_interrupts_buffercc ( + .io_dataIn (core_io_interrupts[1:0] ), //i + .io_dataOut (io_interrupts_buffercc_io_dataOut[1:0]), //o + .ctrl_clk (ctrl_clk ), //i + .ctrl_reset (ctrl_reset ) //i + ); + EfxDMA_BmbSourceRemover readLogic_sourceRemover ( + .io_input_cmd_valid (readLogic_resized_cmd_valid ), //i + .io_input_cmd_ready (readLogic_sourceRemover_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (readLogic_resized_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (readLogic_resized_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (readLogic_resized_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (readLogic_resized_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (readLogic_resized_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_context (readLogic_resized_cmd_payload_fragment_context[20:0] ), //i + .io_input_rsp_valid (readLogic_sourceRemover_io_input_rsp_valid ), //o + .io_input_rsp_ready (readLogic_resized_rsp_ready ), //i + .io_input_rsp_payload_last (readLogic_sourceRemover_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (readLogic_sourceRemover_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (readLogic_sourceRemover_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (readLogic_sourceRemover_io_input_rsp_payload_fragment_data[127:0] ), //o + .io_input_rsp_payload_fragment_context (readLogic_sourceRemover_io_input_rsp_payload_fragment_context[20:0] ), //o + .io_output_cmd_valid (readLogic_sourceRemover_io_output_cmd_valid ), //o + .io_output_cmd_ready (readLogic_bridge_io_input_cmd_ready ), //i + .io_output_cmd_payload_last (readLogic_sourceRemover_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (readLogic_sourceRemover_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (readLogic_sourceRemover_io_output_cmd_payload_fragment_address[31:0]), //o + .io_output_cmd_payload_fragment_length (readLogic_sourceRemover_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_cmd_payload_fragment_context (readLogic_sourceRemover_io_output_cmd_payload_fragment_context[21:0]), //o + .io_output_rsp_valid (readLogic_bridge_io_input_rsp_valid ), //i + .io_output_rsp_ready (readLogic_sourceRemover_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (readLogic_bridge_io_input_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (readLogic_bridge_io_input_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (readLogic_bridge_io_input_rsp_payload_fragment_data[127:0] ), //i + .io_output_rsp_payload_fragment_context (readLogic_bridge_io_input_rsp_payload_fragment_context[21:0] ) //i + ); + EfxDMA_BmbToAxi4ReadOnlyBridge readLogic_bridge ( + .io_input_cmd_valid (readLogic_sourceRemover_io_output_cmd_valid ), //i + .io_input_cmd_ready (readLogic_bridge_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (readLogic_sourceRemover_io_output_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (readLogic_sourceRemover_io_output_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (readLogic_sourceRemover_io_output_cmd_payload_fragment_address[31:0]), //i + .io_input_cmd_payload_fragment_length (readLogic_sourceRemover_io_output_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_context (readLogic_sourceRemover_io_output_cmd_payload_fragment_context[21:0]), //i + .io_input_rsp_valid (readLogic_bridge_io_input_rsp_valid ), //o + .io_input_rsp_ready (readLogic_sourceRemover_io_output_rsp_ready ), //i + .io_input_rsp_payload_last (readLogic_bridge_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (readLogic_bridge_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (readLogic_bridge_io_input_rsp_payload_fragment_data[127:0] ), //o + .io_input_rsp_payload_fragment_context (readLogic_bridge_io_input_rsp_payload_fragment_context[21:0] ), //o + .io_output_ar_valid (readLogic_bridge_io_output_ar_valid ), //o + .io_output_ar_ready (readLogic_adapter_ar_ready ), //i + .io_output_ar_payload_addr (readLogic_bridge_io_output_ar_payload_addr[31:0] ), //o + .io_output_ar_payload_len (readLogic_bridge_io_output_ar_payload_len[7:0] ), //o + .io_output_ar_payload_size (readLogic_bridge_io_output_ar_payload_size[2:0] ), //o + .io_output_ar_payload_cache (readLogic_bridge_io_output_ar_payload_cache[3:0] ), //o + .io_output_ar_payload_prot (readLogic_bridge_io_output_ar_payload_prot[2:0] ), //o + .io_output_r_valid (readLogic_adapter_r_valid ), //i + .io_output_r_ready (readLogic_bridge_io_output_r_ready ), //o + .io_output_r_payload_data (readLogic_adapter_r_payload_data[127:0] ), //i + .io_output_r_payload_resp (readLogic_adapter_r_payload_resp[1:0] ), //i + .io_output_r_payload_last (readLogic_adapter_r_payload_last ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_BmbSourceRemover_1 writeLogic_sourceRemover ( + .io_input_cmd_valid (writeLogic_resized_cmd_valid ), //i + .io_input_cmd_ready (writeLogic_sourceRemover_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (writeLogic_resized_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (writeLogic_resized_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (writeLogic_resized_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (writeLogic_resized_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (writeLogic_resized_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_data (writeLogic_resized_cmd_payload_fragment_data[127:0] ), //i + .io_input_cmd_payload_fragment_mask (writeLogic_resized_cmd_payload_fragment_mask[15:0] ), //i + .io_input_cmd_payload_fragment_context (writeLogic_resized_cmd_payload_fragment_context[12:0] ), //i + .io_input_rsp_valid (writeLogic_sourceRemover_io_input_rsp_valid ), //o + .io_input_rsp_ready (writeLogic_resized_rsp_ready ), //i + .io_input_rsp_payload_last (writeLogic_sourceRemover_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (writeLogic_sourceRemover_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (writeLogic_sourceRemover_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_context (writeLogic_sourceRemover_io_input_rsp_payload_fragment_context[12:0] ), //o + .io_output_cmd_valid (writeLogic_sourceRemover_io_output_cmd_valid ), //o + .io_output_cmd_ready (writeLogic_bridge_io_input_cmd_ready ), //i + .io_output_cmd_payload_last (writeLogic_sourceRemover_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (writeLogic_sourceRemover_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (writeLogic_sourceRemover_io_output_cmd_payload_fragment_address[31:0]), //o + .io_output_cmd_payload_fragment_length (writeLogic_sourceRemover_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_cmd_payload_fragment_data (writeLogic_sourceRemover_io_output_cmd_payload_fragment_data[127:0] ), //o + .io_output_cmd_payload_fragment_mask (writeLogic_sourceRemover_io_output_cmd_payload_fragment_mask[15:0] ), //o + .io_output_cmd_payload_fragment_context (writeLogic_sourceRemover_io_output_cmd_payload_fragment_context[13:0]), //o + .io_output_rsp_valid (writeLogic_bridge_io_input_rsp_valid ), //i + .io_output_rsp_ready (writeLogic_sourceRemover_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (writeLogic_bridge_io_input_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (writeLogic_bridge_io_input_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_context (writeLogic_bridge_io_input_rsp_payload_fragment_context[13:0] ) //i + ); + EfxDMA_BmbToAxi4WriteOnlyBridge writeLogic_bridge ( + .io_input_cmd_valid (writeLogic_sourceRemover_io_output_cmd_valid ), //i + .io_input_cmd_ready (writeLogic_bridge_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (writeLogic_sourceRemover_io_output_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (writeLogic_sourceRemover_io_output_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (writeLogic_sourceRemover_io_output_cmd_payload_fragment_address[31:0]), //i + .io_input_cmd_payload_fragment_length (writeLogic_sourceRemover_io_output_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_data (writeLogic_sourceRemover_io_output_cmd_payload_fragment_data[127:0] ), //i + .io_input_cmd_payload_fragment_mask (writeLogic_sourceRemover_io_output_cmd_payload_fragment_mask[15:0] ), //i + .io_input_cmd_payload_fragment_context (writeLogic_sourceRemover_io_output_cmd_payload_fragment_context[13:0]), //i + .io_input_rsp_valid (writeLogic_bridge_io_input_rsp_valid ), //o + .io_input_rsp_ready (writeLogic_sourceRemover_io_output_rsp_ready ), //i + .io_input_rsp_payload_last (writeLogic_bridge_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (writeLogic_bridge_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_context (writeLogic_bridge_io_input_rsp_payload_fragment_context[13:0] ), //o + .io_output_aw_valid (writeLogic_bridge_io_output_aw_valid ), //o + .io_output_aw_ready (writeLogic_adapter_aw_ready ), //i + .io_output_aw_payload_addr (writeLogic_bridge_io_output_aw_payload_addr[31:0] ), //o + .io_output_aw_payload_len (writeLogic_bridge_io_output_aw_payload_len[7:0] ), //o + .io_output_aw_payload_size (writeLogic_bridge_io_output_aw_payload_size[2:0] ), //o + .io_output_aw_payload_cache (writeLogic_bridge_io_output_aw_payload_cache[3:0] ), //o + .io_output_aw_payload_prot (writeLogic_bridge_io_output_aw_payload_prot[2:0] ), //o + .io_output_w_valid (writeLogic_bridge_io_output_w_valid ), //o + .io_output_w_ready (writeLogic_adapter_w_ready ), //i + .io_output_w_payload_data (writeLogic_bridge_io_output_w_payload_data[127:0] ), //o + .io_output_w_payload_strb (writeLogic_bridge_io_output_w_payload_strb[15:0] ), //o + .io_output_w_payload_last (writeLogic_bridge_io_output_w_payload_last ), //o + .io_output_b_valid (writeLogic_adapter_b_valid ), //i + .io_output_b_ready (writeLogic_bridge_io_output_b_ready ), //o + .io_output_b_payload_resp (writeLogic_adapter_b_payload_resp[1:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_BsbUpSizerDense inputsAdapter_0_upsizer_logic ( + .io_input_valid (dat0_i_tvalid ), //i + .io_input_ready (inputsAdapter_0_upsizer_logic_io_input_ready ), //o + .io_input_payload_data (dat0_i_tdata[7:0] ), //i + .io_input_payload_mask (dat0_i_tkeep ), //i + .io_input_payload_sink (dat0_i_tdest[3:0] ), //i + .io_input_payload_last (dat0_i_tlast ), //i + .io_output_valid (inputsAdapter_0_upsizer_logic_io_output_valid ), //o + .io_output_ready (inputsAdapter_0_crossclock_fifo_io_push_ready ), //i + .io_output_payload_data (inputsAdapter_0_upsizer_logic_io_output_payload_data[63:0]), //o + .io_output_payload_mask (inputsAdapter_0_upsizer_logic_io_output_payload_mask[7:0] ), //o + .io_output_payload_sink (inputsAdapter_0_upsizer_logic_io_output_payload_sink[3:0] ), //o + .io_output_payload_last (inputsAdapter_0_upsizer_logic_io_output_payload_last ), //o + .dat0_i_clk (dat0_i_clk ), //i + .dat0_i_reset (dat0_i_reset ) //i + ); + EfxDMA_StreamFifoCC inputsAdapter_0_crossclock_fifo ( + .io_push_valid (inputsAdapter_0_upsizer_logic_io_output_valid ), //i + .io_push_ready (inputsAdapter_0_crossclock_fifo_io_push_ready ), //o + .io_push_payload_data (inputsAdapter_0_upsizer_logic_io_output_payload_data[63:0]), //i + .io_push_payload_mask (inputsAdapter_0_upsizer_logic_io_output_payload_mask[7:0] ), //i + .io_push_payload_sink (inputsAdapter_0_upsizer_logic_io_output_payload_sink[3:0] ), //i + .io_push_payload_last (inputsAdapter_0_upsizer_logic_io_output_payload_last ), //i + .io_pop_valid (inputsAdapter_0_crossclock_fifo_io_pop_valid ), //o + .io_pop_ready (io_pop_rValidN ), //i + .io_pop_payload_data (inputsAdapter_0_crossclock_fifo_io_pop_payload_data[63:0] ), //o + .io_pop_payload_mask (inputsAdapter_0_crossclock_fifo_io_pop_payload_mask[7:0] ), //o + .io_pop_payload_sink (inputsAdapter_0_crossclock_fifo_io_pop_payload_sink[3:0] ), //o + .io_pop_payload_last (inputsAdapter_0_crossclock_fifo_io_pop_payload_last ), //o + .io_pushOccupancy (inputsAdapter_0_crossclock_fifo_io_pushOccupancy[4:0] ), //o + .io_popOccupancy (inputsAdapter_0_crossclock_fifo_io_popOccupancy[4:0] ), //o + .dat0_i_clk (dat0_i_clk ), //i + .dat0_i_reset (dat0_i_reset ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_StreamFifoCC_1 outputsAdapter_0_crossclock_fifo ( + .io_push_valid (outputsAdapter_0_ptr_valid ), //i + .io_push_ready (outputsAdapter_0_crossclock_fifo_io_push_ready ), //o + .io_push_payload_data (outputsAdapter_0_ptr_payload_data[63:0] ), //i + .io_push_payload_mask (outputsAdapter_0_ptr_payload_mask[7:0] ), //i + .io_push_payload_sink (outputsAdapter_0_ptr_payload_sink[3:0] ), //i + .io_push_payload_last (outputsAdapter_0_ptr_payload_last ), //i + .io_pop_valid (outputsAdapter_0_crossclock_fifo_io_pop_valid ), //o + .io_pop_ready (outputsAdapter_0_sparseDownsizer_logic_io_input_ready ), //i + .io_pop_payload_data (outputsAdapter_0_crossclock_fifo_io_pop_payload_data[63:0]), //o + .io_pop_payload_mask (outputsAdapter_0_crossclock_fifo_io_pop_payload_mask[7:0] ), //o + .io_pop_payload_sink (outputsAdapter_0_crossclock_fifo_io_pop_payload_sink[3:0] ), //o + .io_pop_payload_last (outputsAdapter_0_crossclock_fifo_io_pop_payload_last ), //o + .io_pushOccupancy (outputsAdapter_0_crossclock_fifo_io_pushOccupancy[4:0] ), //o + .io_popOccupancy (outputsAdapter_0_crossclock_fifo_io_popOccupancy[4:0] ), //o + .clk (clk ), //i + .reset (reset ), //i + .dat1_o_clk (dat1_o_clk ), //i + .dat1_o_reset (dat1_o_reset ) //i + ); + EfxDMA_BsbDownSizerSparse outputsAdapter_0_sparseDownsizer_logic ( + .io_input_valid (outputsAdapter_0_crossclock_fifo_io_pop_valid ), //i + .io_input_ready (outputsAdapter_0_sparseDownsizer_logic_io_input_ready ), //o + .io_input_payload_data (outputsAdapter_0_crossclock_fifo_io_pop_payload_data[63:0] ), //i + .io_input_payload_mask (outputsAdapter_0_crossclock_fifo_io_pop_payload_mask[7:0] ), //i + .io_input_payload_sink (outputsAdapter_0_crossclock_fifo_io_pop_payload_sink[3:0] ), //i + .io_input_payload_last (outputsAdapter_0_crossclock_fifo_io_pop_payload_last ), //i + .io_output_valid (outputsAdapter_0_sparseDownsizer_logic_io_output_valid ), //o + .io_output_ready (dat1_o_tready ), //i + .io_output_payload_data (outputsAdapter_0_sparseDownsizer_logic_io_output_payload_data[7:0]), //o + .io_output_payload_mask (outputsAdapter_0_sparseDownsizer_logic_io_output_payload_mask ), //o + .io_output_payload_sink (outputsAdapter_0_sparseDownsizer_logic_io_output_payload_sink[3:0]), //o + .io_output_payload_last (outputsAdapter_0_sparseDownsizer_logic_io_output_payload_last ), //o + .dat1_o_clk (dat1_o_clk ), //i + .dat1_o_reset (dat1_o_reset ) //i + ); + EfxDMA_BmbArbiter interconnect_read_aggregated_arbiter ( + .io_inputs_0_cmd_valid (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid ), //i + .io_inputs_0_cmd_ready (interconnect_read_aggregated_arbiter_io_inputs_0_cmd_ready ), //o + .io_inputs_0_cmd_payload_last (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last ), //i + .io_inputs_0_cmd_payload_fragment_opcode (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode ), //i + .io_inputs_0_cmd_payload_fragment_address (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address[31:0]), //i + .io_inputs_0_cmd_payload_fragment_length (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length[4:0] ), //i + .io_inputs_0_cmd_payload_fragment_context (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context ), //i + .io_inputs_0_rsp_valid (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_valid ), //o + .io_inputs_0_rsp_ready (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready ), //i + .io_inputs_0_rsp_payload_last (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_last ), //o + .io_inputs_0_rsp_payload_fragment_opcode (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode ), //o + .io_inputs_0_rsp_payload_fragment_data (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_data[127:0] ), //o + .io_inputs_0_rsp_payload_fragment_context (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context ), //o + .io_inputs_1_cmd_valid (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid ), //i + .io_inputs_1_cmd_ready (interconnect_read_aggregated_arbiter_io_inputs_1_cmd_ready ), //o + .io_inputs_1_cmd_payload_last (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last ), //i + .io_inputs_1_cmd_payload_fragment_opcode (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode ), //i + .io_inputs_1_cmd_payload_fragment_address (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address[31:0]), //i + .io_inputs_1_cmd_payload_fragment_length (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length[11:0] ), //i + .io_inputs_1_cmd_payload_fragment_context (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context[20:0]), //i + .io_inputs_1_rsp_valid (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_valid ), //o + .io_inputs_1_rsp_ready (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready ), //i + .io_inputs_1_rsp_payload_last (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_last ), //o + .io_inputs_1_rsp_payload_fragment_opcode (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //o + .io_inputs_1_rsp_payload_fragment_data (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_data[127:0] ), //o + .io_inputs_1_rsp_payload_fragment_context (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context[20:0] ), //o + .io_output_cmd_valid (interconnect_read_aggregated_arbiter_io_output_cmd_valid ), //o + .io_output_cmd_ready (interconnect_read_aggregated_cmd_ready ), //i + .io_output_cmd_payload_last (interconnect_read_aggregated_arbiter_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_source (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_source ), //o + .io_output_cmd_payload_fragment_opcode (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_cmd_payload_fragment_context (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_context[20:0] ), //o + .io_output_rsp_valid (interconnect_read_aggregated_rsp_valid ), //i + .io_output_rsp_ready (interconnect_read_aggregated_arbiter_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (interconnect_read_aggregated_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_source (interconnect_read_aggregated_rsp_payload_fragment_source ), //i + .io_output_rsp_payload_fragment_opcode (interconnect_read_aggregated_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (interconnect_read_aggregated_rsp_payload_fragment_data[127:0] ), //i + .io_output_rsp_payload_fragment_context (interconnect_read_aggregated_rsp_payload_fragment_context[20:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_BmbArbiter_1 interconnect_write_aggregated_arbiter ( + .io_inputs_0_cmd_valid (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid ), //i + .io_inputs_0_cmd_ready (interconnect_write_aggregated_arbiter_io_inputs_0_cmd_ready ), //o + .io_inputs_0_cmd_payload_last (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last ), //i + .io_inputs_0_cmd_payload_fragment_opcode (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode ), //i + .io_inputs_0_cmd_payload_fragment_address (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address[31:0]), //i + .io_inputs_0_cmd_payload_fragment_length (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length[1:0] ), //i + .io_inputs_0_cmd_payload_fragment_data (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data[127:0] ), //i + .io_inputs_0_cmd_payload_fragment_mask (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask[15:0] ), //i + .io_inputs_0_cmd_payload_fragment_context (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context ), //i + .io_inputs_0_rsp_valid (interconnect_write_aggregated_arbiter_io_inputs_0_rsp_valid ), //o + .io_inputs_0_rsp_ready (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready ), //i + .io_inputs_0_rsp_payload_last (interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_last ), //o + .io_inputs_0_rsp_payload_fragment_opcode (interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode ), //o + .io_inputs_0_rsp_payload_fragment_context (interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context ), //o + .io_inputs_1_cmd_valid (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid ), //i + .io_inputs_1_cmd_ready (interconnect_write_aggregated_arbiter_io_inputs_1_cmd_ready ), //o + .io_inputs_1_cmd_payload_last (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last ), //i + .io_inputs_1_cmd_payload_fragment_opcode (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode ), //i + .io_inputs_1_cmd_payload_fragment_address (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address[31:0]), //i + .io_inputs_1_cmd_payload_fragment_length (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length[11:0] ), //i + .io_inputs_1_cmd_payload_fragment_data (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_data[127:0] ), //i + .io_inputs_1_cmd_payload_fragment_mask (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_mask[15:0] ), //i + .io_inputs_1_cmd_payload_fragment_context (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context[12:0]), //i + .io_inputs_1_rsp_valid (interconnect_write_aggregated_arbiter_io_inputs_1_rsp_valid ), //o + .io_inputs_1_rsp_ready (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready ), //i + .io_inputs_1_rsp_payload_last (interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_last ), //o + .io_inputs_1_rsp_payload_fragment_opcode (interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //o + .io_inputs_1_rsp_payload_fragment_context (interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context[12:0] ), //o + .io_output_cmd_valid (interconnect_write_aggregated_arbiter_io_output_cmd_valid ), //o + .io_output_cmd_ready (interconnect_write_aggregated_cmd_ready ), //i + .io_output_cmd_payload_last (interconnect_write_aggregated_arbiter_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_source (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_source ), //o + .io_output_cmd_payload_fragment_opcode (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_cmd_payload_fragment_data (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_data[127:0] ), //o + .io_output_cmd_payload_fragment_mask (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_mask[15:0] ), //o + .io_output_cmd_payload_fragment_context (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_context[12:0] ), //o + .io_output_rsp_valid (interconnect_write_aggregated_rsp_valid ), //i + .io_output_rsp_ready (interconnect_write_aggregated_arbiter_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (interconnect_write_aggregated_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_source (interconnect_write_aggregated_rsp_payload_fragment_source ), //i + .io_output_rsp_payload_fragment_opcode (interconnect_write_aggregated_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_context (interconnect_write_aggregated_rsp_payload_fragment_context[12:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign io_0_descriptorUpdate = core_ll_0_descriptorUpdate; + assign io_1_descriptorUpdate = core_ll_1_descriptorUpdate; + assign ctrl_PREADY = withCtrlCc_apbCc_io_input_PREADY; + assign ctrl_PRDATA = withCtrlCc_apbCc_io_input_PRDATA; + assign ctrl_PSLVERROR = withCtrlCc_apbCc_io_input_PSLVERROR; + assign ctrl_interrupts = io_interrupts_buffercc_io_dataOut; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid = core_io_read_cmd_valid; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready = core_io_read_rsp_ready; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last = core_io_read_cmd_payload_last; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode = core_io_read_cmd_payload_fragment_opcode; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address = core_io_read_cmd_payload_fragment_address; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length = core_io_read_cmd_payload_fragment_length; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context = core_io_read_cmd_payload_fragment_context; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid = core_io_sgRead_cmd_valid; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready = core_io_sgRead_rsp_ready; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last = core_io_sgRead_cmd_payload_last; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode = core_io_sgRead_cmd_payload_fragment_opcode; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address = core_io_sgRead_cmd_payload_fragment_address; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length = core_io_sgRead_cmd_payload_fragment_length; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context = core_io_sgRead_cmd_payload_fragment_context; + assign io_write_cmd_s2mPipe_valid = (core_io_write_cmd_valid || (! io_write_cmd_rValidN)); + assign io_write_cmd_s2mPipe_payload_last = (io_write_cmd_rValidN ? core_io_write_cmd_payload_last : io_write_cmd_rData_last); + assign io_write_cmd_s2mPipe_payload_fragment_opcode = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_opcode : io_write_cmd_rData_fragment_opcode); + assign io_write_cmd_s2mPipe_payload_fragment_address = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_address : io_write_cmd_rData_fragment_address); + assign io_write_cmd_s2mPipe_payload_fragment_length = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_length : io_write_cmd_rData_fragment_length); + assign io_write_cmd_s2mPipe_payload_fragment_data = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_data : io_write_cmd_rData_fragment_data); + assign io_write_cmd_s2mPipe_payload_fragment_mask = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_mask : io_write_cmd_rData_fragment_mask); + assign io_write_cmd_s2mPipe_payload_fragment_context = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_context : io_write_cmd_rData_fragment_context); + always @(*) begin + io_write_cmd_s2mPipe_ready = io_write_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l375) begin + io_write_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! io_write_cmd_s2mPipe_m2sPipe_valid); + assign io_write_cmd_s2mPipe_m2sPipe_valid = io_write_cmd_s2mPipe_rValid; + assign io_write_cmd_s2mPipe_m2sPipe_payload_last = io_write_cmd_s2mPipe_rData_last; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_opcode = io_write_cmd_s2mPipe_rData_fragment_opcode; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_address = io_write_cmd_s2mPipe_rData_fragment_address; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_length = io_write_cmd_s2mPipe_rData_fragment_length; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_data = io_write_cmd_s2mPipe_rData_fragment_data; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_mask = io_write_cmd_s2mPipe_rData_fragment_mask; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_context = io_write_cmd_s2mPipe_rData_fragment_context; + assign io_write_cmd_s2mPipe_m2sPipe_ready = interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid = io_write_cmd_s2mPipe_m2sPipe_valid; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready = core_io_write_rsp_ready; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last = io_write_cmd_s2mPipe_m2sPipe_payload_last; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_opcode; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_address; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_length; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_data = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_data; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_mask = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_mask; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_context; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid = core_io_sgWrite_cmd_valid; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready = core_io_sgWrite_rsp_ready; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last = core_io_sgWrite_cmd_payload_last; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode = core_io_sgWrite_cmd_payload_fragment_opcode; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address = core_io_sgWrite_cmd_payload_fragment_address; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length = core_io_sgWrite_cmd_payload_fragment_length; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data = core_io_sgWrite_cmd_payload_fragment_data; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask = core_io_sgWrite_cmd_payload_fragment_mask; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context = core_io_sgWrite_cmd_payload_fragment_context; + assign interconnect_read_aggregated_cmd_halfPipe_fire = (interconnect_read_aggregated_cmd_halfPipe_valid && interconnect_read_aggregated_cmd_halfPipe_ready); + assign interconnect_read_aggregated_cmd_ready = (! interconnect_read_aggregated_cmd_rValid); + assign interconnect_read_aggregated_cmd_halfPipe_valid = interconnect_read_aggregated_cmd_rValid; + assign interconnect_read_aggregated_cmd_halfPipe_payload_last = interconnect_read_aggregated_cmd_rData_last; + assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_source = interconnect_read_aggregated_cmd_rData_fragment_source; + assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_opcode = interconnect_read_aggregated_cmd_rData_fragment_opcode; + assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_address = interconnect_read_aggregated_cmd_rData_fragment_address; + assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_length = interconnect_read_aggregated_cmd_rData_fragment_length; + assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_context = interconnect_read_aggregated_cmd_rData_fragment_context; + assign readLogic_resized_cmd_valid = interconnect_read_aggregated_cmd_halfPipe_valid; + assign interconnect_read_aggregated_cmd_halfPipe_ready = readLogic_resized_cmd_ready; + assign readLogic_resized_cmd_payload_last = interconnect_read_aggregated_cmd_halfPipe_payload_last; + assign readLogic_resized_cmd_payload_fragment_source = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_source; + assign readLogic_resized_cmd_payload_fragment_opcode = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_opcode; + assign readLogic_resized_cmd_payload_fragment_address = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_address; + assign readLogic_resized_cmd_payload_fragment_length = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_length; + assign readLogic_resized_cmd_payload_fragment_context = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_context; + assign readLogic_resized_rsp_combStage_valid = readLogic_resized_rsp_valid; + assign readLogic_resized_rsp_ready = readLogic_resized_rsp_combStage_ready; + assign readLogic_resized_rsp_combStage_payload_last = readLogic_resized_rsp_payload_last; + assign readLogic_resized_rsp_combStage_payload_fragment_source = readLogic_resized_rsp_payload_fragment_source; + assign readLogic_resized_rsp_combStage_payload_fragment_opcode = readLogic_resized_rsp_payload_fragment_opcode; + assign readLogic_resized_rsp_combStage_payload_fragment_data = readLogic_resized_rsp_payload_fragment_data; + assign readLogic_resized_rsp_combStage_payload_fragment_context = readLogic_resized_rsp_payload_fragment_context; + assign interconnect_read_aggregated_rsp_valid = readLogic_resized_rsp_combStage_valid; + assign readLogic_resized_rsp_combStage_ready = interconnect_read_aggregated_rsp_ready; + assign interconnect_read_aggregated_rsp_payload_last = readLogic_resized_rsp_combStage_payload_last; + assign interconnect_read_aggregated_rsp_payload_fragment_source = readLogic_resized_rsp_combStage_payload_fragment_source; + assign interconnect_read_aggregated_rsp_payload_fragment_opcode = readLogic_resized_rsp_combStage_payload_fragment_opcode; + assign interconnect_read_aggregated_rsp_payload_fragment_data = readLogic_resized_rsp_combStage_payload_fragment_data; + assign interconnect_read_aggregated_rsp_payload_fragment_context = readLogic_resized_rsp_combStage_payload_fragment_context; + assign readLogic_resized_cmd_ready = readLogic_sourceRemover_io_input_cmd_ready; + assign readLogic_resized_rsp_valid = readLogic_sourceRemover_io_input_rsp_valid; + assign readLogic_resized_rsp_payload_last = readLogic_sourceRemover_io_input_rsp_payload_last; + assign readLogic_resized_rsp_payload_fragment_source = readLogic_sourceRemover_io_input_rsp_payload_fragment_source; + assign readLogic_resized_rsp_payload_fragment_opcode = readLogic_sourceRemover_io_input_rsp_payload_fragment_opcode; + assign readLogic_resized_rsp_payload_fragment_data = readLogic_sourceRemover_io_input_rsp_payload_fragment_data; + assign readLogic_resized_rsp_payload_fragment_context = readLogic_sourceRemover_io_input_rsp_payload_fragment_context; + assign readLogic_adapter_ar_valid = readLogic_bridge_io_output_ar_valid; + assign readLogic_adapter_ar_payload_addr = readLogic_bridge_io_output_ar_payload_addr; + assign _zz_readLogic_adapter_ar_payload_region[3 : 0] = 4'b0000; + assign readLogic_adapter_ar_payload_region = _zz_readLogic_adapter_ar_payload_region; + assign readLogic_adapter_ar_payload_len = readLogic_bridge_io_output_ar_payload_len; + assign readLogic_adapter_ar_payload_size = readLogic_bridge_io_output_ar_payload_size; + assign readLogic_adapter_ar_payload_burst = 2'b01; + assign readLogic_adapter_ar_payload_lock = 1'b0; + assign readLogic_adapter_ar_payload_cache = readLogic_bridge_io_output_ar_payload_cache; + assign readLogic_adapter_ar_payload_qos = 4'b0000; + assign readLogic_adapter_ar_payload_prot = readLogic_bridge_io_output_ar_payload_prot; + assign readLogic_adapter_r_ready = readLogic_bridge_io_output_r_ready; + assign readLogic_adapter_ar_halfPipe_fire = (readLogic_adapter_ar_halfPipe_valid && readLogic_adapter_ar_halfPipe_ready); + assign readLogic_adapter_ar_ready = (! readLogic_adapter_ar_rValid); + assign readLogic_adapter_ar_halfPipe_valid = readLogic_adapter_ar_rValid; + assign readLogic_adapter_ar_halfPipe_payload_addr = readLogic_adapter_ar_rData_addr; + assign readLogic_adapter_ar_halfPipe_payload_region = readLogic_adapter_ar_rData_region; + assign readLogic_adapter_ar_halfPipe_payload_len = readLogic_adapter_ar_rData_len; + assign readLogic_adapter_ar_halfPipe_payload_size = readLogic_adapter_ar_rData_size; + assign readLogic_adapter_ar_halfPipe_payload_burst = readLogic_adapter_ar_rData_burst; + assign readLogic_adapter_ar_halfPipe_payload_lock = readLogic_adapter_ar_rData_lock; + assign readLogic_adapter_ar_halfPipe_payload_cache = readLogic_adapter_ar_rData_cache; + assign readLogic_adapter_ar_halfPipe_payload_qos = readLogic_adapter_ar_rData_qos; + assign readLogic_adapter_ar_halfPipe_payload_prot = readLogic_adapter_ar_rData_prot; + assign read_arvalid = readLogic_adapter_ar_halfPipe_valid; + assign readLogic_adapter_ar_halfPipe_ready = read_arready; + assign read_araddr = readLogic_adapter_ar_halfPipe_payload_addr; + assign read_arregion = readLogic_adapter_ar_halfPipe_payload_region; + assign read_arlen = readLogic_adapter_ar_halfPipe_payload_len; + assign read_arsize = readLogic_adapter_ar_halfPipe_payload_size; + assign read_arburst = readLogic_adapter_ar_halfPipe_payload_burst; + assign read_arlock = readLogic_adapter_ar_halfPipe_payload_lock; + assign read_arcache = readLogic_adapter_ar_halfPipe_payload_cache; + assign read_arqos = readLogic_adapter_ar_halfPipe_payload_qos; + assign read_arprot = readLogic_adapter_ar_halfPipe_payload_prot; + assign read_rready = read_r_rValidN; + assign read_r_s2mPipe_valid = (read_rvalid || (! read_r_rValidN)); + assign read_r_s2mPipe_payload_data = (read_r_rValidN ? read_rdata : read_r_rData_data); + assign read_r_s2mPipe_payload_resp = (read_r_rValidN ? read_rresp : read_r_rData_resp); + assign read_r_s2mPipe_payload_last = (read_r_rValidN ? read_rlast : read_r_rData_last); + always @(*) begin + read_r_s2mPipe_ready = readLogic_beforeQueue_ready; + if(when_Stream_l375_1) begin + read_r_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375_1 = (! readLogic_beforeQueue_valid); + assign readLogic_beforeQueue_valid = read_r_s2mPipe_rValid; + assign readLogic_beforeQueue_payload_data = read_r_s2mPipe_rData_data; + assign readLogic_beforeQueue_payload_resp = read_r_s2mPipe_rData_resp; + assign readLogic_beforeQueue_payload_last = read_r_s2mPipe_rData_last; + assign readLogic_adapter_r_valid = readLogic_beforeQueue_valid; + assign readLogic_beforeQueue_ready = readLogic_adapter_r_ready; + assign readLogic_adapter_r_payload_data = readLogic_beforeQueue_payload_data; + assign readLogic_adapter_r_payload_resp = readLogic_beforeQueue_payload_resp; + assign readLogic_adapter_r_payload_last = readLogic_beforeQueue_payload_last; + always @(*) begin + interconnect_write_aggregated_cmd_ready = interconnect_write_aggregated_cmd_m2sPipe_ready; + if(when_Stream_l375_2) begin + interconnect_write_aggregated_cmd_ready = 1'b1; + end + end + + assign when_Stream_l375_2 = (! interconnect_write_aggregated_cmd_m2sPipe_valid); + assign interconnect_write_aggregated_cmd_m2sPipe_valid = interconnect_write_aggregated_cmd_rValid; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_last = interconnect_write_aggregated_cmd_rData_last; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_source = interconnect_write_aggregated_cmd_rData_fragment_source; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_opcode = interconnect_write_aggregated_cmd_rData_fragment_opcode; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_address = interconnect_write_aggregated_cmd_rData_fragment_address; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_length = interconnect_write_aggregated_cmd_rData_fragment_length; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_data = interconnect_write_aggregated_cmd_rData_fragment_data; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_mask = interconnect_write_aggregated_cmd_rData_fragment_mask; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_context = interconnect_write_aggregated_cmd_rData_fragment_context; + assign writeLogic_resized_cmd_valid = interconnect_write_aggregated_cmd_m2sPipe_valid; + assign interconnect_write_aggregated_cmd_m2sPipe_ready = writeLogic_resized_cmd_ready; + assign writeLogic_resized_cmd_payload_last = interconnect_write_aggregated_cmd_m2sPipe_payload_last; + assign writeLogic_resized_cmd_payload_fragment_source = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_source; + assign writeLogic_resized_cmd_payload_fragment_opcode = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_opcode; + assign writeLogic_resized_cmd_payload_fragment_address = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_address; + assign writeLogic_resized_cmd_payload_fragment_length = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_length; + assign writeLogic_resized_cmd_payload_fragment_data = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_data; + assign writeLogic_resized_cmd_payload_fragment_mask = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_mask; + assign writeLogic_resized_cmd_payload_fragment_context = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_context; + assign writeLogic_resized_rsp_combStage_valid = writeLogic_resized_rsp_valid; + assign writeLogic_resized_rsp_ready = writeLogic_resized_rsp_combStage_ready; + assign writeLogic_resized_rsp_combStage_payload_last = writeLogic_resized_rsp_payload_last; + assign writeLogic_resized_rsp_combStage_payload_fragment_source = writeLogic_resized_rsp_payload_fragment_source; + assign writeLogic_resized_rsp_combStage_payload_fragment_opcode = writeLogic_resized_rsp_payload_fragment_opcode; + assign writeLogic_resized_rsp_combStage_payload_fragment_context = writeLogic_resized_rsp_payload_fragment_context; + assign interconnect_write_aggregated_rsp_valid = writeLogic_resized_rsp_combStage_valid; + assign writeLogic_resized_rsp_combStage_ready = interconnect_write_aggregated_rsp_ready; + assign interconnect_write_aggregated_rsp_payload_last = writeLogic_resized_rsp_combStage_payload_last; + assign interconnect_write_aggregated_rsp_payload_fragment_source = writeLogic_resized_rsp_combStage_payload_fragment_source; + assign interconnect_write_aggregated_rsp_payload_fragment_opcode = writeLogic_resized_rsp_combStage_payload_fragment_opcode; + assign interconnect_write_aggregated_rsp_payload_fragment_context = writeLogic_resized_rsp_combStage_payload_fragment_context; + assign writeLogic_resized_cmd_ready = writeLogic_sourceRemover_io_input_cmd_ready; + assign writeLogic_resized_rsp_valid = writeLogic_sourceRemover_io_input_rsp_valid; + assign writeLogic_resized_rsp_payload_last = writeLogic_sourceRemover_io_input_rsp_payload_last; + assign writeLogic_resized_rsp_payload_fragment_source = writeLogic_sourceRemover_io_input_rsp_payload_fragment_source; + assign writeLogic_resized_rsp_payload_fragment_opcode = writeLogic_sourceRemover_io_input_rsp_payload_fragment_opcode; + assign writeLogic_resized_rsp_payload_fragment_context = writeLogic_sourceRemover_io_input_rsp_payload_fragment_context; + assign writeLogic_adapter_aw_valid = writeLogic_bridge_io_output_aw_valid; + assign writeLogic_adapter_aw_payload_addr = writeLogic_bridge_io_output_aw_payload_addr; + assign _zz_writeLogic_adapter_aw_payload_region[3 : 0] = 4'b0000; + assign writeLogic_adapter_aw_payload_region = _zz_writeLogic_adapter_aw_payload_region; + assign writeLogic_adapter_aw_payload_len = writeLogic_bridge_io_output_aw_payload_len; + assign writeLogic_adapter_aw_payload_size = writeLogic_bridge_io_output_aw_payload_size; + assign writeLogic_adapter_aw_payload_burst = 2'b01; + assign writeLogic_adapter_aw_payload_lock = 1'b0; + assign writeLogic_adapter_aw_payload_cache = writeLogic_bridge_io_output_aw_payload_cache; + assign writeLogic_adapter_aw_payload_qos = 4'b0000; + assign writeLogic_adapter_aw_payload_prot = writeLogic_bridge_io_output_aw_payload_prot; + assign writeLogic_adapter_w_valid = writeLogic_bridge_io_output_w_valid; + assign writeLogic_adapter_w_payload_data = writeLogic_bridge_io_output_w_payload_data; + assign writeLogic_adapter_w_payload_strb = writeLogic_bridge_io_output_w_payload_strb; + assign writeLogic_adapter_w_payload_last = writeLogic_bridge_io_output_w_payload_last; + assign writeLogic_adapter_b_ready = writeLogic_bridge_io_output_b_ready; + assign writeLogic_adapter_aw_halfPipe_fire = (writeLogic_adapter_aw_halfPipe_valid && writeLogic_adapter_aw_halfPipe_ready); + assign writeLogic_adapter_aw_ready = (! writeLogic_adapter_aw_rValid); + assign writeLogic_adapter_aw_halfPipe_valid = writeLogic_adapter_aw_rValid; + assign writeLogic_adapter_aw_halfPipe_payload_addr = writeLogic_adapter_aw_rData_addr; + assign writeLogic_adapter_aw_halfPipe_payload_region = writeLogic_adapter_aw_rData_region; + assign writeLogic_adapter_aw_halfPipe_payload_len = writeLogic_adapter_aw_rData_len; + assign writeLogic_adapter_aw_halfPipe_payload_size = writeLogic_adapter_aw_rData_size; + assign writeLogic_adapter_aw_halfPipe_payload_burst = writeLogic_adapter_aw_rData_burst; + assign writeLogic_adapter_aw_halfPipe_payload_lock = writeLogic_adapter_aw_rData_lock; + assign writeLogic_adapter_aw_halfPipe_payload_cache = writeLogic_adapter_aw_rData_cache; + assign writeLogic_adapter_aw_halfPipe_payload_qos = writeLogic_adapter_aw_rData_qos; + assign writeLogic_adapter_aw_halfPipe_payload_prot = writeLogic_adapter_aw_rData_prot; + assign write_awvalid = writeLogic_adapter_aw_halfPipe_valid; + assign writeLogic_adapter_aw_halfPipe_ready = write_awready; + assign write_awaddr = writeLogic_adapter_aw_halfPipe_payload_addr; + assign write_awregion = writeLogic_adapter_aw_halfPipe_payload_region; + assign write_awlen = writeLogic_adapter_aw_halfPipe_payload_len; + assign write_awsize = writeLogic_adapter_aw_halfPipe_payload_size; + assign write_awburst = writeLogic_adapter_aw_halfPipe_payload_burst; + assign write_awlock = writeLogic_adapter_aw_halfPipe_payload_lock; + assign write_awcache = writeLogic_adapter_aw_halfPipe_payload_cache; + assign write_awqos = writeLogic_adapter_aw_halfPipe_payload_qos; + assign write_awprot = writeLogic_adapter_aw_halfPipe_payload_prot; + assign writeLogic_adapter_w_ready = writeLogic_adapter_w_rValidN; + assign writeLogic_adapter_w_s2mPipe_valid = (writeLogic_adapter_w_valid || (! writeLogic_adapter_w_rValidN)); + assign writeLogic_adapter_w_s2mPipe_payload_data = (writeLogic_adapter_w_rValidN ? writeLogic_adapter_w_payload_data : writeLogic_adapter_w_rData_data); + assign writeLogic_adapter_w_s2mPipe_payload_strb = (writeLogic_adapter_w_rValidN ? writeLogic_adapter_w_payload_strb : writeLogic_adapter_w_rData_strb); + assign writeLogic_adapter_w_s2mPipe_payload_last = (writeLogic_adapter_w_rValidN ? writeLogic_adapter_w_payload_last : writeLogic_adapter_w_rData_last); + always @(*) begin + writeLogic_adapter_w_s2mPipe_ready = writeLogic_adapter_w_s2mPipe_m2sPipe_ready; + if(when_Stream_l375_3) begin + writeLogic_adapter_w_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375_3 = (! writeLogic_adapter_w_s2mPipe_m2sPipe_valid); + assign writeLogic_adapter_w_s2mPipe_m2sPipe_valid = writeLogic_adapter_w_s2mPipe_rValid; + assign writeLogic_adapter_w_s2mPipe_m2sPipe_payload_data = writeLogic_adapter_w_s2mPipe_rData_data; + assign writeLogic_adapter_w_s2mPipe_m2sPipe_payload_strb = writeLogic_adapter_w_s2mPipe_rData_strb; + assign writeLogic_adapter_w_s2mPipe_m2sPipe_payload_last = writeLogic_adapter_w_s2mPipe_rData_last; + assign write_wvalid = writeLogic_adapter_w_s2mPipe_m2sPipe_valid; + assign writeLogic_adapter_w_s2mPipe_m2sPipe_ready = write_wready; + assign write_wdata = writeLogic_adapter_w_s2mPipe_m2sPipe_payload_data; + assign write_wstrb = writeLogic_adapter_w_s2mPipe_m2sPipe_payload_strb; + assign write_wlast = writeLogic_adapter_w_s2mPipe_m2sPipe_payload_last; + assign write_b_halfPipe_fire = (write_b_halfPipe_valid && write_b_halfPipe_ready); + assign write_bready = (! write_b_rValid); + assign write_b_halfPipe_valid = write_b_rValid; + assign write_b_halfPipe_payload_resp = write_b_rData_resp; + assign writeLogic_adapter_b_valid = write_b_halfPipe_valid; + assign write_b_halfPipe_ready = writeLogic_adapter_b_ready; + assign writeLogic_adapter_b_payload_resp = write_b_halfPipe_payload_resp; + assign dat0_i_tready = inputsAdapter_0_upsizer_logic_io_input_ready; + assign io_pop_s2mPipe_valid = (inputsAdapter_0_crossclock_fifo_io_pop_valid || (! io_pop_rValidN)); + assign io_pop_s2mPipe_payload_data = (io_pop_rValidN ? inputsAdapter_0_crossclock_fifo_io_pop_payload_data : io_pop_rData_data); + assign io_pop_s2mPipe_payload_mask = (io_pop_rValidN ? inputsAdapter_0_crossclock_fifo_io_pop_payload_mask : io_pop_rData_mask); + assign io_pop_s2mPipe_payload_sink = (io_pop_rValidN ? inputsAdapter_0_crossclock_fifo_io_pop_payload_sink : io_pop_rData_sink); + assign io_pop_s2mPipe_payload_last = (io_pop_rValidN ? inputsAdapter_0_crossclock_fifo_io_pop_payload_last : io_pop_rData_last); + always @(*) begin + io_pop_s2mPipe_ready = io_pop_s2mPipe_m2sPipe_ready; + if(when_Stream_l375_4) begin + io_pop_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375_4 = (! io_pop_s2mPipe_m2sPipe_valid); + assign io_pop_s2mPipe_m2sPipe_valid = io_pop_s2mPipe_rValid; + assign io_pop_s2mPipe_m2sPipe_payload_data = io_pop_s2mPipe_rData_data; + assign io_pop_s2mPipe_m2sPipe_payload_mask = io_pop_s2mPipe_rData_mask; + assign io_pop_s2mPipe_m2sPipe_payload_sink = io_pop_s2mPipe_rData_sink; + assign io_pop_s2mPipe_m2sPipe_payload_last = io_pop_s2mPipe_rData_last; + assign io_pop_s2mPipe_m2sPipe_ready = core_io_inputs_0_ready; + assign io_outputs_0_s2mPipe_valid = (core_io_outputs_0_valid || (! io_outputs_0_rValidN)); + assign io_outputs_0_s2mPipe_payload_data = (io_outputs_0_rValidN ? core_io_outputs_0_payload_data : io_outputs_0_rData_data); + assign io_outputs_0_s2mPipe_payload_mask = (io_outputs_0_rValidN ? core_io_outputs_0_payload_mask : io_outputs_0_rData_mask); + assign io_outputs_0_s2mPipe_payload_sink = (io_outputs_0_rValidN ? core_io_outputs_0_payload_sink : io_outputs_0_rData_sink); + assign io_outputs_0_s2mPipe_payload_last = (io_outputs_0_rValidN ? core_io_outputs_0_payload_last : io_outputs_0_rData_last); + always @(*) begin + io_outputs_0_s2mPipe_ready = outputsAdapter_0_ptr_ready; + if(when_Stream_l375_5) begin + io_outputs_0_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375_5 = (! outputsAdapter_0_ptr_valid); + assign outputsAdapter_0_ptr_valid = io_outputs_0_s2mPipe_rValid; + assign outputsAdapter_0_ptr_payload_data = io_outputs_0_s2mPipe_rData_data; + assign outputsAdapter_0_ptr_payload_mask = io_outputs_0_s2mPipe_rData_mask; + assign outputsAdapter_0_ptr_payload_sink = io_outputs_0_s2mPipe_rData_sink; + assign outputsAdapter_0_ptr_payload_last = io_outputs_0_s2mPipe_rData_last; + assign outputsAdapter_0_ptr_ready = outputsAdapter_0_crossclock_fifo_io_push_ready; + assign dat1_o_tvalid = outputsAdapter_0_sparseDownsizer_logic_io_output_valid; + assign dat1_o_tdata = outputsAdapter_0_sparseDownsizer_logic_io_output_payload_data; + assign dat1_o_tkeep = outputsAdapter_0_sparseDownsizer_logic_io_output_payload_mask; + assign dat1_o_tdest = outputsAdapter_0_sparseDownsizer_logic_io_output_payload_sink; + assign dat1_o_tlast = outputsAdapter_0_sparseDownsizer_logic_io_output_payload_last; + assign interconnect_read_aggregated_cmd_valid = interconnect_read_aggregated_arbiter_io_output_cmd_valid; + assign interconnect_read_aggregated_rsp_ready = interconnect_read_aggregated_arbiter_io_output_rsp_ready; + assign interconnect_read_aggregated_cmd_payload_last = interconnect_read_aggregated_arbiter_io_output_cmd_payload_last; + assign interconnect_read_aggregated_cmd_payload_fragment_source = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_source; + assign interconnect_read_aggregated_cmd_payload_fragment_opcode = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_opcode; + assign interconnect_read_aggregated_cmd_payload_fragment_address = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_address; + assign interconnect_read_aggregated_cmd_payload_fragment_length = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_length; + assign interconnect_read_aggregated_cmd_payload_fragment_context = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_context; + assign interconnect_write_aggregated_cmd_valid = interconnect_write_aggregated_arbiter_io_output_cmd_valid; + assign interconnect_write_aggregated_rsp_ready = interconnect_write_aggregated_arbiter_io_output_rsp_ready; + assign interconnect_write_aggregated_cmd_payload_last = interconnect_write_aggregated_arbiter_io_output_cmd_payload_last; + assign interconnect_write_aggregated_cmd_payload_fragment_source = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_source; + assign interconnect_write_aggregated_cmd_payload_fragment_opcode = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_opcode; + assign interconnect_write_aggregated_cmd_payload_fragment_address = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_address; + assign interconnect_write_aggregated_cmd_payload_fragment_length = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_length; + assign interconnect_write_aggregated_cmd_payload_fragment_data = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_data; + assign interconnect_write_aggregated_cmd_payload_fragment_mask = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_mask; + assign interconnect_write_aggregated_cmd_payload_fragment_context = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_context; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready = interconnect_read_aggregated_arbiter_io_inputs_0_cmd_ready; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_valid; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_last; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_data; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready = interconnect_read_aggregated_arbiter_io_inputs_1_cmd_ready; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_valid; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_last; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_data = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_data; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready = interconnect_write_aggregated_arbiter_io_inputs_0_cmd_ready; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid = interconnect_write_aggregated_arbiter_io_inputs_0_rsp_valid; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last = interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_last; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode = interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context = interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready = interconnect_write_aggregated_arbiter_io_inputs_1_cmd_ready; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid = interconnect_write_aggregated_arbiter_io_inputs_1_rsp_valid; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last = interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_last; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode = interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context = interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context; + always @(posedge clk) begin + if(reset) begin + io_write_cmd_rValidN <= 1'b1; + io_write_cmd_s2mPipe_rValid <= 1'b0; + interconnect_read_aggregated_cmd_rValid <= 1'b0; + readLogic_adapter_ar_rValid <= 1'b0; + read_r_rValidN <= 1'b1; + read_r_s2mPipe_rValid <= 1'b0; + interconnect_write_aggregated_cmd_rValid <= 1'b0; + writeLogic_adapter_aw_rValid <= 1'b0; + writeLogic_adapter_w_rValidN <= 1'b1; + writeLogic_adapter_w_s2mPipe_rValid <= 1'b0; + write_b_rValid <= 1'b0; + io_pop_rValidN <= 1'b1; + io_pop_s2mPipe_rValid <= 1'b0; + io_outputs_0_rValidN <= 1'b1; + io_outputs_0_s2mPipe_rValid <= 1'b0; + end else begin + if(core_io_write_cmd_valid) begin + io_write_cmd_rValidN <= 1'b0; + end + if(io_write_cmd_s2mPipe_ready) begin + io_write_cmd_rValidN <= 1'b1; + end + if(io_write_cmd_s2mPipe_ready) begin + io_write_cmd_s2mPipe_rValid <= io_write_cmd_s2mPipe_valid; + end + if(interconnect_read_aggregated_cmd_valid) begin + interconnect_read_aggregated_cmd_rValid <= 1'b1; + end + if(interconnect_read_aggregated_cmd_halfPipe_fire) begin + interconnect_read_aggregated_cmd_rValid <= 1'b0; + end + if(readLogic_adapter_ar_valid) begin + readLogic_adapter_ar_rValid <= 1'b1; + end + if(readLogic_adapter_ar_halfPipe_fire) begin + readLogic_adapter_ar_rValid <= 1'b0; + end + if(read_rvalid) begin + read_r_rValidN <= 1'b0; + end + if(read_r_s2mPipe_ready) begin + read_r_rValidN <= 1'b1; + end + if(read_r_s2mPipe_ready) begin + read_r_s2mPipe_rValid <= read_r_s2mPipe_valid; + end + if(interconnect_write_aggregated_cmd_ready) begin + interconnect_write_aggregated_cmd_rValid <= interconnect_write_aggregated_cmd_valid; + end + if(writeLogic_adapter_aw_valid) begin + writeLogic_adapter_aw_rValid <= 1'b1; + end + if(writeLogic_adapter_aw_halfPipe_fire) begin + writeLogic_adapter_aw_rValid <= 1'b0; + end + if(writeLogic_adapter_w_valid) begin + writeLogic_adapter_w_rValidN <= 1'b0; + end + if(writeLogic_adapter_w_s2mPipe_ready) begin + writeLogic_adapter_w_rValidN <= 1'b1; + end + if(writeLogic_adapter_w_s2mPipe_ready) begin + writeLogic_adapter_w_s2mPipe_rValid <= writeLogic_adapter_w_s2mPipe_valid; + end + if(write_bvalid) begin + write_b_rValid <= 1'b1; + end + if(write_b_halfPipe_fire) begin + write_b_rValid <= 1'b0; + end + if(inputsAdapter_0_crossclock_fifo_io_pop_valid) begin + io_pop_rValidN <= 1'b0; + end + if(io_pop_s2mPipe_ready) begin + io_pop_rValidN <= 1'b1; + end + if(io_pop_s2mPipe_ready) begin + io_pop_s2mPipe_rValid <= io_pop_s2mPipe_valid; + end + if(core_io_outputs_0_valid) begin + io_outputs_0_rValidN <= 1'b0; + end + if(io_outputs_0_s2mPipe_ready) begin + io_outputs_0_rValidN <= 1'b1; + end + if(io_outputs_0_s2mPipe_ready) begin + io_outputs_0_s2mPipe_rValid <= io_outputs_0_s2mPipe_valid; + end + end + end + + always @(posedge clk) begin + if(io_write_cmd_rValidN) begin + io_write_cmd_rData_last <= core_io_write_cmd_payload_last; + io_write_cmd_rData_fragment_opcode <= core_io_write_cmd_payload_fragment_opcode; + io_write_cmd_rData_fragment_address <= core_io_write_cmd_payload_fragment_address; + io_write_cmd_rData_fragment_length <= core_io_write_cmd_payload_fragment_length; + io_write_cmd_rData_fragment_data <= core_io_write_cmd_payload_fragment_data; + io_write_cmd_rData_fragment_mask <= core_io_write_cmd_payload_fragment_mask; + io_write_cmd_rData_fragment_context <= core_io_write_cmd_payload_fragment_context; + end + if(io_write_cmd_s2mPipe_ready) begin + io_write_cmd_s2mPipe_rData_last <= io_write_cmd_s2mPipe_payload_last; + io_write_cmd_s2mPipe_rData_fragment_opcode <= io_write_cmd_s2mPipe_payload_fragment_opcode; + io_write_cmd_s2mPipe_rData_fragment_address <= io_write_cmd_s2mPipe_payload_fragment_address; + io_write_cmd_s2mPipe_rData_fragment_length <= io_write_cmd_s2mPipe_payload_fragment_length; + io_write_cmd_s2mPipe_rData_fragment_data <= io_write_cmd_s2mPipe_payload_fragment_data; + io_write_cmd_s2mPipe_rData_fragment_mask <= io_write_cmd_s2mPipe_payload_fragment_mask; + io_write_cmd_s2mPipe_rData_fragment_context <= io_write_cmd_s2mPipe_payload_fragment_context; + end + if(interconnect_read_aggregated_cmd_ready) begin + interconnect_read_aggregated_cmd_rData_last <= interconnect_read_aggregated_cmd_payload_last; + interconnect_read_aggregated_cmd_rData_fragment_source <= interconnect_read_aggregated_cmd_payload_fragment_source; + interconnect_read_aggregated_cmd_rData_fragment_opcode <= interconnect_read_aggregated_cmd_payload_fragment_opcode; + interconnect_read_aggregated_cmd_rData_fragment_address <= interconnect_read_aggregated_cmd_payload_fragment_address; + interconnect_read_aggregated_cmd_rData_fragment_length <= interconnect_read_aggregated_cmd_payload_fragment_length; + interconnect_read_aggregated_cmd_rData_fragment_context <= interconnect_read_aggregated_cmd_payload_fragment_context; + end + if(readLogic_adapter_ar_ready) begin + readLogic_adapter_ar_rData_addr <= readLogic_adapter_ar_payload_addr; + readLogic_adapter_ar_rData_region <= readLogic_adapter_ar_payload_region; + readLogic_adapter_ar_rData_len <= readLogic_adapter_ar_payload_len; + readLogic_adapter_ar_rData_size <= readLogic_adapter_ar_payload_size; + readLogic_adapter_ar_rData_burst <= readLogic_adapter_ar_payload_burst; + readLogic_adapter_ar_rData_lock <= readLogic_adapter_ar_payload_lock; + readLogic_adapter_ar_rData_cache <= readLogic_adapter_ar_payload_cache; + readLogic_adapter_ar_rData_qos <= readLogic_adapter_ar_payload_qos; + readLogic_adapter_ar_rData_prot <= readLogic_adapter_ar_payload_prot; + end + if(read_rready) begin + read_r_rData_data <= read_rdata; + read_r_rData_resp <= read_rresp; + read_r_rData_last <= read_rlast; + end + if(read_r_s2mPipe_ready) begin + read_r_s2mPipe_rData_data <= read_r_s2mPipe_payload_data; + read_r_s2mPipe_rData_resp <= read_r_s2mPipe_payload_resp; + read_r_s2mPipe_rData_last <= read_r_s2mPipe_payload_last; + end + if(interconnect_write_aggregated_cmd_ready) begin + interconnect_write_aggregated_cmd_rData_last <= interconnect_write_aggregated_cmd_payload_last; + interconnect_write_aggregated_cmd_rData_fragment_source <= interconnect_write_aggregated_cmd_payload_fragment_source; + interconnect_write_aggregated_cmd_rData_fragment_opcode <= interconnect_write_aggregated_cmd_payload_fragment_opcode; + interconnect_write_aggregated_cmd_rData_fragment_address <= interconnect_write_aggregated_cmd_payload_fragment_address; + interconnect_write_aggregated_cmd_rData_fragment_length <= interconnect_write_aggregated_cmd_payload_fragment_length; + interconnect_write_aggregated_cmd_rData_fragment_data <= interconnect_write_aggregated_cmd_payload_fragment_data; + interconnect_write_aggregated_cmd_rData_fragment_mask <= interconnect_write_aggregated_cmd_payload_fragment_mask; + interconnect_write_aggregated_cmd_rData_fragment_context <= interconnect_write_aggregated_cmd_payload_fragment_context; + end + if(writeLogic_adapter_aw_ready) begin + writeLogic_adapter_aw_rData_addr <= writeLogic_adapter_aw_payload_addr; + writeLogic_adapter_aw_rData_region <= writeLogic_adapter_aw_payload_region; + writeLogic_adapter_aw_rData_len <= writeLogic_adapter_aw_payload_len; + writeLogic_adapter_aw_rData_size <= writeLogic_adapter_aw_payload_size; + writeLogic_adapter_aw_rData_burst <= writeLogic_adapter_aw_payload_burst; + writeLogic_adapter_aw_rData_lock <= writeLogic_adapter_aw_payload_lock; + writeLogic_adapter_aw_rData_cache <= writeLogic_adapter_aw_payload_cache; + writeLogic_adapter_aw_rData_qos <= writeLogic_adapter_aw_payload_qos; + writeLogic_adapter_aw_rData_prot <= writeLogic_adapter_aw_payload_prot; + end + if(writeLogic_adapter_w_ready) begin + writeLogic_adapter_w_rData_data <= writeLogic_adapter_w_payload_data; + writeLogic_adapter_w_rData_strb <= writeLogic_adapter_w_payload_strb; + writeLogic_adapter_w_rData_last <= writeLogic_adapter_w_payload_last; + end + if(writeLogic_adapter_w_s2mPipe_ready) begin + writeLogic_adapter_w_s2mPipe_rData_data <= writeLogic_adapter_w_s2mPipe_payload_data; + writeLogic_adapter_w_s2mPipe_rData_strb <= writeLogic_adapter_w_s2mPipe_payload_strb; + writeLogic_adapter_w_s2mPipe_rData_last <= writeLogic_adapter_w_s2mPipe_payload_last; + end + if(write_bready) begin + write_b_rData_resp <= write_bresp; + end + if(io_pop_rValidN) begin + io_pop_rData_data <= inputsAdapter_0_crossclock_fifo_io_pop_payload_data; + io_pop_rData_mask <= inputsAdapter_0_crossclock_fifo_io_pop_payload_mask; + io_pop_rData_sink <= inputsAdapter_0_crossclock_fifo_io_pop_payload_sink; + io_pop_rData_last <= inputsAdapter_0_crossclock_fifo_io_pop_payload_last; + end + if(io_pop_s2mPipe_ready) begin + io_pop_s2mPipe_rData_data <= io_pop_s2mPipe_payload_data; + io_pop_s2mPipe_rData_mask <= io_pop_s2mPipe_payload_mask; + io_pop_s2mPipe_rData_sink <= io_pop_s2mPipe_payload_sink; + io_pop_s2mPipe_rData_last <= io_pop_s2mPipe_payload_last; + end + if(io_outputs_0_rValidN) begin + io_outputs_0_rData_data <= core_io_outputs_0_payload_data; + io_outputs_0_rData_mask <= core_io_outputs_0_payload_mask; + io_outputs_0_rData_sink <= core_io_outputs_0_payload_sink; + io_outputs_0_rData_last <= core_io_outputs_0_payload_last; + end + if(io_outputs_0_s2mPipe_ready) begin + io_outputs_0_s2mPipe_rData_data <= io_outputs_0_s2mPipe_payload_data; + io_outputs_0_s2mPipe_rData_mask <= io_outputs_0_s2mPipe_payload_mask; + io_outputs_0_s2mPipe_rData_sink <= io_outputs_0_s2mPipe_payload_sink; + io_outputs_0_s2mPipe_rData_last <= io_outputs_0_s2mPipe_payload_last; + end + end + + +endmodule + +module EfxDMA_BmbArbiter_1 ( + input wire io_inputs_0_cmd_valid, + output wire io_inputs_0_cmd_ready, + input wire io_inputs_0_cmd_payload_last, + input wire [0:0] io_inputs_0_cmd_payload_fragment_opcode, + input wire [31:0] io_inputs_0_cmd_payload_fragment_address, + input wire [1:0] io_inputs_0_cmd_payload_fragment_length, + input wire [127:0] io_inputs_0_cmd_payload_fragment_data, + input wire [15:0] io_inputs_0_cmd_payload_fragment_mask, + input wire [0:0] io_inputs_0_cmd_payload_fragment_context, + output wire io_inputs_0_rsp_valid, + input wire io_inputs_0_rsp_ready, + output wire io_inputs_0_rsp_payload_last, + output wire [0:0] io_inputs_0_rsp_payload_fragment_opcode, + output wire [0:0] io_inputs_0_rsp_payload_fragment_context, + input wire io_inputs_1_cmd_valid, + output wire io_inputs_1_cmd_ready, + input wire io_inputs_1_cmd_payload_last, + input wire [0:0] io_inputs_1_cmd_payload_fragment_opcode, + input wire [31:0] io_inputs_1_cmd_payload_fragment_address, + input wire [11:0] io_inputs_1_cmd_payload_fragment_length, + input wire [127:0] io_inputs_1_cmd_payload_fragment_data, + input wire [15:0] io_inputs_1_cmd_payload_fragment_mask, + input wire [12:0] io_inputs_1_cmd_payload_fragment_context, + output wire io_inputs_1_rsp_valid, + input wire io_inputs_1_rsp_ready, + output wire io_inputs_1_rsp_payload_last, + output wire [0:0] io_inputs_1_rsp_payload_fragment_opcode, + output wire [12:0] io_inputs_1_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_source, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + output wire [127:0] io_output_cmd_payload_fragment_data, + output wire [15:0] io_output_cmd_payload_fragment_mask, + output wire [12:0] io_output_cmd_payload_fragment_context, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_source, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [12:0] io_output_rsp_payload_fragment_context, + input wire clk, + input wire reset +); + + wire [11:0] memory_arbiter_io_inputs_0_payload_fragment_length; + wire [12:0] memory_arbiter_io_inputs_0_payload_fragment_context; + wire memory_arbiter_io_inputs_0_ready; + wire memory_arbiter_io_inputs_1_ready; + wire memory_arbiter_io_output_valid; + wire memory_arbiter_io_output_payload_last; + wire [0:0] memory_arbiter_io_output_payload_fragment_source; + wire [0:0] memory_arbiter_io_output_payload_fragment_opcode; + wire [31:0] memory_arbiter_io_output_payload_fragment_address; + wire [11:0] memory_arbiter_io_output_payload_fragment_length; + wire [127:0] memory_arbiter_io_output_payload_fragment_data; + wire [15:0] memory_arbiter_io_output_payload_fragment_mask; + wire [12:0] memory_arbiter_io_output_payload_fragment_context; + wire [0:0] memory_arbiter_io_chosen; + wire [1:0] memory_arbiter_io_chosenOH; + wire [1:0] _zz_io_output_cmd_payload_fragment_source; + reg _zz_io_output_rsp_ready; + wire [0:0] memory_rspSel; + + assign _zz_io_output_cmd_payload_fragment_source = {memory_arbiter_io_output_payload_fragment_source,memory_arbiter_io_chosen}; + EfxDMA_StreamArbiter_1 memory_arbiter ( + .io_inputs_0_valid (io_inputs_0_cmd_valid ), //i + .io_inputs_0_ready (memory_arbiter_io_inputs_0_ready ), //o + .io_inputs_0_payload_last (io_inputs_0_cmd_payload_last ), //i + .io_inputs_0_payload_fragment_source (1'b0 ), //i + .io_inputs_0_payload_fragment_opcode (io_inputs_0_cmd_payload_fragment_opcode ), //i + .io_inputs_0_payload_fragment_address (io_inputs_0_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_0_payload_fragment_length (memory_arbiter_io_inputs_0_payload_fragment_length[11:0] ), //i + .io_inputs_0_payload_fragment_data (io_inputs_0_cmd_payload_fragment_data[127:0] ), //i + .io_inputs_0_payload_fragment_mask (io_inputs_0_cmd_payload_fragment_mask[15:0] ), //i + .io_inputs_0_payload_fragment_context (memory_arbiter_io_inputs_0_payload_fragment_context[12:0]), //i + .io_inputs_1_valid (io_inputs_1_cmd_valid ), //i + .io_inputs_1_ready (memory_arbiter_io_inputs_1_ready ), //o + .io_inputs_1_payload_last (io_inputs_1_cmd_payload_last ), //i + .io_inputs_1_payload_fragment_source (1'b0 ), //i + .io_inputs_1_payload_fragment_opcode (io_inputs_1_cmd_payload_fragment_opcode ), //i + .io_inputs_1_payload_fragment_address (io_inputs_1_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_1_payload_fragment_length (io_inputs_1_cmd_payload_fragment_length[11:0] ), //i + .io_inputs_1_payload_fragment_data (io_inputs_1_cmd_payload_fragment_data[127:0] ), //i + .io_inputs_1_payload_fragment_mask (io_inputs_1_cmd_payload_fragment_mask[15:0] ), //i + .io_inputs_1_payload_fragment_context (io_inputs_1_cmd_payload_fragment_context[12:0] ), //i + .io_output_valid (memory_arbiter_io_output_valid ), //o + .io_output_ready (io_output_cmd_ready ), //i + .io_output_payload_last (memory_arbiter_io_output_payload_last ), //o + .io_output_payload_fragment_source (memory_arbiter_io_output_payload_fragment_source ), //o + .io_output_payload_fragment_opcode (memory_arbiter_io_output_payload_fragment_opcode ), //o + .io_output_payload_fragment_address (memory_arbiter_io_output_payload_fragment_address[31:0] ), //o + .io_output_payload_fragment_length (memory_arbiter_io_output_payload_fragment_length[11:0] ), //o + .io_output_payload_fragment_data (memory_arbiter_io_output_payload_fragment_data[127:0] ), //o + .io_output_payload_fragment_mask (memory_arbiter_io_output_payload_fragment_mask[15:0] ), //o + .io_output_payload_fragment_context (memory_arbiter_io_output_payload_fragment_context[12:0] ), //o + .io_chosen (memory_arbiter_io_chosen ), //o + .io_chosenOH (memory_arbiter_io_chosenOH[1:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(memory_rspSel) + 1'b0 : _zz_io_output_rsp_ready = io_inputs_0_rsp_ready; + default : _zz_io_output_rsp_ready = io_inputs_1_rsp_ready; + endcase + end + + assign io_inputs_0_cmd_ready = memory_arbiter_io_inputs_0_ready; + assign memory_arbiter_io_inputs_0_payload_fragment_length = {10'd0, io_inputs_0_cmd_payload_fragment_length}; + assign memory_arbiter_io_inputs_0_payload_fragment_context = {12'd0, io_inputs_0_cmd_payload_fragment_context}; + assign io_inputs_1_cmd_ready = memory_arbiter_io_inputs_1_ready; + assign io_output_cmd_valid = memory_arbiter_io_output_valid; + assign io_output_cmd_payload_last = memory_arbiter_io_output_payload_last; + assign io_output_cmd_payload_fragment_opcode = memory_arbiter_io_output_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = memory_arbiter_io_output_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = memory_arbiter_io_output_payload_fragment_length; + assign io_output_cmd_payload_fragment_data = memory_arbiter_io_output_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = memory_arbiter_io_output_payload_fragment_mask; + assign io_output_cmd_payload_fragment_context = memory_arbiter_io_output_payload_fragment_context; + assign io_output_cmd_payload_fragment_source = _zz_io_output_cmd_payload_fragment_source[0:0]; + assign memory_rspSel = io_output_rsp_payload_fragment_source[0 : 0]; + assign io_inputs_0_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b0)); + assign io_inputs_0_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_0_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_0_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context[0:0]; + assign io_inputs_1_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b1)); + assign io_inputs_1_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_1_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_1_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; + assign io_output_rsp_ready = _zz_io_output_rsp_ready; + +endmodule + +module EfxDMA_BmbArbiter ( + input wire io_inputs_0_cmd_valid, + output wire io_inputs_0_cmd_ready, + input wire io_inputs_0_cmd_payload_last, + input wire [0:0] io_inputs_0_cmd_payload_fragment_opcode, + input wire [31:0] io_inputs_0_cmd_payload_fragment_address, + input wire [4:0] io_inputs_0_cmd_payload_fragment_length, + input wire [0:0] io_inputs_0_cmd_payload_fragment_context, + output wire io_inputs_0_rsp_valid, + input wire io_inputs_0_rsp_ready, + output wire io_inputs_0_rsp_payload_last, + output wire [0:0] io_inputs_0_rsp_payload_fragment_opcode, + output wire [127:0] io_inputs_0_rsp_payload_fragment_data, + output wire [0:0] io_inputs_0_rsp_payload_fragment_context, + input wire io_inputs_1_cmd_valid, + output wire io_inputs_1_cmd_ready, + input wire io_inputs_1_cmd_payload_last, + input wire [0:0] io_inputs_1_cmd_payload_fragment_opcode, + input wire [31:0] io_inputs_1_cmd_payload_fragment_address, + input wire [11:0] io_inputs_1_cmd_payload_fragment_length, + input wire [20:0] io_inputs_1_cmd_payload_fragment_context, + output wire io_inputs_1_rsp_valid, + input wire io_inputs_1_rsp_ready, + output wire io_inputs_1_rsp_payload_last, + output wire [0:0] io_inputs_1_rsp_payload_fragment_opcode, + output wire [127:0] io_inputs_1_rsp_payload_fragment_data, + output wire [20:0] io_inputs_1_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_source, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + output wire [20:0] io_output_cmd_payload_fragment_context, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_source, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [127:0] io_output_rsp_payload_fragment_data, + input wire [20:0] io_output_rsp_payload_fragment_context, + input wire clk, + input wire reset +); + + wire [11:0] memory_arbiter_io_inputs_0_payload_fragment_length; + wire [20:0] memory_arbiter_io_inputs_0_payload_fragment_context; + wire memory_arbiter_io_inputs_0_ready; + wire memory_arbiter_io_inputs_1_ready; + wire memory_arbiter_io_output_valid; + wire memory_arbiter_io_output_payload_last; + wire [0:0] memory_arbiter_io_output_payload_fragment_source; + wire [0:0] memory_arbiter_io_output_payload_fragment_opcode; + wire [31:0] memory_arbiter_io_output_payload_fragment_address; + wire [11:0] memory_arbiter_io_output_payload_fragment_length; + wire [20:0] memory_arbiter_io_output_payload_fragment_context; + wire [0:0] memory_arbiter_io_chosen; + wire [1:0] memory_arbiter_io_chosenOH; + wire [1:0] _zz_io_output_cmd_payload_fragment_source; + reg _zz_io_output_rsp_ready; + wire [0:0] memory_rspSel; + + assign _zz_io_output_cmd_payload_fragment_source = {memory_arbiter_io_output_payload_fragment_source,memory_arbiter_io_chosen}; + EfxDMA_StreamArbiter memory_arbiter ( + .io_inputs_0_valid (io_inputs_0_cmd_valid ), //i + .io_inputs_0_ready (memory_arbiter_io_inputs_0_ready ), //o + .io_inputs_0_payload_last (io_inputs_0_cmd_payload_last ), //i + .io_inputs_0_payload_fragment_source (1'b0 ), //i + .io_inputs_0_payload_fragment_opcode (io_inputs_0_cmd_payload_fragment_opcode ), //i + .io_inputs_0_payload_fragment_address (io_inputs_0_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_0_payload_fragment_length (memory_arbiter_io_inputs_0_payload_fragment_length[11:0] ), //i + .io_inputs_0_payload_fragment_context (memory_arbiter_io_inputs_0_payload_fragment_context[20:0]), //i + .io_inputs_1_valid (io_inputs_1_cmd_valid ), //i + .io_inputs_1_ready (memory_arbiter_io_inputs_1_ready ), //o + .io_inputs_1_payload_last (io_inputs_1_cmd_payload_last ), //i + .io_inputs_1_payload_fragment_source (1'b0 ), //i + .io_inputs_1_payload_fragment_opcode (io_inputs_1_cmd_payload_fragment_opcode ), //i + .io_inputs_1_payload_fragment_address (io_inputs_1_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_1_payload_fragment_length (io_inputs_1_cmd_payload_fragment_length[11:0] ), //i + .io_inputs_1_payload_fragment_context (io_inputs_1_cmd_payload_fragment_context[20:0] ), //i + .io_output_valid (memory_arbiter_io_output_valid ), //o + .io_output_ready (io_output_cmd_ready ), //i + .io_output_payload_last (memory_arbiter_io_output_payload_last ), //o + .io_output_payload_fragment_source (memory_arbiter_io_output_payload_fragment_source ), //o + .io_output_payload_fragment_opcode (memory_arbiter_io_output_payload_fragment_opcode ), //o + .io_output_payload_fragment_address (memory_arbiter_io_output_payload_fragment_address[31:0] ), //o + .io_output_payload_fragment_length (memory_arbiter_io_output_payload_fragment_length[11:0] ), //o + .io_output_payload_fragment_context (memory_arbiter_io_output_payload_fragment_context[20:0] ), //o + .io_chosen (memory_arbiter_io_chosen ), //o + .io_chosenOH (memory_arbiter_io_chosenOH[1:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(memory_rspSel) + 1'b0 : _zz_io_output_rsp_ready = io_inputs_0_rsp_ready; + default : _zz_io_output_rsp_ready = io_inputs_1_rsp_ready; + endcase + end + + assign io_inputs_0_cmd_ready = memory_arbiter_io_inputs_0_ready; + assign memory_arbiter_io_inputs_0_payload_fragment_length = {7'd0, io_inputs_0_cmd_payload_fragment_length}; + assign memory_arbiter_io_inputs_0_payload_fragment_context = {20'd0, io_inputs_0_cmd_payload_fragment_context}; + assign io_inputs_1_cmd_ready = memory_arbiter_io_inputs_1_ready; + assign io_output_cmd_valid = memory_arbiter_io_output_valid; + assign io_output_cmd_payload_last = memory_arbiter_io_output_payload_last; + assign io_output_cmd_payload_fragment_opcode = memory_arbiter_io_output_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = memory_arbiter_io_output_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = memory_arbiter_io_output_payload_fragment_length; + assign io_output_cmd_payload_fragment_context = memory_arbiter_io_output_payload_fragment_context; + assign io_output_cmd_payload_fragment_source = _zz_io_output_cmd_payload_fragment_source[0:0]; + assign memory_rspSel = io_output_rsp_payload_fragment_source[0 : 0]; + assign io_inputs_0_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b0)); + assign io_inputs_0_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_0_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_0_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_inputs_0_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context[0:0]; + assign io_inputs_1_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b1)); + assign io_inputs_1_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_1_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_1_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_inputs_1_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; + assign io_output_rsp_ready = _zz_io_output_rsp_ready; + +endmodule + +module EfxDMA_BsbDownSizerSparse ( + input wire io_input_valid, + output wire io_input_ready, + input wire [63:0] io_input_payload_data, + input wire [7:0] io_input_payload_mask, + input wire [3:0] io_input_payload_sink, + input wire io_input_payload_last, + output wire io_output_valid, + input wire io_output_ready, + output wire [7:0] io_output_payload_data, + output wire [0:0] io_output_payload_mask, + output wire [3:0] io_output_payload_sink, + output wire io_output_payload_last, + input wire dat1_o_clk, + input wire dat1_o_reset +); + + reg [7:0] _zz_io_output_payload_data; + reg [0:0] _zz_io_output_payload_mask; + reg [2:0] counter; + wire end_1; + wire io_output_fire; + + always @(*) begin + case(counter) + 3'b000 : begin + _zz_io_output_payload_data = io_input_payload_data[7 : 0]; + _zz_io_output_payload_mask = io_input_payload_mask[0 : 0]; + end + 3'b001 : begin + _zz_io_output_payload_data = io_input_payload_data[15 : 8]; + _zz_io_output_payload_mask = io_input_payload_mask[1 : 1]; + end + 3'b010 : begin + _zz_io_output_payload_data = io_input_payload_data[23 : 16]; + _zz_io_output_payload_mask = io_input_payload_mask[2 : 2]; + end + 3'b011 : begin + _zz_io_output_payload_data = io_input_payload_data[31 : 24]; + _zz_io_output_payload_mask = io_input_payload_mask[3 : 3]; + end + 3'b100 : begin + _zz_io_output_payload_data = io_input_payload_data[39 : 32]; + _zz_io_output_payload_mask = io_input_payload_mask[4 : 4]; + end + 3'b101 : begin + _zz_io_output_payload_data = io_input_payload_data[47 : 40]; + _zz_io_output_payload_mask = io_input_payload_mask[5 : 5]; + end + 3'b110 : begin + _zz_io_output_payload_data = io_input_payload_data[55 : 48]; + _zz_io_output_payload_mask = io_input_payload_mask[6 : 6]; + end + default : begin + _zz_io_output_payload_data = io_input_payload_data[63 : 56]; + _zz_io_output_payload_mask = io_input_payload_mask[7 : 7]; + end + endcase + end + + assign end_1 = (counter == 3'b111); + assign io_output_fire = (io_output_valid && io_output_ready); + assign io_input_ready = (io_output_ready && end_1); + assign io_output_valid = io_input_valid; + assign io_output_payload_data = _zz_io_output_payload_data; + assign io_output_payload_mask = _zz_io_output_payload_mask; + assign io_output_payload_sink = io_input_payload_sink; + assign io_output_payload_last = (io_input_payload_last && end_1); + always @(posedge dat1_o_clk) begin + if(dat1_o_reset) begin + counter <= 3'b000; + end else begin + if(io_output_fire) begin + counter <= (counter + 3'b001); + end + end + end + + +endmodule + +module EfxDMA_StreamFifoCC_1 ( + input wire io_push_valid, + output wire io_push_ready, + input wire [63:0] io_push_payload_data, + input wire [7:0] io_push_payload_mask, + input wire [3:0] io_push_payload_sink, + input wire io_push_payload_last, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [63:0] io_pop_payload_data, + output wire [7:0] io_pop_payload_mask, + output wire [3:0] io_pop_payload_sink, + output wire io_pop_payload_last, + output wire [4:0] io_pushOccupancy, + output wire [4:0] io_popOccupancy, + input wire clk, + input wire reset, + input wire dat1_o_clk, + input wire dat1_o_reset +); + + reg [76:0] ram_spinal_port1; + wire [4:0] popToPushGray_buffercc_io_dataOut; + wire [4:0] pushToPopGray_buffercc_io_dataOut; + wire [4:0] _zz_pushCC_pushPtrGray; + wire [3:0] _zz_ram_port; + wire [76:0] _zz_ram_port_1; + wire [4:0] _zz_popCC_popPtrGray; + reg _zz_1; + wire [4:0] popToPushGray; + wire [4:0] pushToPopGray; + reg [4:0] pushCC_pushPtr; + wire [4:0] pushCC_pushPtrPlus; + wire io_push_fire; + reg [4:0] pushCC_pushPtrGray; + wire [4:0] pushCC_popPtrGray; + wire pushCC_full; + wire _zz_io_pushOccupancy; + wire _zz_io_pushOccupancy_1; + wire _zz_io_pushOccupancy_2; + wire _zz_io_pushOccupancy_3; + reg [4:0] popCC_popPtr; + (* keep , syn_keep *) wire [4:0] popCC_popPtrPlus /* synthesis syn_keep = 1 */ ; + wire [4:0] popCC_popPtrGray; + wire [4:0] popCC_pushPtrGray; + wire popCC_addressGen_valid; + reg popCC_addressGen_ready; + wire [3:0] popCC_addressGen_payload; + wire popCC_empty; + wire popCC_addressGen_fire; + wire popCC_readArbitation_valid; + wire popCC_readArbitation_ready; + wire [3:0] popCC_readArbitation_payload; + reg popCC_addressGen_rValid; + reg [3:0] popCC_addressGen_rData; + wire when_Stream_l375; + wire popCC_readPort_cmd_valid; + wire [3:0] popCC_readPort_cmd_payload; + wire [63:0] popCC_readPort_rsp_data; + wire [7:0] popCC_readPort_rsp_mask; + wire [3:0] popCC_readPort_rsp_sink; + wire popCC_readPort_rsp_last; + wire [76:0] _zz_popCC_readPort_rsp_data; + wire popCC_readArbitation_translated_valid; + wire popCC_readArbitation_translated_ready; + wire [63:0] popCC_readArbitation_translated_payload_data; + wire [7:0] popCC_readArbitation_translated_payload_mask; + wire [3:0] popCC_readArbitation_translated_payload_sink; + wire popCC_readArbitation_translated_payload_last; + wire popCC_readArbitation_fire; + reg [4:0] popCC_ptrToPush; + reg [4:0] popCC_ptrToOccupancy; + wire _zz_io_popOccupancy; + wire _zz_io_popOccupancy_1; + wire _zz_io_popOccupancy_2; + wire _zz_io_popOccupancy_3; + reg [76:0] ram [0:15]; + + assign _zz_pushCC_pushPtrGray = (pushCC_pushPtrPlus >>> 1'b1); + assign _zz_ram_port = pushCC_pushPtr[3:0]; + assign _zz_popCC_popPtrGray = (popCC_popPtr >>> 1'b1); + assign _zz_ram_port_1 = {io_push_payload_last,{io_push_payload_sink,{io_push_payload_mask,io_push_payload_data}}}; + always @(posedge clk) begin + if(_zz_1) begin + ram[_zz_ram_port] <= _zz_ram_port_1; + end + end + + always @(posedge dat1_o_clk) begin + if(popCC_readPort_cmd_valid) begin + ram_spinal_port1 <= ram[popCC_readPort_cmd_payload]; + end + end + + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_3 popToPushGray_buffercc ( + .io_dataIn (popToPushGray[4:0] ), //i + .io_dataOut (popToPushGray_buffercc_io_dataOut[4:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_5 pushToPopGray_buffercc ( + .io_dataIn (pushToPopGray[4:0] ), //i + .io_dataOut (pushToPopGray_buffercc_io_dataOut[4:0]), //o + .dat1_o_clk (dat1_o_clk ), //i + .dat1_o_reset (dat1_o_reset ) //i + ); + always @(*) begin + _zz_1 = 1'b0; + if(io_push_fire) begin + _zz_1 = 1'b1; + end + end + + assign pushCC_pushPtrPlus = (pushCC_pushPtr + 5'h01); + assign io_push_fire = (io_push_valid && io_push_ready); + assign pushCC_popPtrGray = popToPushGray_buffercc_io_dataOut; + assign pushCC_full = ((pushCC_pushPtrGray[4 : 3] == (~ pushCC_popPtrGray[4 : 3])) && (pushCC_pushPtrGray[2 : 0] == pushCC_popPtrGray[2 : 0])); + assign io_push_ready = (! pushCC_full); + assign _zz_io_pushOccupancy = (pushCC_popPtrGray[1] ^ _zz_io_pushOccupancy_1); + assign _zz_io_pushOccupancy_1 = (pushCC_popPtrGray[2] ^ _zz_io_pushOccupancy_2); + assign _zz_io_pushOccupancy_2 = (pushCC_popPtrGray[3] ^ _zz_io_pushOccupancy_3); + assign _zz_io_pushOccupancy_3 = pushCC_popPtrGray[4]; + assign io_pushOccupancy = (pushCC_pushPtr - {_zz_io_pushOccupancy_3,{_zz_io_pushOccupancy_2,{_zz_io_pushOccupancy_1,{_zz_io_pushOccupancy,(pushCC_popPtrGray[0] ^ _zz_io_pushOccupancy)}}}}); + assign popCC_popPtrPlus = (popCC_popPtr + 5'h01); + assign popCC_popPtrGray = (_zz_popCC_popPtrGray ^ popCC_popPtr); + assign popCC_pushPtrGray = pushToPopGray_buffercc_io_dataOut; + assign popCC_empty = (popCC_popPtrGray == popCC_pushPtrGray); + assign popCC_addressGen_valid = (! popCC_empty); + assign popCC_addressGen_payload = popCC_popPtr[3:0]; + assign popCC_addressGen_fire = (popCC_addressGen_valid && popCC_addressGen_ready); + always @(*) begin + popCC_addressGen_ready = popCC_readArbitation_ready; + if(when_Stream_l375) begin + popCC_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! popCC_readArbitation_valid); + assign popCC_readArbitation_valid = popCC_addressGen_rValid; + assign popCC_readArbitation_payload = popCC_addressGen_rData; + assign _zz_popCC_readPort_rsp_data = ram_spinal_port1; + assign popCC_readPort_rsp_data = _zz_popCC_readPort_rsp_data[63 : 0]; + assign popCC_readPort_rsp_mask = _zz_popCC_readPort_rsp_data[71 : 64]; + assign popCC_readPort_rsp_sink = _zz_popCC_readPort_rsp_data[75 : 72]; + assign popCC_readPort_rsp_last = _zz_popCC_readPort_rsp_data[76]; + assign popCC_readPort_cmd_valid = popCC_addressGen_fire; + assign popCC_readPort_cmd_payload = popCC_addressGen_payload; + assign popCC_readArbitation_translated_valid = popCC_readArbitation_valid; + assign popCC_readArbitation_ready = popCC_readArbitation_translated_ready; + assign popCC_readArbitation_translated_payload_data = popCC_readPort_rsp_data; + assign popCC_readArbitation_translated_payload_mask = popCC_readPort_rsp_mask; + assign popCC_readArbitation_translated_payload_sink = popCC_readPort_rsp_sink; + assign popCC_readArbitation_translated_payload_last = popCC_readPort_rsp_last; + assign io_pop_valid = popCC_readArbitation_translated_valid; + assign popCC_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_data = popCC_readArbitation_translated_payload_data; + assign io_pop_payload_mask = popCC_readArbitation_translated_payload_mask; + assign io_pop_payload_sink = popCC_readArbitation_translated_payload_sink; + assign io_pop_payload_last = popCC_readArbitation_translated_payload_last; + assign popCC_readArbitation_fire = (popCC_readArbitation_valid && popCC_readArbitation_ready); + assign _zz_io_popOccupancy = (popCC_pushPtrGray[1] ^ _zz_io_popOccupancy_1); + assign _zz_io_popOccupancy_1 = (popCC_pushPtrGray[2] ^ _zz_io_popOccupancy_2); + assign _zz_io_popOccupancy_2 = (popCC_pushPtrGray[3] ^ _zz_io_popOccupancy_3); + assign _zz_io_popOccupancy_3 = popCC_pushPtrGray[4]; + assign io_popOccupancy = ({_zz_io_popOccupancy_3,{_zz_io_popOccupancy_2,{_zz_io_popOccupancy_1,{_zz_io_popOccupancy,(popCC_pushPtrGray[0] ^ _zz_io_popOccupancy)}}}} - popCC_ptrToOccupancy); + assign pushToPopGray = pushCC_pushPtrGray; + assign popToPushGray = popCC_ptrToPush; + always @(posedge clk) begin + if(reset) begin + pushCC_pushPtr <= 5'h0; + pushCC_pushPtrGray <= 5'h0; + end else begin + if(io_push_fire) begin + pushCC_pushPtrGray <= (_zz_pushCC_pushPtrGray ^ pushCC_pushPtrPlus); + end + if(io_push_fire) begin + pushCC_pushPtr <= pushCC_pushPtrPlus; + end + end + end + + always @(posedge dat1_o_clk) begin + if(dat1_o_reset) begin + popCC_popPtr <= 5'h0; + popCC_addressGen_rValid <= 1'b0; + popCC_ptrToPush <= 5'h0; + popCC_ptrToOccupancy <= 5'h0; + end else begin + if(popCC_addressGen_fire) begin + popCC_popPtr <= popCC_popPtrPlus; + end + if(popCC_addressGen_ready) begin + popCC_addressGen_rValid <= popCC_addressGen_valid; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToPush <= popCC_popPtrGray; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToOccupancy <= popCC_popPtr; + end + end + end + + always @(posedge dat1_o_clk) begin + if(popCC_addressGen_ready) begin + popCC_addressGen_rData <= popCC_addressGen_payload; + end + end + + +endmodule + +module EfxDMA_StreamFifoCC ( + input wire io_push_valid, + output wire io_push_ready, + input wire [63:0] io_push_payload_data, + input wire [7:0] io_push_payload_mask, + input wire [3:0] io_push_payload_sink, + input wire io_push_payload_last, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [63:0] io_pop_payload_data, + output wire [7:0] io_pop_payload_mask, + output wire [3:0] io_pop_payload_sink, + output wire io_pop_payload_last, + output wire [4:0] io_pushOccupancy, + output wire [4:0] io_popOccupancy, + input wire dat0_i_clk, + input wire dat0_i_reset, + input wire clk, + input wire reset +); + + reg [76:0] ram_spinal_port1; + wire [4:0] popToPushGray_buffercc_io_dataOut; + wire [4:0] pushToPopGray_buffercc_io_dataOut; + wire [4:0] _zz_pushCC_pushPtrGray; + wire [3:0] _zz_ram_port; + wire [76:0] _zz_ram_port_1; + wire [4:0] _zz_popCC_popPtrGray; + reg _zz_1; + wire [4:0] popToPushGray; + wire [4:0] pushToPopGray; + reg [4:0] pushCC_pushPtr; + wire [4:0] pushCC_pushPtrPlus; + wire io_push_fire; + reg [4:0] pushCC_pushPtrGray; + wire [4:0] pushCC_popPtrGray; + wire pushCC_full; + wire _zz_io_pushOccupancy; + wire _zz_io_pushOccupancy_1; + wire _zz_io_pushOccupancy_2; + wire _zz_io_pushOccupancy_3; + reg [4:0] popCC_popPtr; + (* keep , syn_keep *) wire [4:0] popCC_popPtrPlus /* synthesis syn_keep = 1 */ ; + wire [4:0] popCC_popPtrGray; + wire [4:0] popCC_pushPtrGray; + wire popCC_addressGen_valid; + reg popCC_addressGen_ready; + wire [3:0] popCC_addressGen_payload; + wire popCC_empty; + wire popCC_addressGen_fire; + wire popCC_readArbitation_valid; + wire popCC_readArbitation_ready; + wire [3:0] popCC_readArbitation_payload; + reg popCC_addressGen_rValid; + reg [3:0] popCC_addressGen_rData; + wire when_Stream_l375; + wire popCC_readPort_cmd_valid; + wire [3:0] popCC_readPort_cmd_payload; + wire [63:0] popCC_readPort_rsp_data; + wire [7:0] popCC_readPort_rsp_mask; + wire [3:0] popCC_readPort_rsp_sink; + wire popCC_readPort_rsp_last; + wire [76:0] _zz_popCC_readPort_rsp_data; + wire popCC_readArbitation_translated_valid; + wire popCC_readArbitation_translated_ready; + wire [63:0] popCC_readArbitation_translated_payload_data; + wire [7:0] popCC_readArbitation_translated_payload_mask; + wire [3:0] popCC_readArbitation_translated_payload_sink; + wire popCC_readArbitation_translated_payload_last; + wire popCC_readArbitation_fire; + reg [4:0] popCC_ptrToPush; + reg [4:0] popCC_ptrToOccupancy; + wire _zz_io_popOccupancy; + wire _zz_io_popOccupancy_1; + wire _zz_io_popOccupancy_2; + wire _zz_io_popOccupancy_3; + reg [76:0] ram [0:15]; + + assign _zz_pushCC_pushPtrGray = (pushCC_pushPtrPlus >>> 1'b1); + assign _zz_ram_port = pushCC_pushPtr[3:0]; + assign _zz_popCC_popPtrGray = (popCC_popPtr >>> 1'b1); + assign _zz_ram_port_1 = {io_push_payload_last,{io_push_payload_sink,{io_push_payload_mask,io_push_payload_data}}}; + always @(posedge dat0_i_clk) begin + if(_zz_1) begin + ram[_zz_ram_port] <= _zz_ram_port_1; + end + end + + always @(posedge clk) begin + if(popCC_readPort_cmd_valid) begin + ram_spinal_port1 <= ram[popCC_readPort_cmd_payload]; + end + end + + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_2 popToPushGray_buffercc ( + .io_dataIn (popToPushGray[4:0] ), //i + .io_dataOut (popToPushGray_buffercc_io_dataOut[4:0]), //o + .dat0_i_clk (dat0_i_clk ), //i + .dat0_i_reset (dat0_i_reset ) //i + ); + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_3 pushToPopGray_buffercc ( + .io_dataIn (pushToPopGray[4:0] ), //i + .io_dataOut (pushToPopGray_buffercc_io_dataOut[4:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + _zz_1 = 1'b0; + if(io_push_fire) begin + _zz_1 = 1'b1; + end + end + + assign pushCC_pushPtrPlus = (pushCC_pushPtr + 5'h01); + assign io_push_fire = (io_push_valid && io_push_ready); + assign pushCC_popPtrGray = popToPushGray_buffercc_io_dataOut; + assign pushCC_full = ((pushCC_pushPtrGray[4 : 3] == (~ pushCC_popPtrGray[4 : 3])) && (pushCC_pushPtrGray[2 : 0] == pushCC_popPtrGray[2 : 0])); + assign io_push_ready = (! pushCC_full); + assign _zz_io_pushOccupancy = (pushCC_popPtrGray[1] ^ _zz_io_pushOccupancy_1); + assign _zz_io_pushOccupancy_1 = (pushCC_popPtrGray[2] ^ _zz_io_pushOccupancy_2); + assign _zz_io_pushOccupancy_2 = (pushCC_popPtrGray[3] ^ _zz_io_pushOccupancy_3); + assign _zz_io_pushOccupancy_3 = pushCC_popPtrGray[4]; + assign io_pushOccupancy = (pushCC_pushPtr - {_zz_io_pushOccupancy_3,{_zz_io_pushOccupancy_2,{_zz_io_pushOccupancy_1,{_zz_io_pushOccupancy,(pushCC_popPtrGray[0] ^ _zz_io_pushOccupancy)}}}}); + assign popCC_popPtrPlus = (popCC_popPtr + 5'h01); + assign popCC_popPtrGray = (_zz_popCC_popPtrGray ^ popCC_popPtr); + assign popCC_pushPtrGray = pushToPopGray_buffercc_io_dataOut; + assign popCC_empty = (popCC_popPtrGray == popCC_pushPtrGray); + assign popCC_addressGen_valid = (! popCC_empty); + assign popCC_addressGen_payload = popCC_popPtr[3:0]; + assign popCC_addressGen_fire = (popCC_addressGen_valid && popCC_addressGen_ready); + always @(*) begin + popCC_addressGen_ready = popCC_readArbitation_ready; + if(when_Stream_l375) begin + popCC_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! popCC_readArbitation_valid); + assign popCC_readArbitation_valid = popCC_addressGen_rValid; + assign popCC_readArbitation_payload = popCC_addressGen_rData; + assign _zz_popCC_readPort_rsp_data = ram_spinal_port1; + assign popCC_readPort_rsp_data = _zz_popCC_readPort_rsp_data[63 : 0]; + assign popCC_readPort_rsp_mask = _zz_popCC_readPort_rsp_data[71 : 64]; + assign popCC_readPort_rsp_sink = _zz_popCC_readPort_rsp_data[75 : 72]; + assign popCC_readPort_rsp_last = _zz_popCC_readPort_rsp_data[76]; + assign popCC_readPort_cmd_valid = popCC_addressGen_fire; + assign popCC_readPort_cmd_payload = popCC_addressGen_payload; + assign popCC_readArbitation_translated_valid = popCC_readArbitation_valid; + assign popCC_readArbitation_ready = popCC_readArbitation_translated_ready; + assign popCC_readArbitation_translated_payload_data = popCC_readPort_rsp_data; + assign popCC_readArbitation_translated_payload_mask = popCC_readPort_rsp_mask; + assign popCC_readArbitation_translated_payload_sink = popCC_readPort_rsp_sink; + assign popCC_readArbitation_translated_payload_last = popCC_readPort_rsp_last; + assign io_pop_valid = popCC_readArbitation_translated_valid; + assign popCC_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_data = popCC_readArbitation_translated_payload_data; + assign io_pop_payload_mask = popCC_readArbitation_translated_payload_mask; + assign io_pop_payload_sink = popCC_readArbitation_translated_payload_sink; + assign io_pop_payload_last = popCC_readArbitation_translated_payload_last; + assign popCC_readArbitation_fire = (popCC_readArbitation_valid && popCC_readArbitation_ready); + assign _zz_io_popOccupancy = (popCC_pushPtrGray[1] ^ _zz_io_popOccupancy_1); + assign _zz_io_popOccupancy_1 = (popCC_pushPtrGray[2] ^ _zz_io_popOccupancy_2); + assign _zz_io_popOccupancy_2 = (popCC_pushPtrGray[3] ^ _zz_io_popOccupancy_3); + assign _zz_io_popOccupancy_3 = popCC_pushPtrGray[4]; + assign io_popOccupancy = ({_zz_io_popOccupancy_3,{_zz_io_popOccupancy_2,{_zz_io_popOccupancy_1,{_zz_io_popOccupancy,(popCC_pushPtrGray[0] ^ _zz_io_popOccupancy)}}}} - popCC_ptrToOccupancy); + assign pushToPopGray = pushCC_pushPtrGray; + assign popToPushGray = popCC_ptrToPush; + always @(posedge dat0_i_clk) begin + if(dat0_i_reset) begin + pushCC_pushPtr <= 5'h0; + pushCC_pushPtrGray <= 5'h0; + end else begin + if(io_push_fire) begin + pushCC_pushPtrGray <= (_zz_pushCC_pushPtrGray ^ pushCC_pushPtrPlus); + end + if(io_push_fire) begin + pushCC_pushPtr <= pushCC_pushPtrPlus; + end + end + end + + always @(posedge clk) begin + if(reset) begin + popCC_popPtr <= 5'h0; + popCC_addressGen_rValid <= 1'b0; + popCC_ptrToPush <= 5'h0; + popCC_ptrToOccupancy <= 5'h0; + end else begin + if(popCC_addressGen_fire) begin + popCC_popPtr <= popCC_popPtrPlus; + end + if(popCC_addressGen_ready) begin + popCC_addressGen_rValid <= popCC_addressGen_valid; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToPush <= popCC_popPtrGray; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToOccupancy <= popCC_popPtr; + end + end + end + + always @(posedge clk) begin + if(popCC_addressGen_ready) begin + popCC_addressGen_rData <= popCC_addressGen_payload; + end + end + + +endmodule + +module EfxDMA_BsbUpSizerDense ( + input wire io_input_valid, + output wire io_input_ready, + input wire [7:0] io_input_payload_data, + input wire [0:0] io_input_payload_mask, + input wire [3:0] io_input_payload_sink, + input wire io_input_payload_last, + output wire io_output_valid, + input wire io_output_ready, + output wire [63:0] io_output_payload_data, + output wire [7:0] io_output_payload_mask, + output wire [3:0] io_output_payload_sink, + output wire io_output_payload_last, + input wire dat0_i_clk, + input wire dat0_i_reset +); + + reg valid; + reg [2:0] counter; + reg [63:0] buffer_data; + reg [7:0] buffer_mask; + reg [3:0] buffer_sink; + reg buffer_last; + wire full; + wire canAggregate; + wire onOutput; + wire [2:0] counterSample; + wire io_output_fire; + wire io_input_fire; + wire [7:0] _zz_1; + wire [7:0] _zz_2; + + assign full = ((counter == 3'b000) || buffer_last); + assign canAggregate = ((((valid && (! buffer_last)) && (! full)) && 1'b1) && (buffer_sink == io_input_payload_sink)); + assign counterSample = (canAggregate ? counter : 3'b000); + assign io_output_fire = (io_output_valid && io_output_ready); + assign io_input_fire = (io_input_valid && io_input_ready); + assign _zz_1 = ({7'd0,1'b1} <<< counterSample); + assign _zz_2 = ({7'd0,1'b1} <<< counterSample); + assign io_output_valid = (valid && ((valid && full) || (io_input_valid && (! canAggregate)))); + assign io_output_payload_data = buffer_data; + assign io_output_payload_mask = buffer_mask; + assign io_output_payload_sink = buffer_sink; + assign io_output_payload_last = buffer_last; + assign io_input_ready = (((! valid) || canAggregate) || io_output_ready); + always @(posedge dat0_i_clk) begin + if(dat0_i_reset) begin + valid <= 1'b0; + counter <= 3'b000; + buffer_last <= 1'b0; + buffer_mask <= 8'h0; + end else begin + if(io_output_fire) begin + valid <= 1'b0; + buffer_mask <= 8'h0; + end + if(io_input_fire) begin + valid <= 1'b1; + if(_zz_2[0]) begin + buffer_mask[0 : 0] <= io_input_payload_mask; + end + if(_zz_2[1]) begin + buffer_mask[1 : 1] <= io_input_payload_mask; + end + if(_zz_2[2]) begin + buffer_mask[2 : 2] <= io_input_payload_mask; + end + if(_zz_2[3]) begin + buffer_mask[3 : 3] <= io_input_payload_mask; + end + if(_zz_2[4]) begin + buffer_mask[4 : 4] <= io_input_payload_mask; + end + if(_zz_2[5]) begin + buffer_mask[5 : 5] <= io_input_payload_mask; + end + if(_zz_2[6]) begin + buffer_mask[6 : 6] <= io_input_payload_mask; + end + if(_zz_2[7]) begin + buffer_mask[7 : 7] <= io_input_payload_mask; + end + buffer_last <= io_input_payload_last; + counter <= (counterSample + 3'b001); + end + end + end + + always @(posedge dat0_i_clk) begin + if(io_input_fire) begin + buffer_sink <= io_input_payload_sink; + if(_zz_1[0]) begin + buffer_data[7 : 0] <= io_input_payload_data; + end + if(_zz_1[1]) begin + buffer_data[15 : 8] <= io_input_payload_data; + end + if(_zz_1[2]) begin + buffer_data[23 : 16] <= io_input_payload_data; + end + if(_zz_1[3]) begin + buffer_data[31 : 24] <= io_input_payload_data; + end + if(_zz_1[4]) begin + buffer_data[39 : 32] <= io_input_payload_data; + end + if(_zz_1[5]) begin + buffer_data[47 : 40] <= io_input_payload_data; + end + if(_zz_1[6]) begin + buffer_data[55 : 48] <= io_input_payload_data; + end + if(_zz_1[7]) begin + buffer_data[63 : 56] <= io_input_payload_data; + end + end + end + + +endmodule + +module EfxDMA_BmbToAxi4WriteOnlyBridge ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [127:0] io_input_cmd_payload_fragment_data, + input wire [15:0] io_input_cmd_payload_fragment_mask, + input wire [13:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [13:0] io_input_rsp_payload_fragment_context, + output wire io_output_aw_valid, + input wire io_output_aw_ready, + output wire [31:0] io_output_aw_payload_addr, + output wire [7:0] io_output_aw_payload_len, + output wire [2:0] io_output_aw_payload_size, + output wire [3:0] io_output_aw_payload_cache, + output wire [2:0] io_output_aw_payload_prot, + output wire io_output_w_valid, + input wire io_output_w_ready, + output wire [127:0] io_output_w_payload_data, + output wire [15:0] io_output_w_payload_strb, + output wire io_output_w_payload_last, + input wire io_output_b_valid, + output wire io_output_b_ready, + input wire [1:0] io_output_b_payload_resp, + input wire clk, + input wire reset +); + + reg contextRemover_io_output_cmd_ready; + reg [0:0] contextRemover_io_output_rsp_payload_fragment_opcode; + wire contextRemover_io_input_cmd_ready; + wire contextRemover_io_input_rsp_valid; + wire contextRemover_io_input_rsp_payload_last; + wire [0:0] contextRemover_io_input_rsp_payload_fragment_opcode; + wire [13:0] contextRemover_io_input_rsp_payload_fragment_context; + wire contextRemover_io_output_cmd_valid; + wire contextRemover_io_output_cmd_payload_last; + wire [0:0] contextRemover_io_output_cmd_payload_fragment_opcode; + wire [31:0] contextRemover_io_output_cmd_payload_fragment_address; + wire [11:0] contextRemover_io_output_cmd_payload_fragment_length; + wire [127:0] contextRemover_io_output_cmd_payload_fragment_data; + wire [15:0] contextRemover_io_output_cmd_payload_fragment_mask; + wire contextRemover_io_output_rsp_ready; + wire [8:0] _zz_io_output_aw_payload_len; + wire [12:0] _zz_io_output_aw_payload_len_1; + wire [12:0] _zz_io_output_aw_payload_len_2; + wire [3:0] _zz_io_output_aw_payload_len_3; + wire cmdFork_valid; + reg cmdFork_ready; + wire cmdFork_payload_last; + wire [0:0] cmdFork_payload_fragment_opcode; + wire [31:0] cmdFork_payload_fragment_address; + wire [11:0] cmdFork_payload_fragment_length; + wire [127:0] cmdFork_payload_fragment_data; + wire [15:0] cmdFork_payload_fragment_mask; + wire dataFork_valid; + wire dataFork_ready; + wire dataFork_payload_last; + wire [0:0] dataFork_payload_fragment_opcode; + wire [31:0] dataFork_payload_fragment_address; + wire [11:0] dataFork_payload_fragment_length; + wire [127:0] dataFork_payload_fragment_data; + wire [15:0] dataFork_payload_fragment_mask; + reg contextRemover_io_output_cmd_fork2_logic_linkEnable_0; + reg contextRemover_io_output_cmd_fork2_logic_linkEnable_1; + wire when_Stream_l1063; + wire when_Stream_l1063_1; + wire cmdFork_fire; + wire dataFork_fire; + wire contextRemover_io_output_cmd_fire; + reg contextRemover_io_output_cmd_payload_first; + wire when_Stream_l445; + reg cmdStage_valid; + wire cmdStage_ready; + wire cmdStage_payload_last; + wire [0:0] cmdStage_payload_fragment_opcode; + wire [31:0] cmdStage_payload_fragment_address; + wire [11:0] cmdStage_payload_fragment_length; + wire [127:0] cmdStage_payload_fragment_data; + wire [15:0] cmdStage_payload_fragment_mask; + wire when_BmbToAxi4Bridge_l297; + + assign _zz_io_output_aw_payload_len = _zz_io_output_aw_payload_len_1[12 : 4]; + assign _zz_io_output_aw_payload_len_1 = ({1'b0,cmdStage_payload_fragment_length} + _zz_io_output_aw_payload_len_2); + assign _zz_io_output_aw_payload_len_3 = cmdStage_payload_fragment_address[3 : 0]; + assign _zz_io_output_aw_payload_len_2 = {9'd0, _zz_io_output_aw_payload_len_3}; + EfxDMA_BmbContextRemover_1 contextRemover ( + .io_input_cmd_valid (io_input_cmd_valid ), //i + .io_input_cmd_ready (contextRemover_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (io_input_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (io_input_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (io_input_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (io_input_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_data (io_input_cmd_payload_fragment_data[127:0] ), //i + .io_input_cmd_payload_fragment_mask (io_input_cmd_payload_fragment_mask[15:0] ), //i + .io_input_cmd_payload_fragment_context (io_input_cmd_payload_fragment_context[13:0] ), //i + .io_input_rsp_valid (contextRemover_io_input_rsp_valid ), //o + .io_input_rsp_ready (io_input_rsp_ready ), //i + .io_input_rsp_payload_last (contextRemover_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (contextRemover_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_context (contextRemover_io_input_rsp_payload_fragment_context[13:0] ), //o + .io_output_cmd_valid (contextRemover_io_output_cmd_valid ), //o + .io_output_cmd_ready (contextRemover_io_output_cmd_ready ), //i + .io_output_cmd_payload_last (contextRemover_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (contextRemover_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (contextRemover_io_output_cmd_payload_fragment_address[31:0]), //o + .io_output_cmd_payload_fragment_length (contextRemover_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_cmd_payload_fragment_data (contextRemover_io_output_cmd_payload_fragment_data[127:0] ), //o + .io_output_cmd_payload_fragment_mask (contextRemover_io_output_cmd_payload_fragment_mask[15:0] ), //o + .io_output_rsp_valid (io_output_b_valid ), //i + .io_output_rsp_ready (contextRemover_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (1'b1 ), //i + .io_output_rsp_payload_fragment_opcode (contextRemover_io_output_rsp_payload_fragment_opcode ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign io_input_cmd_ready = contextRemover_io_input_cmd_ready; + assign io_input_rsp_valid = contextRemover_io_input_rsp_valid; + assign io_input_rsp_payload_last = contextRemover_io_input_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = contextRemover_io_input_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_context = contextRemover_io_input_rsp_payload_fragment_context; + always @(*) begin + contextRemover_io_output_cmd_ready = 1'b1; + if(when_Stream_l1063) begin + contextRemover_io_output_cmd_ready = 1'b0; + end + if(when_Stream_l1063_1) begin + contextRemover_io_output_cmd_ready = 1'b0; + end + end + + assign when_Stream_l1063 = ((! cmdFork_ready) && contextRemover_io_output_cmd_fork2_logic_linkEnable_0); + assign when_Stream_l1063_1 = ((! dataFork_ready) && contextRemover_io_output_cmd_fork2_logic_linkEnable_1); + assign cmdFork_valid = (contextRemover_io_output_cmd_valid && contextRemover_io_output_cmd_fork2_logic_linkEnable_0); + assign cmdFork_payload_last = contextRemover_io_output_cmd_payload_last; + assign cmdFork_payload_fragment_opcode = contextRemover_io_output_cmd_payload_fragment_opcode; + assign cmdFork_payload_fragment_address = contextRemover_io_output_cmd_payload_fragment_address; + assign cmdFork_payload_fragment_length = contextRemover_io_output_cmd_payload_fragment_length; + assign cmdFork_payload_fragment_data = contextRemover_io_output_cmd_payload_fragment_data; + assign cmdFork_payload_fragment_mask = contextRemover_io_output_cmd_payload_fragment_mask; + assign cmdFork_fire = (cmdFork_valid && cmdFork_ready); + assign dataFork_valid = (contextRemover_io_output_cmd_valid && contextRemover_io_output_cmd_fork2_logic_linkEnable_1); + assign dataFork_payload_last = contextRemover_io_output_cmd_payload_last; + assign dataFork_payload_fragment_opcode = contextRemover_io_output_cmd_payload_fragment_opcode; + assign dataFork_payload_fragment_address = contextRemover_io_output_cmd_payload_fragment_address; + assign dataFork_payload_fragment_length = contextRemover_io_output_cmd_payload_fragment_length; + assign dataFork_payload_fragment_data = contextRemover_io_output_cmd_payload_fragment_data; + assign dataFork_payload_fragment_mask = contextRemover_io_output_cmd_payload_fragment_mask; + assign dataFork_fire = (dataFork_valid && dataFork_ready); + assign contextRemover_io_output_cmd_fire = (contextRemover_io_output_cmd_valid && contextRemover_io_output_cmd_ready); + assign when_Stream_l445 = (! contextRemover_io_output_cmd_payload_first); + always @(*) begin + cmdStage_valid = cmdFork_valid; + if(when_Stream_l445) begin + cmdStage_valid = 1'b0; + end + end + + always @(*) begin + cmdFork_ready = cmdStage_ready; + if(when_Stream_l445) begin + cmdFork_ready = 1'b1; + end + end + + assign cmdStage_payload_last = cmdFork_payload_last; + assign cmdStage_payload_fragment_opcode = cmdFork_payload_fragment_opcode; + assign cmdStage_payload_fragment_address = cmdFork_payload_fragment_address; + assign cmdStage_payload_fragment_length = cmdFork_payload_fragment_length; + assign cmdStage_payload_fragment_data = cmdFork_payload_fragment_data; + assign cmdStage_payload_fragment_mask = cmdFork_payload_fragment_mask; + assign io_output_aw_valid = cmdStage_valid; + assign cmdStage_ready = io_output_aw_ready; + assign io_output_aw_payload_addr = cmdStage_payload_fragment_address; + assign io_output_aw_payload_len = _zz_io_output_aw_payload_len[7:0]; + assign io_output_aw_payload_size = 3'b100; + assign io_output_aw_payload_prot = 3'b010; + assign io_output_aw_payload_cache = 4'b1111; + assign io_output_w_valid = dataFork_valid; + assign dataFork_ready = io_output_w_ready; + assign io_output_w_payload_data = dataFork_payload_fragment_data; + assign io_output_w_payload_strb = dataFork_payload_fragment_mask; + assign io_output_w_payload_last = dataFork_payload_last; + assign io_output_b_ready = contextRemover_io_output_rsp_ready; + assign when_BmbToAxi4Bridge_l297 = (io_output_b_payload_resp == 2'b00); + always @(*) begin + if(when_BmbToAxi4Bridge_l297) begin + contextRemover_io_output_rsp_payload_fragment_opcode = 1'b0; + end else begin + contextRemover_io_output_rsp_payload_fragment_opcode = 1'b1; + end + end + + always @(posedge clk) begin + if(reset) begin + contextRemover_io_output_cmd_fork2_logic_linkEnable_0 <= 1'b1; + contextRemover_io_output_cmd_fork2_logic_linkEnable_1 <= 1'b1; + contextRemover_io_output_cmd_payload_first <= 1'b1; + end else begin + if(cmdFork_fire) begin + contextRemover_io_output_cmd_fork2_logic_linkEnable_0 <= 1'b0; + end + if(dataFork_fire) begin + contextRemover_io_output_cmd_fork2_logic_linkEnable_1 <= 1'b0; + end + if(contextRemover_io_output_cmd_ready) begin + contextRemover_io_output_cmd_fork2_logic_linkEnable_0 <= 1'b1; + contextRemover_io_output_cmd_fork2_logic_linkEnable_1 <= 1'b1; + end + if(contextRemover_io_output_cmd_fire) begin + contextRemover_io_output_cmd_payload_first <= contextRemover_io_output_cmd_payload_last; + end + end + end + + +endmodule + +module EfxDMA_BmbSourceRemover_1 ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_source, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [127:0] io_input_cmd_payload_fragment_data, + input wire [15:0] io_input_cmd_payload_fragment_mask, + input wire [12:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_source, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [12:0] io_input_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + output wire [127:0] io_output_cmd_payload_fragment_data, + output wire [15:0] io_output_cmd_payload_fragment_mask, + output wire [13:0] io_output_cmd_payload_fragment_context, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [13:0] io_output_rsp_payload_fragment_context +); + + wire [0:0] cmdContext_source; + wire [12:0] cmdContext_context; + wire [0:0] rspContext_source; + wire [12:0] rspContext_context; + wire [13:0] _zz_rspContext_source; + + assign cmdContext_source = io_input_cmd_payload_fragment_source; + assign cmdContext_context = io_input_cmd_payload_fragment_context; + assign io_output_cmd_valid = io_input_cmd_valid; + assign io_input_cmd_ready = io_output_cmd_ready; + assign io_output_cmd_payload_last = io_input_cmd_payload_last; + assign io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign io_output_cmd_payload_fragment_context = {cmdContext_context,cmdContext_source}; + assign _zz_rspContext_source = io_output_rsp_payload_fragment_context; + assign rspContext_source = _zz_rspContext_source[0 : 0]; + assign rspContext_context = _zz_rspContext_source[13 : 1]; + assign io_input_rsp_valid = io_output_rsp_valid; + assign io_output_rsp_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = io_output_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_source = rspContext_source; + assign io_input_rsp_payload_fragment_context = rspContext_context; + +endmodule + +module EfxDMA_BmbToAxi4ReadOnlyBridge ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [21:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [127:0] io_input_rsp_payload_fragment_data, + output wire [21:0] io_input_rsp_payload_fragment_context, + output wire io_output_ar_valid, + input wire io_output_ar_ready, + output wire [31:0] io_output_ar_payload_addr, + output wire [7:0] io_output_ar_payload_len, + output wire [2:0] io_output_ar_payload_size, + output wire [3:0] io_output_ar_payload_cache, + output wire [2:0] io_output_ar_payload_prot, + input wire io_output_r_valid, + output wire io_output_r_ready, + input wire [127:0] io_output_r_payload_data, + input wire [1:0] io_output_r_payload_resp, + input wire io_output_r_payload_last, + input wire clk, + input wire reset +); + + reg [0:0] contextRemover_io_output_rsp_payload_fragment_opcode; + wire contextRemover_io_input_cmd_ready; + wire contextRemover_io_input_rsp_valid; + wire contextRemover_io_input_rsp_payload_last; + wire [0:0] contextRemover_io_input_rsp_payload_fragment_opcode; + wire [127:0] contextRemover_io_input_rsp_payload_fragment_data; + wire [21:0] contextRemover_io_input_rsp_payload_fragment_context; + wire contextRemover_io_output_cmd_valid; + wire contextRemover_io_output_cmd_payload_last; + wire [0:0] contextRemover_io_output_cmd_payload_fragment_opcode; + wire [31:0] contextRemover_io_output_cmd_payload_fragment_address; + wire [11:0] contextRemover_io_output_cmd_payload_fragment_length; + wire contextRemover_io_output_rsp_ready; + wire [8:0] _zz_io_output_ar_payload_len; + wire [12:0] _zz_io_output_ar_payload_len_1; + wire [12:0] _zz_io_output_ar_payload_len_2; + wire [3:0] _zz_io_output_ar_payload_len_3; + wire when_BmbToAxi4Bridge_l243; + + assign _zz_io_output_ar_payload_len = _zz_io_output_ar_payload_len_1[12 : 4]; + assign _zz_io_output_ar_payload_len_1 = ({1'b0,contextRemover_io_output_cmd_payload_fragment_length} + _zz_io_output_ar_payload_len_2); + assign _zz_io_output_ar_payload_len_3 = contextRemover_io_output_cmd_payload_fragment_address[3 : 0]; + assign _zz_io_output_ar_payload_len_2 = {9'd0, _zz_io_output_ar_payload_len_3}; + EfxDMA_BmbContextRemover contextRemover ( + .io_input_cmd_valid (io_input_cmd_valid ), //i + .io_input_cmd_ready (contextRemover_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (io_input_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (io_input_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (io_input_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (io_input_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_context (io_input_cmd_payload_fragment_context[21:0] ), //i + .io_input_rsp_valid (contextRemover_io_input_rsp_valid ), //o + .io_input_rsp_ready (io_input_rsp_ready ), //i + .io_input_rsp_payload_last (contextRemover_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (contextRemover_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (contextRemover_io_input_rsp_payload_fragment_data[127:0] ), //o + .io_input_rsp_payload_fragment_context (contextRemover_io_input_rsp_payload_fragment_context[21:0] ), //o + .io_output_cmd_valid (contextRemover_io_output_cmd_valid ), //o + .io_output_cmd_ready (io_output_ar_ready ), //i + .io_output_cmd_payload_last (contextRemover_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (contextRemover_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (contextRemover_io_output_cmd_payload_fragment_address[31:0]), //o + .io_output_cmd_payload_fragment_length (contextRemover_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_rsp_valid (io_output_r_valid ), //i + .io_output_rsp_ready (contextRemover_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (io_output_r_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (contextRemover_io_output_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (io_output_r_payload_data[127:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign io_input_cmd_ready = contextRemover_io_input_cmd_ready; + assign io_input_rsp_valid = contextRemover_io_input_rsp_valid; + assign io_input_rsp_payload_last = contextRemover_io_input_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = contextRemover_io_input_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = contextRemover_io_input_rsp_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = contextRemover_io_input_rsp_payload_fragment_context; + assign io_output_ar_valid = contextRemover_io_output_cmd_valid; + assign io_output_ar_payload_addr = contextRemover_io_output_cmd_payload_fragment_address; + assign io_output_ar_payload_len = _zz_io_output_ar_payload_len[7:0]; + assign io_output_ar_payload_size = 3'b100; + assign io_output_ar_payload_prot = 3'b010; + assign io_output_ar_payload_cache = 4'b1111; + assign io_output_r_ready = contextRemover_io_output_rsp_ready; + assign when_BmbToAxi4Bridge_l243 = (io_output_r_payload_resp == 2'b00); + always @(*) begin + if(when_BmbToAxi4Bridge_l243) begin + contextRemover_io_output_rsp_payload_fragment_opcode = 1'b0; + end else begin + contextRemover_io_output_rsp_payload_fragment_opcode = 1'b1; + end + end + + +endmodule + +module EfxDMA_BmbSourceRemover ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_source, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [20:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_source, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [127:0] io_input_rsp_payload_fragment_data, + output wire [20:0] io_input_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + output wire [21:0] io_output_cmd_payload_fragment_context, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [127:0] io_output_rsp_payload_fragment_data, + input wire [21:0] io_output_rsp_payload_fragment_context +); + + wire [0:0] cmdContext_source; + wire [20:0] cmdContext_context; + wire [0:0] rspContext_source; + wire [20:0] rspContext_context; + wire [21:0] _zz_rspContext_source; + + assign cmdContext_source = io_input_cmd_payload_fragment_source; + assign cmdContext_context = io_input_cmd_payload_fragment_context; + assign io_output_cmd_valid = io_input_cmd_valid; + assign io_input_cmd_ready = io_output_cmd_ready; + assign io_output_cmd_payload_last = io_input_cmd_payload_last; + assign io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign io_output_cmd_payload_fragment_context = {cmdContext_context,cmdContext_source}; + assign _zz_rspContext_source = io_output_rsp_payload_fragment_context; + assign rspContext_source = _zz_rspContext_source[0 : 0]; + assign rspContext_context = _zz_rspContext_source[21 : 1]; + assign io_input_rsp_valid = io_output_rsp_valid; + assign io_output_rsp_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = io_output_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_input_rsp_payload_fragment_source = rspContext_source; + assign io_input_rsp_payload_fragment_context = rspContext_context; + +endmodule + +module EfxDMA_BufferCC_6 ( + input wire [1:0] io_dataIn, + output wire [1:0] io_dataOut, + input wire ctrl_clk, + input wire ctrl_reset +); + + (* async_reg = "true" *) reg [1:0] buffers_0; + (* async_reg = "true" *) reg [1:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge ctrl_clk) begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + + +endmodule + +module EfxDMA_Apb3CC ( + input wire [13:0] io_input_PADDR, + input wire [0:0] io_input_PSEL, + input wire io_input_PENABLE, + output wire io_input_PREADY, + input wire io_input_PWRITE, + input wire [31:0] io_input_PWDATA, + output wire [31:0] io_input_PRDATA, + output wire io_input_PSLVERROR, + output wire [13:0] io_output_PADDR, + output reg [0:0] io_output_PSEL, + output reg io_output_PENABLE, + input wire io_output_PREADY, + output wire io_output_PWRITE, + output wire [31:0] io_output_PWDATA, + input wire [31:0] io_output_PRDATA, + input wire io_output_PSLVERROR, + input wire ctrl_clk, + input wire ctrl_reset, + input wire clk, + input wire reset +); + + wire flowCCUnsafeByToggle_io_output_valid; + wire [13:0] flowCCUnsafeByToggle_io_output_payload_PADDR; + wire flowCCUnsafeByToggle_io_output_payload_PWRITE; + wire [31:0] flowCCUnsafeByToggle_io_output_payload_PWDATA; + wire flowCCUnsafeByToggle_1_io_output_valid; + wire [31:0] flowCCUnsafeByToggle_1_io_output_payload_PRDATA; + wire flowCCUnsafeByToggle_1_io_output_payload_PSLVERROR; + wire inputLogic_inputCmd_valid; + wire [13:0] inputLogic_inputCmd_payload_PADDR; + wire inputLogic_inputCmd_payload_PWRITE; + wire [31:0] inputLogic_inputCmd_payload_PWDATA; + wire inputLogic_inputRsp_valid; + wire [31:0] inputLogic_inputRsp_payload_PRDATA; + wire inputLogic_inputRsp_payload_PSLVERROR; + reg inputLogic_state; + wire flowCCUnsafeByToggle_io_output_toStream_valid; + reg flowCCUnsafeByToggle_io_output_toStream_ready; + wire [13:0] flowCCUnsafeByToggle_io_output_toStream_payload_PADDR; + wire flowCCUnsafeByToggle_io_output_toStream_payload_PWRITE; + wire [31:0] flowCCUnsafeByToggle_io_output_toStream_payload_PWDATA; + wire outputLogic_outputCmd_valid; + reg outputLogic_outputCmd_ready; + wire [13:0] outputLogic_outputCmd_payload_PADDR; + wire outputLogic_outputCmd_payload_PWRITE; + wire [31:0] outputLogic_outputCmd_payload_PWDATA; + reg flowCCUnsafeByToggle_io_output_toStream_rValid; + wire flowCCUnsafeByToggle_io_output_toStream_fire; + (* async_reg = "true" *) reg [13:0] flowCCUnsafeByToggle_io_output_toStream_rData_PADDR; + (* async_reg = "true" *) reg flowCCUnsafeByToggle_io_output_toStream_rData_PWRITE; + (* async_reg = "true" *) reg [31:0] flowCCUnsafeByToggle_io_output_toStream_rData_PWDATA; + wire when_Stream_l375; + reg outputLogic_state; + wire when_Apb3CCToggle_l81; + wire outputLogic_outputRsp_valid; + wire [31:0] outputLogic_outputRsp_payload_PRDATA; + wire outputLogic_outputRsp_payload_PSLVERROR; + wire outputLogic_outputCmd_fire; + + EfxDMA_FlowCCUnsafeByToggle flowCCUnsafeByToggle ( + .io_input_valid (inputLogic_inputCmd_valid ), //i + .io_input_payload_PADDR (inputLogic_inputCmd_payload_PADDR[13:0] ), //i + .io_input_payload_PWRITE (inputLogic_inputCmd_payload_PWRITE ), //i + .io_input_payload_PWDATA (inputLogic_inputCmd_payload_PWDATA[31:0] ), //i + .io_output_valid (flowCCUnsafeByToggle_io_output_valid ), //o + .io_output_payload_PADDR (flowCCUnsafeByToggle_io_output_payload_PADDR[13:0] ), //o + .io_output_payload_PWRITE (flowCCUnsafeByToggle_io_output_payload_PWRITE ), //o + .io_output_payload_PWDATA (flowCCUnsafeByToggle_io_output_payload_PWDATA[31:0]), //o + .ctrl_clk (ctrl_clk ), //i + .ctrl_reset (ctrl_reset ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_FlowCCUnsafeByToggle_1 flowCCUnsafeByToggle_1 ( + .io_input_valid (outputLogic_outputRsp_valid ), //i + .io_input_payload_PRDATA (outputLogic_outputRsp_payload_PRDATA[31:0] ), //i + .io_input_payload_PSLVERROR (outputLogic_outputRsp_payload_PSLVERROR ), //i + .io_output_valid (flowCCUnsafeByToggle_1_io_output_valid ), //o + .io_output_payload_PRDATA (flowCCUnsafeByToggle_1_io_output_payload_PRDATA[31:0]), //o + .io_output_payload_PSLVERROR (flowCCUnsafeByToggle_1_io_output_payload_PSLVERROR ), //o + .clk (clk ), //i + .reset (reset ), //i + .ctrl_clk (ctrl_clk ), //i + .ctrl_reset (ctrl_reset ) //i + ); + assign inputLogic_inputCmd_valid = ((io_input_PSEL[0] && io_input_PENABLE) && (! inputLogic_state)); + assign inputLogic_inputCmd_payload_PADDR = io_input_PADDR; + assign inputLogic_inputCmd_payload_PWRITE = io_input_PWRITE; + assign inputLogic_inputCmd_payload_PWDATA = io_input_PWDATA; + assign io_input_PREADY = inputLogic_inputRsp_valid; + assign io_input_PRDATA = inputLogic_inputRsp_payload_PRDATA; + assign io_input_PSLVERROR = inputLogic_inputRsp_payload_PSLVERROR; + assign flowCCUnsafeByToggle_io_output_toStream_valid = flowCCUnsafeByToggle_io_output_valid; + assign flowCCUnsafeByToggle_io_output_toStream_payload_PADDR = flowCCUnsafeByToggle_io_output_payload_PADDR; + assign flowCCUnsafeByToggle_io_output_toStream_payload_PWRITE = flowCCUnsafeByToggle_io_output_payload_PWRITE; + assign flowCCUnsafeByToggle_io_output_toStream_payload_PWDATA = flowCCUnsafeByToggle_io_output_payload_PWDATA; + assign flowCCUnsafeByToggle_io_output_toStream_fire = (flowCCUnsafeByToggle_io_output_toStream_valid && flowCCUnsafeByToggle_io_output_toStream_ready); + always @(*) begin + flowCCUnsafeByToggle_io_output_toStream_ready = outputLogic_outputCmd_ready; + if(when_Stream_l375) begin + flowCCUnsafeByToggle_io_output_toStream_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! outputLogic_outputCmd_valid); + assign outputLogic_outputCmd_valid = flowCCUnsafeByToggle_io_output_toStream_rValid; + assign outputLogic_outputCmd_payload_PADDR = flowCCUnsafeByToggle_io_output_toStream_rData_PADDR; + assign outputLogic_outputCmd_payload_PWRITE = flowCCUnsafeByToggle_io_output_toStream_rData_PWRITE; + assign outputLogic_outputCmd_payload_PWDATA = flowCCUnsafeByToggle_io_output_toStream_rData_PWDATA; + always @(*) begin + io_output_PENABLE = 1'b0; + if(outputLogic_outputCmd_valid) begin + if(when_Apb3CCToggle_l81) begin + io_output_PENABLE = 1'b0; + end else begin + io_output_PENABLE = 1'b1; + end + end + end + + always @(*) begin + io_output_PSEL = 1'b0; + if(outputLogic_outputCmd_valid) begin + io_output_PSEL = 1'b1; + end + end + + assign io_output_PADDR = outputLogic_outputCmd_payload_PADDR; + assign io_output_PWDATA = outputLogic_outputCmd_payload_PWDATA; + assign io_output_PWRITE = outputLogic_outputCmd_payload_PWRITE; + always @(*) begin + outputLogic_outputCmd_ready = 1'b0; + if(outputLogic_outputCmd_valid) begin + if(!when_Apb3CCToggle_l81) begin + if(io_output_PREADY) begin + outputLogic_outputCmd_ready = 1'b1; + end + end + end + end + + assign when_Apb3CCToggle_l81 = (! outputLogic_state); + assign outputLogic_outputCmd_fire = (outputLogic_outputCmd_valid && outputLogic_outputCmd_ready); + assign outputLogic_outputRsp_valid = outputLogic_outputCmd_fire; + assign outputLogic_outputRsp_payload_PRDATA = io_output_PRDATA; + assign outputLogic_outputRsp_payload_PSLVERROR = io_output_PSLVERROR; + assign inputLogic_inputRsp_valid = flowCCUnsafeByToggle_1_io_output_valid; + assign inputLogic_inputRsp_payload_PRDATA = flowCCUnsafeByToggle_1_io_output_payload_PRDATA; + assign inputLogic_inputRsp_payload_PSLVERROR = flowCCUnsafeByToggle_1_io_output_payload_PSLVERROR; + always @(posedge ctrl_clk) begin + if(ctrl_reset) begin + inputLogic_state <= 1'b0; + end else begin + if(inputLogic_inputCmd_valid) begin + inputLogic_state <= 1'b1; + end + if(inputLogic_inputRsp_valid) begin + inputLogic_state <= 1'b0; + end + end + end + + always @(posedge clk) begin + if(reset) begin + flowCCUnsafeByToggle_io_output_toStream_rValid <= 1'b0; + outputLogic_state <= 1'b0; + end else begin + if(flowCCUnsafeByToggle_io_output_toStream_ready) begin + flowCCUnsafeByToggle_io_output_toStream_rValid <= flowCCUnsafeByToggle_io_output_toStream_valid; + end + if(outputLogic_outputCmd_valid) begin + if(when_Apb3CCToggle_l81) begin + outputLogic_state <= 1'b1; + end else begin + if(io_output_PREADY) begin + outputLogic_state <= 1'b0; + end + end + end + end + end + + always @(posedge clk) begin + if(flowCCUnsafeByToggle_io_output_toStream_fire) begin + flowCCUnsafeByToggle_io_output_toStream_rData_PADDR <= flowCCUnsafeByToggle_io_output_toStream_payload_PADDR; + flowCCUnsafeByToggle_io_output_toStream_rData_PWRITE <= flowCCUnsafeByToggle_io_output_toStream_payload_PWRITE; + flowCCUnsafeByToggle_io_output_toStream_rData_PWDATA <= flowCCUnsafeByToggle_io_output_toStream_payload_PWDATA; + end + end + + +endmodule + +module EfxDMA_Core ( + output wire io_sgRead_cmd_valid, + input wire io_sgRead_cmd_ready, + output wire io_sgRead_cmd_payload_last, + output wire [0:0] io_sgRead_cmd_payload_fragment_opcode, + output wire [31:0] io_sgRead_cmd_payload_fragment_address, + output wire [4:0] io_sgRead_cmd_payload_fragment_length, + output wire [0:0] io_sgRead_cmd_payload_fragment_context, + input wire io_sgRead_rsp_valid, + output wire io_sgRead_rsp_ready, + input wire io_sgRead_rsp_payload_last, + input wire [0:0] io_sgRead_rsp_payload_fragment_opcode, + input wire [127:0] io_sgRead_rsp_payload_fragment_data, + input wire [0:0] io_sgRead_rsp_payload_fragment_context, + output wire io_sgWrite_cmd_valid, + input wire io_sgWrite_cmd_ready, + output wire io_sgWrite_cmd_payload_last, + output wire [0:0] io_sgWrite_cmd_payload_fragment_opcode, + output wire [31:0] io_sgWrite_cmd_payload_fragment_address, + output wire [1:0] io_sgWrite_cmd_payload_fragment_length, + output reg [127:0] io_sgWrite_cmd_payload_fragment_data, + output reg [15:0] io_sgWrite_cmd_payload_fragment_mask, + output wire [0:0] io_sgWrite_cmd_payload_fragment_context, + input wire io_sgWrite_rsp_valid, + output wire io_sgWrite_rsp_ready, + input wire io_sgWrite_rsp_payload_last, + input wire [0:0] io_sgWrite_rsp_payload_fragment_opcode, + input wire [0:0] io_sgWrite_rsp_payload_fragment_context, + output reg io_read_cmd_valid, + input wire io_read_cmd_ready, + output wire io_read_cmd_payload_last, + output wire [0:0] io_read_cmd_payload_fragment_opcode, + output wire [31:0] io_read_cmd_payload_fragment_address, + output wire [11:0] io_read_cmd_payload_fragment_length, + output wire [20:0] io_read_cmd_payload_fragment_context, + input wire io_read_rsp_valid, + output wire io_read_rsp_ready, + input wire io_read_rsp_payload_last, + input wire [0:0] io_read_rsp_payload_fragment_opcode, + input wire [127:0] io_read_rsp_payload_fragment_data, + input wire [20:0] io_read_rsp_payload_fragment_context, + output wire io_write_cmd_valid, + input wire io_write_cmd_ready, + output wire io_write_cmd_payload_last, + output wire [0:0] io_write_cmd_payload_fragment_opcode, + output wire [31:0] io_write_cmd_payload_fragment_address, + output wire [11:0] io_write_cmd_payload_fragment_length, + output wire [127:0] io_write_cmd_payload_fragment_data, + output wire [15:0] io_write_cmd_payload_fragment_mask, + output wire [12:0] io_write_cmd_payload_fragment_context, + input wire io_write_rsp_valid, + output wire io_write_rsp_ready, + input wire io_write_rsp_payload_last, + input wire [0:0] io_write_rsp_payload_fragment_opcode, + input wire [12:0] io_write_rsp_payload_fragment_context, + output wire io_outputs_0_valid, + input wire io_outputs_0_ready, + output wire [63:0] io_outputs_0_payload_data, + output wire [7:0] io_outputs_0_payload_mask, + output wire [3:0] io_outputs_0_payload_sink, + output wire io_outputs_0_payload_last, + input wire io_inputs_0_valid, + output reg io_inputs_0_ready, + input wire [63:0] io_inputs_0_payload_data, + input wire [7:0] io_inputs_0_payload_mask, + input wire [3:0] io_inputs_0_payload_sink, + input wire io_inputs_0_payload_last, + output reg [1:0] io_interrupts, + input wire [13:0] io_ctrl_PADDR, + input wire [0:0] io_ctrl_PSEL, + input wire io_ctrl_PENABLE, + output wire io_ctrl_PREADY, + input wire io_ctrl_PWRITE, + input wire [31:0] io_ctrl_PWDATA, + output reg [31:0] io_ctrl_PRDATA, + output wire io_ctrl_PSLVERROR, + output wire ll_0_descriptorUpdate, + output wire ll_1_descriptorUpdate, + input wire clk, + input wire reset +); + + wire [9:0] memory_core_io_writes_0_cmd_payload_address; + wire [6:0] memory_core_io_writes_0_cmd_payload_context; + wire [9:0] memory_core_io_writes_1_cmd_payload_address; + reg [15:0] memory_core_io_writes_1_cmd_payload_mask; + wire [6:0] memory_core_io_writes_1_cmd_payload_context; + wire memory_core_io_reads_0_cmd_valid; + wire [9:0] memory_core_io_reads_0_cmd_payload_address; + wire [2:0] memory_core_io_reads_0_cmd_payload_context; + wire [9:0] memory_core_io_reads_1_cmd_payload_address; + wire [11:0] memory_core_io_reads_1_cmd_payload_context; + wire [15:0] b2m_fsm_aggregate_engine_io_input_payload_mask; + wire b2m_fsm_aggregate_engine_io_flush; + wire [3:0] b2m_fsm_aggregate_engine_io_offset; + wire memory_core_io_writes_0_cmd_ready; + wire memory_core_io_writes_0_rsp_valid; + wire [6:0] memory_core_io_writes_0_rsp_payload_context; + wire memory_core_io_writes_1_cmd_ready; + wire memory_core_io_writes_1_rsp_valid; + wire [6:0] memory_core_io_writes_1_rsp_payload_context; + wire memory_core_io_reads_0_cmd_ready; + wire memory_core_io_reads_0_rsp_valid; + wire [63:0] memory_core_io_reads_0_rsp_payload_data; + wire [7:0] memory_core_io_reads_0_rsp_payload_mask; + wire [2:0] memory_core_io_reads_0_rsp_payload_context; + wire memory_core_io_reads_1_cmd_ready; + wire memory_core_io_reads_1_rsp_valid; + wire [127:0] memory_core_io_reads_1_rsp_payload_data; + wire [15:0] memory_core_io_reads_1_rsp_payload_mask; + wire [11:0] memory_core_io_reads_1_rsp_payload_context; + wire b2m_fsm_aggregate_engine_io_input_ready; + wire [127:0] b2m_fsm_aggregate_engine_io_output_data; + wire [15:0] b2m_fsm_aggregate_engine_io_output_mask; + wire b2m_fsm_aggregate_engine_io_output_consumed; + wire [3:0] b2m_fsm_aggregate_engine_io_output_usedUntil; + wire [26:0] _zz_channels_0_bytesProbe_value; + wire [26:0] _zz_channels_0_bytesProbe_value_1; + wire [13:0] _zz_channels_0_fifo_pop_withOverride_backupNext; + wire [13:0] _zz_channels_0_fifo_pop_withOverride_exposed; + wire [26:0] _zz_channels_0_pop_b2m_selfFlush; + wire [13:0] _zz_channels_0_pop_b2m_request; + wire [10:0] _zz_channels_0_pop_b2m_request_1; + wire [9:0] _zz_channels_0_pop_b2m_request_2; + wire [3:0] _zz_channels_0_pop_b2m_memPending; + wire [3:0] _zz_channels_0_pop_b2m_memPending_1; + wire [0:0] _zz_channels_0_pop_b2m_memPending_2; + wire [3:0] _zz_channels_0_pop_b2m_memPending_3; + wire [0:0] _zz_channels_0_pop_b2m_memPending_4; + wire [10:0] _zz_channels_0_fifo_push_available; + wire [26:0] _zz_channels_1_bytesProbe_value; + wire [26:0] _zz_channels_1_bytesProbe_value_1; + wire [13:0] _zz_channels_1_fifo_pop_withoutOverride_exposed; + wire [3:0] _zz_channels_1_push_m2b_memPending; + wire [3:0] _zz_channels_1_push_m2b_memPending_1; + wire [0:0] _zz_channels_1_push_m2b_memPending_2; + wire [3:0] _zz_channels_1_push_m2b_memPending_3; + wire [0:0] _zz_channels_1_push_m2b_memPending_4; + wire [10:0] _zz_channels_1_push_m2b_loadRequest; + wire [8:0] _zz_channels_1_push_m2b_loadRequest_1; + wire [25:0] _zz_when_DmaSg_l486; + wire [10:0] _zz_channels_1_fifo_push_available; + wire [0:0] _zz_s2b_0_cmd_firsts; + wire [4:0] _zz_s2b_0_cmd_firsts_1; + wire [3:0] _zz_s2b_0_cmd_byteCount_8; + reg [3:0] _zz_s2b_0_cmd_byteCount_9; + wire [2:0] _zz_s2b_0_cmd_byteCount_10; + reg [3:0] _zz_s2b_0_cmd_byteCount_11; + wire [2:0] _zz_s2b_0_cmd_byteCount_12; + reg [3:0] _zz_s2b_0_cmd_byteCount_13; + wire [2:0] _zz_s2b_0_cmd_byteCount_14; + wire [1:0] _zz_s2b_0_cmd_byteCount_15; + wire [1:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2; + wire [1:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2_1; + wire [0:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2_2; + reg [0:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3; + wire [25:0] _zz_m2b_cmd_s0_length; + wire [25:0] _zz_m2b_cmd_s0_length_1; + wire [25:0] _zz_m2b_cmd_s0_length_2; + wire [25:0] _zz_m2b_cmd_s0_lastBurst; + wire [31:0] _zz_m2b_cmd_s1_context_stop; + wire [31:0] _zz_m2b_cmd_s1_context_stop_1; + wire [31:0] _zz_m2b_cmd_s1_addressNext; + wire [31:0] _zz_m2b_cmd_s1_addressNext_1; + wire [25:0] _zz_m2b_cmd_s1_byteLeftNext; + wire [25:0] _zz_m2b_cmd_s1_byteLeftNext_1; + wire [12:0] _zz_m2b_cmd_s1_fifoPushDecr; + wire [11:0] _zz_m2b_cmd_s1_fifoPushDecr_1; + wire [11:0] _zz_m2b_cmd_s1_fifoPushDecr_2; + wire [3:0] _zz_m2b_cmd_s1_fifoPushDecr_3; + wire [12:0] _zz_m2b_cmd_s1_fifoPushDecr_4; + wire [1:0] _zz_m2b_cmd_s1_fifoPushDecr_5; + wire [1:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2; + wire [1:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_1; + wire [0:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_2; + reg [0:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3; + wire [0:0] _zz_when; + wire [12:0] _zz_b2m_fsm_bytesInBurstP1; + wire [1:0] _zz_b2m_fsm_bytesInBurstP1_1; + wire [31:0] _zz_b2m_fsm_addressNext; + wire [26:0] _zz_b2m_fsm_bytesLeftNext; + wire [13:0] _zz_b2m_fsm_bytesLeftNext_1; + wire [25:0] _zz__zz_b2m_fsm_sel_bytesInBurst_1; + wire [25:0] _zz__zz_b2m_fsm_sel_bytesInBurst_1_1; + wire [11:0] _zz__zz_b2m_fsm_sel_bytesInBurst_2; + wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_3; + wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_4; + wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_5; + wire [13:0] _zz_b2m_fsm_fifoCompletion; + wire [13:0] _zz_b2m_fsm_fifoCompletion_1; + wire [11:0] _zz_b2m_fsm_beatCounter; + wire [11:0] _zz_b2m_fsm_beatCounter_1; + wire [3:0] _zz_b2m_fsm_beatCounter_2; + wire [10:0] _zz_b2m_fsm_sel_ptr; + wire [3:0] _zz_b2m_fsm_aggregate_bytesToSkipMask; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_1; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_2; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_3; + wire [0:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_4; + wire [9:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_5; + wire [3:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_6; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_7; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_8; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_9; + wire [0:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_10; + wire [3:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_11; + wire [3:0] _zz_b2m_fsm_cmd_maskLastTriggerComb; + wire [3:0] _zz_b2m_fsm_cmd_maskLast; + wire _zz_b2m_fsm_cmd_maskLast_1; + wire [0:0] _zz_b2m_fsm_cmd_maskLast_2; + wire [7:0] _zz_b2m_fsm_cmd_maskLast_3; + wire [3:0] _zz_b2m_fsm_cmd_maskLast_4; + wire [3:0] _zz_b2m_fsm_cmd_maskLast_5; + wire [3:0] _zz_b2m_fsm_cmd_maskFirst; + wire _zz_b2m_fsm_cmd_maskFirst_1; + wire [0:0] _zz_b2m_fsm_cmd_maskFirst_2; + wire [7:0] _zz_b2m_fsm_cmd_maskFirst_3; + wire [3:0] _zz_b2m_fsm_cmd_maskFirst_4; + wire [3:0] _zz_b2m_fsm_cmd_maskFirst_5; + wire [0:0] _zz_when_1; + wire [0:0] _zz_when_2; + wire [1:0] _zz__zz_ll_arbiter_head_1; + wire [1:0] _zz__zz_ll_arbiter_head_1_1; + wire [1:0] _zz_ll_arbiter_head_2; + wire [1:0] _zz_ll_arbiter_isJustASink; + wire [1:0] _zz_ll_arbiter_doDescriptorStall; + wire [1:0] _zz_ll_arbiter_onSgStream; + wire [1:0] _zz_ll_cmd_ptr; + wire [1:0] _zz_ll_cmd_ptrNext; + wire [1:0] _zz_ll_cmd_endOfPacket; + wire [0:0] _zz_channels_0_channelStart; + wire [0:0] _zz_channels_0_ctrl_kick; + wire [0:0] _zz_channels_0_channelStart_1; + wire [0:0] _zz_channels_0_ll_sgStart; + wire [0:0] _zz_channels_0_interrupts_completion_valid; + wire [0:0] _zz_channels_0_interrupts_onChannelCompletion_valid; + wire [0:0] _zz_channels_0_interrupts_onLinkedListUpdate_valid; + wire [0:0] _zz_channels_0_interrupts_s2mPacket_valid; + wire [0:0] _zz_channels_1_channelStart; + wire [0:0] _zz_channels_1_ctrl_kick; + wire [0:0] _zz_channels_1_channelStart_1; + wire [0:0] _zz_channels_1_ll_sgStart; + wire [0:0] _zz_channels_1_interrupts_completion_valid; + wire [0:0] _zz_channels_1_interrupts_onChannelCompletion_valid; + wire [0:0] _zz_channels_1_interrupts_onLinkedListUpdate_valid; + wire [31:0] _zz_io_ctrl_PRDATA; + wire [31:0] _zz_io_ctrl_PRDATA_1; + wire [10:0] _zz_channels_0_fifo_push_ptrIncr_value; + wire [0:0] _zz_channels_0_fifo_push_ptrIncr_value_1; + wire [13:0] _zz_channels_0_fifo_pop_bytesIncr_value_1; + wire [3:0] _zz_channels_0_fifo_pop_bytesIncr_value_2; + wire [10:0] _zz_channels_0_fifo_pop_ptrIncr_value; + wire [1:0] _zz_channels_0_fifo_pop_ptrIncr_value_1; + wire [10:0] _zz_channels_1_fifo_push_ptrIncr_value_1; + wire [1:0] _zz_channels_1_fifo_push_ptrIncr_value_2; + wire [13:0] _zz_channels_1_fifo_pop_bytesIncr_value_1; + wire [4:0] _zz_channels_1_fifo_pop_bytesIncr_value_2; + wire [4:0] _zz_channels_1_fifo_pop_bytesIncr_value_3; + wire [10:0] _zz_channels_1_fifo_pop_ptrIncr_value; + wire [0:0] _zz_channels_1_fifo_pop_ptrIncr_value_1; + wire ctrl_readErrorFlag; + wire ctrl_writeErrorFlag; + wire ctrl_askWrite; + wire ctrl_askRead; + wire ctrl_doWrite; + wire ctrl_doRead; + reg channels_0_channelStart; + reg channels_0_channelStop; + reg channels_0_channelCompletion; + reg channels_0_channelValid; + reg channels_0_descriptorStart; + reg channels_0_descriptorCompletion; + reg channels_0_descriptorValid; + reg [25:0] channels_0_bytes; + reg [1:0] channels_0_priority; + reg [1:0] channels_0_weight; + reg channels_0_readyToStop; + reg [26:0] channels_0_bytesProbe_value; + reg channels_0_bytesProbe_incr_valid; + reg [11:0] channels_0_bytesProbe_incr_payload; + reg channels_0_ctrl_kick; + reg channels_0_ll_sgStart; + reg channels_0_ll_valid; + reg channels_0_ll_onSgStream; + reg channels_0_ll_head; + reg channels_0_ll_justASync; + reg channels_0_ll_waitDone; + reg channels_0_ll_readDone; + reg channels_0_ll_writeDone; + reg channels_0_ll_gotDescriptorStall; + reg channels_0_ll_controlNoCompletion; + reg channels_0_ll_packet; + reg channels_0_ll_requireSync; + reg [31:0] channels_0_ll_ptr; + reg [31:0] channels_0_ll_ptrNext; + wire channels_0_ll_requestLl; + reg channels_0_ll_descriptorUpdated; + wire when_DmaSg_l318; + wire when_DmaSg_l320; + wire when_DmaSg_l322; + wire when_DmaSg_l328; + wire [10:0] channels_0_fifo_base; + wire [10:0] channels_0_fifo_words; + reg [10:0] channels_0_fifo_push_available; + wire [10:0] channels_0_fifo_push_availableDecr; + reg [10:0] channels_0_fifo_push_ptr; + wire [10:0] channels_0_fifo_push_ptrWithBase; + wire [10:0] channels_0_fifo_push_ptrIncr_value; + reg [10:0] channels_0_fifo_pop_ptr; + wire [13:0] channels_0_fifo_pop_bytes; + wire [10:0] channels_0_fifo_pop_ptrWithBase; + wire [13:0] channels_0_fifo_pop_bytesIncr_value; + wire [13:0] channels_0_fifo_pop_bytesDecr_value; + wire channels_0_fifo_pop_empty; + wire [10:0] channels_0_fifo_pop_ptrIncr_value; + reg [13:0] channels_0_fifo_pop_withOverride_backup; + wire [13:0] channels_0_fifo_pop_withOverride_backupNext; + reg channels_0_fifo_pop_withOverride_load; + reg channels_0_fifo_pop_withOverride_unload; + reg [13:0] channels_0_fifo_pop_withOverride_exposed; + reg channels_0_fifo_pop_withOverride_valid; + wire when_DmaSg_l409; + wire channels_0_fifo_empty; + reg channels_0_push_memory; + reg channels_0_push_s2b_completionOnLast; + reg channels_0_push_s2b_packetEvent; + reg channels_0_push_s2b_packetLock; + reg channels_0_push_s2b_waitFirst; + wire when_DmaSg_l457; + reg channels_0_pop_memory; + wire [11:0] channels_0_pop_b2m_bytePerBurst; + reg channels_0_pop_b2m_fire; + reg channels_0_pop_b2m_waitFinalRsp; + reg channels_0_pop_b2m_flush; + reg channels_0_pop_b2m_packetSync; + reg channels_0_pop_b2m_packet; + wire when_DmaSg_l505; + reg channels_0_pop_b2m_memRsp; + reg [3:0] channels_0_pop_b2m_memPending; + reg [31:0] channels_0_pop_b2m_address; + reg [26:0] channels_0_pop_b2m_bytesLeft; + wire channels_0_pop_b2m_selfFlush; + wire channels_0_pop_b2m_request; + reg [3:0] channels_0_pop_b2m_bytesToSkip; + reg [13:0] channels_0_pop_b2m_decrBytes; + reg channels_0_pop_b2m_memPendingInc; + wire when_DmaSg_l523; + wire when_DmaSg_l532; + wire when_DmaSg_l536; + wire when_DmaSg_l547; + wire when_DmaSg_l563; + wire channels_0_readyForChannelCompletion; + wire when_DmaSg_l575; + reg _zz_when_DmaSg_l593; + wire when_DmaSg_l593; + wire channels_0_s2b_full; + reg [10:0] channels_0_fifo_pop_ptrIncr_value_regNext; + wire when_DmaSg_l255; + reg channels_0_interrupts_completion_enable; + reg channels_0_interrupts_completion_valid; + wire when_DmaSg_l255_1; + wire when_DmaSg_l255_2; + reg channels_0_interrupts_onChannelCompletion_enable; + reg channels_0_interrupts_onChannelCompletion_valid; + wire when_DmaSg_l255_3; + reg channels_0_interrupts_onLinkedListUpdate_enable; + reg channels_0_interrupts_onLinkedListUpdate_valid; + wire when_DmaSg_l255_4; + reg channels_0_interrupts_s2mPacket_enable; + reg channels_0_interrupts_s2mPacket_valid; + wire when_DmaSg_l255_5; + wire when_DmaSg_l625; + reg channels_1_channelStart; + reg channels_1_channelStop; + reg channels_1_channelCompletion; + reg channels_1_channelValid; + reg channels_1_descriptorStart; + reg channels_1_descriptorCompletion; + reg channels_1_descriptorValid; + reg [25:0] channels_1_bytes; + reg [1:0] channels_1_priority; + reg [1:0] channels_1_weight; + reg channels_1_readyToStop; + reg [26:0] channels_1_bytesProbe_value; + reg channels_1_bytesProbe_incr_valid; + reg [11:0] channels_1_bytesProbe_incr_payload; + reg channels_1_ctrl_kick; + reg channels_1_ll_sgStart; + reg channels_1_ll_valid; + reg channels_1_ll_onSgStream; + reg channels_1_ll_head; + reg channels_1_ll_justASync; + reg channels_1_ll_waitDone; + reg channels_1_ll_readDone; + reg channels_1_ll_writeDone; + reg channels_1_ll_gotDescriptorStall; + reg channels_1_ll_controlNoCompletion; + reg channels_1_ll_packet; + reg channels_1_ll_requireSync; + reg [31:0] channels_1_ll_ptr; + reg [31:0] channels_1_ll_ptrNext; + wire channels_1_ll_requestLl; + reg channels_1_ll_descriptorUpdated; + wire when_DmaSg_l318_1; + wire when_DmaSg_l320_1; + wire when_DmaSg_l322_1; + wire when_DmaSg_l328_1; + wire [10:0] channels_1_fifo_base; + wire [10:0] channels_1_fifo_words; + reg [10:0] channels_1_fifo_push_available; + reg [10:0] channels_1_fifo_push_availableDecr; + reg [10:0] channels_1_fifo_push_ptr; + wire [10:0] channels_1_fifo_push_ptrWithBase; + wire [10:0] channels_1_fifo_push_ptrIncr_value; + reg [10:0] channels_1_fifo_pop_ptr; + wire [13:0] channels_1_fifo_pop_bytes; + wire [10:0] channels_1_fifo_pop_ptrWithBase; + wire [13:0] channels_1_fifo_pop_bytesIncr_value; + wire [13:0] channels_1_fifo_pop_bytesDecr_value; + wire channels_1_fifo_pop_empty; + wire [10:0] channels_1_fifo_pop_ptrIncr_value; + reg [13:0] channels_1_fifo_pop_withoutOverride_exposed; + wire channels_1_fifo_empty; + reg channels_1_push_memory; + reg [31:0] channels_1_push_m2b_address; + wire [11:0] channels_1_push_m2b_bytePerBurst; + reg channels_1_push_m2b_loadDone; + reg [25:0] channels_1_push_m2b_bytesLeft; + reg [3:0] channels_1_push_m2b_memPending; + reg channels_1_push_m2b_memPendingIncr; + reg channels_1_push_m2b_memPendingDecr; + reg channels_1_push_m2b_loadRequest; + reg channels_1_pop_memory; + reg channels_1_pop_b2s_last; + reg [3:0] channels_1_pop_b2s_sinkId; + reg channels_1_pop_b2s_veryLastTrigger; + reg channels_1_pop_b2s_veryLastValid; + wire when_DmaSg_l474; + reg [10:0] channels_1_pop_b2s_veryLastPtr; + reg channels_1_pop_b2s_veryLastEndPacket; + wire when_DmaSg_l483; + wire when_DmaSg_l486; + wire when_DmaSg_l562; + reg channels_1_readyForChannelCompletion; + wire when_DmaSg_l566; + wire when_DmaSg_l575_1; + reg _zz_when_DmaSg_l593_1; + wire when_DmaSg_l593_1; + wire channels_1_s2b_full; + reg [10:0] channels_1_fifo_pop_ptrIncr_value_regNext; + wire when_DmaSg_l255_6; + reg channels_1_interrupts_completion_enable; + reg channels_1_interrupts_completion_valid; + wire when_DmaSg_l255_7; + wire when_DmaSg_l255_8; + reg channels_1_interrupts_onChannelCompletion_enable; + reg channels_1_interrupts_onChannelCompletion_valid; + wire when_DmaSg_l255_9; + reg channels_1_interrupts_onLinkedListUpdate_enable; + reg channels_1_interrupts_onLinkedListUpdate_valid; + wire when_DmaSg_l255_10; + wire when_DmaSg_l625_1; + wire io_inputs_0_fire; + wire when_package_l12; + reg io_inputs_0_payload_last_regNextWhen; + wire when_package_l12_1; + reg io_inputs_0_payload_last_regNextWhen_1; + wire when_package_l12_2; + reg io_inputs_0_payload_last_regNextWhen_2; + wire when_package_l12_3; + reg io_inputs_0_payload_last_regNextWhen_3; + wire when_package_l12_4; + reg io_inputs_0_payload_last_regNextWhen_4; + wire when_package_l12_5; + reg io_inputs_0_payload_last_regNextWhen_5; + wire when_package_l12_6; + reg io_inputs_0_payload_last_regNextWhen_6; + wire when_package_l12_7; + reg io_inputs_0_payload_last_regNextWhen_7; + wire when_package_l12_8; + reg io_inputs_0_payload_last_regNextWhen_8; + wire when_package_l12_9; + reg io_inputs_0_payload_last_regNextWhen_9; + wire when_package_l12_10; + reg io_inputs_0_payload_last_regNextWhen_10; + wire when_package_l12_11; + reg io_inputs_0_payload_last_regNextWhen_11; + wire when_package_l12_12; + reg io_inputs_0_payload_last_regNextWhen_12; + wire when_package_l12_13; + reg io_inputs_0_payload_last_regNextWhen_13; + wire when_package_l12_14; + reg io_inputs_0_payload_last_regNextWhen_14; + wire when_package_l12_15; + reg io_inputs_0_payload_last_regNextWhen_15; + wire [15:0] s2b_0_cmd_firsts; + wire s2b_0_cmd_first; + wire [0:0] s2b_0_cmd_channelsOh; + wire s2b_0_cmd_noHit; + wire [0:0] s2b_0_cmd_channelsFull; + reg io_inputs_0_thrown_valid; + wire io_inputs_0_thrown_ready; + wire [63:0] io_inputs_0_thrown_payload_data; + wire [7:0] io_inputs_0_thrown_payload_mask; + wire [3:0] io_inputs_0_thrown_payload_sink; + wire io_inputs_0_thrown_payload_last; + wire _zz_io_inputs_0_thrown_ready; + wire s2b_0_cmd_sinkHalted_valid; + wire s2b_0_cmd_sinkHalted_ready; + wire [63:0] s2b_0_cmd_sinkHalted_payload_data; + wire [7:0] s2b_0_cmd_sinkHalted_payload_mask; + wire [3:0] s2b_0_cmd_sinkHalted_payload_sink; + wire s2b_0_cmd_sinkHalted_payload_last; + wire [3:0] _zz_s2b_0_cmd_byteCount; + wire [3:0] _zz_s2b_0_cmd_byteCount_1; + wire [3:0] _zz_s2b_0_cmd_byteCount_2; + wire [3:0] _zz_s2b_0_cmd_byteCount_3; + wire [3:0] _zz_s2b_0_cmd_byteCount_4; + wire [3:0] _zz_s2b_0_cmd_byteCount_5; + wire [3:0] _zz_s2b_0_cmd_byteCount_6; + wire [3:0] _zz_s2b_0_cmd_byteCount_7; + wire [3:0] s2b_0_cmd_byteCount; + wire [0:0] s2b_0_cmd_context_channel; + wire [3:0] s2b_0_cmd_context_bytes; + wire s2b_0_cmd_context_flush; + wire s2b_0_cmd_context_packet; + wire memory_core_io_writes_0_cmd_fire; + wire when_DmaSg_l665; + wire [0:0] s2b_0_rsp_context_channel; + wire [3:0] s2b_0_rsp_context_bytes; + wire s2b_0_rsp_context_flush; + wire s2b_0_rsp_context_packet; + wire [6:0] _zz_s2b_0_rsp_context_channel; + wire _zz_channels_0_fifo_pop_bytesIncr_value; + wire when_DmaSg_l679; + wire when_DmaSg_l681; + wire when_DmaSg_l682; + wire [0:0] b2s_0_cmd_channelsOh; + wire [0:0] b2s_0_cmd_context_channel; + wire b2s_0_cmd_context_veryLast; + wire b2s_0_cmd_context_endPacket; + wire [10:0] b2s_0_cmd_veryLastPtr; + wire [10:0] b2s_0_cmd_address; + wire [0:0] b2s_0_rsp_context_channel; + wire b2s_0_rsp_context_veryLast; + wire b2s_0_rsp_context_endPacket; + wire [2:0] _zz_b2s_0_rsp_context_channel; + wire io_outputs_0_fire; + wire when_DmaSg_l725; + wire when_DmaSg_l726; + reg m2b_cmd_s0_valid; + wire [1:0] _zz_m2b_cmd_s0_priority_masked; + wire [0:0] m2b_cmd_s0_priority_masked; + reg [0:0] m2b_cmd_s0_priority_roundRobins_0; + reg [0:0] m2b_cmd_s0_priority_roundRobins_1; + reg [0:0] m2b_cmd_s0_priority_roundRobins_2; + reg [0:0] m2b_cmd_s0_priority_roundRobins_3; + reg [1:0] m2b_cmd_s0_priority_counter; + wire [0:0] _zz_m2b_cmd_s0_priority_chosenOh; + wire [1:0] _zz_m2b_cmd_s0_priority_chosenOh_1; + wire [1:0] _zz_m2b_cmd_s0_priority_chosenOh_2; + wire [0:0] m2b_cmd_s0_priority_chosenOh; + wire m2b_cmd_s0_priority_weightLast; + wire [0:0] m2b_cmd_s0_priority_contextNext; + wire when_DmaSg_l758; + wire when_DmaSg_l760; + wire when_DmaSg_l763; + wire when_DmaSg_l763_1; + wire when_DmaSg_l763_2; + wire when_DmaSg_l763_3; + wire when_DmaSg_l773; + wire [31:0] m2b_cmd_s0_address; + wire [25:0] m2b_cmd_s0_bytesLeft; + wire [11:0] m2b_cmd_s0_readAddressBurstRange; + wire [11:0] m2b_cmd_s0_lengthHead; + wire [11:0] m2b_cmd_s0_length; + wire m2b_cmd_s0_lastBurst; + reg m2b_cmd_s1_valid; + reg [31:0] m2b_cmd_s1_address; + reg [11:0] m2b_cmd_s1_length; + reg m2b_cmd_s1_lastBurst; + reg [25:0] m2b_cmd_s1_bytesLeft; + wire [3:0] m2b_cmd_s1_context_start; + wire [3:0] m2b_cmd_s1_context_stop; + wire [11:0] m2b_cmd_s1_context_length; + wire m2b_cmd_s1_context_last; + wire [31:0] m2b_cmd_s1_addressNext; + wire [25:0] m2b_cmd_s1_byteLeftNext; + wire [9:0] m2b_cmd_s1_fifoPushDecr; + wire when_DmaSg_l828; + wire [3:0] m2b_rsp_context_start; + wire [3:0] m2b_rsp_context_stop; + wire [11:0] m2b_rsp_context_length; + wire m2b_rsp_context_last; + wire [20:0] _zz_m2b_rsp_context_start; + wire m2b_rsp_veryLast; + wire io_read_rsp_fire; + wire when_DmaSg_l847; + wire when_DmaSg_l848; + reg m2b_rsp_first; + wire m2b_rsp_writeContext_last; + wire m2b_rsp_writeContext_lastOfBurst; + wire [4:0] m2b_rsp_writeContext_loadByteInNextBeat; + wire memory_core_io_writes_1_cmd_fire; + wire _zz_channels_1_fifo_push_ptrIncr_value; + wire when_DmaSg_l874; + wire m2b_writeRsp_context_last; + wire m2b_writeRsp_context_lastOfBurst; + wire [4:0] m2b_writeRsp_context_loadByteInNextBeat; + wire [6:0] _zz_m2b_writeRsp_context_last; + wire _zz_channels_1_fifo_pop_bytesIncr_value; + wire when_DmaSg_l893; + reg b2m_fsm_sel_valid; + reg b2m_fsm_sel_ready; + reg [11:0] b2m_fsm_sel_bytePerBurst; + reg [11:0] b2m_fsm_sel_bytesInBurst; + reg [13:0] b2m_fsm_sel_bytesInFifo; + reg [31:0] b2m_fsm_sel_address; + reg [10:0] b2m_fsm_sel_ptr; + reg [10:0] b2m_fsm_sel_ptrMask; + reg b2m_fsm_sel_flush; + reg b2m_fsm_sel_packet; + reg [25:0] b2m_fsm_sel_bytesLeft; + reg b2m_fsm_arbiter_logic_valid; + wire [1:0] _zz_b2m_fsm_arbiter_logic_priority_masked; + wire [0:0] b2m_fsm_arbiter_logic_priority_masked; + reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_0; + reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_1; + reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_2; + reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_3; + reg [1:0] b2m_fsm_arbiter_logic_priority_counter; + wire [0:0] _zz_b2m_fsm_arbiter_logic_priority_chosenOh; + wire [1:0] _zz_b2m_fsm_arbiter_logic_priority_chosenOh_1; + wire [1:0] _zz_b2m_fsm_arbiter_logic_priority_chosenOh_2; + wire [0:0] b2m_fsm_arbiter_logic_priority_chosenOh; + wire b2m_fsm_arbiter_logic_priority_weightLast; + wire [0:0] b2m_fsm_arbiter_logic_priority_contextNext; + wire when_DmaSg_l758_1; + wire when_DmaSg_l760_1; + wire when_DmaSg_l763_4; + wire when_DmaSg_l763_5; + wire when_DmaSg_l763_6; + wire when_DmaSg_l763_7; + wire when_DmaSg_l773_1; + wire when_DmaSg_l935; + wire [12:0] b2m_fsm_bytesInBurstP1; + wire [31:0] b2m_fsm_addressNext; + wire [26:0] b2m_fsm_bytesLeftNext; + wire b2m_fsm_isFinalCmd; + reg [7:0] b2m_fsm_beatCounter; + reg b2m_fsm_sel_valid_regNext; + wire b2m_fsm_s0; + reg b2m_fsm_s1; + reg b2m_fsm_s2; + wire when_DmaSg_l986; + wire [13:0] _zz_b2m_fsm_sel_bytesInBurst; + wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_1; + wire [11:0] _zz_b2m_fsm_sel_bytesInBurst_2; + wire b2m_fsm_fifoCompletion; + wire when_DmaSg_l996; + wire when_DmaSg_l1001; + reg b2m_fsm_toggle; + wire when_DmaSg_l1013; + wire [10:0] b2m_fsm_fetch_context_ptr; + wire b2m_fsm_fetch_context_toggle; + wire when_DmaSg_l1033; + wire [10:0] b2m_fsm_aggregate_context_ptr; + wire b2m_fsm_aggregate_context_toggle; + wire [11:0] _zz_b2m_fsm_aggregate_context_ptr; + wire memory_core_io_reads_1_rsp_s2mPipe_valid; + reg memory_core_io_reads_1_rsp_s2mPipe_ready; + wire [127:0] memory_core_io_reads_1_rsp_s2mPipe_payload_data; + wire [15:0] memory_core_io_reads_1_rsp_s2mPipe_payload_mask; + wire [11:0] memory_core_io_reads_1_rsp_s2mPipe_payload_context; + reg memory_core_io_reads_1_rsp_rValidN; + reg [127:0] memory_core_io_reads_1_rsp_rData_data; + reg [15:0] memory_core_io_reads_1_rsp_rData_mask; + reg [11:0] memory_core_io_reads_1_rsp_rData_context; + wire when_Stream_l445; + reg b2m_fsm_aggregate_memoryPort_valid; + wire b2m_fsm_aggregate_memoryPort_ready; + wire [127:0] b2m_fsm_aggregate_memoryPort_payload_data; + wire [15:0] b2m_fsm_aggregate_memoryPort_payload_mask; + wire [11:0] b2m_fsm_aggregate_memoryPort_payload_context; + reg b2m_fsm_aggregate_first; + wire b2m_fsm_aggregate_memoryPort_fire; + wire when_DmaSg_l1050; + wire [3:0] b2m_fsm_aggregate_bytesToSkip; + wire [15:0] b2m_fsm_aggregate_bytesToSkipMask; + reg _zz_io_flush; + wire [3:0] b2m_fsm_cmd_maskFirstTrigger; + wire [3:0] b2m_fsm_cmd_maskLastTriggerComb; + reg [3:0] b2m_fsm_cmd_maskLastTriggerReg; + reg [15:0] b2m_fsm_cmd_maskLast; + wire [15:0] b2m_fsm_cmd_maskFirst; + wire b2m_fsm_cmd_enoughAggregation; + wire io_write_cmd_fire; + reg io_write_cmd_payload_first; + wire b2m_fsm_cmd_doPtrIncr; + wire [11:0] b2m_fsm_cmd_context_length; + wire b2m_fsm_cmd_context_doPacketSync; + wire when_DmaSg_l1102; + wire [11:0] b2m_rsp_context_length; + wire b2m_rsp_context_doPacketSync; + wire [12:0] _zz_b2m_rsp_context_length; + wire io_write_rsp_fire; + wire when_DmaSg_l1116; + wire [1:0] _zz_ll_arbiter_head; + wire _zz_ll_arbiter_head_1; + wire ll_arbiter_head; + wire ll_arbiter_isJustASink; + wire ll_arbiter_doDescriptorStall; + wire ll_arbiter_onSgStream; + reg ll_cmd_valid; + wire when_DmaSg_l1149; + reg ll_cmd_oh_0; + reg ll_cmd_oh_1; + wire when_DmaSg_l1148; + reg [31:0] ll_cmd_ptr; + wire when_DmaSg_l1148_1; + reg [31:0] ll_cmd_ptrNext; + wire when_DmaSg_l1148_2; + reg [26:0] ll_cmd_bytesDone; + wire when_DmaSg_l1148_3; + reg ll_cmd_endOfPacket; + wire when_DmaSg_l1154; + reg ll_cmd_isJustASink; + wire when_DmaSg_l1155; + reg ll_cmd_doDescriptorStall; + wire when_DmaSg_l1156; + reg ll_cmd_onSgStream; + reg ll_cmd_readFired; + reg ll_cmd_writeFired; + wire when_DmaSg_l1160; + wire when_DmaSg_l1161; + wire when_DmaSg_l1169; + wire when_DmaSg_l1169_1; + wire when_DmaSg_l1177; + wire [0:0] ll_cmd_context_channel; + wire [3:0] ll_cmd_writeMaskSplit_0; + wire [3:0] ll_cmd_writeMaskSplit_1; + wire [3:0] ll_cmd_writeMaskSplit_2; + wire [3:0] ll_cmd_writeMaskSplit_3; + wire [31:0] ll_cmd_writeDataSplit_0; + wire [31:0] ll_cmd_writeDataSplit_1; + wire [31:0] ll_cmd_writeDataSplit_2; + wire [31:0] ll_cmd_writeDataSplit_3; + wire io_sgRead_cmd_fire; + wire io_sgWrite_cmd_fire; + wire [0:0] ll_readRsp_context_channel; + wire [1:0] _zz_ll_readRsp_oh_0; + wire ll_readRsp_oh_0; + wire ll_readRsp_oh_1; + reg [0:0] ll_readRsp_beatCounter; + reg ll_readRsp_completed; + wire io_sgRead_rsp_fire; + wire when_DmaSg_l1248; + wire when_DmaSg_l1248_1; + wire when_DmaSg_l1248_2; + wire when_DmaSg_l1248_3; + wire when_DmaSg_l1248_4; + wire when_DmaSg_l1248_5; + wire when_DmaSg_l1248_6; + wire when_DmaSg_l1271; + wire [0:0] ll_writeRsp_context_channel; + wire [1:0] _zz_ll_writeRsp_oh_0; + wire ll_writeRsp_oh_0; + wire ll_writeRsp_oh_1; + wire io_sgWrite_rsp_fire; + reg when_BusSlaveFactory_l377; + wire when_BusSlaveFactory_l379; + reg when_BusSlaveFactory_l377_1; + wire when_BusSlaveFactory_l379_1; + reg when_BusSlaveFactory_l377_2; + wire when_BusSlaveFactory_l379_2; + reg when_BusSlaveFactory_l377_3; + wire when_BusSlaveFactory_l379_3; + reg when_BusSlaveFactory_l341; + wire when_BusSlaveFactory_l347; + reg when_BusSlaveFactory_l341_1; + wire when_BusSlaveFactory_l347_1; + reg when_BusSlaveFactory_l341_2; + wire when_BusSlaveFactory_l347_2; + reg when_BusSlaveFactory_l341_3; + wire when_BusSlaveFactory_l347_3; + reg when_BusSlaveFactory_l377_4; + wire when_BusSlaveFactory_l379_4; + reg when_BusSlaveFactory_l377_5; + wire when_BusSlaveFactory_l379_5; + reg when_BusSlaveFactory_l377_6; + wire when_BusSlaveFactory_l379_6; + reg when_BusSlaveFactory_l377_7; + wire when_BusSlaveFactory_l379_7; + reg when_BusSlaveFactory_l341_4; + wire when_BusSlaveFactory_l347_4; + reg when_BusSlaveFactory_l341_5; + wire when_BusSlaveFactory_l347_5; + reg when_BusSlaveFactory_l341_6; + wire when_BusSlaveFactory_l347_6; + wire when_Apb3SlaveFactory_l81; + wire when_Apb3SlaveFactory_l81_1; + wire when_Apb3SlaveFactory_l81_2; + wire when_Apb3SlaveFactory_l81_3; + function [15:0] zz_io_sgWrite_cmd_payload_fragment_mask(input dummy); + begin + zz_io_sgWrite_cmd_payload_fragment_mask[7 : 4] = 4'b0000; + zz_io_sgWrite_cmd_payload_fragment_mask[11 : 8] = 4'b0000; + zz_io_sgWrite_cmd_payload_fragment_mask[15 : 12] = 4'b0000; + zz_io_sgWrite_cmd_payload_fragment_mask[3 : 0] = 4'b1111; + end + endfunction + wire [15:0] _zz_1; + + assign _zz_channels_0_bytesProbe_value = (channels_0_bytesProbe_value + _zz_channels_0_bytesProbe_value_1); + assign _zz_channels_0_bytesProbe_value_1 = {15'd0, channels_0_bytesProbe_incr_payload}; + assign _zz_channels_0_fifo_pop_withOverride_backupNext = (channels_0_fifo_pop_withOverride_backup + channels_0_fifo_pop_bytesIncr_value); + assign _zz_channels_0_fifo_pop_withOverride_exposed = (channels_0_fifo_pop_withOverride_exposed - channels_0_fifo_pop_bytesDecr_value); + assign _zz_channels_0_pop_b2m_selfFlush = {13'd0, channels_0_fifo_pop_bytes}; + assign _zz_channels_0_pop_b2m_request = {2'd0, channels_0_pop_b2m_bytePerBurst}; + assign _zz_channels_0_pop_b2m_request_2 = (channels_0_fifo_words >>> 1'd1); + assign _zz_channels_0_pop_b2m_request_1 = {1'd0, _zz_channels_0_pop_b2m_request_2}; + assign _zz_channels_0_pop_b2m_memPending = (channels_0_pop_b2m_memPending + _zz_channels_0_pop_b2m_memPending_1); + assign _zz_channels_0_pop_b2m_memPending_2 = channels_0_pop_b2m_memPendingInc; + assign _zz_channels_0_pop_b2m_memPending_1 = {3'd0, _zz_channels_0_pop_b2m_memPending_2}; + assign _zz_channels_0_pop_b2m_memPending_4 = channels_0_pop_b2m_memRsp; + assign _zz_channels_0_pop_b2m_memPending_3 = {3'd0, _zz_channels_0_pop_b2m_memPending_4}; + assign _zz_channels_0_fifo_push_available = (channels_0_fifo_push_available + channels_0_fifo_pop_ptrIncr_value_regNext); + assign _zz_channels_1_bytesProbe_value = (channels_1_bytesProbe_value + _zz_channels_1_bytesProbe_value_1); + assign _zz_channels_1_bytesProbe_value_1 = {15'd0, channels_1_bytesProbe_incr_payload}; + assign _zz_channels_1_fifo_pop_withoutOverride_exposed = (channels_1_fifo_pop_withoutOverride_exposed + channels_1_fifo_pop_bytesIncr_value); + assign _zz_channels_1_push_m2b_memPending = (channels_1_push_m2b_memPending + _zz_channels_1_push_m2b_memPending_1); + assign _zz_channels_1_push_m2b_memPending_2 = channels_1_push_m2b_memPendingIncr; + assign _zz_channels_1_push_m2b_memPending_1 = {3'd0, _zz_channels_1_push_m2b_memPending_2}; + assign _zz_channels_1_push_m2b_memPending_4 = channels_1_push_m2b_memPendingDecr; + assign _zz_channels_1_push_m2b_memPending_3 = {3'd0, _zz_channels_1_push_m2b_memPending_4}; + assign _zz_channels_1_push_m2b_loadRequest_1 = (channels_1_push_m2b_bytePerBurst >>> 2'd3); + assign _zz_channels_1_push_m2b_loadRequest = {2'd0, _zz_channels_1_push_m2b_loadRequest_1}; + assign _zz_when_DmaSg_l486 = {14'd0, channels_1_push_m2b_bytePerBurst}; + assign _zz_channels_1_fifo_push_available = (channels_1_fifo_push_available + channels_1_fifo_pop_ptrIncr_value_regNext); + assign _zz_s2b_0_cmd_byteCount_8 = (_zz_s2b_0_cmd_byteCount_9 + _zz_s2b_0_cmd_byteCount_11); + assign _zz_s2b_0_cmd_byteCount_15 = {s2b_0_cmd_sinkHalted_payload_mask[7],s2b_0_cmd_sinkHalted_payload_mask[6]}; + assign _zz_s2b_0_cmd_byteCount_14 = {1'd0, _zz_s2b_0_cmd_byteCount_15}; + assign _zz__zz_m2b_cmd_s0_priority_chosenOh_2 = (_zz_m2b_cmd_s0_priority_chosenOh_1 - _zz__zz_m2b_cmd_s0_priority_chosenOh_2_1); + assign _zz__zz_m2b_cmd_s0_priority_chosenOh_2_2 = _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3; + assign _zz__zz_m2b_cmd_s0_priority_chosenOh_2_1 = {1'd0, _zz__zz_m2b_cmd_s0_priority_chosenOh_2_2}; + assign _zz_m2b_cmd_s0_length = ((_zz_m2b_cmd_s0_length_1 < m2b_cmd_s0_bytesLeft) ? _zz_m2b_cmd_s0_length_2 : m2b_cmd_s0_bytesLeft); + assign _zz_m2b_cmd_s0_length_1 = {14'd0, m2b_cmd_s0_lengthHead}; + assign _zz_m2b_cmd_s0_length_2 = {14'd0, m2b_cmd_s0_lengthHead}; + assign _zz_m2b_cmd_s0_lastBurst = {14'd0, m2b_cmd_s0_length}; + assign _zz_m2b_cmd_s1_context_stop = (m2b_cmd_s1_address + _zz_m2b_cmd_s1_context_stop_1); + assign _zz_m2b_cmd_s1_context_stop_1 = {20'd0, m2b_cmd_s1_length}; + assign _zz_m2b_cmd_s1_addressNext = (m2b_cmd_s1_address + _zz_m2b_cmd_s1_addressNext_1); + assign _zz_m2b_cmd_s1_addressNext_1 = {20'd0, m2b_cmd_s1_length}; + assign _zz_m2b_cmd_s1_byteLeftNext = (m2b_cmd_s1_bytesLeft - _zz_m2b_cmd_s1_byteLeftNext_1); + assign _zz_m2b_cmd_s1_byteLeftNext_1 = {14'd0, m2b_cmd_s1_length}; + assign _zz_m2b_cmd_s1_fifoPushDecr = ({1'b0,(_zz_m2b_cmd_s1_fifoPushDecr_1 | 12'h00f)} + _zz_m2b_cmd_s1_fifoPushDecr_4); + assign _zz_m2b_cmd_s1_fifoPushDecr_1 = (_zz_m2b_cmd_s1_fifoPushDecr_2 + io_read_cmd_payload_fragment_length); + assign _zz_m2b_cmd_s1_fifoPushDecr_3 = m2b_cmd_s1_address[3 : 0]; + assign _zz_m2b_cmd_s1_fifoPushDecr_2 = {8'd0, _zz_m2b_cmd_s1_fifoPushDecr_3}; + assign _zz_m2b_cmd_s1_fifoPushDecr_5 = {1'b0,1'b1}; + assign _zz_m2b_cmd_s1_fifoPushDecr_4 = {11'd0, _zz_m2b_cmd_s1_fifoPushDecr_5}; + assign _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2 = (_zz_b2m_fsm_arbiter_logic_priority_chosenOh_1 - _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_1); + assign _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_2 = _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3; + assign _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_1 = {1'd0, _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_2}; + assign _zz_when = 1'b1; + assign _zz_b2m_fsm_bytesInBurstP1_1 = {1'b0,1'b1}; + assign _zz_b2m_fsm_bytesInBurstP1 = {11'd0, _zz_b2m_fsm_bytesInBurstP1_1}; + assign _zz_b2m_fsm_addressNext = {19'd0, b2m_fsm_bytesInBurstP1}; + assign _zz_b2m_fsm_bytesLeftNext_1 = {1'b0,b2m_fsm_bytesInBurstP1}; + assign _zz_b2m_fsm_bytesLeftNext = {13'd0, _zz_b2m_fsm_bytesLeftNext_1}; + assign _zz__zz_b2m_fsm_sel_bytesInBurst_1 = {12'd0, _zz_b2m_fsm_sel_bytesInBurst}; + assign _zz__zz_b2m_fsm_sel_bytesInBurst_1_1 = {12'd0, _zz_b2m_fsm_sel_bytesInBurst}; + assign _zz__zz_b2m_fsm_sel_bytesInBurst_2 = b2m_fsm_sel_address[11:0]; + assign _zz_b2m_fsm_sel_bytesInBurst_3 = ((_zz_b2m_fsm_sel_bytesInBurst_1 < _zz_b2m_fsm_sel_bytesInBurst_4) ? _zz_b2m_fsm_sel_bytesInBurst_1 : _zz_b2m_fsm_sel_bytesInBurst_5); + assign _zz_b2m_fsm_sel_bytesInBurst_4 = {14'd0, _zz_b2m_fsm_sel_bytesInBurst_2}; + assign _zz_b2m_fsm_sel_bytesInBurst_5 = {14'd0, _zz_b2m_fsm_sel_bytesInBurst_2}; + assign _zz_b2m_fsm_fifoCompletion = {2'd0, b2m_fsm_sel_bytesInBurst}; + assign _zz_b2m_fsm_fifoCompletion_1 = (b2m_fsm_sel_bytesInFifo - 14'h0001); + assign _zz_b2m_fsm_beatCounter = (_zz_b2m_fsm_beatCounter_1 + b2m_fsm_sel_bytesInBurst); + assign _zz_b2m_fsm_beatCounter_2 = b2m_fsm_sel_address[3 : 0]; + assign _zz_b2m_fsm_beatCounter_1 = {8'd0, _zz_b2m_fsm_beatCounter_2}; + assign _zz_b2m_fsm_sel_ptr = (b2m_fsm_sel_ptr + 11'h002); + assign _zz_b2m_fsm_cmd_maskLastTriggerComb = b2m_fsm_sel_bytesInBurst[3:0]; + assign _zz_when_1 = 1'b1; + assign _zz_when_2 = 1'b1; + assign _zz__zz_ll_arbiter_head_1 = (_zz_ll_arbiter_head & (~ _zz__zz_ll_arbiter_head_1_1)); + assign _zz__zz_ll_arbiter_head_1_1 = (_zz_ll_arbiter_head - 2'b01); + assign _zz_ll_arbiter_head_2 = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_arbiter_isJustASink = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_arbiter_doDescriptorStall = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_arbiter_onSgStream = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_cmd_ptr = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_cmd_ptrNext = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_cmd_endOfPacket = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_channels_0_channelStart = 1'b1; + assign _zz_channels_0_ctrl_kick = 1'b1; + assign _zz_channels_0_channelStart_1 = 1'b1; + assign _zz_channels_0_ll_sgStart = 1'b1; + assign _zz_channels_0_interrupts_completion_valid = 1'b0; + assign _zz_channels_0_interrupts_onChannelCompletion_valid = 1'b0; + assign _zz_channels_0_interrupts_onLinkedListUpdate_valid = 1'b0; + assign _zz_channels_0_interrupts_s2mPacket_valid = 1'b0; + assign _zz_channels_1_channelStart = 1'b1; + assign _zz_channels_1_ctrl_kick = 1'b1; + assign _zz_channels_1_channelStart_1 = 1'b1; + assign _zz_channels_1_ll_sgStart = 1'b1; + assign _zz_channels_1_interrupts_completion_valid = 1'b0; + assign _zz_channels_1_interrupts_onChannelCompletion_valid = 1'b0; + assign _zz_channels_1_interrupts_onLinkedListUpdate_valid = 1'b0; + assign _zz_io_ctrl_PRDATA = channels_0_ll_ptr; + assign _zz_io_ctrl_PRDATA_1 = channels_1_ll_ptr; + assign _zz_channels_0_fifo_push_ptrIncr_value_1 = ((when_DmaSg_l665 && (|s2b_0_cmd_sinkHalted_payload_mask)) ? 1'b1 : 1'b0); + assign _zz_channels_0_fifo_push_ptrIncr_value = {10'd0, _zz_channels_0_fifo_push_ptrIncr_value_1}; + assign _zz_channels_0_fifo_pop_bytesIncr_value_2 = (_zz_channels_0_fifo_pop_bytesIncr_value ? s2b_0_rsp_context_bytes : 4'b0000); + assign _zz_channels_0_fifo_pop_bytesIncr_value_1 = {10'd0, _zz_channels_0_fifo_pop_bytesIncr_value_2}; + assign _zz_channels_0_fifo_pop_ptrIncr_value_1 = ((b2m_fsm_cmd_doPtrIncr && 1'b1) ? 2'b10 : 2'b00); + assign _zz_channels_0_fifo_pop_ptrIncr_value = {9'd0, _zz_channels_0_fifo_pop_ptrIncr_value_1}; + assign _zz_channels_1_fifo_push_ptrIncr_value_2 = (_zz_channels_1_fifo_push_ptrIncr_value ? 2'b10 : 2'b00); + assign _zz_channels_1_fifo_push_ptrIncr_value_1 = {9'd0, _zz_channels_1_fifo_push_ptrIncr_value_2}; + assign _zz_channels_1_fifo_pop_bytesIncr_value_2 = (_zz_channels_1_fifo_pop_bytesIncr_value ? _zz_channels_1_fifo_pop_bytesIncr_value_3 : 5'h0); + assign _zz_channels_1_fifo_pop_bytesIncr_value_1 = {9'd0, _zz_channels_1_fifo_pop_bytesIncr_value_2}; + assign _zz_channels_1_fifo_pop_bytesIncr_value_3 = (m2b_writeRsp_context_loadByteInNextBeat + 5'h01); + assign _zz_channels_1_fifo_pop_ptrIncr_value_1 = ((b2s_0_cmd_channelsOh[0] && memory_core_io_reads_0_cmd_ready) ? 1'b1 : 1'b0); + assign _zz_channels_1_fifo_pop_ptrIncr_value = {10'd0, _zz_channels_1_fifo_pop_ptrIncr_value_1}; + assign _zz_s2b_0_cmd_byteCount_10 = {s2b_0_cmd_sinkHalted_payload_mask[2],{s2b_0_cmd_sinkHalted_payload_mask[1],s2b_0_cmd_sinkHalted_payload_mask[0]}}; + assign _zz_s2b_0_cmd_byteCount_12 = {s2b_0_cmd_sinkHalted_payload_mask[5],{s2b_0_cmd_sinkHalted_payload_mask[4],s2b_0_cmd_sinkHalted_payload_mask[3]}}; + assign _zz_s2b_0_cmd_firsts = io_inputs_0_payload_last_regNextWhen_5; + assign _zz_s2b_0_cmd_firsts_1 = {io_inputs_0_payload_last_regNextWhen_4,{io_inputs_0_payload_last_regNextWhen_3,{io_inputs_0_payload_last_regNextWhen_2,{io_inputs_0_payload_last_regNextWhen_1,io_inputs_0_payload_last_regNextWhen}}}}; + assign _zz_b2m_fsm_aggregate_bytesToSkipMask = 4'b1101; + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_1 = (! b2m_fsm_aggregate_first); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_2 = (b2m_fsm_aggregate_bytesToSkip <= 4'b1100); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_3 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1011)); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_4 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1010)); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_5 = {((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1001)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1000)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= _zz_b2m_fsm_aggregate_bytesToSkipMask_6)),{(_zz_b2m_fsm_aggregate_bytesToSkipMask_7 || _zz_b2m_fsm_aggregate_bytesToSkipMask_8),{_zz_b2m_fsm_aggregate_bytesToSkipMask_9,{_zz_b2m_fsm_aggregate_bytesToSkipMask_10,_zz_b2m_fsm_aggregate_bytesToSkipMask_11}}}}}}; + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_6 = 4'b0111; + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_7 = (! b2m_fsm_aggregate_first); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_8 = (b2m_fsm_aggregate_bytesToSkip <= 4'b0110); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_9 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0101)); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_10 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0100)); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_11 = {((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0011)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0010)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0001)),((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0000))}}}; + assign _zz_b2m_fsm_cmd_maskLast = 4'b1010; + assign _zz_b2m_fsm_cmd_maskLast_1 = (4'b1001 <= b2m_fsm_cmd_maskLastTriggerComb); + assign _zz_b2m_fsm_cmd_maskLast_2 = (4'b1000 <= b2m_fsm_cmd_maskLastTriggerComb); + assign _zz_b2m_fsm_cmd_maskLast_3 = {(4'b0111 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0110 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0101 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0100 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0011 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0010 <= b2m_fsm_cmd_maskLastTriggerComb),{(_zz_b2m_fsm_cmd_maskLast_4 <= b2m_fsm_cmd_maskLastTriggerComb),(_zz_b2m_fsm_cmd_maskLast_5 <= b2m_fsm_cmd_maskLastTriggerComb)}}}}}}}; + assign _zz_b2m_fsm_cmd_maskLast_4 = 4'b0001; + assign _zz_b2m_fsm_cmd_maskLast_5 = 4'b0000; + assign _zz_b2m_fsm_cmd_maskFirst = 4'b1010; + assign _zz_b2m_fsm_cmd_maskFirst_1 = (b2m_fsm_cmd_maskFirstTrigger <= 4'b1001); + assign _zz_b2m_fsm_cmd_maskFirst_2 = (b2m_fsm_cmd_maskFirstTrigger <= 4'b1000); + assign _zz_b2m_fsm_cmd_maskFirst_3 = {(b2m_fsm_cmd_maskFirstTrigger <= 4'b0111),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0110),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0101),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0100),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0011),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0010),{(b2m_fsm_cmd_maskFirstTrigger <= _zz_b2m_fsm_cmd_maskFirst_4),(b2m_fsm_cmd_maskFirstTrigger <= _zz_b2m_fsm_cmd_maskFirst_5)}}}}}}}; + assign _zz_b2m_fsm_cmd_maskFirst_4 = 4'b0001; + assign _zz_b2m_fsm_cmd_maskFirst_5 = 4'b0000; + EfxDMA_DmaMemoryCore memory_core ( + .io_writes_0_cmd_valid (s2b_0_cmd_sinkHalted_valid ), //i + .io_writes_0_cmd_ready (memory_core_io_writes_0_cmd_ready ), //o + .io_writes_0_cmd_payload_address (memory_core_io_writes_0_cmd_payload_address[9:0]), //i + .io_writes_0_cmd_payload_data (s2b_0_cmd_sinkHalted_payload_data[63:0] ), //i + .io_writes_0_cmd_payload_mask (s2b_0_cmd_sinkHalted_payload_mask[7:0] ), //i + .io_writes_0_cmd_payload_priority (channels_0_priority[1:0] ), //i + .io_writes_0_cmd_payload_context (memory_core_io_writes_0_cmd_payload_context[6:0]), //i + .io_writes_0_rsp_valid (memory_core_io_writes_0_rsp_valid ), //o + .io_writes_0_rsp_payload_context (memory_core_io_writes_0_rsp_payload_context[6:0]), //o + .io_writes_1_cmd_valid (io_read_rsp_valid ), //i + .io_writes_1_cmd_ready (memory_core_io_writes_1_cmd_ready ), //o + .io_writes_1_cmd_payload_address (memory_core_io_writes_1_cmd_payload_address[9:0]), //i + .io_writes_1_cmd_payload_data (io_read_rsp_payload_fragment_data[127:0] ), //i + .io_writes_1_cmd_payload_mask (memory_core_io_writes_1_cmd_payload_mask[15:0] ), //i + .io_writes_1_cmd_payload_context (memory_core_io_writes_1_cmd_payload_context[6:0]), //i + .io_writes_1_rsp_valid (memory_core_io_writes_1_rsp_valid ), //o + .io_writes_1_rsp_payload_context (memory_core_io_writes_1_rsp_payload_context[6:0]), //o + .io_reads_0_cmd_valid (memory_core_io_reads_0_cmd_valid ), //i + .io_reads_0_cmd_ready (memory_core_io_reads_0_cmd_ready ), //o + .io_reads_0_cmd_payload_address (memory_core_io_reads_0_cmd_payload_address[9:0] ), //i + .io_reads_0_cmd_payload_priority (channels_1_priority[1:0] ), //i + .io_reads_0_cmd_payload_context (memory_core_io_reads_0_cmd_payload_context[2:0] ), //i + .io_reads_0_rsp_valid (memory_core_io_reads_0_rsp_valid ), //o + .io_reads_0_rsp_ready (io_outputs_0_ready ), //i + .io_reads_0_rsp_payload_data (memory_core_io_reads_0_rsp_payload_data[63:0] ), //o + .io_reads_0_rsp_payload_mask (memory_core_io_reads_0_rsp_payload_mask[7:0] ), //o + .io_reads_0_rsp_payload_context (memory_core_io_reads_0_rsp_payload_context[2:0] ), //o + .io_reads_1_cmd_valid (b2m_fsm_sel_valid ), //i + .io_reads_1_cmd_ready (memory_core_io_reads_1_cmd_ready ), //o + .io_reads_1_cmd_payload_address (memory_core_io_reads_1_cmd_payload_address[9:0] ), //i + .io_reads_1_cmd_payload_context (memory_core_io_reads_1_cmd_payload_context[11:0]), //i + .io_reads_1_rsp_valid (memory_core_io_reads_1_rsp_valid ), //o + .io_reads_1_rsp_ready (memory_core_io_reads_1_rsp_rValidN ), //i + .io_reads_1_rsp_payload_data (memory_core_io_reads_1_rsp_payload_data[127:0] ), //o + .io_reads_1_rsp_payload_mask (memory_core_io_reads_1_rsp_payload_mask[15:0] ), //o + .io_reads_1_rsp_payload_context (memory_core_io_reads_1_rsp_payload_context[11:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_Aggregator b2m_fsm_aggregate_engine ( + .io_input_valid (b2m_fsm_aggregate_memoryPort_valid ), //i + .io_input_ready (b2m_fsm_aggregate_engine_io_input_ready ), //o + .io_input_payload_data (b2m_fsm_aggregate_memoryPort_payload_data[127:0] ), //i + .io_input_payload_mask (b2m_fsm_aggregate_engine_io_input_payload_mask[15:0]), //i + .io_output_data (b2m_fsm_aggregate_engine_io_output_data[127:0] ), //o + .io_output_mask (b2m_fsm_aggregate_engine_io_output_mask[15:0] ), //o + .io_output_enough (b2m_fsm_cmd_enoughAggregation ), //i + .io_output_consume (io_write_cmd_fire ), //i + .io_output_consumed (b2m_fsm_aggregate_engine_io_output_consumed ), //o + .io_output_lastByteUsed (b2m_fsm_cmd_maskLastTriggerReg[3:0] ), //i + .io_output_usedUntil (b2m_fsm_aggregate_engine_io_output_usedUntil[3:0] ), //o + .io_flush (b2m_fsm_aggregate_engine_io_flush ), //i + .io_offset (b2m_fsm_aggregate_engine_io_offset[3:0] ), //i + .io_burstLength (b2m_fsm_sel_bytesInBurst[11:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_s2b_0_cmd_byteCount_10) + 3'b000 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount; + 3'b001 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_1; + 3'b010 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_2; + 3'b011 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_3; + 3'b100 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_4; + 3'b101 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_5; + 3'b110 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_6; + default : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_7; + endcase + end + + always @(*) begin + case(_zz_s2b_0_cmd_byteCount_12) + 3'b000 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount; + 3'b001 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_1; + 3'b010 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_2; + 3'b011 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_3; + 3'b100 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_4; + 3'b101 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_5; + 3'b110 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_6; + default : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_7; + endcase + end + + always @(*) begin + case(_zz_s2b_0_cmd_byteCount_14) + 3'b000 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount; + 3'b001 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_1; + 3'b010 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_2; + 3'b011 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_3; + 3'b100 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_4; + 3'b101 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_5; + 3'b110 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_6; + default : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_7; + endcase + end + + always @(*) begin + case(_zz_m2b_cmd_s0_priority_masked) + 2'b00 : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_0; + 2'b01 : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_1; + 2'b10 : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_2; + default : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_3; + endcase + end + + always @(*) begin + case(_zz_b2m_fsm_arbiter_logic_priority_masked) + 2'b00 : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_0; + 2'b01 : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_1; + 2'b10 : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_2; + default : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_3; + endcase + end + + assign ctrl_readErrorFlag = 1'b0; + assign ctrl_writeErrorFlag = 1'b0; + assign io_ctrl_PREADY = 1'b1; + always @(*) begin + io_ctrl_PRDATA = 32'h0; + case(io_ctrl_PADDR) + 14'h002c : begin + io_ctrl_PRDATA[0 : 0] = channels_0_channelValid; + end + 14'h0054 : begin + io_ctrl_PRDATA[0 : 0] = channels_0_interrupts_completion_valid; + io_ctrl_PRDATA[2 : 2] = channels_0_interrupts_onChannelCompletion_valid; + io_ctrl_PRDATA[3 : 3] = channels_0_interrupts_onLinkedListUpdate_valid; + io_ctrl_PRDATA[4 : 4] = channels_0_interrupts_s2mPacket_valid; + end + 14'h0060 : begin + io_ctrl_PRDATA[26 : 0] = channels_0_bytesProbe_value; + end + 14'h00ac : begin + io_ctrl_PRDATA[0 : 0] = channels_1_channelValid; + end + 14'h00d4 : begin + io_ctrl_PRDATA[0 : 0] = channels_1_interrupts_completion_valid; + io_ctrl_PRDATA[2 : 2] = channels_1_interrupts_onChannelCompletion_valid; + io_ctrl_PRDATA[3 : 3] = channels_1_interrupts_onLinkedListUpdate_valid; + end + 14'h00e0 : begin + io_ctrl_PRDATA[26 : 0] = channels_1_bytesProbe_value; + end + default : begin + end + endcase + if(when_Apb3SlaveFactory_l81_1) begin + io_ctrl_PRDATA[31 : 0] = _zz_io_ctrl_PRDATA[31 : 0]; + end + if(when_Apb3SlaveFactory_l81_3) begin + io_ctrl_PRDATA[31 : 0] = _zz_io_ctrl_PRDATA_1[31 : 0]; + end + end + + assign ctrl_askWrite = ((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && io_ctrl_PWRITE); + assign ctrl_askRead = ((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && (! io_ctrl_PWRITE)); + assign ctrl_doWrite = (((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && io_ctrl_PREADY) && io_ctrl_PWRITE); + assign ctrl_doRead = (((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && io_ctrl_PREADY) && (! io_ctrl_PWRITE)); + assign io_ctrl_PSLVERROR = ((ctrl_doWrite && ctrl_writeErrorFlag) || (ctrl_doRead && ctrl_readErrorFlag)); + always @(*) begin + channels_0_channelStart = 1'b0; + if(when_BusSlaveFactory_l377) begin + if(when_BusSlaveFactory_l379) begin + channels_0_channelStart = _zz_channels_0_channelStart[0]; + end + end + if(when_BusSlaveFactory_l377_2) begin + if(when_BusSlaveFactory_l379_2) begin + channels_0_channelStart = _zz_channels_0_channelStart_1[0]; + end + end + end + + always @(*) begin + channels_0_channelCompletion = 1'b0; + if(channels_0_channelValid) begin + if(channels_0_channelStop) begin + if(channels_0_readyToStop) begin + channels_0_channelCompletion = 1'b1; + end + end + end + end + + always @(*) begin + channels_0_descriptorStart = 1'b0; + if(channels_0_ctrl_kick) begin + channels_0_descriptorStart = 1'b1; + end + if(when_DmaSg_l318) begin + if(when_DmaSg_l320) begin + if(when_DmaSg_l322) begin + channels_0_descriptorStart = 1'b1; + end + end + end + end + + always @(*) begin + channels_0_descriptorCompletion = 1'b0; + if(channels_0_pop_b2m_packetSync) begin + if(when_DmaSg_l532) begin + if(channels_0_push_s2b_completionOnLast) begin + channels_0_descriptorCompletion = 1'b1; + end + end + end + if(when_DmaSg_l547) begin + channels_0_descriptorCompletion = 1'b1; + end + if(channels_0_channelValid) begin + if(channels_0_channelStop) begin + if(channels_0_readyToStop) begin + channels_0_descriptorCompletion = 1'b1; + end + end + end + end + + always @(*) begin + channels_0_readyToStop = 1'b1; + if(channels_0_ll_waitDone) begin + channels_0_readyToStop = 1'b0; + end + if(when_DmaSg_l563) begin + channels_0_readyToStop = 1'b0; + end + end + + always @(*) begin + channels_0_bytesProbe_incr_valid = 1'b0; + if(io_write_rsp_fire) begin + if(when_DmaSg_l1116) begin + channels_0_bytesProbe_incr_valid = 1'b1; + end + end + end + + always @(*) begin + channels_0_bytesProbe_incr_payload = 12'bxxxxxxxxxxxx; + if(io_write_rsp_fire) begin + if(when_DmaSg_l1116) begin + channels_0_bytesProbe_incr_payload = b2m_rsp_context_length; + end + end + end + + always @(*) begin + channels_0_ll_sgStart = 1'b0; + if(when_BusSlaveFactory_l377_3) begin + if(when_BusSlaveFactory_l379_3) begin + channels_0_ll_sgStart = _zz_channels_0_ll_sgStart[0]; + end + end + end + + assign channels_0_ll_requestLl = ((((channels_0_channelValid && channels_0_ll_valid) && (! channels_0_channelStop)) && (! channels_0_ll_waitDone)) && ((! channels_0_descriptorValid) || channels_0_ll_requireSync)); + always @(*) begin + channels_0_ll_descriptorUpdated = 1'b0; + if(when_DmaSg_l318) begin + if(when_DmaSg_l328) begin + channels_0_ll_descriptorUpdated = 1'b1; + end + end + end + + assign when_DmaSg_l318 = (((channels_0_ll_valid && channels_0_ll_waitDone) && channels_0_ll_writeDone) && channels_0_ll_readDone); + assign when_DmaSg_l320 = (! channels_0_ll_justASync); + assign when_DmaSg_l322 = (! channels_0_ll_gotDescriptorStall); + assign when_DmaSg_l328 = (! channels_0_ll_head); + assign channels_0_fifo_base = 11'h0; + assign channels_0_fifo_words = 11'h1ff; + assign channels_0_fifo_push_availableDecr = 11'h0; + assign channels_0_fifo_push_ptrWithBase = ((channels_0_fifo_base & (~ channels_0_fifo_words)) | (channels_0_fifo_push_ptr & channels_0_fifo_words)); + assign channels_0_fifo_pop_ptrWithBase = ((channels_0_fifo_base & (~ channels_0_fifo_words)) | (channels_0_fifo_pop_ptr & channels_0_fifo_words)); + assign channels_0_fifo_pop_empty = (channels_0_fifo_pop_ptr == channels_0_fifo_push_ptr); + assign channels_0_fifo_pop_withOverride_backupNext = (_zz_channels_0_fifo_pop_withOverride_backupNext - channels_0_fifo_pop_bytesDecr_value); + always @(*) begin + channels_0_fifo_pop_withOverride_load = 1'b0; + if(when_DmaSg_l457) begin + channels_0_fifo_pop_withOverride_load = 1'b1; + end + end + + always @(*) begin + channels_0_fifo_pop_withOverride_unload = 1'b0; + if(channels_0_pop_b2m_packetSync) begin + channels_0_fifo_pop_withOverride_unload = 1'b1; + end + end + + assign when_DmaSg_l409 = (channels_0_channelStart || channels_0_fifo_pop_withOverride_unload); + assign channels_0_fifo_pop_bytes = channels_0_fifo_pop_withOverride_exposed; + assign channels_0_fifo_empty = (channels_0_fifo_push_ptr == channels_0_fifo_pop_ptr); + always @(*) begin + channels_0_push_s2b_packetEvent = 1'b0; + if(when_DmaSg_l679) begin + channels_0_push_s2b_packetEvent = 1'b1; + end + end + + assign when_DmaSg_l457 = (channels_0_push_s2b_packetEvent && channels_0_push_s2b_completionOnLast); + assign channels_0_pop_b2m_bytePerBurst = 12'h3ff; + always @(*) begin + channels_0_pop_b2m_fire = 1'b0; + if(when_DmaSg_l935) begin + if(_zz_when[0]) begin + channels_0_pop_b2m_fire = 1'b1; + end + end + end + + always @(*) begin + channels_0_pop_b2m_packetSync = 1'b0; + if(when_DmaSg_l523) begin + if(channels_0_pop_b2m_packet) begin + channels_0_pop_b2m_packetSync = 1'b1; + end + end + if(io_write_rsp_fire) begin + if(when_DmaSg_l1116) begin + if(b2m_rsp_context_doPacketSync) begin + channels_0_pop_b2m_packetSync = 1'b1; + end + end + end + end + + assign when_DmaSg_l505 = (channels_0_channelStart || channels_0_pop_b2m_fire); + always @(*) begin + channels_0_pop_b2m_memRsp = 1'b0; + if(io_write_rsp_fire) begin + if(_zz_when_2[0]) begin + channels_0_pop_b2m_memRsp = 1'b1; + end + end + end + + assign channels_0_pop_b2m_selfFlush = (channels_0_pop_b2m_bytesLeft < _zz_channels_0_pop_b2m_selfFlush); + assign channels_0_pop_b2m_request = ((((((channels_0_descriptorValid && (! channels_0_channelStop)) && (! channels_0_pop_b2m_waitFinalRsp)) && channels_0_pop_memory) && ((_zz_channels_0_pop_b2m_request < channels_0_fifo_pop_bytes) || (((channels_0_fifo_push_available < _zz_channels_0_pop_b2m_request_1) || channels_0_pop_b2m_flush) || channels_0_pop_b2m_selfFlush))) && (channels_0_fifo_pop_bytes != 14'h0)) && (channels_0_pop_b2m_memPending != 4'b1111)); + always @(*) begin + channels_0_pop_b2m_memPendingInc = 1'b0; + if(when_DmaSg_l758_1) begin + if(when_DmaSg_l773_1) begin + channels_0_pop_b2m_memPendingInc = 1'b1; + end + end + end + + always @(*) begin + channels_0_pop_b2m_decrBytes = 14'h0; + if(b2m_fsm_s1) begin + if(when_DmaSg_l996) begin + channels_0_pop_b2m_decrBytes = {1'd0, b2m_fsm_bytesInBurstP1}; + end + end + end + + assign when_DmaSg_l523 = ((channels_0_pop_b2m_memPending == 4'b0000) && (channels_0_fifo_pop_bytes == 14'h0)); + assign when_DmaSg_l532 = (channels_0_descriptorValid && (! channels_0_push_memory)); + assign when_DmaSg_l536 = (! channels_0_pop_b2m_waitFinalRsp); + assign when_DmaSg_l547 = ((channels_0_descriptorValid && (channels_0_pop_b2m_memPending == 4'b0000)) && channels_0_pop_b2m_waitFinalRsp); + assign when_DmaSg_l563 = (channels_0_pop_b2m_memPending != 4'b0000); + assign channels_0_readyForChannelCompletion = 1'b1; + assign when_DmaSg_l575 = (! channels_0_descriptorValid); + always @(*) begin + _zz_when_DmaSg_l593 = 1'b1; + if(channels_0_ctrl_kick) begin + _zz_when_DmaSg_l593 = 1'b0; + end + if(channels_0_ll_valid) begin + _zz_when_DmaSg_l593 = 1'b0; + end + end + + assign when_DmaSg_l593 = (_zz_when_DmaSg_l593 && channels_0_readyForChannelCompletion); + assign channels_0_s2b_full = (channels_0_fifo_push_available < 11'h002); + assign when_DmaSg_l255 = (channels_0_descriptorValid && channels_0_descriptorCompletion); + assign when_DmaSg_l255_1 = (! channels_0_interrupts_completion_enable); + assign when_DmaSg_l255_2 = (channels_0_channelValid && channels_0_channelCompletion); + assign when_DmaSg_l255_3 = (! channels_0_interrupts_onChannelCompletion_enable); + assign when_DmaSg_l255_4 = (! channels_0_interrupts_onLinkedListUpdate_enable); + assign when_DmaSg_l255_5 = (! channels_0_interrupts_s2mPacket_enable); + assign when_DmaSg_l625 = (channels_0_channelStart || channels_0_descriptorStart); + always @(*) begin + channels_1_channelStart = 1'b0; + if(when_BusSlaveFactory_l377_4) begin + if(when_BusSlaveFactory_l379_4) begin + channels_1_channelStart = _zz_channels_1_channelStart[0]; + end + end + if(when_BusSlaveFactory_l377_6) begin + if(when_BusSlaveFactory_l379_6) begin + channels_1_channelStart = _zz_channels_1_channelStart_1[0]; + end + end + end + + always @(*) begin + channels_1_channelCompletion = 1'b0; + if(channels_1_channelValid) begin + if(channels_1_channelStop) begin + if(channels_1_readyToStop) begin + channels_1_channelCompletion = 1'b1; + end + end + end + end + + always @(*) begin + channels_1_descriptorStart = 1'b0; + if(channels_1_ctrl_kick) begin + channels_1_descriptorStart = 1'b1; + end + if(when_DmaSg_l318_1) begin + if(when_DmaSg_l320_1) begin + if(when_DmaSg_l322_1) begin + channels_1_descriptorStart = 1'b1; + end + end + end + end + + always @(*) begin + channels_1_descriptorCompletion = 1'b0; + if(when_DmaSg_l483) begin + channels_1_descriptorCompletion = 1'b1; + end + if(channels_1_channelValid) begin + if(channels_1_channelStop) begin + if(channels_1_readyToStop) begin + channels_1_descriptorCompletion = 1'b1; + end + end + end + end + + always @(*) begin + channels_1_readyToStop = 1'b1; + if(channels_1_ll_waitDone) begin + channels_1_readyToStop = 1'b0; + end + if(when_DmaSg_l562) begin + channels_1_readyToStop = 1'b0; + end + end + + always @(*) begin + channels_1_bytesProbe_incr_valid = 1'b0; + if(when_DmaSg_l874) begin + channels_1_bytesProbe_incr_valid = 1'b1; + end + end + + always @(*) begin + channels_1_bytesProbe_incr_payload = 12'bxxxxxxxxxxxx; + if(when_DmaSg_l874) begin + channels_1_bytesProbe_incr_payload = m2b_rsp_context_length; + end + end + + always @(*) begin + channels_1_ll_sgStart = 1'b0; + if(when_BusSlaveFactory_l377_7) begin + if(when_BusSlaveFactory_l379_7) begin + channels_1_ll_sgStart = _zz_channels_1_ll_sgStart[0]; + end + end + end + + assign channels_1_ll_requestLl = ((((channels_1_channelValid && channels_1_ll_valid) && (! channels_1_channelStop)) && (! channels_1_ll_waitDone)) && ((! channels_1_descriptorValid) || channels_1_ll_requireSync)); + always @(*) begin + channels_1_ll_descriptorUpdated = 1'b0; + if(when_DmaSg_l318_1) begin + if(when_DmaSg_l328_1) begin + channels_1_ll_descriptorUpdated = 1'b1; + end + end + end + + assign when_DmaSg_l318_1 = (((channels_1_ll_valid && channels_1_ll_waitDone) && channels_1_ll_writeDone) && channels_1_ll_readDone); + assign when_DmaSg_l320_1 = (! channels_1_ll_justASync); + assign when_DmaSg_l322_1 = (! channels_1_ll_gotDescriptorStall); + assign when_DmaSg_l328_1 = (! channels_1_ll_head); + assign channels_1_fifo_base = 11'h200; + assign channels_1_fifo_words = 11'h1ff; + always @(*) begin + channels_1_fifo_push_availableDecr = 11'h0; + if(m2b_cmd_s1_valid) begin + if(io_read_cmd_ready) begin + if(when_DmaSg_l828) begin + channels_1_fifo_push_availableDecr = {1'd0, m2b_cmd_s1_fifoPushDecr}; + end + end + end + end + + assign channels_1_fifo_push_ptrWithBase = ((channels_1_fifo_base & (~ channels_1_fifo_words)) | (channels_1_fifo_push_ptr & channels_1_fifo_words)); + assign channels_1_fifo_pop_ptrWithBase = ((channels_1_fifo_base & (~ channels_1_fifo_words)) | (channels_1_fifo_pop_ptr & channels_1_fifo_words)); + assign channels_1_fifo_pop_empty = (channels_1_fifo_pop_ptr == channels_1_fifo_push_ptr); + assign channels_1_fifo_pop_bytes = channels_1_fifo_pop_withoutOverride_exposed; + assign channels_1_fifo_empty = (channels_1_fifo_push_ptr == channels_1_fifo_pop_ptr); + assign channels_1_push_m2b_bytePerBurst = 12'h3ff; + always @(*) begin + channels_1_push_m2b_memPendingIncr = 1'b0; + if(when_DmaSg_l758) begin + if(when_DmaSg_l773) begin + channels_1_push_m2b_memPendingIncr = 1'b1; + end + end + end + + always @(*) begin + channels_1_push_m2b_memPendingDecr = 1'b0; + if(when_DmaSg_l893) begin + channels_1_push_m2b_memPendingDecr = 1'b1; + end + end + + always @(*) begin + channels_1_push_m2b_loadRequest = (((((channels_1_descriptorValid && (! channels_1_channelStop)) && (! channels_1_push_m2b_loadDone)) && channels_1_push_memory) && (_zz_channels_1_push_m2b_loadRequest < channels_1_fifo_push_available)) && (channels_1_push_m2b_memPending != 4'b1111)); + if(when_DmaSg_l486) begin + channels_1_push_m2b_loadRequest = 1'b0; + end + end + + always @(*) begin + channels_1_pop_b2s_veryLastTrigger = 1'b0; + if(when_DmaSg_l847) begin + if(when_DmaSg_l848) begin + channels_1_pop_b2s_veryLastTrigger = 1'b1; + end + end + end + + assign when_DmaSg_l474 = (channels_1_pop_b2s_veryLastTrigger && channels_1_pop_b2s_last); + assign when_DmaSg_l483 = ((((channels_1_descriptorValid && (! channels_1_pop_memory)) && channels_1_push_memory) && channels_1_push_m2b_loadDone) && (channels_1_push_m2b_memPending == 4'b0000)); + assign when_DmaSg_l486 = (((! channels_1_pop_memory) && channels_1_pop_b2s_veryLastValid) && (channels_1_push_m2b_bytesLeft <= _zz_when_DmaSg_l486)); + assign when_DmaSg_l562 = (channels_1_push_m2b_memPending != 4'b0000); + always @(*) begin + channels_1_readyForChannelCompletion = 1'b1; + if(when_DmaSg_l566) begin + channels_1_readyForChannelCompletion = 1'b0; + end + end + + assign when_DmaSg_l566 = ((! channels_1_pop_memory) && (! channels_1_fifo_pop_empty)); + assign when_DmaSg_l575_1 = (! channels_1_descriptorValid); + always @(*) begin + _zz_when_DmaSg_l593_1 = 1'b1; + if(channels_1_ctrl_kick) begin + _zz_when_DmaSg_l593_1 = 1'b0; + end + if(channels_1_ll_valid) begin + _zz_when_DmaSg_l593_1 = 1'b0; + end + end + + assign when_DmaSg_l593_1 = (_zz_when_DmaSg_l593_1 && channels_1_readyForChannelCompletion); + assign channels_1_s2b_full = (channels_1_fifo_push_available < 11'h002); + assign when_DmaSg_l255_6 = (channels_1_descriptorValid && channels_1_descriptorCompletion); + assign when_DmaSg_l255_7 = (! channels_1_interrupts_completion_enable); + assign when_DmaSg_l255_8 = (channels_1_channelValid && channels_1_channelCompletion); + assign when_DmaSg_l255_9 = (! channels_1_interrupts_onChannelCompletion_enable); + assign when_DmaSg_l255_10 = (! channels_1_interrupts_onLinkedListUpdate_enable); + assign when_DmaSg_l625_1 = (channels_1_channelStart || channels_1_descriptorStart); + assign io_inputs_0_fire = (io_inputs_0_valid && io_inputs_0_ready); + assign when_package_l12 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0000)); + assign when_package_l12_1 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0001)); + assign when_package_l12_2 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0010)); + assign when_package_l12_3 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0011)); + assign when_package_l12_4 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0100)); + assign when_package_l12_5 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0101)); + assign when_package_l12_6 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0110)); + assign when_package_l12_7 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0111)); + assign when_package_l12_8 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1000)); + assign when_package_l12_9 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1001)); + assign when_package_l12_10 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1010)); + assign when_package_l12_11 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1011)); + assign when_package_l12_12 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1100)); + assign when_package_l12_13 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1101)); + assign when_package_l12_14 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1110)); + assign when_package_l12_15 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1111)); + assign s2b_0_cmd_firsts = {io_inputs_0_payload_last_regNextWhen_15,{io_inputs_0_payload_last_regNextWhen_14,{io_inputs_0_payload_last_regNextWhen_13,{io_inputs_0_payload_last_regNextWhen_12,{io_inputs_0_payload_last_regNextWhen_11,{io_inputs_0_payload_last_regNextWhen_10,{io_inputs_0_payload_last_regNextWhen_9,{io_inputs_0_payload_last_regNextWhen_8,{io_inputs_0_payload_last_regNextWhen_7,{io_inputs_0_payload_last_regNextWhen_6,{_zz_s2b_0_cmd_firsts,_zz_s2b_0_cmd_firsts_1}}}}}}}}}}}; + assign s2b_0_cmd_first = s2b_0_cmd_firsts[io_inputs_0_payload_sink]; + assign s2b_0_cmd_channelsOh = ((((channels_0_channelValid && (s2b_0_cmd_first || (! channels_0_push_s2b_waitFirst))) && (! channels_0_push_memory)) && 1'b1) && (io_inputs_0_payload_sink == 4'b0000)); + assign s2b_0_cmd_noHit = (! (|s2b_0_cmd_channelsOh)); + assign s2b_0_cmd_channelsFull = (channels_0_s2b_full || (channels_0_push_s2b_packetLock && io_inputs_0_payload_last)); + always @(*) begin + io_inputs_0_thrown_valid = io_inputs_0_valid; + if(s2b_0_cmd_noHit) begin + io_inputs_0_thrown_valid = 1'b0; + end + end + + always @(*) begin + io_inputs_0_ready = io_inputs_0_thrown_ready; + if(s2b_0_cmd_noHit) begin + io_inputs_0_ready = 1'b1; + end + end + + assign io_inputs_0_thrown_payload_data = io_inputs_0_payload_data; + assign io_inputs_0_thrown_payload_mask = io_inputs_0_payload_mask; + assign io_inputs_0_thrown_payload_sink = io_inputs_0_payload_sink; + assign io_inputs_0_thrown_payload_last = io_inputs_0_payload_last; + assign _zz_io_inputs_0_thrown_ready = (! (|(s2b_0_cmd_channelsOh & s2b_0_cmd_channelsFull))); + assign s2b_0_cmd_sinkHalted_valid = (io_inputs_0_thrown_valid && _zz_io_inputs_0_thrown_ready); + assign io_inputs_0_thrown_ready = (s2b_0_cmd_sinkHalted_ready && _zz_io_inputs_0_thrown_ready); + assign s2b_0_cmd_sinkHalted_payload_data = io_inputs_0_thrown_payload_data; + assign s2b_0_cmd_sinkHalted_payload_mask = io_inputs_0_thrown_payload_mask; + assign s2b_0_cmd_sinkHalted_payload_sink = io_inputs_0_thrown_payload_sink; + assign s2b_0_cmd_sinkHalted_payload_last = io_inputs_0_thrown_payload_last; + assign _zz_s2b_0_cmd_byteCount = 4'b0000; + assign _zz_s2b_0_cmd_byteCount_1 = 4'b0001; + assign _zz_s2b_0_cmd_byteCount_2 = 4'b0001; + assign _zz_s2b_0_cmd_byteCount_3 = 4'b0010; + assign _zz_s2b_0_cmd_byteCount_4 = 4'b0001; + assign _zz_s2b_0_cmd_byteCount_5 = 4'b0010; + assign _zz_s2b_0_cmd_byteCount_6 = 4'b0010; + assign _zz_s2b_0_cmd_byteCount_7 = 4'b0011; + assign s2b_0_cmd_byteCount = (_zz_s2b_0_cmd_byteCount_8 + _zz_s2b_0_cmd_byteCount_13); + assign s2b_0_cmd_context_channel = s2b_0_cmd_channelsOh; + assign s2b_0_cmd_context_bytes = s2b_0_cmd_byteCount; + assign s2b_0_cmd_context_flush = io_inputs_0_payload_last; + assign s2b_0_cmd_context_packet = io_inputs_0_payload_last; + assign s2b_0_cmd_sinkHalted_ready = memory_core_io_writes_0_cmd_ready; + assign memory_core_io_writes_0_cmd_payload_address = channels_0_fifo_push_ptrWithBase[9:0]; + assign memory_core_io_writes_0_cmd_payload_context = {s2b_0_cmd_context_packet,{s2b_0_cmd_context_flush,{s2b_0_cmd_context_bytes,s2b_0_cmd_context_channel}}}; + assign memory_core_io_writes_0_cmd_fire = (s2b_0_cmd_sinkHalted_valid && memory_core_io_writes_0_cmd_ready); + assign when_DmaSg_l665 = (s2b_0_cmd_channelsOh[0] && memory_core_io_writes_0_cmd_fire); + assign _zz_s2b_0_rsp_context_channel = memory_core_io_writes_0_rsp_payload_context; + assign s2b_0_rsp_context_channel = _zz_s2b_0_rsp_context_channel[0 : 0]; + assign s2b_0_rsp_context_bytes = _zz_s2b_0_rsp_context_channel[4 : 1]; + assign s2b_0_rsp_context_flush = _zz_s2b_0_rsp_context_channel[5]; + assign s2b_0_rsp_context_packet = _zz_s2b_0_rsp_context_channel[6]; + assign _zz_channels_0_fifo_pop_bytesIncr_value = (memory_core_io_writes_0_rsp_valid && s2b_0_rsp_context_channel[0]); + assign when_DmaSg_l679 = (_zz_channels_0_fifo_pop_bytesIncr_value && s2b_0_rsp_context_packet); + assign when_DmaSg_l681 = (_zz_channels_0_fifo_pop_bytesIncr_value && s2b_0_rsp_context_flush); + assign when_DmaSg_l682 = (_zz_channels_0_fifo_pop_bytesIncr_value && s2b_0_rsp_context_packet); + assign b2s_0_cmd_channelsOh = (((channels_1_channelValid && (! channels_1_pop_memory)) && 1'b1) && (! channels_1_fifo_pop_empty)); + assign b2s_0_cmd_veryLastPtr = channels_1_pop_b2s_veryLastPtr; + assign b2s_0_cmd_address = channels_1_fifo_pop_ptrWithBase; + assign b2s_0_cmd_context_channel = b2s_0_cmd_channelsOh; + assign b2s_0_cmd_context_veryLast = ((channels_1_pop_b2s_veryLastValid && (b2s_0_cmd_address[10 : 1] == b2s_0_cmd_veryLastPtr[10 : 1])) && (b2s_0_cmd_address[0 : 0] == 1'b1)); + assign b2s_0_cmd_context_endPacket = channels_1_pop_b2s_veryLastEndPacket; + assign memory_core_io_reads_0_cmd_valid = (|b2s_0_cmd_channelsOh); + assign memory_core_io_reads_0_cmd_payload_address = b2s_0_cmd_address[9:0]; + assign memory_core_io_reads_0_cmd_payload_context = {b2s_0_cmd_context_endPacket,{b2s_0_cmd_context_veryLast,b2s_0_cmd_context_channel}}; + assign _zz_b2s_0_rsp_context_channel = memory_core_io_reads_0_rsp_payload_context; + assign b2s_0_rsp_context_channel = _zz_b2s_0_rsp_context_channel[0 : 0]; + assign b2s_0_rsp_context_veryLast = _zz_b2s_0_rsp_context_channel[1]; + assign b2s_0_rsp_context_endPacket = _zz_b2s_0_rsp_context_channel[2]; + assign io_outputs_0_valid = memory_core_io_reads_0_rsp_valid; + assign io_outputs_0_payload_data = memory_core_io_reads_0_rsp_payload_data; + assign io_outputs_0_payload_mask = memory_core_io_reads_0_rsp_payload_mask; + assign io_outputs_0_payload_sink = channels_1_pop_b2s_sinkId; + assign io_outputs_0_payload_last = (b2s_0_rsp_context_veryLast && b2s_0_rsp_context_endPacket); + assign io_outputs_0_fire = (io_outputs_0_valid && io_outputs_0_ready); + assign when_DmaSg_l725 = (io_outputs_0_fire && b2s_0_rsp_context_veryLast); + assign when_DmaSg_l726 = b2s_0_rsp_context_channel[0]; + assign _zz_m2b_cmd_s0_priority_masked = channels_1_priority; + assign m2b_cmd_s0_priority_masked = (channels_1_push_m2b_loadRequest && (channels_1_priority == _zz_m2b_cmd_s0_priority_masked)); + assign _zz_m2b_cmd_s0_priority_chosenOh = m2b_cmd_s0_priority_masked; + assign _zz_m2b_cmd_s0_priority_chosenOh_1 = {_zz_m2b_cmd_s0_priority_chosenOh,_zz_m2b_cmd_s0_priority_chosenOh}; + assign _zz_m2b_cmd_s0_priority_chosenOh_2 = (_zz_m2b_cmd_s0_priority_chosenOh_1 & (~ _zz__zz_m2b_cmd_s0_priority_chosenOh_2)); + assign m2b_cmd_s0_priority_chosenOh = (_zz_m2b_cmd_s0_priority_chosenOh_2[1 : 1] | _zz_m2b_cmd_s0_priority_chosenOh_2[0 : 0]); + assign m2b_cmd_s0_priority_weightLast = (channels_1_weight == m2b_cmd_s0_priority_counter); + assign m2b_cmd_s0_priority_contextNext = (m2b_cmd_s0_priority_weightLast ? m2b_cmd_s0_priority_chosenOh[0 : 0] : m2b_cmd_s0_priority_chosenOh); + assign when_DmaSg_l758 = (! m2b_cmd_s0_valid); + assign when_DmaSg_l760 = (|channels_1_push_m2b_loadRequest); + assign when_DmaSg_l763 = (2'b00 == _zz_m2b_cmd_s0_priority_masked); + assign when_DmaSg_l763_1 = (2'b01 == _zz_m2b_cmd_s0_priority_masked); + assign when_DmaSg_l763_2 = (2'b10 == _zz_m2b_cmd_s0_priority_masked); + assign when_DmaSg_l763_3 = (2'b11 == _zz_m2b_cmd_s0_priority_masked); + assign when_DmaSg_l773 = (channels_1_push_m2b_loadRequest && m2b_cmd_s0_priority_chosenOh[0]); + assign m2b_cmd_s0_address = channels_1_push_m2b_address; + assign m2b_cmd_s0_bytesLeft = channels_1_push_m2b_bytesLeft; + assign m2b_cmd_s0_readAddressBurstRange = m2b_cmd_s0_address[11 : 0]; + assign m2b_cmd_s0_lengthHead = ((~ m2b_cmd_s0_readAddressBurstRange) & channels_1_push_m2b_bytePerBurst); + assign m2b_cmd_s0_length = _zz_m2b_cmd_s0_length[11:0]; + assign m2b_cmd_s0_lastBurst = (m2b_cmd_s0_bytesLeft == _zz_m2b_cmd_s0_lastBurst); + assign m2b_cmd_s1_context_start = m2b_cmd_s1_address[3:0]; + assign m2b_cmd_s1_context_stop = _zz_m2b_cmd_s1_context_stop[3:0]; + assign m2b_cmd_s1_context_last = m2b_cmd_s1_lastBurst; + assign m2b_cmd_s1_context_length = m2b_cmd_s1_length; + always @(*) begin + io_read_cmd_valid = 1'b0; + if(m2b_cmd_s1_valid) begin + io_read_cmd_valid = 1'b1; + end + end + + assign io_read_cmd_payload_last = 1'b1; + assign io_read_cmd_payload_fragment_opcode = 1'b0; + assign io_read_cmd_payload_fragment_address = m2b_cmd_s1_address; + assign io_read_cmd_payload_fragment_length = m2b_cmd_s1_length; + assign io_read_cmd_payload_fragment_context = {m2b_cmd_s1_context_last,{m2b_cmd_s1_context_length,{m2b_cmd_s1_context_stop,m2b_cmd_s1_context_start}}}; + assign m2b_cmd_s1_addressNext = (_zz_m2b_cmd_s1_addressNext + 32'h00000001); + assign m2b_cmd_s1_byteLeftNext = (_zz_m2b_cmd_s1_byteLeftNext - 26'h0000001); + assign m2b_cmd_s1_fifoPushDecr = (_zz_m2b_cmd_s1_fifoPushDecr >>> 2'd3); + assign when_DmaSg_l828 = 1'b1; + assign _zz_m2b_rsp_context_start = io_read_rsp_payload_fragment_context; + assign m2b_rsp_context_start = _zz_m2b_rsp_context_start[3 : 0]; + assign m2b_rsp_context_stop = _zz_m2b_rsp_context_start[7 : 4]; + assign m2b_rsp_context_length = _zz_m2b_rsp_context_start[19 : 8]; + assign m2b_rsp_context_last = _zz_m2b_rsp_context_start[20]; + assign m2b_rsp_veryLast = (m2b_rsp_context_last && io_read_rsp_payload_last); + assign io_read_rsp_fire = (io_read_rsp_valid && io_read_rsp_ready); + assign when_DmaSg_l847 = (io_read_rsp_fire && m2b_rsp_veryLast); + assign when_DmaSg_l848 = 1'b1; + always @(*) begin + memory_core_io_writes_1_cmd_payload_mask[0] = ((! (m2b_rsp_first && (4'b0000 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0000)))); + memory_core_io_writes_1_cmd_payload_mask[1] = ((! (m2b_rsp_first && (4'b0001 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0001)))); + memory_core_io_writes_1_cmd_payload_mask[2] = ((! (m2b_rsp_first && (4'b0010 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0010)))); + memory_core_io_writes_1_cmd_payload_mask[3] = ((! (m2b_rsp_first && (4'b0011 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0011)))); + memory_core_io_writes_1_cmd_payload_mask[4] = ((! (m2b_rsp_first && (4'b0100 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0100)))); + memory_core_io_writes_1_cmd_payload_mask[5] = ((! (m2b_rsp_first && (4'b0101 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0101)))); + memory_core_io_writes_1_cmd_payload_mask[6] = ((! (m2b_rsp_first && (4'b0110 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0110)))); + memory_core_io_writes_1_cmd_payload_mask[7] = ((! (m2b_rsp_first && (4'b0111 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0111)))); + memory_core_io_writes_1_cmd_payload_mask[8] = ((! (m2b_rsp_first && (4'b1000 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1000)))); + memory_core_io_writes_1_cmd_payload_mask[9] = ((! (m2b_rsp_first && (4'b1001 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1001)))); + memory_core_io_writes_1_cmd_payload_mask[10] = ((! (m2b_rsp_first && (4'b1010 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1010)))); + memory_core_io_writes_1_cmd_payload_mask[11] = ((! (m2b_rsp_first && (4'b1011 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1011)))); + memory_core_io_writes_1_cmd_payload_mask[12] = ((! (m2b_rsp_first && (4'b1100 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1100)))); + memory_core_io_writes_1_cmd_payload_mask[13] = ((! (m2b_rsp_first && (4'b1101 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1101)))); + memory_core_io_writes_1_cmd_payload_mask[14] = ((! (m2b_rsp_first && (4'b1110 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1110)))); + memory_core_io_writes_1_cmd_payload_mask[15] = ((! (m2b_rsp_first && (4'b1111 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1111)))); + end + + assign m2b_rsp_writeContext_last = m2b_rsp_veryLast; + assign m2b_rsp_writeContext_lastOfBurst = io_read_rsp_payload_last; + assign m2b_rsp_writeContext_loadByteInNextBeat = ({1'b0,(io_read_rsp_payload_last ? m2b_rsp_context_stop : 4'b1111)} - {1'b0,(m2b_rsp_first ? m2b_rsp_context_start : 4'b0000)}); + assign memory_core_io_writes_1_cmd_payload_address = channels_1_fifo_push_ptrWithBase[9:0]; + assign io_read_rsp_ready = memory_core_io_writes_1_cmd_ready; + assign memory_core_io_writes_1_cmd_payload_context = {m2b_rsp_writeContext_loadByteInNextBeat,{m2b_rsp_writeContext_lastOfBurst,m2b_rsp_writeContext_last}}; + assign memory_core_io_writes_1_cmd_fire = (io_read_rsp_valid && memory_core_io_writes_1_cmd_ready); + assign _zz_channels_1_fifo_push_ptrIncr_value = (memory_core_io_writes_1_cmd_fire && 1'b1); + assign when_DmaSg_l874 = (_zz_channels_1_fifo_push_ptrIncr_value && io_read_rsp_payload_last); + assign _zz_m2b_writeRsp_context_last = memory_core_io_writes_1_rsp_payload_context; + assign m2b_writeRsp_context_last = _zz_m2b_writeRsp_context_last[0]; + assign m2b_writeRsp_context_lastOfBurst = _zz_m2b_writeRsp_context_last[1]; + assign m2b_writeRsp_context_loadByteInNextBeat = _zz_m2b_writeRsp_context_last[6 : 2]; + assign _zz_channels_1_fifo_pop_bytesIncr_value = (memory_core_io_writes_1_rsp_valid && 1'b1); + assign when_DmaSg_l893 = (_zz_channels_1_fifo_pop_bytesIncr_value && m2b_writeRsp_context_lastOfBurst); + assign _zz_b2m_fsm_arbiter_logic_priority_masked = channels_0_priority; + assign b2m_fsm_arbiter_logic_priority_masked = (channels_0_pop_b2m_request && (channels_0_priority == _zz_b2m_fsm_arbiter_logic_priority_masked)); + assign _zz_b2m_fsm_arbiter_logic_priority_chosenOh = b2m_fsm_arbiter_logic_priority_masked; + assign _zz_b2m_fsm_arbiter_logic_priority_chosenOh_1 = {_zz_b2m_fsm_arbiter_logic_priority_chosenOh,_zz_b2m_fsm_arbiter_logic_priority_chosenOh}; + assign _zz_b2m_fsm_arbiter_logic_priority_chosenOh_2 = (_zz_b2m_fsm_arbiter_logic_priority_chosenOh_1 & (~ _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2)); + assign b2m_fsm_arbiter_logic_priority_chosenOh = (_zz_b2m_fsm_arbiter_logic_priority_chosenOh_2[1 : 1] | _zz_b2m_fsm_arbiter_logic_priority_chosenOh_2[0 : 0]); + assign b2m_fsm_arbiter_logic_priority_weightLast = (channels_0_weight == b2m_fsm_arbiter_logic_priority_counter); + assign b2m_fsm_arbiter_logic_priority_contextNext = (b2m_fsm_arbiter_logic_priority_weightLast ? b2m_fsm_arbiter_logic_priority_chosenOh[0 : 0] : b2m_fsm_arbiter_logic_priority_chosenOh); + assign when_DmaSg_l758_1 = (! b2m_fsm_arbiter_logic_valid); + assign when_DmaSg_l760_1 = (|channels_0_pop_b2m_request); + assign when_DmaSg_l763_4 = (2'b00 == _zz_b2m_fsm_arbiter_logic_priority_masked); + assign when_DmaSg_l763_5 = (2'b01 == _zz_b2m_fsm_arbiter_logic_priority_masked); + assign when_DmaSg_l763_6 = (2'b10 == _zz_b2m_fsm_arbiter_logic_priority_masked); + assign when_DmaSg_l763_7 = (2'b11 == _zz_b2m_fsm_arbiter_logic_priority_masked); + assign when_DmaSg_l773_1 = (channels_0_pop_b2m_request && b2m_fsm_arbiter_logic_priority_chosenOh[0]); + assign when_DmaSg_l935 = ((! b2m_fsm_sel_valid) && b2m_fsm_arbiter_logic_valid); + assign b2m_fsm_bytesInBurstP1 = ({1'b0,b2m_fsm_sel_bytesInBurst} + _zz_b2m_fsm_bytesInBurstP1); + assign b2m_fsm_addressNext = (b2m_fsm_sel_address + _zz_b2m_fsm_addressNext); + assign b2m_fsm_bytesLeftNext = ({1'b0,b2m_fsm_sel_bytesLeft} - _zz_b2m_fsm_bytesLeftNext); + assign b2m_fsm_isFinalCmd = b2m_fsm_bytesLeftNext[26]; + assign b2m_fsm_s0 = (b2m_fsm_sel_valid && (! b2m_fsm_sel_valid_regNext)); + assign when_DmaSg_l986 = (! b2m_fsm_sel_valid); + assign _zz_b2m_fsm_sel_bytesInBurst = (b2m_fsm_sel_bytesInFifo - 14'h0001); + assign _zz_b2m_fsm_sel_bytesInBurst_1 = ((_zz__zz_b2m_fsm_sel_bytesInBurst_1 < b2m_fsm_sel_bytesLeft) ? _zz__zz_b2m_fsm_sel_bytesInBurst_1_1 : b2m_fsm_sel_bytesLeft); + assign _zz_b2m_fsm_sel_bytesInBurst_2 = (b2m_fsm_sel_bytePerBurst - (_zz__zz_b2m_fsm_sel_bytesInBurst_2 & b2m_fsm_sel_bytePerBurst)); + assign b2m_fsm_fifoCompletion = (_zz_b2m_fsm_fifoCompletion == _zz_b2m_fsm_fifoCompletion_1); + assign when_DmaSg_l996 = 1'b1; + assign when_DmaSg_l1001 = (! b2m_fsm_fifoCompletion); + assign when_DmaSg_l1013 = (b2m_fsm_sel_valid && b2m_fsm_sel_ready); + always @(*) begin + b2m_fsm_sel_ready = 1'b0; + if(when_DmaSg_l1102) begin + b2m_fsm_sel_ready = 1'b1; + end + end + + assign b2m_fsm_fetch_context_ptr = channels_0_fifo_pop_ptr; + assign b2m_fsm_fetch_context_toggle = b2m_fsm_toggle; + assign memory_core_io_reads_1_cmd_payload_address = b2m_fsm_sel_ptr[9:0]; + assign memory_core_io_reads_1_cmd_payload_context = {b2m_fsm_fetch_context_toggle,b2m_fsm_fetch_context_ptr}; + assign when_DmaSg_l1033 = (b2m_fsm_sel_valid && memory_core_io_reads_1_cmd_ready); + assign _zz_b2m_fsm_aggregate_context_ptr = memory_core_io_reads_1_rsp_payload_context; + assign b2m_fsm_aggregate_context_ptr = _zz_b2m_fsm_aggregate_context_ptr[10 : 0]; + assign b2m_fsm_aggregate_context_toggle = _zz_b2m_fsm_aggregate_context_ptr[11]; + assign memory_core_io_reads_1_rsp_s2mPipe_valid = (memory_core_io_reads_1_rsp_valid || (! memory_core_io_reads_1_rsp_rValidN)); + assign memory_core_io_reads_1_rsp_s2mPipe_payload_data = (memory_core_io_reads_1_rsp_rValidN ? memory_core_io_reads_1_rsp_payload_data : memory_core_io_reads_1_rsp_rData_data); + assign memory_core_io_reads_1_rsp_s2mPipe_payload_mask = (memory_core_io_reads_1_rsp_rValidN ? memory_core_io_reads_1_rsp_payload_mask : memory_core_io_reads_1_rsp_rData_mask); + assign memory_core_io_reads_1_rsp_s2mPipe_payload_context = (memory_core_io_reads_1_rsp_rValidN ? memory_core_io_reads_1_rsp_payload_context : memory_core_io_reads_1_rsp_rData_context); + assign when_Stream_l445 = (b2m_fsm_aggregate_context_toggle != b2m_fsm_toggle); + always @(*) begin + b2m_fsm_aggregate_memoryPort_valid = memory_core_io_reads_1_rsp_s2mPipe_valid; + if(when_Stream_l445) begin + b2m_fsm_aggregate_memoryPort_valid = 1'b0; + end + end + + always @(*) begin + memory_core_io_reads_1_rsp_s2mPipe_ready = b2m_fsm_aggregate_memoryPort_ready; + if(when_Stream_l445) begin + memory_core_io_reads_1_rsp_s2mPipe_ready = 1'b1; + end + end + + assign b2m_fsm_aggregate_memoryPort_payload_data = memory_core_io_reads_1_rsp_s2mPipe_payload_data; + assign b2m_fsm_aggregate_memoryPort_payload_mask = memory_core_io_reads_1_rsp_s2mPipe_payload_mask; + assign b2m_fsm_aggregate_memoryPort_payload_context = memory_core_io_reads_1_rsp_s2mPipe_payload_context; + assign b2m_fsm_aggregate_memoryPort_fire = (b2m_fsm_aggregate_memoryPort_valid && b2m_fsm_aggregate_memoryPort_ready); + assign when_DmaSg_l1050 = (! (b2m_fsm_sel_valid && (! b2m_fsm_sel_ready))); + assign b2m_fsm_aggregate_bytesToSkip = channels_0_pop_b2m_bytesToSkip; + assign b2m_fsm_aggregate_bytesToSkipMask = {((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1111)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1110)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= _zz_b2m_fsm_aggregate_bytesToSkipMask)),{(_zz_b2m_fsm_aggregate_bytesToSkipMask_1 || _zz_b2m_fsm_aggregate_bytesToSkipMask_2),{_zz_b2m_fsm_aggregate_bytesToSkipMask_3,{_zz_b2m_fsm_aggregate_bytesToSkipMask_4,_zz_b2m_fsm_aggregate_bytesToSkipMask_5}}}}}}; + assign b2m_fsm_aggregate_memoryPort_ready = b2m_fsm_aggregate_engine_io_input_ready; + assign b2m_fsm_aggregate_engine_io_input_payload_mask = (b2m_fsm_aggregate_memoryPort_payload_mask & b2m_fsm_aggregate_bytesToSkipMask); + assign b2m_fsm_aggregate_engine_io_offset = b2m_fsm_sel_address[3:0]; + assign b2m_fsm_aggregate_engine_io_flush = (! _zz_io_flush); + assign b2m_fsm_cmd_maskFirstTrigger = b2m_fsm_sel_address[3:0]; + assign b2m_fsm_cmd_maskLastTriggerComb = (b2m_fsm_cmd_maskFirstTrigger + _zz_b2m_fsm_cmd_maskLastTriggerComb); + assign b2m_fsm_cmd_maskFirst = {(b2m_fsm_cmd_maskFirstTrigger <= 4'b1111),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1110),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1101),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1100),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1011),{(b2m_fsm_cmd_maskFirstTrigger <= _zz_b2m_fsm_cmd_maskFirst),{_zz_b2m_fsm_cmd_maskFirst_1,{_zz_b2m_fsm_cmd_maskFirst_2,_zz_b2m_fsm_cmd_maskFirst_3}}}}}}}}; + assign b2m_fsm_cmd_enoughAggregation = (((b2m_fsm_s2 && b2m_fsm_sel_valid) && (! b2m_fsm_aggregate_engine_io_flush)) && (io_write_cmd_payload_last ? ((b2m_fsm_aggregate_engine_io_output_mask & b2m_fsm_cmd_maskLast) == b2m_fsm_cmd_maskLast) : (&b2m_fsm_aggregate_engine_io_output_mask))); + assign io_write_cmd_fire = (io_write_cmd_valid && io_write_cmd_ready); + assign io_write_cmd_valid = b2m_fsm_cmd_enoughAggregation; + assign io_write_cmd_payload_last = (b2m_fsm_beatCounter == 8'h0); + assign io_write_cmd_payload_fragment_address = b2m_fsm_sel_address; + assign io_write_cmd_payload_fragment_opcode = 1'b1; + assign io_write_cmd_payload_fragment_data = b2m_fsm_aggregate_engine_io_output_data; + assign io_write_cmd_payload_fragment_mask = (~ ((io_write_cmd_payload_first ? (~ b2m_fsm_cmd_maskFirst) : 16'h0) | (io_write_cmd_payload_last ? (~ b2m_fsm_cmd_maskLast) : 16'h0))); + assign io_write_cmd_payload_fragment_length = b2m_fsm_sel_bytesInBurst; + assign b2m_fsm_cmd_doPtrIncr = (b2m_fsm_sel_valid && (b2m_fsm_aggregate_engine_io_output_consumed || ((io_write_cmd_fire && io_write_cmd_payload_last) && (b2m_fsm_aggregate_engine_io_output_usedUntil == 4'b1111)))); + assign b2m_fsm_cmd_context_length = b2m_fsm_sel_bytesInBurst; + assign b2m_fsm_cmd_context_doPacketSync = (b2m_fsm_sel_packet && b2m_fsm_fifoCompletion); + assign io_write_cmd_payload_fragment_context = {b2m_fsm_cmd_context_doPacketSync,b2m_fsm_cmd_context_length}; + assign when_DmaSg_l1102 = (io_write_cmd_fire && io_write_cmd_payload_last); + assign io_write_rsp_ready = 1'b1; + assign _zz_b2m_rsp_context_length = io_write_rsp_payload_fragment_context; + assign b2m_rsp_context_length = _zz_b2m_rsp_context_length[11 : 0]; + assign b2m_rsp_context_doPacketSync = _zz_b2m_rsp_context_length[12]; + assign io_write_rsp_fire = (io_write_rsp_valid && io_write_rsp_ready); + assign when_DmaSg_l1116 = 1'b1; + assign _zz_ll_arbiter_head = {channels_1_ll_requestLl,channels_0_ll_requestLl}; + assign _zz_ll_arbiter_head_1 = _zz__zz_ll_arbiter_head_1[1]; + assign ll_arbiter_head = (_zz_ll_arbiter_head_2[0] ? channels_0_ll_head : channels_1_ll_head); + assign ll_arbiter_isJustASink = (_zz_ll_arbiter_isJustASink[0] ? channels_0_descriptorValid : channels_1_descriptorValid); + assign ll_arbiter_doDescriptorStall = (_zz_ll_arbiter_doDescriptorStall[0] ? ((! channels_0_ll_controlNoCompletion) || channels_0_ll_gotDescriptorStall) : ((! channels_1_ll_controlNoCompletion) || channels_1_ll_gotDescriptorStall)); + assign ll_arbiter_onSgStream = (_zz_ll_arbiter_onSgStream[0] ? channels_0_ll_onSgStream : channels_1_ll_onSgStream); + assign when_DmaSg_l1149 = (! ll_cmd_valid); + assign when_DmaSg_l1148 = (! ll_cmd_valid); + assign when_DmaSg_l1148_1 = (! ll_cmd_valid); + assign when_DmaSg_l1148_2 = (! ll_cmd_valid); + assign when_DmaSg_l1148_3 = (! ll_cmd_valid); + assign when_DmaSg_l1154 = (! ll_cmd_valid); + assign when_DmaSg_l1155 = (! ll_cmd_valid); + assign when_DmaSg_l1156 = (! ll_cmd_valid); + assign when_DmaSg_l1160 = (! ll_cmd_valid); + assign when_DmaSg_l1161 = (|{_zz_ll_arbiter_head_1,channels_0_ll_requestLl}); + assign when_DmaSg_l1169 = (! ll_arbiter_isJustASink); + assign when_DmaSg_l1169_1 = (! ll_arbiter_isJustASink); + assign when_DmaSg_l1177 = (ll_cmd_writeFired && ll_cmd_readFired); + assign ll_cmd_context_channel = ll_cmd_oh_1; + assign io_sgRead_cmd_valid = ((ll_cmd_valid && (! ll_cmd_readFired)) && (! ll_cmd_onSgStream)); + assign io_sgRead_cmd_payload_last = 1'b1; + assign io_sgRead_cmd_payload_fragment_address = {ll_cmd_ptrNext[31 : 5],5'h0}; + assign io_sgRead_cmd_payload_fragment_length = 5'h1f; + assign io_sgRead_cmd_payload_fragment_opcode = 1'b0; + assign io_sgRead_cmd_payload_fragment_context = ll_cmd_context_channel; + assign io_sgWrite_cmd_valid = ((ll_cmd_valid && (! ll_cmd_writeFired)) && (! ll_cmd_onSgStream)); + assign io_sgWrite_cmd_payload_last = 1'b1; + assign io_sgWrite_cmd_payload_fragment_address = {ll_cmd_ptr[31 : 5],5'h0}; + assign io_sgWrite_cmd_payload_fragment_length = 2'b11; + assign io_sgWrite_cmd_payload_fragment_opcode = 1'b1; + assign io_sgWrite_cmd_payload_fragment_context = ll_cmd_context_channel; + assign ll_cmd_writeMaskSplit_0 = io_sgWrite_cmd_payload_fragment_mask[3 : 0]; + assign ll_cmd_writeMaskSplit_1 = io_sgWrite_cmd_payload_fragment_mask[7 : 4]; + assign ll_cmd_writeMaskSplit_2 = io_sgWrite_cmd_payload_fragment_mask[11 : 8]; + assign ll_cmd_writeMaskSplit_3 = io_sgWrite_cmd_payload_fragment_mask[15 : 12]; + assign ll_cmd_writeDataSplit_0 = io_sgWrite_cmd_payload_fragment_data[31 : 0]; + assign ll_cmd_writeDataSplit_1 = io_sgWrite_cmd_payload_fragment_data[63 : 32]; + assign ll_cmd_writeDataSplit_2 = io_sgWrite_cmd_payload_fragment_data[95 : 64]; + assign ll_cmd_writeDataSplit_3 = io_sgWrite_cmd_payload_fragment_data[127 : 96]; + assign _zz_1 = zz_io_sgWrite_cmd_payload_fragment_mask(1'b0); + always @(*) io_sgWrite_cmd_payload_fragment_mask = _zz_1; + always @(*) begin + io_sgWrite_cmd_payload_fragment_data[63 : 32] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + io_sgWrite_cmd_payload_fragment_data[95 : 64] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + io_sgWrite_cmd_payload_fragment_data[127 : 96] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + io_sgWrite_cmd_payload_fragment_data[31 : 0] = 32'h0; + io_sgWrite_cmd_payload_fragment_data[26 : 0] = ll_cmd_bytesDone; + io_sgWrite_cmd_payload_fragment_data[30] = ll_cmd_endOfPacket; + io_sgWrite_cmd_payload_fragment_data[31] = ((! ll_cmd_isJustASink) && ll_cmd_doDescriptorStall); + end + + assign io_sgRead_cmd_fire = (io_sgRead_cmd_valid && io_sgRead_cmd_ready); + assign io_sgWrite_cmd_fire = (io_sgWrite_cmd_valid && io_sgWrite_cmd_ready); + assign ll_readRsp_context_channel = io_sgRead_rsp_payload_fragment_context[0 : 0]; + assign _zz_ll_readRsp_oh_0 = (2'b01 <<< ll_readRsp_context_channel); + assign ll_readRsp_oh_0 = _zz_ll_readRsp_oh_0[0]; + assign ll_readRsp_oh_1 = _zz_ll_readRsp_oh_0[1]; + assign io_sgRead_rsp_ready = 1'b1; + assign io_sgRead_rsp_fire = (io_sgRead_rsp_valid && io_sgRead_rsp_ready); + assign when_DmaSg_l1248 = (1'b0 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_1 = (1'b1 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_2 = (1'b1 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_3 = (1'b0 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_4 = (1'b0 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_5 = (1'b0 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_6 = (1'b0 == ll_readRsp_beatCounter); + assign when_DmaSg_l1271 = (io_sgRead_rsp_fire && io_sgRead_rsp_payload_last); + assign ll_writeRsp_context_channel = io_sgWrite_rsp_payload_fragment_context[0 : 0]; + assign _zz_ll_writeRsp_oh_0 = (2'b01 <<< ll_writeRsp_context_channel); + assign ll_writeRsp_oh_0 = _zz_ll_writeRsp_oh_0[0]; + assign ll_writeRsp_oh_1 = _zz_ll_writeRsp_oh_0[1]; + assign io_sgWrite_rsp_ready = 1'b1; + assign io_sgWrite_rsp_fire = (io_sgWrite_rsp_valid && io_sgWrite_rsp_ready); + always @(*) begin + io_interrupts = 2'b00; + if(channels_0_interrupts_completion_valid) begin + io_interrupts[0] = 1'b1; + end + if(channels_0_interrupts_onChannelCompletion_valid) begin + io_interrupts[0] = 1'b1; + end + if(channels_0_interrupts_onLinkedListUpdate_valid) begin + io_interrupts[0] = 1'b1; + end + if(channels_0_interrupts_s2mPacket_valid) begin + io_interrupts[0] = 1'b1; + end + if(channels_1_interrupts_completion_valid) begin + io_interrupts[1] = 1'b1; + end + if(channels_1_interrupts_onChannelCompletion_valid) begin + io_interrupts[1] = 1'b1; + end + if(channels_1_interrupts_onLinkedListUpdate_valid) begin + io_interrupts[1] = 1'b1; + end + end + + always @(*) begin + when_BusSlaveFactory_l377 = 1'b0; + case(io_ctrl_PADDR) + 14'h002c : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l377_1 = 1'b0; + case(io_ctrl_PADDR) + 14'h002c : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_1 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l377_2 = 1'b0; + case(io_ctrl_PADDR) + 14'h002c : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_2 = io_ctrl_PWDATA[4]; + always @(*) begin + when_BusSlaveFactory_l377_3 = 1'b0; + case(io_ctrl_PADDR) + 14'h002c : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_3 = io_ctrl_PWDATA[4]; + always @(*) begin + when_BusSlaveFactory_l341 = 1'b0; + case(io_ctrl_PADDR) + 14'h0054 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l341_1 = 1'b0; + case(io_ctrl_PADDR) + 14'h0054 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_1 = io_ctrl_PWDATA[2]; + always @(*) begin + when_BusSlaveFactory_l341_2 = 1'b0; + case(io_ctrl_PADDR) + 14'h0054 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_2 = io_ctrl_PWDATA[3]; + always @(*) begin + when_BusSlaveFactory_l341_3 = 1'b0; + case(io_ctrl_PADDR) + 14'h0054 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_3 = io_ctrl_PWDATA[4]; + always @(*) begin + when_BusSlaveFactory_l377_4 = 1'b0; + case(io_ctrl_PADDR) + 14'h00ac : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_4 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_4 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l377_5 = 1'b0; + case(io_ctrl_PADDR) + 14'h00ac : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_5 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_5 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l377_6 = 1'b0; + case(io_ctrl_PADDR) + 14'h00ac : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_6 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_6 = io_ctrl_PWDATA[4]; + always @(*) begin + when_BusSlaveFactory_l377_7 = 1'b0; + case(io_ctrl_PADDR) + 14'h00ac : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_7 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_7 = io_ctrl_PWDATA[4]; + always @(*) begin + when_BusSlaveFactory_l341_4 = 1'b0; + case(io_ctrl_PADDR) + 14'h00d4 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_4 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_4 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l341_5 = 1'b0; + case(io_ctrl_PADDR) + 14'h00d4 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_5 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_5 = io_ctrl_PWDATA[2]; + always @(*) begin + when_BusSlaveFactory_l341_6 = 1'b0; + case(io_ctrl_PADDR) + 14'h00d4 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_6 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_6 = io_ctrl_PWDATA[3]; + assign when_Apb3SlaveFactory_l81 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h0010); + assign when_Apb3SlaveFactory_l81_1 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h0070); + assign when_Apb3SlaveFactory_l81_2 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h0080); + assign when_Apb3SlaveFactory_l81_3 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h00f0); + assign channels_0_fifo_push_ptrIncr_value = _zz_channels_0_fifo_push_ptrIncr_value; + assign channels_0_fifo_pop_bytesIncr_value = _zz_channels_0_fifo_pop_bytesIncr_value_1; + assign channels_0_fifo_pop_bytesDecr_value = channels_0_pop_b2m_decrBytes; + assign channels_0_fifo_pop_ptrIncr_value = _zz_channels_0_fifo_pop_ptrIncr_value; + assign channels_1_fifo_push_ptrIncr_value = _zz_channels_1_fifo_push_ptrIncr_value_1; + assign channels_1_fifo_pop_bytesIncr_value = _zz_channels_1_fifo_pop_bytesIncr_value_1; + assign channels_1_fifo_pop_bytesDecr_value = 14'h0; + assign channels_1_fifo_pop_ptrIncr_value = _zz_channels_1_fifo_pop_ptrIncr_value; + assign ll_0_descriptorUpdate = (channels_0_ll_descriptorUpdated && (! channels_0_ll_gotDescriptorStall)); + assign ll_1_descriptorUpdate = (channels_1_ll_descriptorUpdated && (! channels_1_ll_gotDescriptorStall)); + always @(posedge clk) begin + if(reset) begin + channels_0_channelValid <= 1'b0; + channels_0_descriptorValid <= 1'b0; + channels_0_priority <= 2'b00; + channels_0_weight <= 2'b00; + channels_0_ctrl_kick <= 1'b0; + channels_0_ll_valid <= 1'b0; + channels_0_ll_onSgStream <= 1'b0; + channels_0_pop_b2m_memPending <= 4'b0000; + channels_0_interrupts_completion_enable <= 1'b0; + channels_0_interrupts_completion_valid <= 1'b0; + channels_0_interrupts_onChannelCompletion_enable <= 1'b0; + channels_0_interrupts_onChannelCompletion_valid <= 1'b0; + channels_0_interrupts_onLinkedListUpdate_enable <= 1'b0; + channels_0_interrupts_onLinkedListUpdate_valid <= 1'b0; + channels_0_interrupts_s2mPacket_enable <= 1'b0; + channels_0_interrupts_s2mPacket_valid <= 1'b0; + channels_1_channelValid <= 1'b0; + channels_1_descriptorValid <= 1'b0; + channels_1_priority <= 2'b00; + channels_1_weight <= 2'b00; + channels_1_ctrl_kick <= 1'b0; + channels_1_ll_valid <= 1'b0; + channels_1_ll_onSgStream <= 1'b0; + channels_1_push_m2b_loadDone <= 1'b1; + channels_1_push_m2b_memPending <= 4'b0000; + channels_1_interrupts_completion_enable <= 1'b0; + channels_1_interrupts_completion_valid <= 1'b0; + channels_1_interrupts_onChannelCompletion_enable <= 1'b0; + channels_1_interrupts_onChannelCompletion_valid <= 1'b0; + channels_1_interrupts_onLinkedListUpdate_enable <= 1'b0; + channels_1_interrupts_onLinkedListUpdate_valid <= 1'b0; + io_inputs_0_payload_last_regNextWhen <= 1'b1; + io_inputs_0_payload_last_regNextWhen_1 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_2 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_3 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_4 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_5 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_6 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_7 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_8 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_9 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_10 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_11 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_12 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_13 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_14 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_15 <= 1'b1; + m2b_cmd_s0_valid <= 1'b0; + m2b_cmd_s0_priority_roundRobins_0 <= 1'b1; + m2b_cmd_s0_priority_roundRobins_1 <= 1'b1; + m2b_cmd_s0_priority_roundRobins_2 <= 1'b1; + m2b_cmd_s0_priority_roundRobins_3 <= 1'b1; + m2b_cmd_s0_priority_counter <= 2'b00; + m2b_cmd_s1_valid <= 1'b0; + m2b_rsp_first <= 1'b1; + b2m_fsm_sel_valid <= 1'b0; + b2m_fsm_arbiter_logic_valid <= 1'b0; + b2m_fsm_arbiter_logic_priority_roundRobins_0 <= 1'b1; + b2m_fsm_arbiter_logic_priority_roundRobins_1 <= 1'b1; + b2m_fsm_arbiter_logic_priority_roundRobins_2 <= 1'b1; + b2m_fsm_arbiter_logic_priority_roundRobins_3 <= 1'b1; + b2m_fsm_arbiter_logic_priority_counter <= 2'b00; + b2m_fsm_sel_valid_regNext <= 1'b0; + b2m_fsm_s1 <= 1'b0; + b2m_fsm_s2 <= 1'b0; + b2m_fsm_toggle <= 1'b0; + memory_core_io_reads_1_rsp_rValidN <= 1'b1; + _zz_io_flush <= 1'b0; + io_write_cmd_payload_first <= 1'b1; + ll_cmd_valid <= 1'b0; + ll_readRsp_beatCounter <= 1'b0; + end else begin + if(channels_0_channelStart) begin + channels_0_channelValid <= 1'b1; + end + if(channels_0_channelCompletion) begin + channels_0_channelValid <= 1'b0; + end + if(channels_0_descriptorStart) begin + channels_0_descriptorValid <= 1'b1; + end + if(channels_0_descriptorCompletion) begin + channels_0_descriptorValid <= 1'b0; + end + channels_0_ctrl_kick <= 1'b0; + if(channels_0_channelCompletion) begin + channels_0_ctrl_kick <= 1'b0; + end + if(when_DmaSg_l318) begin + if(when_DmaSg_l320) begin + if(!when_DmaSg_l322) begin + channels_0_ll_valid <= 1'b0; + end + end + end + if(channels_0_ll_sgStart) begin + channels_0_ll_valid <= 1'b1; + end + if(channels_0_channelCompletion) begin + channels_0_ll_valid <= 1'b0; + end + channels_0_pop_b2m_memPending <= (_zz_channels_0_pop_b2m_memPending - _zz_channels_0_pop_b2m_memPending_3); + if(when_DmaSg_l255) begin + channels_0_interrupts_completion_valid <= 1'b1; + end + if(when_DmaSg_l255_1) begin + channels_0_interrupts_completion_valid <= 1'b0; + end + if(when_DmaSg_l255_2) begin + channels_0_interrupts_onChannelCompletion_valid <= 1'b1; + end + if(when_DmaSg_l255_3) begin + channels_0_interrupts_onChannelCompletion_valid <= 1'b0; + end + if(channels_0_ll_descriptorUpdated) begin + channels_0_interrupts_onLinkedListUpdate_valid <= 1'b1; + end + if(when_DmaSg_l255_4) begin + channels_0_interrupts_onLinkedListUpdate_valid <= 1'b0; + end + if(channels_0_pop_b2m_packetSync) begin + channels_0_interrupts_s2mPacket_valid <= 1'b1; + end + if(when_DmaSg_l255_5) begin + channels_0_interrupts_s2mPacket_valid <= 1'b0; + end + if(channels_1_channelStart) begin + channels_1_channelValid <= 1'b1; + end + if(channels_1_channelCompletion) begin + channels_1_channelValid <= 1'b0; + end + if(channels_1_descriptorStart) begin + channels_1_descriptorValid <= 1'b1; + end + if(channels_1_descriptorCompletion) begin + channels_1_descriptorValid <= 1'b0; + end + channels_1_ctrl_kick <= 1'b0; + if(channels_1_channelCompletion) begin + channels_1_ctrl_kick <= 1'b0; + end + if(when_DmaSg_l318_1) begin + if(when_DmaSg_l320_1) begin + if(!when_DmaSg_l322_1) begin + channels_1_ll_valid <= 1'b0; + end + end + end + if(channels_1_ll_sgStart) begin + channels_1_ll_valid <= 1'b1; + end + if(channels_1_channelCompletion) begin + channels_1_ll_valid <= 1'b0; + end + channels_1_push_m2b_memPending <= (_zz_channels_1_push_m2b_memPending - _zz_channels_1_push_m2b_memPending_3); + if(channels_1_descriptorStart) begin + channels_1_push_m2b_loadDone <= 1'b0; + end + if(when_DmaSg_l255_6) begin + channels_1_interrupts_completion_valid <= 1'b1; + end + if(when_DmaSg_l255_7) begin + channels_1_interrupts_completion_valid <= 1'b0; + end + if(when_DmaSg_l255_8) begin + channels_1_interrupts_onChannelCompletion_valid <= 1'b1; + end + if(when_DmaSg_l255_9) begin + channels_1_interrupts_onChannelCompletion_valid <= 1'b0; + end + if(channels_1_ll_descriptorUpdated) begin + channels_1_interrupts_onLinkedListUpdate_valid <= 1'b1; + end + if(when_DmaSg_l255_10) begin + channels_1_interrupts_onLinkedListUpdate_valid <= 1'b0; + end + if(when_package_l12) begin + io_inputs_0_payload_last_regNextWhen <= io_inputs_0_payload_last; + end + if(when_package_l12_1) begin + io_inputs_0_payload_last_regNextWhen_1 <= io_inputs_0_payload_last; + end + if(when_package_l12_2) begin + io_inputs_0_payload_last_regNextWhen_2 <= io_inputs_0_payload_last; + end + if(when_package_l12_3) begin + io_inputs_0_payload_last_regNextWhen_3 <= io_inputs_0_payload_last; + end + if(when_package_l12_4) begin + io_inputs_0_payload_last_regNextWhen_4 <= io_inputs_0_payload_last; + end + if(when_package_l12_5) begin + io_inputs_0_payload_last_regNextWhen_5 <= io_inputs_0_payload_last; + end + if(when_package_l12_6) begin + io_inputs_0_payload_last_regNextWhen_6 <= io_inputs_0_payload_last; + end + if(when_package_l12_7) begin + io_inputs_0_payload_last_regNextWhen_7 <= io_inputs_0_payload_last; + end + if(when_package_l12_8) begin + io_inputs_0_payload_last_regNextWhen_8 <= io_inputs_0_payload_last; + end + if(when_package_l12_9) begin + io_inputs_0_payload_last_regNextWhen_9 <= io_inputs_0_payload_last; + end + if(when_package_l12_10) begin + io_inputs_0_payload_last_regNextWhen_10 <= io_inputs_0_payload_last; + end + if(when_package_l12_11) begin + io_inputs_0_payload_last_regNextWhen_11 <= io_inputs_0_payload_last; + end + if(when_package_l12_12) begin + io_inputs_0_payload_last_regNextWhen_12 <= io_inputs_0_payload_last; + end + if(when_package_l12_13) begin + io_inputs_0_payload_last_regNextWhen_13 <= io_inputs_0_payload_last; + end + if(when_package_l12_14) begin + io_inputs_0_payload_last_regNextWhen_14 <= io_inputs_0_payload_last; + end + if(when_package_l12_15) begin + io_inputs_0_payload_last_regNextWhen_15 <= io_inputs_0_payload_last; + end + if(when_DmaSg_l758) begin + if(when_DmaSg_l760) begin + m2b_cmd_s0_valid <= 1'b1; + if(when_DmaSg_l763) begin + m2b_cmd_s0_priority_roundRobins_0 <= m2b_cmd_s0_priority_contextNext; + end + if(when_DmaSg_l763_1) begin + m2b_cmd_s0_priority_roundRobins_1 <= m2b_cmd_s0_priority_contextNext; + end + if(when_DmaSg_l763_2) begin + m2b_cmd_s0_priority_roundRobins_2 <= m2b_cmd_s0_priority_contextNext; + end + if(when_DmaSg_l763_3) begin + m2b_cmd_s0_priority_roundRobins_3 <= m2b_cmd_s0_priority_contextNext; + end + m2b_cmd_s0_priority_counter <= (m2b_cmd_s0_priority_counter + 2'b01); + if(m2b_cmd_s0_priority_weightLast) begin + m2b_cmd_s0_priority_counter <= 2'b00; + end + end + end + if(m2b_cmd_s0_valid) begin + m2b_cmd_s1_valid <= 1'b1; + end + if(m2b_cmd_s1_valid) begin + if(io_read_cmd_ready) begin + m2b_cmd_s0_valid <= 1'b0; + m2b_cmd_s1_valid <= 1'b0; + if(when_DmaSg_l828) begin + if(m2b_cmd_s1_lastBurst) begin + channels_1_push_m2b_loadDone <= 1'b1; + end + end + end + end + if(io_read_rsp_fire) begin + m2b_rsp_first <= io_read_rsp_payload_last; + end + if(when_DmaSg_l758_1) begin + if(when_DmaSg_l760_1) begin + b2m_fsm_arbiter_logic_valid <= 1'b1; + if(when_DmaSg_l763_4) begin + b2m_fsm_arbiter_logic_priority_roundRobins_0 <= b2m_fsm_arbiter_logic_priority_contextNext; + end + if(when_DmaSg_l763_5) begin + b2m_fsm_arbiter_logic_priority_roundRobins_1 <= b2m_fsm_arbiter_logic_priority_contextNext; + end + if(when_DmaSg_l763_6) begin + b2m_fsm_arbiter_logic_priority_roundRobins_2 <= b2m_fsm_arbiter_logic_priority_contextNext; + end + if(when_DmaSg_l763_7) begin + b2m_fsm_arbiter_logic_priority_roundRobins_3 <= b2m_fsm_arbiter_logic_priority_contextNext; + end + b2m_fsm_arbiter_logic_priority_counter <= (b2m_fsm_arbiter_logic_priority_counter + 2'b01); + if(b2m_fsm_arbiter_logic_priority_weightLast) begin + b2m_fsm_arbiter_logic_priority_counter <= 2'b00; + end + end + end + if(b2m_fsm_sel_ready) begin + b2m_fsm_sel_valid <= 1'b0; + if(b2m_fsm_sel_valid) begin + b2m_fsm_arbiter_logic_valid <= 1'b0; + end + end + if(when_DmaSg_l935) begin + b2m_fsm_sel_valid <= 1'b1; + end + b2m_fsm_sel_valid_regNext <= b2m_fsm_sel_valid; + b2m_fsm_s1 <= b2m_fsm_s0; + if(b2m_fsm_s1) begin + b2m_fsm_s2 <= 1'b1; + end + if(when_DmaSg_l986) begin + b2m_fsm_s2 <= 1'b0; + end + if(when_DmaSg_l1013) begin + b2m_fsm_toggle <= (! b2m_fsm_toggle); + end + if(memory_core_io_reads_1_rsp_valid) begin + memory_core_io_reads_1_rsp_rValidN <= 1'b0; + end + if(memory_core_io_reads_1_rsp_s2mPipe_ready) begin + memory_core_io_reads_1_rsp_rValidN <= 1'b1; + end + _zz_io_flush <= (b2m_fsm_sel_valid && (! b2m_fsm_sel_ready)); + if(io_write_cmd_fire) begin + io_write_cmd_payload_first <= io_write_cmd_payload_last; + end + if(when_DmaSg_l1160) begin + if(when_DmaSg_l1161) begin + ll_cmd_valid <= 1'b1; + end + end else begin + if(when_DmaSg_l1177) begin + ll_cmd_valid <= 1'b0; + end + end + if(io_sgRead_rsp_fire) begin + ll_readRsp_beatCounter <= (ll_readRsp_beatCounter + 1'b1); + end + if(when_BusSlaveFactory_l377_1) begin + if(when_BusSlaveFactory_l379_1) begin + channels_0_ctrl_kick <= _zz_channels_0_ctrl_kick[0]; + end + end + if(when_BusSlaveFactory_l341) begin + if(when_BusSlaveFactory_l347) begin + channels_0_interrupts_completion_valid <= _zz_channels_0_interrupts_completion_valid[0]; + end + end + if(when_BusSlaveFactory_l341_1) begin + if(when_BusSlaveFactory_l347_1) begin + channels_0_interrupts_onChannelCompletion_valid <= _zz_channels_0_interrupts_onChannelCompletion_valid[0]; + end + end + if(when_BusSlaveFactory_l341_2) begin + if(when_BusSlaveFactory_l347_2) begin + channels_0_interrupts_onLinkedListUpdate_valid <= _zz_channels_0_interrupts_onLinkedListUpdate_valid[0]; + end + end + if(when_BusSlaveFactory_l341_3) begin + if(when_BusSlaveFactory_l347_3) begin + channels_0_interrupts_s2mPacket_valid <= _zz_channels_0_interrupts_s2mPacket_valid[0]; + end + end + if(when_BusSlaveFactory_l377_5) begin + if(when_BusSlaveFactory_l379_5) begin + channels_1_ctrl_kick <= _zz_channels_1_ctrl_kick[0]; + end + end + if(when_BusSlaveFactory_l341_4) begin + if(when_BusSlaveFactory_l347_4) begin + channels_1_interrupts_completion_valid <= _zz_channels_1_interrupts_completion_valid[0]; + end + end + if(when_BusSlaveFactory_l341_5) begin + if(when_BusSlaveFactory_l347_5) begin + channels_1_interrupts_onChannelCompletion_valid <= _zz_channels_1_interrupts_onChannelCompletion_valid[0]; + end + end + if(when_BusSlaveFactory_l341_6) begin + if(when_BusSlaveFactory_l347_6) begin + channels_1_interrupts_onLinkedListUpdate_valid <= _zz_channels_1_interrupts_onLinkedListUpdate_valid[0]; + end + end + case(io_ctrl_PADDR) + 14'h0078 : begin + if(ctrl_doWrite) begin + channels_0_ll_onSgStream <= io_ctrl_PWDATA[0]; + end + end + 14'h0044 : begin + if(ctrl_doWrite) begin + channels_0_priority <= io_ctrl_PWDATA[1 : 0]; + channels_0_weight <= io_ctrl_PWDATA[9 : 8]; + end + end + 14'h0050 : begin + if(ctrl_doWrite) begin + channels_0_interrupts_completion_enable <= io_ctrl_PWDATA[0]; + channels_0_interrupts_onChannelCompletion_enable <= io_ctrl_PWDATA[2]; + channels_0_interrupts_onLinkedListUpdate_enable <= io_ctrl_PWDATA[3]; + channels_0_interrupts_s2mPacket_enable <= io_ctrl_PWDATA[4]; + end + end + 14'h00f8 : begin + if(ctrl_doWrite) begin + channels_1_ll_onSgStream <= io_ctrl_PWDATA[0]; + end + end + 14'h00c4 : begin + if(ctrl_doWrite) begin + channels_1_priority <= io_ctrl_PWDATA[1 : 0]; + channels_1_weight <= io_ctrl_PWDATA[9 : 8]; + end + end + 14'h00d0 : begin + if(ctrl_doWrite) begin + channels_1_interrupts_completion_enable <= io_ctrl_PWDATA[0]; + channels_1_interrupts_onChannelCompletion_enable <= io_ctrl_PWDATA[2]; + channels_1_interrupts_onLinkedListUpdate_enable <= io_ctrl_PWDATA[3]; + end + end + default : begin + end + endcase + end + end + + always @(posedge clk) begin + if(channels_0_bytesProbe_incr_valid) begin + channels_0_bytesProbe_value <= (_zz_channels_0_bytesProbe_value + 27'h0000001); + end + if(channels_0_descriptorStart) begin + channels_0_ll_packet <= 1'b0; + end + if(channels_0_descriptorStart) begin + channels_0_ll_requireSync <= 1'b0; + end + if(when_DmaSg_l318) begin + channels_0_ll_waitDone <= 1'b0; + if(when_DmaSg_l320) begin + channels_0_ll_head <= 1'b0; + end + end + if(channels_0_channelStart) begin + channels_0_ll_waitDone <= 1'b0; + channels_0_ll_head <= 1'b1; + end + channels_0_fifo_push_ptr <= (channels_0_fifo_push_ptr + channels_0_fifo_push_ptrIncr_value); + if(channels_0_channelStart) begin + channels_0_fifo_push_ptr <= 11'h0; + end + channels_0_fifo_pop_ptr <= (channels_0_fifo_pop_ptr + channels_0_fifo_pop_ptrIncr_value); + channels_0_fifo_pop_withOverride_backup <= channels_0_fifo_pop_withOverride_backupNext; + if(when_DmaSg_l409) begin + channels_0_fifo_pop_withOverride_valid <= 1'b0; + end + if(channels_0_fifo_pop_withOverride_load) begin + channels_0_fifo_pop_withOverride_valid <= 1'b1; + end + channels_0_fifo_pop_withOverride_exposed <= ((! channels_0_fifo_pop_withOverride_valid) ? channels_0_fifo_pop_withOverride_backupNext : _zz_channels_0_fifo_pop_withOverride_exposed); + if(channels_0_channelStart) begin + channels_0_fifo_pop_withOverride_backup <= 14'h0; + channels_0_fifo_pop_withOverride_valid <= 1'b0; + end + if(channels_0_channelStart) begin + channels_0_push_s2b_packetLock <= 1'b0; + end + if(channels_0_pop_b2m_fire) begin + channels_0_pop_b2m_flush <= 1'b0; + end + if(when_DmaSg_l505) begin + channels_0_pop_b2m_packet <= 1'b0; + end + if(when_DmaSg_l523) begin + channels_0_pop_b2m_flush <= 1'b0; + channels_0_pop_b2m_packet <= 1'b0; + end + if(channels_0_pop_b2m_packetSync) begin + channels_0_push_s2b_packetLock <= 1'b0; + if(when_DmaSg_l532) begin + if(!channels_0_push_s2b_completionOnLast) begin + if(when_DmaSg_l536) begin + channels_0_ll_requireSync <= 1'b1; + end + end + channels_0_ll_packet <= 1'b1; + end + end + if(channels_0_channelStart) begin + channels_0_pop_b2m_bytesToSkip <= 4'b0000; + channels_0_pop_b2m_flush <= 1'b0; + end + if(channels_0_descriptorStart) begin + channels_0_pop_b2m_bytesLeft <= {1'd0, channels_0_bytes}; + channels_0_pop_b2m_waitFinalRsp <= 1'b0; + end + if(channels_0_channelValid) begin + if(!channels_0_channelStop) begin + if(when_DmaSg_l575) begin + if(when_DmaSg_l593) begin + channels_0_channelStop <= 1'b1; + end + end + end + end + channels_0_fifo_pop_ptrIncr_value_regNext <= channels_0_fifo_pop_ptrIncr_value; + channels_0_fifo_push_available <= (_zz_channels_0_fifo_push_available - (channels_0_push_memory ? channels_0_fifo_push_availableDecr : channels_0_fifo_push_ptrIncr_value)); + if(channels_0_channelStart) begin + channels_0_fifo_push_ptr <= 11'h0; + channels_0_fifo_push_available <= (channels_0_fifo_words + 11'h001); + channels_0_fifo_pop_ptr <= 11'h0; + end + if(when_DmaSg_l625) begin + channels_0_bytesProbe_value <= 27'h0; + end + if(channels_1_bytesProbe_incr_valid) begin + channels_1_bytesProbe_value <= (_zz_channels_1_bytesProbe_value + 27'h0000001); + end + if(channels_1_descriptorStart) begin + channels_1_ll_packet <= 1'b0; + end + if(channels_1_descriptorStart) begin + channels_1_ll_requireSync <= 1'b0; + end + if(when_DmaSg_l318_1) begin + channels_1_ll_waitDone <= 1'b0; + if(when_DmaSg_l320_1) begin + channels_1_ll_head <= 1'b0; + end + end + if(channels_1_channelStart) begin + channels_1_ll_waitDone <= 1'b0; + channels_1_ll_head <= 1'b1; + end + channels_1_fifo_push_ptr <= (channels_1_fifo_push_ptr + channels_1_fifo_push_ptrIncr_value); + if(channels_1_channelStart) begin + channels_1_fifo_push_ptr <= 11'h0; + end + channels_1_fifo_pop_ptr <= (channels_1_fifo_pop_ptr + channels_1_fifo_pop_ptrIncr_value); + channels_1_fifo_pop_withoutOverride_exposed <= (_zz_channels_1_fifo_pop_withoutOverride_exposed - channels_1_fifo_pop_bytesDecr_value); + if(channels_1_channelStart) begin + channels_1_fifo_pop_withoutOverride_exposed <= 14'h0; + end + if(channels_1_descriptorStart) begin + channels_1_push_m2b_bytesLeft <= channels_1_bytes; + end + if(when_DmaSg_l474) begin + channels_1_pop_b2s_veryLastValid <= 1'b1; + end + if(channels_1_pop_b2s_veryLastTrigger) begin + channels_1_pop_b2s_veryLastPtr <= channels_1_fifo_push_ptrWithBase; + channels_1_pop_b2s_veryLastEndPacket <= channels_1_pop_b2s_last; + end + if(channels_1_channelStart) begin + channels_1_pop_b2s_veryLastValid <= 1'b0; + end + if(channels_1_channelValid) begin + if(!channels_1_channelStop) begin + if(when_DmaSg_l575_1) begin + if(when_DmaSg_l593_1) begin + channels_1_channelStop <= 1'b1; + end + end + end + end + channels_1_fifo_pop_ptrIncr_value_regNext <= channels_1_fifo_pop_ptrIncr_value; + channels_1_fifo_push_available <= (_zz_channels_1_fifo_push_available - (channels_1_push_memory ? channels_1_fifo_push_availableDecr : channels_1_fifo_push_ptrIncr_value)); + if(channels_1_channelStart) begin + channels_1_fifo_push_ptr <= 11'h0; + channels_1_fifo_push_available <= (channels_1_fifo_words + 11'h001); + channels_1_fifo_pop_ptr <= 11'h0; + end + if(when_DmaSg_l625_1) begin + channels_1_bytesProbe_value <= 27'h0; + end + if(when_DmaSg_l665) begin + channels_0_push_s2b_waitFirst <= 1'b0; + if(io_inputs_0_payload_last) begin + channels_0_push_s2b_packetLock <= 1'b1; + end + end + if(when_DmaSg_l681) begin + channels_0_pop_b2m_flush <= 1'b1; + end + if(when_DmaSg_l682) begin + channels_0_pop_b2m_packet <= 1'b1; + end + if(when_DmaSg_l725) begin + if(when_DmaSg_l726) begin + channels_1_pop_b2s_veryLastValid <= 1'b0; + end + end + m2b_cmd_s1_address <= m2b_cmd_s0_address; + m2b_cmd_s1_length <= m2b_cmd_s0_length; + m2b_cmd_s1_lastBurst <= m2b_cmd_s0_lastBurst; + m2b_cmd_s1_bytesLeft <= m2b_cmd_s0_bytesLeft; + if(m2b_cmd_s1_valid) begin + if(io_read_cmd_ready) begin + if(when_DmaSg_l828) begin + channels_1_push_m2b_address <= m2b_cmd_s1_addressNext; + channels_1_push_m2b_bytesLeft <= m2b_cmd_s1_byteLeftNext; + end + end + end + if(when_DmaSg_l935) begin + b2m_fsm_sel_address <= channels_0_pop_b2m_address; + b2m_fsm_sel_ptr <= channels_0_fifo_pop_ptrWithBase; + b2m_fsm_sel_ptrMask <= channels_0_fifo_words; + b2m_fsm_sel_bytePerBurst <= channels_0_pop_b2m_bytePerBurst; + b2m_fsm_sel_bytesInFifo <= channels_0_fifo_pop_bytes; + b2m_fsm_sel_flush <= channels_0_pop_b2m_flush; + b2m_fsm_sel_packet <= channels_0_pop_b2m_packet; + b2m_fsm_sel_bytesLeft <= channels_0_pop_b2m_bytesLeft[25:0]; + end + if(b2m_fsm_s0) begin + b2m_fsm_sel_bytesInBurst <= _zz_b2m_fsm_sel_bytesInBurst_3[11:0]; + end + if(b2m_fsm_s1) begin + b2m_fsm_beatCounter <= (_zz_b2m_fsm_beatCounter >>> 3'd4); + if(when_DmaSg_l996) begin + channels_0_pop_b2m_address <= b2m_fsm_addressNext; + channels_0_pop_b2m_bytesLeft <= b2m_fsm_bytesLeftNext; + if(b2m_fsm_isFinalCmd) begin + channels_0_pop_b2m_waitFinalRsp <= 1'b1; + end + if(when_DmaSg_l1001) begin + if(b2m_fsm_sel_flush) begin + channels_0_pop_b2m_flush <= 1'b1; + end + if(b2m_fsm_sel_packet) begin + channels_0_pop_b2m_packet <= 1'b1; + end + end + end + end + if(when_DmaSg_l1033) begin + b2m_fsm_sel_ptr <= ((b2m_fsm_sel_ptr & (~ b2m_fsm_sel_ptrMask)) | (_zz_b2m_fsm_sel_ptr & b2m_fsm_sel_ptrMask)); + end + if(memory_core_io_reads_1_rsp_rValidN) begin + memory_core_io_reads_1_rsp_rData_data <= memory_core_io_reads_1_rsp_payload_data; + memory_core_io_reads_1_rsp_rData_mask <= memory_core_io_reads_1_rsp_payload_mask; + memory_core_io_reads_1_rsp_rData_context <= memory_core_io_reads_1_rsp_payload_context; + end + if(b2m_fsm_aggregate_memoryPort_fire) begin + b2m_fsm_aggregate_first <= 1'b0; + end + if(when_DmaSg_l1050) begin + b2m_fsm_aggregate_first <= 1'b1; + end + b2m_fsm_cmd_maskLastTriggerReg <= b2m_fsm_cmd_maskLastTriggerComb; + b2m_fsm_cmd_maskLast <= {(4'b1111 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1110 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1101 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1100 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1011 <= b2m_fsm_cmd_maskLastTriggerComb),{(_zz_b2m_fsm_cmd_maskLast <= b2m_fsm_cmd_maskLastTriggerComb),{_zz_b2m_fsm_cmd_maskLast_1,{_zz_b2m_fsm_cmd_maskLast_2,_zz_b2m_fsm_cmd_maskLast_3}}}}}}}}; + if(io_write_cmd_fire) begin + b2m_fsm_beatCounter <= (b2m_fsm_beatCounter - 8'h01); + end + if(when_DmaSg_l1102) begin + if(_zz_when_1[0]) begin + channels_0_pop_b2m_bytesToSkip <= (b2m_fsm_aggregate_engine_io_output_usedUntil + 4'b0001); + end + end + if(when_DmaSg_l1149) begin + ll_cmd_oh_0 <= channels_0_ll_requestLl; + ll_cmd_oh_1 <= _zz_ll_arbiter_head_1; + end + if(when_DmaSg_l1148) begin + ll_cmd_ptr <= (_zz_ll_cmd_ptr[0] ? channels_0_ll_ptr : channels_1_ll_ptr); + end + if(when_DmaSg_l1148_1) begin + ll_cmd_ptrNext <= (_zz_ll_cmd_ptrNext[0] ? channels_0_ll_ptrNext : channels_1_ll_ptrNext); + end + if(when_DmaSg_l1148_2) begin + ll_cmd_bytesDone <= channels_0_bytesProbe_value; + end + if(when_DmaSg_l1148_3) begin + ll_cmd_endOfPacket <= (_zz_ll_cmd_endOfPacket[0] ? channels_0_ll_packet : channels_1_ll_packet); + end + if(when_DmaSg_l1154) begin + ll_cmd_isJustASink <= ll_arbiter_isJustASink; + end + if(when_DmaSg_l1155) begin + ll_cmd_doDescriptorStall <= ll_arbiter_doDescriptorStall; + end + if(when_DmaSg_l1156) begin + ll_cmd_onSgStream <= ll_arbiter_onSgStream; + end + if(when_DmaSg_l1160) begin + ll_cmd_oh_0 <= channels_0_ll_requestLl; + ll_cmd_oh_1 <= _zz_ll_arbiter_head_1; + if(channels_0_ll_requestLl) begin + channels_0_ll_waitDone <= 1'b1; + channels_0_ll_writeDone <= ll_arbiter_head; + channels_0_ll_justASync <= ll_arbiter_isJustASink; + channels_0_ll_packet <= 1'b0; + channels_0_ll_requireSync <= 1'b0; + if(when_DmaSg_l1169) begin + channels_0_ll_ptr <= channels_0_ll_ptrNext; + end + channels_0_ll_readDone <= ll_arbiter_isJustASink; + end + if(_zz_ll_arbiter_head_1) begin + channels_1_ll_waitDone <= 1'b1; + channels_1_ll_writeDone <= ll_arbiter_head; + channels_1_ll_justASync <= ll_arbiter_isJustASink; + channels_1_ll_packet <= 1'b0; + channels_1_ll_requireSync <= 1'b0; + if(when_DmaSg_l1169_1) begin + channels_1_ll_ptr <= channels_1_ll_ptrNext; + end + channels_1_ll_readDone <= ll_arbiter_isJustASink; + end + ll_cmd_readFired <= ll_arbiter_isJustASink; + ll_cmd_writeFired <= ll_arbiter_head; + end + if(io_sgRead_cmd_fire) begin + ll_cmd_readFired <= 1'b1; + end + if(io_sgWrite_cmd_fire) begin + ll_cmd_writeFired <= 1'b1; + end + if(io_sgRead_rsp_fire) begin + if(when_DmaSg_l1248) begin + if(ll_readRsp_oh_1) begin + channels_1_push_m2b_address <= io_sgRead_rsp_payload_fragment_data[95 : 64]; + end + end + if(when_DmaSg_l1248_1) begin + if(ll_readRsp_oh_0) begin + channels_0_pop_b2m_address <= io_sgRead_rsp_payload_fragment_data[31 : 0]; + end + end + if(when_DmaSg_l1248_2) begin + if(ll_readRsp_oh_0) begin + channels_0_ll_ptrNext <= io_sgRead_rsp_payload_fragment_data[95 : 64]; + end + if(ll_readRsp_oh_1) begin + channels_1_ll_ptrNext <= io_sgRead_rsp_payload_fragment_data[95 : 64]; + end + end + if(when_DmaSg_l1248_3) begin + if(ll_readRsp_oh_0) begin + channels_0_bytes <= io_sgRead_rsp_payload_fragment_data[57 : 32]; + end + if(ll_readRsp_oh_1) begin + channels_1_bytes <= io_sgRead_rsp_payload_fragment_data[57 : 32]; + end + end + if(when_DmaSg_l1248_4) begin + if(ll_readRsp_oh_0) begin + channels_0_ll_controlNoCompletion <= io_sgRead_rsp_payload_fragment_data[63]; + end + if(ll_readRsp_oh_1) begin + channels_1_ll_controlNoCompletion <= io_sgRead_rsp_payload_fragment_data[63]; + end + end + if(when_DmaSg_l1248_5) begin + if(ll_readRsp_oh_1) begin + channels_1_pop_b2s_last <= io_sgRead_rsp_payload_fragment_data[62]; + end + end + if(when_DmaSg_l1248_6) begin + if(ll_readRsp_oh_0) begin + channels_0_ll_gotDescriptorStall <= io_sgRead_rsp_payload_fragment_data[31]; + end + if(ll_readRsp_oh_1) begin + channels_1_ll_gotDescriptorStall <= io_sgRead_rsp_payload_fragment_data[31]; + end + end + if(when_DmaSg_l1271) begin + if(ll_readRsp_oh_0) begin + channels_0_ll_readDone <= 1'b1; + end + if(ll_readRsp_oh_1) begin + channels_1_ll_readDone <= 1'b1; + end + end + end + if(io_sgWrite_rsp_fire) begin + if(ll_writeRsp_oh_0) begin + channels_0_ll_writeDone <= 1'b1; + end + if(ll_writeRsp_oh_1) begin + channels_1_ll_writeDone <= 1'b1; + end + end + case(io_ctrl_PADDR) + 14'h000c : begin + if(ctrl_doWrite) begin + channels_0_push_memory <= io_ctrl_PWDATA[12]; + channels_0_push_s2b_completionOnLast <= io_ctrl_PWDATA[13]; + channels_0_push_s2b_waitFirst <= io_ctrl_PWDATA[14]; + end + end + 14'h001c : begin + if(ctrl_doWrite) begin + channels_0_pop_memory <= io_ctrl_PWDATA[12]; + end + end + 14'h002c : begin + if(ctrl_doWrite) begin + channels_0_channelStop <= io_ctrl_PWDATA[2]; + end + end + 14'h0020 : begin + if(ctrl_doWrite) begin + channels_0_bytes <= io_ctrl_PWDATA[25 : 0]; + end + end + 14'h008c : begin + if(ctrl_doWrite) begin + channels_1_push_memory <= io_ctrl_PWDATA[12]; + end + end + 14'h0098 : begin + if(ctrl_doWrite) begin + channels_1_pop_b2s_sinkId <= io_ctrl_PWDATA[19 : 16]; + end + end + 14'h009c : begin + if(ctrl_doWrite) begin + channels_1_pop_memory <= io_ctrl_PWDATA[12]; + channels_1_pop_b2s_last <= io_ctrl_PWDATA[13]; + end + end + 14'h00ac : begin + if(ctrl_doWrite) begin + channels_1_channelStop <= io_ctrl_PWDATA[2]; + end + end + 14'h00a0 : begin + if(ctrl_doWrite) begin + channels_1_bytes <= io_ctrl_PWDATA[25 : 0]; + end + end + default : begin + end + endcase + if(when_Apb3SlaveFactory_l81) begin + if(ctrl_doWrite) begin + channels_0_pop_b2m_address[31 : 0] <= io_ctrl_PWDATA[31 : 0]; + end + end + if(when_Apb3SlaveFactory_l81_1) begin + if(ctrl_doWrite) begin + channels_0_ll_ptrNext[31 : 0] <= io_ctrl_PWDATA[31 : 0]; + end + end + if(when_Apb3SlaveFactory_l81_2) begin + if(ctrl_doWrite) begin + channels_1_push_m2b_address[31 : 0] <= io_ctrl_PWDATA[31 : 0]; + end + end + if(when_Apb3SlaveFactory_l81_3) begin + if(ctrl_doWrite) begin + channels_1_ll_ptrNext[31 : 0] <= io_ctrl_PWDATA[31 : 0]; + end + end + end + + +endmodule + +module EfxDMA_StreamArbiter_1 ( + input wire io_inputs_0_valid, + output wire io_inputs_0_ready, + input wire io_inputs_0_payload_last, + input wire [0:0] io_inputs_0_payload_fragment_source, + input wire [0:0] io_inputs_0_payload_fragment_opcode, + input wire [31:0] io_inputs_0_payload_fragment_address, + input wire [11:0] io_inputs_0_payload_fragment_length, + input wire [127:0] io_inputs_0_payload_fragment_data, + input wire [15:0] io_inputs_0_payload_fragment_mask, + input wire [12:0] io_inputs_0_payload_fragment_context, + input wire io_inputs_1_valid, + output wire io_inputs_1_ready, + input wire io_inputs_1_payload_last, + input wire [0:0] io_inputs_1_payload_fragment_source, + input wire [0:0] io_inputs_1_payload_fragment_opcode, + input wire [31:0] io_inputs_1_payload_fragment_address, + input wire [11:0] io_inputs_1_payload_fragment_length, + input wire [127:0] io_inputs_1_payload_fragment_data, + input wire [15:0] io_inputs_1_payload_fragment_mask, + input wire [12:0] io_inputs_1_payload_fragment_context, + output wire io_output_valid, + input wire io_output_ready, + output wire io_output_payload_last, + output wire [0:0] io_output_payload_fragment_source, + output wire [0:0] io_output_payload_fragment_opcode, + output wire [31:0] io_output_payload_fragment_address, + output wire [11:0] io_output_payload_fragment_length, + output wire [127:0] io_output_payload_fragment_data, + output wire [15:0] io_output_payload_fragment_mask, + output wire [12:0] io_output_payload_fragment_context, + output wire [0:0] io_chosen, + output wire [1:0] io_chosenOH, + input wire clk, + input wire reset +); + + wire [3:0] _zz__zz_maskProposal_0_2; + wire [3:0] _zz__zz_maskProposal_0_2_1; + wire [1:0] _zz__zz_maskProposal_0_2_2; + reg locked; + wire maskProposal_0; + wire maskProposal_1; + reg maskLocked_0; + reg maskLocked_1; + wire maskRouted_0; + wire maskRouted_1; + wire [1:0] _zz_maskProposal_0; + wire [3:0] _zz_maskProposal_0_1; + wire [3:0] _zz_maskProposal_0_2; + wire [1:0] _zz_maskProposal_0_3; + wire io_output_fire; + wire when_Stream_l683; + wire _zz_io_chosen; + + assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); + assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; + assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; + assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); + assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); + assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; + assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; + assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); + assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); + assign maskProposal_0 = _zz_maskProposal_0_3[0]; + assign maskProposal_1 = _zz_maskProposal_0_3[1]; + assign io_output_fire = (io_output_valid && io_output_ready); + assign when_Stream_l683 = (io_output_fire && io_output_payload_last); + assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); + assign io_output_payload_last = (maskRouted_0 ? io_inputs_0_payload_last : io_inputs_1_payload_last); + assign io_output_payload_fragment_source = (maskRouted_0 ? io_inputs_0_payload_fragment_source : io_inputs_1_payload_fragment_source); + assign io_output_payload_fragment_opcode = (maskRouted_0 ? io_inputs_0_payload_fragment_opcode : io_inputs_1_payload_fragment_opcode); + assign io_output_payload_fragment_address = (maskRouted_0 ? io_inputs_0_payload_fragment_address : io_inputs_1_payload_fragment_address); + assign io_output_payload_fragment_length = (maskRouted_0 ? io_inputs_0_payload_fragment_length : io_inputs_1_payload_fragment_length); + assign io_output_payload_fragment_data = (maskRouted_0 ? io_inputs_0_payload_fragment_data : io_inputs_1_payload_fragment_data); + assign io_output_payload_fragment_mask = (maskRouted_0 ? io_inputs_0_payload_fragment_mask : io_inputs_1_payload_fragment_mask); + assign io_output_payload_fragment_context = (maskRouted_0 ? io_inputs_0_payload_fragment_context : io_inputs_1_payload_fragment_context); + assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); + assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); + assign io_chosenOH = {maskRouted_1,maskRouted_0}; + assign _zz_io_chosen = io_chosenOH[1]; + assign io_chosen = _zz_io_chosen; + always @(posedge clk) begin + if(reset) begin + locked <= 1'b0; + maskLocked_0 <= 1'b0; + maskLocked_1 <= 1'b1; + end else begin + if(io_output_valid) begin + maskLocked_0 <= maskRouted_0; + maskLocked_1 <= maskRouted_1; + end + if(io_output_valid) begin + locked <= 1'b1; + end + if(when_Stream_l683) begin + locked <= 1'b0; + end + end + end + + +endmodule + +module EfxDMA_StreamArbiter ( + input wire io_inputs_0_valid, + output wire io_inputs_0_ready, + input wire io_inputs_0_payload_last, + input wire [0:0] io_inputs_0_payload_fragment_source, + input wire [0:0] io_inputs_0_payload_fragment_opcode, + input wire [31:0] io_inputs_0_payload_fragment_address, + input wire [11:0] io_inputs_0_payload_fragment_length, + input wire [20:0] io_inputs_0_payload_fragment_context, + input wire io_inputs_1_valid, + output wire io_inputs_1_ready, + input wire io_inputs_1_payload_last, + input wire [0:0] io_inputs_1_payload_fragment_source, + input wire [0:0] io_inputs_1_payload_fragment_opcode, + input wire [31:0] io_inputs_1_payload_fragment_address, + input wire [11:0] io_inputs_1_payload_fragment_length, + input wire [20:0] io_inputs_1_payload_fragment_context, + output wire io_output_valid, + input wire io_output_ready, + output wire io_output_payload_last, + output wire [0:0] io_output_payload_fragment_source, + output wire [0:0] io_output_payload_fragment_opcode, + output wire [31:0] io_output_payload_fragment_address, + output wire [11:0] io_output_payload_fragment_length, + output wire [20:0] io_output_payload_fragment_context, + output wire [0:0] io_chosen, + output wire [1:0] io_chosenOH, + input wire clk, + input wire reset +); + + wire [3:0] _zz__zz_maskProposal_0_2; + wire [3:0] _zz__zz_maskProposal_0_2_1; + wire [1:0] _zz__zz_maskProposal_0_2_2; + reg locked; + wire maskProposal_0; + wire maskProposal_1; + reg maskLocked_0; + reg maskLocked_1; + wire maskRouted_0; + wire maskRouted_1; + wire [1:0] _zz_maskProposal_0; + wire [3:0] _zz_maskProposal_0_1; + wire [3:0] _zz_maskProposal_0_2; + wire [1:0] _zz_maskProposal_0_3; + wire io_output_fire; + wire when_Stream_l683; + wire _zz_io_chosen; + + assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); + assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; + assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; + assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); + assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); + assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; + assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; + assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); + assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); + assign maskProposal_0 = _zz_maskProposal_0_3[0]; + assign maskProposal_1 = _zz_maskProposal_0_3[1]; + assign io_output_fire = (io_output_valid && io_output_ready); + assign when_Stream_l683 = (io_output_fire && io_output_payload_last); + assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); + assign io_output_payload_last = (maskRouted_0 ? io_inputs_0_payload_last : io_inputs_1_payload_last); + assign io_output_payload_fragment_source = (maskRouted_0 ? io_inputs_0_payload_fragment_source : io_inputs_1_payload_fragment_source); + assign io_output_payload_fragment_opcode = (maskRouted_0 ? io_inputs_0_payload_fragment_opcode : io_inputs_1_payload_fragment_opcode); + assign io_output_payload_fragment_address = (maskRouted_0 ? io_inputs_0_payload_fragment_address : io_inputs_1_payload_fragment_address); + assign io_output_payload_fragment_length = (maskRouted_0 ? io_inputs_0_payload_fragment_length : io_inputs_1_payload_fragment_length); + assign io_output_payload_fragment_context = (maskRouted_0 ? io_inputs_0_payload_fragment_context : io_inputs_1_payload_fragment_context); + assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); + assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); + assign io_chosenOH = {maskRouted_1,maskRouted_0}; + assign _zz_io_chosen = io_chosenOH[1]; + assign io_chosen = _zz_io_chosen; + always @(posedge clk) begin + if(reset) begin + locked <= 1'b0; + maskLocked_0 <= 1'b0; + maskLocked_1 <= 1'b1; + end else begin + if(io_output_valid) begin + maskLocked_0 <= maskRouted_0; + maskLocked_1 <= maskRouted_1; + end + if(io_output_valid) begin + locked <= 1'b1; + end + if(when_Stream_l683) begin + locked <= 1'b0; + end + end + end + + +endmodule + +module EfxDMA_BufferCC_5 ( + input wire [4:0] io_dataIn, + output wire [4:0] io_dataOut, + input wire dat1_o_clk, + input wire dat1_o_reset +); + + (* async_reg = "true" *) reg [4:0] buffers_0; + (* async_reg = "true" *) reg [4:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge dat1_o_clk) begin + if(dat1_o_reset) begin + buffers_0 <= 5'h0; + buffers_1 <= 5'h0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +//EfxDMA_BufferCC_4 replaced by EfxDMA_BufferCC_3 + +module EfxDMA_BufferCC_3 ( + input wire [4:0] io_dataIn, + output wire [4:0] io_dataOut, + input wire clk, + input wire reset +); + + (* async_reg = "true" *) reg [4:0] buffers_0; + (* async_reg = "true" *) reg [4:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge clk) begin + if(reset) begin + buffers_0 <= 5'h0; + buffers_1 <= 5'h0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module EfxDMA_BufferCC_2 ( + input wire [4:0] io_dataIn, + output wire [4:0] io_dataOut, + input wire dat0_i_clk, + input wire dat0_i_reset +); + + (* async_reg = "true" *) reg [4:0] buffers_0; + (* async_reg = "true" *) reg [4:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge dat0_i_clk) begin + if(dat0_i_reset) begin + buffers_0 <= 5'h0; + buffers_1 <= 5'h0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module EfxDMA_BmbContextRemover_1 ( + input wire io_input_cmd_valid, + output reg io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [127:0] io_input_cmd_payload_fragment_data, + input wire [15:0] io_input_cmd_payload_fragment_mask, + input wire [13:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [13:0] io_input_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + output wire [127:0] io_output_cmd_payload_fragment_data, + output wire [15:0] io_output_cmd_payload_fragment_mask, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire clk, + input wire reset +); + + reg fifoFork_thrown_translated_fifo_io_pop_ready; + wire fifoFork_thrown_translated_fifo_io_push_ready; + wire fifoFork_thrown_translated_fifo_io_pop_valid; + wire [13:0] fifoFork_thrown_translated_fifo_io_pop_payload_context; + wire [2:0] fifoFork_thrown_translated_fifo_io_occupancy; + wire [2:0] fifoFork_thrown_translated_fifo_io_availability; + wire fifoFork_valid; + reg fifoFork_ready; + wire fifoFork_payload_last; + wire [0:0] fifoFork_payload_fragment_opcode; + wire [31:0] fifoFork_payload_fragment_address; + wire [11:0] fifoFork_payload_fragment_length; + wire [127:0] fifoFork_payload_fragment_data; + wire [15:0] fifoFork_payload_fragment_mask; + wire [13:0] fifoFork_payload_fragment_context; + wire cmdFork_valid; + wire cmdFork_ready; + wire cmdFork_payload_last; + wire [0:0] cmdFork_payload_fragment_opcode; + wire [31:0] cmdFork_payload_fragment_address; + wire [11:0] cmdFork_payload_fragment_length; + wire [127:0] cmdFork_payload_fragment_data; + wire [15:0] cmdFork_payload_fragment_mask; + wire [13:0] cmdFork_payload_fragment_context; + reg io_input_cmd_fork2_logic_linkEnable_0; + reg io_input_cmd_fork2_logic_linkEnable_1; + wire when_Stream_l1063; + wire when_Stream_l1063_1; + wire fifoFork_fire; + wire cmdFork_fire; + wire [13:0] pushCtx_context; + reg fifoFork_payload_first; + wire when_Stream_l445; + reg fifoFork_thrown_valid; + wire fifoFork_thrown_ready; + wire fifoFork_thrown_payload_last; + wire [0:0] fifoFork_thrown_payload_fragment_opcode; + wire [31:0] fifoFork_thrown_payload_fragment_address; + wire [11:0] fifoFork_thrown_payload_fragment_length; + wire [127:0] fifoFork_thrown_payload_fragment_data; + wire [15:0] fifoFork_thrown_payload_fragment_mask; + wire [13:0] fifoFork_thrown_payload_fragment_context; + wire fifoFork_thrown_translated_valid; + wire fifoFork_thrown_translated_ready; + wire [13:0] fifoFork_thrown_translated_payload_context; + wire popCtx_valid; + wire popCtx_ready; + wire [13:0] popCtx_payload_context; + reg fifoFork_thrown_translated_fifo_io_pop_rValid; + reg [13:0] fifoFork_thrown_translated_fifo_io_pop_rData_context; + wire when_Stream_l375; + wire _zz_io_input_rsp_valid; + + EfxDMA_StreamFifo_1 fifoFork_thrown_translated_fifo ( + .io_push_valid (fifoFork_thrown_translated_valid ), //i + .io_push_ready (fifoFork_thrown_translated_fifo_io_push_ready ), //o + .io_push_payload_context (fifoFork_thrown_translated_payload_context[13:0] ), //i + .io_pop_valid (fifoFork_thrown_translated_fifo_io_pop_valid ), //o + .io_pop_ready (fifoFork_thrown_translated_fifo_io_pop_ready ), //i + .io_pop_payload_context (fifoFork_thrown_translated_fifo_io_pop_payload_context[13:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (fifoFork_thrown_translated_fifo_io_occupancy[2:0] ), //o + .io_availability (fifoFork_thrown_translated_fifo_io_availability[2:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + io_input_cmd_ready = 1'b1; + if(when_Stream_l1063) begin + io_input_cmd_ready = 1'b0; + end + if(when_Stream_l1063_1) begin + io_input_cmd_ready = 1'b0; + end + end + + assign when_Stream_l1063 = ((! fifoFork_ready) && io_input_cmd_fork2_logic_linkEnable_0); + assign when_Stream_l1063_1 = ((! cmdFork_ready) && io_input_cmd_fork2_logic_linkEnable_1); + assign fifoFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_0); + assign fifoFork_payload_last = io_input_cmd_payload_last; + assign fifoFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign fifoFork_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign fifoFork_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign fifoFork_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign fifoFork_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign fifoFork_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign fifoFork_fire = (fifoFork_valid && fifoFork_ready); + assign cmdFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_1); + assign cmdFork_payload_last = io_input_cmd_payload_last; + assign cmdFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign cmdFork_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign cmdFork_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign cmdFork_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign cmdFork_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign cmdFork_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign cmdFork_fire = (cmdFork_valid && cmdFork_ready); + assign io_output_cmd_valid = cmdFork_valid; + assign cmdFork_ready = io_output_cmd_ready; + assign io_output_cmd_payload_last = cmdFork_payload_last; + assign io_output_cmd_payload_fragment_opcode = cmdFork_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = cmdFork_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = cmdFork_payload_fragment_length; + assign io_output_cmd_payload_fragment_data = cmdFork_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = cmdFork_payload_fragment_mask; + assign pushCtx_context = fifoFork_payload_fragment_context; + assign when_Stream_l445 = (! fifoFork_payload_first); + always @(*) begin + fifoFork_thrown_valid = fifoFork_valid; + if(when_Stream_l445) begin + fifoFork_thrown_valid = 1'b0; + end + end + + always @(*) begin + fifoFork_ready = fifoFork_thrown_ready; + if(when_Stream_l445) begin + fifoFork_ready = 1'b1; + end + end + + assign fifoFork_thrown_payload_last = fifoFork_payload_last; + assign fifoFork_thrown_payload_fragment_opcode = fifoFork_payload_fragment_opcode; + assign fifoFork_thrown_payload_fragment_address = fifoFork_payload_fragment_address; + assign fifoFork_thrown_payload_fragment_length = fifoFork_payload_fragment_length; + assign fifoFork_thrown_payload_fragment_data = fifoFork_payload_fragment_data; + assign fifoFork_thrown_payload_fragment_mask = fifoFork_payload_fragment_mask; + assign fifoFork_thrown_payload_fragment_context = fifoFork_payload_fragment_context; + assign fifoFork_thrown_translated_valid = fifoFork_thrown_valid; + assign fifoFork_thrown_ready = fifoFork_thrown_translated_ready; + assign fifoFork_thrown_translated_payload_context = pushCtx_context; + assign fifoFork_thrown_translated_ready = fifoFork_thrown_translated_fifo_io_push_ready; + always @(*) begin + fifoFork_thrown_translated_fifo_io_pop_ready = popCtx_ready; + if(when_Stream_l375) begin + fifoFork_thrown_translated_fifo_io_pop_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! popCtx_valid); + assign popCtx_valid = fifoFork_thrown_translated_fifo_io_pop_rValid; + assign popCtx_payload_context = fifoFork_thrown_translated_fifo_io_pop_rData_context; + assign popCtx_ready = ((io_output_rsp_valid && io_output_rsp_payload_last) && io_input_rsp_ready); + assign _zz_io_input_rsp_valid = (! (! popCtx_valid)); + assign io_output_rsp_ready = (io_input_rsp_ready && _zz_io_input_rsp_valid); + assign io_input_rsp_valid = (io_output_rsp_valid && _zz_io_input_rsp_valid); + assign io_input_rsp_payload_last = io_output_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_context = popCtx_payload_context; + always @(posedge clk) begin + if(reset) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; + fifoFork_payload_first <= 1'b1; + fifoFork_thrown_translated_fifo_io_pop_rValid <= 1'b0; + end else begin + if(fifoFork_fire) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdFork_fire) begin + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_cmd_ready) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; + end + if(fifoFork_fire) begin + fifoFork_payload_first <= fifoFork_payload_last; + end + if(fifoFork_thrown_translated_fifo_io_pop_ready) begin + fifoFork_thrown_translated_fifo_io_pop_rValid <= fifoFork_thrown_translated_fifo_io_pop_valid; + end + end + end + + always @(posedge clk) begin + if(fifoFork_thrown_translated_fifo_io_pop_ready) begin + fifoFork_thrown_translated_fifo_io_pop_rData_context <= fifoFork_thrown_translated_fifo_io_pop_payload_context; + end + end + + +endmodule + +module EfxDMA_BmbContextRemover ( + input wire io_input_cmd_valid, + output reg io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [21:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [127:0] io_input_rsp_payload_fragment_data, + output wire [21:0] io_input_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [127:0] io_output_rsp_payload_fragment_data, + input wire clk, + input wire reset +); + + reg fifoFork_thrown_translated_fifo_io_pop_ready; + wire fifoFork_thrown_translated_fifo_io_push_ready; + wire fifoFork_thrown_translated_fifo_io_pop_valid; + wire [21:0] fifoFork_thrown_translated_fifo_io_pop_payload_context; + wire [2:0] fifoFork_thrown_translated_fifo_io_occupancy; + wire [2:0] fifoFork_thrown_translated_fifo_io_availability; + wire fifoFork_valid; + reg fifoFork_ready; + wire fifoFork_payload_last; + wire [0:0] fifoFork_payload_fragment_opcode; + wire [31:0] fifoFork_payload_fragment_address; + wire [11:0] fifoFork_payload_fragment_length; + wire [21:0] fifoFork_payload_fragment_context; + wire cmdFork_valid; + wire cmdFork_ready; + wire cmdFork_payload_last; + wire [0:0] cmdFork_payload_fragment_opcode; + wire [31:0] cmdFork_payload_fragment_address; + wire [11:0] cmdFork_payload_fragment_length; + wire [21:0] cmdFork_payload_fragment_context; + reg io_input_cmd_fork2_logic_linkEnable_0; + reg io_input_cmd_fork2_logic_linkEnable_1; + wire when_Stream_l1063; + wire when_Stream_l1063_1; + wire fifoFork_fire; + wire cmdFork_fire; + wire [21:0] pushCtx_context; + reg fifoFork_payload_first; + wire when_Stream_l445; + reg fifoFork_thrown_valid; + wire fifoFork_thrown_ready; + wire fifoFork_thrown_payload_last; + wire [0:0] fifoFork_thrown_payload_fragment_opcode; + wire [31:0] fifoFork_thrown_payload_fragment_address; + wire [11:0] fifoFork_thrown_payload_fragment_length; + wire [21:0] fifoFork_thrown_payload_fragment_context; + wire fifoFork_thrown_translated_valid; + wire fifoFork_thrown_translated_ready; + wire [21:0] fifoFork_thrown_translated_payload_context; + wire popCtx_valid; + wire popCtx_ready; + wire [21:0] popCtx_payload_context; + reg fifoFork_thrown_translated_fifo_io_pop_rValid; + reg [21:0] fifoFork_thrown_translated_fifo_io_pop_rData_context; + wire when_Stream_l375; + wire _zz_io_input_rsp_valid; + + EfxDMA_StreamFifo fifoFork_thrown_translated_fifo ( + .io_push_valid (fifoFork_thrown_translated_valid ), //i + .io_push_ready (fifoFork_thrown_translated_fifo_io_push_ready ), //o + .io_push_payload_context (fifoFork_thrown_translated_payload_context[21:0] ), //i + .io_pop_valid (fifoFork_thrown_translated_fifo_io_pop_valid ), //o + .io_pop_ready (fifoFork_thrown_translated_fifo_io_pop_ready ), //i + .io_pop_payload_context (fifoFork_thrown_translated_fifo_io_pop_payload_context[21:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (fifoFork_thrown_translated_fifo_io_occupancy[2:0] ), //o + .io_availability (fifoFork_thrown_translated_fifo_io_availability[2:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + io_input_cmd_ready = 1'b1; + if(when_Stream_l1063) begin + io_input_cmd_ready = 1'b0; + end + if(when_Stream_l1063_1) begin + io_input_cmd_ready = 1'b0; + end + end + + assign when_Stream_l1063 = ((! fifoFork_ready) && io_input_cmd_fork2_logic_linkEnable_0); + assign when_Stream_l1063_1 = ((! cmdFork_ready) && io_input_cmd_fork2_logic_linkEnable_1); + assign fifoFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_0); + assign fifoFork_payload_last = io_input_cmd_payload_last; + assign fifoFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign fifoFork_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign fifoFork_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign fifoFork_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign fifoFork_fire = (fifoFork_valid && fifoFork_ready); + assign cmdFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_1); + assign cmdFork_payload_last = io_input_cmd_payload_last; + assign cmdFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign cmdFork_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign cmdFork_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign cmdFork_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign cmdFork_fire = (cmdFork_valid && cmdFork_ready); + assign io_output_cmd_valid = cmdFork_valid; + assign cmdFork_ready = io_output_cmd_ready; + assign io_output_cmd_payload_last = cmdFork_payload_last; + assign io_output_cmd_payload_fragment_opcode = cmdFork_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = cmdFork_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = cmdFork_payload_fragment_length; + assign pushCtx_context = fifoFork_payload_fragment_context; + assign when_Stream_l445 = (! fifoFork_payload_first); + always @(*) begin + fifoFork_thrown_valid = fifoFork_valid; + if(when_Stream_l445) begin + fifoFork_thrown_valid = 1'b0; + end + end + + always @(*) begin + fifoFork_ready = fifoFork_thrown_ready; + if(when_Stream_l445) begin + fifoFork_ready = 1'b1; + end + end + + assign fifoFork_thrown_payload_last = fifoFork_payload_last; + assign fifoFork_thrown_payload_fragment_opcode = fifoFork_payload_fragment_opcode; + assign fifoFork_thrown_payload_fragment_address = fifoFork_payload_fragment_address; + assign fifoFork_thrown_payload_fragment_length = fifoFork_payload_fragment_length; + assign fifoFork_thrown_payload_fragment_context = fifoFork_payload_fragment_context; + assign fifoFork_thrown_translated_valid = fifoFork_thrown_valid; + assign fifoFork_thrown_ready = fifoFork_thrown_translated_ready; + assign fifoFork_thrown_translated_payload_context = pushCtx_context; + assign fifoFork_thrown_translated_ready = fifoFork_thrown_translated_fifo_io_push_ready; + always @(*) begin + fifoFork_thrown_translated_fifo_io_pop_ready = popCtx_ready; + if(when_Stream_l375) begin + fifoFork_thrown_translated_fifo_io_pop_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! popCtx_valid); + assign popCtx_valid = fifoFork_thrown_translated_fifo_io_pop_rValid; + assign popCtx_payload_context = fifoFork_thrown_translated_fifo_io_pop_rData_context; + assign popCtx_ready = ((io_output_rsp_valid && io_output_rsp_payload_last) && io_input_rsp_ready); + assign _zz_io_input_rsp_valid = (! (! popCtx_valid)); + assign io_output_rsp_ready = (io_input_rsp_ready && _zz_io_input_rsp_valid); + assign io_input_rsp_valid = (io_output_rsp_valid && _zz_io_input_rsp_valid); + assign io_input_rsp_payload_last = io_output_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = popCtx_payload_context; + always @(posedge clk) begin + if(reset) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; + fifoFork_payload_first <= 1'b1; + fifoFork_thrown_translated_fifo_io_pop_rValid <= 1'b0; + end else begin + if(fifoFork_fire) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdFork_fire) begin + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_cmd_ready) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; + end + if(fifoFork_fire) begin + fifoFork_payload_first <= fifoFork_payload_last; + end + if(fifoFork_thrown_translated_fifo_io_pop_ready) begin + fifoFork_thrown_translated_fifo_io_pop_rValid <= fifoFork_thrown_translated_fifo_io_pop_valid; + end + end + end + + always @(posedge clk) begin + if(fifoFork_thrown_translated_fifo_io_pop_ready) begin + fifoFork_thrown_translated_fifo_io_pop_rData_context <= fifoFork_thrown_translated_fifo_io_pop_payload_context; + end + end + + +endmodule + +module EfxDMA_FlowCCUnsafeByToggle_1 ( + input wire io_input_valid, + input wire [31:0] io_input_payload_PRDATA, + input wire io_input_payload_PSLVERROR, + output wire io_output_valid, + output wire [31:0] io_output_payload_PRDATA, + output wire io_output_payload_PSLVERROR, + input wire clk, + input wire reset, + input wire ctrl_clk, + input wire ctrl_reset +); + + wire inputArea_target_buffercc_io_dataOut; + reg inputArea_target; + reg [31:0] inputArea_data_PRDATA; + reg inputArea_data_PSLVERROR; + wire outputArea_target; + reg outputArea_hit; + wire outputArea_flow_valid; + wire [31:0] outputArea_flow_payload_PRDATA; + wire outputArea_flow_payload_PSLVERROR; + reg outputArea_flow_m2sPipe_valid; + (* async_reg = "true" *) reg [31:0] outputArea_flow_m2sPipe_payload_PRDATA; + (* async_reg = "true" *) reg outputArea_flow_m2sPipe_payload_PSLVERROR; + + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_1 inputArea_target_buffercc ( + .io_dataIn (inputArea_target ), //i + .io_dataOut (inputArea_target_buffercc_io_dataOut), //o + .ctrl_clk (ctrl_clk ), //i + .ctrl_reset (ctrl_reset ) //i + ); + assign outputArea_target = inputArea_target_buffercc_io_dataOut; + assign outputArea_flow_valid = (outputArea_target != outputArea_hit); + assign outputArea_flow_payload_PRDATA = inputArea_data_PRDATA; + assign outputArea_flow_payload_PSLVERROR = inputArea_data_PSLVERROR; + assign io_output_valid = outputArea_flow_m2sPipe_valid; + assign io_output_payload_PRDATA = outputArea_flow_m2sPipe_payload_PRDATA; + assign io_output_payload_PSLVERROR = outputArea_flow_m2sPipe_payload_PSLVERROR; + always @(posedge clk) begin + if(reset) begin + inputArea_target <= 1'b0; + end else begin + if(io_input_valid) begin + inputArea_target <= (! inputArea_target); + end + end + end + + always @(posedge clk) begin + if(io_input_valid) begin + inputArea_data_PRDATA <= io_input_payload_PRDATA; + inputArea_data_PSLVERROR <= io_input_payload_PSLVERROR; + end + end + + always @(posedge ctrl_clk) begin + if(ctrl_reset) begin + outputArea_flow_m2sPipe_valid <= 1'b0; + outputArea_hit <= 1'b0; + end else begin + outputArea_hit <= outputArea_target; + outputArea_flow_m2sPipe_valid <= outputArea_flow_valid; + end + end + + always @(posedge ctrl_clk) begin + if(outputArea_flow_valid) begin + outputArea_flow_m2sPipe_payload_PRDATA <= outputArea_flow_payload_PRDATA; + outputArea_flow_m2sPipe_payload_PSLVERROR <= outputArea_flow_payload_PSLVERROR; + end + end + + +endmodule + +module EfxDMA_FlowCCUnsafeByToggle ( + input wire io_input_valid, + input wire [13:0] io_input_payload_PADDR, + input wire io_input_payload_PWRITE, + input wire [31:0] io_input_payload_PWDATA, + output wire io_output_valid, + output wire [13:0] io_output_payload_PADDR, + output wire io_output_payload_PWRITE, + output wire [31:0] io_output_payload_PWDATA, + input wire ctrl_clk, + input wire ctrl_reset, + input wire clk, + input wire reset +); + + wire inputArea_target_buffercc_io_dataOut; + reg inputArea_target; + reg [13:0] inputArea_data_PADDR; + reg inputArea_data_PWRITE; + reg [31:0] inputArea_data_PWDATA; + wire outputArea_target; + reg outputArea_hit; + wire outputArea_flow_valid; + wire [13:0] outputArea_flow_payload_PADDR; + wire outputArea_flow_payload_PWRITE; + wire [31:0] outputArea_flow_payload_PWDATA; + + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC inputArea_target_buffercc ( + .io_dataIn (inputArea_target ), //i + .io_dataOut (inputArea_target_buffercc_io_dataOut), //o + .clk (clk ), //i + .reset (reset ) //i + ); + assign outputArea_target = inputArea_target_buffercc_io_dataOut; + assign outputArea_flow_valid = (outputArea_target != outputArea_hit); + assign outputArea_flow_payload_PADDR = inputArea_data_PADDR; + assign outputArea_flow_payload_PWRITE = inputArea_data_PWRITE; + assign outputArea_flow_payload_PWDATA = inputArea_data_PWDATA; + assign io_output_valid = outputArea_flow_valid; + assign io_output_payload_PADDR = outputArea_flow_payload_PADDR; + assign io_output_payload_PWRITE = outputArea_flow_payload_PWRITE; + assign io_output_payload_PWDATA = outputArea_flow_payload_PWDATA; + always @(posedge ctrl_clk) begin + if(ctrl_reset) begin + inputArea_target <= 1'b0; + end else begin + if(io_input_valid) begin + inputArea_target <= (! inputArea_target); + end + end + end + + always @(posedge ctrl_clk) begin + if(io_input_valid) begin + inputArea_data_PADDR <= io_input_payload_PADDR; + inputArea_data_PWRITE <= io_input_payload_PWRITE; + inputArea_data_PWDATA <= io_input_payload_PWDATA; + end + end + + always @(posedge clk) begin + if(reset) begin + outputArea_hit <= 1'b0; + end else begin + outputArea_hit <= outputArea_target; + end + end + + +endmodule + +module EfxDMA_Aggregator ( + input wire io_input_valid, + output reg io_input_ready, + input wire [127:0] io_input_payload_data, + input wire [15:0] io_input_payload_mask, + output reg [127:0] io_output_data, + output reg [15:0] io_output_mask, + input wire io_output_enough, + input wire io_output_consume, + output wire io_output_consumed, + input wire [3:0] io_output_lastByteUsed, + output wire [3:0] io_output_usedUntil, + input wire io_flush, + input wire [3:0] io_offset, + input wire [11:0] io_burstLength, + input wire clk, + input wire reset +); + + reg [0:0] _zz_s0_countOnesLogic_0_1; + wire [0:0] _zz_s0_countOnesLogic_0_2; + reg [1:0] _zz_s0_countOnesLogic_1_1; + wire [1:0] _zz_s0_countOnesLogic_1_2; + reg [1:0] _zz_s0_countOnesLogic_2_1; + wire [2:0] _zz_s0_countOnesLogic_2_2; + reg [2:0] _zz_s0_countOnesLogic_3_9; + wire [2:0] _zz_s0_countOnesLogic_3_10; + reg [2:0] _zz_s0_countOnesLogic_3_11; + wire [2:0] _zz_s0_countOnesLogic_3_12; + wire [0:0] _zz_s0_countOnesLogic_3_13; + reg [2:0] _zz_s0_countOnesLogic_4_9; + wire [2:0] _zz_s0_countOnesLogic_4_10; + reg [2:0] _zz_s0_countOnesLogic_4_11; + wire [2:0] _zz_s0_countOnesLogic_4_12; + wire [1:0] _zz_s0_countOnesLogic_4_13; + reg [2:0] _zz_s0_countOnesLogic_5_9; + wire [2:0] _zz_s0_countOnesLogic_5_10; + reg [2:0] _zz_s0_countOnesLogic_5_11; + wire [2:0] _zz_s0_countOnesLogic_5_12; + wire [2:0] _zz_s0_countOnesLogic_6_9; + reg [2:0] _zz_s0_countOnesLogic_6_10; + wire [2:0] _zz_s0_countOnesLogic_6_11; + reg [2:0] _zz_s0_countOnesLogic_6_12; + wire [2:0] _zz_s0_countOnesLogic_6_13; + reg [2:0] _zz_s0_countOnesLogic_6_14; + wire [2:0] _zz_s0_countOnesLogic_6_15; + wire [0:0] _zz_s0_countOnesLogic_6_16; + wire [3:0] _zz_s0_countOnesLogic_7_9; + reg [3:0] _zz_s0_countOnesLogic_7_10; + wire [2:0] _zz_s0_countOnesLogic_7_11; + reg [3:0] _zz_s0_countOnesLogic_7_12; + wire [2:0] _zz_s0_countOnesLogic_7_13; + reg [3:0] _zz_s0_countOnesLogic_7_14; + wire [2:0] _zz_s0_countOnesLogic_7_15; + wire [1:0] _zz_s0_countOnesLogic_7_16; + wire [3:0] _zz_s0_countOnesLogic_8_9; + reg [3:0] _zz_s0_countOnesLogic_8_10; + wire [2:0] _zz_s0_countOnesLogic_8_11; + reg [3:0] _zz_s0_countOnesLogic_8_12; + wire [2:0] _zz_s0_countOnesLogic_8_13; + reg [3:0] _zz_s0_countOnesLogic_8_14; + wire [2:0] _zz_s0_countOnesLogic_8_15; + wire [3:0] _zz_s0_countOnesLogic_9_9; + reg [3:0] _zz_s0_countOnesLogic_9_10; + wire [2:0] _zz_s0_countOnesLogic_9_11; + reg [3:0] _zz_s0_countOnesLogic_9_12; + wire [2:0] _zz_s0_countOnesLogic_9_13; + wire [3:0] _zz_s0_countOnesLogic_9_14; + reg [3:0] _zz_s0_countOnesLogic_9_15; + wire [2:0] _zz_s0_countOnesLogic_9_16; + reg [3:0] _zz_s0_countOnesLogic_9_17; + wire [2:0] _zz_s0_countOnesLogic_9_18; + wire [0:0] _zz_s0_countOnesLogic_9_19; + wire [3:0] _zz_s0_countOnesLogic_10_9; + reg [3:0] _zz_s0_countOnesLogic_10_10; + wire [2:0] _zz_s0_countOnesLogic_10_11; + reg [3:0] _zz_s0_countOnesLogic_10_12; + wire [2:0] _zz_s0_countOnesLogic_10_13; + wire [3:0] _zz_s0_countOnesLogic_10_14; + reg [3:0] _zz_s0_countOnesLogic_10_15; + wire [2:0] _zz_s0_countOnesLogic_10_16; + reg [3:0] _zz_s0_countOnesLogic_10_17; + wire [2:0] _zz_s0_countOnesLogic_10_18; + wire [1:0] _zz_s0_countOnesLogic_10_19; + wire [3:0] _zz_s0_countOnesLogic_11_9; + reg [3:0] _zz_s0_countOnesLogic_11_10; + wire [2:0] _zz_s0_countOnesLogic_11_11; + reg [3:0] _zz_s0_countOnesLogic_11_12; + wire [2:0] _zz_s0_countOnesLogic_11_13; + wire [3:0] _zz_s0_countOnesLogic_11_14; + reg [3:0] _zz_s0_countOnesLogic_11_15; + wire [2:0] _zz_s0_countOnesLogic_11_16; + reg [3:0] _zz_s0_countOnesLogic_11_17; + wire [2:0] _zz_s0_countOnesLogic_11_18; + wire [3:0] _zz_s0_countOnesLogic_12_9; + wire [3:0] _zz_s0_countOnesLogic_12_10; + reg [3:0] _zz_s0_countOnesLogic_12_11; + wire [2:0] _zz_s0_countOnesLogic_12_12; + reg [3:0] _zz_s0_countOnesLogic_12_13; + wire [2:0] _zz_s0_countOnesLogic_12_14; + wire [3:0] _zz_s0_countOnesLogic_12_15; + reg [3:0] _zz_s0_countOnesLogic_12_16; + wire [2:0] _zz_s0_countOnesLogic_12_17; + reg [3:0] _zz_s0_countOnesLogic_12_18; + wire [2:0] _zz_s0_countOnesLogic_12_19; + reg [3:0] _zz_s0_countOnesLogic_12_20; + wire [2:0] _zz_s0_countOnesLogic_12_21; + wire [0:0] _zz_s0_countOnesLogic_12_22; + wire [3:0] _zz_s0_countOnesLogic_13_9; + wire [3:0] _zz_s0_countOnesLogic_13_10; + reg [3:0] _zz_s0_countOnesLogic_13_11; + wire [2:0] _zz_s0_countOnesLogic_13_12; + reg [3:0] _zz_s0_countOnesLogic_13_13; + wire [2:0] _zz_s0_countOnesLogic_13_14; + wire [3:0] _zz_s0_countOnesLogic_13_15; + reg [3:0] _zz_s0_countOnesLogic_13_16; + wire [2:0] _zz_s0_countOnesLogic_13_17; + reg [3:0] _zz_s0_countOnesLogic_13_18; + wire [2:0] _zz_s0_countOnesLogic_13_19; + reg [3:0] _zz_s0_countOnesLogic_13_20; + wire [2:0] _zz_s0_countOnesLogic_13_21; + wire [1:0] _zz_s0_countOnesLogic_13_22; + wire [3:0] _zz_s0_countOnesLogic_14_9; + wire [3:0] _zz_s0_countOnesLogic_14_10; + reg [3:0] _zz_s0_countOnesLogic_14_11; + wire [2:0] _zz_s0_countOnesLogic_14_12; + reg [3:0] _zz_s0_countOnesLogic_14_13; + wire [2:0] _zz_s0_countOnesLogic_14_14; + wire [3:0] _zz_s0_countOnesLogic_14_15; + reg [3:0] _zz_s0_countOnesLogic_14_16; + wire [2:0] _zz_s0_countOnesLogic_14_17; + reg [3:0] _zz_s0_countOnesLogic_14_18; + wire [2:0] _zz_s0_countOnesLogic_14_19; + reg [3:0] _zz_s0_countOnesLogic_14_20; + wire [2:0] _zz_s0_countOnesLogic_14_21; + wire [4:0] _zz_s0_countOnesLogic_15_8; + wire [4:0] _zz_s0_countOnesLogic_15_9; + reg [4:0] _zz_s0_countOnesLogic_15_10; + wire [2:0] _zz_s0_countOnesLogic_15_11; + reg [4:0] _zz_s0_countOnesLogic_15_12; + wire [2:0] _zz_s0_countOnesLogic_15_13; + wire [4:0] _zz_s0_countOnesLogic_15_14; + reg [4:0] _zz_s0_countOnesLogic_15_15; + wire [2:0] _zz_s0_countOnesLogic_15_16; + reg [4:0] _zz_s0_countOnesLogic_15_17; + wire [2:0] _zz_s0_countOnesLogic_15_18; + wire [4:0] _zz_s0_countOnesLogic_15_19; + reg [4:0] _zz_s0_countOnesLogic_15_20; + wire [2:0] _zz_s0_countOnesLogic_15_21; + reg [4:0] _zz_s0_countOnesLogic_15_22; + wire [2:0] _zz_s0_countOnesLogic_15_23; + wire [0:0] _zz_s0_countOnesLogic_15_24; + wire [4:0] _zz_s1_offsetNext; + wire [12:0] _zz_s1_byteCounter; + wire [3:0] _zz_s1_inputIndexes_1; + wire [3:0] _zz_s1_inputIndexes_2; + wire [3:0] _zz_s1_inputIndexes_3; + wire [3:0] _zz_s1_inputIndexes_4; + wire [3:0] _zz_s1_inputIndexes_5; + wire [3:0] _zz_s1_inputIndexes_6; + wire [3:0] _zz_s1_inputIndexes_7; + wire [0:0] _zz_s1_outputPayload_selValid_240; + wire [6:0] _zz_s1_outputPayload_selValid_241; + wire [0:0] _zz_s1_outputPayload_selValid_242; + wire [6:0] _zz_s1_outputPayload_selValid_243; + wire [0:0] _zz_s1_outputPayload_selValid_244; + wire [6:0] _zz_s1_outputPayload_selValid_245; + wire [0:0] _zz_s1_outputPayload_selValid_246; + wire [6:0] _zz_s1_outputPayload_selValid_247; + wire [0:0] _zz_s1_outputPayload_selValid_248; + wire [6:0] _zz_s1_outputPayload_selValid_249; + wire [0:0] _zz_s1_outputPayload_selValid_250; + wire [6:0] _zz_s1_outputPayload_selValid_251; + wire [0:0] _zz_s1_outputPayload_selValid_252; + wire [6:0] _zz_s1_outputPayload_selValid_253; + wire [0:0] _zz_s1_outputPayload_selValid_254; + wire [6:0] _zz_s1_outputPayload_selValid_255; + wire [0:0] _zz_s1_outputPayload_selValid_256; + wire [6:0] _zz_s1_outputPayload_selValid_257; + wire [0:0] _zz_s1_outputPayload_selValid_258; + wire [6:0] _zz_s1_outputPayload_selValid_259; + wire [0:0] _zz_s1_outputPayload_selValid_260; + wire [6:0] _zz_s1_outputPayload_selValid_261; + wire [0:0] _zz_s1_outputPayload_selValid_262; + wire [6:0] _zz_s1_outputPayload_selValid_263; + wire [0:0] _zz_s1_outputPayload_selValid_264; + wire [6:0] _zz_s1_outputPayload_selValid_265; + wire [0:0] _zz_s1_outputPayload_selValid_266; + wire [6:0] _zz_s1_outputPayload_selValid_267; + wire [0:0] _zz_s1_outputPayload_selValid_268; + wire [6:0] _zz_s1_outputPayload_selValid_269; + wire [0:0] _zz_s1_outputPayload_selValid_270; + wire [6:0] _zz_s1_outputPayload_selValid_271; + wire [12:0] _zz_when_DmaSg_l1464; + reg [7:0] _zz_s2_byteLogic_0_inputData; + reg [7:0] _zz_s2_byteLogic_1_inputData; + reg [7:0] _zz_s2_byteLogic_2_inputData; + reg [7:0] _zz_s2_byteLogic_3_inputData; + reg [7:0] _zz_s2_byteLogic_4_inputData; + reg [7:0] _zz_s2_byteLogic_5_inputData; + reg [7:0] _zz_s2_byteLogic_6_inputData; + reg [7:0] _zz_s2_byteLogic_7_inputData; + reg [7:0] _zz_s2_byteLogic_8_inputData; + reg [7:0] _zz_s2_byteLogic_9_inputData; + reg [7:0] _zz_s2_byteLogic_10_inputData; + reg [7:0] _zz_s2_byteLogic_11_inputData; + reg [7:0] _zz_s2_byteLogic_12_inputData; + reg [7:0] _zz_s2_byteLogic_13_inputData; + reg [7:0] _zz_s2_byteLogic_14_inputData; + reg [7:0] _zz_s2_byteLogic_15_inputData; + reg [3:0] _zz_io_output_usedUntil_4; + wire [3:0] _zz_io_output_usedUntil_5; + wire s0_input_valid; + wire s0_input_ready; + wire [127:0] s0_input_payload_data; + wire [15:0] s0_input_payload_mask; + reg io_input_rValid; + reg [127:0] io_input_rData_data; + reg [15:0] io_input_rData_mask; + wire when_Stream_l375; + wire _zz_s0_countOnesLogic_0; + wire _zz_s0_countOnesLogic_1; + wire _zz_s0_countOnesLogic_2; + wire _zz_s0_countOnesLogic_3; + wire _zz_s0_countOnesLogic_4; + wire _zz_s0_countOnesLogic_5; + wire _zz_s0_countOnesLogic_6; + wire _zz_s0_countOnesLogic_7; + wire _zz_s0_countOnesLogic_8; + wire _zz_s0_countOnesLogic_9; + wire _zz_s0_countOnesLogic_10; + wire _zz_s0_countOnesLogic_11; + wire _zz_s0_countOnesLogic_12; + wire _zz_s0_countOnesLogic_13; + wire _zz_s0_countOnesLogic_14; + wire [0:0] s0_countOnesLogic_0; + wire [1:0] s0_countOnesLogic_1; + wire [1:0] s0_countOnesLogic_2; + wire [2:0] _zz_s0_countOnesLogic_3_1; + wire [2:0] _zz_s0_countOnesLogic_3_2; + wire [2:0] _zz_s0_countOnesLogic_3_3; + wire [2:0] _zz_s0_countOnesLogic_3_4; + wire [2:0] _zz_s0_countOnesLogic_3_5; + wire [2:0] _zz_s0_countOnesLogic_3_6; + wire [2:0] _zz_s0_countOnesLogic_3_7; + wire [2:0] _zz_s0_countOnesLogic_3_8; + wire [2:0] s0_countOnesLogic_3; + wire [2:0] _zz_s0_countOnesLogic_4_1; + wire [2:0] _zz_s0_countOnesLogic_4_2; + wire [2:0] _zz_s0_countOnesLogic_4_3; + wire [2:0] _zz_s0_countOnesLogic_4_4; + wire [2:0] _zz_s0_countOnesLogic_4_5; + wire [2:0] _zz_s0_countOnesLogic_4_6; + wire [2:0] _zz_s0_countOnesLogic_4_7; + wire [2:0] _zz_s0_countOnesLogic_4_8; + wire [2:0] s0_countOnesLogic_4; + wire [2:0] _zz_s0_countOnesLogic_5_1; + wire [2:0] _zz_s0_countOnesLogic_5_2; + wire [2:0] _zz_s0_countOnesLogic_5_3; + wire [2:0] _zz_s0_countOnesLogic_5_4; + wire [2:0] _zz_s0_countOnesLogic_5_5; + wire [2:0] _zz_s0_countOnesLogic_5_6; + wire [2:0] _zz_s0_countOnesLogic_5_7; + wire [2:0] _zz_s0_countOnesLogic_5_8; + wire [2:0] s0_countOnesLogic_5; + wire [2:0] _zz_s0_countOnesLogic_6_1; + wire [2:0] _zz_s0_countOnesLogic_6_2; + wire [2:0] _zz_s0_countOnesLogic_6_3; + wire [2:0] _zz_s0_countOnesLogic_6_4; + wire [2:0] _zz_s0_countOnesLogic_6_5; + wire [2:0] _zz_s0_countOnesLogic_6_6; + wire [2:0] _zz_s0_countOnesLogic_6_7; + wire [2:0] _zz_s0_countOnesLogic_6_8; + wire [2:0] s0_countOnesLogic_6; + wire [3:0] _zz_s0_countOnesLogic_7_1; + wire [3:0] _zz_s0_countOnesLogic_7_2; + wire [3:0] _zz_s0_countOnesLogic_7_3; + wire [3:0] _zz_s0_countOnesLogic_7_4; + wire [3:0] _zz_s0_countOnesLogic_7_5; + wire [3:0] _zz_s0_countOnesLogic_7_6; + wire [3:0] _zz_s0_countOnesLogic_7_7; + wire [3:0] _zz_s0_countOnesLogic_7_8; + wire [3:0] s0_countOnesLogic_7; + wire [3:0] _zz_s0_countOnesLogic_8_1; + wire [3:0] _zz_s0_countOnesLogic_8_2; + wire [3:0] _zz_s0_countOnesLogic_8_3; + wire [3:0] _zz_s0_countOnesLogic_8_4; + wire [3:0] _zz_s0_countOnesLogic_8_5; + wire [3:0] _zz_s0_countOnesLogic_8_6; + wire [3:0] _zz_s0_countOnesLogic_8_7; + wire [3:0] _zz_s0_countOnesLogic_8_8; + wire [3:0] s0_countOnesLogic_8; + wire [3:0] _zz_s0_countOnesLogic_9_1; + wire [3:0] _zz_s0_countOnesLogic_9_2; + wire [3:0] _zz_s0_countOnesLogic_9_3; + wire [3:0] _zz_s0_countOnesLogic_9_4; + wire [3:0] _zz_s0_countOnesLogic_9_5; + wire [3:0] _zz_s0_countOnesLogic_9_6; + wire [3:0] _zz_s0_countOnesLogic_9_7; + wire [3:0] _zz_s0_countOnesLogic_9_8; + wire [3:0] s0_countOnesLogic_9; + wire [3:0] _zz_s0_countOnesLogic_10_1; + wire [3:0] _zz_s0_countOnesLogic_10_2; + wire [3:0] _zz_s0_countOnesLogic_10_3; + wire [3:0] _zz_s0_countOnesLogic_10_4; + wire [3:0] _zz_s0_countOnesLogic_10_5; + wire [3:0] _zz_s0_countOnesLogic_10_6; + wire [3:0] _zz_s0_countOnesLogic_10_7; + wire [3:0] _zz_s0_countOnesLogic_10_8; + wire [3:0] s0_countOnesLogic_10; + wire [3:0] _zz_s0_countOnesLogic_11_1; + wire [3:0] _zz_s0_countOnesLogic_11_2; + wire [3:0] _zz_s0_countOnesLogic_11_3; + wire [3:0] _zz_s0_countOnesLogic_11_4; + wire [3:0] _zz_s0_countOnesLogic_11_5; + wire [3:0] _zz_s0_countOnesLogic_11_6; + wire [3:0] _zz_s0_countOnesLogic_11_7; + wire [3:0] _zz_s0_countOnesLogic_11_8; + wire [3:0] s0_countOnesLogic_11; + wire [3:0] _zz_s0_countOnesLogic_12_1; + wire [3:0] _zz_s0_countOnesLogic_12_2; + wire [3:0] _zz_s0_countOnesLogic_12_3; + wire [3:0] _zz_s0_countOnesLogic_12_4; + wire [3:0] _zz_s0_countOnesLogic_12_5; + wire [3:0] _zz_s0_countOnesLogic_12_6; + wire [3:0] _zz_s0_countOnesLogic_12_7; + wire [3:0] _zz_s0_countOnesLogic_12_8; + wire [3:0] s0_countOnesLogic_12; + wire [3:0] _zz_s0_countOnesLogic_13_1; + wire [3:0] _zz_s0_countOnesLogic_13_2; + wire [3:0] _zz_s0_countOnesLogic_13_3; + wire [3:0] _zz_s0_countOnesLogic_13_4; + wire [3:0] _zz_s0_countOnesLogic_13_5; + wire [3:0] _zz_s0_countOnesLogic_13_6; + wire [3:0] _zz_s0_countOnesLogic_13_7; + wire [3:0] _zz_s0_countOnesLogic_13_8; + wire [3:0] s0_countOnesLogic_13; + wire [3:0] _zz_s0_countOnesLogic_14_1; + wire [3:0] _zz_s0_countOnesLogic_14_2; + wire [3:0] _zz_s0_countOnesLogic_14_3; + wire [3:0] _zz_s0_countOnesLogic_14_4; + wire [3:0] _zz_s0_countOnesLogic_14_5; + wire [3:0] _zz_s0_countOnesLogic_14_6; + wire [3:0] _zz_s0_countOnesLogic_14_7; + wire [3:0] _zz_s0_countOnesLogic_14_8; + wire [3:0] s0_countOnesLogic_14; + wire [4:0] _zz_s0_countOnesLogic_15; + wire [4:0] _zz_s0_countOnesLogic_15_1; + wire [4:0] _zz_s0_countOnesLogic_15_2; + wire [4:0] _zz_s0_countOnesLogic_15_3; + wire [4:0] _zz_s0_countOnesLogic_15_4; + wire [4:0] _zz_s0_countOnesLogic_15_5; + wire [4:0] _zz_s0_countOnesLogic_15_6; + wire [4:0] _zz_s0_countOnesLogic_15_7; + wire [4:0] s0_countOnesLogic_15; + wire [127:0] s0_outputPayload_cmd_data; + wire [15:0] s0_outputPayload_cmd_mask; + wire [0:0] s0_outputPayload_countOnes_0; + wire [1:0] s0_outputPayload_countOnes_1; + wire [1:0] s0_outputPayload_countOnes_2; + wire [2:0] s0_outputPayload_countOnes_3; + wire [2:0] s0_outputPayload_countOnes_4; + wire [2:0] s0_outputPayload_countOnes_5; + wire [2:0] s0_outputPayload_countOnes_6; + wire [3:0] s0_outputPayload_countOnes_7; + wire [3:0] s0_outputPayload_countOnes_8; + wire [3:0] s0_outputPayload_countOnes_9; + wire [3:0] s0_outputPayload_countOnes_10; + wire [3:0] s0_outputPayload_countOnes_11; + wire [3:0] s0_outputPayload_countOnes_12; + wire [3:0] s0_outputPayload_countOnes_13; + wire [3:0] s0_outputPayload_countOnes_14; + wire [4:0] s0_outputPayload_countOnes_15; + wire s0_output_valid; + reg s0_output_ready; + wire [127:0] s0_output_payload_cmd_data; + wire [15:0] s0_output_payload_cmd_mask; + wire [0:0] s0_output_payload_countOnes_0; + wire [1:0] s0_output_payload_countOnes_1; + wire [1:0] s0_output_payload_countOnes_2; + wire [2:0] s0_output_payload_countOnes_3; + wire [2:0] s0_output_payload_countOnes_4; + wire [2:0] s0_output_payload_countOnes_5; + wire [2:0] s0_output_payload_countOnes_6; + wire [3:0] s0_output_payload_countOnes_7; + wire [3:0] s0_output_payload_countOnes_8; + wire [3:0] s0_output_payload_countOnes_9; + wire [3:0] s0_output_payload_countOnes_10; + wire [3:0] s0_output_payload_countOnes_11; + wire [3:0] s0_output_payload_countOnes_12; + wire [3:0] s0_output_payload_countOnes_13; + wire [3:0] s0_output_payload_countOnes_14; + wire [4:0] s0_output_payload_countOnes_15; + wire s1_input_valid; + wire s1_input_ready; + wire [127:0] s1_input_payload_cmd_data; + wire [15:0] s1_input_payload_cmd_mask; + wire [0:0] s1_input_payload_countOnes_0; + wire [1:0] s1_input_payload_countOnes_1; + wire [1:0] s1_input_payload_countOnes_2; + wire [2:0] s1_input_payload_countOnes_3; + wire [2:0] s1_input_payload_countOnes_4; + wire [2:0] s1_input_payload_countOnes_5; + wire [2:0] s1_input_payload_countOnes_6; + wire [3:0] s1_input_payload_countOnes_7; + wire [3:0] s1_input_payload_countOnes_8; + wire [3:0] s1_input_payload_countOnes_9; + wire [3:0] s1_input_payload_countOnes_10; + wire [3:0] s1_input_payload_countOnes_11; + wire [3:0] s1_input_payload_countOnes_12; + wire [3:0] s1_input_payload_countOnes_13; + wire [3:0] s1_input_payload_countOnes_14; + wire [4:0] s1_input_payload_countOnes_15; + reg s0_output_rValid; + reg [127:0] s0_output_rData_cmd_data; + reg [15:0] s0_output_rData_cmd_mask; + reg [0:0] s0_output_rData_countOnes_0; + reg [1:0] s0_output_rData_countOnes_1; + reg [1:0] s0_output_rData_countOnes_2; + reg [2:0] s0_output_rData_countOnes_3; + reg [2:0] s0_output_rData_countOnes_4; + reg [2:0] s0_output_rData_countOnes_5; + reg [2:0] s0_output_rData_countOnes_6; + reg [3:0] s0_output_rData_countOnes_7; + reg [3:0] s0_output_rData_countOnes_8; + reg [3:0] s0_output_rData_countOnes_9; + reg [3:0] s0_output_rData_countOnes_10; + reg [3:0] s0_output_rData_countOnes_11; + reg [3:0] s0_output_rData_countOnes_12; + reg [3:0] s0_output_rData_countOnes_13; + reg [3:0] s0_output_rData_countOnes_14; + reg [4:0] s0_output_rData_countOnes_15; + wire when_Stream_l375_1; + reg [3:0] s1_offset; + wire [4:0] s1_offsetNext; + wire s1_input_fire; + reg [12:0] s1_byteCounter; + wire [3:0] s1_inputIndexes_0; + wire [3:0] s1_inputIndexes_1; + wire [3:0] s1_inputIndexes_2; + wire [3:0] s1_inputIndexes_3; + wire [3:0] s1_inputIndexes_4; + wire [3:0] s1_inputIndexes_5; + wire [3:0] s1_inputIndexes_6; + wire [3:0] s1_inputIndexes_7; + wire [3:0] s1_inputIndexes_8; + wire [3:0] s1_inputIndexes_9; + wire [3:0] s1_inputIndexes_10; + wire [3:0] s1_inputIndexes_11; + wire [3:0] s1_inputIndexes_12; + wire [3:0] s1_inputIndexes_13; + wire [3:0] s1_inputIndexes_14; + wire [3:0] s1_inputIndexes_15; + wire [127:0] s1_outputPayload_cmd_data; + wire [15:0] s1_outputPayload_cmd_mask; + wire [3:0] s1_outputPayload_index_0; + wire [3:0] s1_outputPayload_index_1; + wire [3:0] s1_outputPayload_index_2; + wire [3:0] s1_outputPayload_index_3; + wire [3:0] s1_outputPayload_index_4; + wire [3:0] s1_outputPayload_index_5; + wire [3:0] s1_outputPayload_index_6; + wire [3:0] s1_outputPayload_index_7; + wire [3:0] s1_outputPayload_index_8; + wire [3:0] s1_outputPayload_index_9; + wire [3:0] s1_outputPayload_index_10; + wire [3:0] s1_outputPayload_index_11; + wire [3:0] s1_outputPayload_index_12; + wire [3:0] s1_outputPayload_index_13; + wire [3:0] s1_outputPayload_index_14; + wire [3:0] s1_outputPayload_index_15; + wire s1_outputPayload_last; + wire [3:0] s1_outputPayload_sel_0; + wire [3:0] s1_outputPayload_sel_1; + wire [3:0] s1_outputPayload_sel_2; + wire [3:0] s1_outputPayload_sel_3; + wire [3:0] s1_outputPayload_sel_4; + wire [3:0] s1_outputPayload_sel_5; + wire [3:0] s1_outputPayload_sel_6; + wire [3:0] s1_outputPayload_sel_7; + wire [3:0] s1_outputPayload_sel_8; + wire [3:0] s1_outputPayload_sel_9; + wire [3:0] s1_outputPayload_sel_10; + wire [3:0] s1_outputPayload_sel_11; + wire [3:0] s1_outputPayload_sel_12; + wire [3:0] s1_outputPayload_sel_13; + wire [3:0] s1_outputPayload_sel_14; + wire [3:0] s1_outputPayload_sel_15; + reg [15:0] s1_outputPayload_selValid; + wire _zz_s1_outputPayload_selValid; + wire _zz_s1_outputPayload_selValid_1; + wire _zz_s1_outputPayload_selValid_2; + wire _zz_s1_outputPayload_selValid_3; + wire _zz_s1_outputPayload_selValid_4; + wire _zz_s1_outputPayload_selValid_5; + wire _zz_s1_outputPayload_selValid_6; + wire _zz_s1_outputPayload_selValid_7; + wire _zz_s1_outputPayload_selValid_8; + wire _zz_s1_outputPayload_selValid_9; + wire _zz_s1_outputPayload_selValid_10; + wire _zz_s1_outputPayload_selValid_11; + wire _zz_s1_outputPayload_selValid_12; + wire _zz_s1_outputPayload_selValid_13; + wire _zz_s1_outputPayload_selValid_14; + wire _zz_s1_outputPayload_sel_0; + wire _zz_s1_outputPayload_sel_0_1; + wire _zz_s1_outputPayload_sel_0_2; + wire _zz_s1_outputPayload_sel_0_3; + wire _zz_s1_outputPayload_selValid_15; + wire _zz_s1_outputPayload_selValid_16; + wire _zz_s1_outputPayload_selValid_17; + wire _zz_s1_outputPayload_selValid_18; + wire _zz_s1_outputPayload_selValid_19; + wire _zz_s1_outputPayload_selValid_20; + wire _zz_s1_outputPayload_selValid_21; + wire _zz_s1_outputPayload_selValid_22; + wire _zz_s1_outputPayload_selValid_23; + wire _zz_s1_outputPayload_selValid_24; + wire _zz_s1_outputPayload_selValid_25; + wire _zz_s1_outputPayload_selValid_26; + wire _zz_s1_outputPayload_selValid_27; + wire _zz_s1_outputPayload_selValid_28; + wire _zz_s1_outputPayload_selValid_29; + wire _zz_s1_outputPayload_sel_1; + wire _zz_s1_outputPayload_sel_1_1; + wire _zz_s1_outputPayload_sel_1_2; + wire _zz_s1_outputPayload_sel_1_3; + wire _zz_s1_outputPayload_selValid_30; + wire _zz_s1_outputPayload_selValid_31; + wire _zz_s1_outputPayload_selValid_32; + wire _zz_s1_outputPayload_selValid_33; + wire _zz_s1_outputPayload_selValid_34; + wire _zz_s1_outputPayload_selValid_35; + wire _zz_s1_outputPayload_selValid_36; + wire _zz_s1_outputPayload_selValid_37; + wire _zz_s1_outputPayload_selValid_38; + wire _zz_s1_outputPayload_selValid_39; + wire _zz_s1_outputPayload_selValid_40; + wire _zz_s1_outputPayload_selValid_41; + wire _zz_s1_outputPayload_selValid_42; + wire _zz_s1_outputPayload_selValid_43; + wire _zz_s1_outputPayload_selValid_44; + wire _zz_s1_outputPayload_sel_2; + wire _zz_s1_outputPayload_sel_2_1; + wire _zz_s1_outputPayload_sel_2_2; + wire _zz_s1_outputPayload_sel_2_3; + wire _zz_s1_outputPayload_selValid_45; + wire _zz_s1_outputPayload_selValid_46; + wire _zz_s1_outputPayload_selValid_47; + wire _zz_s1_outputPayload_selValid_48; + wire _zz_s1_outputPayload_selValid_49; + wire _zz_s1_outputPayload_selValid_50; + wire _zz_s1_outputPayload_selValid_51; + wire _zz_s1_outputPayload_selValid_52; + wire _zz_s1_outputPayload_selValid_53; + wire _zz_s1_outputPayload_selValid_54; + wire _zz_s1_outputPayload_selValid_55; + wire _zz_s1_outputPayload_selValid_56; + wire _zz_s1_outputPayload_selValid_57; + wire _zz_s1_outputPayload_selValid_58; + wire _zz_s1_outputPayload_selValid_59; + wire _zz_s1_outputPayload_sel_3; + wire _zz_s1_outputPayload_sel_3_1; + wire _zz_s1_outputPayload_sel_3_2; + wire _zz_s1_outputPayload_sel_3_3; + wire _zz_s1_outputPayload_selValid_60; + wire _zz_s1_outputPayload_selValid_61; + wire _zz_s1_outputPayload_selValid_62; + wire _zz_s1_outputPayload_selValid_63; + wire _zz_s1_outputPayload_selValid_64; + wire _zz_s1_outputPayload_selValid_65; + wire _zz_s1_outputPayload_selValid_66; + wire _zz_s1_outputPayload_selValid_67; + wire _zz_s1_outputPayload_selValid_68; + wire _zz_s1_outputPayload_selValid_69; + wire _zz_s1_outputPayload_selValid_70; + wire _zz_s1_outputPayload_selValid_71; + wire _zz_s1_outputPayload_selValid_72; + wire _zz_s1_outputPayload_selValid_73; + wire _zz_s1_outputPayload_selValid_74; + wire _zz_s1_outputPayload_sel_4; + wire _zz_s1_outputPayload_sel_4_1; + wire _zz_s1_outputPayload_sel_4_2; + wire _zz_s1_outputPayload_sel_4_3; + wire _zz_s1_outputPayload_selValid_75; + wire _zz_s1_outputPayload_selValid_76; + wire _zz_s1_outputPayload_selValid_77; + wire _zz_s1_outputPayload_selValid_78; + wire _zz_s1_outputPayload_selValid_79; + wire _zz_s1_outputPayload_selValid_80; + wire _zz_s1_outputPayload_selValid_81; + wire _zz_s1_outputPayload_selValid_82; + wire _zz_s1_outputPayload_selValid_83; + wire _zz_s1_outputPayload_selValid_84; + wire _zz_s1_outputPayload_selValid_85; + wire _zz_s1_outputPayload_selValid_86; + wire _zz_s1_outputPayload_selValid_87; + wire _zz_s1_outputPayload_selValid_88; + wire _zz_s1_outputPayload_selValid_89; + wire _zz_s1_outputPayload_sel_5; + wire _zz_s1_outputPayload_sel_5_1; + wire _zz_s1_outputPayload_sel_5_2; + wire _zz_s1_outputPayload_sel_5_3; + wire _zz_s1_outputPayload_selValid_90; + wire _zz_s1_outputPayload_selValid_91; + wire _zz_s1_outputPayload_selValid_92; + wire _zz_s1_outputPayload_selValid_93; + wire _zz_s1_outputPayload_selValid_94; + wire _zz_s1_outputPayload_selValid_95; + wire _zz_s1_outputPayload_selValid_96; + wire _zz_s1_outputPayload_selValid_97; + wire _zz_s1_outputPayload_selValid_98; + wire _zz_s1_outputPayload_selValid_99; + wire _zz_s1_outputPayload_selValid_100; + wire _zz_s1_outputPayload_selValid_101; + wire _zz_s1_outputPayload_selValid_102; + wire _zz_s1_outputPayload_selValid_103; + wire _zz_s1_outputPayload_selValid_104; + wire _zz_s1_outputPayload_sel_6; + wire _zz_s1_outputPayload_sel_6_1; + wire _zz_s1_outputPayload_sel_6_2; + wire _zz_s1_outputPayload_sel_6_3; + wire _zz_s1_outputPayload_selValid_105; + wire _zz_s1_outputPayload_selValid_106; + wire _zz_s1_outputPayload_selValid_107; + wire _zz_s1_outputPayload_selValid_108; + wire _zz_s1_outputPayload_selValid_109; + wire _zz_s1_outputPayload_selValid_110; + wire _zz_s1_outputPayload_selValid_111; + wire _zz_s1_outputPayload_selValid_112; + wire _zz_s1_outputPayload_selValid_113; + wire _zz_s1_outputPayload_selValid_114; + wire _zz_s1_outputPayload_selValid_115; + wire _zz_s1_outputPayload_selValid_116; + wire _zz_s1_outputPayload_selValid_117; + wire _zz_s1_outputPayload_selValid_118; + wire _zz_s1_outputPayload_selValid_119; + wire _zz_s1_outputPayload_sel_7; + wire _zz_s1_outputPayload_sel_7_1; + wire _zz_s1_outputPayload_sel_7_2; + wire _zz_s1_outputPayload_sel_7_3; + wire _zz_s1_outputPayload_selValid_120; + wire _zz_s1_outputPayload_selValid_121; + wire _zz_s1_outputPayload_selValid_122; + wire _zz_s1_outputPayload_selValid_123; + wire _zz_s1_outputPayload_selValid_124; + wire _zz_s1_outputPayload_selValid_125; + wire _zz_s1_outputPayload_selValid_126; + wire _zz_s1_outputPayload_selValid_127; + wire _zz_s1_outputPayload_selValid_128; + wire _zz_s1_outputPayload_selValid_129; + wire _zz_s1_outputPayload_selValid_130; + wire _zz_s1_outputPayload_selValid_131; + wire _zz_s1_outputPayload_selValid_132; + wire _zz_s1_outputPayload_selValid_133; + wire _zz_s1_outputPayload_selValid_134; + wire _zz_s1_outputPayload_sel_8; + wire _zz_s1_outputPayload_sel_8_1; + wire _zz_s1_outputPayload_sel_8_2; + wire _zz_s1_outputPayload_sel_8_3; + wire _zz_s1_outputPayload_selValid_135; + wire _zz_s1_outputPayload_selValid_136; + wire _zz_s1_outputPayload_selValid_137; + wire _zz_s1_outputPayload_selValid_138; + wire _zz_s1_outputPayload_selValid_139; + wire _zz_s1_outputPayload_selValid_140; + wire _zz_s1_outputPayload_selValid_141; + wire _zz_s1_outputPayload_selValid_142; + wire _zz_s1_outputPayload_selValid_143; + wire _zz_s1_outputPayload_selValid_144; + wire _zz_s1_outputPayload_selValid_145; + wire _zz_s1_outputPayload_selValid_146; + wire _zz_s1_outputPayload_selValid_147; + wire _zz_s1_outputPayload_selValid_148; + wire _zz_s1_outputPayload_selValid_149; + wire _zz_s1_outputPayload_sel_9; + wire _zz_s1_outputPayload_sel_9_1; + wire _zz_s1_outputPayload_sel_9_2; + wire _zz_s1_outputPayload_sel_9_3; + wire _zz_s1_outputPayload_selValid_150; + wire _zz_s1_outputPayload_selValid_151; + wire _zz_s1_outputPayload_selValid_152; + wire _zz_s1_outputPayload_selValid_153; + wire _zz_s1_outputPayload_selValid_154; + wire _zz_s1_outputPayload_selValid_155; + wire _zz_s1_outputPayload_selValid_156; + wire _zz_s1_outputPayload_selValid_157; + wire _zz_s1_outputPayload_selValid_158; + wire _zz_s1_outputPayload_selValid_159; + wire _zz_s1_outputPayload_selValid_160; + wire _zz_s1_outputPayload_selValid_161; + wire _zz_s1_outputPayload_selValid_162; + wire _zz_s1_outputPayload_selValid_163; + wire _zz_s1_outputPayload_selValid_164; + wire _zz_s1_outputPayload_sel_10; + wire _zz_s1_outputPayload_sel_10_1; + wire _zz_s1_outputPayload_sel_10_2; + wire _zz_s1_outputPayload_sel_10_3; + wire _zz_s1_outputPayload_selValid_165; + wire _zz_s1_outputPayload_selValid_166; + wire _zz_s1_outputPayload_selValid_167; + wire _zz_s1_outputPayload_selValid_168; + wire _zz_s1_outputPayload_selValid_169; + wire _zz_s1_outputPayload_selValid_170; + wire _zz_s1_outputPayload_selValid_171; + wire _zz_s1_outputPayload_selValid_172; + wire _zz_s1_outputPayload_selValid_173; + wire _zz_s1_outputPayload_selValid_174; + wire _zz_s1_outputPayload_selValid_175; + wire _zz_s1_outputPayload_selValid_176; + wire _zz_s1_outputPayload_selValid_177; + wire _zz_s1_outputPayload_selValid_178; + wire _zz_s1_outputPayload_selValid_179; + wire _zz_s1_outputPayload_sel_11; + wire _zz_s1_outputPayload_sel_11_1; + wire _zz_s1_outputPayload_sel_11_2; + wire _zz_s1_outputPayload_sel_11_3; + wire _zz_s1_outputPayload_selValid_180; + wire _zz_s1_outputPayload_selValid_181; + wire _zz_s1_outputPayload_selValid_182; + wire _zz_s1_outputPayload_selValid_183; + wire _zz_s1_outputPayload_selValid_184; + wire _zz_s1_outputPayload_selValid_185; + wire _zz_s1_outputPayload_selValid_186; + wire _zz_s1_outputPayload_selValid_187; + wire _zz_s1_outputPayload_selValid_188; + wire _zz_s1_outputPayload_selValid_189; + wire _zz_s1_outputPayload_selValid_190; + wire _zz_s1_outputPayload_selValid_191; + wire _zz_s1_outputPayload_selValid_192; + wire _zz_s1_outputPayload_selValid_193; + wire _zz_s1_outputPayload_selValid_194; + wire _zz_s1_outputPayload_sel_12; + wire _zz_s1_outputPayload_sel_12_1; + wire _zz_s1_outputPayload_sel_12_2; + wire _zz_s1_outputPayload_sel_12_3; + wire _zz_s1_outputPayload_selValid_195; + wire _zz_s1_outputPayload_selValid_196; + wire _zz_s1_outputPayload_selValid_197; + wire _zz_s1_outputPayload_selValid_198; + wire _zz_s1_outputPayload_selValid_199; + wire _zz_s1_outputPayload_selValid_200; + wire _zz_s1_outputPayload_selValid_201; + wire _zz_s1_outputPayload_selValid_202; + wire _zz_s1_outputPayload_selValid_203; + wire _zz_s1_outputPayload_selValid_204; + wire _zz_s1_outputPayload_selValid_205; + wire _zz_s1_outputPayload_selValid_206; + wire _zz_s1_outputPayload_selValid_207; + wire _zz_s1_outputPayload_selValid_208; + wire _zz_s1_outputPayload_selValid_209; + wire _zz_s1_outputPayload_sel_13; + wire _zz_s1_outputPayload_sel_13_1; + wire _zz_s1_outputPayload_sel_13_2; + wire _zz_s1_outputPayload_sel_13_3; + wire _zz_s1_outputPayload_selValid_210; + wire _zz_s1_outputPayload_selValid_211; + wire _zz_s1_outputPayload_selValid_212; + wire _zz_s1_outputPayload_selValid_213; + wire _zz_s1_outputPayload_selValid_214; + wire _zz_s1_outputPayload_selValid_215; + wire _zz_s1_outputPayload_selValid_216; + wire _zz_s1_outputPayload_selValid_217; + wire _zz_s1_outputPayload_selValid_218; + wire _zz_s1_outputPayload_selValid_219; + wire _zz_s1_outputPayload_selValid_220; + wire _zz_s1_outputPayload_selValid_221; + wire _zz_s1_outputPayload_selValid_222; + wire _zz_s1_outputPayload_selValid_223; + wire _zz_s1_outputPayload_selValid_224; + wire _zz_s1_outputPayload_sel_14; + wire _zz_s1_outputPayload_sel_14_1; + wire _zz_s1_outputPayload_sel_14_2; + wire _zz_s1_outputPayload_sel_14_3; + wire _zz_s1_outputPayload_selValid_225; + wire _zz_s1_outputPayload_selValid_226; + wire _zz_s1_outputPayload_selValid_227; + wire _zz_s1_outputPayload_selValid_228; + wire _zz_s1_outputPayload_selValid_229; + wire _zz_s1_outputPayload_selValid_230; + wire _zz_s1_outputPayload_selValid_231; + wire _zz_s1_outputPayload_selValid_232; + wire _zz_s1_outputPayload_selValid_233; + wire _zz_s1_outputPayload_selValid_234; + wire _zz_s1_outputPayload_selValid_235; + wire _zz_s1_outputPayload_selValid_236; + wire _zz_s1_outputPayload_selValid_237; + wire _zz_s1_outputPayload_selValid_238; + wire _zz_s1_outputPayload_selValid_239; + wire _zz_s1_outputPayload_sel_15; + wire _zz_s1_outputPayload_sel_15_1; + wire _zz_s1_outputPayload_sel_15_2; + wire _zz_s1_outputPayload_sel_15_3; + wire s1_output_valid; + reg s1_output_ready; + wire [127:0] s1_output_payload_cmd_data; + wire [15:0] s1_output_payload_cmd_mask; + wire [3:0] s1_output_payload_index_0; + wire [3:0] s1_output_payload_index_1; + wire [3:0] s1_output_payload_index_2; + wire [3:0] s1_output_payload_index_3; + wire [3:0] s1_output_payload_index_4; + wire [3:0] s1_output_payload_index_5; + wire [3:0] s1_output_payload_index_6; + wire [3:0] s1_output_payload_index_7; + wire [3:0] s1_output_payload_index_8; + wire [3:0] s1_output_payload_index_9; + wire [3:0] s1_output_payload_index_10; + wire [3:0] s1_output_payload_index_11; + wire [3:0] s1_output_payload_index_12; + wire [3:0] s1_output_payload_index_13; + wire [3:0] s1_output_payload_index_14; + wire [3:0] s1_output_payload_index_15; + wire s1_output_payload_last; + wire [3:0] s1_output_payload_sel_0; + wire [3:0] s1_output_payload_sel_1; + wire [3:0] s1_output_payload_sel_2; + wire [3:0] s1_output_payload_sel_3; + wire [3:0] s1_output_payload_sel_4; + wire [3:0] s1_output_payload_sel_5; + wire [3:0] s1_output_payload_sel_6; + wire [3:0] s1_output_payload_sel_7; + wire [3:0] s1_output_payload_sel_8; + wire [3:0] s1_output_payload_sel_9; + wire [3:0] s1_output_payload_sel_10; + wire [3:0] s1_output_payload_sel_11; + wire [3:0] s1_output_payload_sel_12; + wire [3:0] s1_output_payload_sel_13; + wire [3:0] s1_output_payload_sel_14; + wire [3:0] s1_output_payload_sel_15; + wire [15:0] s1_output_payload_selValid; + wire s2_input_valid; + reg s2_input_ready; + wire [127:0] s2_input_payload_cmd_data; + wire [15:0] s2_input_payload_cmd_mask; + wire [3:0] s2_input_payload_index_0; + wire [3:0] s2_input_payload_index_1; + wire [3:0] s2_input_payload_index_2; + wire [3:0] s2_input_payload_index_3; + wire [3:0] s2_input_payload_index_4; + wire [3:0] s2_input_payload_index_5; + wire [3:0] s2_input_payload_index_6; + wire [3:0] s2_input_payload_index_7; + wire [3:0] s2_input_payload_index_8; + wire [3:0] s2_input_payload_index_9; + wire [3:0] s2_input_payload_index_10; + wire [3:0] s2_input_payload_index_11; + wire [3:0] s2_input_payload_index_12; + wire [3:0] s2_input_payload_index_13; + wire [3:0] s2_input_payload_index_14; + wire [3:0] s2_input_payload_index_15; + wire s2_input_payload_last; + wire [3:0] s2_input_payload_sel_0; + wire [3:0] s2_input_payload_sel_1; + wire [3:0] s2_input_payload_sel_2; + wire [3:0] s2_input_payload_sel_3; + wire [3:0] s2_input_payload_sel_4; + wire [3:0] s2_input_payload_sel_5; + wire [3:0] s2_input_payload_sel_6; + wire [3:0] s2_input_payload_sel_7; + wire [3:0] s2_input_payload_sel_8; + wire [3:0] s2_input_payload_sel_9; + wire [3:0] s2_input_payload_sel_10; + wire [3:0] s2_input_payload_sel_11; + wire [3:0] s2_input_payload_sel_12; + wire [3:0] s2_input_payload_sel_13; + wire [3:0] s2_input_payload_sel_14; + wire [3:0] s2_input_payload_sel_15; + wire [15:0] s2_input_payload_selValid; + reg s1_output_rValid; + reg [127:0] s1_output_rData_cmd_data; + reg [15:0] s1_output_rData_cmd_mask; + reg [3:0] s1_output_rData_index_0; + reg [3:0] s1_output_rData_index_1; + reg [3:0] s1_output_rData_index_2; + reg [3:0] s1_output_rData_index_3; + reg [3:0] s1_output_rData_index_4; + reg [3:0] s1_output_rData_index_5; + reg [3:0] s1_output_rData_index_6; + reg [3:0] s1_output_rData_index_7; + reg [3:0] s1_output_rData_index_8; + reg [3:0] s1_output_rData_index_9; + reg [3:0] s1_output_rData_index_10; + reg [3:0] s1_output_rData_index_11; + reg [3:0] s1_output_rData_index_12; + reg [3:0] s1_output_rData_index_13; + reg [3:0] s1_output_rData_index_14; + reg [3:0] s1_output_rData_index_15; + reg s1_output_rData_last; + reg [3:0] s1_output_rData_sel_0; + reg [3:0] s1_output_rData_sel_1; + reg [3:0] s1_output_rData_sel_2; + reg [3:0] s1_output_rData_sel_3; + reg [3:0] s1_output_rData_sel_4; + reg [3:0] s1_output_rData_sel_5; + reg [3:0] s1_output_rData_sel_6; + reg [3:0] s1_output_rData_sel_7; + reg [3:0] s1_output_rData_sel_8; + reg [3:0] s1_output_rData_sel_9; + reg [3:0] s1_output_rData_sel_10; + reg [3:0] s1_output_rData_sel_11; + reg [3:0] s1_output_rData_sel_12; + reg [3:0] s1_output_rData_sel_13; + reg [3:0] s1_output_rData_sel_14; + reg [3:0] s1_output_rData_sel_15; + reg [15:0] s1_output_rData_selValid; + wire when_Stream_l375_2; + wire when_DmaSg_l1464; + wire s2_input_fire; + wire [7:0] s2_inputDataBytes_0; + wire [7:0] s2_inputDataBytes_1; + wire [7:0] s2_inputDataBytes_2; + wire [7:0] s2_inputDataBytes_3; + wire [7:0] s2_inputDataBytes_4; + wire [7:0] s2_inputDataBytes_5; + wire [7:0] s2_inputDataBytes_6; + wire [7:0] s2_inputDataBytes_7; + wire [7:0] s2_inputDataBytes_8; + wire [7:0] s2_inputDataBytes_9; + wire [7:0] s2_inputDataBytes_10; + wire [7:0] s2_inputDataBytes_11; + wire [7:0] s2_inputDataBytes_12; + wire [7:0] s2_inputDataBytes_13; + wire [7:0] s2_inputDataBytes_14; + wire [7:0] s2_inputDataBytes_15; + reg s2_byteLogic_0_buffer_valid; + reg [7:0] s2_byteLogic_0_buffer_data; + wire s2_byteLogic_0_lastUsed; + wire s2_byteLogic_0_inputMask; + wire [7:0] s2_byteLogic_0_inputData; + wire s2_byteLogic_0_outputMask; + wire [7:0] s2_byteLogic_0_outputData; + wire when_DmaSg_l1493; + reg s2_byteLogic_1_buffer_valid; + reg [7:0] s2_byteLogic_1_buffer_data; + wire s2_byteLogic_1_lastUsed; + wire s2_byteLogic_1_inputMask; + wire [7:0] s2_byteLogic_1_inputData; + wire s2_byteLogic_1_outputMask; + wire [7:0] s2_byteLogic_1_outputData; + wire when_DmaSg_l1493_1; + reg s2_byteLogic_2_buffer_valid; + reg [7:0] s2_byteLogic_2_buffer_data; + wire s2_byteLogic_2_lastUsed; + wire s2_byteLogic_2_inputMask; + wire [7:0] s2_byteLogic_2_inputData; + wire s2_byteLogic_2_outputMask; + wire [7:0] s2_byteLogic_2_outputData; + wire when_DmaSg_l1493_2; + reg s2_byteLogic_3_buffer_valid; + reg [7:0] s2_byteLogic_3_buffer_data; + wire s2_byteLogic_3_lastUsed; + wire s2_byteLogic_3_inputMask; + wire [7:0] s2_byteLogic_3_inputData; + wire s2_byteLogic_3_outputMask; + wire [7:0] s2_byteLogic_3_outputData; + wire when_DmaSg_l1493_3; + reg s2_byteLogic_4_buffer_valid; + reg [7:0] s2_byteLogic_4_buffer_data; + wire s2_byteLogic_4_lastUsed; + wire s2_byteLogic_4_inputMask; + wire [7:0] s2_byteLogic_4_inputData; + wire s2_byteLogic_4_outputMask; + wire [7:0] s2_byteLogic_4_outputData; + wire when_DmaSg_l1493_4; + reg s2_byteLogic_5_buffer_valid; + reg [7:0] s2_byteLogic_5_buffer_data; + wire s2_byteLogic_5_lastUsed; + wire s2_byteLogic_5_inputMask; + wire [7:0] s2_byteLogic_5_inputData; + wire s2_byteLogic_5_outputMask; + wire [7:0] s2_byteLogic_5_outputData; + wire when_DmaSg_l1493_5; + reg s2_byteLogic_6_buffer_valid; + reg [7:0] s2_byteLogic_6_buffer_data; + wire s2_byteLogic_6_lastUsed; + wire s2_byteLogic_6_inputMask; + wire [7:0] s2_byteLogic_6_inputData; + wire s2_byteLogic_6_outputMask; + wire [7:0] s2_byteLogic_6_outputData; + wire when_DmaSg_l1493_6; + reg s2_byteLogic_7_buffer_valid; + reg [7:0] s2_byteLogic_7_buffer_data; + wire s2_byteLogic_7_lastUsed; + wire s2_byteLogic_7_inputMask; + wire [7:0] s2_byteLogic_7_inputData; + wire s2_byteLogic_7_outputMask; + wire [7:0] s2_byteLogic_7_outputData; + wire when_DmaSg_l1493_7; + reg s2_byteLogic_8_buffer_valid; + reg [7:0] s2_byteLogic_8_buffer_data; + wire s2_byteLogic_8_lastUsed; + wire s2_byteLogic_8_inputMask; + wire [7:0] s2_byteLogic_8_inputData; + wire s2_byteLogic_8_outputMask; + wire [7:0] s2_byteLogic_8_outputData; + wire when_DmaSg_l1493_8; + reg s2_byteLogic_9_buffer_valid; + reg [7:0] s2_byteLogic_9_buffer_data; + wire s2_byteLogic_9_lastUsed; + wire s2_byteLogic_9_inputMask; + wire [7:0] s2_byteLogic_9_inputData; + wire s2_byteLogic_9_outputMask; + wire [7:0] s2_byteLogic_9_outputData; + wire when_DmaSg_l1493_9; + reg s2_byteLogic_10_buffer_valid; + reg [7:0] s2_byteLogic_10_buffer_data; + wire s2_byteLogic_10_lastUsed; + wire s2_byteLogic_10_inputMask; + wire [7:0] s2_byteLogic_10_inputData; + wire s2_byteLogic_10_outputMask; + wire [7:0] s2_byteLogic_10_outputData; + wire when_DmaSg_l1493_10; + reg s2_byteLogic_11_buffer_valid; + reg [7:0] s2_byteLogic_11_buffer_data; + wire s2_byteLogic_11_lastUsed; + wire s2_byteLogic_11_inputMask; + wire [7:0] s2_byteLogic_11_inputData; + wire s2_byteLogic_11_outputMask; + wire [7:0] s2_byteLogic_11_outputData; + wire when_DmaSg_l1493_11; + reg s2_byteLogic_12_buffer_valid; + reg [7:0] s2_byteLogic_12_buffer_data; + wire s2_byteLogic_12_lastUsed; + wire s2_byteLogic_12_inputMask; + wire [7:0] s2_byteLogic_12_inputData; + wire s2_byteLogic_12_outputMask; + wire [7:0] s2_byteLogic_12_outputData; + wire when_DmaSg_l1493_12; + reg s2_byteLogic_13_buffer_valid; + reg [7:0] s2_byteLogic_13_buffer_data; + wire s2_byteLogic_13_lastUsed; + wire s2_byteLogic_13_inputMask; + wire [7:0] s2_byteLogic_13_inputData; + wire s2_byteLogic_13_outputMask; + wire [7:0] s2_byteLogic_13_outputData; + wire when_DmaSg_l1493_13; + reg s2_byteLogic_14_buffer_valid; + reg [7:0] s2_byteLogic_14_buffer_data; + wire s2_byteLogic_14_lastUsed; + wire s2_byteLogic_14_inputMask; + wire [7:0] s2_byteLogic_14_inputData; + wire s2_byteLogic_14_outputMask; + wire [7:0] s2_byteLogic_14_outputData; + wire when_DmaSg_l1493_14; + reg s2_byteLogic_15_buffer_valid; + reg [7:0] s2_byteLogic_15_buffer_data; + wire s2_byteLogic_15_lastUsed; + wire s2_byteLogic_15_inputMask; + wire [7:0] s2_byteLogic_15_inputData; + wire s2_byteLogic_15_outputMask; + wire [7:0] s2_byteLogic_15_outputData; + wire when_DmaSg_l1493_15; + wire _zz_io_output_usedUntil; + wire _zz_io_output_usedUntil_1; + wire _zz_io_output_usedUntil_2; + wire _zz_io_output_usedUntil_3; + + assign _zz_s0_countOnesLogic_3_13 = _zz_s0_countOnesLogic_3; + assign _zz_s0_countOnesLogic_3_12 = {2'd0, _zz_s0_countOnesLogic_3_13}; + assign _zz_s0_countOnesLogic_4_13 = {_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}; + assign _zz_s0_countOnesLogic_4_12 = {1'd0, _zz_s0_countOnesLogic_4_13}; + assign _zz_s0_countOnesLogic_6_9 = (_zz_s0_countOnesLogic_6_10 + _zz_s0_countOnesLogic_6_12); + assign _zz_s0_countOnesLogic_6_16 = _zz_s0_countOnesLogic_6; + assign _zz_s0_countOnesLogic_6_15 = {2'd0, _zz_s0_countOnesLogic_6_16}; + assign _zz_s0_countOnesLogic_7_9 = (_zz_s0_countOnesLogic_7_10 + _zz_s0_countOnesLogic_7_12); + assign _zz_s0_countOnesLogic_7_16 = {_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}; + assign _zz_s0_countOnesLogic_7_15 = {1'd0, _zz_s0_countOnesLogic_7_16}; + assign _zz_s0_countOnesLogic_8_9 = (_zz_s0_countOnesLogic_8_10 + _zz_s0_countOnesLogic_8_12); + assign _zz_s0_countOnesLogic_9_9 = (_zz_s0_countOnesLogic_9_10 + _zz_s0_countOnesLogic_9_12); + assign _zz_s0_countOnesLogic_9_14 = (_zz_s0_countOnesLogic_9_15 + _zz_s0_countOnesLogic_9_17); + assign _zz_s0_countOnesLogic_9_19 = _zz_s0_countOnesLogic_9; + assign _zz_s0_countOnesLogic_9_18 = {2'd0, _zz_s0_countOnesLogic_9_19}; + assign _zz_s0_countOnesLogic_10_9 = (_zz_s0_countOnesLogic_10_10 + _zz_s0_countOnesLogic_10_12); + assign _zz_s0_countOnesLogic_10_14 = (_zz_s0_countOnesLogic_10_15 + _zz_s0_countOnesLogic_10_17); + assign _zz_s0_countOnesLogic_10_19 = {_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}; + assign _zz_s0_countOnesLogic_10_18 = {1'd0, _zz_s0_countOnesLogic_10_19}; + assign _zz_s0_countOnesLogic_11_9 = (_zz_s0_countOnesLogic_11_10 + _zz_s0_countOnesLogic_11_12); + assign _zz_s0_countOnesLogic_11_14 = (_zz_s0_countOnesLogic_11_15 + _zz_s0_countOnesLogic_11_17); + assign _zz_s0_countOnesLogic_12_9 = (_zz_s0_countOnesLogic_12_10 + _zz_s0_countOnesLogic_12_15); + assign _zz_s0_countOnesLogic_12_10 = (_zz_s0_countOnesLogic_12_11 + _zz_s0_countOnesLogic_12_13); + assign _zz_s0_countOnesLogic_12_15 = (_zz_s0_countOnesLogic_12_16 + _zz_s0_countOnesLogic_12_18); + assign _zz_s0_countOnesLogic_12_22 = _zz_s0_countOnesLogic_12; + assign _zz_s0_countOnesLogic_12_21 = {2'd0, _zz_s0_countOnesLogic_12_22}; + assign _zz_s0_countOnesLogic_13_9 = (_zz_s0_countOnesLogic_13_10 + _zz_s0_countOnesLogic_13_15); + assign _zz_s0_countOnesLogic_13_10 = (_zz_s0_countOnesLogic_13_11 + _zz_s0_countOnesLogic_13_13); + assign _zz_s0_countOnesLogic_13_15 = (_zz_s0_countOnesLogic_13_16 + _zz_s0_countOnesLogic_13_18); + assign _zz_s0_countOnesLogic_13_22 = {_zz_s0_countOnesLogic_13,_zz_s0_countOnesLogic_12}; + assign _zz_s0_countOnesLogic_13_21 = {1'd0, _zz_s0_countOnesLogic_13_22}; + assign _zz_s0_countOnesLogic_14_9 = (_zz_s0_countOnesLogic_14_10 + _zz_s0_countOnesLogic_14_15); + assign _zz_s0_countOnesLogic_14_10 = (_zz_s0_countOnesLogic_14_11 + _zz_s0_countOnesLogic_14_13); + assign _zz_s0_countOnesLogic_14_15 = (_zz_s0_countOnesLogic_14_16 + _zz_s0_countOnesLogic_14_18); + assign _zz_s0_countOnesLogic_15_8 = (_zz_s0_countOnesLogic_15_9 + _zz_s0_countOnesLogic_15_14); + assign _zz_s0_countOnesLogic_15_9 = (_zz_s0_countOnesLogic_15_10 + _zz_s0_countOnesLogic_15_12); + assign _zz_s0_countOnesLogic_15_14 = (_zz_s0_countOnesLogic_15_15 + _zz_s0_countOnesLogic_15_17); + assign _zz_s0_countOnesLogic_15_19 = (_zz_s0_countOnesLogic_15_20 + _zz_s0_countOnesLogic_15_22); + assign _zz_s0_countOnesLogic_15_24 = s0_input_payload_mask[15]; + assign _zz_s0_countOnesLogic_15_23 = {2'd0, _zz_s0_countOnesLogic_15_24}; + assign _zz_s1_offsetNext = {1'd0, s1_offset}; + assign _zz_s1_byteCounter = {8'd0, s1_input_payload_countOnes_15}; + assign _zz_s1_inputIndexes_1 = {3'd0, s1_input_payload_countOnes_0}; + assign _zz_s1_inputIndexes_2 = {2'd0, s1_input_payload_countOnes_1}; + assign _zz_s1_inputIndexes_3 = {2'd0, s1_input_payload_countOnes_2}; + assign _zz_s1_inputIndexes_4 = {1'd0, s1_input_payload_countOnes_3}; + assign _zz_s1_inputIndexes_5 = {1'd0, s1_input_payload_countOnes_4}; + assign _zz_s1_inputIndexes_6 = {1'd0, s1_input_payload_countOnes_5}; + assign _zz_s1_inputIndexes_7 = {1'd0, s1_input_payload_countOnes_6}; + assign _zz_when_DmaSg_l1464 = {1'd0, io_burstLength}; + assign _zz_s0_countOnesLogic_0_2 = _zz_s0_countOnesLogic_0; + assign _zz_s0_countOnesLogic_1_2 = {_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}; + assign _zz_s0_countOnesLogic_2_2 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_3_10 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_4_10 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_5_10 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_5_12 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_6_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_6_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_7_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_7_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_8_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_8_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_8_15 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_9_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_9_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_9_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_10_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_10_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_10_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_11_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_11_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_11_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_11_18 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; + assign _zz_s0_countOnesLogic_12_12 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_12_14 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_12_17 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_12_19 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; + assign _zz_s0_countOnesLogic_13_12 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_13_14 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_13_17 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_13_19 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; + assign _zz_s0_countOnesLogic_14_12 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_14_14 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_14_17 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_14_19 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; + assign _zz_s0_countOnesLogic_14_21 = {_zz_s0_countOnesLogic_14,{_zz_s0_countOnesLogic_13,_zz_s0_countOnesLogic_12}}; + assign _zz_s0_countOnesLogic_15_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_15_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_15_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_15_18 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; + assign _zz_s0_countOnesLogic_15_21 = {_zz_s0_countOnesLogic_14,{_zz_s0_countOnesLogic_13,_zz_s0_countOnesLogic_12}}; + assign _zz_io_output_usedUntil_5 = {_zz_io_output_usedUntil_3,{_zz_io_output_usedUntil_2,{_zz_io_output_usedUntil_1,_zz_io_output_usedUntil}}}; + assign _zz_s1_outputPayload_selValid_240 = _zz_s1_outputPayload_selValid_6; + assign _zz_s1_outputPayload_selValid_241 = {_zz_s1_outputPayload_selValid_5,{_zz_s1_outputPayload_selValid_4,{_zz_s1_outputPayload_selValid_3,{_zz_s1_outputPayload_selValid_2,{_zz_s1_outputPayload_selValid_1,{_zz_s1_outputPayload_selValid,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0000))}}}}}}; + assign _zz_s1_outputPayload_selValid_242 = _zz_s1_outputPayload_selValid_21; + assign _zz_s1_outputPayload_selValid_243 = {_zz_s1_outputPayload_selValid_20,{_zz_s1_outputPayload_selValid_19,{_zz_s1_outputPayload_selValid_18,{_zz_s1_outputPayload_selValid_17,{_zz_s1_outputPayload_selValid_16,{_zz_s1_outputPayload_selValid_15,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0001))}}}}}}; + assign _zz_s1_outputPayload_selValid_244 = _zz_s1_outputPayload_selValid_36; + assign _zz_s1_outputPayload_selValid_245 = {_zz_s1_outputPayload_selValid_35,{_zz_s1_outputPayload_selValid_34,{_zz_s1_outputPayload_selValid_33,{_zz_s1_outputPayload_selValid_32,{_zz_s1_outputPayload_selValid_31,{_zz_s1_outputPayload_selValid_30,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0010))}}}}}}; + assign _zz_s1_outputPayload_selValid_246 = _zz_s1_outputPayload_selValid_51; + assign _zz_s1_outputPayload_selValid_247 = {_zz_s1_outputPayload_selValid_50,{_zz_s1_outputPayload_selValid_49,{_zz_s1_outputPayload_selValid_48,{_zz_s1_outputPayload_selValid_47,{_zz_s1_outputPayload_selValid_46,{_zz_s1_outputPayload_selValid_45,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0011))}}}}}}; + assign _zz_s1_outputPayload_selValid_248 = _zz_s1_outputPayload_selValid_66; + assign _zz_s1_outputPayload_selValid_249 = {_zz_s1_outputPayload_selValid_65,{_zz_s1_outputPayload_selValid_64,{_zz_s1_outputPayload_selValid_63,{_zz_s1_outputPayload_selValid_62,{_zz_s1_outputPayload_selValid_61,{_zz_s1_outputPayload_selValid_60,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0100))}}}}}}; + assign _zz_s1_outputPayload_selValid_250 = _zz_s1_outputPayload_selValid_81; + assign _zz_s1_outputPayload_selValid_251 = {_zz_s1_outputPayload_selValid_80,{_zz_s1_outputPayload_selValid_79,{_zz_s1_outputPayload_selValid_78,{_zz_s1_outputPayload_selValid_77,{_zz_s1_outputPayload_selValid_76,{_zz_s1_outputPayload_selValid_75,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0101))}}}}}}; + assign _zz_s1_outputPayload_selValid_252 = _zz_s1_outputPayload_selValid_96; + assign _zz_s1_outputPayload_selValid_253 = {_zz_s1_outputPayload_selValid_95,{_zz_s1_outputPayload_selValid_94,{_zz_s1_outputPayload_selValid_93,{_zz_s1_outputPayload_selValid_92,{_zz_s1_outputPayload_selValid_91,{_zz_s1_outputPayload_selValid_90,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0110))}}}}}}; + assign _zz_s1_outputPayload_selValid_254 = _zz_s1_outputPayload_selValid_111; + assign _zz_s1_outputPayload_selValid_255 = {_zz_s1_outputPayload_selValid_110,{_zz_s1_outputPayload_selValid_109,{_zz_s1_outputPayload_selValid_108,{_zz_s1_outputPayload_selValid_107,{_zz_s1_outputPayload_selValid_106,{_zz_s1_outputPayload_selValid_105,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0111))}}}}}}; + assign _zz_s1_outputPayload_selValid_256 = _zz_s1_outputPayload_selValid_126; + assign _zz_s1_outputPayload_selValid_257 = {_zz_s1_outputPayload_selValid_125,{_zz_s1_outputPayload_selValid_124,{_zz_s1_outputPayload_selValid_123,{_zz_s1_outputPayload_selValid_122,{_zz_s1_outputPayload_selValid_121,{_zz_s1_outputPayload_selValid_120,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1000))}}}}}}; + assign _zz_s1_outputPayload_selValid_258 = _zz_s1_outputPayload_selValid_141; + assign _zz_s1_outputPayload_selValid_259 = {_zz_s1_outputPayload_selValid_140,{_zz_s1_outputPayload_selValid_139,{_zz_s1_outputPayload_selValid_138,{_zz_s1_outputPayload_selValid_137,{_zz_s1_outputPayload_selValid_136,{_zz_s1_outputPayload_selValid_135,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1001))}}}}}}; + assign _zz_s1_outputPayload_selValid_260 = _zz_s1_outputPayload_selValid_156; + assign _zz_s1_outputPayload_selValid_261 = {_zz_s1_outputPayload_selValid_155,{_zz_s1_outputPayload_selValid_154,{_zz_s1_outputPayload_selValid_153,{_zz_s1_outputPayload_selValid_152,{_zz_s1_outputPayload_selValid_151,{_zz_s1_outputPayload_selValid_150,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1010))}}}}}}; + assign _zz_s1_outputPayload_selValid_262 = _zz_s1_outputPayload_selValid_171; + assign _zz_s1_outputPayload_selValid_263 = {_zz_s1_outputPayload_selValid_170,{_zz_s1_outputPayload_selValid_169,{_zz_s1_outputPayload_selValid_168,{_zz_s1_outputPayload_selValid_167,{_zz_s1_outputPayload_selValid_166,{_zz_s1_outputPayload_selValid_165,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1011))}}}}}}; + assign _zz_s1_outputPayload_selValid_264 = _zz_s1_outputPayload_selValid_186; + assign _zz_s1_outputPayload_selValid_265 = {_zz_s1_outputPayload_selValid_185,{_zz_s1_outputPayload_selValid_184,{_zz_s1_outputPayload_selValid_183,{_zz_s1_outputPayload_selValid_182,{_zz_s1_outputPayload_selValid_181,{_zz_s1_outputPayload_selValid_180,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1100))}}}}}}; + assign _zz_s1_outputPayload_selValid_266 = _zz_s1_outputPayload_selValid_201; + assign _zz_s1_outputPayload_selValid_267 = {_zz_s1_outputPayload_selValid_200,{_zz_s1_outputPayload_selValid_199,{_zz_s1_outputPayload_selValid_198,{_zz_s1_outputPayload_selValid_197,{_zz_s1_outputPayload_selValid_196,{_zz_s1_outputPayload_selValid_195,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1101))}}}}}}; + assign _zz_s1_outputPayload_selValid_268 = _zz_s1_outputPayload_selValid_216; + assign _zz_s1_outputPayload_selValid_269 = {_zz_s1_outputPayload_selValid_215,{_zz_s1_outputPayload_selValid_214,{_zz_s1_outputPayload_selValid_213,{_zz_s1_outputPayload_selValid_212,{_zz_s1_outputPayload_selValid_211,{_zz_s1_outputPayload_selValid_210,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1110))}}}}}}; + assign _zz_s1_outputPayload_selValid_270 = _zz_s1_outputPayload_selValid_231; + assign _zz_s1_outputPayload_selValid_271 = {_zz_s1_outputPayload_selValid_230,{_zz_s1_outputPayload_selValid_229,{_zz_s1_outputPayload_selValid_228,{_zz_s1_outputPayload_selValid_227,{_zz_s1_outputPayload_selValid_226,{_zz_s1_outputPayload_selValid_225,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1111))}}}}}}; + always @(*) begin + case(_zz_s0_countOnesLogic_0_2) + 1'b0 : _zz_s0_countOnesLogic_0_1 = 1'b0; + default : _zz_s0_countOnesLogic_0_1 = 1'b1; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_1_2) + 2'b00 : _zz_s0_countOnesLogic_1_1 = 2'b00; + 2'b01 : _zz_s0_countOnesLogic_1_1 = 2'b01; + 2'b10 : _zz_s0_countOnesLogic_1_1 = 2'b01; + default : _zz_s0_countOnesLogic_1_1 = 2'b10; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_2_2) + 3'b000 : _zz_s0_countOnesLogic_2_1 = 2'b00; + 3'b001 : _zz_s0_countOnesLogic_2_1 = 2'b01; + 3'b010 : _zz_s0_countOnesLogic_2_1 = 2'b01; + 3'b011 : _zz_s0_countOnesLogic_2_1 = 2'b10; + 3'b100 : _zz_s0_countOnesLogic_2_1 = 2'b01; + 3'b101 : _zz_s0_countOnesLogic_2_1 = 2'b10; + 3'b110 : _zz_s0_countOnesLogic_2_1 = 2'b10; + default : _zz_s0_countOnesLogic_2_1 = 2'b11; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_3_10) + 3'b000 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_1; + 3'b001 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_2; + 3'b010 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_3; + 3'b011 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_4; + 3'b100 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_5; + 3'b101 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_6; + 3'b110 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_7; + default : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_3_12) + 3'b000 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_1; + 3'b001 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_2; + 3'b010 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_3; + 3'b011 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_4; + 3'b100 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_5; + 3'b101 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_6; + 3'b110 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_7; + default : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_4_10) + 3'b000 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_1; + 3'b001 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_2; + 3'b010 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_3; + 3'b011 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_4; + 3'b100 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_5; + 3'b101 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_6; + 3'b110 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_7; + default : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_4_12) + 3'b000 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_1; + 3'b001 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_2; + 3'b010 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_3; + 3'b011 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_4; + 3'b100 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_5; + 3'b101 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_6; + 3'b110 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_7; + default : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_5_10) + 3'b000 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_1; + 3'b001 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_2; + 3'b010 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_3; + 3'b011 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_4; + 3'b100 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_5; + 3'b101 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_6; + 3'b110 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_7; + default : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_5_12) + 3'b000 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_1; + 3'b001 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_2; + 3'b010 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_3; + 3'b011 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_4; + 3'b100 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_5; + 3'b101 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_6; + 3'b110 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_7; + default : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_6_11) + 3'b000 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_1; + 3'b001 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_2; + 3'b010 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_3; + 3'b011 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_4; + 3'b100 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_5; + 3'b101 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_6; + 3'b110 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_7; + default : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_6_13) + 3'b000 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_1; + 3'b001 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_2; + 3'b010 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_3; + 3'b011 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_4; + 3'b100 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_5; + 3'b101 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_6; + 3'b110 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_7; + default : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_6_15) + 3'b000 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_1; + 3'b001 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_2; + 3'b010 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_3; + 3'b011 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_4; + 3'b100 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_5; + 3'b101 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_6; + 3'b110 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_7; + default : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_7_11) + 3'b000 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_1; + 3'b001 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_2; + 3'b010 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_3; + 3'b011 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_4; + 3'b100 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_5; + 3'b101 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_6; + 3'b110 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_7; + default : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_7_13) + 3'b000 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_1; + 3'b001 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_2; + 3'b010 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_3; + 3'b011 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_4; + 3'b100 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_5; + 3'b101 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_6; + 3'b110 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_7; + default : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_7_15) + 3'b000 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_1; + 3'b001 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_2; + 3'b010 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_3; + 3'b011 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_4; + 3'b100 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_5; + 3'b101 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_6; + 3'b110 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_7; + default : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_8_11) + 3'b000 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_1; + 3'b001 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_2; + 3'b010 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_3; + 3'b011 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_4; + 3'b100 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_5; + 3'b101 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_6; + 3'b110 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_7; + default : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_8_13) + 3'b000 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_1; + 3'b001 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_2; + 3'b010 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_3; + 3'b011 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_4; + 3'b100 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_5; + 3'b101 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_6; + 3'b110 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_7; + default : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_8_15) + 3'b000 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_1; + 3'b001 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_2; + 3'b010 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_3; + 3'b011 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_4; + 3'b100 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_5; + 3'b101 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_6; + 3'b110 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_7; + default : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_9_11) + 3'b000 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_1; + 3'b001 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_2; + 3'b010 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_3; + 3'b011 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_4; + 3'b100 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_5; + 3'b101 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_6; + 3'b110 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_7; + default : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_9_13) + 3'b000 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_1; + 3'b001 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_2; + 3'b010 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_3; + 3'b011 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_4; + 3'b100 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_5; + 3'b101 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_6; + 3'b110 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_7; + default : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_9_16) + 3'b000 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_1; + 3'b001 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_2; + 3'b010 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_3; + 3'b011 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_4; + 3'b100 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_5; + 3'b101 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_6; + 3'b110 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_7; + default : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_9_18) + 3'b000 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_1; + 3'b001 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_2; + 3'b010 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_3; + 3'b011 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_4; + 3'b100 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_5; + 3'b101 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_6; + 3'b110 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_7; + default : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_10_11) + 3'b000 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_1; + 3'b001 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_2; + 3'b010 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_3; + 3'b011 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_4; + 3'b100 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_5; + 3'b101 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_6; + 3'b110 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_7; + default : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_10_13) + 3'b000 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_1; + 3'b001 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_2; + 3'b010 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_3; + 3'b011 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_4; + 3'b100 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_5; + 3'b101 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_6; + 3'b110 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_7; + default : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_10_16) + 3'b000 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_1; + 3'b001 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_2; + 3'b010 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_3; + 3'b011 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_4; + 3'b100 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_5; + 3'b101 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_6; + 3'b110 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_7; + default : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_10_18) + 3'b000 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_1; + 3'b001 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_2; + 3'b010 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_3; + 3'b011 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_4; + 3'b100 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_5; + 3'b101 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_6; + 3'b110 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_7; + default : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_11_11) + 3'b000 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_1; + 3'b001 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_2; + 3'b010 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_3; + 3'b011 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_4; + 3'b100 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_5; + 3'b101 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_6; + 3'b110 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_7; + default : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_11_13) + 3'b000 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_1; + 3'b001 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_2; + 3'b010 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_3; + 3'b011 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_4; + 3'b100 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_5; + 3'b101 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_6; + 3'b110 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_7; + default : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_11_16) + 3'b000 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_1; + 3'b001 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_2; + 3'b010 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_3; + 3'b011 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_4; + 3'b100 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_5; + 3'b101 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_6; + 3'b110 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_7; + default : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_11_18) + 3'b000 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_1; + 3'b001 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_2; + 3'b010 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_3; + 3'b011 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_4; + 3'b100 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_5; + 3'b101 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_6; + 3'b110 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_7; + default : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_12_12) + 3'b000 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_1; + 3'b001 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_2; + 3'b010 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_3; + 3'b011 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_4; + 3'b100 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_5; + 3'b101 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_6; + 3'b110 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_7; + default : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_12_14) + 3'b000 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_1; + 3'b001 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_2; + 3'b010 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_3; + 3'b011 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_4; + 3'b100 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_5; + 3'b101 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_6; + 3'b110 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_7; + default : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_12_17) + 3'b000 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_1; + 3'b001 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_2; + 3'b010 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_3; + 3'b011 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_4; + 3'b100 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_5; + 3'b101 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_6; + 3'b110 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_7; + default : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_12_19) + 3'b000 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_1; + 3'b001 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_2; + 3'b010 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_3; + 3'b011 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_4; + 3'b100 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_5; + 3'b101 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_6; + 3'b110 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_7; + default : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_12_21) + 3'b000 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_1; + 3'b001 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_2; + 3'b010 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_3; + 3'b011 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_4; + 3'b100 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_5; + 3'b101 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_6; + 3'b110 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_7; + default : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_13_12) + 3'b000 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_1; + 3'b001 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_2; + 3'b010 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_3; + 3'b011 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_4; + 3'b100 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_5; + 3'b101 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_6; + 3'b110 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_7; + default : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_13_14) + 3'b000 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_1; + 3'b001 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_2; + 3'b010 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_3; + 3'b011 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_4; + 3'b100 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_5; + 3'b101 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_6; + 3'b110 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_7; + default : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_13_17) + 3'b000 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_1; + 3'b001 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_2; + 3'b010 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_3; + 3'b011 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_4; + 3'b100 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_5; + 3'b101 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_6; + 3'b110 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_7; + default : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_13_19) + 3'b000 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_1; + 3'b001 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_2; + 3'b010 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_3; + 3'b011 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_4; + 3'b100 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_5; + 3'b101 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_6; + 3'b110 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_7; + default : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_13_21) + 3'b000 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_1; + 3'b001 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_2; + 3'b010 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_3; + 3'b011 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_4; + 3'b100 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_5; + 3'b101 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_6; + 3'b110 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_7; + default : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_14_12) + 3'b000 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_1; + 3'b001 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_2; + 3'b010 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_3; + 3'b011 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_4; + 3'b100 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_5; + 3'b101 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_6; + 3'b110 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_7; + default : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_14_14) + 3'b000 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_1; + 3'b001 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_2; + 3'b010 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_3; + 3'b011 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_4; + 3'b100 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_5; + 3'b101 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_6; + 3'b110 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_7; + default : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_14_17) + 3'b000 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_1; + 3'b001 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_2; + 3'b010 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_3; + 3'b011 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_4; + 3'b100 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_5; + 3'b101 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_6; + 3'b110 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_7; + default : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_14_19) + 3'b000 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_1; + 3'b001 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_2; + 3'b010 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_3; + 3'b011 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_4; + 3'b100 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_5; + 3'b101 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_6; + 3'b110 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_7; + default : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_14_21) + 3'b000 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_1; + 3'b001 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_2; + 3'b010 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_3; + 3'b011 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_4; + 3'b100 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_5; + 3'b101 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_6; + 3'b110 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_7; + default : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_11) + 3'b000 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_13) + 3'b000 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_16) + 3'b000 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_18) + 3'b000 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_21) + 3'b000 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_23) + 3'b000 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_0) + 4'b0000 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_1) + 4'b0000 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_2) + 4'b0000 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_3) + 4'b0000 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_4) + 4'b0000 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_5) + 4'b0000 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_6) + 4'b0000 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_7) + 4'b0000 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_8) + 4'b0000 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_9) + 4'b0000 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_10) + 4'b0000 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_11) + 4'b0000 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_12) + 4'b0000 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_13) + 4'b0000 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_14) + 4'b0000 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_15) + 4'b0000 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(_zz_io_output_usedUntil_5) + 4'b0000 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_0; + 4'b0001 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_1; + 4'b0010 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_2; + 4'b0011 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_3; + 4'b0100 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_4; + 4'b0101 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_5; + 4'b0110 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_6; + 4'b0111 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_7; + 4'b1000 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_8; + 4'b1001 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_9; + 4'b1010 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_10; + 4'b1011 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_11; + 4'b1100 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_12; + 4'b1101 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_13; + 4'b1110 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_14; + default : _zz_io_output_usedUntil_4 = s2_input_payload_sel_15; + endcase + end + + always @(*) begin + io_input_ready = s0_input_ready; + if(when_Stream_l375) begin + io_input_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! s0_input_valid); + assign s0_input_valid = io_input_rValid; + assign s0_input_payload_data = io_input_rData_data; + assign s0_input_payload_mask = io_input_rData_mask; + assign _zz_s0_countOnesLogic_0 = s0_input_payload_mask[0]; + assign _zz_s0_countOnesLogic_1 = s0_input_payload_mask[1]; + assign _zz_s0_countOnesLogic_2 = s0_input_payload_mask[2]; + assign _zz_s0_countOnesLogic_3 = s0_input_payload_mask[3]; + assign _zz_s0_countOnesLogic_4 = s0_input_payload_mask[4]; + assign _zz_s0_countOnesLogic_5 = s0_input_payload_mask[5]; + assign _zz_s0_countOnesLogic_6 = s0_input_payload_mask[6]; + assign _zz_s0_countOnesLogic_7 = s0_input_payload_mask[7]; + assign _zz_s0_countOnesLogic_8 = s0_input_payload_mask[8]; + assign _zz_s0_countOnesLogic_9 = s0_input_payload_mask[9]; + assign _zz_s0_countOnesLogic_10 = s0_input_payload_mask[10]; + assign _zz_s0_countOnesLogic_11 = s0_input_payload_mask[11]; + assign _zz_s0_countOnesLogic_12 = s0_input_payload_mask[12]; + assign _zz_s0_countOnesLogic_13 = s0_input_payload_mask[13]; + assign _zz_s0_countOnesLogic_14 = s0_input_payload_mask[14]; + assign s0_countOnesLogic_0 = _zz_s0_countOnesLogic_0_1; + assign s0_countOnesLogic_1 = _zz_s0_countOnesLogic_1_1; + assign s0_countOnesLogic_2 = _zz_s0_countOnesLogic_2_1; + assign _zz_s0_countOnesLogic_3_1 = 3'b000; + assign _zz_s0_countOnesLogic_3_2 = 3'b001; + assign _zz_s0_countOnesLogic_3_3 = 3'b001; + assign _zz_s0_countOnesLogic_3_4 = 3'b010; + assign _zz_s0_countOnesLogic_3_5 = 3'b001; + assign _zz_s0_countOnesLogic_3_6 = 3'b010; + assign _zz_s0_countOnesLogic_3_7 = 3'b010; + assign _zz_s0_countOnesLogic_3_8 = 3'b011; + assign s0_countOnesLogic_3 = (_zz_s0_countOnesLogic_3_9 + _zz_s0_countOnesLogic_3_11); + assign _zz_s0_countOnesLogic_4_1 = 3'b000; + assign _zz_s0_countOnesLogic_4_2 = 3'b001; + assign _zz_s0_countOnesLogic_4_3 = 3'b001; + assign _zz_s0_countOnesLogic_4_4 = 3'b010; + assign _zz_s0_countOnesLogic_4_5 = 3'b001; + assign _zz_s0_countOnesLogic_4_6 = 3'b010; + assign _zz_s0_countOnesLogic_4_7 = 3'b010; + assign _zz_s0_countOnesLogic_4_8 = 3'b011; + assign s0_countOnesLogic_4 = (_zz_s0_countOnesLogic_4_9 + _zz_s0_countOnesLogic_4_11); + assign _zz_s0_countOnesLogic_5_1 = 3'b000; + assign _zz_s0_countOnesLogic_5_2 = 3'b001; + assign _zz_s0_countOnesLogic_5_3 = 3'b001; + assign _zz_s0_countOnesLogic_5_4 = 3'b010; + assign _zz_s0_countOnesLogic_5_5 = 3'b001; + assign _zz_s0_countOnesLogic_5_6 = 3'b010; + assign _zz_s0_countOnesLogic_5_7 = 3'b010; + assign _zz_s0_countOnesLogic_5_8 = 3'b011; + assign s0_countOnesLogic_5 = (_zz_s0_countOnesLogic_5_9 + _zz_s0_countOnesLogic_5_11); + assign _zz_s0_countOnesLogic_6_1 = 3'b000; + assign _zz_s0_countOnesLogic_6_2 = 3'b001; + assign _zz_s0_countOnesLogic_6_3 = 3'b001; + assign _zz_s0_countOnesLogic_6_4 = 3'b010; + assign _zz_s0_countOnesLogic_6_5 = 3'b001; + assign _zz_s0_countOnesLogic_6_6 = 3'b010; + assign _zz_s0_countOnesLogic_6_7 = 3'b010; + assign _zz_s0_countOnesLogic_6_8 = 3'b011; + assign s0_countOnesLogic_6 = (_zz_s0_countOnesLogic_6_9 + _zz_s0_countOnesLogic_6_14); + assign _zz_s0_countOnesLogic_7_1 = 4'b0000; + assign _zz_s0_countOnesLogic_7_2 = 4'b0001; + assign _zz_s0_countOnesLogic_7_3 = 4'b0001; + assign _zz_s0_countOnesLogic_7_4 = 4'b0010; + assign _zz_s0_countOnesLogic_7_5 = 4'b0001; + assign _zz_s0_countOnesLogic_7_6 = 4'b0010; + assign _zz_s0_countOnesLogic_7_7 = 4'b0010; + assign _zz_s0_countOnesLogic_7_8 = 4'b0011; + assign s0_countOnesLogic_7 = (_zz_s0_countOnesLogic_7_9 + _zz_s0_countOnesLogic_7_14); + assign _zz_s0_countOnesLogic_8_1 = 4'b0000; + assign _zz_s0_countOnesLogic_8_2 = 4'b0001; + assign _zz_s0_countOnesLogic_8_3 = 4'b0001; + assign _zz_s0_countOnesLogic_8_4 = 4'b0010; + assign _zz_s0_countOnesLogic_8_5 = 4'b0001; + assign _zz_s0_countOnesLogic_8_6 = 4'b0010; + assign _zz_s0_countOnesLogic_8_7 = 4'b0010; + assign _zz_s0_countOnesLogic_8_8 = 4'b0011; + assign s0_countOnesLogic_8 = (_zz_s0_countOnesLogic_8_9 + _zz_s0_countOnesLogic_8_14); + assign _zz_s0_countOnesLogic_9_1 = 4'b0000; + assign _zz_s0_countOnesLogic_9_2 = 4'b0001; + assign _zz_s0_countOnesLogic_9_3 = 4'b0001; + assign _zz_s0_countOnesLogic_9_4 = 4'b0010; + assign _zz_s0_countOnesLogic_9_5 = 4'b0001; + assign _zz_s0_countOnesLogic_9_6 = 4'b0010; + assign _zz_s0_countOnesLogic_9_7 = 4'b0010; + assign _zz_s0_countOnesLogic_9_8 = 4'b0011; + assign s0_countOnesLogic_9 = (_zz_s0_countOnesLogic_9_9 + _zz_s0_countOnesLogic_9_14); + assign _zz_s0_countOnesLogic_10_1 = 4'b0000; + assign _zz_s0_countOnesLogic_10_2 = 4'b0001; + assign _zz_s0_countOnesLogic_10_3 = 4'b0001; + assign _zz_s0_countOnesLogic_10_4 = 4'b0010; + assign _zz_s0_countOnesLogic_10_5 = 4'b0001; + assign _zz_s0_countOnesLogic_10_6 = 4'b0010; + assign _zz_s0_countOnesLogic_10_7 = 4'b0010; + assign _zz_s0_countOnesLogic_10_8 = 4'b0011; + assign s0_countOnesLogic_10 = (_zz_s0_countOnesLogic_10_9 + _zz_s0_countOnesLogic_10_14); + assign _zz_s0_countOnesLogic_11_1 = 4'b0000; + assign _zz_s0_countOnesLogic_11_2 = 4'b0001; + assign _zz_s0_countOnesLogic_11_3 = 4'b0001; + assign _zz_s0_countOnesLogic_11_4 = 4'b0010; + assign _zz_s0_countOnesLogic_11_5 = 4'b0001; + assign _zz_s0_countOnesLogic_11_6 = 4'b0010; + assign _zz_s0_countOnesLogic_11_7 = 4'b0010; + assign _zz_s0_countOnesLogic_11_8 = 4'b0011; + assign s0_countOnesLogic_11 = (_zz_s0_countOnesLogic_11_9 + _zz_s0_countOnesLogic_11_14); + assign _zz_s0_countOnesLogic_12_1 = 4'b0000; + assign _zz_s0_countOnesLogic_12_2 = 4'b0001; + assign _zz_s0_countOnesLogic_12_3 = 4'b0001; + assign _zz_s0_countOnesLogic_12_4 = 4'b0010; + assign _zz_s0_countOnesLogic_12_5 = 4'b0001; + assign _zz_s0_countOnesLogic_12_6 = 4'b0010; + assign _zz_s0_countOnesLogic_12_7 = 4'b0010; + assign _zz_s0_countOnesLogic_12_8 = 4'b0011; + assign s0_countOnesLogic_12 = (_zz_s0_countOnesLogic_12_9 + _zz_s0_countOnesLogic_12_20); + assign _zz_s0_countOnesLogic_13_1 = 4'b0000; + assign _zz_s0_countOnesLogic_13_2 = 4'b0001; + assign _zz_s0_countOnesLogic_13_3 = 4'b0001; + assign _zz_s0_countOnesLogic_13_4 = 4'b0010; + assign _zz_s0_countOnesLogic_13_5 = 4'b0001; + assign _zz_s0_countOnesLogic_13_6 = 4'b0010; + assign _zz_s0_countOnesLogic_13_7 = 4'b0010; + assign _zz_s0_countOnesLogic_13_8 = 4'b0011; + assign s0_countOnesLogic_13 = (_zz_s0_countOnesLogic_13_9 + _zz_s0_countOnesLogic_13_20); + assign _zz_s0_countOnesLogic_14_1 = 4'b0000; + assign _zz_s0_countOnesLogic_14_2 = 4'b0001; + assign _zz_s0_countOnesLogic_14_3 = 4'b0001; + assign _zz_s0_countOnesLogic_14_4 = 4'b0010; + assign _zz_s0_countOnesLogic_14_5 = 4'b0001; + assign _zz_s0_countOnesLogic_14_6 = 4'b0010; + assign _zz_s0_countOnesLogic_14_7 = 4'b0010; + assign _zz_s0_countOnesLogic_14_8 = 4'b0011; + assign s0_countOnesLogic_14 = (_zz_s0_countOnesLogic_14_9 + _zz_s0_countOnesLogic_14_20); + assign _zz_s0_countOnesLogic_15 = 5'h0; + assign _zz_s0_countOnesLogic_15_1 = 5'h01; + assign _zz_s0_countOnesLogic_15_2 = 5'h01; + assign _zz_s0_countOnesLogic_15_3 = 5'h02; + assign _zz_s0_countOnesLogic_15_4 = 5'h01; + assign _zz_s0_countOnesLogic_15_5 = 5'h02; + assign _zz_s0_countOnesLogic_15_6 = 5'h02; + assign _zz_s0_countOnesLogic_15_7 = 5'h03; + assign s0_countOnesLogic_15 = (_zz_s0_countOnesLogic_15_8 + _zz_s0_countOnesLogic_15_19); + assign s0_outputPayload_cmd_data = s0_input_payload_data; + assign s0_outputPayload_cmd_mask = s0_input_payload_mask; + assign s0_outputPayload_countOnes_0 = s0_countOnesLogic_0; + assign s0_outputPayload_countOnes_1 = s0_countOnesLogic_1; + assign s0_outputPayload_countOnes_2 = s0_countOnesLogic_2; + assign s0_outputPayload_countOnes_3 = s0_countOnesLogic_3; + assign s0_outputPayload_countOnes_4 = s0_countOnesLogic_4; + assign s0_outputPayload_countOnes_5 = s0_countOnesLogic_5; + assign s0_outputPayload_countOnes_6 = s0_countOnesLogic_6; + assign s0_outputPayload_countOnes_7 = s0_countOnesLogic_7; + assign s0_outputPayload_countOnes_8 = s0_countOnesLogic_8; + assign s0_outputPayload_countOnes_9 = s0_countOnesLogic_9; + assign s0_outputPayload_countOnes_10 = s0_countOnesLogic_10; + assign s0_outputPayload_countOnes_11 = s0_countOnesLogic_11; + assign s0_outputPayload_countOnes_12 = s0_countOnesLogic_12; + assign s0_outputPayload_countOnes_13 = s0_countOnesLogic_13; + assign s0_outputPayload_countOnes_14 = s0_countOnesLogic_14; + assign s0_outputPayload_countOnes_15 = s0_countOnesLogic_15; + assign s0_output_valid = s0_input_valid; + assign s0_input_ready = s0_output_ready; + assign s0_output_payload_cmd_data = s0_outputPayload_cmd_data; + assign s0_output_payload_cmd_mask = s0_outputPayload_cmd_mask; + assign s0_output_payload_countOnes_0 = s0_outputPayload_countOnes_0; + assign s0_output_payload_countOnes_1 = s0_outputPayload_countOnes_1; + assign s0_output_payload_countOnes_2 = s0_outputPayload_countOnes_2; + assign s0_output_payload_countOnes_3 = s0_outputPayload_countOnes_3; + assign s0_output_payload_countOnes_4 = s0_outputPayload_countOnes_4; + assign s0_output_payload_countOnes_5 = s0_outputPayload_countOnes_5; + assign s0_output_payload_countOnes_6 = s0_outputPayload_countOnes_6; + assign s0_output_payload_countOnes_7 = s0_outputPayload_countOnes_7; + assign s0_output_payload_countOnes_8 = s0_outputPayload_countOnes_8; + assign s0_output_payload_countOnes_9 = s0_outputPayload_countOnes_9; + assign s0_output_payload_countOnes_10 = s0_outputPayload_countOnes_10; + assign s0_output_payload_countOnes_11 = s0_outputPayload_countOnes_11; + assign s0_output_payload_countOnes_12 = s0_outputPayload_countOnes_12; + assign s0_output_payload_countOnes_13 = s0_outputPayload_countOnes_13; + assign s0_output_payload_countOnes_14 = s0_outputPayload_countOnes_14; + assign s0_output_payload_countOnes_15 = s0_outputPayload_countOnes_15; + always @(*) begin + s0_output_ready = s1_input_ready; + if(when_Stream_l375_1) begin + s0_output_ready = 1'b1; + end + end + + assign when_Stream_l375_1 = (! s1_input_valid); + assign s1_input_valid = s0_output_rValid; + assign s1_input_payload_cmd_data = s0_output_rData_cmd_data; + assign s1_input_payload_cmd_mask = s0_output_rData_cmd_mask; + assign s1_input_payload_countOnes_0 = s0_output_rData_countOnes_0; + assign s1_input_payload_countOnes_1 = s0_output_rData_countOnes_1; + assign s1_input_payload_countOnes_2 = s0_output_rData_countOnes_2; + assign s1_input_payload_countOnes_3 = s0_output_rData_countOnes_3; + assign s1_input_payload_countOnes_4 = s0_output_rData_countOnes_4; + assign s1_input_payload_countOnes_5 = s0_output_rData_countOnes_5; + assign s1_input_payload_countOnes_6 = s0_output_rData_countOnes_6; + assign s1_input_payload_countOnes_7 = s0_output_rData_countOnes_7; + assign s1_input_payload_countOnes_8 = s0_output_rData_countOnes_8; + assign s1_input_payload_countOnes_9 = s0_output_rData_countOnes_9; + assign s1_input_payload_countOnes_10 = s0_output_rData_countOnes_10; + assign s1_input_payload_countOnes_11 = s0_output_rData_countOnes_11; + assign s1_input_payload_countOnes_12 = s0_output_rData_countOnes_12; + assign s1_input_payload_countOnes_13 = s0_output_rData_countOnes_13; + assign s1_input_payload_countOnes_14 = s0_output_rData_countOnes_14; + assign s1_input_payload_countOnes_15 = s0_output_rData_countOnes_15; + assign s1_offsetNext = (_zz_s1_offsetNext + s1_input_payload_countOnes_15); + assign s1_input_fire = (s1_input_valid && s1_input_ready); + assign s1_inputIndexes_0 = (4'b0000 + s1_offset); + assign s1_inputIndexes_1 = (_zz_s1_inputIndexes_1 + s1_offset); + assign s1_inputIndexes_2 = (_zz_s1_inputIndexes_2 + s1_offset); + assign s1_inputIndexes_3 = (_zz_s1_inputIndexes_3 + s1_offset); + assign s1_inputIndexes_4 = (_zz_s1_inputIndexes_4 + s1_offset); + assign s1_inputIndexes_5 = (_zz_s1_inputIndexes_5 + s1_offset); + assign s1_inputIndexes_6 = (_zz_s1_inputIndexes_6 + s1_offset); + assign s1_inputIndexes_7 = (_zz_s1_inputIndexes_7 + s1_offset); + assign s1_inputIndexes_8 = (s1_input_payload_countOnes_7 + s1_offset); + assign s1_inputIndexes_9 = (s1_input_payload_countOnes_8 + s1_offset); + assign s1_inputIndexes_10 = (s1_input_payload_countOnes_9 + s1_offset); + assign s1_inputIndexes_11 = (s1_input_payload_countOnes_10 + s1_offset); + assign s1_inputIndexes_12 = (s1_input_payload_countOnes_11 + s1_offset); + assign s1_inputIndexes_13 = (s1_input_payload_countOnes_12 + s1_offset); + assign s1_inputIndexes_14 = (s1_input_payload_countOnes_13 + s1_offset); + assign s1_inputIndexes_15 = (s1_input_payload_countOnes_14 + s1_offset); + assign s1_outputPayload_cmd_data = s1_input_payload_cmd_data; + assign s1_outputPayload_cmd_mask = s1_input_payload_cmd_mask; + assign s1_outputPayload_index_0 = s1_inputIndexes_0; + assign s1_outputPayload_index_1 = s1_inputIndexes_1; + assign s1_outputPayload_index_2 = s1_inputIndexes_2; + assign s1_outputPayload_index_3 = s1_inputIndexes_3; + assign s1_outputPayload_index_4 = s1_inputIndexes_4; + assign s1_outputPayload_index_5 = s1_inputIndexes_5; + assign s1_outputPayload_index_6 = s1_inputIndexes_6; + assign s1_outputPayload_index_7 = s1_inputIndexes_7; + assign s1_outputPayload_index_8 = s1_inputIndexes_8; + assign s1_outputPayload_index_9 = s1_inputIndexes_9; + assign s1_outputPayload_index_10 = s1_inputIndexes_10; + assign s1_outputPayload_index_11 = s1_inputIndexes_11; + assign s1_outputPayload_index_12 = s1_inputIndexes_12; + assign s1_outputPayload_index_13 = s1_inputIndexes_13; + assign s1_outputPayload_index_14 = s1_inputIndexes_14; + assign s1_outputPayload_index_15 = s1_inputIndexes_15; + assign s1_outputPayload_last = s1_offsetNext[4]; + assign _zz_s1_outputPayload_selValid = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_1 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_2 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_3 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_4 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_5 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_6 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_7 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_8 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_9 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_10 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_11 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_12 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_13 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_14 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0000)); + assign _zz_s1_outputPayload_sel_0 = (((((((_zz_s1_outputPayload_selValid || _zz_s1_outputPayload_selValid_2) || _zz_s1_outputPayload_selValid_4) || _zz_s1_outputPayload_selValid_6) || _zz_s1_outputPayload_selValid_8) || _zz_s1_outputPayload_selValid_10) || _zz_s1_outputPayload_selValid_12) || _zz_s1_outputPayload_selValid_14); + assign _zz_s1_outputPayload_sel_0_1 = (((((((_zz_s1_outputPayload_selValid_1 || _zz_s1_outputPayload_selValid_2) || _zz_s1_outputPayload_selValid_5) || _zz_s1_outputPayload_selValid_6) || _zz_s1_outputPayload_selValid_9) || _zz_s1_outputPayload_selValid_10) || _zz_s1_outputPayload_selValid_13) || _zz_s1_outputPayload_selValid_14); + assign _zz_s1_outputPayload_sel_0_2 = (((((((_zz_s1_outputPayload_selValid_3 || _zz_s1_outputPayload_selValid_4) || _zz_s1_outputPayload_selValid_5) || _zz_s1_outputPayload_selValid_6) || _zz_s1_outputPayload_selValid_11) || _zz_s1_outputPayload_selValid_12) || _zz_s1_outputPayload_selValid_13) || _zz_s1_outputPayload_selValid_14); + assign _zz_s1_outputPayload_sel_0_3 = (((((((_zz_s1_outputPayload_selValid_7 || _zz_s1_outputPayload_selValid_8) || _zz_s1_outputPayload_selValid_9) || _zz_s1_outputPayload_selValid_10) || _zz_s1_outputPayload_selValid_11) || _zz_s1_outputPayload_selValid_12) || _zz_s1_outputPayload_selValid_13) || _zz_s1_outputPayload_selValid_14); + assign s1_outputPayload_sel_0 = {_zz_s1_outputPayload_sel_0_3,{_zz_s1_outputPayload_sel_0_2,{_zz_s1_outputPayload_sel_0_1,_zz_s1_outputPayload_sel_0}}}; + always @(*) begin + s1_outputPayload_selValid[0] = ((|{_zz_s1_outputPayload_selValid_14,{_zz_s1_outputPayload_selValid_13,{_zz_s1_outputPayload_selValid_12,{_zz_s1_outputPayload_selValid_11,{_zz_s1_outputPayload_selValid_10,{_zz_s1_outputPayload_selValid_9,{_zz_s1_outputPayload_selValid_8,{_zz_s1_outputPayload_selValid_7,{_zz_s1_outputPayload_selValid_240,_zz_s1_outputPayload_selValid_241}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_0]); + s1_outputPayload_selValid[1] = ((|{_zz_s1_outputPayload_selValid_29,{_zz_s1_outputPayload_selValid_28,{_zz_s1_outputPayload_selValid_27,{_zz_s1_outputPayload_selValid_26,{_zz_s1_outputPayload_selValid_25,{_zz_s1_outputPayload_selValid_24,{_zz_s1_outputPayload_selValid_23,{_zz_s1_outputPayload_selValid_22,{_zz_s1_outputPayload_selValid_242,_zz_s1_outputPayload_selValid_243}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_1]); + s1_outputPayload_selValid[2] = ((|{_zz_s1_outputPayload_selValid_44,{_zz_s1_outputPayload_selValid_43,{_zz_s1_outputPayload_selValid_42,{_zz_s1_outputPayload_selValid_41,{_zz_s1_outputPayload_selValid_40,{_zz_s1_outputPayload_selValid_39,{_zz_s1_outputPayload_selValid_38,{_zz_s1_outputPayload_selValid_37,{_zz_s1_outputPayload_selValid_244,_zz_s1_outputPayload_selValid_245}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_2]); + s1_outputPayload_selValid[3] = ((|{_zz_s1_outputPayload_selValid_59,{_zz_s1_outputPayload_selValid_58,{_zz_s1_outputPayload_selValid_57,{_zz_s1_outputPayload_selValid_56,{_zz_s1_outputPayload_selValid_55,{_zz_s1_outputPayload_selValid_54,{_zz_s1_outputPayload_selValid_53,{_zz_s1_outputPayload_selValid_52,{_zz_s1_outputPayload_selValid_246,_zz_s1_outputPayload_selValid_247}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_3]); + s1_outputPayload_selValid[4] = ((|{_zz_s1_outputPayload_selValid_74,{_zz_s1_outputPayload_selValid_73,{_zz_s1_outputPayload_selValid_72,{_zz_s1_outputPayload_selValid_71,{_zz_s1_outputPayload_selValid_70,{_zz_s1_outputPayload_selValid_69,{_zz_s1_outputPayload_selValid_68,{_zz_s1_outputPayload_selValid_67,{_zz_s1_outputPayload_selValid_248,_zz_s1_outputPayload_selValid_249}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_4]); + s1_outputPayload_selValid[5] = ((|{_zz_s1_outputPayload_selValid_89,{_zz_s1_outputPayload_selValid_88,{_zz_s1_outputPayload_selValid_87,{_zz_s1_outputPayload_selValid_86,{_zz_s1_outputPayload_selValid_85,{_zz_s1_outputPayload_selValid_84,{_zz_s1_outputPayload_selValid_83,{_zz_s1_outputPayload_selValid_82,{_zz_s1_outputPayload_selValid_250,_zz_s1_outputPayload_selValid_251}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_5]); + s1_outputPayload_selValid[6] = ((|{_zz_s1_outputPayload_selValid_104,{_zz_s1_outputPayload_selValid_103,{_zz_s1_outputPayload_selValid_102,{_zz_s1_outputPayload_selValid_101,{_zz_s1_outputPayload_selValid_100,{_zz_s1_outputPayload_selValid_99,{_zz_s1_outputPayload_selValid_98,{_zz_s1_outputPayload_selValid_97,{_zz_s1_outputPayload_selValid_252,_zz_s1_outputPayload_selValid_253}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_6]); + s1_outputPayload_selValid[7] = ((|{_zz_s1_outputPayload_selValid_119,{_zz_s1_outputPayload_selValid_118,{_zz_s1_outputPayload_selValid_117,{_zz_s1_outputPayload_selValid_116,{_zz_s1_outputPayload_selValid_115,{_zz_s1_outputPayload_selValid_114,{_zz_s1_outputPayload_selValid_113,{_zz_s1_outputPayload_selValid_112,{_zz_s1_outputPayload_selValid_254,_zz_s1_outputPayload_selValid_255}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_7]); + s1_outputPayload_selValid[8] = ((|{_zz_s1_outputPayload_selValid_134,{_zz_s1_outputPayload_selValid_133,{_zz_s1_outputPayload_selValid_132,{_zz_s1_outputPayload_selValid_131,{_zz_s1_outputPayload_selValid_130,{_zz_s1_outputPayload_selValid_129,{_zz_s1_outputPayload_selValid_128,{_zz_s1_outputPayload_selValid_127,{_zz_s1_outputPayload_selValid_256,_zz_s1_outputPayload_selValid_257}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_8]); + s1_outputPayload_selValid[9] = ((|{_zz_s1_outputPayload_selValid_149,{_zz_s1_outputPayload_selValid_148,{_zz_s1_outputPayload_selValid_147,{_zz_s1_outputPayload_selValid_146,{_zz_s1_outputPayload_selValid_145,{_zz_s1_outputPayload_selValid_144,{_zz_s1_outputPayload_selValid_143,{_zz_s1_outputPayload_selValid_142,{_zz_s1_outputPayload_selValid_258,_zz_s1_outputPayload_selValid_259}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_9]); + s1_outputPayload_selValid[10] = ((|{_zz_s1_outputPayload_selValid_164,{_zz_s1_outputPayload_selValid_163,{_zz_s1_outputPayload_selValid_162,{_zz_s1_outputPayload_selValid_161,{_zz_s1_outputPayload_selValid_160,{_zz_s1_outputPayload_selValid_159,{_zz_s1_outputPayload_selValid_158,{_zz_s1_outputPayload_selValid_157,{_zz_s1_outputPayload_selValid_260,_zz_s1_outputPayload_selValid_261}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_10]); + s1_outputPayload_selValid[11] = ((|{_zz_s1_outputPayload_selValid_179,{_zz_s1_outputPayload_selValid_178,{_zz_s1_outputPayload_selValid_177,{_zz_s1_outputPayload_selValid_176,{_zz_s1_outputPayload_selValid_175,{_zz_s1_outputPayload_selValid_174,{_zz_s1_outputPayload_selValid_173,{_zz_s1_outputPayload_selValid_172,{_zz_s1_outputPayload_selValid_262,_zz_s1_outputPayload_selValid_263}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_11]); + s1_outputPayload_selValid[12] = ((|{_zz_s1_outputPayload_selValid_194,{_zz_s1_outputPayload_selValid_193,{_zz_s1_outputPayload_selValid_192,{_zz_s1_outputPayload_selValid_191,{_zz_s1_outputPayload_selValid_190,{_zz_s1_outputPayload_selValid_189,{_zz_s1_outputPayload_selValid_188,{_zz_s1_outputPayload_selValid_187,{_zz_s1_outputPayload_selValid_264,_zz_s1_outputPayload_selValid_265}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_12]); + s1_outputPayload_selValid[13] = ((|{_zz_s1_outputPayload_selValid_209,{_zz_s1_outputPayload_selValid_208,{_zz_s1_outputPayload_selValid_207,{_zz_s1_outputPayload_selValid_206,{_zz_s1_outputPayload_selValid_205,{_zz_s1_outputPayload_selValid_204,{_zz_s1_outputPayload_selValid_203,{_zz_s1_outputPayload_selValid_202,{_zz_s1_outputPayload_selValid_266,_zz_s1_outputPayload_selValid_267}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_13]); + s1_outputPayload_selValid[14] = ((|{_zz_s1_outputPayload_selValid_224,{_zz_s1_outputPayload_selValid_223,{_zz_s1_outputPayload_selValid_222,{_zz_s1_outputPayload_selValid_221,{_zz_s1_outputPayload_selValid_220,{_zz_s1_outputPayload_selValid_219,{_zz_s1_outputPayload_selValid_218,{_zz_s1_outputPayload_selValid_217,{_zz_s1_outputPayload_selValid_268,_zz_s1_outputPayload_selValid_269}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_14]); + s1_outputPayload_selValid[15] = ((|{_zz_s1_outputPayload_selValid_239,{_zz_s1_outputPayload_selValid_238,{_zz_s1_outputPayload_selValid_237,{_zz_s1_outputPayload_selValid_236,{_zz_s1_outputPayload_selValid_235,{_zz_s1_outputPayload_selValid_234,{_zz_s1_outputPayload_selValid_233,{_zz_s1_outputPayload_selValid_232,{_zz_s1_outputPayload_selValid_270,_zz_s1_outputPayload_selValid_271}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_15]); + end + + assign _zz_s1_outputPayload_selValid_15 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_16 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_17 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_18 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_19 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_20 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_21 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_22 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_23 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_24 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_25 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_26 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_27 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_28 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_29 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0001)); + assign _zz_s1_outputPayload_sel_1 = (((((((_zz_s1_outputPayload_selValid_15 || _zz_s1_outputPayload_selValid_17) || _zz_s1_outputPayload_selValid_19) || _zz_s1_outputPayload_selValid_21) || _zz_s1_outputPayload_selValid_23) || _zz_s1_outputPayload_selValid_25) || _zz_s1_outputPayload_selValid_27) || _zz_s1_outputPayload_selValid_29); + assign _zz_s1_outputPayload_sel_1_1 = (((((((_zz_s1_outputPayload_selValid_16 || _zz_s1_outputPayload_selValid_17) || _zz_s1_outputPayload_selValid_20) || _zz_s1_outputPayload_selValid_21) || _zz_s1_outputPayload_selValid_24) || _zz_s1_outputPayload_selValid_25) || _zz_s1_outputPayload_selValid_28) || _zz_s1_outputPayload_selValid_29); + assign _zz_s1_outputPayload_sel_1_2 = (((((((_zz_s1_outputPayload_selValid_18 || _zz_s1_outputPayload_selValid_19) || _zz_s1_outputPayload_selValid_20) || _zz_s1_outputPayload_selValid_21) || _zz_s1_outputPayload_selValid_26) || _zz_s1_outputPayload_selValid_27) || _zz_s1_outputPayload_selValid_28) || _zz_s1_outputPayload_selValid_29); + assign _zz_s1_outputPayload_sel_1_3 = (((((((_zz_s1_outputPayload_selValid_22 || _zz_s1_outputPayload_selValid_23) || _zz_s1_outputPayload_selValid_24) || _zz_s1_outputPayload_selValid_25) || _zz_s1_outputPayload_selValid_26) || _zz_s1_outputPayload_selValid_27) || _zz_s1_outputPayload_selValid_28) || _zz_s1_outputPayload_selValid_29); + assign s1_outputPayload_sel_1 = {_zz_s1_outputPayload_sel_1_3,{_zz_s1_outputPayload_sel_1_2,{_zz_s1_outputPayload_sel_1_1,_zz_s1_outputPayload_sel_1}}}; + assign _zz_s1_outputPayload_selValid_30 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_31 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_32 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_33 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_34 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_35 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_36 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_37 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_38 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_39 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_40 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_41 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_42 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_43 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_44 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0010)); + assign _zz_s1_outputPayload_sel_2 = (((((((_zz_s1_outputPayload_selValid_30 || _zz_s1_outputPayload_selValid_32) || _zz_s1_outputPayload_selValid_34) || _zz_s1_outputPayload_selValid_36) || _zz_s1_outputPayload_selValid_38) || _zz_s1_outputPayload_selValid_40) || _zz_s1_outputPayload_selValid_42) || _zz_s1_outputPayload_selValid_44); + assign _zz_s1_outputPayload_sel_2_1 = (((((((_zz_s1_outputPayload_selValid_31 || _zz_s1_outputPayload_selValid_32) || _zz_s1_outputPayload_selValid_35) || _zz_s1_outputPayload_selValid_36) || _zz_s1_outputPayload_selValid_39) || _zz_s1_outputPayload_selValid_40) || _zz_s1_outputPayload_selValid_43) || _zz_s1_outputPayload_selValid_44); + assign _zz_s1_outputPayload_sel_2_2 = (((((((_zz_s1_outputPayload_selValid_33 || _zz_s1_outputPayload_selValid_34) || _zz_s1_outputPayload_selValid_35) || _zz_s1_outputPayload_selValid_36) || _zz_s1_outputPayload_selValid_41) || _zz_s1_outputPayload_selValid_42) || _zz_s1_outputPayload_selValid_43) || _zz_s1_outputPayload_selValid_44); + assign _zz_s1_outputPayload_sel_2_3 = (((((((_zz_s1_outputPayload_selValid_37 || _zz_s1_outputPayload_selValid_38) || _zz_s1_outputPayload_selValid_39) || _zz_s1_outputPayload_selValid_40) || _zz_s1_outputPayload_selValid_41) || _zz_s1_outputPayload_selValid_42) || _zz_s1_outputPayload_selValid_43) || _zz_s1_outputPayload_selValid_44); + assign s1_outputPayload_sel_2 = {_zz_s1_outputPayload_sel_2_3,{_zz_s1_outputPayload_sel_2_2,{_zz_s1_outputPayload_sel_2_1,_zz_s1_outputPayload_sel_2}}}; + assign _zz_s1_outputPayload_selValid_45 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_46 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_47 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_48 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_49 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_50 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_51 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_52 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_53 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_54 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_55 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_56 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_57 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_58 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_59 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0011)); + assign _zz_s1_outputPayload_sel_3 = (((((((_zz_s1_outputPayload_selValid_45 || _zz_s1_outputPayload_selValid_47) || _zz_s1_outputPayload_selValid_49) || _zz_s1_outputPayload_selValid_51) || _zz_s1_outputPayload_selValid_53) || _zz_s1_outputPayload_selValid_55) || _zz_s1_outputPayload_selValid_57) || _zz_s1_outputPayload_selValid_59); + assign _zz_s1_outputPayload_sel_3_1 = (((((((_zz_s1_outputPayload_selValid_46 || _zz_s1_outputPayload_selValid_47) || _zz_s1_outputPayload_selValid_50) || _zz_s1_outputPayload_selValid_51) || _zz_s1_outputPayload_selValid_54) || _zz_s1_outputPayload_selValid_55) || _zz_s1_outputPayload_selValid_58) || _zz_s1_outputPayload_selValid_59); + assign _zz_s1_outputPayload_sel_3_2 = (((((((_zz_s1_outputPayload_selValid_48 || _zz_s1_outputPayload_selValid_49) || _zz_s1_outputPayload_selValid_50) || _zz_s1_outputPayload_selValid_51) || _zz_s1_outputPayload_selValid_56) || _zz_s1_outputPayload_selValid_57) || _zz_s1_outputPayload_selValid_58) || _zz_s1_outputPayload_selValid_59); + assign _zz_s1_outputPayload_sel_3_3 = (((((((_zz_s1_outputPayload_selValid_52 || _zz_s1_outputPayload_selValid_53) || _zz_s1_outputPayload_selValid_54) || _zz_s1_outputPayload_selValid_55) || _zz_s1_outputPayload_selValid_56) || _zz_s1_outputPayload_selValid_57) || _zz_s1_outputPayload_selValid_58) || _zz_s1_outputPayload_selValid_59); + assign s1_outputPayload_sel_3 = {_zz_s1_outputPayload_sel_3_3,{_zz_s1_outputPayload_sel_3_2,{_zz_s1_outputPayload_sel_3_1,_zz_s1_outputPayload_sel_3}}}; + assign _zz_s1_outputPayload_selValid_60 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_61 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_62 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_63 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_64 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_65 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_66 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_67 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_68 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_69 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_70 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_71 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_72 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_73 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_74 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0100)); + assign _zz_s1_outputPayload_sel_4 = (((((((_zz_s1_outputPayload_selValid_60 || _zz_s1_outputPayload_selValid_62) || _zz_s1_outputPayload_selValid_64) || _zz_s1_outputPayload_selValid_66) || _zz_s1_outputPayload_selValid_68) || _zz_s1_outputPayload_selValid_70) || _zz_s1_outputPayload_selValid_72) || _zz_s1_outputPayload_selValid_74); + assign _zz_s1_outputPayload_sel_4_1 = (((((((_zz_s1_outputPayload_selValid_61 || _zz_s1_outputPayload_selValid_62) || _zz_s1_outputPayload_selValid_65) || _zz_s1_outputPayload_selValid_66) || _zz_s1_outputPayload_selValid_69) || _zz_s1_outputPayload_selValid_70) || _zz_s1_outputPayload_selValid_73) || _zz_s1_outputPayload_selValid_74); + assign _zz_s1_outputPayload_sel_4_2 = (((((((_zz_s1_outputPayload_selValid_63 || _zz_s1_outputPayload_selValid_64) || _zz_s1_outputPayload_selValid_65) || _zz_s1_outputPayload_selValid_66) || _zz_s1_outputPayload_selValid_71) || _zz_s1_outputPayload_selValid_72) || _zz_s1_outputPayload_selValid_73) || _zz_s1_outputPayload_selValid_74); + assign _zz_s1_outputPayload_sel_4_3 = (((((((_zz_s1_outputPayload_selValid_67 || _zz_s1_outputPayload_selValid_68) || _zz_s1_outputPayload_selValid_69) || _zz_s1_outputPayload_selValid_70) || _zz_s1_outputPayload_selValid_71) || _zz_s1_outputPayload_selValid_72) || _zz_s1_outputPayload_selValid_73) || _zz_s1_outputPayload_selValid_74); + assign s1_outputPayload_sel_4 = {_zz_s1_outputPayload_sel_4_3,{_zz_s1_outputPayload_sel_4_2,{_zz_s1_outputPayload_sel_4_1,_zz_s1_outputPayload_sel_4}}}; + assign _zz_s1_outputPayload_selValid_75 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_76 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_77 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_78 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_79 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_80 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_81 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_82 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_83 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_84 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_85 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_86 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_87 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_88 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_89 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0101)); + assign _zz_s1_outputPayload_sel_5 = (((((((_zz_s1_outputPayload_selValid_75 || _zz_s1_outputPayload_selValid_77) || _zz_s1_outputPayload_selValid_79) || _zz_s1_outputPayload_selValid_81) || _zz_s1_outputPayload_selValid_83) || _zz_s1_outputPayload_selValid_85) || _zz_s1_outputPayload_selValid_87) || _zz_s1_outputPayload_selValid_89); + assign _zz_s1_outputPayload_sel_5_1 = (((((((_zz_s1_outputPayload_selValid_76 || _zz_s1_outputPayload_selValid_77) || _zz_s1_outputPayload_selValid_80) || _zz_s1_outputPayload_selValid_81) || _zz_s1_outputPayload_selValid_84) || _zz_s1_outputPayload_selValid_85) || _zz_s1_outputPayload_selValid_88) || _zz_s1_outputPayload_selValid_89); + assign _zz_s1_outputPayload_sel_5_2 = (((((((_zz_s1_outputPayload_selValid_78 || _zz_s1_outputPayload_selValid_79) || _zz_s1_outputPayload_selValid_80) || _zz_s1_outputPayload_selValid_81) || _zz_s1_outputPayload_selValid_86) || _zz_s1_outputPayload_selValid_87) || _zz_s1_outputPayload_selValid_88) || _zz_s1_outputPayload_selValid_89); + assign _zz_s1_outputPayload_sel_5_3 = (((((((_zz_s1_outputPayload_selValid_82 || _zz_s1_outputPayload_selValid_83) || _zz_s1_outputPayload_selValid_84) || _zz_s1_outputPayload_selValid_85) || _zz_s1_outputPayload_selValid_86) || _zz_s1_outputPayload_selValid_87) || _zz_s1_outputPayload_selValid_88) || _zz_s1_outputPayload_selValid_89); + assign s1_outputPayload_sel_5 = {_zz_s1_outputPayload_sel_5_3,{_zz_s1_outputPayload_sel_5_2,{_zz_s1_outputPayload_sel_5_1,_zz_s1_outputPayload_sel_5}}}; + assign _zz_s1_outputPayload_selValid_90 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_91 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_92 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_93 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_94 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_95 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_96 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_97 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_98 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_99 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_100 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_101 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_102 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_103 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_104 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0110)); + assign _zz_s1_outputPayload_sel_6 = (((((((_zz_s1_outputPayload_selValid_90 || _zz_s1_outputPayload_selValid_92) || _zz_s1_outputPayload_selValid_94) || _zz_s1_outputPayload_selValid_96) || _zz_s1_outputPayload_selValid_98) || _zz_s1_outputPayload_selValid_100) || _zz_s1_outputPayload_selValid_102) || _zz_s1_outputPayload_selValid_104); + assign _zz_s1_outputPayload_sel_6_1 = (((((((_zz_s1_outputPayload_selValid_91 || _zz_s1_outputPayload_selValid_92) || _zz_s1_outputPayload_selValid_95) || _zz_s1_outputPayload_selValid_96) || _zz_s1_outputPayload_selValid_99) || _zz_s1_outputPayload_selValid_100) || _zz_s1_outputPayload_selValid_103) || _zz_s1_outputPayload_selValid_104); + assign _zz_s1_outputPayload_sel_6_2 = (((((((_zz_s1_outputPayload_selValid_93 || _zz_s1_outputPayload_selValid_94) || _zz_s1_outputPayload_selValid_95) || _zz_s1_outputPayload_selValid_96) || _zz_s1_outputPayload_selValid_101) || _zz_s1_outputPayload_selValid_102) || _zz_s1_outputPayload_selValid_103) || _zz_s1_outputPayload_selValid_104); + assign _zz_s1_outputPayload_sel_6_3 = (((((((_zz_s1_outputPayload_selValid_97 || _zz_s1_outputPayload_selValid_98) || _zz_s1_outputPayload_selValid_99) || _zz_s1_outputPayload_selValid_100) || _zz_s1_outputPayload_selValid_101) || _zz_s1_outputPayload_selValid_102) || _zz_s1_outputPayload_selValid_103) || _zz_s1_outputPayload_selValid_104); + assign s1_outputPayload_sel_6 = {_zz_s1_outputPayload_sel_6_3,{_zz_s1_outputPayload_sel_6_2,{_zz_s1_outputPayload_sel_6_1,_zz_s1_outputPayload_sel_6}}}; + assign _zz_s1_outputPayload_selValid_105 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_106 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_107 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_108 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_109 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_110 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_111 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_112 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_113 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_114 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_115 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_116 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_117 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_118 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_119 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0111)); + assign _zz_s1_outputPayload_sel_7 = (((((((_zz_s1_outputPayload_selValid_105 || _zz_s1_outputPayload_selValid_107) || _zz_s1_outputPayload_selValid_109) || _zz_s1_outputPayload_selValid_111) || _zz_s1_outputPayload_selValid_113) || _zz_s1_outputPayload_selValid_115) || _zz_s1_outputPayload_selValid_117) || _zz_s1_outputPayload_selValid_119); + assign _zz_s1_outputPayload_sel_7_1 = (((((((_zz_s1_outputPayload_selValid_106 || _zz_s1_outputPayload_selValid_107) || _zz_s1_outputPayload_selValid_110) || _zz_s1_outputPayload_selValid_111) || _zz_s1_outputPayload_selValid_114) || _zz_s1_outputPayload_selValid_115) || _zz_s1_outputPayload_selValid_118) || _zz_s1_outputPayload_selValid_119); + assign _zz_s1_outputPayload_sel_7_2 = (((((((_zz_s1_outputPayload_selValid_108 || _zz_s1_outputPayload_selValid_109) || _zz_s1_outputPayload_selValid_110) || _zz_s1_outputPayload_selValid_111) || _zz_s1_outputPayload_selValid_116) || _zz_s1_outputPayload_selValid_117) || _zz_s1_outputPayload_selValid_118) || _zz_s1_outputPayload_selValid_119); + assign _zz_s1_outputPayload_sel_7_3 = (((((((_zz_s1_outputPayload_selValid_112 || _zz_s1_outputPayload_selValid_113) || _zz_s1_outputPayload_selValid_114) || _zz_s1_outputPayload_selValid_115) || _zz_s1_outputPayload_selValid_116) || _zz_s1_outputPayload_selValid_117) || _zz_s1_outputPayload_selValid_118) || _zz_s1_outputPayload_selValid_119); + assign s1_outputPayload_sel_7 = {_zz_s1_outputPayload_sel_7_3,{_zz_s1_outputPayload_sel_7_2,{_zz_s1_outputPayload_sel_7_1,_zz_s1_outputPayload_sel_7}}}; + assign _zz_s1_outputPayload_selValid_120 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_121 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_122 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_123 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_124 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_125 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_126 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_127 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_128 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_129 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_130 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_131 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_132 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_133 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_134 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1000)); + assign _zz_s1_outputPayload_sel_8 = (((((((_zz_s1_outputPayload_selValid_120 || _zz_s1_outputPayload_selValid_122) || _zz_s1_outputPayload_selValid_124) || _zz_s1_outputPayload_selValid_126) || _zz_s1_outputPayload_selValid_128) || _zz_s1_outputPayload_selValid_130) || _zz_s1_outputPayload_selValid_132) || _zz_s1_outputPayload_selValid_134); + assign _zz_s1_outputPayload_sel_8_1 = (((((((_zz_s1_outputPayload_selValid_121 || _zz_s1_outputPayload_selValid_122) || _zz_s1_outputPayload_selValid_125) || _zz_s1_outputPayload_selValid_126) || _zz_s1_outputPayload_selValid_129) || _zz_s1_outputPayload_selValid_130) || _zz_s1_outputPayload_selValid_133) || _zz_s1_outputPayload_selValid_134); + assign _zz_s1_outputPayload_sel_8_2 = (((((((_zz_s1_outputPayload_selValid_123 || _zz_s1_outputPayload_selValid_124) || _zz_s1_outputPayload_selValid_125) || _zz_s1_outputPayload_selValid_126) || _zz_s1_outputPayload_selValid_131) || _zz_s1_outputPayload_selValid_132) || _zz_s1_outputPayload_selValid_133) || _zz_s1_outputPayload_selValid_134); + assign _zz_s1_outputPayload_sel_8_3 = (((((((_zz_s1_outputPayload_selValid_127 || _zz_s1_outputPayload_selValid_128) || _zz_s1_outputPayload_selValid_129) || _zz_s1_outputPayload_selValid_130) || _zz_s1_outputPayload_selValid_131) || _zz_s1_outputPayload_selValid_132) || _zz_s1_outputPayload_selValid_133) || _zz_s1_outputPayload_selValid_134); + assign s1_outputPayload_sel_8 = {_zz_s1_outputPayload_sel_8_3,{_zz_s1_outputPayload_sel_8_2,{_zz_s1_outputPayload_sel_8_1,_zz_s1_outputPayload_sel_8}}}; + assign _zz_s1_outputPayload_selValid_135 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_136 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_137 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_138 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_139 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_140 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_141 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_142 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_143 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_144 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_145 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_146 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_147 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_148 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_149 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1001)); + assign _zz_s1_outputPayload_sel_9 = (((((((_zz_s1_outputPayload_selValid_135 || _zz_s1_outputPayload_selValid_137) || _zz_s1_outputPayload_selValid_139) || _zz_s1_outputPayload_selValid_141) || _zz_s1_outputPayload_selValid_143) || _zz_s1_outputPayload_selValid_145) || _zz_s1_outputPayload_selValid_147) || _zz_s1_outputPayload_selValid_149); + assign _zz_s1_outputPayload_sel_9_1 = (((((((_zz_s1_outputPayload_selValid_136 || _zz_s1_outputPayload_selValid_137) || _zz_s1_outputPayload_selValid_140) || _zz_s1_outputPayload_selValid_141) || _zz_s1_outputPayload_selValid_144) || _zz_s1_outputPayload_selValid_145) || _zz_s1_outputPayload_selValid_148) || _zz_s1_outputPayload_selValid_149); + assign _zz_s1_outputPayload_sel_9_2 = (((((((_zz_s1_outputPayload_selValid_138 || _zz_s1_outputPayload_selValid_139) || _zz_s1_outputPayload_selValid_140) || _zz_s1_outputPayload_selValid_141) || _zz_s1_outputPayload_selValid_146) || _zz_s1_outputPayload_selValid_147) || _zz_s1_outputPayload_selValid_148) || _zz_s1_outputPayload_selValid_149); + assign _zz_s1_outputPayload_sel_9_3 = (((((((_zz_s1_outputPayload_selValid_142 || _zz_s1_outputPayload_selValid_143) || _zz_s1_outputPayload_selValid_144) || _zz_s1_outputPayload_selValid_145) || _zz_s1_outputPayload_selValid_146) || _zz_s1_outputPayload_selValid_147) || _zz_s1_outputPayload_selValid_148) || _zz_s1_outputPayload_selValid_149); + assign s1_outputPayload_sel_9 = {_zz_s1_outputPayload_sel_9_3,{_zz_s1_outputPayload_sel_9_2,{_zz_s1_outputPayload_sel_9_1,_zz_s1_outputPayload_sel_9}}}; + assign _zz_s1_outputPayload_selValid_150 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_151 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_152 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_153 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_154 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_155 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_156 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_157 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_158 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_159 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_160 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_161 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_162 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_163 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_164 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1010)); + assign _zz_s1_outputPayload_sel_10 = (((((((_zz_s1_outputPayload_selValid_150 || _zz_s1_outputPayload_selValid_152) || _zz_s1_outputPayload_selValid_154) || _zz_s1_outputPayload_selValid_156) || _zz_s1_outputPayload_selValid_158) || _zz_s1_outputPayload_selValid_160) || _zz_s1_outputPayload_selValid_162) || _zz_s1_outputPayload_selValid_164); + assign _zz_s1_outputPayload_sel_10_1 = (((((((_zz_s1_outputPayload_selValid_151 || _zz_s1_outputPayload_selValid_152) || _zz_s1_outputPayload_selValid_155) || _zz_s1_outputPayload_selValid_156) || _zz_s1_outputPayload_selValid_159) || _zz_s1_outputPayload_selValid_160) || _zz_s1_outputPayload_selValid_163) || _zz_s1_outputPayload_selValid_164); + assign _zz_s1_outputPayload_sel_10_2 = (((((((_zz_s1_outputPayload_selValid_153 || _zz_s1_outputPayload_selValid_154) || _zz_s1_outputPayload_selValid_155) || _zz_s1_outputPayload_selValid_156) || _zz_s1_outputPayload_selValid_161) || _zz_s1_outputPayload_selValid_162) || _zz_s1_outputPayload_selValid_163) || _zz_s1_outputPayload_selValid_164); + assign _zz_s1_outputPayload_sel_10_3 = (((((((_zz_s1_outputPayload_selValid_157 || _zz_s1_outputPayload_selValid_158) || _zz_s1_outputPayload_selValid_159) || _zz_s1_outputPayload_selValid_160) || _zz_s1_outputPayload_selValid_161) || _zz_s1_outputPayload_selValid_162) || _zz_s1_outputPayload_selValid_163) || _zz_s1_outputPayload_selValid_164); + assign s1_outputPayload_sel_10 = {_zz_s1_outputPayload_sel_10_3,{_zz_s1_outputPayload_sel_10_2,{_zz_s1_outputPayload_sel_10_1,_zz_s1_outputPayload_sel_10}}}; + assign _zz_s1_outputPayload_selValid_165 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_166 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_167 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_168 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_169 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_170 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_171 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_172 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_173 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_174 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_175 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_176 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_177 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_178 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_179 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1011)); + assign _zz_s1_outputPayload_sel_11 = (((((((_zz_s1_outputPayload_selValid_165 || _zz_s1_outputPayload_selValid_167) || _zz_s1_outputPayload_selValid_169) || _zz_s1_outputPayload_selValid_171) || _zz_s1_outputPayload_selValid_173) || _zz_s1_outputPayload_selValid_175) || _zz_s1_outputPayload_selValid_177) || _zz_s1_outputPayload_selValid_179); + assign _zz_s1_outputPayload_sel_11_1 = (((((((_zz_s1_outputPayload_selValid_166 || _zz_s1_outputPayload_selValid_167) || _zz_s1_outputPayload_selValid_170) || _zz_s1_outputPayload_selValid_171) || _zz_s1_outputPayload_selValid_174) || _zz_s1_outputPayload_selValid_175) || _zz_s1_outputPayload_selValid_178) || _zz_s1_outputPayload_selValid_179); + assign _zz_s1_outputPayload_sel_11_2 = (((((((_zz_s1_outputPayload_selValid_168 || _zz_s1_outputPayload_selValid_169) || _zz_s1_outputPayload_selValid_170) || _zz_s1_outputPayload_selValid_171) || _zz_s1_outputPayload_selValid_176) || _zz_s1_outputPayload_selValid_177) || _zz_s1_outputPayload_selValid_178) || _zz_s1_outputPayload_selValid_179); + assign _zz_s1_outputPayload_sel_11_3 = (((((((_zz_s1_outputPayload_selValid_172 || _zz_s1_outputPayload_selValid_173) || _zz_s1_outputPayload_selValid_174) || _zz_s1_outputPayload_selValid_175) || _zz_s1_outputPayload_selValid_176) || _zz_s1_outputPayload_selValid_177) || _zz_s1_outputPayload_selValid_178) || _zz_s1_outputPayload_selValid_179); + assign s1_outputPayload_sel_11 = {_zz_s1_outputPayload_sel_11_3,{_zz_s1_outputPayload_sel_11_2,{_zz_s1_outputPayload_sel_11_1,_zz_s1_outputPayload_sel_11}}}; + assign _zz_s1_outputPayload_selValid_180 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_181 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_182 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_183 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_184 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_185 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_186 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_187 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_188 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_189 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_190 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_191 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_192 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_193 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_194 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1100)); + assign _zz_s1_outputPayload_sel_12 = (((((((_zz_s1_outputPayload_selValid_180 || _zz_s1_outputPayload_selValid_182) || _zz_s1_outputPayload_selValid_184) || _zz_s1_outputPayload_selValid_186) || _zz_s1_outputPayload_selValid_188) || _zz_s1_outputPayload_selValid_190) || _zz_s1_outputPayload_selValid_192) || _zz_s1_outputPayload_selValid_194); + assign _zz_s1_outputPayload_sel_12_1 = (((((((_zz_s1_outputPayload_selValid_181 || _zz_s1_outputPayload_selValid_182) || _zz_s1_outputPayload_selValid_185) || _zz_s1_outputPayload_selValid_186) || _zz_s1_outputPayload_selValid_189) || _zz_s1_outputPayload_selValid_190) || _zz_s1_outputPayload_selValid_193) || _zz_s1_outputPayload_selValid_194); + assign _zz_s1_outputPayload_sel_12_2 = (((((((_zz_s1_outputPayload_selValid_183 || _zz_s1_outputPayload_selValid_184) || _zz_s1_outputPayload_selValid_185) || _zz_s1_outputPayload_selValid_186) || _zz_s1_outputPayload_selValid_191) || _zz_s1_outputPayload_selValid_192) || _zz_s1_outputPayload_selValid_193) || _zz_s1_outputPayload_selValid_194); + assign _zz_s1_outputPayload_sel_12_3 = (((((((_zz_s1_outputPayload_selValid_187 || _zz_s1_outputPayload_selValid_188) || _zz_s1_outputPayload_selValid_189) || _zz_s1_outputPayload_selValid_190) || _zz_s1_outputPayload_selValid_191) || _zz_s1_outputPayload_selValid_192) || _zz_s1_outputPayload_selValid_193) || _zz_s1_outputPayload_selValid_194); + assign s1_outputPayload_sel_12 = {_zz_s1_outputPayload_sel_12_3,{_zz_s1_outputPayload_sel_12_2,{_zz_s1_outputPayload_sel_12_1,_zz_s1_outputPayload_sel_12}}}; + assign _zz_s1_outputPayload_selValid_195 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_196 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_197 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_198 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_199 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_200 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_201 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_202 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_203 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_204 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_205 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_206 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_207 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_208 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_209 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1101)); + assign _zz_s1_outputPayload_sel_13 = (((((((_zz_s1_outputPayload_selValid_195 || _zz_s1_outputPayload_selValid_197) || _zz_s1_outputPayload_selValid_199) || _zz_s1_outputPayload_selValid_201) || _zz_s1_outputPayload_selValid_203) || _zz_s1_outputPayload_selValid_205) || _zz_s1_outputPayload_selValid_207) || _zz_s1_outputPayload_selValid_209); + assign _zz_s1_outputPayload_sel_13_1 = (((((((_zz_s1_outputPayload_selValid_196 || _zz_s1_outputPayload_selValid_197) || _zz_s1_outputPayload_selValid_200) || _zz_s1_outputPayload_selValid_201) || _zz_s1_outputPayload_selValid_204) || _zz_s1_outputPayload_selValid_205) || _zz_s1_outputPayload_selValid_208) || _zz_s1_outputPayload_selValid_209); + assign _zz_s1_outputPayload_sel_13_2 = (((((((_zz_s1_outputPayload_selValid_198 || _zz_s1_outputPayload_selValid_199) || _zz_s1_outputPayload_selValid_200) || _zz_s1_outputPayload_selValid_201) || _zz_s1_outputPayload_selValid_206) || _zz_s1_outputPayload_selValid_207) || _zz_s1_outputPayload_selValid_208) || _zz_s1_outputPayload_selValid_209); + assign _zz_s1_outputPayload_sel_13_3 = (((((((_zz_s1_outputPayload_selValid_202 || _zz_s1_outputPayload_selValid_203) || _zz_s1_outputPayload_selValid_204) || _zz_s1_outputPayload_selValid_205) || _zz_s1_outputPayload_selValid_206) || _zz_s1_outputPayload_selValid_207) || _zz_s1_outputPayload_selValid_208) || _zz_s1_outputPayload_selValid_209); + assign s1_outputPayload_sel_13 = {_zz_s1_outputPayload_sel_13_3,{_zz_s1_outputPayload_sel_13_2,{_zz_s1_outputPayload_sel_13_1,_zz_s1_outputPayload_sel_13}}}; + assign _zz_s1_outputPayload_selValid_210 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_211 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_212 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_213 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_214 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_215 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_216 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_217 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_218 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_219 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_220 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_221 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_222 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_223 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_224 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1110)); + assign _zz_s1_outputPayload_sel_14 = (((((((_zz_s1_outputPayload_selValid_210 || _zz_s1_outputPayload_selValid_212) || _zz_s1_outputPayload_selValid_214) || _zz_s1_outputPayload_selValid_216) || _zz_s1_outputPayload_selValid_218) || _zz_s1_outputPayload_selValid_220) || _zz_s1_outputPayload_selValid_222) || _zz_s1_outputPayload_selValid_224); + assign _zz_s1_outputPayload_sel_14_1 = (((((((_zz_s1_outputPayload_selValid_211 || _zz_s1_outputPayload_selValid_212) || _zz_s1_outputPayload_selValid_215) || _zz_s1_outputPayload_selValid_216) || _zz_s1_outputPayload_selValid_219) || _zz_s1_outputPayload_selValid_220) || _zz_s1_outputPayload_selValid_223) || _zz_s1_outputPayload_selValid_224); + assign _zz_s1_outputPayload_sel_14_2 = (((((((_zz_s1_outputPayload_selValid_213 || _zz_s1_outputPayload_selValid_214) || _zz_s1_outputPayload_selValid_215) || _zz_s1_outputPayload_selValid_216) || _zz_s1_outputPayload_selValid_221) || _zz_s1_outputPayload_selValid_222) || _zz_s1_outputPayload_selValid_223) || _zz_s1_outputPayload_selValid_224); + assign _zz_s1_outputPayload_sel_14_3 = (((((((_zz_s1_outputPayload_selValid_217 || _zz_s1_outputPayload_selValid_218) || _zz_s1_outputPayload_selValid_219) || _zz_s1_outputPayload_selValid_220) || _zz_s1_outputPayload_selValid_221) || _zz_s1_outputPayload_selValid_222) || _zz_s1_outputPayload_selValid_223) || _zz_s1_outputPayload_selValid_224); + assign s1_outputPayload_sel_14 = {_zz_s1_outputPayload_sel_14_3,{_zz_s1_outputPayload_sel_14_2,{_zz_s1_outputPayload_sel_14_1,_zz_s1_outputPayload_sel_14}}}; + assign _zz_s1_outputPayload_selValid_225 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_226 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_227 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_228 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_229 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_230 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_231 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_232 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_233 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_234 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_235 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_236 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_237 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_238 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_239 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1111)); + assign _zz_s1_outputPayload_sel_15 = (((((((_zz_s1_outputPayload_selValid_225 || _zz_s1_outputPayload_selValid_227) || _zz_s1_outputPayload_selValid_229) || _zz_s1_outputPayload_selValid_231) || _zz_s1_outputPayload_selValid_233) || _zz_s1_outputPayload_selValid_235) || _zz_s1_outputPayload_selValid_237) || _zz_s1_outputPayload_selValid_239); + assign _zz_s1_outputPayload_sel_15_1 = (((((((_zz_s1_outputPayload_selValid_226 || _zz_s1_outputPayload_selValid_227) || _zz_s1_outputPayload_selValid_230) || _zz_s1_outputPayload_selValid_231) || _zz_s1_outputPayload_selValid_234) || _zz_s1_outputPayload_selValid_235) || _zz_s1_outputPayload_selValid_238) || _zz_s1_outputPayload_selValid_239); + assign _zz_s1_outputPayload_sel_15_2 = (((((((_zz_s1_outputPayload_selValid_228 || _zz_s1_outputPayload_selValid_229) || _zz_s1_outputPayload_selValid_230) || _zz_s1_outputPayload_selValid_231) || _zz_s1_outputPayload_selValid_236) || _zz_s1_outputPayload_selValid_237) || _zz_s1_outputPayload_selValid_238) || _zz_s1_outputPayload_selValid_239); + assign _zz_s1_outputPayload_sel_15_3 = (((((((_zz_s1_outputPayload_selValid_232 || _zz_s1_outputPayload_selValid_233) || _zz_s1_outputPayload_selValid_234) || _zz_s1_outputPayload_selValid_235) || _zz_s1_outputPayload_selValid_236) || _zz_s1_outputPayload_selValid_237) || _zz_s1_outputPayload_selValid_238) || _zz_s1_outputPayload_selValid_239); + assign s1_outputPayload_sel_15 = {_zz_s1_outputPayload_sel_15_3,{_zz_s1_outputPayload_sel_15_2,{_zz_s1_outputPayload_sel_15_1,_zz_s1_outputPayload_sel_15}}}; + assign s1_output_valid = s1_input_valid; + assign s1_input_ready = s1_output_ready; + assign s1_output_payload_cmd_data = s1_outputPayload_cmd_data; + assign s1_output_payload_cmd_mask = s1_outputPayload_cmd_mask; + assign s1_output_payload_index_0 = s1_outputPayload_index_0; + assign s1_output_payload_index_1 = s1_outputPayload_index_1; + assign s1_output_payload_index_2 = s1_outputPayload_index_2; + assign s1_output_payload_index_3 = s1_outputPayload_index_3; + assign s1_output_payload_index_4 = s1_outputPayload_index_4; + assign s1_output_payload_index_5 = s1_outputPayload_index_5; + assign s1_output_payload_index_6 = s1_outputPayload_index_6; + assign s1_output_payload_index_7 = s1_outputPayload_index_7; + assign s1_output_payload_index_8 = s1_outputPayload_index_8; + assign s1_output_payload_index_9 = s1_outputPayload_index_9; + assign s1_output_payload_index_10 = s1_outputPayload_index_10; + assign s1_output_payload_index_11 = s1_outputPayload_index_11; + assign s1_output_payload_index_12 = s1_outputPayload_index_12; + assign s1_output_payload_index_13 = s1_outputPayload_index_13; + assign s1_output_payload_index_14 = s1_outputPayload_index_14; + assign s1_output_payload_index_15 = s1_outputPayload_index_15; + assign s1_output_payload_last = s1_outputPayload_last; + assign s1_output_payload_sel_0 = s1_outputPayload_sel_0; + assign s1_output_payload_sel_1 = s1_outputPayload_sel_1; + assign s1_output_payload_sel_2 = s1_outputPayload_sel_2; + assign s1_output_payload_sel_3 = s1_outputPayload_sel_3; + assign s1_output_payload_sel_4 = s1_outputPayload_sel_4; + assign s1_output_payload_sel_5 = s1_outputPayload_sel_5; + assign s1_output_payload_sel_6 = s1_outputPayload_sel_6; + assign s1_output_payload_sel_7 = s1_outputPayload_sel_7; + assign s1_output_payload_sel_8 = s1_outputPayload_sel_8; + assign s1_output_payload_sel_9 = s1_outputPayload_sel_9; + assign s1_output_payload_sel_10 = s1_outputPayload_sel_10; + assign s1_output_payload_sel_11 = s1_outputPayload_sel_11; + assign s1_output_payload_sel_12 = s1_outputPayload_sel_12; + assign s1_output_payload_sel_13 = s1_outputPayload_sel_13; + assign s1_output_payload_sel_14 = s1_outputPayload_sel_14; + assign s1_output_payload_sel_15 = s1_outputPayload_sel_15; + assign s1_output_payload_selValid = s1_outputPayload_selValid; + always @(*) begin + s1_output_ready = s2_input_ready; + if(when_Stream_l375_2) begin + s1_output_ready = 1'b1; + end + end + + assign when_Stream_l375_2 = (! s2_input_valid); + assign s2_input_valid = s1_output_rValid; + assign s2_input_payload_cmd_data = s1_output_rData_cmd_data; + assign s2_input_payload_cmd_mask = s1_output_rData_cmd_mask; + assign s2_input_payload_index_0 = s1_output_rData_index_0; + assign s2_input_payload_index_1 = s1_output_rData_index_1; + assign s2_input_payload_index_2 = s1_output_rData_index_2; + assign s2_input_payload_index_3 = s1_output_rData_index_3; + assign s2_input_payload_index_4 = s1_output_rData_index_4; + assign s2_input_payload_index_5 = s1_output_rData_index_5; + assign s2_input_payload_index_6 = s1_output_rData_index_6; + assign s2_input_payload_index_7 = s1_output_rData_index_7; + assign s2_input_payload_index_8 = s1_output_rData_index_8; + assign s2_input_payload_index_9 = s1_output_rData_index_9; + assign s2_input_payload_index_10 = s1_output_rData_index_10; + assign s2_input_payload_index_11 = s1_output_rData_index_11; + assign s2_input_payload_index_12 = s1_output_rData_index_12; + assign s2_input_payload_index_13 = s1_output_rData_index_13; + assign s2_input_payload_index_14 = s1_output_rData_index_14; + assign s2_input_payload_index_15 = s1_output_rData_index_15; + assign s2_input_payload_last = s1_output_rData_last; + assign s2_input_payload_sel_0 = s1_output_rData_sel_0; + assign s2_input_payload_sel_1 = s1_output_rData_sel_1; + assign s2_input_payload_sel_2 = s1_output_rData_sel_2; + assign s2_input_payload_sel_3 = s1_output_rData_sel_3; + assign s2_input_payload_sel_4 = s1_output_rData_sel_4; + assign s2_input_payload_sel_5 = s1_output_rData_sel_5; + assign s2_input_payload_sel_6 = s1_output_rData_sel_6; + assign s2_input_payload_sel_7 = s1_output_rData_sel_7; + assign s2_input_payload_sel_8 = s1_output_rData_sel_8; + assign s2_input_payload_sel_9 = s1_output_rData_sel_9; + assign s2_input_payload_sel_10 = s1_output_rData_sel_10; + assign s2_input_payload_sel_11 = s1_output_rData_sel_11; + assign s2_input_payload_sel_12 = s1_output_rData_sel_12; + assign s2_input_payload_sel_13 = s1_output_rData_sel_13; + assign s2_input_payload_sel_14 = s1_output_rData_sel_14; + assign s2_input_payload_sel_15 = s1_output_rData_sel_15; + assign s2_input_payload_selValid = s1_output_rData_selValid; + always @(*) begin + s2_input_ready = ((! io_output_enough) || io_output_consume); + if(when_DmaSg_l1464) begin + s2_input_ready = 1'b0; + end + end + + assign when_DmaSg_l1464 = (_zz_when_DmaSg_l1464 < s1_byteCounter); + assign s2_input_fire = (s2_input_valid && s2_input_ready); + assign io_output_consumed = s2_input_fire; + assign s2_inputDataBytes_0 = s2_input_payload_cmd_data[7 : 0]; + assign s2_inputDataBytes_1 = s2_input_payload_cmd_data[15 : 8]; + assign s2_inputDataBytes_2 = s2_input_payload_cmd_data[23 : 16]; + assign s2_inputDataBytes_3 = s2_input_payload_cmd_data[31 : 24]; + assign s2_inputDataBytes_4 = s2_input_payload_cmd_data[39 : 32]; + assign s2_inputDataBytes_5 = s2_input_payload_cmd_data[47 : 40]; + assign s2_inputDataBytes_6 = s2_input_payload_cmd_data[55 : 48]; + assign s2_inputDataBytes_7 = s2_input_payload_cmd_data[63 : 56]; + assign s2_inputDataBytes_8 = s2_input_payload_cmd_data[71 : 64]; + assign s2_inputDataBytes_9 = s2_input_payload_cmd_data[79 : 72]; + assign s2_inputDataBytes_10 = s2_input_payload_cmd_data[87 : 80]; + assign s2_inputDataBytes_11 = s2_input_payload_cmd_data[95 : 88]; + assign s2_inputDataBytes_12 = s2_input_payload_cmd_data[103 : 96]; + assign s2_inputDataBytes_13 = s2_input_payload_cmd_data[111 : 104]; + assign s2_inputDataBytes_14 = s2_input_payload_cmd_data[119 : 112]; + assign s2_inputDataBytes_15 = s2_input_payload_cmd_data[127 : 120]; + assign s2_byteLogic_0_lastUsed = (4'b0000 == io_output_lastByteUsed); + assign s2_byteLogic_0_inputMask = s2_input_payload_selValid[0]; + assign s2_byteLogic_0_inputData = _zz_s2_byteLogic_0_inputData; + assign s2_byteLogic_0_outputMask = (s2_byteLogic_0_buffer_valid || (s2_input_valid && s2_byteLogic_0_inputMask)); + assign s2_byteLogic_0_outputData = (s2_byteLogic_0_buffer_valid ? s2_byteLogic_0_buffer_data : s2_byteLogic_0_inputData); + always @(*) begin + io_output_mask[0] = s2_byteLogic_0_outputMask; + io_output_mask[1] = s2_byteLogic_1_outputMask; + io_output_mask[2] = s2_byteLogic_2_outputMask; + io_output_mask[3] = s2_byteLogic_3_outputMask; + io_output_mask[4] = s2_byteLogic_4_outputMask; + io_output_mask[5] = s2_byteLogic_5_outputMask; + io_output_mask[6] = s2_byteLogic_6_outputMask; + io_output_mask[7] = s2_byteLogic_7_outputMask; + io_output_mask[8] = s2_byteLogic_8_outputMask; + io_output_mask[9] = s2_byteLogic_9_outputMask; + io_output_mask[10] = s2_byteLogic_10_outputMask; + io_output_mask[11] = s2_byteLogic_11_outputMask; + io_output_mask[12] = s2_byteLogic_12_outputMask; + io_output_mask[13] = s2_byteLogic_13_outputMask; + io_output_mask[14] = s2_byteLogic_14_outputMask; + io_output_mask[15] = s2_byteLogic_15_outputMask; + end + + always @(*) begin + io_output_data[7 : 0] = s2_byteLogic_0_outputData; + io_output_data[15 : 8] = s2_byteLogic_1_outputData; + io_output_data[23 : 16] = s2_byteLogic_2_outputData; + io_output_data[31 : 24] = s2_byteLogic_3_outputData; + io_output_data[39 : 32] = s2_byteLogic_4_outputData; + io_output_data[47 : 40] = s2_byteLogic_5_outputData; + io_output_data[55 : 48] = s2_byteLogic_6_outputData; + io_output_data[63 : 56] = s2_byteLogic_7_outputData; + io_output_data[71 : 64] = s2_byteLogic_8_outputData; + io_output_data[79 : 72] = s2_byteLogic_9_outputData; + io_output_data[87 : 80] = s2_byteLogic_10_outputData; + io_output_data[95 : 88] = s2_byteLogic_11_outputData; + io_output_data[103 : 96] = s2_byteLogic_12_outputData; + io_output_data[111 : 104] = s2_byteLogic_13_outputData; + io_output_data[119 : 112] = s2_byteLogic_14_outputData; + io_output_data[127 : 120] = s2_byteLogic_15_outputData; + end + + assign when_DmaSg_l1493 = (s2_byteLogic_0_inputMask && ((! io_output_consume) || s2_byteLogic_0_buffer_valid)); + assign s2_byteLogic_1_lastUsed = (4'b0001 == io_output_lastByteUsed); + assign s2_byteLogic_1_inputMask = s2_input_payload_selValid[1]; + assign s2_byteLogic_1_inputData = _zz_s2_byteLogic_1_inputData; + assign s2_byteLogic_1_outputMask = (s2_byteLogic_1_buffer_valid || (s2_input_valid && s2_byteLogic_1_inputMask)); + assign s2_byteLogic_1_outputData = (s2_byteLogic_1_buffer_valid ? s2_byteLogic_1_buffer_data : s2_byteLogic_1_inputData); + assign when_DmaSg_l1493_1 = (s2_byteLogic_1_inputMask && ((! io_output_consume) || s2_byteLogic_1_buffer_valid)); + assign s2_byteLogic_2_lastUsed = (4'b0010 == io_output_lastByteUsed); + assign s2_byteLogic_2_inputMask = s2_input_payload_selValid[2]; + assign s2_byteLogic_2_inputData = _zz_s2_byteLogic_2_inputData; + assign s2_byteLogic_2_outputMask = (s2_byteLogic_2_buffer_valid || (s2_input_valid && s2_byteLogic_2_inputMask)); + assign s2_byteLogic_2_outputData = (s2_byteLogic_2_buffer_valid ? s2_byteLogic_2_buffer_data : s2_byteLogic_2_inputData); + assign when_DmaSg_l1493_2 = (s2_byteLogic_2_inputMask && ((! io_output_consume) || s2_byteLogic_2_buffer_valid)); + assign s2_byteLogic_3_lastUsed = (4'b0011 == io_output_lastByteUsed); + assign s2_byteLogic_3_inputMask = s2_input_payload_selValid[3]; + assign s2_byteLogic_3_inputData = _zz_s2_byteLogic_3_inputData; + assign s2_byteLogic_3_outputMask = (s2_byteLogic_3_buffer_valid || (s2_input_valid && s2_byteLogic_3_inputMask)); + assign s2_byteLogic_3_outputData = (s2_byteLogic_3_buffer_valid ? s2_byteLogic_3_buffer_data : s2_byteLogic_3_inputData); + assign when_DmaSg_l1493_3 = (s2_byteLogic_3_inputMask && ((! io_output_consume) || s2_byteLogic_3_buffer_valid)); + assign s2_byteLogic_4_lastUsed = (4'b0100 == io_output_lastByteUsed); + assign s2_byteLogic_4_inputMask = s2_input_payload_selValid[4]; + assign s2_byteLogic_4_inputData = _zz_s2_byteLogic_4_inputData; + assign s2_byteLogic_4_outputMask = (s2_byteLogic_4_buffer_valid || (s2_input_valid && s2_byteLogic_4_inputMask)); + assign s2_byteLogic_4_outputData = (s2_byteLogic_4_buffer_valid ? s2_byteLogic_4_buffer_data : s2_byteLogic_4_inputData); + assign when_DmaSg_l1493_4 = (s2_byteLogic_4_inputMask && ((! io_output_consume) || s2_byteLogic_4_buffer_valid)); + assign s2_byteLogic_5_lastUsed = (4'b0101 == io_output_lastByteUsed); + assign s2_byteLogic_5_inputMask = s2_input_payload_selValid[5]; + assign s2_byteLogic_5_inputData = _zz_s2_byteLogic_5_inputData; + assign s2_byteLogic_5_outputMask = (s2_byteLogic_5_buffer_valid || (s2_input_valid && s2_byteLogic_5_inputMask)); + assign s2_byteLogic_5_outputData = (s2_byteLogic_5_buffer_valid ? s2_byteLogic_5_buffer_data : s2_byteLogic_5_inputData); + assign when_DmaSg_l1493_5 = (s2_byteLogic_5_inputMask && ((! io_output_consume) || s2_byteLogic_5_buffer_valid)); + assign s2_byteLogic_6_lastUsed = (4'b0110 == io_output_lastByteUsed); + assign s2_byteLogic_6_inputMask = s2_input_payload_selValid[6]; + assign s2_byteLogic_6_inputData = _zz_s2_byteLogic_6_inputData; + assign s2_byteLogic_6_outputMask = (s2_byteLogic_6_buffer_valid || (s2_input_valid && s2_byteLogic_6_inputMask)); + assign s2_byteLogic_6_outputData = (s2_byteLogic_6_buffer_valid ? s2_byteLogic_6_buffer_data : s2_byteLogic_6_inputData); + assign when_DmaSg_l1493_6 = (s2_byteLogic_6_inputMask && ((! io_output_consume) || s2_byteLogic_6_buffer_valid)); + assign s2_byteLogic_7_lastUsed = (4'b0111 == io_output_lastByteUsed); + assign s2_byteLogic_7_inputMask = s2_input_payload_selValid[7]; + assign s2_byteLogic_7_inputData = _zz_s2_byteLogic_7_inputData; + assign s2_byteLogic_7_outputMask = (s2_byteLogic_7_buffer_valid || (s2_input_valid && s2_byteLogic_7_inputMask)); + assign s2_byteLogic_7_outputData = (s2_byteLogic_7_buffer_valid ? s2_byteLogic_7_buffer_data : s2_byteLogic_7_inputData); + assign when_DmaSg_l1493_7 = (s2_byteLogic_7_inputMask && ((! io_output_consume) || s2_byteLogic_7_buffer_valid)); + assign s2_byteLogic_8_lastUsed = (4'b1000 == io_output_lastByteUsed); + assign s2_byteLogic_8_inputMask = s2_input_payload_selValid[8]; + assign s2_byteLogic_8_inputData = _zz_s2_byteLogic_8_inputData; + assign s2_byteLogic_8_outputMask = (s2_byteLogic_8_buffer_valid || (s2_input_valid && s2_byteLogic_8_inputMask)); + assign s2_byteLogic_8_outputData = (s2_byteLogic_8_buffer_valid ? s2_byteLogic_8_buffer_data : s2_byteLogic_8_inputData); + assign when_DmaSg_l1493_8 = (s2_byteLogic_8_inputMask && ((! io_output_consume) || s2_byteLogic_8_buffer_valid)); + assign s2_byteLogic_9_lastUsed = (4'b1001 == io_output_lastByteUsed); + assign s2_byteLogic_9_inputMask = s2_input_payload_selValid[9]; + assign s2_byteLogic_9_inputData = _zz_s2_byteLogic_9_inputData; + assign s2_byteLogic_9_outputMask = (s2_byteLogic_9_buffer_valid || (s2_input_valid && s2_byteLogic_9_inputMask)); + assign s2_byteLogic_9_outputData = (s2_byteLogic_9_buffer_valid ? s2_byteLogic_9_buffer_data : s2_byteLogic_9_inputData); + assign when_DmaSg_l1493_9 = (s2_byteLogic_9_inputMask && ((! io_output_consume) || s2_byteLogic_9_buffer_valid)); + assign s2_byteLogic_10_lastUsed = (4'b1010 == io_output_lastByteUsed); + assign s2_byteLogic_10_inputMask = s2_input_payload_selValid[10]; + assign s2_byteLogic_10_inputData = _zz_s2_byteLogic_10_inputData; + assign s2_byteLogic_10_outputMask = (s2_byteLogic_10_buffer_valid || (s2_input_valid && s2_byteLogic_10_inputMask)); + assign s2_byteLogic_10_outputData = (s2_byteLogic_10_buffer_valid ? s2_byteLogic_10_buffer_data : s2_byteLogic_10_inputData); + assign when_DmaSg_l1493_10 = (s2_byteLogic_10_inputMask && ((! io_output_consume) || s2_byteLogic_10_buffer_valid)); + assign s2_byteLogic_11_lastUsed = (4'b1011 == io_output_lastByteUsed); + assign s2_byteLogic_11_inputMask = s2_input_payload_selValid[11]; + assign s2_byteLogic_11_inputData = _zz_s2_byteLogic_11_inputData; + assign s2_byteLogic_11_outputMask = (s2_byteLogic_11_buffer_valid || (s2_input_valid && s2_byteLogic_11_inputMask)); + assign s2_byteLogic_11_outputData = (s2_byteLogic_11_buffer_valid ? s2_byteLogic_11_buffer_data : s2_byteLogic_11_inputData); + assign when_DmaSg_l1493_11 = (s2_byteLogic_11_inputMask && ((! io_output_consume) || s2_byteLogic_11_buffer_valid)); + assign s2_byteLogic_12_lastUsed = (4'b1100 == io_output_lastByteUsed); + assign s2_byteLogic_12_inputMask = s2_input_payload_selValid[12]; + assign s2_byteLogic_12_inputData = _zz_s2_byteLogic_12_inputData; + assign s2_byteLogic_12_outputMask = (s2_byteLogic_12_buffer_valid || (s2_input_valid && s2_byteLogic_12_inputMask)); + assign s2_byteLogic_12_outputData = (s2_byteLogic_12_buffer_valid ? s2_byteLogic_12_buffer_data : s2_byteLogic_12_inputData); + assign when_DmaSg_l1493_12 = (s2_byteLogic_12_inputMask && ((! io_output_consume) || s2_byteLogic_12_buffer_valid)); + assign s2_byteLogic_13_lastUsed = (4'b1101 == io_output_lastByteUsed); + assign s2_byteLogic_13_inputMask = s2_input_payload_selValid[13]; + assign s2_byteLogic_13_inputData = _zz_s2_byteLogic_13_inputData; + assign s2_byteLogic_13_outputMask = (s2_byteLogic_13_buffer_valid || (s2_input_valid && s2_byteLogic_13_inputMask)); + assign s2_byteLogic_13_outputData = (s2_byteLogic_13_buffer_valid ? s2_byteLogic_13_buffer_data : s2_byteLogic_13_inputData); + assign when_DmaSg_l1493_13 = (s2_byteLogic_13_inputMask && ((! io_output_consume) || s2_byteLogic_13_buffer_valid)); + assign s2_byteLogic_14_lastUsed = (4'b1110 == io_output_lastByteUsed); + assign s2_byteLogic_14_inputMask = s2_input_payload_selValid[14]; + assign s2_byteLogic_14_inputData = _zz_s2_byteLogic_14_inputData; + assign s2_byteLogic_14_outputMask = (s2_byteLogic_14_buffer_valid || (s2_input_valid && s2_byteLogic_14_inputMask)); + assign s2_byteLogic_14_outputData = (s2_byteLogic_14_buffer_valid ? s2_byteLogic_14_buffer_data : s2_byteLogic_14_inputData); + assign when_DmaSg_l1493_14 = (s2_byteLogic_14_inputMask && ((! io_output_consume) || s2_byteLogic_14_buffer_valid)); + assign s2_byteLogic_15_lastUsed = (4'b1111 == io_output_lastByteUsed); + assign s2_byteLogic_15_inputMask = s2_input_payload_selValid[15]; + assign s2_byteLogic_15_inputData = _zz_s2_byteLogic_15_inputData; + assign s2_byteLogic_15_outputMask = (s2_byteLogic_15_buffer_valid || (s2_input_valid && s2_byteLogic_15_inputMask)); + assign s2_byteLogic_15_outputData = (s2_byteLogic_15_buffer_valid ? s2_byteLogic_15_buffer_data : s2_byteLogic_15_inputData); + assign when_DmaSg_l1493_15 = (s2_byteLogic_15_inputMask && ((! io_output_consume) || s2_byteLogic_15_buffer_valid)); + assign _zz_io_output_usedUntil = (((((((s2_byteLogic_1_lastUsed || s2_byteLogic_3_lastUsed) || s2_byteLogic_5_lastUsed) || s2_byteLogic_7_lastUsed) || s2_byteLogic_9_lastUsed) || s2_byteLogic_11_lastUsed) || s2_byteLogic_13_lastUsed) || s2_byteLogic_15_lastUsed); + assign _zz_io_output_usedUntil_1 = (((((((s2_byteLogic_2_lastUsed || s2_byteLogic_3_lastUsed) || s2_byteLogic_6_lastUsed) || s2_byteLogic_7_lastUsed) || s2_byteLogic_10_lastUsed) || s2_byteLogic_11_lastUsed) || s2_byteLogic_14_lastUsed) || s2_byteLogic_15_lastUsed); + assign _zz_io_output_usedUntil_2 = (((((((s2_byteLogic_4_lastUsed || s2_byteLogic_5_lastUsed) || s2_byteLogic_6_lastUsed) || s2_byteLogic_7_lastUsed) || s2_byteLogic_12_lastUsed) || s2_byteLogic_13_lastUsed) || s2_byteLogic_14_lastUsed) || s2_byteLogic_15_lastUsed); + assign _zz_io_output_usedUntil_3 = (((((((s2_byteLogic_8_lastUsed || s2_byteLogic_9_lastUsed) || s2_byteLogic_10_lastUsed) || s2_byteLogic_11_lastUsed) || s2_byteLogic_12_lastUsed) || s2_byteLogic_13_lastUsed) || s2_byteLogic_14_lastUsed) || s2_byteLogic_15_lastUsed); + assign io_output_usedUntil = _zz_io_output_usedUntil_4; + always @(posedge clk) begin + if(reset) begin + io_input_rValid <= 1'b0; + s0_output_rValid <= 1'b0; + s1_output_rValid <= 1'b0; + end else begin + if(io_input_ready) begin + io_input_rValid <= io_input_valid; + end + if(io_flush) begin + io_input_rValid <= 1'b0; + end + if(s0_output_ready) begin + s0_output_rValid <= s0_output_valid; + end + if(io_flush) begin + s0_output_rValid <= 1'b0; + end + if(s1_output_ready) begin + s1_output_rValid <= s1_output_valid; + end + if(io_flush) begin + s1_output_rValid <= 1'b0; + end + end + end + + always @(posedge clk) begin + if(io_input_ready) begin + io_input_rData_data <= io_input_payload_data; + io_input_rData_mask <= io_input_payload_mask; + end + if(s0_output_ready) begin + s0_output_rData_cmd_data <= s0_output_payload_cmd_data; + s0_output_rData_cmd_mask <= s0_output_payload_cmd_mask; + s0_output_rData_countOnes_0 <= s0_output_payload_countOnes_0; + s0_output_rData_countOnes_1 <= s0_output_payload_countOnes_1; + s0_output_rData_countOnes_2 <= s0_output_payload_countOnes_2; + s0_output_rData_countOnes_3 <= s0_output_payload_countOnes_3; + s0_output_rData_countOnes_4 <= s0_output_payload_countOnes_4; + s0_output_rData_countOnes_5 <= s0_output_payload_countOnes_5; + s0_output_rData_countOnes_6 <= s0_output_payload_countOnes_6; + s0_output_rData_countOnes_7 <= s0_output_payload_countOnes_7; + s0_output_rData_countOnes_8 <= s0_output_payload_countOnes_8; + s0_output_rData_countOnes_9 <= s0_output_payload_countOnes_9; + s0_output_rData_countOnes_10 <= s0_output_payload_countOnes_10; + s0_output_rData_countOnes_11 <= s0_output_payload_countOnes_11; + s0_output_rData_countOnes_12 <= s0_output_payload_countOnes_12; + s0_output_rData_countOnes_13 <= s0_output_payload_countOnes_13; + s0_output_rData_countOnes_14 <= s0_output_payload_countOnes_14; + s0_output_rData_countOnes_15 <= s0_output_payload_countOnes_15; + end + if(s1_input_fire) begin + s1_offset <= s1_offsetNext[3:0]; + end + if(io_flush) begin + s1_offset <= io_offset; + end + if(s1_input_fire) begin + s1_byteCounter <= (s1_byteCounter + _zz_s1_byteCounter); + end + if(io_flush) begin + s1_byteCounter <= 13'h0; + end + if(s1_output_ready) begin + s1_output_rData_cmd_data <= s1_output_payload_cmd_data; + s1_output_rData_cmd_mask <= s1_output_payload_cmd_mask; + s1_output_rData_index_0 <= s1_output_payload_index_0; + s1_output_rData_index_1 <= s1_output_payload_index_1; + s1_output_rData_index_2 <= s1_output_payload_index_2; + s1_output_rData_index_3 <= s1_output_payload_index_3; + s1_output_rData_index_4 <= s1_output_payload_index_4; + s1_output_rData_index_5 <= s1_output_payload_index_5; + s1_output_rData_index_6 <= s1_output_payload_index_6; + s1_output_rData_index_7 <= s1_output_payload_index_7; + s1_output_rData_index_8 <= s1_output_payload_index_8; + s1_output_rData_index_9 <= s1_output_payload_index_9; + s1_output_rData_index_10 <= s1_output_payload_index_10; + s1_output_rData_index_11 <= s1_output_payload_index_11; + s1_output_rData_index_12 <= s1_output_payload_index_12; + s1_output_rData_index_13 <= s1_output_payload_index_13; + s1_output_rData_index_14 <= s1_output_payload_index_14; + s1_output_rData_index_15 <= s1_output_payload_index_15; + s1_output_rData_last <= s1_output_payload_last; + s1_output_rData_sel_0 <= s1_output_payload_sel_0; + s1_output_rData_sel_1 <= s1_output_payload_sel_1; + s1_output_rData_sel_2 <= s1_output_payload_sel_2; + s1_output_rData_sel_3 <= s1_output_payload_sel_3; + s1_output_rData_sel_4 <= s1_output_payload_sel_4; + s1_output_rData_sel_5 <= s1_output_payload_sel_5; + s1_output_rData_sel_6 <= s1_output_payload_sel_6; + s1_output_rData_sel_7 <= s1_output_payload_sel_7; + s1_output_rData_sel_8 <= s1_output_payload_sel_8; + s1_output_rData_sel_9 <= s1_output_payload_sel_9; + s1_output_rData_sel_10 <= s1_output_payload_sel_10; + s1_output_rData_sel_11 <= s1_output_payload_sel_11; + s1_output_rData_sel_12 <= s1_output_payload_sel_12; + s1_output_rData_sel_13 <= s1_output_payload_sel_13; + s1_output_rData_sel_14 <= s1_output_payload_sel_14; + s1_output_rData_sel_15 <= s1_output_payload_sel_15; + s1_output_rData_selValid <= s1_output_payload_selValid; + end + if(io_output_consume) begin + s2_byteLogic_0_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_0_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493) begin + s2_byteLogic_0_buffer_valid <= 1'b1; + s2_byteLogic_0_buffer_data <= s2_byteLogic_0_inputData; + end + end + if(io_flush) begin + s2_byteLogic_0_buffer_valid <= (4'b0000 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_1_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_1_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_1) begin + s2_byteLogic_1_buffer_valid <= 1'b1; + s2_byteLogic_1_buffer_data <= s2_byteLogic_1_inputData; + end + end + if(io_flush) begin + s2_byteLogic_1_buffer_valid <= (4'b0001 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_2_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_2_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_2) begin + s2_byteLogic_2_buffer_valid <= 1'b1; + s2_byteLogic_2_buffer_data <= s2_byteLogic_2_inputData; + end + end + if(io_flush) begin + s2_byteLogic_2_buffer_valid <= (4'b0010 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_3_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_3_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_3) begin + s2_byteLogic_3_buffer_valid <= 1'b1; + s2_byteLogic_3_buffer_data <= s2_byteLogic_3_inputData; + end + end + if(io_flush) begin + s2_byteLogic_3_buffer_valid <= (4'b0011 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_4_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_4_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_4) begin + s2_byteLogic_4_buffer_valid <= 1'b1; + s2_byteLogic_4_buffer_data <= s2_byteLogic_4_inputData; + end + end + if(io_flush) begin + s2_byteLogic_4_buffer_valid <= (4'b0100 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_5_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_5_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_5) begin + s2_byteLogic_5_buffer_valid <= 1'b1; + s2_byteLogic_5_buffer_data <= s2_byteLogic_5_inputData; + end + end + if(io_flush) begin + s2_byteLogic_5_buffer_valid <= (4'b0101 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_6_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_6_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_6) begin + s2_byteLogic_6_buffer_valid <= 1'b1; + s2_byteLogic_6_buffer_data <= s2_byteLogic_6_inputData; + end + end + if(io_flush) begin + s2_byteLogic_6_buffer_valid <= (4'b0110 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_7_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_7_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_7) begin + s2_byteLogic_7_buffer_valid <= 1'b1; + s2_byteLogic_7_buffer_data <= s2_byteLogic_7_inputData; + end + end + if(io_flush) begin + s2_byteLogic_7_buffer_valid <= (4'b0111 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_8_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_8_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_8) begin + s2_byteLogic_8_buffer_valid <= 1'b1; + s2_byteLogic_8_buffer_data <= s2_byteLogic_8_inputData; + end + end + if(io_flush) begin + s2_byteLogic_8_buffer_valid <= (4'b1000 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_9_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_9_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_9) begin + s2_byteLogic_9_buffer_valid <= 1'b1; + s2_byteLogic_9_buffer_data <= s2_byteLogic_9_inputData; + end + end + if(io_flush) begin + s2_byteLogic_9_buffer_valid <= (4'b1001 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_10_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_10_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_10) begin + s2_byteLogic_10_buffer_valid <= 1'b1; + s2_byteLogic_10_buffer_data <= s2_byteLogic_10_inputData; + end + end + if(io_flush) begin + s2_byteLogic_10_buffer_valid <= (4'b1010 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_11_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_11_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_11) begin + s2_byteLogic_11_buffer_valid <= 1'b1; + s2_byteLogic_11_buffer_data <= s2_byteLogic_11_inputData; + end + end + if(io_flush) begin + s2_byteLogic_11_buffer_valid <= (4'b1011 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_12_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_12_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_12) begin + s2_byteLogic_12_buffer_valid <= 1'b1; + s2_byteLogic_12_buffer_data <= s2_byteLogic_12_inputData; + end + end + if(io_flush) begin + s2_byteLogic_12_buffer_valid <= (4'b1100 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_13_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_13_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_13) begin + s2_byteLogic_13_buffer_valid <= 1'b1; + s2_byteLogic_13_buffer_data <= s2_byteLogic_13_inputData; + end + end + if(io_flush) begin + s2_byteLogic_13_buffer_valid <= (4'b1101 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_14_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_14_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_14) begin + s2_byteLogic_14_buffer_valid <= 1'b1; + s2_byteLogic_14_buffer_data <= s2_byteLogic_14_inputData; + end + end + if(io_flush) begin + s2_byteLogic_14_buffer_valid <= (4'b1110 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_15_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_15_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_15) begin + s2_byteLogic_15_buffer_valid <= 1'b1; + s2_byteLogic_15_buffer_data <= s2_byteLogic_15_inputData; + end + end + if(io_flush) begin + s2_byteLogic_15_buffer_valid <= (4'b1111 < io_offset); + end + end + + +endmodule + +module EfxDMA_DmaMemoryCore ( + input wire io_writes_0_cmd_valid, + output wire io_writes_0_cmd_ready, + input wire [9:0] io_writes_0_cmd_payload_address, + input wire [63:0] io_writes_0_cmd_payload_data, + input wire [7:0] io_writes_0_cmd_payload_mask, + input wire [1:0] io_writes_0_cmd_payload_priority, + input wire [6:0] io_writes_0_cmd_payload_context, + output wire io_writes_0_rsp_valid, + output wire [6:0] io_writes_0_rsp_payload_context, + input wire io_writes_1_cmd_valid, + output wire io_writes_1_cmd_ready, + input wire [9:0] io_writes_1_cmd_payload_address, + input wire [127:0] io_writes_1_cmd_payload_data, + input wire [15:0] io_writes_1_cmd_payload_mask, + input wire [6:0] io_writes_1_cmd_payload_context, + output wire io_writes_1_rsp_valid, + output wire [6:0] io_writes_1_rsp_payload_context, + input wire io_reads_0_cmd_valid, + output wire io_reads_0_cmd_ready, + input wire [9:0] io_reads_0_cmd_payload_address, + input wire [1:0] io_reads_0_cmd_payload_priority, + input wire [2:0] io_reads_0_cmd_payload_context, + output wire io_reads_0_rsp_valid, + input wire io_reads_0_rsp_ready, + output wire [63:0] io_reads_0_rsp_payload_data, + output wire [7:0] io_reads_0_rsp_payload_mask, + output wire [2:0] io_reads_0_rsp_payload_context, + input wire io_reads_1_cmd_valid, + output wire io_reads_1_cmd_ready, + input wire [9:0] io_reads_1_cmd_payload_address, + input wire [11:0] io_reads_1_cmd_payload_context, + output wire io_reads_1_rsp_valid, + input wire io_reads_1_rsp_ready, + output wire [127:0] io_reads_1_rsp_payload_data, + output wire [15:0] io_reads_1_rsp_payload_mask, + output wire [11:0] io_reads_1_rsp_payload_context, + input wire clk, + input wire reset +); + + reg [71:0] banks_0_ram_spinal_port1; + reg [71:0] banks_1_ram_spinal_port1; + wire [71:0] _zz_banks_0_ram_port; + wire [71:0] _zz_banks_1_ram_port; + wire [3:0] _zz_write_ports_0_priority_value; + wire [9:0] _zz_when_MemoryCore_l136; + wire [9:0] _zz_when_MemoryCore_l136_1; + reg [63:0] _zz_read_ports_0_buffer_bufferIn_payload_data; + reg [7:0] _zz_read_ports_0_buffer_bufferIn_payload_mask; + wire [3:0] _zz_read_ports_0_priority_value; + wire [9:0] _zz_when_MemoryCore_l221; + wire [9:0] _zz_when_MemoryCore_l221_1; + reg _zz_1; + reg _zz_2; + reg banks_0_write_valid; + reg [8:0] banks_0_write_payload_address; + reg [63:0] banks_0_write_payload_data_data; + reg [7:0] banks_0_write_payload_data_mask; + wire banks_0_read_cmd_valid; + wire [8:0] banks_0_read_cmd_payload; + wire [63:0] banks_0_read_rsp_data; + wire [7:0] banks_0_read_rsp_mask; + wire [71:0] _zz_banks_0_read_rsp_data; + wire banks_0_writeOr_value_valid; + wire [8:0] banks_0_writeOr_value_payload_address; + wire [63:0] banks_0_writeOr_value_payload_data_data; + wire [7:0] banks_0_writeOr_value_payload_data_mask; + wire banks_0_readOr_value_valid; + wire [8:0] banks_0_readOr_value_payload; + reg banks_1_write_valid; + reg [8:0] banks_1_write_payload_address; + reg [63:0] banks_1_write_payload_data_data; + reg [7:0] banks_1_write_payload_data_mask; + wire banks_1_read_cmd_valid; + wire [8:0] banks_1_read_cmd_payload; + wire [63:0] banks_1_read_rsp_data; + wire [7:0] banks_1_read_rsp_mask; + wire [71:0] _zz_banks_1_read_rsp_data; + wire banks_1_writeOr_value_valid; + wire [8:0] banks_1_writeOr_value_payload_address; + wire [63:0] banks_1_writeOr_value_payload_data_data; + wire [7:0] banks_1_writeOr_value_payload_data_mask; + wire banks_1_readOr_value_valid; + wire [8:0] banks_1_readOr_value_payload; + reg [3:0] write_ports_0_priority_value; + wire write_nodes_0_0_priority; + wire write_nodes_0_0_conflict; + wire write_nodes_0_1_priority; + wire write_nodes_0_1_conflict; + wire write_nodes_1_0_priority; + wire write_nodes_1_0_conflict; + wire write_nodes_1_1_priority; + wire write_nodes_1_1_conflict; + wire [0:0] write_arbiter_0_losedAgainst; + reg write_arbiter_0_doIt; + reg _zz_banks_0_writeOr_value_valid; + reg [8:0] _zz_banks_0_writeOr_value_valid_1; + reg [63:0] _zz_banks_0_writeOr_value_valid_2; + reg [7:0] _zz_banks_0_writeOr_value_valid_3; + wire when_MemoryCore_l136; + reg _zz_banks_1_writeOr_value_valid; + reg [8:0] _zz_banks_1_writeOr_value_valid_1; + reg [63:0] _zz_banks_1_writeOr_value_valid_2; + reg [7:0] _zz_banks_1_writeOr_value_valid_3; + wire when_MemoryCore_l136_1; + reg write_arbiter_0_doIt_regNext; + reg [6:0] io_writes_0_cmd_payload_context_regNext; + wire [0:0] write_arbiter_1_losedAgainst; + reg write_arbiter_1_doIt; + reg _zz_banks_0_writeOr_value_valid_4; + reg [8:0] _zz_banks_0_writeOr_value_valid_5; + reg [63:0] _zz_banks_0_writeOr_value_valid_6; + reg [7:0] _zz_banks_0_writeOr_value_valid_7; + wire when_MemoryCore_l136_2; + reg _zz_banks_1_writeOr_value_valid_4; + reg [8:0] _zz_banks_1_writeOr_value_valid_5; + reg [63:0] _zz_banks_1_writeOr_value_valid_6; + reg [7:0] _zz_banks_1_writeOr_value_valid_7; + wire when_MemoryCore_l136_3; + reg write_arbiter_1_doIt_regNext; + reg [6:0] io_writes_1_cmd_payload_context_regNext; + wire read_ports_0_buffer_s0_valid; + wire [2:0] read_ports_0_buffer_s0_payload_context; + wire [9:0] read_ports_0_buffer_s0_payload_address; + reg read_ports_0_buffer_s1_valid; + reg [2:0] read_ports_0_buffer_s1_payload_context; + reg [9:0] read_ports_0_buffer_s1_payload_address; + wire [0:0] read_ports_0_buffer_groupSel; + wire read_ports_0_buffer_bufferIn_valid; + wire read_ports_0_buffer_bufferIn_ready; + wire [63:0] read_ports_0_buffer_bufferIn_payload_data; + wire [7:0] read_ports_0_buffer_bufferIn_payload_mask; + wire [2:0] read_ports_0_buffer_bufferIn_payload_context; + wire read_ports_0_buffer_bufferOut_valid; + wire read_ports_0_buffer_bufferOut_ready; + wire [63:0] read_ports_0_buffer_bufferOut_payload_data; + wire [7:0] read_ports_0_buffer_bufferOut_payload_mask; + wire [2:0] read_ports_0_buffer_bufferOut_payload_context; + reg read_ports_0_buffer_bufferIn_rValidN; + reg [63:0] read_ports_0_buffer_bufferIn_rData_data; + reg [7:0] read_ports_0_buffer_bufferIn_rData_mask; + reg [2:0] read_ports_0_buffer_bufferIn_rData_context; + wire read_ports_0_buffer_full; + wire _zz_io_reads_0_cmd_ready; + wire read_ports_0_cmd_valid; + wire read_ports_0_cmd_ready; + wire [9:0] read_ports_0_cmd_payload_address; + wire [1:0] read_ports_0_cmd_payload_priority; + wire [2:0] read_ports_0_cmd_payload_context; + reg [3:0] read_ports_0_priority_value; + wire read_ports_1_buffer_s0_valid; + wire [11:0] read_ports_1_buffer_s0_payload_context; + wire [9:0] read_ports_1_buffer_s0_payload_address; + reg read_ports_1_buffer_s1_valid; + reg [11:0] read_ports_1_buffer_s1_payload_context; + reg [9:0] read_ports_1_buffer_s1_payload_address; + wire read_ports_1_buffer_bufferIn_valid; + wire read_ports_1_buffer_bufferIn_ready; + wire [127:0] read_ports_1_buffer_bufferIn_payload_data; + wire [15:0] read_ports_1_buffer_bufferIn_payload_mask; + wire [11:0] read_ports_1_buffer_bufferIn_payload_context; + wire read_ports_1_buffer_bufferOut_valid; + wire read_ports_1_buffer_bufferOut_ready; + wire [127:0] read_ports_1_buffer_bufferOut_payload_data; + wire [15:0] read_ports_1_buffer_bufferOut_payload_mask; + wire [11:0] read_ports_1_buffer_bufferOut_payload_context; + reg read_ports_1_buffer_bufferIn_rValidN; + reg [127:0] read_ports_1_buffer_bufferIn_rData_data; + reg [15:0] read_ports_1_buffer_bufferIn_rData_mask; + reg [11:0] read_ports_1_buffer_bufferIn_rData_context; + wire read_ports_1_buffer_full; + wire _zz_io_reads_1_cmd_ready; + wire read_ports_1_cmd_valid; + wire read_ports_1_cmd_ready; + wire [9:0] read_ports_1_cmd_payload_address; + wire [11:0] read_ports_1_cmd_payload_context; + wire read_nodes_0_0_priority; + wire read_nodes_0_0_conflict; + wire read_nodes_0_1_priority; + wire read_nodes_0_1_conflict; + wire read_nodes_1_0_priority; + wire read_nodes_1_0_conflict; + wire read_nodes_1_1_priority; + wire read_nodes_1_1_conflict; + wire [0:0] read_arbiter_0_losedAgainst; + wire read_arbiter_0_doIt; + reg _zz_banks_0_readOr_value_valid; + reg [8:0] _zz_banks_0_readOr_value_valid_1; + wire when_MemoryCore_l221; + reg _zz_banks_1_readOr_value_valid; + reg [8:0] _zz_banks_1_readOr_value_valid_1; + wire when_MemoryCore_l221_1; + wire [0:0] read_arbiter_1_losedAgainst; + wire read_arbiter_1_doIt; + reg _zz_banks_0_readOr_value_valid_2; + reg [8:0] _zz_banks_0_readOr_value_valid_3; + wire when_MemoryCore_l221_2; + reg _zz_banks_1_readOr_value_valid_2; + reg [8:0] _zz_banks_1_readOr_value_valid_3; + wire when_MemoryCore_l221_3; + reg [9:0] initialiser_counter; + wire initialiser_done; + wire when_MemoryCore_l239; + wire [71:0] _zz_banks_0_write_payload_data_data; + wire [71:0] _zz_banks_1_write_payload_data_data; + wire [81:0] _zz_banks_0_writeOr_value_valid_8; + wire [80:0] _zz_banks_0_writeOr_value_payload_address; + wire [71:0] _zz_banks_0_writeOr_value_payload_data_data; + wire [9:0] _zz_banks_0_readOr_value_valid_4; + wire [81:0] _zz_banks_1_writeOr_value_valid_8; + wire [80:0] _zz_banks_1_writeOr_value_payload_address; + wire [71:0] _zz_banks_1_writeOr_value_payload_data_data; + wire [9:0] _zz_banks_1_readOr_value_valid_4; + (* ram_style = "block" *) reg [71:0] banks_0_ram [0:511]; + (* ram_style = "block" *) reg [71:0] banks_1_ram [0:511]; + + assign _zz_write_ports_0_priority_value = {2'd0, io_writes_0_cmd_payload_priority}; + assign _zz_when_MemoryCore_l136 = (io_writes_0_cmd_payload_address ^ 10'h0); + assign _zz_when_MemoryCore_l136_1 = (io_writes_0_cmd_payload_address ^ 10'h001); + assign _zz_read_ports_0_priority_value = {2'd0, read_ports_0_cmd_payload_priority}; + assign _zz_when_MemoryCore_l221 = (read_ports_0_cmd_payload_address ^ 10'h0); + assign _zz_when_MemoryCore_l221_1 = (read_ports_0_cmd_payload_address ^ 10'h001); + assign _zz_banks_0_ram_port = {banks_0_write_payload_data_mask,banks_0_write_payload_data_data}; + assign _zz_banks_1_ram_port = {banks_1_write_payload_data_mask,banks_1_write_payload_data_data}; + always @(posedge clk) begin + if(_zz_2) begin + banks_0_ram[banks_0_write_payload_address] <= _zz_banks_0_ram_port; + end + end + + always @(posedge clk) begin + if(banks_0_read_cmd_valid) begin + banks_0_ram_spinal_port1 <= banks_0_ram[banks_0_read_cmd_payload]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin + banks_1_ram[banks_1_write_payload_address] <= _zz_banks_1_ram_port; + end + end + + always @(posedge clk) begin + if(banks_1_read_cmd_valid) begin + banks_1_ram_spinal_port1 <= banks_1_ram[banks_1_read_cmd_payload]; + end + end + + initial begin + `ifndef SYNTHESIS + write_ports_0_priority_value = {$urandom}; + read_ports_0_priority_value = {$urandom}; + `endif + end + + always @(*) begin + case(read_ports_0_buffer_groupSel) + 1'b0 : begin + _zz_read_ports_0_buffer_bufferIn_payload_data = banks_0_read_rsp_data; + _zz_read_ports_0_buffer_bufferIn_payload_mask = banks_0_read_rsp_mask; + end + default : begin + _zz_read_ports_0_buffer_bufferIn_payload_data = banks_1_read_rsp_data; + _zz_read_ports_0_buffer_bufferIn_payload_mask = banks_1_read_rsp_mask; + end + endcase + end + + always @(*) begin + _zz_1 = 1'b0; + if(banks_1_write_valid) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + _zz_2 = 1'b0; + if(banks_0_write_valid) begin + _zz_2 = 1'b1; + end + end + + assign _zz_banks_0_read_rsp_data = banks_0_ram_spinal_port1; + assign banks_0_read_rsp_data = _zz_banks_0_read_rsp_data[63 : 0]; + assign banks_0_read_rsp_mask = _zz_banks_0_read_rsp_data[71 : 64]; + always @(*) begin + banks_0_write_valid = banks_0_writeOr_value_valid; + if(when_MemoryCore_l239) begin + banks_0_write_valid = 1'b1; + end + end + + always @(*) begin + banks_0_write_payload_address = banks_0_writeOr_value_payload_address; + if(when_MemoryCore_l239) begin + banks_0_write_payload_address = initialiser_counter[8:0]; + end + end + + always @(*) begin + banks_0_write_payload_data_data = banks_0_writeOr_value_payload_data_data; + if(when_MemoryCore_l239) begin + banks_0_write_payload_data_data = _zz_banks_0_write_payload_data_data[63 : 0]; + end + end + + always @(*) begin + banks_0_write_payload_data_mask = banks_0_writeOr_value_payload_data_mask; + if(when_MemoryCore_l239) begin + banks_0_write_payload_data_mask = _zz_banks_0_write_payload_data_data[71 : 64]; + end + end + + assign banks_0_read_cmd_valid = banks_0_readOr_value_valid; + assign banks_0_read_cmd_payload = banks_0_readOr_value_payload; + assign _zz_banks_1_read_rsp_data = banks_1_ram_spinal_port1; + assign banks_1_read_rsp_data = _zz_banks_1_read_rsp_data[63 : 0]; + assign banks_1_read_rsp_mask = _zz_banks_1_read_rsp_data[71 : 64]; + always @(*) begin + banks_1_write_valid = banks_1_writeOr_value_valid; + if(when_MemoryCore_l239) begin + banks_1_write_valid = 1'b1; + end + end + + always @(*) begin + banks_1_write_payload_address = banks_1_writeOr_value_payload_address; + if(when_MemoryCore_l239) begin + banks_1_write_payload_address = initialiser_counter[8:0]; + end + end + + always @(*) begin + banks_1_write_payload_data_data = banks_1_writeOr_value_payload_data_data; + if(when_MemoryCore_l239) begin + banks_1_write_payload_data_data = _zz_banks_1_write_payload_data_data[63 : 0]; + end + end + + always @(*) begin + banks_1_write_payload_data_mask = banks_1_writeOr_value_payload_data_mask; + if(when_MemoryCore_l239) begin + banks_1_write_payload_data_mask = _zz_banks_1_write_payload_data_data[71 : 64]; + end + end + + assign banks_1_read_cmd_valid = banks_1_readOr_value_valid; + assign banks_1_read_cmd_payload = banks_1_readOr_value_payload; + assign write_nodes_0_1_priority = 1'b0; + assign write_nodes_1_0_priority = 1'b1; + assign write_nodes_0_1_conflict = ((io_writes_0_cmd_valid && io_writes_1_cmd_valid) && (((io_writes_0_cmd_payload_address ^ io_writes_1_cmd_payload_address) & 10'h0) == 10'h0)); + assign write_nodes_1_0_conflict = write_nodes_0_1_conflict; + assign write_arbiter_0_losedAgainst = (write_nodes_0_1_conflict && (! write_nodes_0_1_priority)); + always @(*) begin + write_arbiter_0_doIt = (io_writes_0_cmd_valid && (write_arbiter_0_losedAgainst == 1'b0)); + if(when_MemoryCore_l239) begin + write_arbiter_0_doIt = 1'b0; + end + end + + assign when_MemoryCore_l136 = (write_arbiter_0_doIt && (_zz_when_MemoryCore_l136[0 : 0] == 1'b0)); + always @(*) begin + if(when_MemoryCore_l136) begin + _zz_banks_0_writeOr_value_valid = 1'b1; + end else begin + _zz_banks_0_writeOr_value_valid = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l136) begin + _zz_banks_0_writeOr_value_valid_1 = (io_writes_0_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_0_writeOr_value_valid_1 = 9'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136) begin + _zz_banks_0_writeOr_value_valid_2 = io_writes_0_cmd_payload_data[63 : 0]; + end else begin + _zz_banks_0_writeOr_value_valid_2 = 64'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136) begin + _zz_banks_0_writeOr_value_valid_3 = io_writes_0_cmd_payload_mask[7 : 0]; + end else begin + _zz_banks_0_writeOr_value_valid_3 = 8'h0; + end + end + + assign when_MemoryCore_l136_1 = (write_arbiter_0_doIt && (_zz_when_MemoryCore_l136_1[0 : 0] == 1'b0)); + always @(*) begin + if(when_MemoryCore_l136_1) begin + _zz_banks_1_writeOr_value_valid = 1'b1; + end else begin + _zz_banks_1_writeOr_value_valid = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_1) begin + _zz_banks_1_writeOr_value_valid_1 = (io_writes_0_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_1_writeOr_value_valid_1 = 9'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_1) begin + _zz_banks_1_writeOr_value_valid_2 = io_writes_0_cmd_payload_data[63 : 0]; + end else begin + _zz_banks_1_writeOr_value_valid_2 = 64'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_1) begin + _zz_banks_1_writeOr_value_valid_3 = io_writes_0_cmd_payload_mask[7 : 0]; + end else begin + _zz_banks_1_writeOr_value_valid_3 = 8'h0; + end + end + + assign io_writes_0_cmd_ready = write_arbiter_0_doIt; + assign io_writes_0_rsp_valid = write_arbiter_0_doIt_regNext; + assign io_writes_0_rsp_payload_context = io_writes_0_cmd_payload_context_regNext; + assign write_arbiter_1_losedAgainst = (write_nodes_1_0_conflict && (! write_nodes_1_0_priority)); + always @(*) begin + write_arbiter_1_doIt = (io_writes_1_cmd_valid && (write_arbiter_1_losedAgainst == 1'b0)); + if(when_MemoryCore_l239) begin + write_arbiter_1_doIt = 1'b0; + end + end + + assign when_MemoryCore_l136_2 = (write_arbiter_1_doIt && 1'b1); + always @(*) begin + if(when_MemoryCore_l136_2) begin + _zz_banks_0_writeOr_value_valid_4 = 1'b1; + end else begin + _zz_banks_0_writeOr_value_valid_4 = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_2) begin + _zz_banks_0_writeOr_value_valid_5 = (io_writes_1_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_0_writeOr_value_valid_5 = 9'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_2) begin + _zz_banks_0_writeOr_value_valid_6 = io_writes_1_cmd_payload_data[63 : 0]; + end else begin + _zz_banks_0_writeOr_value_valid_6 = 64'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_2) begin + _zz_banks_0_writeOr_value_valid_7 = io_writes_1_cmd_payload_mask[7 : 0]; + end else begin + _zz_banks_0_writeOr_value_valid_7 = 8'h0; + end + end + + assign when_MemoryCore_l136_3 = (write_arbiter_1_doIt && 1'b1); + always @(*) begin + if(when_MemoryCore_l136_3) begin + _zz_banks_1_writeOr_value_valid_4 = 1'b1; + end else begin + _zz_banks_1_writeOr_value_valid_4 = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_3) begin + _zz_banks_1_writeOr_value_valid_5 = (io_writes_1_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_1_writeOr_value_valid_5 = 9'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_3) begin + _zz_banks_1_writeOr_value_valid_6 = io_writes_1_cmd_payload_data[127 : 64]; + end else begin + _zz_banks_1_writeOr_value_valid_6 = 64'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_3) begin + _zz_banks_1_writeOr_value_valid_7 = io_writes_1_cmd_payload_mask[15 : 8]; + end else begin + _zz_banks_1_writeOr_value_valid_7 = 8'h0; + end + end + + assign io_writes_1_cmd_ready = write_arbiter_1_doIt; + assign io_writes_1_rsp_valid = write_arbiter_1_doIt_regNext; + assign io_writes_1_rsp_payload_context = io_writes_1_cmd_payload_context_regNext; + assign read_ports_0_buffer_groupSel = read_ports_0_buffer_s1_payload_address[0 : 0]; + assign read_ports_0_buffer_bufferIn_valid = read_ports_0_buffer_s1_valid; + assign read_ports_0_buffer_bufferIn_payload_context = read_ports_0_buffer_s1_payload_context; + assign read_ports_0_buffer_bufferIn_payload_data = _zz_read_ports_0_buffer_bufferIn_payload_data; + assign read_ports_0_buffer_bufferIn_payload_mask = _zz_read_ports_0_buffer_bufferIn_payload_mask; + assign read_ports_0_buffer_bufferIn_ready = read_ports_0_buffer_bufferIn_rValidN; + assign read_ports_0_buffer_bufferOut_valid = (read_ports_0_buffer_bufferIn_valid || (! read_ports_0_buffer_bufferIn_rValidN)); + assign read_ports_0_buffer_bufferOut_payload_data = (read_ports_0_buffer_bufferIn_rValidN ? read_ports_0_buffer_bufferIn_payload_data : read_ports_0_buffer_bufferIn_rData_data); + assign read_ports_0_buffer_bufferOut_payload_mask = (read_ports_0_buffer_bufferIn_rValidN ? read_ports_0_buffer_bufferIn_payload_mask : read_ports_0_buffer_bufferIn_rData_mask); + assign read_ports_0_buffer_bufferOut_payload_context = (read_ports_0_buffer_bufferIn_rValidN ? read_ports_0_buffer_bufferIn_payload_context : read_ports_0_buffer_bufferIn_rData_context); + assign io_reads_0_rsp_valid = read_ports_0_buffer_bufferOut_valid; + assign read_ports_0_buffer_bufferOut_ready = io_reads_0_rsp_ready; + assign io_reads_0_rsp_payload_data = read_ports_0_buffer_bufferOut_payload_data; + assign io_reads_0_rsp_payload_mask = read_ports_0_buffer_bufferOut_payload_mask; + assign io_reads_0_rsp_payload_context = read_ports_0_buffer_bufferOut_payload_context; + assign read_ports_0_buffer_full = (read_ports_0_buffer_bufferOut_valid && (! read_ports_0_buffer_bufferOut_ready)); + assign _zz_io_reads_0_cmd_ready = (! read_ports_0_buffer_full); + assign read_ports_0_cmd_valid = (io_reads_0_cmd_valid && _zz_io_reads_0_cmd_ready); + assign io_reads_0_cmd_ready = (read_ports_0_cmd_ready && _zz_io_reads_0_cmd_ready); + assign read_ports_0_cmd_payload_address = io_reads_0_cmd_payload_address; + assign read_ports_0_cmd_payload_priority = io_reads_0_cmd_payload_priority; + assign read_ports_0_cmd_payload_context = io_reads_0_cmd_payload_context; + assign read_ports_1_buffer_bufferIn_valid = read_ports_1_buffer_s1_valid; + assign read_ports_1_buffer_bufferIn_payload_context = read_ports_1_buffer_s1_payload_context; + assign read_ports_1_buffer_bufferIn_payload_data = {banks_1_read_rsp_data,banks_0_read_rsp_data}; + assign read_ports_1_buffer_bufferIn_payload_mask = {banks_1_read_rsp_mask,banks_0_read_rsp_mask}; + assign read_ports_1_buffer_bufferIn_ready = read_ports_1_buffer_bufferIn_rValidN; + assign read_ports_1_buffer_bufferOut_valid = (read_ports_1_buffer_bufferIn_valid || (! read_ports_1_buffer_bufferIn_rValidN)); + assign read_ports_1_buffer_bufferOut_payload_data = (read_ports_1_buffer_bufferIn_rValidN ? read_ports_1_buffer_bufferIn_payload_data : read_ports_1_buffer_bufferIn_rData_data); + assign read_ports_1_buffer_bufferOut_payload_mask = (read_ports_1_buffer_bufferIn_rValidN ? read_ports_1_buffer_bufferIn_payload_mask : read_ports_1_buffer_bufferIn_rData_mask); + assign read_ports_1_buffer_bufferOut_payload_context = (read_ports_1_buffer_bufferIn_rValidN ? read_ports_1_buffer_bufferIn_payload_context : read_ports_1_buffer_bufferIn_rData_context); + assign io_reads_1_rsp_valid = read_ports_1_buffer_bufferOut_valid; + assign read_ports_1_buffer_bufferOut_ready = io_reads_1_rsp_ready; + assign io_reads_1_rsp_payload_data = read_ports_1_buffer_bufferOut_payload_data; + assign io_reads_1_rsp_payload_mask = read_ports_1_buffer_bufferOut_payload_mask; + assign io_reads_1_rsp_payload_context = read_ports_1_buffer_bufferOut_payload_context; + assign read_ports_1_buffer_full = (read_ports_1_buffer_bufferOut_valid && (! read_ports_1_buffer_bufferOut_ready)); + assign _zz_io_reads_1_cmd_ready = (! read_ports_1_buffer_full); + assign read_ports_1_cmd_valid = (io_reads_1_cmd_valid && _zz_io_reads_1_cmd_ready); + assign io_reads_1_cmd_ready = (read_ports_1_cmd_ready && _zz_io_reads_1_cmd_ready); + assign read_ports_1_cmd_payload_address = io_reads_1_cmd_payload_address; + assign read_ports_1_cmd_payload_context = io_reads_1_cmd_payload_context; + assign read_nodes_0_1_priority = 1'b0; + assign read_nodes_1_0_priority = 1'b1; + assign read_nodes_0_1_conflict = ((read_ports_0_cmd_valid && read_ports_1_cmd_valid) && (((read_ports_0_cmd_payload_address ^ io_reads_1_cmd_payload_address) & 10'h0) == 10'h0)); + assign read_nodes_1_0_conflict = read_nodes_0_1_conflict; + assign read_arbiter_0_losedAgainst = (read_nodes_0_1_conflict && (! read_nodes_0_1_priority)); + assign read_arbiter_0_doIt = (read_ports_0_cmd_valid && (read_arbiter_0_losedAgainst == 1'b0)); + assign when_MemoryCore_l221 = (read_arbiter_0_doIt && (_zz_when_MemoryCore_l221[0 : 0] == 1'b0)); + always @(*) begin + if(when_MemoryCore_l221) begin + _zz_banks_0_readOr_value_valid = 1'b1; + end else begin + _zz_banks_0_readOr_value_valid = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l221) begin + _zz_banks_0_readOr_value_valid_1 = (read_ports_0_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_0_readOr_value_valid_1 = 9'h0; + end + end + + assign when_MemoryCore_l221_1 = (read_arbiter_0_doIt && (_zz_when_MemoryCore_l221_1[0 : 0] == 1'b0)); + always @(*) begin + if(when_MemoryCore_l221_1) begin + _zz_banks_1_readOr_value_valid = 1'b1; + end else begin + _zz_banks_1_readOr_value_valid = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l221_1) begin + _zz_banks_1_readOr_value_valid_1 = (read_ports_0_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_1_readOr_value_valid_1 = 9'h0; + end + end + + assign read_ports_0_cmd_ready = read_arbiter_0_doIt; + assign read_ports_0_buffer_s0_valid = read_arbiter_0_doIt; + assign read_ports_0_buffer_s0_payload_context = read_ports_0_cmd_payload_context; + assign read_ports_0_buffer_s0_payload_address = read_ports_0_cmd_payload_address; + assign read_arbiter_1_losedAgainst = (read_nodes_1_0_conflict && (! read_nodes_1_0_priority)); + assign read_arbiter_1_doIt = (read_ports_1_cmd_valid && (read_arbiter_1_losedAgainst == 1'b0)); + assign when_MemoryCore_l221_2 = (read_arbiter_1_doIt && 1'b1); + always @(*) begin + if(when_MemoryCore_l221_2) begin + _zz_banks_0_readOr_value_valid_2 = 1'b1; + end else begin + _zz_banks_0_readOr_value_valid_2 = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l221_2) begin + _zz_banks_0_readOr_value_valid_3 = (read_ports_1_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_0_readOr_value_valid_3 = 9'h0; + end + end + + assign when_MemoryCore_l221_3 = (read_arbiter_1_doIt && 1'b1); + always @(*) begin + if(when_MemoryCore_l221_3) begin + _zz_banks_1_readOr_value_valid_2 = 1'b1; + end else begin + _zz_banks_1_readOr_value_valid_2 = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l221_3) begin + _zz_banks_1_readOr_value_valid_3 = (read_ports_1_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_1_readOr_value_valid_3 = 9'h0; + end + end + + assign read_ports_1_cmd_ready = read_arbiter_1_doIt; + assign read_ports_1_buffer_s0_valid = read_arbiter_1_doIt; + assign read_ports_1_buffer_s0_payload_context = read_ports_1_cmd_payload_context; + assign read_ports_1_buffer_s0_payload_address = read_ports_1_cmd_payload_address; + assign initialiser_done = initialiser_counter[9]; + assign when_MemoryCore_l239 = (! initialiser_done); + assign _zz_banks_0_write_payload_data_data = 72'h0; + assign _zz_banks_1_write_payload_data_data = 72'h0; + assign _zz_banks_0_writeOr_value_valid_8 = ({{{_zz_banks_0_writeOr_value_valid_3,_zz_banks_0_writeOr_value_valid_2},_zz_banks_0_writeOr_value_valid_1},_zz_banks_0_writeOr_value_valid} | {{{_zz_banks_0_writeOr_value_valid_7,_zz_banks_0_writeOr_value_valid_6},_zz_banks_0_writeOr_value_valid_5},_zz_banks_0_writeOr_value_valid_4}); + assign banks_0_writeOr_value_valid = _zz_banks_0_writeOr_value_valid_8[0]; + assign _zz_banks_0_writeOr_value_payload_address = _zz_banks_0_writeOr_value_valid_8[81 : 1]; + assign banks_0_writeOr_value_payload_address = _zz_banks_0_writeOr_value_payload_address[8 : 0]; + assign _zz_banks_0_writeOr_value_payload_data_data = _zz_banks_0_writeOr_value_payload_address[80 : 9]; + assign banks_0_writeOr_value_payload_data_data = _zz_banks_0_writeOr_value_payload_data_data[63 : 0]; + assign banks_0_writeOr_value_payload_data_mask = _zz_banks_0_writeOr_value_payload_data_data[71 : 64]; + assign _zz_banks_0_readOr_value_valid_4 = ({_zz_banks_0_readOr_value_valid_1,_zz_banks_0_readOr_value_valid} | {_zz_banks_0_readOr_value_valid_3,_zz_banks_0_readOr_value_valid_2}); + assign banks_0_readOr_value_valid = _zz_banks_0_readOr_value_valid_4[0]; + assign banks_0_readOr_value_payload = _zz_banks_0_readOr_value_valid_4[9 : 1]; + assign _zz_banks_1_writeOr_value_valid_8 = ({{{_zz_banks_1_writeOr_value_valid_3,_zz_banks_1_writeOr_value_valid_2},_zz_banks_1_writeOr_value_valid_1},_zz_banks_1_writeOr_value_valid} | {{{_zz_banks_1_writeOr_value_valid_7,_zz_banks_1_writeOr_value_valid_6},_zz_banks_1_writeOr_value_valid_5},_zz_banks_1_writeOr_value_valid_4}); + assign banks_1_writeOr_value_valid = _zz_banks_1_writeOr_value_valid_8[0]; + assign _zz_banks_1_writeOr_value_payload_address = _zz_banks_1_writeOr_value_valid_8[81 : 1]; + assign banks_1_writeOr_value_payload_address = _zz_banks_1_writeOr_value_payload_address[8 : 0]; + assign _zz_banks_1_writeOr_value_payload_data_data = _zz_banks_1_writeOr_value_payload_address[80 : 9]; + assign banks_1_writeOr_value_payload_data_data = _zz_banks_1_writeOr_value_payload_data_data[63 : 0]; + assign banks_1_writeOr_value_payload_data_mask = _zz_banks_1_writeOr_value_payload_data_data[71 : 64]; + assign _zz_banks_1_readOr_value_valid_4 = ({_zz_banks_1_readOr_value_valid_1,_zz_banks_1_readOr_value_valid} | {_zz_banks_1_readOr_value_valid_3,_zz_banks_1_readOr_value_valid_2}); + assign banks_1_readOr_value_valid = _zz_banks_1_readOr_value_valid_4[0]; + assign banks_1_readOr_value_payload = _zz_banks_1_readOr_value_valid_4[9 : 1]; + always @(posedge clk) begin + if(io_writes_0_cmd_valid) begin + write_ports_0_priority_value <= (write_ports_0_priority_value + _zz_write_ports_0_priority_value); + if(io_writes_0_cmd_ready) begin + write_ports_0_priority_value <= 4'b0000; + end + end + io_writes_0_cmd_payload_context_regNext <= io_writes_0_cmd_payload_context; + io_writes_1_cmd_payload_context_regNext <= io_writes_1_cmd_payload_context; + read_ports_0_buffer_s1_payload_context <= read_ports_0_buffer_s0_payload_context; + read_ports_0_buffer_s1_payload_address <= read_ports_0_buffer_s0_payload_address; + if(read_ports_0_buffer_bufferIn_ready) begin + read_ports_0_buffer_bufferIn_rData_data <= read_ports_0_buffer_bufferIn_payload_data; + read_ports_0_buffer_bufferIn_rData_mask <= read_ports_0_buffer_bufferIn_payload_mask; + read_ports_0_buffer_bufferIn_rData_context <= read_ports_0_buffer_bufferIn_payload_context; + end + if(read_ports_0_cmd_valid) begin + read_ports_0_priority_value <= (read_ports_0_priority_value + _zz_read_ports_0_priority_value); + if(read_ports_0_cmd_ready) begin + read_ports_0_priority_value <= 4'b0000; + end + end + read_ports_1_buffer_s1_payload_context <= read_ports_1_buffer_s0_payload_context; + read_ports_1_buffer_s1_payload_address <= read_ports_1_buffer_s0_payload_address; + if(read_ports_1_buffer_bufferIn_ready) begin + read_ports_1_buffer_bufferIn_rData_data <= read_ports_1_buffer_bufferIn_payload_data; + read_ports_1_buffer_bufferIn_rData_mask <= read_ports_1_buffer_bufferIn_payload_mask; + read_ports_1_buffer_bufferIn_rData_context <= read_ports_1_buffer_bufferIn_payload_context; + end + end + + always @(posedge clk) begin + if(reset) begin + write_arbiter_0_doIt_regNext <= 1'b0; + write_arbiter_1_doIt_regNext <= 1'b0; + read_ports_0_buffer_s1_valid <= 1'b0; + read_ports_0_buffer_bufferIn_rValidN <= 1'b1; + read_ports_1_buffer_s1_valid <= 1'b0; + read_ports_1_buffer_bufferIn_rValidN <= 1'b1; + initialiser_counter <= 10'h0; + end else begin + write_arbiter_0_doIt_regNext <= write_arbiter_0_doIt; + write_arbiter_1_doIt_regNext <= write_arbiter_1_doIt; + read_ports_0_buffer_s1_valid <= read_ports_0_buffer_s0_valid; + if(read_ports_0_buffer_bufferIn_valid) begin + read_ports_0_buffer_bufferIn_rValidN <= 1'b0; + end + if(read_ports_0_buffer_bufferOut_ready) begin + read_ports_0_buffer_bufferIn_rValidN <= 1'b1; + end + read_ports_1_buffer_s1_valid <= read_ports_1_buffer_s0_valid; + if(read_ports_1_buffer_bufferIn_valid) begin + read_ports_1_buffer_bufferIn_rValidN <= 1'b0; + end + if(read_ports_1_buffer_bufferOut_ready) begin + read_ports_1_buffer_bufferIn_rValidN <= 1'b1; + end + if(when_MemoryCore_l239) begin + initialiser_counter <= (initialiser_counter + 10'h001); + end + end + end + + +endmodule + +module EfxDMA_StreamFifo_1 ( + input wire io_push_valid, + output wire io_push_ready, + input wire [13:0] io_push_payload_context, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [13:0] io_pop_payload_context, + input wire io_flush, + output wire [2:0] io_occupancy, + output wire [2:0] io_availability, + input wire clk, + input wire reset +); + + reg [13:0] logic_ram_spinal_port1; + wire [2:0] _zz_logic_ptr_notPow2_counter; + wire [2:0] _zz_logic_ptr_notPow2_counter_1; + wire [0:0] _zz_logic_ptr_notPow2_counter_2; + wire [2:0] _zz_logic_ptr_notPow2_counter_3; + wire [0:0] _zz_logic_ptr_notPow2_counter_4; + reg _zz_1; + wire logic_ptr_doPush; + wire logic_ptr_doPop; + wire logic_ptr_full; + wire logic_ptr_empty; + reg [2:0] logic_ptr_push; + reg [2:0] logic_ptr_pop; + wire [2:0] logic_ptr_occupancy; + wire [2:0] logic_ptr_popOnIo; + wire when_Stream_l1248; + reg logic_ptr_wentUp; + wire when_Stream_l1283; + wire when_Stream_l1287; + reg [2:0] logic_ptr_notPow2_counter; + wire io_push_fire; + wire io_pop_fire; + wire logic_push_onRam_write_valid; + wire [2:0] logic_push_onRam_write_payload_address; + wire [13:0] logic_push_onRam_write_payload_data_context; + wire logic_pop_addressGen_valid; + reg logic_pop_addressGen_ready; + wire [2:0] logic_pop_addressGen_payload; + wire logic_pop_addressGen_fire; + wire logic_pop_sync_readArbitation_valid; + wire logic_pop_sync_readArbitation_ready; + wire [2:0] logic_pop_sync_readArbitation_payload; + reg logic_pop_addressGen_rValid; + reg [2:0] logic_pop_addressGen_rData; + wire when_Stream_l375; + wire logic_pop_sync_readPort_cmd_valid; + wire [2:0] logic_pop_sync_readPort_cmd_payload; + wire [13:0] logic_pop_sync_readPort_rsp_context; + wire logic_pop_sync_readArbitation_translated_valid; + wire logic_pop_sync_readArbitation_translated_ready; + wire [13:0] logic_pop_sync_readArbitation_translated_payload_context; + wire logic_pop_sync_readArbitation_fire; + reg [2:0] logic_pop_sync_popReg; + reg [13:0] logic_ram [0:6]; + + assign _zz_logic_ptr_notPow2_counter = (logic_ptr_notPow2_counter + _zz_logic_ptr_notPow2_counter_1); + assign _zz_logic_ptr_notPow2_counter_2 = io_push_fire; + assign _zz_logic_ptr_notPow2_counter_1 = {2'd0, _zz_logic_ptr_notPow2_counter_2}; + assign _zz_logic_ptr_notPow2_counter_4 = io_pop_fire; + assign _zz_logic_ptr_notPow2_counter_3 = {2'd0, _zz_logic_ptr_notPow2_counter_4}; + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data_context; + end + end + + always @(posedge clk) begin + if(logic_pop_sync_readPort_cmd_valid) begin + logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_push_onRam_write_valid) begin + _zz_1 = 1'b1; + end + end + + assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); + assign logic_ptr_full = ((logic_ptr_push == logic_ptr_popOnIo) && logic_ptr_wentUp); + assign logic_ptr_empty = ((logic_ptr_push == logic_ptr_pop) && (! logic_ptr_wentUp)); + assign when_Stream_l1283 = (logic_ptr_push == 3'b110); + assign when_Stream_l1287 = (logic_ptr_pop == 3'b110); + assign io_push_fire = (io_push_valid && io_push_ready); + assign io_pop_fire = (io_pop_valid && io_pop_ready); + assign logic_ptr_occupancy = logic_ptr_notPow2_counter; + assign io_push_ready = (! logic_ptr_full); + assign logic_ptr_doPush = io_push_fire; + assign logic_push_onRam_write_valid = io_push_fire; + assign logic_push_onRam_write_payload_address = logic_ptr_push; + assign logic_push_onRam_write_payload_data_context = io_push_payload_context; + assign logic_pop_addressGen_valid = (! logic_ptr_empty); + assign logic_pop_addressGen_payload = logic_ptr_pop; + assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); + assign logic_ptr_doPop = logic_pop_addressGen_fire; + always @(*) begin + logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; + if(when_Stream_l375) begin + logic_pop_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); + assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; + assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; + assign logic_pop_sync_readPort_rsp_context = logic_ram_spinal_port1[13 : 0]; + assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; + assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; + assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; + assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; + assign logic_pop_sync_readArbitation_translated_payload_context = logic_pop_sync_readPort_rsp_context; + assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; + assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_context = logic_pop_sync_readArbitation_translated_payload_context; + assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); + assign logic_ptr_popOnIo = logic_pop_sync_popReg; + assign io_occupancy = logic_ptr_occupancy; + assign io_availability = (3'b111 - logic_ptr_occupancy); + always @(posedge clk) begin + if(reset) begin + logic_ptr_push <= 3'b000; + logic_ptr_pop <= 3'b000; + logic_ptr_wentUp <= 1'b0; + logic_ptr_notPow2_counter <= 3'b000; + logic_pop_addressGen_rValid <= 1'b0; + logic_pop_sync_popReg <= 3'b000; + end else begin + if(when_Stream_l1248) begin + logic_ptr_wentUp <= logic_ptr_doPush; + end + if(io_flush) begin + logic_ptr_wentUp <= 1'b0; + end + if(logic_ptr_doPush) begin + logic_ptr_push <= (logic_ptr_push + 3'b001); + if(when_Stream_l1283) begin + logic_ptr_push <= 3'b000; + end + end + if(logic_ptr_doPop) begin + logic_ptr_pop <= (logic_ptr_pop + 3'b001); + if(when_Stream_l1287) begin + logic_ptr_pop <= 3'b000; + end + end + if(io_flush) begin + logic_ptr_push <= 3'b000; + logic_ptr_pop <= 3'b000; + end + logic_ptr_notPow2_counter <= (_zz_logic_ptr_notPow2_counter - _zz_logic_ptr_notPow2_counter_3); + if(io_flush) begin + logic_ptr_notPow2_counter <= 3'b000; + end + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; + end + if(io_flush) begin + logic_pop_addressGen_rValid <= 1'b0; + end + if(logic_pop_sync_readArbitation_fire) begin + logic_pop_sync_popReg <= logic_ptr_pop; + end + if(io_flush) begin + logic_pop_sync_popReg <= 3'b000; + end + end + end + + always @(posedge clk) begin + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rData <= logic_pop_addressGen_payload; + end + end + + +endmodule + +module EfxDMA_StreamFifo ( + input wire io_push_valid, + output wire io_push_ready, + input wire [21:0] io_push_payload_context, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [21:0] io_pop_payload_context, + input wire io_flush, + output wire [2:0] io_occupancy, + output wire [2:0] io_availability, + input wire clk, + input wire reset +); + + reg [21:0] logic_ram_spinal_port1; + wire [2:0] _zz_logic_ptr_notPow2_counter; + wire [2:0] _zz_logic_ptr_notPow2_counter_1; + wire [0:0] _zz_logic_ptr_notPow2_counter_2; + wire [2:0] _zz_logic_ptr_notPow2_counter_3; + wire [0:0] _zz_logic_ptr_notPow2_counter_4; + reg _zz_1; + wire logic_ptr_doPush; + wire logic_ptr_doPop; + wire logic_ptr_full; + wire logic_ptr_empty; + reg [2:0] logic_ptr_push; + reg [2:0] logic_ptr_pop; + wire [2:0] logic_ptr_occupancy; + wire [2:0] logic_ptr_popOnIo; + wire when_Stream_l1248; + reg logic_ptr_wentUp; + wire when_Stream_l1283; + wire when_Stream_l1287; + reg [2:0] logic_ptr_notPow2_counter; + wire io_push_fire; + wire io_pop_fire; + wire logic_push_onRam_write_valid; + wire [2:0] logic_push_onRam_write_payload_address; + wire [21:0] logic_push_onRam_write_payload_data_context; + wire logic_pop_addressGen_valid; + reg logic_pop_addressGen_ready; + wire [2:0] logic_pop_addressGen_payload; + wire logic_pop_addressGen_fire; + wire logic_pop_sync_readArbitation_valid; + wire logic_pop_sync_readArbitation_ready; + wire [2:0] logic_pop_sync_readArbitation_payload; + reg logic_pop_addressGen_rValid; + reg [2:0] logic_pop_addressGen_rData; + wire when_Stream_l375; + wire logic_pop_sync_readPort_cmd_valid; + wire [2:0] logic_pop_sync_readPort_cmd_payload; + wire [21:0] logic_pop_sync_readPort_rsp_context; + wire logic_pop_sync_readArbitation_translated_valid; + wire logic_pop_sync_readArbitation_translated_ready; + wire [21:0] logic_pop_sync_readArbitation_translated_payload_context; + wire logic_pop_sync_readArbitation_fire; + reg [2:0] logic_pop_sync_popReg; + reg [21:0] logic_ram [0:6]; + + assign _zz_logic_ptr_notPow2_counter = (logic_ptr_notPow2_counter + _zz_logic_ptr_notPow2_counter_1); + assign _zz_logic_ptr_notPow2_counter_2 = io_push_fire; + assign _zz_logic_ptr_notPow2_counter_1 = {2'd0, _zz_logic_ptr_notPow2_counter_2}; + assign _zz_logic_ptr_notPow2_counter_4 = io_pop_fire; + assign _zz_logic_ptr_notPow2_counter_3 = {2'd0, _zz_logic_ptr_notPow2_counter_4}; + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data_context; + end + end + + always @(posedge clk) begin + if(logic_pop_sync_readPort_cmd_valid) begin + logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_push_onRam_write_valid) begin + _zz_1 = 1'b1; + end + end + + assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); + assign logic_ptr_full = ((logic_ptr_push == logic_ptr_popOnIo) && logic_ptr_wentUp); + assign logic_ptr_empty = ((logic_ptr_push == logic_ptr_pop) && (! logic_ptr_wentUp)); + assign when_Stream_l1283 = (logic_ptr_push == 3'b110); + assign when_Stream_l1287 = (logic_ptr_pop == 3'b110); + assign io_push_fire = (io_push_valid && io_push_ready); + assign io_pop_fire = (io_pop_valid && io_pop_ready); + assign logic_ptr_occupancy = logic_ptr_notPow2_counter; + assign io_push_ready = (! logic_ptr_full); + assign logic_ptr_doPush = io_push_fire; + assign logic_push_onRam_write_valid = io_push_fire; + assign logic_push_onRam_write_payload_address = logic_ptr_push; + assign logic_push_onRam_write_payload_data_context = io_push_payload_context; + assign logic_pop_addressGen_valid = (! logic_ptr_empty); + assign logic_pop_addressGen_payload = logic_ptr_pop; + assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); + assign logic_ptr_doPop = logic_pop_addressGen_fire; + always @(*) begin + logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; + if(when_Stream_l375) begin + logic_pop_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); + assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; + assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; + assign logic_pop_sync_readPort_rsp_context = logic_ram_spinal_port1[21 : 0]; + assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; + assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; + assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; + assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; + assign logic_pop_sync_readArbitation_translated_payload_context = logic_pop_sync_readPort_rsp_context; + assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; + assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_context = logic_pop_sync_readArbitation_translated_payload_context; + assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); + assign logic_ptr_popOnIo = logic_pop_sync_popReg; + assign io_occupancy = logic_ptr_occupancy; + assign io_availability = (3'b111 - logic_ptr_occupancy); + always @(posedge clk) begin + if(reset) begin + logic_ptr_push <= 3'b000; + logic_ptr_pop <= 3'b000; + logic_ptr_wentUp <= 1'b0; + logic_ptr_notPow2_counter <= 3'b000; + logic_pop_addressGen_rValid <= 1'b0; + logic_pop_sync_popReg <= 3'b000; + end else begin + if(when_Stream_l1248) begin + logic_ptr_wentUp <= logic_ptr_doPush; + end + if(io_flush) begin + logic_ptr_wentUp <= 1'b0; + end + if(logic_ptr_doPush) begin + logic_ptr_push <= (logic_ptr_push + 3'b001); + if(when_Stream_l1283) begin + logic_ptr_push <= 3'b000; + end + end + if(logic_ptr_doPop) begin + logic_ptr_pop <= (logic_ptr_pop + 3'b001); + if(when_Stream_l1287) begin + logic_ptr_pop <= 3'b000; + end + end + if(io_flush) begin + logic_ptr_push <= 3'b000; + logic_ptr_pop <= 3'b000; + end + logic_ptr_notPow2_counter <= (_zz_logic_ptr_notPow2_counter - _zz_logic_ptr_notPow2_counter_3); + if(io_flush) begin + logic_ptr_notPow2_counter <= 3'b000; + end + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; + end + if(io_flush) begin + logic_pop_addressGen_rValid <= 1'b0; + end + if(logic_pop_sync_readArbitation_fire) begin + logic_pop_sync_popReg <= logic_ptr_pop; + end + if(io_flush) begin + logic_pop_sync_popReg <= 3'b000; + end + end + end + + always @(posedge clk) begin + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rData <= logic_pop_addressGen_payload; + end + end + + +endmodule + +module EfxDMA_BufferCC_1 ( + input wire io_dataIn, + output wire io_dataOut, + input wire ctrl_clk, + input wire ctrl_reset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge ctrl_clk) begin + if(ctrl_reset) begin + buffers_0 <= 1'b0; + buffers_1 <= 1'b0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module EfxDMA_BufferCC ( + input wire io_dataIn, + output wire io_dataOut, + input wire clk, + input wire reset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge clk) begin + if(reset) begin + buffers_0 <= 1'b0; + buffers_1 <= 1'b0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule diff --git a/fpga/ip/gDMA/source/dma_config.json b/fpga/ip/gDMA/source/dma_config.json new file mode 100644 index 0000000..1229f91 --- /dev/null +++ b/fpga/ip/gDMA/source/dma_config.json @@ -0,0 +1,71 @@ +{ + "name": "EfxDMA", + "efinix_ddr": false, + "with_sg_bus": false, + "with_ddr_write_queue": false, + "with_ddr_read_queue": false, + "ctrl": { + "asynchronous": true + }, + "buffer": { + "bank_count": 2, + "bank_width": 64, + "bank_words": 512 + }, + "read": { + "address_width": 32, + "data_width_external": 128, + "data_width_internal": 128 + }, + "write": { + "address_width": 32, + "data_width_external": 128, + "data_width_internal": 128 + }, + "channels": { + "c0": { + "progress_probe": true, + "direct_ctrl_capable": true, + "linked_list_capable": true, + "memory_to_memory": false, + "inputs": [ + "dat0_i" + ], + "half_completion_interrupt": false, + "self_restart_capable": false, + "bytes_per_burst": 1024, + "buffer_address": 0, + "buffer_size": 4096 + }, + "c1": { + "progress_probe": true, + "direct_ctrl_capable": true, + "linked_list_capable": true, + "memory_to_memory": false, + "outputs": [ + "dat1_o" + ], + "half_completion_interrupt": false, + "self_restart_capable": false, + "bytes_per_burst": 1024, + "buffer_address": 4096, + "buffer_size": 4096 + } + }, + "inputs": { + "dat0_i": { + "data_width": 8, + "tid_width": 0, + "tdest_width": 4, + "asynchronous": true + } + }, + "outputs": { + "dat1_o": { + "data_width": 8, + "tid_width": 0, + "tdest_width": 4, + "asynchronous": true + } + } +} \ No newline at end of file diff --git a/fpga/ip/gSDHC/gSDHC.v b/fpga/ip/gSDHC/gSDHC.v new file mode 100644 index 0000000..718f399 --- /dev/null +++ b/fpga/ip/gSDHC/gSDHC.v @@ -0,0 +1,12571 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 6.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _5b3f2212c953407c83e1cf8c9cc77ea9 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module gSDHC +( + input sd_rst, + input sd_base_clk, + output sd_int, + input sd_cd_n, + input sd_wp, + input [9:0] s_axi_awaddr, + input s_axi_aclk, + output s_axi_awready, + input s_axi_awvalid, + input [31:0] s_axi_wdata, + output s_axi_wready, + input s_axi_wvalid, + output [1:0] s_axi_bresp, + output s_axi_bvalid, + input [9:0] s_axi_araddr, + input s_axi_bready, + output s_axi_arready, + input s_axi_arvalid, + output [1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + output s_axi_rvalid, + input s_axi_rready, + output [31:0] m_axi_awaddr, + output m_axi_awvalid, + input m_axi_clk, + output [7:0] m_axi_awlen, + input m_axi_awready, + output [2:0] m_axi_awsize, + output [3:0] m_axi_awcache, + output [1:0] m_axi_awlock, + output [2:0] m_axi_awprot, + output m_axi_wlast, + output m_axi_wvalid, + input m_axi_wready, + input [1:0] m_axi_bresp, + input m_axi_bvalid, + output m_axi_bready, + output m_axi_arvalid, + output [31:0] m_axi_araddr, + output [7:0] m_axi_arlen, + output [2:0] m_axi_arsize, + output [1:0] m_axi_arburst, + output [2:0] m_axi_arprot, + output [1:0] m_axi_arlock, + output [3:0] m_axi_arcache, + input m_axi_arready, + input m_axi_rvalid, + input m_axi_rlast, + input [1:0] m_axi_rresp, + output m_axi_rready, + output sd_clk_hi, + output sd_clk_lo, + input sd_cmd_i, + output sd_cmd_o, + output sd_cmd_oe, + input [3:0] sd_dat_i, + output [3:0] sd_dat_o, + output sd_dat_oe, + output [1:0] m_axi_awburst, + output [127:0] m_axi_wdata, + output [15:0] m_axi_wstrb, + input [127:0] m_axi_rdata, + input [3:0] s_axi_wstrb +); +`IP_MODULE_NAME(sdhc) +#( + .DATA_BUFFER_DEPTH (512), + .ADMA_DATA_WIDTH (128) +) +u_sdhc +( + .sd_rst ( sd_rst ), + .sd_base_clk ( sd_base_clk ), + .sd_int ( sd_int ), + .sd_cd_n ( sd_cd_n ), + .sd_wp ( sd_wp ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_aclk ( s_axi_aclk ), + .s_axi_awready ( s_axi_awready ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_wready ( s_axi_wready ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_bready ( s_axi_bready ), + .s_axi_arready ( s_axi_arready ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rready ( s_axi_rready ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_clk ( m_axi_clk ), + .m_axi_awlen ( m_axi_awlen ), + .m_axi_awready ( m_axi_awready ), + .m_axi_awsize ( m_axi_awsize ), + .m_axi_awcache ( m_axi_awcache ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awprot ( m_axi_awprot ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wready ( m_axi_wready ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_bready ( m_axi_bready ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlen ( m_axi_arlen ), + .m_axi_arsize ( m_axi_arsize ), + .m_axi_arburst ( m_axi_arburst ), + .m_axi_arprot ( m_axi_arprot ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arcache ( m_axi_arcache ), + .m_axi_arready ( m_axi_arready ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_rready ( m_axi_rready ), + .sd_clk_hi ( sd_clk_hi ), + .sd_clk_lo ( sd_clk_lo ), + .sd_cmd_i ( sd_cmd_i ), + .sd_cmd_o ( sd_cmd_o ), + .sd_cmd_oe ( sd_cmd_oe ), + .sd_dat_i ( sd_dat_i ), + .sd_dat_o ( sd_dat_o ), + .sd_dat_oe ( sd_dat_oe ), + .m_axi_awburst ( m_axi_awburst ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_rdata ( m_axi_rdata ), + .s_axi_wstrb ( s_axi_wstrb ) +); +endmodule + +// Generator : SpinalHDL dev git head : 9cdee03b276638ef8e7a948b606bb7acc6e4c8d0 +// Component : Asic32To128UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 +// Git hash : cd16421fb7a4d44431a2445f9a92b82070ab9b8a + +`timescale 1ns/1ps + +module Asic32To128UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_aw_valid, + output io_input_aw_ready, + input [31:0] io_input_aw_payload_addr, + input [7:0] io_input_aw_payload_id, + input [3:0] io_input_aw_payload_region, + input [7:0] io_input_aw_payload_len, + input [2:0] io_input_aw_payload_size, + input [1:0] io_input_aw_payload_burst, + input [0:0] io_input_aw_payload_lock, + input [3:0] io_input_aw_payload_cache, + input [3:0] io_input_aw_payload_qos, + input [2:0] io_input_aw_payload_prot, + input io_input_w_valid, + output io_input_w_ready, + input [31:0] io_input_w_payload_data, + input [3:0] io_input_w_payload_strb, + input io_input_w_payload_last, + output io_input_b_valid, + input io_input_b_ready, + output [7:0] io_input_b_payload_id, + output [1:0] io_input_b_payload_resp, + input io_input_ar_valid, + output io_input_ar_ready, + input [31:0] io_input_ar_payload_addr, + input [7:0] io_input_ar_payload_id, + input [3:0] io_input_ar_payload_region, + input [7:0] io_input_ar_payload_len, + input [2:0] io_input_ar_payload_size, + input [1:0] io_input_ar_payload_burst, + input [0:0] io_input_ar_payload_lock, + input [3:0] io_input_ar_payload_cache, + input [3:0] io_input_ar_payload_qos, + input [2:0] io_input_ar_payload_prot, + output io_input_r_valid, + input io_input_r_ready, + output [31:0] io_input_r_payload_data, + output [7:0] io_input_r_payload_id, + output [1:0] io_input_r_payload_resp, + output io_input_r_payload_last, + output io_output_aw_valid, + input io_output_aw_ready, + output [31:0] io_output_aw_payload_addr, + output [7:0] io_output_aw_payload_id, + output [3:0] io_output_aw_payload_region, + output [7:0] io_output_aw_payload_len, + output [2:0] io_output_aw_payload_size, + output [1:0] io_output_aw_payload_burst, + output [0:0] io_output_aw_payload_lock, + output [3:0] io_output_aw_payload_cache, + output [3:0] io_output_aw_payload_qos, + output [2:0] io_output_aw_payload_prot, + output io_output_w_valid, + input io_output_w_ready, + output [127:0] io_output_w_payload_data, + output [15:0] io_output_w_payload_strb, + output io_output_w_payload_last, + input io_output_b_valid, + output io_output_b_ready, + input [7:0] io_output_b_payload_id, + input [1:0] io_output_b_payload_resp, + output io_output_ar_valid, + input io_output_ar_ready, + output [31:0] io_output_ar_payload_addr, + output [7:0] io_output_ar_payload_id, + output [3:0] io_output_ar_payload_region, + output [7:0] io_output_ar_payload_len, + output [2:0] io_output_ar_payload_size, + output [1:0] io_output_ar_payload_burst, + output [0:0] io_output_ar_payload_lock, + output [3:0] io_output_ar_payload_cache, + output [3:0] io_output_ar_payload_qos, + output [2:0] io_output_ar_payload_prot, + input io_output_r_valid, + output io_output_r_ready, + input [127:0] io_output_r_payload_data, + input [7:0] io_output_r_payload_id, + input [1:0] io_output_r_payload_resp, + input io_output_r_payload_last, + input clk, + input reset +); + + wire readOnly_io_input_ar_ready; + wire readOnly_io_input_r_valid; + wire [31:0] readOnly_io_input_r_payload_data; + wire [7:0] readOnly_io_input_r_payload_id; + wire [1:0] readOnly_io_input_r_payload_resp; + wire readOnly_io_input_r_payload_last; + wire readOnly_io_output_ar_valid; + wire [31:0] readOnly_io_output_ar_payload_addr; + wire [7:0] readOnly_io_output_ar_payload_id; + wire [3:0] readOnly_io_output_ar_payload_region; + wire [7:0] readOnly_io_output_ar_payload_len; + wire [2:0] readOnly_io_output_ar_payload_size; + wire [1:0] readOnly_io_output_ar_payload_burst; + wire [0:0] readOnly_io_output_ar_payload_lock; + wire [3:0] readOnly_io_output_ar_payload_cache; + wire [3:0] readOnly_io_output_ar_payload_qos; + wire [2:0] readOnly_io_output_ar_payload_prot; + wire readOnly_io_output_r_ready; + wire writeOnly_io_input_aw_ready; + wire writeOnly_io_input_w_ready; + wire writeOnly_io_input_b_valid; + wire [7:0] writeOnly_io_input_b_payload_id; + wire [1:0] writeOnly_io_input_b_payload_resp; + wire writeOnly_io_output_aw_valid; + wire [31:0] writeOnly_io_output_aw_payload_addr; + wire [7:0] writeOnly_io_output_aw_payload_id; + wire [3:0] writeOnly_io_output_aw_payload_region; + wire [7:0] writeOnly_io_output_aw_payload_len; + wire [2:0] writeOnly_io_output_aw_payload_size; + wire [1:0] writeOnly_io_output_aw_payload_burst; + wire [0:0] writeOnly_io_output_aw_payload_lock; + wire [3:0] writeOnly_io_output_aw_payload_cache; + wire [3:0] writeOnly_io_output_aw_payload_qos; + wire [2:0] writeOnly_io_output_aw_payload_prot; + wire writeOnly_io_output_w_valid; + wire [127:0] writeOnly_io_output_w_payload_data; + wire [15:0] writeOnly_io_output_w_payload_strb; + wire writeOnly_io_output_w_payload_last; + wire writeOnly_io_output_b_ready; + + Asic32To128UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 readOnly ( + .io_input_ar_valid (io_input_ar_valid ), //i + .io_input_ar_ready (readOnly_io_input_ar_ready ), //o + .io_input_ar_payload_addr (io_input_ar_payload_addr[31:0] ), //i + .io_input_ar_payload_id (io_input_ar_payload_id[7:0] ), //i + .io_input_ar_payload_region (io_input_ar_payload_region[3:0] ), //i + .io_input_ar_payload_len (io_input_ar_payload_len[7:0] ), //i + .io_input_ar_payload_size (io_input_ar_payload_size[2:0] ), //i + .io_input_ar_payload_burst (io_input_ar_payload_burst[1:0] ), //i + .io_input_ar_payload_lock (io_input_ar_payload_lock ), //i + .io_input_ar_payload_cache (io_input_ar_payload_cache[3:0] ), //i + .io_input_ar_payload_qos (io_input_ar_payload_qos[3:0] ), //i + .io_input_ar_payload_prot (io_input_ar_payload_prot[2:0] ), //i + .io_input_r_valid (readOnly_io_input_r_valid ), //o + .io_input_r_ready (io_input_r_ready ), //i + .io_input_r_payload_data (readOnly_io_input_r_payload_data[31:0] ), //o + .io_input_r_payload_id (readOnly_io_input_r_payload_id[7:0] ), //o + .io_input_r_payload_resp (readOnly_io_input_r_payload_resp[1:0] ), //o + .io_input_r_payload_last (readOnly_io_input_r_payload_last ), //o + .io_output_ar_valid (readOnly_io_output_ar_valid ), //o + .io_output_ar_ready (io_output_ar_ready ), //i + .io_output_ar_payload_addr (readOnly_io_output_ar_payload_addr[31:0] ), //o + .io_output_ar_payload_id (readOnly_io_output_ar_payload_id[7:0] ), //o + .io_output_ar_payload_region (readOnly_io_output_ar_payload_region[3:0]), //o + .io_output_ar_payload_len (readOnly_io_output_ar_payload_len[7:0] ), //o + .io_output_ar_payload_size (readOnly_io_output_ar_payload_size[2:0] ), //o + .io_output_ar_payload_burst (readOnly_io_output_ar_payload_burst[1:0] ), //o + .io_output_ar_payload_lock (readOnly_io_output_ar_payload_lock ), //o + .io_output_ar_payload_cache (readOnly_io_output_ar_payload_cache[3:0] ), //o + .io_output_ar_payload_qos (readOnly_io_output_ar_payload_qos[3:0] ), //o + .io_output_ar_payload_prot (readOnly_io_output_ar_payload_prot[2:0] ), //o + .io_output_r_valid (io_output_r_valid ), //i + .io_output_r_ready (readOnly_io_output_r_ready ), //o + .io_output_r_payload_data (io_output_r_payload_data[127:0] ), //i + .io_output_r_payload_id (io_output_r_payload_id[7:0] ), //i + .io_output_r_payload_resp (io_output_r_payload_resp[1:0] ), //i + .io_output_r_payload_last (io_output_r_payload_last ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Asic32To128UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 writeOnly ( + .io_input_aw_valid (io_input_aw_valid ), //i + .io_input_aw_ready (writeOnly_io_input_aw_ready ), //o + .io_input_aw_payload_addr (io_input_aw_payload_addr[31:0] ), //i + .io_input_aw_payload_id (io_input_aw_payload_id[7:0] ), //i + .io_input_aw_payload_region (io_input_aw_payload_region[3:0] ), //i + .io_input_aw_payload_len (io_input_aw_payload_len[7:0] ), //i + .io_input_aw_payload_size (io_input_aw_payload_size[2:0] ), //i + .io_input_aw_payload_burst (io_input_aw_payload_burst[1:0] ), //i + .io_input_aw_payload_lock (io_input_aw_payload_lock ), //i + .io_input_aw_payload_cache (io_input_aw_payload_cache[3:0] ), //i + .io_input_aw_payload_qos (io_input_aw_payload_qos[3:0] ), //i + .io_input_aw_payload_prot (io_input_aw_payload_prot[2:0] ), //i + .io_input_w_valid (io_input_w_valid ), //i + .io_input_w_ready (writeOnly_io_input_w_ready ), //o + .io_input_w_payload_data (io_input_w_payload_data[31:0] ), //i + .io_input_w_payload_strb (io_input_w_payload_strb[3:0] ), //i + .io_input_w_payload_last (io_input_w_payload_last ), //i + .io_input_b_valid (writeOnly_io_input_b_valid ), //o + .io_input_b_ready (io_input_b_ready ), //i + .io_input_b_payload_id (writeOnly_io_input_b_payload_id[7:0] ), //o + .io_input_b_payload_resp (writeOnly_io_input_b_payload_resp[1:0] ), //o + .io_output_aw_valid (writeOnly_io_output_aw_valid ), //o + .io_output_aw_ready (io_output_aw_ready ), //i + .io_output_aw_payload_addr (writeOnly_io_output_aw_payload_addr[31:0] ), //o + .io_output_aw_payload_id (writeOnly_io_output_aw_payload_id[7:0] ), //o + .io_output_aw_payload_region (writeOnly_io_output_aw_payload_region[3:0]), //o + .io_output_aw_payload_len (writeOnly_io_output_aw_payload_len[7:0] ), //o + .io_output_aw_payload_size (writeOnly_io_output_aw_payload_size[2:0] ), //o + .io_output_aw_payload_burst (writeOnly_io_output_aw_payload_burst[1:0] ), //o + .io_output_aw_payload_lock (writeOnly_io_output_aw_payload_lock ), //o + .io_output_aw_payload_cache (writeOnly_io_output_aw_payload_cache[3:0] ), //o + .io_output_aw_payload_qos (writeOnly_io_output_aw_payload_qos[3:0] ), //o + .io_output_aw_payload_prot (writeOnly_io_output_aw_payload_prot[2:0] ), //o + .io_output_w_valid (writeOnly_io_output_w_valid ), //o + .io_output_w_ready (io_output_w_ready ), //i + .io_output_w_payload_data (writeOnly_io_output_w_payload_data[127:0] ), //o + .io_output_w_payload_strb (writeOnly_io_output_w_payload_strb[15:0] ), //o + .io_output_w_payload_last (writeOnly_io_output_w_payload_last ), //o + .io_output_b_valid (io_output_b_valid ), //i + .io_output_b_ready (writeOnly_io_output_b_ready ), //o + .io_output_b_payload_id (io_output_b_payload_id[7:0] ), //i + .io_output_b_payload_resp (io_output_b_payload_resp[1:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign io_input_ar_ready = readOnly_io_input_ar_ready; + assign io_input_r_valid = readOnly_io_input_r_valid; + assign io_input_r_payload_data = readOnly_io_input_r_payload_data; + assign io_input_r_payload_id = readOnly_io_input_r_payload_id; + assign io_input_r_payload_resp = readOnly_io_input_r_payload_resp; + assign io_input_r_payload_last = readOnly_io_input_r_payload_last; + assign io_input_aw_ready = writeOnly_io_input_aw_ready; + assign io_input_w_ready = writeOnly_io_input_w_ready; + assign io_input_b_valid = writeOnly_io_input_b_valid; + assign io_input_b_payload_id = writeOnly_io_input_b_payload_id; + assign io_input_b_payload_resp = writeOnly_io_input_b_payload_resp; + assign io_output_ar_valid = readOnly_io_output_ar_valid; + assign io_output_ar_payload_addr = readOnly_io_output_ar_payload_addr; + assign io_output_ar_payload_id = readOnly_io_output_ar_payload_id; + assign io_output_ar_payload_region = readOnly_io_output_ar_payload_region; + assign io_output_ar_payload_len = readOnly_io_output_ar_payload_len; + assign io_output_ar_payload_size = readOnly_io_output_ar_payload_size; + assign io_output_ar_payload_burst = readOnly_io_output_ar_payload_burst; + assign io_output_ar_payload_lock = readOnly_io_output_ar_payload_lock; + assign io_output_ar_payload_cache = readOnly_io_output_ar_payload_cache; + assign io_output_ar_payload_qos = readOnly_io_output_ar_payload_qos; + assign io_output_ar_payload_prot = readOnly_io_output_ar_payload_prot; + assign io_output_r_ready = readOnly_io_output_r_ready; + assign io_output_aw_valid = writeOnly_io_output_aw_valid; + assign io_output_aw_payload_addr = writeOnly_io_output_aw_payload_addr; + assign io_output_aw_payload_id = writeOnly_io_output_aw_payload_id; + assign io_output_aw_payload_region = writeOnly_io_output_aw_payload_region; + assign io_output_aw_payload_len = writeOnly_io_output_aw_payload_len; + assign io_output_aw_payload_size = writeOnly_io_output_aw_payload_size; + assign io_output_aw_payload_burst = writeOnly_io_output_aw_payload_burst; + assign io_output_aw_payload_lock = writeOnly_io_output_aw_payload_lock; + assign io_output_aw_payload_cache = writeOnly_io_output_aw_payload_cache; + assign io_output_aw_payload_qos = writeOnly_io_output_aw_payload_qos; + assign io_output_aw_payload_prot = writeOnly_io_output_aw_payload_prot; + assign io_output_w_valid = writeOnly_io_output_w_valid; + assign io_output_w_payload_data = writeOnly_io_output_w_payload_data; + assign io_output_w_payload_strb = writeOnly_io_output_w_payload_strb; + assign io_output_w_payload_last = writeOnly_io_output_w_payload_last; + assign io_output_b_ready = writeOnly_io_output_b_ready; + +endmodule + +module Asic32To128UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_aw_valid, + output reg io_input_aw_ready, + input [31:0] io_input_aw_payload_addr, + input [7:0] io_input_aw_payload_id, + input [3:0] io_input_aw_payload_region, + input [7:0] io_input_aw_payload_len, + input [2:0] io_input_aw_payload_size, + input [1:0] io_input_aw_payload_burst, + input [0:0] io_input_aw_payload_lock, + input [3:0] io_input_aw_payload_cache, + input [3:0] io_input_aw_payload_qos, + input [2:0] io_input_aw_payload_prot, + input io_input_w_valid, + output io_input_w_ready, + input [31:0] io_input_w_payload_data, + input [3:0] io_input_w_payload_strb, + input io_input_w_payload_last, + output io_input_b_valid, + input io_input_b_ready, + output [7:0] io_input_b_payload_id, + output [1:0] io_input_b_payload_resp, + output io_output_aw_valid, + input io_output_aw_ready, + output [31:0] io_output_aw_payload_addr, + output [7:0] io_output_aw_payload_id, + output [3:0] io_output_aw_payload_region, + output reg [7:0] io_output_aw_payload_len, + output reg [2:0] io_output_aw_payload_size, + output [1:0] io_output_aw_payload_burst, + output [0:0] io_output_aw_payload_lock, + output [3:0] io_output_aw_payload_cache, + output [3:0] io_output_aw_payload_qos, + output [2:0] io_output_aw_payload_prot, + output io_output_w_valid, + input io_output_w_ready, + output [127:0] io_output_w_payload_data, + output [15:0] io_output_w_payload_strb, + output io_output_w_payload_last, + input io_output_b_valid, + output io_output_b_ready, + input [7:0] io_output_b_payload_id, + input [1:0] io_output_b_payload_resp, + input clk, + input reset +); + + wire [14:0] _zz_cmdLogic_byteCount; + wire [10:0] _zz_cmdLogic_incrLen; + wire [10:0] _zz_cmdLogic_incrLen_1; + wire [3:0] _zz_cmdLogic_incrLen_2; + wire [4:0] _zz_dataLogic_byteCounterNext; + wire [7:0] _zz_dataLogic_byteCounterNext_1; + reg [15:0] _zz_dataLogic_byteActivity; + wire [1:0] _zz_dataLogic_byteActivity_1; + wire cmdLogic_outputFork_valid; + wire cmdLogic_outputFork_ready; + wire [31:0] cmdLogic_outputFork_payload_addr; + wire [7:0] cmdLogic_outputFork_payload_id; + wire [3:0] cmdLogic_outputFork_payload_region; + wire [7:0] cmdLogic_outputFork_payload_len; + wire [2:0] cmdLogic_outputFork_payload_size; + wire [1:0] cmdLogic_outputFork_payload_burst; + wire [0:0] cmdLogic_outputFork_payload_lock; + wire [3:0] cmdLogic_outputFork_payload_cache; + wire [3:0] cmdLogic_outputFork_payload_qos; + wire [2:0] cmdLogic_outputFork_payload_prot; + wire cmdLogic_dataFork_valid; + wire cmdLogic_dataFork_ready; + wire [31:0] cmdLogic_dataFork_payload_addr; + wire [7:0] cmdLogic_dataFork_payload_id; + wire [3:0] cmdLogic_dataFork_payload_region; + wire [7:0] cmdLogic_dataFork_payload_len; + wire [2:0] cmdLogic_dataFork_payload_size; + wire [1:0] cmdLogic_dataFork_payload_burst; + wire [0:0] cmdLogic_dataFork_payload_lock; + wire [3:0] cmdLogic_dataFork_payload_cache; + wire [3:0] cmdLogic_dataFork_payload_qos; + wire [2:0] cmdLogic_dataFork_payload_prot; + reg io_input_aw_fork2_logic_linkEnable_0; + reg io_input_aw_fork2_logic_linkEnable_1; + wire when_Stream_l993; + wire when_Stream_l993_1; + wire cmdLogic_outputFork_fire; + wire cmdLogic_dataFork_fire; + wire [9:0] cmdLogic_byteCount; + wire [6:0] cmdLogic_incrLen; + wire when_Axi4Upsizer_l21; + wire when_Axi4Upsizer_l24; + reg [3:0] dataLogic_byteCounter; + reg [2:0] dataLogic_size; + reg dataLogic_outputValid; + reg dataLogic_outputLast; + reg dataLogic_busy; + reg dataLogic_incrementByteCounter; + reg dataLogic_alwaysFire; + wire [4:0] dataLogic_byteCounterNext; + reg [127:0] dataLogic_dataBuffer; + reg [15:0] dataLogic_maskBuffer; + wire [15:0] dataLogic_byteActivity; + wire io_output_w_fire; + wire io_output_w_isStall; + wire io_input_w_fire; + wire when_Axi4Upsizer_l59; + wire when_Axi4Upsizer_l59_1; + wire when_Axi4Upsizer_l59_2; + wire when_Axi4Upsizer_l59_3; + wire when_Axi4Upsizer_l59_4; + wire when_Axi4Upsizer_l59_5; + wire when_Axi4Upsizer_l59_6; + wire when_Axi4Upsizer_l59_7; + wire when_Axi4Upsizer_l59_8; + wire when_Axi4Upsizer_l59_9; + wire when_Axi4Upsizer_l59_10; + wire when_Axi4Upsizer_l59_11; + wire when_Axi4Upsizer_l59_12; + wire when_Axi4Upsizer_l59_13; + wire when_Axi4Upsizer_l59_14; + wire when_Axi4Upsizer_l59_15; + wire cmdLogic_dataFork_fire_1; + wire when_Axi4Upsizer_l68; + wire when_Axi4Upsizer_l68_1; + wire when_Axi4Upsizer_l68_2; + wire when_Axi4Upsizer_l68_3; + + assign _zz_cmdLogic_byteCount = ({7'd0,io_input_aw_payload_len} <<< io_input_aw_payload_size); + assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); + assign _zz_cmdLogic_incrLen_2 = io_input_aw_payload_addr[3 : 0]; + assign _zz_cmdLogic_incrLen_1 = {7'd0, _zz_cmdLogic_incrLen_2}; + assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); + assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[4:0]; + assign _zz_dataLogic_byteActivity_1 = dataLogic_size[1:0]; + always @(*) begin + case(_zz_dataLogic_byteActivity_1) + 2'b00 : _zz_dataLogic_byteActivity = 16'h0001; + 2'b01 : _zz_dataLogic_byteActivity = 16'h0003; + 2'b10 : _zz_dataLogic_byteActivity = 16'h000f; + default : _zz_dataLogic_byteActivity = 16'h00ff; + endcase + end + + always @(*) begin + io_input_aw_ready = 1'b1; + if(when_Stream_l993) begin + io_input_aw_ready = 1'b0; + end + if(when_Stream_l993_1) begin + io_input_aw_ready = 1'b0; + end + end + + assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_aw_fork2_logic_linkEnable_0); + assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_aw_fork2_logic_linkEnable_1); + assign cmdLogic_outputFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_0); + assign cmdLogic_outputFork_payload_addr = io_input_aw_payload_addr; + assign cmdLogic_outputFork_payload_id = io_input_aw_payload_id; + assign cmdLogic_outputFork_payload_region = io_input_aw_payload_region; + assign cmdLogic_outputFork_payload_len = io_input_aw_payload_len; + assign cmdLogic_outputFork_payload_size = io_input_aw_payload_size; + assign cmdLogic_outputFork_payload_burst = io_input_aw_payload_burst; + assign cmdLogic_outputFork_payload_lock = io_input_aw_payload_lock; + assign cmdLogic_outputFork_payload_cache = io_input_aw_payload_cache; + assign cmdLogic_outputFork_payload_qos = io_input_aw_payload_qos; + assign cmdLogic_outputFork_payload_prot = io_input_aw_payload_prot; + assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); + assign cmdLogic_dataFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_1); + assign cmdLogic_dataFork_payload_addr = io_input_aw_payload_addr; + assign cmdLogic_dataFork_payload_id = io_input_aw_payload_id; + assign cmdLogic_dataFork_payload_region = io_input_aw_payload_region; + assign cmdLogic_dataFork_payload_len = io_input_aw_payload_len; + assign cmdLogic_dataFork_payload_size = io_input_aw_payload_size; + assign cmdLogic_dataFork_payload_burst = io_input_aw_payload_burst; + assign cmdLogic_dataFork_payload_lock = io_input_aw_payload_lock; + assign cmdLogic_dataFork_payload_cache = io_input_aw_payload_cache; + assign cmdLogic_dataFork_payload_qos = io_input_aw_payload_qos; + assign cmdLogic_dataFork_payload_prot = io_input_aw_payload_prot; + assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign io_output_aw_valid = cmdLogic_outputFork_valid; + assign cmdLogic_outputFork_ready = io_output_aw_ready; + assign io_output_aw_payload_addr = cmdLogic_outputFork_payload_addr; + assign io_output_aw_payload_id = cmdLogic_outputFork_payload_id; + assign io_output_aw_payload_region = cmdLogic_outputFork_payload_region; + always @(*) begin + io_output_aw_payload_len = cmdLogic_outputFork_payload_len; + if(when_Axi4Upsizer_l21) begin + io_output_aw_payload_len = {1'd0, cmdLogic_incrLen}; + end + end + + always @(*) begin + io_output_aw_payload_size = cmdLogic_outputFork_payload_size; + if(when_Axi4Upsizer_l21) begin + io_output_aw_payload_size = 3'b100; + if(when_Axi4Upsizer_l24) begin + io_output_aw_payload_size = io_input_aw_payload_size; + end + end + end + + assign io_output_aw_payload_burst = cmdLogic_outputFork_payload_burst; + assign io_output_aw_payload_lock = cmdLogic_outputFork_payload_lock; + assign io_output_aw_payload_cache = cmdLogic_outputFork_payload_cache; + assign io_output_aw_payload_qos = cmdLogic_outputFork_payload_qos; + assign io_output_aw_payload_prot = cmdLogic_outputFork_payload_prot; + assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; + assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 4]; + assign when_Axi4Upsizer_l21 = (io_output_aw_payload_burst == 2'b01); + assign when_Axi4Upsizer_l24 = (io_input_aw_payload_len == 8'h00); + assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); + assign dataLogic_byteActivity = (_zz_dataLogic_byteActivity <<< dataLogic_byteCounter); + assign io_output_w_fire = (io_output_w_valid && io_output_w_ready); + assign io_output_w_valid = dataLogic_outputValid; + assign io_output_w_isStall = (io_output_w_valid && (! io_output_w_ready)); + assign io_input_w_ready = (dataLogic_busy && (! io_output_w_isStall)); + assign io_output_w_payload_data = dataLogic_dataBuffer; + assign io_output_w_payload_strb = dataLogic_maskBuffer; + assign io_output_w_payload_last = dataLogic_outputLast; + assign io_input_w_fire = (io_input_w_valid && io_input_w_ready); + assign when_Axi4Upsizer_l59 = dataLogic_byteActivity[0]; + assign when_Axi4Upsizer_l59_1 = dataLogic_byteActivity[1]; + assign when_Axi4Upsizer_l59_2 = dataLogic_byteActivity[2]; + assign when_Axi4Upsizer_l59_3 = dataLogic_byteActivity[3]; + assign when_Axi4Upsizer_l59_4 = dataLogic_byteActivity[4]; + assign when_Axi4Upsizer_l59_5 = dataLogic_byteActivity[5]; + assign when_Axi4Upsizer_l59_6 = dataLogic_byteActivity[6]; + assign when_Axi4Upsizer_l59_7 = dataLogic_byteActivity[7]; + assign when_Axi4Upsizer_l59_8 = dataLogic_byteActivity[8]; + assign when_Axi4Upsizer_l59_9 = dataLogic_byteActivity[9]; + assign when_Axi4Upsizer_l59_10 = dataLogic_byteActivity[10]; + assign when_Axi4Upsizer_l59_11 = dataLogic_byteActivity[11]; + assign when_Axi4Upsizer_l59_12 = dataLogic_byteActivity[12]; + assign when_Axi4Upsizer_l59_13 = dataLogic_byteActivity[13]; + assign when_Axi4Upsizer_l59_14 = dataLogic_byteActivity[14]; + assign when_Axi4Upsizer_l59_15 = dataLogic_byteActivity[15]; + assign cmdLogic_dataFork_fire_1 = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign when_Axi4Upsizer_l68 = (3'b000 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_1 = (3'b001 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_2 = (3'b010 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_3 = (3'b011 < cmdLogic_dataFork_payload_size); + assign cmdLogic_dataFork_ready = (! dataLogic_busy); + assign io_input_b_valid = io_output_b_valid; + assign io_output_b_ready = io_input_b_ready; + assign io_input_b_payload_id = io_output_b_payload_id; + assign io_input_b_payload_resp = io_output_b_payload_resp; + always @(posedge clk or posedge reset) begin + if(reset) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; + io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; + dataLogic_outputValid <= 1'b0; + dataLogic_busy <= 1'b0; + dataLogic_maskBuffer <= 16'h0000; + end else begin + if(cmdLogic_outputFork_fire) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdLogic_dataFork_fire) begin + io_input_aw_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_aw_ready) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; + io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; + end + if(io_output_w_ready) begin + dataLogic_outputValid <= 1'b0; + end + if(io_output_w_fire) begin + dataLogic_maskBuffer <= 16'h0000; + end + if(io_input_w_fire) begin + dataLogic_outputValid <= ((dataLogic_byteCounterNext[4] || io_input_w_payload_last) || dataLogic_alwaysFire); + if(io_input_w_payload_last) begin + dataLogic_busy <= 1'b0; + end + if(when_Axi4Upsizer_l59) begin + dataLogic_maskBuffer[0] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_1) begin + dataLogic_maskBuffer[1] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_2) begin + dataLogic_maskBuffer[2] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_3) begin + dataLogic_maskBuffer[3] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_4) begin + dataLogic_maskBuffer[4] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_5) begin + dataLogic_maskBuffer[5] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_6) begin + dataLogic_maskBuffer[6] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_7) begin + dataLogic_maskBuffer[7] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_8) begin + dataLogic_maskBuffer[8] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_9) begin + dataLogic_maskBuffer[9] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_10) begin + dataLogic_maskBuffer[10] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_11) begin + dataLogic_maskBuffer[11] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_12) begin + dataLogic_maskBuffer[12] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_13) begin + dataLogic_maskBuffer[13] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_14) begin + dataLogic_maskBuffer[14] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_15) begin + dataLogic_maskBuffer[15] <= io_input_w_payload_strb[3]; + end + end + if(cmdLogic_dataFork_fire_1) begin + dataLogic_busy <= 1'b1; + end + end + end + + always @(posedge clk) begin + if(io_input_w_fire) begin + if(dataLogic_incrementByteCounter) begin + dataLogic_byteCounter <= dataLogic_byteCounterNext[3:0]; + end + dataLogic_outputLast <= io_input_w_payload_last; + if(when_Axi4Upsizer_l59) begin + dataLogic_dataBuffer[7 : 0] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_1) begin + dataLogic_dataBuffer[15 : 8] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_2) begin + dataLogic_dataBuffer[23 : 16] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_3) begin + dataLogic_dataBuffer[31 : 24] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_4) begin + dataLogic_dataBuffer[39 : 32] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_5) begin + dataLogic_dataBuffer[47 : 40] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_6) begin + dataLogic_dataBuffer[55 : 48] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_7) begin + dataLogic_dataBuffer[63 : 56] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_8) begin + dataLogic_dataBuffer[71 : 64] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_9) begin + dataLogic_dataBuffer[79 : 72] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_10) begin + dataLogic_dataBuffer[87 : 80] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_11) begin + dataLogic_dataBuffer[95 : 88] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_12) begin + dataLogic_dataBuffer[103 : 96] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_13) begin + dataLogic_dataBuffer[111 : 104] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_14) begin + dataLogic_dataBuffer[119 : 112] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_15) begin + dataLogic_dataBuffer[127 : 120] <= io_input_w_payload_data[31 : 24]; + end + end + if(cmdLogic_dataFork_fire_1) begin + dataLogic_byteCounter <= cmdLogic_dataFork_payload_addr[3:0]; + if(when_Axi4Upsizer_l68) begin + dataLogic_byteCounter[0] <= 1'b0; + end + if(when_Axi4Upsizer_l68_1) begin + dataLogic_byteCounter[1] <= 1'b0; + end + if(when_Axi4Upsizer_l68_2) begin + dataLogic_byteCounter[2] <= 1'b0; + end + if(when_Axi4Upsizer_l68_3) begin + dataLogic_byteCounter[3] <= 1'b0; + end + dataLogic_size <= cmdLogic_dataFork_payload_size; + dataLogic_alwaysFire <= (! (cmdLogic_dataFork_payload_burst == 2'b01)); + dataLogic_incrementByteCounter <= (! (cmdLogic_dataFork_payload_burst == 2'b00)); + end + end + + +endmodule + +module Asic32To128UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_ar_valid, + output reg io_input_ar_ready, + input [31:0] io_input_ar_payload_addr, + input [7:0] io_input_ar_payload_id, + input [3:0] io_input_ar_payload_region, + input [7:0] io_input_ar_payload_len, + input [2:0] io_input_ar_payload_size, + input [1:0] io_input_ar_payload_burst, + input [0:0] io_input_ar_payload_lock, + input [3:0] io_input_ar_payload_cache, + input [3:0] io_input_ar_payload_qos, + input [2:0] io_input_ar_payload_prot, + output io_input_r_valid, + input io_input_r_ready, + output [31:0] io_input_r_payload_data, + output [7:0] io_input_r_payload_id, + output [1:0] io_input_r_payload_resp, + output io_input_r_payload_last, + output io_output_ar_valid, + input io_output_ar_ready, + output [31:0] io_output_ar_payload_addr, + output [7:0] io_output_ar_payload_id, + output [3:0] io_output_ar_payload_region, + output [7:0] io_output_ar_payload_len, + output reg [2:0] io_output_ar_payload_size, + output [1:0] io_output_ar_payload_burst, + output [0:0] io_output_ar_payload_lock, + output [3:0] io_output_ar_payload_cache, + output [3:0] io_output_ar_payload_qos, + output [2:0] io_output_ar_payload_prot, + input io_output_r_valid, + output io_output_r_ready, + input [127:0] io_output_r_payload_data, + input [7:0] io_output_r_payload_id, + input [1:0] io_output_r_payload_resp, + input io_output_r_payload_last, + input clk, + input reset +); + + wire dataLogic_cmdPush_fifo_io_pop_ready; + wire dataLogic_cmdPush_fifo_io_push_ready; + wire dataLogic_cmdPush_fifo_io_pop_valid; + wire [3:0] dataLogic_cmdPush_fifo_io_pop_payload_startAt; + wire [3:0] dataLogic_cmdPush_fifo_io_pop_payload_endAt; + wire [2:0] dataLogic_cmdPush_fifo_io_pop_payload_size; + wire [7:0] dataLogic_cmdPush_fifo_io_pop_payload_id; + wire [4:0] dataLogic_cmdPush_fifo_io_occupancy; + wire [4:0] dataLogic_cmdPush_fifo_io_availability; + wire [14:0] _zz_cmdLogic_byteCount; + wire [10:0] _zz_cmdLogic_incrLen; + wire [10:0] _zz_cmdLogic_incrLen_1; + wire [3:0] _zz_cmdLogic_incrLen_2; + wire [31:0] _zz_dataLogic_cmdPush_payload_endAt; + wire [31:0] _zz_dataLogic_cmdPush_payload_endAt_1; + wire [14:0] _zz_dataLogic_cmdPush_payload_endAt_2; + wire [4:0] _zz_dataLogic_byteCounterNext; + wire [7:0] _zz_dataLogic_byteCounterNext_1; + reg [31:0] _zz_io_input_r_payload_data; + wire [1:0] _zz_io_input_r_payload_data_1; + wire cmdLogic_outputFork_valid; + wire cmdLogic_outputFork_ready; + wire [31:0] cmdLogic_outputFork_payload_addr; + wire [7:0] cmdLogic_outputFork_payload_id; + wire [3:0] cmdLogic_outputFork_payload_region; + wire [7:0] cmdLogic_outputFork_payload_len; + wire [2:0] cmdLogic_outputFork_payload_size; + wire [1:0] cmdLogic_outputFork_payload_burst; + wire [0:0] cmdLogic_outputFork_payload_lock; + wire [3:0] cmdLogic_outputFork_payload_cache; + wire [3:0] cmdLogic_outputFork_payload_qos; + wire [2:0] cmdLogic_outputFork_payload_prot; + wire cmdLogic_dataFork_valid; + wire cmdLogic_dataFork_ready; + wire [31:0] cmdLogic_dataFork_payload_addr; + wire [7:0] cmdLogic_dataFork_payload_id; + wire [3:0] cmdLogic_dataFork_payload_region; + wire [7:0] cmdLogic_dataFork_payload_len; + wire [2:0] cmdLogic_dataFork_payload_size; + wire [1:0] cmdLogic_dataFork_payload_burst; + wire [0:0] cmdLogic_dataFork_payload_lock; + wire [3:0] cmdLogic_dataFork_payload_cache; + wire [3:0] cmdLogic_dataFork_payload_qos; + wire [2:0] cmdLogic_dataFork_payload_prot; + reg io_input_ar_fork2_logic_linkEnable_0; + reg io_input_ar_fork2_logic_linkEnable_1; + wire when_Stream_l993; + wire when_Stream_l993_1; + wire cmdLogic_outputFork_fire; + wire cmdLogic_dataFork_fire; + wire [9:0] cmdLogic_byteCount; + wire [6:0] cmdLogic_incrLen; + wire when_Axi4Upsizer_l108; + wire dataLogic_cmdPush_valid; + wire dataLogic_cmdPush_ready; + wire [3:0] dataLogic_cmdPush_payload_startAt; + wire [3:0] dataLogic_cmdPush_payload_endAt; + wire [2:0] dataLogic_cmdPush_payload_size; + wire [7:0] dataLogic_cmdPush_payload_id; + reg [2:0] dataLogic_size; + reg dataLogic_busy; + reg [7:0] dataLogic_id; + reg [3:0] dataLogic_byteCounter; + reg [3:0] dataLogic_byteCounterLast; + wire [4:0] dataLogic_byteCounterNext; + wire readOnly_dataLogic_cmdPush_fifo_io_pop_fire; + wire io_input_r_fire; + + assign _zz_cmdLogic_byteCount = ({7'd0,io_input_ar_payload_len} <<< io_input_ar_payload_size); + assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); + assign _zz_cmdLogic_incrLen_2 = io_input_ar_payload_addr[3 : 0]; + assign _zz_cmdLogic_incrLen_1 = {7'd0, _zz_cmdLogic_incrLen_2}; + assign _zz_dataLogic_cmdPush_payload_endAt = (cmdLogic_dataFork_payload_addr + _zz_dataLogic_cmdPush_payload_endAt_1); + assign _zz_dataLogic_cmdPush_payload_endAt_2 = ({7'd0,cmdLogic_dataFork_payload_len} <<< cmdLogic_dataFork_payload_size); + assign _zz_dataLogic_cmdPush_payload_endAt_1 = {17'd0, _zz_dataLogic_cmdPush_payload_endAt_2}; + assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); + assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[4:0]; + assign _zz_io_input_r_payload_data_1 = (dataLogic_byteCounter >>> 2'd2); + Asic32To128UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 dataLogic_cmdPush_fifo ( + .io_push_valid (dataLogic_cmdPush_valid ), //i + .io_push_ready (dataLogic_cmdPush_fifo_io_push_ready ), //o + .io_push_payload_startAt (dataLogic_cmdPush_payload_startAt[3:0] ), //i + .io_push_payload_endAt (dataLogic_cmdPush_payload_endAt[3:0] ), //i + .io_push_payload_size (dataLogic_cmdPush_payload_size[2:0] ), //i + .io_push_payload_id (dataLogic_cmdPush_payload_id[7:0] ), //i + .io_pop_valid (dataLogic_cmdPush_fifo_io_pop_valid ), //o + .io_pop_ready (dataLogic_cmdPush_fifo_io_pop_ready ), //i + .io_pop_payload_startAt (dataLogic_cmdPush_fifo_io_pop_payload_startAt[3:0]), //o + .io_pop_payload_endAt (dataLogic_cmdPush_fifo_io_pop_payload_endAt[3:0] ), //o + .io_pop_payload_size (dataLogic_cmdPush_fifo_io_pop_payload_size[2:0] ), //o + .io_pop_payload_id (dataLogic_cmdPush_fifo_io_pop_payload_id[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (dataLogic_cmdPush_fifo_io_occupancy[4:0] ), //o + .io_availability (dataLogic_cmdPush_fifo_io_availability[4:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_io_input_r_payload_data_1) + 2'b00 : _zz_io_input_r_payload_data = io_output_r_payload_data[31 : 0]; + 2'b01 : _zz_io_input_r_payload_data = io_output_r_payload_data[63 : 32]; + 2'b10 : _zz_io_input_r_payload_data = io_output_r_payload_data[95 : 64]; + default : _zz_io_input_r_payload_data = io_output_r_payload_data[127 : 96]; + endcase + end + + always @(*) begin + io_input_ar_ready = 1'b1; + if(when_Stream_l993) begin + io_input_ar_ready = 1'b0; + end + if(when_Stream_l993_1) begin + io_input_ar_ready = 1'b0; + end + end + + assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_ar_fork2_logic_linkEnable_0); + assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_ar_fork2_logic_linkEnable_1); + assign cmdLogic_outputFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_0); + assign cmdLogic_outputFork_payload_addr = io_input_ar_payload_addr; + assign cmdLogic_outputFork_payload_id = io_input_ar_payload_id; + assign cmdLogic_outputFork_payload_region = io_input_ar_payload_region; + assign cmdLogic_outputFork_payload_len = io_input_ar_payload_len; + assign cmdLogic_outputFork_payload_size = io_input_ar_payload_size; + assign cmdLogic_outputFork_payload_burst = io_input_ar_payload_burst; + assign cmdLogic_outputFork_payload_lock = io_input_ar_payload_lock; + assign cmdLogic_outputFork_payload_cache = io_input_ar_payload_cache; + assign cmdLogic_outputFork_payload_qos = io_input_ar_payload_qos; + assign cmdLogic_outputFork_payload_prot = io_input_ar_payload_prot; + assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); + assign cmdLogic_dataFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_1); + assign cmdLogic_dataFork_payload_addr = io_input_ar_payload_addr; + assign cmdLogic_dataFork_payload_id = io_input_ar_payload_id; + assign cmdLogic_dataFork_payload_region = io_input_ar_payload_region; + assign cmdLogic_dataFork_payload_len = io_input_ar_payload_len; + assign cmdLogic_dataFork_payload_size = io_input_ar_payload_size; + assign cmdLogic_dataFork_payload_burst = io_input_ar_payload_burst; + assign cmdLogic_dataFork_payload_lock = io_input_ar_payload_lock; + assign cmdLogic_dataFork_payload_cache = io_input_ar_payload_cache; + assign cmdLogic_dataFork_payload_qos = io_input_ar_payload_qos; + assign cmdLogic_dataFork_payload_prot = io_input_ar_payload_prot; + assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign io_output_ar_valid = cmdLogic_outputFork_valid; + assign cmdLogic_outputFork_ready = io_output_ar_ready; + assign io_output_ar_payload_addr = cmdLogic_outputFork_payload_addr; + assign io_output_ar_payload_region = cmdLogic_outputFork_payload_region; + assign io_output_ar_payload_burst = cmdLogic_outputFork_payload_burst; + assign io_output_ar_payload_lock = cmdLogic_outputFork_payload_lock; + assign io_output_ar_payload_cache = cmdLogic_outputFork_payload_cache; + assign io_output_ar_payload_qos = cmdLogic_outputFork_payload_qos; + assign io_output_ar_payload_prot = cmdLogic_outputFork_payload_prot; + assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; + assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 4]; + always @(*) begin + io_output_ar_payload_size = 3'b100; + if(when_Axi4Upsizer_l108) begin + io_output_ar_payload_size = io_input_ar_payload_size; + end + end + + assign io_output_ar_payload_len = {1'd0, cmdLogic_incrLen}; + assign io_output_ar_payload_id = 8'h00; + assign when_Axi4Upsizer_l108 = (io_input_ar_payload_len == 8'h00); + assign dataLogic_cmdPush_valid = cmdLogic_dataFork_valid; + assign cmdLogic_dataFork_ready = dataLogic_cmdPush_ready; + assign dataLogic_cmdPush_payload_startAt = cmdLogic_dataFork_payload_addr[3:0]; + assign dataLogic_cmdPush_payload_endAt = _zz_dataLogic_cmdPush_payload_endAt[3:0]; + assign dataLogic_cmdPush_payload_size = cmdLogic_dataFork_payload_size; + assign dataLogic_cmdPush_payload_id = cmdLogic_dataFork_payload_id; + assign dataLogic_cmdPush_ready = dataLogic_cmdPush_fifo_io_push_ready; + assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); + assign readOnly_dataLogic_cmdPush_fifo_io_pop_fire = (dataLogic_cmdPush_fifo_io_pop_valid && dataLogic_cmdPush_fifo_io_pop_ready); + assign dataLogic_cmdPush_fifo_io_pop_ready = (! dataLogic_busy); + assign io_input_r_fire = (io_input_r_valid && io_input_r_ready); + assign io_input_r_valid = (io_output_r_valid && dataLogic_busy); + assign io_input_r_payload_last = (io_output_r_payload_last && (dataLogic_byteCounter == dataLogic_byteCounterLast)); + assign io_input_r_payload_resp = io_output_r_payload_resp; + assign io_input_r_payload_data = _zz_io_input_r_payload_data; + assign io_input_r_payload_id = dataLogic_id; + assign io_output_r_ready = ((dataLogic_busy && io_input_r_ready) && (io_input_r_payload_last || dataLogic_byteCounterNext[4])); + always @(posedge clk or posedge reset) begin + if(reset) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; + io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; + dataLogic_busy <= 1'b0; + end else begin + if(cmdLogic_outputFork_fire) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdLogic_dataFork_fire) begin + io_input_ar_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_ar_ready) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; + io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; + end + if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin + dataLogic_busy <= 1'b1; + end + if(io_input_r_fire) begin + if(io_input_r_payload_last) begin + dataLogic_busy <= 1'b0; + end + end + end + end + + always @(posedge clk) begin + if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin + dataLogic_byteCounter <= dataLogic_cmdPush_fifo_io_pop_payload_startAt; + dataLogic_byteCounterLast <= dataLogic_cmdPush_fifo_io_pop_payload_endAt; + dataLogic_size <= dataLogic_cmdPush_fifo_io_pop_payload_size; + dataLogic_id <= dataLogic_cmdPush_fifo_io_pop_payload_id; + end + if(io_input_r_fire) begin + dataLogic_byteCounter <= dataLogic_byteCounterNext[3:0]; + end + end + + +endmodule + +module Asic32To128UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_push_valid, + output io_push_ready, + input [3:0] io_push_payload_startAt, + input [3:0] io_push_payload_endAt, + input [2:0] io_push_payload_size, + input [7:0] io_push_payload_id, + output io_pop_valid, + input io_pop_ready, + output [3:0] io_pop_payload_startAt, + output [3:0] io_pop_payload_endAt, + output [2:0] io_pop_payload_size, + output [7:0] io_pop_payload_id, + input io_flush, + output [4:0] io_occupancy, + output [4:0] io_availability, + input clk, + input reset +); + + reg [18:0] _zz_logic_ram_port0; + wire [3:0] _zz_logic_pushPtr_valueNext; + wire [0:0] _zz_logic_pushPtr_valueNext_1; + wire [3:0] _zz_logic_popPtr_valueNext; + wire [0:0] _zz_logic_popPtr_valueNext_1; + wire _zz__zz_logic_ram_port0; + wire _zz__zz_io_pop_payload_startAt; + wire [18:0] _zz__zz_logic_ram_port1; + wire [3:0] _zz_io_availability; + reg _zz_1; + reg logic_pushPtr_willIncrement; + reg logic_pushPtr_willClear; + reg [3:0] logic_pushPtr_valueNext; + reg [3:0] logic_pushPtr_value; + wire logic_pushPtr_willOverflowIfInc; + wire logic_pushPtr_willOverflow; + reg logic_popPtr_willIncrement; + reg logic_popPtr_willClear; + reg [3:0] logic_popPtr_valueNext; + reg [3:0] logic_popPtr_value; + wire logic_popPtr_willOverflowIfInc; + wire logic_popPtr_willOverflow; + wire logic_ptrMatch; + reg logic_risingOccupancy; + wire logic_pushing; + wire logic_popping; + wire logic_empty; + wire logic_full; + reg _zz_io_pop_valid; + wire [18:0] _zz_io_pop_payload_startAt; + wire when_Stream_l1123; + wire [3:0] logic_ptrDif; + reg [18:0] logic_ram [0:15]; + + assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; + assign _zz_logic_pushPtr_valueNext = {3'd0, _zz_logic_pushPtr_valueNext_1}; + assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; + assign _zz_logic_popPtr_valueNext = {3'd0, _zz_logic_popPtr_valueNext_1}; + assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); + assign _zz__zz_io_pop_payload_startAt = 1'b1; + assign _zz__zz_logic_ram_port1 = {io_push_payload_id,{io_push_payload_size,{io_push_payload_endAt,io_push_payload_startAt}}}; + always @(posedge clk) begin + if(_zz__zz_io_pop_payload_startAt) begin + _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_pushPtr_value] <= _zz__zz_logic_ram_port1; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_pushing) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willIncrement = 1'b0; + if(logic_pushing) begin + logic_pushPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willClear = 1'b0; + if(io_flush) begin + logic_pushPtr_willClear = 1'b1; + end + end + + assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 4'b1111); + assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); + always @(*) begin + logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); + if(logic_pushPtr_willClear) begin + logic_pushPtr_valueNext = 4'b0000; + end + end + + always @(*) begin + logic_popPtr_willIncrement = 1'b0; + if(logic_popping) begin + logic_popPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_popPtr_willClear = 1'b0; + if(io_flush) begin + logic_popPtr_willClear = 1'b1; + end + end + + assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 4'b1111); + assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); + always @(*) begin + logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); + if(logic_popPtr_willClear) begin + logic_popPtr_valueNext = 4'b0000; + end + end + + assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); + assign logic_pushing = (io_push_valid && io_push_ready); + assign logic_popping = (io_pop_valid && io_pop_ready); + assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); + assign logic_full = (logic_ptrMatch && logic_risingOccupancy); + assign io_push_ready = (! logic_full); + assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); + assign _zz_io_pop_payload_startAt = _zz_logic_ram_port0; + assign io_pop_payload_startAt = _zz_io_pop_payload_startAt[3 : 0]; + assign io_pop_payload_endAt = _zz_io_pop_payload_startAt[7 : 4]; + assign io_pop_payload_size = _zz_io_pop_payload_startAt[10 : 8]; + assign io_pop_payload_id = _zz_io_pop_payload_startAt[18 : 11]; + assign when_Stream_l1123 = (logic_pushing != logic_popping); + assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); + assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; + assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; + always @(posedge clk or posedge reset) begin + if(reset) begin + logic_pushPtr_value <= 4'b0000; + logic_popPtr_value <= 4'b0000; + logic_risingOccupancy <= 1'b0; + _zz_io_pop_valid <= 1'b0; + end else begin + logic_pushPtr_value <= logic_pushPtr_valueNext; + logic_popPtr_value <= logic_popPtr_valueNext; + _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); + if(when_Stream_l1123) begin + logic_risingOccupancy <= logic_pushing; + end + if(io_flush) begin + logic_risingOccupancy <= 1'b0; + end + end + end + + +endmodule + + +// Generator : SpinalHDL dev git head : 9cdee03b276638ef8e7a948b606bb7acc6e4c8d0 +// Component : Asic32To256UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 +// Git hash : cd16421fb7a4d44431a2445f9a92b82070ab9b8a + +`timescale 1ns/1ps + +module Asic32To256UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_aw_valid, + output io_input_aw_ready, + input [31:0] io_input_aw_payload_addr, + input [7:0] io_input_aw_payload_id, + input [3:0] io_input_aw_payload_region, + input [7:0] io_input_aw_payload_len, + input [2:0] io_input_aw_payload_size, + input [1:0] io_input_aw_payload_burst, + input [0:0] io_input_aw_payload_lock, + input [3:0] io_input_aw_payload_cache, + input [3:0] io_input_aw_payload_qos, + input [2:0] io_input_aw_payload_prot, + input io_input_w_valid, + output io_input_w_ready, + input [31:0] io_input_w_payload_data, + input [3:0] io_input_w_payload_strb, + input io_input_w_payload_last, + output io_input_b_valid, + input io_input_b_ready, + output [7:0] io_input_b_payload_id, + output [1:0] io_input_b_payload_resp, + input io_input_ar_valid, + output io_input_ar_ready, + input [31:0] io_input_ar_payload_addr, + input [7:0] io_input_ar_payload_id, + input [3:0] io_input_ar_payload_region, + input [7:0] io_input_ar_payload_len, + input [2:0] io_input_ar_payload_size, + input [1:0] io_input_ar_payload_burst, + input [0:0] io_input_ar_payload_lock, + input [3:0] io_input_ar_payload_cache, + input [3:0] io_input_ar_payload_qos, + input [2:0] io_input_ar_payload_prot, + output io_input_r_valid, + input io_input_r_ready, + output [31:0] io_input_r_payload_data, + output [7:0] io_input_r_payload_id, + output [1:0] io_input_r_payload_resp, + output io_input_r_payload_last, + output io_output_aw_valid, + input io_output_aw_ready, + output [31:0] io_output_aw_payload_addr, + output [7:0] io_output_aw_payload_id, + output [3:0] io_output_aw_payload_region, + output [7:0] io_output_aw_payload_len, + output [2:0] io_output_aw_payload_size, + output [1:0] io_output_aw_payload_burst, + output [0:0] io_output_aw_payload_lock, + output [3:0] io_output_aw_payload_cache, + output [3:0] io_output_aw_payload_qos, + output [2:0] io_output_aw_payload_prot, + output io_output_w_valid, + input io_output_w_ready, + output [255:0] io_output_w_payload_data, + output [31:0] io_output_w_payload_strb, + output io_output_w_payload_last, + input io_output_b_valid, + output io_output_b_ready, + input [7:0] io_output_b_payload_id, + input [1:0] io_output_b_payload_resp, + output io_output_ar_valid, + input io_output_ar_ready, + output [31:0] io_output_ar_payload_addr, + output [7:0] io_output_ar_payload_id, + output [3:0] io_output_ar_payload_region, + output [7:0] io_output_ar_payload_len, + output [2:0] io_output_ar_payload_size, + output [1:0] io_output_ar_payload_burst, + output [0:0] io_output_ar_payload_lock, + output [3:0] io_output_ar_payload_cache, + output [3:0] io_output_ar_payload_qos, + output [2:0] io_output_ar_payload_prot, + input io_output_r_valid, + output io_output_r_ready, + input [255:0] io_output_r_payload_data, + input [7:0] io_output_r_payload_id, + input [1:0] io_output_r_payload_resp, + input io_output_r_payload_last, + input clk, + input reset +); + + wire readOnly_io_input_ar_ready; + wire readOnly_io_input_r_valid; + wire [31:0] readOnly_io_input_r_payload_data; + wire [7:0] readOnly_io_input_r_payload_id; + wire [1:0] readOnly_io_input_r_payload_resp; + wire readOnly_io_input_r_payload_last; + wire readOnly_io_output_ar_valid; + wire [31:0] readOnly_io_output_ar_payload_addr; + wire [7:0] readOnly_io_output_ar_payload_id; + wire [3:0] readOnly_io_output_ar_payload_region; + wire [7:0] readOnly_io_output_ar_payload_len; + wire [2:0] readOnly_io_output_ar_payload_size; + wire [1:0] readOnly_io_output_ar_payload_burst; + wire [0:0] readOnly_io_output_ar_payload_lock; + wire [3:0] readOnly_io_output_ar_payload_cache; + wire [3:0] readOnly_io_output_ar_payload_qos; + wire [2:0] readOnly_io_output_ar_payload_prot; + wire readOnly_io_output_r_ready; + wire writeOnly_io_input_aw_ready; + wire writeOnly_io_input_w_ready; + wire writeOnly_io_input_b_valid; + wire [7:0] writeOnly_io_input_b_payload_id; + wire [1:0] writeOnly_io_input_b_payload_resp; + wire writeOnly_io_output_aw_valid; + wire [31:0] writeOnly_io_output_aw_payload_addr; + wire [7:0] writeOnly_io_output_aw_payload_id; + wire [3:0] writeOnly_io_output_aw_payload_region; + wire [7:0] writeOnly_io_output_aw_payload_len; + wire [2:0] writeOnly_io_output_aw_payload_size; + wire [1:0] writeOnly_io_output_aw_payload_burst; + wire [0:0] writeOnly_io_output_aw_payload_lock; + wire [3:0] writeOnly_io_output_aw_payload_cache; + wire [3:0] writeOnly_io_output_aw_payload_qos; + wire [2:0] writeOnly_io_output_aw_payload_prot; + wire writeOnly_io_output_w_valid; + wire [255:0] writeOnly_io_output_w_payload_data; + wire [31:0] writeOnly_io_output_w_payload_strb; + wire writeOnly_io_output_w_payload_last; + wire writeOnly_io_output_b_ready; + + Asic32To256UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 readOnly ( + .io_input_ar_valid (io_input_ar_valid ), //i + .io_input_ar_ready (readOnly_io_input_ar_ready ), //o + .io_input_ar_payload_addr (io_input_ar_payload_addr[31:0] ), //i + .io_input_ar_payload_id (io_input_ar_payload_id[7:0] ), //i + .io_input_ar_payload_region (io_input_ar_payload_region[3:0] ), //i + .io_input_ar_payload_len (io_input_ar_payload_len[7:0] ), //i + .io_input_ar_payload_size (io_input_ar_payload_size[2:0] ), //i + .io_input_ar_payload_burst (io_input_ar_payload_burst[1:0] ), //i + .io_input_ar_payload_lock (io_input_ar_payload_lock ), //i + .io_input_ar_payload_cache (io_input_ar_payload_cache[3:0] ), //i + .io_input_ar_payload_qos (io_input_ar_payload_qos[3:0] ), //i + .io_input_ar_payload_prot (io_input_ar_payload_prot[2:0] ), //i + .io_input_r_valid (readOnly_io_input_r_valid ), //o + .io_input_r_ready (io_input_r_ready ), //i + .io_input_r_payload_data (readOnly_io_input_r_payload_data[31:0] ), //o + .io_input_r_payload_id (readOnly_io_input_r_payload_id[7:0] ), //o + .io_input_r_payload_resp (readOnly_io_input_r_payload_resp[1:0] ), //o + .io_input_r_payload_last (readOnly_io_input_r_payload_last ), //o + .io_output_ar_valid (readOnly_io_output_ar_valid ), //o + .io_output_ar_ready (io_output_ar_ready ), //i + .io_output_ar_payload_addr (readOnly_io_output_ar_payload_addr[31:0] ), //o + .io_output_ar_payload_id (readOnly_io_output_ar_payload_id[7:0] ), //o + .io_output_ar_payload_region (readOnly_io_output_ar_payload_region[3:0]), //o + .io_output_ar_payload_len (readOnly_io_output_ar_payload_len[7:0] ), //o + .io_output_ar_payload_size (readOnly_io_output_ar_payload_size[2:0] ), //o + .io_output_ar_payload_burst (readOnly_io_output_ar_payload_burst[1:0] ), //o + .io_output_ar_payload_lock (readOnly_io_output_ar_payload_lock ), //o + .io_output_ar_payload_cache (readOnly_io_output_ar_payload_cache[3:0] ), //o + .io_output_ar_payload_qos (readOnly_io_output_ar_payload_qos[3:0] ), //o + .io_output_ar_payload_prot (readOnly_io_output_ar_payload_prot[2:0] ), //o + .io_output_r_valid (io_output_r_valid ), //i + .io_output_r_ready (readOnly_io_output_r_ready ), //o + .io_output_r_payload_data (io_output_r_payload_data[255:0] ), //i + .io_output_r_payload_id (io_output_r_payload_id[7:0] ), //i + .io_output_r_payload_resp (io_output_r_payload_resp[1:0] ), //i + .io_output_r_payload_last (io_output_r_payload_last ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Asic32To256UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 writeOnly ( + .io_input_aw_valid (io_input_aw_valid ), //i + .io_input_aw_ready (writeOnly_io_input_aw_ready ), //o + .io_input_aw_payload_addr (io_input_aw_payload_addr[31:0] ), //i + .io_input_aw_payload_id (io_input_aw_payload_id[7:0] ), //i + .io_input_aw_payload_region (io_input_aw_payload_region[3:0] ), //i + .io_input_aw_payload_len (io_input_aw_payload_len[7:0] ), //i + .io_input_aw_payload_size (io_input_aw_payload_size[2:0] ), //i + .io_input_aw_payload_burst (io_input_aw_payload_burst[1:0] ), //i + .io_input_aw_payload_lock (io_input_aw_payload_lock ), //i + .io_input_aw_payload_cache (io_input_aw_payload_cache[3:0] ), //i + .io_input_aw_payload_qos (io_input_aw_payload_qos[3:0] ), //i + .io_input_aw_payload_prot (io_input_aw_payload_prot[2:0] ), //i + .io_input_w_valid (io_input_w_valid ), //i + .io_input_w_ready (writeOnly_io_input_w_ready ), //o + .io_input_w_payload_data (io_input_w_payload_data[31:0] ), //i + .io_input_w_payload_strb (io_input_w_payload_strb[3:0] ), //i + .io_input_w_payload_last (io_input_w_payload_last ), //i + .io_input_b_valid (writeOnly_io_input_b_valid ), //o + .io_input_b_ready (io_input_b_ready ), //i + .io_input_b_payload_id (writeOnly_io_input_b_payload_id[7:0] ), //o + .io_input_b_payload_resp (writeOnly_io_input_b_payload_resp[1:0] ), //o + .io_output_aw_valid (writeOnly_io_output_aw_valid ), //o + .io_output_aw_ready (io_output_aw_ready ), //i + .io_output_aw_payload_addr (writeOnly_io_output_aw_payload_addr[31:0] ), //o + .io_output_aw_payload_id (writeOnly_io_output_aw_payload_id[7:0] ), //o + .io_output_aw_payload_region (writeOnly_io_output_aw_payload_region[3:0]), //o + .io_output_aw_payload_len (writeOnly_io_output_aw_payload_len[7:0] ), //o + .io_output_aw_payload_size (writeOnly_io_output_aw_payload_size[2:0] ), //o + .io_output_aw_payload_burst (writeOnly_io_output_aw_payload_burst[1:0] ), //o + .io_output_aw_payload_lock (writeOnly_io_output_aw_payload_lock ), //o + .io_output_aw_payload_cache (writeOnly_io_output_aw_payload_cache[3:0] ), //o + .io_output_aw_payload_qos (writeOnly_io_output_aw_payload_qos[3:0] ), //o + .io_output_aw_payload_prot (writeOnly_io_output_aw_payload_prot[2:0] ), //o + .io_output_w_valid (writeOnly_io_output_w_valid ), //o + .io_output_w_ready (io_output_w_ready ), //i + .io_output_w_payload_data (writeOnly_io_output_w_payload_data[255:0] ), //o + .io_output_w_payload_strb (writeOnly_io_output_w_payload_strb[31:0] ), //o + .io_output_w_payload_last (writeOnly_io_output_w_payload_last ), //o + .io_output_b_valid (io_output_b_valid ), //i + .io_output_b_ready (writeOnly_io_output_b_ready ), //o + .io_output_b_payload_id (io_output_b_payload_id[7:0] ), //i + .io_output_b_payload_resp (io_output_b_payload_resp[1:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign io_input_ar_ready = readOnly_io_input_ar_ready; + assign io_input_r_valid = readOnly_io_input_r_valid; + assign io_input_r_payload_data = readOnly_io_input_r_payload_data; + assign io_input_r_payload_id = readOnly_io_input_r_payload_id; + assign io_input_r_payload_resp = readOnly_io_input_r_payload_resp; + assign io_input_r_payload_last = readOnly_io_input_r_payload_last; + assign io_input_aw_ready = writeOnly_io_input_aw_ready; + assign io_input_w_ready = writeOnly_io_input_w_ready; + assign io_input_b_valid = writeOnly_io_input_b_valid; + assign io_input_b_payload_id = writeOnly_io_input_b_payload_id; + assign io_input_b_payload_resp = writeOnly_io_input_b_payload_resp; + assign io_output_ar_valid = readOnly_io_output_ar_valid; + assign io_output_ar_payload_addr = readOnly_io_output_ar_payload_addr; + assign io_output_ar_payload_id = readOnly_io_output_ar_payload_id; + assign io_output_ar_payload_region = readOnly_io_output_ar_payload_region; + assign io_output_ar_payload_len = readOnly_io_output_ar_payload_len; + assign io_output_ar_payload_size = readOnly_io_output_ar_payload_size; + assign io_output_ar_payload_burst = readOnly_io_output_ar_payload_burst; + assign io_output_ar_payload_lock = readOnly_io_output_ar_payload_lock; + assign io_output_ar_payload_cache = readOnly_io_output_ar_payload_cache; + assign io_output_ar_payload_qos = readOnly_io_output_ar_payload_qos; + assign io_output_ar_payload_prot = readOnly_io_output_ar_payload_prot; + assign io_output_r_ready = readOnly_io_output_r_ready; + assign io_output_aw_valid = writeOnly_io_output_aw_valid; + assign io_output_aw_payload_addr = writeOnly_io_output_aw_payload_addr; + assign io_output_aw_payload_id = writeOnly_io_output_aw_payload_id; + assign io_output_aw_payload_region = writeOnly_io_output_aw_payload_region; + assign io_output_aw_payload_len = writeOnly_io_output_aw_payload_len; + assign io_output_aw_payload_size = writeOnly_io_output_aw_payload_size; + assign io_output_aw_payload_burst = writeOnly_io_output_aw_payload_burst; + assign io_output_aw_payload_lock = writeOnly_io_output_aw_payload_lock; + assign io_output_aw_payload_cache = writeOnly_io_output_aw_payload_cache; + assign io_output_aw_payload_qos = writeOnly_io_output_aw_payload_qos; + assign io_output_aw_payload_prot = writeOnly_io_output_aw_payload_prot; + assign io_output_w_valid = writeOnly_io_output_w_valid; + assign io_output_w_payload_data = writeOnly_io_output_w_payload_data; + assign io_output_w_payload_strb = writeOnly_io_output_w_payload_strb; + assign io_output_w_payload_last = writeOnly_io_output_w_payload_last; + assign io_output_b_ready = writeOnly_io_output_b_ready; + +endmodule + +module Asic32To256UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_aw_valid, + output reg io_input_aw_ready, + input [31:0] io_input_aw_payload_addr, + input [7:0] io_input_aw_payload_id, + input [3:0] io_input_aw_payload_region, + input [7:0] io_input_aw_payload_len, + input [2:0] io_input_aw_payload_size, + input [1:0] io_input_aw_payload_burst, + input [0:0] io_input_aw_payload_lock, + input [3:0] io_input_aw_payload_cache, + input [3:0] io_input_aw_payload_qos, + input [2:0] io_input_aw_payload_prot, + input io_input_w_valid, + output io_input_w_ready, + input [31:0] io_input_w_payload_data, + input [3:0] io_input_w_payload_strb, + input io_input_w_payload_last, + output io_input_b_valid, + input io_input_b_ready, + output [7:0] io_input_b_payload_id, + output [1:0] io_input_b_payload_resp, + output io_output_aw_valid, + input io_output_aw_ready, + output [31:0] io_output_aw_payload_addr, + output [7:0] io_output_aw_payload_id, + output [3:0] io_output_aw_payload_region, + output reg [7:0] io_output_aw_payload_len, + output reg [2:0] io_output_aw_payload_size, + output [1:0] io_output_aw_payload_burst, + output [0:0] io_output_aw_payload_lock, + output [3:0] io_output_aw_payload_cache, + output [3:0] io_output_aw_payload_qos, + output [2:0] io_output_aw_payload_prot, + output io_output_w_valid, + input io_output_w_ready, + output [255:0] io_output_w_payload_data, + output [31:0] io_output_w_payload_strb, + output io_output_w_payload_last, + input io_output_b_valid, + output io_output_b_ready, + input [7:0] io_output_b_payload_id, + input [1:0] io_output_b_payload_resp, + input clk, + input reset +); + + wire [14:0] _zz_cmdLogic_byteCount; + wire [10:0] _zz_cmdLogic_incrLen; + wire [10:0] _zz_cmdLogic_incrLen_1; + wire [4:0] _zz_cmdLogic_incrLen_2; + wire [5:0] _zz_dataLogic_byteCounterNext; + wire [7:0] _zz_dataLogic_byteCounterNext_1; + reg [31:0] _zz_dataLogic_byteActivity; + wire cmdLogic_outputFork_valid; + wire cmdLogic_outputFork_ready; + wire [31:0] cmdLogic_outputFork_payload_addr; + wire [7:0] cmdLogic_outputFork_payload_id; + wire [3:0] cmdLogic_outputFork_payload_region; + wire [7:0] cmdLogic_outputFork_payload_len; + wire [2:0] cmdLogic_outputFork_payload_size; + wire [1:0] cmdLogic_outputFork_payload_burst; + wire [0:0] cmdLogic_outputFork_payload_lock; + wire [3:0] cmdLogic_outputFork_payload_cache; + wire [3:0] cmdLogic_outputFork_payload_qos; + wire [2:0] cmdLogic_outputFork_payload_prot; + wire cmdLogic_dataFork_valid; + wire cmdLogic_dataFork_ready; + wire [31:0] cmdLogic_dataFork_payload_addr; + wire [7:0] cmdLogic_dataFork_payload_id; + wire [3:0] cmdLogic_dataFork_payload_region; + wire [7:0] cmdLogic_dataFork_payload_len; + wire [2:0] cmdLogic_dataFork_payload_size; + wire [1:0] cmdLogic_dataFork_payload_burst; + wire [0:0] cmdLogic_dataFork_payload_lock; + wire [3:0] cmdLogic_dataFork_payload_cache; + wire [3:0] cmdLogic_dataFork_payload_qos; + wire [2:0] cmdLogic_dataFork_payload_prot; + reg io_input_aw_fork2_logic_linkEnable_0; + reg io_input_aw_fork2_logic_linkEnable_1; + wire when_Stream_l993; + wire when_Stream_l993_1; + wire cmdLogic_outputFork_fire; + wire cmdLogic_dataFork_fire; + wire [9:0] cmdLogic_byteCount; + wire [5:0] cmdLogic_incrLen; + wire when_Axi4Upsizer_l21; + wire when_Axi4Upsizer_l24; + reg [4:0] dataLogic_byteCounter; + reg [2:0] dataLogic_size; + reg dataLogic_outputValid; + reg dataLogic_outputLast; + reg dataLogic_busy; + reg dataLogic_incrementByteCounter; + reg dataLogic_alwaysFire; + wire [5:0] dataLogic_byteCounterNext; + reg [255:0] dataLogic_dataBuffer; + reg [31:0] dataLogic_maskBuffer; + wire [31:0] dataLogic_byteActivity; + wire io_output_w_fire; + wire io_output_w_isStall; + wire io_input_w_fire; + wire when_Axi4Upsizer_l59; + wire when_Axi4Upsizer_l59_1; + wire when_Axi4Upsizer_l59_2; + wire when_Axi4Upsizer_l59_3; + wire when_Axi4Upsizer_l59_4; + wire when_Axi4Upsizer_l59_5; + wire when_Axi4Upsizer_l59_6; + wire when_Axi4Upsizer_l59_7; + wire when_Axi4Upsizer_l59_8; + wire when_Axi4Upsizer_l59_9; + wire when_Axi4Upsizer_l59_10; + wire when_Axi4Upsizer_l59_11; + wire when_Axi4Upsizer_l59_12; + wire when_Axi4Upsizer_l59_13; + wire when_Axi4Upsizer_l59_14; + wire when_Axi4Upsizer_l59_15; + wire when_Axi4Upsizer_l59_16; + wire when_Axi4Upsizer_l59_17; + wire when_Axi4Upsizer_l59_18; + wire when_Axi4Upsizer_l59_19; + wire when_Axi4Upsizer_l59_20; + wire when_Axi4Upsizer_l59_21; + wire when_Axi4Upsizer_l59_22; + wire when_Axi4Upsizer_l59_23; + wire when_Axi4Upsizer_l59_24; + wire when_Axi4Upsizer_l59_25; + wire when_Axi4Upsizer_l59_26; + wire when_Axi4Upsizer_l59_27; + wire when_Axi4Upsizer_l59_28; + wire when_Axi4Upsizer_l59_29; + wire when_Axi4Upsizer_l59_30; + wire when_Axi4Upsizer_l59_31; + wire cmdLogic_dataFork_fire_1; + wire when_Axi4Upsizer_l68; + wire when_Axi4Upsizer_l68_1; + wire when_Axi4Upsizer_l68_2; + wire when_Axi4Upsizer_l68_3; + wire when_Axi4Upsizer_l68_4; + + assign _zz_cmdLogic_byteCount = ({7'd0,io_input_aw_payload_len} <<< io_input_aw_payload_size); + assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); + assign _zz_cmdLogic_incrLen_2 = io_input_aw_payload_addr[4 : 0]; + assign _zz_cmdLogic_incrLen_1 = {6'd0, _zz_cmdLogic_incrLen_2}; + assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); + assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[5:0]; + always @(*) begin + case(dataLogic_size) + 3'b000 : _zz_dataLogic_byteActivity = 32'h00000001; + 3'b001 : _zz_dataLogic_byteActivity = 32'h00000003; + 3'b010 : _zz_dataLogic_byteActivity = 32'h0000000f; + 3'b011 : _zz_dataLogic_byteActivity = 32'h000000ff; + default : _zz_dataLogic_byteActivity = 32'h0000ffff; + endcase + end + + always @(*) begin + io_input_aw_ready = 1'b1; + if(when_Stream_l993) begin + io_input_aw_ready = 1'b0; + end + if(when_Stream_l993_1) begin + io_input_aw_ready = 1'b0; + end + end + + assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_aw_fork2_logic_linkEnable_0); + assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_aw_fork2_logic_linkEnable_1); + assign cmdLogic_outputFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_0); + assign cmdLogic_outputFork_payload_addr = io_input_aw_payload_addr; + assign cmdLogic_outputFork_payload_id = io_input_aw_payload_id; + assign cmdLogic_outputFork_payload_region = io_input_aw_payload_region; + assign cmdLogic_outputFork_payload_len = io_input_aw_payload_len; + assign cmdLogic_outputFork_payload_size = io_input_aw_payload_size; + assign cmdLogic_outputFork_payload_burst = io_input_aw_payload_burst; + assign cmdLogic_outputFork_payload_lock = io_input_aw_payload_lock; + assign cmdLogic_outputFork_payload_cache = io_input_aw_payload_cache; + assign cmdLogic_outputFork_payload_qos = io_input_aw_payload_qos; + assign cmdLogic_outputFork_payload_prot = io_input_aw_payload_prot; + assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); + assign cmdLogic_dataFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_1); + assign cmdLogic_dataFork_payload_addr = io_input_aw_payload_addr; + assign cmdLogic_dataFork_payload_id = io_input_aw_payload_id; + assign cmdLogic_dataFork_payload_region = io_input_aw_payload_region; + assign cmdLogic_dataFork_payload_len = io_input_aw_payload_len; + assign cmdLogic_dataFork_payload_size = io_input_aw_payload_size; + assign cmdLogic_dataFork_payload_burst = io_input_aw_payload_burst; + assign cmdLogic_dataFork_payload_lock = io_input_aw_payload_lock; + assign cmdLogic_dataFork_payload_cache = io_input_aw_payload_cache; + assign cmdLogic_dataFork_payload_qos = io_input_aw_payload_qos; + assign cmdLogic_dataFork_payload_prot = io_input_aw_payload_prot; + assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign io_output_aw_valid = cmdLogic_outputFork_valid; + assign cmdLogic_outputFork_ready = io_output_aw_ready; + assign io_output_aw_payload_addr = cmdLogic_outputFork_payload_addr; + assign io_output_aw_payload_id = cmdLogic_outputFork_payload_id; + assign io_output_aw_payload_region = cmdLogic_outputFork_payload_region; + always @(*) begin + io_output_aw_payload_len = cmdLogic_outputFork_payload_len; + if(when_Axi4Upsizer_l21) begin + io_output_aw_payload_len = {2'd0, cmdLogic_incrLen}; + end + end + + always @(*) begin + io_output_aw_payload_size = cmdLogic_outputFork_payload_size; + if(when_Axi4Upsizer_l21) begin + io_output_aw_payload_size = 3'b101; + if(when_Axi4Upsizer_l24) begin + io_output_aw_payload_size = io_input_aw_payload_size; + end + end + end + + assign io_output_aw_payload_burst = cmdLogic_outputFork_payload_burst; + assign io_output_aw_payload_lock = cmdLogic_outputFork_payload_lock; + assign io_output_aw_payload_cache = cmdLogic_outputFork_payload_cache; + assign io_output_aw_payload_qos = cmdLogic_outputFork_payload_qos; + assign io_output_aw_payload_prot = cmdLogic_outputFork_payload_prot; + assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; + assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 5]; + assign when_Axi4Upsizer_l21 = (io_output_aw_payload_burst == 2'b01); + assign when_Axi4Upsizer_l24 = (io_input_aw_payload_len == 8'h00); + assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); + assign dataLogic_byteActivity = (_zz_dataLogic_byteActivity <<< dataLogic_byteCounter); + assign io_output_w_fire = (io_output_w_valid && io_output_w_ready); + assign io_output_w_valid = dataLogic_outputValid; + assign io_output_w_isStall = (io_output_w_valid && (! io_output_w_ready)); + assign io_input_w_ready = (dataLogic_busy && (! io_output_w_isStall)); + assign io_output_w_payload_data = dataLogic_dataBuffer; + assign io_output_w_payload_strb = dataLogic_maskBuffer; + assign io_output_w_payload_last = dataLogic_outputLast; + assign io_input_w_fire = (io_input_w_valid && io_input_w_ready); + assign when_Axi4Upsizer_l59 = dataLogic_byteActivity[0]; + assign when_Axi4Upsizer_l59_1 = dataLogic_byteActivity[1]; + assign when_Axi4Upsizer_l59_2 = dataLogic_byteActivity[2]; + assign when_Axi4Upsizer_l59_3 = dataLogic_byteActivity[3]; + assign when_Axi4Upsizer_l59_4 = dataLogic_byteActivity[4]; + assign when_Axi4Upsizer_l59_5 = dataLogic_byteActivity[5]; + assign when_Axi4Upsizer_l59_6 = dataLogic_byteActivity[6]; + assign when_Axi4Upsizer_l59_7 = dataLogic_byteActivity[7]; + assign when_Axi4Upsizer_l59_8 = dataLogic_byteActivity[8]; + assign when_Axi4Upsizer_l59_9 = dataLogic_byteActivity[9]; + assign when_Axi4Upsizer_l59_10 = dataLogic_byteActivity[10]; + assign when_Axi4Upsizer_l59_11 = dataLogic_byteActivity[11]; + assign when_Axi4Upsizer_l59_12 = dataLogic_byteActivity[12]; + assign when_Axi4Upsizer_l59_13 = dataLogic_byteActivity[13]; + assign when_Axi4Upsizer_l59_14 = dataLogic_byteActivity[14]; + assign when_Axi4Upsizer_l59_15 = dataLogic_byteActivity[15]; + assign when_Axi4Upsizer_l59_16 = dataLogic_byteActivity[16]; + assign when_Axi4Upsizer_l59_17 = dataLogic_byteActivity[17]; + assign when_Axi4Upsizer_l59_18 = dataLogic_byteActivity[18]; + assign when_Axi4Upsizer_l59_19 = dataLogic_byteActivity[19]; + assign when_Axi4Upsizer_l59_20 = dataLogic_byteActivity[20]; + assign when_Axi4Upsizer_l59_21 = dataLogic_byteActivity[21]; + assign when_Axi4Upsizer_l59_22 = dataLogic_byteActivity[22]; + assign when_Axi4Upsizer_l59_23 = dataLogic_byteActivity[23]; + assign when_Axi4Upsizer_l59_24 = dataLogic_byteActivity[24]; + assign when_Axi4Upsizer_l59_25 = dataLogic_byteActivity[25]; + assign when_Axi4Upsizer_l59_26 = dataLogic_byteActivity[26]; + assign when_Axi4Upsizer_l59_27 = dataLogic_byteActivity[27]; + assign when_Axi4Upsizer_l59_28 = dataLogic_byteActivity[28]; + assign when_Axi4Upsizer_l59_29 = dataLogic_byteActivity[29]; + assign when_Axi4Upsizer_l59_30 = dataLogic_byteActivity[30]; + assign when_Axi4Upsizer_l59_31 = dataLogic_byteActivity[31]; + assign cmdLogic_dataFork_fire_1 = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign when_Axi4Upsizer_l68 = (3'b000 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_1 = (3'b001 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_2 = (3'b010 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_3 = (3'b011 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_4 = (3'b100 < cmdLogic_dataFork_payload_size); + assign cmdLogic_dataFork_ready = (! dataLogic_busy); + assign io_input_b_valid = io_output_b_valid; + assign io_output_b_ready = io_input_b_ready; + assign io_input_b_payload_id = io_output_b_payload_id; + assign io_input_b_payload_resp = io_output_b_payload_resp; + always @(posedge clk or posedge reset) begin + if(reset) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; + io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; + dataLogic_outputValid <= 1'b0; + dataLogic_busy <= 1'b0; + dataLogic_maskBuffer <= 32'h00000000; + end else begin + if(cmdLogic_outputFork_fire) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdLogic_dataFork_fire) begin + io_input_aw_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_aw_ready) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; + io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; + end + if(io_output_w_ready) begin + dataLogic_outputValid <= 1'b0; + end + if(io_output_w_fire) begin + dataLogic_maskBuffer <= 32'h00000000; + end + if(io_input_w_fire) begin + dataLogic_outputValid <= ((dataLogic_byteCounterNext[5] || io_input_w_payload_last) || dataLogic_alwaysFire); + if(io_input_w_payload_last) begin + dataLogic_busy <= 1'b0; + end + if(when_Axi4Upsizer_l59) begin + dataLogic_maskBuffer[0] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_1) begin + dataLogic_maskBuffer[1] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_2) begin + dataLogic_maskBuffer[2] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_3) begin + dataLogic_maskBuffer[3] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_4) begin + dataLogic_maskBuffer[4] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_5) begin + dataLogic_maskBuffer[5] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_6) begin + dataLogic_maskBuffer[6] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_7) begin + dataLogic_maskBuffer[7] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_8) begin + dataLogic_maskBuffer[8] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_9) begin + dataLogic_maskBuffer[9] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_10) begin + dataLogic_maskBuffer[10] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_11) begin + dataLogic_maskBuffer[11] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_12) begin + dataLogic_maskBuffer[12] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_13) begin + dataLogic_maskBuffer[13] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_14) begin + dataLogic_maskBuffer[14] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_15) begin + dataLogic_maskBuffer[15] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_16) begin + dataLogic_maskBuffer[16] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_17) begin + dataLogic_maskBuffer[17] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_18) begin + dataLogic_maskBuffer[18] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_19) begin + dataLogic_maskBuffer[19] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_20) begin + dataLogic_maskBuffer[20] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_21) begin + dataLogic_maskBuffer[21] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_22) begin + dataLogic_maskBuffer[22] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_23) begin + dataLogic_maskBuffer[23] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_24) begin + dataLogic_maskBuffer[24] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_25) begin + dataLogic_maskBuffer[25] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_26) begin + dataLogic_maskBuffer[26] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_27) begin + dataLogic_maskBuffer[27] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_28) begin + dataLogic_maskBuffer[28] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_29) begin + dataLogic_maskBuffer[29] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_30) begin + dataLogic_maskBuffer[30] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_31) begin + dataLogic_maskBuffer[31] <= io_input_w_payload_strb[3]; + end + end + if(cmdLogic_dataFork_fire_1) begin + dataLogic_busy <= 1'b1; + end + end + end + + always @(posedge clk) begin + if(io_input_w_fire) begin + if(dataLogic_incrementByteCounter) begin + dataLogic_byteCounter <= dataLogic_byteCounterNext[4:0]; + end + dataLogic_outputLast <= io_input_w_payload_last; + if(when_Axi4Upsizer_l59) begin + dataLogic_dataBuffer[7 : 0] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_1) begin + dataLogic_dataBuffer[15 : 8] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_2) begin + dataLogic_dataBuffer[23 : 16] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_3) begin + dataLogic_dataBuffer[31 : 24] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_4) begin + dataLogic_dataBuffer[39 : 32] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_5) begin + dataLogic_dataBuffer[47 : 40] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_6) begin + dataLogic_dataBuffer[55 : 48] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_7) begin + dataLogic_dataBuffer[63 : 56] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_8) begin + dataLogic_dataBuffer[71 : 64] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_9) begin + dataLogic_dataBuffer[79 : 72] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_10) begin + dataLogic_dataBuffer[87 : 80] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_11) begin + dataLogic_dataBuffer[95 : 88] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_12) begin + dataLogic_dataBuffer[103 : 96] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_13) begin + dataLogic_dataBuffer[111 : 104] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_14) begin + dataLogic_dataBuffer[119 : 112] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_15) begin + dataLogic_dataBuffer[127 : 120] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_16) begin + dataLogic_dataBuffer[135 : 128] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_17) begin + dataLogic_dataBuffer[143 : 136] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_18) begin + dataLogic_dataBuffer[151 : 144] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_19) begin + dataLogic_dataBuffer[159 : 152] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_20) begin + dataLogic_dataBuffer[167 : 160] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_21) begin + dataLogic_dataBuffer[175 : 168] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_22) begin + dataLogic_dataBuffer[183 : 176] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_23) begin + dataLogic_dataBuffer[191 : 184] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_24) begin + dataLogic_dataBuffer[199 : 192] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_25) begin + dataLogic_dataBuffer[207 : 200] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_26) begin + dataLogic_dataBuffer[215 : 208] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_27) begin + dataLogic_dataBuffer[223 : 216] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_28) begin + dataLogic_dataBuffer[231 : 224] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_29) begin + dataLogic_dataBuffer[239 : 232] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_30) begin + dataLogic_dataBuffer[247 : 240] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_31) begin + dataLogic_dataBuffer[255 : 248] <= io_input_w_payload_data[31 : 24]; + end + end + if(cmdLogic_dataFork_fire_1) begin + dataLogic_byteCounter <= cmdLogic_dataFork_payload_addr[4:0]; + if(when_Axi4Upsizer_l68) begin + dataLogic_byteCounter[0] <= 1'b0; + end + if(when_Axi4Upsizer_l68_1) begin + dataLogic_byteCounter[1] <= 1'b0; + end + if(when_Axi4Upsizer_l68_2) begin + dataLogic_byteCounter[2] <= 1'b0; + end + if(when_Axi4Upsizer_l68_3) begin + dataLogic_byteCounter[3] <= 1'b0; + end + if(when_Axi4Upsizer_l68_4) begin + dataLogic_byteCounter[4] <= 1'b0; + end + dataLogic_size <= cmdLogic_dataFork_payload_size; + dataLogic_alwaysFire <= (! (cmdLogic_dataFork_payload_burst == 2'b01)); + dataLogic_incrementByteCounter <= (! (cmdLogic_dataFork_payload_burst == 2'b00)); + end + end + + +endmodule + +module Asic32To256UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_ar_valid, + output reg io_input_ar_ready, + input [31:0] io_input_ar_payload_addr, + input [7:0] io_input_ar_payload_id, + input [3:0] io_input_ar_payload_region, + input [7:0] io_input_ar_payload_len, + input [2:0] io_input_ar_payload_size, + input [1:0] io_input_ar_payload_burst, + input [0:0] io_input_ar_payload_lock, + input [3:0] io_input_ar_payload_cache, + input [3:0] io_input_ar_payload_qos, + input [2:0] io_input_ar_payload_prot, + output io_input_r_valid, + input io_input_r_ready, + output [31:0] io_input_r_payload_data, + output [7:0] io_input_r_payload_id, + output [1:0] io_input_r_payload_resp, + output io_input_r_payload_last, + output io_output_ar_valid, + input io_output_ar_ready, + output [31:0] io_output_ar_payload_addr, + output [7:0] io_output_ar_payload_id, + output [3:0] io_output_ar_payload_region, + output [7:0] io_output_ar_payload_len, + output reg [2:0] io_output_ar_payload_size, + output [1:0] io_output_ar_payload_burst, + output [0:0] io_output_ar_payload_lock, + output [3:0] io_output_ar_payload_cache, + output [3:0] io_output_ar_payload_qos, + output [2:0] io_output_ar_payload_prot, + input io_output_r_valid, + output io_output_r_ready, + input [255:0] io_output_r_payload_data, + input [7:0] io_output_r_payload_id, + input [1:0] io_output_r_payload_resp, + input io_output_r_payload_last, + input clk, + input reset +); + + wire dataLogic_cmdPush_fifo_io_pop_ready; + wire dataLogic_cmdPush_fifo_io_push_ready; + wire dataLogic_cmdPush_fifo_io_pop_valid; + wire [4:0] dataLogic_cmdPush_fifo_io_pop_payload_startAt; + wire [4:0] dataLogic_cmdPush_fifo_io_pop_payload_endAt; + wire [2:0] dataLogic_cmdPush_fifo_io_pop_payload_size; + wire [7:0] dataLogic_cmdPush_fifo_io_pop_payload_id; + wire [4:0] dataLogic_cmdPush_fifo_io_occupancy; + wire [4:0] dataLogic_cmdPush_fifo_io_availability; + wire [14:0] _zz_cmdLogic_byteCount; + wire [10:0] _zz_cmdLogic_incrLen; + wire [10:0] _zz_cmdLogic_incrLen_1; + wire [4:0] _zz_cmdLogic_incrLen_2; + wire [31:0] _zz_dataLogic_cmdPush_payload_endAt; + wire [31:0] _zz_dataLogic_cmdPush_payload_endAt_1; + wire [14:0] _zz_dataLogic_cmdPush_payload_endAt_2; + wire [5:0] _zz_dataLogic_byteCounterNext; + wire [7:0] _zz_dataLogic_byteCounterNext_1; + reg [31:0] _zz_io_input_r_payload_data; + wire [2:0] _zz_io_input_r_payload_data_1; + wire cmdLogic_outputFork_valid; + wire cmdLogic_outputFork_ready; + wire [31:0] cmdLogic_outputFork_payload_addr; + wire [7:0] cmdLogic_outputFork_payload_id; + wire [3:0] cmdLogic_outputFork_payload_region; + wire [7:0] cmdLogic_outputFork_payload_len; + wire [2:0] cmdLogic_outputFork_payload_size; + wire [1:0] cmdLogic_outputFork_payload_burst; + wire [0:0] cmdLogic_outputFork_payload_lock; + wire [3:0] cmdLogic_outputFork_payload_cache; + wire [3:0] cmdLogic_outputFork_payload_qos; + wire [2:0] cmdLogic_outputFork_payload_prot; + wire cmdLogic_dataFork_valid; + wire cmdLogic_dataFork_ready; + wire [31:0] cmdLogic_dataFork_payload_addr; + wire [7:0] cmdLogic_dataFork_payload_id; + wire [3:0] cmdLogic_dataFork_payload_region; + wire [7:0] cmdLogic_dataFork_payload_len; + wire [2:0] cmdLogic_dataFork_payload_size; + wire [1:0] cmdLogic_dataFork_payload_burst; + wire [0:0] cmdLogic_dataFork_payload_lock; + wire [3:0] cmdLogic_dataFork_payload_cache; + wire [3:0] cmdLogic_dataFork_payload_qos; + wire [2:0] cmdLogic_dataFork_payload_prot; + reg io_input_ar_fork2_logic_linkEnable_0; + reg io_input_ar_fork2_logic_linkEnable_1; + wire when_Stream_l993; + wire when_Stream_l993_1; + wire cmdLogic_outputFork_fire; + wire cmdLogic_dataFork_fire; + wire [9:0] cmdLogic_byteCount; + wire [5:0] cmdLogic_incrLen; + wire when_Axi4Upsizer_l108; + wire dataLogic_cmdPush_valid; + wire dataLogic_cmdPush_ready; + wire [4:0] dataLogic_cmdPush_payload_startAt; + wire [4:0] dataLogic_cmdPush_payload_endAt; + wire [2:0] dataLogic_cmdPush_payload_size; + wire [7:0] dataLogic_cmdPush_payload_id; + reg [2:0] dataLogic_size; + reg dataLogic_busy; + reg [7:0] dataLogic_id; + reg [4:0] dataLogic_byteCounter; + reg [4:0] dataLogic_byteCounterLast; + wire [5:0] dataLogic_byteCounterNext; + wire readOnly_dataLogic_cmdPush_fifo_io_pop_fire; + wire io_input_r_fire; + + assign _zz_cmdLogic_byteCount = ({7'd0,io_input_ar_payload_len} <<< io_input_ar_payload_size); + assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); + assign _zz_cmdLogic_incrLen_2 = io_input_ar_payload_addr[4 : 0]; + assign _zz_cmdLogic_incrLen_1 = {6'd0, _zz_cmdLogic_incrLen_2}; + assign _zz_dataLogic_cmdPush_payload_endAt = (cmdLogic_dataFork_payload_addr + _zz_dataLogic_cmdPush_payload_endAt_1); + assign _zz_dataLogic_cmdPush_payload_endAt_2 = ({7'd0,cmdLogic_dataFork_payload_len} <<< cmdLogic_dataFork_payload_size); + assign _zz_dataLogic_cmdPush_payload_endAt_1 = {17'd0, _zz_dataLogic_cmdPush_payload_endAt_2}; + assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); + assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[5:0]; + assign _zz_io_input_r_payload_data_1 = (dataLogic_byteCounter >>> 2'd2); + Asic32To256UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 dataLogic_cmdPush_fifo ( + .io_push_valid (dataLogic_cmdPush_valid ), //i + .io_push_ready (dataLogic_cmdPush_fifo_io_push_ready ), //o + .io_push_payload_startAt (dataLogic_cmdPush_payload_startAt[4:0] ), //i + .io_push_payload_endAt (dataLogic_cmdPush_payload_endAt[4:0] ), //i + .io_push_payload_size (dataLogic_cmdPush_payload_size[2:0] ), //i + .io_push_payload_id (dataLogic_cmdPush_payload_id[7:0] ), //i + .io_pop_valid (dataLogic_cmdPush_fifo_io_pop_valid ), //o + .io_pop_ready (dataLogic_cmdPush_fifo_io_pop_ready ), //i + .io_pop_payload_startAt (dataLogic_cmdPush_fifo_io_pop_payload_startAt[4:0]), //o + .io_pop_payload_endAt (dataLogic_cmdPush_fifo_io_pop_payload_endAt[4:0] ), //o + .io_pop_payload_size (dataLogic_cmdPush_fifo_io_pop_payload_size[2:0] ), //o + .io_pop_payload_id (dataLogic_cmdPush_fifo_io_pop_payload_id[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (dataLogic_cmdPush_fifo_io_occupancy[4:0] ), //o + .io_availability (dataLogic_cmdPush_fifo_io_availability[4:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_io_input_r_payload_data_1) + 3'b000 : _zz_io_input_r_payload_data = io_output_r_payload_data[31 : 0]; + 3'b001 : _zz_io_input_r_payload_data = io_output_r_payload_data[63 : 32]; + 3'b010 : _zz_io_input_r_payload_data = io_output_r_payload_data[95 : 64]; + 3'b011 : _zz_io_input_r_payload_data = io_output_r_payload_data[127 : 96]; + 3'b100 : _zz_io_input_r_payload_data = io_output_r_payload_data[159 : 128]; + 3'b101 : _zz_io_input_r_payload_data = io_output_r_payload_data[191 : 160]; + 3'b110 : _zz_io_input_r_payload_data = io_output_r_payload_data[223 : 192]; + default : _zz_io_input_r_payload_data = io_output_r_payload_data[255 : 224]; + endcase + end + + always @(*) begin + io_input_ar_ready = 1'b1; + if(when_Stream_l993) begin + io_input_ar_ready = 1'b0; + end + if(when_Stream_l993_1) begin + io_input_ar_ready = 1'b0; + end + end + + assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_ar_fork2_logic_linkEnable_0); + assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_ar_fork2_logic_linkEnable_1); + assign cmdLogic_outputFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_0); + assign cmdLogic_outputFork_payload_addr = io_input_ar_payload_addr; + assign cmdLogic_outputFork_payload_id = io_input_ar_payload_id; + assign cmdLogic_outputFork_payload_region = io_input_ar_payload_region; + assign cmdLogic_outputFork_payload_len = io_input_ar_payload_len; + assign cmdLogic_outputFork_payload_size = io_input_ar_payload_size; + assign cmdLogic_outputFork_payload_burst = io_input_ar_payload_burst; + assign cmdLogic_outputFork_payload_lock = io_input_ar_payload_lock; + assign cmdLogic_outputFork_payload_cache = io_input_ar_payload_cache; + assign cmdLogic_outputFork_payload_qos = io_input_ar_payload_qos; + assign cmdLogic_outputFork_payload_prot = io_input_ar_payload_prot; + assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); + assign cmdLogic_dataFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_1); + assign cmdLogic_dataFork_payload_addr = io_input_ar_payload_addr; + assign cmdLogic_dataFork_payload_id = io_input_ar_payload_id; + assign cmdLogic_dataFork_payload_region = io_input_ar_payload_region; + assign cmdLogic_dataFork_payload_len = io_input_ar_payload_len; + assign cmdLogic_dataFork_payload_size = io_input_ar_payload_size; + assign cmdLogic_dataFork_payload_burst = io_input_ar_payload_burst; + assign cmdLogic_dataFork_payload_lock = io_input_ar_payload_lock; + assign cmdLogic_dataFork_payload_cache = io_input_ar_payload_cache; + assign cmdLogic_dataFork_payload_qos = io_input_ar_payload_qos; + assign cmdLogic_dataFork_payload_prot = io_input_ar_payload_prot; + assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign io_output_ar_valid = cmdLogic_outputFork_valid; + assign cmdLogic_outputFork_ready = io_output_ar_ready; + assign io_output_ar_payload_addr = cmdLogic_outputFork_payload_addr; + assign io_output_ar_payload_region = cmdLogic_outputFork_payload_region; + assign io_output_ar_payload_burst = cmdLogic_outputFork_payload_burst; + assign io_output_ar_payload_lock = cmdLogic_outputFork_payload_lock; + assign io_output_ar_payload_cache = cmdLogic_outputFork_payload_cache; + assign io_output_ar_payload_qos = cmdLogic_outputFork_payload_qos; + assign io_output_ar_payload_prot = cmdLogic_outputFork_payload_prot; + assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; + assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 5]; + always @(*) begin + io_output_ar_payload_size = 3'b101; + if(when_Axi4Upsizer_l108) begin + io_output_ar_payload_size = io_input_ar_payload_size; + end + end + + assign io_output_ar_payload_len = {2'd0, cmdLogic_incrLen}; + assign io_output_ar_payload_id = 8'h00; + assign when_Axi4Upsizer_l108 = (io_input_ar_payload_len == 8'h00); + assign dataLogic_cmdPush_valid = cmdLogic_dataFork_valid; + assign cmdLogic_dataFork_ready = dataLogic_cmdPush_ready; + assign dataLogic_cmdPush_payload_startAt = cmdLogic_dataFork_payload_addr[4:0]; + assign dataLogic_cmdPush_payload_endAt = _zz_dataLogic_cmdPush_payload_endAt[4:0]; + assign dataLogic_cmdPush_payload_size = cmdLogic_dataFork_payload_size; + assign dataLogic_cmdPush_payload_id = cmdLogic_dataFork_payload_id; + assign dataLogic_cmdPush_ready = dataLogic_cmdPush_fifo_io_push_ready; + assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); + assign readOnly_dataLogic_cmdPush_fifo_io_pop_fire = (dataLogic_cmdPush_fifo_io_pop_valid && dataLogic_cmdPush_fifo_io_pop_ready); + assign dataLogic_cmdPush_fifo_io_pop_ready = (! dataLogic_busy); + assign io_input_r_fire = (io_input_r_valid && io_input_r_ready); + assign io_input_r_valid = (io_output_r_valid && dataLogic_busy); + assign io_input_r_payload_last = (io_output_r_payload_last && (dataLogic_byteCounter == dataLogic_byteCounterLast)); + assign io_input_r_payload_resp = io_output_r_payload_resp; + assign io_input_r_payload_data = _zz_io_input_r_payload_data; + assign io_input_r_payload_id = dataLogic_id; + assign io_output_r_ready = ((dataLogic_busy && io_input_r_ready) && (io_input_r_payload_last || dataLogic_byteCounterNext[5])); + always @(posedge clk or posedge reset) begin + if(reset) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; + io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; + dataLogic_busy <= 1'b0; + end else begin + if(cmdLogic_outputFork_fire) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdLogic_dataFork_fire) begin + io_input_ar_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_ar_ready) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; + io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; + end + if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin + dataLogic_busy <= 1'b1; + end + if(io_input_r_fire) begin + if(io_input_r_payload_last) begin + dataLogic_busy <= 1'b0; + end + end + end + end + + always @(posedge clk) begin + if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin + dataLogic_byteCounter <= dataLogic_cmdPush_fifo_io_pop_payload_startAt; + dataLogic_byteCounterLast <= dataLogic_cmdPush_fifo_io_pop_payload_endAt; + dataLogic_size <= dataLogic_cmdPush_fifo_io_pop_payload_size; + dataLogic_id <= dataLogic_cmdPush_fifo_io_pop_payload_id; + end + if(io_input_r_fire) begin + dataLogic_byteCounter <= dataLogic_byteCounterNext[4:0]; + end + end + + +endmodule + +module Asic32To256UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_push_valid, + output io_push_ready, + input [4:0] io_push_payload_startAt, + input [4:0] io_push_payload_endAt, + input [2:0] io_push_payload_size, + input [7:0] io_push_payload_id, + output io_pop_valid, + input io_pop_ready, + output [4:0] io_pop_payload_startAt, + output [4:0] io_pop_payload_endAt, + output [2:0] io_pop_payload_size, + output [7:0] io_pop_payload_id, + input io_flush, + output [4:0] io_occupancy, + output [4:0] io_availability, + input clk, + input reset +); + + reg [20:0] _zz_logic_ram_port0; + wire [3:0] _zz_logic_pushPtr_valueNext; + wire [0:0] _zz_logic_pushPtr_valueNext_1; + wire [3:0] _zz_logic_popPtr_valueNext; + wire [0:0] _zz_logic_popPtr_valueNext_1; + wire _zz__zz_logic_ram_port0; + wire _zz__zz_io_pop_payload_startAt; + wire [20:0] _zz__zz_logic_ram_port1; + wire [3:0] _zz_io_availability; + reg _zz_1; + reg logic_pushPtr_willIncrement; + reg logic_pushPtr_willClear; + reg [3:0] logic_pushPtr_valueNext; + reg [3:0] logic_pushPtr_value; + wire logic_pushPtr_willOverflowIfInc; + wire logic_pushPtr_willOverflow; + reg logic_popPtr_willIncrement; + reg logic_popPtr_willClear; + reg [3:0] logic_popPtr_valueNext; + reg [3:0] logic_popPtr_value; + wire logic_popPtr_willOverflowIfInc; + wire logic_popPtr_willOverflow; + wire logic_ptrMatch; + reg logic_risingOccupancy; + wire logic_pushing; + wire logic_popping; + wire logic_empty; + wire logic_full; + reg _zz_io_pop_valid; + wire [20:0] _zz_io_pop_payload_startAt; + wire when_Stream_l1123; + wire [3:0] logic_ptrDif; + reg [20:0] logic_ram [0:15]; + + assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; + assign _zz_logic_pushPtr_valueNext = {3'd0, _zz_logic_pushPtr_valueNext_1}; + assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; + assign _zz_logic_popPtr_valueNext = {3'd0, _zz_logic_popPtr_valueNext_1}; + assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); + assign _zz__zz_io_pop_payload_startAt = 1'b1; + assign _zz__zz_logic_ram_port1 = {io_push_payload_id,{io_push_payload_size,{io_push_payload_endAt,io_push_payload_startAt}}}; + always @(posedge clk) begin + if(_zz__zz_io_pop_payload_startAt) begin + _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_pushPtr_value] <= _zz__zz_logic_ram_port1; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_pushing) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willIncrement = 1'b0; + if(logic_pushing) begin + logic_pushPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willClear = 1'b0; + if(io_flush) begin + logic_pushPtr_willClear = 1'b1; + end + end + + assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 4'b1111); + assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); + always @(*) begin + logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); + if(logic_pushPtr_willClear) begin + logic_pushPtr_valueNext = 4'b0000; + end + end + + always @(*) begin + logic_popPtr_willIncrement = 1'b0; + if(logic_popping) begin + logic_popPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_popPtr_willClear = 1'b0; + if(io_flush) begin + logic_popPtr_willClear = 1'b1; + end + end + + assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 4'b1111); + assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); + always @(*) begin + logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); + if(logic_popPtr_willClear) begin + logic_popPtr_valueNext = 4'b0000; + end + end + + assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); + assign logic_pushing = (io_push_valid && io_push_ready); + assign logic_popping = (io_pop_valid && io_pop_ready); + assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); + assign logic_full = (logic_ptrMatch && logic_risingOccupancy); + assign io_push_ready = (! logic_full); + assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); + assign _zz_io_pop_payload_startAt = _zz_logic_ram_port0; + assign io_pop_payload_startAt = _zz_io_pop_payload_startAt[4 : 0]; + assign io_pop_payload_endAt = _zz_io_pop_payload_startAt[9 : 5]; + assign io_pop_payload_size = _zz_io_pop_payload_startAt[12 : 10]; + assign io_pop_payload_id = _zz_io_pop_payload_startAt[20 : 13]; + assign when_Stream_l1123 = (logic_pushing != logic_popping); + assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); + assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; + assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; + always @(posedge clk or posedge reset) begin + if(reset) begin + logic_pushPtr_value <= 4'b0000; + logic_popPtr_value <= 4'b0000; + logic_risingOccupancy <= 1'b0; + _zz_io_pop_valid <= 1'b0; + end else begin + logic_pushPtr_value <= logic_pushPtr_valueNext; + logic_popPtr_value <= logic_popPtr_valueNext; + _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); + if(when_Stream_l1123) begin + logic_risingOccupancy <= logic_pushing; + end + if(io_flush) begin + logic_risingOccupancy <= 1'b0; + end + end + end + + +endmodule + + +// Generator : SpinalHDL dev git head : 9cdee03b276638ef8e7a948b606bb7acc6e4c8d0 +// Component : Asic32To512UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 +// Git hash : cd16421fb7a4d44431a2445f9a92b82070ab9b8a + +`timescale 1ns/1ps + +module Asic32To512UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_aw_valid, + output io_input_aw_ready, + input [31:0] io_input_aw_payload_addr, + input [7:0] io_input_aw_payload_id, + input [3:0] io_input_aw_payload_region, + input [7:0] io_input_aw_payload_len, + input [2:0] io_input_aw_payload_size, + input [1:0] io_input_aw_payload_burst, + input [0:0] io_input_aw_payload_lock, + input [3:0] io_input_aw_payload_cache, + input [3:0] io_input_aw_payload_qos, + input [2:0] io_input_aw_payload_prot, + input io_input_w_valid, + output io_input_w_ready, + input [31:0] io_input_w_payload_data, + input [3:0] io_input_w_payload_strb, + input io_input_w_payload_last, + output io_input_b_valid, + input io_input_b_ready, + output [7:0] io_input_b_payload_id, + output [1:0] io_input_b_payload_resp, + input io_input_ar_valid, + output io_input_ar_ready, + input [31:0] io_input_ar_payload_addr, + input [7:0] io_input_ar_payload_id, + input [3:0] io_input_ar_payload_region, + input [7:0] io_input_ar_payload_len, + input [2:0] io_input_ar_payload_size, + input [1:0] io_input_ar_payload_burst, + input [0:0] io_input_ar_payload_lock, + input [3:0] io_input_ar_payload_cache, + input [3:0] io_input_ar_payload_qos, + input [2:0] io_input_ar_payload_prot, + output io_input_r_valid, + input io_input_r_ready, + output [31:0] io_input_r_payload_data, + output [7:0] io_input_r_payload_id, + output [1:0] io_input_r_payload_resp, + output io_input_r_payload_last, + output io_output_aw_valid, + input io_output_aw_ready, + output [31:0] io_output_aw_payload_addr, + output [7:0] io_output_aw_payload_id, + output [3:0] io_output_aw_payload_region, + output [7:0] io_output_aw_payload_len, + output [2:0] io_output_aw_payload_size, + output [1:0] io_output_aw_payload_burst, + output [0:0] io_output_aw_payload_lock, + output [3:0] io_output_aw_payload_cache, + output [3:0] io_output_aw_payload_qos, + output [2:0] io_output_aw_payload_prot, + output io_output_w_valid, + input io_output_w_ready, + output [511:0] io_output_w_payload_data, + output [63:0] io_output_w_payload_strb, + output io_output_w_payload_last, + input io_output_b_valid, + output io_output_b_ready, + input [7:0] io_output_b_payload_id, + input [1:0] io_output_b_payload_resp, + output io_output_ar_valid, + input io_output_ar_ready, + output [31:0] io_output_ar_payload_addr, + output [7:0] io_output_ar_payload_id, + output [3:0] io_output_ar_payload_region, + output [7:0] io_output_ar_payload_len, + output [2:0] io_output_ar_payload_size, + output [1:0] io_output_ar_payload_burst, + output [0:0] io_output_ar_payload_lock, + output [3:0] io_output_ar_payload_cache, + output [3:0] io_output_ar_payload_qos, + output [2:0] io_output_ar_payload_prot, + input io_output_r_valid, + output io_output_r_ready, + input [511:0] io_output_r_payload_data, + input [7:0] io_output_r_payload_id, + input [1:0] io_output_r_payload_resp, + input io_output_r_payload_last, + input clk, + input reset +); + + wire readOnly_io_input_ar_ready; + wire readOnly_io_input_r_valid; + wire [31:0] readOnly_io_input_r_payload_data; + wire [7:0] readOnly_io_input_r_payload_id; + wire [1:0] readOnly_io_input_r_payload_resp; + wire readOnly_io_input_r_payload_last; + wire readOnly_io_output_ar_valid; + wire [31:0] readOnly_io_output_ar_payload_addr; + wire [7:0] readOnly_io_output_ar_payload_id; + wire [3:0] readOnly_io_output_ar_payload_region; + wire [7:0] readOnly_io_output_ar_payload_len; + wire [2:0] readOnly_io_output_ar_payload_size; + wire [1:0] readOnly_io_output_ar_payload_burst; + wire [0:0] readOnly_io_output_ar_payload_lock; + wire [3:0] readOnly_io_output_ar_payload_cache; + wire [3:0] readOnly_io_output_ar_payload_qos; + wire [2:0] readOnly_io_output_ar_payload_prot; + wire readOnly_io_output_r_ready; + wire writeOnly_io_input_aw_ready; + wire writeOnly_io_input_w_ready; + wire writeOnly_io_input_b_valid; + wire [7:0] writeOnly_io_input_b_payload_id; + wire [1:0] writeOnly_io_input_b_payload_resp; + wire writeOnly_io_output_aw_valid; + wire [31:0] writeOnly_io_output_aw_payload_addr; + wire [7:0] writeOnly_io_output_aw_payload_id; + wire [3:0] writeOnly_io_output_aw_payload_region; + wire [7:0] writeOnly_io_output_aw_payload_len; + wire [2:0] writeOnly_io_output_aw_payload_size; + wire [1:0] writeOnly_io_output_aw_payload_burst; + wire [0:0] writeOnly_io_output_aw_payload_lock; + wire [3:0] writeOnly_io_output_aw_payload_cache; + wire [3:0] writeOnly_io_output_aw_payload_qos; + wire [2:0] writeOnly_io_output_aw_payload_prot; + wire writeOnly_io_output_w_valid; + wire [511:0] writeOnly_io_output_w_payload_data; + wire [63:0] writeOnly_io_output_w_payload_strb; + wire writeOnly_io_output_w_payload_last; + wire writeOnly_io_output_b_ready; + + Asic32To512UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 readOnly ( + .io_input_ar_valid (io_input_ar_valid ), //i + .io_input_ar_ready (readOnly_io_input_ar_ready ), //o + .io_input_ar_payload_addr (io_input_ar_payload_addr[31:0] ), //i + .io_input_ar_payload_id (io_input_ar_payload_id[7:0] ), //i + .io_input_ar_payload_region (io_input_ar_payload_region[3:0] ), //i + .io_input_ar_payload_len (io_input_ar_payload_len[7:0] ), //i + .io_input_ar_payload_size (io_input_ar_payload_size[2:0] ), //i + .io_input_ar_payload_burst (io_input_ar_payload_burst[1:0] ), //i + .io_input_ar_payload_lock (io_input_ar_payload_lock ), //i + .io_input_ar_payload_cache (io_input_ar_payload_cache[3:0] ), //i + .io_input_ar_payload_qos (io_input_ar_payload_qos[3:0] ), //i + .io_input_ar_payload_prot (io_input_ar_payload_prot[2:0] ), //i + .io_input_r_valid (readOnly_io_input_r_valid ), //o + .io_input_r_ready (io_input_r_ready ), //i + .io_input_r_payload_data (readOnly_io_input_r_payload_data[31:0] ), //o + .io_input_r_payload_id (readOnly_io_input_r_payload_id[7:0] ), //o + .io_input_r_payload_resp (readOnly_io_input_r_payload_resp[1:0] ), //o + .io_input_r_payload_last (readOnly_io_input_r_payload_last ), //o + .io_output_ar_valid (readOnly_io_output_ar_valid ), //o + .io_output_ar_ready (io_output_ar_ready ), //i + .io_output_ar_payload_addr (readOnly_io_output_ar_payload_addr[31:0] ), //o + .io_output_ar_payload_id (readOnly_io_output_ar_payload_id[7:0] ), //o + .io_output_ar_payload_region (readOnly_io_output_ar_payload_region[3:0]), //o + .io_output_ar_payload_len (readOnly_io_output_ar_payload_len[7:0] ), //o + .io_output_ar_payload_size (readOnly_io_output_ar_payload_size[2:0] ), //o + .io_output_ar_payload_burst (readOnly_io_output_ar_payload_burst[1:0] ), //o + .io_output_ar_payload_lock (readOnly_io_output_ar_payload_lock ), //o + .io_output_ar_payload_cache (readOnly_io_output_ar_payload_cache[3:0] ), //o + .io_output_ar_payload_qos (readOnly_io_output_ar_payload_qos[3:0] ), //o + .io_output_ar_payload_prot (readOnly_io_output_ar_payload_prot[2:0] ), //o + .io_output_r_valid (io_output_r_valid ), //i + .io_output_r_ready (readOnly_io_output_r_ready ), //o + .io_output_r_payload_data (io_output_r_payload_data[511:0] ), //i + .io_output_r_payload_id (io_output_r_payload_id[7:0] ), //i + .io_output_r_payload_resp (io_output_r_payload_resp[1:0] ), //i + .io_output_r_payload_last (io_output_r_payload_last ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Asic32To512UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 writeOnly ( + .io_input_aw_valid (io_input_aw_valid ), //i + .io_input_aw_ready (writeOnly_io_input_aw_ready ), //o + .io_input_aw_payload_addr (io_input_aw_payload_addr[31:0] ), //i + .io_input_aw_payload_id (io_input_aw_payload_id[7:0] ), //i + .io_input_aw_payload_region (io_input_aw_payload_region[3:0] ), //i + .io_input_aw_payload_len (io_input_aw_payload_len[7:0] ), //i + .io_input_aw_payload_size (io_input_aw_payload_size[2:0] ), //i + .io_input_aw_payload_burst (io_input_aw_payload_burst[1:0] ), //i + .io_input_aw_payload_lock (io_input_aw_payload_lock ), //i + .io_input_aw_payload_cache (io_input_aw_payload_cache[3:0] ), //i + .io_input_aw_payload_qos (io_input_aw_payload_qos[3:0] ), //i + .io_input_aw_payload_prot (io_input_aw_payload_prot[2:0] ), //i + .io_input_w_valid (io_input_w_valid ), //i + .io_input_w_ready (writeOnly_io_input_w_ready ), //o + .io_input_w_payload_data (io_input_w_payload_data[31:0] ), //i + .io_input_w_payload_strb (io_input_w_payload_strb[3:0] ), //i + .io_input_w_payload_last (io_input_w_payload_last ), //i + .io_input_b_valid (writeOnly_io_input_b_valid ), //o + .io_input_b_ready (io_input_b_ready ), //i + .io_input_b_payload_id (writeOnly_io_input_b_payload_id[7:0] ), //o + .io_input_b_payload_resp (writeOnly_io_input_b_payload_resp[1:0] ), //o + .io_output_aw_valid (writeOnly_io_output_aw_valid ), //o + .io_output_aw_ready (io_output_aw_ready ), //i + .io_output_aw_payload_addr (writeOnly_io_output_aw_payload_addr[31:0] ), //o + .io_output_aw_payload_id (writeOnly_io_output_aw_payload_id[7:0] ), //o + .io_output_aw_payload_region (writeOnly_io_output_aw_payload_region[3:0]), //o + .io_output_aw_payload_len (writeOnly_io_output_aw_payload_len[7:0] ), //o + .io_output_aw_payload_size (writeOnly_io_output_aw_payload_size[2:0] ), //o + .io_output_aw_payload_burst (writeOnly_io_output_aw_payload_burst[1:0] ), //o + .io_output_aw_payload_lock (writeOnly_io_output_aw_payload_lock ), //o + .io_output_aw_payload_cache (writeOnly_io_output_aw_payload_cache[3:0] ), //o + .io_output_aw_payload_qos (writeOnly_io_output_aw_payload_qos[3:0] ), //o + .io_output_aw_payload_prot (writeOnly_io_output_aw_payload_prot[2:0] ), //o + .io_output_w_valid (writeOnly_io_output_w_valid ), //o + .io_output_w_ready (io_output_w_ready ), //i + .io_output_w_payload_data (writeOnly_io_output_w_payload_data[511:0] ), //o + .io_output_w_payload_strb (writeOnly_io_output_w_payload_strb[63:0] ), //o + .io_output_w_payload_last (writeOnly_io_output_w_payload_last ), //o + .io_output_b_valid (io_output_b_valid ), //i + .io_output_b_ready (writeOnly_io_output_b_ready ), //o + .io_output_b_payload_id (io_output_b_payload_id[7:0] ), //i + .io_output_b_payload_resp (io_output_b_payload_resp[1:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign io_input_ar_ready = readOnly_io_input_ar_ready; + assign io_input_r_valid = readOnly_io_input_r_valid; + assign io_input_r_payload_data = readOnly_io_input_r_payload_data; + assign io_input_r_payload_id = readOnly_io_input_r_payload_id; + assign io_input_r_payload_resp = readOnly_io_input_r_payload_resp; + assign io_input_r_payload_last = readOnly_io_input_r_payload_last; + assign io_input_aw_ready = writeOnly_io_input_aw_ready; + assign io_input_w_ready = writeOnly_io_input_w_ready; + assign io_input_b_valid = writeOnly_io_input_b_valid; + assign io_input_b_payload_id = writeOnly_io_input_b_payload_id; + assign io_input_b_payload_resp = writeOnly_io_input_b_payload_resp; + assign io_output_ar_valid = readOnly_io_output_ar_valid; + assign io_output_ar_payload_addr = readOnly_io_output_ar_payload_addr; + assign io_output_ar_payload_id = readOnly_io_output_ar_payload_id; + assign io_output_ar_payload_region = readOnly_io_output_ar_payload_region; + assign io_output_ar_payload_len = readOnly_io_output_ar_payload_len; + assign io_output_ar_payload_size = readOnly_io_output_ar_payload_size; + assign io_output_ar_payload_burst = readOnly_io_output_ar_payload_burst; + assign io_output_ar_payload_lock = readOnly_io_output_ar_payload_lock; + assign io_output_ar_payload_cache = readOnly_io_output_ar_payload_cache; + assign io_output_ar_payload_qos = readOnly_io_output_ar_payload_qos; + assign io_output_ar_payload_prot = readOnly_io_output_ar_payload_prot; + assign io_output_r_ready = readOnly_io_output_r_ready; + assign io_output_aw_valid = writeOnly_io_output_aw_valid; + assign io_output_aw_payload_addr = writeOnly_io_output_aw_payload_addr; + assign io_output_aw_payload_id = writeOnly_io_output_aw_payload_id; + assign io_output_aw_payload_region = writeOnly_io_output_aw_payload_region; + assign io_output_aw_payload_len = writeOnly_io_output_aw_payload_len; + assign io_output_aw_payload_size = writeOnly_io_output_aw_payload_size; + assign io_output_aw_payload_burst = writeOnly_io_output_aw_payload_burst; + assign io_output_aw_payload_lock = writeOnly_io_output_aw_payload_lock; + assign io_output_aw_payload_cache = writeOnly_io_output_aw_payload_cache; + assign io_output_aw_payload_qos = writeOnly_io_output_aw_payload_qos; + assign io_output_aw_payload_prot = writeOnly_io_output_aw_payload_prot; + assign io_output_w_valid = writeOnly_io_output_w_valid; + assign io_output_w_payload_data = writeOnly_io_output_w_payload_data; + assign io_output_w_payload_strb = writeOnly_io_output_w_payload_strb; + assign io_output_w_payload_last = writeOnly_io_output_w_payload_last; + assign io_output_b_ready = writeOnly_io_output_b_ready; + +endmodule + +module Asic32To512UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_aw_valid, + output reg io_input_aw_ready, + input [31:0] io_input_aw_payload_addr, + input [7:0] io_input_aw_payload_id, + input [3:0] io_input_aw_payload_region, + input [7:0] io_input_aw_payload_len, + input [2:0] io_input_aw_payload_size, + input [1:0] io_input_aw_payload_burst, + input [0:0] io_input_aw_payload_lock, + input [3:0] io_input_aw_payload_cache, + input [3:0] io_input_aw_payload_qos, + input [2:0] io_input_aw_payload_prot, + input io_input_w_valid, + output io_input_w_ready, + input [31:0] io_input_w_payload_data, + input [3:0] io_input_w_payload_strb, + input io_input_w_payload_last, + output io_input_b_valid, + input io_input_b_ready, + output [7:0] io_input_b_payload_id, + output [1:0] io_input_b_payload_resp, + output io_output_aw_valid, + input io_output_aw_ready, + output [31:0] io_output_aw_payload_addr, + output [7:0] io_output_aw_payload_id, + output [3:0] io_output_aw_payload_region, + output reg [7:0] io_output_aw_payload_len, + output reg [2:0] io_output_aw_payload_size, + output [1:0] io_output_aw_payload_burst, + output [0:0] io_output_aw_payload_lock, + output [3:0] io_output_aw_payload_cache, + output [3:0] io_output_aw_payload_qos, + output [2:0] io_output_aw_payload_prot, + output io_output_w_valid, + input io_output_w_ready, + output [511:0] io_output_w_payload_data, + output [63:0] io_output_w_payload_strb, + output io_output_w_payload_last, + input io_output_b_valid, + output io_output_b_ready, + input [7:0] io_output_b_payload_id, + input [1:0] io_output_b_payload_resp, + input clk, + input reset +); + + wire [14:0] _zz_cmdLogic_byteCount; + wire [10:0] _zz_cmdLogic_incrLen; + wire [10:0] _zz_cmdLogic_incrLen_1; + wire [5:0] _zz_cmdLogic_incrLen_2; + wire [6:0] _zz_dataLogic_byteCounterNext; + wire [7:0] _zz_dataLogic_byteCounterNext_1; + reg [63:0] _zz_dataLogic_byteActivity; + wire cmdLogic_outputFork_valid; + wire cmdLogic_outputFork_ready; + wire [31:0] cmdLogic_outputFork_payload_addr; + wire [7:0] cmdLogic_outputFork_payload_id; + wire [3:0] cmdLogic_outputFork_payload_region; + wire [7:0] cmdLogic_outputFork_payload_len; + wire [2:0] cmdLogic_outputFork_payload_size; + wire [1:0] cmdLogic_outputFork_payload_burst; + wire [0:0] cmdLogic_outputFork_payload_lock; + wire [3:0] cmdLogic_outputFork_payload_cache; + wire [3:0] cmdLogic_outputFork_payload_qos; + wire [2:0] cmdLogic_outputFork_payload_prot; + wire cmdLogic_dataFork_valid; + wire cmdLogic_dataFork_ready; + wire [31:0] cmdLogic_dataFork_payload_addr; + wire [7:0] cmdLogic_dataFork_payload_id; + wire [3:0] cmdLogic_dataFork_payload_region; + wire [7:0] cmdLogic_dataFork_payload_len; + wire [2:0] cmdLogic_dataFork_payload_size; + wire [1:0] cmdLogic_dataFork_payload_burst; + wire [0:0] cmdLogic_dataFork_payload_lock; + wire [3:0] cmdLogic_dataFork_payload_cache; + wire [3:0] cmdLogic_dataFork_payload_qos; + wire [2:0] cmdLogic_dataFork_payload_prot; + reg io_input_aw_fork2_logic_linkEnable_0; + reg io_input_aw_fork2_logic_linkEnable_1; + wire when_Stream_l993; + wire when_Stream_l993_1; + wire cmdLogic_outputFork_fire; + wire cmdLogic_dataFork_fire; + wire [9:0] cmdLogic_byteCount; + wire [4:0] cmdLogic_incrLen; + wire when_Axi4Upsizer_l21; + wire when_Axi4Upsizer_l24; + reg [5:0] dataLogic_byteCounter; + reg [2:0] dataLogic_size; + reg dataLogic_outputValid; + reg dataLogic_outputLast; + reg dataLogic_busy; + reg dataLogic_incrementByteCounter; + reg dataLogic_alwaysFire; + wire [6:0] dataLogic_byteCounterNext; + reg [511:0] dataLogic_dataBuffer; + reg [63:0] dataLogic_maskBuffer; + wire [63:0] dataLogic_byteActivity; + wire io_output_w_fire; + wire io_output_w_isStall; + wire io_input_w_fire; + wire when_Axi4Upsizer_l59; + wire when_Axi4Upsizer_l59_1; + wire when_Axi4Upsizer_l59_2; + wire when_Axi4Upsizer_l59_3; + wire when_Axi4Upsizer_l59_4; + wire when_Axi4Upsizer_l59_5; + wire when_Axi4Upsizer_l59_6; + wire when_Axi4Upsizer_l59_7; + wire when_Axi4Upsizer_l59_8; + wire when_Axi4Upsizer_l59_9; + wire when_Axi4Upsizer_l59_10; + wire when_Axi4Upsizer_l59_11; + wire when_Axi4Upsizer_l59_12; + wire when_Axi4Upsizer_l59_13; + wire when_Axi4Upsizer_l59_14; + wire when_Axi4Upsizer_l59_15; + wire when_Axi4Upsizer_l59_16; + wire when_Axi4Upsizer_l59_17; + wire when_Axi4Upsizer_l59_18; + wire when_Axi4Upsizer_l59_19; + wire when_Axi4Upsizer_l59_20; + wire when_Axi4Upsizer_l59_21; + wire when_Axi4Upsizer_l59_22; + wire when_Axi4Upsizer_l59_23; + wire when_Axi4Upsizer_l59_24; + wire when_Axi4Upsizer_l59_25; + wire when_Axi4Upsizer_l59_26; + wire when_Axi4Upsizer_l59_27; + wire when_Axi4Upsizer_l59_28; + wire when_Axi4Upsizer_l59_29; + wire when_Axi4Upsizer_l59_30; + wire when_Axi4Upsizer_l59_31; + wire when_Axi4Upsizer_l59_32; + wire when_Axi4Upsizer_l59_33; + wire when_Axi4Upsizer_l59_34; + wire when_Axi4Upsizer_l59_35; + wire when_Axi4Upsizer_l59_36; + wire when_Axi4Upsizer_l59_37; + wire when_Axi4Upsizer_l59_38; + wire when_Axi4Upsizer_l59_39; + wire when_Axi4Upsizer_l59_40; + wire when_Axi4Upsizer_l59_41; + wire when_Axi4Upsizer_l59_42; + wire when_Axi4Upsizer_l59_43; + wire when_Axi4Upsizer_l59_44; + wire when_Axi4Upsizer_l59_45; + wire when_Axi4Upsizer_l59_46; + wire when_Axi4Upsizer_l59_47; + wire when_Axi4Upsizer_l59_48; + wire when_Axi4Upsizer_l59_49; + wire when_Axi4Upsizer_l59_50; + wire when_Axi4Upsizer_l59_51; + wire when_Axi4Upsizer_l59_52; + wire when_Axi4Upsizer_l59_53; + wire when_Axi4Upsizer_l59_54; + wire when_Axi4Upsizer_l59_55; + wire when_Axi4Upsizer_l59_56; + wire when_Axi4Upsizer_l59_57; + wire when_Axi4Upsizer_l59_58; + wire when_Axi4Upsizer_l59_59; + wire when_Axi4Upsizer_l59_60; + wire when_Axi4Upsizer_l59_61; + wire when_Axi4Upsizer_l59_62; + wire when_Axi4Upsizer_l59_63; + wire cmdLogic_dataFork_fire_1; + wire when_Axi4Upsizer_l68; + wire when_Axi4Upsizer_l68_1; + wire when_Axi4Upsizer_l68_2; + wire when_Axi4Upsizer_l68_3; + wire when_Axi4Upsizer_l68_4; + wire when_Axi4Upsizer_l68_5; + + assign _zz_cmdLogic_byteCount = ({7'd0,io_input_aw_payload_len} <<< io_input_aw_payload_size); + assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); + assign _zz_cmdLogic_incrLen_2 = io_input_aw_payload_addr[5 : 0]; + assign _zz_cmdLogic_incrLen_1 = {5'd0, _zz_cmdLogic_incrLen_2}; + assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); + assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[6:0]; + always @(*) begin + case(dataLogic_size) + 3'b000 : _zz_dataLogic_byteActivity = 64'h0000000000000001; + 3'b001 : _zz_dataLogic_byteActivity = 64'h0000000000000003; + 3'b010 : _zz_dataLogic_byteActivity = 64'h000000000000000f; + 3'b011 : _zz_dataLogic_byteActivity = 64'h00000000000000ff; + 3'b100 : _zz_dataLogic_byteActivity = 64'h000000000000ffff; + default : _zz_dataLogic_byteActivity = 64'h00000000ffffffff; + endcase + end + + always @(*) begin + io_input_aw_ready = 1'b1; + if(when_Stream_l993) begin + io_input_aw_ready = 1'b0; + end + if(when_Stream_l993_1) begin + io_input_aw_ready = 1'b0; + end + end + + assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_aw_fork2_logic_linkEnable_0); + assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_aw_fork2_logic_linkEnable_1); + assign cmdLogic_outputFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_0); + assign cmdLogic_outputFork_payload_addr = io_input_aw_payload_addr; + assign cmdLogic_outputFork_payload_id = io_input_aw_payload_id; + assign cmdLogic_outputFork_payload_region = io_input_aw_payload_region; + assign cmdLogic_outputFork_payload_len = io_input_aw_payload_len; + assign cmdLogic_outputFork_payload_size = io_input_aw_payload_size; + assign cmdLogic_outputFork_payload_burst = io_input_aw_payload_burst; + assign cmdLogic_outputFork_payload_lock = io_input_aw_payload_lock; + assign cmdLogic_outputFork_payload_cache = io_input_aw_payload_cache; + assign cmdLogic_outputFork_payload_qos = io_input_aw_payload_qos; + assign cmdLogic_outputFork_payload_prot = io_input_aw_payload_prot; + assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); + assign cmdLogic_dataFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_1); + assign cmdLogic_dataFork_payload_addr = io_input_aw_payload_addr; + assign cmdLogic_dataFork_payload_id = io_input_aw_payload_id; + assign cmdLogic_dataFork_payload_region = io_input_aw_payload_region; + assign cmdLogic_dataFork_payload_len = io_input_aw_payload_len; + assign cmdLogic_dataFork_payload_size = io_input_aw_payload_size; + assign cmdLogic_dataFork_payload_burst = io_input_aw_payload_burst; + assign cmdLogic_dataFork_payload_lock = io_input_aw_payload_lock; + assign cmdLogic_dataFork_payload_cache = io_input_aw_payload_cache; + assign cmdLogic_dataFork_payload_qos = io_input_aw_payload_qos; + assign cmdLogic_dataFork_payload_prot = io_input_aw_payload_prot; + assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign io_output_aw_valid = cmdLogic_outputFork_valid; + assign cmdLogic_outputFork_ready = io_output_aw_ready; + assign io_output_aw_payload_addr = cmdLogic_outputFork_payload_addr; + assign io_output_aw_payload_id = cmdLogic_outputFork_payload_id; + assign io_output_aw_payload_region = cmdLogic_outputFork_payload_region; + always @(*) begin + io_output_aw_payload_len = cmdLogic_outputFork_payload_len; + if(when_Axi4Upsizer_l21) begin + io_output_aw_payload_len = {3'd0, cmdLogic_incrLen}; + end + end + + always @(*) begin + io_output_aw_payload_size = cmdLogic_outputFork_payload_size; + if(when_Axi4Upsizer_l21) begin + io_output_aw_payload_size = 3'b110; + if(when_Axi4Upsizer_l24) begin + io_output_aw_payload_size = io_input_aw_payload_size; + end + end + end + + assign io_output_aw_payload_burst = cmdLogic_outputFork_payload_burst; + assign io_output_aw_payload_lock = cmdLogic_outputFork_payload_lock; + assign io_output_aw_payload_cache = cmdLogic_outputFork_payload_cache; + assign io_output_aw_payload_qos = cmdLogic_outputFork_payload_qos; + assign io_output_aw_payload_prot = cmdLogic_outputFork_payload_prot; + assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; + assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 6]; + assign when_Axi4Upsizer_l21 = (io_output_aw_payload_burst == 2'b01); + assign when_Axi4Upsizer_l24 = (io_input_aw_payload_len == 8'h00); + assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); + assign dataLogic_byteActivity = (_zz_dataLogic_byteActivity <<< dataLogic_byteCounter); + assign io_output_w_fire = (io_output_w_valid && io_output_w_ready); + assign io_output_w_valid = dataLogic_outputValid; + assign io_output_w_isStall = (io_output_w_valid && (! io_output_w_ready)); + assign io_input_w_ready = (dataLogic_busy && (! io_output_w_isStall)); + assign io_output_w_payload_data = dataLogic_dataBuffer; + assign io_output_w_payload_strb = dataLogic_maskBuffer; + assign io_output_w_payload_last = dataLogic_outputLast; + assign io_input_w_fire = (io_input_w_valid && io_input_w_ready); + assign when_Axi4Upsizer_l59 = dataLogic_byteActivity[0]; + assign when_Axi4Upsizer_l59_1 = dataLogic_byteActivity[1]; + assign when_Axi4Upsizer_l59_2 = dataLogic_byteActivity[2]; + assign when_Axi4Upsizer_l59_3 = dataLogic_byteActivity[3]; + assign when_Axi4Upsizer_l59_4 = dataLogic_byteActivity[4]; + assign when_Axi4Upsizer_l59_5 = dataLogic_byteActivity[5]; + assign when_Axi4Upsizer_l59_6 = dataLogic_byteActivity[6]; + assign when_Axi4Upsizer_l59_7 = dataLogic_byteActivity[7]; + assign when_Axi4Upsizer_l59_8 = dataLogic_byteActivity[8]; + assign when_Axi4Upsizer_l59_9 = dataLogic_byteActivity[9]; + assign when_Axi4Upsizer_l59_10 = dataLogic_byteActivity[10]; + assign when_Axi4Upsizer_l59_11 = dataLogic_byteActivity[11]; + assign when_Axi4Upsizer_l59_12 = dataLogic_byteActivity[12]; + assign when_Axi4Upsizer_l59_13 = dataLogic_byteActivity[13]; + assign when_Axi4Upsizer_l59_14 = dataLogic_byteActivity[14]; + assign when_Axi4Upsizer_l59_15 = dataLogic_byteActivity[15]; + assign when_Axi4Upsizer_l59_16 = dataLogic_byteActivity[16]; + assign when_Axi4Upsizer_l59_17 = dataLogic_byteActivity[17]; + assign when_Axi4Upsizer_l59_18 = dataLogic_byteActivity[18]; + assign when_Axi4Upsizer_l59_19 = dataLogic_byteActivity[19]; + assign when_Axi4Upsizer_l59_20 = dataLogic_byteActivity[20]; + assign when_Axi4Upsizer_l59_21 = dataLogic_byteActivity[21]; + assign when_Axi4Upsizer_l59_22 = dataLogic_byteActivity[22]; + assign when_Axi4Upsizer_l59_23 = dataLogic_byteActivity[23]; + assign when_Axi4Upsizer_l59_24 = dataLogic_byteActivity[24]; + assign when_Axi4Upsizer_l59_25 = dataLogic_byteActivity[25]; + assign when_Axi4Upsizer_l59_26 = dataLogic_byteActivity[26]; + assign when_Axi4Upsizer_l59_27 = dataLogic_byteActivity[27]; + assign when_Axi4Upsizer_l59_28 = dataLogic_byteActivity[28]; + assign when_Axi4Upsizer_l59_29 = dataLogic_byteActivity[29]; + assign when_Axi4Upsizer_l59_30 = dataLogic_byteActivity[30]; + assign when_Axi4Upsizer_l59_31 = dataLogic_byteActivity[31]; + assign when_Axi4Upsizer_l59_32 = dataLogic_byteActivity[32]; + assign when_Axi4Upsizer_l59_33 = dataLogic_byteActivity[33]; + assign when_Axi4Upsizer_l59_34 = dataLogic_byteActivity[34]; + assign when_Axi4Upsizer_l59_35 = dataLogic_byteActivity[35]; + assign when_Axi4Upsizer_l59_36 = dataLogic_byteActivity[36]; + assign when_Axi4Upsizer_l59_37 = dataLogic_byteActivity[37]; + assign when_Axi4Upsizer_l59_38 = dataLogic_byteActivity[38]; + assign when_Axi4Upsizer_l59_39 = dataLogic_byteActivity[39]; + assign when_Axi4Upsizer_l59_40 = dataLogic_byteActivity[40]; + assign when_Axi4Upsizer_l59_41 = dataLogic_byteActivity[41]; + assign when_Axi4Upsizer_l59_42 = dataLogic_byteActivity[42]; + assign when_Axi4Upsizer_l59_43 = dataLogic_byteActivity[43]; + assign when_Axi4Upsizer_l59_44 = dataLogic_byteActivity[44]; + assign when_Axi4Upsizer_l59_45 = dataLogic_byteActivity[45]; + assign when_Axi4Upsizer_l59_46 = dataLogic_byteActivity[46]; + assign when_Axi4Upsizer_l59_47 = dataLogic_byteActivity[47]; + assign when_Axi4Upsizer_l59_48 = dataLogic_byteActivity[48]; + assign when_Axi4Upsizer_l59_49 = dataLogic_byteActivity[49]; + assign when_Axi4Upsizer_l59_50 = dataLogic_byteActivity[50]; + assign when_Axi4Upsizer_l59_51 = dataLogic_byteActivity[51]; + assign when_Axi4Upsizer_l59_52 = dataLogic_byteActivity[52]; + assign when_Axi4Upsizer_l59_53 = dataLogic_byteActivity[53]; + assign when_Axi4Upsizer_l59_54 = dataLogic_byteActivity[54]; + assign when_Axi4Upsizer_l59_55 = dataLogic_byteActivity[55]; + assign when_Axi4Upsizer_l59_56 = dataLogic_byteActivity[56]; + assign when_Axi4Upsizer_l59_57 = dataLogic_byteActivity[57]; + assign when_Axi4Upsizer_l59_58 = dataLogic_byteActivity[58]; + assign when_Axi4Upsizer_l59_59 = dataLogic_byteActivity[59]; + assign when_Axi4Upsizer_l59_60 = dataLogic_byteActivity[60]; + assign when_Axi4Upsizer_l59_61 = dataLogic_byteActivity[61]; + assign when_Axi4Upsizer_l59_62 = dataLogic_byteActivity[62]; + assign when_Axi4Upsizer_l59_63 = dataLogic_byteActivity[63]; + assign cmdLogic_dataFork_fire_1 = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign when_Axi4Upsizer_l68 = (3'b000 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_1 = (3'b001 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_2 = (3'b010 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_3 = (3'b011 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_4 = (3'b100 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_5 = (3'b101 < cmdLogic_dataFork_payload_size); + assign cmdLogic_dataFork_ready = (! dataLogic_busy); + assign io_input_b_valid = io_output_b_valid; + assign io_output_b_ready = io_input_b_ready; + assign io_input_b_payload_id = io_output_b_payload_id; + assign io_input_b_payload_resp = io_output_b_payload_resp; + always @(posedge clk or posedge reset) begin + if(reset) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; + io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; + dataLogic_outputValid <= 1'b0; + dataLogic_busy <= 1'b0; + dataLogic_maskBuffer <= 64'h0000000000000000; + end else begin + if(cmdLogic_outputFork_fire) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdLogic_dataFork_fire) begin + io_input_aw_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_aw_ready) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; + io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; + end + if(io_output_w_ready) begin + dataLogic_outputValid <= 1'b0; + end + if(io_output_w_fire) begin + dataLogic_maskBuffer <= 64'h0000000000000000; + end + if(io_input_w_fire) begin + dataLogic_outputValid <= ((dataLogic_byteCounterNext[6] || io_input_w_payload_last) || dataLogic_alwaysFire); + if(io_input_w_payload_last) begin + dataLogic_busy <= 1'b0; + end + if(when_Axi4Upsizer_l59) begin + dataLogic_maskBuffer[0] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_1) begin + dataLogic_maskBuffer[1] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_2) begin + dataLogic_maskBuffer[2] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_3) begin + dataLogic_maskBuffer[3] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_4) begin + dataLogic_maskBuffer[4] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_5) begin + dataLogic_maskBuffer[5] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_6) begin + dataLogic_maskBuffer[6] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_7) begin + dataLogic_maskBuffer[7] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_8) begin + dataLogic_maskBuffer[8] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_9) begin + dataLogic_maskBuffer[9] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_10) begin + dataLogic_maskBuffer[10] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_11) begin + dataLogic_maskBuffer[11] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_12) begin + dataLogic_maskBuffer[12] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_13) begin + dataLogic_maskBuffer[13] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_14) begin + dataLogic_maskBuffer[14] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_15) begin + dataLogic_maskBuffer[15] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_16) begin + dataLogic_maskBuffer[16] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_17) begin + dataLogic_maskBuffer[17] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_18) begin + dataLogic_maskBuffer[18] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_19) begin + dataLogic_maskBuffer[19] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_20) begin + dataLogic_maskBuffer[20] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_21) begin + dataLogic_maskBuffer[21] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_22) begin + dataLogic_maskBuffer[22] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_23) begin + dataLogic_maskBuffer[23] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_24) begin + dataLogic_maskBuffer[24] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_25) begin + dataLogic_maskBuffer[25] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_26) begin + dataLogic_maskBuffer[26] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_27) begin + dataLogic_maskBuffer[27] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_28) begin + dataLogic_maskBuffer[28] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_29) begin + dataLogic_maskBuffer[29] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_30) begin + dataLogic_maskBuffer[30] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_31) begin + dataLogic_maskBuffer[31] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_32) begin + dataLogic_maskBuffer[32] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_33) begin + dataLogic_maskBuffer[33] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_34) begin + dataLogic_maskBuffer[34] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_35) begin + dataLogic_maskBuffer[35] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_36) begin + dataLogic_maskBuffer[36] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_37) begin + dataLogic_maskBuffer[37] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_38) begin + dataLogic_maskBuffer[38] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_39) begin + dataLogic_maskBuffer[39] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_40) begin + dataLogic_maskBuffer[40] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_41) begin + dataLogic_maskBuffer[41] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_42) begin + dataLogic_maskBuffer[42] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_43) begin + dataLogic_maskBuffer[43] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_44) begin + dataLogic_maskBuffer[44] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_45) begin + dataLogic_maskBuffer[45] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_46) begin + dataLogic_maskBuffer[46] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_47) begin + dataLogic_maskBuffer[47] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_48) begin + dataLogic_maskBuffer[48] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_49) begin + dataLogic_maskBuffer[49] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_50) begin + dataLogic_maskBuffer[50] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_51) begin + dataLogic_maskBuffer[51] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_52) begin + dataLogic_maskBuffer[52] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_53) begin + dataLogic_maskBuffer[53] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_54) begin + dataLogic_maskBuffer[54] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_55) begin + dataLogic_maskBuffer[55] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_56) begin + dataLogic_maskBuffer[56] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_57) begin + dataLogic_maskBuffer[57] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_58) begin + dataLogic_maskBuffer[58] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_59) begin + dataLogic_maskBuffer[59] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_60) begin + dataLogic_maskBuffer[60] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_61) begin + dataLogic_maskBuffer[61] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_62) begin + dataLogic_maskBuffer[62] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_63) begin + dataLogic_maskBuffer[63] <= io_input_w_payload_strb[3]; + end + end + if(cmdLogic_dataFork_fire_1) begin + dataLogic_busy <= 1'b1; + end + end + end + + always @(posedge clk) begin + if(io_input_w_fire) begin + if(dataLogic_incrementByteCounter) begin + dataLogic_byteCounter <= dataLogic_byteCounterNext[5:0]; + end + dataLogic_outputLast <= io_input_w_payload_last; + if(when_Axi4Upsizer_l59) begin + dataLogic_dataBuffer[7 : 0] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_1) begin + dataLogic_dataBuffer[15 : 8] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_2) begin + dataLogic_dataBuffer[23 : 16] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_3) begin + dataLogic_dataBuffer[31 : 24] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_4) begin + dataLogic_dataBuffer[39 : 32] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_5) begin + dataLogic_dataBuffer[47 : 40] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_6) begin + dataLogic_dataBuffer[55 : 48] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_7) begin + dataLogic_dataBuffer[63 : 56] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_8) begin + dataLogic_dataBuffer[71 : 64] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_9) begin + dataLogic_dataBuffer[79 : 72] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_10) begin + dataLogic_dataBuffer[87 : 80] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_11) begin + dataLogic_dataBuffer[95 : 88] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_12) begin + dataLogic_dataBuffer[103 : 96] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_13) begin + dataLogic_dataBuffer[111 : 104] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_14) begin + dataLogic_dataBuffer[119 : 112] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_15) begin + dataLogic_dataBuffer[127 : 120] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_16) begin + dataLogic_dataBuffer[135 : 128] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_17) begin + dataLogic_dataBuffer[143 : 136] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_18) begin + dataLogic_dataBuffer[151 : 144] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_19) begin + dataLogic_dataBuffer[159 : 152] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_20) begin + dataLogic_dataBuffer[167 : 160] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_21) begin + dataLogic_dataBuffer[175 : 168] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_22) begin + dataLogic_dataBuffer[183 : 176] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_23) begin + dataLogic_dataBuffer[191 : 184] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_24) begin + dataLogic_dataBuffer[199 : 192] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_25) begin + dataLogic_dataBuffer[207 : 200] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_26) begin + dataLogic_dataBuffer[215 : 208] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_27) begin + dataLogic_dataBuffer[223 : 216] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_28) begin + dataLogic_dataBuffer[231 : 224] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_29) begin + dataLogic_dataBuffer[239 : 232] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_30) begin + dataLogic_dataBuffer[247 : 240] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_31) begin + dataLogic_dataBuffer[255 : 248] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_32) begin + dataLogic_dataBuffer[263 : 256] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_33) begin + dataLogic_dataBuffer[271 : 264] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_34) begin + dataLogic_dataBuffer[279 : 272] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_35) begin + dataLogic_dataBuffer[287 : 280] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_36) begin + dataLogic_dataBuffer[295 : 288] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_37) begin + dataLogic_dataBuffer[303 : 296] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_38) begin + dataLogic_dataBuffer[311 : 304] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_39) begin + dataLogic_dataBuffer[319 : 312] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_40) begin + dataLogic_dataBuffer[327 : 320] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_41) begin + dataLogic_dataBuffer[335 : 328] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_42) begin + dataLogic_dataBuffer[343 : 336] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_43) begin + dataLogic_dataBuffer[351 : 344] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_44) begin + dataLogic_dataBuffer[359 : 352] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_45) begin + dataLogic_dataBuffer[367 : 360] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_46) begin + dataLogic_dataBuffer[375 : 368] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_47) begin + dataLogic_dataBuffer[383 : 376] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_48) begin + dataLogic_dataBuffer[391 : 384] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_49) begin + dataLogic_dataBuffer[399 : 392] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_50) begin + dataLogic_dataBuffer[407 : 400] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_51) begin + dataLogic_dataBuffer[415 : 408] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_52) begin + dataLogic_dataBuffer[423 : 416] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_53) begin + dataLogic_dataBuffer[431 : 424] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_54) begin + dataLogic_dataBuffer[439 : 432] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_55) begin + dataLogic_dataBuffer[447 : 440] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_56) begin + dataLogic_dataBuffer[455 : 448] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_57) begin + dataLogic_dataBuffer[463 : 456] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_58) begin + dataLogic_dataBuffer[471 : 464] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_59) begin + dataLogic_dataBuffer[479 : 472] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_60) begin + dataLogic_dataBuffer[487 : 480] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_61) begin + dataLogic_dataBuffer[495 : 488] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_62) begin + dataLogic_dataBuffer[503 : 496] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_63) begin + dataLogic_dataBuffer[511 : 504] <= io_input_w_payload_data[31 : 24]; + end + end + if(cmdLogic_dataFork_fire_1) begin + dataLogic_byteCounter <= cmdLogic_dataFork_payload_addr[5:0]; + if(when_Axi4Upsizer_l68) begin + dataLogic_byteCounter[0] <= 1'b0; + end + if(when_Axi4Upsizer_l68_1) begin + dataLogic_byteCounter[1] <= 1'b0; + end + if(when_Axi4Upsizer_l68_2) begin + dataLogic_byteCounter[2] <= 1'b0; + end + if(when_Axi4Upsizer_l68_3) begin + dataLogic_byteCounter[3] <= 1'b0; + end + if(when_Axi4Upsizer_l68_4) begin + dataLogic_byteCounter[4] <= 1'b0; + end + if(when_Axi4Upsizer_l68_5) begin + dataLogic_byteCounter[5] <= 1'b0; + end + dataLogic_size <= cmdLogic_dataFork_payload_size; + dataLogic_alwaysFire <= (! (cmdLogic_dataFork_payload_burst == 2'b01)); + dataLogic_incrementByteCounter <= (! (cmdLogic_dataFork_payload_burst == 2'b00)); + end + end + + +endmodule + +module Asic32To512UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_ar_valid, + output reg io_input_ar_ready, + input [31:0] io_input_ar_payload_addr, + input [7:0] io_input_ar_payload_id, + input [3:0] io_input_ar_payload_region, + input [7:0] io_input_ar_payload_len, + input [2:0] io_input_ar_payload_size, + input [1:0] io_input_ar_payload_burst, + input [0:0] io_input_ar_payload_lock, + input [3:0] io_input_ar_payload_cache, + input [3:0] io_input_ar_payload_qos, + input [2:0] io_input_ar_payload_prot, + output io_input_r_valid, + input io_input_r_ready, + output [31:0] io_input_r_payload_data, + output [7:0] io_input_r_payload_id, + output [1:0] io_input_r_payload_resp, + output io_input_r_payload_last, + output io_output_ar_valid, + input io_output_ar_ready, + output [31:0] io_output_ar_payload_addr, + output [7:0] io_output_ar_payload_id, + output [3:0] io_output_ar_payload_region, + output [7:0] io_output_ar_payload_len, + output reg [2:0] io_output_ar_payload_size, + output [1:0] io_output_ar_payload_burst, + output [0:0] io_output_ar_payload_lock, + output [3:0] io_output_ar_payload_cache, + output [3:0] io_output_ar_payload_qos, + output [2:0] io_output_ar_payload_prot, + input io_output_r_valid, + output io_output_r_ready, + input [511:0] io_output_r_payload_data, + input [7:0] io_output_r_payload_id, + input [1:0] io_output_r_payload_resp, + input io_output_r_payload_last, + input clk, + input reset +); + + wire dataLogic_cmdPush_fifo_io_pop_ready; + wire dataLogic_cmdPush_fifo_io_push_ready; + wire dataLogic_cmdPush_fifo_io_pop_valid; + wire [5:0] dataLogic_cmdPush_fifo_io_pop_payload_startAt; + wire [5:0] dataLogic_cmdPush_fifo_io_pop_payload_endAt; + wire [2:0] dataLogic_cmdPush_fifo_io_pop_payload_size; + wire [7:0] dataLogic_cmdPush_fifo_io_pop_payload_id; + wire [4:0] dataLogic_cmdPush_fifo_io_occupancy; + wire [4:0] dataLogic_cmdPush_fifo_io_availability; + wire [14:0] _zz_cmdLogic_byteCount; + wire [10:0] _zz_cmdLogic_incrLen; + wire [10:0] _zz_cmdLogic_incrLen_1; + wire [5:0] _zz_cmdLogic_incrLen_2; + wire [31:0] _zz_dataLogic_cmdPush_payload_endAt; + wire [31:0] _zz_dataLogic_cmdPush_payload_endAt_1; + wire [14:0] _zz_dataLogic_cmdPush_payload_endAt_2; + wire [6:0] _zz_dataLogic_byteCounterNext; + wire [7:0] _zz_dataLogic_byteCounterNext_1; + reg [31:0] _zz_io_input_r_payload_data; + wire [3:0] _zz_io_input_r_payload_data_1; + wire cmdLogic_outputFork_valid; + wire cmdLogic_outputFork_ready; + wire [31:0] cmdLogic_outputFork_payload_addr; + wire [7:0] cmdLogic_outputFork_payload_id; + wire [3:0] cmdLogic_outputFork_payload_region; + wire [7:0] cmdLogic_outputFork_payload_len; + wire [2:0] cmdLogic_outputFork_payload_size; + wire [1:0] cmdLogic_outputFork_payload_burst; + wire [0:0] cmdLogic_outputFork_payload_lock; + wire [3:0] cmdLogic_outputFork_payload_cache; + wire [3:0] cmdLogic_outputFork_payload_qos; + wire [2:0] cmdLogic_outputFork_payload_prot; + wire cmdLogic_dataFork_valid; + wire cmdLogic_dataFork_ready; + wire [31:0] cmdLogic_dataFork_payload_addr; + wire [7:0] cmdLogic_dataFork_payload_id; + wire [3:0] cmdLogic_dataFork_payload_region; + wire [7:0] cmdLogic_dataFork_payload_len; + wire [2:0] cmdLogic_dataFork_payload_size; + wire [1:0] cmdLogic_dataFork_payload_burst; + wire [0:0] cmdLogic_dataFork_payload_lock; + wire [3:0] cmdLogic_dataFork_payload_cache; + wire [3:0] cmdLogic_dataFork_payload_qos; + wire [2:0] cmdLogic_dataFork_payload_prot; + reg io_input_ar_fork2_logic_linkEnable_0; + reg io_input_ar_fork2_logic_linkEnable_1; + wire when_Stream_l993; + wire when_Stream_l993_1; + wire cmdLogic_outputFork_fire; + wire cmdLogic_dataFork_fire; + wire [9:0] cmdLogic_byteCount; + wire [4:0] cmdLogic_incrLen; + wire when_Axi4Upsizer_l108; + wire dataLogic_cmdPush_valid; + wire dataLogic_cmdPush_ready; + wire [5:0] dataLogic_cmdPush_payload_startAt; + wire [5:0] dataLogic_cmdPush_payload_endAt; + wire [2:0] dataLogic_cmdPush_payload_size; + wire [7:0] dataLogic_cmdPush_payload_id; + reg [2:0] dataLogic_size; + reg dataLogic_busy; + reg [7:0] dataLogic_id; + reg [5:0] dataLogic_byteCounter; + reg [5:0] dataLogic_byteCounterLast; + wire [6:0] dataLogic_byteCounterNext; + wire readOnly_dataLogic_cmdPush_fifo_io_pop_fire; + wire io_input_r_fire; + + assign _zz_cmdLogic_byteCount = ({7'd0,io_input_ar_payload_len} <<< io_input_ar_payload_size); + assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); + assign _zz_cmdLogic_incrLen_2 = io_input_ar_payload_addr[5 : 0]; + assign _zz_cmdLogic_incrLen_1 = {5'd0, _zz_cmdLogic_incrLen_2}; + assign _zz_dataLogic_cmdPush_payload_endAt = (cmdLogic_dataFork_payload_addr + _zz_dataLogic_cmdPush_payload_endAt_1); + assign _zz_dataLogic_cmdPush_payload_endAt_2 = ({7'd0,cmdLogic_dataFork_payload_len} <<< cmdLogic_dataFork_payload_size); + assign _zz_dataLogic_cmdPush_payload_endAt_1 = {17'd0, _zz_dataLogic_cmdPush_payload_endAt_2}; + assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); + assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[6:0]; + assign _zz_io_input_r_payload_data_1 = (dataLogic_byteCounter >>> 2'd2); + Asic32To512UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 dataLogic_cmdPush_fifo ( + .io_push_valid (dataLogic_cmdPush_valid ), //i + .io_push_ready (dataLogic_cmdPush_fifo_io_push_ready ), //o + .io_push_payload_startAt (dataLogic_cmdPush_payload_startAt[5:0] ), //i + .io_push_payload_endAt (dataLogic_cmdPush_payload_endAt[5:0] ), //i + .io_push_payload_size (dataLogic_cmdPush_payload_size[2:0] ), //i + .io_push_payload_id (dataLogic_cmdPush_payload_id[7:0] ), //i + .io_pop_valid (dataLogic_cmdPush_fifo_io_pop_valid ), //o + .io_pop_ready (dataLogic_cmdPush_fifo_io_pop_ready ), //i + .io_pop_payload_startAt (dataLogic_cmdPush_fifo_io_pop_payload_startAt[5:0]), //o + .io_pop_payload_endAt (dataLogic_cmdPush_fifo_io_pop_payload_endAt[5:0] ), //o + .io_pop_payload_size (dataLogic_cmdPush_fifo_io_pop_payload_size[2:0] ), //o + .io_pop_payload_id (dataLogic_cmdPush_fifo_io_pop_payload_id[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (dataLogic_cmdPush_fifo_io_occupancy[4:0] ), //o + .io_availability (dataLogic_cmdPush_fifo_io_availability[4:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_io_input_r_payload_data_1) + 4'b0000 : _zz_io_input_r_payload_data = io_output_r_payload_data[31 : 0]; + 4'b0001 : _zz_io_input_r_payload_data = io_output_r_payload_data[63 : 32]; + 4'b0010 : _zz_io_input_r_payload_data = io_output_r_payload_data[95 : 64]; + 4'b0011 : _zz_io_input_r_payload_data = io_output_r_payload_data[127 : 96]; + 4'b0100 : _zz_io_input_r_payload_data = io_output_r_payload_data[159 : 128]; + 4'b0101 : _zz_io_input_r_payload_data = io_output_r_payload_data[191 : 160]; + 4'b0110 : _zz_io_input_r_payload_data = io_output_r_payload_data[223 : 192]; + 4'b0111 : _zz_io_input_r_payload_data = io_output_r_payload_data[255 : 224]; + 4'b1000 : _zz_io_input_r_payload_data = io_output_r_payload_data[287 : 256]; + 4'b1001 : _zz_io_input_r_payload_data = io_output_r_payload_data[319 : 288]; + 4'b1010 : _zz_io_input_r_payload_data = io_output_r_payload_data[351 : 320]; + 4'b1011 : _zz_io_input_r_payload_data = io_output_r_payload_data[383 : 352]; + 4'b1100 : _zz_io_input_r_payload_data = io_output_r_payload_data[415 : 384]; + 4'b1101 : _zz_io_input_r_payload_data = io_output_r_payload_data[447 : 416]; + 4'b1110 : _zz_io_input_r_payload_data = io_output_r_payload_data[479 : 448]; + default : _zz_io_input_r_payload_data = io_output_r_payload_data[511 : 480]; + endcase + end + + always @(*) begin + io_input_ar_ready = 1'b1; + if(when_Stream_l993) begin + io_input_ar_ready = 1'b0; + end + if(when_Stream_l993_1) begin + io_input_ar_ready = 1'b0; + end + end + + assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_ar_fork2_logic_linkEnable_0); + assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_ar_fork2_logic_linkEnable_1); + assign cmdLogic_outputFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_0); + assign cmdLogic_outputFork_payload_addr = io_input_ar_payload_addr; + assign cmdLogic_outputFork_payload_id = io_input_ar_payload_id; + assign cmdLogic_outputFork_payload_region = io_input_ar_payload_region; + assign cmdLogic_outputFork_payload_len = io_input_ar_payload_len; + assign cmdLogic_outputFork_payload_size = io_input_ar_payload_size; + assign cmdLogic_outputFork_payload_burst = io_input_ar_payload_burst; + assign cmdLogic_outputFork_payload_lock = io_input_ar_payload_lock; + assign cmdLogic_outputFork_payload_cache = io_input_ar_payload_cache; + assign cmdLogic_outputFork_payload_qos = io_input_ar_payload_qos; + assign cmdLogic_outputFork_payload_prot = io_input_ar_payload_prot; + assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); + assign cmdLogic_dataFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_1); + assign cmdLogic_dataFork_payload_addr = io_input_ar_payload_addr; + assign cmdLogic_dataFork_payload_id = io_input_ar_payload_id; + assign cmdLogic_dataFork_payload_region = io_input_ar_payload_region; + assign cmdLogic_dataFork_payload_len = io_input_ar_payload_len; + assign cmdLogic_dataFork_payload_size = io_input_ar_payload_size; + assign cmdLogic_dataFork_payload_burst = io_input_ar_payload_burst; + assign cmdLogic_dataFork_payload_lock = io_input_ar_payload_lock; + assign cmdLogic_dataFork_payload_cache = io_input_ar_payload_cache; + assign cmdLogic_dataFork_payload_qos = io_input_ar_payload_qos; + assign cmdLogic_dataFork_payload_prot = io_input_ar_payload_prot; + assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign io_output_ar_valid = cmdLogic_outputFork_valid; + assign cmdLogic_outputFork_ready = io_output_ar_ready; + assign io_output_ar_payload_addr = cmdLogic_outputFork_payload_addr; + assign io_output_ar_payload_region = cmdLogic_outputFork_payload_region; + assign io_output_ar_payload_burst = cmdLogic_outputFork_payload_burst; + assign io_output_ar_payload_lock = cmdLogic_outputFork_payload_lock; + assign io_output_ar_payload_cache = cmdLogic_outputFork_payload_cache; + assign io_output_ar_payload_qos = cmdLogic_outputFork_payload_qos; + assign io_output_ar_payload_prot = cmdLogic_outputFork_payload_prot; + assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; + assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 6]; + always @(*) begin + io_output_ar_payload_size = 3'b110; + if(when_Axi4Upsizer_l108) begin + io_output_ar_payload_size = io_input_ar_payload_size; + end + end + + assign io_output_ar_payload_len = {3'd0, cmdLogic_incrLen}; + assign io_output_ar_payload_id = 8'h00; + assign when_Axi4Upsizer_l108 = (io_input_ar_payload_len == 8'h00); + assign dataLogic_cmdPush_valid = cmdLogic_dataFork_valid; + assign cmdLogic_dataFork_ready = dataLogic_cmdPush_ready; + assign dataLogic_cmdPush_payload_startAt = cmdLogic_dataFork_payload_addr[5:0]; + assign dataLogic_cmdPush_payload_endAt = _zz_dataLogic_cmdPush_payload_endAt[5:0]; + assign dataLogic_cmdPush_payload_size = cmdLogic_dataFork_payload_size; + assign dataLogic_cmdPush_payload_id = cmdLogic_dataFork_payload_id; + assign dataLogic_cmdPush_ready = dataLogic_cmdPush_fifo_io_push_ready; + assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); + assign readOnly_dataLogic_cmdPush_fifo_io_pop_fire = (dataLogic_cmdPush_fifo_io_pop_valid && dataLogic_cmdPush_fifo_io_pop_ready); + assign dataLogic_cmdPush_fifo_io_pop_ready = (! dataLogic_busy); + assign io_input_r_fire = (io_input_r_valid && io_input_r_ready); + assign io_input_r_valid = (io_output_r_valid && dataLogic_busy); + assign io_input_r_payload_last = (io_output_r_payload_last && (dataLogic_byteCounter == dataLogic_byteCounterLast)); + assign io_input_r_payload_resp = io_output_r_payload_resp; + assign io_input_r_payload_data = _zz_io_input_r_payload_data; + assign io_input_r_payload_id = dataLogic_id; + assign io_output_r_ready = ((dataLogic_busy && io_input_r_ready) && (io_input_r_payload_last || dataLogic_byteCounterNext[6])); + always @(posedge clk or posedge reset) begin + if(reset) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; + io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; + dataLogic_busy <= 1'b0; + end else begin + if(cmdLogic_outputFork_fire) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdLogic_dataFork_fire) begin + io_input_ar_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_ar_ready) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; + io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; + end + if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin + dataLogic_busy <= 1'b1; + end + if(io_input_r_fire) begin + if(io_input_r_payload_last) begin + dataLogic_busy <= 1'b0; + end + end + end + end + + always @(posedge clk) begin + if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin + dataLogic_byteCounter <= dataLogic_cmdPush_fifo_io_pop_payload_startAt; + dataLogic_byteCounterLast <= dataLogic_cmdPush_fifo_io_pop_payload_endAt; + dataLogic_size <= dataLogic_cmdPush_fifo_io_pop_payload_size; + dataLogic_id <= dataLogic_cmdPush_fifo_io_pop_payload_id; + end + if(io_input_r_fire) begin + dataLogic_byteCounter <= dataLogic_byteCounterNext[5:0]; + end + end + + +endmodule + +module Asic32To512UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_push_valid, + output io_push_ready, + input [5:0] io_push_payload_startAt, + input [5:0] io_push_payload_endAt, + input [2:0] io_push_payload_size, + input [7:0] io_push_payload_id, + output io_pop_valid, + input io_pop_ready, + output [5:0] io_pop_payload_startAt, + output [5:0] io_pop_payload_endAt, + output [2:0] io_pop_payload_size, + output [7:0] io_pop_payload_id, + input io_flush, + output [4:0] io_occupancy, + output [4:0] io_availability, + input clk, + input reset +); + + reg [22:0] _zz_logic_ram_port0; + wire [3:0] _zz_logic_pushPtr_valueNext; + wire [0:0] _zz_logic_pushPtr_valueNext_1; + wire [3:0] _zz_logic_popPtr_valueNext; + wire [0:0] _zz_logic_popPtr_valueNext_1; + wire _zz__zz_logic_ram_port0; + wire _zz__zz_io_pop_payload_startAt; + wire [22:0] _zz__zz_logic_ram_port1; + wire [3:0] _zz_io_availability; + reg _zz_1; + reg logic_pushPtr_willIncrement; + reg logic_pushPtr_willClear; + reg [3:0] logic_pushPtr_valueNext; + reg [3:0] logic_pushPtr_value; + wire logic_pushPtr_willOverflowIfInc; + wire logic_pushPtr_willOverflow; + reg logic_popPtr_willIncrement; + reg logic_popPtr_willClear; + reg [3:0] logic_popPtr_valueNext; + reg [3:0] logic_popPtr_value; + wire logic_popPtr_willOverflowIfInc; + wire logic_popPtr_willOverflow; + wire logic_ptrMatch; + reg logic_risingOccupancy; + wire logic_pushing; + wire logic_popping; + wire logic_empty; + wire logic_full; + reg _zz_io_pop_valid; + wire [22:0] _zz_io_pop_payload_startAt; + wire when_Stream_l1123; + wire [3:0] logic_ptrDif; + reg [22:0] logic_ram [0:15]; + + assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; + assign _zz_logic_pushPtr_valueNext = {3'd0, _zz_logic_pushPtr_valueNext_1}; + assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; + assign _zz_logic_popPtr_valueNext = {3'd0, _zz_logic_popPtr_valueNext_1}; + assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); + assign _zz__zz_io_pop_payload_startAt = 1'b1; + assign _zz__zz_logic_ram_port1 = {io_push_payload_id,{io_push_payload_size,{io_push_payload_endAt,io_push_payload_startAt}}}; + always @(posedge clk) begin + if(_zz__zz_io_pop_payload_startAt) begin + _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_pushPtr_value] <= _zz__zz_logic_ram_port1; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_pushing) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willIncrement = 1'b0; + if(logic_pushing) begin + logic_pushPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willClear = 1'b0; + if(io_flush) begin + logic_pushPtr_willClear = 1'b1; + end + end + + assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 4'b1111); + assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); + always @(*) begin + logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); + if(logic_pushPtr_willClear) begin + logic_pushPtr_valueNext = 4'b0000; + end + end + + always @(*) begin + logic_popPtr_willIncrement = 1'b0; + if(logic_popping) begin + logic_popPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_popPtr_willClear = 1'b0; + if(io_flush) begin + logic_popPtr_willClear = 1'b1; + end + end + + assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 4'b1111); + assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); + always @(*) begin + logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); + if(logic_popPtr_willClear) begin + logic_popPtr_valueNext = 4'b0000; + end + end + + assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); + assign logic_pushing = (io_push_valid && io_push_ready); + assign logic_popping = (io_pop_valid && io_pop_ready); + assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); + assign logic_full = (logic_ptrMatch && logic_risingOccupancy); + assign io_push_ready = (! logic_full); + assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); + assign _zz_io_pop_payload_startAt = _zz_logic_ram_port0; + assign io_pop_payload_startAt = _zz_io_pop_payload_startAt[5 : 0]; + assign io_pop_payload_endAt = _zz_io_pop_payload_startAt[11 : 6]; + assign io_pop_payload_size = _zz_io_pop_payload_startAt[14 : 12]; + assign io_pop_payload_id = _zz_io_pop_payload_startAt[22 : 15]; + assign when_Stream_l1123 = (logic_pushing != logic_popping); + assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); + assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; + assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; + always @(posedge clk or posedge reset) begin + if(reset) begin + logic_pushPtr_value <= 4'b0000; + logic_popPtr_value <= 4'b0000; + logic_risingOccupancy <= 1'b0; + _zz_io_pop_valid <= 1'b0; + end else begin + logic_pushPtr_value <= logic_pushPtr_valueNext; + logic_popPtr_value <= logic_popPtr_valueNext; + _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); + if(when_Stream_l1123) begin + logic_risingOccupancy <= logic_pushing; + end + if(io_flush) begin + logic_risingOccupancy <= 1'b0; + end + end + end + + +endmodule + + +// Generator : SpinalHDL dev git head : 9cdee03b276638ef8e7a948b606bb7acc6e4c8d0 +// Component : Asic32To64UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 +// Git hash : cd16421fb7a4d44431a2445f9a92b82070ab9b8a + +`timescale 1ns/1ps + +module Asic32To64UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_aw_valid, + output io_input_aw_ready, + input [31:0] io_input_aw_payload_addr, + input [7:0] io_input_aw_payload_id, + input [3:0] io_input_aw_payload_region, + input [7:0] io_input_aw_payload_len, + input [2:0] io_input_aw_payload_size, + input [1:0] io_input_aw_payload_burst, + input [0:0] io_input_aw_payload_lock, + input [3:0] io_input_aw_payload_cache, + input [3:0] io_input_aw_payload_qos, + input [2:0] io_input_aw_payload_prot, + input io_input_w_valid, + output io_input_w_ready, + input [31:0] io_input_w_payload_data, + input [3:0] io_input_w_payload_strb, + input io_input_w_payload_last, + output io_input_b_valid, + input io_input_b_ready, + output [7:0] io_input_b_payload_id, + output [1:0] io_input_b_payload_resp, + input io_input_ar_valid, + output io_input_ar_ready, + input [31:0] io_input_ar_payload_addr, + input [7:0] io_input_ar_payload_id, + input [3:0] io_input_ar_payload_region, + input [7:0] io_input_ar_payload_len, + input [2:0] io_input_ar_payload_size, + input [1:0] io_input_ar_payload_burst, + input [0:0] io_input_ar_payload_lock, + input [3:0] io_input_ar_payload_cache, + input [3:0] io_input_ar_payload_qos, + input [2:0] io_input_ar_payload_prot, + output io_input_r_valid, + input io_input_r_ready, + output [31:0] io_input_r_payload_data, + output [7:0] io_input_r_payload_id, + output [1:0] io_input_r_payload_resp, + output io_input_r_payload_last, + output io_output_aw_valid, + input io_output_aw_ready, + output [31:0] io_output_aw_payload_addr, + output [7:0] io_output_aw_payload_id, + output [3:0] io_output_aw_payload_region, + output [7:0] io_output_aw_payload_len, + output [2:0] io_output_aw_payload_size, + output [1:0] io_output_aw_payload_burst, + output [0:0] io_output_aw_payload_lock, + output [3:0] io_output_aw_payload_cache, + output [3:0] io_output_aw_payload_qos, + output [2:0] io_output_aw_payload_prot, + output io_output_w_valid, + input io_output_w_ready, + output [63:0] io_output_w_payload_data, + output [7:0] io_output_w_payload_strb, + output io_output_w_payload_last, + input io_output_b_valid, + output io_output_b_ready, + input [7:0] io_output_b_payload_id, + input [1:0] io_output_b_payload_resp, + output io_output_ar_valid, + input io_output_ar_ready, + output [31:0] io_output_ar_payload_addr, + output [7:0] io_output_ar_payload_id, + output [3:0] io_output_ar_payload_region, + output [7:0] io_output_ar_payload_len, + output [2:0] io_output_ar_payload_size, + output [1:0] io_output_ar_payload_burst, + output [0:0] io_output_ar_payload_lock, + output [3:0] io_output_ar_payload_cache, + output [3:0] io_output_ar_payload_qos, + output [2:0] io_output_ar_payload_prot, + input io_output_r_valid, + output io_output_r_ready, + input [63:0] io_output_r_payload_data, + input [7:0] io_output_r_payload_id, + input [1:0] io_output_r_payload_resp, + input io_output_r_payload_last, + input clk, + input reset +); + + wire readOnly_io_input_ar_ready; + wire readOnly_io_input_r_valid; + wire [31:0] readOnly_io_input_r_payload_data; + wire [7:0] readOnly_io_input_r_payload_id; + wire [1:0] readOnly_io_input_r_payload_resp; + wire readOnly_io_input_r_payload_last; + wire readOnly_io_output_ar_valid; + wire [31:0] readOnly_io_output_ar_payload_addr; + wire [7:0] readOnly_io_output_ar_payload_id; + wire [3:0] readOnly_io_output_ar_payload_region; + wire [7:0] readOnly_io_output_ar_payload_len; + wire [2:0] readOnly_io_output_ar_payload_size; + wire [1:0] readOnly_io_output_ar_payload_burst; + wire [0:0] readOnly_io_output_ar_payload_lock; + wire [3:0] readOnly_io_output_ar_payload_cache; + wire [3:0] readOnly_io_output_ar_payload_qos; + wire [2:0] readOnly_io_output_ar_payload_prot; + wire readOnly_io_output_r_ready; + wire writeOnly_io_input_aw_ready; + wire writeOnly_io_input_w_ready; + wire writeOnly_io_input_b_valid; + wire [7:0] writeOnly_io_input_b_payload_id; + wire [1:0] writeOnly_io_input_b_payload_resp; + wire writeOnly_io_output_aw_valid; + wire [31:0] writeOnly_io_output_aw_payload_addr; + wire [7:0] writeOnly_io_output_aw_payload_id; + wire [3:0] writeOnly_io_output_aw_payload_region; + wire [7:0] writeOnly_io_output_aw_payload_len; + wire [2:0] writeOnly_io_output_aw_payload_size; + wire [1:0] writeOnly_io_output_aw_payload_burst; + wire [0:0] writeOnly_io_output_aw_payload_lock; + wire [3:0] writeOnly_io_output_aw_payload_cache; + wire [3:0] writeOnly_io_output_aw_payload_qos; + wire [2:0] writeOnly_io_output_aw_payload_prot; + wire writeOnly_io_output_w_valid; + wire [63:0] writeOnly_io_output_w_payload_data; + wire [7:0] writeOnly_io_output_w_payload_strb; + wire writeOnly_io_output_w_payload_last; + wire writeOnly_io_output_b_ready; + + Asic32To64UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 readOnly ( + .io_input_ar_valid (io_input_ar_valid ), //i + .io_input_ar_ready (readOnly_io_input_ar_ready ), //o + .io_input_ar_payload_addr (io_input_ar_payload_addr[31:0] ), //i + .io_input_ar_payload_id (io_input_ar_payload_id[7:0] ), //i + .io_input_ar_payload_region (io_input_ar_payload_region[3:0] ), //i + .io_input_ar_payload_len (io_input_ar_payload_len[7:0] ), //i + .io_input_ar_payload_size (io_input_ar_payload_size[2:0] ), //i + .io_input_ar_payload_burst (io_input_ar_payload_burst[1:0] ), //i + .io_input_ar_payload_lock (io_input_ar_payload_lock ), //i + .io_input_ar_payload_cache (io_input_ar_payload_cache[3:0] ), //i + .io_input_ar_payload_qos (io_input_ar_payload_qos[3:0] ), //i + .io_input_ar_payload_prot (io_input_ar_payload_prot[2:0] ), //i + .io_input_r_valid (readOnly_io_input_r_valid ), //o + .io_input_r_ready (io_input_r_ready ), //i + .io_input_r_payload_data (readOnly_io_input_r_payload_data[31:0] ), //o + .io_input_r_payload_id (readOnly_io_input_r_payload_id[7:0] ), //o + .io_input_r_payload_resp (readOnly_io_input_r_payload_resp[1:0] ), //o + .io_input_r_payload_last (readOnly_io_input_r_payload_last ), //o + .io_output_ar_valid (readOnly_io_output_ar_valid ), //o + .io_output_ar_ready (io_output_ar_ready ), //i + .io_output_ar_payload_addr (readOnly_io_output_ar_payload_addr[31:0] ), //o + .io_output_ar_payload_id (readOnly_io_output_ar_payload_id[7:0] ), //o + .io_output_ar_payload_region (readOnly_io_output_ar_payload_region[3:0]), //o + .io_output_ar_payload_len (readOnly_io_output_ar_payload_len[7:0] ), //o + .io_output_ar_payload_size (readOnly_io_output_ar_payload_size[2:0] ), //o + .io_output_ar_payload_burst (readOnly_io_output_ar_payload_burst[1:0] ), //o + .io_output_ar_payload_lock (readOnly_io_output_ar_payload_lock ), //o + .io_output_ar_payload_cache (readOnly_io_output_ar_payload_cache[3:0] ), //o + .io_output_ar_payload_qos (readOnly_io_output_ar_payload_qos[3:0] ), //o + .io_output_ar_payload_prot (readOnly_io_output_ar_payload_prot[2:0] ), //o + .io_output_r_valid (io_output_r_valid ), //i + .io_output_r_ready (readOnly_io_output_r_ready ), //o + .io_output_r_payload_data (io_output_r_payload_data[63:0] ), //i + .io_output_r_payload_id (io_output_r_payload_id[7:0] ), //i + .io_output_r_payload_resp (io_output_r_payload_resp[1:0] ), //i + .io_output_r_payload_last (io_output_r_payload_last ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Asic32To64UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 writeOnly ( + .io_input_aw_valid (io_input_aw_valid ), //i + .io_input_aw_ready (writeOnly_io_input_aw_ready ), //o + .io_input_aw_payload_addr (io_input_aw_payload_addr[31:0] ), //i + .io_input_aw_payload_id (io_input_aw_payload_id[7:0] ), //i + .io_input_aw_payload_region (io_input_aw_payload_region[3:0] ), //i + .io_input_aw_payload_len (io_input_aw_payload_len[7:0] ), //i + .io_input_aw_payload_size (io_input_aw_payload_size[2:0] ), //i + .io_input_aw_payload_burst (io_input_aw_payload_burst[1:0] ), //i + .io_input_aw_payload_lock (io_input_aw_payload_lock ), //i + .io_input_aw_payload_cache (io_input_aw_payload_cache[3:0] ), //i + .io_input_aw_payload_qos (io_input_aw_payload_qos[3:0] ), //i + .io_input_aw_payload_prot (io_input_aw_payload_prot[2:0] ), //i + .io_input_w_valid (io_input_w_valid ), //i + .io_input_w_ready (writeOnly_io_input_w_ready ), //o + .io_input_w_payload_data (io_input_w_payload_data[31:0] ), //i + .io_input_w_payload_strb (io_input_w_payload_strb[3:0] ), //i + .io_input_w_payload_last (io_input_w_payload_last ), //i + .io_input_b_valid (writeOnly_io_input_b_valid ), //o + .io_input_b_ready (io_input_b_ready ), //i + .io_input_b_payload_id (writeOnly_io_input_b_payload_id[7:0] ), //o + .io_input_b_payload_resp (writeOnly_io_input_b_payload_resp[1:0] ), //o + .io_output_aw_valid (writeOnly_io_output_aw_valid ), //o + .io_output_aw_ready (io_output_aw_ready ), //i + .io_output_aw_payload_addr (writeOnly_io_output_aw_payload_addr[31:0] ), //o + .io_output_aw_payload_id (writeOnly_io_output_aw_payload_id[7:0] ), //o + .io_output_aw_payload_region (writeOnly_io_output_aw_payload_region[3:0]), //o + .io_output_aw_payload_len (writeOnly_io_output_aw_payload_len[7:0] ), //o + .io_output_aw_payload_size (writeOnly_io_output_aw_payload_size[2:0] ), //o + .io_output_aw_payload_burst (writeOnly_io_output_aw_payload_burst[1:0] ), //o + .io_output_aw_payload_lock (writeOnly_io_output_aw_payload_lock ), //o + .io_output_aw_payload_cache (writeOnly_io_output_aw_payload_cache[3:0] ), //o + .io_output_aw_payload_qos (writeOnly_io_output_aw_payload_qos[3:0] ), //o + .io_output_aw_payload_prot (writeOnly_io_output_aw_payload_prot[2:0] ), //o + .io_output_w_valid (writeOnly_io_output_w_valid ), //o + .io_output_w_ready (io_output_w_ready ), //i + .io_output_w_payload_data (writeOnly_io_output_w_payload_data[63:0] ), //o + .io_output_w_payload_strb (writeOnly_io_output_w_payload_strb[7:0] ), //o + .io_output_w_payload_last (writeOnly_io_output_w_payload_last ), //o + .io_output_b_valid (io_output_b_valid ), //i + .io_output_b_ready (writeOnly_io_output_b_ready ), //o + .io_output_b_payload_id (io_output_b_payload_id[7:0] ), //i + .io_output_b_payload_resp (io_output_b_payload_resp[1:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign io_input_ar_ready = readOnly_io_input_ar_ready; + assign io_input_r_valid = readOnly_io_input_r_valid; + assign io_input_r_payload_data = readOnly_io_input_r_payload_data; + assign io_input_r_payload_id = readOnly_io_input_r_payload_id; + assign io_input_r_payload_resp = readOnly_io_input_r_payload_resp; + assign io_input_r_payload_last = readOnly_io_input_r_payload_last; + assign io_input_aw_ready = writeOnly_io_input_aw_ready; + assign io_input_w_ready = writeOnly_io_input_w_ready; + assign io_input_b_valid = writeOnly_io_input_b_valid; + assign io_input_b_payload_id = writeOnly_io_input_b_payload_id; + assign io_input_b_payload_resp = writeOnly_io_input_b_payload_resp; + assign io_output_ar_valid = readOnly_io_output_ar_valid; + assign io_output_ar_payload_addr = readOnly_io_output_ar_payload_addr; + assign io_output_ar_payload_id = readOnly_io_output_ar_payload_id; + assign io_output_ar_payload_region = readOnly_io_output_ar_payload_region; + assign io_output_ar_payload_len = readOnly_io_output_ar_payload_len; + assign io_output_ar_payload_size = readOnly_io_output_ar_payload_size; + assign io_output_ar_payload_burst = readOnly_io_output_ar_payload_burst; + assign io_output_ar_payload_lock = readOnly_io_output_ar_payload_lock; + assign io_output_ar_payload_cache = readOnly_io_output_ar_payload_cache; + assign io_output_ar_payload_qos = readOnly_io_output_ar_payload_qos; + assign io_output_ar_payload_prot = readOnly_io_output_ar_payload_prot; + assign io_output_r_ready = readOnly_io_output_r_ready; + assign io_output_aw_valid = writeOnly_io_output_aw_valid; + assign io_output_aw_payload_addr = writeOnly_io_output_aw_payload_addr; + assign io_output_aw_payload_id = writeOnly_io_output_aw_payload_id; + assign io_output_aw_payload_region = writeOnly_io_output_aw_payload_region; + assign io_output_aw_payload_len = writeOnly_io_output_aw_payload_len; + assign io_output_aw_payload_size = writeOnly_io_output_aw_payload_size; + assign io_output_aw_payload_burst = writeOnly_io_output_aw_payload_burst; + assign io_output_aw_payload_lock = writeOnly_io_output_aw_payload_lock; + assign io_output_aw_payload_cache = writeOnly_io_output_aw_payload_cache; + assign io_output_aw_payload_qos = writeOnly_io_output_aw_payload_qos; + assign io_output_aw_payload_prot = writeOnly_io_output_aw_payload_prot; + assign io_output_w_valid = writeOnly_io_output_w_valid; + assign io_output_w_payload_data = writeOnly_io_output_w_payload_data; + assign io_output_w_payload_strb = writeOnly_io_output_w_payload_strb; + assign io_output_w_payload_last = writeOnly_io_output_w_payload_last; + assign io_output_b_ready = writeOnly_io_output_b_ready; + +endmodule + +module Asic32To64UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_aw_valid, + output reg io_input_aw_ready, + input [31:0] io_input_aw_payload_addr, + input [7:0] io_input_aw_payload_id, + input [3:0] io_input_aw_payload_region, + input [7:0] io_input_aw_payload_len, + input [2:0] io_input_aw_payload_size, + input [1:0] io_input_aw_payload_burst, + input [0:0] io_input_aw_payload_lock, + input [3:0] io_input_aw_payload_cache, + input [3:0] io_input_aw_payload_qos, + input [2:0] io_input_aw_payload_prot, + input io_input_w_valid, + output io_input_w_ready, + input [31:0] io_input_w_payload_data, + input [3:0] io_input_w_payload_strb, + input io_input_w_payload_last, + output io_input_b_valid, + input io_input_b_ready, + output [7:0] io_input_b_payload_id, + output [1:0] io_input_b_payload_resp, + output io_output_aw_valid, + input io_output_aw_ready, + output [31:0] io_output_aw_payload_addr, + output [7:0] io_output_aw_payload_id, + output [3:0] io_output_aw_payload_region, + output reg [7:0] io_output_aw_payload_len, + output reg [2:0] io_output_aw_payload_size, + output [1:0] io_output_aw_payload_burst, + output [0:0] io_output_aw_payload_lock, + output [3:0] io_output_aw_payload_cache, + output [3:0] io_output_aw_payload_qos, + output [2:0] io_output_aw_payload_prot, + output io_output_w_valid, + input io_output_w_ready, + output [63:0] io_output_w_payload_data, + output [7:0] io_output_w_payload_strb, + output io_output_w_payload_last, + input io_output_b_valid, + output io_output_b_ready, + input [7:0] io_output_b_payload_id, + input [1:0] io_output_b_payload_resp, + input clk, + input reset +); + + wire [14:0] _zz_cmdLogic_byteCount; + wire [10:0] _zz_cmdLogic_incrLen; + wire [10:0] _zz_cmdLogic_incrLen_1; + wire [2:0] _zz_cmdLogic_incrLen_2; + wire [3:0] _zz_dataLogic_byteCounterNext; + wire [7:0] _zz_dataLogic_byteCounterNext_1; + reg [7:0] _zz_dataLogic_byteActivity; + wire [1:0] _zz_dataLogic_byteActivity_1; + wire cmdLogic_outputFork_valid; + wire cmdLogic_outputFork_ready; + wire [31:0] cmdLogic_outputFork_payload_addr; + wire [7:0] cmdLogic_outputFork_payload_id; + wire [3:0] cmdLogic_outputFork_payload_region; + wire [7:0] cmdLogic_outputFork_payload_len; + wire [2:0] cmdLogic_outputFork_payload_size; + wire [1:0] cmdLogic_outputFork_payload_burst; + wire [0:0] cmdLogic_outputFork_payload_lock; + wire [3:0] cmdLogic_outputFork_payload_cache; + wire [3:0] cmdLogic_outputFork_payload_qos; + wire [2:0] cmdLogic_outputFork_payload_prot; + wire cmdLogic_dataFork_valid; + wire cmdLogic_dataFork_ready; + wire [31:0] cmdLogic_dataFork_payload_addr; + wire [7:0] cmdLogic_dataFork_payload_id; + wire [3:0] cmdLogic_dataFork_payload_region; + wire [7:0] cmdLogic_dataFork_payload_len; + wire [2:0] cmdLogic_dataFork_payload_size; + wire [1:0] cmdLogic_dataFork_payload_burst; + wire [0:0] cmdLogic_dataFork_payload_lock; + wire [3:0] cmdLogic_dataFork_payload_cache; + wire [3:0] cmdLogic_dataFork_payload_qos; + wire [2:0] cmdLogic_dataFork_payload_prot; + reg io_input_aw_fork2_logic_linkEnable_0; + reg io_input_aw_fork2_logic_linkEnable_1; + wire when_Stream_l993; + wire when_Stream_l993_1; + wire cmdLogic_outputFork_fire; + wire cmdLogic_dataFork_fire; + wire [9:0] cmdLogic_byteCount; + wire [7:0] cmdLogic_incrLen; + wire when_Axi4Upsizer_l21; + wire when_Axi4Upsizer_l24; + reg [2:0] dataLogic_byteCounter; + reg [2:0] dataLogic_size; + reg dataLogic_outputValid; + reg dataLogic_outputLast; + reg dataLogic_busy; + reg dataLogic_incrementByteCounter; + reg dataLogic_alwaysFire; + wire [3:0] dataLogic_byteCounterNext; + reg [63:0] dataLogic_dataBuffer; + reg [7:0] dataLogic_maskBuffer; + wire [7:0] dataLogic_byteActivity; + wire io_output_w_fire; + wire io_output_w_isStall; + wire io_input_w_fire; + wire when_Axi4Upsizer_l59; + wire when_Axi4Upsizer_l59_1; + wire when_Axi4Upsizer_l59_2; + wire when_Axi4Upsizer_l59_3; + wire when_Axi4Upsizer_l59_4; + wire when_Axi4Upsizer_l59_5; + wire when_Axi4Upsizer_l59_6; + wire when_Axi4Upsizer_l59_7; + wire cmdLogic_dataFork_fire_1; + wire when_Axi4Upsizer_l68; + wire when_Axi4Upsizer_l68_1; + wire when_Axi4Upsizer_l68_2; + + assign _zz_cmdLogic_byteCount = ({7'd0,io_input_aw_payload_len} <<< io_input_aw_payload_size); + assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); + assign _zz_cmdLogic_incrLen_2 = io_input_aw_payload_addr[2 : 0]; + assign _zz_cmdLogic_incrLen_1 = {8'd0, _zz_cmdLogic_incrLen_2}; + assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); + assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[3:0]; + assign _zz_dataLogic_byteActivity_1 = dataLogic_size[1:0]; + always @(*) begin + case(_zz_dataLogic_byteActivity_1) + 2'b00 : _zz_dataLogic_byteActivity = 8'h01; + 2'b01 : _zz_dataLogic_byteActivity = 8'h03; + default : _zz_dataLogic_byteActivity = 8'h0f; + endcase + end + + always @(*) begin + io_input_aw_ready = 1'b1; + if(when_Stream_l993) begin + io_input_aw_ready = 1'b0; + end + if(when_Stream_l993_1) begin + io_input_aw_ready = 1'b0; + end + end + + assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_aw_fork2_logic_linkEnable_0); + assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_aw_fork2_logic_linkEnable_1); + assign cmdLogic_outputFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_0); + assign cmdLogic_outputFork_payload_addr = io_input_aw_payload_addr; + assign cmdLogic_outputFork_payload_id = io_input_aw_payload_id; + assign cmdLogic_outputFork_payload_region = io_input_aw_payload_region; + assign cmdLogic_outputFork_payload_len = io_input_aw_payload_len; + assign cmdLogic_outputFork_payload_size = io_input_aw_payload_size; + assign cmdLogic_outputFork_payload_burst = io_input_aw_payload_burst; + assign cmdLogic_outputFork_payload_lock = io_input_aw_payload_lock; + assign cmdLogic_outputFork_payload_cache = io_input_aw_payload_cache; + assign cmdLogic_outputFork_payload_qos = io_input_aw_payload_qos; + assign cmdLogic_outputFork_payload_prot = io_input_aw_payload_prot; + assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); + assign cmdLogic_dataFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_1); + assign cmdLogic_dataFork_payload_addr = io_input_aw_payload_addr; + assign cmdLogic_dataFork_payload_id = io_input_aw_payload_id; + assign cmdLogic_dataFork_payload_region = io_input_aw_payload_region; + assign cmdLogic_dataFork_payload_len = io_input_aw_payload_len; + assign cmdLogic_dataFork_payload_size = io_input_aw_payload_size; + assign cmdLogic_dataFork_payload_burst = io_input_aw_payload_burst; + assign cmdLogic_dataFork_payload_lock = io_input_aw_payload_lock; + assign cmdLogic_dataFork_payload_cache = io_input_aw_payload_cache; + assign cmdLogic_dataFork_payload_qos = io_input_aw_payload_qos; + assign cmdLogic_dataFork_payload_prot = io_input_aw_payload_prot; + assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign io_output_aw_valid = cmdLogic_outputFork_valid; + assign cmdLogic_outputFork_ready = io_output_aw_ready; + assign io_output_aw_payload_addr = cmdLogic_outputFork_payload_addr; + assign io_output_aw_payload_id = cmdLogic_outputFork_payload_id; + assign io_output_aw_payload_region = cmdLogic_outputFork_payload_region; + always @(*) begin + io_output_aw_payload_len = cmdLogic_outputFork_payload_len; + if(when_Axi4Upsizer_l21) begin + io_output_aw_payload_len = cmdLogic_incrLen; + end + end + + always @(*) begin + io_output_aw_payload_size = cmdLogic_outputFork_payload_size; + if(when_Axi4Upsizer_l21) begin + io_output_aw_payload_size = 3'b011; + if(when_Axi4Upsizer_l24) begin + io_output_aw_payload_size = io_input_aw_payload_size; + end + end + end + + assign io_output_aw_payload_burst = cmdLogic_outputFork_payload_burst; + assign io_output_aw_payload_lock = cmdLogic_outputFork_payload_lock; + assign io_output_aw_payload_cache = cmdLogic_outputFork_payload_cache; + assign io_output_aw_payload_qos = cmdLogic_outputFork_payload_qos; + assign io_output_aw_payload_prot = cmdLogic_outputFork_payload_prot; + assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; + assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 3]; + assign when_Axi4Upsizer_l21 = (io_output_aw_payload_burst == 2'b01); + assign when_Axi4Upsizer_l24 = (io_input_aw_payload_len == 8'h00); + assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); + assign dataLogic_byteActivity = (_zz_dataLogic_byteActivity <<< dataLogic_byteCounter); + assign io_output_w_fire = (io_output_w_valid && io_output_w_ready); + assign io_output_w_valid = dataLogic_outputValid; + assign io_output_w_isStall = (io_output_w_valid && (! io_output_w_ready)); + assign io_input_w_ready = (dataLogic_busy && (! io_output_w_isStall)); + assign io_output_w_payload_data = dataLogic_dataBuffer; + assign io_output_w_payload_strb = dataLogic_maskBuffer; + assign io_output_w_payload_last = dataLogic_outputLast; + assign io_input_w_fire = (io_input_w_valid && io_input_w_ready); + assign when_Axi4Upsizer_l59 = dataLogic_byteActivity[0]; + assign when_Axi4Upsizer_l59_1 = dataLogic_byteActivity[1]; + assign when_Axi4Upsizer_l59_2 = dataLogic_byteActivity[2]; + assign when_Axi4Upsizer_l59_3 = dataLogic_byteActivity[3]; + assign when_Axi4Upsizer_l59_4 = dataLogic_byteActivity[4]; + assign when_Axi4Upsizer_l59_5 = dataLogic_byteActivity[5]; + assign when_Axi4Upsizer_l59_6 = dataLogic_byteActivity[6]; + assign when_Axi4Upsizer_l59_7 = dataLogic_byteActivity[7]; + assign cmdLogic_dataFork_fire_1 = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign when_Axi4Upsizer_l68 = (3'b000 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_1 = (3'b001 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_2 = (3'b010 < cmdLogic_dataFork_payload_size); + assign cmdLogic_dataFork_ready = (! dataLogic_busy); + assign io_input_b_valid = io_output_b_valid; + assign io_output_b_ready = io_input_b_ready; + assign io_input_b_payload_id = io_output_b_payload_id; + assign io_input_b_payload_resp = io_output_b_payload_resp; + always @(posedge clk or posedge reset) begin + if(reset) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; + io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; + dataLogic_outputValid <= 1'b0; + dataLogic_busy <= 1'b0; + dataLogic_maskBuffer <= 8'h00; + end else begin + if(cmdLogic_outputFork_fire) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdLogic_dataFork_fire) begin + io_input_aw_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_aw_ready) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; + io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; + end + if(io_output_w_ready) begin + dataLogic_outputValid <= 1'b0; + end + if(io_output_w_fire) begin + dataLogic_maskBuffer <= 8'h00; + end + if(io_input_w_fire) begin + dataLogic_outputValid <= ((dataLogic_byteCounterNext[3] || io_input_w_payload_last) || dataLogic_alwaysFire); + if(io_input_w_payload_last) begin + dataLogic_busy <= 1'b0; + end + if(when_Axi4Upsizer_l59) begin + dataLogic_maskBuffer[0] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_1) begin + dataLogic_maskBuffer[1] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_2) begin + dataLogic_maskBuffer[2] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_3) begin + dataLogic_maskBuffer[3] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_4) begin + dataLogic_maskBuffer[4] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_5) begin + dataLogic_maskBuffer[5] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_6) begin + dataLogic_maskBuffer[6] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_7) begin + dataLogic_maskBuffer[7] <= io_input_w_payload_strb[3]; + end + end + if(cmdLogic_dataFork_fire_1) begin + dataLogic_busy <= 1'b1; + end + end + end + + always @(posedge clk) begin + if(io_input_w_fire) begin + if(dataLogic_incrementByteCounter) begin + dataLogic_byteCounter <= dataLogic_byteCounterNext[2:0]; + end + dataLogic_outputLast <= io_input_w_payload_last; + if(when_Axi4Upsizer_l59) begin + dataLogic_dataBuffer[7 : 0] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_1) begin + dataLogic_dataBuffer[15 : 8] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_2) begin + dataLogic_dataBuffer[23 : 16] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_3) begin + dataLogic_dataBuffer[31 : 24] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_4) begin + dataLogic_dataBuffer[39 : 32] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_5) begin + dataLogic_dataBuffer[47 : 40] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_6) begin + dataLogic_dataBuffer[55 : 48] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_7) begin + dataLogic_dataBuffer[63 : 56] <= io_input_w_payload_data[31 : 24]; + end + end + if(cmdLogic_dataFork_fire_1) begin + dataLogic_byteCounter <= cmdLogic_dataFork_payload_addr[2:0]; + if(when_Axi4Upsizer_l68) begin + dataLogic_byteCounter[0] <= 1'b0; + end + if(when_Axi4Upsizer_l68_1) begin + dataLogic_byteCounter[1] <= 1'b0; + end + if(when_Axi4Upsizer_l68_2) begin + dataLogic_byteCounter[2] <= 1'b0; + end + dataLogic_size <= cmdLogic_dataFork_payload_size; + dataLogic_alwaysFire <= (! (cmdLogic_dataFork_payload_burst == 2'b01)); + dataLogic_incrementByteCounter <= (! (cmdLogic_dataFork_payload_burst == 2'b00)); + end + end + + +endmodule + +module Asic32To64UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_ar_valid, + output reg io_input_ar_ready, + input [31:0] io_input_ar_payload_addr, + input [7:0] io_input_ar_payload_id, + input [3:0] io_input_ar_payload_region, + input [7:0] io_input_ar_payload_len, + input [2:0] io_input_ar_payload_size, + input [1:0] io_input_ar_payload_burst, + input [0:0] io_input_ar_payload_lock, + input [3:0] io_input_ar_payload_cache, + input [3:0] io_input_ar_payload_qos, + input [2:0] io_input_ar_payload_prot, + output io_input_r_valid, + input io_input_r_ready, + output [31:0] io_input_r_payload_data, + output [7:0] io_input_r_payload_id, + output [1:0] io_input_r_payload_resp, + output io_input_r_payload_last, + output io_output_ar_valid, + input io_output_ar_ready, + output [31:0] io_output_ar_payload_addr, + output [7:0] io_output_ar_payload_id, + output [3:0] io_output_ar_payload_region, + output [7:0] io_output_ar_payload_len, + output reg [2:0] io_output_ar_payload_size, + output [1:0] io_output_ar_payload_burst, + output [0:0] io_output_ar_payload_lock, + output [3:0] io_output_ar_payload_cache, + output [3:0] io_output_ar_payload_qos, + output [2:0] io_output_ar_payload_prot, + input io_output_r_valid, + output io_output_r_ready, + input [63:0] io_output_r_payload_data, + input [7:0] io_output_r_payload_id, + input [1:0] io_output_r_payload_resp, + input io_output_r_payload_last, + input clk, + input reset +); + + wire dataLogic_cmdPush_fifo_io_pop_ready; + wire dataLogic_cmdPush_fifo_io_push_ready; + wire dataLogic_cmdPush_fifo_io_pop_valid; + wire [2:0] dataLogic_cmdPush_fifo_io_pop_payload_startAt; + wire [2:0] dataLogic_cmdPush_fifo_io_pop_payload_endAt; + wire [2:0] dataLogic_cmdPush_fifo_io_pop_payload_size; + wire [7:0] dataLogic_cmdPush_fifo_io_pop_payload_id; + wire [4:0] dataLogic_cmdPush_fifo_io_occupancy; + wire [4:0] dataLogic_cmdPush_fifo_io_availability; + wire [14:0] _zz_cmdLogic_byteCount; + wire [10:0] _zz_cmdLogic_incrLen; + wire [10:0] _zz_cmdLogic_incrLen_1; + wire [2:0] _zz_cmdLogic_incrLen_2; + wire [31:0] _zz_dataLogic_cmdPush_payload_endAt; + wire [31:0] _zz_dataLogic_cmdPush_payload_endAt_1; + wire [14:0] _zz_dataLogic_cmdPush_payload_endAt_2; + wire [3:0] _zz_dataLogic_byteCounterNext; + wire [7:0] _zz_dataLogic_byteCounterNext_1; + reg [31:0] _zz_io_input_r_payload_data; + wire [0:0] _zz_io_input_r_payload_data_1; + wire cmdLogic_outputFork_valid; + wire cmdLogic_outputFork_ready; + wire [31:0] cmdLogic_outputFork_payload_addr; + wire [7:0] cmdLogic_outputFork_payload_id; + wire [3:0] cmdLogic_outputFork_payload_region; + wire [7:0] cmdLogic_outputFork_payload_len; + wire [2:0] cmdLogic_outputFork_payload_size; + wire [1:0] cmdLogic_outputFork_payload_burst; + wire [0:0] cmdLogic_outputFork_payload_lock; + wire [3:0] cmdLogic_outputFork_payload_cache; + wire [3:0] cmdLogic_outputFork_payload_qos; + wire [2:0] cmdLogic_outputFork_payload_prot; + wire cmdLogic_dataFork_valid; + wire cmdLogic_dataFork_ready; + wire [31:0] cmdLogic_dataFork_payload_addr; + wire [7:0] cmdLogic_dataFork_payload_id; + wire [3:0] cmdLogic_dataFork_payload_region; + wire [7:0] cmdLogic_dataFork_payload_len; + wire [2:0] cmdLogic_dataFork_payload_size; + wire [1:0] cmdLogic_dataFork_payload_burst; + wire [0:0] cmdLogic_dataFork_payload_lock; + wire [3:0] cmdLogic_dataFork_payload_cache; + wire [3:0] cmdLogic_dataFork_payload_qos; + wire [2:0] cmdLogic_dataFork_payload_prot; + reg io_input_ar_fork2_logic_linkEnable_0; + reg io_input_ar_fork2_logic_linkEnable_1; + wire when_Stream_l993; + wire when_Stream_l993_1; + wire cmdLogic_outputFork_fire; + wire cmdLogic_dataFork_fire; + wire [9:0] cmdLogic_byteCount; + wire [7:0] cmdLogic_incrLen; + wire when_Axi4Upsizer_l108; + wire dataLogic_cmdPush_valid; + wire dataLogic_cmdPush_ready; + wire [2:0] dataLogic_cmdPush_payload_startAt; + wire [2:0] dataLogic_cmdPush_payload_endAt; + wire [2:0] dataLogic_cmdPush_payload_size; + wire [7:0] dataLogic_cmdPush_payload_id; + reg [2:0] dataLogic_size; + reg dataLogic_busy; + reg [7:0] dataLogic_id; + reg [2:0] dataLogic_byteCounter; + reg [2:0] dataLogic_byteCounterLast; + wire [3:0] dataLogic_byteCounterNext; + wire readOnly_dataLogic_cmdPush_fifo_io_pop_fire; + wire io_input_r_fire; + + assign _zz_cmdLogic_byteCount = ({7'd0,io_input_ar_payload_len} <<< io_input_ar_payload_size); + assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); + assign _zz_cmdLogic_incrLen_2 = io_input_ar_payload_addr[2 : 0]; + assign _zz_cmdLogic_incrLen_1 = {8'd0, _zz_cmdLogic_incrLen_2}; + assign _zz_dataLogic_cmdPush_payload_endAt = (cmdLogic_dataFork_payload_addr + _zz_dataLogic_cmdPush_payload_endAt_1); + assign _zz_dataLogic_cmdPush_payload_endAt_2 = ({7'd0,cmdLogic_dataFork_payload_len} <<< cmdLogic_dataFork_payload_size); + assign _zz_dataLogic_cmdPush_payload_endAt_1 = {17'd0, _zz_dataLogic_cmdPush_payload_endAt_2}; + assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); + assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[3:0]; + assign _zz_io_input_r_payload_data_1 = (dataLogic_byteCounter >>> 2'd2); + Asic32To64UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 dataLogic_cmdPush_fifo ( + .io_push_valid (dataLogic_cmdPush_valid ), //i + .io_push_ready (dataLogic_cmdPush_fifo_io_push_ready ), //o + .io_push_payload_startAt (dataLogic_cmdPush_payload_startAt[2:0] ), //i + .io_push_payload_endAt (dataLogic_cmdPush_payload_endAt[2:0] ), //i + .io_push_payload_size (dataLogic_cmdPush_payload_size[2:0] ), //i + .io_push_payload_id (dataLogic_cmdPush_payload_id[7:0] ), //i + .io_pop_valid (dataLogic_cmdPush_fifo_io_pop_valid ), //o + .io_pop_ready (dataLogic_cmdPush_fifo_io_pop_ready ), //i + .io_pop_payload_startAt (dataLogic_cmdPush_fifo_io_pop_payload_startAt[2:0]), //o + .io_pop_payload_endAt (dataLogic_cmdPush_fifo_io_pop_payload_endAt[2:0] ), //o + .io_pop_payload_size (dataLogic_cmdPush_fifo_io_pop_payload_size[2:0] ), //o + .io_pop_payload_id (dataLogic_cmdPush_fifo_io_pop_payload_id[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (dataLogic_cmdPush_fifo_io_occupancy[4:0] ), //o + .io_availability (dataLogic_cmdPush_fifo_io_availability[4:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_io_input_r_payload_data_1) + 1'b0 : _zz_io_input_r_payload_data = io_output_r_payload_data[31 : 0]; + default : _zz_io_input_r_payload_data = io_output_r_payload_data[63 : 32]; + endcase + end + + always @(*) begin + io_input_ar_ready = 1'b1; + if(when_Stream_l993) begin + io_input_ar_ready = 1'b0; + end + if(when_Stream_l993_1) begin + io_input_ar_ready = 1'b0; + end + end + + assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_ar_fork2_logic_linkEnable_0); + assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_ar_fork2_logic_linkEnable_1); + assign cmdLogic_outputFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_0); + assign cmdLogic_outputFork_payload_addr = io_input_ar_payload_addr; + assign cmdLogic_outputFork_payload_id = io_input_ar_payload_id; + assign cmdLogic_outputFork_payload_region = io_input_ar_payload_region; + assign cmdLogic_outputFork_payload_len = io_input_ar_payload_len; + assign cmdLogic_outputFork_payload_size = io_input_ar_payload_size; + assign cmdLogic_outputFork_payload_burst = io_input_ar_payload_burst; + assign cmdLogic_outputFork_payload_lock = io_input_ar_payload_lock; + assign cmdLogic_outputFork_payload_cache = io_input_ar_payload_cache; + assign cmdLogic_outputFork_payload_qos = io_input_ar_payload_qos; + assign cmdLogic_outputFork_payload_prot = io_input_ar_payload_prot; + assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); + assign cmdLogic_dataFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_1); + assign cmdLogic_dataFork_payload_addr = io_input_ar_payload_addr; + assign cmdLogic_dataFork_payload_id = io_input_ar_payload_id; + assign cmdLogic_dataFork_payload_region = io_input_ar_payload_region; + assign cmdLogic_dataFork_payload_len = io_input_ar_payload_len; + assign cmdLogic_dataFork_payload_size = io_input_ar_payload_size; + assign cmdLogic_dataFork_payload_burst = io_input_ar_payload_burst; + assign cmdLogic_dataFork_payload_lock = io_input_ar_payload_lock; + assign cmdLogic_dataFork_payload_cache = io_input_ar_payload_cache; + assign cmdLogic_dataFork_payload_qos = io_input_ar_payload_qos; + assign cmdLogic_dataFork_payload_prot = io_input_ar_payload_prot; + assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign io_output_ar_valid = cmdLogic_outputFork_valid; + assign cmdLogic_outputFork_ready = io_output_ar_ready; + assign io_output_ar_payload_addr = cmdLogic_outputFork_payload_addr; + assign io_output_ar_payload_region = cmdLogic_outputFork_payload_region; + assign io_output_ar_payload_burst = cmdLogic_outputFork_payload_burst; + assign io_output_ar_payload_lock = cmdLogic_outputFork_payload_lock; + assign io_output_ar_payload_cache = cmdLogic_outputFork_payload_cache; + assign io_output_ar_payload_qos = cmdLogic_outputFork_payload_qos; + assign io_output_ar_payload_prot = cmdLogic_outputFork_payload_prot; + assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; + assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 3]; + always @(*) begin + io_output_ar_payload_size = 3'b011; + if(when_Axi4Upsizer_l108) begin + io_output_ar_payload_size = io_input_ar_payload_size; + end + end + + assign io_output_ar_payload_len = cmdLogic_incrLen; + assign io_output_ar_payload_id = 8'h00; + assign when_Axi4Upsizer_l108 = (io_input_ar_payload_len == 8'h00); + assign dataLogic_cmdPush_valid = cmdLogic_dataFork_valid; + assign cmdLogic_dataFork_ready = dataLogic_cmdPush_ready; + assign dataLogic_cmdPush_payload_startAt = cmdLogic_dataFork_payload_addr[2:0]; + assign dataLogic_cmdPush_payload_endAt = _zz_dataLogic_cmdPush_payload_endAt[2:0]; + assign dataLogic_cmdPush_payload_size = cmdLogic_dataFork_payload_size; + assign dataLogic_cmdPush_payload_id = cmdLogic_dataFork_payload_id; + assign dataLogic_cmdPush_ready = dataLogic_cmdPush_fifo_io_push_ready; + assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); + assign readOnly_dataLogic_cmdPush_fifo_io_pop_fire = (dataLogic_cmdPush_fifo_io_pop_valid && dataLogic_cmdPush_fifo_io_pop_ready); + assign dataLogic_cmdPush_fifo_io_pop_ready = (! dataLogic_busy); + assign io_input_r_fire = (io_input_r_valid && io_input_r_ready); + assign io_input_r_valid = (io_output_r_valid && dataLogic_busy); + assign io_input_r_payload_last = (io_output_r_payload_last && (dataLogic_byteCounter == dataLogic_byteCounterLast)); + assign io_input_r_payload_resp = io_output_r_payload_resp; + assign io_input_r_payload_data = _zz_io_input_r_payload_data; + assign io_input_r_payload_id = dataLogic_id; + assign io_output_r_ready = ((dataLogic_busy && io_input_r_ready) && (io_input_r_payload_last || dataLogic_byteCounterNext[3])); + always @(posedge clk or posedge reset) begin + if(reset) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; + io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; + dataLogic_busy <= 1'b0; + end else begin + if(cmdLogic_outputFork_fire) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdLogic_dataFork_fire) begin + io_input_ar_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_ar_ready) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; + io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; + end + if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin + dataLogic_busy <= 1'b1; + end + if(io_input_r_fire) begin + if(io_input_r_payload_last) begin + dataLogic_busy <= 1'b0; + end + end + end + end + + always @(posedge clk) begin + if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin + dataLogic_byteCounter <= dataLogic_cmdPush_fifo_io_pop_payload_startAt; + dataLogic_byteCounterLast <= dataLogic_cmdPush_fifo_io_pop_payload_endAt; + dataLogic_size <= dataLogic_cmdPush_fifo_io_pop_payload_size; + dataLogic_id <= dataLogic_cmdPush_fifo_io_pop_payload_id; + end + if(io_input_r_fire) begin + dataLogic_byteCounter <= dataLogic_byteCounterNext[2:0]; + end + end + + +endmodule + +module Asic32To64UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_push_valid, + output io_push_ready, + input [2:0] io_push_payload_startAt, + input [2:0] io_push_payload_endAt, + input [2:0] io_push_payload_size, + input [7:0] io_push_payload_id, + output io_pop_valid, + input io_pop_ready, + output [2:0] io_pop_payload_startAt, + output [2:0] io_pop_payload_endAt, + output [2:0] io_pop_payload_size, + output [7:0] io_pop_payload_id, + input io_flush, + output [4:0] io_occupancy, + output [4:0] io_availability, + input clk, + input reset +); + + reg [16:0] _zz_logic_ram_port0; + wire [3:0] _zz_logic_pushPtr_valueNext; + wire [0:0] _zz_logic_pushPtr_valueNext_1; + wire [3:0] _zz_logic_popPtr_valueNext; + wire [0:0] _zz_logic_popPtr_valueNext_1; + wire _zz__zz_logic_ram_port0; + wire _zz__zz_io_pop_payload_startAt; + wire [16:0] _zz__zz_logic_ram_port1; + wire [3:0] _zz_io_availability; + reg _zz_1; + reg logic_pushPtr_willIncrement; + reg logic_pushPtr_willClear; + reg [3:0] logic_pushPtr_valueNext; + reg [3:0] logic_pushPtr_value; + wire logic_pushPtr_willOverflowIfInc; + wire logic_pushPtr_willOverflow; + reg logic_popPtr_willIncrement; + reg logic_popPtr_willClear; + reg [3:0] logic_popPtr_valueNext; + reg [3:0] logic_popPtr_value; + wire logic_popPtr_willOverflowIfInc; + wire logic_popPtr_willOverflow; + wire logic_ptrMatch; + reg logic_risingOccupancy; + wire logic_pushing; + wire logic_popping; + wire logic_empty; + wire logic_full; + reg _zz_io_pop_valid; + wire [16:0] _zz_io_pop_payload_startAt; + wire when_Stream_l1123; + wire [3:0] logic_ptrDif; + reg [16:0] logic_ram [0:15]; + + assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; + assign _zz_logic_pushPtr_valueNext = {3'd0, _zz_logic_pushPtr_valueNext_1}; + assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; + assign _zz_logic_popPtr_valueNext = {3'd0, _zz_logic_popPtr_valueNext_1}; + assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); + assign _zz__zz_io_pop_payload_startAt = 1'b1; + assign _zz__zz_logic_ram_port1 = {io_push_payload_id,{io_push_payload_size,{io_push_payload_endAt,io_push_payload_startAt}}}; + always @(posedge clk) begin + if(_zz__zz_io_pop_payload_startAt) begin + _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_pushPtr_value] <= _zz__zz_logic_ram_port1; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_pushing) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willIncrement = 1'b0; + if(logic_pushing) begin + logic_pushPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willClear = 1'b0; + if(io_flush) begin + logic_pushPtr_willClear = 1'b1; + end + end + + assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 4'b1111); + assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); + always @(*) begin + logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); + if(logic_pushPtr_willClear) begin + logic_pushPtr_valueNext = 4'b0000; + end + end + + always @(*) begin + logic_popPtr_willIncrement = 1'b0; + if(logic_popping) begin + logic_popPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_popPtr_willClear = 1'b0; + if(io_flush) begin + logic_popPtr_willClear = 1'b1; + end + end + + assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 4'b1111); + assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); + always @(*) begin + logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); + if(logic_popPtr_willClear) begin + logic_popPtr_valueNext = 4'b0000; + end + end + + assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); + assign logic_pushing = (io_push_valid && io_push_ready); + assign logic_popping = (io_pop_valid && io_pop_ready); + assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); + assign logic_full = (logic_ptrMatch && logic_risingOccupancy); + assign io_push_ready = (! logic_full); + assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); + assign _zz_io_pop_payload_startAt = _zz_logic_ram_port0; + assign io_pop_payload_startAt = _zz_io_pop_payload_startAt[2 : 0]; + assign io_pop_payload_endAt = _zz_io_pop_payload_startAt[5 : 3]; + assign io_pop_payload_size = _zz_io_pop_payload_startAt[8 : 6]; + assign io_pop_payload_id = _zz_io_pop_payload_startAt[16 : 9]; + assign when_Stream_l1123 = (logic_pushing != logic_popping); + assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); + assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; + assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; + always @(posedge clk or posedge reset) begin + if(reset) begin + logic_pushPtr_value <= 4'b0000; + logic_popPtr_value <= 4'b0000; + logic_risingOccupancy <= 1'b0; + _zz_io_pop_valid <= 1'b0; + end else begin + logic_pushPtr_value <= logic_pushPtr_valueNext; + logic_popPtr_value <= logic_popPtr_valueNext; + _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); + if(when_Stream_l1123) begin + logic_risingOccupancy <= logic_pushing; + end + if(io_flush) begin + logic_risingOccupancy <= 1'b0; + end + end + end + + +endmodule + + +`resetall +`timescale 1ns/1ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +OOoBg4gI2nZAz8wwveQb2xYziCO/14ylivOE2CroC0KR1q446pg5ZHoTPlNXu9oR +FRdk+YQI93EEtwl0LJTuMb+sGUNIUS2ieLbzb7gpgkBuOgUljkWzXsN0p2S8f9nQ +QN9I/ZlxuRJ+sjdUPzEEEWHeUFIamGV/bFLJQRvloxvTvwLpmavqG6GhWi2vdXHo +7WqQVvDZRXw2M1o9dR9PdlpAkysf1TragnGQk5AkUZ3qOXFRHbxOhnJyTnaE1GyX +Oq59frbbD4+rLXSfc5EcBvIcpDJOgpRiCtikYUTFmw45b5M9gLaBYasEi8c7ZLIR +hQNrovA1RmOBbD4PGOXIrw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 752 ) +`pragma protect data_block +om+C6TrXX7WvV09MgL6R62R+Od59uPw5eeLNNbNww55GLUXwwj/XGluwdblYZx9I +X+OGjlllzxPGhddDes1uu0dNKh2ykfPsuWVHff2KPOJBKoYeNx6pVHSJR6EuePH0 +AhyaQM8gII6oK6SM94NjiC9BWcfDvsjfNZytp9D451ZvKE98e0NYabL8MIo9s2kV +hXffla5eL/f4PK7O6Y5XPFWrEpZtzAnWBDgKmEsiwAaDCKqGSY4iiwUewIaBv+no ++Ka4H3jnDmn/kGjkCfbajYK06RFHwFFJlgAzE5OFkMY8Ksmj63sVYM69D9UbM9DF +niOhc7FJg8UxSMZivgX9broAWkURRuJv8CeV37kSTWQY3ZEYK5YVCUjgwJEDCYju +ttWTXEpc3zXD52bxJep6OqjHO4n3brwnDjGeWrfb2IENd5VuXBspvMZ+2N3dGmpM +2nyNRZa7erdjUbB3k9+o0Efs02Jvj7TCsviSczk7axZYkJZI4mxPF+b8FStXCvEB +LXfZ7zKmlAcvi4QhCJ3anblnrJDeiGvv5UisphO/KeahF76MYUcZZi2tkiS7KcqN +BgGiZEgzvz6q/euENKIJAJI7Z+YoEOXDZfFoEW20WgSe2LbF5HK0npobYc8MHqIs +Pj1UIlLucUKcAg865RSblbpeLgNK5ryqdU+QOwi1pM8JFsgF48JfdVWMaFu9sWdV +zMNn55XZ4AvwOAnua8nN1fZ6mOpwJX4Ebii/zW5S/6Mm0kbhHkqZg78eXQEQMbJP +5YUFRgm2EkdKkxUmk2qwycEMEqLvXk/aOg48zpGcLAp9LwMjFRotYNW5+ygxGGQ9 +WR2CYo06vLomSI/uE7XlTHHUArxUtH385f1fq7V4QRutX19Wjq6GyG/YJWl2JURc +u+WqUFTAylQRC8Fhb+BPUoP6oW1YmiFwJ0LDM6xFkFWk7by/1wO0DdZV+slmdKR2 +1sxJAK6dd4yk223AytIzJlN7eZ9pmgJa3n4/X0QNDSY= +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +lvtXQ11Z9LNNq59Ajdesxcgo5CSVwrUQlGzmWsibhgsAsHyCjqyj0vMRSR+QiEty +/yyi7z21Q4K7YH9jOeDy5ci704W9tiZzbY6jJLUXKIB8tCJnB8DHWfmPTJjac1+X +kAprlwdHkFxurVjCyvzvpsDzl+7qd3dfEhaBAOQTrigUU88CdOFxwRcXpGn8arty +jpeOR3kDUSTf2tPHovV/i7635KJFX7o+tzJgPU4pQpgxBuHNN2b2rUy4eZxHS8/K +SkBE3iIjiOUYaJHZOgUGks3PvjFmmj3eD3ktt+v8nt/ozHPjJ7+uP8/p3i+qPyOY +4YYq/Ldon1lQeJanU4emrg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 800 ) +`pragma protect data_block +LXRln5CGH/X3ZcC9f1s9GTxumdb3ijnQQ2FPf5CLS40wU3FpMlOGzCsOTBaQ0U2F +9oguD9QGHXfbD1Nd7PairdinewSLKx8JR2NJDQobGByPc+ysqVmUtvuhRNKAl33p +T6XjMlhW+ErrSsLQLWyzVl/WuxdW9LxIu0sJtoA07ny3Tlv/mazOJBv/qiQeV4MN +ME3SEpILxBCTIfkZTacMxEgSQWExjpebTwhrH+qQ6BlH+G5OLRJkwgGf3zlGBAOv +WooRGb02wwE4zZT8LVq75rMiXDHrLTYLa33sLqoXQlIBMH8+EyVUyg803Ob8M3T3 +P0pOvZ3YinKmZt0udsR76q1filXw7Vr4pNnqfY6jN5Tcx4SfVVOrAgATj0mb6yO4 +PN5I8gqTmaiF2qTM3Z9OvVEH/15Q+L5BIfkaD7NrXvexgwjTCbQZAqOhro8gUp8I +0FU85AMYy3vh0GId10O0gj9uIqlBOCzpSPp4v+vxYL9gXe71r8jkBkx7xWspnrlV +reIqWJt6b5eVQ0Evqm0zoWTq1f3KG2QlOcv2XRxexmjrZJxN18uWjtHJT79Z9HdF +zD0dyC2++DANYrfY3k2Bdjq9ul3WjDfIF1IZmie5nqpY/Doo06O4BvzJma47Ridu +McqvFIpZnD8bO/fJpsHFSTGOJ/XgjTD6L/mAUMgNg/xywOohLinUAFv7btl1cos3 +11npbTSOQo68RlTNeyZWtZ+Jl7ymhhjlYDbUu/vXwSN4eZuWWwL7ZggynnqMSRC6 +mkr+GDI2YWg+2zYAGJ2dbgcgug8yKlwu7pGL1jXD2NIGOTpSB4Za71jBoqh7baly +3w+qb2Jpj3QpmzfCsMJb/QfVrtQ9pXl6uRnvN0hp+MM+hkRTZmW2QcHa0qMk5408 +UYZQGWsUBKVwB9lktWOt7QSXi7MVPzzHtwB0LM0jAYZGP9JXj5w3GXjKQt5lfdv8 +7fEoOfhB23IpJpo70B2ONKCH6eIA2BI9kvFO0JaafaohQixe6ZP0x6E1H9Uj1d8Z +uBMxCVtI9jJ+5v6FXlHl19YPtiRAPje2oBZ7f5kz7jg= +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +YZcxj4NiuiyaBjwj3+i08UfgElpJok6CAPrtf/VeNVjKQ4vA0nsIxPTauJCmLxEk +n2CsXLkWDAo0vTBJ27P2Gzis+Byuf3ie2/rrt4Nsk3r0oYiZI+/ne+066AsA5vmj +nqK12/q++uVjy1BnXRhJWwyJxZPo+9rnGQRERXZmgh+QZ6ejYS72L8ufrSK4hPmE +2/vPW+haIsw4iifrZaqfmJNT6OA24BG8ZnyU/hCNVUwzybiZ5NNgyzuo4U3x3eq/ +b3ZP5uRk7g57KmnXDVio+dAa5DNl+z4ImILcjLDJcqJ7TBRa26pECkiCFo/84A3K +87RH6WBz+a0EgK85kgWFBQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 5808 ) +`pragma protect data_block +cFcWPJSU3e2Rdd62+/WBbQ4M/VpTw2qhSBMfL8eYbNpdXnkifLxwuRR4FoMccpQw +e8cxhwO6YChEAaXawYmul06piurwYwL47Mztl2oLZ79DYbrxpVSfHMHkHrhJ5mKK +gVdWjF9ihtQ0I/uuaoD8MUo9+0t5a1YFFaMVzO4L7If7ZXR+qwx/Qbog7MTv0eGj +uJTkdSBLo3RUC1eGaDV6ewUTjtCxeVAtmeQLHVPMGXQo7dkXXuemALW8ZmUf/M/J +6xCWZdr7rAHAcf3VKTWZipGdIoKTAhEilZWZLXyyseviBUQ8V/TEKrhS7ei1SIXk +xoJdCLu3HWmHy3uptWwZl0difB+wdl/wAv6R/ngi21ZH7ibyk/pWrrriGn+Jblkz +xs5W79JBRnkwGqo1eqscu7nfAK2BUVdFzLn8ZT/dO0Pe5E+/d90EAaj3PuAThL/P +SiB+KqQ9+iRQixjGW0TfGW9ux+CjpnfRDeugd0qrAOsSAVg1TOcYn39+na4hHEyG +PpshSwYq1D8nuu9ZI1MxuWfWlz/6ivTo7hw1zz/WWYthn8o/X6Ny2/biIQ15ORPT +0Z7dtsSVTIBdQrXRy/XMtLoJ7uGBzJSJnDVvs3DJRAnpJ1jfc0xwkKawUzceYsSZ +bRWEEz9IfE0qaifHkoEa0S3wNWEm1dgdMYCBNN7B9OI2gAu4JeU0qcF0e/J2uH/T +6MK0jjtpVX6dnXPia1d8cwVwyLplRRKxaxcieUJ9F6wepJFrE74A8qhR8Z+txgTt +kqO7UP5P3GzRGf9yzQ/JwS+CJ2w7DIUib5Sf2NKz6Teq7xaq9DoHfFPQSkFdKUjq +n4XplDQF50EYpPFMaFOEC2LXkS+Eyh0iGgLkjljsQpRK0Fh0JtyBrHVfWdVUNPhS ++N6A79h0sM9NM5WLV1mwtKzD3y7tUFglO5d8+NhCShTIWW2ETA4Vz0XDh4vPWqAh +cw40tow4feIp04NuP2ORuV0mrNF6SnsTUrlb3YOs/6UmrcNWYdctOhtCAGOYUqMo +4p6Qwe3NGq8BHO2P0xU2+oGvlhZToPyVrqte1UDyhT4UTm0dBTZMsgSF5krXehJv +r56j6EMyhcvoNthZ4P6WLGIZxaGrJn1L5vbxIOV6oDpghbOaZ4gBUgWHoR6jGFRt +pzraIt1Dsr1iJQscTktO8752dsbnAjnXRgx5+3Oo1tgePYu9kXZ8gQ9WvDK1N+wW +T7LCm53NEmyeeBNlDjjKz3fErrmFDatA5f+Ipbq7cAXO70rYVDLhxhus5TkKdtRX +gVLWCp8XXvCl6h43r53iIj3I2jZP9Egj6Yi7baKhVFyNZdI+b/TXaJyrQJasmWs5 +0tYuEcbMZC7L7TAU1BUerxft/4dCnyCssXB4PTMLbkrccp8aRwuJapyQ8aeVl2pP +Aok3nBDGl9fcKWG/2v67T4hbuvKHF+W0bBVTRqw7z8WZBiA+6OH+RM1N5FrOkqbG +zCdDk8YrsKYmiay40JwD5Wa/L0fyawbNITI3LaM2oAMVCPa6ruLYSIap6LzlA9Zt +J9lipWnZ8VXO4wAPwQqAmFmYiBnUVDpmVY8mSAzPfw+t/aJ6xJYNkbWmJsDgdbS2 +l8qxsg4lplnwu6fTrfCKKLv/aakRZGp0/4pPXijvtG9yJjXYTjxChoDgsEjClxPO +m+SBuMavJPSJYqRggaUMezTjNWoFcjcPXAdnBAbIqWRzHlhj00Q9OMiD0x1txEdt +Uzyzh6zg4BRkVHDkPCs22D/GjzFdaWZliOIcH1GvxNXEuEth6dJiC5s+3XmixmX+ +Ov9slVL0wpP271qT8GOIDYX1Lhcb6ezgNxansFCZmo9s3Ape9UzsSJ5HEPr3wCgm +uRLCG2zvHZrVQ1HLSgxnQsmBv2evMPPGRh7gjUtmipp4tDU5QJRSjP005YbneJXm +OsH7sZ3ay6xgiQfvTaeY14dj46y0xgv5fGvw3dZcCpLU7+C11Z7i1O0WZ8g2xEQp +YJ+8FluDVl4cQpGOsVICKevXrV60LJwhjam+TzPLeP+C8miA3kRB5z2tudLGiumI +X9X1EYfiV4j9iriUsc38qRrsV/zK9hbOSUtMrMq+eM9QJ/l6vo5OW4mMsxFR6alw +2G1kDOGtO5pZOm5NiPrLDqAwRHWsWND8x+sIJRG2sAiwTakQBip2IBsR8kArsS9X +0PmS+ltl2ks+7v7/MGJ89UQHMgov0Mdld1O8mz2BeFf5BFH2q3vQHBz8JlWOOGIp +neG9Z+mdeZcYOH5tRtsuMlfO2mdZM+5n7fzVqwuA29S//VlU8LqTIzuHipzQ/Ezn +6V6NeFfr5U/ra7j18kaIK6cy07yDD5ethG8l263qv4a4mdxd50ZrbyHAHwwWr2hv +pm7v2F7Ke7j4HztA3+ZPcSx0u2tQC+YCUWBLjcdR5Jjtx1P+USkO3YXulNR44kV4 +HSQxkuR0Y7G10RYpBGRQ8eS5pJfElq8uNMprROBfqHSbhQ/a9dg2XsUj7C+XxCqR +pSTD55t7QZZXxCJl6mtcLSoofvk2uJY+OhFjiEfaeug52bbK2WqVQjx74ReEwgAG +kDTSwvOvAi+KAAAAVPyKt2m70jBh7bZhQOnoqsq4CwBY6jE1Hx1+yu5w2M34fF9O +0MnrKfI7uBrQRZ8Z4OCIMMpQTwq0EoL4674pywsbO3E0R0PXlWupBEfCG5/4u8SC +TfJodFq2Fski/ix/F+tBDnBdEt+6GXxoRH+SVA3u9v3iQ16zwIJsz31qpXSEBDks +/fPrCGKuqFq4lJfJNlh9pqoQhbfUFCkLzay7l/GhK4jDC+Ugu+D0LRtgK/ieAkUi +q1tsR8hC0xAadTY/IHsmPuuJbWIlCA6NwiDAdwit+KVSg4cuIiiwDrOI+5M2+jL4 +QU6Z6Y8WqCapDUgx9WA4rUzRd3OFMLaRU3+9lqQ0PBVonaisEy3siwmE7s5VdMzl +9xtyDPHJ3jc7zt6ihuU6PQe7ev79hmXof7ZR75hGcrvD0wm6tYDvXsUAoJtKSb61 +LWfT7r/NTAJYb+LyMDAWh0/LOy1fID2QTBqh3Jnw6U2aSCbRzANajUgbygHcUhRe +hOkWaSrLJHlm5Ql02m4ziU+ei9TiCPw0Fpb5IkuDQK2jKeeKMGwjyAIce7PDBZli +sS46r0/hcyldlYekuzZf2rSMnYHYr+K1J9r99A6+6hNyv4nO55tGEdHhHjex2rd+ +CZ16y6983/cLk7PSlQzgKKYMbaXJ2WpDuWUL2s2/muX51vHfUpxH6P+t1UG+xISj +wQ0RTGC+oyqkHMrO056kjkM5voJRKCkfZ6dC4zTqVSuljx1d6C0P+Po9BfHgnoXc +d+d5JrOaO6FHBz+guTKJ93gFUx6QyygRj3CE25M0fuLnw2m0nvj97ZJEVbCzHfBg +qWfK3dYEoRz/gJFnv8seNuE5WCTsqo7p0+oKd+sjZ6hu/hJtLs/QylK7x/puX7pL +E7PmrNinuxg1lftGVhhb9nW5S5LNWZWPwLI7ZqjjpH/5ZipvEtY5Kt7oPPKpWmq5 +acVtItPbKthamzWIGFnTfws4IDsFkQ1C/pt9AdfkH5ztC9J9GUsCfhcwbsV9328Z +Nx1WemRFnGF2T7n4u0F1XUiu3XIs/V29onTmSeWPr8RHvN5LA/StQUFbA16E2Go0 +3y7C81kMEHJfm71V3MVLNDepWWRq+OajTkZ0cX98zMUVNAl4rHn5JLZZMOOm7DYL +DnmhZPMrdoE+ttjsKGloqNegGz8YE3xu2CMhtwPDssSJYoQcXFBnt93GtKva/iBN +XC3V263AJ/JfbHyuMVPZ91n2mcgKtinDYKAnjatNbMCPBlQUYUjZhmAVIRHzEue6 +dxsdV9uZsKFrDVHhpNP+psjIHmVSpWELQD+PR6FR1MqNOEr6c7Kg5MCIzhbp8/OC +kigDpwiPTSwTVLQVCQmYe5pI1yk3IMBddUjFI91pJ2WWP46rhsQJLoWeYhOlrMdJ +tUONdPLNO/zYm2QhMX1Hh3zl+n1TDZlD2zJopIhzz7m7DLfMQDcR/mnLRvYNYv03 +xBjrBES8rK3YVPrhEdC3LQ168g4L5R0IuvXQ3Gv36VCjVsAxmTZXyu8RvUJIMIJx ++MeBng6xFH3jyuYxPsSgrPoBwOEf7kjBOFOWLYvpQI/EmsoJIxm/92Suo5lEGjm7 +qqgFeoIi7TxoDwyPPcIuWnVsQzzRj/v3ZurjPJUxXgYvFqKdC9Kcjngzro01g+ut +yxrtZq1cHlPII6YRvcP8FO4G3t0a8YffE9ZRc5+L+GY1a5EOxsgrM3VyMG3RcWDD +8vP4Zmlokf1bE0L84v/aEhLo+0uyie++iKwL+qDU38X9CMCyEpPmdt6VtBYg5E/3 +Wtph1T+2A/dV//PAnYGru7ziH/GUBh4/P3RbN9PCmO2jgk1arIZZcH6gn41YvkHJ +8PXJ/b5uKdVKfdBft/E38Vm+QC5DJrOe3YoWH02lFdvYboQj54yNARmUwqNvi4gr +wUez5Ms/MFXQv/G/m6YmYv7hJQ7tVaakIs8lOUhHAhLZeF0KLQA4esVziQSgTbEy +2CbtBQ++OhNebhiq8ibJ1hOvpXof4eDOxWZxJAZGeJFTJxw4N9/z+mSvuKuFvSl2 +ryorTTTvjz0yQY360Y4gtO8aTr4dCVaM2PJfgEy6+s7zJZYk7iM4D5QaGDeVtWZl +RUZAomurw5aBuDvqd/kQ0EDGmvklFKKTGUKM+OfLlYJTphgW5bBbtGXb9KyWcW5E +IBBEI2VsXnb00iRXFYZhdRuXBq1UWWwgRp4P1QtaiFkv1Z6REBCmJmaOc58m1Vrp +JXMHktc0BIqJa2LDr6a5KMX9gSbb81O8TqeumbKLCpfe8OLEnrKHXk6e8XAPlTzp +XWcMMneWitPUa90YYb1tep8V8hPuda6VbtLDJQehSMhjJqpWQX3YAjWshdmaZSeM +TZNtWSpDz22i7l8gOb7JCUMqlf+8yukpMKmt51Mc7rD6ppEuWWIQeHBv2+5ymZXO +Lw9lt5zWMQPe69EAJDwX7bfCmxlfkP8EI+MGft5YBG2gXChJo2DVBjFOPJS7+uUv +F9t7ZOvo9K5FlXc3Kpi/BpGYkfChX3YJIwjz37bb/pZ7IetS40OtLlVV59JV+lbi +2DMNNlXdZ5QunrNUO2HzLJzkny9cDTiYkY9rj4D+u3QFxaFiOr6Xm/vCgNdJpGcU +033gGDVBLLjTa1FRhbPwsfM8oELuGAoxlyemGiQKg/kpSZypLUbq1rf6NccDfeEo +mvL1KQo4mQeD+4PMfADDtTDrgTo04Q0+dyYY9k22s2/rS7hLjbRym+kvsZLekG11 +buSVQbMAkZlhVW1Iu7gcQdM2bNT6RCmE75FMI7vn7/jztTgPV129EPmee5laQNXd +GHnBcJ/dJ0JVwoBSvi62xer/61Xr+fNVlUjuJauFn/PsjLJZZsIbQ6iC7gl7wFaW +Xa81QIjPslAzLVq2OOCBfjUzhTWXE4Sb/BAbmylYxQnml1NSS6vnaTbji+pntP68 +pUaliLDS/OOIza2PlYxHVG3zuH6b4+iQ1bFWeJS1kPYQSBb1smoVlSMeWIp/D32r +XIGWcCKsLzpdP2bMk3FfM8niIXjn77DyPNej9N+hS0TqKOdKLAHx0i0kTWpMwlH9 +nhhKvfPxjr/oXwPfBapV4sjOXrwB50W8t8cA650jPWnQLv8SfeqjIBcocy9teGlF +3R7DIDOlt31yWL22elg1zoEJh50nvSbyZAhYsplQnGsUE3C/XfRDjb6O7kpBtCQJ +AWyoJ0wbkimpYv02vSac0yzTuxMrhdKs3aXuWczN3I4sGuyO25iHqruyO2CG/0RD +dJejxndB1DFwJ7JVHy/JaRFh5qmxehOVLJBmaeqH7GkBWvbnQSwoei0LN9qL/LPK +9rcFAMy7AtD/fXqe+IXxtzdmEdteo8IMN+vhCm5L9gxtIU8wCvxBvhWOxYo12NIp +frxsi3IuIvxnuLg+RKGfOaBQF7v5uDNkYLHBmT31zx7Ak1UAWnFcnFPC2yfC/qrA +7ZrIJlCEoigiNr2Yi6A2Zs4MSx9fMWgimfamgGP6+/ujmEQQZuu2xl3emmmc+XOg +Tnv6aQPfcQ7mfgJ8XZH7x5SBf7anOZ5EkiAQBRPSuMY6LwjD2cv4zZRg+ZmidxEH +TQ6cTMB5V7I7JvKj1GKYi/YtmULWziSI/RrI6bO760k96jz6Y4ni6KgdfQkbMXya +EpbqL+YyQN3qYLcjxFuzboZMrv2GrYatoiADyg3ROQ5cujyrOkxuv3r8hk5xv5et +O4lyBPRrC0wjR+edwSiecQ0Y73esrIU1CuoVV72gdLWfad98Li7pUUiyIn0mcfAO +MHas/cZtOU0VGILzY6ExVkizMDHAbiIUghmu3lPyMHGRsrAP4RYZHHRlAOowi5Sb +o+h3D3eflkK5rPIB36kDtMzzuhq1JEXr3Zj5HARBXnO57KbuoOw3GfvdK8g498zS +axGgz0m4OwqkwYBsuNi9y1tfITOdtxvjue4/mxzHLUWdyBTahq2Gq9UO7sPPb2F2 +0DAmbSrScu9S/dnZ1KQHx6rAWz1hWzx7oP0MgzOLJ/moyFGi6ljVwuRlxJEFr277 +SE3wbrkWgw2fBZa322gBujMzWTxx+L4xLma2qcdyJ2JM0/mKTucy1315BvnQA9dn +pJ21mZyh6XH4g5HmwYOyEFicj4YlEWrDN5ptFUzPjlgIYcH7DIjZMDfBCtLhIS1p +EwMqO7MXO3MqRZs5E5PiKrduY04kF41aB7x+1PSbRO47WHAVMhnWeCS4QzUTPRaV +vKo9uVM51UKszmxhXVhij/gi17Hml4tPJe6FteD1jP3LswycfifeDBgw/SCmdbGe +yP9D7xd4rLXtN2TBcyRDjFc0K/5fzMvxlWYTxrz7fdh5aLusbBjIETYFL5y0qOOx +uNnfezwVGFr/7Bp5HXrGwDLHBlRYOu2HrFhkrvoprISX2qgSHeJFL0kHH+2+V6mK +w3kpDJsDZi+QXVeenKqcti1txxSg/MOtNZhGb2eieYo8lI4FZKtQCFA3dWoeGjuU +SpZTDNzo7pIHakf4QUqrYIE1gFn2sNoCbBlx9CDx3ks/PzCDu3uqakh2O093kWQC +/8RxJuzcN+TXoLzz/H0BsGC+1K+Fo8YwQnsLj0YoXSBrHV1hoNBaDwo+ZdQE0KwT +B9huJ2kaIWOG3pej56lMiEiB1W6sQzCYlyfJzt0WCnCRwPNmCa6LGnABzJIYNNhV +SW+ddECTo6TgtdAKH0/k/QalAUjFJJcSRoWO4pgiR2yl65NSOH8R4bt3eMnHohWQ +aNi/l+UX/thdnaAvCZWa5Pw/coPPjvmwvGStTXXrLeLCiliL/DvGgcKSocebaki9 +iF38kB5/CrVvCeg+3G5cRfnjEj9Wcg20C8gRX9wyARDWq8IH78NxBzucmaPZjZyd +eSq09wViYxsMHYxVeblHqgyyzpS0sa9sqrgbPKIW1NtWQLpC7GQJ0nBYGbcaV3p1 +B+H4racUuzHzTbLgEkCXxnL4Iq4+l8nrao+CAKw/iEV7ZrCclvXRoDtOu0CZqBRz +8a90qCPA0xTDBSCkFFqmR0gLN8dKIj/k6fMijBRDtzk6xXqF1XXdYt8vZPTK4oMv +hOtL0ou35/o4JzD2QI3GoZhK4tx48gE9HZm/6pdHfCdyr6Czt2c/ravHkJYAyt7N +dVWd4ZJSsnE9oGXWqqUf/m0Nwilt86ouFanggwNJQzqBH9nAs7z3a1Ou3ML0wOBp +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +mEtbV9EGXcpC/6yko1/E5fksxy4umj6Ln9zdp/k87D3GnzU6MtGj2lR4GCbisMd+ +Rbqmu++LZV+2wB32AtLnsLppKmsYhO9jjXRe4xPQK1niY8CuPx9Fr5cd2zq0iVnF +bFX+yY9CqzKEM9Mvztoxmllg6ROMAs03PPD458s652wcEEnPn5klZ2tYXy1JQEyI +wuK0EmtlFp4B+IrUHiZZJoJBxmxQCtz1uIZrR8PF4sBs4OO9W5NB6s4hrEzn7Jkj +sQlyyW4RgbyZlTqNt3mz8Zwu3iGowx4s4CGhhIpgPPWdlJWY0smeNKsbmJXvOn+j +9uRi9+ghgR+LTAxZo0Ibig== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 2048 ) +`pragma protect data_block +HUh4J+fK6YFhzi0NBDbJqMMdiOtZRe6d8QSG4h9yRGrUBaipIeawvKRtVUjxzOVk +Jrr8kMcAoGyqVG3ZA5rHQbVbOeS1eTWRktkUtgQJkbXJKY27q+jdqM6STe5Xyk/V +bUCeN7QwspaKVLlT+Z1OpcACekiWFgy7fiw79LHgI/wAeVv3w3YXmHvsC48YOuDq +XBKV7gOooz7/lzeIxEL61rgQfg7uOt/BwmbcqD0nzH6NRBrp6AA8vleKetSB8NMi +gRNcQ9ZHg1PxqCxNVVzBmtgFf0Cxn2FdzcyF0BfmBA78aD2dzze9hZT5orFv+/zV +fEQhjV2iAj84cfyH8tSIlnkWMMsYQX4fqdifZXOUtJ+45+uZQPkJ8idEnVj7k8be +zniyfaOum4sfspPnaa1fdpLwUMZQyOW7ZmKD0Ioistig9GqANK23zV43QKe/bexe +jmqhXDJANp4rJ2T23FciuAPkQGm0zeomzIgpjNFTtemGaDrHo2HYY+cpe92e14QB +0glxi1M35cP0FLbHXW4yFIjQswOFRLlY3/GbPvfn+9yJkzOjm4vhq0w40egknNfQ +2Np7SbqTtdRJDVnPZ2oo3UJkBCA7PM8kce1i3XmeIAFuN8m/TMKYV5WJQJiOTDyk +0XVcz6pahWl6rd2HwMLQgbpSejPudFTe3uLHS5Fi2aG2RTpHTYSCOIkNC+DovvB5 ++UzBIUJz4qx546ybA1OWuIWwmUl9BQnt8cxU6ARH+Sny7uRYL5X8RLR7G5qlVZGJ +gs61Eea2+hHgdnV/PJAx9HLDa0t6Tmwq4P8OD9OGH7PEPbPXY45/MDa9Ch3LX4Hh +HedkWuG3ryOYohdpMcmCr1zkojZ/DGaL7eqMKW7JprJxiXGZdoZ41aXt2eiCl74C +TVxPm+U4SSHQh3f0a78LWV7U4aSHb4SbAWaX4mUZE21RaF23DmqlUxuBYn/6+VLJ +SwZ8aH/eKwtPkXwaZ2gXtkGOMxbIgs/GKLRQ0k6sr/EMWEgYXpgY33LNzudM5u7q +XyWfoJMXciiY5uXUovD88q+1Ni3FUOD/brmf/3W3Hh3Db7zmkDcWvT1FDUDcGXep +5xdkPwBEmRaI8D4IYTVIr5kv+BsOFOQZWjLyShpJXPMRJ5g7qxSyUUhhKEgWkt5a +ZA79/VsXS+UQHfIPcWK38VPmkhnLopUe7Y2IoQiDxJJ8gkVfeNP8CvA8VRU2UMwy +SM+kjbARwKj/dLQ1GSYNOwEsTJ6/4M10Bc6kX6DCBxFjqs8dfN7LatGAvifFjmTt +Kdjb4at2888iGfE1UrrsE5NhETXXXdaCLYTk4n+vSvkH4aO4GaWq5el1NeZHvZ4+ +wFU0e8qENFYoZqM01NVm8ij5qtfSqEhuhtgEDhcYc9SXl7yoTgHQ7K/jG6dvfRx7 +p/LmrJj09+N+2ggcsnWOW7gWem7mLad7sAVHlxmYWWQCqU297iKmaHLaPBiqdw5z +/LXYK5ssju8oJaRyieEQFgD+kj6fZHoskYnyv/GA+PnGOkpyGyFaNZ+ZCoVfQWj/ +jGSosBOeflbi97GX9zcnz1kb6/XGWMZO0TQhRjQmLTECtusDlG1mDs0DVHXybjkF +N1fg1l4KuoOI5+sJkqPKAvq0LoOA+1hNUQ0IEMj51stxOiKdiIJV8P2TjFlZJYLs +YvQyBBeYej67sSKpFHPd2yrOtP44NNQAEpvjPt0mKhJXnzSN2qZvbKSBOgn4Sbk0 +9i4XJ0hXqI0JF23f/zw+aAlSGC6NiAIm554hbB94QmEyU3Ow4dojWO7jzkvqfjBR +ozkcMQfuqsBof3gEjovlJSAoHAvHK2w752D+xoLdSzT9iO+UlFCuzCAXblzpQCUO +Ud8xB1E4fgXx0HBegDqx4CRR6Levsch/Mldrxb0JqkgJ6Bkl+FxzmkjwaoYtwtZP +kCZly6WHPbc9D2tAJapm4P0FWFDsnBbF1ZmEz/aWKKkNVy+1P2RAUjChcjycAfue +3wygkO0ftd8oRoCRh2sfzZqJjip2nd0U3YeMhZMV9795zTA2S3v8nv3x0kScC7fK +fXCSZZtWr1J6P1pmcWOTd4f52+Ym5K30EDmu6aXC7tlnUYhBwP7zP4nhFy7ya+dy +eM3UvUd4oIPed/r5rvmF3uJycmC1ig9F6BCgKN2geT3+vi/bSD7RVlTua01tpcdT +dci8sQENmUG7hZ80aeZrZVmP8tWroI+a11/qAj6//drn9qo2/YnV1L4AWvtTnS71 +nbu8cx6B5LhuRMglPXNQWcPdcnqXG0Zu0WLNL5mbn/xjI6q1ksl9Ket0gyZiF3vv +u+c4jrQw4v+36b+nRby8L5rMDL4OdtLrg6ZJZu+nDIOpW4+XcKNDmS3GjgM1gBmI +Nniqq8O1a4Swei4JOAr6G0AJLDNZ6WZAd/bjUOFFg30a3+h9PwVuC34XI6XH1Y4b +nDDn6id74x0Fo82suxDTVUXcvLmO+YunWR/r6EOUmfFAVbww7vKsu6sGj0IVjifm +9sx7GJjNbunSQzLwcSQDMryZC/E/+uzBK+7Rfkynq5XTDPJlKTWxwsx8PmXB59DH +xR4MTfIS/h0JTnlxZfGAuHRoIccuaf3n3jI/OYEvyczsoV8PJKDSXtWsXeL5Sby8 +2jMXA2rVgYqb60AVjct58Qv2VCJ0FM2G7dxkENdAOwFb4yfKL+pynRvPYg6Q9UsA +1lGiJmNiNjrOEWcgXi92beZF2WZDdfs7ZIw/qwVgYuA= +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +J5uwiQrMgxLjAj13SAy3vsBmkypkUHuPQwyAno2NI+dh6ADhBeGoXkLbyWfXNO1S +b05RGEBtTRrRNY6f8sSoZPBYR58MJ73nuTvU++VlZj/tjtveso5nLIb3L9Vkcd9u +0AiQMLa2c0BwzGlJOtCwvWFRdnBcL99FI+19wu3C5WuQGCEmRoMY/ws1Iqm37Kqw +U1xX3Dwt8W6rsiXga2zZB25WuvJH7x4XHQfNqjaLhKknhS2JfB26tukpUQnAWPnW +dD5cGa9rs9jsi3/A7lx2vFtvkxyCF2QF4w0Gp/PVpiJE/shh4MsCHia43FXoq7AA ++ky0TMuOm0HojmlyU4c00Q== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 8624 ) +`pragma protect data_block +oZ0GTgaY1jFft2IB2hWTqNnQiodJUwzfVbr6akyrVbz3jFePptbD6OJF+iN40U5m +0daNATJHzAAhGlugA6j6S54r25yU4y/t7UJwm+H831ajTDW4z9BGSYJz0wMNw3ju +4JMlN5OQxPLh+7lN1i192UAOe1M++DSrXrfGhCwrZD5RZMDC1UiXGtimTv8/5oQw +Zmbe9WZeFxEX2A+HofUOuEdMMchLziAg1HE8FW2cG3LL4c4Ymco67/+jdqrtpFIz +zZymAyvBPZd4u77o16AitfasOtKfKhn+wk4u/BvRNFNcd4x4N2vNR/b+MOp2Oz3v +0mESKr9rFsQcz+nn58QRO87AqKETfMbvC+H2mgLRR4jfdTDjb5wd8a2OAFIwdZmj +Dx9HxKyGAkbs1hDz25qYZHEN86Uok2UN4m4Y3x9edwjdprSd7e8hwzD1Dbfbhte7 +akuJglUszDNYuDqmJSvmZT1yE9P9Z+BKj4krcs0wQ6bRmPOmTC+v5pm53HC46sms +lwiy2x2BjLpyWJXWWBpmd4tHBpXJwy3xhc+YECnyGwgeTP+IfjlyYuSBw1XhjRMz +xCRuQ8ERkhThmquMpedpOcQqNlY/eOSXsaAb49b9lZAzJoYkysUJEugj3acXr8sQ +ixUwQAYHoZUFuf148eU75Pe5g46di9pJ/tsT1Lgw3+sIDUhHFVi05vsHop5EqVVU +tSyEF51g9pnpKYtniZUSC1wblp0pWZPr46kjDMQQf+TTOReFg6U9LVNkmNt7wXkL +zSl61xQdDP2SzIlJ9NZ4LuWtPbCv2phM95WMSzZpwpibh/r1RU+0+SACJCJ/Xv8I +m1k8xKAP30qKGYbwKAeL2eTizUNqxHHeMsikd2d/pi58Qn1NvtwZXvfGrpFdM0Pg +GIyj5BUMTpyDBODwpwdqtZnoOhbN8E0nu5Y6j2kbKkb9jVh67+GZga6BzDZ4HVTX +RexVm+BO2zaGk64cV6WC021eEauuKZs1OU/57uF+NrIN3FQ5s6ST+JOzT+lTySpG +9KeAaDJd2WI78e5ewytrhbE5XPo8Voi/kInyy1NnNIR4rOYU6SOxd7V4Jl6xaaqJ +c7GLAnTCSZn1T37LB7gV7fUYOigOX86fxTc8xD4TXRibkNODXeKCjE4T1j6RL7+y +hYLDCmysyURiXv+EYiWhdFESEYFopkex9y2YN5d55noXxp+am6KfhTVSgzMRD8+1 +Iy/Z5lN6GqPvejjnHbuDkxgFdDc0WSxDGjayOyExTprybFJ/HLOLf3m7DsPYttHr +5+wMOhOryD+bpWuKdKS/J2W/73GlGVWJEaK1uhqJXDZyBD8TgGldEkJuqkAcMLC/ +h3EE3+nzwdU/DX95k9nA9qkceRyCseSBnoC6QKv9IAwlM7f4OZ6NZAtO4h9jXOYs +7TL+F+3bh2TsZvm2rvZohYLL2wvVhIeu0NeP+l9ypxV9JsHSb78svd1hSKEfyml+ +V42rWWi+RLlNptR9Go41mh0j/v3mH0duJWr+veqtiv8Qcctfz5rUO0Hq/i/yhMoe +i9fbCPultUKMjN6N0qUL6YPA06jmI5fKhan9cH+f4YQfgfLzRtIpn8tzdS/Keuh4 +FIDTB7MHeM+NopyfEjmU88OPSRzmEEQk0k1SJcxp1ltIf6xysYLxoLJxlHyWnREg +Kejg5ynZd6bLMSwtelBerOPj0vGSii3Lp/qKowh7vE0cbs8P3qFFaHPIv75Yg4py +sk40lb4tVOvJTCkNSLsAeLW6RvR9t4PD06GRfktXWEdOvaeiBiYacixD3tM5NXIS +EOr5Yb0YvhaLs+ha3SwR1jjVRFP53FL61Ut05WRQ2kG2/A4DTkdxuECDiYDcxtOI +rSsN338KzyPCyqMi5dmGVBpyNN9cR1FLrKhVMXUdiYgiD9kbtibhg7phh0+9BrvN +G9aXtEHmyZVl+4inaEkgw9QxBVq1myxtVAxiSzaf6sPtfhCQcdc8u6qZj+HTqp0s +rcOiAregtA9LPniFYNWtmKwKlnj2eDgupAQCxN0qYjfmCW96IQLBu4QsIifB755M +VCJDL7Z5F8GaooNNPO465dZV1jfNzKgg6InSrYYWQFPYWvaaMT6/FtEjlsYQy4WI +8lNe6PIcCnAJT5qcYFxWv29Eerv/lW1KPxGFA+cZ4qjwsTulVTaGgV3+OvtyF45i +HLhFRsByp4T/rlv05E3wbXXvhAnp5Mw+Hss3qKZaQYr5zpjZL5ooKh7haY94ig9t +WNEC2vWrelrD79iBqywzPAOgG6YT0tmGhY2aWkIC/PkOhgnV5m3sx7JK2tCX7wQA +KbxQ6+UcpqzBn4KBQLCVNkUbLEiqGgG1IgIqPFIr1dYV/FHMJ/yx0dgXapbrcscz +LmOWkRb3Iv8E8vsPl/7QFLmQe3BLzKL7/pcFomrJXc/9RKfbJtTHvleU7b01xMxp +v2v64d7cqRE6eFfTgDa5iTRNs6Pd+UaIXC5CeDRTAbBbSrwywekysQfmxrHIjo31 +hvhQ79PyQVcZG0Or/bGxJNliOV2BOhXmG4F0NUBFx1zfTh4mvVQfFKEOcbASsv/Y +tdMn6ueaLdjJFvPU3lAbXSXJ7Zf4idQQ4DH8Ehgnji078dQcCwAGkq5Z6+6y1RVD +tN3chsFFYEvB0TbM4fC9II6D70+DelFHYL7zoAnFPdm/srUcqhP5Cl7uwNz9XyHe +GEjfSKqzC10mAF00j+8oDFsU4PN5OmQAhC/AkhKUTMxAjcygSljQIylnyr0TnbCq +eZqD+DFg1Y7p7T3aATNAerq3hotV2anIowkMYKzVC00fZvVJdBoI466pTXAXcUop +kJrf8Mc4sXA9Uhat5IEbK8FdNi3bnqCQiEKKgwwDqN9/S8TNqBmpgvDOe5sLeIwC +argIw+Vm6YuQMitlZb4+9Fc47l7Kg8VLLCmJku4Yi80k4IICqozA7rRFhAd4EPIc +IP1zCH0cdz2As/xP8nGO2FSdHM8yw8s3D0ci66/mr8LENM9sRlp64jaXvFa1PW+w +EsJYqTGSROjzuM11zq2Idhq6BZMPmeLKKWOgTm47Vku5U2cyaRLdtrdPVnbZ9pzW +NTsdsFG3xXfKIYbIgusZyfp2s/F0xdSZ/iJn7vR05i9rdLrh0XNhVp2kb9frfpOE +XbWYQ+a6Flfg1DkEivZK/hr+SKOv/EYvPjxCG7SyZd2d6OgiBCDmOlLXUr1RAFGI +nv7WHLTqO7v4I1WZXuKlQs4NZb5Y4e0IKZ+YqnwyDk7BnRsDsGixqKV4chrY8xlm +EsrlNnBMcFermSWHpC0WUD2OyagcjsM8sz5NwMFZrMGbA870UMkd2k57PCLKnBfe +aiWik8W7udT6mHOp+R0J0xNlP1AEFb8w0KnGnoI79OlVHySfBd5caP4iakeKtXCV ++HIZEUhpe3IUsK0aUlaXagS8ajZVj8MVXWPq7suv9tWWrGpMviqd0HotMDSSfGWj +GnR6CjQ4L74xTIlOPvuk28M4YgvBdbyakX+EHvoLDYoyoW4wUn/wtAlZsmFq5ku8 +a8SByzHlJTmWiH3hvrvOjyArf0jyri8KFymVaqZE8hA8SsleN+Hm1w2APb4VRHAF +eI/PxpBlA62tFucZ/71Tn2WGIt05ZrsL5GYtBGy4g7RidkA3SZ/3WvpzHemrS4TK +CV54mHZ4XzZV+MmnYQgA7V2OoM3bmEe50xiLSZxGjX0+kHRzv4XHftMj5VAsjqwh +IUz73MlKc9GlAzJ3kmjH1JqGw8fTKzFlt+nYn59xNlWTskdo2pQRZQCgx1ym6fPt +BJ0zzysIHo37BeW1mDszGmsTsEOEKpolPolqf9fmGAkrR0T+NHzVn56ZEYtXOkRW +B2G3WiNWKLEk13l+lCnH2C6G/NIQ4/1MEQ/kGrTd7q1NUHbvJoX0E02CHqYSlfzr +HSjys2eTx5YDlMUTtWHwwlEvHUDTHSr2FR3tIlb6l4VOq5gmwZoZGA/38/YkU1I6 ++G3+V87uuqpY3AZa9NXTiWB1qtH5qZkC5jwxLOrxXrYFcqRwav0NR6tibIAAlcHc +4CD9IVP1xazuBNzD66yG9RB+bUwgVhSihNuYL0jvCg1dDSBfU8GLLlmIUCfF9Kpz +Lk/bdpJpftgZPqEpK/v1FW+p4+g0mc8/cBmifP+7Xnm8vB+Oup5kHlOOWsbju/Po +zGLOOTL3jSnhil7cfon9m2xRWM1WkxU4ArLDY5adIV5ULYE5rmKEL1WWwsWol56/ +1pRtR2BTtju8hITLkSya/RTeYWS5YiwmNnFQXGm3pGyOLJ43WEV/EaC1gH8P/W0I +DqpKNL5vSDj9N7weFKcOTpFbcxX3kpahwU2ULRwSwXTqalA+WuP1XU9/4A9AEjhj +fez71+ZbHJlK9ezR2HmuFMQlZlbsiLNKh98mkbWW1au4cRp7xNkZt1URbJn5AL/Y +q4U95NsxfkeEBXyk3wg456KWFQ84k7anIOiB8uJ5LEShRYs5ruW0bPdisaAAk2kz +ZKrVKdq2yXyT78t39B4RAwlZTkKkv90vqj7xRCKLG83PESlFo4hXY1FE9dL3Hfwr +NMS4mu+AHM+SBHDa9TbFzEdomxhNy3paF5pum5vS4G0me51SHDmLmn2tI0/BFfX9 +ZhbN5JewanKLgGI098qHtIQa9Z9cx95nqKSxvFqFxGqVTDIpZH7hP/SpaADqj7h7 +dCk6C+89eYAWaefqgig+kCYbaVw+93vnO0G3mUO/p1tKyELYjpCsOLZmjwS/Qjsi +oQZ36rvv6bJAi/FnkEEDrB0OCoNYE/KxyUtfRRWq+N1K1KXB4ytYTR6tnw26FccZ +mtzwSKqBxkXYpY4QMdCRcI5oMU1NqhaFpCIa7yghpDGbOpLBYQpSEjJr5EWoF6Zo +uy4LnOUgwP5xhIKNdBx1Pz5iMtnq7V0UaHqiIh3bryJilCIxDZPP0jg7oFZbIT2a +179Xgp1kNa87WvZz+C6LI9JWC5jYySRx+A6Lq5PaoS1OYVtzIESLUrjc0H1Dmh27 +ih77kX8o4CJiyzYYTerK58dzMLpc6GLFR/VTD8dtHwZRZLIW+ipoJ7RoYxHtGj97 +YAcrHxG79X+hy9kwVTDqYzL0FyW0ouXXnpBYAbEju247ayzlQ9o2SpLoVC3vfb3s +MYhx8rFcpXVbAUAOc0NbIMRBcHXAMHzNl3HUMhODFvcrePAGVKOUWrhtpE9WdzBn +EnH3ie1WnvKn4agortzwg3IA+GivauDCliyjrIFeAz1Iz0eZEtEOw7Dmnbb+kmYS +uuqK1D2DsSidRnAxGv64YNOWbq0GtcMkdFMtlu4rQhZUxiwd4SG4CUUe3x8ST8H+ +CovnzuRiUV8+hrBDk0sNNv1KTYvDI+eRrAhH8SpOI8cib+7v+WP8HjlaL26yWPpE +JALxDPS/iTBtMH+35U2fcE1L03q6qTlK8GGBw62gO0WAXHowwQysm09dMM+KmOAU +7mRjDPVN0/0U8fUoY66dyapphccsF6cWt7XcL1ZgerlrjLA38wX5uTf8XdQXeTjv +OHQdYodU/qhaxt11eenyjpNusG3D14H0uxF1enpZa6UtN1BFVKjSGI8OUjBarjLE +Q9t+9xqTyoq1W+o537sMzyf8RjRlU44bbczAGuJzPJbZm+FV41AclsE8tBS5Nkz5 +oaIR7ubx4iEigUx6myN47DWCJpIb+lynyt60KTyRX3Hfatcmfs5g2ZFt4t2neCuz +xwTscdBH8NAbrCU1m/YE74/122opIGpi7uPOM/M16bsMWi39S24jhHjvo0oWwff/ +voRnvA0/p410VrFJo5xfV52ukNeFIZzMThiYj8GeFLpPcd+TWJ8AHZaWspILG9PY +DT7VK25LyADc7PfKSyfrcbpJfGznRR+BQWhEQncfM+JwCYXia6V5o1WHjNZd1CG2 +fe4hIEmql8+5XKBmEdeKrUxw3wrQlHWkbPTtlR14YpkuXPXUUcJwsRz7ymS7Dj0b +A8Gp/DIKICjiij0ahYKmAXjzVHdc7tsIG9Qty6qpn1Ablz/JudWzEwQ6XJ8Erl5K +A62PwXt+/R2s0DMzdip45CsCVwsWO8R78pJBhKBVCnxaLDCEP4uy29M6u3zT3kII +bqZZPj7p0k1VRjWrX6uCoSg/gtAcZr3irnAxJ9p25ZpNsgA1GVUPhO7kWi11oh1u +N3zD/Dp0xDbRRmgP3eAB8mckp/1WHxeR80/4/29sxCMVM5X9CdYOwaou6b3gP2Ew +Q670b3MNdxjyNXwPIScWOF8fnqUtAyDYxpRzioCuVJtyl7++7fmUIcv2Td4vGANT +4R0/lKwaaYdo3ynYOI14D/pmSGBikJHHKRZi3OMXzDpVbvk7/PylJTtTy19QCNqi +ipfc25vNU2Y4FarOErt5Bu8hE+gKgPuikGysuZx7vjM11TfoV2ag88Zq5Saz1i3E +Wxw5eMqWStnAK+cfc9slUQGArzuNosbnY21yLNHiSeGtS1XO49xM0gN2CueYH2aJ +0bUEpqXurQ8QUyWEVvxnvEImtylwL+UVwHlNwHl4h0VGdDLMM/cppit/LIXNXcI1 +E5fzjAjS20BaySMeZSIRWv8aXk1iaFo48hMUmmfBdDpxfZ29Y8izRsbWFSF/cNAz +wyBdN4o/Dt5eKfs/93r3rkm5AS9o1lW7OyWoCJv9gTsI1qfrv8vk7QGKZ1lj0FC3 +hzwuk/hP/VAodV6kaLIX2M0tuJomGPjgvjqa5P8Z9XKW6sTWdCJo0V1i2GY7eDfZ +r66xmVfRIJUYL5hkMOLhoiNEmZAa2xTpXH7dutcvR7UODPtRE3H5n0AIi+RkIQFi ++S20fSeAn+/IYRVGFXxVK4BwNiE11s+Kjl3nbfoktakQGqP/4iMJ5IG+r0IZeIwa +XtyWycglVQkwGI1ifbydL/BMmoE8ak6SxCG1gTvgttR6+VARcOsUvNkbJDu/+1oO +jvoSJ1Es57ShLXy7WAYMv4D9OAOXidnz2JtNPzl3C3H5pcFMzO+xdlXkYQGZyhEc +ohbefOz2GbER/9HHsjhjCeT8x4CgLORz9dWBIdZy86M0RGbQDiAar2X17yhaLNuk +kb3zQqoY6KwmJIsCcoibFEBk2PQnyQDOiGiR5zPYfYEnZHTgW+RN012yJb0WKnh2 +vda50OJVf5V1K9RNAb7OgYrcbKEgp9pJXRIU9UU3G4Q27kSSiFf8oOwS1GebJBdi +LLN8uV7PLS0WyYCNTrL6J15GZMC0ZkvpCB53vVGBrQNtJwVJ7d/dpfjwLxEz0WEa +qobG5xHW7lGhUkFftSoIgdmn5QN3VAWAyDTznWzd56ydMbLiIwOhEmpwyWpDohVs +avQ6r9zLhri3OuFsZ0Hum4MYEwRtjcy2/2PFVpEmaRJGuPWBBaYy50wJTVTDPYA+ +ZGxggn1R/urXShpedMlu14ivIZiJIHaIRMjYChFrMj1XlvcEUGfnhOTi6oW/+/YP +DoOePHBBLwdDFy9NtkxdJxTPA2GvB687OQ66qCr4KsfOCR1ScSTYhDmf49eDkrmX +HiUqNr4aLt/M3uQzo9IZbY8MB7p/IPQZO3Fvp+r6sMu3Sn8srWizPsmWFyGR2wZZ +Qy7uyI7kO3ianMoZmIDVkJRuwZkBHBEBby99HK/MFpxbXM8ZXo/R0rJoyIDc15Ib +lclnvBm3JYw8jqh/iZNLy9UU1TlevxHHb6MBEXHHBtAtpYyAjcYnmNJeStQGZIPh +L18CjzQxBMfgmf3ijQzRCqFRQ03cstLXJGcWVrK8Yap3FeBwca371pGxrWg88SKB +KwWLiL+aoQY5DG43DD1XttYMunQ3TPGq7XlJJJGdcJZI3XkB5xG4V2PwBmgREYI0 +XM+nv4V6L2PIV/eNLp3Vn+5Hn2zBKwOlurRCK/Y/dfpQ7ncXDLb9p4Xuwhs5Nw17 +cVW6F8FXlcK//w3fstNd8wlNtq6BsEpP+SD7hgqI2fInaCpjykaFXzVuCpiXFr3E +EtWs/a/ANiqMKIdPQjVJOiRUSSe19FtfTIxzW8mJmQf5FCSAf5tDj/Tn70qq5Tu3 +DfODMDwjbxp3fWKA9TG2VJ6lw9L9TAoz2vUTsHw0XjYJDSO8CeJC85o4qhnkNSMB +xemX5lxa0Vgj3zZQHjAv6iV3CaKAdS7Fj4OZHJzN1sQv4dZRCzGzKLsg3JfByevG +e1XtBVZYnK6AgmeP+2FGSlmVZGV6NqQwDlt913GC8EBJNjyMYLzQUCS0UHHNOJx9 +MzhMLmD0gOUIu4rEk27NcUiDwHHO06T0ha9wT5XiesDaIa6TpM/+WKOYdL2HhXY5 +xgxgOsRh0JcYAat4aeq2GaKnNP8Af+/9vI4ENRCWekZugbraNqi0bSGAJZ23kAzd +geQ4fgO+/uJ4eTtkhUMribgSkh5BvwdywJyvfWms8qx/NddwgIINAzAizcbQFSIr +TafWZoW9nh4Dozs/D8mUhasiUl3EtDdyCDvKDHN8ePT8xb730CIzpi/K5HMUZCN4 +7wqzaf6H8tcwhafIr44Bv4q3lCOjvaNyN27RPHVH4N/MpItgw6Qcmwsj7047vthF +LxQYokY1/GUWhbnW0mW5Iriyi7R+dTGAMvUQvMoW1l+dIrAlgo/xR87AzPA1DQQp +pjzyPq9yk5wWX1dZaJUF0evp9wME/mgvHd5y3v1nM2Xmx5HS5YXDwx1CBPYqy0Fn +OB57WM1NBiXM7eiShrDnFcRAgjpdoL2o4T923UaEMXtcxUUbkt5l28wladjmqVwV +rWxo87yCWRR0OYKDWBty/QNXgcWifwoyZ/dOTdiLm4zWxeoBkRM9hSmqzQyq3QDw +BsvoAzyDiSqtKwVBIQkk41Huf0NazCqJVNrJ/mkDpWcyvVwrUVpbKMMRL9sGveIH +USU6fqLGuti3SziHxr5dqQeJ9jatT+WBwsuSEsXNz6FmhXRZZgwEkGDetK05E0af +2A0L2mhrVeG/AlzQf3zIXD5Zs9EaWi7UZz1Y5z081gShrcMlrkp+KTrwloAScl0J +6tchOOT/5XnWTj5UGmMHH6C+AD1EE+593b1qdhQv9DtD9gfF5xdqb2m0QbQc0Li3 +9iIrdCWC7cLalnsdn1m0hPZfA9dfqVfIQE19mO7YqQonV3uwLV6RBMvbvyoaIVRa +tSzwNYj5V9fc+J/1KU5XaY9V56XD6EjDa6RD/fyu5ZbpfLuvdavbswSDYnakHh5p +ctKeCrOK07oFPtSPCQjTc84eNRaw6gKaml8ZPtvuQwfJPsDnAJ4XeAqy7B+2A6Ij +NfLnGt54vskBkBnQz+VqemZBTAM+h5g6etoe0SdmVVOJviXT40oLyh3Hwd+jUPP+ +f4DfYwwqiW23WvEdEEKNEaTXfqc5gmmvGjcnqWFcLhScXIueeZcUa7HwtMTjSxtr +12a5UOwHEepebFzd6dMc6BkUnbBIqEKvGzZIJH7Kov12PrfzLk0FhiHMQVCrqmBg +xiq8i5zpt08Wxw8ZClp4v1USkVDR3yXcrAS4InvKa/ZxO7AWIUR1B5+w2mygbkxc +KMluz8sKuQWe8QJMxJ18haqRSXXFPK1sWwFQ3G2MDQtK0u5uzjaJWEzCixqIjEvG +aPiPoU6oKh4b0Tynsa/X6sibE8hPt121rb77zQSr27QLFSu2EEZZhk6GvtNMT88O +0o+fHPKo9UJVXTqCh/n0gjYLx5Fm9UR6hhUVKWS86LMqoq++UlK/VhlPifBer+W4 +Rm1U5WdsqmtVP1Af6Piq3YZhLxgOUZiOinlpT4LV2KkXdMlnEgAIUGH6RyTEtKF3 +JQ72fPPjsv3f4X4mm38soHmhIvf7hVJVcUKMFXuRan7qEpWiwsJSVHh/Mfkmowee +8MThc7HvPOj2OVeLWWTkW/UXxK2aD8xzlyr91BAm13PycbfjjHjKsv11sVm3ynK9 +F8T0B8oFaZfDshBGXENi4Ct/xPE1Cao+9ngrI5Y1SH1gNxWuP7GTmTW6hzcWHD5t +bw+tyV8tUbSIoZBMhwP2vD3nEVnBNrVeWB+rfth+c/3ZkyitXYkU2icVq646epIx +p4N+rop/Mffky/9U8fyyTHCU/bppSuCY/DmaVRhdwUdGKMbvd2ENS1hfK910Dmlc ++5UAJlPpTx9MF+GKbJD2RxBRyY+SEeeZgUULJJ1mvLGTy3JGK5r/QWzmzn2V3mXB +8HwpV9tIu102yT1nwE3sfQ1m10PL7sD/jE8edNkKN3tOHxCu9cQIESRxx+DZUMln +KiYY7MioiBAOwZWaOaPFm7Dl8qaPZAzMlWstkfGXxBoCTFmEk3MJs7PAt7ORmmSm +Qx0CirSeW7S+eMiDmoyaXqHDlWjoObqrP+qsP5NSEvHFIUJIP7lR6HyQSdiLUSN4 +MdmCeHep+eyraWvxVbJIUgJpUvjz1Ou1iiojiHU0aRai3RnXKQWviUZlkNpBfaJ1 +vXVL+tQwfkulj+wZ529A5yYc2d19GHkCJQL6kcFcxAxmnq8HHkImFM6Xa4cNrnUQ +UCjowezIh5WOMsxFgberDwfi5xD6fZPm+4JJabJvvMcczsJS2WGFi2KldZ55nwY1 +e+zh/AS+nb/aAWiWE88ty89HHATXGV2TOqRL7P1GRdWEGfrzsAwDqeYnQni0MH2Z +TuNXCZkvIe3JkIck6CgmAkSoxN5tBSgW6U4hRIBo+QedLrV5QWfJaCnPiEOm4qfA +HOQkgRa1KEh50CCCIEsiMfG6+uoAeKs/SbGeWEwBNFJ/VQNDzIdcBFkTeR5u+8cl +24sTpOrJW2oRN2PmwwHDlfBvq/Pr+9wBfSBy43cK42+7NkodyLIPoy/4ERTpXVme +b1sR6ZaWPlBfD24WkUrBHePuaSfFh3OXI1vQbdOYVL9FScYoF0AFNvg2WJR6Ngsz +4ju2zJNLaRif/4wHIJdsXXmb2wZHlM1y8o6MlXWuX81+P7wgaQtldH7VQOEtCXZy +JRA643/2XOamn2oxrSEQHN7PU03HKVI8j4TYzU2kVtQ9ZqqeoqWGBMo70wCI9hIo +sXPt7UbwQ0jr28hfJZ/7bCZKiC36MX+7cKP63GNnIAILn8IuUwaO1y9Y2ejHIfuF +2N7ma1YPhjWKMsI0HYW9jjTdmqQ/xaAVXRvbTfjAXPSH+FNT2MkIMCZYYM/Ti8WU +vxnBpd0gSLKzsFvnNCDLTv5bXHWdoOJ2RJVf95B+SCeVqHUaik/iEXPxQVDrUOW6 +LLD1dQXpRCWiTiL3Ju9RtCLK4LKXBDAOqyWeK/MNN6IvmOd083bo7vlpJw3ksy8p +fl/FzC6o2cFT+Z1Dt1I/HypGuYgCthj72G5zNuTWEPnf7+cZRDTIaN32fUuobpmF +VhZNJUPcPv5lrHc2E1y6XRFS0m3Ngzg5Z81M1Je9bFVVWYcXz1RDJ3hqCS3fVbti +8rzMdh/lpmaXB3JMGXaoTGdJN2cTpWLHIQS8CG+Rf+LHjUDS1gCDNq80F+ip3yB9 +HBcwyl3MqEWyhiyY7wHaREvaM7f4NpLubezNM9nuu2FkiXbIN3UCCnbLK+rk231E +/yX3yqBrWGYVQNDq2CP5yDdRpHJLzDwTwX30lKYfwcI= +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +jUjs/IOtuXb97xlmyLq5Edj4QcB1X4njm+CwasvqhiKDISF/uEFDJMVIj/u+M795 +kVf3cOwkzvRxZbOyaqa3d3dNrJpmCfLcCQe9XSPq6gw7Zx5h7mCBR8CgBosd/bPN +dJDcmWwSeM2dAAY1L8RWZaVAt0ECVzK/jKZ13nbpAbZzrtXkLSGEm7C2YEoVz0ZN +pBI0A7g9Sefz2Hy6Y0d8HdbJMKW7zm7KRME3k29eMtEmlE1qKdJfxIduXCGWs2Mb +qKWPodTwUcLeIzd872zib1vwIJdgR6giq/AJhdiN5IcJxFDvjjatsulWYSfE1iO/ +jiC1tGg4ec/+iJP41bbQRw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 15200 ) +`pragma protect data_block +KdNDALrSiDzN/aVTuRIcd3tYoSHmqNEwKAMOby6rJyhY62B0zOwd1/PkXsicwrji +SE6MbG0JEsXRHFgNneDXFDdMCoHDYrKL1s41Iw6Tt7cmuszErzY5umojyGFgO9o+ +ChLfS8W6rbLMWO85cc8UwpiiEBKiKa7WF5aM3fLymhss6eFjoqtkjNCFjM8EtcLI +fAMWzSX9mWKiJMRZeknZpLP21dsjYDmEzWQ4ZNGVdxMme6lCd1xiwkQXp1tUnNoV +KFaab2gLghoP/JNsOtimnPV44pv+O7vp4Pcju9puVpB8u2V5JU9bVvjJ11aD2aNN +ETQPGtEPu12ABXNGhX1uIGwYdmBczC58WF2owIn8NMHMp9oiyj7mMIpr6YkHqGJD +7VUemv/WRidINkyXxkaJ8ArHXixKdT0EM+okMDz9hlh0fTXtAnOpiNMv/dclAGMa +xkDmWg3tYj40QfFgGIdfOhbWfg/4qTvHIP1VN6VXEdjaBsc+AVUvyZ099ERutDz/ +dBntwwOAyI7IjNGQbe44QCvty1cH7inGi1HEQ0i6Ca0ibm44mJK5h3e7j459MXJf +WM+FZa3P7A/kV46TljSuL0jyGvfPHwVchF9X8UWiQeNSQlk4qUrJkLAfqSJBZPNb +unAQ3GYpPs3rnbLZ3lQoIWc5+CZEgUA22ndLe9PwgwC20cSO9huHDWmnZPFZlPt+ +W2JyZ49wxmQUUJ+AToZ6mBKJSGlfsLtaoSVu/60ctxuIq8ASnGm/8iY0G5V6GEFD +b11srFlGG4dSG9XjGxj6+MIwUKucL3XUvi54KE/xj4u47YJCXgQV4mtDT0bo80wg ++tcc4uup4/cow0j2PDTjwlDqvGE7iPwsFm0oIjidzpfEuFxldIbFzk6DcVgOeqlb +dubk9E+/d0exqS5g2IqKEUfrQjntIdrXjs9b274JhgtLXzG6RQbjG08tGUVKmsYS +DDtJEeeTNu+qXM8hyixPLxVd+ABocUUeNrdPY7bgHX/IrVhtrep3HTVTR9tNNsOG +EtJN0PKWBeCL8Osq9zCdzTw6a5/dQPx01lwwRxwW351oSCZI5zwG3Tuqrt3cYkDK +y7uIY2aZWDFhzyYpclXknK2LZZIJdTJf1yF3ICAJlMNM6e90lnkp5E+ciDC5aiBu +FJBgUaxeBCLW9E1RCdl71Uet6ERBkEgF+Nb7W85MCXfTao7deD4W74hXDF4ueJo6 +005qPsnfR+r7MTum+1oKdQJdNpAEBAvVdJ88/hdL1rUvhwvrjMtZm3dz7ICxOOrV +I/SopOYKdzs0oyDnbjqHBKi2BKw+EuIuZG+Xc3sdS8jVzA4esWizOXumOOkl5MM0 +5WxXI8JcXsMjWm982wD7qFkET9puyDe6lSVk/nV6rjVplTYyu4Fd7nCQfkMDjEH1 +GfXrq6+BNCeT4jf6H1UT448OQZCBlj+gLDphg5Mp0fhhVGT+Fl8C1qVRhsSwBWC0 +s5yCaB3L9deYB37hHsd4MNMKBlUZOvd4p5YU6Kda/CaL0J3q1wSd2SgTnCJl04Di +iKdFNCVJCOxmvhd88WS9XiTUGj7gnJnFKpzQcTmYLzFkijnmdwvuSaHynfvd7pJ1 +8J2tbICPqZb0OyUQOMbr5+VLS57DMYvNaNMS+1LuPXYxhAGYnNBx/0CRL1Rc7LQw +X51OdaxfFU5AUx9J8upmbM0iivAk5rb0UvqXyeWvcSD8f/w3fg9fNBD7b7hVW79N +4BnXYghP9LIfPs5C+cd7R+uyLUk0HFrk0+DJjcSM5Npe9mL/Ic+my+HLagqRLbIg +R5p4Vu8oP9el2xZ4es8M2rpnL3C5yYv0lzdFb3txGTJojETfOShLDGcTLZsCDwVG +hiCO7z3GmFcyOpzwDp+tNkZdrBJY/4xJIId2LmNErDNlgVBEaGYYj63Gw2E+RGhL +SPY52ZCmYs3fHbYrJmsxbkP+Jak+kXoUYMZt6LRl2DNRHHCisHo8t7hDy040HxnI +bmgxE6DyC9JXEHZgVC2PpD0ihO+kvwSAhDe/1R4CIRkyCH3iQ3N2lGc76QPi3ggY +1l+crSQ+wyajwOyEiR8G6A9fzE2hgBV+dCWKzV+BNQxHiEomZkzp9WGY5gdHcuYF +d/5yFzT5nxFAAc+KEMQE8nQRYxL8EbCWFjqE4xzWCP4IgQlzxSj2LYcJFh+jnxcW +4r/oLZKEZZGUSNzqKOfZ/37ZXzwAMRH9Az/qUHIyZB6n9L67MRuehiigYTef4c3N +7aNVpWaRoZrOyh+4/CZ4jjuGfp3DFBQ+ZbmtudqVcZHVugllAccroeKObbPRGmUK +rrLmAg2Uqh1QW7TX3X8lRlof+jAWjCXtecwx95/q4Xvyvpf1vlaHV2SLEibrgjAT +95aDaa0a/avJpOvMMyCVPgjTOr6Mqcy3GQyVXOVc3uyuvay+7L14vkSaCQCVpdhI +8UgW7X+sLHTdK8PXS3UC/U/UzCkGHBD9xWtyWixGdLF+E3U0exECMR/KUJsFz0aH +znH5clZQpd5M+4h1TAq3shd/KyUcI4ZaNn5F/byqCncsQWppcBq7nH6zof+S+ljn +TOqjbzrvmoq8KYbnbe+CTJID9U9SS99Mz20BBQVfOZ46l5CLt8+mrroWj1b1odj5 +ealVioyrjHDTUz+17m6vN7hQlbTgWt1g7HHm5jOt/9lnGqT3yH2BndvrV0bTej5d +weH/2Rzm7Ue+CAw7+Ohh0eDVoYyN7XwlUSgsRvBUovBJg0OqwU1W5+1mP12/6j6g +WudXk+xTcboZDo8t32RqqXXnHCD4j3GOk6Fd7XYiddWIrsgpc9dZMNYISSaRMTBk +ap555c7y8nFWt4Ju9EKDYI9CxpQxUrPCrVjtGYFX0hvbqKgd1f3X2YYt73yCIGwj +NI9yxs3Di/YzIDtUtcM2+s18E+MZQBkS4WNm7FC8LqKZML1d2Z1zSRcyPx26y8sA +CLV+9s1SsRBTtz9Q0vsGFeJGzTANG4cgCHY8lll8kfYaGjYOGObQOqUaZb5/eEP8 +U7UUrU/Cq6ftT00P0wntoyGMtmHzTjCLSxF50Id6ahWCcgVedWZoQsLXL+N0WTLn +p7GcZAw1kq5b3cpxCTT17/DGl4CzkGvAWj1CBcyCkq/LjbYHpRlpJSrU+1W3WTyS +cg7TeWHFv8JotLhfQ/IumumP6buNX6MtZzUhVfNVCNNg6bgwraAEmp897k3KzWkf +e/qTw6dXKJbnmPhGPD1aFDrJSothZh9br/L8qJp/+oDPEb9wyGYb/eYBCwbvoOOX +azx8yDzKPF3JUUvXhcRMA3NrFfxad15HrhSAjrSPcY26vFbAyFSGtddp1rXGPmV7 +LP/p56sVpdA5/b2McaWTm77t1Rm8nOXI9Lf0wq3VbcEFgSC+PBhmdeavPsaOwUe8 +LktbDr9Ud4XntUuyMAHeIk6hBMSCJ6PB2MzAf/UYF89SmMnJx8RQm1BMM+CCUo9V +QjI/MuQQWHkBzCpa9ywQ2AGTQnp6ytrSQreRjWtT1cq9nDJk3RIzridPGyA12kuO +zoWhhoXBsrRZ3P7L1cbCF3jU53RvynXJPTSV+kVo47fSGQp/1Gi+HZ1jQU06pNiX +O4SrNkPO/jX9kUEqXO7L4eYYdHV3ZB7GdrBXQfOUEjRqc3lE/Euz7yUUzS3lNrYL +KMn4Sie013W0EjPp7894ynIV2tVg1/XUkgzw0VScPh/CuSCAWSO2vbEC/a0rdcXB +P/W7IOEUgUJ1RsQToX1I/B2wtYOBu9nMWKOcwkN7DKqphdcA7eWelSZt0IzfGuJH +5HQv7O0mj43doKkPdh14SJ2rOx6al+UYUgU6nXT/m4iQS95v8B62iezY3YBDSp1o +TgfAEaNw0kBz9ZLs9tkW9A5L0OrcVJueU5VaoFbTs7eBZnapX/BTC+395LdolBMr +Beejz39QlbUas5+Yxry5aPvbH2QzqnbWc/oiBJDRR6toKNk1Ui2l0MQnSVVFYroK +Lq1qRihWFRmtxSGaFwCsMDkoE0+OCSdXeeTXDjC6by6uzxu+th8szb3yKiy0jK5h +NaG1P7KkvpUKf51WoMO9tAVkTOtk4Y6DCmQ8wTKo3uvs3ivdzcBOBV1npkjB4nZi +nnNkJx9L6jhNmJTnXwt44m8q3qiMT5AM2UtB0AY4D13XO/zCv2h/E4jcrH4oWFdt +a+PKPiR/fPzqTn0RU4IXO9eG9C9Sg8upfSUPfT0+/2RA5xhWvMWPAhausEl8tjYp +2NBUvax6lBqML5j38C/ChMz/O/6udVUUxGAKYaJiPK5g6sHXv1tu7qM+SCM2cnDm +iX+2+eCBynsTPZwlEMW2P7zfOnQ3+MJLdQG5XWBlpUXq9DDknega1/iGXOyObGig +fo11FpNWehSh9wb6g+WyD7pV1QKnkffVaZM6nbHdI52u8M+iA4Ym57PZu7t97VdX +MgFzkATvfMJQN/xXJ+f0vSPGTdyWpm/KfPV0yiwL7+NPC+e61y/jQE3/daIffg37 +qhm/iQkKNg2hjpJJeiUQO7nW43GsQzrGUP/zXWRxllaHI/N92nD/+oBXDSUhrIMt +6O74bYiF22bfY57LX7BNTAyGWDe9gfk21OyVvQyXeZKan4uLTiAr/j3+HcGkx93t +Ohk0bJSqI5azcYOsUxSSDfNM/h3RdZwNUsZ2+Ip6TCG8WrbgkX93t+18rM8u4GYw +RLLf41504oUUmBkw1429QuSs6CwdPDdIDDXhkhQ9PKRxyI3C/RS9T17+Ly8BURQH +f3bB59XlnGwsMQYnqFC1mm9CDRXF8dGb2MiNVAaKYY/kzKbFIlPeqPAYztaxvF2O +jhsmC0SmbO7h+aFOAfPtjHznHxeDktpyCyZgbouNGjGvftF8ifKdm5Jjvt0f4ta0 +WdUcmiNgtL+kwxQNQvOGPGYXPsVe4UBI6KBlBkoPNpfCux56Zz72RzvKICiFQPvl +AozBTY0VFAyftdJr0e7BxmlCx4wdkTKXogP/s3iUNVEbU1Hw0moKPKTAmo1OcAdC +NpBfStU4dTCVJIHUkDXnuBqGsHCa/70j0FjPTPl+sXpuC+3LirMXMdHV0hw/8Koj +FhXguO/4Tktv9i9hRvaRJi6nRRPyHAj6I7Aoft1BrOzT+Zsk3A7PWOHhw+swV5vB +vCcj/NokOGA/lPRE+w2WMerqsUP2KL57k72HGpk9B6WpG+p3KZabwww0wyRJk5bS +ygi03D6thcM0Ma8yzH283FqzfiK0/l0HrPGfcQuiedk898Oj5V5ULpaZdnmkv96i +afgNAASP3Ovh3ZihVR0bp621mfueNru/1jfHY/6DZgMqLrrHClBykGpONKjKZIY9 +wiC5ZBzEWgI0AprNt/Vu85LWlOQoeO0PKAUmpZ6WewxtpBISKa2+T7U921dSKLmy +BlWA3dBqUEKtF822l7NmuYQQ+s2qgz22QmaEsYOl8F0SzLL714aMlI4jksddydQG +eLkq4xeGJ9nWhKZvcShrULAieg7jdHrZ4vZfXWCbcVXSKPJSsE//tppN00KvCY25 +Z+p+89L7/uhTloFqw5+J4EK6v5AoqOJuFrY4LHtKc1Lc85MdH5SZN/AnUwllCb5Q +RbkYshWoeT5xRAagxseuEGlzuvuyv5xHB2q2iEPOS3T38nH9ENSuDP71kvmgiN+D +FSnUHIBi0C2pzCjTw0JXDMJ0kfJp6RaFm01DY49B6wUrFuy+45EGA62VVAHIhaJY +/9M675p8M+6XVDJz0zbc2chxsXF9OLm7j/w4/W30VmTPnNQttOwdU021cbTtmLkR +MW1lL5YNRLbezN7+c9LGcZ3+ozMvg3avxlCzrYAj2ZbRG+N+W2pmew6L/kPowh0r +o0erK7zwb9zUm+mUr3G5GsGJ0KRSEmJDQYlFGgu819hHBcLTfMYSCEYNZgGzmZ53 +AcFFPlXvPszd57Fo/JJd/1yLFZCCKJ2x36/2AzjH9Q4pb+Y4/146iL+EykxonGHC +eUjyWE9Vm3eV6jcm8ehbYItQjW6L+MiQABHFXrWyfxghE+CVsEEH2w3+rBaR0hrQ +m7Mkfm1ScT0z9fUTVHQpyUBSrIqDK/ASYiMKgeiVR6tFHsTUuS9g8fHlRt/KmO69 +8nvDs6j+wmaeXDq/6erxofP5iy2lJVS/+7SQXhFuavogAlNcmp2cqscLghg75PLt +hgcnyPY27VuV/+yqFYo3UP9FnQzmoU50j+t77f5jiOR/oFtancRjavOhII+ZhWEf +JWtMK39hnpYkEs+oF0Tc2mmW/gCOCuen47M774/MnXE4+w/NrJBAdMBnaH9pN9D/ +Imc/uaNYPsZZyK+Vwp+ary5bZPo6f994sPBWPruHK1Bb3NgKkWOlySP1fYYnn/qW +0K5O5GUI1HwUI2UUQnT+06MMDhsafs0/5mZpQnhNaLOnbFj7rrft+TOsFJ3EBeF0 +zEdRjAH8K6FMQtriQXWYy0hwsq+AhHqa86Kg/szKTCgpz8e0YDSlYwH0xXLssFxX +bW7mJIXeSHSOfE770g3zKZFkdYCoT9dFdqkYaC5A6hYVxswUuKfc0rRlegRYEKAe +VVwr+Nly4t2i8PwaVNv+Sfeigv8QzWxKlpSvK7EXxe2fMLORG3HP5QBR/UTSEESK +o7tr3ATYKDFEgF3Rrr5X9L+Y6sJ7GUzGBBvEK59Eg+u4YeH16uGY91j5UE+zyHa9 +NTNGUwh20Omqi14xkUPGRiaaXDSoPL4JoNMyN7TBmx5yXGUXnygz+nLhhCtx8ddJ +DNOdr+TVKGVDUv/6epLtuMqDaOr7AtPbaGkESRYG2Ao6oBe1r56SMwbFfiaYuGxo +qz84rg206JEdkKqk7qR58VXr7hC+VwfBAt3lsvOaQ95H9RvPxvF/owF1oLZumnql +0p2q9zNm2s4utFEbeOsr+azYvw4dnggA8MqP6IWDw73hUXi9Lc3LTb63mVxFEdCT +b/L+hBkyGFo1oH5aP+xvC2Ntcl2PqfxLd1S35Et6Voy0Gu/1U8HvgjkTeuU5Z+kq +oNYyax/Hmk2DY5wUNWogedbzItEe2RX1oia0DtIFs8lMNJh4Ag4S5NS9ycEWQfqs +Leh+2ltvCkdclEG5pahNTqXvrVDrCh6tch7lTGet7mhW8gXHhzYvDGPFbM3HWX2d +bnL8oDOJTs3fYj9eV3q9F773Xd0tBf+Wnp9g7r1f8wWoVm3wnl6sQvQu84gYA5i0 +eMo6RzO5JAzrtB/3gemVTawD7Qd49D9nqsjWi8/ST63X62mzNWgxBmfMlCuv/iMb +2s+aR8YJlRsHGctATKOUX6ERPmqK7SYqYVlEYcjVtiTdQ8sfu6sDoRrxl/u4Jcsk +wtghbU/ZoQQTpjVYFJoN2lCnCp7PcwJ/jhoRLToUzQMUIO9pGGj9BX/aEcRPdVia +UNwl3Hh8GHV9m2VJEjy8PYO8tP/9LdGzhjrbL9/7F3pxz/Ttax4dxitnbajdYqDz +GLEFSAAqxjoi3jw+HGMyEjv1BeFiGM8p42kW2N2BQn0ZdiQDKYu/c+w2AV2Y9k7J +0Ud0H6yXEcxZNO6zkvnCoaANJrRmNZ305sBNw8E38CpfwVLD4UXfHvwCQAsDK8IK +7Mb0V4+/r0GlAuAnirx61HHHTIhzH58DnpgKzZ0O4g1/HYIUDt0TJfPDUaBjLztn +azQe9rGxzAlXuHoB3jfg7XK6dYXKjNo4abwJHuGVvLMsAOaGhTm98sKC0CA8Aufg +QcsCZf26W+548oP4zMHXzO8T8O5KDLvgXqX2xRIMOrkuXND8mqwHwFEUmruJPvsZ +bf1UHsfiA6Gexf1mIz7Uq3Z4LzCCPm+7if9YKwp8kTfrR23fltK7ImyjUHl1+r78 +ha/hzabIYfFlJ4iOYVbaNsnu88cMtvxT9WfjzAEcaoiY4qXKMv+ElryWApULUwRt +mCpZJIGtt3Q2fg8d5qaU4WXiNUvGt2l+PXarQi+z7OC6c0TK5awJL+abKlzRw9Ar +/m8xBkvwAHxC0NXgXDD1Ha2UVERKkG3f4F1b5G/N5znDV6ITpK294sc/vnUKxO9y +8mvL8L1cKCgmJniW63FwE0F71PxT3imYt601LP/7l9qoB8JAb2ofKv56G7mq0DBb +hVPEowwFIeQb6OhQpXghazbdui7H/MP23WZXmgBUho9ysRNiPcHl0lyQfYoManJK +XUb/1oG/BjkojHnEsR3fjg2e47Weah46lPeSokV5VK8VPHiT/sfBAofIZouzvIJn +hzKmnv+GLIF0Y24Zo5iKhe4E328I9n0z2Au+ec44ja9fq4chQA7jg8fEbdRPWCAi +k7AJhJMNnrNxJxgK+vdef88zHtmLAGAcl1qQNQzaBWqO3aMGXtLndpF+MBAMdPMG +o8BV7+D9G5PWWqR19WNLxbt0WG04YkRUo2WxeEqjkUKdC+fu2afkLNFrO8gH9fl0 +6J2V4TLronB2cUOyGGi97q3G85ROsyyxVw2bMbwBvP877jUwmKKxef6Av8WwoUxj +WZ3JCA9Wym5zQF9Phtgm07GrJyMTK80YuSChfPPy9gVhbGKlEM6r2hGBdZwna0Y8 +n7/I62l8GCiSLFFB7POMByI4yxfub8jpFoWsNvpMOaSuSSO30Gzl20e3VKLKqHZn +ZYi/9b86VVkvCS5UHX7vgV17uJO4VEVTYscE8ZIZWlMRALbVRi8gKIjBWQ/46CIZ +6motDm6FlUXhj4kh9TJXayOX7I+EK5ud7d1pocreyurnbveXpVb4ae1l3SFbMigq +00BVU2T90fN5nOgywKbdGKRWwvZYsU7IHjHN4gZyF3grHQWfZaPXMHEWtKj8LUko +AcDH6+UP0KFWLkMhIktfmu+RAM/Buu3hJadHdaOwt0U9CwszATPV5kbgSBx+hNmm +BpDeXAlhfDAVfRRg2S2qez4dbL0NvucanbXNUGV5Bxns9jfzHax/kO/QIbkKiObz +O5zgiH2NQNs4/f+t3gucv7iqNXMC/Ug6u6P976VwngaCV4rhwdcDkWx25lTx/MeG +h0geYsj5q/YPL5AllRaptlqd2SB16R1ivJmdc5Mrg+x5PErJ5oQRGKkTbNOWWJ6j +mt5SpTp/8cNNat+rDDOpY0EKrg7nSLPyke+5UBktpWFglPAkl45ztoRfg+u9SfIH +I/lJntuTnITxxlkbaRvXDuvTyp7zfbuAA17kVFgQY1cLxZjN7zEuF1rbMx+Yy2KJ +dzPicmFfQNl1Iatq4vlOj6uKWWjW2/mRawz8+jgivIwFe1jj+5UnieZHKPXL90V+ +0gKO8LZTFTIn5MXijMgcMmgz7FYb7+KZPL6bA7w7jUaWNhYiRw6il8ru2rV8phxX +eYzbXSl84ULZiSSIQvleyYJvjfyFay2Rd3RZaH+I+RySny8KKA0tQV0LwY64tWIh +y4xIun2AyzUY6r4kkVUMt/H/Lb/vGvvl8EKTa4FaBJh8EJZCstExqPqdFcwWu76d +zWSHYhlUQZbTfsp/bi9916XOddb0tqJIf3bNPaX69x7Vpqxu7/Aq9we+EUVWy5nP +HLvpiAWjU0LTxyJ/btbaZkRTqwqpuYjnGzv0FYnBHo0KEdw7KCqoJKynmSbE5bhW +e0MZuYZSymCgPe/gVUff7UUHD1FFmGuptZUeAMGhP06nlgS5E6nb6vYrtnd8cEIH +wHN9CFIH4qo9Uvdt3lu2Y919z+UrPiGWgtUNw0N++/i5k7TiZuJlatJ8/ZbAO4Rb +/YPCVxPahH8/7MkZj1VatTm01GRMZwpfjZm/o6WmI8wLyk+bCl5qYdE5Iqb/hRvF +HZKyGBruBO/NmOqWW60vE48Y0jvnGcRpS5fxv4mi3jEIQZe2PLFL9u8i73DbnQ3n +OgnNzJ/umKsHb1KbGEnrZ7axsfNTxYQ+2WVmsqNlqIoevPqQui3xG3FbIEth/htX +aeSlZ6srXSrbPdUkxD9fP1heo13SfKEdXhQpkE+nJpzwiUvWtmnCPOkCRwGlQdYp +YA9uxRO5hMen3T6Q44AKVASlj3roTSHiyGY7244s2xBGhzMJYfJQq5Bed1ATrGm/ +e5sIxxrfL1ANYkBgrAxv5LwqV85uhOJs5UOGUxYnRRvPxusMPfPqlZm5jJSwhrHZ +EbiwBk/3u13JLKuvye4Y+PF3bCg+nmOw5rS3jt3/Pi83CwgA+gZlwgWz+hvlkpmL +LCaHAv30IsEknmrsmQG4cU4Hg7H1mJQmtQ/TeQQk6zrfsw9//aED8+XjxXXFDJ12 +vqdKPIpLJ9mJjzS229V9vyW98oLUSVC5L+ZstQVLqVcPZqWOifJe//78K2JBXPoQ +Eqn/mKxcwzZyMhV5W3zC9OBe+SEBE1I/qz9RocuJDP2IarcWtxUc97hFafoAfNeo +OQMi2yOkuYuHRaeSobVg/eRfOmZ7qKYIvnVZ5Re1vqpShjpwPudcb/3ebneFdH8U +IE8KIxG1ilHxzJY+KTwoWnBT4E2uLTsqallDvaftiZofECSNhaIfNlihYD9mbk61 +amp5HSZEbvTb35JRqPwCAA6jD8B/zCeoqdHbUrhrqxaQDAhcIczsschjCVsLU+qk +1x1SwR//jMt9PTFbOZxFIMA7TZzhVeHTRy75RJmA9IzR1tINo/5jl2BMp6xh0+3q +k0Dhzc3qNn+M48NQcX7T/erZRjPZR3/Fv058Z17Ah/sYl6xQlEgmLOgJfTpI/2xf +tyxxs5n2dleSje/AvF2FaDpRawZ9GxnSPDQfwu3sOl3qz1X8NRNkk86iSO/My6TV +kynfQRIXol1WhyLTUpc4jSzmSKYPmfvKqU6pShKzjsRu1pzA1y6nhejsamkz9ibC +dQ5qPXu6hZ5ij8TjhlDPLJobWlQ4TeFXPkzkyeIO9qjrbek6c1aXD1TctDEVjlco +4YqRH1wI5nsKcdjcMi4ujDTJWWD8AvQSVkzxndGxwwOraEU8MZtET47QkXQHTNxS +XYD5HvuZExQ1Y1cTflS5oi9PSEpYgmpxopRn7xlRon+avuH/Turu8q0+5C1guJAj +89oPt2s27fCpyMsUzbP5P5GBpvvANch/9TctXNxdbwFUam87ZSNHWg32yMvjFNWY +aMsn1IYJ3cXdg+knpwHdIuP00Q5NG4g8ZkMjSkwPXOwBB2YSeGWgvWsPhpcf6YVK +p5U49CFncYhQlJqrVaCTv4+mY3ccXyGBTen2nUKkLw51x8vVukzcHQ2jerqwCM6X +mCwcfC7EHNMEmvaItKLYVxFTBGOZjJXhZlzianYvT8qjmpUEurU6tM+hvPyZblav +KFWK8cWwNOm8xZoK5ipGOAWiVcSgf0cHJ7PM9B7KwyrIVwSDjPXfH5fPFTLfN3hC +pCkPn1i3KdVpWokBkelCi4YzY+eFMYDytFLvwG/9y0v21UrAwQEBBzHyU1i3mxId +2JCdsqKHd6XbMjDlsED+zwb7//2YuUpwVzIS90PG9ReuShIrNbw8pXJAu2WBGzIk +QKRb924xIf4+BwwuQKUpC8j77pxENCZtg30gVOTOMWcSk6rVqZv49muuPOrYDnKd +uSFt7hihafHELlDcbTt394cTri37ZzNpq++TVMWYLzgtEDZCvcjIRjk6X4EnN3hv +1j0YNhVMrAsJhUZ81lHhC3d7lL4vJV3mcrISgEQEpOtODZrNoPwIT88bw/umQIyl +t9oFTac57MxITc87pW7cjP9+xXo9hkkQASOdiSqIxJFaU8+LHXzJy9nUliWXOnpb +Mh5R65xz9KnhZm0svlfk0b69s4Sk0z77pMGs6LOBTn2taMnmkjrPk6x9XaAXOB6A +LhKL/SzYMVOq7zUreG0tOyLH4CYG7Zc6s7FzV1v8JAPpkkCZleSAUpGYqMj5QquK +GSt2X8dTqDXMzdp5Y6DVhmGqHYSYShr+ajqOTWkMZy5JbVuPRt5preSijsVNzdpA +iaHACH/CDAIEmIX0GgwU48LZXm5/apjPTMwOkL+FU/dKuHjqTV75D83orK+FSIJ/ +Onhz0XC0afy0WqRLX2RO4XEu/4kv8O86wFbBfKZd3WW/SVyjeE2BxtfZnHalGcES +F19H8Aug3NtbjB9hRHH5AfuIP9I9+PXmtHUK8BEDg/fjKEvsi8WdH+wM/DC7cUQg +FglOomfARduEywTypLTA2E8quEIFMJ4ZBFM8XMwZF8t37I5tZWcjPeK5kXrjgveJ +SfFtZw0OIURzMcCks3IE97aI2ofybWwGuBmYVero5wXNORSbRDJyLKufFksgDyrn +f+r3GOGVkS9xv9S/IOgjaRsex8nRohlmLsYgabeoWpjQWBbMr5KfTsRdlSfoN5E7 +UwJJlHM+uxtopqrC+eeESL9m/liQfgqK0gEPR1xG6pX6vkauKyYD1gAb9afUY30v +f8lQtHUUVMnkyLdTwEn7P/ss9z44dXb056QB1uoGZgoasepiKD9UgWtwmVl909Zk +qLCnZiXUH62u988GFri74boVsSnsB9RBLDSPjkBG/Xt8qoGLtoKX80aYuFhy/ahM +hsv0wKPuv/TjgWTW15Z+69gkY48p1s1v9PXACKc6Es+U4vpCdQDDbpT0kD3oZK++ ++QGOEKJqEEbZS1DOaJXoJEfPFZ9texUAKl6mszMhulmpce1BpicL0q/ZT2CitlPd +i4DypB5phLkFzbA7wcGB/Inu7Rx4CpXfGeXILLF2dQUeaE4u9ya2SX0fFQQloWdf +lW1r1LUwXZDUh/e4L/dj792xfRSWlVNa410OqiFITpQkgvRP6Ir8GnvrCXDPso0C +2KDi0j/dicb13wUVqHfXYYT7yQDVrAkvACKayvAwRG0zcfdEN36SFYQ1dCm4l4rR +mn7RE+Vt0WbTntg8rKO0Oreb3DLRdN1g1VI3fNfXfMUl7c2K/lI3Eb7Ol1KkIhLe +tVGiOga9G24/aYcgqS5fPuTMoUleJY7NPaUjo1l9M0/n7qo1pLGmKC8z9NZb7Uut +exbaDRDUFaRM5P2RuA5V+oow7YtxPLoHe9xDIS5LdIatWM41aSR9UnmGyBlGwgOs +bSuRA5T/EmIDCiF/I4KV/etUvzMmsXDsljWUpN583FqcQ+H0zUqifyqanfofve9r +nhx0DmmFpvIQBl9z5BZ9a9tZA8tNjO/uVjvdXkcaKHWMw4mHVbSaRBS2aPILouho +b3VtmbilwZRI/92Z5Qkr6UCMETHokPGQlvFSJqCBWW9hfA3CrbEvvAAdE9W6qn7b +/F5lhnMrxA5UaMq9v8HIkdWsfxZZF3DOzLZiW+AqRUm2lboChUkqxhHAp9+vU4la +nW7/KpuuOxlv6uPQS+Hpvv7m5tUqFmuM7OQhnUfn7/r5mj5c6SXyZOQkVOKYCv3Q +lbRHIsSgIN05GtGpxL9e+GXk90hLHAxyTZ4Vc1PFV3VrUtlNXs/RfRfHfaJQnaDV +2c1zhUSYvR88/V2CBYUI9xK6Q42Gnw9ZF+0GSV+lt+z5EOxtvm8MLAHGX3NgQdS0 +DdiiaRFCS/SYEHVA6CjRkbWeD/6B3EodC0y/GzGHv03sbIqNc3Y2nOzsxWs0tyfm +IPV2VfKrfuOBWk5TAUdv24uduS9k06tZWibesYMrFSm7r7GyQxJo/4lbCnDpt8KX +nGio/xDlrFjsbLttB8le/4bIkIBTvAHdk7WUH6VP53hUVpFsgXvCHTzOR7ZFR5Hu +U49rB+4s10FyuvCQ8hrdeboPurKOKQKKzImsAx5KzrUyGVFjYUw382RH4NRZ0/x0 +/jA13iXU625VOO1cFe5LdiST7vVylPHOE9znaMlqAtVrbLBXeDzfO7/VizPWOmOb +XXv774L7OhLD968Xi6UaGX+X8FCSA0OxHL751jOTBJ4MAa7l7anji0FGwGkZjYKU +pXWSNLr6OJcjMuAQEV59TTXL9rz8nI6ARjybdKmCTpuo5Z6ICTKnzsYiGEO/I2XI +YUZi22ATTUXfL7UV3S82bQo0I2Lj23a1Snl7IRFICcocT8G8Y/oiD9Hvt89HY8Z2 +ZZ2/8Rjc/wkTDxhVo9stxQzUpJeSTBNlr4oWaSu9JoHBqw8lxjlRRHp9WJEL/tNz +QO9kIreGtAIDy8F+03A7qRGAe+Zy1aUrNvlcQs+DmAzXaljQSYg7HicAkHdQy7zA +nPPZtEulCiJ3l+AZK+tBkev2zIQtOHAEE40chjzHH7eHjG5dbFON7C1GTlzVhkX6 +Cbz761F6x6CefNh3AlvoXMfCKVNIF/lIyeVYYnlnpWE38z19VdZX7HswOfgMaT9l +PzRyaLPNdcWJsXj6ogPVmjB2C+VMcfuFe0cMkwHjxwDr2Ej9ZK/WZz0vIY8DlSE6 +5BPnlbxZ+rEGfnfsmarLjofPMONY6uJOKU6gYp88GIP0T6ofQFbRM3jCzeDWyZG7 +tvKCPPZS4aPKclIcM+SmSjECKJRfqehR1QYRDLc737O8VDGVRmRLfPVUeonNcQ44 +foRtA9dnKOz4bXUPxit+pTjhIRh4Cqv+G5TtOdy3mXF0D/IWeHRq7KNmgd88I1KB +zAYSIKPpM9n1SaytnKVjIDmVp0EdkF5aIW0k/GwqJl12fQGU+s+ZJJkRsA4Cof2N +LKpZVlHsKp8kJDKE8bvaeBvyJFLO3NCayX3PSZAoyna07ADj5nqpSVHA59GS0pk6 +mhtggMd0y3xY1SPv/bri8CWwd9WuTFKQmZRPXvyw26NPjivSWtptDHJhmRaSZg4F +sBV+vk8GalmiJiq7uj7LWPD5/kwKi9FIpllp6DW9Qlpfp83v58ZBr52aq++9XYuP +NtUwHKFzUrunUTHFKheDW8IUHBIDws62ZHy4PWvadjM0lkkr63N0UyWMjxqsmDY/ +Cg5W/1r28m1JRgoR52HNQfNwTRjZm19bYC/wedbd9rO5pDtHts/g7rkzv6IEMkCP +d/GlqgEiOPJkiq7Lbk1GCFc2tLDCUdDcbmCEr2qJD2kYemyKPKuq5CAKRgNNBLe8 +pNHmwNm21N1peyHHcWccU4o6PKtSMKjgZ99E5oKuAxDizdpkNhylTHqVL5ggGhd3 +EkLZoYDzQAS3LiotIr1iX22JkqWoiK67I/h31hX/bU0Mq7MsKPN+2tv3wRCtN5+n +zPF/zleNk2HR9mDPTxG7PotdZnPyqViRLlQh81YhUDZYi62wX28onOsqf5qF5HbG +WNauP4v31X6jls0/JwkBJk4k8npY1Wb5eznPzPhbrzLDwgB3u/thqki65+Hf26Ln +7b79byQD3z5SYWlpxsRz23ujN8PFPJd65Lga48jPdMEAAOFggIr1hgvzA072JNQd +ZulKotjq2lX6LgwXVqJg5Un+GyosztruqVOicqb0EKQqc0vwDgLKQMz4hfVeI6Ia +F2SP1Ls56Ypcb/hVGHiuE5vHNkvOrI/QjH/Ta3i1t1ki6uDY2bru4be9PMLMJ4DM +fuxabXLKJKM/iK4zOWcBhobLzvOcIdI1601aYqjyXkTYggdtcDLQJz2FQo3eCdYB +ZtaG1SssrZY7UyttRssibRZOGfP1Ve1A6KIlWwu1LBwFtj/AYTCX1lf+5ton88Jh +TyQjCz9yXNMNUusvutk3HYVSFCgnL1Vi1vPVO0ANI+waw2ew29OOiDcrqBtOhBfF +lyVRosEK9RCzUj8kH+lMyWNXJCjhoct/TKs3TFL5Han5OI3phlEcqIrPgmRwkwcG +q47LbdEb+39AF7Jc4qFZ9H+1UANp5g/Hark3bBa571SL5zTh878gke4EWWCDqq/4 +TGtcRF5bcKYzZvfb18NfPIHJh+L1TJ5ffV8AW0X7OUPTECk4OTh3YjLGTQ4M6qVL +fyYi82bwVbZ9E3PY5n9G8MCG20Dh4znJNfppVtus9YpSNiJVphvpRYy1im5sWxyW +eiQIADXrLEGOK6ndLRwJVwU12N9GdUZIuT7PZ2S9Nmo8SlvOuj8lZO8bccLVAqOa +GBuOz4Kdqm1M3EHtk3BIpkm+PpthW0w8m2qOV0PymdFxSByaSu3CCLms6P1ami7m +zvONXQmryZZQ2gByRO9wLq13adxrE3r9PKJK4M/OzcxEnKV8zPfqLolgdv/XIeVO +6BQPmLBL7h4ozNDKVcCI7miKIqgL1LCbm4Ahh6cOfWXkqgNHnS458WcoYB7UYCIr +UskAWYgYfw7/A9FqFv3BOmaoh1NkTE0OiFZmerwaQvKRtzMYCMB5SRUtxO5vXkHy +EFMkFQQkl9rXan/BYUeys2XYMV0vZiE1sREhF+yyOwJOhk4hUPxqF3txiiz3DXs/ +6dPvOjcPquJhsORpnj1Lr3iusmCc4zQIMS6w5oouHOQvY6UDAReRZ98VossnIJyK +RXIa5GZqgJqcvWAgY+khcOXZG8oz/F78rXqlMLniXcxVooLTZ9uG4ZaNYVikEgxI +VUxA7iHZ/R+z78oxJJznDv13enmrO/98HpQevcV8BcCYdvvepybhhGeVbG6bk6oV +qYKRpvxjrUhWGXP0U0m5lR7/KWIbecQQ6bGV0ziyyZW571NeQVsO8AzXX+0TO8nW +rvoUsU9Wx3qti35GKc8EgMFXrW98gWfdBMx3WeaSO4w4m8dp9pzoBFUAlF7X1Zcf +jDqpWa1tKcDpkqB0uzErscw1akyQY+G67QW1M4E9sfEd/pOC4XuELYUE+/NPkZ5J +Igmy95redBEIidABb7GcqRp0UHJijLFoGn++j4NBUrAryqi8AHX8otau1iYPnzN2 +OH2YfrLCstEadKjM8uzZW+kdls9jCbTBitsi02n83eGXA3vcJzKCx/AWgd65IbLQ +c7IbnMg9rVlZmnZ3MUnYPknwzMKsBKHMAInQ5JUF0eTy2ivEAlyElSJB1Zlr0/g/ +Ek8v4RKVAB1gu7tQVekmTc230tWkWJIRyG9z1lK2LPnhse5LVyWdVloZO/qm/lgm +adOWcFUmuW7o9ZPy3x2+lvkGTzoxvGkNyb2laJNiWsxYCERvGuBXHbHD9vQ3UEcd +kAXGPFfhWqWxrvtNXOQMaugFaRaf+59gZ1qdwLnkzJ+0uNlwqaVVKShUkGvFkrz6 +oXZ1mRvH0IAdJ950XGN7Z1ccnTjL1MwdxZgOo0HXo27s5aJ9Rdb/6lyRqpjqy/m7 +0Sz4uDsfqI2MnFslSEXDav0mOv/5ro9GzCQenSskp2NiZMdn+i/dtoKfg/xN1UKB +LmNT13Qc7PI7c1tqWHRrt/ZReAZvwKnzPUICN5rEDRNvz3UG/iOfB9w/t+1Rm74/ +fbr2FNhAFzh1FtjuXYiuD8AOoMqB5wVKOXLlVoxNpKyQLhBbuV2OjYfIjbz9UmZ2 +9kdeOiWx9quJ1oeHdvYow8J5/hikVLcDBes9tB0aUNC9qX+Vxp2MlKOss75Hgadm +T/Q70e0W/AqNm7tCgKQh75BNxtIS8D+D/cMoLCBtsZO2+YTPAclO2pRtFlcVk1Ct +Lh0HCuRKQ4nM3FrcpzNazJsxk82GqqTN2RE/ioBcBWLGRwhp6RFRokkFYperjTis +fkRTbhFiQEsxbLAv0yspjyAcMyD9jylxHHa6jVv0uEvYswjE01nNhgkB8JtQBIHN +dXHbfgOPQoY/Mke+8tTubzNcae3G0vdPuwOoGdGW+ZDf843D58dwdpnzTQ6XNJ/I +Wvk4sSGkNxlfz6okJRHpx9Cm5+gPwrRKJKE2LoXCk9x28cdpj+0jV/dQCuLj7NWz +UfKETHFFj4qCJNENWZpKCav35a5llrcgcwWEOsp3I0MBTKJSXR2rrN/zp9GgH5gU +Z7p+EsABfisuGs0LIq/k7u6Dut5q0sKGz+K6zY9qEo+P7sM4CdS7U6MhiYl8cHrD +VP/d2nINI5ZUgyrOkGO7v8CH8tZHvhl64GS9vCRqCjz90uXx3b+JHFTpsyMmxNIw +HXr9udJoC66LvvV2G8vJ+9HpDSNZyLUGb5p89I5iX2ZjYpL4W9PXO7ljA1ZRidw5 +T+JPhbMJQi6IpFAT7Z1/D5Jxx66lHSFNTYzQEbUmolovqljDQD63eAxuIQKUzXuU +v+ZZ0P79MM/C8B7lLIwI+B4jE6ku7AImY/hGyy0LdJPq9/t2/1Ro6GaHDEw61jhS +vpn935hkVpgOt90dnvwWPItfCvKMYL3p+c9EtndGwVKMKRKQIcDUW2qh49iWUYui +pgUCONn/LDxaT9o/eAyf+9t3aGdXQeorc3F0vW3MlV1PQ49z2q75UdDtzaSNJ9fy +gNYoCRXqFdUo5lFwlsJx6XsuoUU182nhFythlyCVSME7GLDY49jqTtCoJ+GExU9g +PMjXbKl1bfegqjJCIo0n/NAhks/2TT45mU0QanXQjLo7JirD/adXi0NZ6eLj7OWX +rMu110LC4+nLXG4i0DuK6jQmXnpmbVjetHKw80Ge/HdXrzpQRS8ZPvTJ7LsIxOOS +Bz6P7V+P8zixWcX3Bw2hNcV+yUTY5y6Y8+Mcq8pOPZw7836r1mRTY7P6k6gVLep3 +ixEW8sMUclEIiPr42EazjMzuG9D8Z2aq0vQbnzslpGBPoceSnQX2mP9Keej5ux1j +dXKNb/VMBLTOlPkQKJHz44Otj7Qw9J1L/QAwP3r4JQfuirSHMr+RUrFKovlIrMPt +cYUJrJCOB8eQTSb3JWbGKmbSNE47/t2QmggJgfZNyjPPluiIodKzyACxDWt2kv3J ++kabEukYi4GoNOZuTsuHk4M+9TCME9I94AcOmynSd+7naB5w+Ddn1XfGih+hq9pX +k8Ug1HLtvwkeCS29DXRLMnvMxKG/cGWN2Ks3y0OUG7VhVPkS4ciU83zciG7/wQcR +yM3R52pOdbOWOV7LtqAJR8WtGCge446nuuPQ3/h3Zrpoy6MTezJ8tu7MGUEvTz1z +Edo+r8wvmr5kt2lInDYQjXZlCEskNM2Dsd/WHZC7mkLUDqHFdL4nfSyRYZCRJFoq +MVV3nNQO2RMvJqPuY6rO2Y3tDhF33Ulc6uURsiQQQuPAqsBxF1Iq55TppHYsQ1Vx +Idul4Cnll6sri7+pCdFOOuV0gTogZgfqqE+QnN/vnceEj50chmKRZH/F1BKbDJoB +OEVr+eNXZWPl+e1NpalqJhVjn0Fi0WhqVXDqbePdzfaZDl5OUCDKbNCo1aZbCqqm +bDNiVvdM1nGmSJsXvPsSYhOphq7at8o8TgOOUbYt2cu3gEwPPC4jds9MmkbXpjBR +xzsqIbDENujeid6t0+N7VB4WS9+i0JeY+7Ly2yXTgfPuegAPkphLj3xVI+DcnlYR +FeGcZd2Qo3/T/fttiLIQMLMkyjl/x5aBdWtHnHL8ioNUjjyqQdNZeD7fRBuUndXA +vP+ZL0HpBJKBaGEL11A06Ke03BU5J+hWSc4tHJwwuuiqcpf/I/8CUZuV+FQJzPUn +NrNPXjGAGHBcgX1LO2GGznMRNacWqmt66ikfxQpGLWodXWgUi+/zHzt+1fct6Fwy +6Qdmex4CNIyXbiz2nzuVnm1LBTSTz6hyMfuXc9OyTG9sI4cXwaj0S7g+9srk/pYC +tDYgt2CQBlFh4f02XpbPAiboTD5xH0pp3ZU0QkUhfjYvLd1FiD5K/Kl4ouKHOtHr +QdFeqKuGzG9AD4lzR/MhSJyBUs+Gk9sE7ZIUgDXlioLh8zXgwxVfQGc26TzrESS/ +g3GKSh1HE0Swbri0vGi9THVkwCdmhvMrNJI4ymQGJ4mgF6od6fAM5J3AZsYsoml8 +rCa73dD4UrFQk6/r2SzW/0kpPd7VCDHYKPhsvj8H9GMOSyH3NxsWtXEIKEW+WmPT +tGk8cniZerhT96aolQYq2xx4kYyJRa8jMHmTDUH0Ar+EQ/MO3BLAW1vbxQ+DStco +CJPdFSS9J0sWfK9BoimaaXT8yYlI3rSzcI5RdvmiJw4J/v4EHAOlkCyRj0NVPC/6 +brg3rUxQF2qtKT7YzS+Kh3O8LWnVlwgMNJbUoF4+Q2xK6hH5bjt+M4xpoEjKoAOS +EmfUsZvCkIt80O73PoIvXOAZay4pp4ry1Ssgdc79+XhIWD9G1jlpDzQ+w4ExZvhK +8NWdZ1R5JeoRoh0pQEPte2BXbZ62oEiK+5et7zvbHgCwWvVHzp2sK0zSFvFIZ8Ti +Og9yOXDXBGDOVW1BDBdgiiyMsxJq/rOAi099VQoZsdCDgmCT51mjvjsQ9HTQV+Y9 +h/oAHVXaU72ogYVQA1kEhzoXAGWz5P11UPh/6HaNircqniVnxK133P5BE4CwE91E +aB29X8Ds8DvxwDB66BGnkiV8k9OkG/qhb+FbFd3gR7f1gUI5LDCaBg54p+5yMv20 +6K7bPREX7+mNd/mz8/JPLtWGsNaTk5mMcyXzztWkX1Jx0SD7vZhj59nXoWLqxzjE +sKC7t9D9vJbccjM+ZZOu0pX5QvGKDd9ve82mV+OR/EaSy8W7nb+yXL1/CFGUbl/+ +7mwehw+R0PULXjFYtFB+HlhwtyNMibnGSA3iaXq25io= +`pragma protect end_protected + +//pragma protect end + + +`resetall +`timescale 1ns/1ps +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +PmlpB/6YO0aYZmLonOSfv1AKI1gSH8MDYymmabRlHFrShbqvDGa8mxE4q7jVthDq +MeTpb7dntYmVLpQ3jrou9qzgE3VzCDgyllo3TuIcQpf8xbi/clZ9EKTPRNrkLHXj +Jn2QVUXy1p5jRGkj8FP9VCUZbrPJDbUrwkO2Q2VtHlAdHQAM6Z7U9pJ6k+4Lt6z1 +rqGgvu8nZroCzTOKDA9a17sB/IvYRCebzdw86ug8kfwFO6z9joWnFo8nHyg56sAc +aAcfkjyAi9uRiIQ3EUPJmFFtDYsOMqGzh3SmruIKWWPaL4HbH8ef7gp6ZFGqR+Wb +scvgrPSCW0tEJhX8tcsUCA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 9184 ) +`pragma protect data_block +FGHQV6qyvL9P2mdzMtBf6ysGowZyPSEb8mK2B/uwInbUMlQwqOl1LKarMIzLcVVN +pNXodSwWPs+yWcpFZo1A0q7pR8/KYA9ErUAfBLveXS3xtwJk/69qmW1J86sXrDb9 +EN4a2OGoQhCvs9FITpUsknvW1uSvMAXAgD4mSNXIsLV+HK2T1fKojXZadDHED4s5 +jPKZCPyAzVgfSIYTAPwui22k+hYubEUCNX1nXIqb8gF/2XTI/SW+4xvaRfFTiqw9 +BRJFIE4801ZSr7w05i0MOWzf3ITw7xa0itEPexfmE5ONII12ATMOBzi/9rfKgd42 +CitshmLHG85XD4ioUN1PAlpKWiq+KkqusFB5ApyLjwE1/4t2uQyS/RaCHhf6/p9B +9+v/nueQSjZFT7/LvfUoBEo2zFeiH6g922aX3BGWyXcloUzjn/yMQUBCQ5o9uJLe +18Ghi2Xhxqve/9uMUk247v2rmlwhla/LtkCH3DjnEawWLoK7Yw5V8VB81bug7S7M +uohJ09epc6KDVq5uputtQjBFmHQZ6x43bqNV8/hoAulTXbBwmMIdmsvqpPKZcncO +BwBJ6nxG2FxUoTUazAGsAMybFDRBQ0j5N0OUC4bR6FqeFJUYpGBm+MyNeiJe00UO +8a+yN1RwfwjiNvKy7PmiXw5b7SJxbU+2jA7uhGYy4sGqn+6ikxh/nVbzub50l3+9 +h6ma1i4wCxHu9WHqq46tNj48u8mrMxS2F+Q4VRAby7qGF1u2W+8D68Pe7RJyTtVj +IyKXly5CziAtte/wXJKLh8FQ2N9ZGzO/7/LQMwghsFeNYhg594eF/5EhPtco0SrB +O0o9JJrlsff6becYm7XFmqDAYrEbxjEBjDrthom31OGTz1vSA/kXMNlK5kMjrOyA +nfnOBCNrCB3+ZL4WftGEt9+XM0kMj4y1Y0s/RW+W0zBgUrspNWO5jjX41XDaXPun +4L+Ahmwo0POtjtt8skB8gbkJFk8wY7VwowKfOrHuuH5GQAA50Tiv07qoiLF5rjia +o4L55vE4AZdKaQu2fSaJYFVjzrd1JJyw9EgeatCyPJSJXbBUJB2nyq+2PzjmWzcH +2L9jC3tZdby1D1mPxmeHt1/9NlMiKiYx9TgSA/L8NsCans476eYXfHFk580Ziuj8 ++7QXXtQATbCyShZONTC1EVYO3ZoAg8aLr5Dxy7WAkjFms3t5uwb6eWc/hE32jGDG +yOnMTP7/iI+PT5p9ye2OK9mbB8qbwj3jWSHIqlwnxA+INAQEkqRzID+hxSrmlmE7 +QrXaq7R+23tjt+PPaD6Df4l2dLdac2Q7erlNhQB5nfKVy/AYv2E+UvGeUfUAwXEZ +P0XgkAYXQ1VDQYuX6tKM2a3oTikRkwSG6KXJ+QjOFsntVcLheqqF6c/Vlhs7Wr5p +0wOGmHXc4QFK0RZR9A2rZDi2DqMAgIaMUVc/rT+od8rQuxbfLApsWxwdgYblQbuK +fGUM6PtsNnFVaVcAwKk69lOXa2k19j96JPVv49Nzxvz9FQyeDepegxy2GpRv/lmG +qHNnzgZB+NUb8MwObhkCr3CIf6980czBxhNPi5yAlhsvZPmoBm5wj8jWjiT8m0f9 +KVU3SORhubl4A24EzPwkJe7FepJZc8bfD0qs6n5kMSJnGDWvJd1ge2+hvnoStOlc +hwj1U4ZkjCH4MJk61c+UpJx+/Z3pVPPZDQ4TvEdbiTrmUCJUQcRwgIQsdWowKEgX +rDZik46C++xB03FEcKKwIDqxLHJK6Geovzq7QYTlKk8JMjb13MgK5aw6uJ++ipDB +5Cxzgm/Z+x9L3WHRUP7wvH86ek3CqDc65sXgy6wn1uqWJt/8msa+0af6Y7Pf3fvn +lI8UD2ppQCsYviH0cpVD8TBVzjIZwhOzBY2r7g3y51gT97XjgNcNkzW2ao2IqNGn +a0neMxRjP3TShgNzGCMuYF+383wGaeZPxqttmfTcwTO3ydF57ep4wVGXe1HLmxBl +RBklFk+iqdG/gK82PlLL02JCF+jO4yJ0Y7akEC4oofDnljC+ikO4wc8hiLPqedvd +NO/U1hn3TDdm8lt9Nz4jC3U7+dKHU89fqNvKWZG6ledOpOqCr0rAigMWe+xZ5VWk +2wjRNS6zg3kXYCQT70bgpXF/Ka+JWxRKQ1f+bbbvSNvn6fftk+WLrk9kL7Mi9H35 +laKd1l4eu/6fYw5gNGDzYRyPEwLfDAmVRckRWtZ+POBcbPU6N6F86cH70rYSosgz +B22e9kUIIOLaNGwB+wy3jXPMAUK3ygm9MfPqQ+toWvcsaC58L2qFlkSgJYq9nLGE +fze2l6WSicUstMn+8f0jZFdk+ewzFShGTKDI8+G2FWJFb1JQRxkSEILUYhL51uHQ +PcyqvExdoAY5rz1nkMfHEa2u55omLgPj93d2AjdlSdR1GaySgtLrCGN4OT1PnCfr +aMFP+69fEV+BB1XM/t5AY/pw23Ky2I+hc57h5nlCmQHyJ4QstcRF+63qJ5a1gfTa +cyAOPRtkeTWY4nZQDHJJjmGyy2Z/6LO+4N5lJHSu20pgb5GumIoNc2XMbs7PSiyd +H40yoWH/kk7YotIA8MJz6fFkhVNtr92ou6qi9YHrAt097XLPN6AUDlwxfaEwWvXj +8Xsof2qB+DLQqmWTKueGEWygvL9dlqVDdVVf9lsSq1w6LIc3/MldnXxNsD6FEFvV +aCI28AHJJOYBUNbFCV1H8QOF42B6gZCK37jSjChai0Faf5wtOzMaqHwgGz7p/Jgn +Si7AhQBXSJgWRw7Bhcl1xkREj3IMHQ9sMOajGsjXjDO2/eGZ3t1lyJKIgKHN7Ljy +3xMt8OAFhUR28AEYbySZ+87IzcoAhVtqtx363catpBKLUVDUjjrYQSQKQqZHMTEX +LbHzLcIU2PO1vIQmJ/CL2EvJmnaIdS+NI2R05Gr0rVNRIJaQLDV8sCSg1ETdKIrr +9mDkPz+somQhK+GPpO9bHGtUHeXcwu8ZGYZihVeHQo6EQF6yjrzd/TB5e4BUCVaT +5jJHCaXh0838EaYCLGnG471LhikeB61KftgfvaH8ByxUH0W7wntg0cCgBIF/NgDf +JV3L0OtKJebw2z6a78dXunlcNxbM4B6ZlVJ2hg4Vi263m7W+HksqEVUhU6dmxS7h +GMTHs/MvA+SgsYO3VPKHh9OdHxydFdmkNOX0WCD7Yle1ZGTOBpajmnR9IP89G8rW +tzgLKFhhFDrNVOxmHS/lx2Oq1NdUTyyX2JUPBVKP5VGrzWXiH5G1o8x3L/WCCZUS +ZW77xOHgP09NoW5fafzRKZRA+HM1j8kV7k7fVi9IR5eqQpqsWXh4akEfZ6bDRm4t +7vWpeJH6a38gYMA/4k4qahFI6b/FIxEAn+NtoNjGwc982N2m1iZQKx8nfEcFDDev +fmKl4VbSsyVglUX/ja/TxiZwfN22rBOOuTXAdDbfOTYUOzYTCtlYwbqJ+I2iXiT0 +r49KI/5CqpkkS8kfv0uuQTDvXBzVtLBuyQJjLoO87saOSRlDE1DqBeK/7iMibre1 +IHR5sdcO+wkDn2mtnXCpatM/uLnFLblZp7WtDBX8Si62QAEL6fHHR68RjjXTup7B +VA7D3bFCZuQ64hf9icb/uWkj7+cNCVPWREQA3ukojOaM+174Q9Zyu51WGgKumFc1 +4LYVKG/TNAw3YC4c/dQyZwmh1TmvFEvJB9SxC6GoLREfsGIGDzGg2qkDGj/c8QJ6 ++7gWIdoBQTgCn/LPpEovpsjAIKhn6b8ehiBlp0jGJCvYVcmyD11k6buKru4f36aq +bQr5BddwHozJrCZ7UAqv4PMOyq5ilPmlFumJpFid3Tnx8x1U9UT6i15Xz5JB99vy +u2dMrFNN/njplWeTRHfqM2edpzbLfZZPYNzKLAVyrgjJsHl9QvOSVCFiyWGTZ2F6 +kJyDO9gmiyRwmW2Jq5iMkoq3DAWVH/pYA9Xidto6DTyZDtojAbzVqKoG74Z+4lqn +ILK7PvV+C9Kx45e9D71hfe8jvMaDjvrPViyjpIwWDXhr8u8dUDfyHAdfno6d9P9Z +BMEd2ZAXu4YxdaujoheOsgMvNn5OPAMMXq/IXMWz/RAUL5QblmeaNQZefEU0Vnyb +Gmbdly3Z32WlB88d76lmjdEgTtux9sV+ppQJujHzoOClouZr/+JyABtYkfEIlS88 +1InQqcVEcYsFJE19Ff+woV+I/doTI23HiTIwIDw3DQW2osXzBvELPY285P8/KK2c +pm8vK9TUcrn5S2YnmRBMlXE8QCd9L451jYgjqGxJcNxFeSN2zUb7OgpLssEp9o54 +f1YCcQjBoS0m+5W51CLYknbTzYk7IjVfefH3ahzgH8mZ+u2l9ruQq/3fl0Ej9ziW +ZwncgiogrrK1Y/kyrnyDrXaYHUYKyFxIBNfs+PSkw21P5lh7mAb6Drb5y9u5d8jj ++Q2KyjCHCROk/eH0XbZz5Sj5oM9ahQNM1A0aCx2KuEAO3iHSVDi6VWyiNVxvZPcB +fKT3tbky5MNnd2JO7lA7NewT/Rinj7N8ma3TN1nW3VK2H3/49UP7cxfDeTWFQe1G +ZuxyKKWI4fZTyL+xdMM0QBw6Tb8NbWfOBVJjuxnIRMPWMvUQajHFxWtNm8RWUoMD +AYkI9B1OUrjiIsEXRcIE7eK+x4ppg65qLLcQkGJYeotnFrrqrK3ptwh8TYKgzroL +znChFlI+P7KtjMWojy2L9aSgiHoUxGb8Y1yxLeE1QOyIPvYOAV7XLz+giWovnAny +0/mWaD6Q/6q5U73LXW81SWakaZ8nBZSfRKezLOB7Q+rXPx8KaFJp6KeQPbJ/u+Im +lZp/iSYPjy6vQ7/bQgvUgPuWKyofNXsciF1kyCXX+gSbhXmhfDlvX31sQp5njg6b +4b7G7m/mqbyX0RtJYkOVoh8uOvJfCrQoLOqSSd8c9jYiWiNbyQHVLgdNXYRf6d7U +mFh5KhIwvqJb+jTL60gFS/ssQwNv/zaDPrzz53NwuSCU700EOM+1hATchCTaSLlc +XGLKgBZVHkPlbnaI5C0vshaIN4gubF7CcdHmldlaRJCviIjxOyfapxRHFq8A1231 +H5jZBKbzTnwlsVlvSPWURjX3KjvR23BG2A3sAoqNIRD/yQwMPLXUzVlOfoszy+dh +GVTDVYknVJ9bHFR3wgL2a8YvDx+1ICFXmlRg/2MZaEPo6BBTGONLnTknCH9vFSSi +Dlb1dAs/SuxP8iDOiF3wxAGu9ZWSIYXIlqYL1KACvwEab4/q6K72UEKBIQ/AplNE +yd6ktpfpa8hR7RMBTVErq2oDK74hK7+kp1mIE51ij9USpPVJYBIEI0dxKHlQi4FG +k8hPKCvBbpFs8oBGJy6PZrI2MhJQXYLZ7P5bnOeY0mfDhxpK1W/8ZBpc7mB31R0X ++Fk2khHCrysvOPskTddQH83T0cVernWt/5IjTJju5HT/j4J+tSGhFUM1/qsAwKpW +YIOAA/PsdMS2Sfje9QqXo6b1EyfYAyqEMdZH8nUfPf4rlKaq0sW7w/MPMvPY1Ega +fUvfXE2C46lTCO8dbfH2v7neHH/HKPr7wRvGHjRtVvrRLwyZsm/nwTVsVI/nug6L +NIJJrEs5nC0lpiMmnhK2BmFBvJeHxNj2OYEGLX7Fp7T4LVo8P7GZ8BMPlzMF/mBw +r6fhLr3K/nxzgr/PhYwwN0hmcTKFMMWhaNkdiy3rgcYQKvMWAqH2A2fCZJd7EiOt +WuAgU+EMbxHa3o4mg1hsgHr0vktOuOnbLw8s9XDz6s6gp5Xqg6RFI78BSI8FqyRz +A7q8u/++pdf7ZUT72EtqA7xlWtIheeF/X6wyGeMD4fTcrJ9CJgDHLJv9BchVplHv +JtDpI8tb3/orr8ILZrMDlx7OP6OFnLNV89we0pv2xSgMznHDT8UTBtb8Qj8mSF0+ +4SFC9llm6Iy9L7swA6qB527eFPvfl1nPidYFogq3BI/thqL9ndvu+SHayWLMgDw/ +6TyZwn2zsdUjUiVp2a0lcoL94HSJB4b6KxAoyuY/GYxh09ZF/4Vk02eujQ0ouccE +xKoIGngVC3Slt2DaRsPEdfo+3pkcCkS8QX0B1+BospYR33gtdn2G8CtZshL1zHbR +fHV8vHkbTcpk74KXvDz3DWt+Lprddq5G698ugyvnvaig5FXPZsWgwVDsN3t8cNqX +aLUTn8QQICK4Qw/GZSs16nLcuMaqCT0txA8tZqB+f6oxpturK56yyjr1hkcvbdKJ +wjtOps+ZrGE9CRVod3Rjoq0sef3cmGHUDhkK9RJgUTAlZhKXE3Vuv6gJQdkPd1kE +1O3zjNjTSqCjBgrb5PALfb+CVV9+qopHXvmgd02Y38uExd84oUpj+O/TdouRzJKZ +aHxNOoR0xmix5MyVV2538aTNVLolPL4y0iO1f5/wQhOhScioU3CDstV0a25O1DFb +36C40OJnR0wAFVzHa0+l4CR5R4svNojQqLv6YIfkS4pur2TM/08r574kMwPXXQUk +C4moipASEz00kqINvyVnW4YQnAMXQwEqRPeAs8dkWiZ2qXO6jo/Kn2Qf0tcsz45U +vch1EcFlaD0DnklYJoiK4LM2w8ywBpQqnobuTXOe9zCmYxWds2SjUwrDqDrFYSe6 +IvH4KA3wNk2V3tfusLwippuM2glCh1f0aDTGMI4CImmg1JbR+OPMmVzuFDOhmSgw +e8FYxahRmMyLOEZf9riLe3FcEBdk1DnGW9SzREGR33U8jKvROxeBPDDwExO/w3d1 +vvzMi7tWq2IhC5SVVf7Ds19OQqBwCjVFALmvLMl+MtrXpLyxMp/DbO02HcKBTInF +ZI+K/I8EcOBDSI7kMqtlDTVUqTIyKytWJWzwQ8MDMcmhSj3YaO45QRtv5oZj51gX +efJa0BTOg3nnsbFgUVVdJK+PWWwrpO+p5NHdDoQ+YvSHgdkly7/8EcjPLtIBExEQ +Vb045HmrE84UFwImxOgNnbBn1zbXVB1fRUrEEfdverM56oNG1mQvBBCox1YuI+k/ +xDZ/0Lbz0ixMpvp4Z5wLhAJ+ZkbmJ1plrJ/8LuaufznSurKNnbdiNNtIzC8h/hdr +bqNdXVNUFoS9JEfF0cmcRn5GccSGu/ESNCk9OaPwqLf9+cRR45LtukNEt8bNAYB1 +oWFemTMd/sk0vShjrvO7rMTO4ITdXkuSDpIAo+IfvJELzVkLLpe+uDVupNQUKH6y +gFXP/Tmo/H6JvuhvXVZ2inb1nrAmUsxSGCSH0Y7+UbQBMP1B/MzEw7XVmGm81gXF +0kuTRhTgQ7u2jrcvzj8Nmyj+KiQEFFjb+EK629jFN9HX23lQJEsP1lDADSAKzyGY +eyZ/ghxmPj/pwTfvK3gr0BExpcCZr5eDfe+2LVm6U/KemUESAaJNzhQDDodPQdLM +nTNc79u1uinhXAxpX7Fi8QciYI1hpSKrFsDjBdxX9nHOM4VHJjb1atO7Pd1vfWwP +xQLfsgKKvokbo6lx4KTomorqjLltfULZcCfFR4KO6XMeJ7r4o/F7kZMMXzlbbN0E +bRSHc+HTq9O9/32Z+CNSUqGilsQwo39XPMRPUR4YBjY7lN7FkWjIOodTh87ZBufD +sV8urDYFyYpvqhLCGwLgLzZMCx/4QymouwKW9iu36RpXZk+P5bO4xVRrmWSW1atb +nd5GTXRLucQ5ej7/PRxOcgXJdMqMMVostHDtjQttulzNL9xiCny8J12/YsKDON0L +fuSfCuY2oV8bc5N8N3+ECmylRXUTCvA0bwXt+uCYqEOwAli0hgB9pztPCqyH4sQI +2iEMap6z38/OfmW63V2NjADQXm1hOoMj4oh4Yk/DLvAxU9mwDtZbrl/nfXTyFCj4 +ZKbY9DEV3MMHdOXBYOJ+b5Hm1hHrJtsqqQlbKayk8RjBHOM6sUmE6AthPovAsTHP +aheXM0HcGw4YemJyLKCRd9n8odBCYUogdLi1C0lAeMqLWBXLsvIO8Ze0zaOsv/Pp +weLryxRqU683PPPQnZaAVVPeMhz+1/W1+22LtJ1g1LC8YKWiE7m/9WTOM7XosRSg +H0xF/pmaymjh/CgWHX9lWbY9QDZV6OT6UuFK9ChVc1h/pdGKt5q7yL0ranGQu/Uu +nhmDRtPButETLs+mTKaiNEjILwA4b1AzfwOnqCJ2AzXKOWwZaykepmDulNJ2su// +u5t+cAw2fVd6fX605f8NBhusEHsfNseAPpp7UQknC+Ilm5pDE0M2hE0x19cr/GPj +HhFDrbpraI0HjL5fgDuIC+afF8VOpPVEomsyV4xF2o59pfHhiSMlWWYWxxkqKf5X +Pph//xTK5hvetRfe7q1/706eXEtlCsElteFuLtwoMmigCk84sTQiCHAFO5YTDwoo +3j5YIw5U7b2JOwzIBY0aiKVWngXsDb3Tc/GnKvBn09b5a+JmGjKi+aGtPbh02QXQ +eHhP/EN8NOHN+990narM/DJhIEKOx8B6PcF6Iow6GwSp9rXrOf+NV48Gew+scvGz +UzZ2RWfgdgF5SotRXgVjtfaWj2IeuqjCqUQSc9kCs0kDMqcHKBK7l2AByKNNwj3n +38Oobi7xlHJyvGVOC4f3jtJWVTOTG++aUo72cNJ2RegslMOOkE0zXogb2AZeGhKR +S0o5/BrHl2Qp5q+PzWrVWkGLEsiVwY2nWvUXD+iHkYSzEVaJOEkGCrbtBDIFwKdQ +Lh3jaka5VEYdUoPmb2NPrZcDuYB1CvV+WQ/Gawj7KRUqeBns0KPbAgTGAaKvIVpK +VjIUVKOZs5ZdK9of7Sfr2bSkEH43wu0uUrLSIMf6LkT8G7FnAq4G5gE4h8MsiZWj +s3A+/iFK6ppqDvcp1F9UxYw8qRu/2wGlLd4eBn8n3ITOA4My+EXyYcdMGNVVIQIR +VzPkUDdkkIbftgbrB9ssX0qzXRxSjBaLckMRjIFzx5Af9izv2Edkv1k+2TS+FHZx +rY7/IWU+G4xeoSxlB+RZWyHOUS9cuT7LdePNM8b/pCaYBG++B1ag3M2iMoJL2qZ8 +6sehls6yV3FnysLKuhqMd5Yn0IWTDLW3purUMrDjf6ezU0bwr4ckErZWutU84k/C +z91wvNpy2oa5kquqSKl1sJmvXih+bpadcTPdfIpJF3IisM76aEUuoBWldYoi+w7q +pp/E+t/v72ICWgF22CVVAwGL4zlRSG4dCvVCeKOPXd29VlKnG6zmLKZOxy7KVa7V +SkgWL80ZuhiTu2zda6LogUPHGW1Y3u05T7ee4FlNUuMf9s7J+2AlpZfvwnwZedAu ++OHFFgCR9a5cQqMon1CiPBvBU+u8spLPzFgQ+FaQSwP/KXS2wQdxyMi+hV6h+O1r +TX5pzgq18vbSwi9R1aSjPOHaoQZjqv3kWMb7q8HRRq3kNKHXc25sx4MKswHAfkMQ +Rj47vgObsbfDADgisP3Ib+/Ex7q+WruVr/ip/p+aCjeelo1xl70WfQgYkKea2bLm +5WMM+7wn/oz8RENBJNZj8iY2taWCLxhCbfkvTaxqszemrojVTZnexo7Ez52rBegF +hgMg5WnMEcZSOvRle7V/DR0vvoUkkjUqxcMu35DmreJAqeLEs9XtmRc09mO05R+X +XphyjvkOSvs8LQQoR3U8Pm109APCDFVJRGpmH8NYGkiNKDTBvsTW5br3OLrjhN85 +xSeKLmghqXYy7bvn2W2aEkRY6/fWEWxYDkKjJTF2EYip+QPCoS/kF1IvSehtABEy +W00ViZiH2MKHm82zSfdG1MGC7IflZlRwvn9gr8ktUfGGd9DOSUEMiE8QUdVy+T4/ +m2Pok8sWnEbUfDM9NIIhdfa6sY1+SjnaYHhkVRfTv6iJHKlj6uhymFpsB/P7K+CM ++91tWd/Lzr+xyxlVnWfAE+HV6DNkb0UTxe/Rs6zU5YHyaQQJMZu/ro/3yplkDsRy +eNCLBLSq1/eFLQrhaQucfZ7poWhs+MWPDy/JxUoVm7WEToY6kTvyAR9PcmHG0TSB +hopnFs1xaXvszjf13aHnTqynHR34uEP/zg08oU9Y5bOSWPZff7RNaZVSiGGjZpzy +uwNYxJ2TPZBXJdJyrLPg3PNrisSgbdOTwsexYGzxRwl+xfho9VwsubNNrcSC40M3 +KPDR07bwuPeF0BN4SBc/VFlvVbLyUIk7yswPIyV21xX7k6KPXSsQADAj0AmD++xZ +CHkrtBCSQqsY1X1NB2c0GGbsthCNd4VJs6Xwv7llLw2rTEZ0JAeNnLRRfDoBWc6t +Yk1+afgRXlRY0y68j6kyPKnc7mIR//wYpHR0aD8IRLlXMZn+iQgDZpXx2uv6bUGf +atdlwLT5HqtdqT/G+Tt6+WxbbxfKckTtcqw/CRam+A2qFORh2ldV3MIK8hs9jFv5 +z+Kn6NjUOjmaaojA3RfFYOTzsKPK2Xa6uTUrM+iimSnopzg9ZhhUHcf5xbWdivou +ylwioEUBQ5No8QnTY1k+t9Kvm6aA5iZbpn7jjhLLz4P1ZodaLZzvnehS86XFCirP +cfPd5i/2gw8mv1NoQJLDS+wyZSVBqyvyHG2RMKLvUF7jdRDN1kA6O3UGz+Cxek/7 +PCONO5vBroIQ48YmlePbS/mWxId0Fk485w4TzkD8kv7b6oYEUsMWsS75HWYF2+Q4 +79RFjsCz+53ZR5QEMLE1AAeoCLn810C/hxS7s7E+dDV+M8gmar2Oi1WS65FmWYqf +rtVAtVxpEH3muphkjuUauwPN22VB92Qu1JYl8hoStt6b0I82LpRP4JurLlk5WnE2 +a8Uz+Gif0lfod3awons4qVIydRqPWhs4jKwgKt4fpneRFd/Qsf4PCdXCUgOTp/dg +AeTHgspdmHEyilg3oo+NYd+dBbxqRjph7VqzxKJAa0qA5fqgKWZon3UXdhrAxwVe +YQYsU6P0Dpi++qFWHrD7hMMp8pxq8bTm5cnowhjFKZyMCu5N3/cAjd/DUYyiNuh9 +zYDywjCHDRbCS5nfyPCVySVt4BpT0yfcdq4eNT+rIfwMSxcWp6HANTtEvYU50EP9 +eBq8yaBrFHiFvrcG0us6XD0jf0JNC7FgfEmQSQULag+eMLkw5a8ID3zj3DF28j8e +1y3LHZ0odZRUJBmkOiM/4CzweW913iZ5BI4mHqirrOdQghXvhdPcRgAN8YVPb/JN +KrLu3NSv+OYZ9MfJfTnjyRnt4J9tzQnSJd26m4ibeOJxrXi0fITXtO0h0G6xMRr6 +BagAt86k0XxGcgKR5wbzjkqjqSVELaBJ7YjDub8tuYWVQuvC0KyfE34pVVHGgtds +2ydWDkBvtPDVsbq7UYiRglDXzo7NV1Hbd+2XucJLjb7gEUHqoNFTgJYAg7QhtaYx +FpLlKbe9a1NiEcb2L8sVNX710Rujp1d1tYODQcMo/ffOnSMir0UkusCbcfVDm0AK +PPhKrtrJ42vG86YnV/CfeNobuSJbv4ERE5EyL452EG/5GVz/j11IELBAIT/h0Kci +qB0tlwR4Ub0EezVlXznI8Kq9u6KgsjfV0bfV8fbzUnZDp2F8FQ3CqUx684gznDeY +M/zHw9vWJTEz+qxDYhXAW5CAnEsNHaoO0sp0pvUXROjORaa2V3LzR0zTDS6Pt1vR +OLRC3XycBX0xG5OeIK5q7exLAaG2g6OUko6fwnxV/PnRaH3o+gs+UvW+1E68YfVA +zgpSBOdANw+bEY8UHclUSdn7D27heLi2uAGfmJsR23LkxBR1vylMfd6QWkV+7pFg +wsThh+eO9vgDcf3/01iN52iGWRA9HtquG8Dkbl0LaW+KZslEHAv9hjKCkK/Rhpz6 +RNgrQgjJC0ErECLjkgoIfeFjroBOSmhlYKogIAFpUruS0kTRnjUxZ7PXlHrr8cfg +7loKXmU3NorEezi1B+SgabLkJKPV0L2/Px0LsvsE+MAjqM1fBqCb+GWI9zlEGKMv +hB+EfCw7C0bqVHiK0esOCbhBRd+azsd2gMQy/VkrvLkhyWtvfw//IOO3ngHbz8HK +mck2JQRiKcWB5gWkib1JK1Vp9MWllvVVWiv1q3ucs2G8p03F4VFfv7yd+ERtCauV +2EyrRHQsVLGSBuBRJeECDAJAKoMEF4gekzax9jAyOx2sGqfmwEDb1jL5G/+u1jtU +9Qk4dHKgULI8m05kPzk/PkWwDBQMV9S3FfWjKkrm8xR9ft52kBzAlzs0NzP1O5sz +6ZG1wZdJd9qR5QE4Lm3gaxPvccjdjlGoZH24mwloYWAG2mgXb4hutcoRBINLlkOo +c3Isz3kUwDcdTNryYiDmxkLECtp8g8bNrabmdI1goigD2qwcCqktvWZl8SxtFcnV +WspkIpJhdVSfmzKexGLmdg== +`pragma protect end_protected + +//pragma protect end + + +`resetall +`timescale 1ns/1ps +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +nUxQKBNOPAXm4SMK2ufDYCaxH6chMgD/G9EkTxUt+C4Nt0uAomJL0bJYD4mF8lOC +r95tiqs1UL9IxPtBQ7/tBv0W/JFRZJ/wPbPiqsu4V9ZtWkRNwuwhOdkOe7peQbYK +zj/GKqe/6NnDKvo2Xqr8SF+tE+6MaDB0XilqCHc+dyO0o3AqDAhL7mynjFjvo2j7 +F0v0ToZFohVnUNWznEKxKGU+H0NlmNfYSoUlYleeUiwQo0B/drPTh3EFxzaaGSSm +pPi3nW/4vKGCaEpyX/VJFfaWzNLoaHeq0OqPZ7aGQpV50GLpDMglFlYSca6t4OZR +MdwaEqtceeAjFhWd1AnrWg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 7296 ) +`pragma protect data_block +Q6fip9AYrrc6csSM4j0nGbidOqnpUvFllvtr90ruMh3QiH6wgCa3Y1I6FB++ylFh +hIfnz0EzOo0+SG0Wc+s9BtsY+Q1dCChpha1qQ+FWmJwH0ylGnHU/vZF2G+coVnb/ +mnQLB03/zpjBEay172RecdOeH2x7ztWgIzA+bfJDtvnJ8tOYBmwP57I4zENEkq9V +YU834CcpTWctHvMPn9p5bdRWIMD5YGFGw6gENULNdAr1ISPBcDLCwwwDCrccHqo7 +B+7rlFPC/C2v6y6GiZDH8YBP2HfT5BcPJRdo+9HhGDIvUFgdbwiJLAsrctiEFHxo +y/kL3BEz4/CSFMIMIlcpwnBM/JRxCRuNBS3pHTJ0NzxOfP9KyLOduKFzGq5/5XYE +KbWo5Ww+/881aF6xY1qA0bUhMLx4aoU+4JA1Ny8jl/UU63kCqTDtDSg8LvR0bbFa +CHIiDjDyCvsQiIRSD/yOTuAn1/m5ZCYHLTRQo6ZtFb6ov+jrgbPThCEKNmVWJqoJ +3OPNjVnHf4JCP6EOCW4dvJ8jDecKctTqcEQuNgqHQcwggqlUfzM7JKRxyQQMHtCT +ELDN5DUETXncy1HO9hTCODvRAVJ6/gwOZ1/FEzPAnR0Atvq6YyOmPDe8fWO0wRRo +fJ2mCimbWcnDnYRYtUtlBex5f7joH9hc9beZiOJmwnf5Nfds0OvNSs2xlT2hxJEn +OcS371snjjJ+60l+b+qt45RbdwLVWzhEUm7FtaYRqX9b8L0wRYa9EKI6TedvhM6E +A2IhdD90G9eV6mcOQnvoLS4wJFJgHru5Xa/K56U8b7Vef5Sv3Jt4x2Zby1x6Mycq +s3C5qj0yNolPaJaM13SgMyZKf/OXD49EXPRhwQQJeV7/3V44GEjIbCJ49Q0Wskuf +n9jyn00Q9FGxrJReoBKodFy0A85lmBnNqX5Ni70pRh+lUOTnALFX+0veYpFf4CpI +W3vM+z0+WT4lr0zChxnFXDFhWAlkJjtOn8fcMMtMoyg5Jb/8C9oM8FSS6b4+Tqjv +saf8ujF7F+BDbOzswjqZP6cvj/WuIUPiW9MdWmg0FcEIuNFzMQfYciXi4pCc65cF +vgzZcLmiwLxZjQn51VvMjqPgK/gtmLqdLamWVBjIl5DTm0LxwjPsbkssQ/M5yvYV +nUo+Q7QbcnWQkV9R4D4mlLuU28An4OcdJeFRgpq7D3/97Z2IjqsrU3vDV+LDsdn/ +FR2cbyLD2ipf0jsGZbhhNxmfkTvYyYoGdklMGCfNVJDzlW3+AyYJAmE9jcfi5G63 +AgHw4X8gOvXCyoYDameE56H2kfwxlOvENcET3WJXMI7XnrnbG5TZ51ukUxKOOCwg +ui+NMT496RJdKcaVZa+N5hXzVPNY11joE0bjXYJXo7PZF5dqfsKXms/Y56SHhpbi +GuNgVUzlNcCPuil4WTkcZfWIEHFB7mQtQ9ydazrIzSQUCmGJ+xeQmdUE9+XdTsN0 +21a9b2Ayq4tV4oxqExHScUON6RVY8qD9bKNdGR+cK6NLTsN//sikvcAJfNFnukzq +MzKq1C8QnNJ+0k7KHejyqYqsr6CKdpdoE3sWlJ4JxPABHKGZXV2qJDbsM+/bakhT +vlyKWGEJ0Afl3hQDdvOYX1vhzT1CtIkQHAWJ5r7KX94grHVWdJ9H5jnrdC+hyEcx +Qqg6XMT/oYXYPf1DfuZQPjm1XXCJXYIveMxivbNmY2Yt3ZWrSWBwVsaIz2fzQKVS +tMoT65j2DbBjuAzlxB1+XrowwxBIZzRqv6Gfc2KzGBZ9jHstPkfSIwevgy+etgPS +3HQwTXpmvLI09d1tMVEMLr6CaJ27LGp83T0cgC2pHHj5MOAdM8Z/t1hxQ1S/xT7X +MIsf+InTh4cEBYXf/fUZag1Tt8BVsirYvbnC/kqtN9sHvT115rFFScIaIzgOr84k ++qK+i2BueTRhV4iCxx12D8eqLNSKPAUMAYHNmFsECekHujATkh/AIL7e7srYTBH3 +mUHPUrSUb3mqpighjRgH3WDKQ3x92alyN5GxP0vAdNsApilCgjB+8sT5AzY55NsQ +WEriVOpUZ9/29nmdDX9S3E/AYb6g3J5cnGlsBkIm02pOFgY2mWjbLJOO3Lt9dDnI +N5qxM+qSbcoVzFIYnznPwyTC0vlrEMiHSgMNHFWYmUyEjtWPr6CHA4k0s5PH6pUW +lIFt0JpCYIupXMLmYOb9RitMKwqox1ltblTjVapDi3DthT58hetpJhdXFdVLSX82 +u9MjO1NyAZlL1kpfQdGx4DQAqncvqFumRZL798yvw19lf5UHjvtzCFNevyUZj0+i +B8TCfk4QpVWxhznPURJm4txzFeZj4Wz2SOzh+HSf4yd+b2eddV3TSMdluvu/G9Ee +PqWL00J4S0D0Ff8QoQF57r80l//UDpxQXQ6t9NGqPkMx5+Sgjcj+sWsAumaIZNSw +C54Nca4SBm/2AOnZPP1/T12XAi/X3OsoOK77S2l5YuFg919JW2+rj3e79I9Y/iJY +wROxbcW+7FXb8vgHROIOwuoKeQ91q8A5kBCeq3j4ynNyBePR1sjMR49DD+Oo7Icl +Dwu+Iws5urc6szjWAUIXa+r9k9I5EFizKTHaf1B3hYt8z6EdIs6hFRQUDBLJ9IgC +0/SA97eM47MmdmB6O4O/12wtkXyZsec7jY9KaDRZ2Nf7dX9T3fU5NJsF7078BrIX +uAuj4DEunJMePjVw7RCKd5vMlQczA/UO1mGaCmQmKWiC+BJLSqY+w/fp9XWLsJ+N +7pyv8KpOhAi53U9awGiJQ6cEDfcvbr1VHanD6oyPrcUWQlbPSS2dMg+cHLeC8OXz +0f0Iat3sCBNDKzRmwBui7Qo5t5OagWjjZatw77ssxXyyL8o+uJn4xMWRb6EmchDC +B5z2oKgijN/Fq5B1/nyYUyUPdE+JuQ7wVci5SwZPbxgIEgr7QdgQ21d6mhrm/wAP +F1vjkebNndUr9qsEvcrkIrvP9fjQ87vyto7jCumrO12GcWx4ZwmQ0y3D12YCw3T1 +BtQlxHYkZ+lcevU2vRoTkFdnoBOtQ+V+vfdRD822o6hphpKdLAraT01y+EMmclFn +L0Go3uH8JWtsImsPA1d2AaWrp8XSc/VnL+2CajeYUW7SXH+9V4OhqRoSo6Qb0mCK +tjtYN7RC7HITqi+rNytMEXClrRSVB7EbgKCimOyhT7b9UfS+BkZXnf53n0DLdH0Z +K7mT043yMml62YYl5wVKBQiztpytWucEm7u9D27oVvFOp1ybcsvtN+wX0FIbuN+v +2LKOwapkCDI83rkWLLbOBS3SlwaTvZj+pI0/GZMLYab89eZJEWd/kv+p8Cv7hzG8 +JJIVk58qBp6WMWwT+qIay24yWaP+OvY9vDd/JRpngXkrpeEoq/DHv8VHMWQ04acO +sY28AfcPxJroWTPdnVjHbYkETCeZsYHVAnynMeLu28jwDsp31yMiULdxWqOtN4AL +JP0TBDe9PqAZikAAXdOOZZX/R1YDCRKu4FCAEGuxnyRierkb0K4jRqaIZ/8A7b+Z +LCzBH0dE9Xje+Zczn/BVZ7nA0nErhQlcZAG+JEjTj0E0zqA+1fxkRw/7AnwPzFTC +hBtOSswTlaixJs/Gz9AQieWCJMPrhD//53rySDQgrSgmi6Ug9ga265sxETVr4gsP +2VLvJjurTe45X4l2xjGOI6kk2g3yJ8D1EG/HgqDIPWqJ/6CpFYxcP+Yrvwb6m/50 +0Wee9VPJy0+jNH8csS7nBkEhxU5YA9yl7z0gODt0OiXgmt92k//3rIW/yzfPQFTH +nm/ES9HTnm+VCoa133N3EK39QFzfRcEIYx2uzndeMGd7J7kOdjC5lq10GUcZpMai +VgXX7PK6+1YIsm6Ssgk+5FnduYxaWShwZkFr9hKL6LBpnpm0xifo1o8g7IXnkEYI +pbWPcX3rLxlAfrKiit/uZs10FuyFC3k3gZ9exAQdVzUZqfDDNlecnzcQ+sqpaMy6 +SFZoRE4K1ZqRvly38lxZ58zmnefwNsKl5VOpOdycO7clF6Uu0pxgtJjqEx1/JAYJ +S49wIz0EJ+AjoxwykzjjqgU54I6p9LNgCZpIGpI9hqB8qKz8gjpW+JRmZt/zaRUp +AgPM6vE0vJ1Oduvs6PRrcDXuIrfjc0aJM1BPi133nixHlZ5/m3dL8dwpaxPX4oUT +9LEs4iQtLMaAStespnirSsirc+j21jnmx6IkWQm+W0CF90gjFoFAMJ9h35cjtAE3 +Id47YBFt1NgH4ALSTVEHV7x4IrjxQ2MHMdAe5LXeOU52VXddJ6gIvAhML5X1tuUq +BPP5VCeeUzM028RmoHLJqTOMIMCyZODwq0+6AMcYqc2KD5ere1lAhN19RuCk8EF+ +tYJxyIHKQAGZXiAZWTX668VqwX34aQSI8xq/wqO9p9oT4vVQyM39HBFNOYiasza9 +ExE8a4zoBs7S3SlL6jS58okzRipapsRMJxG2NRVD0Xxdl81VEqpVH2/MVGOsGa0U +8CRaVKh2CO/0JIZLRsBxPp5Si1CNQz2fOz2aofu+hmqUZ/662XmBtSV35E9y0NHi +QBHnsezOX7jQURZfd+t0C6X3O0vkJ2ELl8z329YJeJ22wQp+ZpvV47brv3vgVxS7 +Cy7MajSuAAco28StxVDrmWuzIS43R7shGXm9wgW7YF/SqhnIxLpWQgQYMUzG36z+ +stURUtjAqw5AQhperfEQwKcyM7Q29jZO67RWaphoEywrf2bhQHAbhb9JSZ+EjbMb +G2fLydbXtrvxiYsVsVq/EBFHpfM0RfdOjvNy5bNJi20jXcCAZNu6wUnj9vZyIsCz ++B7nB8bXx6TMeaXV2i1iwjkBGW8TkU5VxLQrBkNwBRRBHY8n8dF/fdiYorN9h+MM +8/5WMDXFr0kMvkLIbidyJ6/0hthDOqN87LDkSPx3UFKTu33IH8QqDTtI0UiV35BV +Gj2Kan0BJSDy6OEn0HqK0/tmmoqLnmZ8posT9j92XqKq6PaooQbwgaRuAMeS06CF +2ozcKr6eaL1X5MFW780CW2TNUs+/gEBMYSIkOU12hOqeM7Czro6fksF5Q/rhsNRa +G/JRHcV0i/CkchOF11xni2mBrYPkewNr5sCcWEj8AEhkDJQdl+toe+XH5YFgugn2 +ArE0OLvzz5iGS3UhZruKRID3ElhobPIHfkqlBsGEVqzQBci7xCQ26roIVFi9aRGe +6k9R/RbZ0BdGmvZRpNXRaTPXCMrSh31xovUUIgWW8270DfHz4mkojQugfgmh/91O +NnHecOMoqLJdprdM8o6SfpIe8xNHfFYhg7rSwkXs/LOZ8yDENlmeNqx/M22vqTpu +aZuHKAuyqNG8q2bw1V22MerQft7QgZ+nJLm4A4iHt9l25nm80mTDS7dQawiLyoIZ +WApRhI8v4JSenXLAPs3ymEhw2QKLI6rK5Fbi46/MeaZq/suqIpuFwjIvBNH3t1+d +icJoSOVp17VG8jEydqt0UF1JBnouBBjJIh/5BSoJyRbApWNY9sexXtR50ubfoQM9 +7ynEVkXfIPd6X09pCqqRiL80hJJxPwm4mrPCQA0fVqlICgsJTaDg607xmUopsfPj +zSibNtReklJqQLW1+ugcuYtP/5kl094KPcEISVe2LCVTUNTvIX1mjkSSsAACx4Se +DH9gjdIxh957Fd5AdSbGDQJCDKbfaaFGwtqVAoT7tGE2fmRqh4zliTDaqEE95eYH +xIHYoXoKQ1803qgfcNK2eQI4zbSePZA+5LTJsHIYPt62Y6dgvI2mvsqDy5Cl0cQO +GITr7KhlZZwHp3jG9CF/FOSsSpbV/5oa2o+uBomc1zvNQc/pLhRwySvsrXqqA7Li +VZrlg8RDO25uNQUDfaNpMDX/pdrP/l4EUOkIlHMAscUxYUtqsC7mpKghqorujTUH +bO2u5twNPdExGuBbtTQkmBhSwBhW1tcs6FVHgwkMsRuD8EwqOe8bIlmkzvkykVPb +Skaig+S7NPEUoDTI2Swb0bOkHMt7cTzzfpZCsbO7YXOCKmIrQpEK8JyAhVGwA2JE +UDOVWRnFY/yIkn3DdJ2vHl7B0GKgnMeNuYWJI0Z5QDt1bD/hFPCRDvIDIGsz6RYY +o95ESkC9rpOt7mk09RDhEitJO/lD3oOgSqqEO6wPM7Os/i4YD/+NZ9LeVGNfI8u+ +P8pmJOa2GNYG6Q4VtQhLDuuwG47h+7ePdpaui9+Q9E6DCO1R+4W7qAJU7JDwScYU +mfTGNfj73nwBPJDx7e645Wyr306YKSb6qhrv9vFiPyZypc2EI+DvPX8W63fl+fxc +pPsFLiB8oFFE/7nmvlPYtsghmmh2QUDI33XjLyvLcjQGKbR8ROknj9X+68ehmZEG +vqdZkedcr9QAkivpHYq05CqmbeJDeiXjGQ7qvDmHvHoXcvT1M8Xurf08+Eiho5gc +VlPPGmCznj0f94hcS5OC3utyrKgbwQFKmCdif08XfS0M8P/Pn+8WJze0Cx7gWg/d +/Ia4J/Hp7ShvoIAMz1wugbk2avFiAWAOR9rbhb4HCV3PITFYWizG7hkWweiLzzow +5n2FU4PpU5plWvATgxrtOuXxuAtmYVYwxC9BpCcmYzLqZ8H2s9a8LEQF9hlfGEV/ +iNaM9rPeDajILcFwRJfPMOV81LGQIQcNoX7JR0dXtz0q/U7SS+MPGC5xS8AYS7V3 +QgRmXAChppye+enyGIFS3wkfKUM1b09zNHCj/iodg98NyYNSQpHrlKG+/8lrixMG +Yzz0CtAS1925TJRYOjWQbmePV9WOdX9eZr1UG4hmJMRQc6mmdSCyuewKL0Zz3ylI +qK9C/q9I3kaYFoNl9D44ECNGZVCIIR6ZeOXCJ5C1X3XZJ4kIL6P3TQunaWzOA5Ct +tt2yd+eEnL+pHQy1ye0+n0OAQUDTRuJOgTKz6qQ4uSEiD5Xp3OCO0WLPtqZXgRfn +/XO4QhXVFMOb1U9/ANjQ34xYixGn7GmH5077LWiHlO2zpsZ22pofD6lBqZAf0XXQ +uWQyNYWMgwbIrwszEcSaUNJpqtAuez7z0NSAhXcXnGIy9QxHuQdDRhwLk4Urbo9E +Rb/wrGLSL6FhmXmMtcxHgwPXogBzwMj3TLwxnR4JhxwACnD8CN6RNR0mIfeEWgzw +qbm18AzglMftnR5/pcQR2yGZKphYlhWEfutjAt+IQDVQquH/0zp8NhIGdt9kYomv +a80reNjZ3O/rgXEz5aIqH756ZaKQ+FpuxHKdvkwgHgjqw5rqhMbiEbILG0h1LdHQ +36DSg7+bdi3r/vEeQC6uNW7VvGdO7DDNROfCvPAFvAkp9aISRGOa3SvWOE9miHDt +otdifgoIGeBDjUe0zN2moAnUR8tY7jtigKd4KrX1nNK5g67JX0pxKLV4sV/OLhDe +o3naAQS0McARa9ym4EWzALwi66lzON6YZFfgD+oaarmFDQYzhjeZazzitGAIsE4S +Pmy+/JTmyPCOL81IschhjRuVQBA0GDaHfWhnBN0x0L0jgXX4flpqCoiVO3JSO3FX +jqC+M5czzC9L+259aqMKv63eyxizbwFTA3Hh3+xmIjBSOw4bcwhoFiHR503ncLSZ +euLkt8WmvLWrFUBADX3dmIYSFdpFFgZPa5QklofIW4EEAHPTrsE1hZUerzqYJYZ2 +ecNqVbM3r0mV6Fmz5BjgIni7OMd9/OgPfMUnZ8hxQ1L0ZWRFs23bg2t3mfs0OroD +pnFUlQb9553X/f85OMuQBnQCxoYlIHjLpX7bmGWJw1ZxPKOnEz0jGZxtsNjCN5PF ++Tj1VydsDG3tqqi7UYNjAqnYTF5y5DoC2UyaXzdkFS83yOubX7UPpuBtKJ4A7+GJ +AcxNZTVPIwBf07qIoJfYUlCjFWEXg2qS0xWUcy62V2lkEmcUKzFMc7DarhhBz8JE +M2jMXQZf9ze3gLmVV1U1c924nevzsCe0/9lM/Zmq1COdeQ01O7FqJi/3Ds7jfG9D +axN5EXmFj/0gvAHVt83YTI7yZ/JE6frXwRiI91edNk4RWFf+Oj4afSNkw6icbcep +ca59EkI5Ynz75BOU8WncIhrkVFDaqnn/YKAsOEZHPE0miu7nyb40Asi54+LNCJ43 +ZXgLHy4xQVJJidYioBGt8YtfYa8P1iBn4irW1iD98BtNNUFtBSiTlfJRsDxjd6d+ +odcrQ75X1VNxQMPySLxJWkT8hwVPVaQEtlZMoaXTltDbwqafq1iHoCUHRMDqrk/B +GoWgC2Ajk4p5fsGl9KvhIYcXD3kDn43HctFrogekW5ir9PszL1l6rTrLDAo2JsOf +Sz41kx0W3QKb+UrVD5aJKvtPN3mVvBpf3t5/gHenMLvY7OqDEZz2z5tRqFGMiemv +qoh+2vv7LHbxPFlJFjz0mW464CnReU7ET29fQjAqW0d5V1BneLiyYWcQYMLPH8Mg +puh/ZSh4UTOvrRkET+r9mVB2gTbQW2/PqCa2J8HTRBc8OS11BDLj2ED5N37w5SuH +eeucQHGXYTzxkF0Hi2h35k4hXXZNSF5zu62fBXBQRjYmK8uzC2hz4Y27dKsFK5pA +gCpBGgRjV9g4rz9P1X9ksYML3moBgkeN9Wm2gJRItPi7k+oi/RxWOhxagR8Bo6DT +7YEzFG8bmTS6kR1ozpueh59E8meG2UI1wp4WMn9ZwkehlbnAkBW4n9f44H2z4dEj +gAey0FxZvnxKnt3reIeZUi+001Zwhs4VTFwZF8g4MNywhJe0gnkKF5DdBUxXTzXc +uOGOsT3e0caxIv3KmiVUOQV+As0jqGd3wUsgh/i2xA/3lkpKIFqfIzrx9PLhvSR2 +PZqikRQD6i1EorJU3/1nhTnDePnIxmxtwGkQFQKyXiGKL3GuKnvVIBTicf7Xjra3 +zEvaU7e1pUCGRB6ul37jb3h/Ul6283BWXBxi3jE3R8mjMXkK7kop4H2SE047fYbT +ofm8QOQqV37K2fGczgPa5byD9EnOLNDa/prNQZjNKuBJcTOM7R+TwKzba//Zf1wO +Ap7oWVHmy2RSlDtGolQQpvBSvHOmolAP/5IuaPaXN5eyKRkfBk/YeYNtTaiBbNh9 +Ps8hFQjFw/TvZumIZVHY7NT3U5tHvI2ggrjlMkgHrDWGbPtZWVwWdmQwu1EFQUqq +MlI/TXlQZqXa5NC90NDGgBV1Fi9LWQb8KBRQGQI78U+NmnyiMThG6Iy9ROYAe+gW +Q5hTOtvg/PNxLniPcx6ak5ASFxKxwAggikXJnUexFVurxAGKZdiBxIUvdShZwmx/ +iutX1fZy232qr8OGxrv7ekQT3d//R3S94ezYaA9aKGWerGftBpORepKbrEtow10O +Sac1eo2+m4wBx19voN6mxnknfaVqYkkQydwXmWOeN+msSbbCsHOCpxVfWrznj9+A +VEF2g1vF8iYJRtWU9lzUBxSEk51Bra8DbMmvySFSvT0Sc1kz8wAYtGcQmkXkYLjh +AAeDMJkC5DGT9cO87uNe+yZjbtaoMlwTDlMzC6Pg6zjKlG672zB/kV6ay60jqT9Q +Usxy+cqV7FYQct90gsJlVgjx6tpYc2BHoJVz8srifZQygKdLcaMfSalT5NgqKEz8 +Yo5OTpILb1IfcWeM3GH8QI4SAVCRtVyoj8UxBZOMXXXyBp4Av7C9mRqW4YxX0GG7 +4XH60qtENX+q9eqIYQpQ0xqBlyNGJHtML+n07pwhb6G+RD4ZuWSrhfnIBxcc2jm1 +UwdRohaGn5ptVXFoUwzz5Pu41QWk6N2ZUfCosSz2vOojOQo2csahEBd+xhJL7uwV +`pragma protect end_protected + +//pragma protect end + + +`resetall +`timescale 1ns/1ps +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +MItf4LQolnfNNZYJvjTV4ETejF9FWX+Iw4l1AlQF8c/u5UZCDVmqg2Z2l3n+esxQ +tbWXCpsG/kio6VnHwWXHXsEhunA/mY2EAnxUsfL3KKUd4+4eAhtjJdq6aYmG1IAn +eLYlsFV5MOuibkR5Bk4JLcZMSNn6d1XdMUxIAvwj0O5grxxtVAj13Bcun1IXhnp2 +s8I7f+zNaUtQMTYUZNSicjSk7p8QVxCfaTAmwZK5E7qQMcaFvHjPEtG5nv9ne7PD +mQnlHeodgRtKy1OFs3ajfiit9bQRYdPfmBBJurC1Gn53Z+6x9PiMb6wTheXN42U1 +6PnKOGnFskNUTm9yXBibqA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 8176 ) +`pragma protect data_block +AkpifhCv11FqdyW3SLOja2cvQGwIgr+vEkQ5XQrx9WBU4WbQPBi5r02VYk/j86Cl +Zkx7XpMYvsHTVC5SL/PRA98jiWoEr4FUfL3DbCS3KygzmxwjF2e64U2t1E2zCwhw +7ytcZfB1ap+8OW18VvA1Tc291fOGATSh1Yp1QZ0NosjhYdplXxqFEniRM96FTvgw +B3IbQCWH/VG9lTlKGDlcYw84ZuplhWzz+238XKfs0qkaxng4sfwrfTJtMAnzAiY/ +/hEyuT8MDXHDrkCQhhqloZ102sGTeQkwy2mD/gihtzC9O72YsoyplYAFo6F0fib6 +UWUPm348phjE1gkyqR5XLDF1wYQMxm/O5suT3ESAJW7/Fj2sPyjMTxTFbyI8g0Ml +AuLsZyVg8JuhriK5yNXQLmUBSHloM76A2p2lc20WT7CtuZSH1u7L5F8GxHAd2Zqs +/SQQ1hYKHwIahZ8Tm+Qu4WxNKDUJ3w604WFft7qbcS9jZJzqPWFXPdC3n6c/5BB4 +1839ZDZSsa5W7FcFram5/SoQeQ09cXuBl++N7i626NgBOFJ+bQKd/PMlYIG3QaqZ +292V4BnTUVmBcQcfg/Gz2Sm75fgLLHioLwY/XkeQ/o3K4r4psWeLYIrdSbKSC9Os +A3lWV1dibtocr58kUrVJCdTiKq5rMheVpcBDL8gNsOS5GO/HmA/i0YlG8gWa6QBq +NiDe7hW+a+b6EhrCjvYwkgCaHJObadzlmj4MYF+qxqNS5yXyEX+C8aNBxGgYdpnp +Uehl0Z2Oq5TcjY2woT8dV7GY4PNiiZ5c2yI11DpqG5aOnoAWPKvILntlPdrOZytE +tjohqRRc7Q7SXnsluCWFq8tEL7aiLO1LmwGVNDICm/kpq8PzDVmKxBFNoSbaFkvl +ISBglcWPl3IUkIgG5LuGVsrzbISi72kZyobOpXzfCI3UT66OC4OXGC0S+utjtDlT +9D6dbZIsw5XYRP47RlLV9aJxVXzsr7KaeEiaelHqrUQ0mfakVTy0I6atSSKnkhDE +G8yNnXFLfCaFjTpDjoGjfMO5qdxZhhuItrGRPz2VS7z9XWJC86iTNPfh0Q40e1iy +4DhMqf5aoQxM7OeO7b7SymNheb5kqhrMUUkokrfKNXoV+92NGVdxB192thMo6lP5 +DA6Jv3RoRfOZXfkkwcT4IOBP6IrId2ep3M2NTgBJQxMhVzLm6ewQsU9zblTXKs8M +/sWwSlB5xUYLodCfPoq8bDG+tnkw1dKkFLNZm0Pvw6wrQyhLcKfZc50XcFtilqkP +TlrF2N+MQMFu7+1meJ5qDRDX9LHWGlTE6tg2f77lzpNWZ9Dd2z9XPWuhiJQlSea6 +E9aSTM1K1MgK71R0AjQygBjy5t25YdCRtfa1F8Dean/X5NhoGdZdcXC/FBw9Soya +1lXWT9Kqmyk9VUAjZVi5cWMGCIp4Jq2MYJbAQQgXcfG/bHxDT2lrEBeja4R75k6Y +MWUYC9yZhN3Z6PF1aDUiP2rUUmdbFfJPWFs+tAnJWMQy2T5qHmUiugFNk036kzzi +aVyGvAzSnAQOhihwmy1veqjRSAhtjIGk0eNhVHom978G/h8BAGLFO+btIv2lFHmg +mOVbLgPpU+d4Tas3AdP043j03d2iMlGF7WW3fzMQfxjF883keQK40w8+LdX9wG3y +Rp88Y1ILdeWV/RDwCa3JUTmcE4GjAGyuu36mXCUbresySS4PRp5tFz/EopDr0qEn +StOEeZEl5nyOCMaI1QhreVPNPwN+zLYdBOX8PbOZJwira05+mXzpCqrGUnH/IMAR +7xI45VF3pG6ENBwdPW/O7VefIiv8Hg9ZgyeQi2OK6+PrxB9H9qYUX1uS4QULWx7D +rywd4i20iU4rVTR5gMO0cBOKbUZHC3RwfhC8Ofi6oVUdxK5GibA+bTmRgH6dO7Kr +tCT/Odw/9qUbIcbWq1dSgiReAOc05ma8zV01apvywEbTWy7auliK/OK0V/DYf7d8 +1ZoXfpd6quL4IIabWVifWiMsQhvfp01iMseBnU0kmy8Sje+rpGfUwKzLkxF1+UQE +djBTdUfNN/roVhVmoTAzsg+qeUgdUqhqkQqa18IS9Mi8nfq04PBtpVt4A/2zZaus ++SCXVEjKIvxCLVtaCtlhHNo2wluZaKOQAQzvGKvKE6vX6h0PzUy632xl5IuYamon +oHOdD1b4buQiPHVGpZHmyWMeyoT0jkinec9Rp65mzCpb61Bl7kh0NFDlfM/LINf8 +kFdNiQIsn55/atIJb3TchZWDRi69zDUCBYjKk9njuTJZPvSVLHpW4OV44fTMgR50 +fOKFfXeoVDGY2vjDFu6v+I9EnTVVcD7yhn33zFBOEpQ60+/DXjpLqOGez5TjOOvZ +e2YLw67CQ8Q7hTQJct0TTCGqGIAv+rP00qvLriF58KTq6ZpGefrmgiM8UbtsiAfA +ofsecAPiHDi6dz+o5a3Sn3a20hsL2rujwAXOXHzyXYqpTMDP5/az5+dG8MTjhv7X +QjbP8HBs1Kt2DTgWg1WBsB0j/4ROl1VKp8HWLFaRhGhHX2Bop2/sALiONqSQ6n6X +VHzTD0IM/rVu5yw1iY5vgCjsTyFQm65gtXbURvCizRDz9QT0FNuwiD5A8L1PYuhW +EPTtTibSwNZITtsdO6DxDnnjxBy+r/36YwVxOhyvg75T6DfHOTknQoq5O8xjPXMh +CBs716SJvcD/hZf2ThwoiFlDCECoOVNNcaRrtLfIEuOFs04ctVx4Fjf8hRQhmLca +b5UGAXiea3D1KkNE7y5iBdxJm1nCAsU69ikZyaNtmO1uB1/vXG1YhAv+YGcuIQJu +In+mi+6bx/XbJdXq+7osu0QUAQJ0f7GX0t/qlNatvu9oIqdaY6/YFVxh1cppeFGI +40B0hR8gR7tewLTAaMsuPyRr8LijLS0U+gMSvfN2ReV6xZgUXRO8zRQKy5wseFM3 +uyglsQz3TIk2IxCQPESh86uNezOH+3GM7y7qd/n8ap3dc1jX/OPuCwMrE0bgbsX/ +AnI9sf6hLiXMBkzPtr18KOqlSj5e9ZWlBPUzmjrS2Oms9lkBzDjjrGRVcohzuj4t +fzfwIVF4KFgc3NCht2QTbk3tTENBXFQt1eNMXlGkWLgguGNO0KoLL/CQAaUjemfN +0nrrPcQMbYwWK8fnUzKTz2xPb0oBz8RN6wtHewIRPROIHAVTr1Bbdqw9s4LFT/1c +cJrzbqAM72qEkROdvZb4sLCUQdKEm5sXh57xh0AYtPf5s5zlch9cd0uULiKAqfac +1H8GNNRs2DUG/udSIwRq4Da6qpHLmkmymgw37TME8XKC96tP1KdZTQTMFzATh3oo +fhR//KjyM6Ghfs/oT3XxpF2UcO5RW5+jDl9dcsuCLQ67GKmbeXop/qQKkcQHU42A +m57aM8g+VlhalY8aTnbeRBJr6EhQ7pyjbArYMLCL+qTu+UYs0XhksZkiX3icIm4Z +Plaj5KU6fMhIGgSL0d0LflwSULBWOfyxA+lny5GLaLKdHbuV9u7Gf8jsO8h8tf3X +Bq8xkA0GaMEMc3SZ31r7zFQJPuFSjkdypo/pgigH7xwzKo16NoE8saih/6fJhWf7 +C1kP//ZC/mbEsBwO1CdHYDW379jJIcRzNsMn2mC1X8ZBOWoTo5Q2adT87oSUw5ZI +3UbX1g3vQ/EmO4dFV8PdrZ24hJKBlMLHJ8OqSKHz1RPZMqXzZ8ZWOwVqMuQCc2fx +pUzDF3/UPhw1/EHiMPuQV9Y4c3o0q2icPD0uus/tSwKPfsppDDeJbTboX/WhTJ71 +mw3N8ryaN85puE/Z/kAs1hCpPiocn708MisQB+2r69bLGnIyVgwOvFpaKpEOh4jz +F14OZ4ucWLqMFEn10YehXPOKnwjRXglrXDBx5KAabNwsQRZd7qoblmzcQWOlSvSQ +Z+jGOb8tt3gIc8f2VqtFbMrHCjnbclMJnXGKdZn0aFtTNXIDBQV3rYBvsIFH/ByH +sGeQlU87pYwqO3DvgvYrftD9ElmVxl9fxHOHvNVImiPqUPJW0EfTKdoiST12PM9H +CQs274WC2C+e79j4bCpysmpknvc5Qono4MWVMlEx2/KFGhPGLcMBF88ZagG99pne +cMj0R+qZ04p7g6uXCgMaTpAKQU3KAv8jt45f1dh61HX4VxLEAduaNDL6YJKD58Cm +8XakGOVcKIfEIP72zzCHVphqjp0YYqUtqGJEeHjLIPouL5d3pEcqRv+1870IjcA4 +TNY9g6GQ3TxLzQ3MboYsPeqIOlT2MoaXeC4rxeIQ6725h22s8j5aASQhtUVAWjFe +beFXDGQGxyKytu2szIlv8ps5BnJh5KZei4YvvQOZJ2jiBOjLffeAQMVVNBRxi8Ej +27v2b61Qs1QCh6nmExlw/IRpUdzvCvf8Qx2ZiE+Yx7G0wQxaU3+ELylEdbw1itcu +btJkLkVWuw5JMepilg0dKff7HEfsCxTamK8DYy2xnpp/Q7IEbgoQSX0qNnlIFQoy +M1Tr2tfPUOH2RisSW+Rti/mNsLNGNWhfCdQMTsiezLqNmzoAxcWea/QyEScQWleK +GIyr3cNatncXkGBJN09Bzst8KTOtP2h57MtILBT5s7Y+asGwi/spEdtUZZZsNwx5 +a/VwpWJiwz3poi2I0VJKyydC4LyhGImVF/VZ0j9dnJmtzMrAIZ/NFhihlh2Rc2GJ +iqYRvHNORUpQb+VUQuirxIdnNqT+4eerBZcx7EUSO9gc7YR6rpMuqcE4xZ45m6sx +du2pASZC3tKdscE+Tt1rE8vPquw1jDmqmO5w5fzkqSXo/rke1FuncQcoJgPAvvTA +vai+SMChZsGQqOO+r6e2B/zrqJeuKI4gidkjAFR3HOF5xZqI0ehWyp7oSlefgdu4 +TQkbaY5Xe9McbHPw3eXzybnsc1bXWANFh0YJCIGu2iwBbs3jeZvGycpViR7jmiMs +UeFRUNYnlXfNKpYht+0mQPQ68m/oGvrX9U/fPyfDkSTspyQozOpMHpPakWTaginD +O5fLt7mwbzL3Ij2F6YwDXNFI8LD6j+1bqAaxxyUSDxb152LFBwhQqbtfMPxvh52y +Yo5wHamtDKCOWVHby0TR7qNM4XL//QjhBz7P9HJfC6Urs0DzoIIvuPuKiMNlf/HA +8GMdB71PzKXVMYiuZC2sr48Aqr+Bnmcb8UQ7x+FVbmJcVukKh/Xcl9eCMtcpQOfw +9OZAGGkpkeKG3cfHbYF+etjPPQTkypMa32wihAXcwiDe8AAFMTvIcW489fnowHv2 +u3X00iBPjel6YZ9/lCUUT2EtUFpuU7vkC364VUkJfJP4adl2Y8z9MJ/fR28Tdbi0 +Y+AKdgAI98NhyPWTFTzhWKar2EVNnsJdmhbVCxE7jY5vFATT1ITqor4zTvdGN4NZ +QOaGoBFkF1SMW3ev+H1G2PVmlIOs9NpjXmy3/geXLBNT5GZQURxPB4du5OA8nh2T +hGjlAzMu2UKciMu5PeY+XjBcvKB46bt1hRybiqTVptHfwzjrLZy4IBzLLQ/LIpbs +CvifsCPZ5tMzMRm1cxAB2qEZmRA9fc1nEGVsiTlHkUzPjyzvzAFnd1UuzLErUwo5 +h3vbm0V/H1pvmOwrz8CfwhbYzLREgAfTRPcKVAwhkS5Vgqp8grENwng50EuS81RV +CK1iOg+Re0Lbr/QIvWsge+vz+WWHC6o2v5JQPHXZ0TiC4CLEHVvLa6/lVdZJNyJX +h2hdaSv/DWnP0lLIXGGpegcOpHC4GJSyu8x1HY3stSmoeHfuP7Q6FzauUwZHNVsB +dyE1eCuA1Lq/TrzfVyzfeeFewMOhr5rFcs3ja8HIDToL26WxnD3Faompy0ltdb0/ +nLnZQpcr96PtmLDrZHIYCQF/8odkr8mylns1URk5JJ69eK/VzC2RKrAJIjVVryU0 +mwjnKPAVm3JzNAheqj+R49JTsIQR1RFIGN8ADddDn1N7F8pCiHEazXwYrtgkiTnS +3U0VD3GFUpDeKuRyVlS+eiP6teIfRjy4/eD/8Lc6kkiFbsnmTqrFCj5jAfJLqx8a +pN4GBozu8q32XsQ915SyJfcnZUVkqCcxWtPUSW36kYNpCMBFMxhRdOf7LLx6wBkQ +9+d8Sl3bDPXuWs/AGmCzuKXSVSh33irCZqP/sOiaem59Ii+2T9wJX0DlVFXZy4Qk +GczSltXtyZQ3hr496ZQXyQDxSluQCYA+CnvDeAOu/m08ky7XLkppO5Xb7mvL6KrL +0C+gaS71FsjCZvwgEgZHSGYBQ5Y9LxRHHQ6YgSA9Po8ydiDffnBHef9UEH+GeJxg +0LcnebxFURMkdgqTYsHkx+Dtfj2L3T24AooCp2ZXM7yjm8MeVlK+xlBgYmY5/Q4F +fZzxKmePkofG0S2GgRg5iCnbzlut4yhNXE0G9yUQJKD1+ijxjpZWf+PvYMk0tlfN +7vAjG7XIN41Rv2K8pEuGbtij6B6oM+RsCSvOHq6wDFmZmoGUtA8ZNkFUa+x7IbmU +pFzdawJGtIYPva1atTcE/riUJbfHA10gbVbAhrGWLizvpfyM3aEiz8MZobK77/Ta +56yyqwPo8O2z9yE4xFGTYu6G5cqHWA60W7RBzOrMcXC21n3COZVP7mUir2WjinMl ++U2YYolKnrAufBnWY8YHNG0VFM6BzaIM9GZ7wyXrkPiR3/6jbmyvjLkB1vsR1Cfd +fZeeFMzIuiy9/e673UtWHqHLJlF9dtiDa+i4ALbWD2FNkDYxn5p9KS3H/lfUKrJi +oDm4C1kk8CkHuWC6C8xJKLWWqjkzJgGRF0y+DwC890NsPQRYDTO1DqoE4HsGUcXK +JDHr18v0ySs80lmIm65YW2pJrW8mX8rotyuWWWRbfCff2LqJInC8LoED2mhpABnv +w33+DuGeZ/eZOJFwcKxFlvVysGEyJ+hS786AekvqOChQwiT+KTqj63TFejTQjcoK +eivYy0o289bWYU3APUNacZpaw+V9zSFqJbqjPkRQarNbK8UP9uvjOSASAG1kPMln +DqafGkDwRNKdDsRgH+Urz4xBm/deIj7uyZx0FQ6KoKNDhjJ6mUlrnxym1AAZKPcQ +UfpEaiaGEPmMLNA9VfcZypQABp6RbRNEn+ahvMxk6kcmc0CojE+7GsWVZ3PFipCU +FROXlQpob9PKv9sz+59/QkrSMCgDnZP5sAQV+fmQkgZf/QyXTkNUNc8rKZJFRMi4 +PXYagmu48T0+Ti1p4LK7rELcP8xwuy3/UvdKYtMK1hR5K9Sd3bl5IKsrqI7SYOFA +oxBufMro15A0JsFGfcTe7Ep7h/HuG7/VdGNkuB9bvAvyqNuvSo3QlEzLe9MxkmPg +R+ZPVnxHi3N962O/Sa+vk9M1dTXUZBHI0IFhe4jyv/NzS3/evD5lLKScVF7MYc3R +ewekyeQatOFK7T09B6PD78ZUMAXK829UmYPIW8qaatQbxN/lSZlNn7u41DzU2CbD +pyyO+RQvZRWNTO2NQOpcOYnMyT+gCHnStxg8rboY/MqT3XM7eh46Wb24ipeL+Zxu +ffujx//n58BJjK/YoiUI3fQZofuEJVIIKbVLdZmR19UoWZJSL5Rnn6HdCpQgCfTo +O9aDGLTt8sKD41Mi6YqMVu3+T65V75wOp+enWySpDVSqzk6SS+sEWGC0DJj61pvS +obqsToP+I243hVuXcPjZekHIKwW63S2GlAYt6n4K5lySVM3V9J3LPIpLwo7TF/Ij +Imm+Uwfx+Au8cICPay7ryhJX7b0n8X2nNeTPHNK1HT6esy8PebwviypAuxCgBNdB +swg0OgXDq/xfuB/jlW+KYBt87ZXooNaaCrjK0HGxXqiCzmAK51dzKL3ehrQJzDDC +Ky3b42zHIxyzpeCBA+10nN00dqLVJOkA0ElvxRNRw4vmRD85eyOV2az6nmMxJBlu +mAFOOcPqROyonBBmK4HNbuhNP5rUhOweeDA+E8vk6A/cswqyy25Iis/B1agM0BEz +u7GnE3mz242L6aLkBwZkgrReDyebrdsofQAHDpKeBTIDmkRR5JZUUZptD031zFsv +f5aVrkX4NAtN+6OHYf9i0K65l1IFlObnG2zzwj5VxYdREf0KmZ0hbavdcVn4Oxhd +C8gOR5k9fLk/iE9nAqLdIrwzZdpLPfreeENg0J82hG/4SRtpG1zBOGhK9XgyQY6C +LeskK8ZdSWKriWO+FSICM5bGSNoFSis2nDHQfgR4MFY17MQlhC50zKdML+YG6XYN +P5UMvUGE5+0qfl6jJPQxjh38NBc4YG6YHnucO+QjOyzciq9GPFaxmzhHfng2d4rq +LthmltDr4hqJmqvwrHyxQETJbKMqOKMQbpvHvDjXBDeNRL+wVGEVrAcY80MlTH1u +zQJ8mGUTwkgQ328lCdbIKEpzaeVMrj4UNpZdERFsxUJtEcurKKxEPI0W++hNKfO6 +3g5PNZ5dJaPfrc610rSzTaBOUooaQKUQIj2NVgy6bwZ+KzY3a7VGnb6MAQmNSco5 +mg11RNCWIn2fVgT2fnKRVFM2NfMaS+p9+h5NPEsbmxx7KwWqA0oqrNEp04f/HqN0 +fa6vSNqpNihQhcH+VJEev1QJjtTT6NBrdl/f4ZcKoKzZu+NSm/9koPl6eh//UvvF +tsQUU+qWPdtVQWJQF+mWC+12eyS6cOIh8M9pfjbMNA/lyhCLSrNsnOdHMQhR51A6 +fTLY4PADyA7szeVZsyTxuR2umh646N9c6aJyiJeCEKuK8gOCV1AGCZ55IWQgXERv +cG3UXvw5vqNIv3YH0rIPmHw/6OeRW8KXIUl50/tQ8qJvb1prsQlBIWdPMRok61MB +pbvZo6LOpmeKWDUtySFU/mJzI5NICuvPQOd3JMvVCuBxVsKpgRdBdFYNJPUZJ6hJ +caSSgs0vdIhwQOV7fC3be3Lm+7ElhErS+69OVCReJSlKRc/R0nf0RSnxfv6lD+ks ++ZoI3J0IwbIIsjstJ+NGPj8lr3aS//GOLU6J103xs42VMZ+dig4xDjReXJvMtes3 +OZaPlIi+xEn9aO7sbjUvearQSKULtoik7Hbdy1QsHk5jd6oAzhBiQE4VrbKy/L7H +Bg450Agt3i18wKYiIR/dApi3/Tn/PU50G7Ij8IBog1vW8d4m4SZTkCNHT+gBNhJy +Ez1RT4GLP7Dck3F7cZS66QkqtY1nI/6jFgHdkaWxHg+F9ewmKhmRPcW47HKBoC2t +lSq80tfBm2rP2PvUJyw5Sh3BxtiOYPZmxl1hwcI8H3yaIP3IO4CjtYQGg0KVoSya +zbi5jUUzhjCFXMHfeF0p+yUntsf2fVIM6XSykb7OdvMGMOb+0bvv9hFWjn6UD4Ro +KWc7vXwh83ZD+FybrlumJd4r3lHMwuc3BIAZ+P5qQqjGnbyJPefZJgzbiTfpuvop +sEGlfgQFU1PKmPh6/e3uToesfBaEo7TBp+zoEaC8QAY1s39esB7aKfbe44ysdV34 +MroIOlodcGHgz4VRHV0BnBp9Rb+sa9iXRnHL0tFgZpFsky0uBIKao4Sx50x3V3nu +N0AmcdTbyEx9t2cg/TUwu9dNX2hYfX5ZbrSvd6ZV9grMiIksvmlV42EjBSASgMU/ +E6O1cJKQjGjWzu8lGYc7SeKuszetr9IFWt4ZY0z4zzX1qw2lM7aV/Lg0UrLg3ooG +neIjUOUO+qLNA8B5k/d7YKVKYthM5OZLzje9tNud9HIMMsI/LKVd/NFiaE2Wq5fH +CgDDxjm5Oq+Yzs2vaov2wGHFPN5bvhKJkW0/1Pf+4HxgBmLvrNcF4/745C4E3fTQ +7BfgRWW2nskofgHrs2IjAnI1woh2JsrTHrNeSLkT2n5PpxxH8CRjngtESwuYzm/E +r0tSU6Qv105J2YO3F1FSpFMCZFecoU4pe54oGw5HC4AEOk6gvKy4QNBrtmiIx/Or +jJFDqXZ4CA/CZc9iekajccH0WmoenaOja+19Sb3y6JP63N/ior+F6yb/YHtjF2Mh +cVkcaeFwE3ro8hotEbpZeDlFSjk942EQ8TZyO27VLaHTjs93+mcWmvzzoP5Tuvkn ++E66nQ3z5RvdAPexC9tJ46SXXHNn0h4p8Ff2rpGe3PYJk5uToH280bqoaD7YMset +iOhcJ+mUZQ5G3NMaDqDndUIQUREYfLP0BdC1jp+9OgNuPyExnaWiIj8xH7744+yA +GrSFEBkHueSXFUfBsQFa4FrR68nKXqPN/D8jOwDHPjQq8G9ZMyREqbuPF80HFcsn +65/3JZoJbTUWa4BahXkC2VIS3sbwXRkWapsn0wssAabb0DoRzpAZcuxO7q3m0NSG +ay8mqcynY+uS6TuSsEqIfQAtMgPUaayWe2vCZpyW0y7RaNGWSthsT+CzOx6Src5H ++PaoVftVEpM8UHfkHegJ+luUdT9jYph/BNld9XPSSmSNF6FFD6O5velOfySxQrRe +XV5HGUNqWwdi3HeS7AQU+Wtz2Dpoj50EiZbTk4VdsKxaB4wTeQUhhM2SWKEg97R5 +cFLBQ/uKT+Gn21yss6HoBD4BhakqbFBxFlwCC2cEsvzYeO1Eq1lHugI9RzTU6iF3 +2JIZvvebu3N/AfzDyk3ob1TO+CYgNknzgonXN1FAf+vXspLscFVnUY6AlTUi2zf3 +Ok2e6DLX/JEa3eb+YV/YzSCVCsOKjQh7q0wVtn3HFeZHCS52Fctn2CgHF6RZi0wr ++FgadPPX3Vg5MUPmQt9u/5d76jpcj5HYCyEBv8DTFMRV76v2M1ucLrEXMRaSHtjX +26FCC6I8GSYNnxrfwCQpXVcXfO0gG7y7Jk9eT8I4kNzyPAifyyvWJTAP1VfkVXGw +5dPtXyPKVuGKfa+Ie4kSgso4wyFuqY4DcSK/9eETXhdCJ0JcJiAa3SC6mNSQJbSW +EdMjVjOjxDOmI2tMzNVrCarF700Sd7EelcK6Q9Fq0g3/6lYWeq+XLav5Yj2aAuEB +Yftoo8DW41HDqmpgZj/tUg== +`pragma protect end_protected + +//pragma protect end + + +`resetall +`timescale 1ns/1ps +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +IbSG7Grboq2nZ104ab+a/+lBKvy3RnVPf91eIPRpwQOtsDLKLPZ1ylPWfu5llh+u +0HiEpTDTBNXfL5Z/Bw0JVPbF658H8g4lvM2q35TW/+HM4h3PPwAG+H8j7XJ46HjA +QUI5/vpzx1W069wbVAKK9JZGH/SBrS0FKlV7pupYYQoUWwKULicdTyUn2enKQF1T +B/+KU8whV5QuENrwXYZ4JGl/WkO/WhC8xWW3G6NwnoxUenpB3Gzg/KsaekaN2GhI +FD3esESRqJsvtSUJRBOwm+QdjdhIm+pkvJq5eptgpqANXyyO6YVIJ54bKK4cCmbY +UuWQyYsM4xa1ficMoB6TIA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 7280 ) +`pragma protect data_block +naLN5qhzy4XXLyb6zLajhcevS11hu/SfzYR7GfnloyPaUYlRclKMhyZ9F1AZraFl +BuymX3VA5Tv7D02ejw4vpgo+LCyJxGhxIE/esj+Hl5mTk/5s+dHeGIYwCi7DH9N0 +e0H9wNHRryN0kKnj4LVtJPuI65dRfU6N2p6aIIoBGj+fJva041sfAcE0StR0ijbV +pmzOxPNeIuaylF5Hwbs28IHMNnmJUj/2EjzStsIxaozgzwvHkGv0ldUgqSBfVla8 +9fEOsq9yjC179N5onPmsDD62CmaSgUoGzKl14irUndtToyHC+6+NjkSP7jABqQgU ++dE6c5sKAJM5EpxOHZZOQXEhAciZ+8zqwIPzsotXAb0AxDcW1dc7S9QJLEpPi4jA +Mbg0f0w18K7IVTpG5/Yt7iIMxaKaPuw8ez65cf6CdhVP2IdSzFvS9/MOieSiM16x +yRFmQQkzUfdPoWwH+uRPjZgqy8N+Hr11bbla1nUTL2E3C0w2tIi9U6R8iAbE2A3F +94CckZZor6nzBvidleuD+F2Vai2V/4Uh3YX145Pp4+r1KhnnT4ZMFbXb+n8I8fRn +dg9rpH0wotOJ9eREBeDWZe/lGQ838d/njGilvK1azurlR3e3jZowtlU/q/2d8m7G +aCRUD/EVda8+w6LkvG5dkr5XT5i3n/3J4FKu3PjR4TuNkdYFGacaUdUvfoPxZK3+ +HY85O2imphxYTpRA4CF6ZhyR6NbFqav/8W22kIlxRGF1anClIgfMBw4wz4TUz3WN +1awPPgmYRVu8+CgRUxnBAYQnwmYnGn4bc+oIDukt+0fuO+dPLb5NvEILB3l8xi6k +7er4AQRx9JNGIUG/rnCdiy2anaJHuVnqCT5RMp7yLnQ9wL4X1N8nwGH9Lmr5y5W3 +4xmgBieqOCr5QqpVpB32IELxPms5LdQnzfMYy9xOshbCzGUOXJnOtdcV2St8JvTM +oXQgClYReYYDS32cbn6umLVlsK1jMqJtObLsXbKaqejsXJjopFirb2sMrd8my9hf +cfiTKUxWCO/fDJ5I1hMt+aWtnEe4Vyg5AqHc22nNClXGi4TcqzBkpVDoGpsYpFw/ +uRowYonwzb/bk2hfprJeujLzq2RY58AW2Wf8oBJhccybdV5kM7XMY9ci5ssldMSx +VT1UIoUlZ7pqDPFxyX8QubuPMSOZFeKPW19U5jJBP9AGpdCK8pCo71jpc0EJ4/uv +S2RlRm9jtarabKm1/jOx7ArDfJkCot/0Uc4JUx7qmhdpDtuCUANuiyn5sdM448aT +dBdotDopJjVVY+0q+0bBsvlFuAwDBSZJLjFILGfrjvVA0uU2v+7ffVvmPCbgt963 +Q7jwxcMQSb5+68YTyRyg9bfvfWeirDNJawCCuWlO6ZCDT2cW/vWKtg1W0wHXcnC/ +c8WY60Kfu8ryx1x8KmbD38LEsbMBIZW8mdVkgQWQ1ffK+O9mHOawHim3ut5UdoE3 +4laCqnJrfpfXlF4dBmPc5yI2t17cxbQoTpRMH28FbmCLE1Kcfo52qV2BZfRvliyF +2Rr7gyNU6lrkcJh4Mj6//LsD0AjnGCbZcY+xMFjXxDjJrNGqY5fPZmkejFYYe1vP +Rh/8htFO7ssBwlHyFET/FS2SVfgq7aKxEKgdf3TvX/wgWRINVJ4CATYnkN5RH87K +eOTl9ihXwo5tnpp8Oy1fAZNhqMVtp4Xtu2oKO7T+p9pYk+N8ILEx5tTMSgl4sxHI +g6z3kKOWyq/XXiR3wnC89aqprXPBwXrhkXFN5iw48cwIKwmRxwTrIEwpjqr9jnRF +XL/S7Q6WkKJDyKq4v8ktEEhayBC1tjPOVDK895nbxCG9uPyUAK9Pd1ow+WumiZWN +YLP/QOD44oKaMptxTjxDKeVQwEjNJmGKlwJnxLXI6jQ60aFbQHkO2qHKpaF/xS2w +toL1XhZMM15rgIuIaUOYaWQEC2QhvGW4ZqI1CUHgzgPxE0C8ZR07TqQX+RdmvAfk +hJpwnY4caaftjpM1ygjjtX3T1s16T4nRMTO00wBWYeqycgG1THtZXsMubpbsH00t +bQ1c32C1BRERRMQvWu079zuExFutWr6/uGpnxLXIg4Nq/ec2s7p+0ewFlE+oLGrT +iGt2m2LL8HTsHu/HL33Mwqumzyc++PredpJTE3lHlCIyBKLK8fwHxFaSLtiqFxnK +lWyRoROOAgrGHi9Au4vMikyUElrlyC4XEiIyAma7P1txsVkeMtUQ2TmiF1C3l+co +Os4MzsMP0/LePW2BY+CsuhXuPCi7y+6BTantFLo9md0hkmeNhHfJlcIzkohRokNR +ITg7VufkiEMFvqIqyjA8QN5tirGi8KLn0Ox7AYfcaYOlNrxfAqZG/bw6jm4m+G28 +DZ+5SpCwO6WD48XhR9MPdmAI1k09prcfcJs5Vf84a6wbneM2yj51Bp5rxqYogwV+ +iV4fkoO3ok01odzxijwIcCSjuFHqijps4kVIJ6X/w6ipi5Q7yDrF40rH641K+VL0 +TK86dboQw0ZcgKnc7zsmDzrvDD+dcX3dp3L/AFulpz/TFZ69pXpoHEwx+TFXkErF +wdAjDiQ5Jpa7Mw2kodQggx3FPgx77Sq0zQxvi3N6yO8FR7RiyiJFdjmBDXUwy9Wp +Gb0EVMaN40PLCeY2CAc4LhipCBEcfRh4gK0fh8Sw5sE7xWNUr9ghiu1FzJlKckek +7BUmPbtKJlzpwW5y9mr/kTGbgWTzZtwvhsMxbACbklEH8BJrjqFdaNqCNyiL/dzx +7ZiBSU5dJn40eMHT6lPssTtawVNIlehWZMiVkRdD6fM0O/DHtH4/LXHup8k7mi8D +VG3n1S30H+WZmJTx6NLJIIArcu1uM4wc+UR8INNSd9riAM2mtWSm2T+OGm6UfuWN +BHQQpnzflhPm4QJ6x3NYP32+fCVZ4vO8Iqe9to//f8+O+b49R0iMVNf+9C4vx4cX +oDUJhllunytkbdhevwGBlsCe5gQsj7EZd12mt3jq1Wff4+qvnPZBSFvofBzYk4lQ +qXSDgN/ilJV0yjzEEahEUGZLr/ZMXvpdHkVaH8WrdEilaS5ZstDVjpMnzPMWUxeR +jY5feomXJG2Y6wzsbGMXrOLRFsS8VqqdRRR8mpesUX0UILXwB9HwgtB0gAp9Jbza +1VMs3YuvSQ+aHXkCAWSS56FhkgPDsntJKC9ju40cKki8a53SfeSAe/x4TjGnqWGT +9OCMtyJctd203IG9pBc1KOYOr7/8x3OVAO9UUr8jnv3zIU5tuKkGOHMj7cLV3f6n +NLQsNhbmPOU3qgohq6Yont+2HmMc2Mh/1mc/SsEY781O7EYO5Lro+YpnnLHbYX0u +kFjg/zjhG99FLSdrCTMsH13HpoDEiYFx7YUae9e/I7wzG34OBBy+jliSDSxwu88q +rKDYrPb6TVMCDnlqyLFCQVcZygFWuWCupPi+/tSvQ8GoLNcZLUu4ButNb8Q/vZ31 +C/SAAlEHDBKz7e8NI14UYgWnZNyzo6qwRSbeg+Kb/+BQ/9DwTsj8VdIBcL9NsSfr +VmWFbreRaqT2vzrYDYuWbcniLX0xN/0zwEOM2WHHd5rUx32LjGmKtInkbq4mlagn +2uQ8/9tqZbSMp3egjYRM6dmLRvWkZyFT47MPP2KVsXalMyxXQxIADHJjiWE2T7l9 +9+LBzl+NkKRJzak8Ymz2EpAQ7gxkqC0NyFN/H5XBR2uxdu6vB7/uGrFVazIz3JGD +aG7xOCZOnFJmxVfC/i1KR5xKZa45Mq4l2oOZfQq61fy6ZCYhMLTRAV9IeHiPmmvA +k3ZY5/3QU8chqCDsmwzJsRgCqRC892aJ9BQ3SKdmgX2wnOxKfmQolNovEnS+TZuP +hp+PH2O3H+YEy23zbu9TPRGHAC916GXfhOBV00DrLhkDl3AbL9XIiiY6rvZWDdJ4 +aixrmwvPhCp0bvf65kVqQvhtqrhqRDkN/ONy2Gi4aOkuU6aXYEF+skuDYYGPS3hV +8UmBuTmQvuYXohzAEdtKvIblvrVFyTZ2go9G7WhzpZnMqhjlPvFJMLF88aDzBB+7 +DshEPz4hIBzg3e+Vie+nNrakNlS0GG8shRQAE5mB1ydpkd8p+hk+lsLa+ej+R+kQ +jsCh2r1oEks6s/3Zs/tTs1SXQmwEDFRJrYVAD62YdiB4CpqKa1ESJO4VKX8sVVUG +y3VZFYi66btcQY//qZHn8MQX+/89cIvwtax9KGdZSTBdx1u+8986VBj5KcH4rEsM +05geOZPvY41+YNFBKyeJ+Dm9zhu8fS4QBW3PAeYuiGG0fovDGsn2ESVLZxdu2zS7 +zm/nsfKZd3/wx8UCqmRkLpTfVyedo+yGP9C0K00njrILBTtv2cmNjsCTFnlEeHO/ +A+2vK17KjiXhdcFCfCUZ0AW5gAVrIRvpA71oV3Lo7rwJ+SX9s90nM7cPTNEo/N+B +yiug8KW5KkbIVZMYBpV3hkitR2zfN0qH1w3AGLLr+nKoThcGj43ORTNZG0ZM7+pC +jDnBgfpCW0n7NuBUm0PUEGYRogNs1Fsuvk80WJQRGbMMXQ6C0z98CUa81wd8A6ET +kzYoQj6z+VxTG1LhOx5J/tNqh8EFhlD4wjQDFgutWK2qzrSoOOayXIHxFe7HrjkN +vGFW8UQ8vocWm2RcXJZHNQhOiYA2yTucQE7y3dzdwFE/rdMQcv4BEhnp8zMM4VVB +Q8xjzCSfwaB4entw9o5rQZAujrMTudgCd3YGmU4emoyPoC6xZYla5ZBoJ83mO0N+ +y1DWT+Uwi4MLsxTHXApEwkrPJFk9TpAxBngJsWTQOzq80tyNIiopkCDHGv9T1Cmm +/bO7FiCWVlSxESm+y9yJHaw5knZcjl4PpwXIu4JNYsz0sUJ+F3QKGLhe8GsyuXPL +RDAtDNJYKCR0jNULQMrAJ8SoWVTtHmukrTX/W6/03CIlBIMbjar8ipFOTu77C6YS +YXs2Cs7lwNnKlrTFheHsG2MXoY3gyDOifM6sOv3CAj1G+fyWnA1ODCA7JINOcAwT +L9dRQq1Dv6oFl9BA03YCILPi4XzCvvQ02+0EEde3othfFx0HPPglL2D5FPhu5OuE +yWwBc2VVXfLHP0QN16femvb2L0GeArx4xZNXtGZV3zZMIgHwL9wv/gC+50Oa08VI +mzCLFNA0pdzlVluLeSSDgWqY4ma44SXDwB2Mwq0ndrLpp9a9p1XlLfdCc0+m0ObQ +5SQGZ9QeO4pI4yyD7hhczTHqXRUgSi2clyl7RysbGMzUucOUGCdkw2Nr5R/NutZ8 +Auh6JsCBD/AJnPu9t0gkp+6qa2QCsrU6o11Moh8ajaxJxZGtgh9vlHV3WhBJmRuK +C2C6eZXPl3m5taoAyvyemDURDl47bsh/dasGFepinwq18xvML7yqCIEJUSfV7HFk +FXXpL1C69xvlZ/oLMzCUeLVXTnIOND5BTjvtYovfad7K6tmF3N/5acp3XK8OSSIG +Q7g/k01wQ4hlXEPQyd0lmp6+/en0WMlI+KPQ3Wcvd4YqeUOsH2jbgSC6EacvJ7bv +uPRa538cg+9jTaAnqBxg1sqllXLlP3SzwImLvuPZ6R9k+rYtepSwNxssFVUimPwO +dfqHAm/s5yQlQhxF8JKYRnbLFsDjQY1px4owLenlPMjYeTC1DzLICSkFOEcGdUwX +K8A/IN1grPUbnJHpV8vyFGSEYK+VJnTrFlYLRmnXbMY07scpjoCLe91dVC94Q1a+ +k5MXNCD5qYlbRVaXd/iTR3rKjmsZYi9fyImfsXUkyFiV28Mla31YRF7lHr9AIemp +CQkPb0RWVe+HT1UaCjchZTtpjgLXHE+zA02RLDfhvHHYxPFrlD7Ec65NyOnzutZ6 +yFClITy+6IfmeeORz/AGM6pfsiS2BygJpA79lx0M3l5DjIHZEfuY15Pg6UQFYmcy +bO6jUDdANU40IDJh0YJH5kh9ZzZYHJr8WB5EZ9K9hB5wXDenWQYlvW8vAs/3+KcB +EJAD2q+M997wugL+L+W/cw1TXFQNZKvkJYhXNFNm9xVSEEbxZsZAByXOW1B39K4a +wbxkNFnhaVMl0rR+02jDF7ZvuPsGi/HLyavLD0oRt27mvnURL+xOCbEs4Zd5SXvp +/kE4Q/e614pB3MumOSSimJ9PtWhTT87VQ3nxsZuCf595bdiQ8kIssXHVFOXrKn7M +2lb5LPZpc4GpiSV3+SFqiS+IHkNsN2rac9f3AR5o/7rRDrKSocdz0dDm5l7no/vX +1i+ohYjut06E54vXhPQlsoEylTvCU8D7sArPOU3En3iO0suMTdzN9ZjjIrcnG3mO +kMDKLNFnkVtw85Wk/SpVzzvOauHl0Dbn6lA95pS/j9zdR2XPWkenLEznLPnhKpQO +wL/A8VIWkMrvzj09wzcpxiqmR/BMOn5AmB+UGAEZBd5qnEjeitLQDQbzQIPn98YM +SVYmcLFLweTxQsKnOM1ObfoeqV9xpqeWJ+H35pdh9GpIy6vDysqeifZIqDKz8bK3 +JVIO7tA4oCiBjZeeK56JBpDN1dT9I8qBf7QpXYly9FBbz/aDrzx82kgdtiuQSdXJ +s6fhUimgs4NBtZv52NmymUTuejOTyRXR3QmTsIBLMihI0Qtml67u8KOujd5MGxaX +AEQ+8IWvQP/HEIgaNVqGvzgRGy277eBTI1piX8zEpmP8KbcfUiwR6TRRVMNyXRGH +zU3eZ0samPhQMjCgaMb4flgX1YN02TnhSQA+THGGUL4lIcBklbNmLevdBRZ2J2An +f08ScFKxe/6u8gef2lcuHEoSEPRKYoRAnpCCdc1aYI/2aH0JKX4do3OGguEDNVyx +WnVugMP7uqG+rwRKKkF4BNxspjC1k7YOvxfgntg3R4X2Ri3J1L8ZoBlR1habHTtv +P/31hTchZztrHrhcUm7zUASRgMVgBng3Jtd7c2tYIc7KQYBR4Kf6o9WjiEqLyLrN +0y32VJmYF0bVlTC04khERRNq0VIlk9vMlOmeMMhn1WrLdDE9H1GXRDXvqIEMKZ/b +fMUCSlHw/5rdcj/Wzm4oiDTIGKlYbhRSv2biB+ziSNSQFuIfjgGMQaEXuDG4ytSp +nlCSROqhO8BMz9JEFAC7wK/XWPg10yP+f4OAh51T/t/ilBbxiknk8SDHB+pQ0Rkb +2tbYNAbV0tGb7m3FEgjYDLJ+2chFPBN++C97RciEPrQdolDaeTiYmCJnPuBsWFNG +1+JEV0FfHvoDLThQekQc9//cZR65+tjZHW7jlRhj8QBuIdRSBJn7gwZgn10wtjvS +rsN2dmajbhIvOr8+57Ue41iLP5gylmAIRhtSNsavXiKRgvY6/VQBPJrPA/Elm7RI +L9Ve425i4CsKWXY0zN/N5gPdP+tgp02Bi+bvpzJzE6L4ULOXtTsPMDbFStTeKN6/ +4BuOtpQvmasMkKJnxlu2BaqtwY+DyWQXwBzMyEnRXOH6FDy8QeJxJUpqeM9prSNA +BuAI4hskQ3FVPOdKSkQsR8oXj5wd95zGJg9uNZ7UlMvOk3ETTZxDe4Wrklvyioce +jRsQ2X7FkXuIE811AxrJO8g17XY9ut2J3XcmgGx6MfKOo2M1TbKMtw+rsYLAmyw8 +L9dchPSFZWMXaNQ5HCaF/Cib7FQNRlN5LYJBPpB5aacaOTXRnPCxpXbgloNnRvx5 +GhRGJnidgGz6j/9NEXUtVwxbs1z70Ws8yZRklauH18BkfSpH0zxzsk0e6AF8AHUq +AwjZP0IN7INFYHxB3+wjnmsYiIzsnxLwJk5EFbn0x63fJlJR3QsmOr7MwlvVw62+ +PakhGAa6UEOJB6Vn/DrKUpjbcy8gENGF6Lphk/KdM7vPMq9M3aiwyxCZkPiiRVVD +dhQG2BL+O+cf+YwNbYAOucjg5mrv85xosabr1YGizfR+1Dom3145p08UMfNMISms +QYgW451lGwAmCp/ptuh9mNQfLnzdW4VaylD2Lw78uPDHJ940z8X7+cB7T1yZIWEv +T4asMzupr2E0onu3V45UAFgRn8Y0imrRtYWivEVJuP2l2E/iUDIda316gQZtvFUc +hWJDd0fUBGuP6i4P/zj2H1kAicfEHggPUXoIqWayvAR1ce2MqbXiXSw+VNPHVDEk +ICf38xQLoX1HtpP3MSi8O6NGbsid6SHMxvFhRA/9Mrc7UvrChV8YqXqpOh1OYwQS +9SiHPSHW8HIPycU7Li+PcbO+HBUT66sD6ltCqhABPGvbx6/oBa2CN3YJrqMGxqkA +cUP6bvLK6fAZaSJbE9fxDTjfWbwjg2igQfRl+wkNmL6+WYCJt9KF9Q/isAZcTu/9 +kAMgNqLKVQDOxrZFJmR3cq1h0KCf6rJhewzMy/plJpuF4vp5vkD9f6q7lIdQ8Dzz +c/MvFZUj8cP1EBylfgR/97CHoM/NlVxevqqg1Yl+baQuewXjv44/eZUqpELEQwIl +j31BBrurg9cszfLYyMQT/y6Inrvc2bb7uirGCBF/5F/w32BYbIrkxqOmCJegiZg3 +6v1NlPRhI8xl7xS9ww2wPyAxZCo1egXaF9Wc2/hu4VtRekd6gfeXg9daeEwyXGVJ +/IanHZ1piGfaFSNrlyBDqz0KejB15cv68+/lYpoA8WjLbUTZLUlyWdZmgsMeVSLZ +PVMijZ83AFATFqTwWFJ3kXccC9TBwbpvxMOj/3wVvGiicXf9JUbZSpsiziSLlw8x +gkwU/yEeYYRXzKxRkgJRGFGpvNp+K6NSIdtNIkbtCh2WWfOZmGTHWtJPafdAJ63l +idCzh7Cs/Ia1F0Zfso1pCV9eXWzbv461WF/guS/PpAEKdZsGGPqBHbVn22vMOOlO +CekHm9Ynk6ZijLlCKqZl5DF9WVcmo3pOgqb6vmII08tqKWAgilF/7GCau0xYzUQO +90rXqbiYFm57pebSvY/taA00LPhVKG/TH7l3n+9OXmb1wfAsIdlA9RBDRiAA9MhG +pFmDBeSg68kQITM/wq9ljX4BxhkEuLLr1OUMTXdE69+5DgTON89WA8eZdh+Km2zm +lUy8AoJhm8bYcZytZaSRn3fjlGqx9zgRyjrh2lBgW/4q0/RaGz6AcH4g4/lF+Tm8 +ybMq1Nww2vaUl4fYC/QncZq5OiXem+GmXfFL6NTZWinBMvHC3umZCO7XJHDHUbb8 +Q4vBrga2xKnfv3fIQ/n4tKv1ns0rl4KUw3oS67HQhIHgTcOgBjecDiQ8y91svu/+ +dzvqvF6PMOD9c+YcONSA1moJ1PEtT4qGK8+oVfU/tU1U53b7m8vn9PDr/N/nC+kE +o75kx2YNABiIngmou+yFw0ZRDcijDwzpD75lYw+yy5dKi+rmXdiqGY5VgLgzZ3tF +KjRloh4BS4wIq0dNhblYSSuKj9S7kGeoQlstd1tbvLoS6S4CzrbdRwL0LlRicQau +6GywrhpkJpPMVypS7xEVPGvPK1bGfp+y1i9lJ77YmzWbAzrl0a84DCGgAjAF0ZtT +jObPhfdXNOEvo8YYwaCRscnU1xHaZWUuX/F96ej6bR0sGdM4sGyySYOH0gMJQAQ5 ++ft06ZZ/rRFAovTbZa8tV/LrZNspwjkjILRD2rw9jkKKP1BuDFLusATMDXAzeySk +05gSIfnpHz566yR7/yurZljJ1Owfm1FHHGZCLD6ecwoaKcvpSlXTiTnUvSDmel+i +iaJNNOIqcOAoP4PZ9DB1HgWqvc77FR2qlM35zH5IoSWg1VVN9f5ZS+wPwo8zRXru +H+ywdu++A8khD6Z6ukzkrKiDAbwjGxzwOqPayzImo/g= +`pragma protect end_protected + +//pragma protect end + + +`resetall +`timescale 1ns/1ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +Xm1S9sj1JuCixXxxRRYRKD14QoS3afZKjplPN6ZSLQnAvIon2j7qx5mq8XGsgaSS +IEzaBn837INyfSUXRKCDbOHB6vgrTaXMb6v0UzxxzPWS+b1IVkFQr8FAS35BRCmT +NbIAI/Yorvx0WO3MSnUTRRpDBG8iOn/eVIjECdf9yJE/4mpgec+WdTcvzPWMSgUN +AC41MmhJ+dYzesMt9m+NxO6FhP6/22rXjdUpKCdKZCyCQFtmRGfykI7AbREfU4zh +oGDWnkWlKck0HShR7nAecXqLfG7+Gq5YF7MGzZ2f7KqpVXIzMVxQ015P2LWLKD0Q +W1FNsNnFrHW1pzexa7KCDQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 688 ) +`pragma protect data_block +d9NgTXPSU17ADKmxgIGRfmNOqDVkC3xL8aQNJSfELvwqHjM12d0BwF921Y4NSrAB +2hny08w3bwVwZmMrG4mWIOg4TJhZFU8abxx16JZIuWDoFZArp2nzhXyunUk20E18 +DjbINy2UJjOconqd57OAgrFbkfE1sjygBNKBfNiWruHnc9ACTZgjNP4kMMKYnP4Q ++C7F9/Xpq93riPzugPgorK6JMDDO0j484pDigDe2pslBOviHjuiG1PusCsYQjS4k +8xyUzI+IMaFD1o2IH2CaHTBym+SFlLR4MF6uh+o2fsJ8sDM4MRnxJqfeQlsbmGsM +JEiYRkbaUze/Ftjp4hhnVIQwlkRQnqhKk2wI3RrFo3wNUKHuEZ9Jt+zFEI8VBUxU +xG5JozZ1GvO3bl3emvy0eqcjgNDycd+VzaGXIFIfkPyFI6t7a+VoPPWd5L5OY+E8 +CxORS71knWP3SH21cw/7DBok2mmAPRx6gM4RSmpLWGBILWNMdDEig5Cap21OX7kW +rNGUsqAyTBZZcRbvvubH7ON7IFuJqyGi7KCvM8q0j7GoWeJ66fcn0otjGNjPz3VJ +m2oVkFMjqkHqzDURgMpzkkAY7P9tpeLJEnt/ETbNwEp/epgl5QwjjNrig/HP37yK +t/hyIpWkFjWEjE2Es8U5/qbIaeYOGB3dHbMO+5cV6r8NfqB2hY3HivwDXVpI7pyl +vswOsuKJk9+V0f0jzzr2T2IFXBzer5qGpQhtGTugdfzMu+VsQMEDZWYh9+Ui0PSk +fQ25ZrSBkxXSck2Esed9zLN7WZvAEIeH84e9uGqHV73TJaW8pm6B9uc6S1kz8h2f +JVb0WcSJCfMoycYsEStOZgOpE1mZjhqG24gnM8NYZ1TlgrGwh9Z4kqhhlooetldC +cHL/fnhdSq7YRzoZsgU1lg== +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +YCP7u1cObVZvbCw+OVJy7l9oTBWleoq9pu7Q1OQPRSS0YTyAEOS46qp9gwzKKhwN +0zR5GV65ytGjNdr4ypFsh/u1ryyP+Xi25y1v0IaneY13gDBicykWGwlQqUcNiJM5 +hpa+wkVEQE+opumFfZGNlYO6XWC6VPewxzGFLG0jgTqLSxKckpAMOhtJRe9QDDID +1Ogm7c98iqLCmdne915Er6r79LaO2eiQ4skhTnXdhNl4fSnifNNJAOHRzuLqb3Or +nv8PDAzc22u35tJPGB2x/4lyeoh4L4sOlbn1xCyk/GoTqJaaB+cKDb6CkcwK6BMD +W/DKlLnHCsJtQqRpnPB8OA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 6880 ) +`pragma protect data_block +tIJMLPz+Es2zE44XNEZaphc3xNIDE0DWrwDXZwanlE4+DEu0gwUKVHaIHCHiYaP/ ++iL7I0zAyRuQCAYC7iplK/3+YeKHiT4Rf8qdVORZqU8NFdayBFfx5par1YcSopM3 +bwf7Sl+ysL7y7Z12IStzoXWEGzwTE8jL43T4Oy4/u8lej7XbKcPuNubOiSKyctvA +2bWWOqRFB3kwb9WZzgQnEXqu/cYVnTtMg40x/46cEFJ42tIQ3hpv4APDzvHQLVzn +cER4PuwnsgjGp49n4m/qHNx9BSP/cod1d8P658Uwq7z8WRnxYqRmFu62VLtKSOjc +j+4XUh6EbulwKRRG5BKG4e6ke9CK83GQjZvygRfGW7aSBNccDfvAtWBU8Fdfmclq +NNgvvyUfsi8DPNX2Vk9qSwGzq8yJxXZWHs6Me71b+bH66amBd11yUslxiophwCRk +oM5WRdtZDJs6D6ochsv62c5qqJftPE9CrhzHOOKc4qFDOeg29Vup3LAdf/v31Qxi +8GO9U84yOmDDbniVOPBuVTntcb2ftAFJDfJQx/XPcVY9vqs2e98imCJsi1fL4eBd +KVwMT2ut6Uwle5BGNMsAvvUPMud7ujCNRKpjDJ9GN/cQKzP9/wWJkTMQ+K4qkGRw +VJ7K074M/b6spLgoopn4Yi1jh9bhn7lOr+/zKB0wsI3RtPlabUV3VNdnqggZ2mwa +Za3UOitMGGujkSFoJyTWA5GqHGK5TpRgk01hTOgLdxYgwWFci96Spj8CHok+1ZZb +nKbPIIRLM98EPTl+1QgrWGwBmLoPjq1NqIteySNzRcCd9wcmQ+0lTFM1la/lMwed +sbEueU28y6ClLbFDfqyLnlHr7LASyc11OAeXl8H9QV59b6wkUL32R6YegLwXUPCU +u1Cmv34bNPMhtoWePJ1BmJS62YxMeuy/OYNeVugzJiz0fU7D4GbAN8063xaoAlzV +YqihWNDLMAITg0SA+2Uc8yZVapOQ3EQqlBgiO1qRKmyQhCM2FqJ8R/J2SjNppicZ +fImEqq2DMC/TthwdWwtFhtR/zVFXIbibvusZP3U+UlXkBgAu0tOYl9N7IDylXJUL +4jsJrL9i8mTBrOOnaCM3ruEagjLBcyCAIhKgrJRJLxYLUVVI59kfZdOAHu9hANzz +XadvsYv2SgrJEWvb7pM6cYSoy61wvaI/dCa+m2MFaCef/Xuj+cD2GFsXKJCJV30j +ZMjm+EBMpgrzPkk0wzwV8eIT35yipmZPuMpVqMQJb4VLapzIhqXotEL7VbLwVbov +IdWy7gV8zblmMkzmb1cer7UgFu3c5Uelk/l+ynKmqFsdYeoBsNpJj/tXTJzyHn3e +PFMxvO4wX5UalH1uK++ygjja04oZt378+eEeRbikMwWm+EWvQQqCXGD1il0cj7X+ +d1sf0WR7sMIyMzL8ZMY/EfqNAUYDHgHTGohRaMg248Cz2gcb8KLSitxnga/VWu+2 +AtAEjB6C0sWfzPLaM2HwW4CAo3RAIOftC8ltT9pqjWsmrfvZhNEuTvbS92bgDyz4 +wCKX8HQdWemibAot+dQYI2WimGhq6WEYrfvQKPCZnYyLGWFTJUETgiN5+1K1H0JP ++gO9yWE7MnRDfXEm4pxTvLvVtu/AUSIgdOPkekHEElbMmBRpOQukIkduyraCUz+Q +wyRb0j1lkFckUK8egEdcJ5Ot6RPLx840zHkapofON8QHlB8oKJfQ1Ii5Fr3PN2BZ +I6yk2IsDQZpJgxm5gS/norXnz6CX8ABOe9gYhcSNMfOYXKEIsxkHxy+K1x5HkQAj +TyEagU56d2T4runPfI/Upgx3JztvPS0ui7/5yHikqgwnHHwcZiFhgELkTzDhSkJ4 +D51SlOQH+wdXreBpu5+uBqPMHlYxuXOiWIL9kagYYABDd39MDkx9OvoXmZ8d8ks2 +Ijs17qWnZ+MxpdurVAwQleVwXg5JHJi3tN2oCYgSB0EJ1jCujzHJ28GSjkvsTzzf +KytGWm4SH9RbhKZtmUtDOY2DGeuvtlH/ournvYWEfmnyNwbICGApeLRJ1VSaggY2 +NfuVA2trp/4+r0Zjfch7AsmmXArJy1bJK+GhKOky3Bu+KdWp3j+txXg0bG4haiWm +viedcLoQAY464HWysJHol292x+48kkiCN9zk6RvpHGhJFv9TbSIrIIlpiUiIt6KX +MOPKy/RmE8W88CpzolWB9ACo3G/rXfbQX5rkPdBvnV0vRxXLC5vYs+SDPqg5y7sm +4zCr/661kfV7F0lLZIA7rMSbdkjBNEWYoHKfOqIqBVJPmEBRbamge3i9fZuDi4y1 +aSmZrCWiCVzLM0mziv8TLtiIz0b07zkwWjiM1CTi9hJC4aXQJYbDYYa1yjW87+3a +9iX0oHuPCyEvlBw082EvB2eSvAUGPS0vCDwJivS/UgZdjt+GURMkKACDzue97pwW +tSho4itjdiYd+SOcCJPkgnPRtKaro9x10/ZEI7x7ALeiwdVT0SzprgND0cVxR7r1 +9AM99RPBMDtSW2b+hcC+qIz9Q1qWkj0CQYQe6JujGz3eVJh+TMwGC4cwHRjpDv/L +Eo44UsmeldvE6e0eQ0rpcdXV6NuhFKCPZXo3k72HLhwaqjbMBV7CnwixRtLduu1+ +2x2EVTsnC2uug26ad3J3UnrRptxJq82oDuoEoqHvlgiWA4kM7GISVOORTnOBUl/y +CRF3KEwkM3YiZto2S+bMhavRcf71iXCDV8k2epbQB1ySCITZjVTlw8cJOHTI2XLp +zoqKgaf/UcVOmlJDksVSPrYkljR8aWdrB8Zc7RcHnC1EHmAS5Htcy9reWKTBQma2 +V0WtbSPahWImh1Bv3gGy+S9tjzb8I96MYJmQVGIRMfniGNZnSK9Xl26WGToTzuw2 +3QghJbF5bQ5HwMScxOnYI84MfKW56i2dvPLcFfqhGSYbXVdw6NfTo2lN63W8OXI3 +RhY6h2LlZZqPCVKyuWxvLEeyyHXaadgtLf4F4BlgYJD3Xul83gEwBlqQNDl8wlNK +crUkavtDEy7UgijAQuQ99CTMywVN2dmKWXGvwR54mYSsGGWwxXW6TMpHD0LJ8/zc +biPWx25+B26M7T7nfhkSzJ6riQFWj2VlhWORPJ3gKHrck9pL42Sv36gcLrb3XC9U +Gg29nVbQy7fHdkpXEogpNBlExgrwdyD653G9k2Y3xrFSObjjsSs5ANWqadEWm/Gr +j/PZfhGtopF89H81j8vUTWufCEzV4nsWsoVaHTGcHSUWFUwxC102CUmO6qAbJXca +4I1xe3SRrE2uu60LG9pAm3lxfszi7ObXfy2icZYctgNOLrz8fFuM6Qf/6O3vdEhy +7dWPE5eMQ6Xhi+OpCIRWRWoc57zATvHXbjCo6f0Hs2z0HzBSGo/LEC0obKyEsIIp +T6AJ05dj8xcnobU01S9WcDfrLEGTDNYp3daGNOehStP6KbSIIoLIsiMN3/X7q2MA +rwXU5e/BDNF8NHPkCUkwlUQ4EPK4WyibqII8go9HweIPjmE8xVjDywQC4IjUqLU+ +4uReik5E2KLvYsQJlRBkJv2465Ig/tJHyYofozUBN+V07qYfnKESe3/9zEvNwRNJ +AfZgjxfmfGEPR8eUs+YaPWosfJbkRAwHLVynnG7rmEEnuG+U7T5idnw+PjZuSwV7 +V+fllE2v8cThv9gnpTefyNRqMpfCn4am1/Ou+IQ+oqFtaqVjGc1mmSblUqC4VeWF +GJ2pPDCvaX141N14ObQqJ/F+0BLfGF+hNu+QMKcr1W1EH6ZVtCf0WJq5D/UOLYSf +bg745CDHEZuxnzy9gCCpOs6jBZVsjwnM2yUbDgJUYRG7KBn/WT+SQLfoiayQ9SP3 +bZvxj236suRuJYs6H5Q6Dc3UULcMAfto/IQwJyaXh7tqg1vuUWq9t2uTHwguSqr5 +9sR++7zDphBWqfTgWV+qU6f6HmlmysZ03xO8G0o4R5kJR0Qj4BG/Ob39VMfRZRE7 +sx+0JWPaFJtifU3AAtm1sC9tT1fPLhZqEo6XNWcN+l4w4/Xas4IkDUy5RmaVbD8x +4Y9udtJTngVOHQv09IRGdow1Elisk4iK/nQuFFK1go4PrVW0oUAXog35RFdaYt84 +X/corK6G+toRd2lW5K8P0BpNbL0YvkhioByvCKlaBG5EapzWPZ5Sw9hFfMk1FcC4 +fZhvTWrypSCfj0BwQTOlnUSsxGwg5wsbo164JzWtuAIv19e6hUKBiQ5AVRcHTUWR +jgkz9iJlEHoD+dp1/42sNlEv/d6VeMUwag3iQgdp6jCpkW7LUtxPcrHCi1+QiFjr +UnMnq52q+ahJjsaqUMZwxGa1rVv97S/gJ7aAL2u7svJMrtMl4CAXTQhbFLK826K5 +RynQqWUNoVZsXz8E/DSvcmp+hdfenOSYRqZYhbhTQVNoZcXlOvb9TJ/QE3tZCJV1 +THrjsFTa8//12EvkNjWmd2nXAf9ODm3psLb5AI832KZfJjcNkmMRmd/r7fj/JZS3 +FtevbG8jNS1IRtpg1JPdwP+oxu3GaTbCsAJeXsYxH7hfMp6LGpnTdJDTPZPZVFUm +5E1O4BmZCesKZn6s6zmPz7JgIF5Y6hZfQxsFJV8Mkbj3KIrB13MNNJMIA3aY7bBM +UZ7kFPzF4eaGqa/2yDCngWcb9H8PLT5SHS4YCP3DNBqigntH7xtWIu1Sxh2IZLHA +mm1YxVX5p7Oc4TDDlwBOc7zKsfi9Vo+hvk1gJLaNfa85P3I2DKhqd/H/xPeRu6ME +3a3O3ozXs/C+8YjlwMJ2LT+7efTTVolukZCCObYFY0G9Idhuai4HqixeH7FgGu8E +DbzqC9DqM2CDpsmE2GbzE1+5XMq7K/1UMF7rK65NSLiYjs2aDoimMn92w2UQVVr+ +VrmW+k0jb2zccpu+NlFLaNykEv957P4P+Lh/AC5SOgz5aqE786wwMJKCigPMaVL9 +oP8t68rYh5+jZZ1fJO4Se9JCdSAx6rX22b9bk4EGHXMo4qKDtY++Z8Oe5JP5f84x +VkxG2CWx/An6k8aR5kLVzJQSb/txqqvpjkUEcmzZZGjFMZ7UbtWVDIV/TPOCf9t1 +Gvhcepag4zXt8hovyTBbIh9fQe1vyd0cKh7ReKe92MOtb9i8/L7uu8g+ywLGBN5l +qZ79zDnaFD9c1kCo0bAI+pAt/KrSn5WcpeiMIuw3ioawGbfXQSpE5O9O0PMwksJh +DZWrm6Mk7wq8bRygvYpQ7Q4w03V9d7vLEXb5AmNcljosabldsNUx8AEBGKralWna +T1iJ2x26eVrzdEOjnXO5n5agzUqysAuDAvWebgtGo0cclETFQF9xaKGNT6Pqj1Hm +Lfvt/6rDPWDY2MWaDvFVcLA9ZbDTTvxM9rxvE3TZy/xEi2QXrY4R1mlbe9R2DQMW +TVWwMw96/3oVOWTnpshsEMHjI15VA+garjiSlXWY9Jopx8bgLMCsxRK9I/iwPeQ4 +x5ticfaw2Yc7PeT6pwYoiaUI+V06tgibvgkwqCNWEihIu6GqIr1jEIvyLJWHFh+I +uEqPJWhJBBCUyyF4OMCF1uQQ4dM+9oOJ4zMlCqqhSfQZmcPlZDzq23UzgJ0l1dvt +xGZD8RIzcf/sZ2rik4mwHZsEjZAJgVakmoczzJOFesC3Eir0GgQ6YdrsRLHuJ3Xi +JJOrnYmJZOLeGHvAT3DjEcrrlQaA5Jp1NPQOl/yJc6y2AXKOvADuOYcdl9iTvkhO +MT7IA5gkzEC5/pcXm6cDP9TvxQAVMady9mMqjOK0/bv9a7fdbt07O6/QETf7C9Oy +VkIjcyVHCvVPacC+UtAjXM7rPDWAKGMvrNG6F09+nmctu048qoTJ5/kcG3nDBI8G +CVGM/WF1qXOnv2NHXxjVdU3squxnBTMtEO3bq2US53yI6KYr1jiFnn1M8gFS2pUZ +aPZxJEVV72QxAYgZSEZBbHZDCzEQVRU54WZYvtytb/+lEJbvkGWg89FCOgqmoN3i +3mTig1GzdkQMgJn+c3C6XCyfuZ76g/QKFXZSNfDPtCTiIaKNfmM2G+Vk2mjtUVP9 +CPZAMDUFcw4vk0FC/K2IebZdn/lthETFWXjIB7vOmN4tloZlgG/5EA4nXECYB23o +EIhZ4RRVm50SHtriA21YEgnmRHlKwcRIY+QIH1WpaHHkZIk3dzWmSMyhol5EL2qj +NxOejxWboY9pJl1KYOf5Pi5txcuoRnur6Qvb2tKPAapt5vnDNKYLz+/lFFJ3hMns +agBkLPEFcdEpkfu3WT8eXk1zK9Rma4s27yI5ItU/VBx+ejxpO6SvcA6IsfoBtSWR +0Q5l0k/m3DP7yDKc0I/KnGNNfWrV7pFlmppKEqMOgCxOfy6aqFcj2YSrtA/7fedH +Vb+UwN4Sd6rQUyW03wi509fPSmZLlaqV5iCypVkdCsrT8fJV09fn05XblSFULtW5 +ZMCoiyE3E6S5aK5qeyNfmEPKmBLChrZ3bQ5jvYRUewWuPw+5c2yD6o2M2QziTjww +gkEW8OyWuaBwtAO+LYPc3g3vwEjwC8j9ZA6zmE3F+1e863isgCyFJ9lNOf5lJsJe +dkpSkqHvh/RTpaRUyg0Ca8udX4AZsGCTU3R7IzRowhxXxl9/w9rYLm/Avp7oEN5u +KgGESGHp7SmVw0xyVE1H6fVZluyRh9r5IElsXvX6jvp0Ibuge5xD98UhItxFGO/s +5f9tRuag+H7UhobLbb6GAktNX+QF3g371PjQFQBTj0ojZyq2GMvo60GgIiYNwMGF +txmXP4lE32xl5v/2GKA9+H+CR1jWpITu1XjcFtlqS/adrWCYozRAsRyqC99MxvdH +QwZWZQENLg7t6AB10NX/4QOC0tbxB/VzmVyX+ojqdeajDzf1u0DS7KBEfCsumfVw +BYeVqx+hWcZyw4EEW0+kwp/M8aToLSvvDUR9PayTfWzuQKCW386MgfY6KcE/RrE8 +yamUgNREc9we0w7W3623SNK7+3CxVKk2mtLqarMVEfxoo5/SpH4k25GmR7cBvSWm +1zvkTTVigmCJoRhPULpB+MKmdkwwq9TJf8C+sBKIzLvdH0hrUkPHKY9rWTnpcMZQ +3YNgxHo6ovwvrZHoNuAVM5u98vc6tABdPyb9Zhd4yvFLpd7KpPNlsNQ0cZjh2155 +XesRnY0/P46ssKfbiWS88JICzhZOU5WkUxma6dkVve8MZvs8QkNRk4DQZBXq2HaB +yjn281fa1U1lvBTirjfTBA/yvWxmStqCGByqB5ZZ1AnwJ4S7WK8LwrKWRR1PcwEe +Vu9wOhF74PBBuDnj187M48NDaaHRXskyFdQNvVeIxgeSt+N1W23Pky5mOgzSptUb +1rrjRvKKRpANK9Rjyogv6BVzSO8AC/YU8gOvr8mtvgyDkgcHg0w0c4/+/8kGskSg +dtSGUUjFU2EEP6qKHbM913aq+XtzgH//1ZEMzmCePOn0uYXLvDK/LNXOkOiA8xqa +4gtgpWLDDJKXN/D1osMBSWX3buHq8nKs1xHHTzk2n3pjkOleaOJe1sERVBTSH6hw +uOH8kOJatpJLsVVOyXPtIrA6RPQjGzw37RVngV58/EzssMSmrHWCnGWNry25tQ5r +9gZCNmhoaZC5tMHlyryj1wRfUdhExOkHrcepj/BmzlhfQRDfq+OEIA38qzQU4e2e +HwhEaU7KVYAENzX957QrpB/7Lav2+5nwMRRhT5LRFDul7thxNdOCwtb+re0kU8SF +ytpxNPhchJR24cvwTJrX+0LucVD8cxf1JMatWh1b8TDEi9Qk3LBM4/HnMA7vqCbJ +1UPtqnGFjdUAwfzhZ5HF+ed28PR82eRh7AJvorCuUVoxtFZh1ckMbz3StmvkexbM +p8U9Zeqi/Hx7XHyyAHeAMBcZ0xAN4EWSe7l5ie8a/vi7xgbX1GQWTlFZTz6u5BO6 +HIJ1PB0JJsI+SI9I/CUzLwWqbt8RZFZs96YRdjLHc0K4jUnPBYiYuaL3DeAhhQbA +Te8khE+kaEl4AUtrXcOZjN9iY2pnnWwS0JyHu8a9Bms69526/faAs5Ck6msZ2lQf +f14Fb3ymNsx+cO82yQLJGpqkvMxJmLwST52bsZGPgxz1YT6BlpPr4XOkn7Mr5TYV +UJDFOdhlqPq1SVJwjSzuyCYyyVGzP2gbX1LMoMFOqJg/UtDqdMAMn/xrA4nZWGzr +WODE0xHvYv47l2Bxuupl5rs4E6CkBwxzY/CVY9FmifLcNdf5PsIcnx9zaxOA6iIo +NlEn4zFRz9DzC1X31AcUTxlF/rTNO+4vjkgFMHW+dM/BRX8FK7PiPBvQXornhQRQ +pP4dwx7wwomhAc7ywgzmODI4bhJHJj5w+1fRTE7aGhH4A2/u0shgz+EHQ1cPQukf +AZEURX0ay7ckNC47IIbeQ5vNRqxEdvv5CmxHbF983tEXmIwizM5lhP0WZ7/23hWC +2wVU6fGY7Bq0RP+23KCLp3cCPLLzBCC1csCY1i4pXVLr9Vtzi2E885/kt94wPuEm +Oq0DJ3wjzHvO03tiQvbo729zMY4AMBoH/Cyq7c2U8ZvPuB4NN+tdHMZRRYUlWqpf +yjZV7u+3sTqvzmLKjl98KyOcyHhj+0lxuqu9skR87lC/whL8c8ydlAj8tsjdNFGZ +XyOLphHHwpYsb2VxT85BlWHjmmNYzUqLl324bjtlnXHXvLpL5Xp359KxJgBx3w+N +dxXOSmpWi8X6XUSExPTGVDt0qfmWmxmedG+V9zvH5p9tHopBskZaosC6gqQoM9lj +Wq94fNIuRsTDqluCOCn50/IGsM79dakdbEoPsvInlM26XQMbOGQnfa1JfvE/qaT/ +Hb+U0VFpTG109vWMB9I3uE2IM3QFqOxurdpyGzWmGExAAdJEgquuxaUKchtRo0/h +swzA091pG9w8snK80AnIuTUE6WD1JJ0YM0q3Fj4i3Ucwhi7wzKaZLcei9C4KH8ak +RBErex4h7NxRySZGdmyj9r32hSUqeF9pdGE+AyXhCY9loV/0+IPQEBRw7dyS+kqu +k1oDCjQPIXNZSteVg2NEq9Ara+Nr5i8qBNEwCcbJfze3RwRRUJHfHUYZZv5Bw/Ma +UcqJGYuFA0TQxK2fwwr32E+9qtHQB6KabDjkfXkxos34RSOE4PuUwRP+Jlnp9LJj +P2uBo+YOxrlPfKLgavKoB+66pJqqBFxpkN2UjAls4A++BpHqrrD3GinOHtejw6LT +S2jcAZTRRhYfI2g/A6k3ew== +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +UHE03qwRSxH7Y3SoeZzOc2GpMslhCPTTv2Gw5RwahMzvF3iwatslvcgDdd8fI2BD +Dlu1c84ye8ZtLWKjSb7N3GsBoo3WL36AoYpYmyVW+heegZ8mZ46dNYCnxJYxoED7 +IvzgWWoOU2Bm2YgFxPOT2mKantYJ/ATXd8bVM09X+TEBE0e71DYDwhKvq3zCRpBI +PRftlHhH8DbF/MWedexxU6i66X/9S2mAQwPN4YRBCOf/c7OJ/Ole/Zpf+Dnwo9qX +aJp6T1LTtodRLhqdPlIWFk0iFCi1UWfs2NSsVGEcn05HspdOy/Fp5sIeXIK72cob +oDG+vayEozPxF4e7YU1aAw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 7968 ) +`pragma protect data_block +45VSHw6COPRciAp4YlIWeDNBlQFLxnoaBL7tEnrZqsDFxRJbl/F47dG5u/ha5AyD +xPbkq3jFeg3hEfPkniIXtKce2gZuH0X/X47X091eDfUgjgAJ18QpbQHNVovaB6+J +gKlnY6U28bOx4J8kuMnn69Ghg/4Uz9X/v5rVNiN5kDhYBs+nIO7aq1J3DvF0t6qA +AtRQOBAcFt0N7HHLvM0HP7NtjuyEk0LVFgvLnisDko7YC7HI0jKBgYG3YtVb9p0h +lgW89Uki861E0g5j7eKUfCHPQubEtpWo+x0QnI8BIecVowCTHC7ibLqBKbU/FbIG +EqtoCQ90d73V4sF0jRI6zT1Rvg9rNQSNg1xAOPB1oE8KJF/A9LyvPxPrCbvb5arT +luHxhRlMXtAfqwlUTh2BosyFNDSF3sKP9wR3VZeXh/ea5l8jOKdtHpDFQJIDLYrM +UhJRlsBM/cj2BXD1uMn5W8cUi+DlRcDrq9M0/UG0QCek+hGRRa5h9fcM82L2bVNC +CJHanBqB5f3Q3ysiPu3BOy7H/j9SFrerpYXVuFLUoy2oYnv8qf18UP6IsRJy4XDc +F02jGCHEpqn2itSCAmkorsQ9B2EiNL7qJnR2w8YoWbuz1qPL0LGoHmwAgHMJEW7z +BAp0+OBwj5FYAKteI3f12CTEriE1CxjzzUBHrCGyHBfpKe+BSmt1dFzsmYufK03b +xRGl6rwHv5qfNTvL6cZunfmLx9KLo0dopahxryVi4eCU9RMmSGdVEuthAG49NSAV +JU1nFyXQg5A2H2+pzRxwS953RYWH8zyNlVzpEu3coScuJRpB3sCLYq34eEWYpC0M +Z/KiZEist+kCNa/eWtXpZFu9BMgd/QPRFuxI5LBMBImlXnkIN/LiwhQmNyV2xwxl +CZSoA5eaaTs1EozVmqN2NzReiua9M8Q++n2oR6qtQw7L2kzlLO/ANTZ2jpFL4I8G +9fXFNqF9s+x55pe0HPpDh6H3AAQv1V4Ki0X/JsDvpH75c3gOgJegLqjN5+e0MF4Y +yThx1l1zYcicQEXi8c+o93bLr3kWTP/2Tcf5UawXoSVylz8bi57eKYdegbhyHivC +sWapRNixUIfGKJUZCO1lChL/IUJt5tjowYqsLGgthxvH5qc/db3MbuPaYctMRjkC +T+4YahLXYAW4pT6LZzFacA2LqzSzvtYDg5V8rSPVvorDy0DaTuJfTByHmCN6QEk+ +NMB7a8mAtDBA/jfXNGmKzyL8Wufx4sOP+G1Vk2Hju/9CR0QRcDPwt9/8o2ZdEif7 +OZ7qKBMJp9qJbfmX9iGIc2n9QAHdJlq+SnHnkACQ+fbV+R0sde0eGVsAMT3GHJty +CiJGg85E2Zz1ZeWlKz2K8M10rb0U52Uh2u5qa2t/OJTzlklkK2BHxuruKrQ8+XO6 +pQQnOI3+V0RfeEuIMki3uxUKsznJ5ev155bwBh66CR73jRKvXFECTv9MeZAnw507 +qjBYQDVqxznDWgqi/Vgs9cVudB+72DrN0CLd6X6gjEkxiYQBaED8ODVUgbdiarbX +mwJeiwOUQoN9No03iLVNA8psLMl6vPjyGtRaRU2b9noWZqhhi3bgLO17R9dRRHFN +k3UEjELluVBeIgkgLsPFIGTaklBvDliqw5rTcmByX4klp0B1D2CPYN6W/jgwDt1s +x95lWRZn81DRHcnl7+SE6SR3zpVkBXpyc64vb2eU8SEXiKbDA4ht5tbx1oY8HL+D +lhVMhbTQnqes8Qut54qshmrlbm6D90gqOOVRz7CExPEsdXb7x0s46Is3RMJx0fAD +Na+oEfW3+p6roRLM1Dx86Yf/I46FNxtw+zHcco6/pveCsa9BAXwowz0j8CrMEY1c ++0uGZDnWFPfcQ6/tkfcm9fBSCiIOLHD0rpjQ4sHRXeNu+xkqm2xUlv9LtPvocbEs +GQF9sF0Rw6/Z3lGQ7WBehy46E2ZlsNUmQBQEAf252+G2az7F2akLt1D5Jyksc0vL +F+60IV1C4VszKTLphmViEHLSc4EaxCfxq8Tc3wBzBk2BSvdjVHsSMaaBUqUjIsV3 +nRvA9VBDugCLsMhMc4pN8vh+nXUzmsMiiVzIOQlUzU3zycSswTI3QytuYZLs6VPo +ToaIiYMRFUQPyhesTDx//srm3cNiEfFU39bD7b6RsI3H9t54i+/kvrBH76Hwalth +eKpZj5fPfR0YdVksPwqhBbPz7EQLLOUcotvLb7Dcdzd6vsl5E/EejWv6TkE6bP93 +MX3UYd8lObguj0HTNvvN94RljIJ+lfCb4OIgsExwzcdfz+FUzRr+vvPdKgC8ybgM +u3rXD/hMn/oFz1G5p9B+vucJCypD42L6w/qwYNYALWKDOCnu80ygtqSuQHJ+kIVA +NcFs0wp3VrpQE9knMZswO3zNiuXXhRI56LVln5Oh/srJuyO4ZZDeOhAPUZm/7rar +tN7qJg2d/EQiT8Mp1tUGbdQKiCfHN9fAZ/lrQZA0jqIVaD1JrXThBux2ZDwyBZBy +y6gF2vKDqZOECfRZ3knSu3x9aZsr0PzQeQk2ESV9Dwxg8TeZAbf/uAMyYKAucVb3 +v3R12Zy6zkARSPfChZfIWNnh4o1OSYbuz9emMliBV/vK+pG4hK6jjLyTNQiGyoX0 +ft3xDSKUUDmkXw+0cOg/yzQlC87HQN/ZMsXZy3Uu4qa7b3uT1v4Yrvhx3M8Bwzwk +cw2/BI5PLrEkEhtRnd+0yjY7FSr4f2mFDoqJsgZpDm0nm70DkdOulIZcGyxBLH0M +n8y/qyGhycyJiOJ3+03D3v5wuGmXgEgLC5C9ufdUEOK2htabBu2FbFeBLbew0cBI ++IeglFuoXW/lonsQQ3YtGVZoLBjaEXQa9LMUMPLhP0h+cQJ/xvf4k2lEsQNAJCGW +OVIrFyu/7eiF5Wb8R3v4sPvwKQEvfNXf7Al13Zwnw85AEKemceT6tuIAL2DTu5Dy +DyBWFYCMo/gcuexXXiE8zZexW1KNocwfMR5jMP7WUraZX++WObwNLevsrni5a4zM +ujwr0ifEM7kgLL2Rs2xTl7O4FJvuyrbzoLXlJPUs1NOJ2qBUH1iRWa7UoD3Xdctv +A0Wl8uAjB25HnD+5UfMkuMcznD1ydA+Yhlhmig77E5nAeVahcC6CrajZ9lulmXGc +2+4A37EcrKYNtwRZqfd4D6g6qjQFnfzT+kSvfpGtT5VC/e3/wn4ixWR1MGWokfgg +22qjLiMfh3xNwpDk64nrYrFWXAa1tE+9rP2dwIC5yW2vfuV/pZ9/SB1xQRCTn9iN +ca2HXivIi9N5GhQqH6Pf9VNekXbeCiEaKxNP/MAKH/dnCQ5VIJY83m0/Pme3wwHL +bWgHWufKkZAfQBuXvqWADPgybADQ6E8GrNd/c0wqdVbzXzAx6LY9jMnnthKigIEL +7TiFRFlW9mngUVvZuDhphiFFvimiewtxNoTcFNQy+dBGZWcfT9xswHR2mRoEmp5Q +V8Uafl2tPESdezBqOe2bAvDRZ3nEcs5Mzh87IZbDv+3GobTgDQxF1JJj3MUCqGed +3cqRoNgdon0DfGxP8nO5DFqYka/oDJOjaewLIQS+RZHQfOmPVCBZo6t9czgkEhg7 +Xdczvk7YL2hBMSJpQtnYwQYG9MbX9epF0zYkAGCrQVMiy65LRgGmuLg4sZq6isZg +Ub7TGxp/g0izOz91FyTCMrudQrefmrde2Ex09attj2vfI/tIuq9IPbCMn18dnsFK +4a6xbKgRw6xwwzttLjEj/1S9qRN17RM7ukJAVUpQ7E3ya0AU5/BV9FCwEdsRiXLC +2ge6vTrmtIICgEyroU6mSuApdlFqgOYF40xP5SwX1EnvyjNDWwMfqrL6ziIixTBK ++B0zVBahAcssDU4GF+Zzq0hjpSdVVbU9erJPWDtCt13C44v0wGHfHsGI9KWPAnqR +fNHzCSf0+02MWMeLNs+IrGy++4+OacGQYmh2x1EuoU0pXKVGVM8I9+d7E1zDqucE +kku2JLWniUWNF9BEIik6IQnqWsedCcjiiQbDvGXRK0I900dlra3eoVoWPNM7bJ8r +beKnmQGOsL0YoUttnF10uj89zSmJT0lxNfLp8Ho/yzcqFhv/PTcCk580lt+7EfSI +pULVLUU65mB8RmRxfLO6l7sVL72GRNvkveKOqDO8vBYROgHFHEe2rYRLTRv70Epe +x3PH9Pp+ZpGs7IwGqCE6icuPNEDXey4xLSG19MxzCev5k+JNAwKDHv/SRvbEnrWV +/Rbro7xz68W52Nz/uhAbauWIFTXu7VB8+HMH8l17EhZuUOic9VmEe9TDkjzkstms +3a/hyVINE3K0fJ53D7z59kOx3pmrt2zmYyugxcqxOCXDdrXw7soR4AlAqCm4Tgms +yR4j9dnsC24dhfp5xjToIeusogmtafvx+GJ8S/fC3wLvLX69z4eloFG4eMxS6ijT +1I+ZHl8SOQp8WDQc3IgfMxapK5LfmF1lPA8Qk2/hKdjNI5f3K50FxYNn9gNBHVkv +fOneHMSPpZkfwDJ3Gj8OS2RPTUeyxtSvsYFkhsbuAcmF3YcbymnAwRoi2h5BkHO5 +GG0pY8m1DR6+iDTOVppGFW1rRm3Wcdrv3heopFbNW2ScVPD1AxeAbsrNJwht0c81 +htE4t7qLncl7jrwsPfU7Lq7jXWVRK9/qqv/IVZuTpl6XjsrUG7SgCtxqAezVTKsX +ovBVrzhcPMgH5q5Q8xNaGMaZMgS5GrBmTVr7QjW7/1vg+KgA0PPlKbd1eh6jTkUI +EZixhKKXrpqUlaU8aFyr8cH14+Tckgm3EMCmlSEGL2b85wNkOPEW3pBRX4bucCP9 +YPsArkdUpP7gnVHYvQJoEIxwoTNcm2uYNKQWZl4XTFzZOOo/5qYUt73tilTrR/Ku +SC0qgNJKKHescLZQLWc72sCj8Optt8XNanNuLo1jcqjyrXsNq4xUCNnbFLVfnAOB +WXWSHnjrtqcdKgk1rcUIPZOV67tDkuoRiw2IStzhUZVZOEIEc0O+bT+yxfPafl+D +nlkVB6lqdBs4XpMgrXrkhwAWi1zKEw9TxQMYEtZ7axHHmpJuA1Z2CT5nXyVJZZOf +vA3VkHqti4peqAvKHoG+XljlCSUHhHGBG5SOVGsL2h3rtIVWYXlp6m7SmJnAd+aC +ZK3/+/bSS/C4a5/4+YphJwtB61jUUClzbzn1HFPN0iWk5hq2vp0GL7iQSFe7528H +kjI1WgzX63u6PxF/AewaFWKRDDiPD+43uEkuMbJ0uUxF3hezsnwWIiVB/zeSb+0w +nV+jRo4jykOcIGbFDsQXB2YU+VgH351S0ld8NekGfTvBrw0CzKptDOAlh0gunZQo +LMbRvFLghwoEcCU1XduUp5Zl4tePfwQ0poVp8kxaTj8qS2WMsEXBRXnihfiH6eI9 +PmEEj9jAUUDZvOwhARpZP8F8PXRzVZKsNvIwSNindUBVcgJK7zAybOJVbFgOW4z7 +jWRxbfxERTW0U/kvIJ7YfMmTTDRQpMmtvqZOtQVO6u9aygQqZDgkfNRVjOha2Y06 +uVaDDVIGgrQDKJUxUrxsbqeToUTgKw1SLLcaL8LK0YzvM9bbEBnCKU7cZxQ3vuOB +O5/u5FCzB+BgsxKPFGMjXH4gJ3nRgsEYEGWg+i1wSWTd3ROsAsNTK2LS3pobaG9t +TtvZhORoNgz3N6B/VafvxL0JHJW8+qIMjJBu3xlWEqgfcmYOvJ3rIDQgpcy5pdor +JUaK9GAoye2sMK/fjvDI3kZK5eldZ3Of8x8K2qnvlEJtURlI0/TRAOFk0FJ5gvVw +9ZmUgHF/0Ub/MT6PdC87HhuvK+Ivw1Far45J14c887NE4zCYNLYoPSgsWoHtLD/k +HRSmQwuvet2688ZsOK1gXvK41lKLsiUFVf+LDFw3VxP6B8M3rnjOAvzAHSkGXtq9 +IMTZcGD3ejZBLXNFVI7Z0SSm6NS3PJ7k0lsL2awyZApwHGU/fkS6PNQSOPFdt4mW +KoAP3s2pGt3SGhAh5iISNS9wAgy9uk3P+UStWtJ4F6/P1mlvIMJckHVI7dqo50/4 +n00ni9rermeAgHSJPEXHeUC5y1gcREuBaToQzAosOE4xfqubLrpnJLvvbL+8W1LI +gQvllnxA6USRafwaSO8whWtyP2Qzy61cQEudUlj5ATGa7x802bCdWv/2QTPJVb1n +RgAWJs/lf0JkKwcHXe2iF/3+zz8K90RrEbujYgI/3Udr5OTe2nVkr114ZfuAXint +9RzW8nvQ1lQAz5JdDs95rrJyKny+EJVHJKDSijde6yFfu8RwUGZYKPrk2bKIxYT/ +HebHKfyHRt/FPjD7LHPBR32qCN4J5LTPOZjkY3AhHHk0oZ56ADucdHtpiRH3di+r +FgrKoqruwY8TjAI4EpL/NEzB0RApkh7Ysdmg+7oqQ6NFZtX3TaUnKswkSB4Rt8EI +JoM2PD/mIEwLCEvBTwxfWRFA1QThI4JOejEvRrPb9/DgAQ6OnjLgr0OxFNwEX2vs +Xv96FC8a/ecOVHxvyApjo5A9xuZQwXN+1lMGCUWc+TYBk+boCLv2oMvD0vhp4n7D +msVXjRRuCq1HwGN6ZggIzLiCBatz/F8fom7LR66O1EsTNUkk+ZUBdUpudb50FG3F +ngulbDUEx1bfP5oiLhJdwnAd69+fZGZ+DS0emQIAUDyKeDEriOdsCPpOy2V5+kwp +eMOUkrQIToo8NqKQ2wl/iXOH8o9QrPcFoFuclVrDQdyjJEtk/1XNUhc8G/y+uG3J +qwCi/MO/rpPReAryaLOGlmCSa3BrrkekthpKRvnGF2tcAJaMX4X+YgcepnIudhSO +SNK2BaD9/B3BWQ4OGnMlUZG57njqYVrij3M+9DF/bmNdBTHzMXFUCFEVus9kAlRq +uOtrP43hi8nCUTUm4UjcOnmO+n0HWv0+C2V7NcIOCQj/aBrOy/g4nakw6IVUmL8A +k7pLPUSFvi4KGO2cLlodRD231ulgX+wKSprXxY13MbkZ62akr0D8E8HmegAgWQtT +WNgE8K3t62271/sJL+OekSmN/JITzh3VGpKX6mBj79gszZgEsL9rQXlHadk8rv8x +85qiuXmGgQ5bk1T3zLzlrGewjLV9nSaLwBcdcEdXOuPLPUdM1zrHswyeyfgm6ykd +vdffnbGtTpx34iRZsLQMDc6ghir9UH4C0HvP2loHrRlo158nSBOL9fKwsNPaEB3l +Ju9CTMyymP7kwhG8Mhb3GQJGbZCHoQ6DXwWLm8sjxIrxHbYI3urhhgoqqgDyRVA0 +FAaTxAmLUyPMIy/CQrAIyhXaYdE7OYPbtbKN7fxjS0i0S/IzY6bb4KO47ueLTsKG +9lyeMwHJ9+EYigaf7zEEXM3YxaA1GCpSlQeO5QbC0H/keT0mGWJuDH8r5PZBlm1i +mseJXU7C7TnPQ+5xbY8izL3NIHkO30t1pb+mga/5wBbyW6uWxyBWnl+xhikqRSMW +Yp+AnRYFXjg/AWaB5N///HmsIMH1Ba4Ew8e2KAvkUvScIJISJM3xJEAoxYvRtqNd +t6N2OwWXwqHckirdePd5x58Dnhx6gf00RyxKkU16uGxoAXptphizOlLNeY6N0KAc +RmcCSbAXPU+1luobU0H2LVCJ5Dq0rqFSVljCbw0P7EFNdUJCZ79DfYaueYFhDbrH +l4/D0sI0LzZJVYqWzBMRMiKWLCZzl/XnLj5O3YfuX275CoB1nhldApsnTj4MJfMz +NjQM2w9AlramXF7TJOZkSusF85DxQ2YaFzgxYzSjdcr9QLQWQvLG4hcIXbBGe3tF +tb3R3mGxB28LIvT9FJZip8TOrLJrriUi/75BBeEH25JB1pZCzmR1/9HRftmrhqjh +L/y2Q2a+5WWIuuMIwc88hjpNCUPlTj66ssfLIJH5UCIoxL9mjbzTposT20LReRwh +wML/OTVZn76sZUGPz2Mku7Qb+2nOJlGEvsnI0+ICJ/VKSyp6ZzYuMIc/mWN15m4Y +B72kxpMvcuwDNM8i+IqT7VHn7cYGCRjRtiZvbK1GsLFFB8UPrqSCzAI6hdhj0ApD +iLdZjYfiiHp54E8TEBFg+oLkNTRGrknHma0rVgbtEylkVz7LxoPyXdoRGb7GONki +UhsXHpTTOsZwDUVI/6Lm+9OZz2vMMIKPJDP3lRzolEdELj9gRgnA+bGO2/aEBKuK +VztNCOK/J6FczLGdP3umq6Ow8Am774N3IEOhVMY2cRmNFEiAfSSdO08hJi77QtoD +mJO4EefEU6TQxCSwOb9VRN+CsWv2ZS3cPUWMd3s/U3vZoEbITn4/veLTXsVtr4mk +B2qC9Gy+27CE2Fe4E/nJ1PN69pfx/BTnjEG1DrxXhH5r73TYVlO7kzsgkwN4TOm0 +4vc6LpAL5OBiq4A84PnUlldrRl3/f8QmndGsxPe91/RiVH7CAtL2jdk6QT8CMlAf +V57yvACorUugUR1SjDFxqO4hozNzHe87nJAg7p+t6e3yU3KytrlJxP3ezvYPHIy3 +clHIKyOGJkqLadaZwepNA5LPTAuGZVrg9Kly/pBUUQ8HrZKW8kLaZ7VEfHIycuc5 +dTM8ECWhzcREregYfBZ3JXpLoz2wTdtjm6Fy0CPX8lmA7+tnJejTGQpbm/WYyHCv +vub8hYvwx6nVNyQo+YL4G6mvN37XvuN4EKZ+qxuNtOkSFu6TLi3AmEtxMyWyI3RF +Jf4H5Dksmhtj85v8urjcybhOjXJOKKuiNY2+xvfldkjnOP54CF+DpSW/QVFS01FU +q33eOMmQduA/HPzRtli72yaRBkAEyA7i8RxO/THkyLFP3jgMsOpebHTJq6bUs9zX +mGZgKeOsemiHuXwLPXKHslrIA2xvjeurDPIma/2vWhCyOutIiNlXP+tAG2lEilQJ +vpvQ98SLBvzhNcbiPENwt8hjeXiILmw5OF0Waty340Fze+9udtmnBSwpM4Pws4tx +NLXc1R1SuqplWI9idRS9s8Mq0u8LTrulbBOwJtyOT5O39ednV5+fX+IezhjPq8zD +L55gnivv9bpyiVLMKav+A+gK+Tpk9cqZor4o/YDTrmJynyFatN+CqgOMTOpxwzRq +nb3xi6UyuEBBVqJBMYOWNJjHsLK006W6+Bm1nFSz8jo7xGKUjejVci5cXy3HSVaA +IAtcbI3zthferPLaKokQvzmEbLO+ZyP3cH8YlH7hwcagDxaKPO4vmymDaKlq3WgJ +U0H//CsRsvJc6/gaKI8wXem5Q5Mq3AwLalW1/r9i9rmjq94/6YodKPKk6eDP1wrO +nC5cMe/DOv7+2aizaWAhfrVVzo2tBbTI9J9l8KJfM3GC1i3GHdD7C3q99yO5yHl9 +52V2pvh6ycE9dh2q63qrLvAlAmIv4PNvGrLEEgu3D262wuwNCZJyeLLxUHbvQG09 +lRfMecZ0cUYoScp3QMbg32o06o2KQJzyDiwj78A0kPT0UTnnqUmiOKTpI1Ffg8Zl +6uqOPnRrijCqzMzrQIVqWrNvkiw5tn/daY3adz9AaTW4uXHK3ThHWVp42cC2tsCD +0CIIGfg5CvVm6rNRz9S9zJS20Om8ZrbkfL5hmXoDL2nq4C11r5d2m3Yyqrpl9hqE +7dRmAp9EHx+rGT77Rr5z1h+jXtFWwqhn5hvn+BmCFYUQGo3JL1bDnk7E6g4gHy0m +OgKHiCFwUHWYiLhR9afzNPuYKfydhjxTfz/fOPli2WJxK4O6mG4J3vXGJ7JBRTWv +xb+pr0HqR5huMNvVLLzvxUq9uEg0+IhY5sZj8cNV+NYnYPgBK9XIQYgDLu+9d91Q +UK7z8oo1M2ieR1EHxEEqz1Je/byjkjzXh1QTclKaPYJCqSzdG0ei3gs3RQHYqcri +ibwKPMEx/zwiRHhJ8js90S+Utw/inYdTDbBXhf/2jANGbWH53M+L+zwLU9JPUgzf +SKUqZomlgwzYoitnSwX3OWGLZQzC8KDDAh2tr9j+s8a4NwsPZtoMRibp8gl4jVwM +VQp3c19CrrLraOhkbCSCM5M03WSaUNHCu3X0hC6nRJUd+OI+vnHluU+wQ745UlPZ +mQySnl/aW9rjBoXpjGhDzfdmUOQ2X3MPnGyVYKZ/0THt01o4Yse9w4RbX8S0iTd/ ++fIma28pu0HIj4CytbffI5DCdRI9BP/A5j7nNnp/xZYfmU2J0U7N5+X8z+YZDGdr +KgyYIMwuVSWTgWA80mtGmlauVjBRFoM9QrFB5PlIQzuK9TzsMlzqbbt9CpYhwxd8 +20GJ62/I4tfnyAtSesj3Vxsmh2CcP8jncGmsswSacE5PjQ0OBbM0JRQzuqNS5fLr +cVpGYGEG5fOCPUmBdaXsR6ck36TM0W5yIX8cyKHjoGe7X6FtrNvTYzgxjhprlXdt +z+9H7hh4/n5TuFXCD/m3VxukTolCF4eThGusLF50AcvHh9LIpefTtYIKTDHyLK2I +7FPJZ/MCytqRTwcKxk3gdI2PM/hnHX3yS0IAmzjhYVhbKC6HulkPO4bKmaP1aEcB +iIftyAbivNxeZb37AmrSU9ongkc0rxk/63IKi/AJY5Mq0Op1RkJpt6TGQmfmgrbI +txdPUJ8EbETX/kEN1zDsEc9TNTkI9GTqPzpFtMbW9wL0Grce22pW+0c9teCkFqyZ +WCG5wKnmiQpeAVv1VHpYwdEOzjJv0UbAyfG8kRoSOC/TgG1aFA4o+/XW0wpw8Xhw +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +Z0bYUsBqE8947zdgGWPpqFrvmEzhq04RKLUN28rQ1wkTNc3p6zFpUJeEKPaQ9Q5V +tCYl0NaYT5qvQhZvCzl+x/jJ8wBpv9J3+d7GNb7nnUIy/NMuLGEslilaFQlBW3Jx +JcuDPbbVPZh2va/NooKz+kXCo82BfGYEKaWptjDHUpp3QHpOXlNpyho/A0yFqBSM +AejUEZks6PR4s5Chf6BKcUmh7/XmEjgEZW9NnltYPxumu4dD/IWfrOuVW8f8xwYR +Z97hT01NAlA3daomFvT8ZWfWFTypxCaR6SyOEXBxs3X3UloqjzT2lLIga9ZeNxnJ +dpGd3a3KAPmgul1Fz5Mtwg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 816 ) +`pragma protect data_block +Pf/yNaDaWKTTpcOJbNx90t35XxwYm/d9wJOyWLKd5c80p1TKmFatZvMBgclEa4wm +8M2luNdoyRCXtgCXi50UFmvDCdnKyfDg4RmdAGBqvP+DQXzbgq0r8Hcu3R2c3wRN +dTOMqbGACK9r8AnAP6JVOPyWpeKNQ6fdAs0PxUHD/zDAy3eIY8xzpFkIH0QIw5Vd +zg3YQ3fLlhg/CMJOliQARr+M0e286QIKm3zg4VEiVvBGJWAVCaM35O9a9Zk+yH6l +or2juNa5ufSiR0AWyOVS6UPlrT5E3bIcuwEhZa9K8mocpS8sd99uS3QYwilx6wTX +xpw3po/K6CcTc2xSIRZuGtIoDL7Nxa2aWlsl/pc2iho2+Y/HYDZThrmd7tw0XvFJ +PtsreaARZHeJ7ANRzyrlQMdPmAvHCT4CjKIiyVKvcbgFUw7D2hMP/688qBFJwEPf +OCQsn9Np7TGUpNWt6QG2R6M66lkyfaWYNx3vhn2qGO40/el4dpXgD1AlrDUgBuRu +ZpBP0qIOOvsxghto0MOUaTuj3+Q/4iCLSc0dJ6d5o2j8sxz0klLbzDJySqdohJrA +41mUZUvEZ4JN/flYe1TRCCHEdSk8h+KkvQfDqqJp/QDS7siyLQzm1JyvTKhFo8xu +9buiNusDvnLILyoCW98w5kFDRf+zHhWKN73zOeHGQKfR0aO7fX3pxXLsEwLhK54b +Wir5u7+9pv3n3v7469KZUa6zWzkjWcFjOHxaYA6DuURi4Smns05T0Y0rMtc8FSbF +iUZCA5mPFRKviK+6VE2SsjuGkMCA2zm8qz9z6Vgh9t9Njkr2HoPnzquYQg3c58Kl +iGHWXfuurDXwM/EkFVUF85ojRFGfXLF7sD1V5UNJYnKp4aQBM/8+TZkMB7aADvGS +/pmGmD4xlwLYjDOWgp/7091/kTLRZSLPoq1OEcfO6Z5VqaAnDiL61UTbl3/DLjMh +cH/jr8xaYKd9boxsCL5d/mSuu+iFFlVTYcZLhaoa8P4MYLRW2eaOjjuciNYperOb +CgHc+0M97uB37gtHJWr/eMavucWdrh9vHieFTjsQ/ov7ZK9++h/m3x0K9faH7SvB +`pragma protect end_protected + +//pragma protect end + + +`resetall +`timescale 1ns/1ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +YgWaHP1VVrn8q56faPuNrQinWLe/8n2gJ9/4MU4MDUiGnK0PUfYovpXAmNkrRzRs +VtwlC6Jj7InRw6kd0R+Y+eTMlcbioFK/qAxJSWfvQxCOPX8d7BT5wuWQFVsUoS+M +oh+4OFFo4X9aa0mI7PEcrjEhR0n13PG73T68EVWvHz7FFgytscWtG8kwqOSOXmav +jLPII6xmu7YPzZm/HiNsnMvvViuwT5aJb2CnGBw6n76GIMmghRK9Q0a/Qiylcaxx +teyYIGLKW29sOz3rZ/ENSLo010LeR2MXNKrLgL+PIW6y4v/FQ362XfI1qYw2kVQm +jpzkoevv37iwQEH6GlMwgg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 480 ) +`pragma protect data_block +Dd6JpxWofdheIkHFwrjiQ2TUBTsSrHi5N4DZxL5ImyVO0a8v8bX+ETlfPNZUE+8r +SwuVh8rOFSay7+0pb14JXUqp+DkrtVuid+Hu0E/AF2LxkH8xuI4mtxHP4wpCkof+ +XA15pr/1OIO2oas5XoAkb3d4JYntYFFoODk4+Ry6tArSi0pQCUAbp2xlJccIS+7g ++yQ1oXZ31XRzEQ5dk0k3B51+5qfFF+dKhPCH/Df5via4wF9ZESfu2YPZlRfXdmiL +yy9HzqqqDPfcuBtnGBqdYg7E+a8JV3eJr31WINkRjB466nVEkWlBw8tBpYiaDqZo +u0czdrGrPhk/G0pUqGMW9g8fhtSf8+oKfEhbK/gLqlQ78J4aXdv53kni1ylyInQ3 +wV2jwkio/Mz4dx3QJbRxdjGpui22vVZ2a5YkBVEL4E2xARB/u4I0mhdtWP5+FIhJ +TeOjuvTS4qw9jLUgJTmvsHnAjDsfwZzqa+7FQRfiR63Y073cnUHmB0H9CT2EuM8S +Wb0yYNeBSqFL2A2zJNIj6ruwaUeT90eIoNB2hglHXBAkRfqiZM0hdbbuk/CcAjuz +XD31yYRsEQXfcMmJ9P647dvYwdzECtBFUlP/DaczaapgIKvsnSArzKsq6691veHZ +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +mUjzSHf+uYPqL1n4IVyPVci4v0CrLYmPDHLV4awO61biHqpmrq1JTFqZBQseHQkH +6cJcU4LYtSNM3V7yBbMqQgr+2S6WRbMzWLDk7oaYThKqu4qR52i/o1CLubg6qn1I +ZFZY4okKZs8sbexheNKJFEH4N3Wx6tgv6nV7d6h7M2htuzLclk8xDgldmWT/3b+p +G1LAS8Dq6Ll9eTtFx1t7AYLaCpaSUJfGQejrDqvXmTyUs09j8PYV+q84M8ow856B +r6VT7J4TsQhul/FwXdFtG3r6+gx0T6HnCq6M0DDmeoz7gLnekNXKa5FMEstTWXIl +ctxitcmi7/Z40dajl21emA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 816 ) +`pragma protect data_block +VLstfW6D5LEE7ZexczR1r7H5DG8rlhP4PiND05BP4I4l0Z+YIQHuCADYxsh6LEn4 +hfTsh68yilbNO1RYyv5EU2gjhG1upfVQG11+GG4wJ+ebrmO38+XL7NE4vKSi/uq1 +/FlhR19oRl1Xje3fr8W9zaMTqhu4zTBn09eWOORepwS4fMkhXDRdfK0Lcj6cfR32 +DajYlFXlce2ky2kjndjmYy4p+Ii2I3SMM253IdlwVcL/vDCxsPGhRjM1BbXXs3Rl +Fg0A1IZPwQbTFdpIK1uNMjbEGfX1Rd1Axz2dzVQIpouDD7GKfL7fcDbknBi8ax72 +z5dSqevuYtuAYkXME8N35J8kSEm+PDHri4PAQn+PTZ7SlAAdwGoCshfev9Wh0FuA +6dBHNnp1Xolo5hgBnLEpwk86eMfpCEmS2SOKT+PtQzbH/9ybtCy9cxyeQa94puNB +pqLt2Yz6ZADpH7a1qHCSWk0R0KsH3G28FWaDVmx3hMo3v1hO69SSL8MaDkY9VaSy +LeByRe8Ocunna3yDiT+ak3nldI6eEkox1A7a7fzP0wr/izyUB1nnoDUKTBTpUjQs +imcM6DvZ12xUdevxNNDoT35XfdHilBxnXNUHukbkfKKa9DgELM763LGt50La05JD +2DRS5asmgZUt3P6om/SMA5wupzfyGwJ1sD64NGeXn+9UY+o3kmQb1PFd3ojnGCSs +Yk09kJiIMVT/Fvaz5kh7T3Fwq4fW54zRwQvkbBzHW0g4v3hQ14CKOY5ay57C1KPA +Xd/gjm3erxvE5KRquwl9qBbPG5HXLdKGYsBkeHO2syi4KI8RepNnQMko2IFoQf3U +Dj4vIBHKC/ghUO9ivy4/445hL4JU9HiC1bFkmP2Ojg6j5gR++CI92d6VcPwzsR7+ +5Pan2unlYw3kppVlIX9wgI8lfRtiM5zHhTFf7akTXgwmzfV+L4QWrKzkjoNu56Lm +znT7+JDPsManGGeE+DsdMT6vcBDhrOC0AI82jEGnniFeT6Ftj/Mw9J+x9J8c3/z2 +LME6fkFQf6gsTUIeBwvpixHwCM2oIjWDkASPIl9AXmSnqjAWrFqtI7TuJfWIkx7I +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +Ye1kA25/n0nWVEkXGZy9SyuUjU4Y6TvdjEyZxdHOYyJqvaDK62VmGBEQpH39t1uf +G8L8coe+k7Rady+4qr3L1go2bL3nKa6Zs0iyCYjP+pJkLJCd8FNBNVuiXjHTLmaA +iCbjJ2285yoEhYQ48PIBTgBPoG68Vwof5V2YLee39KzlRpYFRuoW4j5BotITbxop +M9I7g2lHQpoxnmuMjZUaCRZOpg9YTqzaJ9bGFkZj/vOS+iLMgBpS8FDmw0+JzJgy +murJ26ZaRXJi9Kd6iHqxOXbae4vBRW9ICST2GFrNJ80p3zPkYroT+xnxhhHDUHEM +CifzZu0QanpCfZ2ZIgURxA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1984 ) +`pragma protect data_block +Garu6n66/nHyqmePOZzFG3PDA8QRaG7IaDod4zrXzSsO6ogd5o2PVUPNh5VMNGy9 +77oznQYEYGBW9IuZ9nDC/aq3FUmblLd4hWpjknTruUObUXBgYXaE6zMd3KjLtiM/ +4HMFuoRnCWnZyu3P7Dg3/DTIzYgrY25ZiQvg32jyrQBc7JVQX/Y/E9XSYLCAbBVL +oMLOlqe2q4buUzSavBhEQxxg+mbrCBeF0D+HkAv64VjUwYTLcq3cmDHG2FPNTcAt +4q16s7PqBBLVN0zu5nDAjR1odHpOwf9+2aNSHbAnCOf9vIs6plPeaJ2dTcGMnzbK +A5f0/sGUSCm6rerxL+40kvFbQNZwTBe5oCNzi50Qo3p+tlJJpUfWIE5Adfxd+5El +xm8NVIZsarHxpOQCmEJoAekwXHtguYTU/JAdEjvQeqV6yttJ21Cw/xpCXCdayaIc +w6rPPRuNOi4jGbQOlrqGkXDjaNXicd1qbCvv1pKKg/gG7bxQ140/0q0DMpRXbhL1 +82sVECjdRMV+eMCmK6hxiPDwgzUqCXGPZLwXrbnTZJ7jX6cJwpVEMXGI4IsKAqju +2BwaPCYMXPw6PxIDLs1j478nZUi7oBJGYOOT2sMI17gE5y6VHQFR9o1wPVU7QASv +/np7nqSaSEOdq3ayYfKG5YFEKesSD/5vEJS5OQqcVIqiERMhmo5ek+IugLUgDcpM +YKz8V3KZMPR+yrc59mMTBV6omcWLEB8RsejTADaKvILD3uOjHW/dWZcNe2d6e2cy +bkRCVUgodXyLhoZMiwcEovjMdfclnV+xESfrCRfBgKsyf5gIqq61T1FbHB0YEfb7 +1yEc9Kyl2Ysnj5J2UuoPhMwHx8yIwpKkCj8B9oTig0SlacnFmVs3gek9gm2LZ3Jc +zo2OPHngZcEwvgZK6/2dn+uK8ZzMQ0UDsDvuJ0kBG75cn7fdNMuVhcTJXQC6qyHZ +QHtyBoqt8Rcxj5wSb7yZRtcjINE0SIOeBzjTIAO8W14D7iWr9ASUKE/eEoXi+DJB +AEYJrIaAE/b5EcxHDXxmemU/KfB4mXbqifqCoJwd/bYxgrv0QaFsLcEvpvEgHGU3 +rg4digLRvmw330qRA7Vl2+XXE4VpcCAn7zYyk1/e1kqY3Auogqvv05f291LQ/PqH +coKVN1Jb9PwuZHxREjU2Ef/N8Vjne+33IiSVPP8V6BYUaeNTK2X9yd/r9VrknpGW +OwGqdheLqFABvI/5/pXuBh6qGxsZu/O6nHZtNCGIz+A9jF8sJ4FYvcWIQB1ZGHSU +aWeUO6EQrGl5iXv6L2n3IzhAlibOo5LUx4LlGtmAgSF1fcGw8/g59TjYE/XF0RIX +MuKrd6LkKTzcQwP0i1dsZV8POnyjddy0bDlKe136KYMAoBEJaGpTxl3fTFAwdnJo +lKypD9As61wWh/RvfvEzFepl74afSLx0hp20ap18naHyaTNX8iSbnRhderywFXGg +tNbBqygju/E8tSi6bAtMg8UxnKIiHRqZTfXvXeXywzxg+6Zu3IMJjB7ejZ+wROAy +W2qqvT2xIAKnTESeVYdebjIaF4Akjhn55d+fCKjLCcjtiYSEvH+8/YwEq1NsCe2v +BqPUcQnpIhQQ3h1+q3xgQxu9izSvSoMfnzcA0XJbnLEvjLXL/LNkEPygUO1vXpBd +ovxP89b2JvD5Yj8TlnrPd2zVXpGLizuYbiTkL+eMAIkWqGCeuxFjPdyFnu/ecPoT +v4xeadWKjrntjRyty43Ir8w55U9lL8t4uXf6pNvAnpkklklowO/KXOGYT/VsStj1 +k2hSgN8ODWKbf44Zvqq2OyMFjqg8Pll/Iz3UgvbGll4c9mdwvTsZS00etus7U9BK +X7o+9rt1SSr4jf4JfYpl6M07nDaFwFGpwO/G1oJ++sx6C/iiInH8tvIw2m63aPob +DagCnY9qhhMIsvfWQl99bHuRiajikI81oQGPCZda3m/guOv3aEzat9njTPuk20SG +RL4TSWqHRiL7aJm9QG57LjyeCSXKS6A97pbPXnNDaoWRkxpXTbM1EG2WQVxidS1P +tCgpf/HR8z39GbDT6O7uEirisfd6YS0r0PRYEGEKzSOIfH/sX0RU7SRiDz2t/EPA +BI+rdXHZWziUI/CqkUJnnEXjkIx78TvcJrgbyY//FENn8hw1K7ylBbHzIWrtbYRP +kyIFCE2HDgHg4oNEX3RzyZbeJgsPiz3gq9ZCH1A44K+YFDJeN1oadbFQ3ulpu1Bu +5ASwlCWwro6xmU7lnN4ICbg9lFnzd+XCmKSpzh7nM3OSDdReJ+lIxOiS5WQjVGyt +C07oNXUo/+fnvTG3hyoimK48X/3LLef1LKIl781mNlwEvrkmRDhKFtSYTFikH9GC +qreMKzZkYV6jV+/QN8t38WsgH6ggI0W3hBG3Ss689xQV6ZURLAAswSyqACD8IJGU +EZ0Mya4MZgvCLnwJAJvIYFxaaVgkNXMQPBa+KMtZ+w+dsNiJmT+OS1N7s8mMNd7C +whNLkDItqcD+DQp4eLUa1y7SDWaKBT1zn8ZnYFaVu2fvBlkSC9i/V7xudCy7s6Dz +CZls/n+CDakWQp2eZ9rs+hD1GrR+dlDoactpTFszWYY3ujiDcs+oB+PlKiCziGzD +2CXrv4rMXPfj86GCN4+2Pg== +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +gsiyAh/zL1xUwpmprr6NAQQaIGczBGjhcuuUGvpHL8hMBxgMPcIMpvp8WS1ajEHn +py5FCDlR4mW8uXNvTts5kgng4OG96+DdQ4XdXqST/b20UGq4PinSXtk1LOUv7TFw +yYAQKVWJda29Ami/BKJegEbhdCks1D69roeJH1DSwVfXs4+eMQrjc7MbTbY1mpoi ++36fJivaA7U/YlJiaS+2qIhWoSM5Fyzla5dhoW23p2f9pCfJOwY9bYe6tjCBi/92 +qgy3zls0rjtKupkAlBZ6bW8ESkTjiRN/IyOih61JTRjJXR1AGRDFnndbdKW2JBRX +DDpVDAdIo0PQsrjeXscc0A== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1120 ) +`pragma protect data_block +oJzELbB5LZeNsNweu5uYWTTwjiMIVGEKkku/Cry+UEzxU3xbxPijNdpqwF1CUnIu +gyeQXm4W/aABy84cGADozOtQl9tYT+8iEZDzwxiL3TduRCLut952DiLthKX7tDiz +K/Sfo/5K8SoG+5gMrxRT+PS/OgH99ThFjftnZaeUDUL2YAVcGoD4l/tmXQMaYC1s +0Czgtprrh9KgH8U1OZPWXeGSCQ/Wcvby4cJ6waaHQd1XX9mgmkyX/DoGVWjHksfl +ON/V2l80YzUA7kz2S03VWrm4E0gsaemi9zjfxMffXLvxxFfUfh27bbeGbwIrV2P/ +e9ACpAixlZbLiy4SPN/TE/N/fx9mmqVCzM5nL5Hx1Y+zloPNKumf+FN8/LHE3vTI +X1HR4/qS0EV9dA01WpmmGNaHi6RZ7hoh80NoK+5VYpuJHrnzM5+ypXOqpKkAjzxA +PyB5y6AMGk75Zjm05EOdWq1bscTch9pxEYwmpnwNrD9SeE6QZK3cSzn6BWR7cGYa +Vh2bY6lwovJVl6uxaJms1dMTnny+SrkIitPqD8Z05k7gsEIdH8UjJnhvlhP9Vzg0 +vJx1pS8CW75PYm/7u0U4o8iVOebmW6uHmra+CbWEHrdv08OZ+VZdJhY33uao+Hhm +fKI7YBd4PCnbc9GiFI5j0hxpSxw70bDx4nkVZU1E27kM3unKmi3SkIE7cC7zFQUq +1OSt/GgzDEU9BzLXWd8ghruhmr/a9kORV7mPvMts9jKCMgXxS8LmXeyAwgw8GJYV +6fjbL0qWyPd4UQTGmBZOpQJKadU7ru9JPIrr+1w2kPg+jMqzH8+ctqwHsbx8lqzz +re+6w3Hin7b45rVm3ABrbdS1JwelNH4xoTy0X/oroQFQglbZ0vJPk4X8TLDsz1vK +OnDEtNKwlLg1QZLW+lEXBoSUk5LXQWQEgxmC5YU/svO/VqGARYosvV+pF8aA3pwa +HZkpdtk6kNHxhQO4OlV6Tq9+kp8XrvNYEjtTkwKCzqSuJqNL5cGqKCHMzfz0lmI4 +2Hg9HDZv4KxkbAx/5QFoSCAE7sO5sUxRed2562cljCUP1B7HSg5Otgw73Fz1UupU +MIIkAlf4wy8MNnM8pU/YiYqabOUUadN/Vs7mOg3Jnj/UfGRrKxAnYw1YGQTKAI4A +qu4GPVqmPP0dYEi8h06AD28jO4wlSHGwb894S1YlipYskzfVg4PD88UduuEmPkwk +ob9Zgj3JPMAErReBxRpJGxDLrK2CMpTdWGlYONQVoSkdKvTj5C1JEtymuUM4IgP2 +/DfWb2DbudqukHzzwVjXUdiXgul0T/LseZLKviSckTQar+nVfwHYH+9YNK+QzQ2E +QhYCBCm2tTG7f2xI7wjqUfEG3hedAoqoYGoq7GWaNHiW0sMK/WPVl9C464c34HWo +RLafYBMUzzXknRsFej2hOrLiGD4VHJFlUPXDEjiyQ194rUWtmjDJ9x+0cfOTPczJ +N17QQBmIYiQGeSX9Q/1rDg== +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +E8dXbDShY+3zW/pawy6A7D9NWDBtkXfCt/ri36z9YJa8KqfJdswpb2811maQtonI +mB3I6Qx3vugXgBL+SuJDYWmPAuuK0s4V7CfYmd1uFx+gIl0nQmwrz7zGXxGxS1IC +Vo7cclA1Ux8nkd5kAV/a7XqDP9d1xr2IqDWp4sIwfXVYSpJ3b3Uv+AvVC5PLbSpW +WLZrBDJ+ktUNqvP25HjEDcwmdyKx+IYXtSdF2F0OTxq+KvyMkkhCjJDno9MKfPla +WDec0k3Tua9WFgnQXwkfgJtsFE7azzWpPTAIYYyNo/vsq82JL9wksdOpMC1Q6/Nc +ldjaRkUQ34XjBHxGGe3nUw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 16432 ) +`pragma protect data_block +p6S9Mf9ezb5qk5YXeBF0LIfOw6RxpYgFZJx5NiE5aVzqjzLHCcAfDzR+wfDEMRnH +ugRW4ejCNXHLZ3kxkHGU7cPkawbGSlG/aHdksosyhU87kn9tY5IkMzUexUHcZ9Up +dE38e6Q8nKLcRJGOycCeInYlFvAHnuYfS323Hm3KWbmRPxZaa5Um7Y5lJeZtwcgr +53fckM/1BVxrst1Ml1lVrWuBZtRn5Myc+w3rvgatUHSxt53UkyFuefOxAjgZTXxB +AywmGpNk0BBWrLp2FbWx41HfBbT1T/WtnO5kEmNMHVuMcd3e55a4R7cCOAoclg5F +ObBPt8bCZKm773oRVCyY/9peEAr4ANfBoAWQpE0WrVFmNVRQH041+hTn3up8PVxd +ul/r4suz4eKLKpP6oYaExd2bALNTQIo4zV06NWtwK8iWRzk+XGN3JE9UFFmJcuGS +thyc0zET0dcPIzGGkKNDUEC6xtQ05cMiWGLvFsNjUZMExsKJC3luxBXHLhIyrgXa +MabHH+q5qC6qD6sicrxUx6K8HN7dD9CznT9B2Fe1HQtkkGDDxZz7XTmlE/gty9c9 ++7W/0icmzGCHzGaFr4UAPleM3vYmyBEgqx0xioFPBglmKnJGll/vk9lZZHktXJdo +l878DiRwpkrITmWOt+8tmYV82pYRrnz9ELSRE1eNiI9jC3XVDG1aWw+CzrM4nFKa +xV8wao2DAK8/Jx49uox1u5eE6swZ84AWBj2VGZYWawarhrBR0OdOtQ0YwMkrHMS7 +fqifOvJreMXHEJKVi9CO4M5QlmAUZtg04f85hunzEcc/ugjlCUc5XVqJLR1NGNED +zTh6stxoAwdedJNkPje8JJVCvO97QpfrEjgY+cCYCgroNSbKUzX4n2hOayfQ2dF7 +37GKvw2hj7gQURLrogK/WLaumnfV1GHZA2hSSV9AT7p/50uC4t8QgQd5dT6VzngC +QGGE2Ey4UcAi00q5oPwoft+aE/Rih4qA61D3ab5NUHg4VKKfjS75aLwv1mO9MUtm +Yfl8TuuN1XTno9Ar/UN/8Gqgjucp52YVrzBwt2D6dhCPdH12yM/+SXr6wxb6ab8C +q3nF4jBxOKh/lL7FiqWp0ksvXBqgySjbIEmny+fQIP6eb8/IFnG99L858Disp4dq +2zqVT3t4p4H/jdcVGtE4JNl0Q0ySD78eMmf/RWA9u8TleGSjIF+uUbHJZzmpUoRL +ZzqlAHnaYcOdgD3TnA5K3B+TKq3ELgQVUyPk2a8fWGeQYOLQ1409zW+5Y5Ceqb5u +mJWsNUqzdWT6oz/XX3tAbkbQHG9Xdo0TY6nkWGOVeWmHW84qsEGNPttSKc5x1IEW +ckNnU+2bU9sYh4FWMb8wi5HemLyP8hoKJRyVnZAK2aLfylFcJn8YsODkggcyfzTW +XRQhGbwcGwDhvOXSimKvE9eNGB7q/cPfl1j+rM0PNwXN7rzCAwAydG7B/4/uYkzo +vVxUuQa0P9VxtovXYVDXvoukQae2ui5nYB4MKDBhJ0INfkIHsM6KnuU28hwZ8g9k +krUq7Ow+HSpCy5S4V2UIg6Tb99REHIQvdURLbDWKEN8RTvz9Ywm4Xlu/QoHkiXE0 +0QFSnJHC4jNW8Zvdziz1ew3VnmO2aXB1hcyTk7jLAlImJ8v8/mPfrkQZy1KScjih +UJ2Wdel8L5K+0WvLMSTL4zVOMKSiPN3uC6pJei8dxbSoyQkZYtqzBPlI0aGHwmc+ +SdveDfiYOOG9PB2q6GpTP77afyGlrnPxAeEZoRrAq7Pk5CTR5CL8ptFGjx4yZNZ5 +UtM7WwoE7BMkiaLXfJH1vI9uXA7tty3lGl+5X37+9XUG0qwZ6GsCfzD2LjBsrIzw +1bAld9npILQK9iJk5qcdzq9RnozBbCo2VwtxSTuEKTfWixXHi2kruXy8c6JrRMah +DOouewRO5ecNGhjyNFKTuMYMmQx6dXBYJt9saekpPCG4ZCDPAbWzP+qARAU3Oax0 +TIOtkYqEQ0AnL3I2YfZ8/w54ZukM6qzwU60eTv4LH3TGXE6OU6Wt/Vv9tFH2gn9o +he7jtpbE3a4I+eSSTOhvgK6Ulax0GMag/e4sDhSuyVOA/bgMGzx3CMwDHt/mYcJ6 +dqBFGoLirgSUkLpHr0czzVnW0yn8MPPmB+xgAjcKxTg1MD1V3eM4QoY4pwQmNOyG +GMTwTxdMOEFshm+0ej9Atg4zV+Rf7gtvUdbe0a2yRNnntGFfYKT+VizdazH1Pwlb +ZTEjaXdjMpJL8Qja0y71hGiIiFM3L6SYY+Yi64hy9maMT1/i3k+Vwz6wF41bbqcT +dbWrtUvOgmMpZKI8O1B+7Hpc9orW6ADHGK9qzqKnl1S1gq1oCtXDKovVr2+YEIsP +qdOz9TMgvNw5CRbScgQ/H20QZgkW+Tua834vUfFYkVS9UTTCCXFJj9I5aY7dBiR/ +EgLmvs9M3VzQ2nrVbmC07wewOmVdBy954jdqhE62P7a/HW+3dMFMTaEGt/lZRdTH +fZ34JL8jmMleq4WKyKv+yXPpaFnloKKBL5gc8eAQ1fmHIdU1t/1CcA21d20hgaN1 +Eap/h2H7Iv7tVFF1Sd8xqAecwGSuV0XEIX19x/AjhfsYJArboigxKwnosVMwcGS8 +/xIExsYrogtH1Nn0ygcpLDulm6BUG8ZiclfArGQImcV1hr4oOEz+BdU1XiEPMbpW +BNjL5X2OpqjtQ7ZdiCsX+zWWisGwpoWvV49es9VXk5seVj4WX1vyBej7NAL6AqFd +MjWWvt3feLtkm3PvWfG/jZHPt77U9WXX9Gezn6WE1BQJ4PZtuXbdlu+EuG8p8AOV +2QceQHI9nd517VAVOW9O6ytx93SSBrx3LEM6311/LeIibk2P/ZTXPLH2jCVlZC1F +fV+XW+nZm1JaZl/BZNzIaEIgqfphflTz8bXWs8Kihuhr3XhzTyiuNlffgspj+aSu +1we4AxaWpPTU9ihO+LNZMJyOHZQ0n6z8miBpkhuzDmw68OZ91lKExvVqXNr3keH2 +hhMJ1NQz2ASXC3JBKC6R6+T2F+TwkYZLoV1LMGrozgXCmeudleOdTSJ7xlPG+6Gq +b8bzZxHmpO9H5oTcNKbT4H5UncaB9PqqHfQu1amfH4/PpCimd+SKK1xKWT3IOJ0h +2jMDyzwr+a+9OBbz2zSa4WMVH/fI8gBPdOowx5dPTpsqRusasJl45lui4rVuYi8V +DdveIIhbjvTVbHb8Nvaw3oXo+fhY12KWqGQ13yYtlsEtXDhn1a8pOUlC7qVITVzU +uP5CcCMTM1tEoWrsx69CKw8KyMKJ3ngObqXr8uhog3uYlg7aMGDhumLKDiDgSat4 +rX9fJzrfq0uOeNxrKHBpujI8JKC2herwd9RDdNc8/BN0+csXNP/cpxpOplEWzCFd +6p+XIvtZJmSDTmZtRw98hSMZP8X3TLjbLAq3bBEIaES4mOVxzZS+APkDwi/tkFDY +4MBYv+htxg/OL+fxw2ZXded/mcNwBCDkBd5BTe/u29COA+Ky/KTdAa0Z7hWGhrMB +JT6FHJw8gzvuf6Ruq8quvu0526zF698y4yJgf5oaZNdvTS2Lu8o7NpVEWXUf8WzC +zjpXiRrNi1a2/O0zLcEQYN4Al4a3OgnbtgTu4tLUIAF4IP+bdglD4XMUIy7ucbxQ +BuOQ8sLRYci6HvmUv79DJcnMAacA0V9XGQT9Huk2J6ChtWfKq1x+nj+y1pG28flF +3ISmc2FNxbjOsppQW67GvEaaHG8XUtnQPtD6iqY/cFHPHXj7sLMa5f30n3RUKUNE +4IClRNMMdGW4tQIFShbIOehosQ2m81eNghHLY4M+66Ms8pdq1GncCN7qtzKKLYLc +GKQyqZbTUxeEWOZY1reAFpir7FpYdey22kylJJNqwJx804f9uHfq3pHISD/Be7hD +rIrbj/cMzkbMnyLZ3sMUdqQhdUIGz6kHbsKsS4BcT4J/qyi4XUQ0QBTU6H6ONnnf +5u182zQrsJ56CTl6GANWsFW18Zy+kNcz7pccadqq7+iMYRcv8EMDmZh0x02zpjbW +dxubV9e7V2kJ/eS0Z1T4QGheYzlfVOJBykFveBz+NEqdGvHZPw7z0u67IgJyjKNv +DXPBUxyzrAht7FDZlRcf5wLSUva4HoXSZKt6LZkqQQnhz91od9zgpwPLDvaxRpOC +cgLzQ99XL8evrrUvyKyrqN52sKreQh0ecLhNNFzwkqnBkc3pZP3AV3C41UpdW7UV +bxBJAmiRB8KbTg+h/PYcQJ+WeRcaBP1qNQqrMqgth3q7qJqEd8ptZprZUstFoB3j +9cvZPunnTYe0rePJiTy31rMo0QU4ruuQCB93Hr3vTsO7U//2eRwM8DNRfioE7jID +oUMkL4Ogqy2fvfN+5xwi9oMsSjyCMoqYJVH+JxnjJi/Ju+m4Mn9YVweBygjZ4rv4 +D1+1h5Y5YpjbixUp71WaFE7YP0PRvHVXQ8VFzRrT4+h0kxxqG+JxTWIsd2fSFw+m +8YWjHQqLuTWILmVUNmIvCg2MuK4LDhHkc1y0sKaBcnMWtiRllqXbzHbICn9lNM5u +fxOA9hBnQLHdDu2ay/ZLhBgBfs2z07coEZtUp4uXnM6o7jraoVdle+vxyTjFMPLJ +U3rogmTttDcRatYkd44RFU2psXmkiEAJgWM5vSROjFKcrezRsfhJAkZVBfHxAP8O +CmgJqpMZ3Pi89Re7OeUayTewiawCDmyzrk/RO1oWieCWj2+kzbU1E2io6t1a2BGl +1YF9VFm1IVU1Iyga/fl+RjYea/Lh0aEmjloFHzqh3Qkg6L6EIx7e25MyTFr7PY4j +rQ7y7jXDuecWXaTh87rrZc+/i0xXfm8rVTW05+SGZJix4TVwuh1eFcPwAaByBp6l +O7LOoqkso2Tlkey+hA70AMcFY0vFRbEgY8yuSBohuS4CMwg4Z0xTiNe6Js1JNOje +G1xhCenco8h9e952HlxpQqRxiBesAFDFVn8AmeBI3KfBiLrkr+icWje0Daap8fPh +zOcLnyMSJKDL/lomHbT3cSvlo8HlWV4Y4ciKbqGiqnQd2buHtNdXVZyGYZkk/RUB +kiaZl6MT0tSO4KN45/hdlK7tXj7G7mRAexzG78eq065y/gamrR2B/IdBQhOX8kyX +/zB7MHODC2rdzNQdZksL5/P8uMCU+6KYCkb7msiFxq2eCeFWutoazo0ADLwM+EOM +GGGdfcJiVsbPJxMalVkVdwLjvII1GdtdCdRLcH8JL0+K9IuWmqPSjZuIKhNvYBpw +cHtKGsC5nO9FS071Rd/w9PLPrZGgaJhjrKcv4VWm3Gh8O+cDa6QoEeOf5chb9U3R +7e58KLom48SCl1BNWXRlFKp751ixNDTkMcr3H7HE4Zsi2q3vrHk240swZ9SZcq8q +jCH5ixqQ08iGyaLAcxoe2dNki3dcULqWVbXcVHFS/YxaMIx+xTcqyP0PhT9AUjiC +4Wy6Ixvy4oEfJZB9TohDXLYTPyvxVJ3001qB7uodT55t1J0RXZVor+8mBGJmkzw1 +sVA3xQH5O/Iigr0vnICyi7SdsJDEe1hoG+orixPYdUFQ721h+mTIv4MrBP+RYYC2 +IGfma+OnrfOxa7SShvHtuzpNWM58r/7TbLADCsQwFP3bCzzzDuH8eoQkuSndsgbX +SCkpYCw4hvhcNJtrfJPqQal3OD4SC9QrfX1EN6mvFmq1+7MVWrIShwH2+OAVJmT/ +1TFfALHQwXvpY19y0lDCaIj0+4xsgpgdzDg4cpFZejAKDstaycQyxES8nCrKRaFQ +4bRY0fiobTybGM34k6QhqlsBDuZOcZRrgW3H11GMuNNKBroDCewt/U6ZH5276Bsf +nkpz6WN1a1XT7Xs9vng4wLhcNugVpooOJWjAy8QFTLMMRuaUnD9xJzptFi2ZuJkA +LvToNFqfOdRLLUt8KhVZiWYmcRxaBaCruZk6yjoZc1Yx/f5ZypTlTguHfCfAnCrJ +Uc0Okv9fFTODfargvu0WVaYgwDJZ+fE6RKwF1XfRSGeHQTxzQWRRvvrCzPIH/K4K +i9027X8CS1mpOJ+Pkemrx7aR6x8BWg4w94a1DKRAJoRVB3LnLZKEx+dJ0GNIH2+c +9BfbfabdLON2O9rFRCcvyjvjtCEkOb6iw/1lwvpzTYa046KzBiIbbKtcNSLpQ1Ao +PWyewRhxsJ3De3vZZwZkbF8GT4tIu8Iuxbsas9MNbCu3invv78UOVUCSo2NooGew +UjVF80oVnU9woatcV55xVEZjfFcgyLgA4bWLUvKzdiCu6Fk0bztDaC3DmHZWIt5y +dK2CmEbQM1cSLB+AdFmzE+oQA82K2f7wlcJTrPwB/PkFUGrsRIE6nziH3WwEd14h +KqY/r9eC+rSdtYPJZ7xMwFrwGmpLx7fMJOBoO7TJt67sfu+MCW260up3MTn96/k6 +PKKDkX4+KXk1pD/YqqRiScgoVRq3m5wuO687uAOWicpPK3YWjJkQPVQjiARLggUg +5ahTu9yvyBhfqC2vTM1CBDtDMQq4DcPr7en4ujCo+CErNTBHF0klDlAIuMkG6vA0 +HBA5pPKiM+VPZSkHVEqxVap8wR5tJJJXur9AueNtdekLqzarUCD9jyw4EzqyTBvA +nAnM6TpJ9Qjso5Ush3A1oREeWDeaUstnfr2s2xV1A/aMkNIFPdPXoDnf09iTIcen +HNAjVBlrQ97+o0wZ0mgCDYVUuYdC1tQcKdmPGKlIfRVebBFIk0liqUMhrsUVoylu +5YLC/Hq8uYV1dOZVnwlG9g1w3Af21UJ263zHFaV+v2/GwF7ID8eqvmIx7zD/xjA8 +5008d/WNCfOzMpU9l088LXs7mklZUAk0vwZRKvwb9k/fI60dusaKpc1ML7KnG3nS +sZMs8wpeinNe3rXuzv3WZgNKVnWPUaBVYBZTm3lYie0qKyJuym3trQt5V3amYsl3 +jzAbakTJrssLFs0P95NvuYRHFOArGlahpTsHFhZXFrGYcn8x7VtpTvyqQ/v90V9W +T6DP+o0XCg5eEfC3ttzKCTFAvz1u5KOuYSY/R1OLizyC2YVhkkVdVhtn0pG8gjp9 +ikFBWUn6G8g0h/qL7vzEdqjtdpAASveKdBNjYDe5VJ0+udX1DZYTivMeAWBzG3oF +82coEAJnHhU/NIByGuxSnxlABG54XH+enLgD2cNFwjkkc0aSyqFvE6JV4+g5eAKN +XmonAya/7NKIBWWadhdABHGHx2ZjZ0c/gSXWmu9H9+NmPudtT12VobfkrUbGDIH9 +OkS2AoP2K8wnf8t6a2pzwBsXvSmTDN4PSmG0NOXC14rxKbFebgNKDcWAkcidSd1P +jN4tO4W18ALBoXO9Inua/EwHO/m/wF/OBdEXo317Tn04ILOAqdkuBLtv81bFdWKU +63A/bxOLSCKyAcxHomVP624NiLQpQ2jxFwKAq6G6If4W2dqCTL8BjplBYIrK5Nzy +Me62uyvAVHFn24B/iTVS0CaA6FLG5tUj8nGQyHxEXegrnrhYVG/Xw8mXnkDvya5c +t13z89Jokf2A8gRKduqWULfPbZ6owPWfvqQPWj7fxn0mn7mBgrDrZWZN7V7LYj21 +Guqj2AAE5q4cCVQAOn067QoYS0bQGeecCHsF+/z4tH9jtXnWCIbj4XfCaQgtPHoR +Qt4Z5QoUuM8hIm9T3jnjvr8BN3ActC3zDoBnHbf+o8dijID8NlynAMGJ+N6iz7hA +Nv3UZbnyyizLDrNmahqGtUC+KkV3VATg5iLClF49S10EsO8/F0iKlniuxOaUpHhU +7cyvXkMGhohKichSmtsSiySCCCrbeYQpmatZXMA4mAeStX4EFs5ALVSQsCDfKZhM +2CETQnFqFCV+q/G7/Jr/o+Q4hVqOeeUcyARlRHc6lTbfkXGU4AP+f+JUlRRw702A +aVLJu1a6bZmqYvritHM8DmWFnSIPdK0/pxBe7tCSJk9Pm4Ild+B+X+zxqUaaJKeT +A69Z7fI1cRDTSAm9LXVZ9p7psE5AXh1seg/8uocdCbOlvmfBUrYgS4k/P0o4mac0 +gQNejL5yhR4Ea8KdVLrpX7HkP15mJPG+W0HCs15EZrPhcUUoPnWrcVDCZl8xhC/U +VD8dXPKJ9YfzL29UhlQKycVQffBTwmpIW/us4JQFOZUeASjfuZcalqR0jYxACvWw +ydnHUuAmW8VaF4p9uXSClNWukOLBmnYetCZObxbtwsGrCapQnIMTrPRBVn+KDXtE +A/uDdno45wtF8OrXEw/OFu7RdXyFpltuvVwZQ8N4ZVQ1plbJsc/NOUzpgOliC0d/ +9EHtQOTIuSwnD+de43KQGEBewf3A8MYQjO3tH0TK2Ru9WJiqUXtZYq0oYj8591KR +s1vDoRomV/e4j55BGzLEJb3Z7Ht7YBI8IhfM/aqTeldpmVe3HA3Fa9hx+/VjtRp+ +Q92iOuLmz5em5HKqDOgcUaJEqshG6Hk8LIl7lQRcpkKNnhGWbFWDxUlami/bjE1+ +7orj6c8Y6Aqxzfb1PWI8QNEjJUR9zJcScoA6uGCpFqpik8pb5xReOQ9hdgCLW8rG +e1Qe3oRgfJ8wgRMMHaddu1vCavTfjmmsz2ztjs1P/DEmxblhKG9Fnyrfx3ykfdLr +jAB7TBre3lY9/YoCNRi+qvFpwLo6GQ9IquT68j3IwLKl4PEDMBJj3SfJckr5wG/c +FalG971P8mqyhU6KbCumVarKjNJ80sfh4WIKfbFvdCNgIriJP479uYLehazEOgai +SuO7WQj3h3iteKtQNerrDiAZxEpJyWzdKC7w2xFuF8havm1LUBUCZvYMLoo+5upf +un5FKIRpA2+9sA4nq28tYwPysquZoC4yD7LzVDFtc0e4uBgplusKkD+vL2ZEiSGo +Ry5uWffF26yATqtj1rxJbCzQfyN6FWXOYHgpHIOgNTLLC+1Gec1IHyUOg9Q67ryO +sOrUSPL/lJUxHgQ8R2gO3nhuNidjJrSW5K493n3CwrWvYcmWksEBDndoCOXxETqq +jfMaD2+h4OqlSuacvc3OZefQZRiRFhmlhlC3D0aRIn1+xGOvy1PB1D4UlwSMtl0/ +2sgkTfN939UO45yp/y7bPechYFRZIqr5/SVZBw/Gt8r9sY5U0RYUVGaHdOsPEam+ +UCKqnaFUzHjlyPeZjtFLmi5PkIi3kOmlQ6gf8r7p5xUfz61tncZro/AJGnnP5Fp2 +Yw2owkJhpp+vL2pS2y15zY0jlyVor6qsYKfyMldCTkW29qKidfSEmfanUY4IhGEA +fJrVeE5vuLx4YPmUiQIRJxvIZ5LT9nvW9vZcXEkeWPa05PiUmwFtUJ4/YiX2+qYV +LBjubZJFwaiILODHT85QUlU1g+V8gN447ByIuuwdB5CagJu5R8ZtYFETc3BGBK2D +4wRvRUEJDhNpQxDVPj2rRbRBX8F3OgXchjRYA0bboCj9TZJAkhi/+RlyXF2F6z9u +Gl2lL5Lne2D4mqlHYotmDh6iqDAPBJOzf4NEPKwjWLE/3BvfmHtSaVVnMHGgT5VX +njLajYw983K4ivcdS3mAJ51UAEpKyBgkfpRjbdE5Lydkb72Np9cZVDjz0dKs+Haw +enbP2eztx0eIvVjggFCrUPSJY2xCMiyefCHhCzvX/apmpQR7xaF/Lo/uwJuSEGob +/mVil8SO2kn054007R0xthDgQyQPV+4OQprKwMYTAYWylVHl/wcscvWac3AH73Eu +8N/T0UrUkOGauloA91oelE82mBE8WdZpdWRhLToLAYEEpIRYLWHw536KJ6/Rxs0W +ytNuSSdxi1PsZf23lvF529VKEO1Rmiip9CdeAT2QDt35QUo/U4rlid5OgGxnNsNi +qnbJ30TwQv33nwSfNts7BopzzUSmN4/jF/bwiheiktkjEzh7IBqvrByaTN98qvJE +QPf7CirwALyjS8ICsnMm5FlLME2NnGJ2QvklBPhlMeVbHikjme3lzNbXNu+2yMzO +H1qkP9XoZJFub8tH+1Nc7aiGBy0LQRnuPyF/3OBnWNy83dY1pIhzV1XSmWTIXYpp +diZ24OipdP1xsSomHFWxCcyt/S6pp6a0NAqOakXx5Ww+DqdY1DzuDl0GjGql+77Z +/63OF6ohBX/c/1+AMn0uOtrrC25Q6eV5sx7llI6PU4oa1BttxDns1pTBcLjmJf5L +3NxY5tmZNtLiI20xt8XkJhfHdPiljdB3PORiCsdhGBjiRbnToAJh/gv0247mSIKU +dD9tCqdsUa6cJL/ihfiLlSiQcj+WQhSr81+4PpSK+cMgYPAqJSAtWd8sszPbC3dh +AR1HR7kRyuQ9Dz3p1/L6Yh2VNgphAdAyITAxoHciEl7ThZ3wwe1jG7+e9+8a5Hqv +H3I0iB72eyhX1xZOdgNBiYmwj3hLik3WarZOT8YrUVlUZUu+p5vSIH7V/7YYqPEg +/632DLN9hV7IdGaatFVHDZX7B89sN41qeFFYEvDe/N1EBs+HzpY+o7Susmp1fcRi +u36l1KmlQn04t+o3gZfyZufkGIVbQc67tF/U9pNyCgQLRw1AO+xgHGU7ASu6EgV0 +jlilKTyj4me7JNj8+g0SGqSgAGCKFGbCjhcObC0pgYsRmh/O6NES5NyNt1xcnLlf +EtiCfBfOJTl7griPXSU55rDhBimDN8j3Gb7+FjirLAfYKxztNTatybUSCDBlt0Mu +kXAEzhRXk2j1mv890SvbHfzHysW8hz0oq65FJcFknr0rZKojw4Nq277D5G7V4s3J +lq55UlA32eDl+c3uvuGWYIKocoIBnflLa5VyIRsP9hINuv3zeRyCwhYLTrWEiCf0 +AEO46Qu7dFcvyx6kkfC+xmxYEa88PbqVSRnLd9DHW57qEHw/VLsJvnWujGgmBcyn +VZno+u7hkBa99ePgREhkJ33ojOYZva/XGIHfDjvmUoQHmCYxgXkJnO6P7eekjoL2 +K4jDqKk7tXLv0vqIk0L3QEzZ6x49Ve9F1nTf1IgOFwMp4UgyhSqDonBwe1zimpIc +uvC5aHU1zF2hM8HxPxOfB1eHEEUANGkgGk/01ht/vkXTzST984Gz29qzJ0G7Nri/ +k4h7rECPhL56nEFrGkrVbOPkoS6W7mgRbdFSMrOSsHorblep9eQABIkZ0sKFIf3Z +7UD8GZ0t/CXQYk0WGg32MU3PeBqYSW2hX/5DfXJaxbfOOUa6TGjhZrsOMSN/DjLB +AU4hgWE/oaPoS9mE38Q8TNTnQt41pfbkq2ZzXQq747xZHAyAbkkkkAqpUlWEbcyZ +v5DTngOK7aj1gzG9lOmi8THP9vRe3xY5kToVMOJtxFnoVftakjnmvztGaNXL/5qe +6qWiCjJ0E0f/OQEP0jUZsPb3JOe6CAR5Vitft5IE3vzzmqAu/6gs6qR8vT4YRytn +4giXgvQrpfWAMj6wVQjFKv254pyxvApehEj+waH8V/5bcmTBEx+YdQG2ySJxvebk +JOMLt2RC/ak+VGZwh7lPEUSRkrkxbzSVIzU4CeoDvbtw5mfZzHalqf3nqBJaGI5o +FMGlDGZT+jP4WIayQCJznYWIHKKAWrvVPMTfj8dDej6ceY3/Ybyp+NdPdiswRBcv +m+YwWomtFXXc8khnx0VS41kAikYsoJEehaBOkz/pc9NROiGjyoce7LE0Dip+NDaC +psLvqqGA+O9byQq+C0CIIwiNt7aXatgAr7tjf/vM8ovNUIWG0iP0FOylrvmq/Br9 +tL0VgMpI075R48hDJ379uchZxLjGxtebr8V5jF7V4SWopTZ/1zj9/cSTm3h9Y6hp +5D329zHxyKEp96eJJjCLplueSoNyVGuN4sB07TR8Rz/vRPSErP3HdBaAcWz/HDTD +nNYGBaV4LfVVhbZx8lv8zOUOQ65ZPrqer4BGvXJP4s3Boi1QHno8dgrA0w4/hF+i +wXaYHP0YhEU4cEICdEI+9DJlEKZ7tRyttHc4iWYBSKORx0Bt96HlTLSYcfYHRnYO +Gia5JvSMrNdW4ti7y9vTpe25EJPf6MfH3pPZOUUiLpjeAM2u9seICdsTJ9QtswGC +/anV18Y10CeMsVZHIC7ATl+2psmWcdPlUvoM7DqG+YYpUUlU7mVxfUoA0LnGoSi4 +Th8/3MPA0PDML3IHenKlOoPEoIYwIGEij6yoWxllrkipMNuQKw5SqYzLtrCc6ae4 +jhyV2S7xys9hpJH6fG11QFSoLGKLBdvYeC2bebjZACUsk/3NaixbzvuSOj/NfoTv +QmSp1ovuWmtlMqkvnA6Pm61mswfaYC137cox69Zn/yzEG5I2fJHqtpSJmKo0kPl4 +wDOBCigBK+iqVnNS1vn6mFlCa0t3DjqKoS5IUfmhgUjWV+HmAgd44TDPL4ui6WyY +oxr6UC4fWQmP5B6qzH9raqnNHMsjM0Kh6kympgoXW31643K0zUZZvY48LvNY4Y2d +YF1v5EG0tFKQi/obbbU+kYVuKiftzeEQI1OfXNDJhgg8ld9WjrdunNYJ71onuifd +prbgxNU7mLUXYgSkeaPOXGtsepD2C2lLoB33swFjOmVo9/w9wybVwC0fYfoEtTG7 +or9Y2RZmaMDAu7RMFUOE0YZqUKnnWB/9xOG2/4/qUwt7mwL+F8s4VNTmi/czdE0m +PXutMecj6njAngbo3/7Cr4dokYQEupvEW9NCcLO1EcN7xvR4iyesuEf/dVx0dgNO +F1+m6grygC5ZjSizHMYiqYQ3M/kEkPlipKeUJVD5JkqD7ByLjmgIxXxMXvUCMW6+ +HHmhGoSeTZXhQU8lOlBWdhZYMurPsYTLHOjZu0ERgEtvBWVGgNnJVc6JjXNoIxG0 +K+dynC0NKRbRM5dVR2O0sMoealD150PArzKt+ufbykRgzohw9nTS6k+QiBHoEc6Y +RFlz+3sBXH37VfQ7/QelO9tFDH3SysrTjxZE8DRj4j6p4BGxcpFKale/rqlMTK1M +kgmXnQYCu07UX+8QUL0Li1kF9org4fU+l3hlNW1GcmrnUvw7iaidSC90dEbSfo2F +0ZXfLi8+wl2ibE6aswJWnxvSykn1U0fccAorKUSSTULmT0fXwTfyOOJQeYSc09PG +8qYw+dbLV5l5ln+f3WDWPfuFzOppTBFOeNu3bM80jy7oPS9AWClKAzmsyGJyrzJR +C/k/0RQrUTt7xPs4/aF4d1FUtgtT5CnlcY1iozh+1kmzMMaWsDLnNi4s9Cr+T2Lk +DOtVFBUPnGmWTy22r4w8Anq9U9q06JjdivMacN4cKieGVHbFdKXHGfRpqfzwOKQx +0x21KLwCwv4aQwX1EcOCV0UNKy01Hn0xUlObxZAaR1ENxlYVBZLIo84AatiS0WgQ +7VfYqAaLu6W7bAwUwpqUr0pjArp+C+bZ8ady5epUxC18Ss2GsLulX5zHogwTD5qi +J2OonxSzc3immlmKLa/zgLU1aAQWVF6vtJOGK693TVSlsRgVy5wCmC09yB9CWaL+ +MzokW4SoMsIXxrua3vdAPMowBNiPrc/xWx3iEAJUhZxHIXiyFxaigWF9m2qV+Yjx +aBMLPGXcPx3GCIPrEo9XyJzFSgDXYl8NZ6Aj+CGaoLx/4qP+8zzZKg9ApMEv6ryc +vaDtrVxQuELK8hVLPGkuu3NBLCcS6EPJU8C3bnVzLcKjl2WWuoVDOAFUjseGjbzi +hx4m9afLl2iY59UdFDgptc9cLRLNBZlyESZ+aIAmHKxfLru2UVxfcJL91sdrZsuF +i2aZp61mspvMUrCJyaT/1wN2UQvKC2d7bqX19+aL51ybXBmcR4ZX5b5o0uNVb50V +HMqiyMnEPJgXspg0HU+v/NNRrnju/m9u0w187uWAFGUSXCSD11mpX2DLLAUtust1 +uCJUXG9ebmYeO9oXj932Ji1u9fN5CBsC8zHA6+YiG/P7IHVB7ecsMjBcfujMygva +tSMm/of0Q8V4Lxz8QVa4gAS6PnbWI00z1Fo8ZrQoj8ncHXIgyW+VsSEAZ+IWMwXg +jKUOj2DgtX5/QJ9k+9Cf7UvKsOdg07zs6SRoK3usS7PNyT00FLlaX4QXfACKfLkt +zb+8mTfsXY+/nerr1XvaIcam0t9BR9+Fe3WNofP+bwBXWGSYzq1m0StaVJf2Idf5 +rdU6YriSFnuqNE4UGZwFbQvbQbFngga19/qHywCKIb9x5u+XVFeQAnX+kI1U4qsL +mYrGmxykf9AIHD4KlMfUK/ZQT9rC6cS2LpOiWm64c4kLQnfWLW1ffxdQ7QqINPbI +6bESLY8ckNX3QTs7v/RMrh1ncNa2m3WkScYKHPdfgl1q7duciwgYzeeDVjxZrQIi +AA/5AITCb93f29JyEn1mfjY877Dla3ehhWBaj2DIDTYbllQbuZ6Ndi1O/xSsA/yd +X5V4mZds4RtR3dLCYVpQpk9qQjc4xkRXj8fZbswJaQWJpvLxBaYyZwrdo/1Eg9yN +34EFaCiS2/aKRMohhp5kx0Ei2gDdN0ffjhBJF1T+PXA0weMcO9Q1Fe3aLFZPsyGT +LNqlfPLKKdSe6thUvurl1f0JJ8pYl1d0fYcZ90s22/SwYrMHGYZTVaO/7DnOHhma +mCsXGsnYCRTWowDYva11VIXMNsjb+cwNpcv1evzuch1pIkcrmO9ypY4b/XiNCyqF +7CZaJLT0Lq0tiNyDBstARxXqpQ8xyiACTgdNG573HYN+y0zhiaLSb4hTNl3ogKCE +CNm/bleEf/dFOoDY7mQ3PwHEpWX/SjcWGnGRfk9ME5F2fy4C5HJxXtYSYg9rnwUP +fFPDPe0pMyRCufL4kay77OjRoffkESAfMJHwtTtK+NSsPJPDuESPpgoaJTBtW6XZ +rQ+0ItFtmYL0XqcS3xva/t88SvblP9ELvTESynRGiySho/i48aawNQRVDk2CqdM2 +wpapRmILIR9D2ux6ony4pRKs3GW3l1IDlEAH7L3Nf+VKEoW2GTuVR87/orsAw4T4 +vtyCoP4M7x2flsjGY34oryq59ajNHgH2jHaIZGYu2wm1QUPY61SYEtNBdf1cTmu5 +TJraI+WYYncG1Xw9Ys74r5oarAq9vw0S4owfI6h9iRGPhvnVkpWFfO7ikR7ubNeY +KPgpEJ2KP4a4rSSatg3minnnfe8HDyl7WElIRQ+GAghh0Kz2dGXCQsl7WDsIAXUw +Qc5DtLwANXrad6hlM7cAgZ3vgE5Tf/88jtf6Abzgte2bNSrN9QZdxdtkPgQOFz8f +Pl4XvTxbnz8vVuf0IO0JfUxbbFOjE07stw2Dcm120x0JvdiXOvqVu5cVx3l6oqGG +OIrv2T3G0xT3Vvfi0J7PcFjmJSS6ln0yRCwh+AH/nfWrVHv75BiED1GpNMkLoAj1 +o71EZElo0YkuaHtyivcLYJ/Ti6PpBynlEaPnqXZqNDLsRHYjR+2uRHF3aXw8gFH+ +fRjTyxRK9mC2VJ7mQe+nc7yaYGQaeoFAK5NmDOh2KKm3I1PjiwhRlkdN6k+Sy7eY +CMaBbFqvtEWDtpRTlXIKZB3IBwq8vgg4fko5B8XxBftjNQa8lpEGkjNnpI4HSX4l +7Vvkk0vYafZYjW6z79rJ1CdaBr5M/vX3pK7K7HMcKC3PLjiQxCobtbMpVXl7qL5S +cY5438NtpWzMtCDh9N69xyBRM9n9SG3eIFxAxpFqobOlZXYx+skVNQctJComnrpl +d96W/Q3/C6adEa3SS7B2UUyLbek/Usej+BZW5unJKeKm7W7ExITkSOjn4yMeHzqs +RNVuJ1JfGNV95MMU6cZAPeSJiNeZQcCW6+R2pblqkF8ByQY6Q0lvhtvcSI3EUzAc +0ArOlveYXb2OV0bu+OZtijtmFV9BrSWVnCQlVAgGBiV1zw/lfLQLqDEqbwk82Io3 +00Ur0ozK2KkkF4lzJw8Lyjf4YbK7p32Tr5Uf+JVTzBKy6cXC5QImTndVoukCEXeA +6dFSugRll/VcwhJuxvyprhM/oWYEeVo0li2K/q464tY4mMufxs2NK+KXNkCLJAXr +Yyv97Tay88A13FpNkSaJjx/jdHIHheU717ggdKBqRm6WQwRe3e8gPooE2qKWQWhv +Qqa9xPc0P2UpYx8nHkL0Nc+7FCkIZSarBPoK/8VS+w4FK6uESSlcUVWbldN9g9+q +vA0fOQNRNo80I5VqvYqiX0z6JdimbYqEoUjfUBDp0WB2sz5REQAXZgohX6sZnWsV +GimfW1WKlcFCk5axKy6V0nBNBhrZ9oE7vK1SvkEa4lHr0ePvsocnYUR4jImDpVcu +uIH/utzz5KQIMhHGKwrd8pLJM8RBO3zLssTu4t2KAiX0BGsEkJbLDbEC+dXvMblH +cr1/pZX77MtjUWg8wqNQjQGTQw7NVjdmlU9wOpQ3ZCwmVttNbJlQ0TawM7gAbL54 +/5HBGPthL+/brvxd8GUyeCneyf+6QENZ/PHiElE02s5FmpLR1gADOKQ6DoI7Cin9 +FBaNHT/BG65YK8A5R6I8BtwKAN8SrDMUProXTHC65me/z4aMeqk4fuU5cvNojP7F +yH4ilCxUfr2hVmvKL/Fl5W5TakTbmeS1dR1K1Y9CSxFF8f4galdHCEQHPOZTgtQ6 +AAAufWo8O823Oa9ztyogmIy0B4ILXb+IGPw3bxTDXMoF25AMyoC8ua9jpdS43xlb +QLhPIVVPzeutcpor+HzoE8bxsTHfzUF/QqEMVtSZno6KKVpQxc+4EuME6uyVLwf8 +jOUw/GD2vEMKAiQUTFYllIX+ABmAIOcdLawNwSIqmnd/PBSIYKSqbajjFnD/N6fa +0tuK+ES0j1D92J233pniO78Av8G9+NqtVxD5xtJwhnAnCMl5Mfqxf9uCAtJ/ZoRL +ziOkxtR4uCNPYgAjAP5QWnXqM0TiLysVp1Sq/D/MdmS2SSdI4c4L0Xw6f9eVrWfT +6rgQKOKcQEwS5HRpUsaY1EW0hmDLRGXrADBqRA6RYXr7Wul6rNqC3De3P3VdcD1+ +6COoHOrZQr+R6JXyCnEQ3lt2daqge/Qks0+fH9EmuggggcmtM5udadu8BhLtTip7 +CH3Hd6HfJV61lktt8JicigA6qbP/xXjcG1fDlMEXLCHOU90gPLEiVuUTMrMUUyWb +UvOVAif80Tjc2J14zZIUigP3GvCIClhNvY5butYNucKRiKbTVt04pHWDd76cdlMq +u52cjVCjQ/t8l4XSY85eNCRAB8RRN/NVPFEp0Fx8NCRMG76e22sgb4lkHRdD3lKP +i2qxIAqVEueu18br1B881zh4ZelVc/YOJWwIG9KZvv2fDFsRFqWX1oPq4+/AG7rV +5+fuUEymXdql+yCTW1ZdxpRR/UdB2pV9AWVsOTcLKLKP8R/b3jobcG83KNl/f60J +E4TC9ds9q33renivLbGlGU/UQylvc6nFi2rOgZy2BJGgg/xczxovXQpyw2OP/RGC +drifiP2uNFTbnp0oiz2MvKUuv7xzPrFyjtIBOOxKSjEKS64CJHbQHJMxGvAkfp3v +Fz5SxlXurGapMyHsGVEwEFdA0cLxFV2cINhaTfI+1vlrQCp/OoUy2N7Vv+NHgWOz +RcVLj6Re6vdnHAnUsFqtErjW7MEwDVKvmx8h9cEx/q7hyrMo897siYrJTiV0b7Lr +x5G+gjRA+o0KL6F2ntqB5VUbuiBnJaIZzju24sIs7QcxkhPW6Hby205F/iXOGQSj +vAAnppXpgS1q7/Sn9scIPjWdofBVbXv+UHv7XDEiKrKwv0OwUrBCglWAQPSqFuPl +izisVmCl3dfaCY6xMEdIfQDj8f7JPpIyIRE7hJOduPE29TnSlFWnjCQVK0vyINVi +B12VDnMwevQBNkWwCRcDbcrxhJB/yVxyvLtJirRPY/18SqLKd6DsAkdHhO5GSeFs +Rgu9KpRtrfQHQupPOkbHIJMVpeNpB66jCXamppIedvjJ7G9umf9RGL9up8rXnx8V +xg8Is+SWV8cHbTbemaMcjsHqBkgmfMUNea6Jpq7XcQSNt5eVWXc6dmLE05X1TJ3S +OjEq1pmIsWdYAmw65Uz2/drvWukrWAmLWbW/Esuo05e1+kJyys3R3Qch8I2d+4yM +Vqkjf4/fiKbiJoiVE4LEW7hbXeNDfs99T7h8gYG6g/8Dp/V5g82I/EqD/Au0TIjf +c71Fln7pZPPJPg8bxsJgRHHVCNmWuJDoDPk40OWi68w094T05vrFbcpzsEIxCBI9 +YpbHeovMNh2wDzz/7K7Nqwy/Rfb70//zIW/KFv/2h9MHXspXpYqTwrcIREbCJoZ8 +dUPTeF2hq8cGtvkCej+cbygmTO/K5KNXEZ/8ZacpRSD2p1a6H8VFKbxTqESXfKU+ +u+g9RRzT7x7YWxdw53WF1gbFhAHhKyLGY8G8ofPY4yMTyha7YM7VNj5de+pLBBix +AKSW8SrSNckeXuPq7sizcRi/V6t8wEs7Ip5tMKNR6iNI6oD20Bm2wZh9rg5e2KsR ++vtgn99UtzXly5bGIMwjGvOPEIuN6ENYNfES9YFWmFIuNFggaAgqWWCUDbfOrW/X +lgxG1G6aPMibCm47zz7Aswc9yOjvXZeEpDyI2BaL1uSan7lcXBtw0gXVvNwJCOXw +iqGddEVwndbGxVWf2fG/f0Z0ylEVI5SFDiwQ8a01kSCT4rOMJLVlOb04YgybJ5mw +0G5B6TPAG+2YQ6ikr7Et/FBauzX1dvODGWdytnQl05toGYX1LpL3Qmr1h0yQXhBL +oyLLE4A4BZWFhSPGZXhPsfSfmcd/6Er0k/mbX0m8+HWDBb5wq3ArvbAvHCbE3+uy +eSTAyYADU6Arrnesjd4a5BoHHXQe1JwxoZ5T89GeABHLK8FbhUSdSC6fsYzGHou+ +I/n6LQhd6ALGoCLqVI1fLpC5/R5a0sfDghK6NIjqg6RtAFwRVSNl/D3Wiv9Tr7ar +1GtAVvjCgnr5UOG31RrBezrAVJHzukz8EExdq+SdPFXXilbe/FqWCCuyO0aRZB5r +HNSDpEellLw1P0iCx17c2VN30Bg3yozBb/qyeUShxjpkKgRTj56BQOOYaC9T7QX9 +o7bFD65v7BzJWGiNbWfr2BW0jjiHAxQAGB7w69H+kgqnIhtaNezFwqf5P4uIBbaW +7Y8ymlYbetHSc/rMqzmGWHxyCdui5JmUkQfWJYiXgMA30PKqcd7gmYA2hLZFI99o +hKqYV+Fc/LnTWGoqeB3uwmZF4gtIQIfT3M7heNZDixpEsZc97jEP5Fnx1Xp4DvbM +7IOZXn/Svbq8liYAhr3om3wEf/Qcxpv8d0qirlVvhBpc5D9TK82IOYTkSqJDmwzN +EI17WpRJ8qeKFP/NmHo57D9AVuypLvLqDT5rLVqbGniMNiSarfDrtHebiQywP/iD +Y/d/AYN7KaTmtNMCD7qVCz68FaohA3EID4k63j1eHbdjt0a+cOkCiu56IPotwVoK +UGdU3OnDKdkW1J4qqihhk2FQlDmvfAJ+Et3cCa4G70S/WVBYFTqmSpQs2umIwyym +ErGfjn45+d6nswjjpbPyY/ZIFy1d6t8BbFfxmwWg3XjK7nlJ9zEEx19Zz2Do/oN1 +Tbvd2SLQzL+kQWow3swT/MjT0Rb9IwrnY3ypHC36aGvBLxHpno3I7SI8YUTRjqSC +N4xLn1LF2g5Gy9iOa4flAPnJ/5B/d4V64mSwDhnc2ugFZbKTMJkCpMCNalTNi5z2 +63e/xbgEYxXA4AGl3GkRGdMhcvUjP+KptST0VoUJ1dHTdGHijz3xYHlDdL/U5iWa +qPBuGrFW+vkfV+PGlmEy4sUqutymcQtDtf19LfOMU4JvhWRhZ01G+okSktAfp87C +60ziQE+sp7a/ZaE5vtXem5MwNnGiIkdawDM+jBSN6ymiUa6fXyfcjbzmf9tjPcuX +XBfZB08SN1+dEXlx54/K+wFDd0XqMxV8lUzEl3DhDxdkrEh+H9xjmXA16ZA9CIq8 +62b2Yx+9XHMwGXc456g/pEQUJnV31ZaY4ryID7/DdIuz/pnSngRjInee4wX+yPBJ +xaygQLbPyWZcZatffnit7Vk/1462BHm3H4iCh8tD+3bfmIQRhM5IwmfLule1mKG3 +relaH0qVbYolDQtzr0i9zMna0IpwlFmwGrymbwF2qnF6sS1b9hyxx6KMcRr97IbC +7UX6SDa+dNlURyGvMEH6CSQI9/XAotZu8dCHsgCYdPzTbf8chfX2uRHd9YHwSho6 +Hab/EoDWK+koqq3OjamyHB1CdGofU5zfRwVfs6G0o/mTmOvP5R90S1t6spUGcxD7 +KAlZ1PIEMrla8r6dhUUU4ji3wWI8CV2eCg0GZ0DpPJUsU90QNwCQeE4pqnl7ezis +DsiSjd2bTrsyYa44Ws0LdhYKOBQQpdXFKKbi1duomWvP+q47IMrRIXvyUegpY7i5 +7FZoGGdDPNFejUlm/pfFT8fbndFPVh9rds+jnOPKz5XjvwPW8T1aPMvHgs2F0N4d +/TvwTGBO+/GyA8mwbOnQ5ubFLymfR3gusgerQXvb0zxdHXk9oFWuPLXcYhd7ahH8 +6PpnKAXLf2ciC3L96pQVOAQ61ftumQnVDn2CGri34renIhoDdhH7GAgmgu+xKEsC +xUMyRtLETiT2j2fQhXMwDpqXwscYbqhQTarcgJrO/jCtHRFsb38S5APRmwk78Fn1 +cTXANzrRQzcf4z37QLcKa5DyCmz4hNTleYLoWPklVnwk7Pou7rIzxhB5E6xNzWWf +eayQ7013x0gFJZ4xQ3EtyUDKkJ827FxQU+QVZoWmkLjt53i5Z9Anv9pUlX+izgob +gHQEb+1BUeh0ZPtmCznkeMTFwfXn0l7QPIpkLdAhg5AS9IqMjA/Fp9gYKsip38oa +IGSCGpm3L69u/xCAfuto3vuBwWzq8Ola3cUkPyGtPMVIAm29fv6eSYmN3lkvZXC9 +qMFtoF7ldm185oxHFQ/1GgHyZSZtd+A2ktHqsI1j6KbpfmfXrol/k8Wdq9fgsqNh +JfDWBw53z/+mJNnKiUHZApPlQuKLCLBBCF7gCDn/JYPCq7Iq4w2zQQtZznvd5vT0 +s8bq7r6++3voNP5PuAta9iizBrXyu3Afp7qWDhaIntBIb80ODjO54HNNMvFOpyWW +JrB+SYBjCtxcWMvEIi4nPKAODhLb0fauMUxB52DipQErQHgZWDcf5Hz67LrqbJ+x +UQb8j9q9yMJAYTbuZf6DZ+4khR+spi1m6C9dfvmh5K3Yv+X1USclvA64qaodpF/s +VEjSupWQoTrZH+IcThHFP6/+gwJcGC2Hg3dmoZSLT+fy6CiZfr4IweUHFdr+0kUH +MYXN653lENH5fe9bV3HqaLH0uQoCDwJL3qqe0In8pDbN4fVISPnOAewpF5J98558 +v+AMTj2UvIMIipCOCrq6Bc3LG2Zl3RbxFULNIQQ0PHsJyYVdJM4hs/C4wSYG8qrh +qoF4PacFlmo4sf2CtrqcawPMNaLjwSYTavBxubdGUS8XWFiIwGtA6neZgpu39gdP +BCT2pAWPYr5Q1AI0IUU/uGgLgUDR+IDvTqf6/Oc8pJqrbiuUpZOhY/AI3DfOXwnV +oqjcZ9MO+sbgaWL1ah34oMik+Hizaf9jY6Gg6htx7Y5MtjKUbOQ4SsSognoTmjdn +mCCyV4J7DdGHgR/VUkoghbU/qTN5rKqSJdNIYQsJZOj4U2EsS7uQn1ukE+arouDv +PaxNj5CyszH8+UUnjiP5VPxl+lLny0vlfYn8B1+3RNtQHrE1NC3AhGG0zhzetnTA +UHGCPkCudAhYRsfYnF0++r2eIjwst4ojWQEhLh3U8FxIEsVoXCarYvp6bt/ldkfO +BLZJMmAcZRO64umdvzTJ13A3esrnaxoy3ueZFNvUtPbRZUfxS17tk+vmkPAKgGSg +JZj5lV+5240xqCT9sebEKQasb0idjeDTkDyOL1J7k07eSPrn7zRd2u/st2FqvRTI +nImshMgENidTWbSi521415tdtxbVsRZhelHi9RkhlFPrJ8lfdu31tQizIm94lMd8 +LcgEM82AjktEp1f9tdHXk/tVM1S2O7acH0d3R6aoCb226xT5Q8lzRleFwXXZnUKd +ZHPg+aKAUszd2jux4LDCxg== +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +l8pSZBuUsKv4mAjlYxaEkiVDG+rJC2E24ChAvazlVAUEO33jqkTqU9mRgJBkqPoX +NHPGUDldGPqKjTPawC+OSftjFiM8lMJzjAkfksW+XarV7lA5cu+qu7v2XbxDukoK ++uhYE4/EAf/rzRsh5USNikDLA+f31pWUZVpinXRjhv/X5UQe+9w9Hm77jKdn2Uwx +V0emfy78QX+lPds+RYQJOL/zv1iBbf5zGLRrdNyKznh5Q4hQem73AFfkn91wDKYZ +OzN+WxeSeYfSzmJ3fSs83IeIOJNsgFhF5z9clPfWlGUh0CkmBV+8OGu+/3+pOfhv +DiIQj8Jx3VxwINYa+WqsqA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 42304 ) +`pragma protect data_block +qQ6LZII2teZC7M9biVeS/s4BIfyoFyRdHbSsz1i5I2cIYWMRQg9JIUFh5wFo2gYh +nryE1wWICKrHtjOOxAiWfek6kWGep5CdYiN1IPqiWeIBBWJUfZYj1dFWY94iuPr7 +MhhvWzhoreki2JUlutxW3U78BDfBycv4rcaMTHa2U+QjeB0x4RkPpQdVKevm/E4D +QrlKM+EY8H2MbzJkMUp+qQQ1ZRiPAawwv1NWKqHY+U2uTht08ekD/MXrUk+fT381 +mqLnzFuMgy8NnSBG3V6lGw+R9YQrjZnNT7aCVsApWTSmCu/lcXOT6IXL/K5+I30d +zkc2/4HOFETY/LSl5yg1dpOKLBgWDME9RuUZCr4xVDdVSTDwsfwQGY2X4echNYyu +6sYJoAxJAK35veIbYcfjsYPgqs0pcQPtywGCPZD37hbj83ZckadcFMzOTh+DTBUZ +2gc/SzeSmb04Wy7EADxsxmnK3ykiGx7n128hDcUyF/9kMQfZXmJniQPXxKYxwqcN +22I7vpOQ6TGu9JLXo1JS1sSsmLNntDrhfERlUn9Ibk/iOYwnaZEFvhcK34WuJKki +aGnd02EZe+xAz/zqi3sCmAL6XKddckG/zrK6lfpjQBKwEE58Xd7Osl5TTTrbkQAr +vxulzMo0LgaEzg1j9pc02oHnqgVglM9ev1DOWMWGZn30kUgd6D9tw+8OCFSDd++3 +rmC4SqJNzsAc88sGvTxlNFMUJsnQfPlK/oJ9yUrTh/2TkLhr42qqfT/7u5o8bPDP +jojX2ey2fXIVTTYOCvS0w29e7HztnenwMiWhwzvcdauwpxZyYFWFXYlhI7+CMxN0 +JIB32KtSPFwg5n9fitRxxA2hlsYHo1NRFhquWoY3Gj/NfWIujSXsmTFsbNfRxx16 +SqoTkcGp2X3+ALQRIEaWjC2mgrhIVTkxeS22VpBzXfZjWvdzudqOP5ksceTgphE6 +b3mE8coDLrtaiMtfBPc52ONAO1Q4snxHoFXmZTD+BtL8bVA0AN1Gy5G+5EQn/x03 +UfhORbTVXeGK0rusj0J38+cFSvcd7OhKevfMvYekSfUVlzfPGVKu/RZ7tOeMJiBd +0jfEYla8qMz1xIJHdCqDAUFr86ca3hR18RgQHQ6E5rYVIQm7ZSd0Qy+QQiwwzA12 +GkcoQ8KkJrpLNvm7qp6Supitk3IuQErxUmw5t7xYCW10aEhzkpdv+r60BC3KuCMv +fTNBODtxYFLEaWW0UnD4JIhNISV2jcGc6sHXWOyg+8otpEpryMtyEKGM84cNEOot +AKvjYj2UE1auOOPPH2rQUMcoKQrT6N+zTFDEyujCG5tMIaIo3pPmuL745KCgLrbO +J91oicPbOAcvpYQTGzoLL+WpnsB/RZeEyRdVSpAk7FZugCS0CYqbo0qM+Vm25uS8 +IKyUlR6qSoJMaHCLvbXXOkCnrdEIuMeA5syQwRJbKWfm6Xld2e1BEcWQjtwpkB/A +AW7Zcbm8vcZXcSxA3QVK0Ayt6uAks8sz8QMVcwvToO7dWOzroROsnRtzA6N9u+ke +hCpFFKw1pnN5Fs5NVRlSprAqVbL4dH5IWFKFKeJMnL9791iFGhzZPmhvfR5mOmmX +vwqyDF+cK/+S1USMIYxjs6gTattAulHhwyYpHf7jvtdJsGzQ+WubGbCmEvjp5qaT +ZuL5+y7gcFX0d0MYjy5WJj57s6bvQ4pkN4Od8HNT7ZOnt6YIxcxu4q+T6vqAc4EA +cpjL0/TtcPoCtBTjr0QquXethL+Xj4yN7vjSzBeqT6na76PSHlgzLMbf3GWBQNFk +yQKOIhybyNJguc6UhWlFCiXvaZtRJFILfx+Ks65BwLdhvjJlNFupdV6iaW7Y7SCe +ks065N5ShAwJRgAraWJWSqs7rjh/OlHsLgxy76Zskp8AbKluTQhWrxjOPDOKUYCf +bxT+XZ+hzy0evmNQ5iuu54V1WBcKiruo747uCplcOY2kQ7tdoKRHvMgYZX/0nXDp +zOkIy4w0l4rRtxms4YAlqj/0lzrdRgXHu+beG3TOe7dNvPc9BMIKpZj0BYjvfoUl +Os1HxKgYQ70vmFHe0hNsBCnicCsR0wrscMIpCBKLXqjITunV/t7k8ZefiuX6HFLU +afnq2/1gxJNIzB6Pbjg8Oeo7R8BovoJwYvtDGiexh8tApMAGrgkHM+a/Z+BlEe62 +HMH+p0PNV3j6PPqpSiIiopHvP2ENO9gVZc+khdLkl8yqSSnE/GGmZuMEP4UKTlNl +aXO9NKDuAfZAnKMmugay/EB0fskh1ZxyfSbQuAt13+ZHOjp0jQ1yd06RpHLEA5Hg +hnQGVQY3Jrf9idjvjZKD6uhEubyNzmbSAvOrnL7mdVajc3xgXSE++LfJmTIviopR +dNEWqQV0QX0sICttl1KtmLMWP38d73vkT8ENHh2XuFKyqF18fQOzdfjtIOgAft8/ +/idVwiIdYMvi1fGPlFlaKi0qCTq7IUTLCGHNbLG1kuhtP0wbD5wnIwRoi2qV2LF7 +Kbjg9RWeIh3ZT40NyJaKwm87tvYSlF6MH9F/rJLYjwoUv3XTtaX9VXwI8oun93dU +yLW8AtdyNfmKi0oEx8MCYLXl+oPdj97NwHIez5jd8Jddda79p17MxdtPAuxyVs7T +5Ee7+CqlySL3eL8ZKjP6q9TLRxDR5an2EKz8ScCW0qjWDMKTqYJ1L2AZOin+12Fi +7cxMlypolxIQb5jFbV1CimtTEhtxPnNdOJaSJ9Onc3flTNiBDWy0UvUD2pdJtI96 +mwMBC+H/jvVK5ESYyOP2a3fcn7U0DG6X0wPX5oQqXYwlatncM6BXuQg6qgyq0BX7 +Uy8Gqsk4SMswuHp1++kIkLZMylH08FQitREcfUEGKX3ykQknShXEvUlO92wEeluz +d0pt8P/Vgf6LX6J/1hzWe6X0YfcHRyxgW6dL5JEG4HDXtakbNK1khDTmBHxIri+T +iPqlOLrR1lLS6jjuWAQFAPBaq/6SZmuym7W72JuLbq5HiXdVs8/EiI4mxflziUaq +PwNznT1kcmv+mnNnGzeezddaySR35zng0KLNQIdd/nuyWTihXpxf3OJj/1QzmrnE +CDv/aCAgVTOOWq5bC6LXhcRJY+C/qmDOHxixu/8cuiFWkjyRT+Y9NkrDeJygnbOV +z5rteU1PsMf1brJn2eeqoFpwDZCi6q/JHcQZlQhydE9QWQgmQy4xBS9OlRK4Ttru +aTB0DwD57fZPp2uos/VxPdSUHpgNZs7c6d0SxD/rKML2xkoinqkINAH5zZ8o18JH +heQlWbpNRlk+caNM5jyQ0MgiaRyReCtA3ZZL+Khm83PiZrwwi+PPB8yyR39djXPC +Vi1YZhqzp1tHDRlnBBDQAG5Oj1r3FxDCkxBcaw9RiCXWNpbHJ6sY7cetcFHzO0yS +/4wp7Fn3GqZWMdOrtyV4VlAkiKUga6/tN122df3CmB1lFr+3/iSii5eVrQqAkkpc +iBD4KbM1J8JMDoNiqWrwtzcA4m2mYrk8AuOAR8pqk9hyb4l7XlS8HhFmFlYsKo5v +lvGmbsOWwZOmcq3ChD2EuwKnzS2e480oM0S+Gh9P3MD8ERFU+12RpwGqrUl4eXHi +qNbHO6hmZFOCxRwOMstLo0NB606jbZfL/bNULWy/XEN0VB2pDAcj+jDdVqQljzVY +0KNFxZAya2TeupfLlEC2hd4YyFkaedZ8XZK+YAuMpNsGfa+rG/TiBQ+dC+od7mEx +BhDdRjFDkiL1STOrCCr31WRZnYLeRw7sqQr7YIiAkuKvbQebW5roRMo7EXs3m6g2 +wyW65S+k46C3cssYb5ueUClh0vIu4VhNoFZbNye5Rd5PRe4tqU3Tu7GjBw5SoYmU +yTa0i9XqyEkAYazDquSsnxenfBkeA2zzctGp+aXl4YmsrlCWmCULtkmqY8CrCqQL +JHo7lazibktBAO5hj+HO4p0U9lcp2pJQnfIa03rrI55ENhEn3mQlEFM/EMGIzovM +Amsl6xjfdVPXgIa3K4J8rPgnt2SomXJsfL9T8vyNohYJLJOKhPft3T5PznGrNXQy +o1iKFC3h8vRhPh82FlxDWiv5ejCmS1sWOCjSCiagFGlolTo7a/gWIRWteuma8PMW +IzHifFZm9HAbCDFbUMd4fQTC7MlUajystOkAZTX4MXeGAe+pkM4rOTvgrKxMT+xl +pe/C9HCWSWgnCCXvJZ95/3jXfJm6rdDCXXR9RB8F08PdgTz84BlyyLUhxjdUCTcq +KY7bXawDrlPC58+1MC1WmFsflBI4vhsVGA3QxFYhNP+PCtqpfFZ4sor9B7c4HvtN +FCcN7cDf/bpoNK8I5uLJAaKkHdgDCRivVQfOwqqFR4Zg9idB+dvVapbsJFAv9Qt7 +3bR+dEJIkRe1DcvnmgxUHWVTxC/FI33Xf3I/OuHfeWOTyqgvVhPDnh96lPGhBnJ5 +bS+inO6qf8JdObkRB6rBd6c2lRBfGZ7C5RXeAQO9hmPVsf0Yw0AwSj70yw7p9uLH +t3QqoXBXv+migmeOzjICMWYDQDc9a7jg4WXinZ6JBROSWCZWSFLjRCf6sUXrdAbn +TErhrkx3DC0eYweiJLtwZSzciwdBUXJVjhAadps+nhT1QTiTd5MYyi2zLtsAl7zE +nSJC05TJyqOPcoYqTfqQnMCFoZCmUwqpQ2HH4yZiFQSS0TNBMlfR60rR1NbbmopU +MuT+zZFQNClu0SxXQSyNzI+QDY3AZEFcRyQ1MDrvyJn/PwM5aqRWk41XR4ynPMpl +fdbDacGwkXJS2SbxGfyb7DJoIVAiREykuLnm7Hm09o+yzdbYcdOJLY67GfKterZJ +RmUonG+jqp5qhkJvUvDP5ylQ/Y888peSqarOFZeBAzzfHqcOmIaJxrwGp4DjkWcH +gAcIF+0+JcbJ66S6OvS5cRV5wWL3vnoTNxo7V26+KirT8/VOBDIqwVgvTDJQiFEA +6X4OYjqOb/4xby3Lr0aZ1MP9Ttl8QbcOvG/n/sYKKz22N8hGktyX47LSBW1wct+k +OJ3yzqa9BcNh/XmOMYRn84XTnqQndzMpHgRKaAr/sk/ryLZfeArIKUBR8E5IUxPc +VNP7rEGuvzCS0F8h5M8IfRx9FwnWw0fL/h+ONS7Pi+WBOW9TE1zBiByYs4teTFOk +LuTLkqriX4amHGM941RKbrAresBkJd5o/kJItPKdm3NOe7PCcoBX1UtWwDz1uCo3 +y0K+g9Fk3xXetDZmzDMkFYowZgG6NBYQirJogdfz7b7XcDaAo8GPwMo6jvsRqrrK +694Nll502TsFvzDLxin9Nsrj/5wEiIQKzt3OxMj+kRjfs/qX+hSyzPvydopiApte +7q5M5+B+YLKuAtKeu7Vr8Auubx8uvV2FL5pFjyXdXWd0MOJixFfwcg2VcKc3Kx6n +Xw0DYP3uQX2Kak8D5WuYf4WD620ZhvDGdYGQE7nL0GL3LT4kBXub7FlFPFij3drg +FsVtLD8z2dYqFjK5FLZjGx+9ghGvuUi1ILtLx+4Z+8y7J/7MKJekx1pzBySrhZIo +RLzMmmRnpKcs9+XInDu3xjb7THW8EEi6ayCPOM2ltn3ejbaYGPOt9eJCmB5zHfOr +FSWI5hCIn9DeLj8C0WsNxT0VpOAPCCbrP5/rCfCUHzq1OTHnbqJIL0mqHG0OfBrO +BRy1+XApR9cmE6CiYkKlwZevWV8Xvhuu4BXc8QmY3QvO77RxxcD5BiA9bW15Ub2I +u0lnuBqPrq2ep4CRRAHFbLy0o89iBE8W3d8En4QVdM2e/1MU8K9Sl2bHHxvuE4AM +SXuYeV8ql6YyY0aS61NCddcTWh0FiYAA+3GrmSIJ/2jQnEvqIBaTxCErc2b3lAfp +YQrZHrfU82hCloWuwvY9OfJEf/vYL1S3qEWjKqg0q2aFiknIFmXaNTrUQDew707E +UFTpeIIYW6MTFCQAHVYDNv7GqjVwLNxfj8hl9q1ONtNUCMTvOIXDdMeSEDKkeVqh +aMaBI2WR2PuayHlQtJenSYH2AI5aijyQHE74kp2jJQalZSz0+sJpA0Rr99glov1q +5L3r6hGcXdJw/mZv80TWVTj+H7/AhwcSrGNx5QgBkgM9Xl4/I8rIFYCUDDawggnh +To4L8ftxdsxs47g7eui7P7tk/gfAM8UBe+SwdJZsErsdkLxrhwT+oAE84hQtG277 +URIQIkA4+Dz8UivMnsrc+/ukKF0BCq3UIoO2FIK/5G8AnI5LYnQ5zEg6eW5Ae2LL +mD/JS+cmuWb3tUgr0PTcq3ieAQRDQibx/GYa+37P7raOuNAGJGqhK7hxnp89aPSr +l1/AtK0cZLwFfRvp0MgdAAgiuEU+daa7cYtIxvPo8+Uqfs8QAwbzwt7QrSPMFoKM +ZlEaYp47O2vvxEnCqwLXyow5iOUKK5ns3pQHGdrVFl1iFjsiPiO0ND0bgNlKtytH +zH0/C6iJzu3AZk0qHyeKun5EKtwQH8r8XCoxjT+6eKU2y5p5+uSQmHHXI8yCsWK1 ++LWo4Fi5yFQacuhZNbkXqfR1WKjYjPWbpXcpDLuBGx5SnD6J4l4tr/KpJKUMCQcr +2rbdrfQaakCx/jB/28N2dp/vW58q7tuuSo5jutpxN4AtkJfhbwJuaZl0RaDWvZi0 +2ky568h0UHbrGZRSTnjdXl5IRGskBA7OZCZOprGaur+S7/avnlxpgpO93mRjJKZV +NyGND8yoAlJmhWFQEGIhp+KMqjFJHRsll4rr45U5YK1dajbtXmh8t1eapXy2DxPi +xMg9QX8sYrl6VYjfFAazPOGVn4ItSsFQQeChm50X7mgytzAhGnmWO6yO0RWOD+9H +2g0GQoz2VEhiDlRB4inB3vSdp/rGT4J/s3M1ETD+GZyB9TtYxWrzsMmgulPcOOIQ +O7TnZE8CfCC0cfwu/7wzXZ9gRguzX76Ri2tKOcAwkUKw6u7eRiwrNRv8NNBBt8ct +nZwaYy3ujkScXk1SWjHrrlVAd6TY7ZDkJoT2Hh/tMp7+eTtX5vv38IK+h7RfIEEM +ECEo34eL7bem8wXUwFgT0daz5lbr7BuInp9Kg6LAJILE+uFv2vcYCC+EyffRnMkH +ezSmQlzInAXV38UqcR2D0fceQ6pQ+OKEdPsAMIxBnxT4cY8/zHDaPjkD1tiPT3AE +gjBoxTRZVcIbGzD6zcBpADaRh7xFUnT3NRRw7K7FN2K53G+buITSny3+92mD2rty +4reIOFSI1njl8tzRaPvw7WvIsOFdngpCIUh7jDBi30I1RgrIi7mXOrb4eBd2/nwR +JOWdM7aq4jLZbTDuQtVqiWA/svc+Nbs+0NKL76S2T07sJRbzKtvN+iDLlzHT9CjF +UmOpk/R2QsSn5jdm95EFZ0t0MHAaIRH34YI4YOmUpN3CD6CUkJu6N7ksYedpOYx4 +guRJpMPIqZzBGqs2B9ApUJ1+7L+HbyCx8Ekc8HKX/afY2OT85VOWZJEq8Mxbqp3c +/PMCNar/ZR1JDUseJFxRPS0EbG9W/XYRYN6VZarfCMBOeJ06ath5UE5uIDeHrX4a +ZD0tFMlxC3kMFgYfUfSF1zVe/5+yXkGq8tFSp3bmno+rEg042IZjkvpW9Nbxpj2t +7iaDVx9rzhcEXdgOV1fD4N0pCCdioUycpp36mpdQIvB8qrJNljRSWekabj1kPcCm +d8jqQtFOrHiTH9F9lRI7NkwxiR8eECyomZZKiBqSI0dnNjEG+HlHyvsNf28zAnQe +k9M6+MZvqGT8Wh/XVCzlOohE/R/euMZlXa5Plsns/njNEEbmIbdZjohuKzs8T4pw +568z1MGuiU/pg+vdA/7Z/RquTORIyZjfuN1HZ/pDM4TYXnlrvP/A4kT6MojJHPcr +J40rHPNPPXEC9rdDV7ROjzK8iwSKZfAsPzedMshuF/5h7Y2MzAFTpWeboaJojsPj +CKSsqeuXjMWkAzjsGQsCB3jCiGCnPdVM0Z8zikn6m5NRsQGe1ELBI0HI/1bervdd +DDbcWNK5NGCXmB+SaCzE2EyP/620h67J9rVUlHo6fPRxFQi8LWDNY+W5Zjw9FRhQ +CcFro6nu5SWUSZPVCleK5tq/q/SyjbGAO5uS+KOYkSKhDFJ+uHRJjiuR8dFtnKH9 +NPfIKRchp73Y4oL9tBAvJ3rL4Yd62ty3NY9+pYRpA7MRgmJgp9MaxJeFQ0e1cRJx +Qn2mzJqjdC5SJ3FLsIpl2VcJl7Pk8RUnLMsuSJZVNdhMNby+KuuDN/fl0ialPVi6 +J4zZNlNi9A+1dDOSd1iWmqYzEcRk3iI7B4Drl0RtSqiwRTeqx3jfBGALXL2mbMLi +/+UQUoVQAutCvLptodmU01DC+xmj2Bx99kpbKKkCNFbTdDjLQj4LHUGFCu/LTpcB +Q+ruMYjL2EEAFSlKGd5aAH36Wa/mUl3v1CUYmMiJsWyGU5w4vSyvmhRfD1b0WlWG +5Gr1mKmZWS3KJtBYbDcZ5paU7vXpskcv3uQqJ0cvGuxpm0JdNPz9LyBlx4WPALI9 +Ojk9r4atwKx2UsMSQNgPnA2IzrofHB6t/LSEJuVwYTURjY8udhK+eDq7sG8g0Lym +vS9R+kAHXoFlyIed3fz2JepJPzN8vow/pwbB/1P3dr9Xxdv/jC+wUuEJ2xuB/W4w +RmwaQZ6pRnfLU0sFcDhm8/w6DWTzGXB1EYBcboSp/TY+0rt5uaQUpk4wzRP9/JAV +C1IPonqFd+CyknNXhJHGIrXJAtwpXFjAFBdhmEiSWCqn8LbE2u9SVC4MQiymntiq +BTUpqm3FjXutIBwE7HqKqaGpI7b7fy2ohA2i96b/rXRNFnv1VIq6r42mvcEdDxtY +rzsfMDQBipDEhlp3sLC5hFYr1Zd5DhG2LknilMynty7gI0BXab2+44aVijdGgTwh +o1rR3IzCTjCXPyEzPidmA07C0bDPzn4/tUOnXLQVbY6C8Ln8pnuvXDL4nyIyMaPY +lnJfI8gAPgAfjYXnWbN8oBNt52gnHykfcF59LjLSzZJbPHMWsJ+lY5+3VgxbdZD7 +iAS55x7YjQ1cnzM8IIjXd/IKoJECxjLM+yVWf1kJhEHs/fMK12f9cjkgQFw+RIuU +4aipfC2YUt/4jVR1gz0K+B7pcK97f4WNOnxZynIZQwvHa/yXexFF5lXl3lWt+Rdt +K01QcFZbkPVC2yfdt455jTx8XNjX8lgxGLl27D95/aYvay8YcODUYXtJIev14GGQ +KXYmdSKJHaYIH9AYgJQGjRA47go4qwVdz7jDCrAvCVDri+ZDHYuLe5/T6K4JPqkR +6VYIcOcWSWpqTere0yQ3xrtuCQjI5TLAZaE10EPFExIi/Dv8sRcVOfkjO/aTqoOx +ssoI7ZQPWjpSApyYBGs/uy1GGbwmv7mukfQ/nqWYS6z0Qe2obq9WrUs0bZ7MRG2T +bHRjwRjcTUEfp69PnBTu7aKZI/RGW1ttPRWEioPKzbg04Lg3KqEwp2EmQa1OM+dV +xiJ/PBWqB8gV3y0XwWHxf9lqpB2DzqVK5lOZ8SqyUFKoPu4AvwdzLGmvNa85BOdK +OIvl+8ir+tBD0tMKk1bMx8rNWJ7HgXtdvHd0G18BZwKCeiyJDiSemvJcG/KJWmhB +98ekHo3wWsPaYkHRCjD+r7I9aLGliVKbXw7Q9DQ9c+buFj+PKuaqJNnPLZuSMete +U7ZwdkNA392yvR/Zo0umDU+pX4fyy5L7yne47w9FNlCu5Ol/ydU2QV/S9UAk/Rt4 +7lMJLqL+y3OKMKIbzPsM3WLgbut7OyTa9g3K7r0wX6hwPaXlk7uipn9xSnIq6rqJ +Ps9LfwUeDyohnp6+Bn17/k2H0+OYluMQEEIpah+0Nh2zWVkGVxo4eT8cAuUGOorY +PPupVwZJkQZO1bdTSDmoe3bNTgjgu5K1mK3YDhqiXyQhaaGSvO4jfEbhSPoqHOIh +lcK4mAsaFR8zlG4KwuRIb2rNWR9NwC8+BN5TudjDuoeSvAnjHEKpqtXcJzYbopwB +fqzuwdQAXAOx48NvgBl7MYG2EjdFIUvJjFhPkzUqxQ+bb/37UFI9chsrd5vb9htd +myDT52mD7HydzY4bRaai8V4N96D7+PcZm92nKtzBzt+UBCCCcn1e2tPhDk7D2ynw +EZEjyzqV8UVnIsiZqPnZOAqlrYfItb3i00FMk1WxsQcrdKg2keat1WfXGtW5HXUJ +WC0kSQyrFAddSckTe56ccyPpmRhSNyq9k0huejTrA6HKSAmXGJsjib2u9qOpBl2u +hz2VLLdzYQV+TBOwzz7nCTY+gN2mqz1c51tA6pfp2rxkA2hkHV/RTJw3WYUpimbJ +UbnP9wzfmRBVXpFsCYlwaI3zkvXpEGNClhj1xXE8LCJgZJW18rrfeJhtjkoDQRRP +46CAuF6tz/jZu1R5Jxlyb22+yJaW2SITugCQYyBJ85mXa2HsKdPHaZnwaa0DvoiN +eaJ0by7J26hx4Rm+MuPiN6q17LxWAYIBn4W9pyAT3aO7MWdcK6N77XjnRxSUf3Au +mqk8Q9NfkcYmWyChUvxH3cezgGrYGJbJY/n1O6N+zyivxERiSM9XEOWjC3FlxOjT +aT3CeSESjCTVfD524vN9M4xoMqKVC2reTDxjmY0UqhweZurs9thX+VvdA9eQwIPC +0Hx6X5pcpNXwvKfiQDw4WGluO0fS5tEKl/kX+6FMJWo0JOJujEKMFtCXqkgvI+5/ +J84vkbyjna6+Y8c0bcshTtKBQFzWpz9++pdW1oq7QKxuSzlp8O5pclC2DdLuUoR5 +GuuUPWxNXQfFz64wELf2ZB9f5LWwFdZ+IBkFDBeZXGiKpK0JBF1uIHkc7YjcOEBy +TIYx8DXXauokWOn7cBPqWaGHh7cxMW08yazvDb7oHRmjx1sQoE/tKbdXXzQenUis +iTvVHmRy8vM9Cmu7h7Xz/XDmXAi+0LtWoPufi5+o/TCZXw31q196o9otYvMfHzQt +y8nMLtljctQ7wVCCxTXVOaoNzJF7dOLw+aSuavsP9XXdnh1zXLlYpACr++8jWxSQ +0rgqWA80x7K8slxTXClhG1XATTbyGQT0eDOmQTqAUUN/HLLGw/eAaVw5lMOS7FdK +KlfEKfp/RIWzPBwjDu638nykASD2LWjbMSBjLTtbNkcFRrVlCsNJUxZI3UatuBjC +GyKf9vESnwIiVTy8jiy5rlLSjdmuJPu/06ZiDnDihMQiJ4vYZczVp5F8JCY1q0zQ +ScNChIP0btjsH+UJyaOuRzRUqDPZZwFcs6n3jlDCKG6OPHPVRabeA/u3569/8LBM +V1tkU5SDjgl9sZP3rWZUgDsOJg6ZxE4TNfJSbcn/ePx2U1q7eih8ZiA3nfeUZtDu +/ucjW7Z7ZTnIHJlsgU7j2oezKTkHcwoAj9zdhNCrzPkfNDPrCVkrrauK4s5fGehp +D+rejXW0vKn692S5mXW8sTVneRdAUp2Xco6cikzCIHoATmYwki40uALKXycqKGms +4iBgNCuKrXNNdjDXCT/r63IWqyurvwlDha8eSe50jwkkGSF6qNzrsHRd/iSCN97N +cdQ4l1LUqYLR/kLfuu0F71ITL0QWoNLWNSu/PIguMaktz1tpGTaSKhtQBQhga1nW +p1iS+QZ0binwtJLbLDpaUOoNIXBtUG4Zqq6R8opLdNlZYe5ou3N4EbTaWkOUy2Lz +SY87Z29PqTvJVzaujtiIzDm/8Shy6e0n+AUEUrAjLnYX5tCUtxo1IFu1Kc/Mst6X +X+rz5wGXDqn1FmZc6u8sATjJ97KIvspIZGHmYf0xzJHDMOlWqtf91AdJEaWjjxeH +yEwugsNru5Id/rWoXH2wTTnMcl5WZah1XOn+AWkpHgHuMFeAf1Ual4m1dr6MjtK+ ++lJK3j9jHNDJJxLOahna/tSkSbJL3uo7CyXyoVUW/oTSNtwob8kT+MHu6bUv2n2M +waFlzEdmdRDwj4nLR9vV8xwSATAzs7Nz90UwaZUMYHC/9GlshNq/+LDDsPHcS8UP +ELfTts5VXvu8kRIVPfXghGv5vjRs4lZht47obKRyojxuatilzoy/Yf5Egb+7Iktn +IchBqS9S5U/wInYTky1aJMoWRY5K7fwtANkgIZQE5x4Dqi7MplMV+OSnZCZ57ady +x14VCHzCmhBLiw2aMBjLtW+ouFrj4JB2nkY3Z0Te3PkhHako9OBqjl6q3jI3mTBY +EfP1cMzQ+Z/xZyyc9T2bnAzTCtPOEXjsFvVctWUuecSsrif+NE3BAaf+I3tpWTtU +AgM+PBkOUYV+Igkhpx148cpZJ8KdJI/gjNFAPUQJx6xFSZOdnKbgtcB6F3TKOrR8 +9kppjlU79HaFQu84K9uzqLvCAAUMPI0/ZMzZk0P5Mm7LuyfKOHxpXlX9kG12U9h6 +/S2AUye94t1qKYi6aWoy7+QlWvBuYpF0aOEdhkc7ek+E035aEe1YCOMv/VK+H63Y +wavYlhinUDYW4AWIJdY2DuZXst3YGDxZowzS4Pe3BTNZpCQjeC5gDGMJKWX6zt81 +bhzqX3zPW0Zl5PUiq+2FYi+x4QINnQYi8yjTylt4Ixvg6vHctx8iBpw5l4T8KeUG +2iq78n/YGkvZvxeIWgqUq+a5gJZwjn/jDmyIA5N2Ny6CtNGs69/dTaIewLBTGsfy +VTdRJkbnd2KGzGCRgOppZNnK/ah2KpwAbEwLjRWU9bdk/PiVxCETvolfwl/drRDf +QKRFyN6HKX8GHkA8Yh8FWcXYtlm5kRJkidTTXYueLWFMnG5kyyo8ueRwxyjUwATz +1qeS9z1ogonGL2Hv2K817QrMup5XSGKphquRf5dKW/lgrAep4YIYHacO/KAvMksZ +TpVXYyiTFPArjmbB+T58DXSooaFKBAMf3Q52gWkXIxkNJuevu71DaU7yCNyHidPw +9EnkOQLf/5FCPG5hlQ/ma/sdQvPIDYVfTLIHrKXR4WyOMm2vNNzRBeQQk2FC6E1n +MpHgIERfxiZEUuFqC8I6ZJN9nH2CTD/jvHKboFY93XPbHFOC00IPk01SYuXpPxyo +IZJgJDTikHgw+cqskPqWdnLffxBlEgh3qo9K1zyClBe470Ccx1ckV/0xG1cPLvCt +u2YLyvn22rXzV32Xr+8F0uzEadHyab4LNNgDz3hQiFpaWCF5onyG6hTRXnlZLwiF +VS5pfUVuIEHbJWF5rrbfMg/i6j7M78W3isAUreDta1mSbuCMrM9FvpHZephmu8Sw +BGXZl4uspzG8UuIsuks567VgARRuR3frFYTikVJoBzbk0crrXqeQXqE8RZ8oYq7q +0wiHoLeSKsbMFM8bLWMT+Qsf7nCSss4mCML2b0Qb0Lm7bX3K74D3VmeSpk2Q7w5a +kaitHiTGo1+vMyy9nt2PwhmI6HWWQLWQUAArEvw1hirJ17NU2U3xNaoUTkfVT9LQ +a2MgEjCr18aT+oewQpXHgi5VwfI6PTgYhstjXRXHZYG6QRCqkZNNw4Vs4OSoUkl1 +6Cq863GRPCmqbN2XLJIqpIJYdT6o+jmUzcI65SNCZXJrc+vc2a3uQxFN2R0NS5UK +fUMWO+JkSu3HEOj9WwB36s+d4FYRf5raysD/g5OieoDHdWQgL3frAQkSwfsQxaHP +HP/swusRYnyzr6YwJqujbn8a5wDNuGcq6WsrHy8433H70QvqTN6CQjyWOid3L4Ca +AWsgBwBG2kTg+0BxBCeHg8JKyZCSn4yEF3zH5q2uAQ6/9s3v63g7NgOZDy0TqulA +2VSrMBYISjTncclm9enb4h+nZv30wwGY73q7p2yONBfpZRmmbZRAXKSRWsFlG5LA +ANHV0nFsL2jWrPNm3JKX952DuqEdPTpEaQfELPkBfxvjQuixJwoeF7W212DR+kDX +u8OQL2GUr72CcmMnt+UfGGp+ZS+K60132quvYaQ91B7ynxty/xvWSZyk+TV/m7rX +HlVAvpEYRnBstD4uWjU/cleKd5WZGdt9egy70sGzLXiNmQOq5122kgrU8qhIsfXk +7CCoeIBOqsn5q6PZAWecX0r5RyaOoovobI1PAYTnFLi5Fq+XRRzZQxGgKMMGPUPm +TDMqFVGhgoKJpuda6UJAsAtQzOecHLqbE9z2GR2xopq96MeWgYOwWYtj8RsKVaPa +hrf/eVCMQP0eDHu5V2+Wni/iV18Dsdyy8Gvg6ZnTc00E06lFzBC2UCf5AWw7NJyl +U2YNWfuriACgjLlhyeLmxVYHs7On6TIYbw5f3s/H41lMDjoCJX3IFZtvgK/J/rDe +4egUHKYTt/XMpkwI/RM+8/3V5+HFFm9OCp6YyggtDiiDvAwZfK2r791fCdj4YGDS +hzVWru0+McMFWXI4bkB4+MjbBpWHOgKob38nUghpeqV8bMsjtxidPK4tMdLShx8C +dDQzvJqbwO3Noi3gNFxpb3gwBGQShcvcAFxfv1SMU+9kOjleZ6aVR46crGG7edze +aiODodo3KJxSa7EZ25vTXbnKTkYJOWvaC63tYgEiBV8O1KhYLIDBeL7ciyuU/6Ja +qm7gep0N5f8dHBqSVrL3y18MSXsxj5Zk15Alu1pyCfIMxed+ntZsX/84G11lWweP +7JngP+b+wOvNYYThmXPU4g1TzfI4U4N3uJha5YfaF8+XGOtQ1vJOKTBFtIqquZ7q +JsXjRXdZm5wByx3JuEf9EHvM4K2lPj/knGwGRUpoPzHl9D5PpvvT00I3uJEljryh +KFQkrFm6Bj0B4s/TzIDkVUseVhhM8qaqRoKffyyPBkShZ+nw9O7eH+BgaezQeYkN +XB8nKxqUpvqQxrcR23ds/xp1mHhwz7f/I5vJMyS0w+IyBtVVqFwjY/5x5vJRZ4ux +MIcDCUzuI84qyky7OXQUxrocsH5QRv7K9aK7n/ZTuhEAdbJi3RGLf3pCR/0LYxKs +WOkaiN2dtv46wXJh4xavYYoNBPHOYSOJtnJKXWV+j06igkEmM1Z4iQJNCkM5vgtX +oDRAeNgfb/ea+WEMCG5hS8XiNSiO83OVCrtNCWBSGPmqC7cjwB2XjBXtOJYTG1J2 +WhhU3WMeL9ogI61h7nanJlNF0/onmL/9Gzh5Mw39731z8KD5/A0qFCQpYJYgvG2g +/2AGsPApU5j1Var5CA2vuSlF1j467laXApssEKQz5ekfmRNB9E3uf1f7EWKjjBXz +IFql9MPgrIe+i7EkLvj6YseXAPSdUZLkFu8vOgESEF4i8S77h5pPcpzvXFvF5Wgw +Xr5+7MPGe+QQCCgxA9YJ/i5tM25IV52IuwLDy0KB85WFtKBK2pHafwCDYaeagBqT +v/vPAnSH8Cb/Bw/EGOvgRmaThAJm2Wk9Kb63XI/bq0NDiaU9+3pKYTFMcXZT+5QC +hBDAaKE6KI3xv6VTGE6YZvniBVXFAq2aQ0JpaBXE9Rn96i2BFAZ6/L17IyYOT6i7 +7SfCuS0AccwUnrSH10NMbhiAmY1TzDm6vUjABv4CjxzflhG7WNr/3oOxwvZQUfcI +MKIuTwQ8q6JPNZFyfYtg/NO0AN6B4rFqg6P/TzkvXnRaVmYkrhDl1y4HyzkOzoQo +J0+5Amd28Zb8rl0Z29fdwzsuxAF2Ajz/+pPBB/agT7S67WT8JeawW5xGCMGjn/Vz +StISbz/5yD5WbxWc4nUg6hGuqe0K2/8QvCutV4RQJBiOwotwoHVh6wi6DNK9ABzg +5f/YmPgL3+NfHh1E8oSAAipkXYZVzx2fmiFW36sMriS6ZI6FHYzzpSFx33T22nU5 +OLDgwmGhB4sMJwGnOQfQu1hfibPRmo0L8uMAFMsNFR3AJ+VIyVFHZ156GAdAxD23 +OXmZ16mtAO+lE+1eURqmxdFPTDWE6/R6DoP/qJ4bzlCi9cTL+LwDAMjDKmocorE1 ++S9hJGsQ10WD2OAtz/S4Hzm0KsLQ896R5kp19V4aUGX3Eb/i3GzP/Ua+qke5xs01 +v63FfdQ2FMdYHipiliCfkgLVJ5lXivzzpXS66nPb2YtJosET3pou1tJg9T9T2x7d +emXGAuGWVSzfvk1QuHk7tW8pZfAS7EdyCbXa76z7VK99y6iTxg5q4/TumdUFO2fj +Rx1pBDu5OBmVGOqvkhAdSH4UqcCkfFukkxDWm16QFS7qZONvmuudR6aphy11PYCq +crotZRDeDF5Oq5YFgeUSgXCM+iAQjlarqhQxuNa5ZWwPLvAh/FZCnRwq0mdAwllu +kmBJhm+jBmPIHDbgEsnbztn/TETRI3mt/CpORvRWKhqMsITdh0UfNkQxy8RQ2qal +dRFkTonbxQTmzBeWnnT5HfHfscGU5F/Ik170Vpi077j2HJOq3cmwE6wO9d6bKhiO +g0FRdkCAM5tknttRC4xPzDQsmjPPpsLCeQdzwVbUpHVUVjw+KzTQGar/2BRzTv+J +AxqpVXSOQq13RKxVhPAa2UhGvvNOJJ/KRO6irzsTHRSfWyaAuERTM6IHNPhL47fH +Zydr9WRFGoievtFImuC8xrJCxpUZ/Lla2gMacmLWXHfo0Rzl7zThDlkOOWXvAbPe +puZVUgVhEUhYFqhpZl6Vctvnb7sciSllm29iOvezgh1uC0lIYNCvZn6qJTvluJAQ +uN7a2hJW28mkmP06G/15li/oUwpLxlpCCyh3EIL4SVqtyR4iBEU+3yQvS7/oqyiu +h2b2E37mBVBlo5mnDtEQbd4AKfp8pNi8PEh6SUHpy3++XigJsWIIUIgVDxrUdYGl +fWAbvQbk9ffKKZlqzi5hl7V05sH/qU75Nes26KkXII/oLiNiLOtv2nOaqwmEONnQ +A7R2VxlJgRV99ehXRr+fMdvKPhitl3qm28vGFFED9kszkMvuaVZNdmw5cYExiafc +4TX6cMOJi8LAbpqzh14O9sVCfKAqYdlQ2T7uKvbCzzFDdOwXlRwiuWrdzrRibo/l +atnN+G2qxHAvbTbl4LL66SP51ejCfWe06EdnYIWRHTo++gQzIQpWlFYBVzUQFEMS +k705leNl93tyoPp0GA90XUlp0NSEvc1ySd2Kl94WZZmF6A3b1GZ85KG84rflb6gU +MTtIregVOSfUfgBtRBa9yUv+rd8mPKfxieINgbB4QW2WrpMdN2mwdRczKLlNsRm3 +xihgc4jbsX+/EoduSlZ8G6I+cPE+ttudrOcHNN6hJjjpbXShFAaMkYLQSaJQWS/x +rOrEO/b5+nCwJwnFErRn8VPa5llRRprDSv/ZaN9e10PtAJx10s0yzKs3Y6WTe2fW ++AD5DZU8pzV2gtsAGzMw4RyVX+0/uFh3ZhAbmB61yTgL8GWxtZYVKD+KKcD4kZt/ +5vuG6MNx5745ocQkA20paIvxJPp5UhOzMlOfwbKiSh2zImW2lLgPizZICOMr+/Ul +CFJ+fIFS8ooxMJ4uumDiY6ed2eohN+taUFO9P+/ZL6X8TKmtgy4b60dmE4BsNQfh +alG/Pv4OKnBKnFvZnnYhgA0vICg29n19LrRTze4bIPzNP2bh7Tzw5A38SnwzVpuE +ZDEPTbBVWIOIU2kfkK0Jvn6zE8Y9Ougg4uF6KuVSfJzMmcu24P916BqI0Sa3Ciwl ++HWq7Vyj/EMgz1Il4dYX3bDuZA5qX4zUU+5rhiAv30Vj9QfC8RolxDdaEZIHT70P +uYUH3Q/fuL4OCyR953nfp4OviOupJU9P5N6CwHvmuxWmFk5p+Kib5OrYbC8Qj/YI +872ntwA+JS4rkWYREvyenhSs0m/8dBISgYoAX71gFqoD+Pk7C1FdR4PbHlFXCrL7 +xA5RNJAkDzAHU3DwQHcRtdWlGBd5QXCRZdwD37e7RthZreUWR3IrAWu+yf8G7yN+ +B+kaKkHA7Sh61StDvi9//Bd+0CsPMYKESNxyZnQfJuZlvbaFg7yFNlyRAibTNRe0 +tCrOAjHqI3tciHqMg3aUhRaOdixJTZbvGZ+PVRCmgkhXYV1LG89lzl/7/zWRiq3x +Yuhs1a+Sm6iLFEGSlIR1Xlte9ANAcd7eZBIBWaft2wbEr0WGqJEy52v5bcotbYFg +XlxW9AaYDnm41pSCv7mCJaot1q+OoU85tFuzgzLmj7/RdOguACm64HL0hgDpRYE1 +JDHpozCngCyFkxcaq/yzD+X8UIbx1qJBqxi2nK3eg3djrTBBdZ8zDITsa/aJvFMh +h8mKkYUJ6A/0LvBXNn4AADuehNosqtWEvJ3SGKnXecH3juOJ64eb/5f5IVmZudmi +xeOWvMRYBZLZwTHNbD+oEut55xz1akeUwhSmUNEv/nLsFAh8kwUJvM6dnappOM6Y +1XjkgqiFGZvRfBAXufkc5tuVsJ1DSUvMH+cvXktAcep2TEeM/qvdSTAyRvso78Me +L3w+aL21DzT5ExwOLiTF3jceBwmWp1euUpoe6LL8YZ/IZb77oLOWeYFoyajn6Uj6 +mIa4Ng1Xv77ZIy0spSwNWNvjekibw35pDpgV/0BjQtVKrqcXTSY+xiAZlDc0jCIP +/zzZAYGu/hjO0cHpmbMjd8a/JSN280SN4buseaDS8rMFGdBEaixbPv7gWXxe+k0G +9rzSlYZXv3eRyhw2uXcuGuxQqmVl73E96P34maLULRD7XiZGib+k/IINr2prak9g +IOmZ2qlHuDVgM5bN+7ChSG4OVIdptwIK/p/4VGcQnmIBlz/CjOcEzIn9oDv+2Lil +0WHE4hc+QgntKeVATT3CpbYdH18x9Twv4j/N4Pf4j1udHMuGv6US7Ey2/20L/JPj +3GjTPfPQc20g1/06zI9scJ12WCtUqGF7ReZzwO0DPc/st28TBAK1CqkcQEW+M+0Z +qFeYWUCGEjDT1QXyeDdk3mhWXIYAe3sGlIUcKv9rOr3p8ZfJihLNnh9I/dTPCO// +yb6QbItvQFFtaeKZUJiUbLpUzFpzVFvbGLlYdOJpaI9kcgBF6zF0BTUYLsB10F1L +ffycfChal7EWysMtb8RKPSonr89CAZqnruCFuelN2RYdyT9HihZGP0USAZhLUdmq +VH0VBIc+VYM1Djj9r8Gn/G2fvXjhsqiMsPhu5MLOnvdygBAsgzIzrywJD7w1Bxyj +WXUfk0Oxju0GCOXA0EI0Bsls5OGPcKOLVGj3cZimR0Jo8bYa3ZJeDJKm5gV36Msx +6J10abuDgJK2naRA92YVZBehA9kmdp6vBPCG+dfxokT9tZvFykRL59MDFL88+zMS +vqZLhgg1TGUfA+YZ1g9xUaXEq5SNxoIg+Bs0gaC4NxOJFPq3516tAwqAFbEXj71x +/H6CunqU+ZbPY+oFg/ZeyFfpuVUOUCxSlQWtfaChaVJVIWqZKIIelzrvzOadmXSg +D9OM7VJ7nbZI6nL+eRS0CvB9z2zMD+k19FVXxoBEFPUfCKK7DuKfOoo30yMp8bDA +dXOWtpg1M2XewaOxijbdNdn41PG16i4Z7zfbmI9q5KAXZNj8JboY0XE39eq06Y5K +QtmdYJTfUDl6n6arswWadymwNIZmR3EfZ3I3EpKUxT7ckwwMk9OsWPO6mHmxv9Bq +3istC4BEaBS/ibpuV2Iy63HVEZkHwLIiJTKC1mkUmVnunbv0YfevNPzuSG+ySKyZ +dEy+GDlE6piaZwwWKkUDyTbKQddmTXQ3PIvWGAsecHC4+NXXIL/G2Cn+aS3gjifT +SZMoywvejT2HJHTiD74beG+LipFuPgxms8SB36dqIqiUgLVz5mPfH0kFzqXAQkFp +WBcHFtptuqyKAow3NBTVflBIUU/aM5DEpRGgPpGJpq7ahoB6H1wQrbKdLqa3Bc86 ++hJ5z7llTARpQjsDq0fDOCJOLoIz7eBJMjKKriLuwGGhtNNUFOaXkgexshdfMn8l +AJCS+K2iHZBHoCUDay4Gqb4wJhAIQmEQBK5XlVd0idF6aIq+fv4QLe7Q14BkSmSu +FZulUdz8QS53jzk2wWuQIl8cixCDrM3tLwG01K8+FTvgnNkd9vrdW3jNnot2Bzl4 +SD3HcMOYN9y3WGsm5uLyO3+RnqE8wO6tBliGuImj8RKz8OUFwDHg+5gIeK8LuVgC +nOlng9s0msQTxOccHU83DpDvFfv1Mz2lCA1ruhgraa5kicQvobxHZSUzlgK8j41a +EVxD/FDU2yIZKeII00zB0YALZsFm6W9wljMbI3N1dVja7V/9e30Pxf1y9crGUxg/ +B0NdOWXtfVcULQYXiT49z+VtlYWiXWJll1YopFa49j24feG7FaWCSyDWH6TvVbN2 +dPFn00VSIrqumo5uUtAlSYTWb2sFo+66uopGHm2Bzni2RlE766xbdbtTWGTpF4UF +1djExoBq5CKSywTjs3URfulkWQ/VzTWWmtjnYifQHC0uV436f+GZlfXkl2W+myae +P9r839x9MLxPxRpoeoLmP2I94Q99Dg7V4pUI6bkAFzx4yoCFZSc+dd4dLR3RTDK3 +uY955PP8j+G8UMw/0DcGOk+vV1uRDZTtE0xi+uIQz42apHYBjI9aWnSwa7Z8/WcX +pfzcFdmidcJb4ivhW7fMjuMZ7d1JzY3tDZs9xMAdFJWQyYxR8B07Zm5+EAp4N9O+ +RoJdQVe2/lYygMulz5xkL8Msl8fVBY/jDD6Iz1pEo/zam5/JRNP8RPY9FtY39oB+ +kN5D+GH9k4cUxBvQD0gRCKPj0vFhky9CeSWdaOFzNyd6nr/kH9jqxVtRM3d4Upez +dGP7JZsFdMgqxGPRHp8GQp7h+dViR+DB7M+V93kn4prLPxpAWjJi1TT1DUpbCIRU +PwpaoELhAeCwDMXhcKLmLFHKlrrOunpnqlFM6v9MkSlI8MIgEG4RDRggM6jzZZut +D9zhoBn+biqpxpPDaL/yOhRRW4CXfLM355Fc4luYlHA2ISsSQFAapCVTbEIryJ9N +9MuuloQSg+ApyfwnyKXG7d8vlhvEGrYPcidv7uEzCSS1v5/AOTnNLAvXoXm8D5pz +mfZPVIx5JdwydrC+/ZpbnXCNoffo0m7GbB7ge54wIrS6INtDEVpM5uEfE5XU+W5u +xfrhJBPGPSmIzsrngILI1moTRGCw0LUwQaO4PKrogd6nyXWTIfzlarcqt7nEWkXz +PGngJjWEQhQaS3fSQhAUufzFvxBz86MoYZCr5Hj+WSbdNIcLb/PmRc2CqsCBaqo3 +cMBO1pJbaKN5kKtYx8Vz4L+a/QMYLfIuN1d+fYrluHoH+NDHcQfvCHqm3+kvbGOU +bYVKOvq+Lbk3Yzh92cdw8Nh1U045gmdHLmSpUB7tG2UipppeiDI/Gszk7H/nA+Jd +Dp3aM897ApAzkVLQo8iXB+geFtvH7icFnijpFXlH+3IYWm53uzvXRN3V5PKldAX2 +6qLovBcWc/XeimFcQpqw2nVDLUBxFOJW7cWBZWtee003GQmHYiMNHU40C9PzkkMY +K39WgrPnu72GtRRCh6R5yh9C1Wm/82F1Uo3lgYlnorOZd+g5WJ5hdQhSe8rBcHyi +j88y26aAn+q//Y0GrHUasksuIWLsWtMTbd2V8r1NAVMo7tH7svDHmBhMZWm3N6aV +U38GL9GCZJsnVwDSQ/ufNNGe5sHhG3Cwbv9SuMGwg26L7uuqYEnNq4HhlCL/91Ps +z4bXF9Izt8ghtz3Ed3B+JvDhR2cdgmHk7t4amDSLylrsR7BHm9+s92u+MfIQPFwr +MWDaSVeN4apqSllgRZ/6DL1DSQ/jwaHZ949O5djkFcc1G91ZlcHEf1h1FIPmBcfx +npRXk9BQhl1y8y9qIP2FS2s0g7fdju42Tiu9kD3KXpYsZyLGbtk1J3GKPW0Hvl/z +lZaLoIWCrKysktdktt1Oe1Xi8Yrc6mEF6jwWP7KRs/1cpQ03uBGJbA1FKaW/YnzY +jjq/Len6pV4szF0BetncFxi1U8y1oKNBa78Dof1/8a/hMez1D5ma5zI6fpVQnfaq +otZhfQrK7GVMBLeK8gmbbqIk7agAvH0/gYvXmKOXg9yLOuFfIQQnZp37HDr86kVz +YmvZTlW1H/R8wzVLLuXR8j8e85HBYjKa3davKAmdA2hpQtEizXb3nehVcH199dlk +AjULHP996tz5d3x5SvZlZ2cwm5eLW2n5vU96SAU1/Y/UaRTaN0ZJ3NxRJo5dSF3f +CSVtoxOobnyDBjuowE31PXXm37jwsZKPwOUHEkb7aSdp1E3iSfMKutu8FdslGA+J +adJb5CkXtNFLto3NjPIv9Bhq1N1VQ+Et+v0E1JeV8Je2rLvTWIUQmrXXdpgRB3KM +Kr+mkW8imKRgD5vCSY+ll8xVCHCNEsU0vTBila87mmReUxa2Z52+2Tz0VQkJTS1B +Y7rU8pFwl8ZeuF1P3BA1kE8khuNv32ul4UDqBzKysZoVgybtLdIm/G+uQV+hy9NY +B0KbK5Q61QAupO3JdCBQq6ua8vxxDbioeP4LXXD0ZCFa8IjPViAOPhMzRV8aG6n0 +BZma3KqV0fGbZE3+DBbWm73jKeTiAShkyKypUiPiyvSa1qriUvhOLVILJp41vmVW +pzcvIRXvoN9ocMQxWh8cqqC91p4ZtfpxwVpgRT/S/NgzC2BWC50uf7ZuVUuIdQ3V +mKCSFo3eGL3p8Tyn1S+h9tOFUVfCa26IKxifRpENzTqhSbGaKHNvUBIACj+x8wUI +0YQ+zFwd9kHssTDktiOVtWvHGEWVEx7hWGclY7MYe6EUJ/zxJ/lbZJe2iV0lq+Au +6O6nDHmIarASkLq6Xfkfr1Q7px24OCCiOalEFpL91Ignmaa5vD7MtKI2m4n7km2n +gGns9hG7dlHnYAaQgr4XCwqQRDeyI1ZGynEvaugFuaTzTdbaxN1Bt87NYe7fnbnk +ISNl6Pf05VqpJUiM/H+8ub+gb2AxoKg+ciVnzZDrsMu7kDbv27IGhyI+9QCPLnmt +eHKuvbUsO9E1R4L3E58Nk4S/EglabEB+SaNpzbhetp8BGD/kDN1SFQQ8977qnW/F +7gTyedThEvjUHmycgn6X+5mfCH47V2zRbLW9zpDEczie1gA9zOZMOUMBKtmwF9Sw +d+Mjpu4OsNBTq7Fo9XBU7NK9lBfsD6Fx3FVXljNIwKDG055zezsJ4m9r3oxDxex6 +YBvIfehVm70YIDJvuZnHQWKJ6rQwfWvQEw4Yw5yvGTxGLLk2tk2yi7PFRmyrMOGh +3JHfOQDRn08pNY8R0DdTJseLHK7iCdYsTT0CGLZ6eeng0U/nPDGELTXXga3hbNNf +Lugg5M4DXWQBOo3fhTLe1u9KKONDtl+C71ztzexhkt+b25YWiugLh5jEqOCBUdWE +SeeNuKs+JJM6grI4bHrlJpXTawC83obxCdIhKhfNXBVumgm8lnSPB5dY8RmXDx70 +FFud6pptxHDQkate3S0+a71ewkX7w/LW/uuCmHXIl5lBhdzmen+8OvvGl3mj1R06 +3Y6clk7NhyagIjh/TG6FfxXNJPU22yIosaqaaVOv+l1o/Bno18aZb7HL+iZRtGPz +WJ7Rbkkgc+HrgVt2gM40Rqzx6G5gfAzpxKCK3WLx26KKLJ7MCWyFASV1uX+526vG +WBoYJvz8c5yWjtXeo0KHKAzNWR8fMVhvTbiOc9dch4E9VQB6TzRSTjrX4IrWAbF5 +kVTLzDGTHW7liKbokJNCuGMyK3PCUr5c7/4FotqqOCOffH8+O4kshnGFfEJtfNM6 +NBEekFK9Uw0zLVMmQb4GsWUxFqxckUVMeuoTZvgxK1nt1tj/f57UagXXOjs46lYC +ctLTQKToQUZK8ANa+TkIsbIlFfE2VGQf3axhWDZxZk5zXcfKJKPGSQM48GeT1WK9 +i/oY/ltHc2uNY6BjwFmWG+vltiEsMO4gIOSl3zg4KckMx8zFCI+Ue0ciU8VbkHIn +G5g2DNjhkLAR3Of0Cn+ZLectZM0aym3N4HSrvJmvaYEuz832v3dMMopenYZRzu5R +8cukW/9Unso27kBIhCvFDiB1ODaD1hKA0Tuz+Cx9ST+mIsryRS//MN01tDu7GHAX +S22NPjAAhqAi/Os4EczM/BrmzvwxTBkIP5+G6df1X8ClNiVoaMCZHM3FOQzBY8FG +n17f9N0FQU9OLCMM2o4qCesEipav/8bPo0LivvwdI5Zcp84wHGHMbnMqg2YEAxR2 +Bifi9nSybmqf4o9asN0s9jkdqJvzI5TdQQARgHHqkKTmKu1BRWcFMI44w4RFmOvA +bq949NUZFcHyUUsT3vzttlIOvjbV3tEW5STZ2TNKKFsmMF0BQuMm8XqN6DSnOm2v +KNWfVF8q7HrJ39ECCsblVkDG6IZDs0hKwP1KogmDaNYzypHN/hZZ8SnoPfJVK56F +K3JxB6FSBxGyHMTdETpPBfz0c//WdL1sxRY5/Qezm2XvK98C3C7D/7dcdROtQ8M3 +oS7POAhlblMJ0lGNan7/HzrCnFgHlyKuJ+iAE9RNTaQ34NvO0zw18lyZdK475afp +Rt+BpMTsHo4TRyxu74xFPhcwZ8scaVh191q8ZjTU/pEK8/RpbqGOXNUDMRhLHEHn +gNMXWOOd+bT2E01rlAeh4POFgSUiaFAcwSDeRo8CuJk8ddg6gsxS57d/6mxzDX3O +/yarW5miUF4Q01ek+VQ58dbpyGITPycpQlPF4epLl6wyAFdWMg2dhESGcRaRUxV1 +O3fPMEqBwDFxjN7M4eYQpXa8zApYWS3SPCColubINzg4YYJhOmsNs1dw1cw6R0nL +AwWS4VKOGVzU22q+S6U9+Jc7dfIWjr2CSTKTzao0MYSQTbxDJRpz/iyVgHt462DF +kQC64hEDZ3POvkUVLh8psYdrhpSU2DkYzUeH6EN48HYD1pf4lOJQucOtD+PaGmb0 +1Lvj1Cckx1ih2KuhvqZQDfEsOy3/G/l3EWDmdQanFs8mOV9y1Jc7Bdwi+ogMwpHN +F11DoYgbRtadbF/SYtJDC5ofPyoqvmgATbVRjj9jhGlJCMqnlRbCOBm6DuTnHD3N +Pee2djKOEzCZ7j0v2iDCFe2n/YzB0T+qAE3fzHZ1AcoTBzHzN5GUkjCZwfXLj9dQ +dSYqX3U/Bm+rZFFUi8Gk07tU9WpqqeavMAWWN5rXyENTRfMb8P6KO9pvfsY0CMeM +8dhz3lPfsz/9DR6OxxFIMSEIzMAUkFVVJiPuCJcNy3ARiLkcXl/LFfSDrAJFhxP0 +G9iQQDGk5vlmPKG2mtD51F+bzArwNDsLOMt6lIfgNumiyKwKyemtQTuqzKF8NmN1 +39PewGZXcXmHlSK89kH1HN2ySlbCko+1tUX3cETZ9i/UYqL9guErrb+jzKgRHGSV +MVhMmIhjh0USYx9ekoaSGqzeK6LIu8u1VaRBuJQ0FltQ2mP68pWVZuRoKduZwdvG +Kc3nhiMIMxVKKHifhtSJjbNq/3VjbVtyVF3Yc0DClrBr3LWqSubyOMUNWQS9qC39 +j9B6aZ6kLudMe5VRz1YUm6fgCuYivbn/rvnEV0FzUy7QO26NW7MbxDJ3vxQloiWq +RzyJzpn+z1ajY2ObFrlcW2PJT31kksJwSU8K02p/U5aZFW+kgOnFk1gK0ABQawX0 +T+iWTIjGGgy4507HxEDrftvwkiezhzKaMmCwYOyAdzzFXdx4kTinVlBnMOM63HQz +l2o829YNY+xe1F9AUVTZVWBsXvabv7mof4wVFD0gHX4n+5QmRCF/Qx/c3wQFgMTm +x8lgMBVhRTI3D6aate4lB+ZHyce71VVARK6gi8USLSGkwKhlZi+C7qagmwa6PBYU +cbq3fjjByafUY2MQNAd+tBM9Ivq5oQsph83AfwJvd6571cyaSBqmWMxzqL7SqdOS +5jRPRopT2KkTKzZ+WBObZbM6gJmygVHkI5qbME5601NIPYuzW/wLaNk9zBlrHGmV +eTSMqHh2Rjzl9cIHPkL81qL/AcFW0yjIdN2jRSijXpsNiUnGjLmvdF8nwbnoRZVe +CnF8xUFg9Mbq5K40hSIPB6zfWqwn1aRXRXWgDZuoLW61jxXKN6xbQgm6Lt6iX6UI +3DD300RIUgPIL796dZNZDxueyKzMPLH7RSpsWaPYl6Zq5U3LdM7XtrzT9k2+qpON +RpaDx+cBFkk4PcRIeb4m8r8fGmQfhJuqk1sDY3BZre2ilWS5ODONaeA7T84V6Iuu +rjlAZEr6d3aYM4C99yh7jHfg+7DjmeaxPPYN/QM/WitNuXdhE9rUl812qrmFx+k0 +6jVVNaB8mrOxVeOJKgWhWk6/j4SA2rWEq6au8g0EZtmWGSOslbr7kVFru/XzGum9 +Rh4tzWgS4ZSFaXnEM8BNfwwltooOgO+HVUpjRlPB7W1/Qk9KO5iyrdr/i0q2Czjn +5GHWiK+2M6ho92aeAIMGI9dcSWujrwvX2lqMncoy+IeYDQ7CFAduKU4gKQATSOjL +vn8ygZTlSld3kOQunFzGNzIIiNYQYCSzENTyORMPtDT0Izhm9FQJnMKzc0puLjHM +nA9LvTmQFSnwTYWIWJ8X3ENU9AJ5mo/+F4nYi9Cx+1eoMkalBV2SJQsalZcD/tPI +yNK0vTMEpso/486Ujm1NSBSupjgYDF3ZxOoVeE+hk93JL2XPtbFWpduJBvjZ938s +i31Yj2NNkSLT/LXMHpGZDvR/uCPvsNsJrhu++xXt1y0/bGbsEt3q1LWQSYx/6PKo +eTD9v1zuc9k994K14OyyCBlHOWRXT8l8MU/ToORJtGH7ikVQgr3HgYMpx8BN6DLm +tIT8z8rNv/0p5yqqrxSTfHjHAL8l72p5UdLA9S2ygut91Mr+UReFFJ2dN0LgdvCw +NGsypgBmiwdC8uPjLyxYDTP+5Jtl5zeUCyrwsR5wU5QSWVIuRep2LknnYm2ThP/O +9zZYVH7kK3VMWRgazQ+HAppf6ZGfh3C4UXqSlRNWR28mbTE1sN76RVZbAy9rX9/M +hJ/0Yn3hWVzFfUpSdEDVHWU1epbMc1+cWi9ReXR9rDD2GYqTYUSCnrdQ7PyPz5qC +0nb59ZgnvIwJcO/gjp4MFKBjedlBfnAsG5e7tFe0Fku1mGEQ5jvo2g3a+pB2K7pR +7fRhEsC7ojUVM4WTvEkc5zk44g8noMAbBDo0HN6eEBVgDSckWEulZeaezy2yJuuP +UH6i7MZWAc0cDVyFxmCocM3rR9YRxh2H+ZUOXvBBGBzFjWjLE2JQe+yldG2Nhc6V +fSKH2EkTWkTNJ2dZBrBQDsgTjTa8AhashDrnXRuEsqO7mSoO6O7w3J7CqSa5VyeV +suaFWBdlfSEqF2DT1HXxVfSrZ565HH/yJ1/KiKFqjGHcM3qrYD/Yv99xzDsTNadw +NsVuycy+3L8bwjG2ughgExmQxVUN11nIZAJXVFll5vb4Lw0UgnAjRuR3CCt2t7xd +iatt5e6R7WPg/JY6J5kzaOrCynEBedrhXuchwjD1vd9Acs75JmXBdJSH0wbGp0B1 +FjStuziC5MCy5SUixsNPWSIMQVasvalbdaNr+W0gOcM8+QxVYLj9rUlOqeFMHijx +yNU5MHxJSZX2GjyopqtNR7U2x7VsxoAjOZwa6d0qDhnOVgdyhhholSqrLD3tXqbM +liFK9GtsW8tvvqi7S/0ESErx1cmVL5J0DDF5hyK+fPAXACjp0ACn3s6KGoRvRbON +CAG4FCsHtrz2PWCfy+mQqJs0dZKpTi/kQjnlYV0ZvTliO9LjPDutIPXrmoBP+dA1 +gziqmuORBjO5Xuhwf0ruBAMXM/r6qC1ge+215qj4vSB3p92r2seQ9sSO35p4xbVD +kkcx9GfsgKJ/HIK2ZETr944djgoBE6Gzta+fE0lRmzOBNOmZ32txJxCQ0V3xX4im +CtWxip8AJhvQZGj9dN+HldqG0rkwBrr1hH6aU4PXn3LoswEqtU+EMoNumSnzjHEm +yccnxilKBrH/ypF56ET+oIcXzwZC5lKQGo1GTpBzfAY5+Xq1pDIstgMHwygOhpf7 +Ykv7pN5vNFMOfB9KLtsQprGNT0txnfPdRO2dc/u9i4/rL8+0apj+Fh2tHQlijuhr +W0y71SytN4YOsL4yxJUlHywwOixUpC/IOKs5LArTsoLkQALhM/I3eZk+ZCx51VjU +gbOw7urRfUrSMeWgFG/ZV4/+tzntuOWKwLCmnZILF5cF3crD/VWYAZYYyyrSn/11 +vz2k/+C3TMeuDIN8F6ZJamH7n5CrEp7liXMeZTwDzn4pdk1flURCiEPY6r6GyG6S +R4k3HWPTCgpKuezcTHnUAzr/GNLEJjSDrcJsZ0MB/BWunrDDEqAacPsbN2bufP6c +IyQCzyGJhRoIBVwTl8XdChXlReb5D/PgiFiblFLjQ8DhonNZxATdNEn2gWm6bgky +w078SLxtLBNp5Q2htjtJL5r4HNS80uCbDQtbvYEkJnGut25f/6bKsUj9zAUH4JOc +ENFdHs+ZcJy5+97UdJHNmXQKNVOwfZv5C+8vniAsWyEAPrxJvhV2z6lHJh7i62Av +1HzayNMEBQ9c2zW4pylBpDoZr5ciG1WAdcS4sc0cC8AgNrwRC9DbxtsT3MqCkn1Z +UeCzu2BqEIBa17ubTTSHDhkXSOCvBVS0rfrKbzuzWyVKqr0byVr0gDnGyg80ARXi +qJ9VJsEa6c3tSSjnYqqIzFRxkj/kF4aTTuuIf0FtAxL5YKUzOjGmlN6MHODc4amf +InB34KsbaNCRAOa3bcZs51pKteT4cgAGCFf1Plfd12UOe+0sPzqdPp9AEvOi9p8Q +j2hwNoJXqKYhA9ewKhXAgnSSZ0jeqp/Fw6k0przlg4o34xMU0H5DUursmJAdHaTR +EvIoyny3HKqJrhw7T079DgAgcqeJkPXSNvlDjNqfj4nhEkVPxpXV5CFCG0eDTgCl +9thY9GW2zICX60kLtu2nr1Bq+nYSXnluxaWqn7AqdXMijwVz8AcvlY49H4JlJOwy +4u0ZyR9DFkwlTRzBnOg2PgnKyRi+hB1r7x81s4n2qFjbyjq+fSz/6SM6wG6Zc0Y3 +BN+yNYQPydirk9O50C8cA9RNDM07DVTQj98qeQx01Q5G95Sh7JKF2hfgAznaAYVA +geO4sdTsi1gJMITSoWeHB+HFU8kSeBWFMdBiM/jlrPkPVWvmh7o7hLnahrn5d2Te +xwt5O2StwKTEU8cXIU0FVQSKRljedfFVqfj0dUr/dlc2dGNFvLqJSc5Cg1wblFYV +1PK9ssEYbaTO0U2wq4xuN5rw685TtpAqGJX/pXSyP9SLbGd3NIbFCHEgXExQe8T7 +/x77tVADJBGpFL6jEN6rDCVSSTLMST9KgfCDpZWi8gTir+Efit9H67ExEyrZyTJx +QaKPHvrqKogTi7GHPksfnSTpQIWXVEcMgM3v/ZnDeoAqTe/bS562VyE+6osCVDbP +C7xie0/mhmdxkdQRe51+gnz9j2fUBuE4jTWCLxFGlF9UeUSkL0Kj7hVaK637Iusy +pV6az3FbBrK2PFnWDBUVlPoAu1OQihuCTKyCU7HWzN8ygPGuAAk3tv/v6VFnSre+ +lHpiYMWRfPUSEsIJWmB5BxF8tl3Bd4PBPj3gy697C25MueJnoXnUImD8x8Lbz5c2 +YVRjZbA7fafofiAM6nbdUV4pT/u68/cWsZPJ5n2iVcuW6D+vr59crOuNOGRuPsLE +blHbrcermYx9rBrmbj2ugzK/oKadDt9Ra/RBQenlNX/nv/y4Ffcja1Uqba4nLwpu +Jhn/zrKSLAVSOxHmYlUQAepjorXGkVN7CRbz1K4cvpZxMZ52QO+A39wZrRO4HYvC +mcWq94sipFzBTw4+gcbGsRuNC+UC12ZPkx8hEtHWlqzV5M5/ydWuOVaFsVWNsx5o +AOxrmJse1a9pb4G3Z1UoA1sbzcuyHfHXfs2zqQiwQFUMGNcorlxCvvnczRFVNgra +b9xGYtSbigMV5SjxUlaLQS03l7S4xllgaoM1BjkySgtAWVJ196pGHkyAC0kGKv4k +ldaX6hDuIym708ahJQQnUL0vu+X/1nb/9clgCt9pNE3OjKE8q8mhmb2kExSxFWzB +YsrMgHBNdxJlyueqcvm4Mss2gXRZTcpXpwcfPgVIiuh7znVrtdp/i3+KBjmtcTLS +YU9++yZ+A8vGbiINY79E4oxDoSsRT2R4IZZ1QyW1IBMDiili/5aMrksOWrU/H7/N +bGJrwqXtTNwmYQkn1BLpFkoNFwuNGkcKN/AeZSyfxz+bT/W4MM6VUVFmwnKRhrkC +jzSfiACgydZRjuVctMEcfMnS+my5ITjZtoS2zsfuWrYJnUPNfLxmg7P54bybEB4A +OvWaBBnP2x5EIY0MXzbucGaQX8MbqCZteUp0U0fzPxI+nA7FafGGrVOs0JhjVhg5 +xpaf/hY4uCrFqIAShlgc/tT9S/1KnbNQ3a4jyIyPjh76wTQqmStb7ghO9nFtgnds +WKF2Mna3ikwaOtWj2iOVrkCaFW/KzbYYc3KEqhTakFzVmk/CIFfHps3KntZPPV4r +LXK1+OGoMy6YBEM4fPOFqThCDl4OP/uHzMdHgtB7sodcadjVxqyvDyHhFGZKwJn8 +SCNZ99ewhu3+vM5NuMONHmAur4D6aVoSRQFPM39xk9X3R6tHICONf4rtl1OF+AIU +SRHa7aOUx4ArPuqY3WeFf343aNKnWn+Xy+8LLjprfEjP4ebnGoyQzMRk/7pUq726 +p2jIKIvvHqsxKaq/pOmbe7llUvB/e3+2uSlFQuRtrCrS0c+TMnM0LN5jnzF2tJVV +EnzVOd6edG7uHHvG5H9FqO577ogmtjfe6XOF3XtTUd+5cUEUMfWXFBLQiO190QqH +EnfovPfIBqjmKEKvgSVb2l7RD4Agc7gFZhby4PAPMhjhurFDqha516cPhbavX6Hs +bLN4ZTUoOaVJCkhh/IvvCdVCkgjyNyFFMZ9iYUWU4InSeSXfdqr+I6AMX9PEF9BW +Y5XTd4eQRzC7cI0IO0175TQNgMu3fZip/TDe2EKrRCGjyd8p+YiFsFDNIAHXa3xp +DqMjPLfdFUP3q7qO43aP7QG0DISoc6b97JIbQwwbNdIoHoeqFq2MmJ3717xPWlXS +2PcqtPFzckuThtvi/lqmL+2jxG6TrKe5uM7aFjv1Bc0gvPmxLBe72HEq2KlfEtNc +yFjsk1fcsLeqQVC4gxyzI0YweRCPbWA72NaFn9TcWovAHRVhZT1HBEYqg6ojCcG5 +Q8B4/wk43eT/sHzZDc5QBYQaXh8QcPBsfl0ai63Pj9QsfDigksVGkISlWMsx3Wkl +TH/0XjgnavFFa7wrSQbjqfK9XGpaEP6lgkIJehtPmudeZKKQmlsezxQ50vcCykUy +JC3g6GuU4Kq+BmS4zq1G8mm9ueeeBfIj3z92NK9gvYfZvwsH29UKH5LDRUu9ncwK +/HZqsQ+0RdOHKvNhfiFAR2t22mvRKCtc9hQzaE7UhAxUIO7Hx4NqEpJeL4CJEcCk +0ApYqeBvzwPKvInH5663Ql5gpiVL5i5QiBJ+U3yrUVaY2QfQTzhHL6Qq7juMh6kM +hvCK4jg3iorYwEescHUWOIcU3TaRsf8XNJpwK2RTt6qZsxSpAvN6yMFGhzYGeHCW +7EJyh6BrMlCMA/OGbQ8neOpPL7NcvQ3UusX+hWk1NrNYxmM9X4vMRCUclJoYp879 +Lmx06xE63WWYTQYV3QM2b2oRi53u+I+sEnkabhZsKNT11Gh/J9j6f6J1pYDLu1fp +znMkx8q3GfUJ6COP0nPCuMxW8oCPoz06xo8Qpg0WjY6yVbpakp8S0PQnoRTPbtLp +n82AArC00E8NSorbdPcA38d8nBwgT0W7aOxHhS2HNPOSyY3+fUAEIta6QOVIGA7S +KzyxR4m/PR85CkUxClmaPpz+0OEn9pxhyOyLw2y4DUCvd7fpzCTnjkdrQ1Gv7Eox +/gmo89UMm9MMLZGsXO5+4N+8DMIlRMtAM7fIvdxz2t+sA2uJigGhQdSlJ0XEedQq +TwHmuSmRaFVyBLny77lW8sPWel0WoB8y+9eyjB7BNd7Rq0LmPHj7rMP6bnTw97rX +X4r27hG3P9Fq7Q3mLQLi+36ZIw3eUZ61VMHfO5VbvPg5RyUrTOxPwRCy5LK7TIdi +AsZB+G3Oz+FOyCDw6fWsklGD5YTJCPwMU8f0mKUMmmu4yCKsQ0yuxUTBQVcGvzGO +XDsl80EMbiromCVU2xslR8ARPP84iROSd0ifx1xK/ssnMUaYyoT/pDpRYgonMPBO +ZJcXYivT1kPSsDvrhnE1H4entBIzSv0PPsE0M5nhrgGAD72J6yE3T01zOcYvfMSw +mThqc3/qmuCpBxCFvuoIURPtbqsFergmyXC3aHBJgqBNPS/l3/GapFT4v+eMUxmd +hijq/yclTzfFjRzFYdf1gCTw9hCNRiG8gXjZ/JhhQX1wvYG/ZYMhiusl6GL8jv4B +mF0I7OMuVx9fxCcahCZJ8B809+86jdybW+ID+EtdjNJ/YI29NSFiYuGDPH0oi0iE +UnwEb1Vhm59fDeDF3nfV/E+tZ+GkMzF51LaX4ao7CSBEsApsyq+JZ8WaQkdAb6pn +vr+pv4nfxii/JrMjnDumCxADH7EgWqoAyrDLoouPXVJSA+P4Qthyq8puComKDuBs +VrofZOAPIkXAKxdk09G8iPVZvbIHizefolodm+n1TnIwTFvhG4b+VBvz8fcozEcH +UbcjqztdzvoB3RamRX0jn25PB57t76d3xnUy/ZVpqOtt7eMtlXiJQjz+yJVr0o8x +IuCL0VcLcKUMRG1txD0EUNrHAHJI24+Q1cbuHjfUA9IcslKrcnIf6OOdcOGDkyc4 +LT6iGG8Kww7sTLp/ubz/iWXTvV7lZpamKyABYsevkNCV0qYMcvl6ihqPSAzNOkWx +z2g0VTjqOIdcRPTN+HaQ+9UhQB0kt+R5Zcib3RarHOxiCENuiCvRwOBbewxW93eA +dEKhPjlBKhWX300mea2sKHQVN9egsrw8X572T6oUmgZxpUNK4RkDI0Kmh15rUNOU +sdN3XFUNP1vPLDgyb+4SE6TzT6r6PEs0qPMKZHDS+W5bFDSC0B+3n7QNiVT3RcX7 +olwqUrRB9aAt9/P1LwK50U8tdg/ESzigx4dU86tppMqaMN+Cz4DGU54yWOyQZrwF +Oeycs8zbtSpJVuzCiiP2PddLEIjiIXB73WWK5StcpKzOKWY1rz1d+OJVvdherTBv +IwttpGkX0Hyfm8Dj1/8zJodSKwxgS+aAM2llKZCnpybAiSPgqFMWz0N0n/lRU83I +6So7mhlmtFHFmfKlQwjlTNk6zd4NrYCws3RiYhYvTFVOgXCGHr+22Hu/Tj7KzmXt +lR9MtQf8Y2tLeKeOFMgExzU1MQNMKcepOk/uq134rYzkdlM5F6+Fb0BBpSLflbg0 +LVWH2i3ih6fH6C6MX8B4qPQ5khfm9pasnnPEh5nPOYKQNbGWquPK4BDU+h1I5xkY +JvM/7xeF2pSuG8Xj+VVAx4m0J3BJSoaOFlSijAhx4xm37MY66YaJoyFvGx5sw5Hi +Qh8MV8cdiTbct9SCdng8qfIAWsIC1cQLabd3+jdaRJA+ddFN1aRqdBJk8ELox+KS +dYKg9La29D7epSP11G3wep5Y4ejSeoGFCP+DjkYR+KfQy5pAog0JCDs+fDuEGKab +oIVSj5tjCqtEN+jpkQYefdXjr8yCIPsGjBVJRVnStcpN+zlz/K5tSRRQ/kYyeSs1 +go+Vvxm2GL3vdz0xjzJ5fLcJteh+kfVLvqg9nKXAOBcif8r5OhSQ5ltJ61wrcz0x +FHzBNBvoZPe/c1WDTpFIVB4NO4CNjGeGg/Hc2flIz3RbH3MJNh6ZnHVq4sDB3eke +FGvvVX9yWTiLCyhart7tuAFZKkB1XNV5n9smzyWaKWHnMV47oLUXe+1HCcUoPv6U +u8Iyt7shxmq5p384/t9GZDg+bjecdscaaq5Ly8ywWsaUFJr6+hlOg7TyXp9Zr2h+ +pIilQQeST3hc8JR9ww+eo1HYRjNkPNnMkm4idKtkq5Ec1QlFiG2+zTxQPBMF4RYI +7jfYahS2LKs2asQPvdy3Gr8OmTawq+s9yG6/GgD7eTe5O/8BpIXjIaNj1Hc2ZhbD +zjzHWrOp15/fogWZod8doPLo0XGQqwkKQjNrytv6mACvHvJrN3chbTiI4jP9w37W +h2PCAClZvsFfLUg33WINNKzOrE2ch9XAP5aaWVjrklsyadBjvarIig2kMao/UJWO +BzBO89gpptmRXO/el2gTu1aux2KVGfjh+Rwb5RU7S/6KKQUoZmb1h50JO7Ctqh2C +7oDRxawyJ3GZkynb/CY4GcUoyFaTrSKTzfUrh6fGY7pTNLNmbYoWujuqjumGZGBB +B8L+1+e+VaLRKcar1uX50S2WMdnCfg1eh+jchiqlRx77VoDl8CHxZ9nVyMNRKqas +lU0kwgZu9RD+1FDT3413C8Z8qwttOCUpcHGF4vceamwmGcgPMyyPG8mXvfGh35x4 +E4jSxO6TRplCaX16Qk5va3yKYE+I1FJv7mJXKEGOdALr+fbRQc63T94bNnNE2ltJ +fezRFqcF0k17pTuKfmbu8pk5PUnV+VufTWGFEEp5m9jOP8noDyhDx9X7ma6neOOM +Rejbl6lSwniBZuFEWJD1gJ+JArdIl/ruSx/qQNFIqTCGUbj0M/dvpdM5z0Tj+17e +ig92gLfHYRTRI8yM7KlxnIOrJBKJMHVDzw2PHxnDQwf2OGjXkQPE5v5oAbTxut33 +HEPtUlW6akWZhNwC1PZM8giAORvUmg6jKaTgw5Z3vDS6/javm9JpBQ6yjaYKpYAT +iMErbiwxJxQ2L5BRlMtaOCwcI+4B4ciZkSti6MGH46yCvgxnd6zdUnfDY6R4raoU ++fss5/UM3a5SyW87DUIEX/lSBBKl8GYdhckbFHDDxA+gIu8kCwQMOC+h9+OGdURi +vZY+2nqjmavTnfnvzDwCnbNMbhlRpnUoaDRjnsMmO8sngTFjUqLQL19ToQIJYH9X +WmrtCHoqlzMA4jyDINlP5MR1jY/OGxplEZh920YrAJKYQuBWEq4bZhI1iXhMHK8Q +8C/R5u8MDb0eL6SFoSN9AgIF7ZYLUP1A5NZetjL9cieQUc24JFKLacVj05IVX0si +XAz3PDqwGVIgGCex19d1WHy3bduRUOF0VNC5g/CevDv9Ow+JVS1hF65b9DU1gnZa +vvUZRovSO3F2x42EKD31Mv2TG48MbB6X/WC+4NhTpoQsgF3O7AoYirLjbj66G1Nf +tSMOYv8sehLDVmS4JO+IyhULQfYQKlwg2NIU+f3n9EA5skl8i0HRiRLt3g32v6wy +jenJFcIAt5eTvXZTcq+cIW0IcVisoCzwkZRTn2TThVIQTYo0MSflzT5J/0agaNVA +zAMV9bGCvNf6h+pZhSdKa3TWInXwPZyiHRwH6pxfJ1pIc9b0bfr6u/+IZchkpCfc +OUmPIaplaegyNM+bxdqO7cpzH8SMG3lgsuoUhSlAboaWczJJeu+PDli5ogLapewH +14UCRCZxMGMxp4UO1W3LPU3s6XrVJqsXSY3W8fhXBuO9l4amgVd9QCjRQlhF3Nzb +bzlZ5KQGm5Z5uGOKZcOnTmbvgB351Ld2sfKgkxp4fuHYsPXqStzTCdrAif/0ECMM +oDM++8LQgjkVATyCZ6UY1Tgb2oG+X0NSB1pUu+ZxKw9fH3Rgs7+MZtxHpxDtcstg +pcVpNbXVmB0JFp2K9DddhHzeKP+AEClYoyUREtaboMRUFw3zpiIbE8chpHl4w3OY +7i1O3Kz/+653hHGhjBUBoccjAS6BCHnD89CWwXQEy3zA9GI9MdyscKCNs+UOLCZ/ +1yoa22/5q+clXlylWjcc6Bgruws27jST2spmbgYJUcPqyr7Dz/qvZJk6YOpmTGfV +cw4+BrcaPObQKAT1mZilYmfYboVrGo20x7rm/w78uc/HP8gC1G65giI84+pdE4VD +Ey2Rkg3ufyNsEnj6A7+ow2aAJd3071WmNl9nKxE7Z/SHlkdw/77NEg2jLfdBEbmf +BrKIKFfJhm+sOE1dpSjS1AtsvdUkoDp9A7JF27uFiTPQidBK7P442L12PHXbQNL9 +ghD8EnKziTxwog4Pyghe6zXM4cFsFchfupkDXBeFM4W9aASXWQlBhBkVQO2Yfw80 +oa1K1SsTjm4btM1q7xpbZvXHtv06OddER9wJ4P+j9dX3FK8cQzwgvY8snQsNsczD +xK2GZ+lFfghnfEkY1wdxXmAiXw4AYW0AfNAT+JQE7rzB4620LEShmip94oYozfMq +95HbmuAcYQFVMHo46dfUDZfB3VBHyDUC3SKYBFmKOsAMD+vZxGiIzIASJGsKoqcg +/vJanQWz19/PJEI6enP05LLu7/WqUvJTZ64lZqGjA2m/KiS0klIocS8u7rkSx/d5 +ObbsV/hLch7/WBadwWDq1i5NsfBlUaMiFnQjfk8/rt5Op2OjTeR8iugWEdoboP5S +GbJVhN+vUpG6BS3M5cc61IIaRvAI8YPfYLI7OLTPHluhUoIaX7HbxYh+7RvTgYRQ +weJkN09tgOtaWmNs3fulyD8qnsgsy3qRUcX7Kbptjn5D2YGShO/jIn+i5CmHEnf3 +KJ2oiSAnzyF5xbHm7NeUCgxpmUR1f1AgS1morPvIXHkD+dBIwuCIevvuU15rXVWf +b2PWSc3uZM7m9Mrd2dzM9KHvYSBUY2fplX+DqR2EzUZAMKKFvMUocURztZjVJv85 +gbVJOKwOCJW2AJdQhdo+Nms4mazpUrLOx9mAoqYfe8rJLr193L2q0m7Vuagm16aD +qeNsiG2t7Pn/n4k6gJkeIfnX3Jvd9gVpUij1dO2UfbU/GJ54sdtUbD5vB5ZhvLtd +phJHpAmqkvNSeHNpCsGRNjc7iZVycV8IlXyjihhB1cN2e6gy34NRojhLKOix0HMB +MKhAKv2hRVY7R/hco/cKe70HJjZeO02Wkdga3XD51hF7c9LAjD5bM+E2uYqux+iX +XpDicfuwjcBHWy41KWIzySTPoK1MYWbQCp9uxxvMyDKlXcwgWOeE+E6qkHapgFtc +lLkDxzLP4smL6KciC+kHSqiNfXw2F6a342kwrCTJOnfzK0E6vghGOreX9CnuaopH +/G6Cuf/Uoym6Pij1OvzNMg7ARBYptHs+qIH4jbwjRk8PE0PzfFvlju9PXPrWtTBb +v1mZ4nGcf/h5652YkztPDzPtfcZOqzbmOKgHRtBrYXCVlIgihzjOxaXdkzZkO7rc +XqDtGKdVX82nC7UCHEGHnAnUg9CzbuB2NqnhOsJ5+dxMxqZVO8oqFHRDzslilVED +F5hW0DwQTQ0XqVCjfMJdnBqlGYbELhLHe+MUKQpUaIREfSR3JbDv9MJVp1GxpCtr +W8wiBRvY2qdfHIxdnvmNIxIxMnEuEL7AxLBZ86ADJcPcnddLnghB6wyjvQzTKgph +jPvs1rn6vSV8X3e0cqsK3O4/A7UTtM4Y1m5a1A8GVSA2VqnlQGj8tYV5JpYSw8e0 +Js2zURg2CONPlHhTy5FscKBjdNWC00wK+zdX3gYF5OA3QseZsTLSYV+JMRGTRn8t +pWT9yVncEWc+zezNfH6TN0NQ9aB5NtE1Y3MilBg/ovmdte38HeWzTqigK7hQOcsP +KE1bN05ZfIHtk5MImSWzg+AnbMYv5mtd0EfltVudZFJSjUoc3ju92TFnQyr6/85u +0S4IlygiQPTla+22rXJ1Co1QniqcvwapDU+HZI/CmdpNhSS6W2jKrjifqKGsXUEb +WvzZ53KcuEJEL3nyg6G9512pOohtOKRKsccO+gfvX1gViSr5Y3earDSx76pUmsvJ +PoSz70Nd/1dJFkbXKpg6WIhBTbOSvc1SFr85M8dOUnaz5E9QkmddPVAXe4kc2syz +8oX5gSBYcS5lFsV89nbaxzoqex/+xacgSU2LId9AuwYGsn3MyqNMDuiITZ6FVVXR +mAoQ/3HAM8TB7jzqTIlV1A1nv8Oxv2mpHdjtoqgXNZH4PLMptMUlcbQsskOD0ATs +DGVNWCCnZcblzK0LhsVfdICOm1zIOAN7tKha82zwn3zNtsjr8suhdDZtQuzw+n3k +TGiLrMLxgCHOKQieSyPyQyZOjxn+X0B30PUS/sMlFd4DKmqfKwunkh+gjaBKeQc7 +nQXhcdXXtvSoF/SKFgiJstnjj+QuwsGPsYGL50gV+PdQGvwG7zvK+h3MHod5ZtRQ +uRXjwFUOJaMTwqsB+SxZP4+xx2WP+7TK6TqqgcIhy1oK8TnOCRXP3EQ7xHFjxcb4 +WAUCW0mukweAKdLnAbz3GBHjRQeXpyALAPbTC1Ifeq48lqWxAMJe2lzP+tq31RUp +g4hK8xq9q6QT5U9EHxrrNPNrkREOl8oS3A0dVD+gJYkVFZWXLGBkHTUKAeSePGQm +DSHXRNMyjZhmbGQR4meIh4zv0VrRFE7DN94BnP8zSzKdkEwJ34VLQ8SiIkSQcceQ +OoCuw2efSAYc38aVyGfS5m5yqw59MtPXsoFYwg1aQyv8oZHS86bUwPEH2tFAWS8s +bpARSZC8r+JxF5/d5+zNPwR2Vf3J+9hNksMvGRAUF9Bmy2exgAJ4Ct1/Nn79Sx9h +QC1hGFy+0uNxvPv568Rh7cF+WNIJE1CFkk1fdLkC568OvZrgWZHSNKrAo0iNtsXV +vGOGBJW1NzPkLKSTMyUb/mfSQzNy4gMd6LAGu17NEJmN+j5udMHzI4rhJaFSga95 +IgWTLSsZ3DvYNOdnlHupjnfM/y9NvxSzr2gHCP7l5UtULDOrStd6ZNgdhxLneaEN +yEbS5h+lNZJEK7jrxcSLeZJ9VlHpsXWDK5YHYwbN3tk5rzANQGJtL2yn2VBznDv/ +XewzukFkKRi0gw4J55rGVtG2ubutJQJWCHS8+Ri3m+6yqN4HystdkeDVjAvtz1V/ +jkM85GnWiXa/HNa2KQJP4H9jfpz9aU7bytk0ju6FPfnVphzVOnaH8yFdLkMnqQBM +Z6LuLQtkhj9Hq3YkWKSigJ48kHJCjpVhnPxpjEjHY9yUJg8AVG62TWDt5lAJOiBa +lYcQjcGex9vboKndYGW+UBwPW2sRFIu+kwnoOcT/eHKyBghREw63BV/sBCLjC6DR +qRjJ0V+s3UzXiswHLesWl30eOZKt45CtpxY0OveZyDhdj1XBEMlddU+AKPb5Ga4P +A1uFWM2MXUBP2Nk9+unaeA48bSQZrER9BGss+OrBbnedR6BYRZ0qt6+dy+Vf9RcS +TXxFkWLN3HzyMcGSpF1XtXtmrhRLQZTUKop0L3iS/nRC8s6dXHTTbhWuTXWAaUwv +SKjH6BtK3LGE7oKh7X8nQL3PQNiC/Eph1z0a5cY8TY5zqnuudbAIieIQGlTsNg5D +kQiCc6/IBikNODUkK6r7wlZo3qZZHxmNyPYReqYRUHLHmMcVSslZJR8f0paCbkQD +YqWE8D9fZWRz9jN1CtEFKPu6ysHmXGQp29mPeONXzcZmJvN3XOJFEpgkWRvUPUDG +8tfy1w7huRTf0YTFQdykpuOylIkN1QaNGV/aU5yDyAE4BRvpG+jPvWmJuPp1Egt4 +Qv4gM3lm6WxFVDrdPUaHJwcLMSTiqkVzwQBGQ4DURDWZ9ytQoFKxXbnGcTnqfS7a +Dqzvs4uUNbvzDSSzQCKJtxQv+aukvOLCL3/i7V0P6kszFH7aEYDiwUVZHK27tRoT +npD9RxVz13srStNUovBvWJoddaKztaXmgVNfVSs3M5ZLU2SK3yt6rMi7nqwsiSng +8ZUqaZspWnmI2qqVxgs8JT16d0hyNMssnspw9NpR3iiWOKw/Hhtx9lzWs0r+i66P +VgKcdWBKPZP8Avrygg6u3Ruum6YPRZqn05kod6X/6NFBz9V0ag9UA1JAIwoTqGm0 +yhnZpkZjckX5LN4ROQ+4hCzSvlW7Wn7Sz+6fFatxqtnewm8l5B5IyGYtvOcDgUqo +tfQog0DBAkmmEggTZAeTjpzCHq0p3pTmbkySZvElTxzFnGB4sfzhjm/pbzJvqDfs +aq/plcaIDPojObUhq3Z/qYtdYK5zKAI8pKUGswXrOyKk4WweCQad5AXdDxe4txSk +DPbozpeV7oqvEmx6lk8jvNPl9IF3PCkZOZcNLKXdMmi7SFJnGty+aK4svj3+PUzg +62xX1yt9Va54SIx5IsXTEBLMmzA2GdDaAr6l72+ltkb95KyK3eySeQE3niD/YNss +lNlvMuD88mm+WSoJO+NyTPCt5En5D+2FHdvIIB6khcN3MQWT2Js+U06t+lJAPeiw +0nYeiXyA7+WL97Za9SVMQ/t2CswM9KZK4YwKSj6FTNC7GkbvvAA3WyNvyQ9OhQpA +b1/MeXaSf4BHdv+r7PzlAau8M2Bi7tb61Pa+IJdTy6GrDcF0/RXhFsxzbJAfzk/Z +Hfl82HXtKYPrcGzQcw2giY6apeiSRpOhlgKKlaAADbqa/dS1H2da+HFQj6cF4Kew +xMqcs53jSdQOQdXIMipLg4WEH6LzeAOwCywIDWKAH3d30ZSfYA850rotrUnG3TR9 +hgdsPgdjFYfrpJIDu0IfDM/cw/DXURqZHWP/6lS5DPaJKeRvMZYfjEg3W4nYb2Ko +DpCIl/+2799EizmGbgdTwKnPmzYhzuqPtzt8FmTdZAL/OT85wTlmNSGoCa1Lh7fo +bAFY+nICR1sPcPfYVsV3mSTz8upFSbxp14mU3/vGcJJH+3sOHfHR9pdUkqyXkHC6 +c2rusVRWZO4yfcWXqcMwR3ELkSlaEcYXNs2lqA4GUi46LJlSrrlosmfwqDFsRB4G +FBIEjcAwScvuzLBND0uEgpigNkuJ+MwnucaGB8+BATfmAXUcoLOI6EU8Cl8cb4Cf +bnGC3UlCcQgRLdEhNK5LuS1mKvkVIbCmvy1TZHH86PJqdQVU90CdmPmixStoJR09 +XmUHO4m6jBAEmiSDlgyKNDoIKTappeSA7rdXNvKm/2iXXq2AE9+jgAVOnldfTp0z +Q5kEhzIdYRaeVSfJIc+DbfUOZ8KnTCNtbN63fdwYEu8IBohdeGnlJxlh8x2U4Nma +iDH8H3uvqwypkHgW5WbpooUQcgp8UKJP6ROoHimMhawWbTzYG6VH1KTc57D11oJs +9FyvMd8OR0F0bFN5Y/igjdkMuZmUdg65JJZZrrFGAM/6WZJXg00QPHUH++ILYlCG ++b3f7TALO28K3+FAD2FdYV/+xIbIXoE4AIlgo5DKvcsmpf3wWkESRbxIoMfObibe +YWFV8j9JDONoZ4h08WmSrC9J/jrTycMtSv7mP7Z9ZQ3nprWQZRCmcGILApiEnQbz +Nq6RQGUkYdLAQHuUacy/O0lnwI3NyBLlkoiMYN+jEuQAcbRBOMLwv6+DdFJqxmRM +wuIJ5P+MV7l5wNiIq5nsfs6czcyt+5LKFDyBOH8MvoOoTOrAU28oTJ7YO1mtHfFa +Rfcu9wCnYHSCY5MaSYGsEQkMK/lrVrJuyK3yurG+d5ovDRWNk8lfxJYMR5ftI3Be +G/JxrCsu1NjmrOJL1L3o5uTOPRsj+cmxZ0A8D9Vb0713UUg+vaafTEv3l8R1g+kk +UObq+gmJTxwkYAIL0f2RAeHpwlem4BU6YVm8DDouheDMULe9SuK4h/MAEts+ZwiJ +c/6QNjdng8yfADzT5496AVKbM/DobzMDIRx0jUVlAGiQkRSWEDwxHfgyDWXogqgu +cP6B7hQ07As/PPEl3lw3BbVbQ5xWtybldoGBlSoY1nMA/TwJ8DVvadfp8Yds5Pd4 +8/GQw33H9LtqRox4bhjN2cGxPQI6cUZJBG1PkEoXHwAAEdyrW6UocQTC/IvYGr8f +YY5p5J4jXllttPu72qePijsktmlaNhSDW5YDOyQVVTzc7ON5r6yls6fpPVolb/UZ +kuVaafHFzci/MnZB43DQeaE0/fLeec+CBHBR2d2xGu0RGpF5DkPWBA2swxYpXZms +Yi8XOfxRRrzC6qe7JNVzBxOJYI5SwqE9NxCvW1UoA4uHEvzawQ2VhsDgf5Z6xx2m +qKnA5YuhqjtjidQWb+IMHccZF/H5AqB31OFxhLuo8lDeBlJ22fwfX6tT0DuDAc/i +vRVSaGE3eSxeiu4ccTq+cYUz96eRsTATbHle/vT+4sr322dKT3FcLnVPPNpYWpXw +25xN26HsHZ0R8WS4F7qYbRIDfGvHva0roOh1iLce6GWawypb0E925gDXAZiwHb/q +XJO/1FxQ8axjWFvpAlcdTs2jThtp39M06tRJ5iXNxNk/5Vuz/QbhmN11MKo5Fe3x +sJ2tnbjvWlg04abZQxWqz1S3WzNzO5dtXhCLLXieu+qNteLlALBC32NGdXm8/BKZ +UZRmFtCmZ5zSLfppT+pKXygnXDCvBRJ6sIAnkUOMi3FYj6NA+tzfBQhtrlxSHp77 +5LnB/G0MpJ8HLKbVYuT73aKNGjfDPOnDhCepw037jgXKTnMdQXOnMkYs6FrSyd+d +jK5iH0DlmhT94dJi3wbb4wJGWJRFO0FFKJCLC/+sX0m+hlsZAifRbBkF9lQr+XFh +E5Sqw5hK21sY5VGXNlul+RLR6tH8YlWIvfvLQRgXWT9GPD7f6m9kIO05sHhdTNx+ +wT3J7DcsZyoB0GgepfOMeK9mhQ+JLozndBepxqhrtEMM0N/ULp4TvJCREm3YghlK +YqdNgBYE14NXhgZyRN5fS8EC4vwFMSJftocksmIcQC6d7rtMBSNGi6+JtGrajAMl +SqHp8202/MDj5nFlBvkpPhHXuqHN6X+OsPypKOMUB4cz99Vw3MAFPY3mHP7g6EI8 +/LmahIEl6zzx0wdqX7Ky+26VxWwoOenJqo4Z/xx+ATVjRlUsRfgnlBBHI8IQUh+p +c9Ag/nbINjA5cTsQa7GoITkIwfxeeTni+6fsAfP+ebLATkglEe5J2Erw13dyGsjH +ykUeBplMimrDB/mIU7QokHDiId5R/Z7ISQkcM0PJ4x+LbIgtKMRFzGNgWthHMJeS +EMCy5/k+TSFMp2goRAKH1rWl3HXfbqX6Fp0YVRSP7EyVTNDeAg8pOTvgrmmZs0+J +HQWLxhMbAmlorDfEeh67swEYCWINWbvRwo1Q3eqA331swkJBP/V5ESqHGoXD4E+/ +R3rf0zr/8BRGuVckhy8jRVUQcg829Lj+hvB1+UwV+ch8LH1j0v/KEquGKPJe0fjo +em6dkeEyk5lXTgSIY3Iq0DLA4ZRh8iNYB8fNlPTGxpm5EsHxyUp6+80zFnilVhoX +6LPIqIOWRfYhECRgUoqmV9iZhCGj0Vm/8rJU2basBgSwspzC7Mo4HTXVXjMZN2X1 +aQh0AvazmSn6xsgr+pHJjBmmDPmsXwUh1hkjeqoJk5vmpMV9vBkF9Z8NcBxLZVMH +mTTD5kKWr5uIlf1ipOgdirOOMcbbj0jnuOPx73KQeiuh4FR/wUo5+5UM04SINRPx +5bGPYLPv/eBgYyhD5Krp+tvTiTNFlfYTNvGinjE0yb58k3Fcd4zKKFD2tc3pfQX7 +q1bp2vYu8kDbLur4UlL+kLrlUwVghJGdBtT/ODcElr1K3GIZze0XNPB53u5r332Y +MtmxaIzXgNlLDESQSN1cFacfHyyrN1K1OjKZ9+iYxxfNxRpFyRacqqLnO11QihHm +WSPm4g4WDDcCfFurMKnrciBf38eDNy2QrR47ayoOHW6yXmBuLW8cWrQAE3Vtl24A +aeCXOTI/GFcl7i4INTSL5C/KoeQR0cDUa85+67K0HiMl7q5akU2bmPPF3EagjZZv +5z5LPalBqnB1reBG4lsd1BEk3SrlWxgMI5ZYlJtI6EAhDzAzJBVSdJGAsQ8CL5lx +05OLuMezIhisg1mvHu7cJkP/3Z1c7M+27CPWdmLI7vTYdkUeNS5qR9QKIY+BaKQ5 +b2eSFDw8CDwHc2anSmx5gz1NwJwrRO1bAPZGGLjcwsiTCOD5Hh1GoRTdcNw5RY2G +TuxbMlqg3XaA6otakCLC/guWO/v986oLfM8hJ8gtdECoGfRRNf4BRWeme4n6T/Rv +qGgg6L2VcXiKzFXXY70Pi1b8M8Pon45xdR18QpZ25YDkH57u3EJtsylj7/MBkviu +6Z6AHHZDHUU0tlwKhcJ1Z442ebLYambow32pv25XzuIcnvfKBRxoVK6qH2zXHDzu +KJ7/gUHobNj9bKe9Jn2yihpreQZs+HFo0ZERhVuh51wpbao5a4vSz1x+KOigMHRi +sC8wxeqP+wHa/+2C5JtG6FrPgSiY1EE8B+0QTjkKzkQ+XCOVK6R6d6PFyNwkBvEh +pLbNhjoSC5+xzmgY/HoOVpK+KXQuvLmV4CuOqaNEsAAZfdbf1Oa6E94GRx1ItCJo +23CTecKPOQX50iSPFDNVyNgyWUMhg6VKkTk1Q6WCBbEUPqB2Os6dkiDQikIArUQK +5s2kR/yX22b3wsiPt8xOpXHACqraSf3v33A3CpeKOTnL66sCEZ5sqNZOdPtkfTRk +Mt3K3Pwpk34VR9U8pxtBh8DHpDLUpBg92nldLXq4fKLx9VfJagjyhw+OfGVgecww +QD0hgASgW7tn4CSe44Z/Wr/htQFGU5GSi7vETmFNEVr+ALgOGUH96lFwxvt+PfYZ +mPVAuYszzUjJl+RSaTHtVXWpWzn5m1vZCS4FliFPNULLeF3RfHgBKGLqE/TJEeRX +LKJoKc143OBiO6BGvGqIr4F6OIihUF7A6NNDYOpH3hBJgUVqUQLfQukVsPQe359z +5cm2cIyJ36n6SF2Eg7mm6U29gyOLtGv6ytnOjskzhiKXRN2cQ9uJ5pzEiQK9s1Sf +ugKws4Ge7hc8rA5ISzfYibBWSsHoTFgcOIrCOMlhEfqkkbaStxh0llYTagVPe3A/ +OZkcdd1bC3rWfZ2JzlLPoeK77VF/ickOcL+6PCRRuAzjCW29Wol5Up0y3cRpIedZ +xUaNF5rKszJDm5TIucmKeEms1B/2yK+ejZfgvYmv8pVaeI7yQ/hzaxHyTfcRRNnW +co1Og6BxC8a+Y8KfrrdedymOOyfI6wvyVLfqp0sjhSLvrZHp+d8SWlMZg2ZeKdXR +qjL+hx7kCVAFad9ZyHgfunnjkDYurphdIQTjfmgexp6iANBJEW9zwpn9r/JJKEWq +gHNCHvQEmJtmPK7IqmV03ASqLEKHXuUyJAkYqvJrBMS8oUMahwrfsM/ur9meh/Sz +l4HqeKOmLeP5mX3/6z9sPwN8Fsg2FD7j7xOZWO6Wbj4D1C1bGJEbHgIfBHNxgtHt +nnNSnaTrWfVCgm58EqP4TPPXj+adzRCOKNWGAQwfPTi5CztKISLHnJ+vgnBOy2DB +bUyGJa+GIcI8UXTvwV4pO4ZeqvMVTOZRn8IZrF293RaBaBrWS1wn8XgBTpOWnS7f +IR78F8Rb7Clf51+tqglckrOrgzTKl3vhGvwwH/w9IlL0XGiK+xM7pXpHdFvyaqfO +EDztmRfvIbOFxXLxIf4KLOoaVUELAVYaEsPL6n/lGZW0MmFqs3iEc0m2To5FLpjf +zH+Zi9Q0vz+uefhEJpD2EF4F17dBWxcF7qGh62oT/N55pCjTGEGZr1LwMxC0aukU +P8L+cBgRfviPbImUah7/TUaW0eAPZ37IzQ2VUBaxrLLuAJfRsBZtH5mMcSfs6x3e +XQMD1zhVIJr19wuxiYdbgMaVTmtwmH5duuwGetx/t6op8lep1MJLzxJKTLQ7JVoS +ynnDBvvoObxZIisFOw9+s64KBlqSsO5f6ASH21E8rJ+QLHSLSAq29KI3DA53ojKF +7ZiQ0jzx2UYgJt9LXDNZrUaXYkS9TRmYIA+NMDK0JPxfUeTr6XBHFbxMNhVl6XoT +q3LflNIgTElDgioecUoA+6UEEoS8ODRITGma0fRCN2CT9ThwSVE+PuS3F3P5droD +bmFcVRF1O542aTV33R4lricU3RHi/8YXgHmSEQSxBT/nOjarqVStYPT97yR3Zbeu +uChVXl6iCmOU8V1dgoRPnDiAPYMliBiBrqjiRPKpEKfZgVisj2sDJqpBmReKLyUm +qPs/qlXWkq3H6BS4q9V8uCSFRAckRmWxLVcaEDAzL1vS4Tqj+B0AyQ5C3Lce9NSN +TUtVuJ9474d2u5EgdnUxQ2M6PuB74RqlmxEFyFAAFDexW3h3M5Bm5pGxxK8PVJei +oQ907wsbia4SeuoidALjmGQo9PSU4idrL4j9DWOoP6cbs+aWy6ChBPf+pO63h0iP +Urg/b6+EVlQBbAQKIxMWMglY3Ibz5Rk4TRADaE3Qpv3VLgPH60Fbnem9nyVACcQa +uFTnTCQdXTrFa7npvwmG4QClMlN7aGNqDDiKSiVH+xOts4tOR8plED+b7YiQoMqR +MzvbRfiB2AYwezSXKkZcwPQIdd+vZsPaBwxKnTOucLJJGfQIks4igqXIYgLpnXFb +tCIjkrT8ItPICLdc/s0oxT+nO20/8d9o/6mifg0kHLpiSiil368JHaQreWzjvyrb +g4zkvGrBtjOPEtFHdtZbKeKRtKL283a1T5Nh2W5cttURJr790ukLt37u8HK8iswx +MZfvynxiBrLdBLpZiOvC4BIf8HjclvN+FA7V0u/IqkeJJoRY6Jk2uLsdVKWzrBW0 +hqBfuXsq+66gsD+AgDcD9eDRU2/41L4l2LXF8zF4bNMTLCxnUSPuIbefYKzUDJt2 +Yx9qowcsqTSIhUepCzomAUzXKSeQlNzruMYoFxW2F+vFn/3igg3cZxFeSpn0Kr22 +n0oofEI599sj3JWWagqW8zXWylaR7PUXxN2jHTO8Gr+o2sBNZYHSWtrJVD66SEDU +1JW+52SyYBx5dz5UH1dZU/i1iz0g5ST9d1h9nF8Nc2VSN7wpz9LZ2y8hngkFiG2f +BZsAmJGRIMsa16iCnrouctfzZ3mQL13XqeSc+osYxeQZOBI9cDmWQHAHBzH9/ioU +D3PNg/AsSegAWqE5yYfHoBpjsmyaMQYVFM/ktj2PSm62zfvMGdwz+pm4Lrwzmt5a +zJAyEBRuZyTuTiLde3fLPo+ch77gWLDjviocLtuGDyGETNOlhAoXFhNI9A8w/trL +DNw+IEAyYJ21nduDKgBrNhF5Pu13oWR8jqZI/n0I1rMy03g0rEyyraVk9HvoDUke +6lGxvjPrEvvPnQGPbvFqvUsUgfUoyEJ+OAvRpKvNFUg7QhnmAUi8B8A6l8/70EFC +B3q+rwjwPZRul/p14j+qViuyElRyytDpz8HnS1l7MEukw0mR0krGgigQtCCEYAMG +j6RXG90bmOiaQJfFWFK+CJ4g4ZME8jbnrr1jy+khTR3CuP/xe582B81sAc1e92La +ozh8ymk+ses1ZHXzOVxnfLlDGmELolSc3QPQcaZWAed0xKxAPZ1MtAJwfJREJRT8 +3Io25mRMDzFiOO86SwJzZAMkq+9DV1/zikJGwTvPagT+2KDDxxhUCeNDBS0K5Vt+ ++2rv/8350t7o1f9+K27yiwkzzmnrm2Vs3vqLxXvINl0u13I3R79yGObmlAUpvWdD +YqZzbVYaJ869W/L/u/e54YOuw7aaowRT/IDpj0XMQEZQ7aqBeeJk6mvArALyo1lp +pbLw9MxGrcMojzC7rBMc3D3HljYolWdP1WLruIMN/f5Ed9jttE6IrpFKIkD5oW/M +rfJhZx7z+YNsze/SmWHP6SoKiRvP+97dsuqtqScuHFc7ljghon7wUWMfQ00gqYMh +4z30CVK5HWULgFKxhPQTvPkq4OfQtKhS+t8bmPD0KV9OIAL81o+4xPfp5UdT9VBK +12y4ISj2t8dmPeDUdzwSx8P9h05hhRSP6av4MmRcNy1ps2UHPmLV2D9OPw4sc3NP +Np8L6ItZs2tybErXMt5OBp2WysqzIvwl1avJ/pL0zVt1K7OPKlKljLvNJBKIERk+ +nOz0BC7Ci4lncCZFxrElMa+tIgO8+cDzqbwGln1HPe1ww77/Pu/i9AJRyYxX/Csx +uH1xyezFbfFZlL+1odwK0PFq062pVvU3sJt1LSHTlJZubltUJQZl4+2dW1V4HMEp +Jq5KGoDY7bvnsLf1lnv1Nxso4RgBGn8BSKO7pQ45UHFRlvYAmxAdQqlE8/0vMPgR +TO3zsPrczU8OplyGp29yHIEW3Y+EfVnsldsngDvQPYm9Q40lYjkqU4OL4xDMtnCf +AmZp2C5Wfecmskeu5S/wxzfT9qXezi0Zx4yNzQx9vz55HsUMf/+q8dWDMduWW+qx +fYD2UzBQgD6yKXO3kcB1F9NUygyURkoxxPqKkLykpbpIlA8OE8clsRWp6Cvn0jVA +jJWvRh2f4Iki3zeU8V/u/2IvKj2odJHp9fozJNESzSs7f/27oxdtYLzAHKooAQTp +HrLp3HquC7twMur7j0581L5fUHEfbY1TW4oFKYF2ziysDZs7xFwilDy1VxjLIsQs +j0lDJc2N6/gJWg7OfMAn9+8jDgK125mPHt5+CZBi52NAO//9QhB5x5FE5Cf4bnFg +z7NOxX/t9ThY428vDMzcglS20JM/SbKnhTZXlNf+1aL90lJvVwCOb2hK7F3Roi5J +7LWtOaCLbnMv12D1npokRqEhKDHDW2qP05IHyDZcHtBklXKDgNDH80LggRwZlkOf +27+ZR0vdENXPoT37gt+Opm2eLVR9e82pNfww5zI2hDn8Y1lJs5kSmZ4yUpoE4ixa +HhoLCB2lAGO0IM342ckr6tJppWdEw5TRQbKQueLWmF9NgkNo+RND8wr6+ApKL45h +J4DUEmCGBu+nOXSFXUazVAu3VQGs/wgGveLtSgNz2h1+ivsEhrZ/sJrDac8iy2L9 ++kXCGaatiyWgQ3bYvpAGBEcPOJAXS+RJJiq8WPfsqifb4pOn4u31mjlWEDGPgVPI +BOttPPnmrDynbiqQnVOKJnFlpoWJvXe5G29yJp/9cGu0IRyFnDu226OzTuwCZDa9 +V4Uu+S4f4YA4Z+DtcStj/zYtTujFQ8jtI2w44Y54+qgfVlX/kgCknaiclG49QQMx +Mwqokbfu+q4/qS/2EmpLy3/w7S4XnuYLINbbPY8jIZoEOdNLVeDeuuzYTE0cyd7G +GdzuPzZYMcLIM6qMxOyqhkIbFoEWBYknkK6aSf4p13BVQ8cmi3tTkG1F8dW7u+ot +3KiVc+waBTTJBm4pCeL7PspHHNbNJJEgGOvdLrkt2m9SUWgZFxiKo/qd8widATXv +UhtzNMwHR0W/ZVeiW4FvU87tksCRelOqRSOtBReSsQXn9noUUQWGoEsk+unuB3vu +9lRraflrO6l2q0X3uoNqdaX3w6EhffvDG7LSdYsk9MLRxMUC+IOjMXvjyvm9VjWL +Ny1p8HHeERJQZEnfNoP9sm45pTndnCYJ56d3ZXU9r/f1+qeF0nyW2U3n1mno3hmY +wFXMuePkzhl3rEKXlaCQlCQIluIJUsqycGPnl1X/t73Lcpfeo8LAG+ZxrXrhTWiG +51C/V4W0jmwHXxEQ5TGiEfcdVKk+VwspkJDHiayHUEw2N0eDgH7T2k3q3t0mCtz/ +dys2MXdtYbIRU/0R90A+eplpYfcX8NHgsydWffj1eB1x+toBHbGqIBqMdXE4TVlF +LJvKPzbBNY5XiPrPLYbdsydtCRyUuyKjSt8rpzyIi0pRH5JZoB1Tknrop4lX/eVQ +s5d6Tov+JiXda41ZXX7i5fVYpC1OTykBUvA6tUEsoABtfoe1EkhrxVOyB5/zGh6d +cjO3BPq/VF+H/7EOjbT50tuof0AVaQo2lsc5g/bfgBA4C7d5ijfDNxvHNxrIfvtB +DaGhmusDdiWDH7H750toqBH9IuZWDBZHXdwNNysRez6/M6eF8bGASFOzG95PG3SF +cnL4f3Ds0LPTbk9YC66mlQ2mY/BU+J8bDz+hm/EOCuzEPOTwHTvWbhGDunjQnakT +ovpFcnEKSPFJFzA2FNT7qVwRnMVqYhBaoUdqtfSN68edIvZ0Yl3Z6RFaNPT22k1S +VHIF2/RAThqpBwztOL6WS6/d/PWb7lJ5dewaiiuvPf+K4Mi2IyHtBE+YdzogWs0I +sH6+2fmXs7s5bfpTxbU6uqkyNEscHhgH7HpD8EGHVt+b5W+yRk9MQS0xTrr2CNWB +uwgdaN9HFvV6Q4bSzwMNmcGf8C1+FkjF13rtTLa45+qJbLIkqtrz8ozcmJ1Zu+dI +E5CN5LQ7PQiA4sTVihtP8mpCJyLGHsdlEe8J+WlRAJ0ioPm+3Uw/lgQQpd1Z+dr+ +aceS5lhdInZGIaSd6n3lgb9CG66HIVY3otHvLWmCjbwW2N5ZFS6Srq4RsUu8o2gh +rJFHy6lOZRf2h+NnzcmWD3KpwkCUAltRAJjQ3kAMSDpdGSDkBA0EilUo2Ogeonwj +gsgmjGF67c/rtQJqvr0IvHvYbumyeBZwjswOfP+pa2vX2gavc+98z6mNj+GxAKoS +53RIu1Mimjm0IjqN6e8K4Ar7mhSGLNyshaP7rFwnK8PQ9hqiV8O6sTJNT/O1JG0l +kXWQd7AkMWFcl5fTaf9T59UqVdWh1jLtKbTwDb47cIbbzLvnN8zmgUAeO9H4vrKd +lKECSguXN0h1pk8qa3QkGo0g/fhrOqJtVK15Ikj3qAK4cZQPDlM/YP7JgOoDZxUo +U5A1b11hGJhy1JUnmUUlLqpHuszi8tI73NGUJUYnJgWLs5EHgV2MpupaEd/INPrM +fj48APelV12j6kDKZmYmRRZbEdY1s7xBtQZ/XW2YWcDVTuFzdUAMLx0L3U4/Rn+2 +WAzy3alYfe1zZvB26JKTkpPh3hs2/XCmwXjVB1Te8RWVuDMV5VDPGiIK8ywUyznt +6koBRlPYtTJkz0irNUgmt9P5HD4R6oucR6ukT3AEXmrBYoDuTNxcs58Fn8Dp2VZx +LwjmCEyvMNndQQH1lQWn6izPemYqCs8ppG0JUdbcz7rmCm9kyjgs7gMx70WJvDwS +95WfmZX1GIQhepTr2yt2pG7kptOYvH6rttcbg+GU+zMbfoKRwmJenN8FwaoLDc3q +8ihtPwdZrnG1WfS1260GfMPGcI89Q/csAmptozfpGSCrrzpvJbGhlmGOQj+ajNo5 +P8KfSQ4MKVYLI5AAe9GAoDhvON6jRnpcf2szYfoO4gXLnoB0mp4+6zRmdwMN9nxf +WVnKYQtWHtIoNGUgTKnKRpR8JsFrR2B3rWLMUiHuJxdReFMy5Cb7LoYRXtLZBLa6 +a5fioH6Y6tv4XNvPfaMQTcn8xDA5C3Ho+fsDak5SF+uNppSY6OhTz3jVRwnFsc9C +m6yAtIcCvB8ZAHrSNbfsNSWx5dQrxGpPaxC9L/N70KlrVwXT4bc2xkjwgGCqW23K +5woqZYpwBLcYtlXf/SxBKSgkdWGLAJzqjBLRBsVgJ5TqoOnxfMV6zZF963Z8yPzZ +yJsX6RQLgtUq6SgbQb3icsjjGyQcScB5bLsQBQ2ZapLDL2Yy08ZbcIGpUE4K7j6J +ddCB2JPCrS7N7VMp5VpE2+kWnFA83KXEYHquwZYut/Cimc1NDaMt3JITp/A0RTMt +b+Bbj5HcYgh6SKWRbOuiM+rbq/MjOjCmz0K3cdutY68Yt0czeie1OnMcNLtQoM0I +Q7U3brPTwuQZ6pp4273MPbLXeqC635q40LAFJNB08BSBnhp/yy6UTZLjmRhDxSSS +nYzaJCORda1e1LE8KPyACsQhqu3mvR45+4BhOnI8PL55FS9sQxMPYGgk7iQWXreF +tsB6E/NzTkdjpoQ+R099rzk1Hfcvl7SYfil298ZLjKpic6DlPzlsAJYzu5DazKbT +WegRb5v6DM36zDpa63+P7ybIo5PKslgrwxjBrY01ZeGKyRtoke4sqZIo4EkLVaDY +Gk/Q9qseUN62UtklaRBC6gByvhlmDSx6cxlve6hWaidevBC+876GLt7XrY9XP8mf +7oJpPEU86kO6KVMnVSdOvFskrAlNiG6fdQdCfpCmnGpppGBnWamz1BG3ppdqmj+E +Y6APlQx2he2Xmwoowplj1KwFXKibETLBtDa6wrU+3yicgL5ygnTTVbyzPwiAEnDD +YS9tzZ1Tk1EaAdTSfFJrU46J+lq3xQvYJ4j22jTGiZdJ/77k6g8H8s3iu/7OARjQ +ibPCE6X9Yd+UeRJQ9P9PWgq0pUa2scdFtNbGOInkd/CgzjwEDz9oB/Fd+4BMz35Y +Vft562yE8STQ6xFE9h8vt2KJQ/yfHNfSWOhFZkhWkni82w1FVfkmfbr1BDnNSTKj +bYWFBBU0dQ3Pcrag6aUll5E6eYSAPFI8eGtA+izE5XAc0NBv0QzEs++Vm5NX3FKC +bSlbPAUx9wGH3U/V3hS+exgD8GM+y63Qd5Eday8sTBtxVyi/LKoTxqGfhur26+Ji +K7cYXl7HLaltr/FGCBoiX+XQmJ41wKUKliIXg0cRPXQaIV+b8wjqCj/PO2NW+UID +5sJPyIntLEDIR+ys0CXfLseCVNnuSShI0TCD1wYzX1GhhldIeksAVM8dU/hTEJXm +RCbXi3Mz13iyyVHCCb5C8WLFJ68FOxTFNkt86X/FjsUWm44ejPQLBIy/yJNG8RAB +AhwQl3ZNvRQmPWCw1mP+IGf4Gm4WXyQYbonmcLQsBNwv5epX1mADNDzjoF/NxFQ+ +GErnAmx8w0IVbeOdJqdVDxyTKD+zaW02I/1THbwY0tbQvhdQnDGIVmeviaphspDG +hbjvwVFoKjYx6gUfsoWWYfO9J0NPjodljHX9fNoDCbL+9K7pi+hYbU9A6qffJAPO +aKMFeu2akKawV/81OfH5MnquJJ+4b7VzcUpSYVpYRCcSbMM9hpEMPloSTsI+KeU/ +gRNfCt88SOA60KyJ2ROsD5uhU8A6127hnG4QbfqLxOeUF+JkQur7V99Ixdg3LDE4 +neZnZ/YsJrgbjaAQnPLRY/Jclod0KcxpD+wG3ymp/CeCLQgwgsN7Ykis89qGrAWD +FtvyS7BTV4Qsrlpg+6x0UvTTijp14knZYaRF59z1z3l6w+VZ2zIGsjz28QDV10q1 +naRRTZaJQ+fLYGTCqYU8zvw+eWevCcakEnv8GOAY8qMAHcyhSFFqTQyJ+rq7ZOm9 +fRa6Q7MrLsY/4b8aelWLfLxwz9jMG/MigCQ8asdjyC/AOvtwW7TnfZGgyu9yH5p6 +nf20PvGdo7DpTlKYCBU2qu19FfjP0/pqXF1giG435Xqb6nUdwlsDRVKnILve15Ht +/ADZvRbScrk9mAl2IBxZCU39jFkuNmGtZ8X1skDA4iRolfv6nyVF8EYCIQXtVGqM +AL7/3l7WCXBgoGEsc6qhzIqr1Rhxxd8sZiHHJVqZBr3fkazdtmnZ/r/b7s/7DM9P +35nOcQDvjlb6ZvxYM7gHFEKI7MWymGrVHeHif6EnH8r5ruqQjxO9g+uyAzF3OVrr +66nNOCQPPwGwQSMWJWKFCqPBAqa09apUqlYtfJyPRYPwuW27YB44qIKajzyyq45Q +nc/+B7rFtIw6Y1fBxNnHD++TX+b149LA+1AF/eTb9XOnK3A6k4fB75TuhWTB3sgg +xVbXaEgCAH8inxUnpMs+nwT9I99bPtjropu+UPv7Dt9A+ESvYWwNtZp9ePQPxA64 +voVr6uvGMzzxm1ldhmRBs3pYchWdoFD+BSHFt4OQ+gqvKmiHTzhvmrn+4woCjA45 +8p1a0R6XPVy+WGPTsOw2h+xFgCdxpu/1cBq0B1AJM8Ututcme5/YblYQMoX0FsBK +S8KxJzCaep1PQeirMVyjKlz6cibXIHuWfrw2hwb9LzGggJvvC2NMVpm0a37mqkEK +6vZmrc4KP4ZQrC4mvb+M5jgjWQcEtOH/6j4tZ0m6LjsP5g8Nwr1eABpkvDb7B/sW +U335SX2Q45aF3hwJo6wyL/Q79JXTpRmD0oiTQWxhGmVPoDK9s625vPgIaJ1F3/Vw +itG0/LAsnF2yMaCH839PUjZhf2JoeMZokLoPJ/j9VqFZm3Le58mBHMYemOVSoaGE +MdcuU2qnZXA/BPWaSTtkIZgOT6YfB5skDZEYrn2vGIYS5hKEZzn6hKh1dVOMUYyg +bd/2skUO5xGNJKI/5R7SUlErRAAp8MrTLyiJm5N8r2GplT450lwnDTvornPGv0jS +eqsDvA7Q9BKHuhy0VWxabuNSIxWMb2ILadeva0cFCdl6N7UfPeYqLn2rAGDBAx4/ +zolcAs1ShIuNYQzQoVyFcddg3zRd4NdyiWpdWLAdK6sBoVhk8QPVes//lQLLr8es +HOgokvv6RhdT6Fm8EX6XC4HQsooXKcgW1yO0YAX2HdfDj7E13zgN/hwATySbwiMc +qDxblYiOfIDOTfZXC17+DOYwyxOjCqaTenE1zQKdOM8og4DyDBAd9Pnj+8WPOQrO +eZ7Ll3Rwq4nx0ItFXJ8e2Skbp2wCEPALY37yEAd2mhMjDI8oyMii6CJiVe9KNFDo +ZpVYI3na8ZoKgzXd8LzoetXG4W7Ac0qIiD/SqwzzlhIm4Ql7RQtvyeH2PCDQbzs4 +iL58SexBeX37/4KW1PkhLSwLgznoj83FIh8NwaWf3awK/K/fnPl0UH3VCsmYv0nf +Z2DCoIBBwUX3XLh4CuZF79QZUphP1OG3IPg8U/Jat4LbuTfVnZMre61y2FsIR1cE +iyCGOzKUevybI2DFU/tF7Luy6S7J+9kXivnQCWtMrecfJzw5gu9f3s4mcb1K0bsH +Ua69Z0r6FAKlIkzzNaWg/ZsYscx5/zYBlzrweCH3dwcsDysE10mVjxGtwu2CNIn4 +bJp0CmQVsVMi35qSaQpTXL34HjsW62saWnkNmqc5WgGTx4yII/tO89iabkuec6NE +blHhRvn/ZP8D2PbmKX5P4rObyOOy1IL8DuKzleofyj8X0bQa8CCAKVvQVYT/gKpe +PMWnhe4LYj3eKcpIcHzcIMg5dEPeaBssaw1DryqcxWTES3sHpedG1w5rWUA2uPcJ +fdlRLtnVTZPXtes4PwpysIPrmzzufEor5OroVe9hfQ9im2/78KhI4YnBNG8WSUMf +HLnOhP28RVlb01Er5SNeFxp6X8sXV/ZFtzoIgl67Ha+2BtySCEs+cJ35YZAm8hfC +Fypkhtw8BkFDdJ4xqCCQa0oCTKK7bvGpK0551PB4yaPKzWEhOY6G+v4I0rkxvZ9F +OFRppwfiPKX08ZFDnMxP8yZZ9q7YkiOfxjrTntnmXkvnxCwrmofxCxu/c4zch2r6 +BeVr//bMhQ+EijV0eqvldt3BebFaBT6N69unpyj8nq/ALSCcISx1Wdk8YfgZt8/l +ATsuFiRRYiYSRUvJqPNwFj3wrJMRi4DR5CCDm/Kh8B2Lii4Fe5OOR7dVLEBeBDKV +Zm9a2Hjbr6CXNuFIrjZSCS96QOIO8mZ/+HPDCYyV2M5wlQ1B1VGYLKQ/8hCOUln2 +hsSiLjGbF8DpBWH8p/PqY0vxrD4Tf5lOwtVcpSPleW/yjMZJZFgbI+jsteL4v62k +3zC13lVTJmjzuPgVwsvG/YRGwqCJkCs2O6oP55vp5qFayYD6fiOtJr46e4JHHkj+ +Oj/W5CkDUngBsJelV6xnQYh/ldmJdMIUV+eSEwqHPYuAl8PqOw6w0gwukwr3Sh3q +RA5GoidObmZKJBd/ip61yUPwxjuHC4qgwTETxjlnGdHmwf8Ys/4dpjEtrY29hHLt +zbwP1NjdbYCUCy1kl/WLc9rYenJ+8ZNT6ezTd8SbEvSisWGIbIZgdA2n66gbn+i0 +pogCJRtLTglHL7aWST64bPI2zIZ0Z7OhZ0pHSHt3iBV1rwj6Lbn2Hq9bbmhOIibE +hhyHcThyJYdnWfYxaVNMyG+j206k9Q/Mhq8B7ZRvjN9DoGTnKPk69BWVoVLJr21M +0D1NoLC32I3P3iIUtLQDXtpOBpvle4DfYZUA3b/RGa48opRNnhbiAOLr1QdsQWCv +jCu70c85SFzhuDwzMuCfFVj6AJ73lBgnXIfi7twihnWw+Fnit0SfEspYXwawG8MQ ++tA14oerWdyR8zJfVs7ojnH11O1rR7gd21fad8ysxU4D6Vvastg30+XWUDpZ8FPR +bSW714OKlfkUJcv3t5GHwprizK/jpEWRd2CiILQXTUjD10zVaPl7HvsbC/jLg63t +dHfjRLq3kEjPNqdreqkvXlJI+6BMHo6nxecILT0mrayu/avwigYlFcc/YnMiACXR +zd67IL2r6syblSg3mJ9hqcPjYe3fuBn05Fmnn6kx3z36ZRIk3gStUh7s5IxEIAso +H9CN+2cBfGa43IEFH36wPON7ySe0ethWtSr71vA/LYNWfrOOuS+UytSIiJv7PdSU +ryNYYi7+AoCLVUCr5hPsmNktrzp7YdzAz+9A3Ffep9OsekbgSOm0kFlI5gvxbrKE +vDxY2S3kjNkU3fQwdXV2YEj+gmtzMVAxWWZfcdLy1s8mojHqEDEizq71VutmlxEd +Aas5PpIBzqXqK/13Sq9PPHHWJeoaPv6iPdhjN93ixu2KWAbBYdNt9YbyVarEGayr +imQpWYNbnMhPRNXtVil13XXzZl/PUHBcKQSg9hGEn8uPPqQvcjwfCVX5MD0qu6H9 +cvuSTqi9aNlHfyNDOm0r05dtkVRstXoWbjXRrI8FdUMqP6yHrprHKF/a9WgqMcpx +qMpzkpvd//ZEjKMPoTicFo6rulap2/gHww5p3r6djDcNFfmGqB6RGwD9o12B2+71 +7OjC2+Z7Ai7T+CmfOuStooBVgfxuybBA/trKV7rVww3KetP+KltippsiMOukOhAU +2Jo0TBtYcAFFvZlVh4QgW47ATVcRCpqpqDMNMy2Wn3nnahQ8d7Q0IV9XXZZiD/0W +7ioaIclYcAI1WFspHWROoAzjOFYr6n01a5RoIm6rRVuZ9Ao/RXDyemlqVrdskeAd +6iq/aAnOrcpFtwKqFf5CHHp0OJmYB4LrI6ZImtwWpLGYW7Hg0Z32VG2rg1AUrI5/ +2L7DtE7dWHkPk6WSylj1ZQ== +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +T3JVVv4olTqmMR7B97zmjDKAAUqT1HR3dA4mr7nZg7imRVPYr+xDs+3/lhQy92FC +czhXcdpkyt1b33Rs5P083o4weI51X3sRyi3HEkwCUu1XaupRk6Sw6k0Y36TQtWFJ +tUgv8wnSw1+0UdCO2a87/+reXVlx8SyGA8iDp48yhsqPZMA+RPnemFIyVfrmY6RK +MSstWf9ubliJLYM7oRKCEJzl2BQhLR2vQlKzYLAL5JvvsA11Syrps3oZMNq3TQy4 +HNGfGBSOgs26G/gi0Rdm6hP/gylYErMpf2WA72ULhWtBnZnyNGg9+l2l9kwdrWJE +G+hqYrrJLNDYKubNop7Lug== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 13344 ) +`pragma protect data_block +UfeheRgBRxdnaqiFTvEeC0Q/KuH9TVOzWZxM4U24sjhn2RQRPREHerSOK/3qaI+x +rfDb0OaF4D3GaMmC4S41VrXRwQmIRu52ShkWonVwf2z3h4z3BDOk7s17R8tzX7l+ +imJotpd8E+lOr30U0BIWTBbWIT4aZJ2hUMAxkCa6/g0otZNqObQenri5RJhQvnGA +HjVhegbZQdLVWuGH8Y85Vgi/+IJ9k04gvp8SpV+dgp4DF+bTcVVqMbz8CCC31kTD +210mJOvXnxhbyhikFen55GPZzqrg65Lu6Hj6zEidaqJNKcml9lmq3bajxYmcezEz +8yvSkxpytQMgHTgZl1oHypPxovxUd+l1rD5zJShPIXMnY2jybKvXS8l7l0B1EF8U +IKZnzYJPNb6HEQ81PxXaD5CexMQqth1iJXDbUuuA+sujmc93z0Rj1aByZAEf59Ms +9uQhUHBFCMEpHndl26JaBW8z3ApFpWVRfo66UwvQ/PUCvZcNv2GVKEm9wsO2yjPf +ZNuEK+NAAxP2vWruAuu5wW4pqk+Qhp0z68wgv9yI4j+KVwXs5weTTyWJsh5j8XAs +iYNYd5OaR17O2IEfKQ/XDSZlJzGjQt68XkM+VzHnULQ+jz3dxFCqL2uysExdEl+m +nj3uY4mSrPTrSPHVIrPqikhVtWfJ3QG+wGlbKbhKt6Glre3gJl6tw1HA/qY4ZB3w +YtmIrA0hx/zWKWAkJ8hrhegk2BWKj4NKtGfgu52HcOvZ1oENtJjSqI3YMyqZkKd2 +MZC7VtCAPqjuXBfPwJN5WYM8b2586IXgx1GFMQ5HCUzau39L4jxkPKVZkVqbE+IX +yDuzNa+TTlOCKiGnTLYNcsx7UFwc/Yv/jQdRXZmxL1VRSBNJEDJP4HR2jwA93Kwc +p5t320sj/7hVJiujQTQJChZhJYRjCGPZ/rh2dBTCGB0oRqSFbQTM/0OuaHrNcKke +OF1XwTBuV9BkhPwWGNK6QI1f1ulz04qxZe8YI/kHDgvqOzDtqiIH8kC3CVqU8L6y +QaDNWc94W6461Gq19w5tWWdvaBUon1Hfo8sdVP3mM08XOqNb7DSbDxPPSQIIvtqq +IlcVs6UWz7Kkp4wCy8J/sGMHDBi9vIoxk61pv79Hgo8fxhe7swnk2MBaHgRhPWI9 +MgZPOt08DEPbQS3hYX0MJ4MSoHh/zUQ5xrPdzz+JHiN76CrATpfTI87lY4ARbw3x +8TpW7HhRQtea+sjBb5QXh9Yr+ZPXQtTZmVczMZ3mpR3WC9GQLbinGdyYGM3SUEYz +pbU0f5B9teKsPQNJXJ8Y9TTG3zbC34aHnD+g2Ep+L3pG4l5ooRwfWCm0hKjRNblt +R+/5xE9hp/OmLB5wFp0Eiid4P1DuH7oojKrDpw6J1rJzJQfRIjc0B56lVw+/5t9L +Igsp6utF7TN9fNe1/T2A5zyYjt0bE/75pzacvTe/eeMpkgoQWWmzWd4/hFlhW57a +YAfG9eyIW+cAvyn4BYCEfDiXOFXBhGCfjPeDSvWZEfsAxx1hDcu4I73RjKh9JBvM +Cx05eWJzBlpo1e0A1SHLucd535MWvd8WcelDI+F5t9CpPykwNLGUxsSEmzmg8mNC +pSMLE++Gb6K5b4Rr89/vvavX639U8/4TDPVdlCZ9BNiTGiIPn8rFCKhu7l57I3MJ +TqIC0ktGVcbyHMCrQSzUNcaKRdLZPimq0/tUImFW/WPPzXnxibjE1W73cFbTixpd +2kX+cwGfQATGdpN0sNyRPxGQMYbptdeXGB0mFwKFE+3FiY4VQXNVtugYvDS7hHqQ +BEtUqbERIcNZ/rXKBCO14NcdU6ZjBvGG5Ejzidrzesjg1+9bswF9O1qLPftKR22S +1SUti6ef8ZDrAp+iBRrwOnTbo7xotdqeVDrTLQLXLnk3RNKX0aXzFAUGcf2ByLUe +RUHxiIlYeKCHZgoakR5Fo6JftG+2OJ+R8HA86fygLlQZsCJTB3gUdn3SwuxM4/Oa +sETP8If/9bkAv6IEUIY4EhTR6iQOVfe6wCLaNn6V74XSOWkVFtl179M8SxS41AFn +l/i3mCxCQeR1+bQJVOtvXq1o9wpxJf4qm62D1/a4sMDnXaVXgemMrbGfwnKpB+wl +j8cUf9lHJKGJX91RFQbA00vBHf/Piotl+urWuwf1tUFY7kAHFKy3r3AmjKW2XpOY +dQfAqh0D3pAUovMmlPWhrlesXeRaJ/JRcAA2UqO4r5+UFdNmPzaNjM6uUakjmaxQ +fRZGzF8RFz+ZSy5KGQyXRmc2O/twrKvfRlDPPwbAqijQqiLDG8DdzOxvvnBxdp8F +tByinA4/3jpoeAhESfMGUF1upkLaWAbuU0U+dpDudMxHXhVHiV1/NCyPxGsvp6SG +QNyg0UbMkplu2OFUevxNhv7FO0U3u6yjkeKsPzgBKHL3y6w+h8TBKm/hfqibVgty +6Ua/oCsYNTwktG/vlvMCdhxu+ENjcFdBSotAFIkm7fPbbcprEKmRUo0rj67EBKwt +k/s0EYQvW/L9NCLXg7eoq+dg29yeDxWYFZxrJv2L8Y2LYHLk2xnTs3qQWSYYhmC5 +A6mIUUw0iiaFG36LTUS9svQcjrEo6XwZauLTpY5SWsgR+c17Jkvdi+Do9GT2i92d +vmTQ0ukDZAQmHtFD6aJ/fD/dRtwwLPJOPPyGFbIHe46biXjW1/usqdTsItyk5Y+c +LzXlcioeDgJ3M9X2XJ5y4Bnyoup7bJ9U0giT7Oo/ZZh+0RUDQPqegyJ0Vjr1JkLB +OHS8nVXzhMMwC6Gc+x9ThGyL5pshHGKGF20xzOvqxZSHp1jKlI5FR9SGYsAvYCzJ +IegMxx+87cRyCm8E66Cj7ERFENo2jZWfqzezU0W5N0ARdrcy2h9hJQu6YAnGg+Cd +gH0uiRsxaFmS3DSS1X8iwktzkoAf3gSRKQxmiz/PP1q85murCy3zDkZL3IaNfJbT +FLV1+daLO6/rvxaDorc94xGDlc9JEvgcg+p9SAtZy3vjL0JLYM980cmOBlSsRUj6 +HEGaZoZ/sx9Y+nrVPSmM/LYVFBtiMGYQwu55Tc33UhSg+E0r0GsjW6FhPzsmzw3n +GdhKxFpgm4QW8tKuRCFO+0vo8fEkuPYp5/3zm4gujtyNSMMIWchMp4YZkpr6XxeR +PJe43rQmoHd8Mtlh9OpvQR8w4Bacu/4hnVWfdNKgfns6EqOd8POS9zpPLOufrULH +WZ+ZxUjzzf0tNHN39Bz8YaAUK3tCEfHvnoJd0FzWAx/mcX/xRHYsyaCb1a/EQ17l +kBsonsvYFL0dvo7vyih+VLLKE85tvDDd/Vb9sD0Kbo2KdhnVVZiFxIJAgffHQcZX +qHnDBQ/+adozZqVPN9b6JwBETHxucY3uNIZylEVYzFfE1bsoSUJq0HvvL+Bjzv8+ +A6m8TXGwgUi89BnN+fZxGnMFxqz+wRekn/bf7JV4dR6bTTIHf+2QwAXcLSI1F2FT +cL1V7sXxiBiVFix13UZRMv+Q87VZG4qOaYC9z0hRqSpKq2nOhe0WLdN/RI4mzEIu +m/YRRqHj62DxcLh7OiMo1itUQkC9LWwBDa9eRm3MXFYR3qQgjbG80bGRVDnaNqNE +hvosDePkFvco34zqhI/RvlhU1YuZM+yqizbyB/q1KnPv0j7j/+DKEzAXUruQPt8O +GdvlyK1i3+SthiycCJkCOwgu5agV0ojvO252TYnmxs11pBqgJQ9aFVlmMqlBoUMe +J9qdDEkFygQCO6ph7L86fPNNXuDmM49dlnqIJPUAsv0wX+/dWpweaZBAacLbqI7I +62PvkXi+5KqWuCiKmhrqJsRzI3AuPvvBq99mBavpN490hhKJxUQBSMyW8GFgqLPR +rv4iNIHUBGeCqACJNnEZS+Q8LItr0EAQY5oBtoBW298QhQ2rQ8s7FkCiSjiYSpoi +cJSkwERNUwS0qJ1RdKXOVp5e/4dvkq0L+DIoYRvkc7sg6XQcGTClRXun+J3T0ndV +n3l9zTDcvLveW5t8VEAceWOYm8JZ2dD/ckKq7nHBs9CMSl5o6jxVTj8ZqT153M4r +r6cdcGq0h32cSsiNAbajCqPxesHZQCRc1XotGk2QI7nB70/iTi+wI9EwWC7WRyUB +iF/4wMUon/7tK4dNiR6kJHMLbsA2du8i/iLRPgM+Toiwrsr+FWvMICX3sVhJXeqN +1raCVZn1N7LIH5VWQxJlQvtCr/IgIp1NeMxnQvdmPJQcb6Zuq4EvWiWjLKy3Wl9n +KHUjSeDPv+bhTV0Xyna1akzlp5hniR61LJcvCEdpGeBtPgC91QgToo+oe9oMYEgE +c56kORksUBVAmE510vttzoZDCEdoepc5eH4fk/+LIJo2CDXPEXzCHMf0ugTQsM0Q +3u6FiiVfJgfWjxVFBmb9vEAFPFGztcItZPbaa3YLr8hvAnxH0q6sSzPdO0v9KAq6 +MxrHXxO8CjoI5JRH4cc2hPWlnlq+vht+KhL4qDi2H29XSUb6p/8D3rn+NoKZpeKa +Bl4ARM6ozyuNiqaNTIoV8EVRgtFWCh4N646xDcK2HJMz8Kplslc3W0mgVGG2C3fZ +Eh30V2h27waApHHLpfuoEocwOwoi5JsLdqmVnS3eyQKB9+zJmcCXvxECn8lFoqQX +2eLUqkWUYPOIYEoVY4sHEr+DJYnb5b+DS0p0+mHfGcATZx5i7OlFhMKvTSZKeb7d +jZnI0vG8FShOY5voUfhUvw7giZywuDzT4oEQeNqeKEjlxuMcsw7DQD7zlWB/5SWn +tTlbIzv663KU0tOt13qXvqupMnzY2+gcPJPrO2cFt89vBsP1QgOYKZsNvamzVCs2 +83XKCrFC5w2v5UranTu924fAcmZ3K7mtoq80llis5iC+yc4hrNU1uGsntt3V0NQa +V6BborwU7bImN7LU4UnuJ/gaqXKvKZ/eaDQhNP3sl72t/ZJIsRkdjXmOnJjJXtjL ++lKh7R3aOX8uFuJy0pXzvNSV+zfUq+12A3Ilz4DkpMCmnDDXPopqbDuYZ59aEMAP +IpGnkTyQ1z2mkjVH8DbLNMuLXR9E4HVrZPpUh7FSclQfkUNaSTgsAtQgZbasGRCM +Ph4sQUxWs0tBLPa9faFvE3yj3R7XOvYsrRX4s4GomQKh0VxRJm5x/W0YX9OBrdes +ZQF2dKmClKeoaNBIfe2jK1VNdhSMx2fGoGuvxl+R5Ghn8Yxgo27yiB2AkgGpd5ye +flLqRoQEWokRvyBvOvKsmd3oHaUjJRtUdid/cg+B8xE0QKr/d2v6RFOcAshMOuM0 +cQ5pTAVQbsBijB3E5LRYMm5bzMYvMXg+lglFYereYXfu3g9gn/w9m0lyuuBt1cnL +qH3Vrf1q0tK6wIEYMeKLJXvFmmoL//VtUXCrwlGeg4kyReEWABQCkVGqR9RX7gv1 +N+O7M5RTR/RNNJsU/Ut3sZsOX80YvBWwBQZWmL9/lwmKDXrIEy4Znoa4aMpEY13+ +mAVdlFgOCU+hZhi7bndKeGBcvN+rSSmppHNyOkurIsNmVw4AO3gUPcYefpUTpgms +X/T+TG+ZX9xRz1eHT9WTTzdcB5rhZ9KGQGs4yIA1vRAALZfUTIMVKojHbKaLnOk7 +NLa3OvyS7yAUDjgsN/xMLd1zMQ/Xk8JtOD5c65VuO3NPK6gEcdaIklQrztAIsZ5O +Di/UxrgdUOjCJmcg90DQfZRrU/SkqkevdvwL9NAudyDCbf1zLKpvdLyfBMA0WTEO +hgirEBDDnXLUx8gLMWbNKky+v8MHwbDv1+m9rHBYJawNWAI4PRNZMaKKXSEAJavZ +kW4VkJD2FVSrBpVWOojJuRThdCxUWgPC6FLkALviiius3FyrjfnGGDNV9ApmVq+w +s07L3gK5p5JM0b+zd1t5GN/PbWDtg7KZMUoGDC5mSnOxLc8UOJxalhh5v/x6kef8 +kCfT6zOp7QZ0FfcYuxKAW0AMEe0FhUWT3sT8Hzou5PFJGkVHwsY+gIanNrt+Zgc0 +tC+d3ypia2HNtcajcbO7fDkvxMHYEjFVgCTw+PWhItvbV8NroBPzrUCUg/JE/REC +eFS5CwuryRc1t2Hdqyo7bss3NEgAalU2k/kNL3LOcLUW64FfIv2L9VqMhUPLQ6OQ +D07LYtwWEMQQEdHacGFyoz3UvPJMtyY8r4sC/A/YHtLIFZiid9R7cgW+qMV7r2J2 +qMwuIP7TG2KuSBAds3c1S7TD2VxHO3qY4kdYHR6q0O9EIwTx5mUZ05ShnOnn8Wp4 +w4/+dYFT93DuIhgtiQnFEnK5NjUazPNiLpTuRChpBbFCq5Sb6w8w1Qw6Ht4nxdj2 +no4CwZE46W1AO8i1pNtRb1DSsqYCyadoap4/Hu5NACyC88c7HhAUH4r7Oztg9NNG +s79zq9AKZAw/UW5Hh6LnFyJrjHD3uayA1chRnqZtr3UY4ygUSJsQtbhJp3KgMPw0 +fRwLp4X+chO+wJnVIuTNThQK+DvXsmyWagYDkhYWFpTZleBZdmyzeaLvdQqkI9Ye +AUkErdIEsA8qFvhsLdmsgUCDCIOgWd+C6NUrtCamExDXRGI+pfyjOUfVwHTy+Vz1 +1D4FIO8l23BuhE9pPNMp6kz6cqnQCpxMqy/tHPrXZzi5YFi0MMb3l112T/AVFaJZ +aeESRiE2sPDcLGxzvMJxfCTHTzmaAQCUfmgHflpJG3WoFTkq4ZiE/ET5WgUAU7Bn +XgmEyPIRgfwzl4GnckztYJua0TX59q7rv4B3WSNsZ26jfphM6Jrv4KKuWD7qZt07 +lflAJAw/QguEwvW7X64Th5OlV4PaIaoGPQ8Sg0cAYONYAZg9shvM4jgBdYgGdnM9 +FHW/Hlv/xKQ0qOuWXp/tEkvzcrL9G9qa2kgDy1b2qpZTIjEQZLiuE5z0cNi8nfKl +8fpBGanu08A1QDSgJHGhZ4W/3lqJlVEYYNfgH2hXs5e2TuvcHIUPC6LFqPrdSWyE +Zsh52V6P798eGWqWbCoTdsh/Wp9z4L6Cu6P0L4UIyLaowORhUXZh1bBlQH/YzEDz +HjSQiQ6ZWgTwUhSidzOSGsn50pZaBifsOfJviBtSqpGHD4bIXI024zOxUR+W0vEB +tCCzikH0jUsxnwNlrXIrkCERKnSmPPxL9Yrwgns+IKHOTVS7T1BPH+jBYCnHEZeh +XtSAFCnCJraPZfQzkchtlmPYIy4xrxeq0Yw18TYCeh9JZuWriV1QSoBD1tubI5VA +cB8dzbXwozSXUG4XolRJjMMS2iIyFFMU1a/8AcdazJyYNYtI3yfHDb3No0iIfCZT +cioK3jjNLveH6Yl/moXU5wWMTffXAiNIRQjyWAcGkHpc6vO3eXcTLQvR2K3hLf7U +bC8WVo4F1Bk+FEZs5UbBRf/XldNVB7xpnSMbaBCsk0dIZpTNPkIl290AkZjqf0F1 +tlIQl9Eexnjd0Kv6pSiNDxPcWTd6kkCi1SaR1HAc4DX2D7yLjLl0tYw8TWFA0bN6 +fhHpP7yUCVYsfKBfmpySCPQRcloN2zTvk4dM+GXI/akAaa3kFRqEe7WTShhWss12 +mMa52J+VzPpinEo9e1SFtrbd+Ei2Zv3OZ3cuxAksBAhRZKbTxAsWmG1fV85YrzRE +yZ7SbVXVA5OVMNVVbWowb+PntL5CbSU/juuTh1rWTFj2KzM/+5eSRVTlMWMKXSKy +tTLlQWjlBGtMmtSF4zVUgKNAcmBttUnRwnroCCzTN4GlrBq9bI/hUw1h4MJAlikA +NBZzByz72RKVSm/C5k/TmpHGSKInm3TbqbF7V+xQYpgPXOxgJkAz/6rQi5rcAYjH +u5Y0R5/0o9Jp3fewRPIdOYkIL7/QAGXXMbJkcc1fUR+udyAMZLUMPv0J2KZgWk+3 +gUGk/L6+Yjfxw7mGqhsY+1wGHOjthu5mkk7dXc7erhsB4IwI+svFKuJKapDj+DOY +cFsyGkjEknK1R7FBGVipfiQtUj2s7RitXXz3zaseHlUpCXhKPLj8yss7GNDLql1r +1bSqHvDXMCVP1CLLiMRtt7OviU+LD9hV6a+0Jc4NBegg7Fnvrg966RrfK2w5knhS +aqhTVeTzEy4pE4Rs0AAQ//KqXSUFQWZaP3fPBGgTJawVXXszreVNHrPCgfomWDz/ +Dg6BdhFLE623A4NpoMGzldZYS2fkZMHH0K/Wzf5Yf6dbikiqIhAWLnf4y3g1ZGGE +8TXkIRjqzS+8BnIxtZTDXgW0K+IOnOZuhRAkTAKhLnfsfotx4fGS4EwhXXn/Mimi +fRJvfoGKMP+dzJo7fsIZVJrGHJ+Rygqmk4RMwjoEpiQrQPaHIxWzNDqeeBaC2GUK +wanaEngiid6SaOOglaooQ93UTnbWqEOsgUv8LWvBcEAp8ImiVcgZ6P73JJ3i0TqU +fuR/63QG3w/bkjQz/XUlGT9mj2821tcWPiPTDsRK9T1f7dIT6eEjIaDvmGS1pMzz +3oocfft+/GrlybpqzFUmNoZKH30VueIbTdTgK3P+OVp882bJJnL980t/yDmqw7fm +EctJ89VPH4bPXTmHxB5vooTnQswWsOaPvby/s4ltV/weydAQNjNs0kxlxzZ6oZTx +XkEdgGc6M1z7fDII1H3z8jZY5+mufBnc3FINQIzBsLJ8rzKdWg9JzvCD+8ffWzD/ +7HNTOaxHFPqyejhMKMWX/rp3VqhkIGcfYqE4h8wDYP73u422YzhhceFQ6uRfYgTs +atU/uezDfSy2/j0FjuAWCQ/Z5xX44VkvWyUC+PUrO2uuILUgHH19UXP6VQpjxwv5 +Lip2Dt+TDHzkbgrOD05izPoeGZIogcW1Q3n+N4/uQ92qwNI7L99z7GLuSdFqEGwd +166Oaw3vMnLkN6gEMX0QGWnpHXbUxxhLlTVEOWli0It9Fmq/BZh9hihztmWoAec6 +rohxq5mluNwYcc7kagepVb1n+br2nG21V83rAylL+ZDDCy8dbgai9mGoV8eGkqXM +FCXP/OxM7oge1H3koYd/Io/HrQTb6TgTNtkf8IAM2EFFxnGxdrQpeo/nPCz/yOcT +EgQKEo8wPUU+ERH8QHbBGaBCs1mEdp6TxjZakVLd7oLBXqwj+XNUcwnRAmRxN0Hu +W+ETPLIOJX1UORecgHmBss7VBlJPIasYod9ohdaDiv2L8rEZQTImwh1Nj2+8/zeu +1bdIIRO27MBuJKH0fzzH+/ePo6QihGhTQ0JhgjewRdN9C72SgR5EnWKuZO5nb8uc +tb6/iAJxsIva63tVNshjCO6V9l5d4hJLCux60hQtJSwfO4JX/zBF4QQbTzpyn0Ff +vVGCJUw6cu0ytHtSvvtrJlCUuoNv4Nn98ytxcml8nV3tCMa9nUFU3xGAHNbw6rHN +WuxWc+h+/l0EBUHutuH9ipG7MX0TzIg8NvhoNsaAasnWmkP269IaF8nVudZYks8z +pki/gP9rLxnD7ZBCUGj/7c+AjoDPgo+Ml4I56k32glnGv+DH8uio7FfBxvYcU6G1 +dCS3/pL8mV6nq8XpRVwEr4rAixKSxeIMVGvFtzcUePCpZpjz24YrlrLz+ugJiC1f +B/95OFC6RAhVZETqXrtE9cQMlTEzKyNVBs3uQp203rMdQyENfi4FSKjlcq0K8lGP +qO2+Tz/IqhZksaHKnIZ0PRvrgTa8XuSVM+2X8V3rhzI8WLfpMyJhml0Kit7vFQY5 +Cic9KaWr0iqo/wl7nuRPFwfz/YUE9Rk9P6FhsBkaHKE81Fy+o0qdiZJZwSr4uh3P +gdebEllOvuCzZsN04TMGrjEVyhUHW3iHtp2A4O5zjnzI7PhS2Ev1NQ6D3362TTmC +7q90a1hQTa7T0cBvwqNvq7vfg+/Ek/xCrzR7l3OxWHv2YWLAsMliiJMK8hR8uhaA +NXHhL+v6Wnc7ho8cfoVie3gzWzOmh8LlS4xGws7HO3jKoU8IzdrIk316/NQgVFA2 +1yKi14nhevBVv+K1SCvzv1BCMlJMCB/U5NxUX2zQEsQ+6UiPJjjiaXqmkOtZNYxw +9yNVaQ5FlJgsUdfjXfggQ5gekuZMtr+SSHFljzsoZXbdyosHxDdNYTLqlipqujMx +e4TdxbDYlD78jnaMqjs2Acv8xGVDt+RmNuOUqOCc2NIVL2UsxWwpDdIIJFcB4ECe +p4A9Y+Sn543tzz6fHfoVoWxVshP+DTY+I+d7SQWhQYy0RyH1Kp3f3ZoqaszBiN8d +NCjEAaVgrot/fDjhk+7Rj1ties0OE4PSzg0cl8ENVoksi+pFT80tcij/JGFDtAsv +GkRZHbW1t9wR4EAIUEVWLhCeYCIzvA/GlZFuWFKVN6sLyH3qghPoF/C10YyITzG1 +cT02OZ+4XSseGPRI5yZuHWJC5/ZQH+QQKzCSijCSjxGTdvQji8qkpSdDD5JVhmIv +0lYC5Z2n/Fz1SoCbNngz8Fo/IIEW/QowxJO7cwO6h3KTUbDlj8qMCMRvImz8kBC5 +7VVL61JJYf+B7xXI6H3ZSekw7llRvbGBY8Q+MlcDqxMZ+sAaM28XyaVb4fnw5Mog +jqgF4A7ii5M7+6wsw2ghy7UiR1+2A8Je5GrWUA0Jd8oi63RVBZEdCdVAh4fGcrEM +NeVZgKHwhaNIFisq1Z9NU3TkyhNBgwkAtzKrpkUHkuTTvvF8qD6dgW/FQSquqnWN +znCfqz+vYYgykBUmqiAkmmS4fJRKNJCWw3enSgxRf13Qw218lZLtooRmqwdaPiTD +MG0li7usrgQfpGkgAQGENkGplnMQIvbc0rOffCkqJWF/pouicjrWF/ARBr3297ko ++r9fimc05rl6zS4f5lRFxN9pejDlOq+/gnnmdGpWkLl23jNKffX9jVJ5C1ioqZVO +eD2uVoDRuHQ+SV/SD0lvMMxgXA2l/KcCgpf6KJSbYykwlU8llFrw/OiOFT08Nkkd +CFZkbfpHx4dO42FdaoONFF7Z5VZJwMqjmf8tfJfUSBsLwNVkZ3MyEuimVg4yq19E +Gq3ONm/vAQY/lURhtr4FqXsEDlm+NXNC75PuxTXlaQErR4rYs1FMywMjqFzlj+60 +rezA325w+t/hRsRTMqjvxG0CZPS5lzK6vlJmieAbqnuIOD0YAUhIgTRjCwubvSfJ +srGxoQPe3mmFTQdaTTQtmY1nQS4jiVG0xw8EPaAczwKsC+taUBsOo1QTTXPJoB1R +sgr4vUGTa7lUXg2Wd0yvb/R+PDszLID+oa5EHe53e58n79ADI8kwJF9Nkfpbbu0z +7+kkDKnRcRAaycqEnFodZRD4uXPR+DsBG31e0/JgoMfB6QVi/rUnKRsBzcD6YqW/ +2JT+NSDkP4+HGaFb167czavR3rOffv1Y64QcgBVjQM0eaQ/qLbXr6Jc1de9lvS6y +bZ0TvcbILMVHyHL5rPbEqp5gvW8JXgI63Aj9YkEq8gUH/zDtcdER/xBOjWh2xSXZ +BYn8rJ6PWEf/ezHaYQhB1kAFsGmkSIoIqvtxDPdXxv5qkPIRx+0ZESXuZ77L4Suk +Kutd638YhdCyiGZLWetsHdgFIz/QLGVUvtBto4Jxopxs7uQXFMPGdZD1sw4qIupT +fVFFlWEkKyE0pu5xhzNwZqbJfhuDD/jjvTuyGAwwdMLGQcD0B3BVpxP8bqYULASF +V2QLvCYYccYcItk0ZGnOjTO9Yv5/5uct/piDaMr2/Hoo9KmvLs+QYr5LE/FawzaE +qm1h6ExBafhikpOl3in1MJ9zdWwuZ/xC+CVRPO9sL4NBxU7hNL9H0HPfo73Bss32 +hjhE7+TFK4RTBTLmbn7JQhpc5Sk9fgbgduXYkTWyBMjODhxfUv8MHl62HqTRB166 +WuN9Lh61bvKtIQdo0HkcOCFOV1sVWebolQyfgqIzeEGMTs3wPgU4dTYpijrMJ4Sw +euGxAPvKVaOHpCzwDm5RMK5rHzVZwi2eY0PysITGvx4hgEfU2njUXnQeQXphgA3Z +75wws4nQsN0492G5B3SUeUd+dIt7CZFCCkJQJFrLdHQz/Z2Yin/abA7wxWQa4YE4 +dzoZpOx4vqG8PQMGIQZA+u0SCr5itDRrLh8PxNz7xoMtGH4Iev2bhxrKy2pXHpiR +81q/NnQd174tBQ4oyZqt6rqd1OKI+O1uJCxFOJWIBK6jcszL4BrinVROuFVpzzZH +vekKNGVZnCjtzzjTk335gxvLdRM16VCdg/IhM/ECMaeCiEqRP142/TlqfPizLh4I +j3ycoz7JqgtrYK07nG1sKiQMQybA0QX/9+tie50a0o1LoVlZvX+0Sg/1meaCGJyr +WKffy01WQ4CN8Ed46WjTb/yF5hyv2ieKPBf5U6d/GKiHD7aGXrW08Cae/cQGvi13 +R/udZZ8vlQhcUgJQApJ2/PQVdL7QhYjMrN/YL+mQx4nPiyl3uoxDJykQqyLh1sI0 +qry7w/zWpkemZ+t5vy28XHlmQtuR3D4qfYFt1o63SI7g8JhUqXdcYoFFYtSlvWf3 +/gRAKXJpV7ibs0PBQy1zqPthgQyyao3tWuEmVC96a+j/IQlKcql4Nt2zwkpAKa4j +QnWxFcORZAOj3nMUFRFXIBSRpgl6Av0TQz3ljU2WBL02PafDowJhbMreCQtuLcnQ +uwMq0LcujFFmmGgp469azJSoGLNv2XPcCWZ618KX9CBxDSOzBA/4bxtM/9XYHEYl +FhbqBdhEnqcZXg3bGmkh1s3KfgJD8gp0sFnV6JH1IbIOArBWUv0d/F7o1TY8Iizr +ZQNpahHEGTReBzVdbBxbjMFA8RY7nOXCGz2az/qT8NvSMi8WZrmGbDIKZXrmACkT +CgNH3JhmYEpMfO/GxPplHBhahCuvwEuCTr5hGsAEeFtyZR8mqy6/UcezvxoVJ0ge +hI3uS6kcM+2dQkseirSrdxvKKNG47ua1rbL2Lnzyi4wYPiKH8HqMix0oy9VXTN9w +T7vObW9Ac3cAJWC/jF2F3XX3Zd23XIUwn+WoOzpVQNaIqXa/U0kw3PHAoi7MZTIb +p4d9Is4uReMyUvU7KpURP4De4jP4vmPH6D8H/cqM24eMX2HHVd4RvPC6mKIUGCna +ElELKsA1FZBKTOJJbvSIrSztQ1aDh+CQeTh9ey8D48ajDVY9CDJ3EXgJxvtY/BtP +txRJ1ly2r2liE7yKZL0KtN3C4qdYPmqzsy4oZYw8BE9WdERYFh37uAHqs3RV5+HH +NKZ/zWrFg1Q9SUxKxdZsY/jYlQiqlMqT4W266aycaZcWg7SISQ+wQCEbVT4sXmKN +KUPj9YQRSJdXHTGnQd7c1sNisBqY3LN0hTCOBna/eZcEgcpk+gf21mP/HbNPUmjc +moCOBcrTpEYkE8obdwTVMbDI9BCZvefSbixbj5VbX2ThZmgWLU1WOCkQlJk0CH6m +CZmtZyar/4TXjy/07VvLZKUWZbUsQBLxWtO4VtDcV/uZ0myk7ZSBLzGSHQ4XUuoK +rqcCGb8TGp1YDzc52EsXIlmkqIYzOd9xj7Do+6+m/hRC+i2IdWRgGMqZ9Aq3yLSg +04GL3Vdc7hiiWjzGqCAS09tRqC3uVm0tIoDg5Ra7XbjrQKcTAjOAleUDNf0B9vYu +Y4bqyxkHFIQ8CGPZV7DWv7IlEuebcco8xJN2xcqAqsRSZ88EjNo1tTdDAxpFOLVp +2IWpoItDSSOW99hbNyyrIKoAFXF9ZdF8bvZAl4jSqtdoD5dm7xabP4arBEiOoGIy +RUvsZw8fYqtmOtkKjLYmGd+wAI19YVlEthJ+XTZwXdpYZ1mh1XMa1XFeJ/yqjK/x +boswjus904A6aR/2l7Irtwp17l5luNW2ZMueAouDE3g53s5WwqeNrLXr0shDu8EI +64pJB2jBvLVuZJyluN54HcV4O042LwZWiRaRxFzLUwjehVvkha0piOnshULmV3w0 +4ymIMZF4MtBORj7mOD0sCH4l+9MG7oYhfFjoM5ujdmkSH9kPkJGbjNZRLFPNDaqT +jtrhRwoYFlZnRUfpl0Euj10AMzMgObCJNU0L7CvIbvkw3mkCMfyT7U/y1N/GaQNl +2KoO8E2xUwf3tyEpJ+jvyvABf75KShI0Z+nBR31uBXRn9UwmKrhKdp1WP5fVvwiZ +5WiTrx/UGNSwZ+LfSF0IR853AwmtNFFvVu3OS1fveks7GF+MBU9AZr26A2Ewjmed +Vzofs3BZpb1s/LMy1W2spC8OrJAImwRiWpzTOsb7uzbJ+e8/5316OIiZbHB3Du9W +3vnXKIyp2dzhM66rTZC+UuLwoUkmWmvZnMPbxGZZ4OCt1WalwprLpJmxGAJjA6xS +jNo5t39oylpOaBBIj5Kq6At+kPOwJK/mSty4+5TFHuV+fdoppI94sCEuz9LBfRUX +SEuK8vCWSTxLv/E63wB5t3uyqIVv3okNNWWBza2YTG4I1mHqOYa7qy7+okZ0ANFW +tCEKSEtA0ypQt3y+YIVzkrEynX8kBG6EWSIbpVIuK+rDGs2FYvyYT+dW1x9kEQ+v +M6TPjBgiF5wMU1DecY4qwTNTri/fA+MaOaNFCKKt+UTPuxIno7IQUWJgcfbhJWfV +BdkyEoeChLiAHDIRal5T4wUAfPcZIZhV62e6F22FjOR2C5WAtBRWll+8Ww2WKIml +OZUxJj2am94kvMk70oTc2QYgRoZWiYWDZfPbSBslUYsl+XPyQCT8BILJB4lrGW68 +KkWnPO2UjaBjOdPkZXjzdYRcfjAfmxSrSH8tiyw0zUZpBHdAdQw3tfE8miFOhTKC +sAXRvkyMoMnuHAimhQxMUnRYIvXWLA0ykUbGoq4T3TyQIB5qHLjceYS4cW6GFUWw +BEQ+2BiW6shiH+oivdsaxS0SsOSl/S+FxW4SsHCz6x3ZDmJLVFAlkQGtm3kycQmz +IFVLYGpuhYBjujZyh4IHHaps4ZC/vf22lG8KPc+TruuXv5J2TKLzsiIKSPqyeUvA +oVhZXPctuv3r4xcZO0YDuW6VtjCbj35f5RMJPrZm0lizC0fhjr2o3vdnyOO1jcID +dlMVTwQ1hcG3CTPRCk95D9RyC6Oh/WVtufmDqO0XnJXbJAgBHU/Q3FSDaPJRdWU5 ++fc9q+g2TrN9bCQB2UsMW5dLkeb5N1VANv5j0moBmMxT9/hJpwxmoJMWLJS2wqk9 +thHzT12yi0J24HofhDVD+gY2KWw0iD386OnpUbYO0ti8uRpfp4B47Zp+xEQQwlOW +l58a7+hnQ6b62l1bazXJCimB/OVobOgo4pwXYY+Wt2b0CML+iVn07FiDF126edx1 +bqnWY6L6lzKnIfcKWkeah3ZMo0cXIv2fXboquq4K6CQNM7HVSNOczVeQcfPhfP6+ +Oa1Jv6QM5S3gi4WjBBhROR3SjDHup2ftRQ1GPvBve6dMZ9jwDTm590AimGWxKJtT +AeL0qOcmL6JGEgL4JaX6qbybBV8cPT6ZT1rpDZ/69qZsyLi23Y6e6X8/Zes/9HGi +tJs98BcFOVP+k/LZvWwB1bb9O3keeMXIjXMpZhomWK9GOPalRS3WYVOd+IF5y8mC +HS1ffjhaVpwpH8U9IomY/1vh2YDu1PVm8SDEggrnKnI+7OcMM7NIcxZk4CxVpPUx +HP61pqH/li4BLt2dwso3vYFGLE9E7+SZi1RVhiouFHXkwM26Yh9NKCDFcMiB5weS +UKK/6K3GUKyLxigRD7MZXlnF3sWPwkrA7DJJnbQ/3PMK4/kZT1KqTijXLVPMm3cT +NdXTgNCwbv6wkVXlVtkP/sP0YHZf9VKi6UxFet6F7tl/uJQRghnA459MqSrSs5yq +YyKJgp4GphSOLvPZ75mEg5NrMiR72xBTvYA6jxVwy8/RflHCrM3ift+K02fuKm9t +j6T5V5XPCT2ukIw6X48VuMZlRtWrtnXw58D3tnnOsne80rhQfWBAD9umBGR24q7l +q345o9SXTqwB3JTnEzrrakB/65PNVH3VqUDnlPuOxTlMqgPNJoCp3DjxPsw9UYr6 +vPHSOFdwU+WJ2rBrR78kV5Hdx+QcmbRMIOaVytbvWGGumu/Susso8EUUlSha7lVv +iQCG3yYU/UwWojBb20kEO7ZtySUgTE1GeX7GnsDomVg88bAxwweNiA6ajGDE31KA ++sthyYTjFc8BFGJMvZNP3Myk2LA6xBE7fGawPqaQaA7KLkUNu/eUwXg/3YAwgHEL +q854mENUOoVigUL80r7cIwhaMYdhNnrfFL7dbhLrIkAHx3Y80GitH0A04fQGYgJa +mRhpLpJrag4s8Defe8rLwxBIupfTS9+rWQXY5JBdVUFyO11GnEWGogFvvGR/7ATu +EpFMXh2f8JljpqrNl3CLFojZEx6kEhBFDmJV5yCGR3ceHMCD33uu02S9fuTmuQz0 +Uyr9Q/5xAbctKJzjbsbT1fv4y69259A4sRYw/PtWsJUdeH3U8rjEeQIw3yOkQi5s +KO3rqLh22T1mYp5ozTH7cTsz29xPYiEixqUZZE/NRVIuGP+k/NKd4WQdtuCfwyDn +O/QbxsdFpr36SF30z4C4EXOxSPWf+Skfn5c3Gqf5pjYcsE6rJgisDzYpppiq5x6c +iMfcxuAKmI1vAgrM6vKwN13j58icozNHRLjpmrSgq0UcAkvShLy2fQgsgSnE/Zkj +9bJ39ZYmx/WYeTOU66n5n/RXxXVVwm4A1j9AyuG+xoeIt6GDTRroDMZArIyvtCUO +Mduj6RjgxY0Ju1F596J2v9l0Auiwdwq6g/iNXz/J2IwZL/j0pMxVc6W11Zk1t1Xi +S7fW3xD/KFWvNPDeb0+wP6tLLaZp4vBnlckmkh2r49/+6glg1GvPsCK0zdseKbQZ +CpvUnz9gRxONxasd8iDMx4XP+cZU/qt24Yf1N7jT+SRhnVBpNw8hD2ARxNHUY5b9 +4EjQoZcw3C6NYSpZzbqqqUtftIhJAeewARw+Q5c+BBLtGTuUd7RagbKBSOouSNX1 +259lwPs2AJiCss77mpd3sJxhXrGBDGaSb5DNpftM3UAmMsWaY1vowGwkulWJmP86 +jp2VbN9GCK4IoGSO6iVNb7o+x7w+cwaOBfFXFg4LVUGLbqT/LSi0O4+y2mTPoZi1 +SruCYP5KmzAqToixBjl5l8vrDUB/paxNnDSOCp3nlPW6B7572K2DNCEYUpEreYAW +iKuOiiM9a/ikJau1sCFhL9PJ65WqdLWeMSH/6jf7peNsv2lK35ucMksieRK2jfHc +NWdrGetAMlcB2rVu0xiERh87SWP8ArnjLJomTpMV6aKuTB3gxhUkExfWbUQDQtA5 +EYCy+NPSfAPaLVSu6c/WsnFW+VwydK60bL+kZI/Lw+uRAGwF1RW05jYpAREDhvWm +C2sVIAXnjZ6bAHaLVt5WpJSmhoFoIrXOvX/2f22cdUcPxmi5r3N+am35jyICj7TZ ++foK8hpnT4uQF5gqaMw2UYhNNDribdOn8W4e1CL6p8ubP42dgvvPECvWRI8/jIhT +bHWKZAMhjeBxSBCiFi3GczMfg82lcwFBNrHUDrHBWhqwjlk5SRmgsDgnGmDBaRdn +OhaJ8qX8XkUMEXsUaTDC3VeXK6Vcw41JaOG5pgCceRjsGE3KOM9SJkOt8gl3qjV2 +4f8PfPgRSCkcOdRDkiDIQh9TDg4CK3Rkb8wYVziLfZHgbdLVrlJ5PM2lp4OGvArm +bU9dk4oCzdHAoEIys79FsuDVOLSdBJP24p3MQLLZN6P2XNSZ0WcL6ejN6XxGk+2N +aR6iwBUPpta4J7LNXNMeH4iEFgj/IfbtHg70zFk5ju0gt5AUyKRZz0wYHm6u13Ui +okhzQUM2WzLAsdXyYehTUxz2LJhJSYDg0r+d1TPTrXauzh/p6vMwZlh5ucaHAPuH +MqIJIgobWRKECbX0m3m4cLyNU8CBb+4H+26eIskpaShxtGpbWCSBjVNA6faG+lB9 +LdONLxhGhir1KpFPgt/O9N0FT37KiW4zHFroj1G8fHAmaAe/jLKCLb6j44P9psF8 +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +Lz6FbX/pVyGiIjjEfPgmiw9+t39Y8KY/9do6W/TSCEeKEEctN2g6bJQE8v5nII51 +HQbGd/vhbqxxBCE+F7odeXY2yLF1W+2PypPquLqJYyk7NUpJl/WduF/X7kY6MeYK +Pk/pHOnHR5bHZpq4LdjlBHexIla4ytk1fbeAUNpGqFXfdxUKHuhg11fsCHtiL9Dq +e1yEAbHO7lBU/2M6Qm7hP579EJ0mRY+Ig1KTH78gvnGxybc7j7db0iL8puxUVdPP +onAP5LlxeZuF4UycDVI368UfvPX6c7VtYauZ3+gl64CbFKm4PNUwhsB5RV8Vh/Jy +YgUU6BkJ4rwDsAJ9lWzKTg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1312 ) +`pragma protect data_block +Nu8my/ZeIqCKlm3k1LIhDfNqSTp8cd3KJe/bSS0MRXyvIthmdoUEvoeqsfQOFVfD +pp2eufeN3GoCh7J+3r+Phu01vJQLR8Xj6d1wgx5lyrvjCOUmFvFFalaBgF+3uAxT +A8NiL81w4ArWYfTqfTtii2tDTvcptbZSgg7pBn4ylCLXwufQOJfvBLB0Bk8cG5wv +sXg2J3jZyB0MrvgS2aXEE/bN2JWct+PKBKNfUUlbYEJmBe7gw3VUPrBto9CLOHX5 +nMPOUKtz4xRZDz8X6YB/FmBQjGMfR8Mxn/2IeGbmZG1jK6vKjjSIfoz9sPybFavN +V/vmHsbaTqB7PJLQZuW/Nk/v8ghiZ/WTOiljvFdHiDbUpLL7O/DBnNiHNZrIKqRS +xKp0D/r+mFHW9Y8qeD0YAFMfTe5ikm9fd/BQacaCJVt9T3I9ls/TF5vhS5INrLMj +TMW7Me8IpXpfzrxVHdSvuSScdayADuCD241qJ9XSStRV16lXAZsOPUYG58D8dPg/ +mbQaWZ2bUBKEUDilERYH/PUxcScQUFgRuP5GamoUxzCbKo/LzMFG+sYYtLHn836z +FjHPD8lkfHlbl9mgHF4VVJQw/Rs0Qv69p7xpGLFtOU9bV1y01u0vXio9VsggoKUn +/caeofCscxAH/MOVM4qTcB9cjPQavBQ0pjmsLKpR4C+GWaFRvRs30H2VKUxSUmRo +77yhZZGA5j4kgb3WsTVlsMfH2tPhoooQqfbSbFnDGMNg1SAmwfRv8NPOLDF4Kr0j +0JGbxMmioiKfQaHZBjj85xUhl+ro2mepDdna1r1zgyK/Zjr3DHJuvE8wTukFernn +JGeGkSkcV5kO9WR+DYc6Mec+osrCWn3D5EI+fzUKSgGRJjy/mYecaY8SQ4k5McYX +0GIQoHqm6Quv0auLsYnoi/9m+NV/lwaEMP2TMJ/rOVLXlY8sXy8VU5/bD/QVc4L0 +0W0wdxYz9G7gdh2HxLIRIhzq85ig6azxlLndlLJweSmcf9OxT9eA6GxAAjw9Mx6c +PfPz8iYqjG261x7sxJOwH0RkRouIXOmzKNVB16BfaJuXZjHZH02Fw0LCxbT/pbVv ++jbFg+TtbMv3guRyAMcLNwbUVe+8UBEYeaN6uc5pQUfTMtRoHbE80j8NY/jpbudU +m7ApSKt5ICdBSZ/wCHKTA+Re//Cz2BOJ/8u3ltlL8CVRrJ1Y7F8AGVHRpNuX+aXR +nKnpMJfEZw9z/6m8EkLWOa1fiuGYQHg/PLDRPiokyTMWzKbZSzZjmLoZs2dSs97V +X3MgZ1M8JYK/yBEFrnqjFp0I+cMuLaoPVk8Md/yglRpWDeH/rtRUSLZOOvPAYviX +yUceuOLEJcCTs6/lZt6zd79nj7gTp7x6t0kdxyYOP01LjRy7MmQOYaSj2ivIzRIZ +dLlQPtincVC2IuAfhrkLrZHUWk+M6eJy4FSI2FnB/4JZydYWbFgmJcKP46SV4/Sv +zh5cYPsnhA10nthWftm7tqucJ92upyvJUUh4IniyzEMuOWtAdv3I72mCd4e91SRo +su1u1tF6rXt2Y9nU/xZV5cX+xe8V/+tzX0OgsQXyp5nSNY+Sj0fXKJGJ6hw/EUoP +pJqW+FV2bVzlf5V2CS+ztVOS+tV1R3u6k5YtJJYY5qydjUfnZQsl2EhXxK3f5C69 +Dk0JiYoUCdkDWyWI9q+XIYEH0mKzhCDcKA2QDwTcULObaug3TwQW8wV7oDWL4O8b +ojats1eBZvP5jP8UkR9o5w== +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +TTxOuiZPb3z5XXLY5O7KZo9Sci79nGV1/MfaMohoe0ccAJaqk1GLzchKYcHE/uM8 +mq+Lgt+Lq5ExtX3mWQnmAaV5bf2YjuSduyCMYjYr/WfeFQBrvYNKJLOCq59+YxLz +R1Ad/3JrTQChewzV7VLmOrTi4b6Bi+rDUv/eCPyQZ3m2f4PErw7ca6P7QWDC58DQ +xpUxlnB0Do5YE6IOORhfzH2J+kWMIsNbu5b5aZ6GQN6SQfJD01HlPvwLe/Qd3aVe +PSqjzgzb2QHjnBWsZPDaphU2PQu357OnnEpf3tDzZxPLGgdN4cAJCd98mmfu6wAI +dGHx48AfKfxh4sbfr2V0bA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1024 ) +`pragma protect data_block +fJNRvOMBPIBRM0scZqncFSaKb9GwamqRassaxCczcSmNF8lcC+CosRzsWGqDDmoh +V3WvSyIsxrrqzsK405YwAg8C9eKJaCdieD9xRWROdJaM8lW4+KOdCYRRwSfNmPwb +Frh1AHi3c/YSX6Zp1iEyyQoiZlnCOgvfrQTUYSZjRMFqklJnLqQpBZOLRkw5X6JF +P/K0VFKoc2rsqnlDPvAzO2+mWAlcnec1pYEM1RElbmT7UpF31swFtOUruI/xU5Gx +y+Nc/Tz4c2rF45s1N8IydbP1VI8IyEzJ0efHLlujJ43Z2Yc9syMX0bzDX+rXHSFA +d+zaFPINa3yszIawwhLSqQlS2oDFwi/oRL1a/xBQiMHn6Bx1ldYGW579tQpqmY+T +dHHBJsV5UwMUv3mujvW2HF9J7XnIZUah3GG86n2VXJdZRMnYeA4ZZxfZdYlBccHV +3rAduoBxGe3tof66Pv9gMhN5pMe+w8a3njKo/CwLLCwK0WUMCphlGGoanAmvtGZf +tRu3d6q4eW1ACzG+qPfSsQK3ngH0Ts998DWee1VntgJr2h30KqUIJooJ0fwGIa8k +ILZKXUR0msmcyh1ti8Di7FlsiuPodnRaUCgXxVirmYalnCYT8kGASRzJYW7OzkHQ +xTZsFbSTactBcHjpvFZSv/qSK3BXR2BMGQtRmTUhVft+O1sLoycki1yTwjoFU2zg +JuenKFxnJmUl1Ac8R78Ikx2Fbn0EEFA4UEHoYRDm9mRwsdFpNEwf/WoZmA6CVYgh +pw/2DFRbirJYlv+QDz4E7xr4srHJfkbnUGr5T8kS6PTt90zGl7U3dvynTPMIAyz4 +GyAar2RCSSQKRe5qlWfVwZ2KIrtRWljAvHrq3KOcvll2vzKP9/Xfceqarm9UrydI +41HrB9c4GR5rkIjau5iSSkL7xo1VdUOqfc+l76NataG0KaZhSLL/UGhEfxw9j3qD +ebumDLu85CVO+eeB+xpMUOp1kG9jCIuUWlc2QJY2PSatE4vf7d9WZv3MjE+dCWna +9Zt9YawSS4nXGo5Fh1U3/KEdkMVIwZzEEq+48YTFNaEwxjeMmkWNB3LA7tB4aq2x +dyRdJRzn2ZFnpi+e+5sh1zyUUb/VtKgp67mGY7QYiD8s0Ld16MyjVFbg/8cJ217m +jwOaR8MzRR0YANi2hOfeKppvM2Ev1+fEM1Lce5AdoSSEcNuW2Mq1DJg7QL5TT+m6 +Uu+6EuhTWF8eArIXCX/MGms+//DSUYcn3+fjKqnyoiPMAeN4fN7X0qvfDFnuI5wB +P9IQQZrLuaA2YQbnaMCA5JrlclN/C/hGHQhh1VFOEB648lSTs/nnRr7kaMDRpVmx +xGA1BK7JL3oGZnE4JdvgSw== +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +nkhAcPFy5CVC81K2XeH27Rc3XAcv7GTNij0DpNy/tGyGNqkfm8/I1LfCR4iJsPE8 +U6wXF59KtCx1ze1dlOrt4lb/rddSlMcjclAf/22Pk/Ic3DCXCY0Ma9YAKx/HDotN +1dAaTDyDrmMf0i4h8jArjVEkdRRMYvXcwIYMQLgdoUxnytiSl/z/kA+HNl9nfVla +F0F/7dY9wlvF2XLOT6OONbt4VXzzSKlXn8yTOKl5QXjp7NZg+R6xKHy8uv95jz7W +GAMfUNRgH0a3b/wnyq6xyxtaUxFg4EqRSmIB3/vuUWN6CTQhUgnUCMIr4vYn5G/S +ow6ZCwubW4TjcOE5DpOfdA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 17296 ) +`pragma protect data_block +Hdm6Faz9e16HFoSKmVivS8fV05dlV+LAzpIs6QDXyT9Y0Qi5oHgeb9r+PINXpgZo +KKUvkxr0RGfRoWE1tmxx1AXjU4aujlITqfm8eUr5YnHni6ny4wLXbYJemzd4Im/j +xoyaeleBgWEciGAYXNXIOVWi/ULg1ADkemz4F9opZrFpeT0xfPmSiVux9EalFf3s +J5MgOhOa5F3orX1Tc77ZKLMWc5DSJ5usMhkEz/xlR8NpzRdsMugaToGEWz8kki6G +zCjIppz9+iSbc63Sst0osVlQ8dkJVK+31yiiWwyufq73nsbKbEHtSOr6BLpgFSyE +QnnMyRVld0OnanTgECcKVbmcH/IU0Wqs/t5f8je7ccAfsZhILP49aQfocO7uPff1 +vQk7Xq1LPp3xWZuJ2SILGg2qzr8uOnZ6yFL+by/Xfw53vKIYNcedWOJTMx4OYjT7 +Xa2Qsy7qMs7gv1U2YGPW6Gm4f+b5C7wT9OGZnERTLX1cCqdE30tC8J1oMGJx84qF +xuNpnRv4xLSoSYdH73xu28yh1y/LAq573bwdjfxYG0+lpt6bPFiJiOT0HyRm/Cdc +gdaV47Ou/SP8/Z4LJQWaQy0D21AeVrT8WbxHBxy9+5pv8ogp0f+hQdp7+NPNuNMa +e5S78E62uhfaietO4AGAZTrN12usLW3OhT6O5p9Pfik4APPFyLJUd/TWqlzNy/mw +OUoi4AI+3PMR/zt5yKD6twD5FzryerMVh9qZkeiHXKrrgFLotgodz58m2si+nyrp +vg+Tu3jNSvq0A3TzzW8q3mNuWLV9l5O+ib6sEOw8ccFBBgWMv8I79Uv62uJH7AGX +RldIx5M612GtsxtCya2P8o+7Ds0b+9TmvLK7obcrDqD9/wumPpIWnVdtbjSu15Gb ++4+78Wuu0GivmcG33J+A3XUqwSnSqf6IbCwxYzuCeiSmChWqdAL1Q6f47J9Yo3HT +n0nND6OW/hjkzhtsuUJlA96yRoeU2lfX+Y6k4OOkScrDbick6fdfSpcMaDNkpFHf +ESC80xu7N/BooRPEj1XIO4vQ1dm3wGrFQ/JvO4VSPPrfXIoUVApqEYOJUD0zTp6T +xwhboEAQ4NPPavhznP3khd0scrq0m8fkzs2Ab7aORQLseuwSoNL2ks2egcOCAA4R +uXgMDfS/DN5Fyee/nsrPScKnaiBFawPPTDJ4RtltMvY7ttmdrwqtKqIufid2Tc9q +El274rdFSSxB2pHbGgg2L2M/JzNSFhEBxGwx9vuc92KYV724m/9Lp8qIvYsmDQ/D +YUIG0gYxeHLMHiGZjTdFQsvGGQ3D/pWLltTe0qmpedymXZyfs88oIygeMH299UJe +QsqZE+JHMLHPzueZDfNwCJVLRsWQMrKcKW/BNPqz3sCiNG+zCQBwoFJ1JLo5pAVd +q085F+QC98XvrqI1oiTv4fn2/4XZDljuQ3BN3ptVO5i2Iqkd8EdU+BFksCQJ5VZh +O9PAnZmtq+ak+AIVqwv7KQEDF3lYTQf2mY+0mWHVo/1uG7uOqiKVlDmZaGt7mNSn +AqA0vrN3NtwAIdslnA6IGbkBOjHi0NB0V0Rb2fDBf3CPgVOIRohgRzNt4/j10wBG +F9LyAUcXUMHnYwJ8PJecMoEfvPhMrQIznBBt81kNWNwxwUKjPQdNM4WNxon5Rgrc +Wl/CfwI3BJeMgs3o0OzWlZzeKBBGXDVrltQYL7M38PKo13VZ/LIR5oAjzRr4BrTq +bCHCaDU5OXlXQVwct4fj/mZIq+MxUWN7lDZvOEFbf/S1313YynEuf4vJTPfmhIe/ +Nl3fkMfM1nX3wZUNmPGf2Hw8KhMAn8698LnILSlCsNE+8dyjb1GcaTTR4KDYBBTQ +gO5JxfAhX4b/Ty9rtxhRf+RXkcxHqpeMjSQBCQy40stLQTRgCsVbHtOWwfZfSlyR +FTJ8VoVaauZ/eYTHhVBFU16hHKMErZRKhPZ0iQvad0Qj528ge66J5n7v/oG/xbV+ +L09vhKuL5jjyhRncmmQiPnpWfSAl/vRek+Gv2AkE2crDujkcCxZvsMRcz+3SqAOl ++cpZ3JqjBsgiIIKVWkfBXD4BBbDROKXDXMouA/8P3mLi/ZHrbw9YLrUP6OkLEC3R +pzzCROPR2/deBg0nm1Ptf2Oj7pj2IjLF8L2zJUZAKkF/xI407kfUfUQG31WaSjCu +0PkGhwgojIuFBYFrPej1SZqfrZmgyWL1Rx54OlajRTrylMy/BF77z8eJApIWsoDe +fD/pSz295Cpouvrkh0H/ijJ5s7LQ8xAYk5/PG3ojyHx7uDj7hpM7OeOZFpDm1Fqy +GMG4m+5fF2Y9qFV1Bbh/0A21k9xjf2YmNZU4IpDXNrmbnH+sLDojGNwdYFhaC2YU +Xk+9fJFKfUa6PPeZyct36Zo/dGhX8zbX+LPeV0cUr3FJxq+hXKfpVVqHr+dhKufM +gWkPjjSrq2KM3CYfNSADNazT0WLg+eB+7iJtbf7AFnkRHKhltFSKJHZtJC9hAfjF +zF5grQJCFFv7gyJleq/cijbiGdOLSP1ANQuFq8BK+m1U0GHVbFS51Lc3FNOHlK60 +dAq5Zg/TH1wnvgCeyYO14aOHzwO6Z9yZqwWHhKmoCQjkTlojv+LYZTdCjeeilCGV +YuAKJ/iAyxF5vQNHxkSUODbJRkNVgoOANyMc3CEp7ji5+UWgQyTnXAEUd+1QfIaz +hFm39jg9WA93rtLyi36uGhc4J+CwneqPASelJ+TnJpbtipU+znJhNE6hUBc2uC86 ++GrOw2qhUSJ51/JwVimYcssSlpQSZa3ha63OuHf5oBQjM0E9KzUDIbTVSe3ry90Y +RaCt5Vm9CnPk/N6CjJqwMZt1QOwcB/Ed6aXATRyDYOwNdyOEx02evUMS+s7YdnNh +7nv5sOf5/YzF5xO1EDFt3UxaGlx+FjtmM733xRnGaV6s1iIwM6NVlgm1o+c7UCM/ ++RQ/N+ju6ooFAnA2MDD8CaF7XqqekOhDVxSvNWzU6SMdvGIGc0rOxCWGA+kKUzva +q8MkVh8T66BiRFGM5l01QO6Zf7yFQulCl9n8kyngC8UTh+p58na52kQzgeyTTSgI +hoG1wpqqgjGjvuoj4PHqKcIw2XLfoETsnH71a+lBOBnzfulp03FX0vQXRAxRGrY7 +H6757ORt8rNgcGdMI53C1SD2sT3q68QyV935xbzKCchXFDOzKedQnqA8dxos4rBC +wZTyqDxMeCd21pXXu9I6ERUxP0elhshoA5qyd2vIWAg8FF3Hz6t1pr95RjeX8uN+ +QKdD/bYzSxJDuu5yLXPd8TeSMt8sfowxB4n/+JUlJx929KHDm3zCqZZc77Lx3o+C +AjNN9+Fj1aPWaRYCEwUjM6zSbMNNAasfqxkU4dbYvXNn/Mc4nzXxySKnggpMtI1M +eLuDNv+42YA2EzpDoeyPHAUn+NI/waRTns0hTEHAG3Ngu/aflW+zh/RXTAnlGfpA +ugjmpYEpGtVsoW2UWMrBlZKQZUt3YObaKL2HzHLuVMstgyuhpdwvrTtKCA7sbU8M +KznMfXtyadntP/oFLXTSSJU0xn9NSNuJSsKuN4GwxRw5lSm1HhVvuCOw3khW9gCG +nDBY2uKUZhOtlIjll3Tb/R4XncJWcEU3TbVNu+PD7bC3gIP13c6b7vlQJcxt93p1 +VNE/uZiwa5wEmgEnHm6yGFQCplwajPFxgxct5Bf7LLuuzvx47WzWQlgoc1CKVkbG +Wz4ah/j+5OzPQYBT2Pt44HuMGiTx9HWwoei0tslh3mv4HjZGvhaDuHkLFtnE2/Ev +r6fpe4jkpn0NTa7LTxLb4P3MQ0E3VLQAuatNy+u3gD7BxpRhuEh1J9Cjg7BGMGbV +kUMHiyGjysFjDeFfLnrmu8fPrJAkCxnszGxa1o+ABPAAlMQlQbbehO8gk1L/Cq+5 +iV5NFSGsEdMcZV4fGW/DjWf3UEk84DyCfzgq6Xj401AQxvbWWIqh0HJ3gTvd+/EY +Ju6ppl/iNkO8EIZX3Rj1VvtNshXUhEU2dNtY/oN3CQBnfcHRInJ3BQJDwjaD/Wja +HwWbBfWDFPqrWqndJiD9GcYx6NCn9wpLrja6GwaTewbNj8m96ONsLQFbxtq4Irpc +8x9EOvtH3vZxEYTmoWtD6a0ONtvKlhOXiYTt31mPhwyh9JY5/hZhPWEMPM52n4WB +LlPXYn/BZXmdGS93XnwMJbjI9+CDID5ojJfKg+krWWS46++3cm0iH+ka0cCm3Y2J +15IHiImkWKD7eL4DzqVCzyEVGAmWtD3jA1swSUgVNbkLowkij5MDvO+0VvfMJfHz +kfYFVFb13O53w/IOwLZtBYjnbMBQHXorKq6CfhGGPJPp7R8oOn4pur4htnZNzhBO +d6kuldp2A4i1nMV7oQNU3M2H8L7GWD9hEIujtXY9idS1WhrGZaDFgauqVH68KtrX +AqQwCm3we3x/0aoVj7u5pgMrSdAVq3oxyxXPSsZmuC5CLBrKtG7DwUjSFjlJfGMB +zbaIN8L6O5FdYCKVJZaxtkhEQxOSlzWX6yIX1QZtv6HUdy7rlF/itfHhSlDT8irp +4zkhilAKXPWhnZ57Z2sIKWXgpnbsGJv17IUpW6rZV6bNaDE0O3byt0SFZVADPKtZ +8MZkb86ecFhamVxtgYqBAUWRf/BIO5QORpnhI52w0RSo3LzDoWO9cbomeJUVJ4iY +SDRuqDvPmm0LsbaIxnP3DT1oMk3UUz35KW820kLgIlFct36TMpXn/MrrRhHq/aFe +UyJ7kx751XnBGD3n4r2XUzjsqzEqseN7M5cvyEb97PNM4SPxUyCBkfTwucaXI52O +1bPuivzyWkqld4lfzwPnt3XtCwnhSgEJ4VTdN2zCLTj/AZNLqFZr1B70jdA0TP6D +an8T6M4+ozUsT5ThNVId1DMMPIM3WUUUL4H9t5sm3bSeYS23xmKb8c/cFVvRokY7 +b8PtLeVX7PmUIInaWlJ7IUQLbvgRQZ2RUTppm4iqrHvGSjBNgDPttaunBE1ew0qG +ggzCsnWMG7s2TsjusvpxqzWKEwtcCwsHZn/lpRhFalLBNCPMQz7tpcWuXLxE1jg9 +G56KjCeqQp/pZ4HJZAPMRMGE/r+ttJdU5zxGgudnMvJ/VenpkOik7I1y4+vUKb7v +jmAXbXMORu4kHKSJ8rkEoSzuTeGrS6Lbz0h0hSC91OIYPX70yRiujIZD4Cavf/iH +2HGdStyU+fUX5bJ9VzJnQ8OutWLrKpKnMs4NMKpqFQK7VrE4/IXGVNm/xl0iRlZm +RihoWdyk/8gMdO6kj901dD7B1KAOPT+OZqrnAv5Wk0EKBm99yTjolLDrNNXzQh5V +m2AMle/ab636rUnyBJrB2DjeErP0OV9U0TBEzsajQJbDw+ycdfsfsRhDyO1R5JC0 +I+G9OW2jHpj8OFBQNw1OWDiIoYbW60hpY6VdGv7cFG1zD6LLvOjU/e4brF0lkz+Q +5lM+u2ywGzrxBWtg7Y6vTVxykUv5zbCznnJVGbDbxzXkEOKZTuWyQW2IWjoLxoWb +wL6IfjxERVOJ8Ne7pSZz2xp0PJ4g1sc7nwhUZanYL9MbvG2yt7BKldV4FJFTB6X5 +5c/C1hDpQvXDBiZXhjF2V8Tx7M529zfwmpTT1c/q8xgJ3s4U3E5ftZ3d2cN+WuZg +NhAXb+GbDkRtOanAxRYf//TJDawY/fR+GHhyfCsJymZiIBG9M/Mg40o2PmHQdn46 +eDBMtBqMIP+k+yHkUv6hzF2lil9IoWe2j9rLzerY1e5S8+IY2LStPLEMf04MC2VU +cqR9C5KTlJXXykN+4XXPeVxma+eDh5EipaeNtJw4x547GIojREw4/keUKQUbN2UI +g7RKw5lD5qSxukMpzUOtmNBqGOblBr1YPvqKPoNWyhpNgOqae+JLwMyXMLlNXg+6 +E9UNJ6xGkeTgJ5VbN1S0xIFtoAWdCZX2Rq4AggdUSgeEZWYEsOUQDK59qP2VGM8P +xXTTYz2mAXQNBqwdw2Y9tUNPIxBHEGH36Y+0+980Mv3N5UsPgbyvXJQSVJqNCr1O +S41YN6uO1ZSFwNRyJziFzLH/iVWN7n2mPku5ABahRX0xB90MlPAzXbaK/Zp/1ItT +f4hfEU4rAJyAskUQwyenMTmhzfPij0hwUALpPcCFeqVl1sgSrWCkjg21CjalYFKV +29n5NR0RKyNPIErpkrX36nNOro6svb2Pm58Pdrxo3qPtQcoXdXV3mGlN6KmQI+O2 +a/GM0NBZF5u/5ve05xHz5TWxa775HSwOhsQ99eS+zCrT78h7gZgf3reYYKDGUnAg +XxvGGAiRm0VDfZZSoLd1wDjzyzvkcaXsrSvq0qLdIOgqnAFklYki6yg8PQ8QztnE +G1Db5zWpgPSKPoX/1lhtgSbVRW9UHbcuk47JlnD3ucLT63olrAVQjYPwNKAPzAJ2 +Ha3PzqjfpzIbcKqD60H6to9dh9NBz2wxRZVj1YFMh1fn0FyZGUvujQn8COQ+fnqD +j533hIZk5WOUbW0F+i2T1smw0CEyX/pXaaybGssypWWZYIjtb/rAD6OCv/pP1fHO +tT02gwj2gFLovv9oKtulGyosnxoXTzJiLHnZ1KExvtQ3bUKdNdOODjLZ5DUo1wBI +Jo62JqQhzOYpL91qDykWHC3YH1cc7uNmpompbt6TkUeeDVahRbmx6ztH69TEVYk0 +EjgyLjqUqPW8yNU117Bv/G/Jv3+E1KRJQyrsndRZPkODo55q5GVD81QVD4sWlLvi +8yl2ExB9zNVdtkIpi3BebH2C5S4q+52ToG1YP8gUaBGzC0s+maENniRX+3xR4avz +9RXxxVbBz4wGThTAEYe3U/DgC94Z1KERaO/SjZiEpcieL3RTIFgPKRD+gqG3sN+z +W5WGIf8QlfDqtMV35Iv9nQNrm2K336Rir3qx5wfs11Vr7TkxJoJWPIXLo/6iTS8N +58mNbAJPEWrRpSNGZJpazWY2Y3RJKDs6WvYnRFH9myCYM4o8wG39Q3M6JGJDynBJ +i5liUce2oH184b44vSIUWAIjyNX9dj4pl+D5JfWjdnl753UQGiwld3P1jkEbZpYn +kFxSDlpIQ11rmescW881k1p8lsAQ4B1OSNPHumxRpbjB5Z65y4wGNKYsWVMM1Hlf +Lz2BhN+4ZFykUQ5AfV3nzEcEyQ3lLFSRzkCn5l1r4xS0asglUM2pZmYLgtTJSfQ4 +yGiOtbqXVbNmiJTT/IkgKTBmSt/3BRxxAADuTRhNTasWdlk3EdHyRjzdna7eFLs9 +9Jjel15KTZ+TXHi+I5/vS7VElNpn8uD6Fc/zy/TDsV3kthRzsEmOgyUkCOLa7xj7 +Xj77h1BUT4rwYk9S3RfsS2cCj8jFcfad79idIo96aRtEY4RVPfiBTKVkwve5R9n2 +S40fb7pl5NC3A7cwZ+Mi9O5AidNSpPRVkxecNpxi6j8aTUyikCERJzC3q4li75eQ +cvHVcCZKOmqjj3GvHVqWsCzMrK382KDs5ba+V+YqVI5t81CT5LboYGSACkYRKrVX +cTNX3sxE2N1JhzPKpbo1FNPYNxSsPJmUawER46e8kHieENwCKB+aAmnx+kmgPp8g +xyBTdVYa5Uun9gu5rYWjcHKSzFWoSI2wrpfRsiZarh1FGrrg4Z8OS0+eSIPdCPIG +5L04gMkpu4VX5tCoseytO5FIgZst5lo7Nmqz89MHGRbNQIZrq9LzPehJ6dvDw8tv +mFsNlE0RgfVY2M9MzcBpv3Ue3uRLe2mqK8qMme93mi7l0y9hZXsOGOn/K0SIzzP4 +70YbI1IJKoI+0N3GZsPQ3sDnzi4nzzs2wrKUcKEq8kW3vf0hsgJxK8RNRCAQ76Q3 +tous+JuiulEM4E+DTnj7wfZQqaNGSgYCqAw7awlosJSEKe/lxN9YArRDA3lwR0/f +vfl9X7T/yUBaPJmlt6NR2LBl86WNp4mvo0VMWz2NMykwAnseuKvXGdtDedrRO8Pm +82ZgZ6wgDO6qbQBCrewc4cKU63AXKkh2asrL6nqEz3mJ9RG++s46LPQpa/K5Wccr +coPIxFko4+CLtQ57y7Ryft0K8/OTccTEtP40HxfAtwcWBvlRvbQ0QuDCxCvR7rUI +xMXXCYN9jG9sa/q0MTmWzuf0rMXVzXFDLNkSGRxCoOWaUt03ElUExbtHCGzqiZ4M +3XDWc/PkTz2EOWxDy5qDtG0Xn2semZYj7XifP0Q3efeO3JaezOmUhFvdnw9ImkEV +hTsXVr7sg+sfdrHVCztfzHdhkQGNJbLFQDQFjG65iif6A30c7WLM5euLmfCIiPe8 +/gIbsFDX6WbDJtI7lE1+EVyMwf0ZDZ0H5wZjdkYWkuJo1kWZO4IYxjVgRhrmjhV9 +fvciKi6Yez+WXWfcPZtwmvobEXCIn/2M9OnX52QJ7RcMcxuAAGxEpt06HOcqNZLU +uOXTzv1a4EnAIwQhVbg7qnlJVQ4+OfUZotLMDZ2CIN4ubC2ql04+emqWkJ1MrMq4 +iSt60/2nRC8nDuZ9jyEGWsSGP5dn6+aJbmcVQWHPtFLmsE1rLnpjrdL/XYLn1n/d +IgbXkI7pb1TvxpXSbY6m5bQ1e5tMbzReS65uMs5PGq/msVCc2YAyPnrvsMHZnTAQ +1HvwQiuZnxn7QZ3yx90onOYLXRNXil0rfsQIVyTKsd5JFDYHwrD60sBDRaNz26Um +RtocxxkCIqhgLPjzjgOqfEUDR5y6CZKkJDnRPGJIK8HavDawdi6HVavlemxcazIC +b2skqRK5UgGr5ysMfDrjW1g0bf81XZUqNkppSvI/HvQaH26MZksV2samR314UUDX +zWWHEcpVe6urRw+MlEoobBO2cjAkXcYxlz5iA27WXOAsfQHXCjmREqaOLs2bDLgA +urJuIL0SCM1DcEmBVRoQdT06yPHcu0t4l+BFsQ8J8ZGpc6G4k9O+uKmsEYIqAOuO +YQgthl9+vqR9xkaOKLOjCOS0FFUyQCHC0HExXZ+KX7iK4aotSc/kcWirlcpI3F0h +CUHPcJGCMbqQ/p+wxM4VlJD1zEjtYoc7sMqPB8LbOh6/vxv+LkT5tcEG45O8CHJM +tjYk1HaHldXU6fEVhTI/SAWCbBRGEkq1aECert4L09QV7ToK536oXXC6gIu6noc0 +cTc3++PA4btW10OTRen/gUeGwAWjvPNKUbujNevM5mPh3Dik2MADIoWs4pYta0Z1 +9X2JKk0aiI2TCTvE6zf/8Om51jeTQ58RGa2nRJ+ydDP3EfhN/Y794hXBYGqZAP1g +9t9foQLf6+pa6l1Ui3fDCuhOiLTiEgHcEyZZP0n87i50b4DF49ragW83P1gC0+W1 +LQoUOmD6dagrizszijvrQHrmA0DNGJvB95VlXGIiSI8qwtxJWOk5cXEK1DAV8sJm +U2Hi2M9mcz9P64jfTA6iqffh1llt6Ofl+TahUh+Jkh4RWSWOKBwLbK7s7JXLqcy/ +LY08+Z7fDWbHDwJnDhmIclFOtGxFesamrbETz7GJ7w/lmG88XB+p7mvTROYVXU3n +IS0kiMZmMxQXOpdkoZ9UYYV0Gj1qwzzkvTbVHdcxm8rvQ4Sx9jCZJ37vewIirlvt +zIQcklIqpTgDYCvCiy5uNH8+bZIvEJTvXUHhxTQczijMcO8wdXn7srQA+Fk0maIn +yfs4a0X21LkBiC1qpOQapWWATbuqaAUsik1CcM8wlv34qiZrY3vdeDADX9J9YV2Y +hi40pgjbJ5q0ZKXLhuiv67IU0ZaxI0C8U1iGqQ3O+cXvamL3gRUTI1cdYVewNgi8 +njMqoug5AiKsoH7uz80OYBA6izTXZcO5Nh2qc3WEK7I+KHPq2Sa87BYyiz67f6g0 +fSZR1PGEtaCkZDLMeOf8HjZrFuvC+nKo8l5uRBAR2+R8omXjRz7o3ie4FYA9955R +FTF3kiNhEea9uD71UyXHlTF7A09mWJuVLqF424jSIoIkQASpOOOQ/D/GhGRFvNvd +5AWIRCxo2zJREgjDy9M0aWQG7MbmyLkfQEz3thICyM6OYWx5WWCN/M0gPDScrWow +0iD8ST9vdQwHOuRRGnXPabWQAl0OrcZ3rti0GYPDtyEMqJwU4b/XgJJ/WSz1sPkp +gupVGFe7Z0xjSzYOWSKaaQHx09Wlj/X4V2ks/M9PaTe8f2IYkZ9wc2vRXX+ZUaT1 +pMW8B35GVjuC9Js8MAIPH9pHCrKrC8rQeNYAgFUecNg1uAFGW7EuJgsrBbkh+95Y +fUlv2cXAGAHw9sVjz+DLsDcR4bREbAiuVu/Hk0hfHcl7msUl7N/iivBcwWabbrcM +P+cCJRTHOWB+K/or4jxp/Lkg4f7dmf3RzQX3UWhX9gbw+SRcGB9gNX2cSxqt6g9E +xnGco6tZ/aC65evx899UWiqxy3MXcLTeT5APBOGqZmDwcZCfTc5cT079QBQhHkhj +rADE2lKzbTuEeepxJ96g3dmcb/+7ZbtsurRQi2KTbJwQSHdjopdEmWDUzV8F48jY +eosqyj0C1pu1B6CvPcMlj/cSQVJ9PXcMtJb2ZtrxF4scAmu9JNxpAJNB0QSUMLak +tDZ6XSJYesMaJnPBSj/VndfZxynOcif6Bpwyy3z1Ho3HtH4XwO+nz4CA/pFwfTzu +vYhOXkE1ls+M73mCdDI7NX3wJWyIfMR/TNJw5D8/Th6UqyDIHLbsa7kSrNJsEOhy +PcQ8Jj8ZSGF4m+D24dPtpTZtQsI0d8wx81ObW71pj4Wk2fDSz9OCWbJMJUNXkbYY +xrDnwCOqCNTZ2uTruQidwbcBS171l4RACoaXGL8KS610eptyKkvlqsODRdDdzhkN +BCkMjP1VKlIbddZL0vV2mTlJKN3S4rlJHaaG0DNPpKpKPrY77EC3wPG7ES7sR5Sf +tbElL0VtfD7CdRmRsUg7berZ+l1j2zfys2FqkX/QXd8K4n8kQ5lWsDHhgM+6TLx0 +WOb7uALiua6pPAKWhXXTnouZimODeC6GgrrEAfcurOl9xIcLUScfmwaMJr5w0BFX +5UwZiEJpglT2CXgtbRljbU9B3iUA9Izxoa7xYJldSJ8OciI6epLWMTo1bw7ICgSo +EDLzBSR1S+MuEDSiIlhlZD9W+2b+Rlm/rHuRxZOS14ztYCvAPyJHj6ukZgvmEsiP +q7aUZXQAQY1n7XWDHU/3oSEqsWEx/EcYWPPsyM3Dh2VCCpH8yPDIANFl7Dcq1TLV +A25X1GkAaFVU8T6qN8ZW3SmetLS4YqRIGKSrKtUawXtpluR3SV2CdEr9Vahw/OF9 +a6fGBCwYExaSX0ObPvl3ViN8wwoxuBG5LNM11qibOc/swHdFQfFxtLs0T9JA3vUl +JSgNBxCgfN1KimCCtjcx2b+jRAOek5S5WOMjQ2koMy7Aa2DOuBPqNE3C/kWdHhLN +iIyDHzXiYfxIO2SepblatbTw3LKErMSW1Zc3C6JcNPYxqPA96R/Zl4DTsFLmi/c7 +XAGxxWxFrkaJgmZp+F2TimM0ljKDEfNeyyFC6rdCpewpdg9IqrM04mCgmJTBBtW1 +8mtV8sfyDgizS/o5jbhSUSDab1tl6Jx4w8CcK4uUvwNb2Z8h71ZgIduyGOIEhNT/ +SoySeLImM/NjSrK9QGgn7q3aceAKHlRCOcT+mcVng2CHbGxJyrP8gqx+oE6sMQp/ +54gkG6Qvz5JH0UaXfzqEHeINo0gXCua7TebqvVTcs2fGpchqrLe6UB+H5dK9FO/9 +FVz6ZWsQklwkP3B2OCvX6HDnE7OBlewhoNKKUR5gB4juepGDi3eRc/sOn5x5oVZr +f9D/WxVLQNdWMuMJihOOKZRhleT+GolAcjDGP8lvzis8yvImpZixK57qGfdQKBgq +HIJ4GdngSE/fx4bwcIgxMPjdOdeZ2iJ7JfcxRhCSDgNmvlvg15/zDSUJHZ3OflnC +dxlfTfCl++8x+I0Lvw/ecajlnxDzuYHL0+bKGq7hN9lER/C6bwe3AnghWVFy1kT2 +m2fz6eTC9AIFSSJYRRRBDDYPZlnIkla9gMn5xFO+xXNLefs1qSCtare3RBL8VkkW +zOfhVBN3r7xGO4jaXlXFlC/RxfjKM/rRqcOsuzt9h9EZtXyCUN+QjVtEpClFF7Za +XBtd3oANePStT9TMLDRpBh/R9NHZP+uWM7Ywx+I5pPn0SRONtTINcn4BJD74Sfn+ +OxcyHgd9DWFGe9bJRhNNvuXnTEh/LlInpQLnQUlcsYkDKMLOo667Zmfdagi7fPmk +IpM3x9Ph/SUxsMTyfx50B2b+7SuLsYGATQgzzc6Ko4kACPzmpZNH5e0rC4nxAB2w +I4rpEUPupze2PcFHFQjE2ShsHqsgEfnsCKGINb4M9+EM0DCtAwArYTjPvxKAFhse +1etBERLLyMXzmwvD0cjNqot8ElWBgH0xY+7rg2HG0lTKlA1lDWhvOGWvTuLhKeb9 +6jOf1Cuo6XKj3KGdakHi25f08VdIFhiU89wWiUXMI7H9FmLrz48LwK4R78SeqAc/ +47gJ2EsHT3in81JahbHehhVa+4eipgOb4aT/7dJVaNJghyqCVh2ewtfUpdgryyMX +JFM5Z8GwCy+90nfL1EL2L2Ix+rUA4Rq2sr+gsj7SsEPMGKDTFkkOPlb5bNQqCnvg +VB8cw7kX78nxti3CVN8xRfcDqBJEn0u+IwQjT0SL4qz28v/EwOgpEApTbt+2x9vZ +QvhdagNEyRMS/+pH4w9Rn/McJ9Di3eZDJgeDyPNJiYaJOH3XhjVSC4H1SHAxo4j1 +1MoYbWpAcP0u7VsoU3JiYelXdxAZAqQs54D9k2TuO1fbj5KbAYl+zivV2kd7P+BN +pjnc0xkzGsOuf0WrnaLFRXOBzDm3aBEOnboq68sL4G3iv07oCWqY11WkHHQytaw8 +2S4f68Q20SuUlb0j8wrn3peqW1nAeOCFT3hJoZfSFt3oND0ALijddpBCwyScdlZK +AP3WYAqiaFKmvJGgX0rVi9yCo0BNEJQrKWNcZp81v327d5hcdGQs+ETtv5N1LxMI +Kn3fO+2fDGrT41MMraMaIocN0klre0L69HA6TAq64WdCnV98Upyi6N25l9utVowL +pLxcHIkkL5zoNbDez7iXLvGL1h+2a8rZZF+xUzoHYRb+c41Pl9NpQVzbn1kR+CQH +jOaX2Je/5lj/BJnmofr6agWEMdXkCJfwl86S3p4bfbLCE38si8PO78Tci8hrHNLB +vd1qjocjwVva2DXYdAHn8/S/5yLTadzBFx7SBj2zrTtxnqw1Mp4x1gY1Xl1l3zEl +Z4p0HaZIdeHNVLPAx6pQ5uctciWrKYMmHCpV8UQ2YjzsgZIA3jXhLMH7RxTdCpG1 +HKG39+minFjkg/b3pQg6SmyXCIAWI8Bz4nBXZNoKPqAoefbaGKjYnGh4U6j1FjZq +Xt5anIS82qP9+skOjZtHjRtOS8op3ASvLaN3g/E9y96pW9f8df1e2lkMlKmzPr0/ +OdMbAzPUfE8pWj7nSuf7dMJzVzHWkGkK7ZsQ04OveUmglABC1Lk5YPBLtBfif0m+ +vi1yA5jtofWbdqLCXWRn9XZ1BFvAKEuyIIcvv6UsFCv+pWGOIBgEw//8sr6O4qLc +SkdZm4OpruDb8iwIZ8vnTZAarBDiQ8flRi/4jDv8t4p1oDQetfZ2aek4foY93qvR +cNAusy76BB46flLwZB8D2G+rOrGfE076num1ZyVgR+j0mt+RYw7AJAeTmLZ1HrcW +322XIts/nmnaJItUC2N5G9hSY5NTAj8/41dS8PygEvicjjUS4xVGBSD3M1Dg52C8 +xeVcS8iFDZPf+ecl3xyV3IRss/6tHIwYFy16TSsGhBNQDM4fzsFjMFwejfRgHNkv +KqUlFL/Q4Q9FEOCgw/P3RdugtqBm4Hk6gZBAtxuZkCZnmcwIzmWvElTFajeK3Qp4 +RXZ2GQr9ruJe14mB1mH7/9DDkZ835+hGPe3xOdoS8B2BJJTiSqOj90QhtNQhnZqI +hmpgfAY+gVpfNYDFBmpPHVZMOgn6Rwj4Bvb8i8I3oVpyBi3hoo47a2lQJ0qty3qt +uBxBtLIRS459vbVS1wT3ZjKekPyLpbPr/RjBJNvOY8xoKkvsSW8udohUg4FRlX56 +nz6jR/PfR4Hk0P1rTEewmqvn5LDu6kwU7OnMZ5xC+jc5o4XZS1umPEKDU9n6k+oM +g2jA22QbrrS86LIH3iB/S1E5cbdpxh9FQEEdIHFn7yxbXHijOtB94zEKg/7eMjMJ +rUB+cLn6hHeBMMdu2fSPz3a7ZK1PnS8TTbphd69g51LYtNXezL5eJCKKoXDuHvKw +Zo41OhhWGxsHVED1nuwhA+Zomylu3nuX7G3/r3ZwuUk1XpO+E+mdFvXpE/3M2eDY +ZV8PN+MP+/PNCWnfssjNYFlFijrNnKUOzHf1wXrs5Yg8Hw8UJy3CCo0of6x4yZKG +FFFIdR42W6wVP0Hp9++ZAa+ivMDWuBwD8IQfvaDD/S8v1ISeTuQmegfO2roxe/E7 +fG+5+ltebaXBxiJZ/qJL5oVktWwiPi8qO//RlAkMHSnlMnCzVaRkf5Tuvi7wwKl0 +mAenSDO9jg4bt15ZEmmDQeSdAGN874VHHsC/o8FvwTnS7/tOyaNU3nb3/Zy+pwUy +kjDwXOiC6mi3wpQo/fO2LU05Xf1RxBlYjqzrFHCTRp6cDc/9x4070bhoAV1t0tSm +CmyeTcKxBVf08xmefeBou9tWz8sDuLa+w1kiR0WgPX1WlWaR2NZS+Vxf2aHKJZ16 +3i0bFnexVIJr8WIeyeq6IOb4uJuqhIxh7zwgxDBhSs760vzhCm0TgSBjW05WwmQ+ +6FfDrvFiq2819eqMozl1mxqAuYKHHlP4N+qj1GCYVxWXnNmzezMGFVwSLa5GclTS +7lW+smVVsOdlWn3kJbzHwAaZAEIr9I30u653s3ZYRMLCaB31bnpcWqAOhYBfz7Mp +PMPo9Sj4YM5tbTSZmbPVCiUlP2B8yFqDKgmGiuKWdp/a0RNIAJCnwIQLqGQlR2pE +ZhPi2Vq5oVQwhWdy1JoDTD7k5AFVb+XHcTrk7c231v6/EaoRzMkQ8TfF5R4cR4h4 +QVNckFcE9W9QmqFM9MReJddP5b7r0l6juBrHq50EtDtAn/7qctbLfcyYyr57Cm3z +wklAPkGCAimd9O6yVH2XztnXpHyQRu0yU3yY63sLVmt/ujvsRLGbU0Mh/bu+j8rN +OlIV9qi5r1q4JLFyCunUTvlNdPuLlQmgj/6hIfU/F+7qG8XhUoralT550faPEwDv +rsZjCOPbxeoOAeZDQS0z8VSTLJMg3KjMBIvL3Q56pYVc57nio606VQ0gqOr6JqDA +wNy7tPS62LqNfeIOSuEUQ7Dtscr5hRHlBnOFaWhQgipXw1onnlpLwKtmmP8isjje +SyxuixaEfxE7tCmovFyLdnobsr0s0QS83txK9vINWr6RCsZJsuxsjwud2va62xkd +rDDkCaVrOg/nlBPvL4x0ozawaHGt9DWG6ZGHSUFkAV8vwRLb4JrXw8F8CG405Vdp +y1HWR36KblQ+LMRbxcYIwRTc6ICSx6SDze07ckdRWdEytB5tr3SWOqKQ49xL1h9e +IN6qJSNdZPaPd+6XWsQasdy41S3zD9dKjBsDGZIKzltoplt2YGNUNhbaJGDZLQTW +FMSDAd90boRAuWGF2zsbtoDTj+9eb7jpwcTrrVzA0Z6wc+J4hbofM8LeKvoLne2h +olqMU8ytp+HcLtCW2XZN/0cBJPoMlYCLsQvGsyyDcP5CBHSwKljKwChTeEo+D+gv +UX5u6ZoNxd0/k1dD7DA32VfEui63r24RLYRBwHbNOmza6Rm4tkIU0h5/NPrCDfIG +LRoAQOuyCQ80pw3RJAUKRwgSoSKYBTAOdIvL79oZDkbJ0TDkFAjgSyjiwXPTIVtP +ajuGm8y+RbCPb0tY33emsxkESrNZIEr58vyhxCgbVvBRWsAHVfEz9EqFftTeAXWo +GpZT1YW+wyXLxeeySm7LVEwvbOV+VzA0v2PFCGBo3OqxioPqHqCwQyQMvGOFZjbL +cbiNMl3a8N9azbCacFfoMSnfTb5kU9J6HuJJAOtIGJaMZfcyOnRQqi0LtHmFboXm +e4yi7JIALAnVmvscB6cjZyiBJ6EwmAh/F2CJVFX3kXhXQUCwImAKTUk1cWWhtxC1 +YQoSfQgxEVBoeqCigYCaXyULyF146VSipsQIaWdfVCbiHH7CgVYkaTK/3Nap8Pso +UWD3HymtcghOSfRsJayhH2NkLkD0RaOOgYmARKL+zNRGhu6t7rRDzx1NrFZuPUfO +mxG2pJ7Dr9NqW927dm/epG0uIkM0XVJ0dxCfHDqo72IhbBhTQag/A+gmSFmkNAOq +Cj1PK46Dzx02UsNXwLOSeRs9+FbZWeRMceIaiVl69RUkC/Glhgik6LPcl7aSzjU4 +OItJYcOubXg11owyzpjoRiZQ+QmoP8rDfAV0tBLmVdYpZATgfxp+QLJNFOTqAVY8 +9wNbFXPa6SGPphvWwO2hvFfzT0sNZxxbBTOErJq5dP04c4Wu+5cCIG5dVCXSCHOn +e/jGwDgr6yLAzxmufp1kcSP9R3cwqOe+R4ArUjdTQcyXY/kOGhw1xpSb1YaVN09W +dntobpyYGmGl9p9ra8lNzNSrvwkhF6fVRGI6FhcGEhnPkZPaEPrCooorheH3sf+a +kZiMNHY4HcMkNJH1G1U91yEy0Y7fYcSwe1dLcVIrp81UKvUUPSNefom88mSVU+cL +QnMbJVBShJJVHWw7hWWfDK2Jz+UdAYP11p+OjUFJW278fK5SQ6NOxqF89rIVxhMe +OrbEurazrKNhzu5CFROfpN9CYHW5zP6LSepML6cXCAuNgypJEPVIEof7v7SO3uXL +EzNvzskeHOSDilrYXtKkhka3jDkN2tafW8Qa7IurjITZL9eOMH3xkF962BOKk6D0 +kJg/qKlFDi9DaYNeJQVUQCB4gvH6xaZ/LYJm7jn+TcOrEleh4Fc7r8/QxwJQXvZG +yJToFkXGP/klDnTcg/0mjinMnyXkvTy4IEeF1nvUv7KP73YQsyOh8829ZvCRsaeW +kE5aCvl3Zml/q+nrPVEosKD+Pr+X/zD5PM3Q2x7w8ydCW6oIaX32xfJLVaE6riAl +J5imLHKfy4MjhfM0wLuRMXLRKCJHc7yKoBvgJx8N1FnbFqlzTp9p//1s6AB3P1Ch +KSr9w0bSNvHzEvyED2DZKaP/DWoAHx3wciU9JCthLh7FIVgwdHZsY6AJXjDCcVuN +YSX4CAkynfG9nVqHsi2X7DGt+p94q94e+QmRIK3K7ELRevVzgX0ukob40lJq+Qv6 +WgB8IE6WyMSRS91hlhjcocshsUPzQqm7Nz+0EPSaxTSoqbUl7Tsl+lW5rUf9dYyy +ofNM4jybNxOoiA7mGVP6hSshpC5mCczLe8q50EEmhihuZV2cRr+pDRFuLqrzu7J6 +EWgh1h6EMQxTEi49tFH+iCPztXfPZJMmT5FePQ21+rX1kMNkyaXwjUWzSS+X3LoR +VtBeJNwNUeJND6s4R6NRLfY0aj1cRyJT28JldAo4LjxemOVtiD5ZFA0FIR6qvW86 +pF2o6fkdkEePOkwf4gmVTLrrzzKRj0WiqBFQqyRmiPPArqrajIgNhXToCG7qrXsX +8D2aHeVl7b4wCN/Ez9zYVVWNTA2MK/4LwWwZVV5jxQ0nTJCUqeDVcHZnzaynwfmc +5HiOh/3jC8cujMEUbfygd1EozYCPRg+xs7UUOMDBIKpjddAl4U3K4shWVGg6q5+s +P76lxcr0KPV/zMJl4VCXD7Nlx180RS/pLsu28tr9eXsPWZVCMPg1AreE36Edt/cK +oXSh8NdB28OoTPNeSlY9DCnt9cF1djL8VJ0QF3vFU6Xs4fb1mqh3QkAqHHPCwL+J +9EVyGGOKjJfQp8+f90+qYz6XHVup9jzqcmIYvNYsKT2RxtbwVx+Z6GETuRYI4FJw +GkbNWil6TTBH2rgEmcnP3CvJzEsDGO8MGAckduOM9JdDLhEj1RaArG0Bbj+zP0KS ++1YuKu2tWAIIDTRS2VzIbVFqjc8ml1e6SkbPjzji4FgZe4ohBZbxYPDLxK9yqOeo +KnCE/eXOHQl28fuGgWZJ6M9Ib/AEGzyFC2F0za6NAXHrAvLX9bKBW/QGGuzLggUw +tcFiWki0U3Awpn/uVFk/7O6gVAEJYLZHecUTt7GTYL4Y/Ru1s3o+Eh4cQUcT4w4C +VKWnAgSNfe/d85IslxZuGZ94yOn7jUjR9HNNm9ykqjl3e/IqyTpnmuXmA5jbRzXy +PQ+khRosot+lUnMOY10A1mVT/7skma93hUddtMvMRWGZ+LgMNC2qLJNTDlj6VQn+ +OPi8UEOIKlxxX3BA9u68BEpAQzvGtAC0h2bLQ8LouDcPJO6j5knRf7hreRclZsky +6gOBsykJdtjuVOJnUcl/X7ncOzOT/HpP1aXszeU+OJlC3jICNaTesq5H0MO9/5Xl +pb0pltx6Ll0V5+MxEMElw4s5rdqPKw9UgVZVzD8yHzt8+bOdWw7qyAZ6L/ceDp7C +VS9yXF/RgA9mVFC0Tz4D6im1aEsR+prxHJWbje2UQcjplptZoueFQ5QZ4jpEKF6z +Ap0yeU7CHJpxNbYA5lQslr8Hdhh47MQiGYmH0iiBsWf44MaENh0dafB1sKFfDw1e +2gPlegToPNPiG0yQnluliPVq70JdO4ri1nnDXu69+gnFSimnZ9LTijW9rk/K8izS +qilN9giT3Kjc8z/itJBwF5SdfNbidhNpjQHq0otPSbf7v6vLGxNHT7gx9nRFerxM +c8ISjIaSbwspaytzAFfg6VPz79axpogaKNpcj1ifXXs1C0D6luN68qaQwPF+2ugB +rUFmeUhmLPFrn7SKkJwDMuZVkoPKZX63k9KmXQHrZgwlYf6ZUIlWqUPxr5NWiy3I +AwU9v+1/acqmZowHa2YRLoOVTfBWrW6dugHxxdkD7agDtYDD2aXMIG6DYRYLRyQG +K5UStVaJmLwMY0XoxhbHTaYiRUSwRnUKsmJ39XvUIO/tinZCCvSCCCNin1BixuNs +hZg07cJprziUvLk4FO1KRVzBXyJ5Cswx8V9jqJLkjlTqSEhNUuHPzokVAh1ba3X2 +SvTc+FWkC/eLfoFEdpGUY2qzPP5KCcmAG61MYV29Sfj+vMomx7C3IIt+sbDyWpQr +g2TXt+gN74G7J2rYjMu3HPriaaYATnjPDsl1pA21ms3SS0dE+1nuxyfGmDLCsp8m +MqTM0U/FceszKZtlxUAiL/wAF/vDzR9T/hkjaF1eEy2m+qYw8vKl0kmIjYVZtPNH +X4bv5EG30G1y6SqjBBg1ZqD8SjjGRfNjX1q4GtZ4U8pPorMnLFVKzuPSi9eZto6G +YhHG6FZliEWcR81ssLnza7nry++V6yuDBslWiJSjQzgDWxkSpNRgtMteQ9RN7PVA +0AUzWgDpUswink12CXRNHlTLeDO3EUahvgxaPSgPwVu7o0syuZDlizLIyOvSjdjH +mQ4CU5AEec267PrM+zKfwFYRYmULqfwSCSlgykIS4+/LVviMa3RadvwnYkMc/sVv +HMNBIwICcmzXRsDCujSnm7Ir4OaKaimPc9HO8xTaI1wggcqLH197H3el5VA14GcO +5XSx4RiphJFt0pPgAJpxoqQQ7h451bumaqsGQNMjTsKp4AAh3ZVop9uxvzwBNE6p +f5Fy2UKIVZdIb0UaGD6BEaVGTx6MR3ZmiJcSy38nru/U5YMAKOPdfns/qc7PglRf +pucZqQa9uE30Ao9zLduVWVdO/oUOO6DhhTwdIPrZ7VuvZDH6J5EuX0iAml8njb/J +yuE3S+YQmSOrNdEOb0zBOH0kWIQ6i93DkbrU3f5L+iWL+ZHs3ANtC31r2k6AWfuL +PF9rZmmJbz6lOy4izJxsweh7ImJ/WuQT1vgxWTwFE6L2ywzD4b28xeGReL5MCsK8 +BxovMyxEJdWCuPWESsIcTmsjucSyv0El12cjMersOjvLn8MZm+TphSsI9eaI/2Sg +ACfkMkvxanSm+oy2PsocPt9+/oNbKwAzKbcQ+wG+SB+hw1ZSjoK47SKLPuSF5rYk +0oxlPwEG+wLECYjE8fDtonvT0parUblBXn2M+/PxEVAf6GTit2bb4RdQf8bA0PZJ +v0PNxuaejkK00dEbA4zY/Tpo30RLYFg1L53Cwy+smQyXPQk5k93CUoNrytaPF+YT +Z51O9ZOxBv7Gq8f3lEnowPVvqDVUVmEdBk3zWCKCXpwLBh1f+fdCIOMim//31tRj +q1cLZNidLe/7QVTtVHGDXnL+JS/WzHFP5lIJC5F4hahlTxA+2l9D4YuSPpch6Ssv +BUN/54TPWn7kLqvEUyGcAy7gmyY/MaWmiQry9h7NYjsuEkF+7po0HbQ+VxJH3qfx +O4CVlxcn+IVzIvRiZJ5Zf+INSWdr6DPGTTJAXVrA6oHt5VYf4I/RbjvE3lkktUEr +NB1/PkopzX5rWe6WEC9SGhG6cuD0oHs+LUFwXq2AchleoRriyfP/PnOE0qm1LXEb +gr/S/D8gBvGHfmjFD4XUk6WOQX3lCGbkLIucf6uj8SqJ0MBV4ZG5VtylJ8Dzh3PB +xsGnC6MUJBXl7t/qtdWKE/+8Gn9vOSpAWTO6h6q2c3787drjlYPHCSb6y/N6VLWh +DUDjkb8Wedj4wpkri2CnPyotc5xJnyEYuHCEtz7BNzQVCqgR6pPagBJs9ebeSe9A +Bw9TluP6D3LzVBnYRNH5CxHcH/XJRZK46yA37DXByKmc4naBcO3tDXQf120yGlhK +Id91U8U7MLMA3/D7u7No05nbzi1OxxJPWOrAWnGHrl+tV8ZE1gGBL3mkmCws6KtP +uZqQB7CrPXH0I7x7uQXus5x+bJagi/cBsllosvJisPMrzi68Ms3LirjgDhsCkaE2 +uCboBWO0ylwya45Ze37WLs89dt1hLARcWBfJEJIkqPMIRNc88mn/yDg5CQ+f7oqm +SsMHeqXQXwJZBGMFM4b9h27oaIbXHq609EAhaEkZP8kOmG/G3A/QQgld4KcVPN87 +TZPnkThZB5v8e+VVGM7XNhS65hqOlSGf+DZJCC4IdBaIDHROoYazaWS9HM/hBQnw +H8wOWnFrC4MWaG0mBxD0uQ+QWZDwqWoGFcv6WSrO9YL6tMjUKj4/i5zpj9aDcK8Q +najlHPaxFYrmd8eFI4atl5tkKauovlbhghbH/oVmNlE4jqzIPPv+6iUjo6+whOnD +plQ8PYg8UJCzE68e/KYi5aRzwIKPiO1st19mJ2tndPIXOZOQgSo562f+/GlE0TSi +zRVLMai+hPVVdGLFSx3AaNFL3zChcIP/4wtUYxZozP7Ed8/7RfdmRj1OxpnfGhW+ ++eY+QcoOElsCKruQa2LYKCKnbdSiKBxqQwZSGHZr1wvmiV4XBq02mLsHYj9s0o/O +r1ckDLwBQXQG6/e0tRko+QJXKqp2GtH8darXNEtGVk7zIa6Fp1LBgIVnjqQTv4Jd +k3KAyJ2256YXBdgVCO9xhqK0pNYBs7RcBpAwM6wj8FTIiUQ15NinhAGp4FbD/0nt +5DRM+tvEFOdN6AARAgNsKYgkyxYVPyvhZpz81qeIUquMhws8ho9L38or6+1bdBAv +jNKeKs+wYHbZS77zUX3IDJOOUGwEcpDe0z4iD5F8d5epwy/92EPBrlm8Y2a/A29Q +gKc3HI7o9NERsY5LU5GqNOPkZOggWM8CKolEz6yfMiae0BKw39OOZjM3kfwGavcL +rztEqZH8ywuxHz8eZUIi8q8bhG3dSzQngpS9pPxsvDGBtQ4o3Cl6yE0ygj0xQjxv +1CPRtktW/RZyjI9Lo7pv5MYuRaXLvRquZCF6+8oNAhTQrJvTX6apLv/Bl1ynvUKi +OzzpuOA7GD9hVKdjvuyGcxUS2T1OvRUOhBVtTdd2OZwsjparhKjzzIL3y5C041+9 +VlqAQ8sa6xqs0wdNVSOSi+PsI3JOyiJ2sq0jSS0+Me7H1+4A0ai4vqg1mlLDlXMS +mI2p/DzOaXQDRxN9ml1m31aF8wcH/2i7DZ82duiR9qtMtXE1jxs7RAiDhcyvYT5p +8wmgYJkjXGxwPRqLBPCYvKKGBOqGNdV/NUXJCf7KjrBEGBtofb70jHL9M0jYGwN0 +mZCPisKC25QKt9ZLPcRm8msR0ti2k2E2nsmGoKDkZvnNVMLdEA0u45CebRCBUqo9 +3xqLdTW94QpNI4XAu0pA9lIzRAzez2/0NJozrOuzScbX612KP41p+6Ym/smba7AM +3erST3vHpCcGvh9wgioPlKIVpC6iFgWbShmPNRAVecWPYnHwnw7LSLcOkQdvLHCm +U9UUvO5nXKBQZhfE0z/zlhL2URvV6j6y7+ZmssBdIczagHw+SLyAa9TclrlGDpgW +AEJd17gWkzAyZBowgYcvXfp+htKbv68O0mxm/iVNiF288D5SN2QgwCIs2yd8/08W +d8uIT/4YuDmVdaMwq5spcsJXYwpLzzckgBAAUlfZpduUd5XDas/ePTt71MExSc9h +okedq2hcbraL2xgf+Ml6+H0fzEgsNoyydAIacFfuzWcqa/vPLLdYSBAEp8a3mjtc +Yxp57kJH/2DExO0WaqY6sBKDgFvcNwLgJaKaQU5DyxArrqZNk/HLMAc7iKTBNYoi +/ITm9NqxLJ7iaoboVaMu313skoRTQAexCgfCbi3bHnu+09pKdqrYw6Xu5WcIg+JN +Vj0kessoTtgm44DT/jjmujG98CSvI1jG1l4RlhRe2vjMi3BZ6Uz4eF/xAwp1okhi +MRwj3HG2ymVg9IoMWnKG3DZO1KXZTTM4IwTZVuYEKcNdvZlyZ4in9c06sIeFViPq +JP1Spd7XDu3CI0s7SGstRwwcG9VB+q1PJlDuKPq3IG9hdoolGf6Gt/OaCo0UtAuo +iXFUVNFcDW1tXTqlwttSHiF5T/w3Ma9Q7Y0zRidtqU4b87/FjOHlj4S9x+c9u6x8 +WhueGU+1B6GkpkbsduV1JiaTXKCo+f5/DMJ/vxAL75SlmtrUB2rGlKNzK6Fmwupl +0n3XT3IOAN0hloJqBFOH3UyRFQjT0XVI/vPrqBLghtHguFx/eV2ADwYOnEOOkPjU +9FsRNevix+td71QaHz7yvWs8/57YXMU8YI64KITyvXu2WNJts6G0tyB/TcBAL8NV +eM99LElCOhN0M9qbaWYR+A== +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +GI9zPoGKbJfy2uLvVqFFpipF7/f2E0S5JCwnjimYOsXWBfeTRJgBk40QuB7U6ppk +RnRJbZv2OAchR7CcU493ey11kvcRu+CeNfDt8W/FwNevjEwgx6j+pAQG62JczJDr +o/PnmspeWHplQXZHafFrk5KYU72ihYx7h/trZ2z6PscwC7iwkq6yxBspn/mTNfsI ++8dxS8+L4CJWMqe4N2/a8p/cEuapk+wDl7ZL/KiR+F+DZA56sm8QfQ0Lk6Q9Qeqj +hYmgKytI9gqPfVFnHs93nZ3nXu7PLVu/OVCtpZX5R1lTa6klr+sE+NzL6Ni4yPGd +1AlzNXunjlmbzVno8FSMaA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1824 ) +`pragma protect data_block +AXQ5Qa2OI464gGZ360Rr67vUd7TzolMvE+xgiKUVzC2VBgolXmsO1t90yfbP46dR +mh/jrH57yGnxqv8UUrBPLk0/tQadu3ezS3iYP7B7ktnIA3yhLj2dPmuUEivQgWGS +b4dwjQtWTDyGelChU66CogT4DFpaFJ32LDUqN9NOqRJYV5bILduoCjJpfBIJa4Cn +Hlz/tlSkwP3YgJJkc7yFXLgByqFqxKPaiZreu+P5ozbXvd+twLrBhF206HDosMYb +udnkVPMAEm3NIFM2W3/+jh2Pb+9NAbP/k1E+roMpISqIWGCyv0x5LIYyluqNNTTN +7t1YBLRi/tEXV9xPLl+0Uirdu2zkM9J4NnNjI4B6LgaQJyx90Fg3pELvZdQkcypk +ygl7L8ZLWnx3arcpBsWMexpBi3TbTtpS7wkwwPefAnWbI3IWGs5KJzT8ZUr8ko2s +Z6R9fKPFT6gw9tOoqkh04G7rJUqhWjfQwb3cBF42g4CdydwsqdnbBNAX+iu/umog +DbgYl8xXTu4tEiVGaeaWoU/fsskxQxN6WUp987ytSz+jSXZgqerOXbRRA4d9Fwnv +PlWzegeuPbjszIrWU6yQp4l2RhmG4zoe7UycyaCLW+6Bnrskysq077hnNLEHBFj1 +08LjWRFkaDr8KLcClHN6z0rUydt6EfeTMZhd2Ihnx79VronjC7aOq7jB91m1S+3s +iU4/5apxus6iK0sleXQZSWxkM2Ho6iqN65kd2OSDz+YnAfGP7K/GJJse0ZcI4Nz3 +5moYCZJayoxX3e/voS2oMqGaWjySs6qHcj6YHBWwtsAgwyllH9DsECMMfOWMsaDd +aHUYqLDz7jrPIbPWOoV92R1lr5oFBPU6JPv4AxngJ/Kr9/+ia+BPuKs7Lx61AboO +T/VjoctK5L4M79s3Lfy6YYS0jvFTqtZiuN7zLoME74gkSOXL0JnkuzpmiWaG+/AY +734rCDkTkiHlI7eP1wF1aREUg1+h0HcvzytBhFm4XfIkGpq+9Q+YqOEeIrahRSlJ +2ngxaIOlA6pp3242SqSaW0ihctnACi/UoxtA2HklHWNQl2WgMcWDsEqhA6n4Q5r2 +nGtDk6bbvwnjftokgIwekinx9e9T6wi1r2c5cLbIMF0DnXLwYvD6AGDqkuGg2FN1 +24my4mwnzCOVSUfr6XmE8oMo6BLParwh1fZC5zYowPRJSRXCT20L0o7uOpaAnwZr +oK0g0z6vzG3SAJlkEGQXdWw8V4ULn7ZtDYFHdRb3PAQXTOaHr8WjvSeT6DePCS8h +P3yxFBcR/mLUtA48SCUx04qH4l90Gi0taDVLC0Gu0/sBbrACFfURGqwneJ2oB4ER +fBHYiaONCWPS3EJ7btcoPjLxmebdX942OvVkjN1fDTLyY1ni81K3o5wPA0jOhGXD +U8PU+xldQjDAQFYYzJ99bnrhfKyQTxquYLUPZnqYy1d34kMC0swCLWhDGYucZqt3 ++RXetjN+bBSRknxd8O69HsJYIe814Uf9Hpc2GHUAbMaGzN9ixylh4i6qxgbCKxQk +UBgrK0xsILH75KnZP/OQLq0C+QWtHxQyOCllILP69QlRp8+EcQWnfh1F2BbnOisv +Y/pDX6rJ/qb4FvJnneIa0lzPR9NQMqyHgJrauuphCXA74HgRxvKgSBa2WpTmKEWk +wnL1Hx15qR8MqbS6kyvPww4FD7SJ2A+p61v8x9lmiK6tCsnBQZrNk/wNUWqk/jQm +BhVfPc8vFfkVdcR8+Bo2qo08qSVW8jp9ZbQ9Cr0c1QgeKm1u8T3ig3qZaevnehf6 +z7QpXCZHUY4FXSPKMUTPqPj6ETUbZi6qozi/CBKAsTG41/Ps+Wsix2X3IA0VdzwV +Azw53vScURpLzk25Hh+rm3AlOTnFQe3frjklqNekflvJ+6gHbx3xCHVqKP2RpwMB +5URU8WKvZXkso1j5oYxw51If+rOZDq7sNchOW5RJvnqY5s3FzyxtSVufn2JDLNWZ +h/EjUx3Of5U5psZAHYm6R5cN9fdkknxKN2XuuA56Nk3Kh+dS34/0w8cdRi4vgjYZ +bz5Geod3rcyu9gtNtE6qAUnaY8OT6vAkibllrQvZMbffuMOucpe0RI6ReI1mTh69 +EbN2m4fMLQyYvPWQ2xYaiatxeDG2ptL+PUF7Wcbfo4i3788cg5hO3Vug32Nv22YN +b2UIkqKqLpGGmCUI8QyrYlPzidzFMpJnIMDe02tMAOD+eV5T+o5zX/OFa1x3xKVQ +RHuTIbeWKNyN9pXUyeHaos/evAe6KkA71793lBLaIru2totmPZuqiNw0ZcWlPPgP +3yZC03I1kVMuVAcuOp9HWtTQTH5ymzpEwpzSJ9kq1rVMT/pvaRRnRa5So7Fh9xml +wjnrDkbbzTuGM7mqUEKXfmidtgnfA3bzq1I87BY/IGE6n8jHwMvBRwdEjnLdfj9k +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +FriMp8xwFwm0LMCvekNwlbVBo1AZgDrmVtXw5xoD88CNjKwH072pbhCEvnL8vRnl +vwGDwLxlRtlWQ4sJTitZ35eQEa1/sG6RQZQgx3YRT8HTCrZEOstluUKNA65H7R5F +RrDJXRVBFyM87875G2KnKbK1qciEHc7doXhzDW8cxk4WNln7mBb59Q8+4ulz7Jfb +6CzMT/u92j/YQMXR8AhnC6Pja8wdJWzpF6niWmDVnN5I/Cn5/moWgLPZcQGs5uX0 +EE61iFIk4nVjslZ2wvRuE2KADoIXbCvvM3dB0EI94cVmNvXbWccVsGk6CSLHTYe0 +AJXHTXUxbjKoGNyhUhGkLQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 41984 ) +`pragma protect data_block +JNjowIfsT2PtKwZSqh31spktaerSsONTTAwEjy3H6YNY2/rvCMy7Z1McdBBZM9K8 +4DGBOhpqLlYoul0cZLw02zLTFNumYLtIouMgePR4fj7782eYQuX7+vhemoWeIX7L +sdVpb0P+t12x4i3ph4BHmuHAwZrnfxfcz/38L0wkCzlnbT5ijPg4W5R09jbmOLRy +0U7myUXnbMhP3omnzh8cWV5MmRtg9dqQdLGCCuQlTRmffNwKhxs39uhcCVp64/oQ +7tOXWFgR4cRYs7zNCVtrBPTdDcjFO8dXSYyLqyYaEc8gmSFhSjMbzw1z7HTjJh74 +oHL/YUcqEVI3ZF87eh65KzwOXdsk4ni/hdI74CKS8vL+NCKafK7VhzfX7D45sRAU +8nzN4Kapit2hNwrpMmX5krUcziv2tBVteJ/fO6nRqU8RAHfZHITh+a9xH/KpZ57a +7uodaE7uM81gvcnvCy7PQ/2m4Pj1ej0n0yCOO22Gg1iuP8AIx4hzryQce4UbqR49 +M6FCFKhwl7SIG/GH1B3ZZ0j3mP3Lt4WIyTYh6Lhlz7H8x3wrQ0MYECsChRbr4ky5 +SCoCCUnT11N5btkcj+nrQEu//OACUjkYt4qJUZe8gO7llGR9eG/T12cnh/g+iN4R +do02kRKWo6Tde5fRM19uRHvtXHlH2IIIt6tQh0ceJQzX8HADIPgAASHdHCluRYnK +Nq34VVJ1roK4pK69ecqvfeymIPqCay1NCYUs+JlZcG2S3O0yZfGcNT37m0caga4S +Aao77wX6RlHdl5zBgSpiXZYqO2K+bL8XUUgzFVOu8Rd/eoK/PEagQBbrD6P1cauq +v1ZEAGpPeDm3zBbgz1Ukxa7sGohJlvjzr3MVChXdYQ2x0Wi5tmqSBUaiHLA+qtL9 +l13WeEXGsvgaI6X1MHzbOv/BC50PvHB0hMum5fzYgQoGEtt0hgCTTAmIZec5qc/q +0qoEt8Smr4elvH3eUz1EESxvEs+8BnymD8WR29hNTmhqHC124yd5exRszPWkQJXJ +BO02EPTwam6FxxjIttPd/3zwiFSMyoHAQbgdiB4hSZOdu/yuN8NJG63Ffus1Tndd +kyiFmIHVk1QwxeRa+vdfbJWAKuQmnUfY9d1CPeO5pUhG47JBK49XSCQRGklDrx/J +XXffrSFKfp3GbBk9TPhl14SCxCjk3ZKjRZYSKUT8LJxk156didFzni3D3nGvNAUE +r6Wn+R620kauXkypjBYgFfMLwTr/gK1A2SfPlg2taGs/esG6WJqNX75xdR4FXmdx +N4Uf2WaAUH/MxIggTtcx6J28uVGRGNY2wTNLviemtACjUAmbmcwxMnSZTewyIaab +YL687d9OdQyYfJxrXry4wQdd22vRiQDy0ecAowNYRsvLIIfQen1OLm4a9qV+iuh7 +zV2zaJdAsarydyHbrn6zwkNhEDrZHB/mWZOuwtWD2PPUjO+hThIoYDf4F91CiY9u +H5lHBIdKodPKpZovm8aCaQi+hQmlIC1sdJzDhhj8AO75WGTM4uTG0CyZCHg6+rTg +bF+5MRublv1HOJvMH26iHs9h2o44iAGQEPyPgiRIXxAnfGLKbJtxxCxESj47EbD2 +hM+eXxgv8bi7BPNcP6IOtChFzi9GawFpE/zwkjEMdx4qMaWYbqnmsTT7PF3Prygd +0xirj17+HrxoIBDKB+U4m7ZFRWJeY+elTMfolgn3RDNPWkiBNyx0YYQQhvRGJzDu +58Yj1lQYrjKZOFkJqJA4eb5aGiRxMGFfVjDV0g0MtJ2c5OqsLAk4UoNa1us/xo6z +pzgUlDXoPB1wEu3YVmAnv3A52DlgRxbDAAQhN/un1yebO8bvxQU8mQMwdyg8s0f6 +dc0P65NZIEVpXJ2T4/UvwkKL7ScO3eYraUJ0yxkkuV44BrB8q4QUH3QE+piooS0Z +oX1h8XbMXLvIiBEOBF9KqdZYO0XjpQhIZ9idF7pUkJ4oaH+kaWnE4DhdRehX0Eqn +TlTAVF78PGjMx0dBp3MQsP2slAxac7/x5ciIlX6JCqzHu86ue2GNcERRDVfDzrQ9 +J5OXnP/M0Y+f3gDfRu6c2knzOv2uTppYxf5VLgggvivkAsJApNyFLvV/fNcKSUL8 +MFe3R6whm9WTi7F2ux67pv86Loqqmy7BrCCkpHjuwaznClDtonSu3Ae1cXnUvoyZ +5is7MJjmCK+lPqAIh/uwITmxgNvNLDEN4I/bYI/dMgo7P959ZAwZXyjEDCfWjtl8 +xECu1CGLDDaxtLcBEjG6V2/0/bu6oGGY+qLJ6dzdRKhHsVxIPzQB98FgjvuN+i4U +Jf/SEoPgiUFFE3yvRj+tQdAe8t+gpFcbtS7nMFPa73gF5vSHCEZ379Kc7cm5hKjT +k5YX1S91S1LpA/2/sEWIFNBFGs0+lynwk17smQlbmyFbRcmWhgr24VOR9T2CS6Jv +k1/k1kT6nd6qNn2QRHsGSQUryVQa4wXKZezi70y0vDdpd7JQTbJy4dPTUGJfJ/jf +DadsedN6eyRUmDTmZ85lRo/goB8+kTS1WaC2wSXcG3B5JEK9oOam/aVIyymUhDQS +hgv/Cdq45UFwopRPlrTJVk+Ons5vOepNriWqBZH4wSjV0yqq4HeIFTlb0xRHiJsx +mH3ZjYvN9Tyhs0xmqI3yM+kDY7Er8HLKcrpF0iJKoHhUn4ZuT49iBdedG0Vg+YUW +PgvWrjqMgwlBJKKl/KjqVGlMPTf1ghpnW/LFqn5LD2tFONdldCtLBFDGlloPIGsB +ovTr5Gv8CKhPEkJlFtmPSjwRUlhXyQzfj5jd1xdkp3MBscdWQ37UhHfs6ZSQPgML +HcTzIwdOFjKuABA4GdmtF1u04L09gcudVg4YHXUSuji5Y2WbqUk7YfrOPRdSPMus +/f3wjoxCifuhDO1Qquklc2rmm4H4TG+/5RTD0459vtcw/KO36aNEKM0SVLqDkVk0 +6qisCRfZatlLWdUooeoAInP4oBxxygi7ya3MDmNsAhLTQLE6W+jF7mdTmvBpE5if +PI4hHuJdBckXiL6OKDu2myfrA5IIOh7iIgJpFW5vKyBHYkl2ECV4PPYobNzjBdx0 +lkovNN2VCXhsakgOaK4L/qSEmpt/cuV81WDuhHzmEkNSaQFHE4D3VxhWCkYzadD/ +sPk09puy4ReirRxGtciytaCz4FB/DhG6c/jhl46gDrjAQykV/hCZzdcS2FhLuRQ6 +wF5/qks7ee3nsPMBu/00RTP3KaOVjQ/EwAKavuDoFMNEqvgxgs9YBUErtyZ5BfdT +lSCWHmZsLh66/SubnAp6VOuQwKM/+Fh9Z3oywGqX5ux4ZraJFmQJYHuiP+m8iU3R +QopK5vcYFMlOedbmUKC3agAC1ef1XBEjHeyUi33Jm7eKOMqL1EsqJmlQTbDPyrGN +yaHQcag7OJyDSQpv8Ms5DVh9mSzjpB4jrXVgAvc0P8EZmUAawpbFWO4FVoHFlklW +pCxckBSx/hUJciMm+Dmenq+7aSdo3xYR9qT3LYlCLw5cgGZeRouPycrzLJ41Z7tB +B+CMDa2mzD/Q1HsHsBoUKWukqmpXN43B/vQ7F3ul9CKB4T67RAniOWPGxWFsrxeq +9YyJe/GqnSF19mb3rwCqQ17oRcxDVZ1XKRiyUP1rwqtZ1zx5cHsfJ9JsAt1VJes4 +NzKWgZorJgrVZpkOAeJgsuG1FNDfS9L3sYiwROJb7SkvVTKNV6hSGpLHod8Et64N +3XMlMARMffpfkezHwx8BTlons2LA8++CwR3eOyvtU2rP/k5V4WjUHx9v1SpQszPo +5HQIHKv+6CXmr2J3hf5cp44LJD3BKgmt9f9XFigKzznxtK0qjdd6sOyQWey6k9hp +ewtgA1u0nAT8mliYPtQP01yVvzW2aQI5TB2NSR4+YWFe2hBrcNQaqWCFDnInv7/V +aswU3ZuGrT2htdlziLzuCCon+VbIYmTWLHp+GuwGsnGyudpEFpg1hawhCmHrazDj +fi5R5wTUr+Xty+Ry38YEOkFH6nnTz4jga4zuhjGWE/hkWZk3tH18L/qfMjshqE/T ++uFhmFlJ4l6SNg7Ioj5g3z6gkRmBElskgseYfg4eh6MnqfhXVRc+53wA3Mq1TsBZ +bINIcgDUm0nBloY/DTSWP1sapsQpQ7YL8KE8yJuQmrul70xRQzpYg+hd+JHHqX0U +5L00hs4x3vCNcE23m/kBhpsb5n/HcUcFqY5VWIEhfH5ATLu93/lQGclkSCHsdQpO +Hv5iazW/FaMcfWWnXQ1E1tqNKectMBTzOLf6L1UkrLPJ4lxe/cliE+Rnns3MFCOy +MsVGa4fNp+/jIIDryR1LLobnaKbuY79KkoN0tu+eGrRJRXHsPBRwfAqQ30r7I69g +UeKKH50FKU5/IDeR2wiZxJYWWAXRDz7wTQCwO++J3+RGBPv1JkMM6IpEibPL2Qrw +wZkTg52mmoOrMjIHgzs/nFxmJTxfy0PXTCz5SGGBLLNyx0T0Cq0jXeI8mUKZFNao +ExBxODBF+l5oy2c2OY89pcS6e8WFdtS33/vZ4dp/6bSObtxYm8orFITSNrshV1Wh +wPNo9JiPrx/Q8ebON5r0qF/4X39zl32OfQH5kgrtQ5/i8jDZtgKPtj3PlWjXSPda +1Wu4aK3zrNPoxeC3N0VW9WtuPpH6aKQhnCoRjxGOvNzbqUAZZLJeEhy1mYZZBoSE +og41VlwRpoI8Sqt5BYtByf7iEjc4DWWgXKch7VYhy5/RFG4bq5eqmzSz/VEH5gAR +N6+8NsZ2PSa2lVyc7104iaON15NfMl8CL8nMfZhmdXaUe5MZmssc2lvqXG1B6WvR +MLhmPGJsDwZY6ktLCyrEb2qdCdJUxrwLyO8lCncDwZU/sb0/tRWXvFkhe7mGQr4y +AlKmzXG6S1mFRwoCrqTFo5OMol/xqef+V6BP44NkM0d7KkmIl02K6ooUrxclaHMZ +3vrRmZwkl1XWI67eaCDs2zA742WwMdPs603Iw3nbUVY8vA4Mr+vBXBq2yWfuvT6U +nEkeAyMmdtGUQ1Qvj6sDfhN6RfwNx8K9m81DkucXm371vedli4ctvCgiPTP/Lf20 +1P7cE1KCfnDu4NuCBmy6HMHo40PRxhHwmTpKSZwJRGOL9qJ9j8EUCiLShU53HM6I ++lS7e+Bt4+lRvGqr6OMs9Rj+CKndu2I4QyM5cmT6HZxMjL3ifpwA9Xn8b9/z4hFU +VVVpLG0FaE20oa6sTqL638pe3Rs0JAk/96ygCbJRV5Q+0F3YDP9ESqvHAMgZdir5 +zTazpRTURSDheRLE7ScVA/aHkr71M1t0opwJXnw1fW9hgAhBXuoTBj40Zn3em5E7 +OGmrPWUkbtrv8ZZOzFYoPY5anDCd46mEQAMd6aXgXuQYlzH8vpGLyhUjRtG3iZyz +RWm4lzrna0DmkGZjPB6RpehM347HP9XjnGE/5PH7I6xVkNUK2c5AkXAt+sK/qyyz +vn+l7A7DBoxutCkoy606kx62P+sDnCfLAS+f8BV/f2j5GTNs8x7IvWNfKpfEaRjZ +IHNM0cxvKQHG+k3GmOZzLAYgTNchqdcJ8moMK4f24D2NNKh/kkV047DtMudr30wQ +Yk76A/7zgwaXH2JmwWNlWV8o8USMXJM8R5XcG+TxdxI/e6gdZoQpNS1TOoi2wxYm +sosN+ciBcO18+UqZ1Op5FWpFqaIlAhHQkpiZCy0JD9oUw9z9jJ8QYZbaQvWkMfUr +3+VBXtuhmlw28K5eNG5kKqFXTAxTtuJX9QhLDS3yDfq3LWAmwWBRgoXI6PMVHY2j +ogn5yXZahIaChSIahcKoDNALgjB24zeOjMpFSQw4oE8NAwhXcJXcwBGA9WAl2kD8 +8ReCka1ntk1sC9Z6upOgfMD7E+JyDlmaR4WWSbA6/6ReW5FPljmbTh53eoYLkUOq +1O74wy35XO0kj6zmbX263D973MDIu/f64DNWlO2yH8XQFoRPjVPNmZ5dN2QEySYu +8r8fk7UC+bhT/TSSzYUlePlup7NMUINJWMI06j9VSsMycH8aVu5WKC2UnkRrjm6+ +qlUv0uNU4xIcNlFRfFyYTC8YX0UdXAYC+gELKyWGFBMkkEsBDDPqx8PkCkWGK1tX +mXbNnpZsJsJM1YhHm47Tu/4CuGlSt55Tg42qRwHtorv04hkHPl2VDFUj5SjS3qZ2 +vIkx9aVfq8gu8n+OGhQemm3wJJTYfc4d3qclpaefPxBR8LwZ4CiVAVSH5NtHE8N2 +IElvwgUHHH6LzhBpkkJkbh7XLLGY3uEbU5ZjWe81rXJbkJKYGChsxDB7eGEEa3hI +W45vvNR1Aj8tKsOcjfi1TAYxU+wJHYiCN8ptXdQ5kaXKMxx4cueT+VpNuBikRIVI +KhpTr3cOzKJI/7ZZxSo24VKc8zn/Ki5mOIKBdp+ptp6ZulRgZLdf2bF6xfCxnyjS +9uWf1RFZe341SDwowiO/88nQMvse8FBEvBzFtJ5fdAHPyHZbRwTi0Rnt3kysagqA +7N1XUSOxgpxXbYdpVs1wYkLIYNhAVwe1VPzbKQBmk0eqAn12K8DO/B34rHGIyh9g +qoiWtutv22y5WLCKPEpRkuzmeLxGGqAaioPA6HWl2YEQESBKSMsrpYyJgXCNxO7g +/TESBC6ykcbCGhtpdBZgBnUfVadEl3yjuAruzKc5NBfOvL08VEnJeJrdHvUw8dpv +3WTKSjmp55rWG61dw2jBs2cOsOwBVzb7YzRr/XWALEW2+U9JVS9pdEU34c43GILx +ip+hL1+fzV2iuq66ARnKjGoXm+yabfC3zDNY68b34nhr/Zr6sU5pvOgRK308aqWf +3qwLS7NEXHXwf5AgLo8miqM6XRObk7C4HhOBtkhUGJkpDoNmDSBgxVCjZTsrnH9a +8E9VAm18vGPIcYPm49yMCpYe86mcmCMNulN3Dg5AjeaGZ6Sv/S6OIU3P1vTFObPm +ktupdogUiBL07NeyUMwWKnS/3Tr/aukT1nrhpkaorx25Gkzh1gjD8/Ey/P+9ZRtP +umSv/tthgBwZLURRt8Bpq9rIajAEHYsXW+YmzS/+dqQf+MS6IWT2MVS93a4VYQWN +H9HV/Dol5Mg9VRj+UxJwiT/d0b/+hsLq82pHbTspFwOcVd7v/Ld1Pp7wmzKZFrPA +eyiglGp1aNOK7luh/UKxMwIptxgaEYoMoW9gLrdUX+w4Ibm/9mRI0duzTf+GcUoq +wdDosaVA0qIgsCPysPb5Rxs2sUeNF7Rw7lj7zz7Y6oXw44DejE23HD4wbZ8NxcLK +bXxnnDr0Erw1XaYZkpeobMUxubYFDf3gOcmaXlj0N6SVLnd10vW6Y5tSLQ9jAoES +6tmM76LCxmAXGSxqJtjh4UP5yjh0npD2Wy4aSmw4Bdqv80P85sRbf91pJcPwYtwJ +z/t5BfZKKMRUWzD1FkOdvP5g205Kp2v11cYtHZnUdL8AvkOHj/F+vy9c29qRhwDo +JqbgaXW0Rz8JlEmshrs8NY3ncYD4bJntuoqR3HWQ1EqVmxoInCGEamsaFggg2EkY +BI6fw4Gr4GQxzOegaeply2heY86OUi/vQej3eY3S0TZTQ52LP7TbZvIqxNs3QSou +VUwU5TbeaUMIMT1dY4xEioEQb1BQJF0aUXiqQgeJfxeH2elY5LN2ZoXzpWBbjG1R +cUhdfBAFa53rxWAdapuynkj9Sj5A5TiEBAWUM/XkJhNU7gdCIVwQ0OGeNZoHC1Qt +X+SK16n5DOJe9NAesxA+1EIKPaoSkd5EjSb5Xkp+YxbcwvBME0Uwx1uMzKUTGj6+ +lJPe+UDwkd8oOisYlE/cvYE2voQi/oiNHHfb5jHkVjCT1ZvMqKmcnLSIx/C1teFf +tRGfYL7cvAviMsSZjjhWykUKv13yF8djZiH+VTTjD604L0xB+jN03mLHDpr0Xy8E +tjyIqcsgASFdYblK0gVKfnHF1SLTcJZa5g4cdBQkbDaLV3pzS01gvEiB2j/nVTpv +im2cY5poB2oI7vMXcAcKb8b8JOTbuH4AFCZGFt7sQR1G/eNRoR7zAqmztJsP0u78 +90d0bU10tw9s7el8EX3bEovgZOB5E2/VrpjKJeWlx1o/O6BJuk/8DlzT0GtdaWbh +dL+fqfmTkaSPDkPtYvJNvxY8w3L+FFcXwiHW3zT0Eou+6nnM3bxrgXT8JQYeU3jQ +46mQ4IdaqiS+8wYhe1VYik4f25tke+cN+pWIhHuBjuuRApKG+37Q3ktTrnqwWPRd +QfSfrUDKJMD8q37z3qvmZs/mk9WChGl5R5nOUoa4lS9mSbw/HL9TPn9mx2XxdeWh +j1P/rrZlsdex/z7q6PK6NJzwPKZP1C/fsXZp+pmyNMGKZHMM/ggd5Nr8QHC5D8kh +Ok0I5RrKIYgvvL+rc8mUbgdW7A1z1lm45P+qvcOILymckZqYPVSN09vwEVYQWME1 +qwqa4O665oizwmsXydonXyIaWgJIVe1GsPpkh9nZR1hksXtgt8YVSakKWMkUnSwg +oZf41LNcqS8smw8AnSPYx5eHm/+5/TanG06G0o+73IA/QHB0MBNtHpTIv1t/+0Cr +TYwt3PJXVqK+1X1m7FIowqO8+7PkOTcobX6DIVJVsQJi0mkp3w0Y2c08UWA9u1h7 +UCsGf8UQjE1o0KHEQyzGKDzGYGbuKMKC66CxDZHU12KLKnhUkjwS4poSYahYRrkC +8kOYsYRx+9S+DXO1FL0htWQujW1Ov2jBNgy/GgBxJ0rje4GKvvqqLcmMPG5IM+lQ +1XuPjk4ch2VX76cstytiuYWelk6SsHhXiDG5yrq4ZSpCdv/FkocGUu02mFzR1waf +ZSELmQ02t7ZX2kJouUfe2YZC2UC6NRBWaPea1mYYFyReNXurMkwTmeP3MeVOke+D +9L1tr04G0knCZ/wkCmX3skMrcAsaXWSZeOFeIA6eU1qkPagI4Xf0i6CBaDsh7AGL +aUY+9Kdq/q+02enczz6KT17m3LETPoCX79ZmRDayeEg+BLHUCBrx/s4kwg4zuNcL +XlJXWdbX+S4/vWp7iP1m38kk98PpPu4n7GMNqF+lykgIGXgVYA1t3YOZzNpOPLg3 +4wiyL9qVWWZaeV9rn/YTVG1EfFrWwrcHEyZgVc/UmrYvPvymJX7zzAzhv/0kFSdM +5a/6JYQVfyeE8qtxJ6cxYmasCLvrGPIziEUarUYDXW68N1RXxZBoCoo56BugwCNu +FCz2ibkqJoejsoQOT5oN9g1sttBfbTL0tN6LUUjQtwuIb7NrBh8ms2lPOWjorYh8 +9/J8o5LzLL5T5gDPPMwfxi8sS26njjS2FfT34LDv/VQdFJ10cS00w23/5sM2qbSr +snJYS7o7kGiG3MbUHdwddYbpT262fDrpOY9C4JJNgRcV17srf4bLA6+TQ0/j0t7t +lkQ3PaKNAm6ZCSNnjM2p5Z5I6k+D+IRyAI7D9ZnKZmvETONZTbYFvbhAvMKnd5zx +FydBJF94Fuqp20qFS2tAtbVozOblnlw4gIg5T8qD3BVQVLFx9EnUynLR9VKehQ3D +0xtlfhNYx2p16i2W831ferKvH+QmZmAv0/OJdHe3fJS7QCNofLUfJTbzjNaswshY +2836C5vUmtBWk3a6W5EbhSdsLjEUqVUcLLjOHioCo4G9jxydRSdoRJUdpdnbTlZa +X7pIQ30CCyxr0W9JKg7dEzLKohof7egLknkfkyWrb1YpOPMcbZkoYTg46hP6Xzna +oLrwzUZRiI2pl9ajLZFDzlg6SI74miXNqW4/L5mxwTv4YMa1KqzanvW+f4rLuoKd +m9JoeyzBnLuS3JIVvThhmWzFjtKP/+P9gUfhgyV0Q1j+iPdtpXgDMgJcF+Zt4ZFF +MCZrOjztrdEBO73X5zQDOnVzymDdHAwSlbKNdEA4nQnmN9x68xIzf8OJmv8t8SBI +AlOO9LFUongj6jzx6Mjip1Ff7wkzn8X4c5r9+fEbnM2eH/IvXYVY2qeZdHN3zhGw +Kjja1x1+cpyOyf0i6kFDS8cmGHoPM8D+VkISQ/fjz5mU6CuOb0MnE9jLiFgrjaX5 +q804lz6dbH0Z6jPtirSV7ySoZU1kde8ObgS75M3NNv4L+zC/YyZJDeKU+2ksIK0x +1GGxk51CKuXV5F/XSCpl72wZtkR4ZfDiRDdwvMILCEvtADbU8LcjI0CiLEy3dRnR +pJWDCUmmNzheTMqsIU4OtpBmu9tLMs8iNufU6mGwEPxVU2pTpTgWefpNu/wwyD1z +fFu529/A7ck/dVyc3qsYzN9l+/RP4EowPsrHIUr0u1D3dO7NXfJEeFCahQxKEwEl +SJpGYEAgWHNMcXi+sv4CP2HT/Fl/hJ42PdV3wqTd3yqALRCmGw/EQ1rltzwDmfTx +E1PBPA5BAzAZgzaTimPxJQb4V9uzTsORg0+oNejfOXw0k8jupFlNpprLuSNmm/k4 +yOecv/csDDmH7fg2MVd15inVqE4dJndKfWB3isPfTUepv3OdSWuZnZWOII3/ytUe +XI51emL6VDBlUwEF8lkQrHTa4D5viDHXCOdxCcjUZN4PrTRRAwA1E9Y60ppPtGDi +ZPejXegYqWvqZ7ZJAUeZLHmGAT9ZVOIT9EM99/0tkLSQ30ZSXEL4ZE9WCjAUzwSI +dl9a/HtlQRnC4IIgWG10LYfdKjX5JjG2lMxinVO7jJ3i9RrPfHP7+fdjTFf/b5Hh +AHOpYV49I3cwfKDp6q7MnLw+te2DDavXwWp5/aoPbtCsYmDmfDjnaKNkrauvI4JJ +fBw3E2G42fh5G1Twjt65RmzSlcI6CQqaacpZqCsiTsdm0rrM4NB7rsoM05ihipEb +zqdywqmwAEdA9nO9PcU5L5oyUtViDW9ds6NvkmVzSmFhN+OoLLjqFVApfBsxuDol +qjEk4yF+WVXN3yqEetHs47bY60ItMCJDGvZYQfGgfmXfqYoNk3vWbmWWmSlDX16V +P/bRTj1Q6oqWxsCOjiLUZGI/U7K83y8yaszm2xyBVDCWWMtw9CGLoZN9erskuY0i +Gb4GqG5dhSNEHtreBGFEyCl3yrNofdeFCXiWNhN6mFb4+M5s6RUP+1Chf9V5rcNr +Iwkrvu6OtttkoC9X7CKekzQpST9f1I/iErugphrbw19a2ZITrBGv0e2VLRA5hdGD ++Sy7m2D2eZafliXD2oBFNHxxPQPBJL3rQAgvKdDE+XxlzpCbAc8ex4s8D4yKFgt3 +aHbhE+I8zD9QKLgABFOKdnJbu5FBXfq+NPG5md7wrD+6a9bNLuimwsUhKswUu+3x +H9tP1a/IroW5Uq5T6FjiV2QvgmMkzt+9bdzjv4gdUtnm41QRkuVzqQCFpTxcenVd +KWg+WLhkfrf19FTmDneqpnMKyv8wffzQavz171D8avuAK11E+Xe5UcJoGvFP/Vbv +jl4CTsK1rxafT0bObfdu8U1rTSpy/6inGJF0efH/uDUPcTW/YeRoGZNW61WtI1K3 +U6DzNFn52xudLhcPiZkjtFhvG9MwraL/aBeJ41MDwDTZiA5FezKEboFV6qeEmge2 +UlOJ4FGeIqSmr1x2DCyPlVepK/dJy+4WkV6ejvu9B5mzT+BjkXvvyi3OjDRdGJwr +xL8gJG6x8Vn5SfEqvvLbRiC2d/mm57R3+bWJmm2zSqeY7WGfjHxKBSlm2f9NPSv0 +/zv3XY/GLFz8m83yS0crkByyvTgoUgaD/y5DH8ySE3+DxvdXSHnMt+SdLy6FEHzG +a7GLdrK9pg3i52PwxrFYXnmCsTG/pUzJ+Cs+l7y6A/oKBlrAb4b5Qszp2RMEH4oA +8JL2SEm0DT15XgpShSFWSukJal9d/WYmrBLxr+1LeKSTb2T1mTiSHwpDzMHBs3YC +/0MLB47xEmcOIKf4ysmBcI8K/XbzXJXfy3Uz/p7u/kLhRv17B/FOfM7Ph/agYlmf +yJXjDhej0Vfrh6CkpU2zwGodLLEZevof96LHObr1PFpwPAyIih9dcCC3kW7vYLa0 +4SFo4+tk4OkBnX08qFUAoZp8znrQtZ370fQNfHSEB+QLrQjByK7LVGFl21xX6zYx +85zNLDdijLLHGpNZAYua4lLp05HV17wSqy2i6L5lheg1vNC1pEOmL9ofCDfYIzUY +w4hoXeIqBCw44Gjcbf8gp1/heDLELYpcV3t6Lh1F7y6LVbU6YzqzZeUyYjpivlB4 +EvBLMikp5FgZIKdzKkhreiyjXzj4r0Pg108ITI3Ehnhsvp2UIsd0wzGUETsR4q90 +7lTfIp5FiO2gQj1V+u18QXvu7IPn6IuwQkNyBT24XbJF1jP5QqRaNgOz8Qsnf7Dj +HGJB2jZW15hi7/Ur71WwVGBxyHuBxy1GWyvD2s3f7iFp36ledhzof+77vRfm8lRK +9J8ClK0cC/3emcCiTn4pHJp8a95Ul+igy6P0FYhW/L/F+8wAwDlgX141v4LTT6d8 +eHKIDL6hS4xxtO026OnGDO7RbBD0A//uYcox/hEKn2xxkGwiR/ZrtqOIvyyaonM4 +MR3bHS2s7kDXQTVHHWeXpH33am5F1l6FmslO7nmkGJgTzhPmINi3IGzb+ki0ZnEd +/mJNDqOj5Zjs1bAemwCwGGLyU7QDSVPBvB0HwxhUWsooMc6JZKipa0WUhsPBPngg +EJsFLh396IdiB8us/FGOaPKTjKlMsgu3T48YYDOHI0+UI6t55ZECSAV2Vpf+75Ae +ZRrjnaG22vehtP3lCC+oYGLJPqhF3M0OXH9fybfOCUNo6E9831jgeutxpHYgQjHQ +aCJhV39RdBy0RnhixG4mSwSBwGzreXj8xzaOTLtNlY3zNjmeKQvwagUBF9CVtLmm +OX6KZiID2xqwQgEl8QJQDyc4I3MGsU+RJGWREYK224isib/ZP2QnPWk4zDdezQAC +2SOpv8M8lfN9cWsBE5TweHt0Q3VMdhuDblj0/tHrl4dciwN7tzpwBPQ6QXFOwoLz +ufe4JebPE3guaHiFrYb/6dqqb3Fx2A+aKm1MfKeFp4/qyE7KmSCm0s7mxtWm7cPQ +kAV7y4Z+V2hK1FxuubIk85eL3ZxStvXxNu8dw1T2R3DSsrhzAnvhP2yoeRaO8FST +jJgWwI5N2RYhG8Vqe9sVyGkbtmfOaudJ2BDkJw9ckol7IqjCp+QIhaC/EvjqaOWJ +fQ0UZNIYfQlOgkFQKV3nvt55LzZlA9M2aXCfeAbPEgoOZpkxe1nuAvjuZgxUuBwZ +fy61CJ9ooK6Qc0qF9SytoQ0Z0K19OE7rB70gKgsmOWxF/pA1jYOyqonR5eZIa602 +gOXXoa0r/WXHZcD90uKDfnmmaJJ928qPkgYE/0RkUs3BipFnWQ4s9ZSgfOUBoLTi ++ee0yx+XoVP3XhcAqU+d9+W0j4SXcZ4xovXclYAjueVp3trt1PzQqMjJlzmb/gHp +A4UYKJ6DNI4xVeYog6obWCn/L9FR+buK/t3J6rWaOOcLDn/rr7vQojCY1EUQKGSe +3pyUcDK1igOCj/j+/JxM/FDXsV43DRfckiJkClntzmuj890YMSMvng2nNazKbTUs +BK/Z8KR6kX81oum4TH1QT0+drqfIX8cGvnVYRnqoEodzUf9jLEZ0nig21wFWNRuk +s8dnrx2HXtspPzCdYyH1qL/ML5j3YOCkKnlgbxGFNsZcx8d9Mg4ZiXsncsVcNAGL +dyE5yQm3dBUEzkHdli3HfG29/eN3oMaHzoc6gglsm/TsSfUovpcKHrwuZGBcEFYO +vwvz5TQHBA8sJULMc0GisMy4ox6yuTvDp3mMrr1gY27k2RTsAfmvOUkcXIXQOZjS +A5/rkUVmFhzrlvue9v2jLfbc8PLM+oEcP7MymzvJE/griYRrSnCg97bNjZOGMF3j +oCEGiKgSMsJ/5RpMIG5WDTpsK+PbHrrNoHqbbNhsb2wQREe4kj7FWoImExytPE8C +KcoKPdcXFBmxJHZSdlj4WJS+/fczTX0L8HI8wRP5yYBo+ZarQ796F3YxxWtIou3Z +suxroh4OOK4z5QBc4Ifh8WNM5IBryufSRqZ8C92Uyil8h287LpwhI+lSGO8u5b2N +4PHHR4F9n6mrGEDjTxqnyLAqki2PRtlmQ2AAfkRmpc2RhE7Le+369nFr6bBjPslK ++wkxR8qWF/J+L6wpgrUyLdyaIDqkn34pLJt2g00L12xWTI81oMm5Y9BAB3xwgV8a +Sf4I4D1gl2WWzSxAcW3Bho9+unRMAr7ocgIW59JAFWKbvJSEvXhYy8o34AWwG7BY +FJmRNjmrhaofcYPjeZMHJio2h9V9DdlOJXXDJbq+OPoPABSImrPw2ZOWURQwStKn +NLH/YISOpbX6QNpa6AyvCWUAO5e2oIlV54xqQ9tfaS+4ud2cVHDI+3ncqtG1X2Ra +gdZOfxJjp3qEZusA0GDWySbqm6zafP7s3FwEAi0WDGVA+NntAqyzZNs4tRYajXmw +ZbkNNY4hrXOetCnJjajM/ZAST6gDOPlJGjcaW2nXbJQ3DLXcRYlEQWg6rgpiR42u +bBRWQjA5SEz4SXdhV2epacQM+SK4+AGVqSRE8IM9dfX2wxrpLUUI9rNGeWyd4zlX +qMo5uuzKx4+gzi4X/W2GXOPUtZtYuBjvyuuiX6vqdnPt6PaS4iWGJp8a/nHV+uQ3 +KgPARiSu6lTSeG8w6aCx+ZXaJ7v222a6DPGXcPYmjCwZXY9wjUTLrftxXaETkn9c +Apc2eYCMPfQin+BDuKTrfv3UD1STSM9SrQaGQIhOGtbQd+5r37wyh04hsdfsoulS +LR9XbtTWC331ruppQorOfV/8k9yh7E2NJ/g6r6M8usycAKV/HcJnh6xDk7inqpac +ZqzUx/cSB9MWx+/lmyjDs5MgDoCNJM2jFCyKaUqc+pXafzbVnaAM/K+Jjaq0htB3 +XBmBoa073Q33Q7+1ZI2p9B+lwWBz5fQ1eeJuOlP9uqvvJzU6TBhqfG26D6i1oG2n +BGBevxVQSt01pC85enPLt64965f78Yf7GwkAeThlQeeAOfLJmVND3zOa8MMvPfSC +i2dOAvz2I1Z1qjv1xRQWPnYXAzC/g/EcKCHMR4OlYJ+HS7QP6iHCStFQ4hqThIDs +N1jHVeK29w/bbs7H/Gwq0Qv2caSwN9VGTRWQQ1jNzAjT/eJKTHAjclPuW+gwoz4V +DdiVEp3lDqrJ21Ip3szsvVbVQJ7+McSvOcym+TpDYWP+wvP6E0gVtrO/oHemCWMj +mGaPQeeE1k4r1nMEuHm97eXJNnMHFeP/RPXnUvAQmcZd3KqlOuEc39gqUD/1grL8 +VewByYAaVC4uj9fCiiyBmwsWN/jLFsEGkm0+prBFvEngGuJpnJsqA0npENam5HVJ +o/BW2AIDfC61/u8Mwn9Y5g9FnyBmPq7j1ZSY7E0l2Bk3Ig9B4sXUavsxaZzVm7BR +uu2CPLzNDxdb/RCj6wrYL1IiGNKF7Z0KrRPRIvAzrWVH6xadlPd3Yy0LPQ7V+x7J +1AlGj/q0kPD3OXpFI3TpnwORUCG2JNiKFI1juFZvmq+YfTlHXITE41Y5L0Ml3AyK +WNRWBa9z7Cv1PashBDgbuaajwDvyA1H82krtnLVx5C0Jppi8WJEhPXkKEWffdy0d +Bz8vc8IPeqG5Nb4hQIEkBQjcGV0bIhUvHBoQVARQs/q4OmSroZTl/cunmCmMfBZZ +1YrvYcd1EwUloLOaVlA/59ACMAu8YlI2BYdGNjgCZDeUxy1LIJezCSAMrTTOlMz1 +kE+BT4ZasdGwgiDQEFlx4mwN7A2om/5sK0np5axqIza4Tm2MjjOKlvtMooEdpIwB +x6jbsIaEnXSb0edOHNzU93p2MnuNRk6dH5U3v3FjN6KRvAj6g8Z+dtqJHfaEx84E +5Sk6JztKoN4EtSxdHp6zCwHmG2sz9ULFduKlssk+Rnk1K7o7Dhi4mvU23uxm6xRM +U8nHmVTKuM0usJ+4WEfQlSRUwPLti3SE/BBOc++ytgjjKoJG+4v+LlyKJ1XkZW6k +8Hmhc0lTRok2uH2GyOrGUBuwFMBH//IAVhaGgcC9btNCEQUJ1gG9kYZZfE2V4sS0 +ax1cvzsPi9jIhi3wlc0j+wKoiusyQTEjPC+tYqsBCmMcr6xN4ns+jJWVXlZNULu6 +qXhec+EvhI62k8P3/DjURtYM/6FLdHN5hWbmWMA853b4rxG6FKyBXMyVcjM62Z3h +tAjhiUzE1IW0h8rGgxcpJsZLubTHv+LY50yr4zcHwa6TS6J2k1XVVXHg10ozbLA7 +KA93wh/XlG7Gz4RhHsTQ2KwEL5sn3LBW2PvxC1RaGSGQsf3Gj57pPaBj5VP4GBf9 +ySS8oeXgapGhIEqv/f8196sQSYPmQEvJkJbH0uLgPMRDSSz4vuxB3N4SxJejE3sK +SbGH7TkdSW94RT3PXH3wI+1M0pWD0lujV/2LnlVkXaIFu9keH+SD3hdR1XULewwE +lzdrCY6tn/3BhQlYC/q0hifVkxZVVfZGKCJkMjHjGcYf0FFhFVHNfhjciyugln40 +rBOl0IWveZxf9gc0dk9uucqYHYI2CzvtTlU7n0wL3Ec37gF1R2FyJbOaVAZ10fGa +y4U6CBsZECkNiMJ+qPj1Pc7jPBwFrmYD2I0v1n7ArwLdHAJ2vtpwY0a8h1PcsLB9 +/WuJLiW4cppgm2nbqtJwP8HiZDkfUFKiBH6A06A6i8g5zYd8a83UpZRbxci8MwgU +cQG1IMJ/fTqZflI/oMRDUO9mfN9NiIFrjRSNM6exwxenjYp3LiCJN11P2hXfDJac +G9yHxkxs0MNOP4131u9QoH1vsH5JSPoy4xSSxTlCFK3DQOPwL49wLV6CFyuJ40bW +SnTJfivIqHIZcQ7WbAPLB7akWRILMbUP9tY6m+NdD+TMiqNO3I09hv/S/JAa5vzz +qDJbIRJ2Gk0MgZ6OFnibSrhyHREe85aflgni22lOWVqZr2kJ4zcLoUh/fd1JnpL9 +XKFQ4yGmamHsB+65y1V+VE40U+XCMW/Hul/hskaeWAiPG60AWeQmlVMhBEANupQI +XsFzHhchSvG+KiO6ZCIMOSSyvu3g5qYu5nvHjNrrQb/rieDgwiewcnfFABWrMeWi +sizlxgqf8L4X8WBgDJsestZxJ/mJSKIvrXEEN05q+/7OYAXdN5Z6AnKxFxDpDUe9 +6jDIYBDS2JXm9XEvaS93/JCZaJeAjJuMJUJ4gNChyiA0/9TqRQwAkJ29d88msTaE +gftSl6EOGXi4wTF7+Lx9cOj+fLW0DgUW5C8C24S8nLScdeBAPzC1lfORdcXyUWhM +yLUZUehXUzDMlYLm5RMPcWCzbq9LVDgY4bANAQ0+OW3FJ7xrUh4Y/GoRnTW8NVtB +DtFTS9T7r3b+Et3Xzuqc30LokY0peDw7gFOTYX+eXYAM375VQFBC+MCxtIL/ytrH +iTsZiBHpqGkoZEnrAoHeKT8YcAbfd2/hhnkLTvoK7WhLX+MPg1anwxPLS02KEEzA +TXQP1pUqoEcjeSHxEkoz7h5garGUqcr01yTdSkddf+JrttWDbCZhMbCQjcLgD5TF +PiW532mjtGZ7okmqMEJg7Ous74ABuBJOu6DBEiaPJQdd7hMle4Dkx1a9M1NQNvpU +HbpHtC7jeqgQ7XZR21geFbNSpIVbQn+3Ac6hnA0t2yOLo58zJDbBJ2cgxyrkxCy0 +Z2ajFBT5Mv6NpvQMlkRqAtw2rx0W9nOFL3VNPH08MwJh6iOciXQxf4QqajBcOR3R +X6NXcB05h9k6CjtC62IE3QiUY4EpFafAD2UnH4+Qty+ND+jgpCW25KHSH9p4/nje +NKnrdCMP7Bps1p32xoO4cn3tIhQri0eulSTGnmjhgxr1iDR0Uo/6qQfeqxiFwdYs +b3ZLuSA+e3LX/7lA2yu5XH0wh9Bda5w6Uarqn6Od9xV7OVBjKoYRLSJdy6K+hJFH +DQiTf27AwymER5s+P7jOF9Sih4dZpP04paizbPeXdfr/D1amGLPGXX966pQKlJSQ +xoFphCGy415FwizhutNY7c6ydN74nbeSGIWBx8j1CH5Ka6O68alvSVU5C1PyGn/X +MyfaooNJBe9Fqkkgq65nigdYy6dZxvVV3y2wMiFox8TfjuTdwa3ct+QsOWUW7WYd +bbzujbBseRRwhcwb7FJqDFUFxrN2lSS+lUxt593FrDppYkNW1QpNXWWNBYvAauDr +8ww1Eb0KDuiByFBCisBae411dBZ7AWdV3KogNOlsk6X+UrvR9nsG61fPDrOJrZvk +8ERnAN3pLrWBzxuL7ZsLPf9VjKS6H03G38L1dhcFqcNCYBYnX0MT3owMBXt3cDEN +gwJKNcluGcbt1Avmq0qqIj0PnF9QTGDdjhWHDFNYPagiJdbuLmzz+lfR+fv4v4eQ +gPB9uRkdDPUUZ6Tj/PtqB5K+hUtNGpuNV7GCVgbvrXGNE5nRXmmKrPJa5k1X4EcU +cfBpUbGsHYyRNQKFtISa9S7bdDLlqBNLDloNJaa3OWlwil918j/8/t5eYg5XV0oB +7CnSTiF8WoxNzKyAPtzxHMDwzev2VV3Z4875+hXBVCPDYYPzSbQJ2cjceIcpvlHk +5tiRNm/idW8sns8myhb+Ov+p5zrprgZxfFpsnjFLNAM/ZcHvaG4OckayD7GTnLDV +ci0KLoit6OWEe5vXoYvLlShdKhLlXAlza6lwi3XjV8UuFFNfdETqfvM1L9CJG3XC +CtaRMraQ92JB1SOfdVwa3+dbPxs9h7LDhDvHZd4Ngal+/bP2seZYw5//gJaUfrId +iXr2yB2uXRteFv7hn7meexaHPMC3VVb+kMx7igFuQQ2pOeEhpqFPUhqJtFhPlZf/ +Q+kKCRcRlxm86FH09DNUtfNIjSjERlznOMGpmnjJ8PF0W7evF7frT0+ZArnsZSjP +LeQqgHYYBOK/xWCwYaDoebpzPw+fs3aglJ1g/arfAW+dbZOX5jXnzKhrU56+6EPB +kLlJwXssUjvKT3bDmb5iVFMLYdA6A3nbGN04usX5Pp4Ak5GDq5RjwCouycClxy// +bvZvheK8u4fREErrxMV8UO+TFHyM6FJS0vzk96F9OSiAFYF/R4HO6+ZPl0+flu0C +XsKV1OuTxlgy1bkehtWi3bn7tDJllgaI3GJvqmesYXcqD0sESmKTZ33n/i+sbGVA +0QcI5rdKPSvFoln81x6mCdGDscel5G6ajuef/wD5FvzZ2VbP+5Iwn4BR/71nz11R +E0JGDBpJxUrDwyOnoH2BBy8TYJsIeVt/OCdfV3poM686gu5K0V5FX7hKVaXGJQgJ +Lqh7o5GXaj5oxze1Odl3Qoltl6X1umhU9lKGw+l/4pYzu3QtIxQ24QfFPuq2Evnn +1/IhnLviAfZ0QMqcAeVhoqwJ47S6sh2q00MYlt1lJHouUZTeuUOv/csXHA6Tfzeg +vAw6WSqUVWZifWkPqGUQM7vrcVNHDvZ+9o3OZZMLVFvKtLUvYjXrSu19ovijQmlv +3jh0PJ9qfkIDXfyrcAX5MT0RSbGTb9/SNXDYu5eOeilO3E5N0hufBM/LLT6J6BY3 +o66HoT8tZoz1I2HhYbMKdMHn7zJR4AgFAmhSIb1TPZk0vOUWIbMIA/V3in7Zrz0s +ZMb6z78GAp15EhH6ekTpR+WF3hJb7c/AcXfcWQpi9RjZZINEinmBy9ibFXk08tze +h6J3mXraIm0b/l/z4yiPPbsYWpPMe4l2dlLUzKdW3Q8zWOdVybdowUV1qk+km9rq ++M5w5MgD2oU0z44YVQgR4r9wzzgKolWWVZoS2o83N08uufOn0IylEQ6BJl4FlRiC +eT2FtGxA/K9Qkxqp0dCg+6E1yc49VPdf/BHt2zio7LYIdVfpINVsC7bsPXPp3hjE +aJeYtPo64tIKvtQHkx4SpxHCb6S/x/H+Y4jkStuE8CgTn0+8+/uJlQj0v1ZMKr6D +gev0XgC4OzXUYv3ySEiwnSKyE6cdKiOWbjmB5A07WTF5P/qfdX/42p3QvnYGKxCU +sjorhwpt1V+3GxaipjeoyYAFYNPXIY8Ot7f4ZjSQQaTkywmj5wOEvm1JaZ6KUIUs +5HkGZWTffbRqGnLtZymEU7zrg8HaSAjAHk2gdFYvXlyCZAD1mCtW/Wvdq+KIfREf +ejl8t/5fFkl+fXuI8B8KCMJQSqsogPQ0IrH6IFBmuIBj72XZGIOCiJ5RQykrhsCH +gEpM7sxkmJBx+GA5N5nPpRCIjG8useXmQmwojLwV/xdHK1ETC3kGU15Ib3e4bRio +wk9pDrdhLjQiqa0p3qBojK/ebbHnaZW1DR5OusjRiJQ7U/F7wCew0Bubeetsy/9p +r1Uz7Zmg3osMozGIBF4+q0cFxHgVC55kyYgzSOXtVq03EkJVuL0NnJtpqEWJOfB/ +eUO4ff8uamuG0EwBPw2+NftoKOCS3noybuPJVwBQ1jq4d6Hp96KaH29spS2142Vp +yQbXwJzk18sp/aOulvWEfk3hukG2tCPH3MxlSUC0uIgQ1Kc34pdeLa3uMkVb348Q +SNYYkW1K/l4nmNu2Yr7T/d2X31r7lTfAC/ZVmrkNbh3pJXhxpSO5vcrosmD688iE +2/IkLxuKyMEd6sdVWJhtA4bnYeHQNFz+G1mnN23Vt+DERZ6K72qt5HUiLHVjeNt6 +0yHoekSOMMS5LAHthiH6ugm1NwOrI8zLs6R2dfulPD4YjA7MD0ga4elOfmvF/N8u +2xIBD+Wbm3RB/IQ1IBHmqgLHNfQ9jTfiMnVtVpubO7yP1CX2Wh44KEUHYbk6u7wr +hsErncMr+9NGdnRdSiODSIlusKPk/rb3pthn1rdDFEvB1YGUrEPzcUIp8uPV8C/G +BnOGD9RnJnpZjBADtKkzj24OkwrGrDZhjVzHcjNNcQAbpYSdpCTrbd2SlL21vac4 +pGf14JMGx+KGJgfby90b2HcVoPUp+1R245vAu/f1FTgnyUKEKOdhJtnl9SEWwhE4 +db6ox2ZC51QP4rL4i7uKoDTeL4XRYfY/nc3FDywgu7mmpRtY/0jXeILUASLLTpfS +E7RmG1/24P1cWmFBJzH63Cgjlg7DBuq0Ufu9uHpvVGIpCR9FZBDzhA0hBRSVaLjJ +GyyQmJ0R7+EQ+UU5RZ9xY06OUe9e0o0AnzBX2dKgHSaexqtXS4PCUK9DhAfyzflI +dglJ2x1ecZ+JISA4zWMAfu5PLNS5NFgYF/kOBZLBM/c60u7xGWsy0tzBpGmqDEwV +wZkNzh3UlE6X8Nk3s1v+Prrd9crKV3UHIB2AH7BuaAcOPGgmlqHbQ6qxOg58XPw6 +cRWljv3Scboy0betp2+GHfmrjMcSA9NFei3JBVLLeweCZX33wxy6CjQ+1ZIv3ai+ +sE6Sg3pH9UdobHyYUpXMII8bex8+5c/bbeDYobtE3ZR6f56GWpHkEDbi7lOYENB2 +JcLcTZsnElUH7Iv1dHhTXMirqyn5ly5hyxA2sMX1e0WQ6fNItiU1//ONX9B4EbuF +rcti4zs0Ubk9U5AQUU5wQq/ml9piJrcAK/1kBGKov78tESApwXIFGk0ZQwZLbD8m +b8Eps/3vDp1BNcM0vEVe4c3e1Qsi9v1E4rBlNnZrLrlsJPVdAxhVsQxDzr15RldI +NqgKSUPlUWwMjMSu3VgQITQMfFij90xRq13pKG9cQ1/DdgXAzj+aLFdm1v/mWq7/ +jjS93Yi+lRIYgf1sk+9athSMjOFPe1TpCcAk51jrU7yQgVIsRtPEPx0bmew3xUOS +y9b4endclGYqHlsR5jNvBrRbwVXxPCjhcsrDPUKhE97vUUf17kZnjbDi4GRzLjoJ +YOaCTIan9ktRunTzcIRw3vxdMGrCZfyByN5NPEmYne80O0QAF23EtlR6gv++sbHl +X3F6FMXo86fQzgjkftUTaYapCKnPOBfIPnL92UCTUx9x7TSSzofoY0Hv9jmNpkhY +c/WWaO2uxjslVjE8Lld9Y/94+lk4ItFDa9C9twOC4ikPBj4GB/ShXlQ2aUAj5ApC +cSL8lfmOXg9mrEt0JJQGLmb4uztuVmCkuH8QdNPo6soEm2r4YcGR/W7Oe5DDYjTs +YSw0uFQ2TrL+wJnZgiAKwqxu8yiZoDGpv/HAtaNrK0n2pVqICIEokrZA4pwZ/YlG +vwaNKqLJ69X0dHYwbYOkBZcmD0+fKXTu+fmtVtzo8gbT1GU6jdka3JxvbH16uxAD +aIVvfvRYCRuon2Do+vK9UeNk6CCevOQsrzgijnJt7KZcOuDFEwOkl0HCUxsWqIyZ +ShyiGR13zk7NE1zTEVQTDOJndCAXl/SlPjryiUt+cSFtrG108XB8J0K+shdrEmJp +xt0v9aic4bRSjz9Y/HZkQDhgMfcLlgXIqbOHlBFptittRRYNzG8vJ8B2d1wJm8Ow +emePXQowvprWqzCxttgpa2X/Hl+D4jcoFsEX1scrX7vxbPY0gzTgjTTFDwXG7UQ7 +26Zbz+9IqZmvuRVQuI1Y8C8XkpbaZQP7pqbZUINfVFtQ++RD+gqWPpXa7dgYK8Vq +Gi4FbJoufGAJUpBsFUbRajzMFTJAd/HgBWO7MKlcDLfa8yi74QhZA/88oQherccT +Omm1+0LZhfG0dv8nHa8rGoxrY7Fq+JjV8gEJj/IOSOimgEVxskRfTwRvWHwYTOUc +NvdRaPxLWUp6xTded5Vp95b1vaX0Ogb60Qz8tVz9LEzXARHF9sKNo5ZBwoo7T0Th +irT6pLLccDiBf4aFpmS4oQVeJYNnYxhPxLLF2eqlvHHPccCvvCegiOKAevwr2wDG +bWIZYn3wYbmNuGbi/Qt6PL5wrVZwFsVsp/ehhhTlths51NzyfS5MghnmneTat0Hy +IY2rExt5Ekg206IrwCno8pTuI79IEPk4PK/g4uavv4Oj2xxqXR92c746PAoCT4T4 +x3pe7sNB+hSlFXhTNdt8iaQjmex/T4y/KoQrKYg1FtiPQfxDHQVfaYclS20dLSkn +9d6T1YcG83bumpiTpmBB9ack0qkujrRjA/gttdNPh+qvOX6F8MbgW80gZVSQaQlv +gcNWkE2J0CD7kgegnk63ZK/mOzVxFB5CtLvuivgz3LKJITV50lZbKjLT//1kFlqI +BTbp6/CLlTVLBOyeNjrxyQDrGTU06dLhBKu+6Bpp7DFmDo9FEx0H+ndoBkoqWakx +r4l83+5wz2Gi3I141ISYzFxJ/QtN1SHxg9sCmddrQauT8IjIbbdBSG4/P/thsBK6 +VkrypezHofVdhZnnsxBWtqdO+EWekPM10R8yZKCj4rPhhRNkvwxDA3Qak+jDpHOe +kQmEt1bdTyoHOXgOiN4tQoLYvOPJLbh0S/KGwLsQyY0mKH3nCquLc8DvWCNPsSHs +Oo0d9mqHY6n1BmHZRpzAp25/9npUkvCHqHP6NcS5uVK8pF9A+q7+6eI+XkU3KSXZ +3MuSxwMcmTnKy9jolurat8ilIUrTNN9m5jmb1c/rmcrprRa/I8k5SVtvf7COwbRH +55rOHfS7+E2SmiJbru4VYvJs22VTxFVO9MkdMTWJvD7f8olCFb7OXXhzki0C6I0z +O7AFaZHOiHwPVjoLy1WCMGYO3vamR+i9dnt0wXAmifRSILBPXTKgRUT/U2OFNwVO +CnOsgTCR4r8YoRANC4bzPYJ9EVhB4eD+spOUyRmcR6QXMU2h+HyT9Id4OWamp2J4 +xvq9Gv+uw4A2+v/waXwiUQuqya23GUn/pQBkOy45AAsWkzNtajHSa+qslbc1AW7v ++SykQ0C1DY0jCQjyb120R7AawlbGPKYg9rqiC/QCN5Sb7E4IddAbXzRUsIyx5ATA +iGbz/eM5gV9oY7XFXaPiZqog9Sc2hM5Uq5Au+y+mVERiMBiDeg1FJ+xcUcLs7jKD +O4EVV6ApiBt/WzUEeMx8CJTQThja7fL0XqYyoZCE4SgXa3vMcQabnuhU8GcZJOnM +PkF+P7AOEe7WrTwYUxYI370dM6nJmv3FHovO0+DW2oqqmoD16n4FiX6JlU4lYGnV +i4uMzdOdSkH8oL1qvOaHgQllSjev3VH47teXglAp2MnMy2WaLGZjsTcqBXJ2FiLT +AB6+4bDd8NoUh8857MHAsVhPxN2fiyjPubpBCw7lNaScLPOK4clgEkYcym8iv+Qf +bBIANXaoW7Fhl5Vlt+mZV93+N76BD6hbZ0Jf9gFby0nhBz2JytQmqjpxJyAhbfxo +RvnJVzoyHMEfH+ttKblNRNGoL8XBYZW5437xJJhH4ospVzfr0rjhE3sl04A4Q6eR +3OOLsJ9XFUbavPq0vmB/pSAoAgGaoW1jwxFamqiOZN9XT4eLNbZZPtGstjUvjdV9 +e43qwY2Yz+vb1yQElleJPdcnxml5OF1VK5bFmMHRviDvltskEOoehP7yCQxSk2+m +pDBwUEeTF+MAOxp2Hw2Oyil/lTVb6g+ExrzNgdsdFe8619vK199hCzQ++0lf7E/n +YrUXLVwXBzQs8bAON6Tk3aHr2ZCI7hj31i/a/8KQqkCpjZE1z8zoPwQcejwzfxDs +uFuNfxkOWm1TX8bI1zKsvlmd+M0bDJIQMnO0sIeEZ9RgvzAnOWdo/2mpD4eHi2Ix +qTZm2FQ3tUID4D9hVnhpY9IJvWrY1wzn5vGfUzzJTxhZ2O6uMUiLJgDeMNorsat3 +BqavLmfz5FI8qVHcAyTBGRCfWfJ4FHIwU6pORy8nUV5xLvCCDi9u8U6WfMiruC7q +Q1w2Cw0VT91dZ+/DMhLctP91LJ12tQsdTCprxVHzEy1IHRerqtV5rrX+k3GTFUqf +bkJ7K7BEj7JEkRpG2qbhiahavj6OFghuWJEVJXV7Mzy0mBYPv93iaKE2BcQeTXEE +Ytk+Z9ssTVd6vNIHntqGlzb9k3Pdj559TJpibViy0wRIiDqtfKyIwl/WHF0wvURx +UjwzOy6bEamuR4A1EcGjnZPsqNqMqPSijpOZvhiB6O90+T1W41R+6Zddag9b31Jk +Vjv61w6mcrQXb/0bBpMeHISZOTRKIS7Cn9TRKSWeX6iX4aJtS9MnYX1ux4/aF/bR +kDd862OlIff6xdzL2yH5O0ncGHRAFWfgdWeNfBQvkEs+T3rBGp8Bt7MspHkaUPiA +sou/GhLATGLQgvlGKovVicKiDueBT3uv3DTnuKIX2HOUD0SAXnp7BhWypjWUxhpL +RxrOsxFgpaVJTeMxv1CFxmOD0UFJNmusMxpDKv2fsHwGm8R0faWD94ppfMqKliGg +N0nAzaqGW0g5p5/q0jdxPxp4kBItAbUqxJfPCrYcNFFpGeiiI80Pjyj4IIRIA6Wq +YUmg8vwdtUFuIXds0mcJ54rStR/dqfukmqQgMITJ5lifqfU/SkHQSgiLmEek+v42 +uIXo3A9tVlMBeGWUsyGY93NpXmgkSLEXsJE9ua1Hd8RKlAssekLtuGZdrCa5UI4H +BXPEi4w3aW7ZHNtO5JfIN9Kvr4enng04xaixkWCT5HLZNDagasjGCJ7SUTmofXFE +0vX0Uzukxo47Md52bLr05uyoWfZ6+GyDi7cxV/t5w02IcbUPnGf8yASRwxbQDnhi +iNayYaSwIxYFLy2AmH9TECy1ulEQLMIx5otn12Iiz6AMEpunL4cdcvEaIn/XAhpm +V6T36xoGJSxdf+ZhlKzYNX6tczXXuFpHpLB3eCS7pJTeghfGsbnWUvqyWyuV6JDK +rttSBQOP+wLv0KzR0uxnDtoGzk+kDR4EWDKuTseO8QmuGUN7K4SAcaTjC3v/7h+h +tsltDomhd/Ce/uxXtUyRL2Dn+NtMkrA4gdDrJIvxBqU2GUC2LNiuGaxjrzqbnYx2 +hbYIZSZA43Z/i6u/tzbBo8v1AyZM3FKOytqbNaqbWfpskXDwtTQEt7n/9lSLPFBI +KF+lfpRwirgWx9WWhspkNy3++c6+iCp/dyqk+pyirp6MIgvC4Y0IoDyts+yPoSYr +XuY5PAXmCv0IrOzX7unx8G/tg9qaMv20KteRc+iSFRHBrt1PduSQ6j1AqwYOuMik +GCCCXTq6SKFLUuI5WK91SAM6sEVOvz4MHBWIiaIgSzzTFtVNFi/P3zZ0jPPm05xH +oVsSOOADrjWataxjsGQF+8xJFrfU6/Ly9tioEp8azSZeU6X/bF6ASSnMhfRheQCG +2NBlZJBvdGfUD93bQGig1HMyqSIOCj/2+hcye++CqdoZ6mAAH/+KVwV8HrPWuC09 +BZ/SObbCzkGifSxahgw3U8WIzONEcODTw+lBPX4QQ0N57wJlPSjyg/PfBFwzf7fQ +UsgpWV/PefApv6gP6NhEFWLivWjFxoo/pXKyzRGD543byC/SMd0e4+uSZkqwo3aG +3awy1td6pQAbzx46G/YuvqrJhdHT/CqgQ59uCdPDtn/eY2YmKulUvfHYU8WY6zco +Q/ePVo1XtBN8EaK+MMtAknU/hKXfZzOhy2foXxjXREk+OsiDl60XJXtGDynjKbUy +na4bRKZEPo7AdRgMKSUVL1Bl4Yv1ZZ4nYdR5aZXrkHp1eJIuZ9lpQvMFR/y+7CK9 +ZnXsNt+FqP5Ig6LqRtHtXtu26yZNQxyOOd8H3Fqhuqzqg5yONN0bidtX5wld3A4T +2U1No5OMF+kcjl3i5Zv9nM4/IzYfAblA0aAB1nQXIdENIKVOB9YjEIm1XrJ4Um3J +9u4mJ9gwaGXPZ2yynI+6UcbJlC8wlG5NC405nfRtdnQo+zHGO+GrsT3nVvuRs199 +pJGUr01nY4kfypxboRJotvei4T7nfTJ6V8S5m7j8NWRyvSIt1eb6fY3TN7rEfugV +PEUH9gWlhwVuRtZqhX+SzMk4hqxi9WDhoX5qjVy4ao+K+2f1Xrsy+xdHVU8sW/hB +bVsGjJVeLAPUqSSQHT8gXdBqNFGDo96KnhwlpGrxi3QHKFzKVoGd9TzoUo8qdrC2 +/5T6JYSzO59Ry6Rlj10hTLGnUzevXeBgu0RGCANTqcqczJ2zRW87mdzT868Y6X9b +uBToe4W0gCqcxnuAgKMEcCWH0Jnf+cJ4zgW+6J9zF7uFKaDi50ZdGlhI0UNbmpae +2N6O+GUonQELZ/Dud+bwFf6Tdic/FMc5dEKCme+FvcH8+ut/a2z8b30vXpQ3Le8B +vTo5vvOYQWUfLm3XzOJLqFGmpjV1FBkQ4NA7cE+Gtu8bftPOEMT6bjQ0Cr8Yq3lO +21KGoIQv1hjRzt8fzq3XyPwD6JIIWv3iYQKTd1y821ParuG+qwfhjPiRgwfEMShP +aSKAdCeThhp2JZUTb3S/HFuhbQAg+prAY/GxXcjXHtxximu1OGcumhWRB9YikDmG +U+PPx+URw4wxEQaAOO/6IgnvqtRsazglB7iq5s9Veaj6dETk0386rzcnsX1UqARi +7bziMNQ9iAf4jZasSST/gqcY2BwbnqTAVEZo/AeZCVNiw3MJcVKLPwUHBkgHga97 +/oPi/ZM6NliN6KMWsh34pAOFx3yaRryomI/kobDLl4s4wOHgqq7hXKpkzkBxLWZp +lAUiTHrMZKWmuHT26OCBfSUTKn89JzdT494KBLs9JsHfR+V3qRO2uZLsTEyoXtDq +dRivdl+FiZ9VSph13pigaZigd+v5XBR5VszfxSvtT3gJMU2UawEwCVWP4/ZV7yX5 +eTQaYgxK3Jf9ysHnYTXUEzANIKQ6PFk2zRsLOOplwPzaS5XLIkClfbGNWHv/YvnG +uS/fRXjXrlGoa5Xj493tQy2z3BTHI9Dn4gRcbJDMbIRJ2ljIdsXljP9NpWJF5vtT +B7MTEFAGPWpQW2OGLX5MB+hnpy9J3WGlA9/j/WVQJoG9PHKcdWSA6Dvn8pk9kyFC +Zi2x1E33c6jyXNaHhPDSCtJm11WFTkbDKgZO+v6Qcj4BGJC9y6XSwchrvlPY4yf6 +6T08meufckOrWgS7fJrbMYXq+c7Vxqrg6fTf70voadROvTm8EKYYnN1rR73Yq2Tn +gZLQufMBWYeEkGcqarJZsY2Nz8NdpxA8uag4hYG6K+NceDqWtET+ETymLkIEx+IS +hY9kONdrg83adsEsf0zvozZf8ri0YSEByLF0CYEDJDaR52U9dKCyUSv9FgT6/SJr +sjfMXiKdQfMMwzXYJK++aaaLuUqtaObpky7uTQ0oE+QMtw0WAm87SoLWmJu5QOMc +ISmlEjUcKGEkhJXC4/k58HAX9Asnhm9g+w79cN5Q+c7engwMdBMWlOQMi+eTOfTS +cuPonZFDvR9f3mFGb3R3BDWDT1zAMxJFGMx9YdJgcw8G885ThAmnMbi68v6PNgXe +UzDyBp2R+tmduy0qwlsfG3rXkJRXDOjKb+q+eFpM4P1bsqL2M5IUWlHx4jNGPmF3 +2JbLa41CESWjyx1DSawcbhGtLq/+AaG8UvQi/5YYi5RoqOhAYF4+LhTGVXyWJG5/ +j/e08gVH/XReaXkszNtPlgddHh5yS/8F4TAP4Hoi5R7UJPWZ/8ZoLYt13jKG8L6O +h4s60T3G4fkMRdPz5nTYQ+shWrHUfLJMtAQ07PY15UWg+8Qr1KHgfuwWqSoOBQQn +ALctRV8bmHXuaZkYtDyIEMjBRY1z++NuXT1AOStbpsaES65cUTKJJKNDkXsMXwA9 +YIRqXhuOepRGyh4QCg9WCVF+frCVF77zs8P6b2jDPOWnjp0U4ZY8I0xEB6f+3UUh +f4jPk8NRq535q6E/GOv0dPzQMrTVxvaVwPLNRLzmsgPd99OUmdM/NMKq6VkTxe3b +vcvcb4GKoLKVQ/Z48owSs8c1WEih8k4rWo9rh2uHWa/223KSRs16qA71QECD8LWQ +qTLW5wpDTzHlrbEWneWrJ1CXcbIegEu6hgxwspJW7lTbLIitvyP7GSbeBdEdpDwF +5BiV/dC+zJ9FzYpCzthVMfNl2oAGF1fXvOES4vgjaf/PqkOINjBbDhX+xZXEkt2b +XIvy+IUHRk2JqosKGo939v+nmbZWTE8Ipe57aBCjoQ92hq7cMNu7OnPpWrcwEcc2 +FfS/MsMhsljVLisgzs909DEtt2HCeeM7Do8Cl/JxwguEI2PcY1zR9OUJ4Vv8F87e +iJFfuDbQL1As5z5kWmAnQDgDffjms/Y9g8I4qQSPLxzap2sXZS0fGwjsymp5/enf +d4YExpH1inEN3lX2t8x1XRRljOG6yNr3ybACuFVKIFbtgNAjeLDCJPSO/p7pnURz +wztTgWQLXmYfhi1UW5V0L0CwG/9Tf/W2RRZOOqD3J3MYwXNgBCK9R+dMOuYuHAj6 +7LjQL4HZalxbHUp5QkNK56HxDMOStVTDz8R0+tCHtKElrhNXwZ2wiXMtPHmOqz9c +Wp+zNuIzqBYKxNwGQnpPQJ+xR6u30D2hSv7u8fMIz4lhTY4p2OiZ4u1IH+u4Sx/s +GdZBnPQBxLv3GQc8d+6hpwV9OwcFaIOWnz6RKT0+dUlCRO+g/YZqtAZ1d0NprWEO +DKE70DH3KRRKvW91e4Z6SE/pBTMjJvBdIBkiVQrXqfhcQftfHeJSTS7Xl/WFcrbJ +/z2dqhSys/4ZQ9USyK06O9pQMHR05RuMbYkC+AZwUy1xc81cqVV7M/ORoaBF+bCn +FbNFp55TNoDrLtuQIfZqFzcnJcJ7fzoo4jYA6i9PPULC2wUtkAt6wS3iVpYvDxn0 +SiZSbC9iAPsj2y2fDpycTWM1DJ8TxYk51rTZ5UUcu8HpLpgzAo6wuYL3ATacLU12 +82exUDJVJEI0NNcHhZPJM/9151RWrbZdJeGJGrYv+0J5awliPjrN4S9RIPPT37A9 +Zoodf6yB64chTe0X/e2Z3BA257/xCwUUYpEXInrRC1744CSgQJ9+p0NvYycqgoEQ +boVtYEFrUzIWhW0kX5uN65qtxj+Mj2px8s0TZpMj6n5lZVi7m7IKLQwbGe4efTD2 +tPSMVfdw31DEcL9imNpBN52Qj7N+t8aMR2cJR1tmtI3I8FSj0j8PZgZvNY7lU21p +nqCcMVO/JFhfAm1eyeWMvXhd+1D/c4iCGjClBfJUANnO00C8kiRPO5OjJGisRAjG +uEUoZrjaI/AenbG8RLOhtCa3CKmJYFF8aYLy+hg9wLFsF2EPM6jFk81NzZhMEnOt +pKpkoJ5ahOqNArNhA2nXcveTGqY6tZjHTvL1gczYXaeA991AcwqJDzf6jnK2c/9J +eS7HSQthAvo+FFXVp5oItNt13uiolD9zRQCTw6FGC73pUTWGauGE9Wrc7NqI503S +T3iqRxG1PnwwLAiullFDAoiWFNEax88QawlBHDDwgICS4G/WsNXtS9ia4DuIITt6 +ZJhtLb129EcvsFYrpwpWplQIDXBUVvWQeW+KFONtiLUoo0nt1EqqK6F3+oPUR4Oe +tOG8SAw3UuLkMWfSzI0ONMf4tAhdLjYbOxMZWkdY9rdbBx3i/iAhwyknHNW798nS +OhwP7fs2rpbOVjo5eHSvgN8YgEAhnQawxs5Ub0H9RDvMyE/+AsOO63W/TMrsVyri +om9Yff2+BxsDCZ4ZFuH+YTaPst0g9NpN3hIRkLObKn+ZFoRCi7iX6r0giuyPWNbi +wunaZeckX0u4ACtqLu8PDCJHW+EVTawLIfjiIOQfLAlSQZQN8VHECw9Kn2w2lKRF +WdMM476smdwwHO269rGtkfwYF7CnM9s2wiVAe++xAxofhaTf3Qb0xbkNGTrCHxyh +rX1YjD3L7C3dBvz7VNPSTXODiffC8MAswdWIthIousV5P7VUTqZ3UVY4gNOCtHuQ +FqbaTkBva928BbPqg5lwOPCg5yoIV5EMzTQEZC91IlnjH0HmQhJQfpxHK6GaKcDa +PoyCaeIih0siJDPrVM/lG/gS3IvrIswP2H5f7WswfANRdxnSeBqgGKPoAgUGv7aS +T6SAo9wQCns+CwiuEPrzdHOBSfaZYR5D2Da/H5Ix9ppobdV8y+R9ilPcYZKDxIfu +FI75X25EgcMhjzPRt+/E2Dx/+ycdfvTbKTDY5wBBRUoa5ASYjiOLgARx0sJJJSUr +SmB1p4J2yvrc0bJYgGTCF/G2v9KZu9fuJYO3r1XdqAguRB3vmSpMYlFyQ0OKTZAk +rwvd2v/7nu7yX8njV5RTwHU584l5WJ91HiTNJIY2FoSt54AlFXYm91nJCJG1FkWc +DkFzt/pLl866dEcHekQ2RjilOUtNuYblni8tUtSCwqpkJEOIsK4SE/LW/WACnNNT +b1M4N1ETdZZTaciv8Zq9pYxmMAaHwUFzE6SGJzz1t1JezoD1pAZtYdDBz3vc1U0D +dCXu0nIr41Nm3RtW3Xp0zg1EGQFltUlgstLl6dTl2psnzza8lL2RIhlm47yezMBw +29gXfttc6FI7Q7bzE6n/BrfpQZV9L2NO4VViiqG6H7t1+St8KPpWVAd/5A613gge +qulVVP284Iuk67NJvREd6LABe/etsb4RjCly4qHH26DVwU8ysQgmisPms95rt9CT +y9AFIkReAUqIERGbwt2W6vMHtDx4EqxzWSef7FzQsBsZwGtN2nZbozJO4xfoWHDS +jll+IaV5uigBlKYTQPusCOkE4mn2+H8amq92jahbzm05VOd7duXOXUyplKlnE+ub +qGBhJ6Kr82UEXd7DT99zpyJ+pUh2anY+wtDu7sj0cWTaFal/aj3BznvbkGIMnxit +DbJv3JBYH+TzSz4PLDF6LCePT4Kp4L18siRQJuiqHHyTQCBA3sDci7Va1VeJYctO +cDCG00wWr0sKB1o7QpN8cZ/AuueuXgdBJ0DHWIBMtuRgoT3i5APzItvZRkMUDdY0 +A5VG1F9+2vebQ7m5tAj6PjwF80QKNgkM+BUeuygVWgwOoH7mjkyazUY4vFypo/sC +QH5Xi34wT6KJWEbaulU7GXRAgDJq2mRw2GZQZMjmPyMz4AzVOkGqOGzXLJi5GIGo +pspzv4/ZDeNs7I5EYQLBbC5itqGMdovkCUAmdeG3K+Y774M2Gwi3sV3w/2ewhFnG +GW9vDNgKtkU38lUtk7FiEiv8Pi8u55hOo66mDW/fnh0sbBg2R9Fiyu7krWlryhNn +1G8u22wys5VmOZC5EGlr7Lctt51zj/s1/KncrKOZ3+wns80AJxl+EvNBJlowy3Lh +0uT0bl2x6+jAY/l7UQ+X4kG+N08ZFq+a7JCTzWRtqgVN1i4NEIJKbF55eENYsQGQ +n8JsMDVT8f44WD8fNz+asjwRR0z8VzJf+nJLi0rG5KiOeCQRASMFxOeJxwKjD1mg +6I0cg2mZFnwTUqy2lkhViWNsigazVclp6YLGR0HpCob9nYiBZ3yRUAasJXQRrBFU ++U0Nve1mPXcA3trb4x3YsZuGfl22VZLebmCpWU0MWxL9lp8iN1CV16XMogqdmGib +eF9RsTIFn6/O6WpDGlsCmUZqfm3vyIuQ6UTI8FICof7P5pJJkGwcga0tSM46hpnP +U6/5jAI31uTJclKyl53R8XI8XzmvEWmaYkFHgqGaFrQhZ0qvmLMw4GS/4mpRd+b/ +wo53unDg+gZ/RaOI2u2U+Ai8tu87E4rFf3F7PWZpVdakPQePFJaFqsqkQG2epDNy +cjXKbLOmB7+BApUk6UD9wsm9rhMrIdm4OVB1qmF0OXcZScvFG/bDjddhJ2BImY+6 +92RwRqBS4PYLuxwDz1b83nWkV3FgoM/m//tUBoktshVjUhylBOq1Pqt9Xo5Q+JnZ +UncAHc0rkK86YVt5HYdKrKOGsVz3Bok8/MuSiYMXR/IYmSF6AU+5MjMOoTIefhmP ++CFnOjnQ+To1LUSTneIlJbEw834sVLjotXAPNLCi51oAcN+2WrQo8M+C2qsp0o1z +bAlU+oPwLGyURAVMD3h+QuM5oDR8CPcYTJ5wXPathqFra/GcnATsOtwyNnG4j35g +jBi78K+LB1otmM/YwkKZCIC+qrTJ5UCGiElhSg97Q0c1Vd7naDGVIqiHH752hPtc +PMVWCrV92g54n3WpIdpqo3GHq3F/rbaWXwuhZM+O0M9uBbQCbsT4SUsaCYHpF4xm +E8Ma4Ta9msBvRJ4rY98P6NZtf8ZfcbwzdyGn8wzO71BscIIBib6gfMq69EGSx9hX +zjPntUqkgs4K1yVzXUdUzKtHlz58+pIQ45TKRt7pFP+yUxEFpoKQ2G8swdbXBq0X +vDaM0CGHXTOtXgfPFGXpXz3tk5AiD00b+duGGadG88qrFz/XA1IQkOW4Imkkajau +pPaD1wgyFJEuDpDsABfuG+11mvJ5SBk8pnlhtP03+KZn5Gn1g612i68qpVqm5bXV +EtsBamhA1GDCFSY2otDAb5FEWUTxkx259Vt4//UTx8ObGlBxYJu2ddh57NaNWfuT +PLIe9r1TBowP1rb4rZTwLQcJDL14gj5uyZ2VMivb2BsgxcB+39YWAWxK44esunBo +TY8jfznmyOcmg13rD94t7w1i2s99hwHUAlWxxjS2TDaDAYrZaY/FXBHQKaQKZZlW +j5Zet8neaUllr7P9SCD8U0lNdGzz7JclI6dlp70zB85DW6PN4SK9WlLayPJonvmw +b827IOMZt4kPhT5N1PiheDNPHp/TXAIUtHetmy5z4RshmETdvSanpWaBIGRzP+2J +ukm9pH6K4N0wjKyHpGwyJAqSm2uHFnpv7MYOevUIUmBUBu6gygwI0xpQxu0p3pgr +4mDu+Hc/iDcLkhnht65qDLs9FcfvqeULd7b+nNpXeBp/o+eUAhXHcD32vKQNKwOM +9yXCOs8CVJfvLR3BD5EO6tGLzdyypNzlFDlCU6rJ4FskO8sgs3A/MBNVu5N4OmNq +OLW0tryeMESABiqv5Sj1CjBIFjxxSNiICA3VkgYjow10r6sbbk+bR11Tjs99FC4l +W53NlIAC9KLnuly5xF6453HPftVQJCi6oC3L4QhY+sHpbdNLuoEexzXO8JQ3gqj7 +ZGvL1ZlsSdnLbyMn6cHeTmaJwIs6+TwlhphLxxMb8JB2QllH+6UtWF51EU230Ah5 +FHR53MPHSbxm1r9OyATNQtGSj1cGuZVe+njfzl6Jo53YAeJfJsou7hkxhwKKHY7w +ZQilw5+UcdUWbAeE5oHCZlOmaJWvvs9AytGnD5KCIADJ1o1TTn14I6JIe8wEVez5 +Yv5Y+vbB6X6ZfSfCs/N/cf6th9r95hdRP+o4eE5hU9kxsrZqHAnC9/OBBYQY/TzD +8mxpOD2DedaUwCVI5eKE4atkmc4A8zpbmWM25M6uZFcQxr059tG6zBlhH/AXjn7v ++teHjaJrdbbIt9Yflr74k+gId/wa6+HhD4dD/DNzH/t/s43BTXDG+0jKuQY0EHpr +vcv2qWMu/suOwQxDjo2PbVSf1u48mvA/sdLpEjilnMOFZyNld6fmZBEDF+F0uo8W +mhCP3xzY5ViEi8lNfzpbV0ZN+KSAYehipEOSkYyM9HMRn64ntVPxQam0gx+8YQES +ezwln+MgFBiL+nauWrXBovUus1Qt47hLXv3ivJ/+jpnBchiQZGKhyT9UkxDLYpAa +IrxaNmssqsEjaLQAzl9rH2hnandAMSd9a5EaSItYwZW+fwugpC9/NZhGCioLQivl +/6KALOZTQB33jDfRwK94om3hdxt3ozldnofB3Z3RzOYa7Xaz8xbVMvqnSIo5NU3g +5+1KiE34Lo3IXJ6hsGIpC41lA3Z10l96Cs7I+vfFjqfKFyJ92u3mm0+xKZ5OlPTQ +LnqlMtER82jiBlEtgcl/M6We3eD2p47bC6LELe74boUtM8Wn55rOVJLW2pVdeHz4 +gS3cTKkPBDLZ6kh9TPeBayRJWwVV9CZ7Mp6BAxDPdWq67BihCVWKp8YxwNxOVCow +YKNHMYyL+cOLPVA/JHJW9ImuU7o7dqk6TVRFuMRMxRe3/cq0Y885T7GqaIOnnqLe +Ja03gGMnGsCamsG9LLv+Zq5KDXxuQycmHWFIovDt9eLHoaY0Dd7cvBVdHatKXx1n +oeThvEXkdapEoIXK97+kC8I6IXkFQgWKNGzB37hRVAGXlzlnRp9keSps7ttPl9Xs +QrwUxHgo7E/QE8zG0GJRbUTCIZ5ULV5AYrrT4EXiknHo5KaS32hHheegw87B3v7/ +mBd/kAl39YZwcKHR9e3BZ/iamhXFJ68uzaz6S6gRvcFFRlb91Cq9NqY6Labt5A8j +YlLQCfdaKkXlN9XfpPNMJtpiVBr99EwYfnTN2pBLUcVXYN1r1UNFeRV4wKRcT6nh +YWjUd10fwlTgMly+RNafcC49kdiUndG7fqLUucnRpYSOr7R60h9oeq5GbIVvkbAL +Qa4hUZXeMxWTZ3bL098v3pfn+57tLc/bD3d/HzpS1c1FIYtFMQVhK2y3wyT/tNWr +WgkdFJd2J55QwR4du2jdLjKPaT4wSbImgTkuAv2OCIuV/Zo9sAy4hzvfOTWsLMh+ +IIbgKWIjF6MD+s22vKsJXoaGhyEu2UDU2RXcUJ9YOQvEG8zPL5NjriFqtQA2dL2r +fWXLRgOGC0uInG1QJN/sxIUCpe4kS+UUYIYTcG+QcFajf/M4bD4RU02X6MWJHMiH +t+zl13OqaeL6XNiTyg+zB+iGXU1skXYE+PWg2gLcFNNU8hpsjKgsum2cke4RlZni +WJbLfrCYwypQj54E7xTybyU7g64hQQkSS+IUxrowEwmf6nUkeW4SAzPyk2VHVDj5 +rrTe7pXQO24A9X732nYTRunDLh5oWtUXgQLN40ocYHvNeirGKxdnJVYzKNuYDvPa +C/s9JJHznubpOfFBOH3xXEHidyUKh5g7gr9fsokaY4X8dWsdfQ5mdjlVYyy1aluT +4c8Zna1g6pbDFSDUKsbYb9oz4hVNwGC/rIYRh2WMuNk6mxigXpq6Kc10pmMHToH7 +VIugzgS4NlcICbbVl2S6a35cqdyWdS28CXbDMj/+DtAD6svay9ELPOWyCoujhN9p +BHLkup71zfIQ26mv0CB5L/eqR1iXNMyZ6U4qjuPFvaIOFgB6BkfUvqqQsM4+YNxI +TuZ2E4LfbggJ4Te7qouArpvvkRBX7PsQB3TJL8bmoehh6riIrjyUETWpDIQsk9hE +z1JiKdM11iYEtHv0rLw3ga3W/rt56w/8VZCuc3kNcekwcdMU7u0kmW4OYAD35KE+ ++1/5TYUo8PRAuufLx5KwkJVIv0AwpyLsvsqGq3t/p36U4spSsLzXdXNRBk61jQKB +ufLZ6j8tjqXOZ0KgGkC7OEDiLCOzJb7IuteqoppLUZKaKaOk6K79h+CPc9aaVG1k +tZRoWFZS2ZszKD43o+KMRAUUlzYdsQGDlSWXKrFdro2RY7InH+/9SNtI+ea1wilv +nRDy6sHMzPh3TYdrUv/YJ7VsPgMIuiYrD0SqR0dQnJuinUQN+orohcP3nemevBpO +EfOgQDUdmiWm+XsYjPBm0THgD1DnxtL3cQzYqvblt89wahnf/qthrdCx3+VRX5G5 +p6eEBTPn2QA2w0Apbz7RrJmGt8omPNOoIaiUz8SrtI7I9mUooDLqaKIvo/fgBwFI +5KEdfPjtNaky6DvnM/H0OV/xK5Tljm/FdaN1Qe1qQ1dAKShMPIKWeIgXC5JmXAaK +R88Cwc3DNvoM55UVTROhZVZ3UTi7ywfM8XrZAX9LhXTrNAZS9LcwR/BU8C61Lckn +qRjd/6dmNnWsehjxYRPQ83oBJr+VAeNX1WxS1WwzNPgIhofBVcoaYei7EXWtLgmt +cHB4w4/2zcN06pJu0d1yPPGnnySIIdVJztr/hOc9XjGKKLbdLRlrXRQp0lmyW9Jx +YNyGm1K68iWsBHXMA8U1R1d0abzUNLj+JxodFXAapGcdQ1VCk1Zd6DH1/NgYClTr +cHMjDFVpbMuDX+ENWrWFbP3L2zMLMdN/PiaIJIy3a2QfjUmDFvPKFMDhz4Qy7Zvo +rFaUjxRaYq3cF3n1l2CA4F7frJ4JBeuQIIu+zgsPtyN2hNPgsHGDC8d4QgTtpyRi +3QFOjeHhdtgwTcdxSuJNbqglJbJVHej9sxbNYRAiZi8JApWXKzfHbUJ0A2mjFMqx +geCxNDFFFov7/qAHgtEyWlqF5qJTWYB1szfeJbUnCY+5ccmfdX10KaluPZFzOqY3 +/Xb8d2Zofixq/R/g4NY3YbLNguCwKABh+dw2ewtFUeQREub2H/xK1lQIEA7aaWdT +t6jpYk5jGotk3CUkwA/odiil5N++/6LwO01s6lDkpdeOvrAXNYS5wV4PEUhpOoW4 +koScEvbfQVGw5+ySIKLGGyuw3EprWRcyLjQpn4vjwEBYkNHxPtC9tSR+N7+FJVQL +de2UQnKJsqcDLIu9StW3LzKhEfIrhx6b11Fjt9ry2/9jUKrvhrMOFUgxAZgwDNH+ +MtDSO8y69Advco479mGdM9Hn1BmRLo6L6hVpy4k5xw14/F35R8I6QiIikr2yue2E +iKdDOyAlnEDkZNyiV0bkWyGPw67ZherFAYQ0CraE6W9kFAdN/dkVCPEmy3BHESw9 +tdOMs+WmYmIXrC+Y74uzyGdCldjzhj1UB/jyV4/s2BAmh2HFHeCe2osSncJUc/FK +BftTNG6bGH8RGdSGBhMBrD7dbpiQFh24qAWCuEF6fOg2GrTZlEwiETrmohxHBv0V +Vj5qWLr5lKfm4ipSvmOYLJlRZ2LyRpbHjt6T+sjWg2YB9Ji+lwriG1sczGaUGmEJ +DcsbETgfTA53y6oTC8KclcryJBNj252mkE4KrMnDw9RdnnwyDIOKhdyzxRGy2zYr +sLSQnRvH3bZu9Wl99uwRz2IorGtUuOJXyOu371q/qUNyusvwKG49FxnZstJuUHdi +MCdMwRyNAoLEuf+6AaOOOWMUk43+jZ4d79S1lWtpyrNPFOao8PjsY+byHfeNZxSK +7JnJVdLiv4vzA/tb4xJZPcfFguvE6ERXy5QjDrJN8676+FU8fNgy7oUjMqy6N6Ah +PhRamUHq46TwafUZPof6UttjXeAS6pqsP6rEF85mOXWoQRh8s5jv0ZMHjZ31wyvO +zbaYdMmM49faN4EJVKikzqJRiOT7/FIyeM6/VfroMRGFPtmnSa1oL+AyOjWrUXRh +xXT11Vp74CfiyNo5kFmmvkwXWuU3DA/qT8M88rINUk7byelmsWU74mgkZza6jd6P +WSot1dPSxZGlLJDSgkBAGjbQ6UF91GPJu3psk6hD/BSsHfctKkrGYFTioL7sm/rm +XNgmzwSgCBUrpFddu4SbZceOVNAMOPAlPXsTVieDG3Ny5aVfUkR4gsqXEYLYHc7g +rvZoJmLSGCBe3KZLOG0odHRCcHoLHASk0ZRgC9jOW9+G6XkfGevw3J2iuE3Z9VhX +7H32wwts2kORZ8pWG5DLDB9HApiKFOAtmjZi8kmXyAftvXcSawn8Rw5l/sSte/vP +/eIgRpiQ/Aw6GsBo5OJFim69QQkwjX5Zclw/JVWWIgY+Vk7HrLUUL45IXcwvyj0i +ef4DU6fd18oGBOy3AsgIk79sLnuUpqA7Ue6bhc/kg348R3CscCRGA0lnwpd4zESw +ZtFCOowajWmZ2foPU42wHM3in31R5TutefUs5puLggqkGW4ZRhb9QGdBQPQQmkqR +ivIWyLgdRaYYxA1K5T6dz1Qtwac4Gip6g8IdItUW/URJngsqlMZ0MQ/gXD5fk3Pl +KERL40kYFTl299q7/1NpLBPD0oXPkju8YVQVZ/3Nh9qIcAFErc2cgFXY4m4sC9m8 +Vh310EebC771mC1qSaVGLehdyLmrRVJndZrIP06xsFwQJ4wERLlxR/YsRGGrdr4G +mU+r1j4Sl8j5gq2ntEnAJ9PCP9yevZcV5BtarzWPLSEXlic/OwKYUxEm3xXZmkLP +ZUaqDInWEj0bK1db5/p2mFgYotBrj4FDvJwgbIzONjowKT1KGlD/vd9zUik1NetI +EXVkiR1HF5ko8qQKYvA4TW3ct9/O7CCnDGO7qvOgF4yOZLD6h1rzwxpo4LTkVORu +yB6Y+V7gOHYyxroK3U4vV2HyBAvHdLMzB164rRCWLPppzYm8faaf8JKNEsvWu1uz +885/g+M3AdUA7Mc82zwYpVo8jgapou/hFWBxAmKMeXD5ik71ZhJdQ8i/8jpNml6B +WXEPjXUTP051oZvqD0Gzy+K4lzdrajJCRe2647K7QiTDw6wofkrE4hZxXcw43NdJ +17+HWFT/C68tpnUpSzsGHOnlH8Zl75kBmqttl3D19XRbE5oaVPgZytH9ax4mgFDd +800RP6WWfDAX+cfYb6uxXAPQoJ9/7UMJXP/4ZE9b+MyuIHZInCWunVs/RluUxjza +a3a6iwJ+DMenM3WQn5HniQdlgPYzzge/UcHffLXoN/h1ECJWbVU948zvE7UYVyA4 +wpHGJsnuJMbWAvkORPaU7lRNWl3Y8vBwUnhItt53EVXkPBqBWm3k94TL7mFiVGbf +9q25jnIsuOwyNeUHM9vxcg6j0KhxZaK6Iel77sVIcCOV1YV53GcCRt4EUhor73uF +rC8jicHaU12R/Z9zQtLGuouQ5d85oror0J8WD8dU4r8cMhEtPgO8LN1XIjAdEmJ8 +ghSsynb1jGyW4ggZI2yA3m29GvsEOZdPzR9kfcQbviVvruJH5sgAoi9cJDyZtFYz +CvBspKwsGUtZrsWbYRyNwY33Jcj2zmXfHa7NGUCktWyaEL/QjgTTZQr6UHuglvKV +bYVDuqcq1BiYnGJ88RU2u9IWHXnwRDqbbjIsUC60Wc575wwfLJjxvpnwrjLEtjT4 +9OJK617J2RCULNrKv+PL493w0W3BUFOZ7BJkYvXB9Hp2ZBkcdiuXrIgdriPy+e2C +zRbDPZsm3skUPCD8nsE4VxJgp/FQFxUnhIgJQ64ECd+CIJty/2zUWajKFGYzTEKW +bMArHkyCpZJ3vROK9yyTVE5spmKLie4dCYalhBNnWbWv5nRjFNL+Cney3hj6Z6zV +HQdhmn7MFITCDmcYR+muQg7eVoTFy9md5dFwS9pyrOUvVhxUFAxrfYpvNkxHrVBt +R3eHXTJQ9Hq/gy2eKTSndAmWlv4Agkno/jVHMDeph+TFxmc0dtqr2HGvwdAbiOJe +sB3ROE4LnPshWexLffwS2g5GBtZvFgD2h4eRSuRFNevhLWgto3oc1W8fHgdKX2yh +sBEbXtlea11P0OKdw8BIgbvFLJc4qJoQka1bp1K6L/g4GVAuHeXmNkoeJ+fGKD/O +pXAPctm9EZa0Fbqx2gonfZoB/6XCUK3Ylw87Tc0HUkO+qRL4ojwOCaEM2FGWqkoy +H/y8Vg4JnJ9oaCurFvN2ry7bLhs0+Uotx266SCAOvxrZ6UYYHsyDotx6IrPY+GcZ +PJnNIy7M4x/7ao0lhYgblE+Qn0yfCvY9X8wAqNzT9NNU0FG4fSuxaBnStF7g8dJC +wUFDpQKaqndxmNQcm2pQBf7iXCSJYxcuiKO35UlUdP2Idib5PIS27io3niROH7Rs +NA8NB4/0Tc/AFtz8j6M53LYfor+JBLfOCFG96E1aAdB75zVgmYLr7/6ZQltDV9r6 +J6ziW8iwP8nb/6lLkhmSHzgLeJsVcvZ4vu7k0GxAGH3OaUGgcT1SH/vNSzIan3Br +kpn45k8SMPo+G/34q7jkk8u47WO8wGHyZmH1kOBE/ghlSbfkwVE4NxjDmjNa3axp +bPuGxwKCkZT4eAfOs7LReUWk8VrIBS6zxieP/O4BYL8cWYeBxr89S4WCfudtMHiw +aaoRjE4ZMoRYb7O/4BEoa6K2wQylj/VPEh0xI303quE1JBnbqh8IMa98CQS3rILD +KhBT9ZLRAvz04kWpqOs5W58Bk0pFFfVtPCqjjU02bd3fAw7lmpX5zg6to/1yipVX +1WX26iD1UP9T2OXsSOpEZTH8+SI9G7onOeXh7s33ovbOb12pTPz9XwQbHoxnlEIw +LRI6X3qv+wEumAKbTr4WB4+JVMEADelrgty7PfsZcwGvO/WbUGJfl2JI95Eg5kSj ++eN9RQU7lTEHeby5/ExhcAosGYzhTYeXtGqbU5FufNHbOn3YkWeysjF4wQglPKhE +WbCVdOQP3SuGZOafFgGxxDenYv3oD+dRCQP/r7QkESr0uBGSALils05YwWyOxCNa +CyCpNNhv7HjlMAzpMnERH6AK2jHBYAm9kma6J30bhJ2tnqZojRlZ+jNboQ/svRe9 +sFMbmu3kXYFoslCiUXcxpnMYk8xbvb48p4mZ5RmJjtq3oGA67pIqe+ZzJyLeNmh6 +CsAcv+7ZQ5TSUrjgKLy4rvKee7V3mXCy/Q2z1eBdup5j/XQyhqLNdvM4jkoevL65 +vcBaK5tWd71TDHEA7FG5HbsF9CQWQiV1YyN0QlDJyCnYF73oIzUxUtwSpQCCqTQA +QKb4/2kB0fOMTF55xlX2dv27zFStlTXEGOBNXdHp+gwCqjyRH5peEjTabPGoyvNv +yFVsyal/tkMAv0g66PIZYBtNWIAtvungEt6OewbcyRRbe4nvl9K0Fx3XQN35V5q3 +p02OxXh6GvTlGl92Gi0B3gLdvEzQ2zRnqLciM1UYmcnqrMndrcGwCq9MVDGDzlXU +yCcOnU1yope8Tz2ifdbIXz1P74sIkhPkXsRcL+BFf8aHE4DRc1wJgl0h80StkRIA +VhQuhEirXAJPHxyF91L+jVRVtJHGgFIJR1R9w0r9TZHNtXFdkj0Q8iDDVEG303iY +TFvmQ5Sj+9QGK3dMV+12KrmZjHgJqhkPPMfsu3IovI/WhgyzQvRpg3PDI6MsJdGK +vYpYRTdJqtZAfKALha+MvYNmbhvlYnNWHtifUYnxGwfs3Q6bK1FFQcaWvU2yQLc3 +ZfazD/7safKqjFf4/6XTCxRj4dDcrwDr+B0z6Np2uudxmluSV60fDhptfibcurcr +zf4am6Re1NRMvODrvO58EOSD20I3HXgktyQO7kSvt/n8cqz6bBZJ27QJAN8XVTvj +6VkuLPj8TnpSte95I3fkhhi7SYV8ILLQekqKRFLDXK/xW9j6ma422pvi0BP6dozY +UPHtpOgg50x6fwMps/GJdPTlqm+V3tBqBKbLUF0ps9iBY39n6tTp6NFmJdqcGRGf +GlqR8quZ7EyrBiBn3uv57eBguQjlzbit8oSQdmSZjx77/S9fu0oJVkGzTFX+t3ts +45+kZi/GISMfgszpFa4h0BwMe6QeMUoAsmTmYGkZMuXoWyJvcvjvRJBdomEuBkoi +RT/ZDWaLj4WNgv+lHFydKxDDgWsPUuO9Z2Cro1XKEineTopFvyCPXElkuo7NSWoF +XUBKEJT2ELld8LNlYfb9yF01jFmTIm0qIEUtE8NSm42IVoQpBpSEUHdeCoKPkDFT +nlvE3gH+JoBwDo0UF6qNzV/WO5JMXICLs/z6tXiQntzjlH6ZRwbROIe8/0aEF+o0 +4xw86N2x22u94WXZbjnKNkDncMBMtg3/6kZEBe0HlFKTLKHYNdbvdIi8zJF2za5Y +BKO1/ouKM/76xRCWotV/4jKkptf/J/siNBpGoV4BTetTrKTdUBV0tVDM2f55VzhA +uHPMky5HNcF3bD4jZmPehwL7UXvoY0TCNXUANNSqyNa6ocoh7jhPO6/GJPVutDGd +nC6AJuiNe35bDuulvybUxCOgVvMXVJoEPVai0fvdsxPZPyWKcmgi4bfIiGgd0jqh +hqVUdrmh5NKtqJAkuU8ekg5pugjwf5QzFdKiIgLKfDE7WMZuN+nLiTlreqX989ki +zc9iJ3xX0lyPzaZ2r/PnH2hlfjKvoOynlKU6vwpUnPYfc8qqx5AxZiwhxOYI77HB +LHM8GFZDJewJrNfQMnRinF1Hy6rlh6rkBtGLGQdOlhVPoOnGOWGnHg6fdfXGHCVH +Gq6WVxHw0Kjemylc1zUFcbV19D4YcpXtMIHuJrhwFoJEU0ShwVAkyAUZHqZbgnz+ +K2Fv7fddBOEdENzJ1V9/JIMnz2i4yT8shyFuJmqn6bvlVMYrQs5uE9aqvM8vHBjF +YMY0pjiQsw41MRyZlCHocEO0yNlhCCWeO9RPwbvBZllsD/WV/cU3EFr7m6hyitCP +T8V/Cdr0inmShN6/VsECVnzP/x+w++O7t2d/xkxTdKP0riRfMJcNcPrdgLsLW/eo +F7Ia0nPrHNeQRV6LfUbj7Zy7Eatox0MU2mVYW/yNQMMO5kZFMLn+jRS1E6XQHrx6 +2aTeHV2MOFsYa6cKNb616dpRD4XvbiTX542T4Sf8p1vzEVrqyv/jHU/7u0blgn/u +6d7gWyEMTNidLXfNvw4GVpm8b8rCTmStUkTXHQLP/2U+dr3VbP1olE4piQDknvjp +TsUcgTec+ArHzDwgtE5JyN/aFVG7VKCLWltVnLMhwlgX08vkxrCnDa0Q5J0gDRNK +gWkRctIZ9z6Z8txBXxAWdwtdFYQKbkSF1Vzrl2RNMOaUUtjOvDaQw/RzsYV3svho +C+9oVeqPLO5iz+poVp9ph2M3Jpy7nxmsU9aORORAXAuyqEb1Ck0DVyxWjt2z374y +i8d/Wc0zdbjSJYf/2crxJxyhg/IuE0ApUvdIi0im8Rz0dHJNsl5nEhLIgwGOl2HT +PKJmmuAYfPU/MILy04dV1DU393lM3e7XAY9JmzSYrLfYwWgJfOgLHvQhIYIOytH+ +2y8e1ENqQizbO9V2jQ3+3pVg0UhLO3EXJCcPfka6wCgHYUnI3U8DlSyMTedR+mYj +Zzhx0hL0pEzpW0mxIw3mC3HaegfKsNCdEox0e3/hqW+n/Uo1J1DBGvjXQJgt0MxC +ydQBcNEF0tVKddlCXegnT+BkSQur0itTCdKBppfaZ8uXLZthaiiJ7oB3Xvlnd/km +8k34c0EevDvznD5e9ChO2ElV7XAA69eBHYKyOIyCe5EgNBE4HQcDzjH6522ysxS1 +wXHhBT9SJHazqf2S/0p/07nmRqhT5vBgp7D5yu236ethvUZmRhBVQeQYl4S2eKG8 +PKmBhJrrTiU15fZ5EWb1wsb4DjQTMhENIdWcxZa3D//Q9Ihm2ZXlk0hj3dDLSBIE +o+QRDXy0ZS7Ys37bGsac4vDsj4NRizFJ22g8NQBwl9zZKl3rXbOTChHQkSxHic95 +5GQudtI7HZZtV3fF51n5C1JtrTCd/BI209GHOdIAda85W2hd+A7xRp/gs+7R+eaS +OrVRLOqyNRnVsqEpC1GtxlLg9/9iZ+jm3eVPKbENdycFRuFBofFj2QUUpQ5bNFRL +SuXBaSmJnCT8k0N+PygJQqcDcnIsBzqherl3muJH0TgfqLimQo9hfcdYZQWWct28 +C6HLPsHAZOY27zq/sLYUjIHx+Iu4pFz0gso1D0LVWM0SWeuBrA+HgNCzkkvwKLHH +SuOGgEZ33GpyHqTLbHdcmmcDKLxWtuf9od1Hz7ZRyI6iSCbGsHh1dISwLxHmnJkd +bSJbHgUKVpCNTbcPqfTT9sm2d7qPWUSt9nngaxy7b45YkLifnqhNDfkF6UX07+iH +0uWbZK1QoXhd6s2Jydd5jlOTCgy9UzzxDOZIzVKOl3Vc3Q7PuxfgRJ0EAcC0UF+D +Qh2W+56Nab7fjC93EHJCp15Cv18k5QSR0ng5h1E+GCCK5c8CZA3HuwEEodK7vHXK +7ARQwoRrf5nAKFgBaWNyCH6CaWoJqdLTPaaXCHXdAjDoSFtJijD4hcQxEL2acCQ5 +KHmchBPEfqsyQkPo54sI4Yt5TahBvg2sCMT/h8YrO0ifXFpT6CheheOzN7AmF+GE +Qy5EP2wL5y7UWhxqjrP6zn0n67k17+HlT/Bc/AdvZI9Vq5B+8LzaI7izb0QVMk7g +nns5Yic0JpsK68gik2OvICAjp+uPouaZBWPtaQsFp3VU6vgY0wpZe5xDScuk08e6 +T9MCsunJdNPMus4EHVSgw7rfO8BsFpiP8uwP3xh0i7quK1v7R7272RiU+RZ4+Uzc +2SDHOuVMvtCxkNT48Fuc0o2NuZRGrm5NIo9wwrH5MblfGBhglaz57feifeWMDRdl +lI4loZwVB46Uw/BFtxc+Q/nm6V5qP3v3Q4lW32DaagGIb+AILnWX55Q2xMhaCwfs ++fRxZ2S1c/QZzNfP1LE5dsuxAvD5oxJw9m59L5eBPvBUKTMMsO2xCkRZp+ooTkD2 +Qn7MygL27JV4PlpXNMFsLSNiu9+VxXyTUD+d+VQN8u55qaP2dKrG7M3T4x+qFpvF +FhOEj0ZVbS09kKcUsjkjUgyv4m5nJJCl4Kr1O5TdRtbhG5oHhSwhcYBV5uahpfUm +dkc3LB1Is+d8Vg7ls/qbbPGXLSiTlzmZT8xHscgLFdemimW3LTSV0w1aEt2HWKJq +kPQXoHmFmOs0/m5RzvfcccChyJbwMj9LkZCQTrat8Msqgqj+ZUoS4Xtyp43tUhnp +WVCg9TW6t5v3HNP0Ld9jawX/DNgPmScyUjvfO1LxD9KQuXzBQ5Ox2e5v/3YeHnlP +CLjeFvq5IGGy1iQEMIURIb2FPEaB2JkI0JbHdkNKQm8EldHNpOPXlILGqMd1c+Dl +cRafz36fFYlAC7vR1bhbSoSiWWvCK9nQSSUckDAfCyW3EXD2r/TNHChIlwduZxtm +U9uqqyvvKrz5aJFTR+X56oukSD93wLqVy3w/nk26tY+pqnAlOw8apYLabGzxHWQM +5UgZqBoRDIA8M+ep/jtw45M09gcdFxQcJGZkNHl71MsiZ55mSzIQRcUdQYwunlmT +Og5P4yhMiCKn8z9imHveHjfJ5pNEoRNyxVhAshrQ8c+YAug7sO1gCtCC17avoEGQ +YJtOxwjIARwMHG8XAKkhEQcWtUAtaHDPfW7iiTPiXMj5iBeq2ogA7Qh8Cvm+w5+f +v7IkP0AZ6VcLz+dy/fc59DAtPyz8RXNSrEYgqdxEmCyEcsRlAMHfOCH1hgtPuMX8 +zE8DmiJm/iHLdBJFAOoXwTuJjWuUML2PFWky5OqHD7NYvuVks1ak0Gfntl2xfyQB +SjFIwNxBtXerJrv+JIuSYsyvDuOYJegm7qSYPAGn58IwwmsQNynRiYQ0IQpaXZes +tIaitKRw0pdlqm0HwZ3KW8Fjd0yGphUfgRKNgABwge3Afnd4xT7hmwUHnxkBviOg +BgFVu715+5Ih+rcehMbzcx4Iuf/KvyfxDreoYfgiWFbVJ0R3fRSp5JXTydyMOgQb +mL9EXMnIoe3fj/50CgbVyogK1/uBMriNp3ipK5i0nQf4CFbM56Q7FoQdzomoaNUd +ZGjy4A4t8bpJVMBFVsDbkO4dBx5rFFZEkj4nZ3F8y6wHuWAZI0wDrslKNHuxuv62 +kziWqsIUmmC3FHzmC8qsZPQ7cXAduJY1Y8DEPJjgvLHT9yGXjuWbLT2XuNSVI/az +175f4TKRc0wCEUNnwKuaY4R2p1Mf2Y0Dfk9QaAUPVeNeXcE9vih5XVSWZJYtreRN +H9WRbnm25FrT8eXa4tsgELpzxLUnc8dod+7UlbYe57kkec0UQCGLzlSDC+fFeiFD +T7VlI1PaJsngKi68QH/ey50bfdDl545Z2tCHoPUmqKn+ei4J1IovuvhJB8y0OajY +islleSYyg4KrS0zFW+T8IxizTlvea6TUw1M5xD29WXhRQ2zxwWqMvR/b6EQBsoQN +faMmj4j+PHxUfJOKF3G54iyMW4FG/sIdM7m62DAGFl9K+Gg6d6x6enDCJq8nMuNs +OzSA/rScUeVu8dT0Q8dC9KyMnXxGNCzoZW2w63NFMLpjqGur30/3w+Fir9NT1DrX +kg1ja7l7NSLsLwap/tu06CY3DpPs6vLv+i4TnngHN97+JJcfRTYz2VjdHqcTkoYj +h4Zzib3m8cpF9k1ZkWvDgyNyp2cD0ToB8QZP1cCJBpJSUB1kQ2iyyNeS674F5z7u +meaAiKJBHUaQoiSkZNB7HnghDXEZwRvtijAeM9BzlXPG+ZYrMvrK4qmFHhcRESU+ +Gb3RXc/TQpocFv9qVnuucYqqvv7tJSMeId1N+pQoPc58e0/TCwfbqBOdNCqPeFbr +8VUKf0rucDDc9ZdIo+h86dirLXOJ9ShO87E9SaT2rwAMF7IwhAr8LvVVbZWeSABu +p7KYIo/164GeRC8JwUYOWS37O0bal5l+1VuRZ1ZngwxQ3FeW8syrT6/sh0kEM3nc +qQtC/z6PqVyY+6XgyXgE0FFgV51EYT5QsCD6Lx3oRAxTHVuiEqufhD2MTeWcGDi5 +haN0tFjTHC/dkX3/jRqu8XhjR6bJFb6QCWp7vMm7MyYEFalycR8UrmEgh/q3ckoT +icA4fjt1n2tv36uzAVf4gZMXDTNwfJ7F2y4xd006uZ8TFn9TO6uZTOMY2yLEVp+b +2klQ/WaxtGUUf6TnV068ANB2Q92MxcDNy8hSHT7b/6AQEwz5AQwqw99cDGQB0Ft9 +ftCX8okvNs8n/RBhzoUZiydvWqe2zFLTY9dkAikD4oLp0p3kU6nGXn77G47pYg54 +MpaG5svyl4kT5TaIYBN8P5K92oxPCryabtLCCm+OYpCHDQZ/xmJiUltTOAJPUWNS +uD20A7mQ5Ib8ABygL29yZkmU6Pilxf1+lYlNDcFqssHR1lDEJk+lBu69XdduvoYE +tcnjEVxbLSJgi22tbcS+xmssNTtAub4ff0APfnKNK923H/P8/qt8A9RG7CdXGjzb +Ii614/WjrKV6evtJ4I/QF68Ke2i1yEwJf9xavzUeywshiiGqaY2egZtp1Zq9ap0x +jvcb/uNAk1ckaHonoN086yfCtvc6iUcJ5XQjCxXDWZGxrOKhnExilGwnZlLscP1R +9bGMdCbYDp0sEQ7gcIRZOMPxQ0sArwoLzpaSDJbiRaeK87bvMooX99D9FUNSsfA6 +x0bZUNfTzm+tDNLjrBnIvxYzEktLiFp/SzKuSUvMxQxXK+1q8UXtWz01AGgdrPan +bdgZ6Dr9qlaebCCnBr5Lx7tXLkKCR+D1uVNB2zRzygdGljNGk7+K069FZqgCKq07 +e5Hif4TeCMK1CNN3eJN14AUudxFViS2ZARdBP5/bw4CH++Zhizfc2TZcJuRbSOEZ +gjiJnZppXBVWtW7H9cJ1SXRcr+QADq0+be04SpquoGaWS57oThhBxv/0VkhpQe3w +Zzj6rQK/9GB62qTPZ+1XtVfU46VNYlJy3L4NIyaMHH7V+0IUz3+RYacSHYwc6ql/ +mjYyt/hXssIG76nmzzzepP9UpedptN7gjmKwvTkbSR7oq7PH4W+VqPR1Kl4yGXOb +8sranw0Fr2iXvt9eNQDOpvcw9S5CRMd1a4FUDGROyNz7C6NFngxULrI6ehzciGlA +yGGwHWpEijp04sGzHrmXNWOWxzC4CXEjQpbK8LfFEQM87Bdpj6DGUUzs0c62RGjb +pxBg5MrU/sns+7OTWsztU/nDpHiPaiUXoid9ss5ybw486gQ7Q4WRCA4uEwwkAyxp +n4WlX6Gymmw1bdkHJxIGfp9TW91zSsiV6FtiM1GWlTPDveqcDbS4ToDO53MctDnw +ojTtI85cg/SkjZBv2BxXm/QACuLHDXKJMkJ1DMdOhJ9Kx8RwXJrfIPae1efIK92C +qfw+F1v0swqxYct9AOUbkJP7x/YaC9jtgCBMDHdxirc/Tb/yn94fdhFJ30/NbLYV +PTE5Vf65iBaCnONJOiD05z1BwQr6CqvDla+dIHyTL2pjY5c/LUvzkvUBa01QYCFI +os83K63TLaZDGbP427FSYbePZBWdCx43F0b9mDufZzZ1wfSaPGZ/8yDTe2ld3qvG +d2KaAnv1HXAIiKPCYwFh9xquv3cvbZ5pn9/rJgSc6CuafSWOm9gR2j2zIaM74fvQ +OCDK9GyN1F6joU6sBpJYgXMNIZ7we3WcS4IXD2ia0MrEG3H8iqsKcWbHvWOUs9Wz +aiSKaRGsQqY9tHc6Ztcoozzm9unwqqtJow3E9msFzUJg1DhDDbE7bcgvl2fRVtC+ +Ilw1KJ5X3X8kp0+Rzhi1t4HiVqo6wJyUwBuPaS7cDx8d5bIH7sHoOXATPmCipKLl +PXO0JaLgpkiNOKenpav0oQBLBCDSFGUQ4mBKgVTbV43xabuRN1TMUwaSHmVk9DCP +N55kpCKVoJ2beArOQOwB3y0aKuD3Cw6HmaAu/nDK7iVXFgKNb+ueJkfEM+z7ibyd +i2xcK3g8uHpAdrWZ65ag2vKqqk/6oDTevaoK1MVBnwwZ0I9F1VhuV6vbxIehkTm+ +HWs7tZnRTN75TedPWNzsh0MRBrtDZE4I4kOX8Co0LiHsuSYLFERs7IzqFBoQ8ogV +t2yuuL9M5XqY+mY9gWw4GgKbsGENz/sMzNJ/WjR0CxYzOJgAtVPnQUwNWGGnKYWo +ECIbsEMmRzPDwvzVaQEITJOJhFcuP8eur55OY+QBHrBAdOGZreKaGoEfG9AAtpyn ++/F/bqooe8XWPhu3sJob2oDZgwo1wGH/l4Cw8em1Je38WuCwWHzN3CHe1AvRJpyF +RDx58nEQ8cXRCQYAE6V84vB+BQUHvEfQjQuW3qy+8RSKvDK7YKc/K6AHNQFodMA9 +H49xbMBH7723FhDSRNuCognCZELuZTYpsTda8nARGu1aRNC1BntekT3loKnAEApZ +ShtdBIW0TRuxEJbDxeS7KokgH+bG37oC9L6CQpMbfwIwN0SWjokKnR7/14HVxs9J +Pg4Oyr7vzTaRlv7Te0LrgLcAd6Z2L3KwaBJYpUnPSmbXWaiIhjRsD+LmvYG3dKQI +nMIsgZ6SKg3HIkCjdyWsTlIsnZDIF8DQoGFeD9gsdoNNIJIL1LYTJ+lfmyAv9qp3 +N6ppiFATqQ/jSNCtdHlTR5KNNcOg5NeiTTTuCpf99pX3sgHFxc4Qh+kI3Eg5vldO +kttMtryfGsinoww4nsL6azPH/NYGMYF3dAa7UiJQBANFbVHoGgD0Cv4rZPZaPn/l +TNhP9Y4AZSc8r5SMfiKJwUMvHKB9c121WfQaWVKC6IP8PnVzd7jht/b4g/0nU2zB +07Z0mMzqvKnbnkLYmVBnZlbUPJNNdsHucgSw2AIyQeUuASSZnWoVSGCAejzs1zNj +NMSKgF70HGn5FziUOo9QiPO/no9GkO20pI2rS4XDqDkVu/FE24dXfA8/761HiSou +0VZX2oY5rQouWCQrbsLoS/ljff1ma+pVARhhca336Y8mDOkr0y3ve4pAI+zSdbsz +p1g0P9ZCfEH9du1cM4l0wMQqCQohSzu0bUUO+KbClsP9CEGIyRCiuc93H/J9EGDJ +9OIanF67BfU574fM2cc5V4jQaXMXW2bdhHtO/73zg//jHdm6a7ws0gMbisUgGBkp +MsajgD/NU8eY8IRyd6nBESwrxFW1zKOmDQchOE859k1iVoma9onHtYCww0zyz1Mb +zoCoY1nK0HqUmHVBv9NSrZ6BgME3gXPYVX+1Z36WKspQ4br18SofP1EVAdtTzy8G +52dx67sMzA1ui45amt4BelRsOyiUH5nubf9f8i9eM5FsQIfbD06QQ3kwtoy66MRN +6ICy2ZTb67cl0sBsyjMK4W+jfbJMgApg4xrsnL5CC1NyvCvsb5v3VwIIv+Hdn+Tv +cJD+QYCaJr7mi5VqFll4K7E+8gXB1cg7KzzqRwNseMPOsfjM3xMSLGjZl9Rlq98s +YGcclSetfjsZXyShB9/jszNsXvg+H7OJIq8slP5SFRqdVt7WEN46yITwof7Cjjdz +Tm3lwXx8wGejEPlv+Fli1oppzGkL8RgUXAdSiQAwn6D8N52g6Y0sz3ln9+0979QB +gxeFRaXe/IiyfvG4g3/wd17rgCfiIPfj0KLNA7xvUzyVrtYIgHmHeLry/ZvJsSJD +9iVHX8HmND/Cp+TU3hN9L48JJ9Qlr+TseFVek3oya2zuDT9+juzYLACioEM7nZpx +epyVaWdt9rs70xptSVtka9b2ESFPriq9cxPxQRWgfl+rn9Th+nHG7H1CGgwHmcdX +BArKV6dT20jJZzoYZDYzRuxmLflTXan+x2hWOcfUopQrVDoRrywWGeYgPazO3d8b +syrWNwrNRldOFJitL4x3r1jHFHpl/L8bGNnwR2x8UMsXQbYf5ge2HAQM1Hmxu1c0 +8wwnOigpud+Hi7NWrO8tLBt5pKHgOlOvMMbOcID8Usj1a5uDZ6ibbwuTgQStscrn +F0/AhD5KjEn6sj3J9TGt+71o2vG6HXXda6x9fYlnohVREEdwlbOfU5CqSrVn54y6 ++1jKKXmYNhq0BkDJX8LdCTfemvExy3e3qUVyezQNJRf0bjwRmAN3HZ0fS4zSmVgy +CzPzbqVnppKMPMF8jfp4FQa4vanvQhWR5blpibVu+CP/XsCgw4XsL6snsVVzaKFM +7DO3ka1N/vLYqjLZLMZCOfLCegLTdZNJ660NPKUuLfkGnQ/b9EmelR/SungqE7KJ +MnQPqtVvJEdDiv+ANiwbD42SgPilx/tRcgDSVdmNowM2HZFZkA+9kAFbvEpM9L3P +RmQa/+sYWkyVVljWIN4Ihz5v2F3pwNxyX4p9tsf6WXW0KFB50+WICRi0lA6S/uSD +v264fkPMefir+MEMINuvMe1mkjl4YNIVvLiiXoLjgj9MfXKXgpAXMsWbEIo8RfFW +1iFrnzcLwXowEzPtzmx3ta7kyjZ2i5ReIuHvFhQ6yy1U2fV8YVF4GkzHtvfjiQ1E +I5+tgrFTbMPzZJ/YHI4sYonnBkFBjx6A+3ozDyhGf6Ol/1X1X/mXDSbzFVOmFn4F +VpNsinjNPxS3zzrQfuhmcxJ9xiXKyKt7/nmNDOCOk+ZrNQpo54WtpajlmR3kqdkK +pulWLv3kitFjjeBeUoK9PXKmUPX5XllShROUwTdfZoLNBZ9vP49dr6s+rjv4Nqoi +NlRyuM+2YA2Tx89NUDra1H+/t1y3rPW0YwIVrsK6UE9CtHZ0YYWgrUoA0w+cjC9R +8xV6qGoXS5dWVtbKt2+7Nn75EALdwXPeVKvlLd5c++5j4g3iT9xCdzICv6A9p1pw +be3zfN0hflvBntjxGaHtrkDrSFxtN415A2tcw9uiWjKFUKmkO+vtw1S2h0y4inaw +Kcnh0N2HvzPQhu4j7mliEm1KP8IUVHvb6zWhGKjP3aBO1CYddu0iDrXm22l5oVnj +Ee81Yn85cz9v/p0bj0fBQDZXRbo2LX4f1VGJFZiSXM5gm9ZqKw86tSolEMt2jrE8 +5Jw0LEcQjzBhJYyI3McRZ2Bb5PBS7tJv2wMDpT1k4oqLE6hkCO0qW6Jk0mgyQ6Xo +SNT4yQqdjo3Tl30qhKAze3gqI0wcQIt6B4MFFcoGr/+61y9sm5sF8S9kSjy9EPgy +xbJhHLCbZRqzgyKCAiQW1ltyd6/wjRVUythswVsGhCFlgYtWuzojteO7t/F2SSHK +wy/Gs5iSbImt9SXUTbX1XCs1sYb/9wCT/YD4x9sxPwrx7GU8V+WFjVLDubIIiOav +FK4eidf3/eKq0vyvqKXRXoPnMFrER8Iw6Ouk7VrAdp9/UZFiZd1/ejR4qINQFo4n +i2pppTbcaNWtjrKBsokKN2yQ21lIr6kP4OuSuigknddXRaBmV5JPoqS4XpzyF4/c +BhhTFS6q6axuM6NBpErGxTJR5TYDG0H7Xa8Bze7pyjIgdf8/12LyVAt56HDUpGXd +oaC7EMvuS2OBkTAqu9Wqnk7N5FjeTfgNisVB+CmZAW9GBEU7RSuDgr6bOOrNT97h +52IFMicAGEGqO/igClC2nQ5p/bwFvRHj/tPmN+JUkIL/3ePZR5nMnvIy03jGBqrj ++akLAKIYqyqVk2bsZJbPFgzP8W2VossD5ranZcJpYqY6vRoDhRnVDyYRiSh9MOan +J85UIWKd5zTG9ml1us6BJkzPVEa8wmXkEQT0x5LW3RnZvfZGBLmVWec05WZ8nj6w +a38HkKz1/jvcVIS5Ol00iMxGPWols6zj6WvFaOPRVNUH6p8Tri72SEVLia7h9d0k +i2zbntWKwTA5UDpLDvWmlb9o7WajhSRkPXL01pm4afFKJT6vSocqZbJoCQzS5OSS +ayWEIaeFoX0XW10QSWhbja4Q3nY+jbWEoBsxL7PwJAmh8JwK393IdcUxWB52M4o4 +q+jnlkGJVLHEqdvLgTVtxMjpq8/PxZZp4RgNhPoe6lju+M/vvPhX65R2nr9byS0k +CxgtfmRduqFfKjT+bWBpqFTC43VqxwEaTHkPnQ4lZZDHFxX/EeKsZlDMUL4+tGdD ++7PWmZRH8N5zxLZqepFU1nOO1mwT+zJcmCWujXzuQhn2oflK1CvvHSmvsYRdpZRK +M1uKZU9IQe5ZXhXzBE5jteTb3qjuRv/tbmsq+3ad28eILlQ02lU2jxY8H6ytU3mt +UnoaU46ylXDaLOiMiYV/VsADwAJltZqRmBLOVReK+i/5s4wztNZVwye6x91GTcNw +WGa4JB3o4FZovI7Juo3Epe0SIHHU/ZtRi6yNskVKkrGzQLs3Op5c+84TMvb/NeP8 +uqkYBK+c9ESUA7ie/Mknqz9bMmC6vXMBAQn7TRItS3kqLjqa0Flk2doCkOU2NuJS +RfqBY1mscAvgCxA4mWD8eTyYSKsPam4Im0wAfnm4/fmo+3aqkYd47OWOhfwph2Yu +skUwzzCIM0WTK7F1SN/4571nMzZYyY+1U5gEokyfhGB6Fs8K8bhhl8FWkWxgmf9e +mwAs9O5omJfk4kUxD9vUOH6SgD/uTQb8kgYed2glVT78v5MW+hhQJGNAd+DkMZJI +rFr9ti2Ahs2pQyDMQXYgXt5aL4J6f9sobefo5PN9hjWhLuU5OX7yHaChbPQsCbKe ++SF6MAfRCDrGO7Rzma+PKZclib5g9sizqE2SovNAoaDbd3s2z1Wuw/EuhEhJ50pq +n+MURfi89w6B+Eqz0Nx0lB2OOlehM2EdbIibk9HWPV5qKOV3+bZpC+jDkjO3CFHM +EbEQb07rFPP/ZdrpY+VB/kdLr2SJHRwPBCPTSXn0frzjv6/OLG1wreDLtvkhxJ25 +FxLqZg2i3QSzH2fYBgRAlbp7QzXMajeVwpfRXUBdfH7Dd8ppIMzNqmdQqiLOVqPF +X74wVUQHaW9ITDxTTmgMLx01sHMkkH8jojsjBmZXQyCigj3wfs87xVWkNQT2vkN5 +VEIiPnnPW6mJ8x2xAWgeAKWcP9vvaQ9lZ1uccuOuX/ouivmMl//ravQIZ+XTPz1r +BcP0CfU3NSM+RVlxKADO+laD4mdirWTbDal9S0t+QCuMD66EsH42lRH0iuHOVBPh +zjKK7+G6RTR2Mlrh2lVLGLOrh59DRg9X26Pn97R3sAjG1eZR8hc9q2Qkh2/Fq2Uw +mGgL5fBBPX9LRg+30MaQaPCh+CcgI7ZUAT8GiMa/CdsptVmYgeEUdPmjq2wYMX+N +wbULr1S0t/AStBUKi4vHNusVvyFqu1iXU0kLqfnqe6+VKsC/RqEf8EYj4DbSe614 +o0j5WXACGqHUV636HECh3Fz1bzk5XjtZXXya07FaqXD438AeZZi8W8htmLGwLhZy +CxNo0cpzQHaB8eJSW6T+jdDmqBh6U5TibXiGTtxMoNXBGW81ccMrAPxicN5PttPH +09OqFQMaA2jLznr0U2APkBaZfwdhLgBoAig8ckBiYr0NRJ2UZgHMM6Yqr1cLKT70 +9tBkxDd76ygnGWqnTpDz+pMTylRHJ9mxlqFFdApFI3RzT/vCXPYM+p8SBjzPJ4Jm +xcofzZw2Y2OCnvssMYsnvPv22mAsGvtvyD0KBkOdD/KJ6HVZc7B8NUcB5oEGNuEA +wiwicMF/nAJT0ZtVE9fvXSH17rOQZLBNR7DQ8TfqB4sFcVHSHMocfrtIml1bjIQv +OOiTF5ElzJEqf7x304cbcVI6R8jGljdEn5SwS/M5r/KKI8UzzlwgcCXrOafNDdDH +3nOPkZtKBa59HrqBzN50oZS8stfKIs6YJnWhwdZ/hqW4mLKFRNFY5uHMNNQtpfqM +bUhMBCwpUQsgdbxyTNdtQfDOYXhYfTFMlQgkieC+IWxLmImeLf5Po4Yr1Dn0FiCJ +gluYUOMATIsZ0DVHt+ZeOP35QaviTP1g1YQF6u8oATiVTMc3HOTY6vYW9xz2haqG +W98E5fULykkuUkVkI4ckBkQ2N0wPknrmFBg6S2sdMe1GDxPHtaMobg9i4cNfdqu1 +xzaniNSG7VcNnWNNltPlH90SvkbKjExUiPqYBQpju6Bp6dJvpKOFfKgHSSxETsTE +YlWtN2yjCaS60D8GCJG7x2lpZwa+WheFcGxZAbxaZ0rwEaNMbJES0bjzFq+3udm/ +JIjLl7NQvPhiEYkOeANgDAttvvxKMmHeEsAC/ZgY2bROOXLLqUovMKtCtK0C3s7p +TlDcNkMVNy9AkGgbTCDlzy4kwM0KXJOeqPACOUsIB4GQIYoh1l8scM2+IOR41qk2 +capoS4mT1SDiIw6wnHFKM8AM3QbDFwKnlW4AZOAlsBvpd9bajpHMr4PnnPOdgtCJ +ImE+zKnLgMskFFyOQutUnkm5EcjMmDYOhoBf/+ov3cLgxfex3VQ38NhcOf4XxRbC +2dfB7dbXY8Hdz84+/HjMzdyur8HQBLLujnAPds3T2JZJSporm9btl+xlwbVOlv0/ +yBeHJ2+0Uo1pdsdayy7R8VUgOf526yeto30uv2plnBihlvfuEmSquVdktWGsJfuh +dK6QPavx+SBgoXHmlZjXlCRRfYi6tNHjpJmx8/cpQQjiZDcnVfKrlKWyza/83fyB +NFy+j1JyCkvkFPNWYwj7aRqo08gpXrZoRSHN1xlCQUuib2Kk9eohU9PoY5g3Kn9V ++EyuusDToBNpF5prWD4JQhBDbwTRr0iWdd5baeXaYZ4g3SW4Dk1Pq2O2K+I9+ISb +5Mic4crU5GZYwqvWk9L8gzftmTE+0qcJrfmy0SOgo96pBEAjswzdNj5Y+Cni16Oi +6uUpMofWOh04+pargm7AV8bctIj4CijKcUJbHo4jnYxPw+VzjUaw9oy+Mq6mwrXC +vs50jCyrPhe2nUczZn8Fv35mH9PG9OsGW54d0lf5iR27ctPOk48mBZeISk6+LAHF +Lk33lADqkiH4fgHir0S/uxNK6wdBqqSDxVceNJD+0ReKrLDDgF4ZcTytfziPIKJU +2qgc+bWiPJEvVqosEkJBS32lLK6SPjiBONmPrLTsE/DYKkYrcfmEpmYCDuEC4ywg +ZPPjCeSAjCj7Yj7Ky3+JMOKFdN98vY0YZN7NDlX3VZ5IE0W95iQMi7TCUdY7D8bd +/ED1TactGMNlMDykPOx/aUB2snslA2NqC7rHMrrXLIo9pps+WjqQSKpJt3bUkM7f +OAuM4URSePUqyQ+NXT3yKsiGrmsE0HivaratDGSj6RfM2MhoYscx3+GDLle+52GL +FEXYXAwFIU+KrjvgzXGj28luy8ZPXDex9B15ORmH5oLUEEMcmz/gTuki+BojjHga +6210vAxd5rKEVjo5bMQbJXQwpSMUronxaHlhbFKWtXPFhtIvM0aS3varaPxrJ0mk +mncXBZiL7nYGmKLyjBybCQu6ZDVT2ROHW54fZeRne9g= +`pragma protect end_protected + +//pragma protect end + + +`timescale 1ns / 1ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +MTh6YEb8fd47amN2cKNawaQawHld8lPdghxaCndTGXumotjbHWt413hSK/NgcsEo +Gnt8Whe7lgFMcFazYmT08o77uaPY9mP8ImzOr6doHD6yp21HOzTAKEHU93tMh13D +H7s4W/dTurxPSDUL0ipbZxO2VZAj35Pme2xieR4PHJUM7jBgdbYEn+Y/ioiS2oFl +KywnU98yjp1OAHaQ+EEa9TUS25IEaVNIOaiFbTaJX6GYvqIgtv1piLkwfSU3PyRz +bvLUm4CsqqlbZrnuxrc7aAru9jx1Yw+hae1UzJQEJRnJ0xdmSx2wjq6SvVT60BfU +tM7iyI/3vbP39OroA7oiyQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 27872 ) +`pragma protect data_block +yEFH9TMGaoqsZtm+eXDLw4g797WYufoCS6kxNzsb7PdM0sF/jwquUBGpjjNmJbHb +HZXjotlyenEI3Q1Ywatqdfzm/FtafBQLgtn2FigpJi5zeQ2y56edjPZdaVL1cOWK +hYU35erakUi8qgU5Ku72vG/8waL85moGfQ2GNmm7eJTwrlejtb7PcMu7vgPKUQ27 +qL3ywQzzTgZAmyMJ13MGU+MA6oGFDX6T03tbO0ToPLUcp2cUzLYefW6LyJsHI/7r +buaEEy58FNW28Z2xJHJ7gi0OgAUvMkkdbKx5XCePm3dwc8WVJTk/yjoUjdpUKZo1 +0TiCEVvrzuGzKp83TKq7hp+3QbrFWrjpqAq8Sg6W+DwGTgAeYC8rnHcSZ34i8rOv +7smiFfL4TdR5A/y7a99uGueqFWKG1cGJC30s5BCWlix9xdCngV+YZUQWZdznNQqB +24WoYosejqDQB81nKf4UZ78nCflmqO4Rk8xQphf9NZZPq6KsEcOoicz3vx0+YadT +iHwWpun714FM2IIU56FA3zX3rXErT1IHi2NffVN8yJeOhX32CzKiu1gDUmQuqbMR +ldDOxi7QQsfLGCZRjjhl/wB5WncMUoDWtwfFQStbg7nHIA9mNcDypd3E02OP6W6E +8IEs61k5LayOVUpMG/oycbC2/tzFsqnP+X13V+APgjEieKDlkO5pcYao7lMwGPf6 +Njm/tMaDABHFTWMcCp5St9ZtAF2sfsv9LesfYHpk0D7xEowxmor38lcb2xmQ7+ac +rahsh7Rg84O0LR6NlXjXrAhg6bYFuf6wmIQjb+oFKQPYBvumCcqolBqjqYMDdpp3 +9dpbBgg9L8LhMNsKvNtw4+Sep0jDW1Umd1/cTBxCCoqbq/2ZzfqyXzDoMgUpwFYM +KauE1n6AjxOnVjfw0ZNGVwujLYKejAXgqpcpKyECzgV9ZCNg0JtWkr288qoeF0zB +DFeZw6i77LEv7H+TU0GfT2XIFjur3JHlzDsVhCwpjBaOnMVNzqWYfCShpG6f/ZUu +HlgZtFSj9XUDCVHwMZfb/bGABdOBQJYpo7ZASh7gxzoP89r59hpedN1ig5eVtEQ2 +l0Ft0d84sqsTnNqEg1v0MlkZbLQCxCoPIjkc2Gh+TH+sn0J6frFsvcklKXOpi7A2 +eMEh5kGr9X+H68S11VS20RCKxaHF1YNeCCh4rS57+t3X8+iWtKpBTkWKuanOHfUO +0mrtUTzrSZcyUzDREipLYGXa/ddZIZhL5Yhn8CdoMBi7wETvp12mI/IHLoY3LRcM +Z00O0qH/4sqj6xSSFtieBVUteeD6g+755hbT+FB8+C0X1lT/3i0oowL7uWCEEm+O +x1DEEcC0yYKXtjSXmsWMFdDmuvoUDN1mDdf9GJ948mMAMwlSwn22u1WIBthhdz0C +EKvwKCzbILLS5HwjWJxmqAwocNkh0SZqYjynbyRtuyJ+b7XW8VGpEDDm1qtJ3ed3 +y9h+kYyxknUDIXu4fJf6AH8Y2HBlz1tRFoyyq3Hm3LOtnfMJZqIDbVmjnpf/GgxZ +NHHcluQkhKgQEZDcYHWl71bhv9pjxzHWQ1seuUSMWmhWXGq/P4Jv9eu7OJ7Kb84b +xAzDnHAi4gGvpykNiKGaeTk5MFIiP0gL1059xP8Hzt2tnE90pKGlFxEWjLXhWENm +6823G14ZQu+riwJAuBX8REBtmjK1UAAlJItnyTRK6JhbWc4TW9t1HRN1/H1wuqaY +RYQs1Ek1AgXmiBHO7h5EaGCeqDxjln4vS0g/7D0SwytAreSIxAaZWzwTufYL/TR9 +PGqhQXx5i6aCU5jKSss2Ui2s7XUoiRU779GHKyuMQNFpka8yE3cLQvg1ERdTfOAi +EzyhPM2aogd7d30B/DUAgTghXcBgUqcIwakwke6uI6ww0c7vpG2ojeKdg1xalJxE +/3wq3p3tfE0bBLDihnYZoubTIn/glWo2IaxlO7Rj1SBOBnNgfRg0GaDyE+XYysDW +Svbi2WJ4Rmt75vREDC0t3IQL2TdPx7jj1kcJEQPdHSRRHW41ryO9zAvBgvWjU3ng +dVwjZsTT95aunAzkwqlbTyvYlKnF3PHE6jQIO97cMJtLkbxK8sVMyfMAuGOxf0WC +iL502qvS0OGZPs+gG6MW5g0GWqplYXndyfmrUSEQ2btsnk+u6llMZAFgJv7s1WVH +c1WreJFniYt0lj2JZ31OQZimQHFXuz+yta3RQLpefoNinj4HKANnwtdtl8UCdarE +YrDoav1TFGuUnN929xD88OxFlnTvRQmLFlvTmfoK7LyyTvwH664/MxUNzFdv9MqF +yjG0Kspl15CTxMEUv6l2CISmNyvC3ND9DOS4dikdmagZdn2CW78H9ItDN2bMdSWT ++OdLJVFrSCEYKEYPnlQkQ6W+9eZfjJJ1XRSUzjRQmPON2HJ5OiZl4Dt/dfD08Mcv +7ttQIJztuFj7QSOSGbwd9RdCOl4NYPNniIsRaMHTrUz6AYzHkmpbACqsPRNNr4s4 +f5gwSig7LnUPw8JUfLAX/BiVd1c+mvWvYSmtEu0eoaQd3yq18p0P+xFq4LeoFyiM +Fb7/lNznINUxnR+ER3c7b4HS4PEMHC9B23krJCvLLpIZEcImMoKjJ6c44aot2P0Q +7kpeooViJSuVRKg+TQhtKY9H/FaOibhISvgquozdKDq6MhVjMZG1dsr8ZeY1wdMH +ehcHancUxD4RLcChLaw4E6i9iKHIiJGwBkmihmhTpfgI9ITVXA0BqWyOd40AxgIF +NCXzRbAtW74vBxBjGj4du1d3FoSfOYiGRydPk00d1icFbiM+NNeLB19Rw5UGB/y8 +lHOba6tB4TZ5IIv3yk2oV8atcDOgCNE4S7IqevaUdO9EpR088mnVy5gY1Vj/ara/ +0XiIFvOEJ0LkOnzFnUvn7y/PvkNA3xd8peqVHx2ITjH34PzuAJfI/HudEP5LDe/e +VE5AbmB3xjWqIi/oJwoWWB/z23FP/Va6lxiZokx8DnTOrUM9RfF44fGgpVlkS/R8 +/fio8qv9hWg7+Nud2A5luM7+z0i3owOOpTjdcSuEWdseiZbtdVUMKIjHro0D957m +BzGLhj3aRGtpZAfK1nrSGWzyf/+8G+j28yJxkkukl/fzKlZOn0O/z6o1bkQVKw8T +2l+PVMf/UgCvGMIj8HH1tsgCAjmbX4U/VnPZxUilq4E4uW/PUfArhsMXP2FeSFxf +S/i3zBptJzxcKFWIP2LpKZrCDh7hhlQKi3qBGkrMI9Jr4sRNTIVPk8pD/ZatzhEf +vBG0onFYIQqBCM/wfafmxq6xuogL5uT9iy3UAcB6/TfxVqkOm1YBBjapNrwsIKgM +uRRTIdbDdEW8vD10pH696XUhboNpLfLipRcPtL456VwjjQ1AGrp5SrsWz6RMapFD +opeLRhXqKGv7kGh2k1R4WIEAv41DSeTMaYpOo8YXWeU8+Cfzr2Yxonb6TaVdfEYV +SrtWN8xNSYAZHBUcwkbB6eVxJs8+PXErTGjvYeFE3s2Jv5jHyqH23DWPO41Pq8Et +pdKFgzd0z6qNOEWHqMyq9iW23+ox0i1BLmFDREDoSnXWuB+iKqq7oIeEn9u27Mnh +Y0O+kokSxkiXeziVlxNL/UWg4QQ9cvy++kFr150xInGANLRo7b3n/umh2CZZ7yBV +oPiGBlkThvSiToZv0pkUSopGnO5u2Lf0iqSFLSAHoWrGkhSlclhs/cvi2Eqt482e +LwBuAzfRz3MrzjKhW/hqydRK+9lc5fnP7k9/IwhQG23v8HMEzQiJ4ovXlRV4pxtj +iWkmSsDu3NnxJKi42JwJVtXNhycINNpqtK97ADpDL2LcRK+WmkqrsAf4Eq+1pm8K +Oz/6X3mSmArpy01RufL3a/8E5++Q79kGueFypFyCI14uLnVezCIVrJaN1KXJnj2f +8Pw3PYL/8OQcZNfWM9FZiaoDBHcTUceAaOY2vITAAZez5UCHxthU0ZoLcjRGv9uE +j4/P9lEjgZ8VzupiskQ3KCihSNRVrOInQtC7eE/TFombjfX77CnYiHf98IIT97/F +rRbfoZixQ7YEY9bhBq4sQDJBC4TXzdnX5s8ldKpweJ/4H+ME1MTYGAjQIpPqFcNs +niIrcAjfJPSJeL5CZnDw6SvVCqhE2y7SCjzGfLqipN3a80UD/alo2SFRmeSKSim/ +WfkqFY7LHLvmx2KQYDi1f9vRINYcmJ8Ygf4lA6CPQhsTzSbZx/XwvD3JhgibQCO1 +XYOKTKjyzvF3PqljpoSgWvXYVFE3C1o4vQBA8RfesIF3opOT+3Y+31J4GwaRwi2r +R28PMilPvtOCXRK99pvPGOxu1w7rDg44DgOAH5nVk6ekyxUBDWaVRcVl7pFnKJod +wqQKYXEL7MLFxDnqfB/MWiJ8k1ZzWidJUkFxovMnKWd/EgSsNXs9S1R7cJwN1B9l +ABr3uf4chQA3SE5tU1guKjVcI8Gv2FtCWH6UkCMQa9yqz3tLfwwzLGLIyHs6P0kd +hqcEpsU1wSQVvcE9iWDCUptK+G8Q56fHbkMsn7mA37NE+/6Q9hmT9lZSi+5mSj0s +67ZWWqv9BqTtvE70uImcYIqCNg+DoYZEyB3vnNiR5lD/B3kSrOgnEMTb8tRIi56I +1HnGt3EnRbPmYAMd0o4EIRHfcmI6m6Mak6DfmdB75zZWLgh+JdPeKceWY8uIb5lQ +7KF/KsR8oPD/nu9Ghpf1ElYDjGksS/dtEDBOoT8wvXg68jOM4Y56g2BlbMfGsq48 +o7oVt8LlZY+5vwHCaPkOvLpaTnxSt/AkdkeQ2FYgvrYoDAxK1L5mvuUYkImshkYe +eX3+YgbYzzR2Prh+gDhkHMKWnE3F1p5WI3XqhhWEf5sGxroSZM5a9JmTFHNqZflY +k6k4X4BQhviwF+huXizqTykrUgSeVlsh5MVq+My31pORpFEotTmR6lTzW0vz5IXY +8HGGLZU6IGl+Rsc87+LYd5MD6Hxn/gBlErsHQiKysKTIwJkRVmGJ3y3e7qPlmYNB +zjUuismHIRYKx5Wi3QlxVBpSJVjhoAc55L7BUWCPTzhj3UUIdM1rKvCiRVl1Xwjd +qIkw24Ujje2MqUVOr4AyuDK7MBkD3DNoTGphCtOjAPQb4M0ky+effH0lQhV8nACS +k9q+5XFFgX6+E9ONRTDewYLJLan9DrP35bsF2FzUGF56ULxfvW4Js5THySADB2yz +IvsnS3PVeDJm2RxvK+5jjJOb9YdW34hI/BEdErAiMWG5QLfQy28QUmJV4omdXOSg +hMnooL6m7+2EgDzCm89IHj855oSp38XjivoMFrz5Mg4nV8B6ry57ReC47xZ2R4ZH +PGgEZzbuAE4lcywB7nuwHQt5lkS9yBkpCZ8Fszub/M+ceCGmnrVA8P7HNq3l8qJv +eE123S9nP/VxeI2mgC0+qxvllKBNU8Yy0nWgED2LG3FWu9E/Pf3lORForGzVqyTr +xXlBQbeuQg2jwo3oIy98qw6Q2QevMHiNUHDSRwzHvvI1/w03oBf2lhVBWHFvfpBd +QEIpLXfy3K/e8PGtsjT6s7g0g1TxLB/OOiFv54+IZqU2Sv82NPFARK6zx2bLOmhV +FvEVeSrmURoxdCedNSQS8qLWeLOwTB2qfT4igFUWWugpW2Hhq0EoxDIm05+t1Wjo ++8164ZK8CnuT9mSo68uu+R4jjwD/47L3KNkoK8jKtdUdePwZElSjN4pvVFCCsFzU +1t5X6S41I/mmBBV5rrJCkOXihBGIyqNf+7WpV6f0hrmfGGtiXniNtwx/seejL/ec +XcTchSZ1UvdG+6f25br735g/PHh7oBAkxebyIg2CkUkM8kGSdS3OdahRbjw7Zvda +2nBAQR582nthCPQBHTXuPTmTlzZn4yTChJHtqJs4SmZFmk1QseaeZC6cbwS7gHqE +NZb1xmC+p8yHpt5PUJ0mmyws2cyb8uBmfjL8HkU9UmUHyDYqaXQR0KFJ00OQGN/1 +vulPyteY967aFqmEFo+1ZM8SwTKiNMd1J10OUs+V7VsgExptSjTAwrSP+ewfoY4c +LmGArLAArjeocmqyGptT6K7pquKa8OjvUtCDdS2NXhVJzyptOPca01c+X5xcb2m5 +gyg8CrGTA6roItvK25x9pZQljV3cEh4GUvP66b2YEORqkKXkKLZ1h/m+x8M+338y +sjehFyx5bKcsTrJ/SsGFE7aen5/tDfnv9vPlgrEc/FqnaGoZ0MrdMMIRe2NMfHI/ +GLDQLMc8XRt6uvpz3Yf65ncg0elFy2EwGnwtNJ/YxVOwrWjtzlPVs2WDACY5uHyh +RJ8UpgqFzo23mfjEPMwBGY1hUjfDGQagKj9oC6KfuZTQ3Kuhfy2YjXSQw6nf8bmx +RL0PNrYt4FOLkaWg4CXu8BAuIdHvmD8Y5KfSsZiT+0pTtabJE9i7zNf3lXgHQTnQ +xWEVx48+Hn9j7oJ1Jh1fNZaT3g//dCKlBslld0Qp0XNAWIG6OqVaw3Cp441/XQNg +k+o49RTKKaUrA/vXHXF4wzDsGGZ25V/eb9YQqSFvRtBQVS8PhnuvDLn8foyEhRcM +DBrnAHpEQLwL4xdWb3O5ifh4VloSSOJgPj9hkUdUpMI5eoQFuxGCzKeo5K/B6uw+ +7l9iS8KmQmkqm4ypMqroJ3qiFh/42bhKAiCTvIpodRM2W1Rmz6Cqm5odiGypD1IP +Ed2SVWamu2UK+mGtxc1L6x69IufCiuRY2wE+u8LiUU6yTXsvj4ZjueSPFN7wzvpD +HbDEhPQTSzK+CVX4QQdhBZidZU16Fs1yl45P3mefAjEAqGGbOcxFiPciNYzaZz85 +xvrbr1Nv/gAVuBhxfC6zfxGIDZHbOoZnlV5IYtX6ZVss0SxUVr61uyShbYJ+WRq5 +4fPON3Bf/xKGNsFjS9MmjcbQg81+sW4dIGaAh7zoERP+1Aku1YRHbHpdS8IqxIG4 +scBNn6EDMYkqjnBs+jgK2Z2TFOQWrCk6lK28a2Z4avVlvI2v1vdNJ9aHGW7GMiQy +NwW5vVjbn/WyFe4OLaunkf7/z3YAFOktiTv2E0bXu67pJXuN5AXSSARcrc5TlIlo +piRl05RRkaWLaXlX2F0geewvMsZ//PmN0+hoBHjo9cwx5cpjYgN/dfx1Qt9EGzYq +KVtOXWJ08Hb81NwsJIqLQkLE2J+6mdJrLc03A07qBnOqR0FAILFGxtF4TlyCTDi5 +GRfClYKoyKey98pZ0rETZ5a0Tus2vkaHBzQn819doj9SYIwqYgSXw5+/HI+uVPjy +eiAR7GQv69wxfLGa5Olk+RA2v78onDKcnpBMrNXXP3WPi3L9zGgZ15ieCV8phe12 +AnqOEkDPqeMZNkA9e136xjWkLiz8fXCJhjNepVwV/gGEJ5CMtajWd9YfCTRqo229 +MetsX+vKKp4qrfb96/sgTqL6LgS7+6Ddu/v/Wq/w11rkQaqsnsTPP7HbNjUADIPv +Ak4TbtzFrqWOVsxbF61iGkyalTTntiHOhaxhbUav37+1u+qihDb8nsISskPm6BhP +KQ9LNHUqEUY30v0Yy0MB/7bUr/J9+3LdK+j98LIWjDWxFj/XPddqrHYiMjUIaztZ +1QNn9J2ncFltUwXqguzRqlOcaHdIfGc82vUzLTdgzg7YbvSkBzQy7ydYWhvMfKJu +VI+dWGwEWtJxH1dj+YltPk8qQ8GS13WqBDKr44FxgbEoDczrl+20ekB1UuSoD5Pv +IUUhln3BtqmMnx7jknkFccSXo5L4R0qgB31bQXLwb3opBm5q107Eh9hC1t9rgvth +plbWclD8LwetHfTHvF0gxmGDvMWNQyQDkq0fKmVMeNGOlADVJQk3u/PX2ISfWrRO +XscL4/LFYNnIIUgrdyb+JUNQqD+4F6L4XVahqG7QZuWevwmIEcS8pqIudoVxr1Kx +vr8pUk0aVaNOz+toKze910vy7VoSVlqlu0lQDYQU3I+I+ZSljZ/CBR6ZxltQrOPA +Ca1rstKMIqo4ZIZRQRIgHQlbB4EopFlESjFMQfOpf/kIYmjl8kM+BjiqiVU7zqtI +tljIt9h2sqXdhBG3pTr9f+CNXWevxqOOSy1ToIJpOZdGmUEUBIdO3s5dwFXhnfxf +osoTw7WD3pxC8WcNzUQFnad6xW2yQrFuLRVIkHS1uNG16EId4cEziQVfgwyz5GFl +BqFt3kt/OXJ8sFKeDiWmbA3R8YIpr3zIGTThw8JoO60SF8k/wyRHWzgADHl47ogF +V+PGn2dSXcAmZWEd+nPhTKAWHY+OIvm7IFoYnKlGTBeWcO53btW/sBjkek3+Uykp +S4BxZ3uZB2obhMa7nHLC8x0LcFeFOLBHQO3BoXxbM4hPlHsWt64H5SGDb6e2A+ij +pX5ORnv3NzQC7wPmjk+dbGniuWrGD/jGxC5n0/c2BxKVNgMdbVzD2tfzOlVJ7FXJ +97vamemDJNa4JMpAy9pCyqIzmXVXSXDKVydV9fDhapC+vOWjrhiJhKNTFxnUC8HE +pGJziUoBJvCjrFoOrQQ96eBp1hLDrDeaP02ZXh8Kz5He9VdThfrczE36O/a1b/Fn +gShdZ32O6KLw/PQ/02jZSBktcXlZ5qBZahKizds7AUO2DnYqGEUuZZCAR3C9f+qW +m+pLd9ZLgUHvcRtUQqa0Lh6TUut7KXSxZuuSLGJO1+wUjLcfPTc1uzOe/oL8tBGv +nq30FrpyXxJl9O26qESx3VSgLF+jsYXTa0WsOCWL654jGUSWVqbYch4A5/V1uiwR +85Q0HwwaQ5XraGjjDlKS2pmwmu8cztCQf7eZTXWnTvitOWJHymIU/3XmR/yhdge7 +kGY7VhgPaSSm7OZQ3INxVH00bH74uJf9uBWIvuIs8xLHAHCCbjdxsZpHdTKSrZYF +oa4KMbAW3WiPy0mZ095f7UFQa5+Z/Wput03Y0tBqN1yMRh/QzSQ0LGMVOoLuV1du +NjqxQGPR+aELlh79uw/zmiYgd31NPNM7ahQtIquBe6mZu4yk+dkI7roSOU4+GC7X +A947GIETz6QJlGit6GPQR8Ui5dQk67L6tBRIb1fEz3RxYoXEnyvHQvrV9AazVcYT +xS5n9/TFhlWX7rwRln7i27SAm/noNV1l1oOm3uQTmyzAqzzzxXvu07e9hDqB3X6t +0YjfNQHXBwcg+3NlrPQ5kYMe/a4R9PGVudQ1w3GvyyWIZ04z4Byu6VeJZTYYRrTR +vnHAFe7zQi1b3i6CWqvWvLH2tbVZ7zOp0IhIax9+vOglyu3HbST5R2DDuyWoAdLO +XFa4x6VPiYMq1sExi3lbRF3s98VSSfSIcGGDNswq/YemFtn6VLcvelxGObRQ/Qc9 +QuvIq8MOOlEOgkcKpX85uc3vSTKoj7zg4AJjoO7YqPLQsdF21RXNCCuTOCccV4J5 +ug7O8yCedNiyY/SvlBKYyn4m1tU1ExCw5ykc7b9HbT7rY8fkodOU4Htdao/iLUDE +ZzG4S9Tbi1vFKsc3CucUbhj5C9/XqD2EsS0vLV+sflnxRBD2Jovdd4sNaErO6H9U ++s/25uYtdcCM9LBA/Nlarw/wMyt4UUUIDt4O5ngyTB5mee8P54+2PV7MgoKLI+Ix +/e4YLsv7CDBmsEdferAlmSeh16pt0BnODkDHtGoAlJjFiDJYo1gC5UjDZft6WmDe +a/c6BBDZZoGOt9FMWmqEn7gCiDtmvRNHofquXcZ59vTUhLQTQ/7ucYEGeI87rtD3 +scZavWjFORgP8Vbo6KiNIYnrk39/jEPV/ixXbxPvyr/+3Xqi3zWEyRrDVqFeFiYl +TPhIMyNIAr67DxYxAhV7SzkDpsnQjgrcshl8eP7THRPYQwkKQ01WMc8kMQswOQ63 +xzW4tnHkNimE33gg+JLf7sTCRDFGaZ2tM3FzSDke6q+ElULDjFRddvhty1Ll1Grd +/nV5fOSBI2rTjxDD71jtwCSRzD6ZzbzAI6RHQJVjYwO3+BaYHTpihcZKJDy7vsxU +Hj4F5mgUS7LvVO7Jf5fD1pqAdPqo/tag0OZrMyhboIAlrz/RbNx+C2KKiEVDwkGC +2ZWbu1HHba+clc2f07nnPPngN6pYttF+zYHJzrHR04Z94lzJu9zSLM/Z6ulcFbJi +FLZqLPNoHELUMtiJRIF7/Ou9l8f1aw1/COWi7VG8JvJg1bktEfdvOUeW+bCMJyrx +hBhhPjKUBf4pDfuYtD2zOukXJ6U5w3fd10C3YTpanbYEsst0HblEIbYtzFan+Ufp +cmRIiNqsEwCdLhf+OpHsC3x1KyWs0fx2ZHvQ+PtKX4CYB6tmVEYI809fz+O0Tm6A +70L37IJ1VZaskLoTaGmi0JeaLBmGe7VzmrV9qRZCZDTtB29bCQd8pSWjJ/4JAC2g +hiPhjm4fjLK3FyTfXGjvNe3FLgxLc7X84cV7K2qEVDkqMdsZJ9S/YNEws1RO2rFZ +MqlkbqtnE6FRs3tKYsuknIQpiFvR/yv3n+F6hqz+4mT86p0skXbb4ZP8PPhN+UiC +FB+acXG0+kPT5jb1KbfhN3U/DTsk++yzR4jL3hd9YxeX9uVFY2C7U0HAReMSgnm7 +ixV+K1a2POUcTGUwiqhrpvrj5z37p54U3r1eMh4Vgc9ORh4jvKeidq34tKRo2Odz +aEJdxb/+Xt+A4sLa8ERN+UhbhAXusIbKhNJFRXG9X5xcIrX+y96zBlxn+Uk41JDo +DgISumubf8IlWBzWANx4ntev0ec4/mrqCKHAiHk6vGgowVUloYGNSQX7EydgLo5j +mqEp45GrlbECIS9jrFdM1GwQ6+WQc8NYiIjv2H3L4Raazp5cx4I/HHTLVaXPJnq/ +57RzGggyzWcNeYvk8Rim8n7p9bzShQF3X5xIv9aGMcFNM+oa3jsYKjzgZNtXoenq +T9vo9aKqjnfb//qycf+R1SHO8IkF51tUFwa404DmrTKvNw4yj48xPdBjgeg4cFx9 +hvFlRRz9i9CXptlNyq13rDSgoQQUSWgU1a9Yq7Cfqij4IETRcOthPzNbNpP8IRyo +XHJ8CLiQazj8Yu+eq4Ye3DAiHKAG0+vBj3WkMuyJyU2m1XxlSo/L6qtTVue0jwfr +cRH6qma//UkLFjrYvOZOiQ/9cJ53AJ8PnGbMyRx/ksINtY1kfO19p7dPOZvN9Dri +eA/nQsmaivzIdcy1JrV7/hjQhJ5xvrcXrSeJF0fn7jE/Sv7DwFVBPmqZbSGpe0Ih +N+RGB+nXUfJ0tcIcZsDS93scGnxEOD9a2mmH+GrJPom+huiH4znxnDXm7d59ALf0 +vDH6V25hgVYwZcv8aizGzp5GFYoaPKF5chIbH+MghdvYIiThwG8cC0pBZ+3IpaCs +SWEPksj4pvojCV19jhveN2+BmgF/RaFPEecR1NK0SV/9PYhstNfFDvwaPCw7p02L +LNambLkQvcWxzWkTfTPB68GgZK4rseJRVJMpikdhmXRFEWTlm9gBlLAcryxEmDOD +YHK6VfrX1kR0w/YRKTLuGEfSSSyL3pJqzcPA9FGpKJHJadn0dCgepeYyJjNTALhL +rESJNSMHGhi0Moz9wjUR1N+EDwuUIsIJPU0GjcNdmPjGGIK/SIQduIs0N5siefnr +pH34k3oinSfucRhIy2AnrDjfeshpyps7lIKgdZ4yRHVj1hKXCo1vay7Otc9vNMO/ +EJHKbta86Jlq6WtEV8mmFG18JKrrgbI2+0qm0F6lpOXCj38UTAIRQSk7teuQf72G +gUlKvOpq7cOPRB7YUA6kmvrCP2C15gHaOSTwojz2M6J7VB0jCmKSh9neUgJyzpYT +bnAfrISKOpeVHVV/81gFyjQu+Y0b5J/DUyqEyt4BW3aP9zq30CnB9VM97cqBtZMa +QdbgjxyNVtSJp0zM2mjwCjy3sebE+uqYcdp4GN4so4VjPsgiIln2skX74KNTGHFY +/mHbaPIBo3w8mY8FwM1qscc7Clclbr7yAwuIKqxxIjHsJCMYQm5iYLC0V5gFIGsH +ku1H8r4fCA9gy3F9RIqVF7+hhndUf24veLubd4oXCLwjl3AdtF2FD1c70ZPTPJ84 +/nZkg9izOASQZ0sJ0WhwoUbvWnVsnaBibryM2SCDpJBQ483hVv812vDIGjlZMZQr +lLup77BQ+PCMlnHbs5qz9pNx4I63jtQflCYGWICQrQhsL/+x9ESfOJOnczKqJkww +05bUs7tMkV+ifP9ioU+y65oBUKyxYPPqGeOgBLarI3gZPpAult+5UJqK9fNCn6O/ +g7NXBvLUntRplXT7ch7VAsj1G3TKU2JidW+u5ZfRqugrATIjB3aORllBvbD+ETu1 +m6v4Wu65GK+9uQVoZr7RKcilN8liwlgXrbLqvB+sMO0m7Vo1Chgc/9OWt1RFcb7O +yL998uCH3ylQi4w2z/zuRRUsqLVGm4u6QQslcan2TpMC1dO0not6VQ7BFrI+FZJF +u7O+DkF5QZBCDIWkDqlxhYk8hfznkitbiQw8As4BtoNmOIUP/XzPkr0n4M04F7TH +3G6k9JjJPiQ5/PVwLt7m7MkIODbLwBwdJe1OXpyqVH72NdHFpmhkRAnCZPC6A/4T +DM8yBIbvCjsaWUATp5bVGUrR1DP8zBQhFSvGLYAUCMQlqbdUTxTiMih76jt8I+ei +a/9DVKD7W60ymNHob5thjXRiQJ4GYZP1Cwugz6fhc4F8e/btNUVIzuNJMTRALkyo +7LHV+WVEa/Wd80/QnZZDWXv4LbpXhK5sa9IUkXWabFalmJFmIcfV6+GaSWPDWT85 +K+ArTH65uyN3DZ6L9HcvROPkk2jNHqwtCJAPTvQSdhSfxyi9rUgJFm1XwFb76vVd +rOZSmz8cDpK9zK20vISot5XW8nMgrdyLh7XmV+nLt3o5gOTP7jAiKleB0CH+xYgs +hGHjsvMvRBlp8pzg6GfP1DE+2uSFQEj83rbtKaL+AkJpOSJTFNordwJZ2hjLS2Vg +WBMfexhfBij6+s1AEIqxvhrmDCrLqFxrvSIDPyt//O75FHOhWbpq1OPNcuJviPaD +4tkF06m77nOZ96hJG55xoFZqGwECxUJ6kdFoI+kKlXkqVntY+TvgzxpctiulPuz6 +meRdLjJgTD8zcpUsAcV71zYydwiOw5bHCs9BVOS2Eob0wU758Yq+coQltR1pqL17 +8qM5gfi9Jm3t7+HoKo1ahydnHFjVIG+xmnIvIl5oxSFIJtXTqmbkThpwjYwZ/0Fq +X4gm5dO3zfIqaKq96M8GtuwNZcYOUCq0A4kTdWJw/lZs5XHFuqsD+HiMfpJWEq7X +SoW1jUk5qa1xbBEw2buGAOMu2RKxtpKLpibt3+RSrYZ0L6WDn9wkYuXVFtjANCwi +QMCJdNlvIv/3uVfniW2QaqdgS76VKZIRhi+MJ8Sa5ojg5XasmaQhv7uwuD1ezSvO +MHlUjw8G+pgRuV8Jv5bcR7l+Jhs1g5GFVd5NCZ9eDVziTc3huOBF1d9F9run2pjd +8NB/tqX8asi4WN8+39nxb/KUYZfexo/xiSfA0ktr186nwqVsMZ+k7EGSl1fPjqzv +ujJLNPyzXM+17/XZ5kTH8kKFpCd2aTvWWAM17eZli8//vi8+Mz3rp4FunttuYVek +cU4koSNJFwQzIAUZCNCYQHGNrkPFlYIDDNqkDyqMMNKToXHbe32NkRr+1x89FiRZ +fO5wpGLQTvK27AVqWmkOAjoVjedaY9SAyIbkdL3KBHTU/w4Ofp/MyPGOCB/zPUsz +Xyxi5iw7uop6NTJHGIGYdRc1RX9n7dEmN6dDJ3U/G0AKT68O5nVZANnzLVomnyrR +hHoNsX9QCNQtcE+RQqy+59YThxM92y+cLAiT3kPZkq+zcBQt3I7snUt9HINjtmzI +4DeS71DgybJnZCu/u6FYQ4p/tMQZMHpiEyfOuE3fhhT2UOynmfuv11GVkBAvlsbX +fO1jrirED5qe8wL7q5al66GgEXuhu79QlSQ9k/GwUlQau/Gj9O8Zc9ORM5aZghFO +B8mQlZgz6he3fWC3qsO/69xjr9zMWjM6nsQHsanCLghC2BbU6gwrXENY8++Dki/R +LdsD0TsSoUZOxIyqTacONGbElhyNcMtzn6GL96E74yAWxkOupOxgpNu5vKxU6mcX +TN8GwvyilLjRA7sBXlKwJpBk5LsjzwPCm1LO9NGyBQmhGlo2Mdx9O9+YeT2/507H +CdI4z0e8Dbw305ftnp9FbLkWWr6hG8YYZ8Rjeu8l6Yck3F4GI5qfzOedIWfpU123 +tpXbae2BTlqhCA4QXmPmEYY9lsGqE5DCqS1jLx+Da4fuw/JrulT8F/GYrHY7x7RZ +aRUrEJeRP6Yb+Cph40ss9GcU/5yxGRSosjrqw0nid4c911lJYUE+gQzgvT2aTrVN +9fy2Ql5bs1aO2brqT6GJ+VcgfQ21Ai/XGQb8jBZLyKjL+LR9IPwNnYFwuvG8sik6 +9t/NKS0+cykJDmFMZJDZry3xmrgfwb34dn87rkM/dgqp+t6kEdkh+78YIqqGuIyZ +7WQ/Gs5nTM1JcUHX6m88f8l1Vh+CkS5JMHvYgZM9LT8kYiZ6+gKcWavdI1t5CDYv +PkBvtt1JXrFHjOO5+yAf1lHZlC9SP9uKfhabcj5Ljo9I75fO4S6egSM3GF4vzwr5 +/P6eydlPP6s8UTnt7gEFOiwT3FfMpGOEh1IOY3kkwc8qERzkFeE89u5CYxAHJ418 +U+XVCWJnkVcC2dC2fdwCEwv96FCxwE0xix+tytBfsXYNObOmy0bv8lyglhFzhsIv +ifPg8FIo9SfwJPpwapq0D28AjDyb63KLjS/BUxpHoT7GAdRqv6tEYDvKZTkmDOdo +RO03PXSz1z8T8aBJmHDH79oasRwMCGSonj88R8Iou8xFuMHw2YBXoLVKGofdVBRV +BiRvI4007ZwfOYx6AOTY5nEfvnPVMaLIjC6pl8IKd2GLfhhanYh9bGFl4Ua5l8LO +KK7T/fJFSA8DKmphbhh5PmTAMd9jVPcks+nCdBGeQkFFZ39KZz4jLABTEXbiJxKy +JzdKpfppr/qVHKV1luYwUxodAg5RmKgkxjCqPDkSh22vHczcxf9haaZm7KqDu5N5 +LPzHtG15TJUo7oXYGA5+pKP56sbLvMZ8fU1C0xFasQDP0yrEKL/austbE7U9w54q +YJy2djGPNh2e2QJPOD253IJjsnxo6Z6myGkRwofyvMojdcgfIwoG5FPi4zx7VhZY +uNKX1n1QE9L991RxVXJG0N/X06HGHMQ5NhUGNJ2RSUGDIJXpqAf6IB1SzYrXmPep +oBy6CAH+icVE4ooxv6ahAkymiuuGMsm/se4nNko9XFMir3HNbjkSLBFfcxDZLqEY +J+Sa50GXllr6s794wK1sQyxL0pacAD0Ega9lZZvKnqbpDfWB0oh91VaWZII+K+8s +5DAwB83/nYArk301JQCbETZTJ9DKOKpLjegX1Z8y05/PBs9SnNJkqMBbgj138k7l +dS7BiIlrq097LJ9+lrPLtzO5czdlhCeh7hoAPd0oTr67nEeraTRUDG0w7EaFKIdy +cLJgW6ShIJVEls06TR6UDJ+JoTeeGWQWyZYIXbcQs/EmxQMeAFlg6P3yKIPasncO +NST4DnOZG52+n/VyLaq9+V4/sb/ownYUyQFG0lElNDfHKuJ2VNY32OK7EzoWiezR +8bMuQe77nDq5U3u7DY59jrnsqoQy75q215xH3mke4TXewGMcrFoFmD5fdAPwugPn +WnFQURVFu5kHbM5T+sokR7uds5D+L0WkL+GlcjvnvxTXik38GCWNHSjr01z+XOE3 +mdeVIqXU7NWuUzJxlM49O2M2vdvmx35hB1Go/VtfaYUDjOeJ+R/CZHjtVbHSz5FQ +dIJ9sVPhtMVgEeWP57s3S1QPZUxZs/zHr2qfIzehYXw712WuT2qbHdgMSaPdTszF +Z+IhiS9ZWjfYtnWtV2NeX4/lGq15t2Z+u5Ju3gshE3RM+FmvpIx5sq8Uk6yzFQue +Sn7Xnu99OLLq0R9jrVBB9c42t7NH2xXmeTbsIhy461M+EMtyyCok6B3Om5mm3FkU +A186AT5m73nupX0+KCM9pMGqplF8hh7zf0dJKlD5y+K2CCiGAHn8ER2XlKf4dKfR +eBlDtPVK9KxW/Ak83aT9m9l3/qGusMa3I6ACllryAl32ZISfGZJLv/Xnb2EvdYC7 +ZMmH/73ijZ7gNDU0gMg9I8EXLGbNB2lT7VNmRsUzN6eny8+tS1MUUIYZKlt7iiJc +5Elwcsh8WjqwlSxD/Ikgc3ktbgB/0crlXV2dM3rTqe89ydhKf3dBVVPNXmdNluyN +o3z/Kb/4YCxx5quoQ/0go8JNtOHOI6HCqvNyEOAVB57aXl4bKhU/OZOOpblGKMqm +LUSWqBTsoDwp2RWlFvQz24EmEtB0g7FJHGHkvO6MrJ18WmE18TwM38dQqV7XkKHM +jIjJvibzIxJD/usEjdIR94IvSUxC1KXjTxIO9fm9zCcbTqURSsp/dVbSKchbxQTA +fg/1A0PHGqbKS88RRAeiW43vYRvh8uHcl8Dh+GP0AOU4dWNUXQG2LaPG116n+hGr +chf2maQk+SVNrPHaZ/5Sefx930MbQWUcrvokvTAPLZsLywHkYAX1FkeIcm2yhhf2 +WNDrIRTFyicrd2D9K5ljDMbWydMcQAPql8N8MV5XPuBmX/Y0MblUVFao1Fs4WR1q +/28SFC29im7fTero2a+u7rvdDiQ+IGJ4DKJO5jmvaghT6LKEw89NFj8f5lsw7ci+ +e8oXALOhMMpIyj8xWNI79oVXTujDjR6Zxy3FX0+OtuOnhMtvR9TBsbNMtqsTUm17 +sMy901/XtiQQMhU/sYlghvSsLOA1VlyMJJ3aWSa3768s0ebmGTQFICD5Wxl7epfv +KtuwRnFkoVtqdHb1+/1ZyU05wip1JHmbNGwSGV3Jxl7y36xZbwj4c+PgpA9ZMq/F +5ImyQ//GDi7e0j4SwFUehRwPUiwkpvTgKVWJUovjZv6gdqpg9K5YzoTBggmwIMng +gbKLltab3ufIzgACS6UD2+S/R3IDlZbUc2YrFp7gIMvAObS1TmPtTFSrWfeVYoG2 +74TxGEDiZMwiymK9A4Bl70FQyeGFwhG+ul/4ud+7+A555jrCYCeqqCzqCCbhFZIF +wX7zMg06nclF4Cvwo370MQseZHj+HtbBkV9cE1gQQsQt0Nmt6Yuic6BLZAB5ReLp +iJXiJkSop4PgmYzAsbnc/jOPoNfSz4qiGcxCbHFtSY9XajiOV35Wloqw923QvX+9 +KmF/elPJZHPS5mcsBTuumIR8jKWUb2tZyg5TTQC+Zgf3bMEeu+f0vd/MPfAvA18O +soX0wfGq0yRic0uDKeOArseGczQ4erePWW1CvWesPKKVKWsEMDOFKXGmN1SrJ1M+ +x+9AEspHhab1vqBkHyrHCVfnMIHZxLvPjjIdRncL5aA4LxJsIRvPF2It/e4Pxkh9 +VSsY2ZDW4684/y3skv8OM4wwhtOEKnwCnGLf8vfRhG/tqqWcndY2UkDalzTC7z9y +43m/iVTU/zYTg1MRQm2+sPkYOY/lasUw8nGYKAiNR5hBkgWRWJ7GGlP9LIDAdK6K +rvwOxbQT83oBYtMF7uNK0r/rRlrNTtQ5WHP9qN1N0Fhoof2UBNu7Pyik9IT1g0IL +fRB4ZNHM2uf4CXMeyEJcgrppGF5OGlx76O7QBbecPb4c5WJZgkeETEAJshQkuNDu +BYB1zwLvIjD9sjkbrkvEf1iZXsrPfRiBzekTpGnhJMbbcpOu2DokTHt+uXKHQg/o +eZLhbgNTOlxgEUUHkWAtIHEfsAXOLM2A6SSA6IfziVG0iV2aPxzx3yjKrm2xeFgv +EyXRWijsGKa9+a7AFtHeXuA0kVNciNJl7yCf1KUL7dseTpCoWVbMYvxDBU8NLOFw +xrfLhK/DiYJ0ZX6UEqXn4YOx/Jdao8eR2NGOhSBdPR77V8zr89wXjvhv2bZnThbs +t7uEb8lp4aALWUOfYDUTz4378eRWRtt2s1p6LyG8ssNMR5p7P1l4R+f6EO4znKA8 +zt0rCXf+fz9+a0P4lVgti2AS1TtpGaIh6fTwug0VgCZCHRNuk73tRvoh4ghA8Wlb +u3oC1/h4ed3uiDKNZ3ZDogJpQcg2+2rG/gW5n4xkJe5spJcFRXFZe0bt862OYKQ4 +z8Qu5X01GdtzxLQnzcujV7aETP6fCoGM+Q+bKBDzHGAYnW2cyQIHKxa2CtV/X41U +IYajGHOICeOLIujsD1RNvAuTqAeCeDNtUo4KI17jtHInHD2NgTePcFUN13ikJKWt +SHccK8kuBk4YetGuSjrsbBmu0EAjfcbMzomwLXjvkuDnwJMzFcEez07GRrjVcriZ +3Y9POvidgOfi3yhti12hwPI5qbq9iLCbBFRXbre1aXJDTTo0of4jUJN04dTOW5qS +xQck0oI0yp4kaB9CQkhW1JHz4UIkgGU2T37/GPI6+b5Osn6KsYZHgK7fH6Fzi5tw +CnxhcldgB6Lx+Xj0Lwebb8i5viWnyDkFxM0KXNKjW45+S0bzvf4jwrWnsDaPYLXx +NWggS4NRchAJhmWx4uY3rROvXzz/KQs3SmLrdLJUwiplDtIdtOjUIVwHuJanLWmu +n1wDW0zlIw/aPd0o0dTiStAbmy/vM17wJuEZtq/urjr0GDeEOs32/NwA0a/nbvAD +g1xZjtMICmi+iuTlKp5DQ7/R9IEJd69p8cExWNn8qY2oHDMDGfhZeo94qRnwqs5A +Kgj2F1XmvJegzy3dtJJq1rQhldnnuPb4H6JcipeEEuhBG12z91FhhHJz0IMlum9R +ne3hw59rfFsiZ3derGUXW4Ud7TxQkgltHA+KPeI/7mIuVF2LkCLblY/qV2QPQUeB +a1YEBpea4tTUSO/LU3JtQCJccgj11hmu3kdIEy48H8CVJ1OLP5MOyuAQlUjvFjNS +0TNNYr/zt5knGCOMC15/SQLspakPX1Q/XhpjDG/3nctQhHSgef9YZ5fhjQcQqxCs ++yAFHIA7O3ghiGKR/7aqmSPUzZiWGs6fmHzIYxuCiTBsUe7wLeHvR8BMb9Sw0UMf +5iejX8uSoknNIo7rjfgTOfEKdGtGjBl+MGP+p0ZFgcTg2EA81ER6sNguypzrqspB +RUsthIZuBmx9cQRvKNz/QMf4E/W0QyY919EviTDLpyf647Q2oqDBbe+w4hbrJB38 +hZqhYW41A9oprq+PEdnuB1+2kxAEz2AOSCelXKMrplMfrXI/xDevXiUPQqakjKvo +SY479yxL9c09RO2uDw7hNO9pjA9x9ZuTK4DDwvjF2dd+1SekjSU8YDCnmQtwPC/n ++tiWV4G7l8MYA7xR7wSKIQVJOV6/sVCpGv6a54LYpjDuzqvvjMqy8dkMjTUtqptd +9auD4BtTBU2Jx4K2raOR7OwW9QQlUScucjNrkmMOjT/u+XWkQKT6QcUKK0SOqaL2 +u87MBFviE3eCD85pxF8Q89cIv1BetTw1X021z6ePT8YEiGB6+yI6UX+uhZM3ZAIR +jMo0ax1tFUxgVqA45hRqqcnASKfwiFu7VVowGX6HtK8KCp3n+T5+weNH7w3ZR8m3 +jyytNkPUultez0O1grcHnTWlkCuFUGbjvPbgH9V/Tb9LqXPJVBW+Or/ZhAUAQ+SH +L2XmXHkdyFQU8OD+OvpYcZYNBxY604M9Hkd2jfmGS9myCRKhZ2EVqW8H8Dka5zMZ +j7nLEKDe+svFkeJODV1NDQXkoLLh3ltlMyvX39D3dK0bTDJYFkTqm1y6HEr/SNrw +2iwwJNU0sBvfzZ/q/8JZ4OixL3M2fSbEjUc9z5EEFauyPQ/GYbaghjRjJoRYaXhn +quF5/vFlBHHQdSOt/g3PfshYpaYKwIcFJQ8zbmk8NT7QoD61MCe/rn9H9tazwWOA +1dbgtIYMcQy6KkRjrodNVmwUfP5AyEbGss4g15E/7i5pMrYpbkFNpyHm7c+WWo9d +uWW0YR570UUo72pJi0F8xh6kXG3wzJ4WcL8G3rfRK2eO6ou/yC7z1ekF7oHi6hPH +Pwf0jZ6DbBBsbKWX2fpnvpn52mTcFrY1Q1FauN6hhnojzJk6ICTSug1aRud/U7tn +5a3B/TvkYVp8iGVa5ySJTfx0GxXExD216ORHZbaXFVa7yb/nX36tC5cQi2H6afrX +4Lnl50ORTMPER+Z1eLTnohlTEv6555jTe7yln4cr0/KBs2ccHXkkKQjD00xineeF +IdadMY1ibRmBJXsw0AKLJxod3SVWubJ+3mvIwUsvkTuL1wqdsxjpBZJPsEPVtVZ5 +0yHyAHvFjTCZfnvVy6DdwwKLNLGiMo8NdFHE7/QIjLQtBICn9Ii/wiT2jMzkGM9a +Et3fYrfvRYbnPwwc/u+jkwQUJ0E1L/AK/ITrejU5t5cELwHKaCuebts5UusCB7Ea +egzWGpJFiSSiAmkOkX8eHYFfkJN3NUKoBkiVTKlQfhQnYqbrW93qehkZ0XCYMWL6 +Wke5B1TUa/wWN+S3+abuJ5bpfoL0Y7WWHTA5R2IfL+1jBj1YPP00Ck7vcVaxwTgR +rQXrdOslL7yE9DsLeO6V8c9n7wc7Dtcml8lwypraRYWN4leKdOxzvVEmQy1nos75 +Em1iFVQ77P5iO09dzANv8i+3XGj88BMz/FyU2wZ1xdDiclxUsd3FzBTHezaD3AtY +9n47GVPKCJcUtYBK18sco+DlQ6RJbqLNZnnqrDBNNLhaFOG6J1GtRCfQYe7o4PkY +RIAv5zueqGdWFoti/VMjZKpMBYE6zPi4gYjsMlnb/le/UjzGSxRDCoiokZZF/nGk +3JDF7kzTLtK0rSO6wuBjr561eicZtgYFuDlqbxBNYfiIgXX1Wowppko8wkRBqSfF +SLU0LEfjGEJaTlEPXBhBROQR61tqSNRFqic7pd4TQNbuawpLCKazS7ondypvvwip +vmrmPzvyzgI1QBfkGhCLKG8F73VptZQ5waMcR9OvmB249fGQLARB9cX+vJlhOQGx +m8XqlWndXcqfUmT8726q7WeqNPnnJs2VcyW54vmF1jx8cUGd7/KYxFMePSks2ZcS +hyiOPViv68mSCddEUuXMeNQcUmGP6f2cqKMeo006vY509uX6n8WC9Iq7OdHPO6n5 +WUy0Q0z99CmrgZ3NJUymaGAYdpc2KT/dplILwLTdtCrNCUm8NSCCoOSJ3OKKGS2n +iQ3vvM30oFMVjYz8WRCns8wxNNLzAhAwZbYcM2SvyUgtG5L3b5iqtcvdCu3sZ7f8 +X5rhVa0PEFOUWM8V3zx16MjdoiU4BFhh+ufWY0TcDBeeGEIWPNrfz00xwQ8fK4id +ikOgWmYLlcIUN8KbeMVC+6nPK7sQz8YTodBlnCP8wymXEnLfL2eNjDP6Zxp0AFqE +x7OEUhYo6i/ENI/V4mcRRqqYYssoPkcGHcPxWwNLqpzV0fRdSp0F68sFxGOE506O +g1/1JhrhkALFeuK0JEGdF5cDuEJRKjNr2H8QXlptUWZwFUjz+mLNC49PabNDnuwq +zq6UEuA7HCgeFyBRaC55worzqxSXD8l9AATZVH3vp3Y3x7YrFm8dKca/bRQpALJk +B289h0nTYriWS6FJYbELXyCNFdi5bBaiaNZQZZHOzNxihFCZKPAQZMA8ZhK2Tzev +Wvj907SaqIEM+5y74K5Vw5ZGADNV9ckv/uBWZa5w95BLLmzJf607Nl2PuSGRGeA1 +N+PbdajCbmmlWcNlKmNikqerHJtVSs6+x+2XjdZHHHpVUXote+kOZtU+PndN4uth +C7RrzjDT6YLWHqPvDTKwQ0YzyB5zYimhuRvSg2k+ZxWn6mIl4aWWnW+qBDl8PdmM +V/WBhVmkhr8GL6+ICRIecLZtwAQ1SanBkjsfTIAmRWdH2Y4X16s60eRyn8OpzHkQ +U/QTFH8qXR8s6hVbqBCUtGTDzuUpArlrz3qttniGmdzAmVOSarj3JMFsOzkODvVm +gaH8Bx6T5mzmQIwz36tsD/KTgmG6dWTZNcMABSEVk4sZ0YZM/mNW5//Wri5/qEnT +soYqXMnhgqD+6aVERvFB/RJvZAxc2VLnGT+wZHRI33fqiIKrc/WjOrRJyfNWInzb +m6YfPLPlFQGWmqaIHTyjbscf+yDm5Qxb1BtSreevtSqLyzOnyJw/FYIDoQsGbgFo +nj8Hvr/bIa5EnxPLzCXhSxp9G9NBkatxfhrfUfG2gaptreWukE7SjzXM4dbYXZV2 +8ehq0OVnfvwZpet1ohOvjhJ2SjMSCUGMDwJ2K6npDXpr0hu7C45q6vhJZlCklpYT +VvBh5tdFgmEer9xqQxnA0lcQ4S1zHfpBWR5o06C086is9IxwPd+hwcPSTGKHV2iS +qtX5UcJ1JwNLdrvk1aWp7ivCoLMc7X+cGI1sbQrk6S4sqtUvguTqfAHSiK7TK/vO +ZZZ/1HYNhBVkqbSnAMM67ek2Aw1mO+ZUixYAIV41n/57MT8yQ0HKZVtz1mzEsRjs +exIz0wCgC8Fk4CVBK9UsFi8jput8FbCVYYU4A42ABYOJE3BuRmX5I9vjWJSA3WqD +UABWy9bovRDHe9M7GtT9fBAjpt6uRDSWzclXFBwyKkOgJbmzEuHbfJxWLJHWBOmR +GJYCGoPrkta1EbJbDzWr4uuQ6ry6+L0KSEuAZklOJZTz7K5S10bvKw27v6Ns/5Uc +A1mjvw24DpGrrEsXz2ZeSA9qW12vr3a2S0hVVeD+TG7AJYYMw0uitA94YSRu9yte +1vAB5kJeqyRlhJsy4qfIiQtTRehh0SVlXKDQivV8+Ju33uXWSwOOdt49VZ6uDkiW +Ro8S60VNoiJA/6VXiI/lChc0dhNZAhUVutd4EyFAuC4fXLpqfpcro7KaiApqdVnL +jVesRkDzBQDtkw+vx+q235r+MIPwQft+KCcdSuLB3aSsqs6uZhF+FELz535YXSdb +7esBA53NA5UQ9jiYGDkbfuQIkg1oXMUJRvPAHPlaD1I+qPyijQxofYcHvRGp4VGo +QE3LK7d+L7QmbbcRqFEba1kv3PUMrFGN1Hp1hjcwFpUGccn6D1bBr7dc9iJgeSdY +TUC+k8+X0+t8F4X3zm9DoH/fPvEG1d9qDrtVzu7TvvaJ1AMhkfgfGrAZxwAZJeW1 +bZZGrgVwDo5FPgiwxql6OuxHdm1+ku/VamUsaPmMNyzBXebzzwge118vir0p9aQ0 +lQPLWJz5IpIH5cpN+mSEfpgZEAv1mB0bgla5ZYZb8HvDanBjZg0ztTLWxJL+neGw +hMqsP78ZCdj5bZZ6lvURZ9Dk0hjKa2CThwu9hb5t3DJhQqTv4w0ICz7Q9y7rl6sR +ko5lZ2Zs8rG5CbHmVRHAZtd4ZDvdQ0um/Vhgz3XDxl91V6h8gzI+OZURCQFqxxst +Y19mRw7OGTPtCjXUcz74UbvYNt1K9xEV9ubHkdcVLS2fvt7BqmkVKf46tW4rki7Z +ZgX53/dRuoNvoUwK79JgRCUNHtziDL5cCb4tAdPcogpovEUxeDj8RYqmJ0+8RvDF +EJWeZAcfqp+tOkgkQRPAMnPrZ/tyQRUuTEqhzOKzquAANckPVo+jfQM+jUC2RptP +tNHiFEOnlR0/30iB3NUoWrQzl1FNUjHDp3PCk8TtNADa3X8vPFAGi+IQPqGUsapd +7L7yeIfZfa89BSV0zbf6K9L6BcpGAtFUYlw02930rtBiwPCmCQJ5hx2W2BlipW8l +gEgBIEgOVJQWBWgrS8QgACSA29HXjN8mk8kjH4UJFFavm2DHLVei2oAqFwE1ao2l +CWhYBZ73M3TSPc/EiIEf/3x/i1j3F0SfV0U6fLSiFVp/lim29CKdl9xxDhwBUQ2d +3jhKmbIbsi23TEvtzEX98vCSfStLu3UZUxOBof8uqVMxdzQuEmAuivlyjCqXwlwB +syNimxQ2OteEmuNnl34CtfEGmWrtLdxUlNgkEZkDvW8XggHrszCllbLm0EQm0hwd +8bhdmsid3tz/xPo/2uPV53EPcyx0QNk6pKpyqEPhjdiD97weLD5YoxpMWTw7Zk7i +sfG2AcBDqu5Bpum8Q5bxgy8GFQAMh3UeibF+NVNw3fdQDqAs8U6m7LJak8msa6es +WiFXd+wxBNC1lmZdAyd6khpkx3AVUr64tyqy96IkWV9MKsB/q6CKiuuhmDNNhmOV +vGt5tnFXJ4aKS2n40GDv3QkHVBhcSVWO4LmY38qM0TiugAphxXrrXypGhCN3WblL +sh1JH23M8EfZpIGdnSy4H1c5IVehnA4dxaPtHsIhLQZX8xxAAKJvtdBUKy+yLhXI +o5VWIT28uoE7AHCeBLHyF6d+MZO7SoodDJENSyUTHGLwQDmepraofr5qwwFLOqnF +2MnvfCjeqpXtiaVmLQ0CjY0+1mdoIIxIHEEWyfDc7AhspDLZfFnRDf4fmujjZtPI +uAcQzxPsJ39aKeXyZLVwuLyI5SELvDxpWN/McFuXwXC+yhyGJZZWrH2uC4AXHdh8 +dpsWLVOGlz6EmMYc9nUBQeNziyHMLB1G3t05ud8TJKsPimIvRdxcG+UBkymjw2cE +tHeium1jSozRIoXJo6cV6au8UGMIvigpKaEUyTF/cmtPE4On4NdT13NJgpJBL7e5 +bZzbEybvsXet4iBTBO8TCKV9x9+adh4y9ApOCBjdAfH/wEID4I30la748i+6G4J1 +lGP14Ux67U0csqS1nOQnJlNuuwP3JbcErxqn+soMU5LdArEw+k5ziwtV6VYVLF2f +/xxYWjvpFfjS80WOgwgTQBqrp/TmzbZXQ+RiBPYMhBjgBcqTbWqnROHTTZV1uIN8 +m897Pi7dBK8yXByggz+AbYBB6YVvNBveN/7yvEBP+f5ENZPJ29cp83q12XQX/xhE +uWBqgaYFn8jyteY6/zQ8sHuLPxbkMSNE8+fSuNpKPBWhppJBEAKX4d8ndr7KlzrH +RIE0zfrOzhQaz+87DjNr5yKMp7NAh1zoQwTWVzK75ZAxYMByY+W3/2DtkpDaH58q +BYFIf0pbB9A5Lc3vW0jNEwsileV2fH2H3nj0YMuex8pMRv0dmlgCuyes0ntIlx6m +Tf+dZjISahvl/jaCWLl8QTs9w6Mka60p0mnp25G23Wlg/5p2Ol6WMI9IHYZCGaQf +59pwbusGFuYod8NqW+aw5x8YaRSNgYvqMHJbgmGAsWDJdQTQhoXhzA+/m/U4BAlp +6NDHQWCDvNwG06xcj/gM2HqWOvEUThB5rlq9ecwjh/ONBM94Xn/u6X6XW/vZ+hFT +MpL6hcQrttvN1ZZimZX6lvop4oW5sz/IfLblh26XiSMQzFXdC9iPk7MLTBR6umbb +HhAI7GGlmEuZZEPa9OakrCGici+G+BY/p/PT0BWuuF1eBs6F5sXMO9OGtWjVjzkh +dEdCoeB427lt1j1YglfvN60vqz2JJqNRLf3fn/84r5rPiaeiF8OwqKJeBe1jGjTv +AuUveiLTr3KkqfFV6TyOHhl8GQI7YXaX9s2rz72hCD88yski1oTlgfrbOqVIVxWI +9+uiqX2h1b5an7UHiTEKkJPoAIQzwFOV+rdG5BEk9Fna16i+7vcDWmaMTFDYkvaM +f3JTBSWA4+T/egrPYJfnKNfdEDansAim/HrI9rbyMYIZnyF0QTJpylsznt8N4Z17 +TSItx4nkq6CnU0v1Q6hVS0MWKLM1aY9/xlb+sUFNxAjVj5MW4vO92+x5Gl0Gu+Mm +nBkcJlpAZhzGuPSqud7MawLRskrNP0iz824kVzW8mHbmdnCXINNoeTLRvlvru+VO +Vd7D8+9LSksjREwhjc0YKK3SHIMmOucgMxr4bW2bVPgyOyImy6tDrqJFhqwnzNlk +R4vSEaTgg4Va78G20QJrPEiaQB4ZfV0zEYWUihH1G4BUYfOfMrSFar8IbV6Cu0YI +fwJCCnqc8F2Pv3+/JLG1E1PQrNbc9b7nuJNNzJOeyXfujodXEbe8mOujhHdWRFXf +UKQoV6WAUW+W4eHwJ5Bxq4a8rqLrA9oU3cqnb7Tw5pTcYtzJqhPH02wuHWDFZ/06 +7do6dW7RCtvd7Jwqw/cXJbb4R+nV5wqOi4oqwVisxriVpTciIgCuT5etKrIw0l2k +G958N7vpHyHVjHzQ1/lH8DypAoEr4MK3DOd+5FrwRC4viXId14Dv3BkKEaF4DsGp +dP4w8Wqyc2IBobX8daFWrdIUJA2aIhkvV58rglqudYhNsx+fwEBaDsp3iPBjr2SZ +6TOV1soBJ8aOTN0RRI+wr8Q4UZT5SzU94oxqfj3L15IVy9SdoskGR5RKYUGtvucb +w8RY0w9OFEKYMwCnomWegx5OF0sxX4hYTCU2H+MgJ3ML1NmS2CTvTKm/uHDnpMg3 +L3CMlSyc9+ckzitr3stVP0ncYxpwvdnSS5/b+z1wlIT21mwIR9WaOBZ/gJNUUF2U +kYtF2UYFVeWY6ezzLOm9AablEPFvHqcZ7GKL1mxJPnSU5YeD0BpHxszc1sJtmF2N +xGiFSL7Xc6ZdzasD7gqIwTwUQLIhItI98M1I5DD5L6DHN0EWl0AxM3f6UOvj8IdQ +uOwtWJP9+Soz+tYRXaz+BiiEYY30lp3lOlRvmfpN2TQUguXuX5oezDjJvOpEVoEz +Yc3kX3CPBXgRP+WKXoDcLcnMx1pgMKAVZIw/uBuqcz82LIGj6liXy+pz0JfErXeG +7gnpd/nKdcCWxgz3fIQ61VqCra8hlhDejK0i5kul3DIwKSHScrXhKx/KTRAcvXcO +GraxxI3JzrL3+G477kw4wIyz1MfmhmCyvfO0B5PhWwZRWWoe8p5TMW0kNHvD2Gr2 +V0M7a+Wzd++wWjP84moaowrC0EGLHCYcFG3+0fHYgfEbGD7viOVk/FBqW0ZZ+IYL +4DWQMAEbuxg1gxE/fKkRsj1sCc3dslkCbwadF754TER27RQOVUQM5XT+JRAKbSDB +wehutE0Xm+5w12J5bboOQ9b1IEkKGNFFZlSHcgZU4Wkl0AIBIS5wCZX+78q+h5ws +ccvwTmHusNy1Xaq4/wrX4dkK7MrUz0+CMSdcFZ/xB502gAVHHfLv5uc5K1sYFHM0 +1qMB3NxKPj1Nk5XM6C+dguEk9kw0Iq6bVCzGqe30cJmiiY/E9P+OTrZBtdJPAs57 +yuH0Wq0x7C9WzQUOu9f+9ijtujszSfm2l5lrT6IK6lBmK1SYDzb5aWu7Ch8hQFTN +h3wdaoi1l191P6A4X7TADxHu3ycBK0d46wOr/LueWjK9RgmyFKzRNku2YNBaUyGU +jAGVJUNQ2eveQz6WujESd6nYAOtAId7DM5JGyt+2k48WLAm1lS/lVIqvQgHYnOL/ +6LPusXCvPnzFl3vIoDAedwDGnvhN7KWNLirbpJopjidxONeBcVDC5ymyo6Uxwg44 +T1pyzYlXK94NLW/ovFxHbPB6/N2qOTGwkyCJnOiT+v4VZVj6wWIoU8QPpO1/opEH +eMNKvogtksapqZY9HrqH2keIuSFi8m1nfzteJgMdMiszc9F8I2h9Ea/Tyeeobr1H +Tn56tkn+SOJVUf16VSSb0wHQSCdKJFvjpXGNl3aWC2WTXI8BNpy5meRJuYuNmgSZ +SZ8mUQ6dYlFzvuBaI3AAQwo/w6tbATfymo8DUo1n/bPeM1mQGQiBEYT0j5FGFuuC +wYqoA0FKNMQPPH4vRUMlvHiKiBeOepPImFjSCODYeGM7vpOBTql59enTTgG+sUaw +HK3aowW6aMY8AZ7gfnA9cSmcRYknsmEob5qI+8J1WmZpbksvVd6mSsntajqP5pJY +0rbUF4mzCC/5xqsIXoIrDS3HAno5PbgrcgFKZoC0iPFt4RpeDfYimwTod36HhcsI +FdzsC5sqVNZ5kiv9TVEXOxJrNDyeZA5SlZ6jg42G6y9rjLMCv5g0/dQZvZl3g2zP +9g/PS/MgeszrufZLRRZKuO9SOHpwri+G+pS3p7h29357C2IK+2n1CoN9CM6R/S/I +Xpna9Krke2HyEIH3pO2CBQL1Ch/qsookLJMcCaIdpdNRNa2UCsV0IblRhso3ugNg +eecKq92nRwGSJP78dtKt/7fegmL+m/zE7cgGlF2+nok0SR4mlpimb/rljXUm2k40 +zGMCFrIeyCkIEpFKgkStoRc4I6Qz2xp3iUrXKnTT4Opcb3udG2NRNLmLmrbXWcfQ +MyZuOuEamD0+pvRwaWg6kaaoNW8+k154aCj3gLLviOy1Y+aNha3OjlROpMZiuqtD +mSahR4ko6ErG+6B5aLyuH1V1EXaylcWe+7HwdPf0RPN7Y4xwCB1nWYHkW8ABqnys +Xx4xGiAyPpGDUgZg6JhULqxUTnj2iR3L3FLV+3DlOG00jRrN9EaEO+3TkS2SLPME +dVbw7YpjUT0VcPbGINvWE8kTMs+HrJIScRCzu7fKh+Loa3rgZ2dhcrxE7Af9CK/f +/rB0Hi5sI+WkWd8eQTDkneLaiufoCH8cYU/fypg+AllpEclrh6aqLBoJhhDIXosH +lmqP5kk1xbh0C/vtmTnVTMMPjgZhdvu2ThSs8YJ76Lqy9IGE28jYRjWZ5hOIDMaW +spgdmXSUWuYoZSTWgHxmDX0YTbpJOL6rqjnKYgZYSvcYj/UKG1EEPojbUlv/6piR +qK0vqSvzfYrhbvzNS4T2wtSPhd/WSAI8LriCij8cTUVl5jpBrZt3Y9Yss6htFDdW +XA/Cyt122DpKK7UXl+zs+S7NTqqXShhi4y8eg7K5B8ZnHWMW0y5+0lSSp3BVNs8o +sSTCSI9lFTu/7bNkMeAqyugt497DzgGBG4VNFuBbg1Fn19t+w0pjpTg3qY4sgfwJ +vYlt2zYFzApT/Y+CQORd+duEq7lGgikza39VmmtUmMpS56EclwPbCRkU6Dz5yo37 +Ga0OhcH2zFBlWfLux1VDrsNcFbX+an5dRA09pU6I0Xi5xi9NKx/UZ3Sa+vlvWG2/ +mB7a66AraB5qYIIc6Cgmgw+yhixkAxJWr/EBH4BkQ9FWg9nkSNvOvW6M0hXwX4PL +4/QdRukME5LdYa13fFx5QHyLLpvwkeiqQ6FSNB3goN5pHwqMZUrG5P+RstFvGeWF +9HswD5A2f2zx2v0gp9rVpkvQ5Tela92OhReowc8F7nxym+ZBrvY7jMgs2/l351l/ +bEfufaTkKB7zdqYOqjqaDy3WYtCGPYV65zgok7eHBAFx+hffPBUpo7DB+U+EpdIx +id5Ph7j4cUVYI3h0dpuYTyOqyhYLL/5leDSKAvqAJ5ausHrOb5HnZJURWXpHEfqc +2+oqbyjQt6NPvil3npEGeNKKTyr+ZSTdEF9hJMe3xBPAA4opuoug6FQX2y6PHKUc +qidx74LdfycOh9eHG5scrPHwCekN3mN7Wj0re7UziNPDgETkn2/DZ8Ru0jxntkFU +GkxUPoz62M1cJPlI/GRBFx1iPNqRhlGQptUbePZrr2Yl34gsLv6E1srYsYI7OlPd +rBgjBD8B7HIwmh1ojpsXgoZRK4ZEcyc03WBGX+xwKr8ocrlh+A8bhnj/YAlVikNN +JRAZXO5YRiJBu2qq7NHHyYpdmvq5BBQORa1cLi/js/FAOBPal46FyhTqI873m4R0 +V6K2OmmQr3Yb5QypWiXo+tkXkfZ+MqkWF2CdMG1grBEWDunnYwu/ivg1+27FKA0k +LsVvNPRHubKKtI3U/b0o5eg6ybHnfOQQ/mM7dRokxMMsba6dPv9kuWUVgIQCtpVx ++t36xmUXj5UP5ZbK1y7hwnHxn901cbudIz7u/86+jPSw07YmEoiZ/VRzedm+ZZJM +7STu4b/PAoghpUUaFjetp/UlhJt56n38Y37XoIMQJWLY9pAU5rjwtDj0/VYfuZTf +Tm+moM6GpiZlTpyNXZ71mHH16047VYo7q/e/q2su+hSP5s92VMOz8MweY/rmdPjT +6CYr/fwsx38juIQNhUujxa8Wm4YYpRMl+58+7qSBrELXOerF/bGNs40bHht5CR1h +eQbOywsBkdyT2rfK4Ih9QbcjQQiWCTg+2fE1VqF/cl3poFdonSLnjSUJS0CqzKEG +WSTmO7O3wa2QQfTzII2fK7Q9C5tmCadMWfNah62E+4IF5E0dCv8z+UXev8Uv8i11 +JX3x3bgmw560Ct6f/QO7bpe2BYMzN2FRHDepOa7Ll6XA02KyguQrgKH+bjWaxVhV +tpAFX+JCFvHHhArlMVYDercUTOaDd+MEncFjeHYbSjZlhK3U7yCQouJkxcV3ub57 +3oKVE38X0m60gqFP6yYHXDLhtlnxgwHOJhfHLmstHWfGfS4f0PIUjqfRwTXOSXf9 +Djp3kSHawQMGNZmj6ZpW6ko4luVUZihB+WmxJaSlV+izT7XvHOKg6W9GCpBCau7h +FE8t6Zl+GdSCFyFf3CaG9qM1vgh+skYPBAro+ubGNfgnpykfa51VbGKRWCFtlYHH +es+w4M5MEnDm//xbIBUigFu/lYdjcWI+watM6Ot5cxvf0D1L3Xgj6erkZrs53EI0 +6qGSVmFfF7ADQ30aueKGiNjmHxbHoZe03r65QNQh75i06qf6us3pIJX+8ouidrd7 +Mx88K/Bc8PwEQP0Nj6nFsJvcOkqYpOqfoyIxO9XIYGV5o3JzVhMDPrs1OcNFODhS +R2I3eq9ltDHqr+fxKmqNnHb/GaiIXdfZEGsPC6N5YcRJJ8m0bUIRlk/SAp1lDYxd +dQaBazA+BRFgJ9UjYFe0Cf6ie7Ydd63nIUenEMC8vT0seLIG/2XmFqZh5fhHACvG +YdTbsJ1TH5IN7m4chgusKAjHW/Lk/XzfiVvwH7rrzYWXGX85ezG3V+Az6LrMW0Mo +mkG2ei71rGx31jRYp0KXbYQapuS0JD2hW9v/SNpMEAJ8HYQrR0YziHVtxQS//+ep +Q56ev4SK1MdY9niV+ydaO9eMOSd8hBj+DMo4PlmPvwsx8c90ia+jNtBHIkSfNUh3 +8Pr2UpdGbi+VpZINiEoYtQBsZ4YF5wA3h67vHfIMiyb511WaKPVmMkmpm0LBtRLG +Ghaluz7uT7dh47Me6VqeItEo7htMTh0Si1S6sWq9/9IMIMwUy5lvPvfR7mruAxmh +8Rw3zvR+8iF4/gWpSrOuMQ0ZeX0bTja0xH+iqumO9Pa0ZxXNSPq+CIw0bpsOw6NH +vE7OhXWmgAeo0RwWnOMQtSO+9ms5pxTdPCzNUMnJu05P1+IQ2dJAHDcKIIf5fzZp +zMLgzIvVJHUDDhSAYA0ZrtPxcU3NVcZrZoVCLVoJI57jFuMi0My/epkM7dk+uB1L +EYQuwxRsCwRqABAZMYfgNzjrhrwChEuxv0JqTtft/iIKq+6511k5ye+PuESyNM8c +x5Lm0e5XflV+mBxJwioEIk899F7QlpOt/85edF94K26QRQ0nz7erhvvxurw8VjPj +L/QWfhl4D32AD6XldJPctTc29G9ZJ4n/NYTVaHifrGXaYeSHQfDsT4C1bHasUhdA +Y9h5VRl9QSIUdWwFqBPEPuZU88J/vGgOKSa3ozXcmSl0TyTZA5HwHqllaaDKo7o1 +PwQE3aAZxciNq39XU3V/yImonkoQ/pEh1lgHqqAIRykU/DpoWqE2uWhfzSOPD7cQ +TAfNCimz/qaDqW2dQyppV8TKLrLcSp658f9ZnCEkQpiAD/E2N5ezOS2r+FJi/pbd +UsV1IV7vOOQv+cRcTjtTdGhQDevJy4DnkgiwgvZaMG/YWhcFTYk5de20fhJJueJs +whqPmvEtPJ2hpiMGE0/pgFUauJ1k5NKJh1bXEuLI8WJLgrD8emDnx0l2yRRH4cjO +O7fiye20lKFX8WKzTMtZa443D1aUDfRbZzt/CPvhHtgwWANrGaojgiVD6fT/i3Uw +ni7gHUo1TZnQmbr9s4u17qK1nw+UJl6Fb0DA/M8i19/iX9XqeAlhGs5gMwbQpnKr +hGNLL3a9wLvVSUIyGp95PlkJZTwFQ3qIDDBGC57BW4kZgt0uGicK/0fIhtVQqQtc +aLcR9RJVcoHBQ53gvdpH049ymC+MHLOndluryrtQwSqUdXUs1FrZ/b7+WLxk6iAc +08BK+BnK1R/B9zas6udTOTU/whksYgiKtULTskha+puyW+MTcy/Vqmd3o1YnzQB6 +Vpw4abeB0ViwTxRhpDPIDqn53nVTnY4fePGGWVTTcOTqQRMMuTgPCsCtuEv13kfa +uLXV1w/UdCCDT2Jr4T+ZmmemY5IiC3VgQMGhAk6yPpiDYNvqvhga01bc+RXlhiwm +B0AI/CKOkIWshogM/4ODHLlsWqKprow9uPplNnPOVkXvY9aOtmLiIvadIRnZS4IQ +byVy9L3wHyAsYiIS0bbMU7GxreNytLiTCuXFkzKpHLDWLwIktbB3bfWSb1lcjtVI +XUHeAyyXpQ5a2mn3TC3A5nPbcNlTpJVMoT54UZdI5IF1zD6Q7aB/und7bFlkv+eP +k0kE435zDA4qhNnC8w/GiarhOwXUUSyI9T0ZEk4Lot8lTM8jv5qJ7ZaiQ+R2nwFY +Kl3E0dNNz7dys/XvHoIVrVaK2H7XlhsDQFreSQ5bwiSCSi96aMzWnQa+9ax+noJI +mDNGmkts/Bzr2ZLWug0JM29NFMwBTXd0Am4YgodixmW8SwZclNDJ30RaPMh2FAM/ +L21n/JlbH07C1orIN60Trc0pplZysp62fxm1wQNcU9mGW4Gw4Q+PU+zhy1TI+pfC +yZEad/Wkgb/sY7QhbZ8qYAqJkFG0+oqH5R+RbbAOsTftW34hPAQ5FRVuG7YjBT78 +WsRhXt9zq/UREd5bSWkQtRrDnLexsQcgISKSy1jrKRrfgYcLB2oFZUTa3/DuQ4AA ++9SntPNgRL2JVz3WUCkv/RG82L/90mVGqic2YeMp7ZTmswwIBprkH2FQdoIShcVc +TPbwAXVzsOTwTBofDQhfPfvXA6W21HZJXasFTi5rn0VgyX8IZ/lRxNMMfE/v9MLf +Fdg9DQlewSBAuspi7QV9iNYoPi4NETpQgJE7yoXNLs6Uhm1UqgR3uP3TKzNPWP0h +2W7IQel4J1siNSzvnnuIF5bYNtzM6NXQ16V4SZjLuXiBRv7tU+PY86f/7brTCCrA +IYQk93WXBlbVBWaTlCtwf8x6LEWXUsjvIbCPxSTRiiaPCz8U8YooQDTSkNc652TV +WVOPNMFe9pASE9cDZGxVH2J8qLjVRWEmCcxOVWj6TZz6LGt4vFILWfubE9Oi4MBR +28nWw/r4qBgu83Xct8X80pro6Hw0OwRhD9J+Il/cueSSroUJK24CmPQDegySc38G +C0SGtA6gTrDoAYAw07r0AVuzfRLc+hgz7+w1T5EDewQ9meZYPrPZD3QxbmMHi/K4 +2Dm100i9lclCwS2VcSv5Ri9tZpsebvRl86gbOLYyrV54ecTliZgBkvB14pl5e7DL +3xkFg4w0ZMmo/qEsozgB4Ie2tg4ogqrJAOvXVirRRTDNBPlqSN05QtE9Kt7+gRCw +jB7tdAVzr/+2BUUH6LLmu5wK397MSi1AqMrecbttebhB8MtWLIHlpVCqNvLKGqUI +77KEEIXlCgQ2xd9/hhogs+gD6WECJVqRexdOtqQK+4TLZ+/ghS19+LDhbVQsvXlS +CBlFZGAtwz/kzDGcEAH5TjxqmXgIvAfLySCz9BQGN/gz0vPUHQTHSVtPPLjQG3t2 +8yHyq2IXGsJvQobMemv3ACI6+XXwe4oyagZTPUHc6YFL6CAfT3ZBKJZfFkr6yysX +A4j197r9QPS7+ZoZ/Z6q5hM/fxDhxURruabw7a2TPG9j7rju98mpkek3SWIV3N6l +7cS+NvBueiFpkescJ8G6WZLzZGE3SSc2v6EK/0AKaaJgnwbKFK2gJXk98VquAbmq +LXkQQdaUj3Jl16qnnsGOcj0hTADQxKyBZAEZ9rBxgt0IcVgqTD6ISsjTnbEswTeH +DsZmR0nyPSUadv2bTjE0evH6oUin4PdBxJdZQHZ1HPPHAxnf0XDqI59zMpkGAixz +A8WO7iLTmXLjj6UHlX3WZe3ci6mmKAGlpBHGCmfK0VtwrpOz+TpGt0Njv4NKITc7 +/rYEuSQEcc/ZK02Eh37XxlZ7l56L/f+sqIhQKH+M8sEe5pddqoKr7PBftqJWN+YI +vUIsCRknxw1l/X0Tk7N635G1rI3erYlljqGcgJhPGvafnhHDPLLlTGJs0+nbpplv +z38toWKWddsqb3L79eRvbppsKBWNjmq075NCqFK9Ep+gt1ZgrQ8oW+o5Gip2+Drx +8kimVDiBTph77RoMXR/Ubh1RLYlrXnNuvM/ciDRRr7fOBW4VTzvq3CHTWW5ubbtT +pQyB9H/NewWIlJfkFvRRTcQML0tGWBXX6YYFjFFg4jR8nzqNtBJBsZpgDZWeu9s1 +2RhG9nSdRCSuBnEdpdYHb6rqQ7drZuh7l56oG87WP1qbxFoMZ925doy9ckqZodwN +A6oO6Trmud3/MsO3DQ9iCL+3B6NQ78tONz3OH7jEpBxWHghYdwsZ95LbR8OBS2z0 +SepqYBx9nB0kbIdOhdndRP1BsdXmhvcnr8s9MFnkA/JppbFDWpxdbGKORg5gK7o+ +Byo2kXWhSue0NLb6QjBKH3HCB35sL+Iy/SM8jNm/ilMtDZOR29E/b8eeLx7ixyH/ +Erw+ati706ubXvkoAXC/n/hRH51apQOvjUystgKFOpg6wNAJfF1Q+ORi9uR0qWe8 +i5qqL0BPXg4l0yU9f+hWRjY8VifxwmpSmV1QG/hz5N98ABYiu87B0gxIdq5Eu8E5 ++CfYDNFor2vNSA8y9rGX6RYsSIoxQScM45zidYtzoJvq29vRVfIC6cGCNCTHtGyZ +bq4KjOmLNBd6e3o4KIelH4ycG6L2c2M/aTz67Ws0Aj8Tykfy8hHl/NpFegOsV4u6 +QVuYUUT+Ufs8wqFjiQbAeTiH7L98dJN9MficHE0zUAETI0jiYCUxj+Ya4oLskx/E +dEre09z5iKDrLM2tyHbXVMeDE0E79jV+rAW+328DPyjgmfLLxSoNuRHKidBYzpQ2 +kxp451ur7XSI22aV+c4Rgjv8s2kBmXt5g1LwGEVHY8CZaqQYrQXaX2y/OmcP9IRC +kCwIZFe9prhAICWTcTLlA75IcYSKrks35Hs0nHJ7wpvj1hzOqRs7Qp4zD7NGjtKt +xQ3WxeqEQpoHVr7okvuNySeS5rCmG+24Vj/1QKGs9tSC30EkuaDqX/pKIh7Ahla+ +NkaBrBAuzQL65ftqqcqcrKkw4ayoMH8grg8hXb0lFTO+0QwrMvCTe6KFA7ujFPU8 +ZURAbjEygRzdLZ/Xv2HHJ6SJ7IQxtuYKOXNlXFwJdRd0B94qqJcs2VivvIZpDMw5 +3r/Lg8Rb1xOX25SKgL9WBrDHmhiYjw9rnRcwiOYM0s0OP58u/i/zcddMC7C7ZYz1 +g+R+C5z+0wQQbuOUqU8RPJ8AP4DNZdi0o6V2aivhocnuH/Bm6LcfdwS96pBH/uur +dPxsKgKewGUl4uj9UOJrNuKimz7qoUOD8bdIYuES+3wh3dcGRLlIa/uALpVKnBXD +b1rG3fea6munFwr3G76O3khv4jSdn7LFZt0tv9Zjjq4s6b2fJIIjNQVRyeqE3e0v +a3KUWalg22N4bYRMYTD8COWmaszxOOfKINahj5oklukATfYb8ya+ZuIuYyOU6DOB +yUerLTCE4ISOQRie3zqkPQNDpAQJrtzt3CCegh3LaNUWKK1k1cQOl6KFBN9z5COn +C2Z07OYh9goCmKDJerUYfbrwfGFMd7y5l15Xs7mGydMBc9IJXeB9q3EL8EWf/iKe +v95d+d2yzbYZmypGMD/pdCJ3H5JKg+mZgC/0nfXnT+Bu+gHL3+ynQ1+5kA5/4sVP +tUWnifc6tbMHEa2j7e6UUNtPriEI5wGTeLBjBeXB8fOVNEdZtN2s4p+zcXJ4Cx1W +tXZH3HXoxEPbHrgQEKvKVFWrcLSHZPLvhAoYOZoQI/+RMnR9qVVRacBTwXiNhqcn +HGhU8FSTK2DowTm110M+dgi5yhVmhnguyrWx9boMk8O0h6pITJU38aMFnPIoNYis +xaY2Ku+IlpBVsm8x6ggOj19977q1U+Km8QSFiYRU2zvYP3qQxyKM2Pi5TDodINqf +ynoUDmY99F/OTVBMLLme/7q7NbnGHohS8ekiEpXiIxy8f1SkzOwWLu3Ii5oX8tBd +wAM+yozXmOaId2eFqTexhnSx7EPkRC5anQRGXsJYTJh2dnJqgRFWtRhZhyr8Dwar +CSNIXmIfflCmV0ZxO2JOWYYpdI1I35pzscvDYhJ6SsDLMWzk6Rc3MxecziG1JBqL +J1XAp3596rLeP+7MTnGpgI6q3+OUSiYRLKRFqoO1qsLzVCuH4LJrMlov2pRFl5qm +O3IVCLxI0FIxw4HQb0Xpcr8WnqstBWoBoU1CcUecCkhrFgCDWSWPZL/PTVeLVv4N +vmNurotg9dTeV1wgziZfLpahgoeqfyH94zySTHZb5vZvI6HTVWK8+TnsMy4h3ABW +eQCTxksLsuutyiNSNMcXHE+dtkeeX4CiDIdeIud10yDV/wOSRxLkpUllxZT3avMz +ssD12W4Jt82Mn5bShg7BookbbAFFA2RKiOLhvYO89wOy8jcVerZc/jJmAkcayUf2 +v54ll13dkUiHlzVVA7t0N2/M179RbeuhIDOWncw20lWh8TdfTUfqANleqARUOn4b +4bgMvrMyP6jt0fU2Zw4P0HKn90YGO7GXhcyVgi1Dp6OPuGbeiAs6wQhlMpTp9Ao0 +J9S2JNRoPu+EffjBhfOxCYxuF+qlp3fIKbBPxEofbMCDBlLJTzQNi8qQ3kisvs2K +UshK2bRjbGCbCzDuwc1aPF/xa3x1OA121Fj65VHfL98TzbRr93wb1Aq1q1w49PeP +IvBaR2pzuKWRRReBvx+J7j7eXqcgMNx3MJZN95nEqmB1/CJ30Qn090FxPM+3+xZL +Y/9G23qsiowrEfgjvkV5Y2aSdtHQJ3FELwIH4mvevhSOiaFahZIyl/b7bzngKYSW +aWTI50Qv3bAyo3e3Ozz/iQm0CN2jUSpqYDqBnGQ5ynahyls2fB9OOxKLWHrrCC2m +ndUN/C4Acg9sTqGeSGwVeChLM/tF663M3VhsQj93Z6gjMBHmFR+r9yTUkp0UyHWP +mcJSOINBj3Fc1kvgUS9cj9zksl5eiG6AG95RAxXBxrKAa8YbfXgZScu4uneKaW30 +Se/uC/k3OWxtvw4vZoIclWFJVqdH24CsV+hzWy3bjjjjqG0fH1plN4xGsNF1gqxt +OYwVWW2m2CefkW4AM5+AbeTlykXquMQOcuYKlX4Z5GV1rg0NjfT0BF5oAKFdxyLO +NwtXHGOza+AzqMhl9yo5/0WCBGmkiviUzJJI2mDMHwM0ExKgb0O4Sy5CuGnomgAO ++xLD57vjb+s9pSMs6JCmw5/5wnGxY5yPXztxc9UGT2s= +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +GgbHzgThm+pxY8qJAenj6M1nMg+PiGn8p88tojq6cijNwxinCZAmPODaDelUBiV/ +7pt9zFVTV7grht3KSqQVNS0NNFR2RViANJyed9qeVdSo+i1niQsqbPxS+dVMrEAH +GLcA4c87U2QITQVVg7mqbwa39eel3uSw5jIs/cPWgUVZwOX65uNekkTj2RtXHhFd +d0pI3dQoLqLefXHWCbn9KLkxN0XEZfWthZgyZS3VmSWHt8u7zaOvBv47vhah3n+9 +KhPDKZWleg/lH12jwGNtIA+ITKMLpp85nyYO2opdw1uFpHhBC1eWGDzHbnzEyKPz +1lNcyRWK+pqU/AY4z4Ujwg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 880 ) +`pragma protect data_block +a2PDY7wD+DHw8OF9GdySBvuAv9crSSeitt71UCe4rRD8aRaQ7B7JOb87rVKNaP+Y +P/pNSHeTA0LgZbqqvIaFxo2MZorvxVDPD9t+dcY2+NwzC+guE60XPM7TRfEWjuoe +mCDMlV1FgD1JBxxH98/PCJ9FdWIitffatZK/6h0zBd1y20gPL4NCldEah/0dlzsE +ZYlSpoKDOkf4ffYl6KkI7rK5zPl/obVTsYxOGLgnsUf6KPLFF8wfh092jhr35joP +zJPi36aMCfqrd+EVpO1Ba+4f2HgslYMGhgxzSfiDw5+qDox8mLHJrH6YiIkPecqY +DWXyb9xcF53f08/oAFMiYMqaYQZqy0QHCrNw79H6/E15d6BdVnG7SVmAlaJXlAQM +RB0LmInhsRXkwvijDTY656LDiQHUezuR6a8w3gyVo/IODO1LU8C2HZj4/NLID8GP +/VQhkQDYOCWzMwG4flLhavf8TGaLmmcsLpB30ad2uGLu5GkPCWLw/xu3pPbHtZSH +QvuUOUfXPzCXwqDLBvLC0Q3vQktfghuGVwl+G5IUeoz+79V0RJxBwiugsA+9kSPc +adazmz2dYTZQg3XuS5fEwjW/PpvmI4AO5L/to3aLL7ScLIXVnAFG/RqthmRn8UA1 +UBBmFSbYLWoZD9+yYC5Z27zL4cpg3aO6/320kboJd09lPyT9dqU7J0sepyAHbSBe +8I/h4S3KDUpk0ZY3p1dq/+WbAAJbFbysshRIobC36fJEPf61smM2n8MSfy33wg0J +Zf7Ox2L7sy2gRSdjOQdz4ewzRS6FowglhyPo5GJOkEVER5oLRxLwmFtNNZ1Z5kgg +/YQ2hAsi7TZWcksSfpM38VL3yRExRkYApK1//eUdZLGG3B0XNL3kMCvO/w7/UyDv +KyZYuYh3rOMk9HN0unGrAYYK1rq4HRc7d+p04AtPql6+UFkj4u7mNkP6Obll0+Xt +RtzuEQvQ0hZvTswe99AhgjofpEIG/YObN9S/FEHmYwBf5CzOg442K4otNJ9USGp6 +xEXuVj4EGsrgId2plsBHWdHiUVPZacoxWIRIEpW3Qy5PXHqYMv4rwxPJAciabt3r +gKxplQKOCbzsgNb+UbbiNSVMtBIAYwgkdUZarHuethhgz5M+fEa+AqiLzEkj5N+5 +3W39ohLhggzKXrAnuVk7fg== +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +module `IP_MODULE_NAME(sdhc)#( + parameter VERSION = 32'h10, + parameter DATA_BUFFER_DEPTH = 512, + parameter ADMA_DATA_WIDTH = 32, + parameter FAMILY = "TITANIUM" +) +( +input sd_rst, +input sd_base_clk, +output wire sd_int, +input sd_wp, +input sd_cd_n, +input s_axi_aclk, +input [9:0] s_axi_awaddr, +input s_axi_awvalid, +output wire s_axi_awready, +input [31:0] s_axi_wdata, +input [3:0] s_axi_wstrb, +input s_axi_wvalid, +output wire s_axi_wready, +output wire [1:0] s_axi_bresp, +output wire s_axi_bvalid, +input s_axi_bready, +input [9:0] s_axi_araddr, +input s_axi_arvalid, +output wire s_axi_arready, +output wire [1:0] s_axi_rresp, +output wire [31:0] s_axi_rdata, +output wire s_axi_rvalid, +input s_axi_rready, +input m_axi_clk, +output wire m_axi_awvalid, +output wire [31:0] m_axi_awaddr, +output wire [7:0] m_axi_awlen, +output wire [2:0] m_axi_awsize, +output wire [1:0] m_axi_awburst, +output wire [2:0] m_axi_awprot, +output wire [1:0] m_axi_awlock, +output wire [3:0] m_axi_awcache, +input m_axi_awready, +output wire [ADMA_DATA_WIDTH-1:0] m_axi_wdata, +output wire [ADMA_DATA_WIDTH/8-1:0] m_axi_wstrb, +output wire m_axi_wlast, +output wire m_axi_wvalid, +input m_axi_wready, +input [1:0] m_axi_bresp, +input m_axi_bvalid, +output wire m_axi_bready, +output wire m_axi_arvalid, +output wire [31:0] m_axi_araddr, +output wire [7:0] m_axi_arlen, +output wire [2:0] m_axi_arsize, +output wire [1:0] m_axi_arburst, +output wire [2:0] m_axi_arprot, +output wire [1:0] m_axi_arlock, +output wire [3:0] m_axi_arcache, +input m_axi_arready, +input m_axi_rvalid, +input [ADMA_DATA_WIDTH-1:0] m_axi_rdata, +input m_axi_rlast, +input [1:0] m_axi_rresp, +output wire m_axi_rready, +output wire sd_clk_hi, +output wire sd_clk_lo, +input sd_cmd_i, +output wire sd_cmd_o, +output wire sd_cmd_oe, +input [3:0] sd_dat_i, +output wire [3:0] sd_dat_o, +output wire sd_dat_oe +); +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +At8NDOCc4kD0cT6FYsAsqOLQpaMw3bVfTTiE5FP1gKwP5J3rADYscuAA9znbPvis +MBOXI5NN1IOCBhY8docHxSOtWyofhmco6KiZiSxlTAMnmzRtihgtqcUXsQWTNJTE +7whQH53NWjSMVPv2SQrHMa1RpUZnyo5STupbfD+3UW/HzNlYy+PEUQwYAxlOnG2M +LOVENWcTIh7UmStLPYTtgneJd8aOpL+baFyO2aNiHXosS76QIqvTKZQ17Q03p5K3 +i8PCPzCbmM0BxPP9kfJ10GKVxW69hi9fUcUUgGpKsloUh/zrI9OINMKLSkzf1fVU +lCxpq+G9vTz3hl52Jvm2Hw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 47504 ) +`pragma protect data_block +6DtJMbz4Ibm2QCuJndBEjY814wOQN1ovsm0I1k/eQ5F6nXmL+8tc6Dg5H5R4TyKZ +q9fOUov9KWzcH+lSAAaN/zzJYb8+4MPvp+PEgjpW1X4DgO69hTRPHwcr5cAdpFGO +zjd8bfu036TONJBBYTZzmJAkxyj2p0KU3zkIpovpC9js6bioz5OgKp5u3XMI8a+1 +BjG+bSDznAAeOMwjYNQhDyLCmyJ0dscHZu/ntQ6a/yXr9eoQ1BV1Yp7+jXu6ouCt +lypRiID+AVbz2gyP3k+PRJts2jYpffgbwCPB85AkZnua3gXlfPWAUKvYub6//sSu +TBSd82JFbBrZEZA+rg9vuzt3RmM7/cO8VfqwOcQUYP5AX5m/+4DbQcSJUJxwLGAs +njVZQ/SNcmsAdAlo9d67Z9nM9jTfdNi1QZP2oJUs0/9heUXixobakPHNc9FdtgFD +5ZHvf54jmPdw5Ko296Xf1eGabMBwGP1O69p/vyHha8zR80v72e+tNuCiNy89ERMo +wp4awRnxntoidrwrJi3lCHd7NXiORFtkmY8Zac8rMBCQ2rHig5/Jlfn3ny/8Plea +lyTGc0FkW851f5MMMMmk9fIZG9hha8nCxTHzWzlW/Gdudz6+mYEfTugrI/OWVGOr +E7XfR0Runql4ANKLVNCzzjCYWBScPSo7bI1Y4IqlHStO6y+L19DZ4Q4dd8H+g8r4 +858IUd/SFT+0PbeiKb4biad+kULqoLLCYndauDNBSwP8cCtl8YTQx4O5Pz8ne5rs +Oks9WQU3PYs5/INVUBoNE7mQaaKK+gjYbcKhaXskEKpMCopy+9QA4k855XdL38DU +oZFMr2PT/EG2w8+5Qntd/ZGQILdijMnL0GJ7pyu0b46VLj8gI/Ofb6bSNCwHASWX +/b9SxX4EhMZ1uj8ZR+rmy0CJWvm0IFdocVofbEKlqKK4cptZ3msiO31/vpph/qEz +xqnc4vBChtqGRAj0rtWEP+4btqdFohKKvxpWCiFkq1J7g6c5xKzTiYzgdBbxyJkP +aS0ep6AZMeQGBftpKhNeBNQMW4Xb6OqrO3z5K5KOFxVWsY8fTxHOVV+u7pNPZfZS +eGPsGdUjFA5YSNXonGVcSnSeTEwMnHmUnyMgzM0QU9li4jlLpUu+ExqP1ajaf511 +a19zjSgBkzGBnkx02D1mIDyrSLl+7hYpXF+e5RiPblCpRAAGeX3Grh+LvrfChIqv +3pDO1BTNUJJ4fCsZiqjUB9HiQmY9q1ln8MNWjPdUQKJ8menPjblIzrXowXAdVvJS +zYwnv0FcTgRYVuh5cZrtZfUMJn0WaDlF9jOt2fxUxdppOCxshB2HRnHQGX0gG64x +wVKdXpo3TSFyNPKqD4d6O1EKY6BQh8VafJa+ot7DyqQJQvG1BR3pGKTVfDs08uzZ +eIrrmLy2/9AxFRCZxJe0eV8V/FDOWIkN4kjVZZNhzjLP7/HG9nZai0JP/PyTCq8b +ZJLmTGnb3W2cnxin6mxrTvIY1iHeTNR2APZIr0V8zANzGmQkxLPZGqdAHM2jSjQU +Bqq61g2ZK+7azl5aj0gqRdiorS3mSIVmgSKiLVZI841ptK2YQLHCWeVgNXHteTp9 +eInPmbmVNNfzhjoxmnaRZdqDfW43VUDRXIIzAzc/UMCw2Vtd8Y+HMrqFOKrEDPEX +7dEqUTtu4BW7BZI59XEaRPLggAJkz55/IiqO12/yZPCNj885iZoVQgxZBwGa+gGU +lTxI8OY7DBXIEBJBmbHYEOnT7ngAIm6wjQff/o7Am2bHA58llLT9VOtR0Giosnzg +la+J2PyacM+hni/JD3bDs3fe28621WTdRlrWDSoluFydnZHv/zu1RNmGkdE28AEy +qv/g50nYxlaCTSDAo2GyRHk3n10d574xrtIQuhhzUzNph42ci3fLkkyYZpEby+Iv +j/qbwF4p3y5B6DYrelujSIUGkx4MJR/l2ndPj5qlh5KFosaL8bCA6hb2VrrR7iLy +/6lkJcSzYG6vg/QBoSl57GdQUQrQ564g4hTnATSmRSqgPJzT8sQ0CMCQuUPEi/wP +LKtgIcnc904af92r7xWpSZO7a/fm/FMF2qOp/aZAJS0Ysh8mpzuafUv31vd90zTM +eRJwgC68jw6zwG4rVIYxsbmes9CvPoCd9WkaKLv0ih8dSypY+cvXYolnzQSbg9Ah +Jov32B+rSUwWA37wP0RcI9x63ybsAOSd8Mk6vtc4b6WzHcDUmOCYOSFUYKqDSCHI +PDl61MF15VfqubbsRY+QiZFN/xG82xFYxP+Ph773X8PW9Q333WJWd5wzRkYtFjp2 +TpYeUC/XE+aiQleP75RJQIzijBlOZeEevBKi+PDdPQs9dnTSswoOvNN2TWMnS7VO +UDl9Or6UzPWOXjN+r3Gmqf3Qv1tryPSpESftoqTGy1x2RhIyLpXboS+H1tQuMRQb +icMVJJlo4YfTQ4Pc0RLoCEs6B24TTGTu578B8aj01gkvPIcdW/D0Mqmbo1QwZGcI +4DNIYzPXP2gEK0acX1B36UlwPFNBuTBTiIT+jSp4/bJ8UeEyoQJFzGTB1fAKIkvF +ChcZxmknW/mLD/dZMnPY7YH7EufCi9wQQ44cIO0xk/cr6Kbg3wkU4FmfiXlsXxzZ +u7Pyw7shJDV8oHAqo8r2mtMN1ji8fzC7jQFHZAhUxtLF9pEiOkj21RznPmll4GgG +Fm8m+sTz4fqouWKcXJBQioUaWCccpqVouDj6ReiMwM2acN8zldgisSckxYWZQvHs +0iANOxILIzUoC3eBla2cm22ygOg6Smj/KJGabSRJ4JlNDBqrzFtazIZ/BZ2r9LMB +uOh99xNHcp42ci72Tbfg0AjMZ5OgUsgBenYR0wKNkznM410x9wm39uz/fx1xmRuQ +nalKxhJtrMG50A+IUSsqVaTEfjIcKNj+sWR+nBib/iti7QdgihYRBm3BP9mlCA4c ++wx33X2q56e61UGRgTPsSvkdsoIQ5D7ldxR2yWNh9lv5mDUhpnR0C6ZAfXSRPFS8 +WsNLxEBl3S9ebzIdcPYAx3wgOLbazzCmPGmfzfDAr8HgPcRHqTV8uIs9At6yvJCg ++CVHifN6AOndnUoBTf6x4qI5DZeh1tVtgBDszCljCu+J9mgxPqMw/62CRl8teyyE +6E9WQUr0WX2B8fZJ9ggXeYKaAI1ESwpqJEBZhFzLnjDwcmMm8JKVezetvk/q4K2M +a5kQmjUtEKzD+tdw2V3y9ojTp8QulL7qSIas/WVohJftDVSwL6oWmXJSkyRkRGfv +WLCvqK0kMsIPum6w1thg64niXS4i/cajcKh/ZjpIqQQZEBCbnHjbbnx8AiYfOPGm +Dj67oTR6ce3RhSbneA1/gnU61TTCDHcB3+drSIgSWTlP2I4YEKtnWwmfo2PIs8En +zraEliSoHgTJly3pFf3y3cz+oSYaBDd7BpKGq/vfRVTm6oTrm025qH+2WyE9aHfN +zCcH5QD0DX2c7Fmka5X5IgTVpN0gNE3LutthyWu+wRBXcye2Rvw9BLHbZrJblDuE +jEVOmL6xg3vUr325hsFZQF3kNoTC4kUKRZuxDtOT9PPLjTAyVJCTubkWikDQAJ2d +pQRFSx7q1p61DiJvktNhH0nsPB2hUoxPbsGvsVALzryzK6ogBirpJmwxRsgU0ewT +m+LOIloMWVyjpQHixJ3O8RVJ1Bb1ysi1VdP6UgCUrwMFVLC7DlqfsumsIz2alDG9 +OJX4TQmf55ykN8TbcBgjqNE21pD7Zds9c38QoD8GZbDTzKXDUxqzTfYIp3i4B2Ku +GjuSQecQH66BJh/lMdi+a+wwJVOrPyz9VMn8igreEcVRsUxzDe+dwD4Rh6qdooCf +H+Rr7Zzyj72cTXpXhjus6y5wpxb+4U6j0PB3UBeNzzQwHcMDkuKwQBmoMl12FzDU +KKX8dWGtjJUDwa8rnGJ82TvXnBsJHGO/9HcrikwVOKUQwaiWUJ2lbdS8MFliJgvX +of5TJBJTu1KPl0DRZFEnqO3/HvIlc5CQYRYZ7IAfE66G0KNHl9UrB55HfbuKymnv +8oWwzJXOlEAuemR5ynJA8vp8QjqYSoyhnDB4YCAUZIxDsU/cvWf2bHf1OtGeT8NG +PfqGfjQ6FwT/Bj+XgVSrSwDwplUFrx6EuzpqoFwhFLEeR7gxajECfpg55u+QUPnh +A1pWcTa7qbW509lPfI6jZbkjhP0cd9yJGdgu6PTFbYsPQTazpdH/lD/QL+gzby4C +WVm7O+SpkHhkVV+nTtnb6WAw81PezNdjnhRhmcP/XxO8zQsIYfU6WQWKmFrJl+GN +RIyfb+oUHadGZk664/Z9c5KPDY4zoosn+zOvwgPNc41qUg0UMVcK/S3jIYrsT4pp +N8Priz72041hqQPCKRtfW9iy7gS9hBXi9fdGMf3no+2fNEMNOG6RdZN0hDO64ay7 +Fty5NH1y2lBBvpTBaaxq0Bl+ovbcsixIVpSfOs9KoifrvubkR98a6kBBFEwu1X5v +sXdupMX5ePAaEOjcPttuYUUIHsiIaIGNMbP8pfPx97JANas57d3vqhoOr4fqR/0N +CTL7uLTsx2fpzYXEs3oJtcXEBmZlcDwpSYFgnH1e6wmjPRiEkUG3s2en0m6OtCJT +Yz44Yu9yzc9zBVQdK7UGVi1dt+MU/SqzH4EjnmCiZy8OsWgx82cuLvwxLmJ4d1ub +uN6XkABIsiTeDBzY2GUD1HQ+pocVSs7cD6WXQvwMW4LszlWC0RSUSh0xw0HR6iau +TVFNWqSFNAHhIpeTwAnkBkw1rRQkWJs2Od7pkd6qL7GkxQhoEQLNSH+Mx6TdlVsf +F640ushHnQLyzD4FoefiZsGLwK06ZcYqk9lJIO4PKXmtAKv9erbBvzWE2bC1Tfzw +RpG3yoi4G0yX+4jbCHnncBS8eGPdViXmQAA220rQ6DoNr+1bVRdJ7iB/fmKdeAGT +VOEY+sHxL7cvuAX/mXTCqoh925R65u3C4Y+ne839CmiA/lCMRxCNQkcCsTjlKLJy +Kxs+q3Bzx1A/Yb3oksr1cHCQh0ATX0rT5OTJbVFSha+XJoNfllxhRTSpVVZfU48s +Dk5LAOz82WHyK1rIS9T7zyozb2+LEc5W1jQyDO+/zvrRYDgxDoHj8fGZMlmdyiCd +ut6hKanh8C/Rx9M8VFTMlBQEEqwsGa615I9ytQG1DS7hcwNNrERPq05UW3jbAtBg +h+DZDFrmlEe33JkpyVSsYV20aEUK79SmC/gAK7ksOv9UvgtxslQOAUycBI4lOxm4 +Z2l4G4bg7OsAlnYfksYIdmkNdMOxwvOz41O9HttWmNyn52IDTYMxMh2QjsgSP9qT +IrL5TpBzgLkgADY8tpDLARopEIJEWYohqDr0PxtIr/W9zG70qmsqEZWR43K/J7O2 +eUsDV+G3fA8+73GccLfWcKrD2HRKbUMeBmVwAzQN1FTdKoIrYVMOcQf3i4n7o4Pt +sfhaQGj9O4glhJ7XqMSPDxQaoE607vBUuDAHaxjMKJxw/App4dxN3TurUDCXZVUX +Clxhjvi2M8nGhKcvNAtY2yyIvHULwkw2TgZfyKnpTaoktxuEdFYSBR2FuLP5FYpj +KAKK8h9OoaVZGWoOy6hIQvUxOGnp5w2spmSLcF2v0lgZ30Mc2Y8ptpCfJMpRCQkV +jJ3SAYU6WjpAbAsRGeEWPuh2dUWP7fEkPWwDEIahtiPM3DkzhX9el5HGbkBIqvf4 +4rUo9Jk+ftAtCg4H9iEaABWL1dFNSL2Z6EcH7XUQ/X8LyUaLat2mxpZBbDwC2U33 +W3XetPVfmaSRgUhB51wBDmDhQwe48hJoT49Dhl1P6NoHOOlTsUU7N28Kx4ZtuWEv +DGIfGzjJ0tbNAsiMVhVlD1OK64TVbxhesxK8HN/Qf5KIequB7WdFJLzsatUbRRN8 +sKlmU1z2SD/rjmoncl94s4fjMDYmHNCsTUPkfTkC7CUiRPjcHKIZIQlTD3LDXFkm +Y6y7l7YbibzwNXlHcfmprCsQh13WEy1DGZmygwdt7g37jINbCe+znJ7wAeOJPix8 +qiHp147iebigz30BXdnjq/nZ8KpRVCV6drGT52OlZ9cRwJymlYFtpSTLSPt02i35 +UZavC5earVpsdrV7S0kzbp5wOkKI5mln9zI/uZ9+W3pBPkA686Hsl+FU+O9frsAz +s7TziT1e4cOt/G9/JOOIG1c/82bZOtCLHnp87XQ7ylG7kcKY7reXsi4EonN0T8ZR +1QSfQXeaPsPYC42vVr/RZqM11Vnx0nf+aQO+k3w7dxmxRtG/jNvv9DHt0CYgqQKO +RfB4f6Nz8B2T9laCtx1yDfthKGbhbXB8xEXjXWOnJC4DxtkpPnb2OqUl0jD55SHH +B1qcFVHe4lcQMKE/aj4tradez+xTZUHFxZls6PV60DgWKwZ3Thd3FwPXOWeckSEe +FDf227nLX1ZppWSQenm50pFDnihF9krrK3qdXUxx3M2QOVi6FB+XhlecT97HVTxA +5OOrCIFdm3JhTIH0bwULoBYO5yenbWOSelzFK/RvFVxLPtRL/UM6A7SXb8Gnpr9g +3SPX/TJh1SizRpnF/l7QypoaOLvOI33lBQDbn7ZFDDqihc8JGGI+Vrn9QPYvMkU8 +JjExZTNFUHKAMJPjmZK2czoKXm8JNXFLoBwzdW/0vjEZX4sxnVnY5665YLJoaBEc +yjNX6MDAZjucbdyN9uTcP1YGNEwCiCJYgeP8V3BnkfHfdpNfYKHiIJkXIujdCmBp +gP61OojAZdFV/2CGgXJo4CdiLSEAbbTGzm09S2JvM45xAX2VhxobmZAqY23c8hjw +JoVpL4lunbm2DLSyfV2773krVLY4GcsYpJPn5uwiV0n54kvDK7cadHIXv0+cvzkI +r7k2bX9yS+JzqGk1AoC16XUXW4DfTWWYV8g468SwgkP7A4G26ctHRnlKLqODZ73Y +oimxkeceL/WzverfDYG2CaVtqMNIoPfQJ/dmaojuLbpcrGqdFOroFmW0h95XcmZz +m0FRd6uqdi03McsqLW24Ah5t22NkeLsxrwqQJgLy4WBCBlMvZ4sh52X3vLrQBzs1 +vlrHLlZ64w7j35JFfD76e7rS2BU2OfpSo4xTrCG7eAYeb2pnpCU2PyvT9fKHVMEl +6N0mZDq08MGwgxSlsrZBihjbwM4NR0DhQ7mkjkZMHYDhU+G5s7J3h5y5cw/hylXf +qHQRZl/g7L5xotEVjhRqMCaPBYqTRYI7JikQxOim8Gn4VJYpxnTrr75a+dIey/e4 +NzOM/d8LJfFIl04Ii8edQzbVyao9o0XMRijdNkct9Bhhn2WW+IwvnbeXtyI3DXJx +zX7tymTssPRcWqaMw12IAOWbsAwqLhulB080IQ2uJv6yUJkQJ/cvNf8fqkALiOtZ +VMphMB5fTRIyV5NOGyhCHStg+9mCW21Sab0xz3m7iDsJtTlOhagMIZHWe5egEYFC +9zC8yIUF4x7IKo37hHAZQOCPcbsWRXHz985p+99xV7ZqSvY9bj6dt26xCCwOw1eh +O6VW5keQVNOHQU315hz0GG5rXt5qGrCJyjya8TB49VSYT8FZGaUS42taV8JzH1jL +0ytRpcjVpNN+xvlOJ4ay3TqAg84ONRwT/X8kCmRrJCGgbpdlh5Vd4LEzE+UISYVg +BbL4YTmW1GV2QTj5yZWttdjhhKCps84eAt5hnrhHYuMaiYHYvOSeOP5Ww7Nm6gOs +8kGv+QClnzFdL0ST4OHL+eYpd5VKOWdc9uc7eJSburqwMRelUn4N9pCY9GyeNMQ2 +9bzhdPbgVmpG9U1uiqF0uD29juyPX51rJNbDtA4sO4Gx6BeIwBcipyOZZk/hsaN6 +MLpaoEch+TtAoPM/7T9mdix77+1WSqwP/too57sJb3Xbh0+VvPgOHWfi9SKqtlXL +++r24kiLP7Qu1KkFFzBud7EYCpIuGvEthcXLn06LDFNDEqvFGxVPA+Rw7yjiPu7O +JvqThOkeGK0XUiy4640+KcmY1TmtOAAM/ol1OgGougCNUlygHopz323rs8DEAkhW +iX06UEIVG3MEGVQaT0B1QMLdeKcttLHsjPSNHEW5NkjyxRx9Fxvh1xWtdAf2q4gp +1TkbxjVcJVaHE9Wg/u68GVRopoaCfKSHKed9t6DbjnnrtF63o2jNfGu3FQmA+LtV +ymEfWdAyGZnrYEYDt2ch9QDGIczM8+uIbLzgL+ShkXYaAAi1WzyD+/InwnTn2R5g +YXar9s37J1LDq/hvClVzGF2shu85iDG3N3nd0J6bMs8YLe9D0leC8Uf/7QuXir62 +jcTnWDsTmRhi2FSRBuQGV6PY/RO77NyPM8Ftoe6LpjX0N99YoUrY7XmJl+5kHtqZ +IachJxpuOK3ss72qB3gtVlNMJGkxOqdVsTsgCoh9nGlEVrZoACq+MbvgpfwKxGT6 +WkCPjc1r3F64/gCaToia4MFU0KSVIm6U78zkN1tDCB60Ck4Z6LJhRz+Sre4AHksJ +4aAjqpYN0So/ZGP0yrsDcaK7YkEF6VLaGdr8tscP6IDratq2Eko5Xs9Pwq5G854O +PMUNX0IIHi/+Rr1T5Avbmycx9C1ibspik00vSvGK75CBuZuepBrjh/hP5KHj2UsS +gNQXbcymTMXLVd1rCJLcx+4xPMpPq4SLq1o2Sm8l8FytTwIfc2ZdF4py8DEgrSzR +CMg+IJtX05oYtrdxlI1h3zekHLh4CGJeqQjk3boqSYmnlMaZh9LN7GCCSsRjN+Hg +iqtvZqBPItEoJr+PK8bqQgte0tD+Lrru5bJX0Es//FMPbSWkOoor5BVALCIZTPNv +sHwgsmH1v97Vrtypqw4UHvOHFW3nwRTrz8O+MMigoJL0a64dz+r4CvWGdyInwa7E +lgzkv6Ru2fucH0H83RY05vacn9UpNqYeElguZ/X5dB5kmUStiQaUNfoJNg0fEQ4k +pNtq/p8oVsE127OSN5sToT9qsZy1k7KqBDC/wu2Aszb0QtIBIFvIEsfsfRbYbr7k +esUpq6PhxsVOXV3b5j2h57Akjl13O1awGDeco2n9qLkfTCTgfQWDSz5/rXmNF2nY +jNf4fu8Zi7HTAtfJlJmWON+nQviyIK+rurVzFzcBAoWt0N648KAgBwPN00fSamt+ +HDr1S2sxCiHJrXr8xknAhX1UH61K0P9r1YyvHRySDZw76CTF56CKgu+XKkxxYTi2 +yARGRl/Av0ahbU330pB/0m1IbtwuVLPf9xbpdE+fprd/3YHXBcXrjaKKutJpTv1+ +lc6noHC5i13XsdX6xMz3eutZivea2dkR/mAlD9rYSzhQTkglleFy0lZ9d1Fv7LD0 +6kA3yp5yZrJZaDLrKpnTnA7F9iNb1kaISxHoM1EAZNQK1CXA/ov+Las4Iq+BFkKo +/V7lMYWJe7/xeNiSzI6oimjhBeHsq1wgJOk8scRGEkWp2onXfktxpP7wMzACSznZ +mEGbaiegFcr2slxtk9y62Hpsqe1++GiU3GvYIlsO75RteSfz7bd7VKllbTmaLPJc +3xbpkoEZ8CbRlhhSR3817S/1f8bBpNe+Q9uSHxiyLQV8H+xfjkW8mXdKNRbn7Qso +H5ncCEs0E6RxkDrlcGST/0j54oJgZ9JShDQkQUwS56O2c23TqNM+Ky6Ovxtm189W +Kym59xJNPHjb4YSd0h2SCcoc/uw3n+EojQkZMwMe/3EtCHvERegHAuLH3fN7pvka +vT2e098uz10znQXmBjM8ScYSeC4h6ifzdED3nM3nNm/bOteLX87vG6onSijMal/1 +6geXZ3v6XhhiER7luRAoM2drLUfacK6jqYL/7g7DMi0SitJRgXdb5+Y2clr5u1Ft +khfDp6ZTlIYwvdtmELrM6G9DX2fT9D6FTDZv9Mj2YjOT6Avwx+cZ331U4cJUJijJ +QtBuphDXyzuNBLaTDH2O3wxC8sZdpWHFf22I0Lhl5CD4AFDyUb22sNnnmodCmA74 +xJtBqpcAOVc0LIFQmGHx5zC7Jaf6EjRKTAwvZ2B0GyFjJoTJTAlU0znezeMMJAiX +kkmTm+lkNdi92wIix5cqNstDMv53VR6JTeE/YCUUpZsfIXRKOoxGS+Ipd1wZw3Ru +r9RU6+904yYdyFMNmoBXIGFO7IAFk1SCCPjSDqkSkZpU/Ag4zcBU6RmVK+Qmem5t +WLaZ54dAlPjjC06VJY69H8CR8Vws6b8OqDZ8CDcZDFhvmawp7NJ8sWRIjUQMj7/d +Q979JFzDKqfvbk5AdgSc959IuKzE+oYeUFSGoCQ6Qvntwml1yLV5t251eIl9/RZs +29wd4p3i4Q3OiZzqxVPYf1vGxInn6nWT9EPQQxYRZT5XtTSk8KCLVzgHuL4MMEB4 +qW2jUrcRJDCYVQDRrBlBogG1dipewy0Jeuvj8jPwFaUdIqKxO9iqK3jiig55CR+I +FberbTPZr85J8nCfMyAeEa1yP955AUQpkDk97nPF3MNdSHSzLTxRgi30bPBj3JF7 +3XC6KaOBereG2wMYbMjdg5qdKcTKSBLkjr7ZeeO+xIgM3TB/8xlHdZ+TmwvPdA/L +G8eXikhbNQks3Rqp/eGwi5By8/w+h1u9SLI27N1QhUINr7SVMM2V+7fSZbH1T85f +pLJGmi3n0KVJgQKkeo2Uet4Sv8lMMpAFXYgbXcY/Uk0qGBgSafSPErlAplnT1vXd +/8sz+rcOmOlN7PfdzCWDrYnY0St80FB/qbjBu8M+vuMKXPO+x8itnZpReRy3A+kR +ywpT/jPf+2aEdtf+I4W8VrkaGNixMJ2/qe4MmRRnDxJhdTHbvt7GpB1l4kwqp2n6 +NWbqoqineTO0odBvcTkXnxfnfywhTEWexY9uMMSjkSD50cScXgPOM4E56tvUnL+w +Tv/jGjH6N3IMd0yGa9Id7ajtbn1QAOzXvGHBvWuxQ6fyKnY8qOxQOP5GiAbKd+Oy +OHn60JuXHTX7YpNl4WFBKbw/o5ltHb6xeT6LszWpX/TR7w2CekNJo/5Gxh01wt9u +g9Kl057h2u2lMOEJgq70VItJ99VW+tFKY0o8l9LKyJa92ZQX3XsSrCQ+nRlxMCKD +r6/KZWWo96AvcS5d2knt+bBJNLmYF9VtS9CNzBL7FuZkQw16vR22eANYSfd1Ggel +PPHtcFNQV20uzqjbj6TReU4KUftRlVi/+6qbFQcifMp0i+Ax+dq75f+qdP/hdNeF +cc8mnNfOdtgzvYUEdHErZa4cD5FIvWpPmCna2dUDyrx9qGnUcM1i7ZPuPicztytl +m9dO70SEaTTexJGpHABSBR5s+COzt3ZgbzHaQZRIBQGrBmvxxVKQythOhYB5+k12 +XeAlHYjq0tK0AUfaEBXGL6Jo2B9dGOA4oVZoPOr42JmVSCTiTnTqQ2nIJ2QghPlT +HM+IiJ2EVQxxK0qUzaGYqzhlrRfmtBSGR0YUSMxdjJ1qDghhaVDFc36hvwPHJKh0 +R/sjuL7GbrtsrP0u7aHym/WW+kUMzjDKNS+R4PUd40L13M4NxN7OnJj65cWfc4gP +5vTPwMq28CEM8Bzoh3ZM3Hx//iYgNA2JyStsWh7V86RB6G4N5eDyoW3+Qch784hq +fyb18lNgjhRoZItQqG2/EqNfZIeobyVO4703Q8arNS7AXWeFD3dx9DVfzQ2/f151 +eebY5tMV9YSnxsvLn8y1ZWa3J2ScYLOPMRqxx8wFAN+eGdnF1UfKm/eLA6TIgrbs +YEpVk5KjluTD9b1lkuVadmyOBV+s2YynmbqZ1hg185TiT4wM5YRcPmZZXkXkOMAo +XLX7wkg1XAU+Gk+P+aPKNZeiXSGsNN0+7xreyiU/x9CsA0P/DUvQFDcaBZxMQKrK +dCJ5XrsiPZDB0/xCztaMzeOHLNIS96HVzJRCH2JgHBrWXIhBHPKGcXMTuS6yhy8V +YjMvPfqft5RrjQXMbz2yv1lZuKRb3S0DM6W48DX+D6jbU5Cw/b9YeIZwaAViCl/8 +wqFo2r01Eo57ELkhVes/KJvmiMPSzOXFYweUzgPGYrtO1yrGPsomiPdd9NOVy+eF +hUDZB2EgM1+u9JbfSLQIB0M0wr5LkyCksOXSnkaCGqbqOuFljwoyTPT6uNV1JffH +d6T4sJbWLkK1eUsUi1p4wUpled3kfpKxAF0z8aC65f4+5mnlc3iz8a7OGzVJLIlT +HrBl7QBdPxD2aIKMrUriF7ezrWNGS1FaGOcIVmlP8onumsY9YgCA5cOa13bGCunI +9niH2Csr/1/n1M+TsWEDihOcOoBAXku4fWtg7BqPC/fyd9E2f53WPDn/cXkUJ+EZ +NChBYytrfsISERPffrxV/U0ROblm55/2ReYVT/Evs+INDqlqFIo7E6CZIZ9YDbyn +qY4OW9s4BnYggwVoaBAL2DFI1OBXic4UsX0RHjenEQJCsXS566Sn4/GbDlE2tp64 +FM7rI0FZGtjeZEHnSJ6p2905VrxdhbxbZ/L/CSQUAs7ITbJqmTDuBgiZXDLQdc87 +MtQgSLienj5GaPDS+WJd5aiTl4d7F03+bSfBl7PI79eM73vPtkZ01JbQ579yBENE +iHzXLO1KFqMCGWAEFOCGtm6ZYeazMcs2gHqFQuRbkZT0f/XgHlA/2B2Mdlqz9d4T +ieKLBEIhgvdQaAZrwjW1B1iKDI7YcYKA80tuGxjRrKALDjwkwnIxpd6ArY3yzmzz +VeVUeTlAd0JKQdIs4HljYu4hPihJKqpLUbWeZV3jecNdi9D7B2/VL3498Xm/RWVU +vYAYUIVAQc0+Ga+Sm455T9M2hX2Bsrs9EdZWhYeE3uFIPOt4Gna/fuXcTfBLDN70 +XXJuTC0uuKkXx4gTbKQAup96H+l162bQ/J2tobKdBGOtK2D7whGIInCPAVMIqvfF +/U2rrhbZw41VXoQCWNX9CSeWl1+Q1duPVF9fdBR/NYS2E+PNo+oNQXzA4n7sgNlq +evupqVx07PdLJgddA6+pUUW8ZzYsRs9kBuoIHmU7FMn8PtYYIasr1eYPE/aiVyZG +dxlWMuK4t9YFnYsYgRx86MR98+gVQklBBY+91j4nQbKFbskuHHY5WMVxNSmB6il9 +PGkWUAdZf0U8Ar/rwKrGzO7wP64w/QdmxCW47mvHlEkxpNWslXFmhsBIKlmowVCE +LQ3qc8NFuiuljpd/alpgqiV/P0uYZrMpwfohKp2WWC2GaPPuVjg1PR0oHSRMiYN/ +msI5/HB90Jmk+sShIAAF4vVkIotkwBO8H74LPrG6Ji29guYdanlwsD2nCaVJ0alQ +4MGiGv0wK0gZ0YeRzPNFolm5C6zONyU1S2Aowx2j+J457WmH1SHWf+qImnmHmeMs +kjVY9v2X1ichn9wguk8QBGMmUa0CTln0B5R3+Y3+kM2XP4X7Xz0TkV3h3TCrRlSp +HFPsx8UFt0IutcFzHwZWFnVQ1S2iBPhuLNJEAHWruaGsW1jCNBTdCgAdlZ4l5kzf +k85frpEb/CXf7SURJ4RtsMM7rCzkmF0WRLFijY4u0HWn3qKUgxwdBST4N18McW1W +6xkXHVLjSIHmCecCcuZWjNNH5zbcwY+ys6pKH8TSrHvSMCBItxM9Hr7bAdBS0ZBy +xRzYeprPrCyPsw4j22d0je2G74gbOq2TAa7N2+fuHaNmhXn6bgm6gO8tT5qapyKx +Jhy6OH/6xACap/yJC72Q9TxlHOv4+R7q9HHYkT+EO5CF1JY2QDeldWjgjghnHtSJ +/8rmRj4slBTo6lvERZ8seVP3wz4hJJ2qaLqTKLjIX32/ytqcNnmHZ6zpp1lJeRLQ +qMlwwXM7PNPzjjGPn97S3R0TMUtlc0bG8hfOg6L/UxDMbCnBJd6ZkGjVQKj0KDbW +FUB8131ZU6EOM4TgViHThVJ3pI/zFiN6WOMX7Ujz5xXKmZvT1jGigb+K0k3fD7Aj +r7sUTm8bSGVSat02N7jZC5orFH/8X7GUjeA4ce3TuknLIugPjOqpKjaWAvfvwaYZ +hM1IFCVZjr++AEBVE3WvrjRLNe4a4mcBN76iWjF0wI3Y9h2fRLdGH2HFLufFNS4I +nDMbRMa/XK+pGXDj6dOT3ufCLWYr4ZefGa1x9UJWRcgTZ2coJ7EfInQmBzlB5HTr +f3iJM7f8624ZBk00qkiurmzlkY4QPvEIpFtgWhQE/k3W+MUMn5n/7XFKDSnm5Rbq +syxItO4QUDYJS1nBYbM7BaoJPqbphhmSwwx1NnVX/J/DIF5ZcVV/iV/2IS1uVaAK +db1aktFO/Z1YTxl7afz9uvorN+PjJXWhi28l3Yp25+ZiQVoRJb8WMyoqlbyQYhnn +Xf+4XpnJrlobtqLfDVHm+37BC2SlOxpG2rRCho1i0+tN2JYEXdPHxXp/UITKSQgq +5HGqoekI5fQiKK9JHGznofTTVEk322wzoRJ1cAX0udKwwnuNo4z9K+NcKn/y9gSD +QHeA+zvF69NvtrcQ5mzUuLPWxgsFA3A0Ehe/T4QpWibIpigaqAnZxIFI880ofoQ6 +Gd5yIUhaVip9uUyYT1pgx/T/Tp3azTb9CVAuu39bxDhp0HellLTtxpWm4koTO4Ef +G30eeVM4Cw12G0f55rHTB/VGpfOIEfXUredXTvKJ7a3Ft5qGnaRoeNqYernEqCDZ +U1itOq16fABFpMNRHrqcCgnCbsb6zsxCOzyw5DzprWeXxaeOONYChIbDZPDREYjC +0g1UP6gvJQf5riKFVy0V5GFq9q2QRYDHBjjOQkYQWdTG355Gz2kfIZ7Rg4EI+SNY +9YnSR5EhmTbQ4kB/JgQB/rH5vre05820V4vQ9l9mRwm370H3FT3JmnIErRb/Zi/G +/n4LMKLXjgPh0eROv4QDGHVk2EG0RXtzcRxN1zY7TTW6cEOPr3Oc3bmWD95Pb3Tq +6WLDHS0qroeVP3VyzIBjsBLwUIYtGW8YDrKHAMLrJYk+2W/2g6Jvd119UZ6THt2t +2TF0xWsIjd5StZ38wqIInSBoAJ9fxvSfO2Hl9o+m2FjyFTHeDDhBlW0QTftoBHoF +YMpw8Tl2du2T+IhY9nsUBBBgNxUaVHekGvFYUd/4tfK9XrsgL04UCiHUAwasSjTo +dT8B3rhb4ZGlqk8lQhM++YEo2SHXOxAw9qfhk8kFHily2QWW/+AZ3IL1U91Qewtb +N+0qiCGqMhlBqZpIBaDgR7FpaTOnnxxtj9fZfFs925KZdZkOR/pLA0AvKRNLF5tm +PB0u43FczlhVRqq/RfQWAujBU8PJe8oQBhTtO1SO9jir5XFDZbXrf3FOKRwxXPuw +/wMkQfhYENglHIuWWmQrxq92+L9iN2RdamV44qz2Nt2z2if+2lIxrD7o+KBvS6YN +0tGxpCQ1PIjTktM9d8L6BzvIic/arsPcNj04NWZoQvO9YjnMmSYfM5O5hke18Hrh +9ZucZlhKW69aautOf+/p9YDlYa2R9glDWFCezB1uPoUzalFC4by3PgpEFphKPRjL ++ERoxWdm/7bPHCIF9KfW7nMtcoyq1qJVH33UyuXhDvYicXc7/nk8bsHnEfiaOxLV +oUT3cJlcZWdhvvBvcWmvQUM6Spl7i1lkDgxCKGSZrgO+g3lzxOEy30YzEWaAu6Qi +SixQgpPuEEDHUUAUkOFm/5IO+RdAj5fjDF51dEn+S/GjxjpSlYTZPhHBM1Gzb9CN +jcvSMJXDK+aa49FpeX6nipvLU4ozbptR8gg/Hu/bocUdcnKUdqjupqj2aNw5asNC +LYY3kB8Z5PNWdovxdsGD0rFxKNaNAalARaJEy/77oXU9bJY/N+zzDOAX9qh9/8jJ +KGI9MvOsysedklUPxQavW7zUkv5KrlaO3h4hDl/ZMEZUokitNe+G+IpQ00ddKwPC ++tFJBBJoXBOFvmxrCgBAHkGLjGoG1adOL1PYUbjEWEMZA3OXIsljouBYm00PnCGS +5kqKjuOVQDt+NQwPWQfX4DAMdNrJQ2+FdLKJuEnc1F07XdG2RoYOJo6lXWMVrXdE +d5Ln6BA76LOuqNQW+2m8ZcA/nwlUCuFPsVwCqOe6nNxD1++FmpVo3+N0Idmeblry +UcPjTy4NoFXMJoWN5t46fsmorb91STx0bdRYADBcJzDlAncmM1WsSCVDeUBLZHd+ +GoW9PyGYJYG6T6TtXtpdl13IvVcRQekuoIbrHFATCG1frrY6Adit33tWuqBIxUM5 +YxwTHa+8BiNDY2agbypwooz2VEfzLoZkbYU2AOR9of1t/GjmGgIDsCynEb873Qik +Rd/AiLsWdotRu6/6BIgzPqLte6gynkPqSlAVsy78Ijl4rwfq/odZyCi2XgAKVq4h +Iuq1mO8wdfiDyP02nRtWhjWf/DGfIoApF0gf5rKfSGlhYvJyyRmPmnJhMBTFYRSM +cqd49Z3Qb1z/WIFoxIPg5YZ1rodeqK3IGSI8x11ujfjLs9tTLAJtAdMCOom7kvJA +UCuCoctkTr4wVM2fqlpgw1FQu5g43KmAfC1oAB6FfRy7udO3AmIlnYYRBu9KPQ6X +fy4q0/DqjCpTdv+y+8+FAo5RDESX0EfXtWQGGQ1oMvinrWbqiLvVb2qK8rFPoM54 +uVqweiZEzkd6gfOenAHQZJplrx9hFtizskY3IRVhbDyHJfs6U0IhehT6cxddEFPc +U4nLmpzigDjvRfeDln3mir/HJSNXIbFLSn+VdABnxJcYgUk7bAKNT7/pCmkUw2SL +zNvfQh0hV41WIKSeRsDwQRKIFocq/pEcHPDyRPLt6uyzWilmrCov1NMSap7NCCTT +smx9DZCgCSB47nDMdSPOA/8KG9lAdrGEddmLPnpxHQcK/qV3QgLj16yzxmZWSmIS +QeD2NGXHuchlO1Ko4AypcwTsZGLeMo7r2OGeX+0N03bJGK7ZG+dKYUJsk3ugAsKg +q9szuvJrqbde7mRCgppF0ifi9GxGOknqc1E42kU6QnsPJbvje0hEUyKgP7+Rmwfe +gK+0ACpnrzQE0a/Pn11Dv87sWFISkjnkzIXLXQBSPKWe9cIUG3mmFzsRtO59yis3 +I2/JYV5erSCf9/tMGO4R/vgZxIuEc1kb81+txImRj7tRk+hSsWSS3DAV+hh26+/q +aezHWMSJ3TqZ8X32hGywf9DNxzsEQkIeCISSuXz0ySTnw1vcpOKU17o41SVrUF9X +4ukthmOHo5WthxFr2pBZ4ctkrGX+YSSA6pjK0UDZYQgMQeqUq5XQLHuo+2MLSwZA +gd8xeZg0wjLEIueyfMKfVg1b2+xbxLsZnDJpkUzRalOpZwIZHViHUNtxkIbWuQDD +T3ndFG64OfIm6K+xtUDFVsCPaZvE/zZV2suzhJpaJ3CDGwhMh9TtHiwEDzFpP9w9 +UjGTiWO95ZJb4xq3QpwRvREbmhgaT/fHK2XNuUSJOsXRw3E/vJsOQNcsETmS6zC5 ++bXNx7BGfNr31qcQ6E+T0AJ3eSxCvbyxtfGErKCvGdnISN9w2BZAg1/zWqet4Hk+ +DbWocYZ9QLepoYVH7sY7zsVEc43ql4IrlH92XYHoDeQgDJ+FptEsMNL2cewqoV1U +FfzKfZvPVgVUpcfIvUnPfWanx16eLdt6pVW9brqZ9P71xhVJ+c0vuItM/w0vvCHe +70Qc/OYGI+DYBjtwKBku0rfL7nBFFI6x8WiJ7Qhdi6GtsePW2m3Y/TWdFXT1e3Us +ZlNgG6sfMPoTRogmOKr9da7t1pKTwYRBQH/pn9zYnr/wc4sjnG3dp0PJjcHqFj5W +uf9TC6tZFvjzgRaecECATTZ60DEB2Ot/tzTbemgeYB6GtUrj/WGy6CRjVvokPRLK +r0cV0UXk1czoAgP9vJmGmpKTbLbEgCtBP+2pxuLk8lCWm2cQPYVtxPGBcC2e+FwB +380LSXmwmlUwzl+yjCxMZIgZrGoFAW3w4yAUfmee8qO6E6p0eSD7N0LjIqIOxy2f +fb/bB8LrK5XwezX3Mag7Y4EbtHtgiFX9PyUF1kW+90jZEKQeJraOrFDr3RyUc38d +1afaqBm+DLzyey1eH37sdT+/6iW1Gj/gJutw6TODri5Ie3tRa5OnQTHC2zVDBAHG +strqiF+p4PGUvn//iMicsAK13ouK2ziJtZhmAxIVMbBMO4xm8/w5bstrW/UjTZBB +7b4IKoLQOEdb0a45TMJTMvcLUM1Nm1UfGFQZhoRMyVkQ0Qinj6S01VTOi5QMj0px +ZSVAIVqec529HaHlNQ6hyChIz17T7znH4d96V0hz5N36IMYwFT7h/fED5nJEiSy1 +OAXqoSajncGKKQSlb/YD+OBvh+JxMcA8LZMgr39Fw9G6DTSJTtJzjIDjsDXdzlNg +PJZX0Mi5gePStWPKIEHjF6MK42PZp4yt2fUeoiMzw4cZhFhZPl2e/0ofweiLbWK0 +PSK8o/sE0ZtjJfTAvf+DJcxiSQHQ89fb73tGgq1zfALTOJY5vvQFr6gCZ7mDxT+I +/X9H6igFMVtIqUvYdH+mqjnPFabunJVZ19wZeFmiGoFBd2MpmJh7ab4pdimmHErh +7WHF2khRh4BypFjmMrwSQltgp8IxziRiu+TmzJKRElvQst4xvLGSqI++5bpDU8If +d9/aEMSuDDFzpGNDdNMX40/MczRPrSqCc5JSp/vcGrQFQgKJFPIWnOGz9YdCR5Ja +oonCwOmekLiqKLqJLFt6G+w6PFXfSYdNuDKOQarfvVHf90z2Gn/NtgAURUifZc1j +ZJAlxvpyVEtjZKd0QVJ3HcdodwuRvO+CuVG7l+rna6n7Typ9bAGluJzmsTK5UefK +Hatr+c2NspScov2ZIXrUpHxFpqGnAbvAlU+oO9wqnIjWGzlCtdIZvbTfyxIMdx+4 +PnYqwu+Rp/5ilapGf7jEi42RozI0IyipwKD5shPa2s9U/sJSxIwzIZ7JiWpJibqe +vpKoQHW/1sITb2FlSWN+72G8MNSBpRDGoE0RLNkgK8JhE9yDXFqJG/WphRhPuYHU +UGCNoy+SF6jO/M1XsAYUhan7sO8Bw0G7cbpnBp8PhlO5wa4aDSuWaB/ojfGk5Ti0 +2kLTCgvYaNq9Yaj1+lkLRj/j0MuxI8qD0DdyroUwVLa4AQLryUp6LuZHU1jb9Vni ++FPt0a0naYNAeqLXrCF4A/4XtHGMPdbP3FR2EgFzbCj5gV/b9aARimG/p5oBPiHv +EkYQd9Q7xInwYFp39nEF0l+CfqzahRhxU+6jNA9knnlJtUiDC/S2Bk+m46NnDgaX +GSAxASWqGoLX5Dpv5/AXYfECDngx56XncaGpn9KiOYJeq868WfowECeF0DXx7Tfo +nyN4FXwurcD5XHSaCcKk3D9HYDYm5Ax2HvponNFZwGFkvwZkzBhwW418MlzKB+OW +iI7JWBtcd4TUfrtBA68V9MMSnyUnY0pDficlKc7piOIPYI1WgSgWkrro+NwM9k7v +ZNhHdzjKeRNvn6PNz8dsTAfKy0Yu5v+23TKJfkj+3mFRlVUlbWMNUDCtEvkYp8PK +8z0GoQslfMGt6DDq+/w762ZhOMIw/5Fv4ThasRgWsjRKcwm7/Z1ws9RXTBcchjcn +RgIBy8aaz2BqZPAtMFdGG35TMb+ayCmeRhNLbLU6+EmhH7iXY4Hn0/crDToCIV6P +wl00ygahdr4silr3Auy2f8BDcXZO35xgsc2uRYQXEU1svF7Av57q+abTRGRwrRJ+ +i/2SAnwcegFQTiZGP+TJgCpXHo4PxX/CsRPe3Nucf9E5NRXZ7wKivjH9ePLqeVWO +0x91VCbkQM88tFuRluLc+VVFyq84qy8QsHYNNmVPou297rv2shyBkwAZNWyyjwge +JDRLeF4ptyfc8iolyYYAy3wGOc13WyTF0IGxR+6B1zfbawXd4fbrEIPUYQf9ZIl0 +9dQ0a4JPoxR5fsKjiEDd5BTDryYVZ1Y/c7vY+PBqZxF8o0P0xCETh0etaD69a+Zo +k5COd/sgs6JeKSdd7reiZSdg4R7BXzRSZzwSQEzde/sgeTd1WQC8jcCSJJsXqYFf +RV6ccuphqSJe6fCPTYEWwJZY9vEn/q7IFAmA24wqpb+IVv29gHfH5CyqEhqLofMF +SMT0mwpd+Azj7QYfYfaiLxpVIPCbjp75rAzY5t73QucNVRjrnyDQofiNStzT539l +4LjF/LXg13rEeMRinXji1YORPff5BM4MuBi1G05FWGTz0/v+jdrtF1N4syq/xpuV +/KSmJHRLNFsu40LsEDvgs4t6SmfR1Ywr4RkBifO1o2X3EXvr2HQJnC5Cb/ZUAoqh +UVWKtKePpJW754kxSO0ec2Sc0wqxIF4sTDILa5P7iyfLea89MurXqXxEtVWQnSrF +7w/Im+nzPleNzer6jDpweQDdi4aoDHYJIeJlFgVypAGxYBAGtFnJrY4HBaur2WW1 +zsJIlwsYvXHHVGNg4e/RgtxRsLOKo0RgG1+1VZikUVhnGW3sPqN+oIMmBkhHzzLB +g32NNZi8EMnnrUWvE/ie6oEil5jfjk/R8hWaKwNhBxFNHmJ+8eQ58xb47Ma1UIro +9TGnRGVyNt6Gx9cNh7BI7+18j+oSoaRVOAy3QVkB8MU5DWoZ+LSJDO7jjb/Ky7EG +rQQmxrou4JLUTJTBrICB+zzJeUdrmfteubchQTZ4Xb9QfcWpqn629taILzpBgZ1R +ucJZWm5f6Iq2bCpmqyzt1HQAJLIkiBdJ/D3FIX86rXV20wXvVGWP+t+bb+QNO0h/ +kCh1CoD40kvGhn9qNbdVGlBGAbAvfPQ1p9BXHsImNX4JT5NG1JSmeyV+2rXjXoh9 +qCi+EPnk8Jc9g4rwb4U98m3xi7XqfIq3quHvHoYmQT2QitHOGnH0m8Hv30FIRL3P +yhQ9B4duBB9ZLRWY9vTPJOqA25sghbmAAoaqtdc8fLP8myTzqwzKJNk1lOOg8ZqC +eK7qTKv6cEBFAnFwRDAKS3FRkKmqzdVV/zNu2EBNWjdOyKYGFSR5AzzTLQrfiyMf +KFaYCyO3AOxALzxQqWXiOmvu51+kaK1gRMgkp+RuVjloqVzpF7lagQla188oDKxi +eOufe7VdxCnQA/QVXZZMaS8zXZ/UAmubYHD+q7Agec8Q1aV6qDQQywGW0hl8duGm +j4/ji4v2zs9tHN0iw+pKm4iCMcPMqPtFBN8rNi/WoTJGr+8djKX4OYZ5YHYHtrHM +P3STOaKZmKPnNgBbj+0STDbUwhwGChT/N4siC27X/SYJLdUsChquGHPiG6soziwR +ew97alcNbGlxF+HHDIYVUpVd+8lfhCVm5Z6oNVs5uHi1qBb+VXVO1EqAq5aukndZ +OfT1n5zehTasrlAsck3psO0cvSy25RuCjNYf2xjkHUdBaiaa65t4FHrbUNF0L8Zm +03q7RjxxPs8HWE8aVDK1FbX/Js8T5uW8IVApg0EhZoDqL8civpt7JOnkiHWTx9pk +1ESwdv1HEEBvyZdt+rKIGPi+3ls72t+ZUPO9MxDA2vk/rSxSenCEYLzlG/bHOXKs +f87qMHSqMX35AQbTEhJiLeT2Eh9M9Jwujqw1zn1bYsK4y6Q2JvfYv427a04P6+tI +AF9VNny5NqwyTqheFiz7452iJQIAsZDwTMGTPJvMAtSwdkZYJ58MKsLhg49fPuZH +Bv4dW+qhuK+9Gb971GF9KK4dCbUU4ySmtKtrGtkFGgli1eTbCZ9BKbKkbGIf3IHH +wg38FgSLE9vfhrK09/zIKn0q35exSrjygKbDP1S4RNe7b8SDciUDi3ZUviEEbwwG +bVMWlIen2Zba8m5NKPOxzErDYF1e8tGG0WESeMf+8t5TqPoRZTFfmWVV0199TkjA +YAOKbKWDnl2KA21A8JcML0kFd38JifMqO8Rv1heQJBZuKgsC98pXTzpbe3K32fDG +ooxUS9ayUe5HOJd8Chh2Tx7p/wFfE2aLRjypp1rpBGTjZV9KkqCnxlXhcSGZ+iYn +VEoBZjnDh6jVkLRKCn5nC8AE83E5Xc38VxzEfAGa6JpTuTYUmx//sIPzDMcrxgBh +/L/8/1OtFTnoJa+xeOU/p3/b/1q5qkbGShBjiKwGpvLHlpnaVABptilWx9X1QfdW +4aa3V1ygMQHvsYsNewN5SG+V5bLa6yp1VTmBzI6iC36SOmMwsfkGqm7xgglNL6d3 +fdjJcF/aFefjKrN0Wi5I6t9jZW32rE6zbp2Nwf3nauAJZwdwXa4iz5R0P7h26u9J +qfFSATNbkv0PYXnI1ApeSi/HTUQt+g9VdF3WV2JQmIC7ckUlFhGNTeyCo5QZIeso +svKx3mwHbBRwWiftyEU9M5KJtZ9PDNEQqNmnlTBuzpqHq+jcshYAlHviF2R/DAL3 +BFUrvwUB1WU+f7Zaw1uVSUhdZQE9mi2BrjrTYkaHEmm/s9g3co7DVi9kyN0vASPg +ixBxEXuid4e/8uqZtR1AEgwZl7qsStWJUZBpow9w+BU64efW3Ut05Qs3+779Zh5A +0LMIFga85wFDIYVhRxciPH65/O0ddmrkHblaTLuyEhzIffwTKGuymEMZo+hW17Nx +CU2V1KPdbGu2/G59iKEYgQUvR0uQOQExw9LF/0viZPLhYbKU6UAEI8OYfV9nbVEn +NjuA8UoH466DPGbW8PB1ntVh+NThvp0I2g0utia6nYPkcMHRB8laeqTFlc8S7uID +D0rNJM6Zl2YSX3JgiLFqrpLg6/YdaFdMlVpjULVFel4BN0Py9+Q+bkuQZY1mJ2AT +tFle67zW5QKqpUUQf6tU4yha0FPfiLGgnc8IAXOxYEZ9FbANjxtrduhTuGzUNn14 +oYdvCPJgTmWJzk0VMZLgtTDLhGM1ZaM8Lt0RY8lZexylaDmupYY5eXdquk8X4diW +uF/sd7oTc/xGc4YpWvKkbv3hMNC7oPZKYWHMvuKHEYPlvhN+JCb5Zj/kWbu5Dj0o +aymJJAqC1vn3dVrvfV8BL79zSFDx5HmvM8azuwsX0DNLZ4D8Gw0X6D3MXF40QN0g +2iwYhHuwgPQ61Vk6KuxA+I+alfKqzAePqywuDGu3iT5SprwPKhHEYphRR+kxUoj6 +Tx49eEK9BMjIecc8HQtJVQL1Ixqx+nKHe3hDtzd5/xst19myULOnf9nhyB1OTVNG +AZPomJP0k9tCvfkzmE+5IvjYDBe8DghzLh62X7j6kZhKY7Z7+r09o3DhqtnkhpYB +vsSVeOOKjsz9uOF8uqhwrDHQxD7ZTD6c4lKzN7YBrPKguVipT7ag66VO/GQDHtl9 +gLbzExg0Fv0HgA9nPgrilZcD5vICBkpG8iQFE8awnfIoa77kJS9uBlEe5rVvfZFI +PFjzLINU7FHYfhGeR17yPCPAXhC97djvEfLi9TKpTl0jEqSeWh5JOFWGh179Hy4h +S9aeUX0dh4xUZx5Yps/tmNnPZm11m8eTk/ijuPlOwowY6StJmWkX95Mi3FIc7Eor +E8ubM1wxACUCH83axaHwTQZW1P1Sx6VhpwYUcCXEVryYN7amTl7vDBWjeV6uUMLV +9jc1SmCPq5dpWWEk3a/acgJhnD1waDwYhXgAxBVCJsTy+y/Mn+X4VusVEebWkNGF +YVuz4Hz9ZL8AuBF5rqAnVhiCjyfJMXyWV013xp+1r1KRYleN/TTBMb13AGFvPKVR +84X2yAAAXfjoR05ZkvGy40LU+iXy6X860EtKtXHdCWELsximImNxv/FkDxmpmjJU +tzUQvj+hhQqHEMynWQfSlOiRfPNDbgTJpckQtFbkxYpNcKy+5ixDdThCinOXH70X +y67T993KjZY2m5YzlgzmdsS7HuOjnSHOS46n1MSZFO/0KrxEmyD5nWIrsotpr9ZL +4xjzXxxXpSrTgmsCJlAFc0Ql6TcNuMAUG+gxM4R4z3Sy0j7FGTg8ulTUdSqJbzqV +/Gc52WUU9IxJKi20W1PpK4jMQSeW0r1ROz9DJghJ2p/IHY80oR+1YIitAijszP3R +vcq9ONty6Yx97wXw38FilFwRb5dYTnvjaX19hHLCM3qDS+VL6KhKajBIoyMFnqhg +oFSk3tZDmi3GXSZmVm4kalnjHD2YdK/kPpYtCrVe0Ct9CfS25kacQ8oqkMJqhL2s +w7hKDGt+a30vGJqQxxN1QKKGkrne5JXiKfCG6ZKfr9QX+BlcmRcHNYZDpP8+T+xg +UAz+vhQYZrTKYhD+FY8Y7TDu0lRbuwy4WCvmHqNnslkIiMsfRS48i+KWr3mz/rUt +1sqrLUOeSqipj+17nemnch0P3c1udkp6Bn7eT1gk2i2c/47goHd83hZ06meWoMWf +kTIVG9bvhDDrZu1n6IZW/ew1rqHaEBXc7Wi+aSjFxvR/Zdf5R3B7hA9mfoemJ+Tw +pjcaBMqT7r9v6O+DXRqDyIcaPy7obo6kBctHByl2yU7DIUxaHjLUy+c93JVLB9lz +RWrg++DXvTGTSYUbFTxhoNLq3u0MfW6VNx3hhFllslr933gAjnF3udLBKyFio8AZ +M3B2JOHtTKue4Q1MTh8b1VYK0eN5YYWThXgykZoSkkf/Fs4qs20itlfpCO4elW/H +/iX/OZgTmOdFFzslc1LvyChEHrPoMpzlo/eB83L/w6wvqHVK9ts/MQU30Iv4HEFk +eKJN+lAqI368y3Yy8SvFTeZeK7rZBJlbHdVQ3J36XUd6T4WrFYKTAzB9sAt+ov45 +QorOlNGrkoom+mWczyV9SDj7Tc8LB0den6Uc0IlTIekDbU2YMXhr3/qPDwsMrebh +bj1PkDm2DjhSajnPxy3LTsrYFrEBs6XBB4ksChClRiUKBPhP5+mh9O9W4kH6QeZZ +NKrNaVJSiJg4qrWtAFtEMpkgIRGGoxMi33wra4mIJPE7gPC338ZTVz/om8FFba/P +R5Pns3ohd5CZfxDExQpZ43p68MGp4sNTSB+cbA7cYlLDN9yZuNjcNG81NhSyhsdO +PizChK7PeTgWLSh8ou8ffxRzo53Yr6PjV8ebegVUndSvRQuLdA1ufQgFfOZA5crI +Tf0DIOxnJutdTTEpxoytCl3TOCz8tUyHoYc6ou+6jpo+ipbyWi7VgIbLEI8kpmWY +wvdzqPlxT7UnFaAn/nIl738lqZKgh4mIz5Qp36wtKgVZVCwj08OmU5S5gOnaWX1L +GQV3lU+ez+fCezipjhQxvZ3QkZAPST49stayYRd56fQqACNPKFnWxwGouDDBm/kF +aUCQaPC5MZZBcrBEMrl8LWmvvRws3yFT1ReIyBpMTbkfS5LjHFSrvnq+rJfvX+Ic +DO3BTvUVtrDBMfGSRUvrEPB+oMI2SHdnNz0ZxgB2fySfX2juqrik5xGbeHWFxIyG +qZjs18jrX3MGoMunwrW4KP1+GcHqZN9Z58IvKA3gBb3JfjVgScJyxGINPkvFjntd +lS2YcFOf/NArAQ1inl5T515J/BI2WCDPDcgJfZkokz9f6P4u3JK8+jaLbTbQLWUU +2mUp6rf9S3bhi1ED/ZmdKuvCh5GrKUzkGBy5sgZzGm0yF0P1SULW6e4IVhQqQUOk +UtCuNzL2t7lGZMQed7fQfcqIwdBqgr4O3ERaBOyhX6stf16S/AdXIhJo6YSOSEuR +QnMUZokXJ49pE9rBjDFKUkUTYXS5aL82ahaUcnXuVIOWkzD2Pl1r4dpwQQ8dd4fE +jYicUNizpVFYcDVhmh2kqggPGN34Jp0jtHayYmtoKJ9qttoj5e3b5OGWAjXchTTP +e0LNJsBTnymhdmFLtI7oRhjdiFREnDmLQuW0jlDLTC0KbXNoIRQmj7ym++CIX3lH +NwvahCb45rxqexuj8mzFSeVWA/VWVnaZX0ZVP4WpZb5KBGBY3EQ7M3q3lM9C4PcN +l1AOSAdFQo5O5Dl8++MThxBUgJFnr3W1bZRG+Od3QaPWg4RCCSxlA/1iroULqBmz +7OWU3BkfgX6hmwVmdG2FjvpHtZgD+g4qiYsQTPTeF0iJVE1vb6bbexlntxpkZ7BJ +8E/Y93vMAJOWFz+1SmSfJx6Z6dBxb/U9U2cwp2ika10scCiEMOmz+2xgKB22MqrY +UKtDj2ljHO84BAXgFdD0xKldJTmpM0j7IEpbfA+ytqraU7xXESHxhlTdy2Hjv6hL +9B6rhL/twXvpIFSGtAGfbuyZGt710fAqzrKfrST7uYfgmsqPEEUmdwQhKEEBgXjg +jjz+rIzHXh01tk/BpGFCAyh1s0FrVkDofgwXRv5J78ACHMaswOpIPSYz1zNM8EGC +FK+gZurl+zwvWlWD7WdrcsSFdqw1rJuz7NnDRvT+SGpBo0AV8yckCilP+c43Cbe7 +7/ANrc3ncflSQy46FUuC8H3GscLEwYzp479Ghza7sqh9HnqO9329BjOGATJXPfJR +Ux3fcruoJ92b+CDlNeCdZLqylLFWGqtmypOEDjShijLMhfiSgq2TiAFmoElbobEz +joZJoAvQhbG8xVUVJo3aNZzVaWv69FVmXmUMtCLUsYLZehkUsBJF7zIl3/r7c496 +BPq9ryINr8+x4OPuQz1tSlFpl2O1Tz9U9AFcQPbaitDD9zXPtEZWy1ojp1EjzL3L +kzSjVieGUEHSlzMdeMJkeQCxcYV47EuoRzFX+n66Rs2DH+FGWf1WbA14OtCdZXRR +xtoA+2EE4YGCDQ8m9V+1ej8hu1zZnCJ5EiukZ2yVELQXVtfnmGarRIirH+8aqu4z +zRNRG11lFSEpCXfWtKinv8J0OJfHPOnctU1wEoVvdQEy2R3wnf2CYw4CDxU6Lgkq +gGKSLPnPYhA6NDAB4zbb29vDYNuDqkuuaRzTVpj2m9tkEIt7y0inSVSqLd2laeOl +9kkM2QyHXiZyQVfO5bbHpoA2XwvX0FHiaokF/YQg/t1LsaXh6hnlIobn2YBK30f5 +WTAUYZznbFIfCEjyHAm9JJE18D3sHR5IdmstJvwQsN90YYMcgz/uHegyv22lIv5u +xtmMZl1cqiCacgQskmn5jlFinhVx8elPO/0bQtGoxarJz22qm4fvjL1HcBqSGP2r +2tW2B+pN/75+9aqrEa9QYd+0HDni3zLLKZd423LHRKauU7solKm/Y/OFOBKNzpxs +lKyZ/o/zaj1BSRIWMe95olul+/ksc3riwDdfUJTYz0hFnMvoGh3F94yhdapfRwAs +Z8e7OdxPBfWzmRopwkgHsa50CzJxCFlzhIqbt92J+HSEIsyq0ChOKfjVAHLXOgo2 +BsT3PS8kk55tMMkUaPrGk7Ok28Fz5C3qjZ93uXAkRlnRLuPOM3SKD0g9+qYDmG6E +UqPLpimnYDdLqXkvwYiD0IFiacLnieAywjClGQGW670vSXUETtptQRGmLQopHb5o +G2O1nC2H2D16IZWRrGfZ7khnt+t0AUff4OanhcOgdERSS+9HhPn0hdZU/sH8diSz +9pENVOQbDUSDt6THD0Bbob8Drf0pf8PclJn7LVQb1XEBo1HJDLRdkYX4+lnFWTmt +kkuF8gTa0wO17CGMEPIEx4EtpNSFSdhqdRXWlUBQ4mCq78GUoUEc9bMKzeLyfCzQ +5daOXdh4mAHhepQzR8zTumRWPzRS6uu/sMCz9UTOmch70JpzZzENDdc9p0r88YZk +Igg7RZqzsJbnl2ILV0ca4EIqbUAGb6KTfjP1j8jRVO42aSTmQ/tHkAr2yYvrAwu2 +jwgaBerq2V7qoJGgjr2OwJWBXCkx7OJF+QTOLz1YDabI2TBQsoZ9+XFftfqKJ6nz +nUT310LCR4JAtZV9PP+yIX9e4tnPEtyDF/o1EM6s98PtQKBaL7KwqwBmG3ih1bcK +e7VApiGuufe7ZKrCDodHR0Z8vOfqx5N99qOy1I3aS4hID9cdXYv0p0DsdZXB7tCF +b6TpEcEi1h3VsLkEwEP1c2FQpb91DjDX3QetQ4qE4Yp5Osfa67B56+k4vgpEqcJ5 +o7THIqxZLr+SxkywEdMiZbPlAFQu0yaQMFSFTYnNAW9nhZQZ669onva5IWxRG/6k +2ZlTxauYyUpNhlbqDfx9Nvu3xpXeyae8wirZWjH8nH2skcVVt0kQPZrxy52cqO2W +v6QI5PAsd4PWNyS/51IUPe++lY9apPcu1FXtGV31uNvg9sx+10a6eUd/loBlcaRN +eSW0ppSbJ02i6+0BS0M/MU5kc/2zR+1tX+eGzMfmoBdZxBbbeJL5JdIy62TF6MTA +32+FoooH+F0/nk7Zeiqja3AAWdIjfT7YmySS3ziJZq9JX9aY6ilea3od7MmjxZ82 +BtJ2U+LqNjib6Gqe4i5MNB3/iBZDbm4Zo1XqvYRNKaxHMXp6Y+4GFn7fd614aXWR +P49bR05+i+YThXq3Pbchrz5udUvQeaP8qDh+tW1XA8aR/bGhjzAMNHUmWKeVAq0N +eOqTVw1cR+agxLyKV5rcaecBCaF9S++sCCxjWYROwh6F5oycAd8h4AzxWBI1JOwL +JuDVQFtvuntub9gqGXMb58xIlqp45n8ev0u54qS8yzNrKR2/LBiflGcjSrNmV2V2 +0ZpdpkU5B7X7J/eVv8M5e5uU2c/VfESjru5wEK26hujb2HUDeLESl0oKz++SRunt +pqi7CWM5QzbyY/Z2j59GyvOYv1sqm9/grCDdv3mM4fsm5xKrY1RPeMnBDjGKvEYX +kcKjzSObdQbQESjCCK+mz17CcGophgBR9aKctf6uXGdfuJagoH/TsQ7xRChbTvMt +HXwTGwofSl08mfNEmH+mW+/EZfcH6z4/YjSjWe0hasehWe5R5OvcFEfZGG+yXXsW +T2U1gSto06FNf69VBVgTs2FaBgsFq1Ud/ATfUYOltearDaJe2LoGC884Pkn/sVqL +70YSrBQ0dt75gY+ag3JsqoTSQPiuU0OXVbhnQOz4NXPL9ZDi7WqeGje/99iEG1zR +U6f13j1fYYfn/I1Sfr5u6WXN+qwsxpd7EozYvhCQ6pnHYqszHDMEGtgi8Rew05IF +9vQpBRB7aqIObbyuCfnpWOdEtgexn3IDsBjuH4+XWf7+qw/em9UV834Svcg3AMC5 +0DviZ9sQO5EPAay5AlGZHhidYWHp4iy2TFvQFY62NpxEYKTcx/qP/zToSjmRO29W +/6kN6hoRxv/M5Pc4t3PRR0bSdKgfKoZCWSswNekhCy2qMnFaQ3VEEq4UuXzdGCjo +S16XBorBtzRzcFk0H2JO4g84ZJLF/A048OHufahmmn2vfqbUVm+j3F62Co41qy0W +yuKEzHUPk8GDOlGRWiNStJjyC0QSgXJY1x2rYykXNdLlVayh8xfp9rPcPB68u2ml +CX1wiaiBOlqfmy7k+iXvWCo9PotRqr8zey9zRwUg5YoUUIgtyj/WqXWIC6xQENmG +NkI3/IK361RXEtgIa02W2J4ISoIv5a4urlzkwh0DZQcjbTV56bt+wXPzR8D7nhze +T/a8SbdYOEquUm9lBkKqd83Ze2p00fLFmf0L1D+BfyPU8udWfdVv+26YINhJwoHo +9bHrGXjUd/cOU/NVmM19ILKpLORB/THNDpw6omhmJXC/NhJLRPpuNtK5izkRTdYU +xUccGkmbHzFnGEV9oYgWlWh23dWcwfTOH0N+A4yuvs4momqEn3E6Uh4BT4qZUDGP +4nKvWKuvdnUW98Ik5/NppBlFHk9PrCxucKqlgKfgtom17p08fc+ei3QBhVjM0lsm +ZC33/dujNSpjK4qCAVoEvw1SwmTPiJmkNedGsM1uDElm06jVaAy7knpqzH9KR8Sv +gl76rmlgpMKLw1xu37i2wVSmdniokFTiR+CzqCNTc0V5YhXHSwv3gE3V2gpQtej3 +79f8ByVhMbbW6W4hnHNGJStPavoQuzT5ToFcpRHvcG8900usnavdPLIwg5mg46Nn +6fYccuzoYbKDs1dRjQkuPtx+O/Nl5dIuKpdeR09E7VEwZpBgu+tFcqGQc4fXUZ1l +cKW7M5DwIeu5/pq6BH+WISzKGsfLYPeuou0sWFuqYoyu91mz+V73/p8xTnAXc71y +lH18j3P24VmHb4j1RzK5HbKQTRKAz1xF+omIS8lpCVC3ui9cBBEIlrYo1PJpB9gT +sabjR/jNBm3RG3fUzrsdrJulK/CJpJ0BVPWUAOLeKOjRr3RQ3gG5rI2UFthyQ9aN +b4vSivHKruRiOsmiZfFGPTuq8G2m1b/Nws1Pk9RK/q3ITdIjZhDyeVV47uOTtOO3 +9oVjvLiONLabvMylgOVUx/w1KTRkdcLzcjm6JUPt2c8j94iMUP8ujHXG5cgFz90T +xjW8fSPo2ddjn0Q7wlJmEq5DCZJedmgOahbsO8ObtRA6LWr2j6Uftlk6I+munD8w +B1rrCn3ZvdbSC8Xteke9P2KH+yiGgx1/VM15ROSOyNjgw2zgoMH7VxFKYoVCzZgb +RwtkFY5IQLM8JOg2c1jfbACvOwzbAuRkcCbHcX6JI0TX17muoljWj4U9cuh1Q16c +/k1UG1I9aUms5ahYQcxTZnbstADMKtn5Y6KuXpp5cnRkkachAoDoc1CqJztt1Yjh +Mi6SJiBa4GJFiOlSmTdFj33xOhIv0h5CcRnvw0PV+IEZ63les9X8jmcxZbih4c/X +nC1ZqelPyHLyoLp359GtV2cr8lKUufJuqc7/ac9DvBzPVLpVcqSpdBg8zY0Q6hH3 +WKE3kgPwlYXWH8UcVrxHkhDKH/A8Lcz5upNNIPz2mTx1RrXolxx61ziBHtXPg54g +qVXjTS24J6kOUURnwSs7IrlxwTYQLbvJniKxlzZukrdzgGcLxYhAoPCRa9YR4HpG +WzWDl55D00FRDe02G9llcgkR1wxEIZKIdUiNVoCmAPHVOEP2mucsa06Mu5Xxwa/J +ndvHc4XDZIx0tyWkrWuN4hnhkHWhGPE1cWTPIjsKWd70WyRUKG9R8+wuLt/WWMjo +RVCs6DU8M4+LI/RVGgbhEW6118gY/4I8IftveG14xHVhXPj6+9943HOxlLTFpLxi +8dpR0RJuT079+aPVUKc5FaPeDO6IhHK8/9d7n6nIhOuy/PAPveYyFlc5sK8F4qMG +OOjHbapOfWtalfBVn9NbOlOY39Pk66dtTM2KQaRBb+6aImcoeeXIj6ioPZs0FIow +TvYp0/ZYPMNZEmpWO0tTo2c8Y+wF5N2f4pcYZvF/caYw8G8KT9btDDytrq20apUL +iCrfaEabj25zm7oV+nLe2eYQjnCj7qpJjZeHj1ZPqF0CriLHTybgeRuMjupy7E00 +z/zDlePVFqteZ0Gqy5P/Tm6zuactueX+0tG3nC0596ccNDXQQ7uH810ZB6zmu9Gi +xaT8veu9ODjeIOCvja8C918rtgNapgpOT3UqNnL+qzi410vC0XzmwGb0Y/vQDcxW +MF4GdDmE4Hn53PD6HeTbnCGPiWsSnBj2d6bxuOB+kv8TPmjEEB/B+TDZW+Yq95pz +lr+CUAJo22IIsMDg11hOXE+fFYm4oM3dvFHpI0+4XvMR/CKVMoHiGOfumhMhke6H +R56f5t5xNXe/wcWChkLNgUxIRnFNpyfWHexqlWnQ0jcxSE3jRgdp0R5Ai/2lqiBa +J43tPdeMlWOG/2l7Hqq68nlgd+A+SvxBSmMXUSXLW5fw1uhg8BzV/0F1z8qUzy3H +616XQqrylgJmJ5IU94SRNrLkK7bU83Fn4v8bvBN0Mr1bHHdXxFPwz3/1Ol3AMRDg +HwavUpzqFdENyV8WAbkDtKQv5kHkawEDAsswENXYnUA6IltLQe/Vy9Y1yaxESYyx +Q7I+laB7g7el69OnE1Cu7mQ161KNTI6EnuYbFmXNjgEdEtTIu5IR3+fVjbU9qleA +izCD3aZBB/4+Wi6FfvRJf1vBVqFxOswx52XGnQBMmz8O0UtWqg0FPLXIWofZYLzC +qW0FmfECMpWH8t0fAZk0CT9h0q8WdODBkIiHxkR1OQuhBT1eWJJJqfA2q5nFGRpq +WLYHIfXUZeb36W522kXj+8H0hdL58kEbMnk0tU+9heHFQJo3itzEAruqgKEnTxZj +De2lIkfDMKzRCPWj0fY1Unx6To3epnONq6q+KYiccaXnE5EofUyvt39chW4NRpLd +dXbShzRXQhRxBZR7QLCPezutXSGbR4V6+6zpN7Fk57Op+41EDZYk1PYxzVD5QjEP +H78eoqa/WhC3yKxVd7xVoTy/FmwQ+eTJFIeZJrHrCnn03lOMAMOLESHkKemDfJI0 +LWQafc1Gzy9cxpH9xbD7zIipVFPPq8N0E58sDOEibHZe3IxuZu0yeh+twM36TIcg +xZ1OSdvIH1yOdRimsJ5tVN5IyIg3ak8Q3ewgHf20snxNjUEsWT92jYqmMvqFZW4s +NjW1eNnbhJ3V/XqFhjtKvueEzHInyZL3qmCeskZnfS6GT5cYrQHo7D1nBx/cqGKA +Ubayh3TGtjK+6duc4FXOryAtx12L7fIVfwd5K/JfwuAudJNg6Xx09ZPhDU0EzdDh +6aWYffxGnJEXqeI68qG8OiJBtqiJV3QKJ615k5ZL2P3tUkbfJGBIZj4pDspP4waU +Pa2CD4FzUcm1CFV8J6KWxu1MOi6Go0RADFZQ2hR+I0E3u6HR5TfwZeGSWvY4kGC5 +91naFO214j+tXU4RrJsRJdkUxkRzsRKm9FI5HMegxLcBSzU/oOm7ak8MW6AeZ8XO +HHOVorkQDu1AQgD+nLGuUSCWxCCVbdh1sAXuuEgQq2PjjpP/cLUwSsqtfHhE8fsp +Ow0OsWq2UBAhPOWfliE9SP6yjymCqnQx06r9MlRW0LqrYEwMoHMKYZlPcViwfdKA +mdijMS18LOb+Y+2gfKDuObJIk57iq+K+hXfl43znt7aY+yQv5c/UTXMURGyvq79a +Fw9n6cjhLo2I+7yDrJVziHF7VmLxrOo6b+laQt978oVszTf8KNNoog60mTZHyTif +KQgUId1CbFuS9ytWPBHlKkL6p7EBbZL5IacIb4F7J09FH2nn8WJlOu57mrW6c4vF +cO4W5WB7Qz3MUppOrrU8KK3rLAV2oDUtb0ask29nC0xuz2RPItNnxQMgZaL8q99w +rqYEa3eeMZHb9p4hHAEReiAetdtahChr/DEDsGx923I6Xsn4f5a/uEo8epAk9skk +GL1kmtDo+iJVH2did+DZssoRMTzxIlbjrkVfcl6JuyUaXoj41BtMCUnYN3X6mzt4 +LAo7JZoQcamV8TlxOL1kZ0q+jK4z/Lzr9ZkaQfzo4EIQdjVay4DG5Wb2g9TjrT7P +rxidLRSujqTQG9SwUK31p5UM2U2jF0NVppI6qbK0/rEodMYVwKrHvvuwLkO2Jm1M +SmKrBkOscI2MdS1/kKhL88POT1dXk3cjjpRhpYQUq0mdetB7ZJr/qpPElVgHp44j +RlKiK60/aHphm6vaiuN1UIZU5QB0vySHjukI1fdiUnW+D/jdSKwHlNA3eThjqIrf +xmmSk3PK+yxo3pPZKiQ7aupTUT50Wwx53tpdZ+IVLyhtgH1f4I58ZHortnhV4Hgz +HlUIXH7D4lEukafUOsGy1fKWXSKlYeTD28Yby7+6hApdOpSuEIJhN7/TkUGKZfJI +cUY4eT2SO3Gg+eVfKBy489sWiAJDC+T/mH/Dtcb4pLza2RHymxctEU1glsxcrxk/ +Hz9KHqTp9vyou8dAT7Y6HH159imWFH76bzPN2NkMIUhkry7gIhhBvDpHRRo6DsmC +cCQOvrUassHRIbpOQmAwIGzbAKzBPkqmnh07/qonPqA860XCq0R30Kk+SChHHo/5 +7kEO/Nh0SbBCXmBBIWtuFyAwmD414uSlq3IcnnHpppwhsgOJK1YcUjC5nU5yMYTU +V9z00u6hvQZUZO7//LHpTgivH8QWNLXof1r9A1RSzbKXguLH06vZfoPe6DVQhcPi +Z7RI06FXqrDHWQSTyZd5/SADkNfvyGnuQjPRHG8yORO28+RMthuPWSCtEM4WWo3E +/JItysKZPf6EaHGzhWeDazKNLIe0FyoN7hCHFqPLSkPZPCy4sDDuiyrQb7Qj+XhV +4q3p8ba9pduwsbCZbGSfk+B/li2D7nKmlNWhNdpuSBs1XakMItFT+QspWQNKYy/g +c8Fn2h3hlWdhQ3W1xHrFgdZGwarNTv0fuzNB3I6chPLCED0UW0+sB/B07agLduH+ +4Sj9hDAyEOlQPZi5G5mcbgbIV1Nm2jltb8T39qmKAJuLLRdEJYFoVu1doql0fonN +uRXcKlGoVncdDFGdhdz1rnEq99EFlErosp4W31AIcwhdEL+jSQti5pILnKaXkmfb +bZLcMVI7SV2vetUlvpyHURYGjthzhAjR7WW6/eTpfaSxY2KN9qs1aVAqC9hQBbZI +RSD5/f8RNpGieBDZGAUyobop6KFy/fxOg91hI8TAjRzAcmo9Rg1D/Z/kahAqzHCx +5CkGT/URjrSSFGA9tPaugAzWzoO47DqxTe0ZyAOdddW2rKnG9VZe6ROosW8WKokW +TLbvm6OSENrjF+X0BSfha1JzSb9Bu4J8cEqsCu3FX/GDvRPn+tQnHIL9REyK6pWJ +RgPcnqz3ecADAmI3ID0cpN3TqU8OZbLi67WU3f92xPrnVvOYrZmUemOdT/Td19FD +66OmzMYjaPzhAyI/twOmrLR94/7gNPT2zHhK8QjXgw+Gc42BbqQ5r9/9Xgb7eHp1 +m9wkRjIeqybW8bEtJ2YOVMH2MjCuQpbFGcq8sLIQ/waR/4vBGIQBaO/T+Cxu6wou +iS0Kk55u+uzKqCCk/7uhgwOT8sy0TKU0l69mvF4DU2XsEVpemUmPKyDDEdSkxBkW +FL1hPtRENwOQe1Xw7tfebAtrEAD/d3P2VEPpmQghRe5iRzLMUhw5+8eUSTxJZ4UB +43fxfzQ2PB36m82p2kfbQYMhIqViBXUxbFmsDC4AyG7YdJxafydJdKNIKVKvnaL/ +JnHZHh/Z2sGmiL7ZyBPLc30Xup3boW0WW0Sw/aLiMNjWoNaxTV7fAiWgx9b0m0/X +TSJPgcPYIjDDMeLVus4EONBeeoDu3Gaz7U0NI6Qr3AIsFHf+/+adnkk3TTU6jIJn +quMHyB8k4ejvnlGkeEvrpSAMeWNKuZm5hbiQMbTYLXIMVzzvWB6jbTAsZ9D8dftP +cs0rtLyNYUzvWLoTDdfEdIdrNLUF1QWE95vbeTfBEWa91Lu7q+Qpz3zc+xUQi/0y +e127eFTH51pLy+GDd2G6BTCal3yMEX21Z55DkfJ779LUx+scxrq3dAOm3MjePpJm +JBeN8SGEkdLjCOFl2ql5Yz0iduJZZpUTIglDOxr/dgT7x0Akj/fKCvPrZp52YsOi +Q90OhIZNJNY1UpvBcp/Z31o8hvW4c8vRV55vLi5y8zsQP00anMdXUYM1zfjFXYcj +JfpRrc9foy57Z6O55sXam6Yse7SeFg7v0nLmQ2qFNr77ezxUE6z100YOTUcZqVvB +iSk3jdwBc5q+fzQhM+r8KraeC0ZfopSrXivqVDuZUq4TG6XnjLg6Ucu9Bm5BJnKi +/Mh4hMBs6G58FRj5WRhYjJO3IIjHHOoN+4h37k4Bq2Py0Cv09/Ov5qGbPaOWrPES +/qGBOCLfXIzVwyX0QeWee7t3gDrppfmqvoxUbjLSYOKfiqiXyxB/W/JJevuF5Tqd +nz9/CTdlmVJsQ+5EY5Ht6TAsL/Xkwvjqc04Fq8nd1tivPxIlqcRGr86NpPYTx4Ko +A74DUiaxCRoR6SiQeKicTq/bB6c60WA7JC1Gl3HBlS69SK6Vk+QSMn8VnyQNcOCF +Q3bBgys++SVVnv+n0grH6CPn+VHxckWRdZWJQHlgWRpJhq2A8EXtr7dTDqQViAdM +yTZSMmpQLlQ5d0aCjna7TSZcZY9+kKzg+J9fv/HeM+PjvRMaTpgpDqOpTE9NbZTb +bKpdLVrKBevzQ3PkCp2wDqDel2Yk54G0RU+N4hGpsoOB4x0LdOhSnzudHlP5cV5H +hzG2X1+SGnW4LBN32kMQzs2NswW1sAEXZ3i0w8/nEqgXB/5nJjzCoog7sCG/hI/F +SIR1UcZbVPAzdmQ5T0h1TQmwDE1HkuD1gUm6whOI0NM0hAqjkuU7B1CNpF7213Bx +74PWrtId0/JC44q51NXr2nL/1A0OkI5eASs0ude63f+ZngRZQtEYsV0fXMrCU7X7 +kvypfKY+5zFpJe4pK4bsnsDlkKZCRa0PgBy8aZAAinFU5FG6O86VxL29jYrVFOeD +f0wfhtPgJPT0XnRh0uVzEQRHknSzwuDZERX+BVSlrseltZ66Zb+OFqEnwVV2eWkE +m2EepSjvQkAq9lWTo6XQqQc0KaZVitBcz02wOmcOVUcoFYcpH1gq7hKFwkByxXcr +IflOxUHFxGrKtJHCOIRTqQH8we7Un74+NG0zMrm8ScglX+f6hqaCs1HRUFbETSEL +5zWOa7iwKEpueOAFs5cNcnlHo+NTWCzsnLWWUCMeqSxl3eH2wQlghe0YErUmX76f +BDNtOkGtpgn0OfKsWe6vinhYwoLxRqmG175U9kG+xVeDzh7RLSEkn77TZaFW7tbc +jDZdT1o7S0lplrZIBVvUjEInpN1NrAIeZT38MpuhkZF+2hSoYlSHbsiJQwYbfylE +BZMjcWqExVtOsh8ZPzOFStgczk/z9w7hiRMQ+jQELGn0nrQe4raDuLqBPmlNhcZF +S/ZFew29LTKKUOgCeaSyebV0gFXaX8G6UFawP/Qju7MrpiT3beII8ias1NlyBxo5 +xnom5Cy8OaMLZtPchpMs9iLgmhZUtBYT7W14VgPA7FlD4irZFRUkbB9l+3MuDQDn +riyssv0Yqzv42798H3m32aMIKD4tHvmpirCqgbHvOb9m0MGCmKtNem0/md0zEfLC +tCY8qyAssZkeWROOS1g6eRZTrKNEgjIMATq9ofFvqxHonw+FgfxgxbLk6lWeva47 +Ej1UIJsDr+Ku3P0s/Jq/KbV0de5yoPv5u2viiRFJxixy+fld8ilCGLBSN9V8WLJ/ +MpcwGdKQs2DTZHBAqkRiQsHW453q8Mk4VxbhxXBx3NIwaTwRykpvf7PUeRAIHdEs +gRtZy+om/ZKt7/Xp18DY8dXPO8WaXs6Gv+9H0Rw+5US7rIp4d6xB/hGGKZZLYY6R +USo1NTgFn53zp6WBx95Z7krc6KJQ+YlQlkyhEK2FND1yinbY4/heFxxRtVUAwBcp +Vfrqxnd5TEAQ7fvV1fLPh/5Rz246FZfjEebg61OFde4iuOYxkf+aKuD7rRR/LDrg +WnG8eahxU61OhHhfZst0b/46m2ku8w6Lc+MAEef7aKj9k0szub0CrWiNQtevySjJ ++zz6p5T/es12fho7+SigM+AdA40Hizt3S/l3W9YJUzBtdJQfAkgUbanj2hjh6L7i +JAmZ4Vtg35D0Bf2T4O4iAPmrE/y5eG9r/oDmKnQSYxOfPrF6NopryUBbsysQ/EHu +ZM4mgr1ryJmoyY/dMDiMNNOX82pH2wuppHR92xfYA9djWL0Scw1CT9sz8f0aJUAT ++/fMEhPMWQiXC1UKtvR6D91LJewNFRjz52QYJOTYBKgH6TpTdFO+GxDJqytHdnma +UFfzz8lS31uLchQrnzgChvQc7RTQBG7NyTAzuYhzZ/aU8PBRD+qETBPYM4s9g8GY +bFeKVJYun/YmlyiWoz53KjzdNv4fkm7ed+DAHGzJEP9O/CIRsM6sTWBen3mYy69A +nJxSAvj68/PBxxj9xXTUhRuq9w86n7lzmEq/L/i81viTyOmo/eBUy3n0URrW9go9 +nwSH09NdN9F88BRsJev7ieheuMCcJFu87MgMbncEUX3uVew3Upj9fNaq3GIkd8vZ +puedWGTjzGhOAoVtM8PlPTzD7lcDKJvDHSNzLPvy6cHAs2C3ldlRQWH+I0PFGn2Z +vRyuPkUj+wGt+OC0H1oXK57E4wCGfP7lmJRs7NOvYW5euA25/pVeypVWQ1CnXmCw +WQZ0SUinSlEt8vYfda7WkaIirjcYPq7N4PqqM0YVKUIsVDqUEMwOEiff01+3wuPk +fpZiUYeG+1ZDAl2SDrbMvmHA5+eGFtAq3X5OlffQbV3oHuuK0/+nN3sp50d5almf +ir0tEeNbSuU6TT4T0gkseCKk9WbZUpupuM6r9saZfc4rWDJr1YSgCQkiIa8jEhX6 +ZBhqlEt9/VMhGPKcigReTcP52gukraoyxFGUxGBkhDMT24eA/K5NqWnXCp2/zi23 +w0WCk7JjjK5Kwl6lA3LWiBG4DQu+UcNA4+eHDa2nMHMdisvr1BqacuRkZeZRpmjj +4fYJAAIcxdy303fXl7CZsNj496s+XRlna4WSt2xxd/M/iZa8l7QMMcouY8YzAfbN +ISIFDs5Ruchaqs6K044iG5KIz+ZkoTtB83quliZKVcO4ezAAmwNGM/qDqQXy5efT +xBdfJo0eFYNcoNEoKGespDo+DNzClq1yYBX14yqmPGGHp6Sea4MRqQbf1z1x0aed +KYwx5+LKwMhuqF7LLUeBrXISzRX9e5SrMIaSAk3QkdQcd+Njh1zOwBxkSMpA6xn0 +xQ7a/R8+vwmR9T4tWOjvhSsAmoyacg97n7yKTTBK+rNqY1mnDkzUNOSzFgA66dra +w7eW3iN0IIK6HquD+F84UGkZdrvxXYIOpn8PaVFLWpalpyM7ZQko58QNA4DFiCGu +yM+/WqbA3MdUVgs8Ttqe3ghK9SbX31zs7PCUD6j+/R4PHM/66R+7c+rWA6OMFYNh +zXbw9pB9FTWewng5HkCtxQu2UvELKsR8tMGIKFORKRHeEzGbFo8n2wBZuZxJYN7p +65aId/7fKm+nk3qRnYpBk/n8+VuPTs6cK49PShFM0NOjZvl36iRcglaEVS6OWoWF +DETHdYJwKZQzfDUCmSsXWG9+YRJoECWU2DxbYRww52R+Si/4qeE+7WwLzBo0kzhk +m0CupyM4UNH6sf71ExZuRpLNGmsr6fXoNwD2uBRPjcs5AIVHUHZdBSyARY8GeA6h +Ur2iAtpiuJk159jskZY7e45tpk/iPKdq8pYha+CNJ3QttHnM11goDXFOBwjDZ/Lj +uMQ9FkW+S+BMv7c6hZl7wO8yRrkLC9LUQuAWk2qbtWRD/tE63vu4ZVovYuDTFG1h +90WeKJvPOHEVH8ksk97M26ekpfvDD+5UbcHLbLVEE6ZYMEyC/RZ8gW81a2tqLhEL +N1+XSih0Y7j7ejILf/HEznnIQlNVpFl6gFYh/Cf6wUEbMJTp2EeaKjLhoqWtbSyA +u/zojziCxyWLuKcyHfVyYb6c9aA+VoKYSAo2fboQIpThFKfPCglEzN6q0JRF3QTu +f9lSgmcX6vA59jm3+P0G0dBwmB1F+s80xZp7WjmCIRh34EgVpcbq4cCrl8NiQfQ9 +lEs81jttX6OfHTMgYM2xAbKh6BAgHMRKmWQRH6PU5YAcrQUQSSG2gdpIBPCiiQjW +1udolUQSydf+9I7vrE1tpDj0mw3a1d9RaeMNxX3RGzyrEbJaf1kPvVp7ehNkGC1B +KwBKNd/MpceG218KfjR8NLv0zKMnuuMe+AExnntjchUU9R6xmWNGiPPkfpDDvv9J +F0J6qON5PU3OLqeu/kiTbOI6hE3YrQcyjjWPBiv1FCg3d/53HTnbSBpt/xKW42zo +BRfxQ8PEMWZTLJCCUl9+AAZxOAdETgC9k4og+I7sF5vlxkUsg1ky6aoeuJxEOxQn +Ht0UKgf5DP3kQhXzbYcHierL1bnfa5FDW0vimGFGjjlHKcNkfVWHIyCWhwANryOw +aIF61fzRQGM8/J3zl+xwRWRAuEviwH3ruVaSQxAw3MLdPM91cgGGVPDYkYlveODO +j9I/CZrZH6+yzzxJf70RUNtIrumCAa+k9Qt0lRrvfXDiSIhJS/wAgwDTs/wTPjas +5oD6iWe4VeFgyKdrsMAIxDkoxyOzNNzFrYyyfbzcJLZQaC4wyKJgQsAVErIoiPn7 +8Js/NMxm8QtXJqsmh3zK7UTV+ktZDOOO8QBRzz+pAicYnaVww1qnUyWRriwb12f1 +QuSdVTwG+RHnu36kcRQvZLNoYqDi8IUtq+ZFc5h6kB546uSnkxpCAU9EAP/iA/cA +mp43JfCWufgaNDD0zCBRBsTwoA1sIi0zWJfGamg5eAEoppy9wRRHIog14p3Q1AjB +6RHfJ9nYgx7TFrTO4N0DWHkNfuXCGGwlTXhtD72njCNkSlCfY+wTigIzQtE89VKV +irp9VixNGPgkC2jHp0ExNvCOsF16qLGr5/qwiK/lC/njuHWuCCo7ZWSlsTbVvmGU +67jHgA2GTRDt1+s7h1yrdGHJjJ/K3yfVMvHx4C28Hm3Y64z5B2qdHJFL9iq8hx8D +6sqEdLSLGXs68t8tVfMcMApBMz7gqoz3UShDMVmfSQcx3EMEKdTXrmxr2uYtxD6r +0JF4xyvu8yzmVsU9B/nfhCbWxIX5ILji/mAlD3/KQ8zRNlbAu1U3PIZn2S0PwaqT +l8NJXMtNcIx3cjQ8SzlFoH35wlBfF6Vb+h6WpuHL3tZEcM29E0fepsKpYqfRM4+o +4i5gft/0Lbm6C/7iofMnYHUJFyQU+nt/7p+ZoLiU85VViBLjcxhjyZcXH19mX7ZP +miqaT6MQIvrOr7KhYMl26dxz0WBUC/nBFUSvV0e/lq1g58lpd3MFSuK3zb2rJE0M +vVys4twHogLK41MdtFc6E5lXewJaEjAvnHBvH8lObgO+cYWDIJ21WI1ipFqChNFr +7YHK2cAOWUctSpfS/8e9s/+HL6yHdB0+cs5CR9Z96+VnsDzVP7KBmxuyUbcP/Ofn +shsqelyvzkwzt1loAkup01k75hLjoZepNQ7wb4Goos1FwdfNy37kYAya00zEd2+I +QkJZ5QgasM3qKn+6FpmNAJRMrw1O5CxljC8lTQDcOwwXWgMR8ZGFwIwYxrngt3/P +ZXGdP4VF1iToMLOwtJzRavOISbFCuocWyzhJdG8t5OVHjA8+P7HcYlqpbjt2t+JG +IaWukfs9BRmQ9qwlHwRxeuv+q0PeeiqRlyXy350vUpEK+E8SDyykPSvAfHjca/76 +cEE+UPBzZ8tpSzMQVk7/6cFVSk2xgmx/kSN/dr+wJcN6TK6Bc8F5pJBexvAwJ+qu +FdkNXB5SeRZUnIDEJIpog0FdzMxZRIfNSSLVkblp34WHjhauwynwuqaIpbwpQaes +87nGGPKo8G1AhrHeHp1hXwPp01QX/3h9rq9RBzkizrq4uNL0XJyudXHQ0PL0E4B8 +8zgHk+aeP2UfMkaKRLvdocp5qJobFaTWtj5jg0O7Q4cP8gJGUTwXTVhl+VRyDkct +cYoF9WHUSkdXpCFGFpRgVx5Li0eGZIORA0iweWJRfpXEcng8+QG3vuaV+pFU+keM +Jwx3a34Lh6c13nQp09hO8bcwvPNyLCbvrdcKqORWsCyywrp3o+2Fzmp1QxL0BHMi +ZYDw53ulBmvDsbkBTb28dyImkalQ7Xi1pfSDNgJdDAcbib68VoW+Eq8klXOdG037 +mOnqy6EpVtP9h2hD99muEeyh76sjT/zoA23v/EhXSjNT8//n2NYwHp3HA5emqfiD +gtygedfep5WSTVtx4mV+AIlnbQI8zsSronDvRWhkANqJT5F1bDdJlAyh+bNkOrxl +MekMKfhS67gZ60xg+1OwIYwMw8ViVqvqpURxTv6aUVmHVh8orRqVhdGmm4NG1GaV +SJ2B5RrvRfrUwwCryGIFKRBYJHXeYqE+AJC05ecmDsFBfSgULPG69XeCkED58xLo +SlrVVEfk6HWbPJeG8eZ5yA6OJWtvo7A48DlYH7bcokxKdnAlX3m1mGZiYJHOvki5 +h5xySPch6Sga3JE+gU+kuXRj0uVbxOxW+qwAst65YMa4kqNC3ytzmCtnrNEZjjwd +qVejxNMiGAlQKmoEnEH0a7Xc0T+8Kdg8ycUS0FSmqCNx04AmeK5O6DWXbbk/uYAR +8EkA1s3rxlD32chs2Tydf+KgN4/1VSUJ/KjGoPR9FkEWRLzetpYB6mtrtAkptF+v +YMxIdMnHj5f7SuYChEoQ5Nq9QOO0PpmdnjrtTuwlRf6FikgWkgOlxAGd9Y5r4BUD +/mnX2tg9YJ/k08smEQOWe0+kQOHdQ2LS2XdWs28qZrb26wkQLBvEsEqUPmwMJrrT +sQo04JjZBa/7G87yQr1BbhMkLbEZstCTcDuKBpunmKzOg5Kq26nt8m72juzf1vML +XUH3b8PvyTz61iJs6QiKoj26C1ykg0AypRZua9GE5f0PsPsDoWXvombX3qB0M13p +3D5L9YfHUccyS4k5TyJIeqaLaHCcu1AIVksN/lucu5bpYqFktwZ67QFSGhCnJtpH +E0dSIRIA4FWErScaXYodrNiUPxwCVsv2DxOXwp16Y8rMj/F4kvc17vAzKGCDnBZK +qrMnuio5O0t0UycxCQibJz2rukWRrSON8G3jEG6Nop0sldDRjKvrzO4x9+dF8UOB +D9OKpRI28Rd0jCUKaeoi2SFN+M+qxKyDJ4dIdiDPHvpJ9tWPpUEjNuxIMe/eA/3F +pUe5Pikf84GTjZXQM5dwt4hg07pHBBgqPV9+0eT8KaEZjuZyz6YLN4UdjuL2JLuw +pXQUuNYSp1u6A5Tpxym5hHZrYB2VRsdca3TYsmsAXBhIYFBssb/Mi2z1G9WRk2gz +5hzgYxIqCyhiVX5d/htgviPEr36afNwzrm/logza2HHANjphNGb28NldlbUkRSRV +flKGA1mJ1u6G8w5bTJPT9FBnLqw2UVOHJtcWt6uAlclE4EDSKaUb+WAGcF6cME1E +dAV6wPCx6yu0gSEk5ZAMKw3jKSJiR4kyiZWjnXBS4KvpAtNzx/+5or3EOZ9h0oDW +BkkfaTaYrVsEcozUU2tdgG0Uev2qTxmJiMRNGcqrps9CF3cMdoqvZ9uHo/B1UIDD ++T5g/+2imxSLDXrevv+kwuwWeiDHUlQVuzWZtozL4mwR9DPrFOqoRLM0Ho5wl7dt +9CXhtGakTYiJHRECCVBbfvIjxL05FpbhK3fwgtltWsNdsH2eOjSGezV4kU8ecOj+ +nMBDfLmFVG4zDOMJef6nv0SZMJ77YO8CPfI+IOC3/CA0+Kd4mWP9PgbmgXNF3h/4 +84NBR1zfA+9lMCftEJbBCUsEdYN6hX+KJGX4UNzNGQUuB6dEhRPhRRVYV/XY93PT +cm05Xc7tVkcaRRdJRK8LiuHy5KaRJTZ8hPTVyVGYZeDwlHCM6d8t89FzZRPj8d2P +pkuXxwdqi3NkuSPpgyoK7ALpUrhbG9PvE35UsUdQvKTD3R9bl4FKI8m1/uNKjgoS ++fQPwX9lpR/Bv+7KxoKnucQO0zrO1Pac5cXxwn81XXkBfSwCVsDIJNCdTfAWzsbU +cEsII6wvy3vjLKAtpw1q6G4fRNmqj3yoAWizlewl6hTiwsBo7qiRinE3zzmJijUz +lWqisJz65DVN1V7qd7oqpobCbqnW6Ye7d15xpr8W7UY8zSb9TbayiAfuTCLRDlFT +PCoQRTFkDcuLtDdDsuPv/5HvFp7ltGd0hnTLm11VdwpelcHTtVmrBWb2cTykvPOw +nixX9/uAIcA4eCw441GSa/mDyeaZG/Fa5kE1Aqx1YNrgYIRcw53EttK6Cut8yE+m +tRfhc9GfFWStIHZBfd5wJLJA9863F5PusF6UrtO/W3aI2WOPTAOrHvQJJJC7Be+/ +8XVlRrtyimBJzzXgdHbn9X9iU2brJCB5zf6DF8ZEG4plqQJq7R6SHsZEdsy7+5WZ +EBrcXC/I0rQ1BbmVZpSTpVPBWimsrVejaI1WbI25Dq/6gntVKOsu5/DaBkCD+tNA +K73N9B/Oa2gZCubK93sanw5JYcR0xVNTMMOBfpTlKVFqDydwEcdLN2Kv61Urf08f +OFCUu8Kj6Fqh/7liKoJk4Ln+u2YV7mJuk0PSw7OHkC3dEO//2RzyC4eiShJ4an6O +jCFTcAwvFB6IAUFedfkRiRik2rJBvy8hemXDuFzp4k4FxwT9wbwUjIzFDppFbCm+ +MhWy9IB3KbuGpmUdkIDdpjYQ1a2KUKEdMnjkvuEAMLQR6hDNLgoXyEgy5ho0zyPj +0Lp+fLTwoLikkda7u/ChIpNGce/nhzWpe5xQa5iE6uxWAy3LJtbOPbQkpvp1Ht0v +VYZqvHOyFhV2p/K1TdOfS8zws0QZ/sXs6qS5O8l7tvxmwzPalMa0osA8U8SzZsdv +KMiWVijX5cTZ2hJC/LgAKG2P1h7U7ANVCxzLruBHr3P9lVML5VOdqpDAyt2hOnrE +/G7jrELZtXsM83hlyA5V6SM0yj05aArA5Esd6NLz1IuQVwMGt5n8orMmrtKskgjt +177rpR0pARGEVXN6746azHK+J4KFtxnFQCIwET1w26roKms7v0MqwzNnXaqXG8A7 +7FEs8enRp/2hKFww6qRqH/LR8Az+20P10J5rQPGxrrPfezGl288XHQtXsQKoj4eZ +qNRVSTTsDZxu/LhF3tuHxFkjZjGUwAp3gj3MYKH9AIC8Iel0MbpwOySBMwB2iG9E +KnGLAJE+1omXmwNdnrJBJPEJKfFSCXKkut4ScwvyGia3MjRcNimysuiciX4EiGl4 +TS0pPGZG2uwBwwoUsIVRdJJFRErcl6/bnMTYOTIaaBh5DlijRxFKZuhjpTzGwxRT +iMYM057BGdDWFp4+w6BDZx/ec39qoOwzBblhm+eY1EoV3VT2ZGxQhHdHB7jk0NHG +2os0GELcwTKXewJAE9SGFbUEHj5XP1ooy5E/gNmkytQck0+z8h1X2zAQuPY0tAzN +7oM50sThDdVKHy85BIeKL2yEdV+26Eyklcycfr04GZFvZNf0a85Y1wE6/w1JuE61 +cTW00XeP2bhQKicjbpluDF2hOlts873TuCvnKfEaqK6axpWBQUHHovJYqDTOMTQ0 +MBhgvuoeTrnRIvuReZE+0T/R7PWfBbIZF7SM4GW/w65xLpxo5toMgFfqz3ijRifB +IKs4nfhoMmjWhYbwY5aWl8xBrXEoTVPsqBSJMjxJYxLJPXHHWyPky9kEhHHdaQB7 +KmdFA27FrxoBPIbm6E4oW7VxZyBd5/lfkg7FPqDt5Zmv1euCuh8O/ocp2mNtvE/F +Klw4i7veTTAJNlDsCOx2+TDpujXJCUX01iakx6MJmdm3Z9hY1752KMWszKEJu3E7 +tIwWBS+YAJO55FSvxrBJ8Dap7UCgqJztdVU5MnzxQ54jhUtjOkIgOIlELUOzySQ4 +TsAztV2qWXltKJLFNoxgoB4V4RiFCeWgIgf4Qc56Ub8WFYP3SEnHH4sb9vmjjKpb +/nTeIpbcdtdaoFId5CttgEXcsMZfbhwE5HzoZ2Gy1CcfDWODXtszD7F+EevwXY4s +B7bnSUpRPWnCO/EX5b3Qk5CRQGwDSmJmz8N1449Sawh0aLBcwglVPEou9uChxuoW +jF7jYhtthAimkMQO84Gs7eFUIDNbCu5irhaePqqw/s+E4+16NDUk54Qyj8/4+Bj5 +xGOEmgiqmtTH/9Wc/cktIqVTltwF05wWMJkFu7EDStfDj5lw0CiQuqpk/zNVKM4E +zj7dfRr+r1jyro/PieXjRe8G4dAnHg+T/RbsYSYekSP17KzzLZUxdwj/zGZCDQLh +a13rTu9HmUOk2XhxZ23OyC8040iNMYDw4DdEq8punp0cbXPBArrPOJzcbVxp+Sj3 +POhsaaUCSdY86QJtlJntlrcoWo4GRcJv+3Ubmqs+h28lak0Ff9aPFCGk6Qbkby37 +NpUAdD/Xtn4fAa1VPdymN0kLqUCIwrGdp6q8qWpkygh8m6IsteR7ZyPkvLNXSidi +fXqOOYRGC9A1u/5NTpsi1eDA9ziisx/BFle7NgVtzut9UNmjI5LcqowYvv6wHvqV +vngTkHfB+vhU9Ju11lq1DHlfCZNPcioMhWzd2JPCj7BEDt2UhdD/pkYtArW6TL7O +Q5l7Fq5vPts8CU5nz6DAD/Bknf8CU061Nj+MWyhvwitYQeE/wRCNfzlW2oxCi5kQ +MPgjPdx7a/Cow+bLzqJb0XCWvOk1b8IFMGj0eLrVt3kPPmC2/cG0PsVh1I+O1XFh +Da1qKJM0GhjjEzhHAeVpymlx17ctIWs1gR45cOhJK0t2KoKOyMpVCZKhUHtPtmc8 +PXHAAam5rHJNfsH1LNbr+MrBJ5YN/aSfcl2WFJIPjjT4Fhp2Goz94iPfJrVpc0HY +tQYa+4tVQZy0CpmGdNsVkuVPPJHXyUm8D//3cLQ+9gqvH7o4OjNP3Jy/klN0Kgtv +KApS2EFVglNBtsVL4IzFZw6w4RDe8TDt8wU2TgsLlqdNeK7ri3r3kbft6cQAWtaL +1mZIAfKh48uQS0DZjsGzhZq3wuLuNGefFZphkqa8faP2TLPjxb3a6AX10n/UYRYe +A+NfTbXdvNu1wYZW8M6lHaQ56m9PWN9WyhsfcOnBPelJ2ckyERyoXvnq1q5jvhgX +LT8QU/xekhPMryctFKhXTVtG202MNoME0o8K8sVbZ94ndSIBagQffJJMRxg7qunN +IuT8ibucQb/3z7C1mQbrsoFsFvemyXpk6+uX2slyvXMiB296tOilcNbKVCuvfZZB +XFaCtzBDlLBjG7GxIFkucO2TY4zHv/s+jjKlDjZ3A+WOylx3Dv3jqS1q9nqXh6O0 +uWx5d3bcQ4ZLNMv/Tv/gqxpekja/gplsvd40Ly4aVPvv3zLCvzhQWmv6GsI2Y/F7 +5blA2YG293KGbv7605vnJK5g2tNR75a2f1G9zAHPNfYshfRwALfQtQqtfPsIeRZ4 +AUkj5ckT1S86N72jDeNCBlfFG/ahQL2Av2RVa++1rcRf7FMn3Dg/8HjkUYKVpU7q +eClDbNnO9MZJRr/ryHiCZu0l+KjZvCY9eihKFvsjPaZOoCDc2iZiBgA3IYTOIOf9 +GM10S1le/gxQYDJ7rtgKFo/KsTh1UWKuoPrkaC3XDDsPYKk16bpRIJ2M+1ptJSD7 +AxjFafxECpjKz0zO+puyqzfQ7C9Z/ugAl8CgFvVeBhebj1whH38yn6PlFvP6rPmm +WZUt/xfBXuK1oHEMW0tE2GT3NJAeyUxLDDUepGVqJpeWVNA/wU4hClO0sJvkjhaj +WmSXpxS+JUzo/CK1hGGSFeu5x4xkE6WNbOGz2pAY7JHsc3+QUTpAVQlsVus2cVZd +L2TTB1d7yxR3Fn/G6FsBvcS8BP08Kn7H9g6Y49dP53VAea8vUprNJpDgNTlptrqx +kpnwiXJKYpAAvPks7n1S0AwEDcwUeOOpHrpgWe4keNGT5MQZDyzZxiMvR7pdlxu5 +JXIpiaugWAjjNOE74nRYWM6Zxb94vNBGnAZ80MImgDnRjvX3ZfVoUzqAD4aA4M7Z +8q7u7dOKSJII+o6eKBqquKm/ahq6q99mrSQWLngWPH6wb4NAjOMdV+JssyL6IkEE +v6KjNDUPLqKSR3ou/bvtDKWm7GDyXNqBIyEJMoEruzwoIPMoGuIitZPC7a/Ep/pY +m+eElhIFMSN/wAsOCGDMmz8vg6eeukXF5Dy5J4HLMyAafF0qYSv9jsK0C9QH8Wy8 +bJZxAhHFqB1tucPBEPQmFQkIv54JUdxzxKqfBLoLnH9ptcNisMeSHXXzlcwl7c7E +7zWRJFt8K26cTxszg6PdTlyU9Wq20wUPtnqvtKW8a6r8C+qSmC74rYGMeLoJ+lM1 +qlExrQ9B71px0CYrxgOtx5jqsSVXyDytgk61X8AZ7cnrPc0E30/aDIWF+qklE+oi +O+DVxzpdgWQUJwVmbVyUFmLdDys4WhhW55JcrnHm22u6kHP3LWRoutESWhKawHt+ +297Qax3eyce2iaO67l/xxFY5E1AE3XeGi5JT9wqD8BSjVsFRX9M2hz+QbYCKVx02 +1LLMkHbesbTYBoZUHCZtauotm0zxbPrUqBifq1QwyEoeci8f1xmqhLLlQ50z2FoO +KN0LOeaoKOrCEP3Pl167c+IORKawHT/Bg5t7D8UZRA/Y2GIL4M9MHIF+4pvtetkm +zw46rqCsfJULyE6bXNs5vcYgRJREBvNj5cYeOcQyj9FHqD3jmyvIQFa4SGEe3eu8 +radfNmdIPkWQlb5gAqN0CGS+BtO6hKYNiiZwCbBOXTZ+cJ+PmL8fOpTUk+Jf/JAr +6YlW0NhG+NNxp/ia3Ro9xPDK73xuPhcsPtOC25gr3V2PnR7KvrU/8S4kSmv6HTme +0H4VYzIUDOYT7vc6dTTZsGqKyUj/faoHfh38PXnLWJGtjVO8XnlWUQBpS9kX0/we +DubSAdB7UfeUpfjyKJYIlRrO+eDqNnoOwRADP9SaBvkorU9eaqJECBZThGMWyfnS +79obNucWzz8rWyCcGOySEVClLklNlsJOvsRyF3vp1IKT+eRUu0Y0VUlWCUhB7jFb +wtYIPROKBlzQtN4DSfnS64xEdELIvN5Q3GhsIaw+jSLJKZdG2HvTkeCCLwoR4sHC +aYoN/kjC1S8B/BPVwpOhqHVX+puKhv6Ik+sVzqcOSJybCC5nfLBIzHJKk3KbZQ+B +mzjjNAqayY5b6YTOPIU9r3ik2tkSKM+bekyaK+dafjChd0Rd09BbdZi83FSmAR8S +xzBXKpYz9HVOESMcdv6q1vsY4BxzCvjnM3eNBJvjwuRYhBxjz2wfinfxpu0D1/NU +O+xEQSMOZyxCWXX7gysVVXhayv7OuTWbQFfxVC0Igls5oktmrrQ1X8kr1qKhfFpZ +kK3d6khinanuL2kU8qtEW0D5OfRr0K/U92K6FKMTi0INT+2OtcInzzFqQvsAItgr +iyG8cmgx93HuQXcT8qAx9YaaxlwPaGJjbzeswTC7otfd53JSgerny+/5WPJe6JJb +kv28lmp5HMcuTvAT1nKwJdAf0547nHcVgVxSKJWWsShO/CFxMns48veHL4Wx+Ifr +GhHzC+ayS5UwN6QQhCNSHTbb9Ze7gzXSWK/dJz0e5e3hwJ/AvHCNWrsajIyqTPeU +96Yvme41A6DeRoXgSnoTun+TYULRL7BBeitcHcYoyPw2+pSF77aBry2mUMDDavKu +M5h5WGfhCtKMitxwXJsAW3GLEiDEJGPYJOyDD3r1WLvVKtHyfJ/3pjJxalrgdoSd +LlUyW80LtUN8rGIADBDYuMICfdpFujXqIYUJONwK2Nd3oMuACw+OqJNCTKOr0Omw +8XZKHKbYDnXwObMT9zDJVeouwhtnILxDVgN+0Oro2LTVjq9A0yjPJ46ZF6SAoStq +l0/+Sxhkf5Ca6UXJoN1eg7x2f07WB6ak4hTGrHAc81V5A1OWerfoFsmaHqZHgGwh +5tgWj1uCDkBoy1wCixNMdnlymyqEX6yk/LQmWHhEl3myhdqlIQPbEGH55KmaJswm +bP4jA1a5lEvCmhxaKNeKq8zAgZhToq1w+fIFvponW8qcOwILXP5y7wphexfnVJCQ +R/KILgC4DqFo+ghRQmEi9Xf7qiLHHUMqeshgPqsK+gNWHwgGQZV9BheT1tnfdts9 +fvAEkGtPsGq74dGJR+cNVhipnN+yP+vn5zYBB0TXtzyQW36C7qRhIec6s3F+vPqP +YT0WsNblmayyhvhyZQYTfcHyMM2l0yBcpccFVcWHaqX+90zMK6Axhqj9Cn052LzA +aTl5RgbjeCEpCcN4Uf678KH5SofdzH4uZFI4/Y5w+F2Ke1K0LLkCZVLpC8yx52U4 +R+FC0AKZDUK1ipsd7W6yZA+CymnhldRA5cYz+C9EQDnkfqfbUpDqLdTb8cUYFMez +vKjP/Yju3Rp8gQZ+MwOIPpvTU73HICqxYTpGMWUs5Uns7i8hHziVfgNLLjSgNvfE +9LlDyROFerHJOZe9UjzRO5OpX0rTgydEwhCitrr88YyT2OzSToYFl8GKT4Mce5EO +d99kE3TeJxDbybc4JCireQL4k6Rmz52HV/WBUFbnKrLlzn7nRWppq1XMt4SoYnmh +J/lbuzGi3OvVrMy+hXxog5SVFUEUSeyqzu7Zg+1Z4vizilBXuBkvhlwm4A1+Wso7 +CfijnTwXjXFgo4+QceKrPGwaRaUj9u+W5oZCqI18DHDowfEw5WRvzydTmQq/O1EB +xS+HuJL9ci9+894eYL5cUgho02Hf+g6aG+u1lJc62usImGnL492N5fc7NfmWm03o +USmzGbdzgAGF0HfutPfsK26X7LYBhjSM8MQSBZOh0MPlyUKd3BkhUzeWw9qclJ+I +TDeO7VSMaGyq1JqIOYtJx/kjSQxeZpHgy+BC839DIYNawiir5CWxXXKIhIJRsOBu +o24lS5RpMhe2JzfJQGTHCE0KjNu8IcXBdVsnm/6FVzT7yIGRHJOMusGkruFlkDQU +pu0NMwuUK7Nrt6I3lVZkj65UqOb+IQKQNCrITK+kbE5oBFHUymTICgL1w0TxiKtl +dzV+EDVc9jojvICkGwGqxuYXDOw6O6erpIEJ9E92odg8TYfPD+4GrhEAjB+8ZVZa +naFP1EuF1HKH7jHS5Z/Pfv9Spy2Y51TQtDheKEfQ52qElfLXjr6ObGi0iXamdn0V +FPmCMKyiH8pREFt6DaNxw3PZhV7nWn73kOGdA+18UnY4sjCwQg6n1oBcOFx3YwCV +TeFiUQ12cGjAynflUXkiovObbucTMcIupqr1IigSwQ/l7qkQ1ow2bAnYLl5Ibrr8 +/5rwD0Wn8GV+1kN13PCjSxu36H1AD9eoE75Ov88/pfxBmXpBJSllUlCNSbUHSm6g +/+4p6K6lCnSk+MVm1xzvnEdF98FItL5zu6E1JKLd2mGUWVW4/TsrZ55SlDWSchar +Lq3EOPtSly5d3cxCrNg0fapAIRFZxZRqXz7knjaNZ34cT28mst9U4/hf0OgfnSwa +156XoTAkCURT/MMRrTeATtKAZ8Fj+k3LMAS7XVAC250YdXXHlQyIAKAq8bGEcuV/ +AOCaY/fYeWb8XGaBwmQNb5og+mDtveQzCO3hgKU68A+f9cdjzWQK8GdS8fKSARKT +0JFwVkOYb6SHdTWU+KwGKcyh4S/QWLil/aDZRDaNZ0YuuV/Puxc9xIOOANAKT1Be +xnJ1+DV1gpBbqx1AcKZEocnryxcKxuNtjkuPr9r3/QvwhNMf8ETWDG6+JsFjfU/2 +8Q8Eo501p2AUy+K4iKoIVMP0NctSpyth+kL96ICXz/740ylEqDUuUBTcOd0tnr6T +223LRlRYFXv7DieZRUYS242D0dtkFI51z+cMU3jdikueHcKthOJG7IR2hckiosCm +xcW/JSe+nPvdM/zQqKbPhhxcWMM3ZdM7nM1AAFbqYWwiSBBRV/Z2Gs2FXDeAjNwi +Cb4lb8K/1rMz1fz/K4e0XX5DXMDG7Pr5qPNp+bosmbCKlcCasgighwbqs058ySJf +SBw+YgDJ6G9FZQ/irFLqg2A827MKDSxdDj3xDVq2oHmHvPUB/6bXbva5mLXy62xN +r9UJhf50zjRT3/BGjeeb0hFniHne9XaUyRmOnxjAooZDkZ5b5tFAFaTflfhG+eQX +UpLPrZns519k9LEFDC6fCnxua2AmcJ8ky0rpQZ2kMfsUOYi6oeBKVQgpHq4DyeMH +T9P8dVXBlXuvqCdomS109ho4yW50AOrsnq6GrexskUFPV49fGbAd4xKKZNIOhjxY +ufaixyEcVHe7+E36PyVnamrTOyfrGZxme27X5F/atAkRuwpREAKSfMeDl1rL7kHL +AZ9FTDizqhVdE8jlpXL7/3QVI0Ujc+NpUtj2LTPzT1uMYZQvxFa7wtRujd3ZJ0+g +ukeriSBzYwFgcKYBJYWzx4UzqchYrEoNHWG2YZ6/VGxl7Z3rwQkMBcbsvm9d2gXB +yyKBuv+HuutvdFQ/0xOkrp1H1uJGIecHDSPb3ZERajyx1cNJxyE+D2g3rPTS0SuW +hu49NCCde5C01UvzNWLc67OIkwuQy3+HIxWMULxCASKeESerxskXH/bAxLqVX/hU +WEfK0PRXXqDAci2/Ko4diiY8xbeKI8WETPcVoxzY2S8mWggxXzH0EeUEw/d9nM6f +zEMyzHoU+mCsbHeoAUFLT7RrNpkWAwUytrnHcR+tolwoqkIyiCMAwalzvmqpb7C2 +IX/tVEELs3vu4QWrc9xaMS8BJZLPztmGvxD6OFI66Eth32sKDd+FG3nH+3tTYDtI +p59Z0F0/gmoQiaC4ficBc0rAr/1r7Hn/iorrsDZk+kqr18tiqenmjdM6ISdGQeWs +xCNKLS32yFWC/HfD+gHYKMYBwizX8gXDTTo1am08YljFfBhUXiTRqK760kmve4mg +YFRzKrmHOcPmj2LXf7DV1De4TXAe+l5R9IHNG7MOtkO3TMzMrolsoFdC4f0w5n/8 +3Ec6GjQ9C7FJxForSwg5HFGqUBHhNJgEAIBNf0wLWnuyXRNGuHRCzvNckhxXDsb5 +McjEfW0+YTQqdM8eYpTKrO2KH2I3KKCnmhd4vU70OuhTyeZ4V/54h3YROWXrnGW9 +c4zEYXsYZHoiPZCp3UdK2B3p5EcUvQLaLor7IcjZikUxKtVUyt9iT+3vCBLdp8UJ +i3p4vYchz6XMccmEq1IjCXJ671Rp/yB0PPL9kMVrlVar+MvzPjm1z76goyKBsv3/ +W8D5l46x8v/B2Gftw1QDCcjTub+JgkuG8Ag4V32rbOXkPwv0qYqEgXmPJIbYDYIG +ZYhvIl84IuCiCpS/KGqdXHUl9Wp3R0eP93x/TIwI2XS5AA/YMr3dbIKL9tk0+TEy +1hFpsnP9dUHtX8UIcoWNtHHMC8U+lKIe81QCZrpErTCuxJMI3j5PDcA4Jm2tLKS5 +CRf2GkiEsFx16Abwr5Dx0RWD7lSPzYuu1HT9RH/Dy5vNGuLtafvRPPwkiRVYTiPL +oZm9g67zO2l82cBc97OSakd0GIRHZvGiT8sqE4pcZgJEyPsp/l0ZqfpITMWu/1R+ +RTcmbeW1DO9StNy7t/czVQEQZcTH6IVk99vsDm6BUKMpBaDIp3F9fW68JjsexPKG +BsaIZpa6WQlx/4/1WU5baXFcNoIkxemy2K8cEnHs77kPJop5xNssE7wL8K2KLykL +6JR3PnlPBOyby2jQAc0+wnNRdcFU8LGj6mXyRZhDgR5D/ME4/o4L52oZdTcF7g4F +nX1bkcU6vADJ3eREZXZ5koqZNCsD4whI3vP6VjZbaKGdsWKRhVNk2Ayfozb+BUGI +kbsUlUzm7wJZWX68PAIVO0lBFuxaOGZjiApDZUoLk9ce8/lK//gm+p7HPZOQa1dT +8zqHDynF3bdkp2RJLxR1lnmrzJTt54YJSjCP5aUJFycD328qOIC9EpTvUNOcskgJ +8CZk+N+RR2TOWxCdoxLBqkpSpO63lH6vLlLo3o+MQbk5Q3NnQUlD3EXJCzGr072y +SZhVN8uU7CSvOeN/CExGSGr1aRjQa6YViLKmIImb4uf5HAnBgRl+xNXVsbqjbqQS +53Gowuaj0xY0Voi3AzZaat2d+a7DThggP53kmLlgc4nJ/Lh+Hv2ndEa7MYVJ21NK +mbIV1UPWNzQfMAaEPFyC63wskkEe5ResAzgDBrzcxDZXQE8ws2peF50iLpKr5qOS +Uv8y8/c6LHrMB0qk2UOdbil7a3tzNm1sLn1mSf3+wVAzd1nu9AsUIavd3xTS0Ed0 +HI7+xQQJQWwrM/fqLSKDWNsJUoIldpPEtTfepX/R9K64NXV/dhIpW4eHWNah/SSz +aGXY7AqjpE0l2G4mGquFINULapPn+fZBRiF5DvX+sAnqGp7i/S79B/170W229zf5 +vuW/6QVNVLGhwud1nIk4TaoaKOCOgbmheccUuWM8UHf35F7td16LmYQlv6LvZLh8 +TtzMPlaJgEwqutXFSSdTorKD+qKPnDnatPscVR32kypECJCXiN7rGVJhrbG8WW93 +r9EncD0tEkdy00hA+nICb5w3czO477WKAnxAOK2rChr6e7l7M11jkA1tNBV/LJI0 +dQDgYqA64/ns2OBZG3hzik/dfr1vrSvndbrdKddfNIfl59Ddiaycg4AOL86YpNYj +xgpvmGHFXX6Le0ASthEkb8ZgF7InXNCtueRcsYGcfXxLyQ2lzUgHPBQ6tKsK8XUC +ZOHCBK50nxV+zKQZPbbvF96GtRVp26mHb6lawA6x8HQeovNgivfGcFcsMRzI9ji5 +Lsk40FzjcZ1r90ume9uG+DpHFLPCCWxkhYx1EtAFwe1ODfFcMXo/Blt6sIxL8Y2Z +0RY9EmOAJR1w27Klla/nor4W+9EtI8AnVaYfWgaIZJrjD0nJgq76rWj0mgwFIwl8 +z86q/7YeqKN/Vbng//5kmjgr4H5KLKJ52vigOZacZNy2SM1vlhGH4QSoSrRhfTLS +CDNez6XZD0tsqGCmXAGt37huyVthnlLMvWvHoJ243bSMVsfb3o4+/0Um7yF870vV +MrQ3BtzwVLv16A1K+SCQEIZV/OxQgO9+0p/EQhtx6yvTcTiqcEaV9k3bZJPld5Vh +IYvUzY001ET373u3cTbbD/lyT/vJvdpy2gsIYeArCyiRjBu2f5nBJpTubeeXs2Jn +ymCgZUEtw1qQvy1aQw4kcoecnsp+C8aUuHFBmRebXsxe+u58VCurAlax03u6K7SI +gAQ5uZxaECChVcxFhRptU+KAl9lQFC2HAJxUVAE/eundE2/Tl7HbMD+cZIM/zuAS +j8ZJW5Y+yAEAM2/dvQqjGScztUXgbMOpsC5zqMSWhja3TVw3WGKuLeJRZVj0h7Hn +0r56oV9fdnBsgkxWlgxA2K0M5lFU0DuVb0VUjVkG4AUW8S4zOvmOKztZAKG56NAV +3kzF0UFVWQZd972Qp52Krs5lK+LwwHeRhbmHlxU2K3h7GELuke7/r4gZ3HGACC+b +vFVUj0U59EizNRftJtlxtG9KqrPIrjWG4w5S5wHN7E5YqDd30lXSAMn2bJp1U1mn +K0uUhbysx+YgBGJV/ShCKhrAIY3/onONwvr5epBOQICQKkaMabUH119e/M/110Ir +Q1mcRBkAEntdYgAY/9q+NlLPB+Z2FVDobyhDB7ZZbs2/HKzFA2WgcdJvo3gs3pkw +xCV405FUbzgtM+nYtp2n3Qjg2if4jNhk56zPVq9EoumIup8JJQo8CeKUcjspRE3E +lgC6eyLtilCkYzXVrmo5UZKZCycOHI3AnPyIYPuKCO4XH1v4t044ZBnGlNtG781V +1XwVssg0NUPbFW5r+EJdLnDLTgFSco0SuZdoEWF0RXLIUm67M/Hl41a4AjjcviXk +b2V706Ad7XxQACfoD99pcuZ7bOWZNTPIP3KfSFCR3U/0GU0RFGNkr0UcTvaE/v46 +rPakKpp2pRSq0omtN+2/JQ0u62H7BYQkXQcW1sIs682wf7VEVSS65kL+tcn3WgbW +NfstTi5Sk9ZDBJHSOpsj7Nu+eXoZMphJFo9BTQ84DfnRHxNIiW5RfzsJydFQQd+N +co6T7Md1zmEnO93GCspDaSJ7clXnGa3NHLISW6zXnKeD8rEEZzmebPQndGHVKME9 +qKVRTJmu9MEDNEm4c+HFNpB2iZA4IJmhGJHwj3Vmnekrjfz1LaBIQB/PMlzk/kZi +Kw2NOgHcP9q8ZQFFDuu1MKhELdChCs7m9d6PxrIQfRxUeQRWoKfRONySA7AvM2wq +INoJBJaXeSryuI2jvIftQ4vObvijFHqkMdESMedEduvwqVuP1AmWUcW95A+EmQ/c +lVmAGWOTUj48V9q+Prgl/NYwQy2wNHd/cuXr6UCnrKTpetbEoSEFYlsZPHSnWW27 +SI4oRjE43FxkQQxpbGPmHa4+u3t+fF5GCn01uU9aQgKwRjDRp5MAjxXKDCOe3qae +jAfjaXMhQmlzfwNgFjvW3fPf8hBz5/kXWjNpfl/0xXtrVaKCJylDz+rEAwjPg5Hs +XxbC7oSEtb2nOtIohNMsH6GYkSnw76vA7d/dBnH6aVr8ftHjvTIwWi/9KKzzqLLE +qwxS+JgvWeXnuRyqQmwkpGRKd0vqoOYSc7tDdQKZ297jc3H8R4L+KiO6aF42+hmA +d2zItoJCPWbGVd2qmshx3wwYSOstxdKqBLZJpiMZnJhHngEMCluqcsWd2mlmbRIo +WjOy5gorRp3Y36C/ZegM4y3QZ4L18nU8hm51UqJiXqB0Vl934IrUcBHUWd35/bd1 +Mr20Xn7TpxtEBtt0KYWCERWK9zbthT8rkHknCGkUt/dxQQ/3UD+oLMmzAAAdJF+S +zKo3kTGLoK/vTcMLzOC24O/HbYQASGRUC3nXYPMib61i+L3bO+BmPyz4/2yERZnV +Dk8AeEjdoLvBHzu+hO51ccxbArJV8DlNZCfSQZfuL8AvpAGaPLMcEac1ZZ8ij8sD +zAjZHDrmv2Dft2FEIAHaqAl6sqEbEcSylXvK/eo/rrvhrj6WtRiPqD5N+jNFATuo +CdDETtLiidtQIj2fue4TkTnbjF8MzgbiLmJgnbhaQuMzbmqrdDW9lTnj+mlD5bKs +lWojkxHNt8yzzEiulLfSQQRVXX612TAdbUNM3aSBE7mXuMrNxZ/Q2/EQ0fJpT3Gu +dlh7sZGmchDo9p/9YeJbBRrz82scqVZZNYMqeLxmigzpugxnEn1gdatYzItLNSb8 +hfKvz7a8wlN70qyBV8q5GX0JXXNrazuOYM7wjkKWVkbnH1fplLQytTVWzkX8MBpO +Z/0X4FHUVN4xxucoWnTQVYX94YBxOS3zBiPa7hmxjvpRfIgGKb6kGM7F0vViRiVB +4ivQHsax0v4SOpGL4VFFwursdPb0CDGNoIHIhZqdtVQ/Qpo0I55AX8vMFy4KzETx +Z+Uc7CIs/ejPWfXaWOcEe4SwHHXnC8yxfATuO6mpnkstXleLOK1QRQIU3h8QCiWC +0TMKhD03sxIldZdvzANf/6W4Xt4ZOAiSdv3hPDfzrhaDtH9oF6IOB/TcLPGBHBek +yAhvrDEThK7ldaTdZK8hrmauF4L7AJjhhg19s7uLop3ljWza2r9qiiA8jdoR/OyO +yRfMr3oN4sm7+dkHax5OMOpmZordNwncrIpPKPUCfFtmGVZ/0wrfeltXqUjUOaDL +s4ryLYzR04iXgdwk1flx5ezArOjHWMdopVVMxImEveCjGC8wLgnWrPkwHwUUDbKp +l/zUC70MvKZAXJK7wI8uh+zc59tpAvAXMdiLgdavVN9smTYWOpqJRl6jXSSi0bzz +TdRAL1whJpFtvHmG6ENDLM8qG75QbhoM3aO0prBlVt5R1dPlHbegFHLv1F0Z9xVQ +rAO2ThHU481I/qj7W+8TlUyQHKvdsnDVjs/pbMJWrxbe7oskXkosZJ5VgtMeAS13 +bOAYgUxS8lObZ2hV6VqOcsWlzuwIlbfxBIcAhGmUylovEFzPTZTj+ZbcbPdaKss2 +V30Ub86Lb+nWz1hR6CtSLo+DRdQqw0o8Gj4hnbSq3zzQSE44HIlYwjl2jHR5LC9y +eLUgzArOjmmYbIIAbDoXiL1SCwlgMUSIP8C4rj4WkP6D1/xxOH9Zp6vIp2q5MKEG +z3PCSR+hbr1d8o+lE3VzHWmXHlIKIc9erpjeccYV3wu+40BmlWPXzhgbaIlo7XYt +WIOIsgnEi4J9Fn6d9h75P8eNrHUG6aseezVUjawxLZBT8CUZlhx7A3icLH/W17pl +cMombnHGCB6lJlIu9xapTydf8P86lR7dkNjaP0/PCfl64VR1mdZWeEVwdyVzILzE +DbLgNWebdy/Bt+XifpYAlQm59+ohqZYBxRAdWiquhAGOoXGTP6HjurLO3LVpk4EG +xh+2jEsh6GgAZEL6dcA/y8W2qSLOpjcpfCNItsyMeUzwnVQaLTA7Qx440tg1J70V +DdljnJzYmKMTC3TOKyHga7PhSJDeS30JCGwsz/PPoD1islx2wJOGZH2Ss2uhjjKd +gSTznFvclMDOVWRdJaz/uKT3+LFcAMZR5+g5Ng4Y8wx2wZ7elupumKmCE57FPmf9 +13wPmHfmk4czreprhDwGvXJbhGAFe5rQIDSI3N8/GhKFPoikNN3hUOnwcu6jryV1 +dFzApEQTfRgduJ5r8tSeZXkKmI4Wbd5Ibo0uhayAcDDaFHk8PWbsfhOY42HqbF7U +o7fi2qxYm5o7JLExQtP5QRSHmLPOJn0ZMGrmaWWaecc39HL+6D5SJCzsbQuEWH1T +kSR1Vqd5Cad0BvLrznlpPKIWHSkEyE2dWGq5BlAAWaV5R+mBhpz3uDTVxwNK5ibD +5LdKDhFFq2bL+IuGHLeBdF4FJQC50mDP2rMambjP1nVBuC6vETb5pK7hC7CleoZP +HLsBaiNQxR3xbf75m98U1JfV7Z7Bp8xTo/5lwAvBdMkyW4Lb8MqhBRWrAPII+82Y +wq/qapMm91RXQmjpNdXR8B2Py+tKFwn2HuuALKlOdyy2XPsWSYnQKWc/Tnf1Y+Lw +8Gt3GBgh6B/YXCzLDZk+VhWvjlAG0qPbSVf31K/8kR6sgD3YC+b3AvWm51uh7rdi +RxFdZoicIbJ3Ma/X5gCGQYuz9wt91UF35CcfhrwiIw1IyQiGXYBL1W4TC9uybJ71 +z/ye1c6O4HeChRJoNrPv8X2LFiWz08CtU3Mgem+ffNyb0i488/EDUJtmk8yDhP/w +c4I+f7VRPi5NcehrBDMXq1hJvoyJ0eDNFzGJuvqK7E4kiqxgJNNctlo/oezqU+3I +ZkDm1GJBNwqfZqKCzCVvzFHUHij2LlgXdrdvEn+qFbWPB41E2hiL8Iy6dvR2MCpv +NaZz6l5pUIp36Yz0BgxiSKci4gFk+sfSmbetIHHF041sPNiiuk4fbAIrFOvxJuKT +kaLkQdqPihUa1vNUje6ulRokpaykeOZDa4KdbMFPGbkwrA9VYtu+QT0TgK+T6R1+ +Zl/RuCwNupt5qy64tLKr4JaNkxILc5f+2Y2YboQwwdxwQICr4vWhp7c9wPSTKWHD +ayhbVt/KmiDTnlfieDCmmBEPT1ngoLkW6tMkWuAxvn0Cu6bY+StueLCfZu4T1sJG +07dG6lynf6v6FOAyNa6n2n8lRoWBvmUtwEHWgImbqrW49z4h8bP1O3W3XQlb8BJX +LCGLnBDIWfSR+9dX9osy47LvycO6lA7Xx5BqgBHfqCP5iwkUMCm9p7Gz+ClDmZOq +nXVu7YhoIVXUoTyYLuLdF6K4VNVMywSYiza4GnI1Q6AnatkzXwH2RnnZyHP9QDcA +2q4xHf9yIXCIDVmLfVJSrINY8AZEuzj3vLq3QWHqgVJkrfuYwEm14HabV6LlwiJR +O2xuRAgrh9w2+0HxQqPqGSJqFr2WFz/AgnqX5VOw1Ls9zuQ4wqBRqgLtrm7U5LvF +eHbUzYXhLzcPjexwt1eUgaB3PkfYEaH1lfOc4m7XtO05itRbHXRAK1I5gadCBvy+ ++4u7SvwCcu1FH6jGsMKroO/J7FZN2O4Gx4rYmmbCoTNZWPpPVJEtj42CwY6G3fLe +5LRdj09sv6iDhxv2DmtCQxVBCqK0eMMZ73iU2IM8dCmtBKk7jd7W94h/N3hK3rqb +VVHEUcVW45YfrHG2BTAexJOVbOSJtd8YO0abMnYjC0TO7iuD9h4h2gVZ6VJAyRaD +UQGUZdaCzdMUJagzkATnnPaJO7CUJdWjuv130WJSo+gsxDJROJgA9CHWhQmPOQ3c +1PXuhQNYLsvH1U1WJXChrO10REqscyxvj4I84SzW4L1BRoMxr+PwSikFUThcm5sc +OGb4uCg4CYSuHn+IGkqBdZCytxAjthjhgVbYyA56kBRfOVVeCV39lmv2DOfj5IdO +ZVriQIM+s7cDWNlyW6XbKUPoJRK1rZRC5MpbsVog9Y1RYIQiNZRFlZW0VVmamGQj +I+W8tuJi9O17Cew8WabWOGRj70DiVYlreDimTpBZKc68EfMheqWBBodlMIerGfPf +Lmp6XeVg4M46r1oeDFRoTOfiVHzDfN8tA6PBllSRY4GqAJAmwImvbmw6L1I4F4gH +HqaQ+rpMTZwBU8UExTwoV/1spS1qZPVG4OVPQXrxToTmqeUWOl4Q6eGNldpvkBR3 +9ukms3tSNqh24e3LxAY4bqQr+uIIn1Xqcd5YZrQA8vCO92Vnesay9Yt1Pf4gdFds +LkXPHH0tVeF/odbdb80ZrwxRg5P3ZtWsKLLfprWWHlpi3mTOUGK2DW+qxhVlDVRb ++LO3rFT9jmSXn+0LUMtGnyxIf7joO1iG9anQsvbzpnK4tKSAQCyO/VM7zfUMTRJk +BguUr5nxaPX6SrBbNElFuEEN1ZbsoiaZ99lPXQ/+cKcD4EG1bIuL5FBxzubxSWM+ +W3Hi5Is6flw2TP2J+7DnhTE0vABoeYHblyKAWUb5diHqqMnIPGkIi2iTFsYkF2Sj +pWQKhUB+tXPZ6+0iFIW+ArEwznEEkCP8rxCaum4H25zIrsJy7NEwrQS3sMBhpYQF +hBsfe6BL1wBoEBBlmq1h/8tFQMD3YMnS18I0imoNO7Teo1NUCEykbBT3jgi9Rcdb +pgt4QJ5gSDmy58u9ztC4uqK9GOsc4DHzUFDRrfHu5rO13zLECEdI3mpsrI/NQP5O +MtGg7U54KkaWEEdWynT50dENYoVRGdxMzCIEfQdQoHmpmpBUsORzzIshMG0v5px7 +iQBGbtlQxeRWsCbTxpFrc9ngxcN2zZ7wHIFI5AQgPda1tu95YxcSE8UERRT+Oz9s +lGDH3sBAxvANt5RW/8VVzwttonLfXaDNm2MQ001teVXhW6wyiaS7gSy5QrYQJnqy +ctN0jB7/cHKg4prKqYMWWNRai4cqmZ2biZPzZd+y5aC2Gj/y7fvWI487MAcvfFu0 +4oyb1UBzSU7uxxhWRVc/kCkpKivljR5nQe66V+4V44IvZeKGNyITlSs0rZL0C+xw +ip5pNj2RBZzl2uMCGr7h1CzznlshCxhHj+pPhRMhdl500LArfKUa3hT7hDbKcwrf +p3sgOF7bEkSMuY7bJyLzC6FgwbONygqfDKv9y24LdGM9WshNkOhQqQDelej3T51g +ggiMFLCivjGJuCsqLNkFwJ9WIoGJvkoSehOyM0FGiUghKLtSSw86Pp7E58j42sPg +S8pRVDowbRaacvT2gCQEYOwTPXEU6qo1nQ3+BKNCVAVTjJa6gtVxglhND+MFSBZy +A5QgsfeZ74mB+FrNTVgNv47QlW8TL5Zr1Xsb8YzJnOft6ktuFtcvALBhJlSbzv2K +ST1IixEleSbgvyVKUt8pCjp+2WrUezNj1ZGVAd1W3qkC37Bo5rCuteAMV1GrdIsy +OdBm900ohLH8Yi3aIJocPf8Fr1Db8J6WC0umvdTmhGVvSfcB3fRyHSfhdo+sSsd2 +kHhNIc1kfYL4HShfInb01qNNjUIqspwmScwyN4wELEcAaSBwaMAzrml0S5pzb6cL +anzyatqlkdEioJxLb3h4u4w17PnS3CZX26xH05gKGq0PmSG7DQz0qHunfu1Lq7m5 +tZlfYu+F6mv4p9j7/l8v2zAzvGkTOWnu8A5d0C+EIuXqUOH/fnJ0CjoW11O5nHHD +EqzmwjJIL6L2vOI1T8pcXkE7vwDMecvgoU4E7rAkcbMo7oKtWhCY+jXrrGMsrHmE ++cAwTefgxlO2Ys0zxAB7ODOlHKXIJnvZ7rklRfFnjP8QeJmIKlFTh4Jvx0/DTLeZ +W6sVvCutnmuiWDdUFrA1oWiazw/uCqkzH7Rj3Eb7CAwOqBoVbxDc6orfPX8VGAVp +zRcIK8vogYaHJYuBMvQ/sDiaa8Glvra3X8rkSpU6P4QNrBQictrzfG4bnYpEsSem +oi336Begi1f5QKzw401WCNleCpAeW8Ucaf0rfvq0r4oE0L6bTmHZlWNDM9HIsRQ5 +a1ya9EL1ZZ/lQvicqN6iPuDmmgSZXQkfMgs/bGS5aZNovI+e1ikwg0eNGPQ6KLKI +y7hRgl27yEn5oSREP4DJ3PTm0Krjth7UXtIC9YEPN/t7lYQo5SR7Ija/Cjh6TtKd +fL62mXIe0C4p+XSMgrEY+xsUjl9afNj81r4OCuEREawF+fzzBhVeXe5Dq+9WoLMY +CX93+f3Z/PkhLou79EzgGo5I6Q+7GSCoLcM3PqgwiP7bJXrJJu6vvRvQhX6WDON4 +pTW7/SzlNwaBW9ANSpNWU1gcewMA9B+q7FhIX4ZcAH67X5CbjE8s3C6z5dbtRjKm +W6UyMssNqc3EtxO+nNdPHAB2VjV/AafNUV14JTwsdwazAhVZJI3/R09yh8hvSeD6 +2O8mCkPZynCnhaVKef/dcgDC2ybA5lutfe/Rks7y0tqCXGGo2yyyYSWRtYiHRyw5 +bf4pj6QZCoQm8LL51juApyAf4R+/DKGLQ8Vf/c7gFOv4TxO726MkgK7ctAIrTRLR +TYbXSvSl6iuRjPFMGSW4xSzUE/oCMnfyP9tIqxesvZuCIkQnq979KcMfV/dUezVj +M9n6LH+r4gkqHQ+eKdZs/IVxJNwpl7Jm1KJsLCfJJx/5VpA3dLarnJjFTq0fFrjz +2+sE2AwBf9kIkCMKQ8BIXRBQ6qcUnqwWXHJNSioclDwTEES/wVzsJZ/OqMlJZC0X +vio/89cf3nIywv9dv1QwUhV6VWr/DuPHQqShdDPTEoiXVbKhMHRZh9V9bJudqYjc +dUesm7cBg8hYWfJhnJWFw2fac33z3PGefVWtlSwE83XdqjEncckNOWy+JrZeD9je +VevFKbCGmKxoe6pybqA9ALo/YiV8zhT+OK7y8GbvhB7p+F4pT4nz+i+uLdxY5MQL +yWaEamEUT5srUIJLYDVWSstc5Re3E4B9eps456KQ1F1/94ZSI+IzkSlQni+my7yh +tfPYn1abp6Zqos6hJnAxT2SzLWmpW/UK5R2//Fikj6Prllx5p7WfmpUVeGCZ+yiK +9O6wCavH/bHeK3yN4mglLtLmZXG1yK7HX2dUYZh5Hq80j8krVqKHInh8fKAANGXO +cdujBcyDE9KWNo5R5KQb86mqfk2IRkf4VbG82YQ/PD88UMsS/7UwxbMXsgODFRUI +LRsGgRJbin9b05Sr0uYov/VDT9UmJmK/miBAhw0IeyEPcrTzcAqfktVSlgKUYyXk +ZBJkEqu01joWzFKvajIGOlqBvLaWRfBlOMpVsWHtKmugiWyGYq6+8790hPsMNqOU +56N43wh/wDk3gHFFQP0r6Ui3jashTlXfTOR3iRUwG/wrVQLg+PzPAaMK2hYH6o54 +V+H8i/vDn7SiXbN5UIukBhuYAeaDe5d9uyrZP2nIYKzpVlyFF+g8yGKOAcQuO783 +3bhAyNCzaqo1l0CL26ZvQO16iXDP4AWUyAKqIgnf12RfwQJy1AhPZGMtpPSyMzCw +/jr0Iu6xgJUNa05E2z2jnZlLnCnHFCE02840u1XmTR8mA27sXSgQzSiGhmr8l6yi +flXW5ac30LeVj/xE4Mqknx+lh4ctydk9bRt+fNJ5gvYUgl2zLnJomFz0Rkwpw7ZL +BEwAP2+Hnp8jYq42TbatUIKRXu9cGhkYePwFZJcbi/Ybp9TH/z7fkXT8taVpgkSl +m3S9Mn3qoZphBjmo9ht/UPU0cWNjcRcUmhENZl3Vab/zf1ZLltgRGU2+7W1cnVd2 +z5tJA/WNDw/Bg0bIpE5vSmf4YcTVnjWvBibFO1w0Zd7+tgX3PCUnQb6HVGoVPP8D +yZ1bzRGIYGDrPj45oRyvuQW9Z4s6Kw6ZcGDFtS11rucRdhbgWilKnPijcUFJrmfv +8U4mVsBdNuiyzUt2PjyVr1jhjsH56S3dN8h8F6F6/cWYF+5BmiGUaFMeinOx9Jqy +cg07i6Iccdj4X/oO+R0i7ziX3dWOlsqIkE9HXIkGG7bDyoM86yJX6cogsqCn0AX2 +Xz76Jty+69/QBGD7s/OgBgW/C1O7AfYf1Inv4eSJ4IC/cxPKU+rYZwdK+gmXdCTU +fdVn7uoqFQDmDOuKCFUyVnYHjfgPiGsBkC1FnklTs9k= +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +J7KosW2ykKi5EFdAMLz/gyhLImwj2gD50cyEdEtO9kZx69ZgsPaqC2N/Cju0QOVu +OHSsUW3EwVk2dnUxhFc96WyyvuSeNjGSIjL+g0hg7h7U19HwGkjyDWXxI0FszAgU +8MtLn0zyRn7rDX4WKBW6e0eKZyxA+4TEGoEs79gD5JEm5GGH/XXqYNlNZhIY7AnO +PM3n/egkRGqxUxmVys4D/HKwWQJqiijl51581+v420/SeIz8g33QCnsj+FVv8FQY +rG0UviGcyHwANSYYV758eDBgsPuT0uRiqdzQaml7Lr1tI9riDfjD2N92Ga/lsJ2Q +1vT8YIB5wgEhiEjyQJNk8A== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 2848 ) +`pragma protect data_block +ApxS0ov/xgjlDiDohm1kcyal7qO0JfHd7W1FXJZHw0gORD2rAIYiL865p8Htsfc1 +hVQtAzpQhmgZn2DvNj7XrLJkMxtf+zUJIx/g7lTELO6oCW0VuhgpGmWS+PKB/AHL +VYS1dcgI7YlztIjcw2Bpnt95fwMvB+dikPCkLZNtzZi+9CTcLpYNzqjA7unRpwv7 +vNS+iRBUQRHHBlxRRQtXW0T8kbRVEzEEgeV8CZ52nBLY/J9iN+uuvDL+inJEMb+s +nvWRAHQyPzLTrpTW7utm+FWRxBwvbT+PAmXrLf7gaJvFDQRbSq4qs6ADjKtFTDg/ ++AKAZNu2/emGZFaXxXwmALRK7yEYrbofI6HxezIDEgnvuBbuZXXSqH8lsI0h3eGA +PPlLRxnBBpU2UjNWefnRqUOdmkAxlMyLAtxjDDjhXF+yY5lQ5tRqZQiR2DfWxXTD +UeGyEfduJZvwERdkTVlTX8thCbPHmeVNHNAcsQBZJgCIq5hYp+y4O6z8rqKOtzX/ +9+0cRd4h3BPgMJNQbD7xBBf6Eui54SBvh6l/p9Zez760ITfu2jwHWVnCa9nvFqlS +20ki8PY4KHcauwYPHuccDIYsEiMVSv7SE9VM0dz5vzRLPADoGNKOpX12E0QO7PNr +Ve9Ld+QKeL3KeVk5l1Dm67uh2Dli5986Sp+axX3mtzqqUWv2bsyoTgm5/jIzbQTy +I2/LfwalvomI6yBPDWdEyTqislROQTj0YI4DOpITzZXV2tjeU1pAny7HBezc2Ywv +D31lq5KKzxiop3IIwf9eatZLTiD/SBsRzx+L9NdT/MramZwtE7FdDwrTwnCW3CO5 +T7phr6Kckvhj23cPJEHaOBx6Hr+y5w8eI/YvA7tVZAkMq9Ja+4O+J0atNuYc/4EE +/wq9wjB6sJDjsfBleR7u+SrWgX2LwacK+MBLSfQGgBgKbQRroRzAd8qAZgKmojtt +Mxlq7pNhxmJsRsKtNbIoGuc0epuFstBuTzqn2lA/YA+04orsjM2NW08gkjQZBY9s +w353o77r4l00jLIB/lrk4UlZ5w9HwbIyFyEG9y8kC6wr1J1fAjeJq8UfCFWoPhdE +lyTzH4E7JEArLElcUurHDLizruJUx9mD/mxs76xF2jvOg39WAxNBfijtt1boqJsA +dSuVj1yfDbY7SzJbrJ0zVD6aKRqr5Vpt2MeFCfVRsvpDdsb9abmZqpF7K/QZ/gl/ +2mVCrj/LYwePiDVlkpbtbzq5yr/y1FGgBn3i+TOo8Mgc2rK/GCqDIuRQMbi12fzg +Inw9B440YGaXcApJW+az2IPgyPeXaFQU0HSPDYr2svR3coZZ9dxmgrTLC344qvhY +bYVamm/WQhRAWeY+N2COlJPrBgoMr1lL5HLhMcpIfVdGc/5wDzdw2+fN/wEL2VKD +6feFMM/Vr+/Pjo3K450YgnqWFDfe6AcpDZqB64d+4b3BduUxiFcAxwzwowXLAQ2h +CuXHyVcX8ndmk5G7fgaL+Kg6Bc3Upl1SBBFs/NcexH3aWF7DIhEjKdIleBLPDGO7 +RrX9wR8PzLLFwbh2FO8sAvU2lh1syoZmpCqcN1+rK93CmeV3EJSN6Q/8+gaKySQR +GZvEM3dof6jIAGaLYKpe4LsmYnLfPydBpiiiFYTEDJXqho66gwyqZI5wxdV1zWWf +Af51a20NbmBUtnTGeag1Wiq/rwQ9eMfprNTZ2bTAxTVJCU1ZaTi249Xx3IZs8x22 +58Euw6ivKFj+p/gvE/orHoIZKFcFl315ZgKkn5uBVJYdhCrDiLzMKZxHl7PMlTJ9 +s79g2J+SA+KyIGyIT9Bgz7+JNpVlcQky4DGS8nyggJWbQ7yoBG+f0tmmMO7V6vIh +XE7x71gom5tY49p7Bdz0NK1XNOW+/YONEKlh4Bi9/MDqYk5VhGRb+4wHvwLCu56S +HYgtuZvqrFnpzCVxq1zBepFDOcGDuT2dx+klu+FfIBhNGIZR1PtvV27jP6e8Sw8O +PB7iHac7aApHhvibH0PkUTVb+VFoBZBb2jwkkknpxlARMLcjv5vIP1XkemRWMiYu +Hy6OrvjlaiNw+kJzmxh+jr2TxFhDYZX8xzDqjSNPI2MnP9JXWm2VqnAEi5NY8/qP +u3uS3zQ4FqMupGJz/jSzyF+vmHzD9OQZtIDKkrtYbkaXaPd5gGgr50f0OIpWwgaq +QQ3Q31jaNFkRgQgDoqanT5glDd/sHTdPgNKWdKhBb41BKDCO5W7KEOaV/W5EPlHf +K6uHYF6HST+fwotOJXVd5d/jmVnXXU//wHxpQa1sH0Si55jeEu4flRICfAxlbBMx +nu8CngFhOihbvXooeYmNrLk/Qb4l088PCbNXnjCyfw6p7Y7gkRejRxanXNBY/0mp ++Uz+fnw8lUiSDcioh9E0ISH1MFCAJQuKI0wCe4l8oUzIqDQ6hUKKgvjvF3HKlu4p +LhSDQeUts6ZNX3CXkIM4igj++o3L0J5Mn/0Y6gksZAUjfzs/SPZtzfvm6/Lm0eVY +JkpBjjDtTtof2yaciBNWPToV3AqMIQv/nODrkJDUuAPpazs9jmiWAXAucoK9FkjT +sWXKDpUDTHdkAGDKL/jiDyRTmdRe+SVX+nsAgJk6ziifNVGkMdoEtjI64Cpp6cEl +tfcfI1XPcSqIE+LRttHIl4PEVJlFGz4jpQcA07FMJc2nyRCzHWpFVA/Oag/zbI7c +WQ9GWIlI2/YzW3VbFyjuJCj2M5MatZBlkqZ863vH6XCWvqAtRO1zAs9bs34WwXPR +xwVPw6TBwsWOWoWvdWfCGbk/HysKEx3gx9b/nKcyE0xxV7QuOg8Tz3+EbKPz0mfb +N8ZJNOfNYhwO6F5C4aBL53HEwzoPzkMGL6d9uKsnHmaKFfymafClWB3fPwoIITol ++DXFS2X2oPPB49LLncsAxvkxoXWB4xwtezM9r2H4vOBtzDTHCL9UQJ/N6H4ZOoYX +SEyNCXNyaHBq41P+EEWTi4lAjUSxv8N2lE/7HBFnbKKMiaivlFZ57AkwHjhR+v2j +nyanQp2AF7c0Cb+XH8Ku9BsUZSKLtoDcGv09ZsIXYcZ4I6HutNLtRM1/NNvhrumx +LZY5GA20F+E3ATrbx7lWEwei1M6jdBuJMiUl7cW99ceL8JckKYUwLq0JTaDKyG2C +4vhDfTtuk8eI2NuKtCV7pCx68nUMMGbc699cGnnrLDTRZl66l0RyPkfxQWKWCtPd +QeZX7zGSm+w6ihwmvRyjB3kz+nymnKe1aTGGABCV7oNdX/5x2iJkoRgq0PTChqNj +Q40HXwizoKUTO0f7P+2SXTLJc6lKQmzHCvvJu6Wt7AR8X2wPlAxCqqHKC+73zY3o +skilQ4PglGzfWixxzE7XbuPhl0vhEukGAMIoGH5iyh7L1WvtCObK2sKCZdE9+MSp +GfCqpX72BfSF4xFFn0IT+AIOsi9AGSrMreXPko9Lue1WiYcELcEsxpHuYZX9I6IF +iA0aqOaO6yZ15oCXDF39cotuYBNeudW9/Jvl6njbAvOEMRbRz134g3fg7ceMZbDD +7NzCaIaSljBFLMS0SVieFxaCM4upKoqI+OMmePMHgZdtNWJqmDO9duysrzre8SPh +r25XGHo7ujT3L/WVz/xeEwbLYOxBrqltcNKtIVal6R4OeIVlUSopJZyvcELBOHhG +kFH2sMU3oZrPGTGF7xN0Kg9L1fD5pn6TlU56B0PJnWEK9FbKA9hDKX/YF/ErHzMw +M5zE+dXaUaAZlIWPUSsnsf9x0ybL4BBU5XMjQrr8rYjQoZGnZxZncHI3JM0kgqxz +o2AWhMH0WmP0QLXwjMSvXA== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +Qd0gHlsfc/XIgslwDiE9K9yr3xlKZY7dRCEA4nolcKqvt+nIsq3FL92/SaoeJGIo +CKSXu7GbU3S4jqPDe0b6FxNbar2owJoFHYDQnYxbcO647ljaPpBiv6x03zTZQgpB +M5+cIbxDDXPyUwmRJLwZAuQE/U8ywGMFDSApNib2YZPLO6URh/xvjhMIO4/ityTH +GRv9t3xhHHvyPfGB2Oa10v7Y98IptlsmWMPEg/cI/gRKKUNcEiTJqTmMFYUELkF+ +5iWuLPjdOzB9CLSbubxWA7at8ubRp5/EFs8cAmvD+yzglC9Txz5rkR+x3ryQkXzr +7HxEV+XcVvxiezPBQv4Sog== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 2528 ) +`pragma protect data_block +XiV3gfci+H3rlSdIMWTxzJU8cLPDqoapCBHln6HDS8BmHn/Fwma0HpaXbMxwsDc7 +m8P265VvSuSMBdnIc1kZNyhKrr0lmSQgF1Z6+4PdX7502xF1ztSIj0FALgQfGnC7 +6emIbDmkjYr0FDhelXSc3r5hh7YsHqGr0AQgUEOT1QykJleSgdfrdZnz9PrL3FXQ +5jBZheIV5/d+P+j1A9CifQ1oFaU02dQ6sOEnFwiPSqGG3c0KPn3RptdK+dP9SYR7 +e3PkVS08nBuXUyC1wO4/qmL1XAsR16kE5nyxbp0ssSmf+WKvDnsyhS2Lm/S5DE3D +hFBouoZKBO41OqKEaOPqE0hHmY8rZ+UDiZ6FpSfPSypgzwRBKCVLHHecjUSnZClU +pb6PdrJqrlZqvAMw6snEDn84vJCY1DtbZ5tkLVbzobw4d/7MXoxjfkMwBdwVWymg +Wgpu2XZ2g48IvQnd22tr3bS4G9OG2ex3fPbaOMKY/LwaaXb6F91XLsjziVWmPR6v +ODOmlrKyknnsMJNwEl8yboPzyk1liTeCxnDRS0iCxPC7St5kY0A6neB9EGyXnFKw +wj19sKpeGx44YvT1UklpZlO/6f6VgPnfCfqosldhCfofKVHA+N3nHWOyr5efrYDP +UiGGLimJOJMUlMjgwh/Q6AHGU7/lGLv+TODXQH3kGwwtdtGQMvAQmCL3hMmnUW5w +xuQYu3a4bpXhPPeg7JgWUWTJCuzUcyBvuRLofPtQqhDJEh9fJuIQKUBq4O4Z9Xua +ItGcNR5Gho1oFm90LS/1+zuQB0XMBqrK+9P5zi97CJULS9Zirgs5EGB5S8tK19zo +OHNycDnFRJ9KpXgwPY+aV4lLZ2cKqd1EVMcf/BbyrMvb7Vj8NZmeJvDJAZFZUsiu +9Vu3jVLUdcoO+0KZCAaUoxunJOFgo+d0n6hGTjMrOCzUsDfFF1VBiEGDBeOOngt3 +Kaz5MN8saN6kFL1WlLGpe8BjMckUuVqjHDYiHuC6O3vNc5YwsFkllDKcAG9RPJT8 +HWFOcQarm6eAv8F50dCks+NAcbfTHoOTXYCjlPMAUzoRPUlc1H4YiyMzali+dzsu +i7u2dK8kpsYzQ40WqkLcA3OV7MD2Ip9sk9vyBzxxi8QZIBuDPBcSIOEHLPz3MFzu +38MeoxDozztBTzGKQzP09wtnb2+s56lfOywWoaHZiHvqoAlCRvF5zdQlI+qNo5ZG +W3gzFcY1UxuaOB7Lg4p+MRD0lWTA4J4vGiIzgY9S6hd4siLlXycmbKkxUrXTaeC8 +PdmFfxe5Oy2iHgW//s0IZ+D/Q0Zgt1E4Y8rmtnpfzKga2nu/J/gSUlqYFgPju/PV +Hy+U0l239VYXVjxpC/7EUwO4ayGLktCPuOqYK8pS/jh5KP/oZxIJa4TKmoJNN8h+ +KOeIHI0mEc2BPYEgl0j/E3E1XnG5lxkzgYzwVQlrIzPJsbOYrCUfG4ZzcV4svFGn +7/4kIHufTWI1pSnfmTs/dYzHnECbqNL3JVFG3JsWjuuhygksP54i2hwEl9zBm6CM +p+7bm8mJlvKRuOJnPscDPDCb7nW6MhejY3vtzgE5aNpw7yjMj/KkJ3zUxqa8/XNU +3oT1vgEil5feall45YeNCKHVgvBSNAPR2a2nQmtXC5H1rXLrobUgagCBKAykwVjb +eE7QV6dF4pwIyo+ZPV8uWotR/OuKJWpiWU2cTqN2rlekqPkWpdWa3ZeDgLW8j6xe +hJ/j3fLpSd5avKz9n+NIBMewwfGlFH7BB5KzBoDQZJCxFwFrStcmy7/2lc61881s +kGLl2mJCpOV9o7oKEyy4Q2D74cQg7CV6aEIcRIyDtf/DHiNc2uauEqyCcEK43CC4 +i7kQUvgFpirRDW8lvjicOQtBaw8txUa6vIA7LsnS7/ylS/y7qmExQ/qGGKVuL6jZ +M4NLWr1cgfE9Nb2gCK0RkZHDRG6iHjzvV66HwQM0p0hf+cxXXERTG+v4aSEqfx8V +4mbRZoeJj8O3wyRhSyl22CUnwTMv8CK2AAbqF5p5w1POPlWtWbrljIV3B3BRnAYa +u1Yv9L7RMc4zGNyeMkgIYF2IarqIkuh32m2TxJ2ifPAkbgu1mRx9OOCTENSdQCCX +6OF2Se1lCm4ylS4ov9MxitQDLJdSmyGDcoaxFdAilZBvbtz9LJE+kwr2qZdszndI +JaiQ26Ft4E6pCpe238BB4woF+rD0Ds18ySy88oxlKnOmKj0kY7UTwSyqB3EEbcNi +r17JbUFPO+0ktu8z5BhdtYeaOPuN9bx0U+H5SDeDUZzjlMrBn8BmZvfAhIg5ov75 +LuiHG2sdy/fuhFsz0dTZ+3fYncTPK/jepV+ZtbRaNNoCPJQx87MUquWxQTh4I9ee +cmxMGg9viRysyfyTTzkucX04i/vAfY1QnJKAfrF4nHoCp+hUUslqL3MpleLKwHBO +WYFiyIXH5TYqlsD4GihlrWY7NJ3iYT1KAjerkmAxMzf+RfANhejoiEpmXh3ERZoD +Ma5gUzFeDlJA6mQxIWXjktbQpcArWhLoXsovpZXJrW4QNPoSem0FCYlpnYL+ue9e +ZOANFYeDntpubIwE0u1QNsUjXOtYErl4fPP/vi5Z8aKoftwHdXA/xJqB7EJxhHai +28JI8dfYPKKPnRQtTIhxGFy/EbtjmFq4Iym7SOuDjGGFwfn/T6XkBbx+vMPvfnO4 +0wZHtufixei9ROJLrwFY0ZBoMcs3BW5dl4y23gB1kkI/4yrSU29D/Ml5RVl53eOC +D7a/X+oC6fhBsA488tIotPnZb5OVjuTVottdPygmW+rU3JZPQ4AHxymiLSP+9c+Q +FoeuCM1em+TGHFQFls2oUUjUGH5mUt+KTJdgU71nOLMl2GWGsUYErMWOwAqY1VBT +iIKBinugO7LV9e6AGqyB4ZDage6nytueroSwfpeae6/CcIANB10p67UistI7fofA +BAsNhDzoJBMsoiHuB1SnTMR15id3BDMv2IknKs22typ00DodzNEpwOcVgkceZTZV +M2lYksxFuOgjraBhFHPGHUtqnnlD/v6KXlJAU0m9Rp1GMaH4AY84mvsgBqCW4RRC +aIhbp/+oVBcW2CT0301R8orpUOpoHhYaurgjf9hcgL2tc/flNxUX5rkHwbjse04J +rENenqhYdRa4UdyvL7g2UXVWJV1VrOiNb/0zSw9E3NM1TQZ9M9z5o9LAXjDI20PI +quHHlk7sPJX9txbZyKKsY0SObguCB2uUt/civinqGKQxSys1+w7xakkxV3T6WXH8 +auGT6bqHySMGFcdBrb/g2Bi7bdcW1ACoSBIkpBT7OE0UDiZK5w8nR0B/iQFgV6BM +fLIndYjxwQRbuIRY2ea3aiNt0EdG4wO4b3Nrqx6rdek= +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +DOiPrSoOsOWFMnUIePF5KkkuP9M9CD3sIOJUMse5YjGpsWljrKw3wVgiaNNbbKIA +tZZ89fOVGIkVEtqDKovfN9hhA0AvJ8mf4/+brMg7PR5hv4fEfoTvaSiSOjxminpj +hDAU9j9J0EeKG8IbY8UBCawYm3GdcS+QXpoDDPl8pGbWFzEtgpqHwLPNdotkODuL +Cy/jYYjISPMG6+XBTCDGPlB5wHTuXk4r+btUx0HJQC86NboLhzI5xocnTZkES5xw +eOtqkXEjljvu/nu/NhhumVFQWtjfe6VAKlLnz9mcqkTlGcJBfXBEcJuVurHCods7 +hizyF/UB7hJKgVj5ZWx4uQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 13568 ) +`pragma protect data_block +Vj8vE3xLVzvw27QQ44bZ2zywreLuPxzb3fPXfP14qyoFQM3H+xA9qigVzMNWUD4N +ORBewg3/lJILIjWK5K0RcF/it1gdkXzzp2leuIQM0hT0eLiBdJwsRhuIbqpf0hHO +Hl7rgQWznqwcU4x2VEuzNj4SmOvP1qrymLItkEL4BuhLora2iGN5wCqJicpy5R/P +JMevjx1kDWakIzoChrsznItkUg1bEJUih0/3Py1PLWvVI+WaJ8Njc4HWGDpDeJ80 +SSYIHHEBFckS1DQSOXqHr9FdhqAk/qNxojOrb3+mBRcibwmpgivfH9ftYpStzC5G +xo2a+ftIH2AWV4/SabJIYwNrRlN9l4ThLouwSwT6u5cimsAegrLrOC9XFSqTcqnQ +x5eqmpE2pItMPml1YbxIqjyLCND/ATjJ6eGJuuLU6pOz6lWhbayLPn+jGrJdk0se +J3Q8iJLOAa2GpxHyfdsIyItbpg/ZR7DjGDocjQfU0vnqRSvPGCpjkToiW80LHokw +raxMIEHkwQK1OHsICbp7KqWi7DD49dYTehT4K7JZeCtViSTe3USPrpwLJo1Ab0m7 +iKIzW0j5fM70z62o893Rr8JFQB10jlGPe8OxwPCdU413oMz0m0MUG+DgXfHideUa +6f3Y47Dg9w+hc52jaMGIAo+Xe6GMbyTxZ1WxpuBGMHorD2aXFJUep6DXS3DD2wTk +/0NQV8mLPGtCzuo6JGIihEmj5duwZVi7zuP+EtEm1t2VLm0ULg4U44JC904TjwCi +kRLNsd3gERmejv54N0AklYGq/fQbm6ulMZTmbMVIwXQVbwY/wbbHzddNTBncvFJW +6c6EVY83ul30bHj+lUOsqe011Php02GE3dpi39ZS+78IiFKH5Eb8f4IFJ4p1gr0x +F5xoqZn7qpHg3/hYsAlErv+kR6WIQh4CEKrHhbPkby+eyytZcG7rWLkfcElddCkm +FbWxAqfg/7qjL2J9IkznKnXXOTn/kRFEFKvoAlxEgv9/oWMP8nAI9+tyOIyJEga2 +FEjIJF5BUk7/6Nt7vOaP1eO7cT411punsp4ikUV2V+KyIJcGsW1dbuKbn56qqyvH +EsvLtOxkGKoIptwTyyg8SgLHoUwR2xxRebgCDpWZqkpvLnkvZZP94NLZVLOOsODM +WEeym1J7aTWYlXllJ/m1kUp+vu2yKB9gbHPvztJgjpKAMqXuzcStpiKdWfpS57VO +eBmUklDDhDkiTwT8uDxeJr+ZCBnzdCitqHWpk+V3eU8lwetbyvmQd7o7QcF2tOyp +tg3rnIO6HT1+BMWWUZCrrZa2OGNqIUboW5bfyt3PIatq0zXoemDPsJgyt0KNlm7N +l323wCUit/DO7dvHf0MGwFB9eLpFyiESZng4uZWDRXVhttCC/JJuua1FC1PF/kQv +L/uT3YmB1RqQ3oGju4aJbEoUBNKK6bH9Uymr3d0L32aG12iag/yvDHodmJQuctU8 +BYMmW6rszqpzH9RJLYGzYZPpWn38F2LkHGAHEKvdqvFPW18SvuqBkcMaBoCkDSNG +lzCXOVVRDFgnLu3wTds5l4NfnpZYIIhctTvbI6EbhGzK6TBJYUW3Ps41MsQ9IXSR +R9rY+atzWV227rlA0elsVDOI+fLECkW6eegEWMDNqYHJmTMnELgEC6wCx3tKzvfo +YtC+iq5cbSfpXQlBBfCC49x0kRRX0Y3Z1KYa09v8a308f+ZNYpbnrnmpdHvAKKXr +IoiBNgzsRMk9NWbGF02UiD0cABomDRCLmXY+0I8d1i/oAa/7mV/ypnaga6WSevOb +HyhoP3Ow618+KEJr8iMHFi8445w377jsKgMbnaw03iSGMc5UPqnfVhAlQ2V/GEqU +GH2k7KkkczOHl7P39lAGP7oT9/o6Y2U0v6fz+SDhx6cYcCRBYgtjL2C7LC7ZEGO7 +Y7rPwvmsE4fswMVo+SHJjiedzPUW0RNsXzRYxAOIBXyQZHG0BOoaibQVdw7hSa/Q ++kIkEI0t5roGDi9SURd1c9o9rSbMjQuv+S1JhfnZiLG4HbrHArem9X6sfhTPmCHh +lD9CFM98GDWloeK6p2rpobGD5J5uwRDEpMKKRcWmLH0RNg1kwY+Dtru5rjUcURuI +W8TkCMgnk7br9+wQG9pSvge/FoGs99zDtb86OgZVEBrz0q7pY0wnQG0x1Qai7D/y +MJRg2lsn1lJnLUiU68Nqm6PXRbKYxVUuEqiW3CeHW/ZzWl6sowZS2ovm6U6L3dWb +bTtpHo9LOWriodHi4Kx+ymcr0Gcww21xwAbPCzRmunhC/qWbwDfcFEAUe+8GpkdT +H7wOA4HUuHytgoPDiY4p072aNuUuJGd+rbbTCVw6MMy4lg3yx5KW7KAHAEigBD/l +NG0fgEI14rxnLRdG89o04b7irZ6gJHV3Y/Df/CILd8xM4JpHCsA0caIjapDvDStG +E8C2APF3fxW5vb58BqgRloHNOebMgxCDVNvT5/eckj0AurBwEsz9qvXGwTrYjaur +1QgRfeqD26CG2GBLWUfmshCevm3WwLP7AFz2zevUmPp3dOMJyTzRnPAw5rUsqK0B ++wqxTtAVBGpzzUpo4XX6ZecR39GSV5xmpZwpZyscvtX9fAvHCX4gP/tDgNqbrF/t +Y1zNR5VY1F60OYLzNmjC8sKIX9A++gwKlCLWch106gIUdnUFCYPJBNLRt9k1u3ms +o7JO5X5geg6rSQfTUb/LTerqZ5IFWRNal8e0bw/BjeuRV6OjWIcVNmPTRu7kKU/3 +S7pJAonfBAr3WD7+oUtQpOubgZOiyLiEmGchAWgym30TkEiIaHytrdEp43TNzNK7 +c5sExHzhdc/CQznIyH07MGKO54Pk4SN3StEbPqUTKttLL5+9AI3ztA6v8c6H2S8j +EKPWgdbMzWylkI4mcCYv96zMyAk649IdaTRdR1WJu3UuAy0Nj8EYInvJ70kmWNnh +DazBFlSQlzc6ZfcNiYNtDItAh/dU0BwojEHG4V+K3mvgiBMyfR8YbMayxD/zdtb8 +95OG+98xV1YJBvMq5+v0O3Sa3L7G5DHD4rHVJUHiyy8LmhSEvEjsuU94ATX7s8Ih +7TCqglgT1TktpzhkBZNAAFXe8+hCVEsZTHP0TchXacAhb81V7cCGju2OnaHuioRP +qxf1wy0nm8AzscOPw0IZ9pqDO01Y5RZXX9v59oUsKPWT3+DxDR0cmcyYeuPHWoaJ +hxtd9KYHJPknCXW0X89JohcsQyey9cW4Wz3l70+uty2dC/BkOzHjMIuwlHFPIM3V +fz/Xf3eANU120acvI1PGolOCREyY/7CKu+nN3SNL5RwgG+xVV4+NcNT2b3LaCNd5 +UmE8ST9+49eQIPxjvARZq0cqT61di/kNxTFkM29Whn/IyVY9twb+vcEA8OtZyFKu +v+4qxW5TJ24t9pOsDidpkvivIViJpIGJPKR2M99si5Eu61Xh3Hjq2nwnGN9EJPUO +LMylEgSjxuhYqU822jnBKiWGBV4lTs5Ar7TwYtv6pL5G2rLeBvFpRKNcdMgFa8CQ +zH9YpBUCv3GpPT3q9D2fOZJfM0szdxvxI/b9TPrDdkky5HNjK5/ahdHPdhbroxRs +HksYmCz9rOVW6O/CFJwuvA0KWMSgc0hBXrm02owI3Wh3zaKA6BpY/BQ4qZ5OIXNF +R5/nYsG6wc4SViqmgsgnEZIOmHIxm+zzh33kHCNL1q0FBHDhgP+DUMKy+p4wdZVs +PjZc71t+3WeuCFiN7hpwPZsXOsqZWnbhdbLk9Bl9wkbdR61pW6b6AiR/NzikBbuL +XsB1i+5Itpq7Sb9oVrN0HrfrLAaTTF1QC5YxU5kiw8Mm/JkdEhEha8fbNaG+AF4u +4WhJSA7NnBJVWJs7kGNPaAdv+GwTcI7DXCBHlc3aoMWSpu0GvOGuaWiODAM6r3uk +1rGSQiHcrJux/4fqXmcGhZq6nNlp+2a+kpdVAGmjLzmDtOOGny3LTRMVIoL5J4Os +P6ioe5/3zlQJ+kwdg3sPveWdA/7kO4/PEVOTCzW6FKhxDWK0W30Y2feUaGmIemWn +yWbuT7ocOEN8nQ+nXrN5nsnPyqH827D97QPWTY933q4tluG10u72ZkpQHgMtNFJt +r9JSZzksrXiKTfwbZQUVoY+EVm70BTBWGJS9rdxZKmzPY5njwk1hSc4FkNDc1ono +gM+XCNYKvMoUU8r5UWvE+ug/2k9OJA0Tc3tN4LkLwRasDozN+00YBZPH6MXEAt6P +cIycbLa2XjPA9SdJmlZdy91QapzNuthzsQA8cT69XbTmVQkCARy/DiPY0EE92Azu +qnjwASKA51Kllko9cWds6xshiK+stJReoPXvIT2BbD69hOnEkVEO2j7LzUJCwrp9 +TiDMMXCi51KDyIWQKyI5EfCSTTM8dzd8sQGmnV3xmErDmmOxvO2tSEe5TbGzQFNC +nHtEGZ+ciYqCKmEiWD2uzqSw2C9ITuUZfMMrYPB+/NUACvZ7dKKqV4oNBEG31Br3 +1AEKM0XKJRa2jeCgzv6y9rmE8W5rAjsPxA7kNfMGWlw0Qf+iL81wFBs5Pjtx3u0k +/5zvtPNMOnbg81PaCnTchs+TbhnHOF3QbBAHXLDPq8S4yjT6LuaLC6Ty4uvTYkfw +HQSxtlSlcJAZXRerOtdKl7z0zxid+ZRIAOdwjveWmKoEE8KW2JPsoE2QMeYFhrbQ ++3ErTC8NpSyhSkBDROs06wcFkAKdq/XzUaFKq1kY8IVH+CVGejnK1cBSk6gbhl6X +bATk225B+kBXiIw3gtIYM1tmOFyRTGPAz/qTiFk9XPtRWBEf8102LcN2UXm+iUD5 +Zh88BCZEFprJVjyuxsAPacRACcG11itoLJ/dG1AZdPyv/A5j7D4L9CHOoJImVx9W +DVtBTgRetHo0ShWT28Gxi24GLqLilCZ2oAWUb6uoZ6kL9gRn+G11JZrlz8KoaNsn +A/X2NTb24a0xdp9Ver0mL4nEIQEZXHfiCiuJmW9ELTvSKQZN7OJIerU5irrq48Jp +kcOjmm+5MxbGtAJRxped3m+YMxBPgBUyNxGiznpUUX2QvySJQ1356287zXxsw3dy +dVxGsnMJhP6pLasmjuc0ibC6nAmjs0d1c/CBQqvuGd5o0k2ZU3mXNWxg3TcLqb9k +q0bf7hgTGKkhh58LDxLvfDpx74YNCGMAGHDamUGWqZggqaf7AQEek5WOaTOUIUb5 +GZ5PqML8agTAPzoEqgVpWbN4f2jx1eauKYQ0gMlovtvPjgz/itz2ZaCZ7/aDp5Hs +1JtOBI3yH67Xra9NVWcHEJJcQM9PXJ+xWbMV5Yp90fRDzn44FwwzIG48RbZs7VIN +scZpaT7PrpUg7Kk26Z2bFSKBoK+Beg4ihE0WCplNOoaqrD+JBXruqZUPldLx6ajc +BxxBZ7P9E1hgSr0Ljf7HfROKeNkNRfZlRNG3Yz0kRt/YKcMFnmCjw1n7KIZZqsw4 +3w1QwWw/mkv5StvHHysABU99gvIg5y2zGBN/nUhH0saFXfsRSxurJVYMArN9Kgas +yTRHyOf5cLBwTsgKJ4Tnl2n+YX5DA7zKSYZ5B9Antlm+T32Z64c/mWp0igMJWUyx +lxCXJL/xRTsHrIZx+PRNZl1QAcj4Xg1NSGEdhXl6e86+JC33YgzBGiSAOJT/aqMa +igYGyFDBEXyDoykIwpGmFSwlKBMrCtMu4vDq1179wHNDJ3bCH5N3ehSzjGKWEHAW +n+9/P4e2AX6p0TJ/YNbDhKoI/u97PVsfEldYV68fsWh5lxddEbMY+sLGtKo8/B8H +Thia9auNbxqhSIZQxLCiIPxfnSKhpRIyS6Tkp4QTdN2rU+MKOk9zlxmV1osIsbqL +9+paBe9xmAbUHMc2zBTXxJWcNUMHEYedg2fnUR4RfJ9ogu8K1bdqGrqR7NSXOnx9 +6mWfeQw+qoW8NPyR8nGy/3lklH7FOa6vjfZoXsC4DEZVmt/CDA/ixoogutocTN8Y +spuXMOnrJs0VIg4FuSB72m3qMy1CVpeRknYhvo1rzPxJnhKr89TUZEWWSa4MKCHC +p3+//fhyKSsqXua0OGEJ1FeTzJgfCkB2C/OqVfX5wzvPN53VhgI80vzI9iD6yhTa +B66x6aX2wU6P9mNPwc7eIzcQlQQgbiQg9E+erKEXLmtV3N75C5RHdwlaOpuNVyWP +RIGcw6rg+utvnn15cloKHL4jRFwz9SoBG6B5OlZgjssAMEy63IIiXxgLOrYwgQ/h +eyjEVUGtnQ6iAbfqeEYu2Mz7BDVW9SMZla50l/BKizvmu9n5LC13g6S8NL6fvrXd +ym46z+SRuJM75JYDjAZh2deVdx/m848zrIBIvasvmdmVyoPwwP7zS3ygWmffgNgT +kDS7XSNT3lJAQXIIh+g5mtI65gitpsJzfDIDzQL0n1BuyXDxvPU2Qz8swqAuRrNk +J4mHHtwNk7mL9sEmn7D9aGX3SSov8z8E5IgydfzXsLHQVfEj4mKP+Op1xgT6c6OK +eLGIhX7/8j/QJQnh+9slET6wyhv/AM+bEBQpxIHNlUchxKmcEYnkN5IySELs/OZ0 +68D7JgiYxOiO3h/KK9PwSaE5uU3NL5JHLY+0b3GQPmG3nXYQA06YqL+A2OSTrjwZ +1dntyXFbTa/vwwongrUGj/UCxLh4SXEZ+JMh6nc+qo/x+U48R8Qe87lKWAaPJ9zX +mxZk0i/ahQ7zJtZs+I0OnfkzMTsotLjM4xsc1Bx7Ivd3oRTlTVOcJsVqwKPVvNAO +AtK76SATXxbQdyjD7XGMY3dDFnNbhmgmy78jAhUoSagdOJH5HV610Hm3MqBxgr0l +Q/BejmYa9YZ4VsOtTn2PjbxmhJ/WYiuBMB/t0dUoNsQiz9axdLvgElY6uRkxiMl2 +1+JUznbxUlhQM9BkOQqeWVPHPRXVyUX0buqORYuLeGew5evFBilwlpcviWnXvmCu +4qxigFAS7vfTxm/oWEvQs+Ceb9ULUGqFmrKD9wN/bNgRYO7rUOkxtVhmz6xUKInc +wTqBE/V/BqRtIWW5y4d2XZAlcM/ETIjTk7JOEZLW2kHTwY1cpmpbKBc8JKcEJ0kt +zTVR3RIFNvTkancldzu/207kyeLf/nS9qzBa53ZO2c7x1qyzSKdLgptruZjEVfBf +LSXfLP9Qtp4oB6ikBNNrEBOsXqbHFjJaTDaRZ9QkSKc/JRA2mrNUouLoiiJuJNNn +gD3APY2vWSzfMoarq0l6TxDLe5RcmUbxBugjP/Zr0nF5UbSL3+xwik81mAb80Oj0 +udVfiL7IJrDw3qDu7xtLRKBaDmZa+phyhEWrCQTxH41jsop+zrxC1qZ7eHkp/EWe +vy0M8u//ybs/85u4Hebg41ltft2oXEbYmjbqKvmOtTpF3GqX3Ko+r/XcWmBcYaIK ++b3QLiNyYHTj36CaAE2wLF1e1VXvCfq0+zHcJGjxxcblJyWjt9JRErQO/0YyAZDX +1tFpYwUhQgcayj65L58N01fqdDFAsdT0Aj2bdLoumberbUvb6lZs9hs76yXrV7lh +OpbsUFgkfxzJm5CWWuwDuFpt8G7TeT2ur2mkx008DrvBKtZOBn5Qv5OxcGvaMwrb +0AzREyLNSZ+P7CEPHWE7GeVOgNNseKHUdfjzPdOTScbWZVYyWL0phro1jqzXTWzv +oeg3Sk1qJklrHlj0+EzbuThmIOM8rjaE+l+B21qYOrEJRetLhZLo5Q7KXb87JR0h +1jxOSAie1SlwN/tTnu0+7VPi/r1IM8Hl71wNMomz7TBUHczjarL34UO8A220b4Sl +xbBBk+Fisijf8SCuT+v7Qiu4doebOeWmZHYOMQuervfPOr5fopMpcMBevwbMdQRl +ek0MmxuAbLdKju/drME0oFcL6OR/ISkTyxpZ6kXVQgTobvIdxtG/RjAJeB/QEcK1 +cvV6xWLLLeSsfdJK8SQS+gg7uZmie76bc7tNhkokgbU3Q6XYvgSUGtuRbqECOjh8 +dabfe4BOtM0rYSw6CJRYGK9yHZ2EX5R9FhZNIToaUgyoaRoHXh0rHkqv5P8G4iUw +gBONBXKGj7/oJE8EMwth29qOVu9ODkC9SbJgCCQQJWnd0YCt2iaCTqt2dwTwnDFV +kM8M0EGo/QhziBZ5sATwaR9U8bwq9RSjjhVcyi56aFsF/qdhdzQ2kp3T4EzJIu4r +TQkpG4EFjKfK39lNdDsmRakRADFYkgUcUhjrCrV1s2Yuh3cP0O7pmqiEFHDPKmxq +wYh5R7/VnieC3eJ5VsYFQYZi0x1RQ3doIZaenGwiUsqqOk4U3LWPhu9N3HtugLP0 +tTLkH9x5Ns/GXYVdPWI+kCBQV4YPlmA4Q3wJA502a30QezwUJ/ZI5Oxelvn9meqn +2DssTuyNlimMuaGHbGkE5ithLhbRJ/m0F/IQdMMTaxyxvhzNVGol27Hy5VCZEF0N +rV62DnCM0jzG5pPxitdYTlrnYoTndq5SNJjwxSC5hqHZQ6cSkxkFFc1OMYb5NI0O +V7bSvcOnshaSWl2hNjs9UCRVukkWng/W8pe0ODMl5o6QyqRrzWGip1R7zJFRA25E +ODbPnz33ougw+uYkFmghp5BI3sNqXbI9xws1rSIyl61KDm/CGh0SnGsE4pU0VRxz +kHcjAo5JGT0wPiJ8uAUErMSIZnYtgi7PFW/sb442imZowS4sMPbtvsX6UgJhI/dv +3Rq9CcJ7GDRYaLfXp9EDjpAY7HoAqtmRtRyMkDtI8Qu46xGpUGgLgHa83L1CRQYc +rhzG69cvu7m/ASoM7vQpAf9HQN2mGnVxagk9o2ou9mfktshrFaP5SNuVpVXL6qK5 +2ca/x+fZmtWFjtpLTOeffpmEJehIliQwRULCg/oOnfzMXmHBnTHUvtxzwjLoSnZl +B6jO7zh7ZCsN5qw0n3NFe03Dwro6OxgYV57qbJMTsUZwjrlKe+v0Tl56I79kVu5O +w1aZDn0ZGLEB5bulXc4atwuuBobx4pGR8WohfmDk5X9+ZViJ8dFJHX2TomhNHg/R +PzfUzb/17kvzBjwtn4aU1p/tLfLqRqtEXVB1LKy/NdaPdlNon0ngKqbJ9KQLlk0T +4XaiUQx9f2ez+y18H5mQQpGhucTTDLt99WDq4HwcekU9ck0KrVdlGrcMICLhv54Z +EtKptnVUG1UR77L1uXATgn18kAA5cSve3gJf2u7r2ghX6oJhP9P1LWDaGFiw7tDS +Vfs4qDADUfmnNJ7vBfWnTqnK1EPnjOWbYyQlfc3fNIxRVZiRAUbV6G5iMcgnA4+f +BXVww1A+lxRJfySj3YsDMYgAtCSFRYOkhpAHeHpyZONTi2FOHR2O3zWS/Ef9chLz +b6OkhcDZJAviLM4QB775nm1NAX6ziakol/qa6hULqrWC/R8Cq5pEKDrsqMIXEFQE +wU3MppePuxtUEPsxqkGCbcgElkU8k2WOLCIQ1rFfrV+yRdk+FO4xp43Sp2f7f+7q +y3isAsKK15soJgIMxqQpTH7vYNAiiuLLllJKhGHHxoD+JAYXHB/DIPqbNaNt/9pB +Luhq/4oHNJhSlBnbQ76EgKVj+gotGM6xcP9tnNterRKK4Eagcj4IPUOwOAdBI4vk +Is6u/1pceDHWRktXrgI/lyAXTXuOCadXMO34wrNITfC+x1uPML7BYr8UZEPnrL3f +7dASPi+PwH8v8WYF0v5QMKH8dIxbXw1VfYUtn+jDA8IRaW+/DaZ0p3SiQZ0XP/Ak +7tkY5A9ZetTCXBAX3M8laVRHCSs+iTLRz4tw9bZRJMfqyq0pnY3g2RP2kUEjetr+ +VQ0RShC2+KGp2czz4/9JwwnsfHbUsey3TCgXG+59szfGIQdBgRtNm2nrUV+HrWB3 +BGs8Dzvm2D7IYBTFAerJhbK94WdHZGviy/aOa7+4ll7B+/M5BSwQHVUFyOBP3v0P +2drGb/cH5l/VQhS+kh6V9GIZ/EbSVXF+fX8pj6DE8QgZGy/fPX4RW8OV8C1q+Q7y +4SH+Y1XuiDQ6ve/vRQDfBu5u2+DlKnoMoZ9h8Zm6omNZM4ocCk9IaknaROl5nR8H +3YjM9pEdGyygxYWPe3rg/W+kkar6K9PRHOAN+6+CXT+OwWasNb8buUUa2DB7sV5q +OYtgcYJaDXRjWiazziyUXTRuzQtoiAsIgmI4Db1gL1z53D4xXgQZJGZleIIzm+nY +R5MlyYruuV/U4Qz4T3+mhxEQktfRzC6eNMr5usF7ILa4ThRrV1O+/gsDIg0sVnfC +UTPnVztaYDkkeynp3ydevcZYb7qHH2ILF/+mzr91WX6gKgBIMcUeZG6AqAG55rhT +KiILwTXveK4WFJ33oDz79FdQBfeG3VTf3ABtqqjfn9zajsPfr7scRIhJeUaCfpC6 +ikDnyvJOtVxs4ReLoQ4mRPWaHlIwnjPbhMorJxIf39bTw8HpnK/Vt9sonxdIw2ey +97PUT+UXVxqcWlE8I+AFU7FV/MikSElco/NojnehqxVkQktMtWgIzIfP209iqgiH +Fxm9yQm1mql7bDvtYF6PNUUWJZf7czGGVT7xv03BbLdTLFc9uWMR5CDoL7RDHQVs +whBT2MBsICXtAMHC7VQlBTIMtDALHeyVxr3Pp1m2cGp9NboF5ARcsbqO/d9h6iKN +uOYHIFg6HJQSmW/SbGgb/NX7Lxz4iy5yXzxlQ//1szrLKE2Klu+SJxiKMWtYLhce +5gsLhyi0gC08DMRdPB1+RQQRoVO+5wuMlHtrzizztogezPJMznbSSmTNt9Nj9zSf +NcW+mSazTQeZLdzAO0BLpaXJhUE8dEZoSdwAvf1XjJe9+5SO9Uvja/DcGa/zjCT6 +5xuIV6KZJ8CeZp0thpOMlSndON00rHQiQ1ml5/IZlNHEgoZfssTlx4G+MOohghwc +a6zZ6KiC4uqU1Ks6wiCmbiMPp6C1RXjPFsVgtB/YcE0HId2DVEUF+ewN69dQu0rs +U9f7esk8U/Pg5OmqVyz3eacMS1rWptHcwt701O0+/lx6qNdVTaEhIxmIZFaVatzE +hYSICVL1VeX7eOWS/wajgqivHiYjlQ+5Admtu/IAJxvcOYZlpqWNS68FMcBh6Mmd +oRy+sO1tx457pCg2+z/w1lAbrGpqcM8yEGwNRDjJJ4phnfHZeQiemzjrq4cMg31u +SRYj3tucjQUILnDINOjo8AoDk3dMrutrZc4+pu99k8mqFY2wnzafeVn9HUmba5hg +bedujN4n6delqKDRvJfwClgIsPMO1JnXTjg1i2YCnHtUB1yv/WxDhtc1Js5pr3cj +Tpht0326w0j8HKRxq+sr6459hqQwKvi2nvU6RKQYACMf627z7ZMvFFz0K2nt0YfB +54L305u1TeIxAfemqFHqFkeGcG203FrlkdWNI6gWi4B/+dmvQG4UbEOioFZ4gmlv +tH3tbHiNVPP1oSDZUB3lErAd+juIqHFQji1vV1NuXOgdJKWQQINuRRJ7hQOk9dr4 +qrMdif1WpUnjO1eA5ZfqXJz420gwSIlxZ2PYIdJc6yeewNTAjir6hP/bxH9kDTNE +xhl4o47XKo1oDohFklg1Y4BDNsXRMVRYSAbCTgQ2tEAN49fzYWfi6iyP/JrzaA57 +dLBD6A8pXbywYpsWsj4+R/4FESL6JGm+WeLNNDeDPXLy8ZXgivdiqnPP9tKPSyRR +O8AcOMuR3PQ6ttaIuFG1s5cYzejmWp/1fVcriyuZZEh6cukee33xvq+1wH2lbiD/ +fWYGRCunMU73+V5h38K3TV9xDL0XqH0va5hbH8rkq1Sb3nhfDDndYIaPzBUafEM9 +oYGgSWJ8wq6sLIokROAbJvgl5JBUV1CJcAWA2nowSK4tCQOkN12t6JeibNa0quDM +WzX6RifNOR8nndqloJhsa4p7W91zqGTrxyK84OQQYQZkBoiZxrZ6SxwOPexJWZ5k +A/5xYQmWR7/ZTL2Jcxu+TXv4QKyPjjquwDHZCNyG6kDMpwgfx4SsXJwN7wp6TvQN +yJcDbzVMnh5Q+L6X47SMqoELiIAQsZYUgD/KcGhDsufS7k4lC+yU7ma7SIliqAw5 +k9W6tqCQjnbSd4EVhEIu+olIozIyg2/F9mroj/aLAxuHQrU5hOch8Plf98GpGvDK +tzY5T3T0lEZbr//+xQqGiO7C7jUAq1Vc8DRnSwWSJ9FTERKh5c6AsrZW37cUpjlv +5kHCH6yGZ6sIFDXtf85ZCM+GO/5mlwt6/btRw4JJC4wtr4kRqv61hwqh3p50FwAD +ilZhVxEAT4u2LUB9/wponOFqLp3Z/Mxl7H+5wtOuan6O3ywA5MEc5Uv5BbypPlP6 +nFiOzGsH7yeZUeL203NTR6bnFCUIqaFT59QFJPkT9/fMd2393O0r0liYGDucFSxl +Aaf8IM51eqxIwixh4GfRDZc+fcaSAOF3Tmp11rH5qjHMWG0tbJW54QvSFMB3sJ0w +A35Vd9vSAS8gsOM66RaRNeLxX9I0bV8CICpJmbA3itc8lYCI15p08+Q/YqSOgfpi +RNk24ZRXdGJkJUe5V5dRxUf5YWHF0gZOJqhkQkvUbme+yxf1D41D6kdQ1P91yGur +rMrV8bR9kd9ENjWs/0jIaxldB6yC9kD0AMi8Y9oerdfGwo/AaLWFt+8V9aYB/zR1 +5+6uXDC+PFtI+QPnY4rYO7J92Mgdou1DTiMobHc7/NATYo6iBPeziOQmvkIYdLpr +Qi7Avmme7dbaffzUnni9M3OVeB8jUvyLqgj0cxs8HtijX9FThluDI9y/B6KjrWKm +jouAA/XF88XCtbm4uT66uh0FuAFuFteRzZNZVHHQXXY9XLY1/v7jmfuRkqVWiY+H +iZzR1642ER6XsUnLC/1s3eMzl9RPeAZbMl+1Sz9zEgGp52Pje1AZIYz94FLi/Cka +NXsIM7aSsQz6bWSMlS4gSvVIWCu/2Xzj7KuZZNOp/eDNdOtHo++NIxDnrn1rPDHP +8/Mv5tfqBDSH5naMhQJXS9+N6UCjeOBCh1EL42mN49I/7rKmIK3GYkrMpxSXv7PK ++nkKhSy6HiBhFvauTIN+r/7UVt/fgIYOmuXdDEE3O13Swz5qG2BLXhE6pttcvViK +nTVeoWwQmtJ5NfSfY232WLqNFGOBT1qx5bzsWfzQ1xDbh+H1azI8sgmPm8RmtUp+ +As97DhKCxrNofuhxA4usr51R7K0hGYcqVIUAbkP62Kzhu3n4FNSTgZOGSmPeVmWY +gEI6Nmbk3qn5jqgCb4fX2X4XG/mlgTBpP9gg5d2tIleNi+4LLPEdTZ5pH8mUNHT0 +0QJfPPBBzNpJxvuLQWvhDfW5sLKpNdvxcBAe5BeH50J6J79WhrCNtl4KCn9w8aHY +oLQSXcYKDa4PmzPDKSQJvK/D8SNJwAR9a3TAl7amZ3IufEBE41KQfaYhpSewYakt +BvHITbYjc+FsyiuyrVtVmTn6Ee+wwsop6Az3eHBEsQqzdSzcOoJC7a5jYfalWty7 +tg4Onty3EfiQsqeGHnqx1OIvkjJqnHVOfZgQsh2Y9FCD4jlO67MfL3vnMhdULyL+ +BSYqpXGq0FJbkea71RkBovjKFdsazThCi9UVYcwoJhDok+N8FJAjYEEHHezAIM25 +mkvdiDp89BnMQvbZCzRw+3nIw+6LA0C3W7lxUKnrPBK5YS4Rfq5AhmBlW3bXOhGV +MW5h0Bx45TOM4iN4dJr8aPnyT5e9mRO5jpLDfoY9B27WHHwsVRrVg44ihOEfSBdt +M/7uprEiG49sjXeKbzqf1jnn650BjfBVqMG/ZWrsonSv143n4ZAMrhTMcFv/Bqo8 +4VMvoU/xRbWoLgIRWzLGgyXfMiOlUDBQwoN2M1OGW0LRMh2JDubbdzSu4Bzuvb79 +WARkp8xpf2UBReuNag5y+UlknSk6NyxcplYfbC74o2di/2xgP9s17nOiNMDgrte3 +6h7v9FYx8s0C7h539MYW0gwRDsmYI5LtAJKYrfRDEIO2k34DUdaCF3Ng8bBzrv/3 +gktPknr9b3DKmi+4SFs+fxQ4YIey/0EFYDW7KtaoelQi6MYkLu+dNSRMZtwKqcmW +c9eUqZqYRcKceZPyeZGFQm0P4kCrEgpdOKiQ+gu/JM/3YnTApDlhbmQQGMkBscUd +zddK64Wr7ofOfXd0/xIX2ZqBZE9RMfA4fpdTWsoJMHPPwp/PNRQjTjj1vlJYLZrc +Z0Xb2Rdmc9Q7tdXyGUtPGhvOWY7Ye1Iy/en20yrhRfYxqOJwu0YsQZMnYSdNR+S6 +JgA76+e7x5xiDKYKNVAmsiGwTXe//F7IGdF+UKXtCClltKwgBjKB+SlVHo7sbt7m +viheuzagYlixvvR8IfPMlF1pb0AUBevqI+wws8X2MZhIocrVzwrtdUSiV6ebZgUf +tXH4suI4rcqOQdyZzQyXEPe14SVP1Y9ClHMCstCz6FwxdlnRZx51ayoEiQfhrZHY +rnAer+A816e+AlC/igI4z5ORwuDIbEXJqVSD4a850uxr6DO7FztOb2vg07ZUXlW4 +CRybzx714qAYzbAud06O+IEB59yxxSyN3tNC4kwDPeug936rp/+ml7VgMxYpPA4p +c63kIgjhcV7/ji1qpc2U5yCnrtX0drn5fIDFZVDKDMKjiuKrFo03siCFAwcr/o26 +nM+PDQF27KZ2u2PXBejMos1lEwwLWL/sgXuK3z4AHhxxEbc+D2boLTi7bi9AV9KR +Uzu8VwsD2XEM6IvvbgR2GP6eG2PvbHI+ZULxq7ZEKHlPK5Ki771kU7f9LEa2d2xh ++O4XlvBZ7QEDBfO0KkEvG9df5A6iJcm//907Wygc8YqebkKyk00Rv6SFKOJ9yY9A +hc+bsxBpHfflFqOGCArc2etvdB0cPslw0X7ik7DMRzr5Lk4v3pvXwQitoubMlGfo +5UzEy52hpv3WElg0gueC0V1HlEMmqAKQ5fPqB5LC2YW8N9Xg8JLR5J2i62p14ISj +37eYx35XEkgvFAbSye/B0qmgUMXBMCp4ee9ayVkK/TA9ooDhreKeHO0NlGZEs5O+ +npPJc62yd1GCQgDoFxX4tTvzjuwSbHskPqEfuiPFghxO5dMH0hgg8/Aw8nrk49YK +/niMAU0WBhlFaEu+gGomSFKr3hBjATbtmpqN0MYSAk4Hw4AyqusNqZn6WWtpu4or +eKSO4mjWrIs5L8gyl4EM6PvUu7aNrcaCt0oOtJZKMntn1B6cM83lMQHmnEVrUAmR +GD2Td6uSgmUlohrfYGBP6+gMSbhZceAbJQmX0GQ7skUywYqaigpKmLAluTGZLU3R +sRDVM8qKB0OMLxfhk7IwNZ+XZNEd3NSgaP0rhsYFgq4ls+BNVKEM9UZ/SZKEatej +Eg5ro8dx6lA8BnF3ZvlHO338DT0U09vJscQkT1F7KCUv8FJPWgzDXdO0P4+zTldn ++5D2/v/BdVF7PRYHXNmeE+WUrtlRXP4QPJlQFUEkAzWJCo1qIlSSWlZW41tjzjGR +IJw4jUGIo6Vdrdk+NtIDpEgw2ODT6cgQU1D106WEDrWtxAJmDD1ZDW3iJtE32Qax +C5uzhzaV0E/9EThacx0SGQco9sVGPgejJx8BFEJZbtgfPlwE8/QtHFt1D8y81al0 +Bri7oMMn83SrhOm80UFsEz80XjQEY9gCCKHQZEDr549toXRICzYrBWjxs9twlwRq +kOA9fhV5pe4x4juvsS6Y48VPi5mVxSiCPqPaAkK8TYswpFTovgMfQZNEZ/8A32Dr +nZ+dQNKy6/aw4TbCFCL9zKlZhpigSul8aKz2+QUW43AGv1IxZVb5XtFfRE6KezV7 +vh4fYMATaR9/WwdgfwbI30x2pFoPVrzsq7Hh1YX/aB7vDfQLSTnC0wo5iVCXF2xG +0u5t39Pq+b+UT4FqnojKXfltxsk2tMG6ZcU3zcZEx3OKnCQhuLD9itj3xIoOvTYE +7a9Fk8A4uaXAkaoZgEg2OJJRAqT/NJRjv/1Ca2VCUPAyd1Xj6ymNAvpuZzL0Mhlo +m6RJKRkadqoQmAFT7LK6vRGMrIQwcYsg09jUJICsk/fgCO+JTRl/x/O8nz62h/NY +YGaG+fakQLwg/Mmefmb2MaaY+/HuUnz1ttPiPhAzDqoY87cRlt1ivjShxZDP6bYh +J6Hk334bkzA81UcNnBjJWr+IYEf7rUARpDNjs3jjmyiVcTNcmklmB1JHaZmwkQt5 +DoezOlry0X9wzNbR0pntAf60B81GHLUOq5OLEuQCT3oALXFLLayrQrWU23mR8Yyp +5USUuch2XHEo0OFPzBkkAu+musGdoOrreEOs1FjYQJysY4mjqLYLXVb7lB4U0bw5 +Apv7qbDioto1hfZ9HIhkzJFtHfyQIO61BkhIpy3hK6CWvu+zw4MOri/90WKl9oGR +VhjXnXrAkSM18kP7RtCzNKQFBigeM6Pw2KcD7iZyyjpLZ2x13FrSyfITf2S3VxXI +p5bHs7v6ZY7ar5EGgMGZFXQNsjle63GhtxjJPBGbFR0pN7270Ch2IPbFzboUDcYm +PqxnBMOAxqqHque0Ixp611g5p7WjDtv+xD9MVkNDR/uokMvkKPpjHiq/GpduWiax +xfcw1KZjR/5yQtJfI2E6GR0ITWPgk/jze3PUEVVhzaySg4AQxFKtxHqAamVTQpfb +o/e/YWICrsznBC4xD0dgZU4RC0Ua/pDfxmOBs7S3yDA1nmIjMbz1bjdXchwX4tJR +GGQ/T/EuI8z3Eys9QIrAkPJ9ivPdWEQyMjiltdKmr9wS2I7UuE8+DJjWxJ/Vrb0L +mxm75pKlogceCLZNVKJtdlaHAnODfoDqzsg5umvzD1vsTEyWLeQphPM5ZDK60lL9 +1BvDcV1J7Awqk3+Fqyb28MLdFI5UI2vfZuPTn00hpaaYWC4h3RoiB1/Y8Jqg3xIZ +CYk+kDiK8vHNAOh0cX+49qWKtp2ZOydkXpKt1UhZHJpP/LyTz5yJQwzCU1IShlK1 +wj6At64TeGEOyTRb8YWAY5qGDpEyw92uvJGzv4nCvIgIpE9KN+xxkuHD7KWkRePU +486AhYRBoBsFO3HaYMkTZusmYkPkAfZUIAqac9zhQ81vG4Pay89AUf1qegWGeo2N +tPr0Bm+KnwnouAQoxL1k03QNpHj+ckxVvC9Yz3qT9TB5dDSgsp+1MGdiqJydJu8g +xfcWE6w9/AaD9OEKxVJGXmzWw0DUv5ec6pvg1VXYYP+5MTgBcwbZqeNQ246AH+tE +lSGJXS1m3Mj7c+8SUnyjjcVQHUTKHkRihOAsyDlbY20tzabI5/cB21SSEvBB+6gH +s60s+BZgD9JcVjtC6cRBhHUjtOl8niLcQfFSbJ26svOqwfbjDrKLaHvD9Dpe5kmI +FWpGHJMBKkGYumEfq3QUkx8FolOiUsx363e4iloH6K1I78+nzKdMru+jn3aEUmxY +wupdht4Wvzt4Qx+5e6NFbc4MhxLHgPE+/8509jT3hPAKypGcySfLkxOpiSkoTIUs +JQ0lI7fNIcqjMLb9wp0tYtqeJvAc8CMHHd1fkV1tvy5/2jlHk6vifZohEuHB3taD +XSdWHaNlMP1qdsi8NmgMS8xSCg51XnHhZuR+K1WRQdhqa4OiY1ZlxeYTXVtDHJ0p +ufLl5i98YD+dYTPM1SK+/JH1IPjtt37nJW7Mz7ZcQuWBn/oZZC3+61tivpRYu4mc +8YYYa1szyhl3L5zvhHKNO6gY3MZBv5WT0uLLhr3wQHkGHsn9+EtDhCrCaONdkT5r +6mGZzfRBOe6B7h3Gwc6AVPODxE2SSS4G8PtMvfDFD4yTPYF/E5OBd5VJ+u9SGGoJ +Bn6sYRxBiZdEBlMLysmtAznaPistaVRigrAeaa03xqNLNkMXL0S3EaQe5KdY7uz6 +t0PcQrNDUoZtYmRu21JUlQ1jih6+/r+oNw0d6WpP2lpW1DoRchC1W8hQK4+WFoHf +Q6TIeO5imAISW5fOiFftw1xgLcfKgnReP8Yt1+ULq9XfMxQWMJx2c8U0upF8nmfQ +om431jc6z7kUiYmPZ7bmWhvrOnzXyogJMA7Tkx+E9IXAgb3E7gvqknomjLyiS6Bi +m/pWWB3lVhBJJSKpJIqN3+ksko28L2oFHeJv0vf1nLP8H0BDUvKsvMD+D4WB9Xe5 +4zyTYXLX7cmkJBF7BLAK/WUnyy22wI/ZOc/gojq2pb1r1p8Evvg/K60+m0KHcZK0 +lhOuros4TEutHVos2cTkcsn82LCeRyESZ8Zkw56EDZ0= +`pragma protect end_protected + +//pragma protect end + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/fpga/ip/gSDHC/gSDHC_define.vh b/fpga/ip/gSDHC/gSDHC_define.vh new file mode 100644 index 0000000..a261877 --- /dev/null +++ b/fpga/ip/gSDHC/gSDHC_define.vh @@ -0,0 +1,47 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 6.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam DATA_BUFFER_DEPTH = 512; +localparam ADMA_DATA_WIDTH = 128; diff --git a/fpga/ip/gSDHC/gSDHC_tmpl.v b/fpga/ip/gSDHC/gSDHC_tmpl.v new file mode 100644 index 0000000..84b81fc --- /dev/null +++ b/fpga/ip/gSDHC/gSDHC_tmpl.v @@ -0,0 +1,111 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 6.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +gSDHC u_gSDHC +( + .sd_rst ( sd_rst ), + .sd_base_clk ( sd_base_clk ), + .sd_int ( sd_int ), + .sd_cd_n ( sd_cd_n ), + .sd_wp ( sd_wp ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_aclk ( s_axi_aclk ), + .s_axi_awready ( s_axi_awready ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_wready ( s_axi_wready ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_bready ( s_axi_bready ), + .s_axi_arready ( s_axi_arready ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rready ( s_axi_rready ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_clk ( m_axi_clk ), + .m_axi_awlen ( m_axi_awlen ), + .m_axi_awready ( m_axi_awready ), + .m_axi_awsize ( m_axi_awsize ), + .m_axi_awcache ( m_axi_awcache ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awprot ( m_axi_awprot ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wready ( m_axi_wready ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_bready ( m_axi_bready ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlen ( m_axi_arlen ), + .m_axi_arsize ( m_axi_arsize ), + .m_axi_arburst ( m_axi_arburst ), + .m_axi_arprot ( m_axi_arprot ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arcache ( m_axi_arcache ), + .m_axi_arready ( m_axi_arready ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_rready ( m_axi_rready ), + .sd_clk_hi ( sd_clk_hi ), + .sd_clk_lo ( sd_clk_lo ), + .sd_cmd_i ( sd_cmd_i ), + .sd_cmd_o ( sd_cmd_o ), + .sd_cmd_oe ( sd_cmd_oe ), + .sd_dat_i ( sd_dat_i ), + .sd_dat_o ( sd_dat_o ), + .sd_dat_oe ( sd_dat_oe ), + .m_axi_awburst ( m_axi_awburst ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_rdata ( m_axi_rdata ), + .s_axi_wstrb ( s_axi_wstrb ) +); diff --git a/fpga/ip/gSDHC/gSDHC_tmpl.vhd b/fpga/ip/gSDHC/gSDHC_tmpl.vhd new file mode 100644 index 0000000..98a4d2b --- /dev/null +++ b/fpga/ip/gSDHC/gSDHC_tmpl.vhd @@ -0,0 +1,177 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +component gSDHC is +port ( + sd_rst : in std_logic; + sd_base_clk : in std_logic; + sd_int : out std_logic; + sd_cd_n : in std_logic; + sd_wp : in std_logic; + s_axi_awaddr : in std_logic_vector(9 downto 0); + s_axi_aclk : in std_logic; + s_axi_awready : out std_logic; + s_axi_awvalid : in std_logic; + s_axi_wdata : in std_logic_vector(31 downto 0); + s_axi_wready : out std_logic; + s_axi_wvalid : in std_logic; + s_axi_bresp : out std_logic_vector(1 downto 0); + s_axi_bvalid : out std_logic; + s_axi_araddr : in std_logic_vector(9 downto 0); + s_axi_bready : in std_logic; + s_axi_arready : out std_logic; + s_axi_arvalid : in std_logic; + s_axi_rresp : out std_logic_vector(1 downto 0); + s_axi_rdata : out std_logic_vector(31 downto 0); + s_axi_rvalid : out std_logic; + s_axi_rready : in std_logic; + m_axi_awaddr : out std_logic_vector(31 downto 0); + m_axi_awvalid : out std_logic; + m_axi_clk : in std_logic; + m_axi_awlen : out std_logic_vector(7 downto 0); + m_axi_awready : in std_logic; + m_axi_awsize : out std_logic_vector(2 downto 0); + m_axi_awcache : out std_logic_vector(3 downto 0); + m_axi_awlock : out std_logic_vector(1 downto 0); + m_axi_awprot : out std_logic_vector(2 downto 0); + m_axi_wlast : out std_logic; + m_axi_wvalid : out std_logic; + m_axi_wready : in std_logic; + m_axi_bresp : in std_logic_vector(1 downto 0); + m_axi_bvalid : in std_logic; + m_axi_bready : out std_logic; + m_axi_arvalid : out std_logic; + m_axi_araddr : out std_logic_vector(31 downto 0); + m_axi_arlen : out std_logic_vector(7 downto 0); + m_axi_arsize : out std_logic_vector(2 downto 0); + m_axi_arburst : out std_logic_vector(1 downto 0); + m_axi_arprot : out std_logic_vector(2 downto 0); + m_axi_arlock : out std_logic_vector(1 downto 0); + m_axi_arcache : out std_logic_vector(3 downto 0); + m_axi_arready : in std_logic; + m_axi_rvalid : in std_logic; + m_axi_rlast : in std_logic; + m_axi_rresp : in std_logic_vector(1 downto 0); + m_axi_rready : out std_logic; + sd_clk_hi : out std_logic; + sd_clk_lo : out std_logic; + sd_cmd_i : in std_logic; + sd_cmd_o : out std_logic; + sd_cmd_oe : out std_logic; + sd_dat_i : in std_logic_vector(3 downto 0); + sd_dat_o : out std_logic_vector(3 downto 0); + sd_dat_oe : out std_logic; + m_axi_awburst : out std_logic_vector(1 downto 0); + m_axi_wdata : out std_logic_vector(127 downto 0); + m_axi_wstrb : out std_logic_vector(15 downto 0); + m_axi_rdata : in std_logic_vector(127 downto 0); + s_axi_wstrb : in std_logic_vector(3 downto 0) +); +end component gSDHC; + +---------------------- End COMPONENT Declaration ------------ +------------- Begin Cut here for INSTANTIATION Template ----- +u_gSDHC : gSDHC +port map ( + sd_rst => sd_rst, + sd_base_clk => sd_base_clk, + sd_int => sd_int, + sd_cd_n => sd_cd_n, + sd_wp => sd_wp, + s_axi_awaddr => s_axi_awaddr, + s_axi_aclk => s_axi_aclk, + s_axi_awready => s_axi_awready, + s_axi_awvalid => s_axi_awvalid, + s_axi_wdata => s_axi_wdata, + s_axi_wready => s_axi_wready, + s_axi_wvalid => s_axi_wvalid, + s_axi_bresp => s_axi_bresp, + s_axi_bvalid => s_axi_bvalid, + s_axi_araddr => s_axi_araddr, + s_axi_bready => s_axi_bready, + s_axi_arready => s_axi_arready, + s_axi_arvalid => s_axi_arvalid, + s_axi_rresp => s_axi_rresp, + s_axi_rdata => s_axi_rdata, + s_axi_rvalid => s_axi_rvalid, + s_axi_rready => s_axi_rready, + m_axi_awaddr => m_axi_awaddr, + m_axi_awvalid => m_axi_awvalid, + m_axi_clk => m_axi_clk, + m_axi_awlen => m_axi_awlen, + m_axi_awready => m_axi_awready, + m_axi_awsize => m_axi_awsize, + m_axi_awcache => m_axi_awcache, + m_axi_awlock => m_axi_awlock, + m_axi_awprot => m_axi_awprot, + m_axi_wlast => m_axi_wlast, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_arvalid => m_axi_arvalid, + m_axi_araddr => m_axi_araddr, + m_axi_arlen => m_axi_arlen, + m_axi_arsize => m_axi_arsize, + m_axi_arburst => m_axi_arburst, + m_axi_arprot => m_axi_arprot, + m_axi_arlock => m_axi_arlock, + m_axi_arcache => m_axi_arcache, + m_axi_arready => m_axi_arready, + m_axi_rvalid => m_axi_rvalid, + m_axi_rlast => m_axi_rlast, + m_axi_rresp => m_axi_rresp, + m_axi_rready => m_axi_rready, + sd_clk_hi => sd_clk_hi, + sd_clk_lo => sd_clk_lo, + sd_cmd_i => sd_cmd_i, + sd_cmd_o => sd_cmd_o, + sd_cmd_oe => sd_cmd_oe, + sd_dat_i => sd_dat_i, + sd_dat_o => sd_dat_o, + sd_dat_oe => sd_dat_oe, + m_axi_awburst => m_axi_awburst, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_rdata => m_axi_rdata, + s_axi_wstrb => s_axi_wstrb +); + +------------------------ End INSTANTIATION Template --------- diff --git a/fpga/ip/gSDHC/ipm/component.pickle b/fpga/ip/gSDHC/ipm/component.pickle new file mode 100644 index 0000000..d292d37 Binary files /dev/null and b/fpga/ip/gSDHC/ipm/component.pickle differ diff --git a/fpga/ip/gSDHC/ipm/graph.pickle b/fpga/ip/gSDHC/ipm/graph.pickle new file mode 100644 index 0000000..6ca87a2 Binary files /dev/null and b/fpga/ip/gSDHC/ipm/graph.pickle differ diff --git a/fpga/ip/gSDHC/settings.json b/fpga/ip/gSDHC/settings.json new file mode 100644 index 0000000..114b4b5 --- /dev/null +++ b/fpga/ip/gSDHC/settings.json @@ -0,0 +1,31 @@ +{ + "args": [ + "-o", + "gSDHC", + "--base_path", + "/projects/SSE/llching/repo/efx_IP_master/efx_IP/efx_hard_soc/fpga/Ti375C529_devkit/ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "memory_controller", + "name": "efx_sd_host_controller", + "version": "6.0" + } + ], + "conf": { + "DATA_BUFFER_DEPTH": "512", + "ADMA_DATA_WIDTH": "128" + }, + "output": { + "external_script_reference_design": [], + "external_source_source": [ + "gSDHC/gSDHC_define.vh", + "gSDHC/gSDHC.v", + "gSDHC/gSDHC_tmpl.v", + "gSDHC/gSDHC_tmpl.vhd" + ] + }, + "ooc_synthesis": {}, + "sw_version": "2025.2.272", + "generated_date": "2025-10-16T09:29:16.536987+00:00" +} \ No newline at end of file diff --git a/fpga/ip/gTSE/T120F324_devkit/DaulClkFifo.v b/fpga/ip/gTSE/T120F324_devkit/DaulClkFifo.v new file mode 100644 index 0000000..7d34961 --- /dev/null +++ b/fpga/ip/gTSE/T120F324_devkit/DaulClkFifo.v @@ -0,0 +1,498 @@ + +`timescale 1ns/100ps + +module DC_FIFO +# ( + parameter FIFO_MODE = "Normal" , //"Normal"; //"ShowAhead" + parameter DATA_WIDTH = 8 , + parameter FIFO_DEPTH = 512 , + + parameter AW_C = $clog2(FIFO_DEPTH), + parameter DW_C = DATA_WIDTH , + parameter DD_C = 2**AW_C + ) +( + //System Signal + input Reset , //System Reset + //Write Signal + input WrClk , //(I)Wirte Clock + input WrEn , //(I)Write Enable + output [AW_C-1:0] WrDNum , //(O)Write Data Number In Fifo + output WrFull , //(I)Write Full + input [DW_C -1:0] WrData , //(I)Write Data + //Read Signal + input RdClk , //(I)Read Clock + input RdEn , //(I)Read Enable + output [AW_C-1:0] RdDNum , //(O)Radd Data Number In Fifo + output RdEmpty , //(O)Read FifoEmpty + output [DW_C-1 :0] RdData //(O)Read Data +); + +//Define Parameter +/////////////////////////////////////////////////////////////// + localparam TCo_C = 0 ; + + reg [1:0] WrClkRstGen = 2'h3; + reg [1:0] RdClkRstGen = 2'h3; + + always @( posedge WrClk or posedge Reset) + begin + if (Reset) WrClkRstGen <= # TCo_C 2'h3; + else + begin + WrClkRstGen[0] <= # TCo_C 1'h0; + WrClkRstGen[1] <= # TCo_C (&RdClkRstGen); + end + end + + wire WrClkRst = WrClkRstGen[1]; + + /////////////////////////////////////////////////// + always @( posedge RdClk or posedge Reset) + begin + if (Reset) RdClkRstGen <= # TCo_C 2'h3; + else + begin + RdClkRstGen[0] <= # TCo_C 1'h0; + RdClkRstGen[1] <= # TCo_C (&WrClkRstGen); + end + end + + wire RdClkRst = RdClkRstGen[1]; + + /////////////////////////////////////////////////// + wire FifoWrEn = WrEn; + wire [AW_C :0] WrAddrCnt ; + wire [AW_C :0] FifoWrAddr ; + wire FifoWrFull ; + + FifoAddrCnt # ( .CounterWidth_C (AW_C)) + U1_WrAddrCnt + ( + //System Signal + .Reset ( WrClkRst ) , //System Reset + .SysClk ( WrClk ) , //System Clock + //Counter Signal + .ClkEn ( FifoWrEn ) , //(I)Clock Enable + .FifoFlag ( FifoWrFull ) , //(I)Fifo Flag + .AddrCnt ( WrAddrCnt ) , //(O)Address Counter + .Addess ( FifoWrAddr ) //(O)Address Output + ); + + /////////////////////////////////////////////////// + reg [DW_C-1:0] FifoBuff [DD_C-1:0]; + + always @( posedge WrClk) + begin + if (WrEn & (~WrFull)) + begin + FifoBuff[FifoWrAddr[AW_C-1:0]] <= # TCo_C WrData; + end + end + + /////////////////////////////////////////////////// + + /////////////////////////////////////////////////// + wire FifoEmpty ; + wire FifoRdEn ; + + wire [AW_C :0] RdAddrCnt ; + wire [AW_C :0] FifoRdAddr ; + + FifoAddrCnt #( .CounterWidth_C (AW_C)) + U2_RdAddrCnt + ( + //System Signal + .Reset ( RdClkRst ) , //System Reset + .SysClk ( RdClk ) , //System Clock + //Counter Signal + .ClkEn ( FifoRdEn ) , //(I)Clock Enable + .FifoFlag ( FifoEmpty ) , //(I)Fifo Flag + .AddrCnt ( RdAddrCnt ) , //(O)Address Counter + .Addess ( FifoRdAddr ) //(O)Address Output + ); + + /////////////////////////////////////////////////// + reg [DW_C-1 :0] FifoRdData ; + + always @( posedge RdClk) + begin + if (FifoRdEn) FifoRdData <= # TCo_C FifoBuff[FifoRdAddr[AW_C-1:0]]; + end + + /////////////////////////////////////////////////// + assign RdData = FifoRdData ; //(O)Read Data + + reg [AW_C:0] WrRdAddr = {AW_C+1{1'h0}}; + + always @( posedge WrClk) + begin + if (WrClkRst) WrRdAddr <= # TCo_C {AW_C+1{1'h0}} ; + else WrRdAddr <= # TCo_C FifoRdAddr [AW_C:0] ; + end + + /////////////////////////////////////////////////////////// + wire [AW_C-1:0] WrRdAHex; + wire [AW_C-1:0] WrWrAHex; + + GrayDecode #(AW_C) WRAGray2Hex (WrRdAddr [AW_C-1:0] , WrRdAHex[AW_C-1:0]); + GrayDecode #(AW_C) WWAGray2Hex (FifoWrAddr [AW_C-1:0] , WrWrAHex[AW_C-1:0]); + + /////////////////////////////////////////////////////////// + reg [AW_C-1:0] WrAddrDiff; + + always @( posedge WrClk) + begin + if (WrFull) WrAddrDiff <= # TCo_C {AW_C{1'h1}} ; + else WrAddrDiff <= # TCo_C (WrWrAHex - WrRdAHex) ; + end + + /////////////////////////////////////////////////////////// + assign WrDNum = WrAddrDiff[AW_C-1:0]; //(O)Data Number In Fifo + + reg [AW_C:0] WrRdAddrReg = {AW_C+1{1'h0}}; + + always @( posedge WrClk) + begin + if ( WrClkRst) WrRdAddrReg <= # TCo_C {AW_C+1{1'h0}} ; + else WrRdAddrReg <= # TCo_C WrRdAddr[AW_C : 0] ; + end + + /////////////////////////////////////////////////////////// + reg RdAddrChg = 1'h0; + reg WrFullClr = 1'h0; + + always @( posedge WrClk) + begin + if ( WrClkRst) RdAddrChg <= # TCo_C 1'h0 ; + else RdAddrChg <= # TCo_C (FifoWrFull & (WrRdAddr[AW_C-1:0] != WrRdAddrReg[AW_C-1:0])); + end + + always @( posedge WrClk) + begin + if ( WrClkRst) WrFullClr <= # TCo_C 1'h0 ; + else WrFullClr <= # TCo_C (FifoWrFull & RdAddrChg); + end + + /////////////////////////////////////////////////////////// + reg RdAHighNext = 1'h0; + + wire RdAHighRise = (~WrRdAddrReg[AW_C-1]) & WrRdAddr[AW_C-1]; + + always @( posedge WrClk) + begin + if (WrClkRst ) RdAHighNext <= # TCo_C 1'h0 ; + else if (RdAHighRise) RdAHighNext <= # TCo_C (~WrRdAddr[AW_C]) ; + end + + /////////////////////////////////////////////////// + wire FullCalc = (WrAddrCnt[AW_C-1:0] == WrRdAddr[AW_C-1:0]) + && (WrAddrCnt[AW_C ] != (WrRdAddr[AW_C-1] ? WrRdAddrReg[AW_C] : RdAHighNext) ); + + /////////////////////////////////////////////////// + reg FullFlag = 1'h0; + + always @( posedge WrClk) + begin + if (WrClkRst) FullFlag <= # TCo_C 1'h0; + else if (FullFlag) FullFlag <= # TCo_C (~WrFullClr); + else if (FifoWrEn) FullFlag <= # TCo_C FullCalc; + end + + assign FifoWrFull = FullFlag; + + /////////////////////////////////////////////////// + assign WrFull = FifoWrFull ; //(I)Write Full + + reg [AW_C :0] RdWrAddr = {AW_C+1{1'h0}}; + + always @( posedge RdClk) + begin + if (RdClkRst ) RdWrAddr <= # TCo_C {AW_C+1{1'h0}} ; + else RdWrAddr <= # TCo_C FifoWrAddr [AW_C:0] ; + end + + /////////////////////////////////////////////////////////// + wire [AW_C-1:0] RdWrAHex; + wire [AW_C-1:0] RdRdAHex; + + GrayDecode # (AW_C) RWAGray2Hex (RdWrAddr [AW_C-1:0] , RdWrAHex[AW_C-1:0] ); + GrayDecode # (AW_C) RRAGray2Hex (FifoRdAddr [AW_C-1:0] , RdRdAHex[AW_C-1:0] ); + + /////////////////////////////////////////////////////////// + reg [AW_C-1:0] RdAddrDiff; + + always @( posedge RdClk) + begin + if (RdEmpty ) RdAddrDiff <= # TCo_C {AW_C{1'h0}} ; + else RdAddrDiff <= # TCo_C (RdWrAHex - RdRdAHex) ; + end + + /////////////////////////////////////////////////////////// + assign RdDNum = RdAddrDiff[AW_C-1:0]; //(O)Data Number In Fifo + + reg [AW_C:0] RdWrAddrReg = {AW_C+1{1'h0}}; + + always @( posedge RdClk) + begin + if (RdClkRst) RdWrAddrReg <= # TCo_C {AW_C+1{1'h0}} ; + else RdWrAddrReg <= # TCo_C RdWrAddr [AW_C:0] ; + end + + /////////////////////////////////////////////////////////// + reg WrAddrChg = 1'h0; + reg EmptyClr = 1'h0; + + always @( posedge RdClk) + begin + if (RdClkRst) WrAddrChg <= # TCo_C 1'h0 ; + else WrAddrChg <= # TCo_C FifoEmpty & (RdWrAddr[AW_C-1:0] != RdWrAddrReg[AW_C-1:0]); + end + always @( posedge RdClk) + begin + if (RdClkRst) EmptyClr <= # TCo_C 1'h0; + else EmptyClr <= # TCo_C (FifoEmpty & WrAddrChg); + end + + /////////////////////////////////////////////////////////// + reg WrAHighNext = 1'h0; + + wire WrAHighRise = (~RdWrAddrReg[AW_C-1]) & RdWrAddr[AW_C-1]; + + always @( posedge RdClk) + begin + if (RdClkRst) WrAHighNext <= # TCo_C 1'h0 ; + else if (WrAHighRise) WrAHighNext <= # TCo_C (~RdWrAddr[AW_C]); + end + + /////////////////////////////////////////////////////////// + wire EmptyCalc = (RdAddrCnt[AW_C-1:0] == RdWrAddr[AW_C-1:0]) + && (RdAddrCnt[AW_C ] == (RdWrAddr[AW_C-1] ? RdWrAddrReg[AW_C] : WrAHighNext)); + + /////////////////////////////////////////////////////////// + reg EmptyFlag = 1'h1; + + always @( posedge RdClk) + begin + if (RdClkRst) EmptyFlag <= # TCo_C 1'h1; + else if (EmptyFlag) EmptyFlag <= # TCo_C (~EmptyClr); + else if (FifoRdEn) EmptyFlag <= # TCo_C EmptyCalc; + end + + assign FifoEmpty = EmptyFlag; + + /////////////////////////////////////////////////////////// + reg EmptyReg = 1'h0; + + always @( posedge RdClk ) + begin + if (RdClkRst) EmptyReg <= # TCo_C 1'h1; + else if (FifoRdEn) EmptyReg <= # TCo_C FifoEmpty; + end + + /////////////////////////////////////////////////////////// + assign RdEmpty = (FIFO_MODE == "ShowAhead") ? EmptyReg : FifoEmpty; //(O)Read FifoEmpty + + reg RdFirst = 1'h0; + + always @( posedge RdClk) + begin + if (FIFO_MODE == "ShowAhead") + begin + if (RdClkRst) RdFirst <= # TCo_C 1'h0 ; + else if (RdFirst) RdFirst <= # TCo_C 1'h0 ; + else if (EmptyClr) RdFirst <= # TCo_C RdEmpty ; + end + else RdFirst <= # TCo_C 1'h0 ; + end + + /////////////////////////////////////////////////////////// + assign FifoRdEn = RdEn || RdFirst ; + + /////////////////////////////////////////////////////////// + +//666666666666666666666666666666666666666666666666666666666 + +endmodule + +//////////////// DaulClkFifo ////////////////////////////// + +///////////////// FifoAddrCnt ///////////////////////////// + +module FifoAddrCnt +# ( + parameter CounterWidth_C = 9 , + parameter CW_C = CounterWidth_C + ) +( + //System Signal + input Reset , //System Reset + input SysClk , //System Clock + //Counter Signal + input ClkEn , //(I)Clock Enable + input FifoFlag , //(I)Fifo Flag + output [CW_C:0] AddrCnt , //(O)Address Counter + output [CW_C:0] Addess //(O)Address Output +); + +//Define Parameter +/////////////////////////////////////////////////////////// +localparam TCo_C = 1; + + wire [CW_C-1:0] GrayAddrCnt; + wire CarryOut; + + GrayCnt #(.CounterWidth_C (CW_C)) + U1_AddrCnt + ( + //System Signal + .Reset ( Reset ), //System Reset + .SysClk ( SysClk ), //System Clock + //Counter Signal + .SyncClr ( 1'h0 ), //(I)Sync Clear + .ClkEn ( ClkEn ), //(I)Clock Enable + .CarryIn ( ~FifoFlag ), //(I)Carry input + .CarryOut ( CarryOut ), //(O)Carry output + .Count ( GrayAddrCnt ) //(O)Counter Value Output + ); + +/////////////////////////////////////////////////////////// + reg CntHighBit; + + always @( posedge SysClk ) + begin + if (Reset) CntHighBit <= # TCo_C 1'h0; + else if (ClkEn) CntHighBit <= # TCo_C CntHighBit + CarryOut; + end + +/////////////////////////////////////////////////////////// + reg [CW_C:0] AddrOut; //(O)Address Output + + always @(posedge SysClk) + begin + if (Reset) AddrOut <= # TCo_C {CW_C{1'h0}}; + else if (ClkEn) AddrOut <= # TCo_C FifoFlag ? AddrOut : AddrCnt; + end + +/////////////////////////////////////////////////////////// + assign AddrCnt = {CntHighBit , GrayAddrCnt} ; //(O)Address Counter + assign Addess = AddrOut ; //(O)Address Output + +//111111111111111111111111111111111111111111111111111111111 + +endmodule + +/////////////////// FifoAddrCnt ////////////////////////// + +module GrayCnt +# ( + parameter CounterWidth_C = 9 , + parameter CW_C = CounterWidth_C + ) +( + //System Signal + input Reset , //System Reset + input SysClk , //System Clock + //Counter Signal + input SyncClr , //(I)Sync Clear + input ClkEn , //(I)Clock Enable + input CarryIn , //(I)Carry input + output CarryOut , //(O)Carry output + output [CW_C-1:0] Count //(O)Counter Value Output +); + +//Define Parameter +/////////////////////////////////////////////////////////// +localparam TCo_C = 1; + + wire [CW_C:0 ] CryIn ; + wire [CW_C-1:0] CryOut ; + + reg [CW_C-1:0] GrayCnt; + + assign CryIn[0] = CarryIn; + + genvar i; + generate + for(i=0;i1) ? 1'h0: 1'h1 ; + else if (SyncClr) GrayCnt[i] <= # TCo_C (i>1) ? 1'h0: 1'h1 ; + else if (ClkEn) GrayCnt[i] <= # TCo_C GrayCnt[i] + CryIn[i]; + end + + ////////////// + if (i==0) + begin + assign CryOut[0] = GrayCnt[0] && CarryIn; + assign CryIn [1] = ~GrayCnt[0] && CarryIn; + end + else + begin + assign CryOut[i ] = CryOut[ 0] && (~|GrayCnt[i:1]); + assign CryIn [i+1] = CryOut[i-1] && GrayCnt[i ] ; + end + end + + endgenerate + + wire GrayCarry = CryOut[CW_C-2]; + +/////////////////////////////////////////////////////////// + reg CntHigh = 1'h0; + + always @( posedge SysClk) + begin + if (Reset) CntHigh <= # TCo_C 1'h0; + else if (ClkEn) CntHigh <= # TCo_C (CntHigh + GrayCarry); + end + +/////////////////////////////////////////////////////////// + assign Count = {CntHigh , GrayCnt[CW_C-1:1]} ; //(O)Counter Value Output + assign CarryOut = CntHigh & GrayCarry ; //(O)Carry output + +/////////////////////////////////////////////////////////// + +//111111111111111111111111111111111111111111111111111111111 + +endmodule + +////////////////////// GrayCnt //////////////////////////// + +module GrayDecode +# ( + parameter DataWidht_C = 8 + ) +( + input [DataWidht_C-1:0] GrayIn, + output [DataWidht_C-1:0] HexOut +); + + //Define Parameter + /////////////////////////////////////////////////////////////// + parameter TCo_C = 1; + + localparam DW_C = DataWidht_C; + + /////////////////////////////////////////////////////////////// + reg [DW_C-1:0] Hex; + + integer i; + + always @ (GrayIn) + begin + Hex[DW_C-1]=GrayIn[DW_C-1]; + for(i=DW_C-2;i>=0;i=i-1) Hex[i]=Hex[i+1]^GrayIn[i]; + end + + assign HexOut = Hex; + + /////////////////////////////////////////////////////////////// + +endmodule + + + diff --git a/fpga/ip/gTSE/T120F324_devkit/apb3_2_axi4_lite.v b/fpga/ip/gTSE/T120F324_devkit/apb3_2_axi4_lite.v new file mode 100644 index 0000000..a167005 --- /dev/null +++ b/fpga/ip/gTSE/T120F324_devkit/apb3_2_axi4_lite.v @@ -0,0 +1,215 @@ +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / +// / / .' / +// __/ /.' / +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* +`timescale 1 ns / 1 ns +module apb3_2_axi4_lite#( + parameter ADDR_WTH = 10 +) +( +//Globle Signals +input clk, +input rstn, +//APB3 Slave Interface +input [ADDR_WTH-1:0] s_apb3_paddr, +input s_apb3_psel, +input s_apb3_penable, +output reg s_apb3_pready, +input s_apb3_pwrite,//0:rd; 1:wr; +input [31:0] s_apb3_pwdata, +output reg [31:0] s_apb3_prdata, +output reg s_apb3_pslverror, +//AXI4-Lite Master Interface +output reg [ADDR_WTH-1:0] m_axi_awaddr,//Write Address. byte address. +output reg m_axi_awvalid,//Write address valid. +input m_axi_awready,//Write address ready. +output reg [31:0] m_axi_wdata,//Write data bus. +output reg m_axi_wvalid,//Write valid. +input m_axi_wready,//Write ready. +input [1:0] m_axi_bresp,//Write response. +input m_axi_bvalid,//Write response valid. +output wire m_axi_bready,//Response ready. +output reg [ADDR_WTH-1:0] m_axi_araddr,//Read address. byte address. +output reg m_axi_arvalid,//Read address valid. +input m_axi_arready,//Read address ready. +input [1:0] m_axi_rresp,//Read response. +input [31:0] m_axi_rdata,//Read data. +input m_axi_rvalid,//Read valid. +output wire m_axi_rready//Read ready. +); +// Parameter Define +parameter State_idle = 3'd0; +parameter State_wsetup = 3'd1; +parameter State_rsetup = 3'd2; +parameter State_ready = 3'd3; +parameter State_err = 3'd4; + +// Register Define +reg [2:0] cur_state; +reg [2:0] next_state; +reg [7:0] timeout_cnt; + +// Wire Define + +/*----------------------------------------------------------------------------------*\ + The main code +\*----------------------------------------------------------------------------------*/ + +/*----------------------- FSM Region ----------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + cur_state <= State_idle; + else + cur_state <= next_state; +end + +always @(*) +begin + case(cur_state) + State_idle : + if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) + next_state = State_wsetup; + else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0)) + next_state = State_rsetup; + else + next_state = State_idle; + + State_wsetup : + if((m_axi_awvalid == 1'b0) && (m_axi_wvalid == 1'b0)) + next_state = State_ready; + else if(timeout_cnt[7] == 1'b1) + next_state = State_err; + else + next_state = State_wsetup; + + State_rsetup : + if(m_axi_rvalid == 1'b1) + next_state = State_ready; + else if(timeout_cnt[7] == 1'b1) + next_state = State_err; + else + next_state = State_rsetup; + + State_ready : + next_state = State_idle; + + State_err : + next_state = State_idle; + + default : + next_state = State_idle; + endcase +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + timeout_cnt <= 8'h0; + else if((cur_state == State_wsetup) || (cur_state == State_rsetup)) + timeout_cnt <= timeout_cnt + 1'b1; + else + timeout_cnt <= 8'h0; +end + +/*----------------------- APB3 Region ----------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + s_apb3_pready <= 1'b0; + else if((cur_state == State_ready) || (cur_state == State_err)) + s_apb3_pready <= 1'b1; + else + s_apb3_pready <= 1'b0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + s_apb3_pslverror <= 1'b0; + else if(cur_state == State_err) + s_apb3_pslverror <= 1'b1; + else + s_apb3_pslverror <= 1'b0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + s_apb3_prdata <= 32'h0; + else if(m_axi_rvalid == 1'b1) + s_apb3_prdata <= m_axi_rdata; +end + +/*----------------------- AXI4-Lite Region ----------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + m_axi_awaddr <= {ADDR_WTH{1'b0}}; + else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) + m_axi_awaddr <= s_apb3_paddr; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + m_axi_awvalid <= 1'b0; + else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) + m_axi_awvalid <= 1'b1; + else if((m_axi_awready == 1'b1) || (cur_state == State_idle)) + m_axi_awvalid <= 1'b0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + m_axi_wdata <= 32'h0; + else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) + m_axi_wdata <= s_apb3_pwdata; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + m_axi_wvalid <= 1'b0; + else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) + m_axi_wvalid <= 1'b1; + else if((m_axi_wready == 1'b1) || (cur_state == State_idle)) + m_axi_wvalid <= 1'b0; +end + +assign m_axi_bready = 1'b1; + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + m_axi_araddr <= {ADDR_WTH{1'b0}}; + else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b0)) + m_axi_araddr <= s_apb3_paddr; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + m_axi_arvalid <= 1'b0; + else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b0)) + m_axi_arvalid <= 1'b1; + else if((m_axi_arready == 1'b1) || (cur_state == State_idle)) + m_axi_arvalid <= 1'b0; +end + +assign m_axi_rready = 1'b1; + +endmodule diff --git a/fpga/ip/gTSE/T120F324_devkit/axi4_st_mux.v b/fpga/ip/gTSE/T120F324_devkit/axi4_st_mux.v new file mode 100644 index 0000000..fc32c17 --- /dev/null +++ b/fpga/ip/gTSE/T120F324_devkit/axi4_st_mux.v @@ -0,0 +1,61 @@ +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / +// / / .' / +// __/ /.' / +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* +`timescale 1 ns / 1 ns +module axi4_st_mux +( +//Globle Signals +input mux_select, +//Mux In 0 Interface +input [7:0] tdata0, +input tvalid0, +input tlast0, +input tuser0, +output wire tready0, +//Mux In 1 Interface +input [7:0] tdata1, +input tvalid1, +input tlast1, +input tuser1, +output wire tready1, +//Mux Out Interface +output wire [7:0] tdata, +output wire tvalid, +output wire tlast, +output wire tuser, +input tready +); + +// Parameter Define + +// Register Define + +// Wire Define + +/*----------------------------------------------------------------------------------*\ + The main code +\*----------------------------------------------------------------------------------*/ + +assign tdata = (mux_select) ? tdata1 : tdata0; +assign tvalid = (mux_select) ? tvalid1 : tvalid0; +assign tlast = (mux_select) ? tlast1 : tlast0; +assign tuser = (mux_select) ? tuser1 : tuser0; + +assign tready0 = (mux_select) ? 1'b1 : tready; +assign tready1 = (mux_select) ? tready : 1'b1; + + +endmodule diff --git a/fpga/ip/gTSE/T120F324_devkit/gTSE.sv b/fpga/ip/gTSE/T120F324_devkit/gTSE.sv new file mode 100644 index 0000000..8095d65 --- /dev/null +++ b/fpga/ip/gTSE/T120F324_devkit/gTSE.sv @@ -0,0 +1,9844 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.288.2.10 +// IP Version: 7.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _4c19f37180ff465ca20760e199a0613f +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module gTSE +( + input mac_reset, + input proto_reset, + output rx_mac_aclk, + input tx_mac_aclk, + output [2:0] eth_speed, + input rx_axis_clk, + output rx_axis_mac_tuser, + output rx_axis_mac_tlast, + output rx_axis_mac_tvalid, + input rx_axis_mac_tready, + input tx_axis_clk, + input tx_axis_mac_tvalid, + input tx_axis_mac_tlast, + input tx_axis_mac_tuser, + output tx_axis_mac_tready, + output [3:0] rgmii_txd_HI, + output [3:0] rgmii_txd_LO, + output rgmii_tx_ctl_HI, + output rgmii_tx_ctl_LO, + output rgmii_txc_HI, + output rgmii_txc_LO, + input [3:0] rgmii_rxd_HI, + input [3:0] rgmii_rxd_LO, + input rgmii_rx_ctl_HI, + input rgmii_rx_ctl_LO, + input rgmii_rxc, + input s_axi_aclk, + output [7:0] rx_axis_mac_tdata, + input [7:0] tx_axis_mac_tdata, + input [0:0] tx_axis_mac_tstrb, + output [0:0] rx_axis_mac_tstrb, + output MdoEn, + output Mdo, + input Mdi, + output Mdc, + input [9:0] s_axi_araddr, + output s_axi_arready, + input s_axi_arvalid, + input [9:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_awvalid, + input s_axi_bready, + output [1:0] s_axi_bresp, + output s_axi_bvalid, + output [31:0] s_axi_rdata, + input s_axi_rready, + output [1:0] s_axi_rresp, + output s_axi_rvalid, + input [31:0] s_axi_wdata, + output s_axi_wready, + input s_axi_wvalid +); +`IP_MODULE_NAME(efx_mac1gbe) +#( + .VERSION (16), + .TXFIFO_EN (1'b1), + .RXFIFO_EN (1'b1), + .TXFIFO_DTH (4096), + .RXFIFO_DTH (4096), + .PHY_INTF_MODE (0), + .AXIS_DW (8), + .RGMII_RXC_EDGE (1'b1), + .RGMII_TXC_DLY (1'b1), + .INTER_PACKET_GAP (6'd12), + .MTU_FRAME_LENGTH (16'd1518), + .MAC_SOURCE_ADDRESS (48'd0), + .ENABLE_BROADCAST_FILTERING (1'b1), + .LOOPBACK_EN (1'b1), + .APBIF (1'b0), + .FAMILY ("TITANIUM") +) +u_efx_mac1gbe +( + .mac_reset ( mac_reset ), + .proto_reset ( proto_reset ), + .rx_mac_aclk ( rx_mac_aclk ), + .tx_mac_aclk ( tx_mac_aclk ), + .eth_speed ( eth_speed ), + .rx_axis_clk ( rx_axis_clk ), + .rx_axis_mac_tuser ( rx_axis_mac_tuser ), + .rx_axis_mac_tlast ( rx_axis_mac_tlast ), + .rx_axis_mac_tvalid ( rx_axis_mac_tvalid ), + .rx_axis_mac_tready ( rx_axis_mac_tready ), + .tx_axis_clk ( tx_axis_clk ), + .tx_axis_mac_tvalid ( tx_axis_mac_tvalid ), + .tx_axis_mac_tlast ( tx_axis_mac_tlast ), + .tx_axis_mac_tuser ( tx_axis_mac_tuser ), + .tx_axis_mac_tready ( tx_axis_mac_tready ), + .rgmii_txd_HI ( rgmii_txd_HI ), + .rgmii_txd_LO ( rgmii_txd_LO ), + .rgmii_tx_ctl_HI ( rgmii_tx_ctl_HI ), + .rgmii_tx_ctl_LO ( rgmii_tx_ctl_LO ), + .rgmii_txc_HI ( rgmii_txc_HI ), + .rgmii_txc_LO ( rgmii_txc_LO ), + .rgmii_rxd_HI ( rgmii_rxd_HI ), + .rgmii_rxd_LO ( rgmii_rxd_LO ), + .rgmii_rx_ctl_HI ( rgmii_rx_ctl_HI ), + .rgmii_rx_ctl_LO ( rgmii_rx_ctl_LO ), + .rgmii_rxc ( rgmii_rxc ), + .s_axi_aclk ( s_axi_aclk ), + .rx_axis_mac_tdata ( rx_axis_mac_tdata ), + .tx_axis_mac_tdata ( tx_axis_mac_tdata ), + .tx_axis_mac_tstrb ( tx_axis_mac_tstrb ), + .rx_axis_mac_tstrb ( rx_axis_mac_tstrb ), + .MdoEn ( MdoEn ), + .Mdo ( Mdo ), + .Mdi ( Mdi ), + .Mdc ( Mdc ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arready ( s_axi_arready ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awready ( s_axi_awready ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rready ( s_axi_rready ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_wready ( s_axi_wready ), + .s_axi_wvalid ( s_axi_wvalid ) +); +endmodule + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_top) # ( + parameter FAMILY = "TRION", // New Param + parameter SYNC_CLK = 0, + parameter BYPASS_RESET_SYNC = 0, // New Param + parameter SYNC_STAGE = 2, // New Param + parameter MODE = "STANDARD", + parameter DEPTH = 512, // Reverted (Equivalent to WDATA_DEPTH) + parameter DATA_WIDTH = 32, // Reverted (Equivalent to WDATA_WIDTH) + parameter PIPELINE_REG = 1, // Reverted (By default is ON) + parameter OPTIONAL_FLAGS = 1, // Reverted + parameter OUTPUT_REG = 0, + parameter PROGRAMMABLE_FULL = "STATIC_DUAL", // Set to "NONE" if not require this feature + parameter PROG_FULL_ASSERT = 27, + parameter PROG_FULL_NEGATE = 23, + parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature + parameter PROG_EMPTY_ASSERT = 5, + parameter PROG_EMPTY_NEGATE = 7, + parameter ALMOST_FLAG = OPTIONAL_FLAGS, + parameter HANDSHAKE_FLAG = OPTIONAL_FLAGS, + parameter ASYM_WIDTH_RATIO = 4, + parameter WADDR_WIDTH = depth2width(DEPTH), + parameter RDATA_WIDTH = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH), + parameter RD_DEPTH = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH), + parameter RADDR_WIDTH = depth2width(RD_DEPTH), + parameter ENDIANESS = 0, + parameter OVERFLOW_PROTECT = 1, + parameter UNDERFLOW_PROTECT = 1, + parameter RAM_STYLE = "block_ram" + +)( + input wire a_rst_i, + input wire a_wr_rst_i, + input wire a_rd_rst_i, + input wire clk_i, + input wire wr_clk_i, + input wire rd_clk_i, + input wire wr_en_i, + input wire rd_en_i, + input wire [DATA_WIDTH-1:0] wdata, + output wire almost_full_o, + output wire prog_full_o, + output wire full_o, + output wire overflow_o, + output wire wr_ack_o, + output wire [WADDR_WIDTH :0] datacount_o, + output wire [WADDR_WIDTH :0] wr_datacount_o, + output wire empty_o, + output wire almost_empty_o, + output wire prog_empty_o, + output wire underflow_o, + output wire rd_valid_o, + output wire [RDATA_WIDTH-1:0] rdata, + output wire [RADDR_WIDTH :0] rd_datacount_o, + output wire rst_busy +); + +localparam WR_DEPTH = DEPTH; +localparam WDATA_WIDTH = DATA_WIDTH; +localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH) ? 1 : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH*8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32; + +wire wr_rst_int; +wire rd_rst_int; +wire wr_en_int; +wire rd_en_int; +wire [WADDR_WIDTH-1:0] waddr; +wire [RADDR_WIDTH-1:0] raddr; +wire wr_clk_int; +wire rd_clk_int; +wire [WADDR_WIDTH :0] wr_datacount_int; +wire [RADDR_WIDTH :0] rd_datacount_int; + +generate + if (ASYM_WIDTH_RATIO == 4) begin + if (SYNC_CLK) begin + assign wr_clk_int = clk_i; + assign rd_clk_int = clk_i; + assign datacount_o = wr_datacount_int; + assign wr_datacount_o = {(WADDR_WIDTH+1){1'b0}}; + assign rd_datacount_o = {(RADDR_WIDTH+1){1'b0}}; + end + else begin + assign wr_clk_int = wr_clk_i; + assign rd_clk_int = rd_clk_i; + assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; + assign wr_datacount_o = wr_datacount_int; + assign rd_datacount_o = rd_datacount_int; + end + end + else begin + assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; + assign wr_datacount_o = wr_datacount_int; + assign rd_datacount_o = rd_datacount_int; + if (SYNC_CLK) begin + assign wr_clk_int = clk_i; + assign rd_clk_int = clk_i; + end + else begin + assign wr_clk_int = wr_clk_i; + assign rd_clk_int = rd_clk_i; + end + end + + if (!SYNC_CLK) begin + //(* async_reg = "true" *) reg [1:0] wr_rst; + //(* async_reg = "true" *) reg [1:0] rd_rst; + // + //always @ (posedge wr_clk_int or posedge a_rst_i) begin + // if (a_rst_i) + // wr_rst <= 2'b11; + // else + // wr_rst <= {wr_rst[0],1'b0}; + //end + // + //always @ (posedge rd_clk_int or posedge a_rst_i) begin + // if (a_rst_i) + // rd_rst <= 2'b11; + // else + // rd_rst <= {rd_rst[0],1'b0}; + //end + + + if (BYPASS_RESET_SYNC) begin + assign wr_rst_int = a_wr_rst_i; + assign rd_rst_int = a_rd_rst_i; + assign rst_busy = 1'b0; + end + else begin + `IP_MODULE_NAME(efx_resetsync) #( + .ACTIVE_LOW (0) + ) efx_resetsync_wr_rst ( + .clk (wr_clk_int), + .reset (a_rst_i), + .d_o (wr_rst_int) + ); + + `IP_MODULE_NAME(efx_resetsync) #( + .ACTIVE_LOW (0) + ) efx_resetsync_rd_rst ( + .clk (rd_clk_int), + .reset (a_rst_i), + .d_o (rd_rst_int) + ); + assign rst_busy = wr_rst_int | rd_rst_int; + end + + end + else begin + //(* async_reg = "true" *) reg [1:0] a_rst; + // + //always @ (posedge clk_i or posedge a_rst_i) begin + // if (a_rst_i) + // a_rst <= 2'b11; + // else + // a_rst <= {a_rst[0],1'b0}; + //end + wire a_rst; + + `IP_MODULE_NAME(efx_resetsync) #( + .ACTIVE_LOW (0) + ) efx_resetsync_a_rst ( + .clk (clk_i), + .reset (a_rst_i), + .d_o (a_rst) + ); + + if (BYPASS_RESET_SYNC) begin + assign wr_rst_int = a_rst_i; + assign rd_rst_int = a_rst_i; + assign rst_busy = 1'b0; + end + else begin + assign wr_rst_int = a_rst; + assign rd_rst_int = a_rst; + assign rst_busy = wr_rst_int | rd_rst_int; + end + end +endgenerate + +`IP_MODULE_NAME(efx_fifo_ram) # ( + .FAMILY (FAMILY), + .WR_DEPTH (WR_DEPTH), + .RD_DEPTH (RD_DEPTH), + .WDATA_WIDTH (WDATA_WIDTH), + .RDATA_WIDTH (RDATA_WIDTH), + .WADDR_WIDTH (WADDR_WIDTH), + .RADDR_WIDTH (RADDR_WIDTH), + .OUTPUT_REG (OUTPUT_REG), + .RAM_MUX_RATIO (RAM_MUX_RATIO), + .ENDIANESS (ENDIANESS), + .RAM_STYLE (RAM_STYLE) +) xefx_fifo_ram ( + .wdata (wdata), + .waddr (waddr), + .raddr (raddr), + .we (wr_en_int), + .re (rd_en_int), + .wclk (wr_clk_int), + .rclk (rd_clk_int), + .rdata (rdata) +); + +`IP_MODULE_NAME(efx_fifo_ctl) # ( + .SYNC_CLK (SYNC_CLK), + .SYNC_STAGE (SYNC_STAGE), + .MODE (MODE), + .WR_DEPTH (WR_DEPTH), + .WADDR_WIDTH (WADDR_WIDTH), + .RADDR_WIDTH (RADDR_WIDTH), + .ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), + .RAM_MUX_RATIO (RAM_MUX_RATIO), + .PIPELINE_REG (PIPELINE_REG), + .ALMOST_FLAG (ALMOST_FLAG), + .PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), + .PROG_FULL_ASSERT (PROG_FULL_ASSERT), + .PROG_FULL_NEGATE (PROG_FULL_NEGATE), + .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), + .PROG_EMPTY_ASSERT (PROG_EMPTY_ASSERT), + .PROG_EMPTY_NEGATE (PROG_EMPTY_NEGATE), + .OUTPUT_REG (OUTPUT_REG), + .HANDSHAKE_FLAG (HANDSHAKE_FLAG), + .OVERFLOW_PROTECT (OVERFLOW_PROTECT), + .UNDERFLOW_PROTECT (UNDERFLOW_PROTECT) +) xefx_fifo_ctl ( + .wr_rst (wr_rst_int), + .rd_rst (rd_rst_int), + .wclk (wr_clk_int), + .rclk (rd_clk_int), + .we (wr_en_i), + .re (rd_en_i), + .wr_full (full_o), + .wr_ack (wr_ack_o), + .rd_empty (empty_o), + .wr_almost_full (almost_full_o), + .rd_almost_empty (almost_empty_o), + .wr_prog_full (prog_full_o), + .rd_prog_empty (prog_empty_o), + .wr_en_int (wr_en_int), + .rd_en_int (rd_en_int), + .waddr (waddr), + .raddr (raddr), + .wr_datacount (wr_datacount_int), + .rd_datacount (rd_datacount_int), + .rd_vld (rd_valid_o), + .wr_overflow (overflow_o), + .rd_underflow (underflow_o) +); + +function integer depth2width; +input [31:0] depth; +begin : fnDepth2Width + if (depth > 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian + parameter RAM_STYLE = "block_ram" +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + always @ (posedge wclk) begin + for (i=0; i 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_resetsync) #( + parameter ASYNC_STAGE = 2, + parameter ACTIVE_LOW = 1 +) ( + input wire clk, + input wire reset, + output wire d_o +); + + +generate + if (ACTIVE_LOW == 1) begin: active_low + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (1), + .RST_VALUE (0) + ) efx_resetsync_active_low ( + .clk (clk), + .reset_n (reset), + .d_i (1'b1), + .d_o (d_o) + ); + end + else begin: active_high + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (0), + .RST_VALUE (1) + ) efx_resetsync_active_high ( + .clk (clk), + .reset_n (reset), + .d_i (1'b0), + .d_o (d_o) + ); + end +endgenerate + +endmodule + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_asyncreg) #( + parameter ASYNC_STAGE = 2, + parameter WIDTH = 4, + parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset + parameter RST_VALUE = 0, + parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance +) ( + input wire clk, + input wire reset_n, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + + + + + + + + + + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect author = "author-a" , author_info = "author-a-details" +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V +o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE +El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY +kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc +/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 +uYJaS5tuGEuFInBHa7oO8g== +`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 +fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa +rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq +PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL +DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w +K3OoKmk3zFeArSsql8B4/Q== +`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 ) +`pragma protect key_block +RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M +GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l +6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI= +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf +RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk +1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw +Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz +eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0 +2HflB1HYKxojQCcZU7qUgQ== +`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx +Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB +rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr +XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD +e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod +B2Zpo2FQ//YDRSAaEa9ksQ== +`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze +vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 +ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 +06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP +fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN +ZoPzFCMjGk5ZmMyIlytNCw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 ) +`pragma protect data_block +0d33xo/2RnBYy8BD6jq1J42m9u/75PA0owNvxlnr0TDOq7sF8XT6xouctVD1XQW2 +Ylwj0urY+dCJZku0aGRpcvb3H/nTlKVdEZOEl4QqB1gNGz/3mz75A3eudu5zgHEr +MaagjyQfDnoIqLWi1r5uTZrlS298IvNcGAJ+xXzpmkFmfG4Tk/5Jf2GPAPVtjREI +01kt8Go4CL1WNxBKcwm0xCiCchxvZ2oEtpERiC+7LUalgTJapIVoLFpvFv98229k +egvgF1KHNj0rAKedSG2Xo58TyA4iZXJJDdtgCxiKgu3Rimjno7l+ekApwmvx8n+p +yHkRGqetWfRhyE4A5q03RzOeSdA6NbCqijB3NPw/p58brAbA35rrjYpGIZXtZ4mU +De3As8VtD64nS2PRuf4/a2lIcDbwMjNTfMpN7iJfVBJ0/48tLHdetx592TLXenkF +GvAZ2yxoyBYzKctj4Keo+19Xp1UjVd3fr2MR3A7nmxLRKDA+upDxQ7ql8+pR7Moh +0b53/4Ri3Mkl+7EC1KXJNt2VbkZmcT7OAFIoPpibmcXS2R6DNVrhSKzfc2+TRM9r +mwRrJy9/R5RR+WGfw1S57Ho3wBPf4belj+Tfd7yhnwOVRXkTMq5M1BiigrGeeQ3q +z/hc1Kg8b/R+g7lnU0pqASnExPQW/DIMfH1RX75U68CAgaBAH22Vcbkoibp8sxyO +g18LefEh48UffnbpCKyv7SQ3LAdj+YO+KvvXHj1eW+CH7GA2lC5vt2be5Ah2/13H +bCeZ+srG6r7wmafy9MNNh8AgjUfZWwMnuJdCIcHTOfAncCd2B0T1Oza4VIkvnSl5 +60V34JXkfrGsNuHxwCF/sRSBbZUSpqig4ZGYHjOHldx2OANZQeUvLES3fwScYY5D +7SpR4ofVxIB/ev/+RXzvC3MNk1N0GT4F1XwokeeQIr/ilRETe/pFvEKttvviZ7uJ +uEVblS2v61DMXEgDavkbA0WdhMChPulwDvZtisWT4hCKRxfuBvNBtz0wH/WgRoX3 +aipWvPJG3G0xvO0u0EQVNdcxE+LZ7vyGF5HWEwKdQYDyhH+yVDeG+M/b08dU2aq4 +sG7dyygyVnzVbk2Lf0nCkGqKkUZUr05Zim0Wcflkhkqy348SOZ3xmEGuYAkzelLV +feQ+0ScsscFL5Cq4ETfFrN8GO8M5kkBN2ELs1MQecPRsgMCh0hcvd8IQrJTybQPW +aqwp9mgnFvS8AJ1ct+XgrAt8zgVnhaZGS9TKa6OWbr0U+SD5m+/pXjNsZA2dni6b +85/PmQeWeAarE/+EaJn/hlP6y3x3R3ItU8Itf6SB50LZ17LAhIRSIYsa7LBBNWOk +ngFHcGBCJnqTJv3hdVqa9cYipZ98XCa8dqrtAM5Rkxwd6H8KxXA+B+PWEz/cQWlb +szi9u5ufmyaJp6PWhklroQkPJEorUtF96X763itgtlAMHfkZglkElUD/gPlkXLtl +yquUmHqPK5D2pJDq0Q0jromE2yrr9fl3OI+eBehd2YBUivGKeaDFkPx7HbzWp9ok +9bT55H8VKYyF1awcjNND+WcXzm2WfvZHBDUJkRm7dnOQRvcX2RxlPRZSzAA3irVn +GFbHXD0RYn/dUR7Vy4kU68P5S5q4bUxD5vmUCN9vDoCivY7WCnlQCHQs3+iFblzP +A636C3dNQMSw0pjDisiZB63VczY8bivFh3cO82inNw5r2IZjvMB9XPhc4FHuIpfR +F7ptW0TUnO1MSDcZvCnjUfVSnHN22l2FM/P5oI1SbG3W+8YmxBvto8jwpES4ohOQ +YSECrvWkLklq68FVTzB7Tvg3JLdSy3TEKBuZE/ot0w/SXusFovOwd4aeiNDAmzwl +fQuCYHuJ0UKLaVNVAO4mw91PJODKCk2NYTr0ghOLovOXiMhUYtXZ+wFchXVkQKDI +B8BXjM7P+blhoOFA6AhRuCX4gZn0dP6m99qnyBJoxf1/FyfJXuklnPll93amUYUx +MzxNNTf7F08tnKQ8pTOk2mfFZnhA2MFn4XQ9FaGvtUrlJI8bvJTWiZFMF0eOJdIw +kzYOXEzKBjIdWW4rtTZmQJb7AOrznUpYdgTAPip/DQx6cg1+tZAVwhZPCjCsb5wa +em5hMtISQKDc92QrlU5O74OXe7641fzFRcKqy9AzwhZl+tmHk1uvpDkpsYiMa7Rk +YrbIjsKQV36PTqYPvxq1EiwYF8PMRf9FG8JZk85EZdM6QEGuehDHqFcZ+SlUb7/e +ji6GgjKxcZwaRREGKSOslcscHS6QNuGCF3iInqNCT4V2l7nboWOefMT2f1kmQOdE +szTFg563SQ8pu7ok3T3XNqUDi5ulvF+XGHDhcQ2hTkZ+xQ8dHFAWZdgzEGMXF2Lw +jU+ZRA2JULfjxOMIU2j9f+aGWmFx2PELMA5K5uOWYUQG2Fn04p1D6u8MEe7fIPeI +k7KH8j/Tumj+kG4t/lCrme6VM9u6A2NGddX1yH1NCejfophy3UWJg9wL/dNxzf6t +vXdm3rGPdZPWFgSIuGlmT03QZmWGPbs8qvkkUVAL37kMJP2r4L+PI00ZxbX8V5jp +GgYN1Rh+NSOwAcUEFCViRhFYC+Gi5eZ6AF6XDSU6qfjGsUKqJ9yrNx0Km6+SjpAK +7Zxblp7vweFVkJ7IESoFeB+vP8JNeoidbBPGEWo+2V08PgfGgjPEAA6pjj8uc0jC +SDFZ0sVrzvc66PZ5FxbI4g+VuXPJgyJsnQ/eHhPVTVTP3/oGMRVktNiJrkJYxAW7 +Sa/EJMjfXX+rMIWG5ssWLT6WfrojlHduEqJ9hJr24RZy514HHF8SMPRBLD6l1wd5 +07U/ChjFdy5qHn5Ce+lanjxnoxgvCsF3lMqoZ7e2bfzXakj7CxahwqRt6yeU0Q+/ +a8tvIJgHfdtOPw/r6HnSrzpdWzTx2e6/MEryHZqpMN63Lhakpjw1L7u3FD/rW40b +LGajigQ7Ql+cZmP7wYl+uSmTFIS6ZgXOc1ibb7yYxJwpeixPHL1iu5ltvriRiTZ6 +DMbbOjNpPuL7ie3AwgmwXwnpnTL6k/Rj2+ma3B7ImODBMkC4SLtTc0ynCcPAFZKA +Xh78wUAgt1T5Nm4XR555DBO7zPHX9rZzMLil4/j0RMDwn1gitmP2PSNFWsrXJG8p +C46kfpdqoM3Yf6HySlhsith6GW41sMF6imUXwahQQRw240HLW3N876LDe6bjTmgN +eIC7y/4NZk7OmpmP8udAEH+UsNfSGtKA8959AoJDr43XsWkOfccNWstu4sTXA5+w +pCALypmBMdholEsrW9DgsIgbgf2pcOAC9+mAjld+yyQ+UNdKRbmtRDHTztGmcVvw +Szip4YUuTM1tPzReucfm38gVFT7eo1qFQg/FJ4VgeYab7ku5OHuwZQmKyzng/t0U +A1lquVENVYQEIotBiOC7jQ1YTkTasGN4xoFgFTyKLFPyk8bl2/anzr1Fx0ieVGCx +2ipzG2JzIQf/FlHXaYrgkWiF817amty+KZp4/dCJtvDXxzOZKnBTVcjHXpqR1Ik+ +tdV+k+21tXZxP0rkG0yi4//2c5UiWGb0UegpemqutykLuT9tGjsqMuc5DaDH/8zk +wLTVfODT+HqN1/ZLqfq9VoAF5m/ujnPNt3wZcsjsAyBD153rW4Q2yVYMat0sFQN6 +XbNAeNBJZlO/aE1PfKBcSDFkJkPqRxlgdiE5B83/w1MP6Z4qwz7LJ8yTYM22xwRo +LIYpKq52yYMhJm42YeQxbBRTx0MyubCb+ompEVBF28Eh0vE98UAZj7t1szSweg99 +Wq6/4kxR2SQj8rFo2wrZe7ngsDmbIrMk2SinS6WmV4Mj+MBbPlmiuwB6NUV04Id1 +9enBBsJIfWt+PZJXyWkOoG/fOVBUxCY+CMCiab0qQ1EVdhggrdI30BgFqcLjfyD6 +/h5AqIzMGWrhWnap8WDEh1Ah6K9f2oCESSXO751sV5eK8jgl63FJMIVsnjVejxrl +Qa7PCXP3BO6Cnv896NBzAsddPq/AYBLHIC6eX3sTtOxTx52NsmJzoyUSJcAoA/QS +leHU1bLA2z+HGfMrkSzsuvXafmqr3B+PHfWdxrYzTxmVhMBPX/FvEU/gfxXGa6kj +niZYGue/Rk+zXL65ENgPwxiz0mm7QyQ6eMBMRovm6MGyIl/8obkOPygH+lhc+bgR +SNWLmxqjR2YABrKsUgCITQ6GK7VmVR3wOOwbZs+YW/0Yj2yzg7ESjaeqI40/OQFD +Ft2IHaURJPk6jl5vRrcCc0J0GCy7CK0BU14n+Nxfl2+CFRe4efoqZry/CmY2+S4M +p9OqgjUzHGSIbNRAXHf44nIAUjWYvijzzLSj9A7WY3TpYxgtqU8Wbf7SbWmw8RJV +pAYDHGmwHa8fL4Y9xEFF/WqmqWSL3g146i41MKWKY7lchvnWtc6yOgk+0geVFOpe +9BLs4TehFA/SueFC99S0Cxcxc0KMWXOKm0I3bI1CAlLje7wUcdI/pki33iqBLJlL +T2vz8ptPqfgAxDW0ZEvEYY/jfB+jCO0MKT7XK/LZNYSuEke3Y3CeuwZ/5IWkDcwy +7BArmDy7Hpw88le9ODL94mS1fUB8jsBaazeiXniZPNZjBkugt/ZAf4XYuoaGVPAM +DnRd8GW5eiDHFCEB42lpg9n7Ak8cXsSSlODCHeay2VtcQP1DEgwWdI5XdXE879gI +8lLU9bH2MfsxI2mNWCMv5immaioZJDorIVzyMGvIn3OcgqmhTU1owINUJf+Hm8Q7 +JfJq4m6t0J5eoKQH57uSGFkWRZ3dtp5QL3d5bBOMmorXUBzdrLt8wurvNke29bHD +UQdmANjayV8drYWAccZdPWyi9jNC/K31BTDI6RCpZdV3Wr5scOZdXWrl961jirm1 +g/2MGKxriuH2F4MRIh2vp3uS8PLbj4cHJv+5+LtLgs0lpdEMYAvJKDACRg68tDhY +XsF9lhHpcF5+tANOawRtnSvy/rlLn+A3wi7v8tnTZcLkocJ51c+nK5/Ij0YgUrA0 +eLrKNlJM78stswPWkvpBlAJ+G3D4Cw6P3XcJWrLyV3u79jf9PRJZmxMU/COGTmgQ +PJdXp90O3u2Pjdwhp4VdtBK2d/jTpk59j8xbQBavf5flZ+PzoLpd8NSt6GdPVJ5r +uVWvNy14pJXUsn+Tgxj+9Wp3vm5mofWtJAkEgr/Rfp7AVLLShJSd6vsbT7F2+TS/ +OMDv0XH92v1G4tqJ0rbxS1TnxX61+1sfjKlfIQdFR9gxLy71Tb705LQHBAw8vmSx +X6Uv+HbtPaEqRCF+pdvGsLNI2Seo6INA/mXqNpd6VPhfQHtp3bgV+Hxnlcc9lCiI +bCZq6KG4a6sVQHIZ3pZo7PQtoAo22niHvgZFoOVnBv+bu+blmvSV6gxCPoV8rwOe +/WD7YikHE7WVSq1SHtTIcbPv+K+1NKqZIiSCS2qDfJLgI7vH4zjIqibDhzGZTeKV +Km234SSlJ1OL4WQ5FtsxjednjUIAKqVe1auDiTzAKY28dwUkwGN/XXQ+EjrmxQuL +qIAT3WP49EeM+CQCp3D6Vxzm7Picq+RtwtbAXnnSQtvPcaSprODI089a0iR46Pp/ +4DLMUOLS+01HozXF1589YdqYep05No/Fp4eP2RdQxicYxK8d/OcvG7E8F1URVmAa +XdZxVa9caM3xYMWDZaiaOo6IZ+YM5VeZ4KxUblS1L1IlOnGOOZ3AiaLsHOh55ryc +Ei7EaFpheCmlTJyxUg8TdA== +`pragma protect end_protected + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ctl) # ( + parameter SYNC_CLK = 1, + parameter SYNC_STAGE = 2, + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter ASYM_WIDTH_RATIO = 4, + parameter RAM_MUX_RATIO = 1, + parameter PIPELINE_REG = 1, + parameter ALMOST_FLAG = 1, + parameter PROGRAMMABLE_FULL = "NONE", + parameter PROG_FULL_ASSERT = 0, + parameter PROG_FULL_NEGATE = 0, + parameter PROGRAMMABLE_EMPTY = "NONE", + parameter PROG_EMPTY_ASSERT = 0, + parameter PROG_EMPTY_NEGATE = 0, + parameter OUTPUT_REG = 0, + parameter HANDSHAKE_FLAG = 1, + parameter OVERFLOW_PROTECT = 0, + parameter UNDERFLOW_PROTECT = 0 +)( + input wire wr_rst, + input wire rd_rst, + input wire wclk, + input wire rclk, + input wire we, + input wire re, + output wire wr_full, + output reg wr_ack, + output wire wr_almost_full, + output wire rd_empty, + output wire rd_almost_empty, + output wire wr_prog_full, + output wire rd_prog_empty, + output wire wr_en_int, + output wire rd_en_int, + output wire [WADDR_WIDTH-1:0] waddr, + output wire [RADDR_WIDTH-1:0] raddr, + output wire [WADDR_WIDTH:0] wr_datacount, + output wire [RADDR_WIDTH:0] rd_datacount, + output wire rd_vld, + output reg wr_overflow, + output reg rd_underflow +); + +reg [WADDR_WIDTH:0] waddr_cntr; +reg [WADDR_WIDTH:0] waddr_cntr_r; +reg [RADDR_WIDTH:0] raddr_cntr; +reg rd_valid; + +wire [WADDR_WIDTH:0] waddr_int; +wire [RADDR_WIDTH:0] raddr_int; +wire rd_empty_int; +wire [WADDR_WIDTH:0] wr_datacount_int; +wire [RADDR_WIDTH:0] rd_datacount_int; + +assign waddr = waddr_cntr[WADDR_WIDTH-1:0]; +// NIC +wire [RADDR_WIDTH:0] ram_raddr; +assign raddr = (MODE == "FWFT") ? ram_raddr[RADDR_WIDTH-1:0] : raddr_cntr[RADDR_WIDTH-1:0]; +//assign raddr = raddr_cntr[RADDR_WIDTH-1:0]; +//assign wr_en_int = we & ~wr_full; +assign wr_en_int = OVERFLOW_PROTECT ? we & ~wr_full : we; + +assign wr_datacount = wr_datacount_int; +assign rd_datacount = ASYM_WIDTH_RATIO == 4 && SYNC_CLK ? wr_datacount_int : rd_datacount_int; + + +generate + if (MODE == "FWFT") begin + // NIC + //assign rd_en_int = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int); + //assign rd_empty = rd_empty_fwft; + + assign rd_en_int = 1'b1; + //assign rd_empty = rd_empty_int; + + //always @ (posedge rclk or posedge rd_rst) begin + // if (rd_rst) begin + // init_set <= 1'b1; + // end + // else if (~init_set & rd_empty) begin + // init_set <= 1'b1; + // end + // else if (~rd_empty_int) begin + // init_set <= 1'b0; + // end + // else if (rd_empty) begin + // init_set <= 1'b1; + // end + //end + // NIC + //always @ (posedge rclk or posedge rd_rst) begin + // if (rd_rst) begin + // rd_empty_fwft <= 1'b1; + // end + // else if (rd_en_int) begin + // rd_empty_fwft <= 1'b0; + // end + // else if (re) begin + // rd_empty_fwft <= 1'b1; + // end + //end + + //if (FAMILY == "TRION") begin + if (OUTPUT_REG) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid <= 1'b0; + end + else begin + rd_valid <= ~rd_empty; + end + end + assign rd_vld = rd_valid; + end + else begin + assign rd_vld = ~rd_empty; + end + + assign rd_empty = rd_empty_int; + end + else begin + assign rd_en_int = UNDERFLOW_PROTECT ? re & ~rd_empty_int : re; + assign rd_empty = rd_empty_int; + + if (OUTPUT_REG) begin + reg rd_valid_r; + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid_r <= 'h0; + rd_valid <= 'h0; + end + else begin + {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int}; + end + end + assign rd_vld = rd_valid; + end + else begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid <= 'h0; + end + else begin + rd_valid <= rd_en_int; + end + end + assign rd_vld = rd_valid; + end + end + + if (ALMOST_FLAG) begin + assign wr_almost_full = wr_datacount >= WR_DEPTH-1; + assign rd_almost_empty = rd_datacount <= 'd1; + end + else begin + assign wr_almost_full = 1'b0; + assign rd_almost_empty = 1'b0; + end + + if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + // NIC + //wr_ack <= wr_en_int & ~wr_overflow; + wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; + end + end + end + + if (OVERFLOW_PROTECT) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else begin + wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; + end + end + end + + if (UNDERFLOW_PROTECT) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else begin + rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + // NIC + else if (ASYM_WIDTH_RATIO == 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - raddr_int; + assign rd_datacount_int = waddr_int - raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + // NIC + //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_r <= 'h0; + end + else begin + waddr_cntr_r <= waddr_cntr; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + end + // NIC + //else if (rd_en_int) begin + else begin + //raddr_cntr <= raddr_cntr + 1'b1; + //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); + raddr_cntr <= ram_raddr; + end +end +// NIC +assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); + + +generate + if (SYNC_CLK) begin : sync_clk + if (MODE == "FWFT") begin + assign waddr_int = waddr_cntr_r; + assign raddr_int = raddr_cntr; + end + else begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr; + end + end + else begin : async_clk + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx>> 2); + assign _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask_1 = ({3'd0,_zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask} <<< system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address[1 : 0]); + BufferCC_2_b62b14ffe6bb44e5a817b8d08e286c6b bufferCC_5 ( + .io_dataIn (1'b0 ), //i + .io_dataOut (bufferCC_5_io_dataOut), //o + .io_systemClk (io_systemClk ), //i + .io_asyncReset (io_asyncReset ) //i + ); + BufferCC_3_b62b14ffe6bb44e5a817b8d08e286c6b bufferCC_6 ( + .io_dataIn (1'b0 ), //i + .io_dataOut (bufferCC_6_io_dataOut ), //o + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset) //i + ); + VexRiscv_b62b14ffe6bb44e5a817b8d08e286c6b system_cores_0_logic_cpu ( + .dBus_cmd_valid (system_cores_0_logic_cpu_dBus_cmd_valid ), //o + .dBus_cmd_ready (system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready ), //i + .dBus_cmd_payload_wr (system_cores_0_logic_cpu_dBus_cmd_payload_wr ), //o + .dBus_cmd_payload_uncached (system_cores_0_logic_cpu_dBus_cmd_payload_uncached ), //o + .dBus_cmd_payload_address (system_cores_0_logic_cpu_dBus_cmd_payload_address[31:0] ), //o + .dBus_cmd_payload_data (system_cores_0_logic_cpu_dBus_cmd_payload_data[31:0] ), //o + .dBus_cmd_payload_mask (system_cores_0_logic_cpu_dBus_cmd_payload_mask[3:0] ), //o + .dBus_cmd_payload_size (system_cores_0_logic_cpu_dBus_cmd_payload_size[2:0] ), //o + .dBus_cmd_payload_last (system_cores_0_logic_cpu_dBus_cmd_payload_last ), //o + .dBus_rsp_valid (system_cores_0_logic_cpu_dBus_rsp_valid ), //i + .dBus_rsp_payload_last (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_last ), //i + .dBus_rsp_payload_data (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_data[31:0]), //i + .dBus_rsp_payload_error (system_cores_0_logic_cpu_dBus_rsp_payload_error ), //i + .timerInterrupt (_zz_timerInterrupt ), //i + .externalInterrupt (system_cores_0_externalInterrupt_plic_target_iep_regNext ), //i + .softwareInterrupt (_zz_softwareInterrupt ), //i + .debug_bus_cmd_valid (system_cores_0_debugBmb_cmd_valid ), //i + .debug_bus_cmd_ready (system_cores_0_logic_cpu_debug_bus_cmd_ready ), //o + .debug_bus_cmd_payload_wr (system_cores_0_logic_cpu_debug_bus_cmd_payload_wr ), //i + .debug_bus_cmd_payload_address (system_cores_0_debugBmb_cmd_payload_fragment_address[7:0] ), //i + .debug_bus_cmd_payload_data (system_cores_0_debugBmb_cmd_payload_fragment_data[31:0] ), //i + .debug_bus_rsp_data (system_cores_0_logic_cpu_debug_bus_rsp_data[31:0] ), //o + .debug_resetOut (system_cores_0_logic_cpu_debug_resetOut ), //o + .iBus_cmd_valid (system_cores_0_logic_cpu_iBus_cmd_valid ), //o + .iBus_cmd_ready (system_cores_0_iBus_cmd_ready ), //i + .iBus_cmd_payload_address (system_cores_0_logic_cpu_iBus_cmd_payload_address[31:0] ), //o + .iBus_cmd_payload_size (system_cores_0_logic_cpu_iBus_cmd_payload_size[2:0] ), //o + .iBus_rsp_valid (system_cores_0_iBus_rsp_valid ), //i + .iBus_rsp_payload_data (system_cores_0_iBus_rsp_payload_fragment_data[31:0] ), //i + .iBus_rsp_payload_error (system_cores_0_logic_cpu_iBus_rsp_payload_error ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i + ); + JtagBridgeNoTap_b62b14ffe6bb44e5a817b8d08e286c6b system_hardJtag_debug_logic_jtagBridge ( + .io_ctrl_tdi (jtagCtrl_tdi ), //i + .io_ctrl_enable (jtagCtrl_enable ), //i + .io_ctrl_capture (jtagCtrl_capture ), //i + .io_ctrl_shift (jtagCtrl_shift ), //i + .io_ctrl_update (jtagCtrl_update ), //i + .io_ctrl_reset (jtagCtrl_reset ), //i + .io_ctrl_tdo (system_hardJtag_debug_logic_jtagBridge_io_ctrl_tdo ), //o + .io_remote_cmd_valid (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_valid ), //o + .io_remote_cmd_ready (system_hardJtag_debug_logic_debugger_io_remote_cmd_ready ), //i + .io_remote_cmd_payload_last (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_last ), //o + .io_remote_cmd_payload_fragment (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_fragment), //o + .io_remote_rsp_valid (system_hardJtag_debug_logic_debugger_io_remote_rsp_valid ), //i + .io_remote_rsp_ready (system_hardJtag_debug_logic_jtagBridge_io_remote_rsp_ready ), //o + .io_remote_rsp_payload_error (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_error ), //i + .io_remote_rsp_payload_data (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_data[31:0]), //i + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ), //i + .jtagCtrl_tck (jtagCtrl_tck ) //i + ); + SystemDebugger_b62b14ffe6bb44e5a817b8d08e286c6b system_hardJtag_debug_logic_debugger ( + .io_remote_cmd_valid (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_valid ), //i + .io_remote_cmd_ready (system_hardJtag_debug_logic_debugger_io_remote_cmd_ready ), //o + .io_remote_cmd_payload_last (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_last ), //i + .io_remote_cmd_payload_fragment (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_fragment), //i + .io_remote_rsp_valid (system_hardJtag_debug_logic_debugger_io_remote_rsp_valid ), //o + .io_remote_rsp_ready (system_hardJtag_debug_logic_jtagBridge_io_remote_rsp_ready ), //i + .io_remote_rsp_payload_error (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_error ), //o + .io_remote_rsp_payload_data (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_data[31:0]), //o + .io_mem_cmd_valid (system_hardJtag_debug_logic_debugger_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (system_hardJtag_debug_logic_mmMaster_cmd_ready ), //i + .io_mem_cmd_payload_address (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address[31:0]), //o + .io_mem_cmd_payload_data (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_wr (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_size (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_size[1:0] ), //o + .io_mem_rsp_valid (system_hardJtag_debug_logic_mmMaster_rsp_valid ), //i + .io_mem_rsp_payload (system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_data[31:0] ), //i + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i + ); + BufferCC_4_b62b14ffe6bb44e5a817b8d08e286c6b bufferCC_7 ( + .io_dataIn (1'b0 ), //i + .io_dataOut (bufferCC_7_io_dataOut ), //o + .io_systemClk (io_systemClk ), //i + .system_cores_0_debugReset (system_cores_0_debugReset) //i + ); + BmbDecoder_b62b14ffe6bb44e5a817b8d08e286c6b bmbDecoder_4 ( + .io_input_cmd_valid (system_hardJtag_debug_bmb_connector_decoder_cmd_valid ), //i + .io_input_cmd_ready (bmbDecoder_4_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_length[1:0] ), //i + .io_input_cmd_payload_fragment_data (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_mask[3:0] ), //i + .io_input_rsp_valid (bmbDecoder_4_io_input_rsp_valid ), //o + .io_input_rsp_ready (system_hardJtag_debug_bmb_connector_decoder_rsp_ready ), //i + .io_input_rsp_payload_last (bmbDecoder_4_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (bmbDecoder_4_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (bmbDecoder_4_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_valid (bmbDecoder_4_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i + .io_outputs_0_cmd_payload_last (bmbDecoder_4_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_opcode (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_address[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_length (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_0_cmd_payload_fragment_data (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_mask (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_0_rsp_valid (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i + .io_outputs_0_rsp_ready (bmbDecoder_4_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i + .io_outputs_0_rsp_payload_fragment_opcode (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i + .io_outputs_0_rsp_payload_fragment_data (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0]), //i + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i + ); + BmbExclusiveMonitor_b62b14ffe6bb44e5a817b8d08e286c6b system_fabric_exclusiveMonitor_logic ( + .io_input_cmd_valid (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid ), //i + .io_input_cmd_ready (system_fabric_exclusiveMonitor_logic_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_address[31:0]), //i + .io_input_cmd_payload_fragment_length (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_length[5:0] ), //i + .io_input_cmd_payload_fragment_data (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_context ), //i + .io_input_rsp_valid (system_fabric_exclusiveMonitor_logic_io_input_rsp_valid ), //o + .io_input_rsp_ready (_zz_io_input_rsp_ready ), //i + .io_input_rsp_payload_last (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_context ), //o + .io_output_cmd_valid (system_fabric_exclusiveMonitor_logic_io_output_cmd_valid ), //o + .io_output_cmd_ready (system_fabric_exclusiveMonitor_output_connector_decoder_cmd_ready ), //i + .io_output_cmd_payload_last (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_length[5:0] ), //o + .io_output_cmd_payload_fragment_data (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_data[31:0] ), //o + .io_output_cmd_payload_fragment_mask (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_mask[3:0] ), //o + .io_output_cmd_payload_fragment_context (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_context ), //o + .io_output_rsp_valid (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_valid ), //i + .io_output_rsp_ready (system_fabric_exclusiveMonitor_logic_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_data[31:0] ), //i + .io_output_rsp_payload_fragment_context (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_context ) //i + ); + BmbDecoder_1_b62b14ffe6bb44e5a817b8d08e286c6b system_fabric_iBus_bmb_decoder ( + .io_input_cmd_valid (system_fabric_iBus_bmb_cmd_m2sPipe_valid ), //i + .io_input_cmd_ready (system_fabric_iBus_bmb_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_fabric_iBus_bmb_cmd_m2sPipe_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_length[5:0] ), //i + .io_input_rsp_valid (system_fabric_iBus_bmb_decoder_io_input_rsp_valid ), //o + .io_input_rsp_ready (system_fabric_iBus_bmb_rsp_ready ), //i + .io_input_rsp_payload_last (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_valid (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (system_bridge_bmb_arbiter_io_inputs_1_cmd_ready ), //i + .io_outputs_0_cmd_payload_last (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0]), //o + .io_outputs_0_cmd_payload_fragment_length (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //o + .io_outputs_0_rsp_valid (system_bridge_bmb_arbiter_io_inputs_1_rsp_valid ), //i + .io_outputs_0_rsp_ready (system_fabric_iBus_bmb_decoder_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_last ), //i + .io_outputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //i + .io_outputs_0_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_data[31:0] ) //i + ); + BmbArbiter_b62b14ffe6bb44e5a817b8d08e286c6b system_bridge_bmb_arbiter ( + .io_inputs_0_cmd_valid (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid ), //i + .io_inputs_0_cmd_ready (system_bridge_bmb_arbiter_io_inputs_0_cmd_ready ), //o + .io_inputs_0_cmd_payload_last (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last ), //i + .io_inputs_0_cmd_payload_fragment_opcode (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode ), //i + .io_inputs_0_cmd_payload_fragment_address (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address[31:0]), //i + .io_inputs_0_cmd_payload_fragment_length (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length[5:0] ), //i + .io_inputs_0_cmd_payload_fragment_data (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data[31:0] ), //i + .io_inputs_0_cmd_payload_fragment_mask (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask[3:0] ), //i + .io_inputs_0_cmd_payload_fragment_context (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context ), //i + .io_inputs_0_rsp_valid (system_bridge_bmb_arbiter_io_inputs_0_rsp_valid ), //o + .io_inputs_0_rsp_ready (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready ), //i + .io_inputs_0_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_last ), //o + .io_inputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_opcode ), //o + .io_inputs_0_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_data[31:0] ), //o + .io_inputs_0_rsp_payload_fragment_context (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_context ), //o + .io_inputs_1_cmd_valid (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_valid ), //i + .io_inputs_1_cmd_ready (system_bridge_bmb_arbiter_io_inputs_1_cmd_ready ), //o + .io_inputs_1_cmd_payload_last (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_last ), //i + .io_inputs_1_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //i + .io_inputs_1_cmd_payload_fragment_address (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_1_cmd_payload_fragment_length (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //i + .io_inputs_1_cmd_payload_fragment_data (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ), //i + .io_inputs_1_cmd_payload_fragment_mask (4'bxxxx ), //i + .io_inputs_1_rsp_valid (system_bridge_bmb_arbiter_io_inputs_1_rsp_valid ), //o + .io_inputs_1_rsp_ready (system_fabric_iBus_bmb_decoder_io_outputs_0_rsp_ready ), //i + .io_inputs_1_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_last ), //o + .io_inputs_1_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //o + .io_inputs_1_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_data[31:0] ), //o + .io_output_cmd_valid (system_bridge_bmb_arbiter_io_output_cmd_valid ), //o + .io_output_cmd_ready (system_bridge_bmb_cmd_ready ), //i + .io_output_cmd_payload_last (system_bridge_bmb_arbiter_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_source (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_source ), //o + .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_length[5:0] ), //o + .io_output_cmd_payload_fragment_data (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_data[31:0] ), //o + .io_output_cmd_payload_fragment_mask (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_mask[3:0] ), //o + .io_output_cmd_payload_fragment_context (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_context ), //o + .io_output_rsp_valid (system_bridge_bmb_rsp_valid ), //i + .io_output_rsp_ready (system_bridge_bmb_arbiter_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (system_bridge_bmb_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_source (system_bridge_bmb_rsp_payload_fragment_source ), //i + .io_output_rsp_payload_fragment_opcode (system_bridge_bmb_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (system_bridge_bmb_rsp_payload_fragment_data[31:0] ), //i + .io_output_rsp_payload_fragment_context (system_bridge_bmb_rsp_payload_fragment_context ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbDecoder_2_b62b14ffe6bb44e5a817b8d08e286c6b system_bridge_bmb_decoder ( + .io_input_cmd_valid (system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid ), //i + .io_input_cmd_ready (system_bridge_bmb_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_last ), //i + .io_input_cmd_payload_fragment_source (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_length[5:0] ), //i + .io_input_cmd_payload_fragment_data (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_context ), //i + .io_input_rsp_valid (system_bridge_bmb_decoder_io_input_rsp_valid ), //o + .io_input_rsp_ready (system_bridge_bmb_rsp_ready ), //i + .io_input_rsp_payload_last (system_bridge_bmb_decoder_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_context ), //o + .io_outputs_0_cmd_valid (system_bridge_bmb_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (system_bridge_bmb_unburstify_1_io_input_cmd_ready ), //i + .io_outputs_0_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_source ), //o + .io_outputs_0_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0]), //o + .io_outputs_0_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //o + .io_outputs_0_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_0_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_context ), //o + .io_outputs_0_rsp_valid (system_bridge_bmb_unburstify_1_io_input_rsp_valid ), //i + .io_outputs_0_rsp_ready (system_bridge_bmb_decoder_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (system_bridge_bmb_unburstify_1_io_input_rsp_payload_last ), //i + .io_outputs_0_rsp_payload_fragment_source (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_source ), //i + .io_outputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_opcode ), //i + .io_outputs_0_rsp_payload_fragment_data (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_data[31:0] ), //i + .io_outputs_0_rsp_payload_fragment_context (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_context ), //i + .io_outputs_1_cmd_valid (system_bridge_bmb_decoder_io_outputs_1_cmd_valid ), //o + .io_outputs_1_cmd_ready (system_bridge_bmb_unburstify_io_input_cmd_ready ), //i + .io_outputs_1_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_last ), //o + .io_outputs_1_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_source ), //o + .io_outputs_1_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //o + .io_outputs_1_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[31:0]), //o + .io_outputs_1_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[5:0] ), //o + .io_outputs_1_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_1_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_1_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_context ), //o + .io_outputs_1_rsp_valid (system_bridge_bmb_unburstify_io_input_rsp_valid ), //i + .io_outputs_1_rsp_ready (system_bridge_bmb_decoder_io_outputs_1_rsp_ready ), //o + .io_outputs_1_rsp_payload_last (system_bridge_bmb_unburstify_io_input_rsp_payload_last ), //i + .io_outputs_1_rsp_payload_fragment_source (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_source ), //i + .io_outputs_1_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_opcode ), //i + .io_outputs_1_rsp_payload_fragment_data (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //i + .io_outputs_1_rsp_payload_fragment_context (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_context ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbOnChipRam_b62b14ffe6bb44e5a817b8d08e286c6b system_ramA_logic ( + .io_bus_cmd_valid (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_valid ), //i + .io_bus_cmd_ready (system_ramA_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_address[14:0]), //i + .io_bus_cmd_payload_fragment_length (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_mask (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_mask[3:0] ), //i + .io_bus_cmd_payload_fragment_context (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_context[3:0] ), //i + .io_bus_rsp_valid (system_ramA_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (_zz_io_bus_rsp_ready ), //i + .io_bus_rsp_payload_last (system_ramA_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_ramA_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_ramA_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_ramA_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbUnburstify_b62b14ffe6bb44e5a817b8d08e286c6b system_bridge_bmb_unburstify ( + .io_input_cmd_valid (system_bridge_bmb_decoder_io_outputs_1_cmd_valid ), //i + .io_input_cmd_ready (system_bridge_bmb_unburstify_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[5:0] ), //i + .io_input_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_context ), //i + .io_input_rsp_valid (system_bridge_bmb_unburstify_io_input_rsp_valid ), //o + .io_input_rsp_ready (system_bridge_bmb_decoder_io_outputs_1_rsp_ready ), //i + .io_input_rsp_payload_last (system_bridge_bmb_unburstify_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_context ), //o + .io_output_cmd_valid (system_bridge_bmb_unburstify_io_output_cmd_valid ), //o + .io_output_cmd_ready (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i + .io_output_cmd_payload_last (system_bridge_bmb_unburstify_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_length[1:0] ), //o + .io_output_cmd_payload_fragment_data (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_data[31:0] ), //o + .io_output_cmd_payload_fragment_mask (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_mask[3:0] ), //o + .io_output_cmd_payload_fragment_context (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_context[3:0] ), //o + .io_output_rsp_valid (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i + .io_output_rsp_ready (system_bridge_bmb_unburstify_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0] ), //i + .io_output_rsp_payload_fragment_context (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context[3:0]), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbUnburstify_b62b14ffe6bb44e5a817b8d08e286c6b system_bridge_bmb_unburstify_1 ( + .io_input_cmd_valid (system_bridge_bmb_decoder_io_outputs_0_cmd_valid ), //i + .io_input_cmd_ready (system_bridge_bmb_unburstify_1_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //i + .io_input_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_context ), //i + .io_input_rsp_valid (system_bridge_bmb_unburstify_1_io_input_rsp_valid ), //o + .io_input_rsp_ready (system_bridge_bmb_decoder_io_outputs_0_rsp_ready ), //i + .io_input_rsp_payload_last (system_bridge_bmb_unburstify_1_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_context ), //o + .io_output_cmd_valid (system_bridge_bmb_unburstify_1_io_output_cmd_valid ), //o + .io_output_cmd_ready (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i + .io_output_cmd_payload_last (system_bridge_bmb_unburstify_1_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_length[1:0] ), //o + .io_output_cmd_payload_fragment_data (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_data[31:0] ), //o + .io_output_cmd_payload_fragment_mask (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_mask[3:0] ), //o + .io_output_cmd_payload_fragment_context (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_context[3:0] ), //o + .io_output_rsp_valid (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i + .io_output_rsp_ready (system_bridge_bmb_unburstify_1_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0] ), //i + .io_output_rsp_payload_fragment_context (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context[3:0]), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbDecoder_3_b62b14ffe6bb44e5a817b8d08e286c6b system_bmbPeripheral_bmb_decoder ( + .io_input_cmd_valid (system_bmbPeripheral_bmb_cmd_combStage_valid ), //i + .io_input_cmd_ready (system_bmbPeripheral_bmb_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_bmbPeripheral_bmb_cmd_combStage_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_address[23:0] ), //i + .io_input_cmd_payload_fragment_length (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_length[1:0] ), //i + .io_input_cmd_payload_fragment_data (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_context[3:0] ), //i + .io_input_rsp_valid (system_bmbPeripheral_bmb_decoder_io_input_rsp_valid ), //o + .io_input_rsp_ready (_zz_io_input_rsp_ready_1 ), //i + .io_input_rsp_payload_last (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context[3:0] ), //o + .io_outputs_0_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_4 ), //i + .io_outputs_0_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[23:0]), //o + .io_outputs_0_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_0_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_0_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context[3:0] ), //o + .io_outputs_0_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_4 ), //i + .io_outputs_0_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 ), //i + .io_outputs_0_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 ), //i + .io_outputs_0_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4[31:0] ), //i + .io_outputs_0_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4[3:0] ), //i + .io_outputs_1_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid ), //o + .io_outputs_1_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready ), //i + .io_outputs_1_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last ), //o + .io_outputs_1_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //o + .io_outputs_1_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[23:0]), //o + .io_outputs_1_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_1_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_1_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_1_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context[3:0] ), //o + .io_outputs_1_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid ), //i + .io_outputs_1_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready ), //o + .io_outputs_1_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last ), //i + .io_outputs_1_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode ), //i + .io_outputs_1_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data[31:0] ), //i + .io_outputs_1_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context[3:0] ), //i + .io_outputs_2_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid ), //o + .io_outputs_2_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_1 ), //i + .io_outputs_2_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last ), //o + .io_outputs_2_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode ), //o + .io_outputs_2_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address[23:0]), //o + .io_outputs_2_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_2_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_2_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_2_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context[3:0] ), //o + .io_outputs_2_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_1 ), //i + .io_outputs_2_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready ), //o + .io_outputs_2_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 ), //i + .io_outputs_2_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 ), //i + .io_outputs_2_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1[31:0] ), //i + .io_outputs_2_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1[3:0] ), //i + .io_outputs_3_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid ), //o + .io_outputs_3_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_2 ), //i + .io_outputs_3_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last ), //o + .io_outputs_3_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode ), //o + .io_outputs_3_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address[23:0]), //o + .io_outputs_3_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_3_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_3_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_3_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context[3:0] ), //o + .io_outputs_3_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_2 ), //i + .io_outputs_3_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready ), //o + .io_outputs_3_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 ), //i + .io_outputs_3_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 ), //i + .io_outputs_3_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2[31:0] ), //i + .io_outputs_3_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2[3:0] ), //i + .io_outputs_4_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid ), //o + .io_outputs_4_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_3 ), //i + .io_outputs_4_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last ), //o + .io_outputs_4_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode ), //o + .io_outputs_4_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address[23:0]), //o + .io_outputs_4_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_4_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_4_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_4_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context[3:0] ), //o + .io_outputs_4_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_3 ), //i + .io_outputs_4_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready ), //o + .io_outputs_4_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 ), //i + .io_outputs_4_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 ), //i + .io_outputs_4_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3[31:0] ), //i + .io_outputs_4_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3[3:0] ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbClint_b62b14ffe6bb44e5a817b8d08e286c6b system_clint_logic ( + .io_bus_cmd_valid (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i + .io_bus_cmd_ready (system_clint_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[15:0]), //i + .io_bus_cmd_payload_fragment_length (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_context (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[3:0] ), //i + .io_bus_rsp_valid (system_clint_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_bus_rsp_payload_last (system_clint_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_clint_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_clint_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_clint_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o + .io_timerInterrupt (system_clint_logic_io_timerInterrupt ), //o + .io_softwareInterrupt (system_clint_logic_io_softwareInterrupt ), //o + .io_time (system_clint_logic_io_time[63:0] ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbUartCtrl_b62b14ffe6bb44e5a817b8d08e286c6b system_uart_0_io_logic ( + .io_bus_cmd_valid (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i + .io_bus_cmd_ready (system_uart_0_io_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[5:0]), //i + .io_bus_cmd_payload_fragment_length (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_context (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[3:0]), //i + .io_bus_rsp_valid (system_uart_0_io_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (_zz_io_bus_rsp_ready_1 ), //i + .io_bus_rsp_payload_last (system_uart_0_io_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_uart_0_io_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_uart_0_io_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o + .io_uart_txd (system_uart_0_io_logic_io_uart_txd ), //o + .io_uart_rxd (system_uart_0_io_rxd ), //i + .io_interrupt (system_uart_0_io_logic_io_interrupt ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbSpiXdrMasterCtrl_b62b14ffe6bb44e5a817b8d08e286c6b system_spi_0_io_logic ( + .io_ctrl_cmd_valid (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i + .io_ctrl_cmd_ready (system_spi_0_io_logic_io_ctrl_cmd_ready ), //o + .io_ctrl_cmd_payload_last (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i + .io_ctrl_cmd_payload_fragment_opcode (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i + .io_ctrl_cmd_payload_fragment_address (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[11:0]), //i + .io_ctrl_cmd_payload_fragment_length (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i + .io_ctrl_cmd_payload_fragment_data (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i + .io_ctrl_cmd_payload_fragment_context (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[3:0] ), //i + .io_ctrl_rsp_valid (system_spi_0_io_logic_io_ctrl_rsp_valid ), //o + .io_ctrl_rsp_ready (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_ctrl_rsp_payload_last (system_spi_0_io_logic_io_ctrl_rsp_payload_last ), //o + .io_ctrl_rsp_payload_fragment_opcode (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode ), //o + .io_ctrl_rsp_payload_fragment_data (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data[31:0] ), //o + .io_ctrl_rsp_payload_fragment_context (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context[3:0] ), //o + .io_spi_sclk_write (system_spi_0_io_logic_io_spi_sclk_write ), //o + .io_spi_data_0_writeEnable (system_spi_0_io_logic_io_spi_data_0_writeEnable ), //o + .io_spi_data_0_read (system_spi_0_io_data_0_read ), //i + .io_spi_data_0_write (system_spi_0_io_logic_io_spi_data_0_write ), //o + .io_spi_data_1_writeEnable (system_spi_0_io_logic_io_spi_data_1_writeEnable ), //o + .io_spi_data_1_read (system_spi_0_io_data_1_read ), //i + .io_spi_data_1_write (system_spi_0_io_logic_io_spi_data_1_write ), //o + .io_spi_data_2_writeEnable (system_spi_0_io_logic_io_spi_data_2_writeEnable ), //o + .io_spi_data_2_read (system_spi_0_io_data_2_read ), //i + .io_spi_data_2_write (system_spi_0_io_logic_io_spi_data_2_write ), //o + .io_spi_data_3_writeEnable (system_spi_0_io_logic_io_spi_data_3_writeEnable ), //o + .io_spi_data_3_read (system_spi_0_io_data_3_read ), //i + .io_spi_data_3_write (system_spi_0_io_logic_io_spi_data_3_write ), //o + .io_spi_ss (system_spi_0_io_logic_io_spi_ss ), //o + .io_interrupt (system_spi_0_io_logic_io_interrupt ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbToApb3Bridge_b62b14ffe6bb44e5a817b8d08e286c6b io_apbSlave_0_logic ( + .io_input_cmd_valid (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i + .io_input_cmd_ready (io_apbSlave_0_logic_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[15:0]), //i + .io_input_cmd_payload_fragment_length (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i + .io_input_cmd_payload_fragment_data (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_context (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[3:0] ), //i + .io_input_rsp_valid (io_apbSlave_0_logic_io_input_rsp_valid ), //o + .io_input_rsp_ready (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_input_rsp_payload_last (io_apbSlave_0_logic_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (io_apbSlave_0_logic_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (io_apbSlave_0_logic_io_input_rsp_payload_fragment_context[3:0] ), //o + .io_output_PADDR (io_apbSlave_0_logic_io_output_PADDR[15:0] ), //o + .io_output_PSEL (io_apbSlave_0_logic_io_output_PSEL ), //o + .io_output_PENABLE (io_apbSlave_0_logic_io_output_PENABLE ), //o + .io_output_PREADY (io_apbSlave_0_PREADY ), //i + .io_output_PWRITE (io_apbSlave_0_logic_io_output_PWRITE ), //o + .io_output_PWDATA (io_apbSlave_0_logic_io_output_PWDATA[31:0] ), //o + .io_output_PRDATA (io_apbSlave_0_PRDATA[31:0] ), //i + .io_output_PSLVERROR (io_apbSlave_0_PSLVERROR ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + initial begin + debugCd_logic_holdingLogic_resetCounter = 12'h0; + debugCd_logic_outputReset = 1'b1; + end + + always @(*) begin + debugCd_logic_inputResetTrigger = 1'b0; + if(debugCd_logic_inputResetAdapter_stuff_syncTrigger) begin + debugCd_logic_inputResetTrigger = 1'b1; + end + end + + always @(*) begin + debugCd_logic_outputResetUnbuffered = 1'b0; + if(when_ClockDomainGenerator_l77) begin + debugCd_logic_outputResetUnbuffered = 1'b1; + end + end + + assign when_ClockDomainGenerator_l77 = (debugCd_logic_holdingLogic_resetCounter != 12'hfff); + assign debugCd_logic_inputResetAdapter_stuff_syncTrigger = bufferCC_5_io_dataOut; + always @(*) begin + systemCd_logic_inputResetTrigger = 1'b0; + if(bufferCC_6_io_dataOut) begin + systemCd_logic_inputResetTrigger = 1'b1; + end + if(bufferCC_7_io_dataOut) begin + systemCd_logic_inputResetTrigger = 1'b1; + end + end + + always @(*) begin + systemCd_logic_outputResetUnbuffered = 1'b0; + if(when_ClockDomainGenerator_l77_1) begin + systemCd_logic_outputResetUnbuffered = 1'b1; + end + end + + assign when_ClockDomainGenerator_l77_1 = (systemCd_logic_holdingLogic_resetCounter != 6'h3f); + assign system_cores_0_iBus_cmd_valid = system_cores_0_logic_cpu_iBus_cmd_valid; + assign system_cores_0_iBus_cmd_payload_fragment_opcode = 1'b0; + assign system_cores_0_iBus_cmd_payload_fragment_address = system_cores_0_logic_cpu_iBus_cmd_payload_address; + assign system_cores_0_iBus_cmd_payload_fragment_length = 6'h3f; + assign system_cores_0_iBus_cmd_payload_last = 1'b1; + assign system_cores_0_logic_cpu_iBus_rsp_payload_error = (system_cores_0_iBus_rsp_payload_fragment_opcode == 1'b1); + assign system_cores_0_iBus_rsp_ready = 1'b1; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_valid = system_cores_0_logic_cpu_dBus_cmd_valid; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_last = system_cores_0_logic_cpu_dBus_cmd_payload_last; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_opcode = (system_cores_0_logic_cpu_dBus_cmd_payload_wr ? 1'b1 : 1'b0); + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_address = system_cores_0_logic_cpu_dBus_cmd_payload_address; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_data = system_cores_0_logic_cpu_dBus_cmd_payload_data; + always @(*) begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'bxxxxxx; + case(system_cores_0_logic_cpu_dBus_cmd_payload_size) + 3'b000 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h0; + end + 3'b001 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h01; + end + 3'b010 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h03; + end + 3'b011 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h07; + end + 3'b100 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h0f; + end + 3'b101 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h1f; + end + 3'b110 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h3f; + end + default : begin + end + endcase + end + + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_mask = system_cores_0_logic_cpu_dBus_cmd_payload_mask; + assign system_cores_0_logic_cpu_dBus_Bridge_withoutWriteBuffer_busCmdContext_isWrite = system_cores_0_logic_cpu_dBus_cmd_payload_wr; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_withoutWriteBuffer_busCmdContext_isWrite; + always @(*) begin + system_cores_0_logic_cpu_dBus_rsp_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_valid; + if(when_DataCache_l532) begin + system_cores_0_logic_cpu_dBus_rsp_valid = 1'b0; + end + end + + assign when_DataCache_l532 = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_context[0]; + assign system_cores_0_logic_cpu_dBus_rsp_payload_error = (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_opcode == 1'b1); + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_ready = 1'b1; + assign system_cores_0_iBus_cmd_combStage_valid = system_cores_0_iBus_cmd_valid; + assign system_cores_0_iBus_cmd_ready = system_cores_0_iBus_cmd_combStage_ready; + assign system_cores_0_iBus_cmd_combStage_payload_last = system_cores_0_iBus_cmd_payload_last; + assign system_cores_0_iBus_cmd_combStage_payload_fragment_opcode = system_cores_0_iBus_cmd_payload_fragment_opcode; + assign system_cores_0_iBus_cmd_combStage_payload_fragment_address = system_cores_0_iBus_cmd_payload_fragment_address; + assign system_cores_0_iBus_cmd_combStage_payload_fragment_length = system_cores_0_iBus_cmd_payload_fragment_length; + assign system_cores_0_iBus_cmd_combStage_ready = system_cores_0_iBus_connector_decoder_cmd_ready; + always @(*) begin + _zz_system_cores_0_iBus_connector_decoder_rsp_ready = system_cores_0_iBus_rsp_ready; + if(when_Stream_l368) begin + _zz_system_cores_0_iBus_connector_decoder_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! _zz_system_cores_0_iBus_rsp_valid); + assign _zz_system_cores_0_iBus_rsp_valid = _zz_system_cores_0_iBus_rsp_valid_1; + assign system_cores_0_iBus_rsp_valid = _zz_system_cores_0_iBus_rsp_valid; + assign system_cores_0_iBus_rsp_payload_last = _zz_system_cores_0_iBus_rsp_payload_last; + assign system_cores_0_iBus_rsp_payload_fragment_opcode = _zz_system_cores_0_iBus_rsp_payload_fragment_opcode; + assign system_cores_0_iBus_rsp_payload_fragment_data = _zz_system_cores_0_iBus_rsp_payload_fragment_data; + assign system_cores_0_iBus_connector_decoder_cmd_valid = system_cores_0_iBus_cmd_combStage_valid; + assign system_cores_0_iBus_connector_decoder_rsp_ready = _zz_system_cores_0_iBus_connector_decoder_rsp_ready; + assign system_cores_0_iBus_connector_decoder_cmd_payload_last = system_cores_0_iBus_cmd_combStage_payload_last; + assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_opcode = system_cores_0_iBus_cmd_combStage_payload_fragment_opcode; + assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_address = system_cores_0_iBus_cmd_combStage_payload_fragment_address; + assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_length = system_cores_0_iBus_cmd_combStage_payload_fragment_length; + always @(*) begin + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_ready; + if(when_Stream_l368_1) begin + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready = 1'b1; + end + end + + assign when_Stream_l368_1 = (! system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid); + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_last = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_last; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_opcode = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_opcode; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_address = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_address; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_length = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_length; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_data = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_data; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_mask = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_mask; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_context; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_ready = system_cores_0_dBus_connector_decoder_cmd_ready; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_valid = system_cores_0_dBus_connector_decoder_rsp_valid; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_last = system_cores_0_dBus_connector_decoder_rsp_payload_last; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_opcode = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_opcode; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_data = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_data; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_context = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_context; + assign system_cores_0_dBus_connector_decoder_cmd_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid; + assign system_cores_0_dBus_connector_decoder_rsp_ready = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_ready; + assign system_cores_0_dBus_connector_decoder_cmd_payload_last = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_last; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_opcode = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_opcode; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_address = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_address; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_length = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_length; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_data = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_data; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_mask = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_mask; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_context; + assign system_hardJtag_debug_logic_mmMaster_cmd_valid = system_hardJtag_debug_logic_debugger_io_mem_cmd_valid; + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_last = 1'b1; + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_length = 2'b11; + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_opcode = (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_wr ? 1'b1 : 1'b0); + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address = {_zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address,2'b00}; + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_data = system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_data; + always @(*) begin + case(system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_size) + 2'b00 : begin + _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b0001; + end + 2'b01 : begin + _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b0011; + end + default : begin + _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b1111; + end + endcase + end + + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask_1[3:0]; + assign system_hardJtag_debug_logic_mmMaster_rsp_ready = 1'b1; + assign jtagCtrl_tdo = system_hardJtag_debug_logic_jtagBridge_io_ctrl_tdo; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_valid = system_hardJtag_debug_logic_mmMaster_cmd_valid; + assign system_hardJtag_debug_logic_mmMaster_cmd_ready = system_hardJtag_debug_bmb_connector_decoder_cmd_ready; + assign system_hardJtag_debug_logic_mmMaster_rsp_valid = system_hardJtag_debug_bmb_connector_decoder_rsp_valid; + assign system_hardJtag_debug_bmb_connector_decoder_rsp_ready = system_hardJtag_debug_logic_mmMaster_rsp_ready; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_last = system_hardJtag_debug_logic_mmMaster_cmd_payload_last; + assign system_hardJtag_debug_logic_mmMaster_rsp_payload_last = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_last; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_opcode = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_opcode; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_address = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_length = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_length; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_data = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_data; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_mask = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask; + assign system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_opcode = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_opcode; + assign system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_data = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_data; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_ready = bmbDecoder_4_io_input_cmd_ready; + assign system_hardJtag_debug_bmb_connector_decoder_rsp_valid = bmbDecoder_4_io_input_rsp_valid; + assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_last = bmbDecoder_4_io_input_rsp_payload_last; + assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_opcode = bmbDecoder_4_io_input_rsp_payload_fragment_opcode; + assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_data = bmbDecoder_4_io_input_rsp_payload_fragment_data; + assign system_fabric_iBus_bmb_cmd_valid = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_iBus_bmb_cmd_ready; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_iBus_bmb_rsp_valid; + assign system_fabric_iBus_bmb_rsp_ready = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_fabric_iBus_bmb_cmd_payload_last = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_iBus_bmb_rsp_payload_last; + assign system_fabric_iBus_bmb_cmd_payload_fragment_opcode = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_fabric_iBus_bmb_cmd_payload_fragment_address = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_fabric_iBus_bmb_cmd_payload_fragment_length = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_rsp_payload_fragment_opcode; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_iBus_bmb_rsp_payload_fragment_data; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_cores_0_iBus_connector_decoder_cmd_valid; + assign system_cores_0_iBus_connector_decoder_cmd_ready = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_cores_0_iBus_connector_decoder_rsp_valid = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_cores_0_iBus_connector_decoder_rsp_ready; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_cores_0_iBus_connector_decoder_cmd_payload_last; + assign system_cores_0_iBus_connector_decoder_rsp_payload_last = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_opcode; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_address; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_length; + assign system_cores_0_iBus_connector_decoder_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_cores_0_iBus_connector_decoder_rsp_payload_fragment_data = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_valid = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid || system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_last = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_opcode = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_address = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_length = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_data = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_mask = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_mask : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_context = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context); + always @(*) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l368_2) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l368_2 = (! system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_last = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_last; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_opcode = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_opcode; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_address = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_address; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_length = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_length; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_data = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_data; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_mask = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_mask; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_context = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_context; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_ready = system_fabric_exclusiveMonitor_logic_io_input_cmd_ready; + always @(*) begin + _zz_io_input_rsp_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + if(when_Stream_l368_3) begin + _zz_io_input_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368_3 = (! _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid); + assign _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_cores_0_debugBmb_cmd_valid = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_cores_0_debugBmb_cmd_ready; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_cores_0_debugBmb_rsp_valid; + assign system_cores_0_debugBmb_rsp_ready = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_cores_0_debugBmb_cmd_payload_last = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_cores_0_debugBmb_rsp_payload_last; + assign system_cores_0_debugBmb_cmd_payload_fragment_opcode = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_cores_0_debugBmb_cmd_payload_fragment_address = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_cores_0_debugBmb_cmd_payload_fragment_length = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_cores_0_debugBmb_cmd_payload_fragment_data = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_cores_0_debugBmb_cmd_payload_fragment_mask = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_cores_0_debugBmb_rsp_payload_fragment_opcode; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_cores_0_debugBmb_rsp_payload_fragment_data; + assign system_cores_0_logic_cpu_debug_bus_cmd_payload_wr = (system_cores_0_debugBmb_cmd_payload_fragment_opcode == 1'b1); + assign system_cores_0_logic_cpu_debug_bus_cmd_fire = (system_cores_0_debugBmb_cmd_valid && system_cores_0_logic_cpu_debug_bus_cmd_ready); + assign system_cores_0_debugBmb_cmd_ready = system_cores_0_logic_cpu_debug_bus_cmd_ready; + assign system_cores_0_debugBmb_rsp_valid = system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext; + assign system_cores_0_debugBmb_rsp_payload_last = 1'b1; + assign system_cores_0_debugBmb_rsp_payload_fragment_opcode = 1'b0; + assign system_cores_0_debugBmb_rsp_payload_fragment_data = system_cores_0_logic_cpu_debug_bus_rsp_data; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbDecoder_4_io_outputs_0_cmd_valid; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbDecoder_4_io_outputs_0_rsp_ready; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbDecoder_4_io_outputs_0_cmd_payload_last; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_opcode; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_address[7:0]; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_length; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_data; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_mask; + assign system_fabric_dBusCoherent_bmb_cmd_valid = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_dBusCoherent_bmb_cmd_ready; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_dBusCoherent_bmb_rsp_valid; + assign system_fabric_dBusCoherent_bmb_rsp_ready = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_fabric_dBusCoherent_bmb_cmd_payload_last = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_dBusCoherent_bmb_rsp_payload_last; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_context; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_valid = system_fabric_dBusCoherent_bmb_cmd_valid; + assign system_fabric_dBusCoherent_bmb_cmd_ready = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_ready; + assign system_fabric_dBusCoherent_bmb_rsp_valid = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_valid; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_ready = system_fabric_dBusCoherent_bmb_rsp_ready; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_last = system_fabric_dBusCoherent_bmb_cmd_payload_last; + assign system_fabric_dBusCoherent_bmb_rsp_payload_last = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_last; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_address; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_length; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_mask; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_context; + assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_context; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_valid = system_fabric_exclusiveMonitor_logic_io_output_cmd_valid; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_ready = system_fabric_exclusiveMonitor_logic_io_output_rsp_ready; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_last = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_last; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_opcode = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_opcode; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_address = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_address; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_length = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_length; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_data = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_data; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_mask = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_mask; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_context = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_context; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_cores_0_dBus_connector_decoder_cmd_valid; + assign system_cores_0_dBus_connector_decoder_cmd_ready = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_cores_0_dBus_connector_decoder_rsp_valid = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_cores_0_dBus_connector_decoder_rsp_ready; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_cores_0_dBus_connector_decoder_cmd_payload_last; + assign system_cores_0_dBus_connector_decoder_rsp_payload_last = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_address; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_length; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_mask; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_context; + assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_valid; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_valid = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_ready; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_last; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_last = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_opcode; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_address; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_length; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_data; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_mask; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_context; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_opcode = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_data = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_context = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_fabric_dBus_bmb_cmd_valid = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_dBus_bmb_cmd_ready; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_dBus_bmb_rsp_valid; + assign system_fabric_dBus_bmb_rsp_ready = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_fabric_dBus_bmb_cmd_payload_last = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_dBus_bmb_rsp_payload_last; + assign system_fabric_dBus_bmb_cmd_payload_fragment_opcode = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_fabric_dBus_bmb_cmd_payload_fragment_address = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_fabric_dBus_bmb_cmd_payload_fragment_length = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_fabric_dBus_bmb_cmd_payload_fragment_data = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_fabric_dBus_bmb_cmd_payload_fragment_mask = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign system_fabric_dBus_bmb_cmd_payload_fragment_context = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_dBus_bmb_rsp_payload_fragment_opcode; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_dBus_bmb_rsp_payload_fragment_data; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_fabric_dBus_bmb_rsp_payload_fragment_context; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_valid; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_ready = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_valid = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_fabric_exclusiveMonitor_output_connector_decoder_rsp_ready; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_last; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_last = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_opcode; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_address; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_length; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_data; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_mask; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_context; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_opcode = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_data = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_context = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + always @(*) begin + system_fabric_iBus_bmb_cmd_ready = system_fabric_iBus_bmb_cmd_m2sPipe_ready; + if(when_Stream_l368_4) begin + system_fabric_iBus_bmb_cmd_ready = 1'b1; + end + end + + assign when_Stream_l368_4 = (! system_fabric_iBus_bmb_cmd_m2sPipe_valid); + assign system_fabric_iBus_bmb_cmd_m2sPipe_valid = system_fabric_iBus_bmb_cmd_rValid; + assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_last = system_fabric_iBus_bmb_cmd_rData_last; + assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_opcode = system_fabric_iBus_bmb_cmd_rData_fragment_opcode; + assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_address = system_fabric_iBus_bmb_cmd_rData_fragment_address; + assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_length = system_fabric_iBus_bmb_cmd_rData_fragment_length; + assign system_fabric_iBus_bmb_cmd_m2sPipe_ready = system_fabric_iBus_bmb_decoder_io_input_cmd_ready; + assign system_fabric_iBus_bmb_rsp_valid = system_fabric_iBus_bmb_decoder_io_input_rsp_valid; + assign system_fabric_iBus_bmb_rsp_payload_last = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_last; + assign system_fabric_iBus_bmb_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_opcode; + assign system_fabric_iBus_bmb_rsp_payload_fragment_data = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_data; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid = system_fabric_dBus_bmb_cmd_valid; + assign system_fabric_dBus_bmb_cmd_ready = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready; + assign system_fabric_dBus_bmb_rsp_valid = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready = system_fabric_dBus_bmb_rsp_ready; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last = system_fabric_dBus_bmb_cmd_payload_last; + assign system_fabric_dBus_bmb_rsp_payload_last = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode = system_fabric_dBus_bmb_cmd_payload_fragment_opcode; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address = system_fabric_dBus_bmb_cmd_payload_fragment_address; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length = system_fabric_dBus_bmb_cmd_payload_fragment_length; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data = system_fabric_dBus_bmb_cmd_payload_fragment_data; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask = system_fabric_dBus_bmb_cmd_payload_fragment_mask; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context = system_fabric_dBus_bmb_cmd_payload_fragment_context; + assign system_fabric_dBus_bmb_rsp_payload_fragment_opcode = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode; + assign system_fabric_dBus_bmb_rsp_payload_fragment_data = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data; + assign system_fabric_dBus_bmb_rsp_payload_fragment_context = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context; + assign system_bridge_bmb_cmd_valid = system_bridge_bmb_arbiter_io_output_cmd_valid; + assign system_bridge_bmb_rsp_ready = system_bridge_bmb_arbiter_io_output_rsp_ready; + assign system_bridge_bmb_cmd_payload_last = system_bridge_bmb_arbiter_io_output_cmd_payload_last; + assign system_bridge_bmb_cmd_payload_fragment_source = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_source; + assign system_bridge_bmb_cmd_payload_fragment_opcode = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_opcode; + assign system_bridge_bmb_cmd_payload_fragment_address = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_address; + assign system_bridge_bmb_cmd_payload_fragment_length = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_length; + assign system_bridge_bmb_cmd_payload_fragment_data = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_data; + assign system_bridge_bmb_cmd_payload_fragment_mask = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_mask; + assign system_bridge_bmb_cmd_payload_fragment_context = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_context; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready = system_bridge_bmb_arbiter_io_inputs_0_cmd_ready; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid = system_bridge_bmb_arbiter_io_inputs_0_rsp_valid; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_last; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_opcode; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_data; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_context; + assign system_bridge_bmb_cmd_ready = (! system_bridge_bmb_cmd_rValid); + assign system_bridge_bmb_cmd_s2mPipe_valid = (system_bridge_bmb_cmd_valid || system_bridge_bmb_cmd_rValid); + assign system_bridge_bmb_cmd_s2mPipe_payload_last = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_last : system_bridge_bmb_cmd_payload_last); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_source = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_source : system_bridge_bmb_cmd_payload_fragment_source); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_opcode = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_opcode : system_bridge_bmb_cmd_payload_fragment_opcode); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_address = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_address : system_bridge_bmb_cmd_payload_fragment_address); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_length = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_length : system_bridge_bmb_cmd_payload_fragment_length); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_data = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_data : system_bridge_bmb_cmd_payload_fragment_data); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_mask = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_mask : system_bridge_bmb_cmd_payload_fragment_mask); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_context = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_context : system_bridge_bmb_cmd_payload_fragment_context); + always @(*) begin + system_bridge_bmb_cmd_s2mPipe_ready = system_bridge_bmb_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l368_5) begin + system_bridge_bmb_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l368_5 = (! system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid); + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid = system_bridge_bmb_cmd_s2mPipe_rValid; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_last = system_bridge_bmb_cmd_s2mPipe_rData_last; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_source = system_bridge_bmb_cmd_s2mPipe_rData_fragment_source; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_opcode = system_bridge_bmb_cmd_s2mPipe_rData_fragment_opcode; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_address = system_bridge_bmb_cmd_s2mPipe_rData_fragment_address; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_length = system_bridge_bmb_cmd_s2mPipe_rData_fragment_length; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_data = system_bridge_bmb_cmd_s2mPipe_rData_fragment_data; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_mask = system_bridge_bmb_cmd_s2mPipe_rData_fragment_mask; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_context = system_bridge_bmb_cmd_s2mPipe_rData_fragment_context; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_ready = system_bridge_bmb_decoder_io_input_cmd_ready; + assign system_bridge_bmb_rsp_valid = system_bridge_bmb_decoder_io_input_rsp_valid; + assign system_bridge_bmb_rsp_payload_last = system_bridge_bmb_decoder_io_input_rsp_payload_last; + assign system_bridge_bmb_rsp_payload_fragment_source = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_source; + assign system_bridge_bmb_rsp_payload_fragment_opcode = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_opcode; + assign system_bridge_bmb_rsp_payload_fragment_data = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_data; + assign system_bridge_bmb_rsp_payload_fragment_context = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_cmd_valid = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_bmbPeripheral_bmb_cmd_ready; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_bmbPeripheral_bmb_rsp_valid; + assign system_bmbPeripheral_bmb_rsp_ready = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_bmbPeripheral_bmb_cmd_payload_last = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_bmbPeripheral_bmb_rsp_payload_last; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_address = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_length = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_data = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_mask = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_context = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_bmbPeripheral_bmb_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_bmbPeripheral_bmb_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bridge_bmb_unburstify_io_output_cmd_valid; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bridge_bmb_unburstify_io_output_rsp_ready; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bridge_bmb_unburstify_io_output_cmd_payload_last; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_address[23:0]; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_mask; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_context; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_valid = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_ready; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_last = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_opcode = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_address = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_length = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_data = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_mask = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_context = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_ready = system_ramA_logic_io_bus_cmd_ready; + always @(*) begin + _zz_io_bus_rsp_ready = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + if(when_Stream_l368_6) begin + _zz_io_bus_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368_6 = (! _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid); + assign _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bridge_bmb_unburstify_1_io_output_cmd_valid; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bridge_bmb_unburstify_1_io_output_rsp_ready; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bridge_bmb_unburstify_1_io_output_cmd_payload_last; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_opcode; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_address[14:0]; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_length; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_data; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_mask; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_context; + assign system_bmbPeripheral_bmb_cmd_combStage_valid = system_bmbPeripheral_bmb_cmd_valid; + assign system_bmbPeripheral_bmb_cmd_ready = system_bmbPeripheral_bmb_cmd_combStage_ready; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_last = system_bmbPeripheral_bmb_cmd_payload_last; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_opcode = system_bmbPeripheral_bmb_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_address = system_bmbPeripheral_bmb_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_length = system_bmbPeripheral_bmb_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_data = system_bmbPeripheral_bmb_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_mask = system_bmbPeripheral_bmb_cmd_payload_fragment_mask; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_context = system_bmbPeripheral_bmb_cmd_payload_fragment_context; + assign system_bmbPeripheral_bmb_cmd_combStage_ready = system_bmbPeripheral_bmb_decoder_io_input_cmd_ready; + assign _zz_io_input_rsp_ready_1 = (! _zz_system_bmbPeripheral_bmb_rsp_valid_1); + assign _zz_system_bmbPeripheral_bmb_rsp_valid = _zz_system_bmbPeripheral_bmb_rsp_valid_1; + assign system_bmbPeripheral_bmb_rsp_valid = _zz_system_bmbPeripheral_bmb_rsp_valid; + assign system_bmbPeripheral_bmb_rsp_payload_last = _zz_system_bmbPeripheral_bmb_rsp_payload_last; + assign system_bmbPeripheral_bmb_rsp_payload_fragment_opcode = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_rsp_payload_fragment_data = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_rsp_payload_fragment_context = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_context; + assign system_uart_0_io_txd = system_uart_0_io_logic_io_uart_txd; + assign io_apbSlave_0_PADDR = io_apbSlave_0_logic_io_output_PADDR; + assign io_apbSlave_0_PSEL = io_apbSlave_0_logic_io_output_PSEL; + assign io_apbSlave_0_PENABLE = io_apbSlave_0_logic_io_output_PENABLE; + assign io_apbSlave_0_PWRITE = io_apbSlave_0_logic_io_output_PWRITE; + assign io_apbSlave_0_PWDATA = io_apbSlave_0_logic_io_output_PWDATA; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_clint_logic_io_bus_cmd_ready; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_clint_logic_io_bus_rsp_valid; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_clint_logic_io_bus_rsp_payload_last; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_clint_logic_io_bus_rsp_payload_fragment_opcode; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_clint_logic_io_bus_rsp_payload_fragment_data; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_clint_logic_io_bus_rsp_payload_fragment_context; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_uart_0_io_logic_io_bus_cmd_ready; + assign _zz_io_bus_rsp_ready_1 = (! _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1); + assign _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign when_PlicGateway_l21 = (! system_uart_0_io_interrupt_plic_gateway_waitCompletion); + assign when_PlicGateway_l21_1 = (! system_spi_0_io_interrupt_plic_gateway_waitCompletion); + assign system_spi_0_io_sclk_write = system_spi_0_io_logic_io_spi_sclk_write; + assign system_spi_0_io_data_0_writeEnable = system_spi_0_io_logic_io_spi_data_0_writeEnable; + assign system_spi_0_io_data_0_write = system_spi_0_io_logic_io_spi_data_0_write; + assign system_spi_0_io_data_1_writeEnable = system_spi_0_io_logic_io_spi_data_1_writeEnable; + assign system_spi_0_io_data_1_write = system_spi_0_io_logic_io_spi_data_1_write; + assign system_spi_0_io_data_2_writeEnable = system_spi_0_io_logic_io_spi_data_2_writeEnable; + assign system_spi_0_io_data_2_write = system_spi_0_io_logic_io_spi_data_2_write; + assign system_spi_0_io_data_3_writeEnable = system_spi_0_io_logic_io_spi_data_3_writeEnable; + assign system_spi_0_io_data_3_write = system_spi_0_io_logic_io_spi_data_3_write; + assign system_spi_0_io_ss = system_spi_0_io_logic_io_spi_ss; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_spi_0_io_logic_io_ctrl_cmd_ready; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_spi_0_io_logic_io_ctrl_rsp_valid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_spi_0_io_logic_io_ctrl_rsp_payload_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = io_apbSlave_0_logic_io_input_cmd_ready; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = io_apbSlave_0_logic_io_input_rsp_valid; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = io_apbSlave_0_logic_io_input_rsp_payload_last; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = io_apbSlave_0_logic_io_input_rsp_payload_fragment_data; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = io_apbSlave_0_logic_io_input_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_withoutMask_cmd_valid = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_rsp_ready = system_bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_cmd_ready = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_bmbPeripheral_bmb_withoutMask_rsp_valid = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address[15:0]; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_1; + assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_1; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1[5:0]; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + always @(*) begin + system_plic_logic_bus_readHaltTrigger = 1'b0; + if(when_PlicMapper_l122) begin + system_plic_logic_bus_readHaltTrigger = 1'b1; + end + end + + assign system_plic_logic_bus_writeHaltTrigger = 1'b0; + assign _zz_system_plic_logic_bmb_rsp_valid = (! (system_plic_logic_bus_readHaltTrigger || system_plic_logic_bus_writeHaltTrigger)); + assign system_plic_logic_bus_rsp_ready = (_zz_system_plic_logic_bus_rsp_ready && _zz_system_plic_logic_bmb_rsp_valid); + always @(*) begin + _zz_system_plic_logic_bus_rsp_ready = system_plic_logic_bmb_rsp_ready; + if(when_Stream_l368_7) begin + _zz_system_plic_logic_bus_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368_7 = (! _zz_system_plic_logic_bmb_rsp_valid_1); + assign _zz_system_plic_logic_bmb_rsp_valid_1 = _zz_system_plic_logic_bmb_rsp_valid_2; + assign system_plic_logic_bmb_rsp_valid = _zz_system_plic_logic_bmb_rsp_valid_1; + assign system_plic_logic_bmb_rsp_payload_last = _zz_system_plic_logic_bmb_rsp_payload_last; + assign system_plic_logic_bmb_rsp_payload_fragment_opcode = _zz_system_plic_logic_bmb_rsp_payload_fragment_opcode; + assign system_plic_logic_bmb_rsp_payload_fragment_data = _zz_system_plic_logic_bmb_rsp_payload_fragment_data; + assign system_plic_logic_bmb_rsp_payload_fragment_context = _zz_system_plic_logic_bmb_rsp_payload_fragment_context; + assign system_plic_logic_bus_askWrite = (system_plic_logic_bmb_cmd_valid && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b1)); + assign system_plic_logic_bus_askRead = (system_plic_logic_bmb_cmd_valid && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b0)); + assign system_plic_logic_bmb_cmd_fire = (system_plic_logic_bmb_cmd_valid && system_plic_logic_bmb_cmd_ready); + assign system_plic_logic_bus_doWrite = (system_plic_logic_bmb_cmd_fire && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b1)); + assign system_plic_logic_bmb_cmd_fire_1 = (system_plic_logic_bmb_cmd_valid && system_plic_logic_bmb_cmd_ready); + assign system_plic_logic_bus_doRead = (system_plic_logic_bmb_cmd_fire_1 && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b0)); + assign system_plic_logic_bus_rsp_valid = system_plic_logic_bmb_cmd_valid; + assign system_plic_logic_bmb_cmd_ready = system_plic_logic_bus_rsp_ready; + assign system_plic_logic_bus_rsp_payload_last = 1'b1; + assign system_plic_logic_bus_rsp_payload_fragment_opcode = 1'b0; + always @(*) begin + system_plic_logic_bus_rsp_payload_fragment_data = 32'h0; + case(system_plic_logic_bmb_cmd_payload_fragment_address) + 22'h000004 : begin + system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_uart_0_io_interrupt_plic_gateway_priority; + end + 22'h001000 : begin + system_plic_logic_bus_rsp_payload_fragment_data[1 : 1] = system_uart_0_io_interrupt_plic_gateway_ip; + system_plic_logic_bus_rsp_payload_fragment_data[4 : 4] = system_spi_0_io_interrupt_plic_gateway_ip; + end + 22'h000010 : begin + system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_spi_0_io_interrupt_plic_gateway_priority; + end + 22'h200000 : begin + system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_cores_0_externalInterrupt_plic_target_threshold; + end + 22'h200004 : begin + system_plic_logic_bus_rsp_payload_fragment_data[2 : 0] = system_cores_0_externalInterrupt_plic_target_claim; + end + 22'h002000 : begin + system_plic_logic_bus_rsp_payload_fragment_data[1 : 1] = system_cores_0_externalInterrupt_plic_target_ie_0; + system_plic_logic_bus_rsp_payload_fragment_data[4 : 4] = system_cores_0_externalInterrupt_plic_target_ie_1; + end + default : begin + end + endcase + end + + assign system_plic_logic_bus_rsp_payload_fragment_context = system_plic_logic_bmb_cmd_payload_fragment_context; + assign system_cores_0_externalInterrupt_plic_target_requests_0_priority = 2'b00; + assign system_cores_0_externalInterrupt_plic_target_requests_0_id = 3'b000; + assign system_cores_0_externalInterrupt_plic_target_requests_0_valid = 1'b1; + assign system_cores_0_externalInterrupt_plic_target_requests_1_priority = system_uart_0_io_interrupt_plic_gateway_priority; + assign system_cores_0_externalInterrupt_plic_target_requests_1_id = 3'b001; + assign system_cores_0_externalInterrupt_plic_target_requests_1_valid = (system_uart_0_io_interrupt_plic_gateway_ip && system_cores_0_externalInterrupt_plic_target_ie_0); + assign system_cores_0_externalInterrupt_plic_target_requests_2_priority = system_spi_0_io_interrupt_plic_gateway_priority; + assign system_cores_0_externalInterrupt_plic_target_requests_2_id = 3'b100; + assign system_cores_0_externalInterrupt_plic_target_requests_2_valid = (system_spi_0_io_interrupt_plic_gateway_ip && system_cores_0_externalInterrupt_plic_target_ie_1); + assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority = ((! system_cores_0_externalInterrupt_plic_target_requests_1_valid) || (system_cores_0_externalInterrupt_plic_target_requests_0_valid && (system_cores_0_externalInterrupt_plic_target_requests_1_priority <= system_cores_0_externalInterrupt_plic_target_requests_0_priority))); + assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1 = (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_priority : system_cores_0_externalInterrupt_plic_target_requests_1_priority); + assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 = (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_valid : system_cores_0_externalInterrupt_plic_target_requests_1_valid); + assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 = ((! system_cores_0_externalInterrupt_plic_target_requests_2_valid) || (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 && (system_cores_0_externalInterrupt_plic_target_requests_2_priority <= _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1))); + assign system_cores_0_externalInterrupt_plic_target_iep = (system_cores_0_externalInterrupt_plic_target_threshold < system_cores_0_externalInterrupt_plic_target_bestRequest_priority); + assign system_cores_0_externalInterrupt_plic_target_claim = (system_cores_0_externalInterrupt_plic_target_iep ? system_cores_0_externalInterrupt_plic_target_bestRequest_id : 3'b000); + assign system_uart_0_io_interrupt_plic_gateway_priority = _zz_system_uart_0_io_interrupt_plic_gateway_priority; + assign system_spi_0_io_interrupt_plic_gateway_priority = _zz_system_spi_0_io_interrupt_plic_gateway_priority; + always @(*) begin + system_plic_logic_bridge_claim_valid = 1'b0; + case(system_plic_logic_bmb_cmd_payload_fragment_address) + 22'h200004 : begin + if(system_plic_logic_bus_doRead) begin + system_plic_logic_bridge_claim_valid = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + system_plic_logic_bridge_claim_payload = 3'bxxx; + case(system_plic_logic_bmb_cmd_payload_fragment_address) + 22'h200004 : begin + if(system_plic_logic_bus_doRead) begin + system_plic_logic_bridge_claim_payload = system_cores_0_externalInterrupt_plic_target_claim; + end + end + default : begin + end + endcase + end + + always @(*) begin + system_plic_logic_bridge_completion_valid = 1'b0; + if(system_plic_logic_bridge_targetMapping_0_targetCompletion_valid) begin + system_plic_logic_bridge_completion_valid = 1'b1; + end + end + + always @(*) begin + system_plic_logic_bridge_completion_payload = 3'bxxx; + if(system_plic_logic_bridge_targetMapping_0_targetCompletion_valid) begin + system_plic_logic_bridge_completion_payload = system_plic_logic_bridge_targetMapping_0_targetCompletion_payload; + end + end + + always @(*) begin + system_plic_logic_bridge_coherencyStall_willIncrement = 1'b0; + if(when_PlicMapper_l122) begin + system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; + end + if(when_BmbSlaveFactory_l71) begin + if(system_plic_logic_bus_askWrite) begin + system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; + end + if(system_plic_logic_bus_askRead) begin + system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; + end + end + end + + assign system_plic_logic_bridge_coherencyStall_willClear = 1'b0; + assign system_plic_logic_bridge_coherencyStall_willOverflowIfInc = (system_plic_logic_bridge_coherencyStall_value == 1'b1); + assign system_plic_logic_bridge_coherencyStall_willOverflow = (system_plic_logic_bridge_coherencyStall_willOverflowIfInc && system_plic_logic_bridge_coherencyStall_willIncrement); + always @(*) begin + system_plic_logic_bridge_coherencyStall_valueNext = (system_plic_logic_bridge_coherencyStall_value + system_plic_logic_bridge_coherencyStall_willIncrement); + if(system_plic_logic_bridge_coherencyStall_willClear) begin + system_plic_logic_bridge_coherencyStall_valueNext = 1'b0; + end + end + + assign when_PlicMapper_l122 = (system_plic_logic_bridge_coherencyStall_value != 1'b0); + assign system_cores_0_externalInterrupt_plic_target_threshold = _zz_system_cores_0_externalInterrupt_plic_target_threshold; + always @(*) begin + system_plic_logic_bridge_targetMapping_0_targetCompletion_valid = 1'b0; + case(system_plic_logic_bmb_cmd_payload_fragment_address) + 22'h200004 : begin + if(system_plic_logic_bus_doWrite) begin + system_plic_logic_bridge_targetMapping_0_targetCompletion_valid = 1'b1; + end + end + default : begin + end + endcase + end + + assign system_cores_0_externalInterrupt_plic_target_ie_0 = _zz_system_cores_0_externalInterrupt_plic_target_ie_0; + assign system_cores_0_externalInterrupt_plic_target_ie_1 = _zz_system_cores_0_externalInterrupt_plic_target_ie_1; + assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_2; + assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_2; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_2; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2[11:0]; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_3; + assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_3; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_3; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3[15:0]; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_plic_logic_bmb_cmd_valid = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_plic_logic_bmb_cmd_ready; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_plic_logic_bmb_rsp_valid; + assign system_plic_logic_bmb_rsp_ready = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_plic_logic_bmb_cmd_payload_last = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_plic_logic_bmb_rsp_payload_last; + assign system_plic_logic_bmb_cmd_payload_fragment_opcode = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_plic_logic_bmb_cmd_payload_fragment_address = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_plic_logic_bmb_cmd_payload_fragment_length = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_plic_logic_bmb_cmd_payload_fragment_data = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_plic_logic_bmb_cmd_payload_fragment_context = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_plic_logic_bmb_rsp_payload_fragment_opcode; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_plic_logic_bmb_rsp_payload_fragment_data; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_plic_logic_bmb_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_4; + assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_4; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_4; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4[21:0]; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_plic_logic_bridge_targetMapping_0_targetCompletion_payload = system_plic_logic_bmb_cmd_payload_fragment_data[2 : 0]; + assign when_BmbSlaveFactory_l71 = 1'b1; + always @(posedge io_systemClk) begin + if(when_ClockDomainGenerator_l77) begin + debugCd_logic_holdingLogic_resetCounter <= (debugCd_logic_holdingLogic_resetCounter + 12'h001); + end + if(debugCd_logic_inputResetTrigger) begin + debugCd_logic_holdingLogic_resetCounter <= 12'h0; + end + debugCd_logic_outputReset <= debugCd_logic_outputResetUnbuffered; + end + + always @(posedge io_systemClk) begin + if(when_ClockDomainGenerator_l77_1) begin + systemCd_logic_holdingLogic_resetCounter <= (systemCd_logic_holdingLogic_resetCounter + 6'h01); + end + if(systemCd_logic_inputResetTrigger) begin + systemCd_logic_holdingLogic_resetCounter <= 6'h0; + end + systemCd_logic_outputReset <= systemCd_logic_outputResetUnbuffered; + end + + always @(posedge io_systemClk) begin + io_systemReset <= systemCd_logic_outputReset; + if(_zz_system_cores_0_iBus_connector_decoder_rsp_ready) begin + _zz_system_cores_0_iBus_rsp_payload_last <= system_cores_0_iBus_connector_decoder_rsp_payload_last; + _zz_system_cores_0_iBus_rsp_payload_fragment_opcode <= system_cores_0_iBus_connector_decoder_rsp_payload_fragment_opcode; + _zz_system_cores_0_iBus_rsp_payload_fragment_data <= system_cores_0_iBus_connector_decoder_rsp_payload_fragment_data; + end + if(system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready) begin + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_last <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_last; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_opcode <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_opcode; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_address <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_address; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_length <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_data <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_data; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_mask <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_mask; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_context <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_context; + end + if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_mask <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_last <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_last; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_opcode <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_opcode; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_address <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_address; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_length <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_length; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_data <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_data; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_mask <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_mask; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_context <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_context; + end + if(_zz_io_input_rsp_ready) begin + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_last; + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_opcode; + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_data; + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_context; + end + if(system_fabric_iBus_bmb_cmd_ready) begin + system_fabric_iBus_bmb_cmd_rData_last <= system_fabric_iBus_bmb_cmd_payload_last; + system_fabric_iBus_bmb_cmd_rData_fragment_opcode <= system_fabric_iBus_bmb_cmd_payload_fragment_opcode; + system_fabric_iBus_bmb_cmd_rData_fragment_address <= system_fabric_iBus_bmb_cmd_payload_fragment_address; + system_fabric_iBus_bmb_cmd_rData_fragment_length <= system_fabric_iBus_bmb_cmd_payload_fragment_length; + end + if(system_bridge_bmb_cmd_ready) begin + system_bridge_bmb_cmd_rData_last <= system_bridge_bmb_cmd_payload_last; + system_bridge_bmb_cmd_rData_fragment_source <= system_bridge_bmb_cmd_payload_fragment_source; + system_bridge_bmb_cmd_rData_fragment_opcode <= system_bridge_bmb_cmd_payload_fragment_opcode; + system_bridge_bmb_cmd_rData_fragment_address <= system_bridge_bmb_cmd_payload_fragment_address; + system_bridge_bmb_cmd_rData_fragment_length <= system_bridge_bmb_cmd_payload_fragment_length; + system_bridge_bmb_cmd_rData_fragment_data <= system_bridge_bmb_cmd_payload_fragment_data; + system_bridge_bmb_cmd_rData_fragment_mask <= system_bridge_bmb_cmd_payload_fragment_mask; + system_bridge_bmb_cmd_rData_fragment_context <= system_bridge_bmb_cmd_payload_fragment_context; + end + if(system_bridge_bmb_cmd_s2mPipe_ready) begin + system_bridge_bmb_cmd_s2mPipe_rData_last <= system_bridge_bmb_cmd_s2mPipe_payload_last; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_source <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_source; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_opcode <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_opcode; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_address <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_address; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_length <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_length; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_data <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_data; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_mask <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_mask; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_context <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_context; + end + if(_zz_io_bus_rsp_ready) begin + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_ramA_logic_io_bus_rsp_payload_last; + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_ramA_logic_io_bus_rsp_payload_fragment_opcode; + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_ramA_logic_io_bus_rsp_payload_fragment_data; + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_ramA_logic_io_bus_rsp_payload_fragment_context; + end + if(_zz_io_input_rsp_ready_1) begin + _zz_system_bmbPeripheral_bmb_rsp_payload_last <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_last; + _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_opcode <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode; + _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_data <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data; + _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_context <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context; + end + _zz_timerInterrupt <= system_clint_logic_io_timerInterrupt[0]; + _zz_softwareInterrupt <= system_clint_logic_io_softwareInterrupt[0]; + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + if(_zz_io_bus_rsp_ready_1) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_uart_0_io_logic_io_bus_rsp_payload_last; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_data; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_context; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + if(_zz_system_plic_logic_bus_rsp_ready) begin + _zz_system_plic_logic_bmb_rsp_payload_last <= system_plic_logic_bus_rsp_payload_last; + _zz_system_plic_logic_bmb_rsp_payload_fragment_opcode <= system_plic_logic_bus_rsp_payload_fragment_opcode; + _zz_system_plic_logic_bmb_rsp_payload_fragment_data <= system_plic_logic_bus_rsp_payload_fragment_data; + _zz_system_plic_logic_bmb_rsp_payload_fragment_context <= system_plic_logic_bus_rsp_payload_fragment_context; + end + system_cores_0_externalInterrupt_plic_target_bestRequest_priority <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1 : system_cores_0_externalInterrupt_plic_target_requests_2_priority); + system_cores_0_externalInterrupt_plic_target_bestRequest_id <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_id : system_cores_0_externalInterrupt_plic_target_requests_1_id) : system_cores_0_externalInterrupt_plic_target_requests_2_id); + system_cores_0_externalInterrupt_plic_target_bestRequest_valid <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 : system_cores_0_externalInterrupt_plic_target_requests_2_valid); + system_cores_0_externalInterrupt_plic_target_iep_regNext <= system_cores_0_externalInterrupt_plic_target_iep; + end + + always @(posedge io_systemClk) begin + system_cores_0_debugReset <= system_cores_0_logic_cpu_debug_resetOut; + end + + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + _zz_system_cores_0_iBus_rsp_valid_1 <= 1'b0; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid <= 1'b0; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid <= 1'b0; + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + system_fabric_iBus_bmb_cmd_rValid <= 1'b0; + system_bridge_bmb_cmd_rValid <= 1'b0; + system_bridge_bmb_cmd_s2mPipe_rValid <= 1'b0; + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b0; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + system_uart_0_io_interrupt_plic_gateway_ip <= 1'b0; + system_uart_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; + system_spi_0_io_interrupt_plic_gateway_ip <= 1'b0; + system_spi_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + _zz_system_plic_logic_bmb_rsp_valid_2 <= 1'b0; + _zz_system_uart_0_io_interrupt_plic_gateway_priority <= 2'b00; + _zz_system_spi_0_io_interrupt_plic_gateway_priority <= 2'b00; + system_plic_logic_bridge_coherencyStall_value <= 1'b0; + _zz_system_cores_0_externalInterrupt_plic_target_threshold <= 2'b00; + _zz_system_cores_0_externalInterrupt_plic_target_ie_0 <= 1'b0; + _zz_system_cores_0_externalInterrupt_plic_target_ie_1 <= 1'b0; + end else begin + if(_zz_system_cores_0_iBus_connector_decoder_rsp_ready) begin + _zz_system_cores_0_iBus_rsp_valid_1 <= system_cores_0_iBus_connector_decoder_rsp_valid; + end + if(system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready) begin + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_valid; + end + if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_valid; + end + if(_zz_io_input_rsp_ready) begin + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= system_fabric_exclusiveMonitor_logic_io_input_rsp_valid; + end + if(system_fabric_iBus_bmb_cmd_ready) begin + system_fabric_iBus_bmb_cmd_rValid <= system_fabric_iBus_bmb_cmd_valid; + end + if(system_bridge_bmb_cmd_valid) begin + system_bridge_bmb_cmd_rValid <= 1'b1; + end + if(system_bridge_bmb_cmd_s2mPipe_ready) begin + system_bridge_bmb_cmd_rValid <= 1'b0; + end + if(system_bridge_bmb_cmd_s2mPipe_ready) begin + system_bridge_bmb_cmd_s2mPipe_rValid <= system_bridge_bmb_cmd_s2mPipe_valid; + end + if(_zz_io_bus_rsp_ready) begin + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= system_ramA_logic_io_bus_rsp_valid; + end + if(system_bmbPeripheral_bmb_decoder_io_input_rsp_valid) begin + _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b1; + end + if((_zz_system_bmbPeripheral_bmb_rsp_valid && system_bmbPeripheral_bmb_rsp_ready)) begin + _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b0; + end + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + if(system_uart_0_io_logic_io_bus_rsp_valid) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b1; + end + if((_zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready)) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + end + if(when_PlicGateway_l21) begin + system_uart_0_io_interrupt_plic_gateway_ip <= system_uart_0_io_logic_io_interrupt; + system_uart_0_io_interrupt_plic_gateway_waitCompletion <= system_uart_0_io_logic_io_interrupt; + end + if(when_PlicGateway_l21_1) begin + system_spi_0_io_interrupt_plic_gateway_ip <= system_spi_0_io_logic_io_interrupt; + system_spi_0_io_interrupt_plic_gateway_waitCompletion <= system_spi_0_io_logic_io_interrupt; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + if(_zz_system_plic_logic_bus_rsp_ready) begin + _zz_system_plic_logic_bmb_rsp_valid_2 <= (system_plic_logic_bus_rsp_valid && _zz_system_plic_logic_bmb_rsp_valid); + end + if(system_plic_logic_bridge_claim_valid) begin + case(system_plic_logic_bridge_claim_payload) + 3'b001 : begin + system_uart_0_io_interrupt_plic_gateway_ip <= 1'b0; + end + 3'b100 : begin + system_spi_0_io_interrupt_plic_gateway_ip <= 1'b0; + end + default : begin + end + endcase + end + if(system_plic_logic_bridge_completion_valid) begin + case(system_plic_logic_bridge_completion_payload) + 3'b001 : begin + system_uart_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; + end + 3'b100 : begin + system_spi_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; + end + default : begin + end + endcase + end + system_plic_logic_bridge_coherencyStall_value <= system_plic_logic_bridge_coherencyStall_valueNext; + case(system_plic_logic_bmb_cmd_payload_fragment_address) + 22'h000004 : begin + if(system_plic_logic_bus_doWrite) begin + _zz_system_uart_0_io_interrupt_plic_gateway_priority <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; + end + end + 22'h000010 : begin + if(system_plic_logic_bus_doWrite) begin + _zz_system_spi_0_io_interrupt_plic_gateway_priority <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; + end + end + 22'h200000 : begin + if(system_plic_logic_bus_doWrite) begin + _zz_system_cores_0_externalInterrupt_plic_target_threshold <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; + end + end + 22'h002000 : begin + if(system_plic_logic_bus_doWrite) begin + _zz_system_cores_0_externalInterrupt_plic_target_ie_0 <= system_plic_logic_bmb_cmd_payload_fragment_data[1]; + _zz_system_cores_0_externalInterrupt_plic_target_ie_1 <= system_plic_logic_bmb_cmd_payload_fragment_data[4]; + end + end + default : begin + end + endcase + end + end + + always @(posedge io_systemClk) begin + if(debugCd_logic_outputReset) begin + system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext <= 1'b0; + end else begin + system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext <= system_cores_0_logic_cpu_debug_bus_cmd_fire; + end + end + + +endmodule + +module BmbToApb3Bridge_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [15:0] io_input_cmd_payload_fragment_address, + input [1:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_context, + output io_input_rsp_valid, + input io_input_rsp_ready, + output io_input_rsp_payload_last, + output [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output [3:0] io_input_rsp_payload_fragment_context, + output [15:0] io_output_PADDR, + output [0:0] io_output_PSEL, + output io_output_PENABLE, + input io_output_PREADY, + output io_output_PWRITE, + output [31:0] io_output_PWDATA, + input [31:0] io_output_PRDATA, + input io_output_PSLVERROR, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire bmbBuffer_cmd_valid; + reg bmbBuffer_cmd_ready; + wire bmbBuffer_cmd_payload_last; + wire [0:0] bmbBuffer_cmd_payload_fragment_opcode; + wire [15:0] bmbBuffer_cmd_payload_fragment_address; + wire [1:0] bmbBuffer_cmd_payload_fragment_length; + wire [31:0] bmbBuffer_cmd_payload_fragment_data; + wire [3:0] bmbBuffer_cmd_payload_fragment_context; + reg bmbBuffer_rsp_valid; + reg bmbBuffer_rsp_ready; + wire bmbBuffer_rsp_payload_last; + reg [0:0] bmbBuffer_rsp_payload_fragment_opcode; + wire [31:0] bmbBuffer_rsp_payload_fragment_data; + wire [3:0] bmbBuffer_rsp_payload_fragment_context; + wire io_input_rsp_isStall; + wire _zz_io_input_cmd_ready; + wire bmbBuffer_rsp_m2sPipe_valid; + wire bmbBuffer_rsp_m2sPipe_ready; + wire bmbBuffer_rsp_m2sPipe_payload_last; + wire [0:0] bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; + wire [31:0] bmbBuffer_rsp_m2sPipe_payload_fragment_data; + wire [3:0] bmbBuffer_rsp_m2sPipe_payload_fragment_context; + reg bmbBuffer_rsp_rValid; + reg bmbBuffer_rsp_rData_last; + reg [0:0] bmbBuffer_rsp_rData_fragment_opcode; + reg [31:0] bmbBuffer_rsp_rData_fragment_data; + reg [3:0] bmbBuffer_rsp_rData_fragment_context; + wire when_Stream_l368; + reg state; + wire when_BmbToApb3Bridge_l46; + + assign io_input_rsp_isStall = (io_input_rsp_valid && (! io_input_rsp_ready)); + assign _zz_io_input_cmd_ready = (! io_input_rsp_isStall); + assign io_input_cmd_ready = (bmbBuffer_cmd_ready && _zz_io_input_cmd_ready); + assign bmbBuffer_cmd_valid = (io_input_cmd_valid && _zz_io_input_cmd_ready); + assign bmbBuffer_cmd_payload_last = io_input_cmd_payload_last; + assign bmbBuffer_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign bmbBuffer_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign bmbBuffer_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign bmbBuffer_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign bmbBuffer_cmd_payload_fragment_context = io_input_cmd_payload_fragment_context; + always @(*) begin + bmbBuffer_rsp_ready = bmbBuffer_rsp_m2sPipe_ready; + if(when_Stream_l368) begin + bmbBuffer_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! bmbBuffer_rsp_m2sPipe_valid); + assign bmbBuffer_rsp_m2sPipe_valid = bmbBuffer_rsp_rValid; + assign bmbBuffer_rsp_m2sPipe_payload_last = bmbBuffer_rsp_rData_last; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_opcode = bmbBuffer_rsp_rData_fragment_opcode; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_data = bmbBuffer_rsp_rData_fragment_data; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_context = bmbBuffer_rsp_rData_fragment_context; + assign io_input_rsp_valid = bmbBuffer_rsp_m2sPipe_valid; + assign bmbBuffer_rsp_m2sPipe_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = bmbBuffer_rsp_m2sPipe_payload_last; + assign io_input_rsp_payload_fragment_opcode = bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = bmbBuffer_rsp_m2sPipe_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = bmbBuffer_rsp_m2sPipe_payload_fragment_context; + always @(*) begin + bmbBuffer_cmd_ready = 1'b0; + if(!when_BmbToApb3Bridge_l46) begin + if(io_output_PREADY) begin + bmbBuffer_cmd_ready = 1'b1; + end + end + end + + assign io_output_PSEL[0] = bmbBuffer_cmd_valid; + assign io_output_PENABLE = state; + assign io_output_PWRITE = (bmbBuffer_cmd_payload_fragment_opcode == 1'b1); + assign io_output_PADDR = bmbBuffer_cmd_payload_fragment_address; + assign io_output_PWDATA = bmbBuffer_cmd_payload_fragment_data; + always @(*) begin + bmbBuffer_rsp_valid = 1'b0; + if(!when_BmbToApb3Bridge_l46) begin + if(io_output_PREADY) begin + bmbBuffer_rsp_valid = 1'b1; + end + end + end + + assign bmbBuffer_rsp_payload_fragment_data = io_output_PRDATA; + assign when_BmbToApb3Bridge_l46 = (! state); + assign bmbBuffer_rsp_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign bmbBuffer_rsp_payload_last = 1'b1; + always @(*) begin + bmbBuffer_rsp_payload_fragment_opcode = 1'b0; + if(io_output_PSLVERROR) begin + bmbBuffer_rsp_payload_fragment_opcode = 1'b1; + end + end + + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + bmbBuffer_rsp_rValid <= 1'b0; + state <= 1'b0; + end else begin + if(bmbBuffer_rsp_ready) begin + bmbBuffer_rsp_rValid <= bmbBuffer_rsp_valid; + end + if(when_BmbToApb3Bridge_l46) begin + state <= bmbBuffer_cmd_valid; + end else begin + if(io_output_PREADY) begin + state <= 1'b0; + end + end + end + end + + always @(posedge io_systemClk) begin + if(bmbBuffer_rsp_ready) begin + bmbBuffer_rsp_rData_last <= bmbBuffer_rsp_payload_last; + bmbBuffer_rsp_rData_fragment_opcode <= bmbBuffer_rsp_payload_fragment_opcode; + bmbBuffer_rsp_rData_fragment_data <= bmbBuffer_rsp_payload_fragment_data; + bmbBuffer_rsp_rData_fragment_context <= bmbBuffer_rsp_payload_fragment_context; + end + end + + +endmodule + +module BmbSpiXdrMasterCtrl_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_ctrl_cmd_valid, + output io_ctrl_cmd_ready, + input io_ctrl_cmd_payload_last, + input [0:0] io_ctrl_cmd_payload_fragment_opcode, + input [11:0] io_ctrl_cmd_payload_fragment_address, + input [1:0] io_ctrl_cmd_payload_fragment_length, + input [31:0] io_ctrl_cmd_payload_fragment_data, + input [3:0] io_ctrl_cmd_payload_fragment_context, + output io_ctrl_rsp_valid, + input io_ctrl_rsp_ready, + output io_ctrl_rsp_payload_last, + output [0:0] io_ctrl_rsp_payload_fragment_opcode, + output [31:0] io_ctrl_rsp_payload_fragment_data, + output [3:0] io_ctrl_rsp_payload_fragment_context, + output [0:0] io_spi_sclk_write, + output io_spi_data_0_writeEnable, + input [0:0] io_spi_data_0_read, + output [0:0] io_spi_data_0_write, + output io_spi_data_1_writeEnable, + input [0:0] io_spi_data_1_read, + output [0:0] io_spi_data_1_write, + output io_spi_data_2_writeEnable, + input [0:0] io_spi_data_2_read, + output [0:0] io_spi_data_2_write, + output io_spi_data_3_writeEnable, + input [0:0] io_spi_data_3_read, + output [0:0] io_spi_data_3_write, + output [0:0] io_spi_ss, + output io_interrupt, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready; + wire ctrl_io_rsp_queueWithOccupancy_io_pop_ready; + wire ctrl_io_cmd_ready; + wire ctrl_io_rsp_valid; + wire [7:0] ctrl_io_rsp_payload_data; + wire [0:0] ctrl_io_spi_sclk_write; + wire [0:0] ctrl_io_spi_ss; + wire [0:0] ctrl_io_spi_data_0_write; + wire ctrl_io_spi_data_0_writeEnable; + wire [0:0] ctrl_io_spi_data_1_write; + wire ctrl_io_spi_data_1_writeEnable; + wire [0:0] ctrl_io_spi_data_2_write; + wire ctrl_io_spi_data_2_writeEnable; + wire [0:0] ctrl_io_spi_data_3_write; + wire ctrl_io_spi_data_3_writeEnable; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; + wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy; + wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; + wire ctrl_io_rsp_queueWithOccupancy_io_push_ready; + wire ctrl_io_rsp_queueWithOccupancy_io_pop_valid; + wire [7:0] ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_occupancy; + wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_availability; + wire factory_readHaltTrigger; + wire factory_writeHaltTrigger; + wire factory_rsp_valid; + wire factory_rsp_ready; + wire factory_rsp_payload_last; + wire [0:0] factory_rsp_payload_fragment_opcode; + reg [31:0] factory_rsp_payload_fragment_data; + wire [3:0] factory_rsp_payload_fragment_context; + wire _zz_io_ctrl_rsp_valid; + reg _zz_factory_rsp_ready; + wire _zz_io_ctrl_rsp_valid_1; + reg _zz_io_ctrl_rsp_valid_2; + reg _zz_io_ctrl_rsp_payload_last; + reg [0:0] _zz_io_ctrl_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_ctrl_rsp_payload_fragment_data; + reg [3:0] _zz_io_ctrl_rsp_payload_fragment_context; + wire when_Stream_l368; + wire factory_askWrite; + wire factory_askRead; + wire io_ctrl_cmd_fire; + wire factory_doWrite; + wire io_ctrl_cmd_fire_1; + wire factory_doRead; + wire [31:0] mapping_cmdLogic_writeData; + reg mapping_cmdLogic_doRegular; + reg mapping_cmdLogic_doWriteLarge; + reg mapping_cmdLogic_doReadWriteLarge; + wire mapping_cmdLogic_streamUnbuffered_valid; + wire mapping_cmdLogic_streamUnbuffered_ready; + wire mapping_cmdLogic_streamUnbuffered_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_payload_read; + wire mapping_cmdLogic_streamUnbuffered_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_payload_data; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write; + reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; + reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; + wire when_Stream_l368_1; + wire ctrl_io_rsp_toStream_valid; + wire ctrl_io_rsp_toStream_ready; + wire [7:0] ctrl_io_rsp_toStream_payload_data; + reg _zz_io_pop_ready; + reg _zz_io_pop_ready_1; + reg mapping_interruptCtrl_cmdIntEnable; + reg mapping_interruptCtrl_rspIntEnable; + wire mapping_interruptCtrl_cmdInt; + wire mapping_interruptCtrl_rspInt; + wire mapping_interruptCtrl_interrupt; + reg _zz_io_config_kind_cpol; + reg _zz_io_config_kind_cpha; + reg [1:0] _zz_io_config_mod; + reg [11:0] _zz_io_config_sclkToogle; + reg [11:0] _zz_io_config_ss_setup; + reg [11:0] _zz_io_config_ss_hold; + reg [11:0] _zz_io_config_ss_disable; + reg [0:0] _zz_io_config_ss_activeHigh; + wire [1:0] _zz_io_config_kind_cpol_1; + + TopLevel_b62b14ffe6bb44e5a817b8d08e286c6b ctrl ( + .io_config_kind_cpol (_zz_io_config_kind_cpol ), //i + .io_config_kind_cpha (_zz_io_config_kind_cpha ), //i + .io_config_sclkToogle (_zz_io_config_sclkToogle[11:0] ), //i + .io_config_mod (_zz_io_config_mod[1:0] ), //i + .io_config_ss_activeHigh (_zz_io_config_ss_activeHigh ), //i + .io_config_ss_setup (_zz_io_config_ss_setup[11:0] ), //i + .io_config_ss_hold (_zz_io_config_ss_hold[11:0] ), //i + .io_config_ss_disable (_zz_io_config_ss_disable[11:0] ), //i + .io_cmd_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid ), //i + .io_cmd_ready (ctrl_io_cmd_ready ), //o + .io_cmd_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind ), //i + .io_cmd_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read ), //i + .io_cmd_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write ), //i + .io_cmd_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data[7:0]), //i + .io_rsp_valid (ctrl_io_rsp_valid ), //o + .io_rsp_payload_data (ctrl_io_rsp_payload_data[7:0] ), //o + .io_spi_sclk_write (ctrl_io_spi_sclk_write ), //o + .io_spi_data_0_writeEnable (ctrl_io_spi_data_0_writeEnable ), //o + .io_spi_data_0_read (io_spi_data_0_read ), //i + .io_spi_data_0_write (ctrl_io_spi_data_0_write ), //o + .io_spi_data_1_writeEnable (ctrl_io_spi_data_1_writeEnable ), //o + .io_spi_data_1_read (io_spi_data_1_read ), //i + .io_spi_data_1_write (ctrl_io_spi_data_1_write ), //o + .io_spi_data_2_writeEnable (ctrl_io_spi_data_2_writeEnable ), //o + .io_spi_data_2_read (io_spi_data_2_read ), //i + .io_spi_data_2_write (ctrl_io_spi_data_2_write ), //o + .io_spi_data_3_writeEnable (ctrl_io_spi_data_3_writeEnable ), //o + .io_spi_data_3_read (io_spi_data_3_read ), //i + .io_spi_data_3_write (ctrl_io_spi_data_3_write ), //o + .io_spi_ss (ctrl_io_spi_ss ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + StreamFifo_2_b62b14ffe6bb44e5a817b8d08e286c6b mapping_cmdLogic_streamUnbuffered_queueWithAvailability ( + .io_push_valid (mapping_cmdLogic_streamUnbuffered_valid ), //i + .io_push_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready ), //o + .io_push_payload_kind (mapping_cmdLogic_streamUnbuffered_payload_kind ), //i + .io_push_payload_read (mapping_cmdLogic_streamUnbuffered_payload_read ), //i + .io_push_payload_write (mapping_cmdLogic_streamUnbuffered_payload_write ), //i + .io_push_payload_data (mapping_cmdLogic_streamUnbuffered_payload_data[7:0] ), //i + .io_pop_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid ), //o + .io_pop_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready ), //i + .io_pop_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind ), //o + .io_pop_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read ), //o + .io_pop_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write ), //o + .io_pop_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data[7:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy[8:0] ), //o + .io_availability (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability[8:0] ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + StreamFifo_3_b62b14ffe6bb44e5a817b8d08e286c6b ctrl_io_rsp_queueWithOccupancy ( + .io_push_valid (ctrl_io_rsp_toStream_valid ), //i + .io_push_ready (ctrl_io_rsp_queueWithOccupancy_io_push_ready ), //o + .io_push_payload_data (ctrl_io_rsp_toStream_payload_data[7:0] ), //i + .io_pop_valid (ctrl_io_rsp_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (ctrl_io_rsp_queueWithOccupancy_io_pop_ready ), //i + .io_pop_payload_data (ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data[7:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (ctrl_io_rsp_queueWithOccupancy_io_occupancy[8:0] ), //o + .io_availability (ctrl_io_rsp_queueWithOccupancy_io_availability[8:0] ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + assign factory_readHaltTrigger = 1'b0; + assign factory_writeHaltTrigger = 1'b0; + assign _zz_io_ctrl_rsp_valid = (! (factory_readHaltTrigger || factory_writeHaltTrigger)); + assign factory_rsp_ready = (_zz_factory_rsp_ready && _zz_io_ctrl_rsp_valid); + always @(*) begin + _zz_factory_rsp_ready = io_ctrl_rsp_ready; + if(when_Stream_l368) begin + _zz_factory_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! _zz_io_ctrl_rsp_valid_1); + assign _zz_io_ctrl_rsp_valid_1 = _zz_io_ctrl_rsp_valid_2; + assign io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid_1; + assign io_ctrl_rsp_payload_last = _zz_io_ctrl_rsp_payload_last; + assign io_ctrl_rsp_payload_fragment_opcode = _zz_io_ctrl_rsp_payload_fragment_opcode; + assign io_ctrl_rsp_payload_fragment_data = _zz_io_ctrl_rsp_payload_fragment_data; + assign io_ctrl_rsp_payload_fragment_context = _zz_io_ctrl_rsp_payload_fragment_context; + assign factory_askWrite = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign factory_askRead = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign io_ctrl_cmd_fire = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); + assign factory_doWrite = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign io_ctrl_cmd_fire_1 = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); + assign factory_doRead = (io_ctrl_cmd_fire_1 && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign factory_rsp_valid = io_ctrl_cmd_valid; + assign io_ctrl_cmd_ready = factory_rsp_ready; + assign factory_rsp_payload_last = 1'b1; + assign factory_rsp_payload_fragment_opcode = 1'b0; + always @(*) begin + factory_rsp_payload_fragment_data = 32'h0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + factory_rsp_payload_fragment_data[31 : 31] = (! ctrl_io_rsp_queueWithOccupancy_io_pop_valid); + factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + end + 12'h004 : begin + factory_rsp_payload_fragment_data[8 : 0] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; + factory_rsp_payload_fragment_data[24 : 16] = ctrl_io_rsp_queueWithOccupancy_io_occupancy; + end + 12'h00c : begin + factory_rsp_payload_fragment_data[16 : 16] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; + factory_rsp_payload_fragment_data[0 : 0] = mapping_interruptCtrl_cmdIntEnable; + factory_rsp_payload_fragment_data[1 : 1] = mapping_interruptCtrl_rspIntEnable; + factory_rsp_payload_fragment_data[8 : 8] = mapping_interruptCtrl_cmdInt; + factory_rsp_payload_fragment_data[9 : 9] = mapping_interruptCtrl_rspInt; + end + 12'h058 : begin + factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + end + default : begin + end + endcase + end + + assign factory_rsp_payload_fragment_context = io_ctrl_cmd_payload_fragment_context; + always @(*) begin + mapping_cmdLogic_doRegular = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doRegular = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + mapping_cmdLogic_doWriteLarge = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h050 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doWriteLarge = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + mapping_cmdLogic_doReadWriteLarge = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h054 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doReadWriteLarge = 1'b1; + end + end + default : begin + end + endcase + end + + assign mapping_cmdLogic_streamUnbuffered_valid = ((mapping_cmdLogic_doRegular || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_write = (((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[8]) || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_read = ((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[9]) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_kind = (mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[11]); + assign mapping_cmdLogic_streamUnbuffered_payload_data = mapping_cmdLogic_writeData[7:0]; + assign mapping_cmdLogic_streamUnbuffered_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready = (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid || mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data); + always @(*) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; + if(when_Stream_l368_1) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l368_1 = (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready = ctrl_io_cmd_ready; + assign ctrl_io_rsp_toStream_valid = ctrl_io_rsp_valid; + assign ctrl_io_rsp_toStream_payload_data = ctrl_io_rsp_payload_data; + assign ctrl_io_rsp_toStream_ready = ctrl_io_rsp_queueWithOccupancy_io_push_ready; + always @(*) begin + _zz_io_pop_ready = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + if(factory_doRead) begin + _zz_io_pop_ready = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + _zz_io_pop_ready_1 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h058 : begin + if(factory_doRead) begin + _zz_io_pop_ready_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign ctrl_io_rsp_queueWithOccupancy_io_pop_ready = (_zz_io_pop_ready || _zz_io_pop_ready_1); + assign mapping_interruptCtrl_cmdInt = (mapping_interruptCtrl_cmdIntEnable && (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid)); + assign mapping_interruptCtrl_rspInt = (mapping_interruptCtrl_rspIntEnable && ctrl_io_rsp_queueWithOccupancy_io_pop_valid); + assign mapping_interruptCtrl_interrupt = (mapping_interruptCtrl_rspInt || mapping_interruptCtrl_cmdInt); + assign io_spi_sclk_write = ctrl_io_spi_sclk_write; + assign io_spi_data_0_writeEnable = ctrl_io_spi_data_0_writeEnable; + assign io_spi_data_0_write = ctrl_io_spi_data_0_write; + assign io_spi_data_1_writeEnable = ctrl_io_spi_data_1_writeEnable; + assign io_spi_data_1_write = ctrl_io_spi_data_1_write; + assign io_spi_data_2_writeEnable = ctrl_io_spi_data_2_writeEnable; + assign io_spi_data_2_write = ctrl_io_spi_data_2_write; + assign io_spi_data_3_writeEnable = ctrl_io_spi_data_3_writeEnable; + assign io_spi_data_3_write = ctrl_io_spi_data_3_write; + assign io_spi_ss = ctrl_io_spi_ss; + assign io_interrupt = mapping_interruptCtrl_interrupt; + assign mapping_cmdLogic_writeData = io_ctrl_cmd_payload_fragment_data[31 : 0]; + assign _zz_io_config_kind_cpol_1 = io_ctrl_cmd_payload_fragment_data[1 : 0]; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + _zz_io_ctrl_rsp_valid_2 <= 1'b0; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b0; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= 1'b0; + mapping_interruptCtrl_cmdIntEnable <= 1'b0; + mapping_interruptCtrl_rspIntEnable <= 1'b0; + _zz_io_config_ss_activeHigh <= 1'b0; + end else begin + if(_zz_factory_rsp_ready) begin + _zz_io_ctrl_rsp_valid_2 <= (factory_rsp_valid && _zz_io_ctrl_rsp_valid); + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b1; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b0; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; + end + case(io_ctrl_cmd_payload_fragment_address) + 12'h00c : begin + if(factory_doWrite) begin + mapping_interruptCtrl_cmdIntEnable <= io_ctrl_cmd_payload_fragment_data[0]; + mapping_interruptCtrl_rspIntEnable <= io_ctrl_cmd_payload_fragment_data[1]; + end + end + 12'h030 : begin + if(factory_doWrite) begin + _zz_io_config_ss_activeHigh <= io_ctrl_cmd_payload_fragment_data[0 : 0]; + end + end + default : begin + end + endcase + end + end + + always @(posedge io_systemClk) begin + if(_zz_factory_rsp_ready) begin + _zz_io_ctrl_rsp_payload_last <= factory_rsp_payload_last; + _zz_io_ctrl_rsp_payload_fragment_opcode <= factory_rsp_payload_fragment_opcode; + _zz_io_ctrl_rsp_payload_fragment_data <= factory_rsp_payload_fragment_data; + _zz_io_ctrl_rsp_payload_fragment_context <= factory_rsp_payload_fragment_context; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; + end + case(io_ctrl_cmd_payload_fragment_address) + 12'h008 : begin + if(factory_doWrite) begin + _zz_io_config_kind_cpol <= _zz_io_config_kind_cpol_1[0]; + _zz_io_config_kind_cpha <= _zz_io_config_kind_cpol_1[1]; + _zz_io_config_mod <= io_ctrl_cmd_payload_fragment_data[5 : 4]; + end + end + 12'h020 : begin + if(factory_doWrite) begin + _zz_io_config_sclkToogle <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h024 : begin + if(factory_doWrite) begin + _zz_io_config_ss_setup <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h028 : begin + if(factory_doWrite) begin + _zz_io_config_ss_hold <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h02c : begin + if(factory_doWrite) begin + _zz_io_config_ss_disable <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + default : begin + end + endcase + end + + +endmodule + +module BmbUartCtrl_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_bus_cmd_valid, + output io_bus_cmd_ready, + input io_bus_cmd_payload_last, + input [0:0] io_bus_cmd_payload_fragment_opcode, + input [5:0] io_bus_cmd_payload_fragment_address, + input [1:0] io_bus_cmd_payload_fragment_length, + input [31:0] io_bus_cmd_payload_fragment_data, + input [3:0] io_bus_cmd_payload_fragment_context, + output io_bus_rsp_valid, + input io_bus_rsp_ready, + output io_bus_rsp_payload_last, + output [0:0] io_bus_rsp_payload_fragment_opcode, + output [31:0] io_bus_rsp_payload_fragment_data, + output [3:0] io_bus_rsp_payload_fragment_context, + output io_uart_txd, + input io_uart_rxd, + output io_interrupt, + input io_systemClk, + input systemCd_logic_outputReset +); + localparam UartStopType_ONE = 1'd0; + localparam UartStopType_TWO = 1'd1; + localparam UartParityType_NONE = 2'd0; + localparam UartParityType_EVEN = 2'd1; + localparam UartParityType_ODD = 2'd2; + + reg uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready; + wire uartCtrl_1_io_write_ready; + wire uartCtrl_1_io_read_valid; + wire [7:0] uartCtrl_1_io_read_payload; + wire uartCtrl_1_io_uart_txd; + wire uartCtrl_1_io_readError; + wire uartCtrl_1_io_readBreak; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_availability; + wire uartCtrl_1_io_read_queueWithOccupancy_io_push_ready; + wire uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid; + wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload; + wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_occupancy; + wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_availability; + wire [0:0] _zz_bridge_misc_readError; + wire [0:0] _zz_bridge_misc_readOverflowError; + wire [0:0] _zz_bridge_misc_breakDetected; + wire [0:0] _zz_bridge_misc_doBreak; + wire [0:0] _zz_bridge_misc_doBreak_1; + wire [7:0] _zz_busCtrl_rsp_payload_fragment_data; + wire [19:0] _zz_bridge_uartConfigReg_clockDivider; + wire [19:0] _zz_bridge_uartConfigReg_clockDivider_1; + wire busCtrl_readHaltTrigger; + wire busCtrl_writeHaltTrigger; + wire busCtrl_rsp_valid; + wire busCtrl_rsp_ready; + wire busCtrl_rsp_payload_last; + wire [0:0] busCtrl_rsp_payload_fragment_opcode; + reg [31:0] busCtrl_rsp_payload_fragment_data; + wire [3:0] busCtrl_rsp_payload_fragment_context; + wire _zz_io_bus_rsp_valid; + reg _zz_busCtrl_rsp_ready; + wire _zz_io_bus_rsp_valid_1; + reg _zz_io_bus_rsp_valid_2; + reg _zz_io_bus_rsp_payload_last; + reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_bus_rsp_payload_fragment_data; + reg [3:0] _zz_io_bus_rsp_payload_fragment_context; + wire when_Stream_l368; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire io_bus_cmd_fire; + wire busCtrl_doWrite; + wire io_bus_cmd_fire_1; + wire busCtrl_doRead; + reg [2:0] bridge_uartConfigReg_frame_dataLength; + reg [0:0] bridge_uartConfigReg_frame_stop; + reg [1:0] bridge_uartConfigReg_frame_parity; + reg [19:0] bridge_uartConfigReg_clockDivider; + reg _zz_bridge_write_streamUnbuffered_valid; + wire bridge_write_streamUnbuffered_valid; + wire bridge_write_streamUnbuffered_ready; + wire [7:0] bridge_write_streamUnbuffered_payload; + reg bridge_read_streamBreaked_valid; + reg bridge_read_streamBreaked_ready; + wire [7:0] bridge_read_streamBreaked_payload; + reg bridge_interruptCtrl_writeIntEnable; + reg bridge_interruptCtrl_readIntEnable; + wire bridge_interruptCtrl_readInt; + wire bridge_interruptCtrl_writeInt; + wire bridge_interruptCtrl_interrupt; + reg bridge_misc_readError; + reg when_BusSlaveFactory_l335; + wire when_BusSlaveFactory_l341; + reg bridge_misc_readOverflowError; + reg when_BusSlaveFactory_l335_1; + wire when_BusSlaveFactory_l341_1; + wire uartCtrl_1_io_read_isStall; + reg bridge_misc_breakDetected; + reg uartCtrl_1_io_readBreak_regNext; + wire when_UartCtrl_l155; + reg when_BusSlaveFactory_l335_2; + wire when_BusSlaveFactory_l341_2; + reg bridge_misc_doBreak; + reg when_BusSlaveFactory_l371; + wire when_BusSlaveFactory_l373; + reg when_BusSlaveFactory_l335_3; + wire when_BusSlaveFactory_l341_3; + wire [1:0] _zz_bridge_uartConfigReg_frame_parity; + wire [0:0] _zz_bridge_uartConfigReg_frame_stop; + wire when_BmbSlaveFactory_l71; + `ifndef SYNTHESIS + reg [23:0] bridge_uartConfigReg_frame_stop_string; + reg [31:0] bridge_uartConfigReg_frame_parity_string; + reg [31:0] _zz_bridge_uartConfigReg_frame_parity_string; + reg [23:0] _zz_bridge_uartConfigReg_frame_stop_string; + `endif + + + assign _zz_bridge_misc_readError = 1'b0; + assign _zz_bridge_misc_readOverflowError = 1'b0; + assign _zz_bridge_misc_breakDetected = 1'b0; + assign _zz_bridge_misc_doBreak = 1'b1; + assign _zz_bridge_misc_doBreak_1 = 1'b0; + assign _zz_busCtrl_rsp_payload_fragment_data = (8'h80 - bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy); + assign _zz_bridge_uartConfigReg_clockDivider_1 = io_bus_cmd_payload_fragment_data[19 : 0]; + assign _zz_bridge_uartConfigReg_clockDivider = _zz_bridge_uartConfigReg_clockDivider_1; + UartCtrl_b62b14ffe6bb44e5a817b8d08e286c6b uartCtrl_1 ( + .io_config_frame_dataLength (bridge_uartConfigReg_frame_dataLength[2:0] ), //i + .io_config_frame_stop (bridge_uartConfigReg_frame_stop ), //i + .io_config_frame_parity (bridge_uartConfigReg_frame_parity[1:0] ), //i + .io_config_clockDivider (bridge_uartConfigReg_clockDivider[19:0] ), //i + .io_write_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //i + .io_write_ready (uartCtrl_1_io_write_ready ), //o + .io_write_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0]), //i + .io_read_valid (uartCtrl_1_io_read_valid ), //o + .io_read_ready (uartCtrl_1_io_read_queueWithOccupancy_io_push_ready ), //i + .io_read_payload (uartCtrl_1_io_read_payload[7:0] ), //o + .io_uart_txd (uartCtrl_1_io_uart_txd ), //o + .io_uart_rxd (io_uart_rxd ), //i + .io_readError (uartCtrl_1_io_readError ), //o + .io_writeBreak (bridge_misc_doBreak ), //i + .io_readBreak (uartCtrl_1_io_readBreak ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + StreamFifo_b62b14ffe6bb44e5a817b8d08e286c6b bridge_write_streamUnbuffered_queueWithOccupancy ( + .io_push_valid (bridge_write_streamUnbuffered_valid ), //i + .io_push_ready (bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready ), //o + .io_push_payload (bridge_write_streamUnbuffered_payload[7:0] ), //i + .io_pop_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (uartCtrl_1_io_write_ready ), //i + .io_pop_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy[7:0] ), //o + .io_availability (bridge_write_streamUnbuffered_queueWithOccupancy_io_availability[7:0]), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + StreamFifo_b62b14ffe6bb44e5a817b8d08e286c6b uartCtrl_1_io_read_queueWithOccupancy ( + .io_push_valid (uartCtrl_1_io_read_valid ), //i + .io_push_ready (uartCtrl_1_io_read_queueWithOccupancy_io_push_ready ), //o + .io_push_payload (uartCtrl_1_io_read_payload[7:0] ), //i + .io_pop_valid (uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready ), //i + .io_pop_payload (uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (uartCtrl_1_io_read_queueWithOccupancy_io_occupancy[7:0] ), //o + .io_availability (uartCtrl_1_io_read_queueWithOccupancy_io_availability[7:0]), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(bridge_uartConfigReg_frame_stop) + UartStopType_ONE : bridge_uartConfigReg_frame_stop_string = "ONE"; + UartStopType_TWO : bridge_uartConfigReg_frame_stop_string = "TWO"; + default : bridge_uartConfigReg_frame_stop_string = "???"; + endcase + end + always @(*) begin + case(bridge_uartConfigReg_frame_parity) + UartParityType_NONE : bridge_uartConfigReg_frame_parity_string = "NONE"; + UartParityType_EVEN : bridge_uartConfigReg_frame_parity_string = "EVEN"; + UartParityType_ODD : bridge_uartConfigReg_frame_parity_string = "ODD "; + default : bridge_uartConfigReg_frame_parity_string = "????"; + endcase + end + always @(*) begin + case(_zz_bridge_uartConfigReg_frame_parity) + UartParityType_NONE : _zz_bridge_uartConfigReg_frame_parity_string = "NONE"; + UartParityType_EVEN : _zz_bridge_uartConfigReg_frame_parity_string = "EVEN"; + UartParityType_ODD : _zz_bridge_uartConfigReg_frame_parity_string = "ODD "; + default : _zz_bridge_uartConfigReg_frame_parity_string = "????"; + endcase + end + always @(*) begin + case(_zz_bridge_uartConfigReg_frame_stop) + UartStopType_ONE : _zz_bridge_uartConfigReg_frame_stop_string = "ONE"; + UartStopType_TWO : _zz_bridge_uartConfigReg_frame_stop_string = "TWO"; + default : _zz_bridge_uartConfigReg_frame_stop_string = "???"; + endcase + end + `endif + + assign io_uart_txd = uartCtrl_1_io_uart_txd; + assign busCtrl_readHaltTrigger = 1'b0; + assign busCtrl_writeHaltTrigger = 1'b0; + assign _zz_io_bus_rsp_valid = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); + assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready && _zz_io_bus_rsp_valid); + always @(*) begin + _zz_busCtrl_rsp_ready = io_bus_rsp_ready; + if(when_Stream_l368) begin + _zz_busCtrl_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! _zz_io_bus_rsp_valid_1); + assign _zz_io_bus_rsp_valid_1 = _zz_io_bus_rsp_valid_2; + assign io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; + assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; + assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; + assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; + assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; + assign busCtrl_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign busCtrl_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign io_bus_cmd_fire_1 = (io_bus_cmd_valid && io_bus_cmd_ready); + assign busCtrl_doRead = (io_bus_cmd_fire_1 && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign busCtrl_rsp_valid = io_bus_cmd_valid; + assign io_bus_cmd_ready = busCtrl_rsp_ready; + assign busCtrl_rsp_payload_last = 1'b1; + assign busCtrl_rsp_payload_fragment_opcode = 1'b0; + always @(*) begin + busCtrl_rsp_payload_fragment_data = 32'h0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + busCtrl_rsp_payload_fragment_data[16 : 16] = (bridge_read_streamBreaked_valid ^ 1'b0); + busCtrl_rsp_payload_fragment_data[7 : 0] = bridge_read_streamBreaked_payload; + end + 6'h04 : begin + busCtrl_rsp_payload_fragment_data[23 : 16] = _zz_busCtrl_rsp_payload_fragment_data; + busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; + busCtrl_rsp_payload_fragment_data[31 : 24] = uartCtrl_1_io_read_queueWithOccupancy_io_occupancy; + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_interruptCtrl_writeIntEnable; + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_interruptCtrl_readIntEnable; + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_interruptCtrl_writeInt; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_interruptCtrl_readInt; + end + 6'h10 : begin + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_misc_readError; + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_misc_readOverflowError; + busCtrl_rsp_payload_fragment_data[8 : 8] = uartCtrl_1_io_readBreak; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_misc_breakDetected; + end + default : begin + end + endcase + end + + assign busCtrl_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; + always @(*) begin + _zz_bridge_write_streamUnbuffered_valid = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + if(busCtrl_doWrite) begin + _zz_bridge_write_streamUnbuffered_valid = 1'b1; + end + end + default : begin + end + endcase + end + + assign bridge_write_streamUnbuffered_valid = _zz_bridge_write_streamUnbuffered_valid; + assign bridge_write_streamUnbuffered_payload = io_bus_cmd_payload_fragment_data[7 : 0]; + assign bridge_write_streamUnbuffered_ready = bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + always @(*) begin + bridge_read_streamBreaked_valid = uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid; + if(uartCtrl_1_io_readBreak) begin + bridge_read_streamBreaked_valid = 1'b0; + end + end + + always @(*) begin + uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready = bridge_read_streamBreaked_ready; + if(uartCtrl_1_io_readBreak) begin + uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready = 1'b1; + end + end + + assign bridge_read_streamBreaked_payload = uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload; + always @(*) begin + bridge_read_streamBreaked_ready = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + if(busCtrl_doRead) begin + bridge_read_streamBreaked_ready = 1'b1; + end + end + default : begin + end + endcase + end + + assign bridge_interruptCtrl_readInt = (bridge_interruptCtrl_readIntEnable && bridge_read_streamBreaked_valid); + assign bridge_interruptCtrl_writeInt = (bridge_interruptCtrl_writeIntEnable && (! bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid)); + assign bridge_interruptCtrl_interrupt = (bridge_interruptCtrl_readInt || bridge_interruptCtrl_writeInt); + always @(*) begin + when_BusSlaveFactory_l335 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l335 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l341 = io_bus_cmd_payload_fragment_data[0]; + always @(*) begin + when_BusSlaveFactory_l335_1 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l335_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l341_1 = io_bus_cmd_payload_fragment_data[1]; + assign uartCtrl_1_io_read_isStall = (uartCtrl_1_io_read_valid && (! uartCtrl_1_io_read_queueWithOccupancy_io_push_ready)); + assign when_UartCtrl_l155 = (uartCtrl_1_io_readBreak && (! uartCtrl_1_io_readBreak_regNext)); + always @(*) begin + when_BusSlaveFactory_l335_2 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l335_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l341_2 = io_bus_cmd_payload_fragment_data[9]; + always @(*) begin + when_BusSlaveFactory_l371 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l371 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l373 = io_bus_cmd_payload_fragment_data[10]; + always @(*) begin + when_BusSlaveFactory_l335_3 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l335_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l341_3 = io_bus_cmd_payload_fragment_data[11]; + assign io_interrupt = bridge_interruptCtrl_interrupt; + assign _zz_bridge_uartConfigReg_frame_parity = io_bus_cmd_payload_fragment_data[9 : 8]; + assign _zz_bridge_uartConfigReg_frame_stop = io_bus_cmd_payload_fragment_data[16 : 16]; + assign when_BmbSlaveFactory_l71 = ((io_bus_cmd_payload_fragment_address & (~ 6'h03)) == 6'h08); + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + _zz_io_bus_rsp_valid_2 <= 1'b0; + bridge_uartConfigReg_clockDivider <= 20'h0; + bridge_uartConfigReg_clockDivider <= 20'h00035; + bridge_uartConfigReg_frame_dataLength <= 3'b111; + bridge_uartConfigReg_frame_parity <= UartParityType_NONE; + bridge_uartConfigReg_frame_stop <= UartStopType_ONE; + bridge_interruptCtrl_writeIntEnable <= 1'b0; + bridge_interruptCtrl_readIntEnable <= 1'b0; + bridge_misc_readError <= 1'b0; + bridge_misc_readOverflowError <= 1'b0; + bridge_misc_breakDetected <= 1'b0; + bridge_misc_doBreak <= 1'b0; + end else begin + if(_zz_busCtrl_rsp_ready) begin + _zz_io_bus_rsp_valid_2 <= (busCtrl_rsp_valid && _zz_io_bus_rsp_valid); + end + if(when_BusSlaveFactory_l335) begin + if(when_BusSlaveFactory_l341) begin + bridge_misc_readError <= _zz_bridge_misc_readError[0]; + end + end + if(uartCtrl_1_io_readError) begin + bridge_misc_readError <= 1'b1; + end + if(when_BusSlaveFactory_l335_1) begin + if(when_BusSlaveFactory_l341_1) begin + bridge_misc_readOverflowError <= _zz_bridge_misc_readOverflowError[0]; + end + end + if(uartCtrl_1_io_read_isStall) begin + bridge_misc_readOverflowError <= 1'b1; + end + if(when_UartCtrl_l155) begin + bridge_misc_breakDetected <= 1'b1; + end + if(when_BusSlaveFactory_l335_2) begin + if(when_BusSlaveFactory_l341_2) begin + bridge_misc_breakDetected <= _zz_bridge_misc_breakDetected[0]; + end + end + if(when_BusSlaveFactory_l371) begin + if(when_BusSlaveFactory_l373) begin + bridge_misc_doBreak <= _zz_bridge_misc_doBreak[0]; + end + end + if(when_BusSlaveFactory_l335_3) begin + if(when_BusSlaveFactory_l341_3) begin + bridge_misc_doBreak <= _zz_bridge_misc_doBreak_1[0]; + end + end + case(io_bus_cmd_payload_fragment_address) + 6'h0c : begin + if(busCtrl_doWrite) begin + bridge_uartConfigReg_frame_dataLength <= io_bus_cmd_payload_fragment_data[2 : 0]; + bridge_uartConfigReg_frame_parity <= _zz_bridge_uartConfigReg_frame_parity; + bridge_uartConfigReg_frame_stop <= _zz_bridge_uartConfigReg_frame_stop; + end + end + 6'h04 : begin + if(busCtrl_doWrite) begin + bridge_interruptCtrl_writeIntEnable <= io_bus_cmd_payload_fragment_data[0]; + bridge_interruptCtrl_readIntEnable <= io_bus_cmd_payload_fragment_data[1]; + end + end + default : begin + end + endcase + if(when_BmbSlaveFactory_l71) begin + if(busCtrl_doWrite) begin + bridge_uartConfigReg_clockDivider[19 : 0] <= _zz_bridge_uartConfigReg_clockDivider; + end + end + end + end + + always @(posedge io_systemClk) begin + if(_zz_busCtrl_rsp_ready) begin + _zz_io_bus_rsp_payload_last <= busCtrl_rsp_payload_last; + _zz_io_bus_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; + _zz_io_bus_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; + _zz_io_bus_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; + end + uartCtrl_1_io_readBreak_regNext <= uartCtrl_1_io_readBreak; + end + + +endmodule + +module BmbClint_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_bus_cmd_valid, + output io_bus_cmd_ready, + input io_bus_cmd_payload_last, + input [0:0] io_bus_cmd_payload_fragment_opcode, + input [15:0] io_bus_cmd_payload_fragment_address, + input [1:0] io_bus_cmd_payload_fragment_length, + input [31:0] io_bus_cmd_payload_fragment_data, + input [3:0] io_bus_cmd_payload_fragment_context, + output io_bus_rsp_valid, + input io_bus_rsp_ready, + output io_bus_rsp_payload_last, + output [0:0] io_bus_rsp_payload_fragment_opcode, + output [31:0] io_bus_rsp_payload_fragment_data, + output [3:0] io_bus_rsp_payload_fragment_context, + output [0:0] io_timerInterrupt, + output [0:0] io_softwareInterrupt, + output [63:0] io_time, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire [31:0] _zz_logic_harts_0_cmp; + wire [31:0] _zz_logic_harts_0_cmp_1; + wire [31:0] _zz_logic_harts_0_cmp_2; + wire [31:0] _zz_logic_harts_0_cmp_3; + wire factory_readHaltTrigger; + wire factory_writeHaltTrigger; + wire factory_rsp_valid; + wire factory_rsp_ready; + wire factory_rsp_payload_last; + wire [0:0] factory_rsp_payload_fragment_opcode; + reg [31:0] factory_rsp_payload_fragment_data; + wire [3:0] factory_rsp_payload_fragment_context; + wire _zz_io_bus_rsp_valid; + reg _zz_factory_rsp_ready; + wire _zz_io_bus_rsp_valid_1; + reg _zz_io_bus_rsp_valid_2; + reg _zz_io_bus_rsp_payload_last; + reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_bus_rsp_payload_fragment_data; + reg [3:0] _zz_io_bus_rsp_payload_fragment_context; + wire when_Stream_l368; + wire factory_askWrite; + wire factory_askRead; + wire io_bus_cmd_fire; + wire factory_doWrite; + wire io_bus_cmd_fire_1; + wire factory_doRead; + reg [63:0] logic_time; + reg [63:0] logic_harts_0_cmp; + reg logic_harts_0_timerInterrupt; + reg logic_harts_0_softwareInterrupt; + wire [63:0] _zz_factory_rsp_payload_fragment_data; + wire when_BmbSlaveFactory_l71; + wire when_BmbSlaveFactory_l71_1; + wire when_BmbSlaveFactory_l71_2; + wire when_BmbSlaveFactory_l71_3; + + assign _zz_logic_harts_0_cmp_1 = io_bus_cmd_payload_fragment_data[31 : 0]; + assign _zz_logic_harts_0_cmp = _zz_logic_harts_0_cmp_1; + assign _zz_logic_harts_0_cmp_3 = io_bus_cmd_payload_fragment_data[31 : 0]; + assign _zz_logic_harts_0_cmp_2 = _zz_logic_harts_0_cmp_3; + assign factory_readHaltTrigger = 1'b0; + assign factory_writeHaltTrigger = 1'b0; + assign _zz_io_bus_rsp_valid = (! (factory_readHaltTrigger || factory_writeHaltTrigger)); + assign factory_rsp_ready = (_zz_factory_rsp_ready && _zz_io_bus_rsp_valid); + always @(*) begin + _zz_factory_rsp_ready = io_bus_rsp_ready; + if(when_Stream_l368) begin + _zz_factory_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! _zz_io_bus_rsp_valid_1); + assign _zz_io_bus_rsp_valid_1 = _zz_io_bus_rsp_valid_2; + assign io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; + assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; + assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; + assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; + assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; + assign factory_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign factory_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign factory_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign io_bus_cmd_fire_1 = (io_bus_cmd_valid && io_bus_cmd_ready); + assign factory_doRead = (io_bus_cmd_fire_1 && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign factory_rsp_valid = io_bus_cmd_valid; + assign io_bus_cmd_ready = factory_rsp_ready; + assign factory_rsp_payload_last = 1'b1; + assign factory_rsp_payload_fragment_opcode = 1'b0; + always @(*) begin + factory_rsp_payload_fragment_data = 32'h0; + case(io_bus_cmd_payload_fragment_address) + 16'h0 : begin + factory_rsp_payload_fragment_data[0 : 0] = logic_harts_0_softwareInterrupt; + end + default : begin + end + endcase + if(when_BmbSlaveFactory_l71) begin + factory_rsp_payload_fragment_data[31 : 0] = _zz_factory_rsp_payload_fragment_data[31 : 0]; + end + if(when_BmbSlaveFactory_l71_1) begin + factory_rsp_payload_fragment_data[31 : 0] = _zz_factory_rsp_payload_fragment_data[63 : 32]; + end + end + + assign factory_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; + assign _zz_factory_rsp_payload_fragment_data = logic_time; + assign io_timerInterrupt[0] = logic_harts_0_timerInterrupt; + assign io_softwareInterrupt[0] = logic_harts_0_softwareInterrupt; + assign io_time = logic_time; + assign when_BmbSlaveFactory_l71 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'hbff8); + assign when_BmbSlaveFactory_l71_1 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'hbffc); + assign when_BmbSlaveFactory_l71_2 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'h4000); + assign when_BmbSlaveFactory_l71_3 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'h4004); + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + _zz_io_bus_rsp_valid_2 <= 1'b0; + logic_time <= 64'h0; + logic_harts_0_softwareInterrupt <= 1'b0; + end else begin + if(_zz_factory_rsp_ready) begin + _zz_io_bus_rsp_valid_2 <= (factory_rsp_valid && _zz_io_bus_rsp_valid); + end + logic_time <= (logic_time + 64'h0000000000000001); + case(io_bus_cmd_payload_fragment_address) + 16'h0 : begin + if(factory_doWrite) begin + logic_harts_0_softwareInterrupt <= io_bus_cmd_payload_fragment_data[0]; + end + end + default : begin + end + endcase + end + end + + always @(posedge io_systemClk) begin + if(_zz_factory_rsp_ready) begin + _zz_io_bus_rsp_payload_last <= factory_rsp_payload_last; + _zz_io_bus_rsp_payload_fragment_opcode <= factory_rsp_payload_fragment_opcode; + _zz_io_bus_rsp_payload_fragment_data <= factory_rsp_payload_fragment_data; + _zz_io_bus_rsp_payload_fragment_context <= factory_rsp_payload_fragment_context; + end + logic_harts_0_timerInterrupt <= (logic_harts_0_cmp <= logic_time); + if(when_BmbSlaveFactory_l71_2) begin + if(factory_doWrite) begin + logic_harts_0_cmp[31 : 0] <= _zz_logic_harts_0_cmp; + end + end + if(when_BmbSlaveFactory_l71_3) begin + if(factory_doWrite) begin + logic_harts_0_cmp[63 : 32] <= _zz_logic_harts_0_cmp_2; + end + end + end + + +endmodule + +module BmbDecoder_3_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [23:0] io_input_cmd_payload_fragment_address, + input [1:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_mask, + input [3:0] io_input_cmd_payload_fragment_context, + output reg io_input_rsp_valid, + input io_input_rsp_ready, + output reg io_input_rsp_payload_last, + output reg [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output reg [3:0] io_input_rsp_payload_fragment_context, + output reg io_outputs_0_cmd_valid, + input io_outputs_0_cmd_ready, + output io_outputs_0_cmd_payload_last, + output [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output [23:0] io_outputs_0_cmd_payload_fragment_address, + output [1:0] io_outputs_0_cmd_payload_fragment_length, + output [31:0] io_outputs_0_cmd_payload_fragment_data, + output [3:0] io_outputs_0_cmd_payload_fragment_mask, + output [3:0] io_outputs_0_cmd_payload_fragment_context, + input io_outputs_0_rsp_valid, + output io_outputs_0_rsp_ready, + input io_outputs_0_rsp_payload_last, + input [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input [31:0] io_outputs_0_rsp_payload_fragment_data, + input [3:0] io_outputs_0_rsp_payload_fragment_context, + output reg io_outputs_1_cmd_valid, + input io_outputs_1_cmd_ready, + output io_outputs_1_cmd_payload_last, + output [0:0] io_outputs_1_cmd_payload_fragment_opcode, + output [23:0] io_outputs_1_cmd_payload_fragment_address, + output [1:0] io_outputs_1_cmd_payload_fragment_length, + output [31:0] io_outputs_1_cmd_payload_fragment_data, + output [3:0] io_outputs_1_cmd_payload_fragment_mask, + output [3:0] io_outputs_1_cmd_payload_fragment_context, + input io_outputs_1_rsp_valid, + output io_outputs_1_rsp_ready, + input io_outputs_1_rsp_payload_last, + input [0:0] io_outputs_1_rsp_payload_fragment_opcode, + input [31:0] io_outputs_1_rsp_payload_fragment_data, + input [3:0] io_outputs_1_rsp_payload_fragment_context, + output reg io_outputs_2_cmd_valid, + input io_outputs_2_cmd_ready, + output io_outputs_2_cmd_payload_last, + output [0:0] io_outputs_2_cmd_payload_fragment_opcode, + output [23:0] io_outputs_2_cmd_payload_fragment_address, + output [1:0] io_outputs_2_cmd_payload_fragment_length, + output [31:0] io_outputs_2_cmd_payload_fragment_data, + output [3:0] io_outputs_2_cmd_payload_fragment_mask, + output [3:0] io_outputs_2_cmd_payload_fragment_context, + input io_outputs_2_rsp_valid, + output io_outputs_2_rsp_ready, + input io_outputs_2_rsp_payload_last, + input [0:0] io_outputs_2_rsp_payload_fragment_opcode, + input [31:0] io_outputs_2_rsp_payload_fragment_data, + input [3:0] io_outputs_2_rsp_payload_fragment_context, + output reg io_outputs_3_cmd_valid, + input io_outputs_3_cmd_ready, + output io_outputs_3_cmd_payload_last, + output [0:0] io_outputs_3_cmd_payload_fragment_opcode, + output [23:0] io_outputs_3_cmd_payload_fragment_address, + output [1:0] io_outputs_3_cmd_payload_fragment_length, + output [31:0] io_outputs_3_cmd_payload_fragment_data, + output [3:0] io_outputs_3_cmd_payload_fragment_mask, + output [3:0] io_outputs_3_cmd_payload_fragment_context, + input io_outputs_3_rsp_valid, + output io_outputs_3_rsp_ready, + input io_outputs_3_rsp_payload_last, + input [0:0] io_outputs_3_rsp_payload_fragment_opcode, + input [31:0] io_outputs_3_rsp_payload_fragment_data, + input [3:0] io_outputs_3_rsp_payload_fragment_context, + output reg io_outputs_4_cmd_valid, + input io_outputs_4_cmd_ready, + output io_outputs_4_cmd_payload_last, + output [0:0] io_outputs_4_cmd_payload_fragment_opcode, + output [23:0] io_outputs_4_cmd_payload_fragment_address, + output [1:0] io_outputs_4_cmd_payload_fragment_length, + output [31:0] io_outputs_4_cmd_payload_fragment_data, + output [3:0] io_outputs_4_cmd_payload_fragment_mask, + output [3:0] io_outputs_4_cmd_payload_fragment_context, + input io_outputs_4_rsp_valid, + output io_outputs_4_rsp_ready, + input io_outputs_4_rsp_payload_last, + input [0:0] io_outputs_4_rsp_payload_fragment_opcode, + input [31:0] io_outputs_4_rsp_payload_fragment_data, + input [3:0] io_outputs_4_rsp_payload_fragment_context, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire [3:0] _zz_logic_rspPendingCounter; + wire [3:0] _zz_logic_rspPendingCounter_1; + wire [0:0] _zz_logic_rspPendingCounter_2; + wire [3:0] _zz_logic_rspPendingCounter_3; + wire [0:0] _zz_logic_rspPendingCounter_4; + reg _zz_io_input_rsp_payload_last_3; + reg [0:0] _zz_io_input_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_input_rsp_payload_fragment_data; + reg [3:0] _zz_io_input_rsp_payload_fragment_context; + wire logic_input_valid; + reg logic_input_ready; + wire logic_input_payload_last; + wire [0:0] logic_input_payload_fragment_opcode; + wire [23:0] logic_input_payload_fragment_address; + wire [1:0] logic_input_payload_fragment_length; + wire [31:0] logic_input_payload_fragment_data; + wire [3:0] logic_input_payload_fragment_mask; + wire [3:0] logic_input_payload_fragment_context; + reg io_input_cmd_rValid; + wire logic_input_fire; + reg io_input_cmd_rData_last; + reg [0:0] io_input_cmd_rData_fragment_opcode; + reg [23:0] io_input_cmd_rData_fragment_address; + reg [1:0] io_input_cmd_rData_fragment_length; + reg [31:0] io_input_cmd_rData_fragment_data; + reg [3:0] io_input_cmd_rData_fragment_mask; + reg [3:0] io_input_cmd_rData_fragment_context; + wire logic_hitsS0_0; + wire logic_hitsS0_1; + wire logic_hitsS0_2; + wire logic_hitsS0_3; + wire logic_hitsS0_4; + wire logic_noHitS0; + wire io_input_cmd_fire; + reg logic_hitsS1_0; + reg logic_hitsS1_1; + reg logic_hitsS1_2; + reg logic_hitsS1_3; + reg logic_hitsS1_4; + wire io_input_cmd_fire_1; + reg logic_noHitS1; + wire _zz_io_outputs_0_cmd_payload_last; + wire _zz_io_outputs_1_cmd_payload_last; + wire _zz_io_outputs_2_cmd_payload_last; + wire _zz_io_outputs_3_cmd_payload_last; + wire _zz_io_outputs_4_cmd_payload_last; + reg [3:0] logic_rspPendingCounter; + wire logic_input_fire_1; + wire io_input_rsp_fire; + wire logic_cmdWait; + wire when_BmbDecoder_l56; + reg logic_rspHits_0; + reg logic_rspHits_1; + reg logic_rspHits_2; + reg logic_rspHits_3; + reg logic_rspHits_4; + wire logic_rspPending; + wire logic_rspNoHitValid; + reg logic_rspNoHit_doIt; + wire io_input_rsp_fire_1; + wire when_BmbDecoder_l60; + wire logic_input_fire_2; + wire when_BmbDecoder_l60_1; + wire logic_input_fire_3; + reg logic_rspNoHit_singleBeatRsp; + wire logic_input_fire_4; + wire logic_input_fire_5; + reg [3:0] logic_rspNoHit_context; + wire logic_input_fire_6; + wire _zz_io_input_rsp_payload_last; + wire _zz_io_input_rsp_payload_last_1; + wire [2:0] _zz_io_input_rsp_payload_last_2; + + assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); + assign _zz_logic_rspPendingCounter_2 = (logic_input_fire_1 && logic_input_payload_last); + assign _zz_logic_rspPendingCounter_1 = {3'd0, _zz_logic_rspPendingCounter_2}; + assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign _zz_logic_rspPendingCounter_3 = {3'd0, _zz_logic_rspPendingCounter_4}; + always @(*) begin + case(_zz_io_input_rsp_payload_last_2) + 3'b000 : begin + _zz_io_input_rsp_payload_last_3 = io_outputs_0_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_0_rsp_payload_fragment_context; + end + 3'b001 : begin + _zz_io_input_rsp_payload_last_3 = io_outputs_1_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_1_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_1_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_1_rsp_payload_fragment_context; + end + 3'b010 : begin + _zz_io_input_rsp_payload_last_3 = io_outputs_2_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_2_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_2_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_2_rsp_payload_fragment_context; + end + 3'b011 : begin + _zz_io_input_rsp_payload_last_3 = io_outputs_3_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_3_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_3_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_3_rsp_payload_fragment_context; + end + default : begin + _zz_io_input_rsp_payload_last_3 = io_outputs_4_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_4_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_4_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_4_rsp_payload_fragment_context; + end + endcase + end + + assign logic_input_fire = (logic_input_valid && logic_input_ready); + assign io_input_cmd_ready = (! io_input_cmd_rValid); + assign logic_input_valid = io_input_cmd_rValid; + assign logic_input_payload_last = io_input_cmd_rData_last; + assign logic_input_payload_fragment_opcode = io_input_cmd_rData_fragment_opcode; + assign logic_input_payload_fragment_address = io_input_cmd_rData_fragment_address; + assign logic_input_payload_fragment_length = io_input_cmd_rData_fragment_length; + assign logic_input_payload_fragment_data = io_input_cmd_rData_fragment_data; + assign logic_input_payload_fragment_mask = io_input_cmd_rData_fragment_mask; + assign logic_input_payload_fragment_context = io_input_cmd_rData_fragment_context; + assign logic_noHitS0 = (! ({logic_hitsS0_4,{logic_hitsS0_3,{logic_hitsS0_2,{logic_hitsS0_1,logic_hitsS0_0}}}} != 5'h0)); + assign io_input_cmd_fire = (io_input_cmd_valid && io_input_cmd_ready); + assign io_input_cmd_fire_1 = (io_input_cmd_valid && io_input_cmd_ready); + assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 24'h3fffff)) == 24'hc00000); + always @(*) begin + io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS1_0); + if(logic_cmdWait) begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; + assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; + assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_0_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_1 = ((io_input_cmd_payload_fragment_address & (~ 24'h00ffff)) == 24'hb00000); + always @(*) begin + io_outputs_1_cmd_valid = (logic_input_valid && logic_hitsS1_1); + if(logic_cmdWait) begin + io_outputs_1_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_1_cmd_payload_last = logic_input_payload_last; + assign io_outputs_1_cmd_payload_last = _zz_io_outputs_1_cmd_payload_last; + assign io_outputs_1_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_1_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_1_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_1_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_1_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_1_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_2 = ((io_input_cmd_payload_fragment_address & (~ 24'h00003f)) == 24'h010000); + always @(*) begin + io_outputs_2_cmd_valid = (logic_input_valid && logic_hitsS1_2); + if(logic_cmdWait) begin + io_outputs_2_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_2_cmd_payload_last = logic_input_payload_last; + assign io_outputs_2_cmd_payload_last = _zz_io_outputs_2_cmd_payload_last; + assign io_outputs_2_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_2_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_2_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_2_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_2_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_2_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_3 = ((io_input_cmd_payload_fragment_address & (~ 24'h000fff)) == 24'h014000); + always @(*) begin + io_outputs_3_cmd_valid = (logic_input_valid && logic_hitsS1_3); + if(logic_cmdWait) begin + io_outputs_3_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_3_cmd_payload_last = logic_input_payload_last; + assign io_outputs_3_cmd_payload_last = _zz_io_outputs_3_cmd_payload_last; + assign io_outputs_3_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_3_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_3_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_3_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_3_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_3_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_4 = ((io_input_cmd_payload_fragment_address & (~ 24'h00ffff)) == 24'h100000); + always @(*) begin + io_outputs_4_cmd_valid = (logic_input_valid && logic_hitsS1_4); + if(logic_cmdWait) begin + io_outputs_4_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_4_cmd_payload_last = logic_input_payload_last; + assign io_outputs_4_cmd_payload_last = _zz_io_outputs_4_cmd_payload_last; + assign io_outputs_4_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_4_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_4_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_4_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_4_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_4_cmd_payload_fragment_context = logic_input_payload_fragment_context; + always @(*) begin + logic_input_ready = (({(logic_hitsS1_4 && io_outputs_4_cmd_ready),{(logic_hitsS1_3 && io_outputs_3_cmd_ready),{(logic_hitsS1_2 && io_outputs_2_cmd_ready),{(logic_hitsS1_1 && io_outputs_1_cmd_ready),(logic_hitsS1_0 && io_outputs_0_cmd_ready)}}}} != 5'h0) || logic_noHitS1); + if(logic_cmdWait) begin + logic_input_ready = 1'b0; + end + end + + assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); + assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); + assign logic_rspPending = (logic_rspPendingCounter != 4'b0000); + assign logic_rspNoHitValid = (! ({logic_rspHits_4,{logic_rspHits_3,{logic_rspHits_2,{logic_rspHits_1,logic_rspHits_0}}}} != 5'h0)); + assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); + assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); + assign when_BmbDecoder_l60_1 = ((logic_input_fire_2 && logic_noHitS1) && logic_input_payload_last); + assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_6 = (logic_input_valid && logic_input_ready); + always @(*) begin + io_input_rsp_valid = (({io_outputs_4_rsp_valid,{io_outputs_3_rsp_valid,{io_outputs_2_rsp_valid,{io_outputs_1_rsp_valid,io_outputs_0_rsp_valid}}}} != 5'h0) || (logic_rspPending && logic_rspNoHitValid)); + if(logic_rspNoHit_doIt) begin + io_input_rsp_valid = 1'b1; + end + end + + assign _zz_io_input_rsp_payload_last = (logic_rspHits_1 || logic_rspHits_3); + assign _zz_io_input_rsp_payload_last_1 = (logic_rspHits_2 || logic_rspHits_3); + assign _zz_io_input_rsp_payload_last_2 = {logic_rspHits_4,{_zz_io_input_rsp_payload_last_1,_zz_io_input_rsp_payload_last}}; + always @(*) begin + io_input_rsp_payload_last = _zz_io_input_rsp_payload_last_3; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_last = 1'b1; + end + end + + always @(*) begin + io_input_rsp_payload_fragment_opcode = _zz_io_input_rsp_payload_fragment_opcode; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_opcode = 1'b1; + end + end + + assign io_input_rsp_payload_fragment_data = _zz_io_input_rsp_payload_fragment_data; + always @(*) begin + io_input_rsp_payload_fragment_context = _zz_io_input_rsp_payload_fragment_context; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_context = logic_rspNoHit_context; + end + end + + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign io_outputs_1_rsp_ready = io_input_rsp_ready; + assign io_outputs_2_rsp_ready = io_input_rsp_ready; + assign io_outputs_3_rsp_ready = io_input_rsp_ready; + assign io_outputs_4_rsp_ready = io_input_rsp_ready; + assign logic_cmdWait = ((logic_rspPending && ((((((logic_hitsS1_0 != logic_rspHits_0) || (logic_hitsS1_1 != logic_rspHits_1)) || (logic_hitsS1_2 != logic_rspHits_2)) || (logic_hitsS1_3 != logic_rspHits_3)) || (logic_hitsS1_4 != logic_rspHits_4)) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 4'b1000)); + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + io_input_cmd_rValid <= 1'b0; + logic_rspPendingCounter <= 4'b0000; + logic_rspNoHit_doIt <= 1'b0; + end else begin + if(io_input_cmd_valid) begin + io_input_cmd_rValid <= 1'b1; + end + if(logic_input_fire) begin + io_input_cmd_rValid <= 1'b0; + end + logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); + if(when_BmbDecoder_l60) begin + logic_rspNoHit_doIt <= 1'b0; + end + if(when_BmbDecoder_l60_1) begin + logic_rspNoHit_doIt <= 1'b1; + end + end + end + + always @(posedge io_systemClk) begin + if(io_input_cmd_ready) begin + io_input_cmd_rData_last <= io_input_cmd_payload_last; + io_input_cmd_rData_fragment_opcode <= io_input_cmd_payload_fragment_opcode; + io_input_cmd_rData_fragment_address <= io_input_cmd_payload_fragment_address; + io_input_cmd_rData_fragment_length <= io_input_cmd_payload_fragment_length; + io_input_cmd_rData_fragment_data <= io_input_cmd_payload_fragment_data; + io_input_cmd_rData_fragment_mask <= io_input_cmd_payload_fragment_mask; + io_input_cmd_rData_fragment_context <= io_input_cmd_payload_fragment_context; + end + if(io_input_cmd_fire) begin + logic_hitsS1_0 <= logic_hitsS0_0; + logic_hitsS1_1 <= logic_hitsS0_1; + logic_hitsS1_2 <= logic_hitsS0_2; + logic_hitsS1_3 <= logic_hitsS0_3; + logic_hitsS1_4 <= logic_hitsS0_4; + end + if(io_input_cmd_fire_1) begin + logic_noHitS1 <= logic_noHitS0; + end + if(when_BmbDecoder_l56) begin + logic_rspHits_0 <= logic_hitsS1_0; + logic_rspHits_1 <= logic_hitsS1_1; + logic_rspHits_2 <= logic_hitsS1_2; + logic_rspHits_3 <= logic_hitsS1_3; + logic_rspHits_4 <= logic_hitsS1_4; + end + if(logic_input_fire_3) begin + logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); + end + if(logic_input_fire_5) begin + logic_rspNoHit_context <= logic_input_payload_fragment_context; + end + end + + +endmodule + +//BmbUnburstify_b62b14ffe6bb44e5a817b8d08e286c6b replaced by BmbUnburstify_b62b14ffe6bb44e5a817b8d08e286c6b + +module BmbUnburstify_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_input_cmd_valid, + output reg io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_source, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [31:0] io_input_cmd_payload_fragment_address, + input [5:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_mask, + input [0:0] io_input_cmd_payload_fragment_context, + output io_input_rsp_valid, + input io_input_rsp_ready, + output io_input_rsp_payload_last, + output [0:0] io_input_rsp_payload_fragment_source, + output [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output [0:0] io_input_rsp_payload_fragment_context, + output reg io_output_cmd_valid, + input io_output_cmd_ready, + output io_output_cmd_payload_last, + output reg [0:0] io_output_cmd_payload_fragment_opcode, + output reg [31:0] io_output_cmd_payload_fragment_address, + output reg [1:0] io_output_cmd_payload_fragment_length, + output [31:0] io_output_cmd_payload_fragment_data, + output [3:0] io_output_cmd_payload_fragment_mask, + output [3:0] io_output_cmd_payload_fragment_context, + input io_output_rsp_valid, + output reg io_output_rsp_ready, + input io_output_rsp_payload_last, + input [0:0] io_output_rsp_payload_fragment_opcode, + input [31:0] io_output_rsp_payload_fragment_data, + input [3:0] io_output_rsp_payload_fragment_context, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire [3:0] _zz_buffer_last; + wire [0:0] _zz_buffer_last_1; + wire [11:0] _zz_buffer_addressIncr; + wire [11:0] _zz_buffer_addressIncr_1; + wire [11:0] _zz_buffer_addressIncr_2; + wire doResult; + reg buffer_valid; + reg [0:0] buffer_opcode; + reg [0:0] buffer_source; + reg [31:0] buffer_address; + reg [0:0] buffer_context; + reg [3:0] buffer_beat; + wire buffer_last; + wire [31:0] buffer_addressIncr; + wire buffer_isWrite; + wire io_output_cmd_fire; + wire [3:0] cmdTransferBeatCount; + wire requireBuffer; + reg cmdContext_drop; + reg cmdContext_last; + reg [0:0] cmdContext_source; + reg [0:0] cmdContext_context; + wire io_output_cmd_fire_1; + wire rspContext_drop; + wire rspContext_last; + wire [0:0] rspContext_source; + wire [0:0] rspContext_context; + wire [3:0] _zz_rspContext_drop; + wire when_Stream_l434; + reg io_output_rsp_thrown_valid; + wire io_output_rsp_thrown_ready; + wire io_output_rsp_thrown_payload_last; + wire [0:0] io_output_rsp_thrown_payload_fragment_opcode; + wire [31:0] io_output_rsp_thrown_payload_fragment_data; + wire [3:0] io_output_rsp_thrown_payload_fragment_context; + + assign _zz_buffer_last_1 = 1'b1; + assign _zz_buffer_last = {3'd0, _zz_buffer_last_1}; + assign _zz_buffer_addressIncr = (_zz_buffer_addressIncr_1 + 12'h004); + assign _zz_buffer_addressIncr_2 = buffer_address[11 : 0]; + assign _zz_buffer_addressIncr_1 = _zz_buffer_addressIncr_2; + assign buffer_last = (buffer_beat == _zz_buffer_last); + assign buffer_addressIncr = {buffer_address[31 : 12],(_zz_buffer_addressIncr & (~ 12'h003))}; + assign buffer_isWrite = (buffer_opcode == 1'b1); + assign io_output_cmd_fire = (io_output_cmd_valid && io_output_cmd_ready); + assign cmdTransferBeatCount = io_input_cmd_payload_fragment_length[5 : 2]; + assign requireBuffer = (cmdTransferBeatCount != 4'b0000); + assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign io_output_cmd_payload_last = 1'b1; + assign io_output_cmd_payload_fragment_context = {cmdContext_context,{cmdContext_source,{cmdContext_last,cmdContext_drop}}}; + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_address = buffer_addressIncr; + end else begin + io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + if(requireBuffer) begin + io_output_cmd_payload_fragment_address[1 : 0] = 2'b00; + end + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_opcode = buffer_opcode; + end else begin + io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_length = 2'b11; + end else begin + if(requireBuffer) begin + io_output_cmd_payload_fragment_length = 2'b11; + end else begin + io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length[1:0]; + end + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_context = buffer_context; + end else begin + cmdContext_context = io_input_cmd_payload_fragment_context; + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_source = buffer_source; + end else begin + cmdContext_source = io_input_cmd_payload_fragment_source; + end + end + + always @(*) begin + io_input_cmd_ready = 1'b0; + if(buffer_valid) begin + io_input_cmd_ready = (buffer_isWrite && io_output_cmd_ready); + end else begin + io_input_cmd_ready = io_output_cmd_ready; + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_valid = (! (buffer_isWrite && (! io_input_cmd_valid))); + end else begin + io_output_cmd_valid = io_input_cmd_valid; + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_last = buffer_last; + end else begin + cmdContext_last = (! requireBuffer); + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_drop = buffer_isWrite; + end else begin + cmdContext_drop = (io_input_cmd_payload_fragment_opcode == 1'b1); + end + end + + assign io_output_cmd_fire_1 = (io_output_cmd_valid && io_output_cmd_ready); + assign _zz_rspContext_drop = io_output_rsp_payload_fragment_context; + assign rspContext_drop = _zz_rspContext_drop[0]; + assign rspContext_last = _zz_rspContext_drop[1]; + assign rspContext_source = _zz_rspContext_drop[2 : 2]; + assign rspContext_context = _zz_rspContext_drop[3 : 3]; + assign when_Stream_l434 = (! (rspContext_last || (! rspContext_drop))); + always @(*) begin + io_output_rsp_thrown_valid = io_output_rsp_valid; + if(when_Stream_l434) begin + io_output_rsp_thrown_valid = 1'b0; + end + end + + always @(*) begin + io_output_rsp_ready = io_output_rsp_thrown_ready; + if(when_Stream_l434) begin + io_output_rsp_ready = 1'b1; + end + end + + assign io_output_rsp_thrown_payload_last = io_output_rsp_payload_last; + assign io_output_rsp_thrown_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_output_rsp_thrown_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_output_rsp_thrown_payload_fragment_context = io_output_rsp_payload_fragment_context; + assign io_input_rsp_valid = io_output_rsp_thrown_valid; + assign io_output_rsp_thrown_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = rspContext_last; + assign io_input_rsp_payload_fragment_source = rspContext_source; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = rspContext_context; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + buffer_valid <= 1'b0; + end else begin + if(io_output_cmd_fire) begin + if(buffer_last) begin + buffer_valid <= 1'b0; + end + end + if(!buffer_valid) begin + buffer_valid <= (requireBuffer && io_output_cmd_fire_1); + end + end + end + + always @(posedge io_systemClk) begin + if(io_output_cmd_fire) begin + buffer_beat <= (buffer_beat - 4'b0001); + buffer_address[11 : 0] <= buffer_addressIncr[11 : 0]; + end + if(!buffer_valid) begin + buffer_opcode <= io_input_cmd_payload_fragment_opcode; + buffer_source <= io_input_cmd_payload_fragment_source; + buffer_address <= io_input_cmd_payload_fragment_address; + buffer_context <= io_input_cmd_payload_fragment_context; + buffer_beat <= cmdTransferBeatCount; + end + end + + +endmodule + +module BmbOnChipRam_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_bus_cmd_valid, + output io_bus_cmd_ready, + input io_bus_cmd_payload_last, + input [0:0] io_bus_cmd_payload_fragment_opcode, + input [14:0] io_bus_cmd_payload_fragment_address, + input [1:0] io_bus_cmd_payload_fragment_length, + input [31:0] io_bus_cmd_payload_fragment_data, + input [3:0] io_bus_cmd_payload_fragment_mask, + input [3:0] io_bus_cmd_payload_fragment_context, + output io_bus_rsp_valid, + input io_bus_rsp_ready, + output io_bus_rsp_payload_last, + output [0:0] io_bus_rsp_payload_fragment_opcode, + output [31:0] io_bus_rsp_payload_fragment_data, + output [3:0] io_bus_rsp_payload_fragment_context, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [31:0] _zz_ram_port0; + wire io_bus_rsp_isStall; + reg io_bus_cmd_valid_regNextWhen; + reg [3:0] io_bus_cmd_payload_fragment_context_regNextWhen; + wire [12:0] _zz_io_bus_rsp_payload_fragment_data; + wire io_bus_cmd_fire; + wire _zz_io_bus_rsp_payload_fragment_data_1; + wire [31:0] _zz_io_bus_rsp_payload_fragment_data_2; + reg [7:0] ram_symbol0 [0:8191]; + reg [7:0] ram_symbol1 [0:8191]; + reg [7:0] ram_symbol2 [0:8191]; + reg [7:0] ram_symbol3 [0:8191]; + reg [7:0] _zz_ramsymbol_read; + reg [7:0] _zz_ramsymbol_read_1; + reg [7:0] _zz_ramsymbol_read_2; + reg [7:0] _zz_ramsymbol_read_3; + + initial begin + $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol0.bin",ram_symbol0); + $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol1.bin",ram_symbol1); + $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol2.bin",ram_symbol2); + $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol3.bin",ram_symbol3); + end + always @(*) begin + _zz_ram_port0 = {_zz_ramsymbol_read_3, _zz_ramsymbol_read_2, _zz_ramsymbol_read_1, _zz_ramsymbol_read}; + end + always @(posedge io_systemClk) begin + if(io_bus_cmd_fire) begin + _zz_ramsymbol_read <= ram_symbol0[_zz_io_bus_rsp_payload_fragment_data]; + _zz_ramsymbol_read_1 <= ram_symbol1[_zz_io_bus_rsp_payload_fragment_data]; + _zz_ramsymbol_read_2 <= ram_symbol2[_zz_io_bus_rsp_payload_fragment_data]; + _zz_ramsymbol_read_3 <= ram_symbol3[_zz_io_bus_rsp_payload_fragment_data]; + end + end + + always @(posedge io_systemClk) begin + if(io_bus_cmd_payload_fragment_mask[0] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin + ram_symbol0[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[7 : 0]; + end + if(io_bus_cmd_payload_fragment_mask[1] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin + ram_symbol1[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[15 : 8]; + end + if(io_bus_cmd_payload_fragment_mask[2] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin + ram_symbol2[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[23 : 16]; + end + if(io_bus_cmd_payload_fragment_mask[3] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin + ram_symbol3[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[31 : 24]; + end + end + + assign io_bus_rsp_isStall = (io_bus_rsp_valid && (! io_bus_rsp_ready)); + assign io_bus_cmd_ready = (! io_bus_rsp_isStall); + assign io_bus_rsp_valid = io_bus_cmd_valid_regNextWhen; + assign io_bus_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context_regNextWhen; + assign _zz_io_bus_rsp_payload_fragment_data = (io_bus_cmd_payload_fragment_address >>> 2); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign _zz_io_bus_rsp_payload_fragment_data_1 = (io_bus_cmd_payload_fragment_opcode == 1'b1); + assign _zz_io_bus_rsp_payload_fragment_data_2 = io_bus_cmd_payload_fragment_data; + assign io_bus_rsp_payload_fragment_data = _zz_ram_port0; + assign io_bus_rsp_payload_fragment_opcode = 1'b0; + assign io_bus_rsp_payload_last = 1'b1; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + io_bus_cmd_valid_regNextWhen <= 1'b0; + end else begin + if(io_bus_cmd_ready) begin + io_bus_cmd_valid_regNextWhen <= io_bus_cmd_valid; + end + end + end + + always @(posedge io_systemClk) begin + if(io_bus_cmd_ready) begin + io_bus_cmd_payload_fragment_context_regNextWhen <= io_bus_cmd_payload_fragment_context; + end + end + + +endmodule + +module BmbDecoder_2_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_source, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [31:0] io_input_cmd_payload_fragment_address, + input [5:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_mask, + input [0:0] io_input_cmd_payload_fragment_context, + output reg io_input_rsp_valid, + input io_input_rsp_ready, + output reg io_input_rsp_payload_last, + output reg [0:0] io_input_rsp_payload_fragment_source, + output reg [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output reg [0:0] io_input_rsp_payload_fragment_context, + output reg io_outputs_0_cmd_valid, + input io_outputs_0_cmd_ready, + output io_outputs_0_cmd_payload_last, + output [0:0] io_outputs_0_cmd_payload_fragment_source, + output [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output [31:0] io_outputs_0_cmd_payload_fragment_address, + output [5:0] io_outputs_0_cmd_payload_fragment_length, + output [31:0] io_outputs_0_cmd_payload_fragment_data, + output [3:0] io_outputs_0_cmd_payload_fragment_mask, + output [0:0] io_outputs_0_cmd_payload_fragment_context, + input io_outputs_0_rsp_valid, + output io_outputs_0_rsp_ready, + input io_outputs_0_rsp_payload_last, + input [0:0] io_outputs_0_rsp_payload_fragment_source, + input [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input [31:0] io_outputs_0_rsp_payload_fragment_data, + input [0:0] io_outputs_0_rsp_payload_fragment_context, + output reg io_outputs_1_cmd_valid, + input io_outputs_1_cmd_ready, + output io_outputs_1_cmd_payload_last, + output [0:0] io_outputs_1_cmd_payload_fragment_source, + output [0:0] io_outputs_1_cmd_payload_fragment_opcode, + output [31:0] io_outputs_1_cmd_payload_fragment_address, + output [5:0] io_outputs_1_cmd_payload_fragment_length, + output [31:0] io_outputs_1_cmd_payload_fragment_data, + output [3:0] io_outputs_1_cmd_payload_fragment_mask, + output [0:0] io_outputs_1_cmd_payload_fragment_context, + input io_outputs_1_rsp_valid, + output io_outputs_1_rsp_ready, + input io_outputs_1_rsp_payload_last, + input [0:0] io_outputs_1_rsp_payload_fragment_source, + input [0:0] io_outputs_1_rsp_payload_fragment_opcode, + input [31:0] io_outputs_1_rsp_payload_fragment_data, + input [0:0] io_outputs_1_rsp_payload_fragment_context, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire [6:0] _zz_logic_rspPendingCounter; + wire [6:0] _zz_logic_rspPendingCounter_1; + wire [0:0] _zz_logic_rspPendingCounter_2; + wire [6:0] _zz_logic_rspPendingCounter_3; + wire [0:0] _zz_logic_rspPendingCounter_4; + reg _zz_io_input_rsp_payload_last_1; + reg [0:0] _zz_io_input_rsp_payload_fragment_source; + reg [0:0] _zz_io_input_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_input_rsp_payload_fragment_data; + reg [0:0] _zz_io_input_rsp_payload_fragment_context; + wire logic_input_valid; + reg logic_input_ready; + wire logic_input_payload_last; + wire [0:0] logic_input_payload_fragment_source; + wire [0:0] logic_input_payload_fragment_opcode; + wire [31:0] logic_input_payload_fragment_address; + wire [5:0] logic_input_payload_fragment_length; + wire [31:0] logic_input_payload_fragment_data; + wire [3:0] logic_input_payload_fragment_mask; + wire [0:0] logic_input_payload_fragment_context; + wire logic_hitsS0_0; + wire logic_hitsS0_1; + wire logic_noHitS0; + wire _zz_io_outputs_0_cmd_payload_last; + wire _zz_io_outputs_1_cmd_payload_last; + reg [6:0] logic_rspPendingCounter; + wire logic_input_fire; + wire io_input_rsp_fire; + wire logic_cmdWait; + wire when_BmbDecoder_l56; + reg logic_rspHits_0; + reg logic_rspHits_1; + wire logic_rspPending; + wire logic_rspNoHitValid; + reg logic_rspNoHit_doIt; + wire io_input_rsp_fire_1; + wire when_BmbDecoder_l60; + wire logic_input_fire_1; + wire when_BmbDecoder_l60_1; + wire logic_input_fire_2; + reg logic_rspNoHit_singleBeatRsp; + wire logic_input_fire_3; + reg [0:0] logic_rspNoHit_source; + wire logic_input_fire_4; + reg [0:0] logic_rspNoHit_context; + wire logic_input_fire_5; + reg [3:0] logic_rspNoHit_counter; + wire [0:0] _zz_io_input_rsp_payload_last; + wire when_BmbDecoder_l81; + wire io_input_rsp_fire_2; + + assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); + assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); + assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; + assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; + always @(*) begin + case(_zz_io_input_rsp_payload_last) + 1'b0 : begin + _zz_io_input_rsp_payload_last_1 = io_outputs_0_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_source = io_outputs_0_rsp_payload_fragment_source; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_0_rsp_payload_fragment_context; + end + default : begin + _zz_io_input_rsp_payload_last_1 = io_outputs_1_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_source = io_outputs_1_rsp_payload_fragment_source; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_1_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_1_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_1_rsp_payload_fragment_context; + end + endcase + end + + assign logic_input_valid = io_input_cmd_valid; + assign io_input_cmd_ready = logic_input_ready; + assign logic_input_payload_last = io_input_cmd_payload_last; + assign logic_input_payload_fragment_source = io_input_cmd_payload_fragment_source; + assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign logic_input_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign logic_noHitS0 = (! ({logic_hitsS0_1,logic_hitsS0_0} != 2'b00)); + assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 32'h00007fff)) == 32'hf9000000); + always @(*) begin + io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); + if(logic_cmdWait) begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; + assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; + assign io_outputs_0_cmd_payload_fragment_source = logic_input_payload_fragment_source; + assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_0_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_1 = ((io_input_cmd_payload_fragment_address & (~ 32'h00ffffff)) == 32'hf8000000); + always @(*) begin + io_outputs_1_cmd_valid = (logic_input_valid && logic_hitsS0_1); + if(logic_cmdWait) begin + io_outputs_1_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_1_cmd_payload_last = logic_input_payload_last; + assign io_outputs_1_cmd_payload_last = _zz_io_outputs_1_cmd_payload_last; + assign io_outputs_1_cmd_payload_fragment_source = logic_input_payload_fragment_source; + assign io_outputs_1_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_1_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_1_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_1_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_1_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_1_cmd_payload_fragment_context = logic_input_payload_fragment_context; + always @(*) begin + logic_input_ready = (({(logic_hitsS0_1 && io_outputs_1_cmd_ready),(logic_hitsS0_0 && io_outputs_0_cmd_ready)} != 2'b00) || logic_noHitS0); + if(logic_cmdWait) begin + logic_input_ready = 1'b0; + end + end + + assign logic_input_fire = (logic_input_valid && logic_input_ready); + assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); + assign logic_rspPending = (logic_rspPendingCounter != 7'h0); + assign logic_rspNoHitValid = (! ({logic_rspHits_1,logic_rspHits_0} != 2'b00)); + assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); + assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); + assign when_BmbDecoder_l60_1 = ((logic_input_fire_1 && logic_noHitS0) && logic_input_payload_last); + assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); + always @(*) begin + io_input_rsp_valid = (({io_outputs_1_rsp_valid,io_outputs_0_rsp_valid} != 2'b00) || (logic_rspPending && logic_rspNoHitValid)); + if(logic_rspNoHit_doIt) begin + io_input_rsp_valid = 1'b1; + end + end + + assign _zz_io_input_rsp_payload_last = logic_rspHits_1; + always @(*) begin + io_input_rsp_payload_last = _zz_io_input_rsp_payload_last_1; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_last = 1'b0; + if(when_BmbDecoder_l81) begin + io_input_rsp_payload_last = 1'b1; + end + if(logic_rspNoHit_singleBeatRsp) begin + io_input_rsp_payload_last = 1'b1; + end + end + end + + always @(*) begin + io_input_rsp_payload_fragment_source = _zz_io_input_rsp_payload_fragment_source; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_source = logic_rspNoHit_source; + end + end + + always @(*) begin + io_input_rsp_payload_fragment_opcode = _zz_io_input_rsp_payload_fragment_opcode; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_opcode = 1'b1; + end + end + + assign io_input_rsp_payload_fragment_data = _zz_io_input_rsp_payload_fragment_data; + always @(*) begin + io_input_rsp_payload_fragment_context = _zz_io_input_rsp_payload_fragment_context; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_context = logic_rspNoHit_context; + end + end + + assign when_BmbDecoder_l81 = (logic_rspNoHit_counter == 4'b0000); + assign io_input_rsp_fire_2 = (io_input_rsp_valid && io_input_rsp_ready); + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign io_outputs_1_rsp_ready = io_input_rsp_ready; + assign logic_cmdWait = ((logic_rspPending && (((logic_hitsS0_0 != logic_rspHits_0) || (logic_hitsS0_1 != logic_rspHits_1)) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + logic_rspPendingCounter <= 7'h0; + logic_rspNoHit_doIt <= 1'b0; + end else begin + logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); + if(when_BmbDecoder_l60) begin + logic_rspNoHit_doIt <= 1'b0; + end + if(when_BmbDecoder_l60_1) begin + logic_rspNoHit_doIt <= 1'b1; + end + end + end + + always @(posedge io_systemClk) begin + if(when_BmbDecoder_l56) begin + logic_rspHits_0 <= logic_hitsS0_0; + logic_rspHits_1 <= logic_hitsS0_1; + end + if(logic_input_fire_2) begin + logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); + end + if(logic_input_fire_3) begin + logic_rspNoHit_source <= logic_input_payload_fragment_source; + end + if(logic_input_fire_4) begin + logic_rspNoHit_context <= logic_input_payload_fragment_context; + end + if(logic_input_fire_5) begin + logic_rspNoHit_counter <= logic_input_payload_fragment_length[5 : 2]; + end + if(logic_rspNoHit_doIt) begin + if(io_input_rsp_fire_2) begin + logic_rspNoHit_counter <= (logic_rspNoHit_counter - 4'b0001); + end + end + end + + +endmodule + +module BmbArbiter_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_inputs_0_cmd_valid, + output io_inputs_0_cmd_ready, + input io_inputs_0_cmd_payload_last, + input [0:0] io_inputs_0_cmd_payload_fragment_opcode, + input [31:0] io_inputs_0_cmd_payload_fragment_address, + input [5:0] io_inputs_0_cmd_payload_fragment_length, + input [31:0] io_inputs_0_cmd_payload_fragment_data, + input [3:0] io_inputs_0_cmd_payload_fragment_mask, + input [0:0] io_inputs_0_cmd_payload_fragment_context, + output io_inputs_0_rsp_valid, + input io_inputs_0_rsp_ready, + output io_inputs_0_rsp_payload_last, + output [0:0] io_inputs_0_rsp_payload_fragment_opcode, + output [31:0] io_inputs_0_rsp_payload_fragment_data, + output [0:0] io_inputs_0_rsp_payload_fragment_context, + input io_inputs_1_cmd_valid, + output io_inputs_1_cmd_ready, + input io_inputs_1_cmd_payload_last, + input [0:0] io_inputs_1_cmd_payload_fragment_opcode, + input [31:0] io_inputs_1_cmd_payload_fragment_address, + input [5:0] io_inputs_1_cmd_payload_fragment_length, + input [31:0] io_inputs_1_cmd_payload_fragment_data, + input [3:0] io_inputs_1_cmd_payload_fragment_mask, + output io_inputs_1_rsp_valid, + input io_inputs_1_rsp_ready, + output io_inputs_1_rsp_payload_last, + output [0:0] io_inputs_1_rsp_payload_fragment_opcode, + output [31:0] io_inputs_1_rsp_payload_fragment_data, + output io_output_cmd_valid, + input io_output_cmd_ready, + output io_output_cmd_payload_last, + output [0:0] io_output_cmd_payload_fragment_source, + output [0:0] io_output_cmd_payload_fragment_opcode, + output [31:0] io_output_cmd_payload_fragment_address, + output [5:0] io_output_cmd_payload_fragment_length, + output [31:0] io_output_cmd_payload_fragment_data, + output [3:0] io_output_cmd_payload_fragment_mask, + output [0:0] io_output_cmd_payload_fragment_context, + input io_output_rsp_valid, + output io_output_rsp_ready, + input io_output_rsp_payload_last, + input [0:0] io_output_rsp_payload_fragment_source, + input [0:0] io_output_rsp_payload_fragment_opcode, + input [31:0] io_output_rsp_payload_fragment_data, + input [0:0] io_output_rsp_payload_fragment_context, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire memory_arbiter_io_inputs_0_ready; + wire memory_arbiter_io_inputs_1_ready; + wire memory_arbiter_io_output_valid; + wire memory_arbiter_io_output_payload_last; + wire [0:0] memory_arbiter_io_output_payload_fragment_source; + wire [0:0] memory_arbiter_io_output_payload_fragment_opcode; + wire [31:0] memory_arbiter_io_output_payload_fragment_address; + wire [5:0] memory_arbiter_io_output_payload_fragment_length; + wire [31:0] memory_arbiter_io_output_payload_fragment_data; + wire [3:0] memory_arbiter_io_output_payload_fragment_mask; + wire [0:0] memory_arbiter_io_output_payload_fragment_context; + wire [0:0] memory_arbiter_io_chosen; + wire [1:0] memory_arbiter_io_chosenOH; + wire [1:0] _zz_io_output_cmd_payload_fragment_source; + reg _zz_io_output_rsp_ready; + wire [0:0] memory_rspSel; + + assign _zz_io_output_cmd_payload_fragment_source = {memory_arbiter_io_output_payload_fragment_source,memory_arbiter_io_chosen}; + StreamArbiter_b62b14ffe6bb44e5a817b8d08e286c6b memory_arbiter ( + .io_inputs_0_valid (io_inputs_0_cmd_valid ), //i + .io_inputs_0_ready (memory_arbiter_io_inputs_0_ready ), //o + .io_inputs_0_payload_last (io_inputs_0_cmd_payload_last ), //i + .io_inputs_0_payload_fragment_source (1'b0 ), //i + .io_inputs_0_payload_fragment_opcode (io_inputs_0_cmd_payload_fragment_opcode ), //i + .io_inputs_0_payload_fragment_address (io_inputs_0_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_0_payload_fragment_length (io_inputs_0_cmd_payload_fragment_length[5:0] ), //i + .io_inputs_0_payload_fragment_data (io_inputs_0_cmd_payload_fragment_data[31:0] ), //i + .io_inputs_0_payload_fragment_mask (io_inputs_0_cmd_payload_fragment_mask[3:0] ), //i + .io_inputs_0_payload_fragment_context (io_inputs_0_cmd_payload_fragment_context ), //i + .io_inputs_1_valid (io_inputs_1_cmd_valid ), //i + .io_inputs_1_ready (memory_arbiter_io_inputs_1_ready ), //o + .io_inputs_1_payload_last (io_inputs_1_cmd_payload_last ), //i + .io_inputs_1_payload_fragment_source (1'b0 ), //i + .io_inputs_1_payload_fragment_opcode (io_inputs_1_cmd_payload_fragment_opcode ), //i + .io_inputs_1_payload_fragment_address (io_inputs_1_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_1_payload_fragment_length (io_inputs_1_cmd_payload_fragment_length[5:0] ), //i + .io_inputs_1_payload_fragment_data (io_inputs_1_cmd_payload_fragment_data[31:0] ), //i + .io_inputs_1_payload_fragment_mask (io_inputs_1_cmd_payload_fragment_mask[3:0] ), //i + .io_inputs_1_payload_fragment_context (1'b0 ), //i + .io_output_valid (memory_arbiter_io_output_valid ), //o + .io_output_ready (io_output_cmd_ready ), //i + .io_output_payload_last (memory_arbiter_io_output_payload_last ), //o + .io_output_payload_fragment_source (memory_arbiter_io_output_payload_fragment_source ), //o + .io_output_payload_fragment_opcode (memory_arbiter_io_output_payload_fragment_opcode ), //o + .io_output_payload_fragment_address (memory_arbiter_io_output_payload_fragment_address[31:0]), //o + .io_output_payload_fragment_length (memory_arbiter_io_output_payload_fragment_length[5:0] ), //o + .io_output_payload_fragment_data (memory_arbiter_io_output_payload_fragment_data[31:0] ), //o + .io_output_payload_fragment_mask (memory_arbiter_io_output_payload_fragment_mask[3:0] ), //o + .io_output_payload_fragment_context (memory_arbiter_io_output_payload_fragment_context ), //o + .io_chosen (memory_arbiter_io_chosen ), //o + .io_chosenOH (memory_arbiter_io_chosenOH[1:0] ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + always @(*) begin + case(memory_rspSel) + 1'b0 : _zz_io_output_rsp_ready = io_inputs_0_rsp_ready; + default : _zz_io_output_rsp_ready = io_inputs_1_rsp_ready; + endcase + end + + assign io_inputs_0_cmd_ready = memory_arbiter_io_inputs_0_ready; + assign io_inputs_1_cmd_ready = memory_arbiter_io_inputs_1_ready; + assign io_output_cmd_valid = memory_arbiter_io_output_valid; + assign io_output_cmd_payload_last = memory_arbiter_io_output_payload_last; + assign io_output_cmd_payload_fragment_opcode = memory_arbiter_io_output_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = memory_arbiter_io_output_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = memory_arbiter_io_output_payload_fragment_length; + assign io_output_cmd_payload_fragment_data = memory_arbiter_io_output_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = memory_arbiter_io_output_payload_fragment_mask; + assign io_output_cmd_payload_fragment_context = memory_arbiter_io_output_payload_fragment_context; + assign io_output_cmd_payload_fragment_source = _zz_io_output_cmd_payload_fragment_source[0:0]; + assign memory_rspSel = io_output_rsp_payload_fragment_source[0 : 0]; + assign io_inputs_0_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b0)); + assign io_inputs_0_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_0_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_0_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_inputs_0_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; + assign io_inputs_1_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b1)); + assign io_inputs_1_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_1_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_1_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_output_rsp_ready = _zz_io_output_rsp_ready; + +endmodule + +module BmbDecoder_1_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [31:0] io_input_cmd_payload_fragment_address, + input [5:0] io_input_cmd_payload_fragment_length, + output io_input_rsp_valid, + input io_input_rsp_ready, + output io_input_rsp_payload_last, + output [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output io_outputs_0_cmd_valid, + input io_outputs_0_cmd_ready, + output io_outputs_0_cmd_payload_last, + output [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output [31:0] io_outputs_0_cmd_payload_fragment_address, + output [5:0] io_outputs_0_cmd_payload_fragment_length, + input io_outputs_0_rsp_valid, + output io_outputs_0_rsp_ready, + input io_outputs_0_rsp_payload_last, + input [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input [31:0] io_outputs_0_rsp_payload_fragment_data +); + + + assign io_outputs_0_cmd_valid = io_input_cmd_valid; + assign io_input_cmd_ready = io_outputs_0_cmd_ready; + assign io_input_rsp_valid = io_outputs_0_rsp_valid; + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign io_outputs_0_cmd_payload_last = io_input_cmd_payload_last; + assign io_input_rsp_payload_last = io_outputs_0_rsp_payload_last; + assign io_outputs_0_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + +endmodule + +module BmbExclusiveMonitor_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [31:0] io_input_cmd_payload_fragment_address, + input [5:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_mask, + input [0:0] io_input_cmd_payload_fragment_context, + output io_input_rsp_valid, + input io_input_rsp_ready, + output io_input_rsp_payload_last, + output [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output [0:0] io_input_rsp_payload_fragment_context, + output io_output_cmd_valid, + input io_output_cmd_ready, + output io_output_cmd_payload_last, + output [0:0] io_output_cmd_payload_fragment_opcode, + output [31:0] io_output_cmd_payload_fragment_address, + output [5:0] io_output_cmd_payload_fragment_length, + output [31:0] io_output_cmd_payload_fragment_data, + output [3:0] io_output_cmd_payload_fragment_mask, + output [0:0] io_output_cmd_payload_fragment_context, + input io_output_rsp_valid, + output io_output_rsp_ready, + input io_output_rsp_payload_last, + input [0:0] io_output_rsp_payload_fragment_opcode, + input [31:0] io_output_rsp_payload_fragment_data, + input [0:0] io_output_rsp_payload_fragment_context +); + + + assign io_output_cmd_valid = io_input_cmd_valid; + assign io_input_cmd_ready = io_output_cmd_ready; + assign io_input_rsp_valid = io_output_rsp_valid; + assign io_output_rsp_ready = io_input_rsp_ready; + assign io_output_cmd_payload_last = io_input_cmd_payload_last; + assign io_input_rsp_payload_last = io_output_rsp_payload_last; + assign io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign io_output_cmd_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; + +endmodule + +module BmbDecoder_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [31:0] io_input_cmd_payload_fragment_address, + input [1:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_mask, + output reg io_input_rsp_valid, + input io_input_rsp_ready, + output reg io_input_rsp_payload_last, + output reg [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output reg io_outputs_0_cmd_valid, + input io_outputs_0_cmd_ready, + output io_outputs_0_cmd_payload_last, + output [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output [31:0] io_outputs_0_cmd_payload_fragment_address, + output [1:0] io_outputs_0_cmd_payload_fragment_length, + output [31:0] io_outputs_0_cmd_payload_fragment_data, + output [3:0] io_outputs_0_cmd_payload_fragment_mask, + input io_outputs_0_rsp_valid, + output io_outputs_0_rsp_ready, + input io_outputs_0_rsp_payload_last, + input [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input [31:0] io_outputs_0_rsp_payload_fragment_data, + input io_systemClk, + input debugCd_logic_outputReset +); + + wire [6:0] _zz_logic_rspPendingCounter; + wire [6:0] _zz_logic_rspPendingCounter_1; + wire [0:0] _zz_logic_rspPendingCounter_2; + wire [6:0] _zz_logic_rspPendingCounter_3; + wire [0:0] _zz_logic_rspPendingCounter_4; + wire logic_input_valid; + reg logic_input_ready; + wire logic_input_payload_last; + wire [0:0] logic_input_payload_fragment_opcode; + wire [31:0] logic_input_payload_fragment_address; + wire [1:0] logic_input_payload_fragment_length; + wire [31:0] logic_input_payload_fragment_data; + wire [3:0] logic_input_payload_fragment_mask; + wire logic_hitsS0_0; + wire logic_noHitS0; + wire _zz_io_outputs_0_cmd_payload_last; + reg [6:0] logic_rspPendingCounter; + wire logic_input_fire; + wire io_input_rsp_fire; + wire logic_cmdWait; + wire when_BmbDecoder_l56; + reg logic_rspHits_0; + wire logic_rspPending; + wire logic_rspNoHitValid; + reg logic_rspNoHit_doIt; + wire io_input_rsp_fire_1; + wire when_BmbDecoder_l60; + wire logic_input_fire_1; + wire when_BmbDecoder_l60_1; + wire logic_input_fire_2; + reg logic_rspNoHit_singleBeatRsp; + wire logic_input_fire_3; + wire logic_input_fire_4; + wire logic_input_fire_5; + + assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); + assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); + assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; + assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; + assign logic_input_valid = io_input_cmd_valid; + assign io_input_cmd_ready = logic_input_ready; + assign logic_input_payload_last = io_input_cmd_payload_last; + assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign logic_noHitS0 = (! (logic_hitsS0_0 != 1'b0)); + assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 32'h00000fff)) == 32'h10b80000); + always @(*) begin + io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); + if(logic_cmdWait) begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; + assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; + assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + always @(*) begin + logic_input_ready = (((logic_hitsS0_0 && io_outputs_0_cmd_ready) != 1'b0) || logic_noHitS0); + if(logic_cmdWait) begin + logic_input_ready = 1'b0; + end + end + + assign logic_input_fire = (logic_input_valid && logic_input_ready); + assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); + assign logic_rspPending = (logic_rspPendingCounter != 7'h0); + assign logic_rspNoHitValid = (! (logic_rspHits_0 != 1'b0)); + assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); + assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); + assign when_BmbDecoder_l60_1 = ((logic_input_fire_1 && logic_noHitS0) && logic_input_payload_last); + assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); + always @(*) begin + io_input_rsp_valid = ((io_outputs_0_rsp_valid != 1'b0) || (logic_rspPending && logic_rspNoHitValid)); + if(logic_rspNoHit_doIt) begin + io_input_rsp_valid = 1'b1; + end + end + + always @(*) begin + io_input_rsp_payload_last = io_outputs_0_rsp_payload_last; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_last = 1'b1; + end + end + + always @(*) begin + io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_opcode = 1'b1; + end + end + + assign io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign logic_cmdWait = ((logic_rspPending && ((logic_hitsS0_0 != logic_rspHits_0) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); + always @(posedge io_systemClk) begin + if(debugCd_logic_outputReset) begin + logic_rspPendingCounter <= 7'h0; + logic_rspNoHit_doIt <= 1'b0; + end else begin + logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); + if(when_BmbDecoder_l60) begin + logic_rspNoHit_doIt <= 1'b0; + end + if(when_BmbDecoder_l60_1) begin + logic_rspNoHit_doIt <= 1'b1; + end + end + end + + always @(posedge io_systemClk) begin + if(when_BmbDecoder_l56) begin + logic_rspHits_0 <= logic_hitsS0_0; + end + if(logic_input_fire_2) begin + logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); + end + end + + +endmodule + +module BufferCC_4_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_dataIn, + output io_dataOut, + input io_systemClk, + input system_cores_0_debugReset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge io_systemClk or posedge system_cores_0_debugReset) begin + if(system_cores_0_debugReset) begin + buffers_0 <= 1'b1; + buffers_1 <= 1'b1; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module SystemDebugger_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_remote_cmd_valid, + output io_remote_cmd_ready, + input io_remote_cmd_payload_last, + input [0:0] io_remote_cmd_payload_fragment, + output io_remote_rsp_valid, + input io_remote_rsp_ready, + output io_remote_rsp_payload_error, + output [31:0] io_remote_rsp_payload_data, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output io_mem_cmd_payload_wr, + output [1:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload, + input io_systemClk, + input debugCd_logic_outputReset +); + + reg [66:0] dispatcher_dataShifter; + reg dispatcher_dataLoaded; + reg [7:0] dispatcher_headerShifter; + wire [7:0] dispatcher_header; + reg dispatcher_headerLoaded; + reg [2:0] dispatcher_counter; + wire when_Fragment_l346; + wire when_Fragment_l349; + wire [66:0] _zz_io_mem_cmd_payload_address; + wire io_mem_cmd_isStall; + wire when_Fragment_l372; + + assign dispatcher_header = dispatcher_headerShifter[7 : 0]; + assign when_Fragment_l346 = (dispatcher_headerLoaded == 1'b0); + assign when_Fragment_l349 = (dispatcher_counter == 3'b111); + assign io_remote_cmd_ready = (! dispatcher_dataLoaded); + assign _zz_io_mem_cmd_payload_address = dispatcher_dataShifter[66 : 0]; + assign io_mem_cmd_payload_address = _zz_io_mem_cmd_payload_address[31 : 0]; + assign io_mem_cmd_payload_data = _zz_io_mem_cmd_payload_address[63 : 32]; + assign io_mem_cmd_payload_wr = _zz_io_mem_cmd_payload_address[64]; + assign io_mem_cmd_payload_size = _zz_io_mem_cmd_payload_address[66 : 65]; + assign io_mem_cmd_valid = (dispatcher_dataLoaded && (dispatcher_header == 8'h0)); + assign io_mem_cmd_isStall = (io_mem_cmd_valid && (! io_mem_cmd_ready)); + assign when_Fragment_l372 = ((dispatcher_headerLoaded && dispatcher_dataLoaded) && (! io_mem_cmd_isStall)); + assign io_remote_rsp_valid = io_mem_rsp_valid; + assign io_remote_rsp_payload_error = 1'b0; + assign io_remote_rsp_payload_data = io_mem_rsp_payload; + always @(posedge io_systemClk) begin + if(debugCd_logic_outputReset) begin + dispatcher_dataLoaded <= 1'b0; + dispatcher_headerLoaded <= 1'b0; + dispatcher_counter <= 3'b000; + end else begin + if(io_remote_cmd_valid) begin + if(when_Fragment_l346) begin + dispatcher_counter <= (dispatcher_counter + 3'b001); + if(when_Fragment_l349) begin + dispatcher_headerLoaded <= 1'b1; + end + end + if(io_remote_cmd_payload_last) begin + dispatcher_headerLoaded <= 1'b1; + dispatcher_dataLoaded <= 1'b1; + dispatcher_counter <= 3'b000; + end + end + if(when_Fragment_l372) begin + dispatcher_headerLoaded <= 1'b0; + dispatcher_dataLoaded <= 1'b0; + end + end + end + + always @(posedge io_systemClk) begin + if(io_remote_cmd_valid) begin + if(when_Fragment_l346) begin + dispatcher_headerShifter <= ({io_remote_cmd_payload_fragment,dispatcher_headerShifter} >>> 1); + end else begin + dispatcher_dataShifter <= ({io_remote_cmd_payload_fragment,dispatcher_dataShifter} >>> 1); + end + end + end + + +endmodule + +module JtagBridgeNoTap_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_ctrl_tdi, + input io_ctrl_enable, + input io_ctrl_capture, + input io_ctrl_shift, + input io_ctrl_update, + input io_ctrl_reset, + output io_ctrl_tdo, + output io_remote_cmd_valid, + input io_remote_cmd_ready, + output io_remote_cmd_payload_last, + output [0:0] io_remote_cmd_payload_fragment, + input io_remote_rsp_valid, + output io_remote_rsp_ready, + input io_remote_rsp_payload_error, + input [31:0] io_remote_rsp_payload_data, + input io_systemClk, + input debugCd_logic_outputReset, + input jtagCtrl_tck +); + + wire flowCCByToggle_1_io_output_valid; + wire flowCCByToggle_1_io_output_payload_last; + wire [0:0] flowCCByToggle_1_io_output_payload_fragment; + wire system_cmd_valid; + wire system_cmd_payload_last; + wire [0:0] system_cmd_payload_fragment; + wire system_cmd_toStream_valid; + wire system_cmd_toStream_ready; + wire system_cmd_toStream_payload_last; + wire [0:0] system_cmd_toStream_payload_fragment; + (* async_reg = "true" *) reg system_rsp_valid; + (* async_reg = "true" *) reg system_rsp_payload_error; + (* async_reg = "true" *) reg [31:0] system_rsp_payload_data; + wire io_remote_rsp_fire; + wire jtag_wrapper_ctrl_tdi; + wire jtag_wrapper_ctrl_enable; + wire jtag_wrapper_ctrl_capture; + wire jtag_wrapper_ctrl_shift; + wire jtag_wrapper_ctrl_update; + wire jtag_wrapper_ctrl_reset; + reg jtag_wrapper_ctrl_tdo; + reg [1:0] jtag_wrapper_header; + wire [1:0] jtag_wrapper_headerNext; + reg [0:0] jtag_wrapper_counter; + reg jtag_wrapper_done; + reg jtag_wrapper_sendCapture; + reg jtag_wrapper_sendShift; + reg jtag_wrapper_sendUpdate; + wire when_JtagTapInstructions_l183; + wire when_JtagTapInstructions_l186; + wire jtag_writeArea_ctrl_tdi; + wire jtag_writeArea_ctrl_enable; + wire jtag_writeArea_ctrl_capture; + wire jtag_writeArea_ctrl_shift; + wire jtag_writeArea_ctrl_update; + wire jtag_writeArea_ctrl_reset; + wire jtag_writeArea_ctrl_tdo; + wire jtag_writeArea_source_valid; + wire jtag_writeArea_source_payload_last; + wire [0:0] jtag_writeArea_source_payload_fragment; + reg jtag_writeArea_valid; + reg jtag_writeArea_data; + wire when_JtagTapInstructions_l209; + wire jtag_readArea_ctrl_tdi; + wire jtag_readArea_ctrl_enable; + wire jtag_readArea_ctrl_capture; + wire jtag_readArea_ctrl_shift; + wire jtag_readArea_ctrl_update; + wire jtag_readArea_ctrl_reset; + wire jtag_readArea_ctrl_tdo; + reg [33:0] jtag_readArea_full_shifter; + wire when_JtagTapInstructions_l209_1; + + FlowCCByToggle_b62b14ffe6bb44e5a817b8d08e286c6b flowCCByToggle_1 ( + .io_input_valid (jtag_writeArea_source_valid ), //i + .io_input_payload_last (jtag_writeArea_source_payload_last ), //i + .io_input_payload_fragment (jtag_writeArea_source_payload_fragment ), //i + .io_output_valid (flowCCByToggle_1_io_output_valid ), //o + .io_output_payload_last (flowCCByToggle_1_io_output_payload_last ), //o + .io_output_payload_fragment (flowCCByToggle_1_io_output_payload_fragment), //o + .jtagCtrl_tck (jtagCtrl_tck ), //i + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i + ); + assign system_cmd_toStream_valid = system_cmd_valid; + assign system_cmd_toStream_payload_last = system_cmd_payload_last; + assign system_cmd_toStream_payload_fragment = system_cmd_payload_fragment; + assign io_remote_cmd_valid = system_cmd_toStream_valid; + assign system_cmd_toStream_ready = io_remote_cmd_ready; + assign io_remote_cmd_payload_last = system_cmd_toStream_payload_last; + assign io_remote_cmd_payload_fragment = system_cmd_toStream_payload_fragment; + assign io_remote_rsp_fire = (io_remote_rsp_valid && io_remote_rsp_ready); + assign io_remote_rsp_ready = 1'b1; + assign jtag_wrapper_headerNext = ({jtag_wrapper_ctrl_tdi,jtag_wrapper_header} >>> 1); + always @(*) begin + jtag_wrapper_sendCapture = 1'b0; + if(jtag_wrapper_ctrl_enable) begin + if(jtag_wrapper_ctrl_shift) begin + if(when_JtagTapInstructions_l183) begin + if(when_JtagTapInstructions_l186) begin + jtag_wrapper_sendCapture = 1'b1; + end + end + end + end + end + + always @(*) begin + jtag_wrapper_sendShift = 1'b0; + if(jtag_wrapper_ctrl_enable) begin + if(jtag_wrapper_ctrl_shift) begin + if(!when_JtagTapInstructions_l183) begin + jtag_wrapper_sendShift = 1'b1; + end + end + end + end + + always @(*) begin + jtag_wrapper_sendUpdate = 1'b0; + if(jtag_wrapper_ctrl_enable) begin + if(jtag_wrapper_ctrl_update) begin + jtag_wrapper_sendUpdate = 1'b1; + end + end + end + + assign when_JtagTapInstructions_l183 = (! jtag_wrapper_done); + assign when_JtagTapInstructions_l186 = (jtag_wrapper_counter == 1'b1); + always @(*) begin + jtag_wrapper_ctrl_tdo = 1'b0; + if(when_JtagTapInstructions_l209) begin + jtag_wrapper_ctrl_tdo = jtag_writeArea_ctrl_tdo; + end + if(when_JtagTapInstructions_l209_1) begin + jtag_wrapper_ctrl_tdo = jtag_readArea_ctrl_tdo; + end + end + + assign jtag_wrapper_ctrl_tdi = io_ctrl_tdi; + assign jtag_wrapper_ctrl_enable = io_ctrl_enable; + assign jtag_wrapper_ctrl_capture = io_ctrl_capture; + assign jtag_wrapper_ctrl_shift = io_ctrl_shift; + assign jtag_wrapper_ctrl_update = io_ctrl_update; + assign jtag_wrapper_ctrl_reset = io_ctrl_reset; + assign io_ctrl_tdo = jtag_wrapper_ctrl_tdo; + assign jtag_writeArea_source_valid = jtag_writeArea_valid; + assign jtag_writeArea_source_payload_last = (! (jtag_writeArea_ctrl_enable && jtag_writeArea_ctrl_shift)); + assign jtag_writeArea_source_payload_fragment[0] = jtag_writeArea_data; + assign system_cmd_valid = flowCCByToggle_1_io_output_valid; + assign system_cmd_payload_last = flowCCByToggle_1_io_output_payload_last; + assign system_cmd_payload_fragment = flowCCByToggle_1_io_output_payload_fragment; + assign jtag_writeArea_ctrl_tdo = 1'b0; + assign when_JtagTapInstructions_l209 = (jtag_wrapper_header == 2'b00); + assign jtag_writeArea_ctrl_tdi = jtag_wrapper_ctrl_tdi; + assign jtag_writeArea_ctrl_enable = 1'b1; + assign jtag_writeArea_ctrl_capture = ((jtag_wrapper_headerNext == 2'b00) && jtag_wrapper_sendCapture); + assign jtag_writeArea_ctrl_shift = (when_JtagTapInstructions_l209 && jtag_wrapper_sendShift); + assign jtag_writeArea_ctrl_update = (when_JtagTapInstructions_l209 && jtag_wrapper_sendUpdate); + assign jtag_writeArea_ctrl_reset = jtag_wrapper_ctrl_reset; + assign jtag_readArea_ctrl_tdo = jtag_readArea_full_shifter[0]; + assign when_JtagTapInstructions_l209_1 = (jtag_wrapper_header == 2'b01); + assign jtag_readArea_ctrl_tdi = jtag_wrapper_ctrl_tdi; + assign jtag_readArea_ctrl_enable = 1'b1; + assign jtag_readArea_ctrl_capture = ((jtag_wrapper_headerNext == 2'b01) && jtag_wrapper_sendCapture); + assign jtag_readArea_ctrl_shift = (when_JtagTapInstructions_l209_1 && jtag_wrapper_sendShift); + assign jtag_readArea_ctrl_update = (when_JtagTapInstructions_l209_1 && jtag_wrapper_sendUpdate); + assign jtag_readArea_ctrl_reset = jtag_wrapper_ctrl_reset; + always @(posedge io_systemClk) begin + if(io_remote_cmd_valid) begin + system_rsp_valid <= 1'b0; + end + if(io_remote_rsp_fire) begin + system_rsp_valid <= 1'b1; + system_rsp_payload_error <= io_remote_rsp_payload_error; + system_rsp_payload_data <= io_remote_rsp_payload_data; + end + end + + always @(posedge jtagCtrl_tck) begin + if(jtag_wrapper_ctrl_enable) begin + if(jtag_wrapper_ctrl_capture) begin + jtag_wrapper_done <= 1'b0; + jtag_wrapper_counter <= 1'b0; + end + if(jtag_wrapper_ctrl_shift) begin + if(when_JtagTapInstructions_l183) begin + jtag_wrapper_counter <= (jtag_wrapper_counter + 1'b1); + jtag_wrapper_header <= jtag_wrapper_headerNext; + if(when_JtagTapInstructions_l186) begin + jtag_wrapper_done <= 1'b1; + end + end + end + end + jtag_writeArea_valid <= (jtag_writeArea_ctrl_enable && jtag_writeArea_ctrl_shift); + jtag_writeArea_data <= jtag_writeArea_ctrl_tdi; + if(jtag_readArea_ctrl_enable) begin + if(jtag_readArea_ctrl_capture) begin + jtag_readArea_full_shifter <= {{system_rsp_payload_data,system_rsp_payload_error},system_rsp_valid}; + end + if(jtag_readArea_ctrl_shift) begin + jtag_readArea_full_shifter <= ({jtag_readArea_ctrl_tdi,jtag_readArea_full_shifter} >>> 1); + end + end + end + + +endmodule + +module VexRiscv_b62b14ffe6bb44e5a817b8d08e286c6b ( + output dBus_cmd_valid, + input dBus_cmd_ready, + output dBus_cmd_payload_wr, + output dBus_cmd_payload_uncached, + output [31:0] dBus_cmd_payload_address, + output [31:0] dBus_cmd_payload_data, + output [3:0] dBus_cmd_payload_mask, + output [2:0] dBus_cmd_payload_size, + output dBus_cmd_payload_last, + input dBus_rsp_valid, + input dBus_rsp_payload_last, + input [31:0] dBus_rsp_payload_data, + input dBus_rsp_payload_error, + input timerInterrupt, + input externalInterrupt, + input softwareInterrupt, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output iBus_cmd_valid, + input iBus_cmd_ready, + output reg [31:0] iBus_cmd_payload_address, + output [2:0] iBus_cmd_payload_size, + input iBus_rsp_valid, + input [31:0] iBus_rsp_payload_data, + input iBus_rsp_payload_error, + input io_systemClk, + input systemCd_logic_outputReset, + input debugCd_logic_outputReset +); + localparam ShiftCtrlEnum_DISABLE_1 = 2'd0; + localparam ShiftCtrlEnum_SLL_1 = 2'd1; + localparam ShiftCtrlEnum_SRL_1 = 2'd2; + localparam ShiftCtrlEnum_SRA_1 = 2'd3; + localparam BranchCtrlEnum_INC = 2'd0; + localparam BranchCtrlEnum_B = 2'd1; + localparam BranchCtrlEnum_JAL = 2'd2; + localparam BranchCtrlEnum_JALR = 2'd3; + localparam EnvCtrlEnum_NONE = 2'd0; + localparam EnvCtrlEnum_XRET = 2'd1; + localparam EnvCtrlEnum_ECALL = 2'd2; + localparam EnvCtrlEnum_EBREAK = 2'd3; + localparam AluBitwiseCtrlEnum_XOR_1 = 2'd0; + localparam AluBitwiseCtrlEnum_OR_1 = 2'd1; + localparam AluBitwiseCtrlEnum_AND_1 = 2'd2; + localparam AluCtrlEnum_ADD_SUB = 2'd0; + localparam AluCtrlEnum_SLT_SLTU = 2'd1; + localparam AluCtrlEnum_BITWISE = 2'd2; + localparam Src2CtrlEnum_RS = 2'd0; + localparam Src2CtrlEnum_IMI = 2'd1; + localparam Src2CtrlEnum_IMS = 2'd2; + localparam Src2CtrlEnum_PC = 2'd3; + localparam Src1CtrlEnum_RS = 2'd0; + localparam Src1CtrlEnum_IMU = 2'd1; + localparam Src1CtrlEnum_PC_INCREMENT = 2'd2; + localparam Src1CtrlEnum_URS1 = 2'd3; + + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + wire dataCache_1_io_cpu_execute_isValid; + wire [31:0] dataCache_1_io_cpu_execute_address; + wire dataCache_1_io_cpu_memory_isValid; + reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; + reg dataCache_1_io_cpu_writeBack_isValid; + wire dataCache_1_io_cpu_writeBack_isUser; + wire [31:0] dataCache_1_io_cpu_writeBack_storeData; + wire [31:0] dataCache_1_io_cpu_writeBack_address; + wire dataCache_1_io_cpu_writeBack_fence_SW; + wire dataCache_1_io_cpu_writeBack_fence_SR; + wire dataCache_1_io_cpu_writeBack_fence_SO; + wire dataCache_1_io_cpu_writeBack_fence_SI; + wire dataCache_1_io_cpu_writeBack_fence_PW; + wire dataCache_1_io_cpu_writeBack_fence_PR; + wire dataCache_1_io_cpu_writeBack_fence_PO; + wire dataCache_1_io_cpu_writeBack_fence_PI; + wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; + wire dataCache_1_io_cpu_flush_valid; + wire dataCache_1_io_cpu_flush_payload_singleLine; + wire [5:0] dataCache_1_io_cpu_flush_payload_lineId; + wire dataCache_1_io_mem_cmd_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_writeBack_exclusiveOk; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_size; + wire dataCache_1_io_mem_cmd_payload_last; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [13:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [7:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [1:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [2:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_4; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [25:0] _zz_io_cpu_flush_payload_lineId; + wire [25:0] _zz_io_cpu_flush_payload_lineId_1; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; + wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_1; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_2; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_3; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_4; + wire _zz__zz_decode_BRANCH_CTRL_2_5; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_6; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_7; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_8; + wire _zz__zz_decode_BRANCH_CTRL_2_9; + wire _zz__zz_decode_BRANCH_CTRL_2_10; + wire [26:0] _zz__zz_decode_BRANCH_CTRL_2_11; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_12; + wire _zz__zz_decode_BRANCH_CTRL_2_13; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_14; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_15; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_16; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_17; + wire [22:0] _zz__zz_decode_BRANCH_CTRL_2_18; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_19; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_20; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_21; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_22; + wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_23; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_24; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_25; + wire _zz__zz_decode_BRANCH_CTRL_2_26; + wire _zz__zz_decode_BRANCH_CTRL_2_27; + wire _zz__zz_decode_BRANCH_CTRL_2_28; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_29; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_30; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_31; + wire _zz__zz_decode_BRANCH_CTRL_2_32; + wire [18:0] _zz__zz_decode_BRANCH_CTRL_2_33; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_34; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_35; + wire _zz__zz_decode_BRANCH_CTRL_2_36; + wire _zz__zz_decode_BRANCH_CTRL_2_37; + wire _zz__zz_decode_BRANCH_CTRL_2_38; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_39; + wire _zz__zz_decode_BRANCH_CTRL_2_40; + wire [15:0] _zz__zz_decode_BRANCH_CTRL_2_41; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_42; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_43; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_44; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_45; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_46; + wire _zz__zz_decode_BRANCH_CTRL_2_47; + wire _zz__zz_decode_BRANCH_CTRL_2_48; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_49; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_50; + wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_51; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_52; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_53; + wire _zz__zz_decode_BRANCH_CTRL_2_54; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_55; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_56; + wire _zz__zz_decode_BRANCH_CTRL_2_57; + wire [12:0] _zz__zz_decode_BRANCH_CTRL_2_58; + wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_59; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_60; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_61; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_62; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_63; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_64; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_65; + wire _zz__zz_decode_BRANCH_CTRL_2_66; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_67; + wire _zz__zz_decode_BRANCH_CTRL_2_68; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_69; + wire _zz__zz_decode_BRANCH_CTRL_2_70; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_71; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_72; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_73; + wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_74; + wire _zz__zz_decode_BRANCH_CTRL_2_75; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_76; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_77; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_78; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_79; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_80; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_81; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_82; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_83; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_84; + wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_85; + wire _zz__zz_decode_BRANCH_CTRL_2_86; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_87; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_88; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_89; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_90; + wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_91; + wire _zz__zz_decode_BRANCH_CTRL_2_92; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_93; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_94; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_95; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_96; + wire [9:0] _zz__zz_decode_BRANCH_CTRL_2_97; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_98; + wire _zz__zz_decode_BRANCH_CTRL_2_99; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_100; + wire _zz__zz_decode_BRANCH_CTRL_2_101; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_102; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_103; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_104; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_105; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_106; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_107; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_108; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_109; + wire [6:0] _zz__zz_decode_BRANCH_CTRL_2_110; + wire _zz__zz_decode_BRANCH_CTRL_2_111; + wire _zz__zz_decode_BRANCH_CTRL_2_112; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_113; + wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_114; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_115; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_116; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_117; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_118; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_119; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_120; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_121; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_122; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_123; + wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_124; + wire _zz__zz_decode_BRANCH_CTRL_2_125; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_126; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_127; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_128; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_129; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_130; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_131; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_132; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_133; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_134; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_135; + wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_136; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_137; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_138; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_139; + wire _zz__zz_decode_BRANCH_CTRL_2_140; + wire _zz__zz_decode_BRANCH_CTRL_2_141; + wire _zz__zz_decode_BRANCH_CTRL_2_142; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_143; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_144; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_decode_SRC1_1; + wire [4:0] _zz__zz_decode_SRC1_1_1; + wire [11:0] _zz__zz_decode_SRC2_4; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_decode_RS2_2; + wire [31:0] _zz__zz_decode_RS2_2_1; + wire [5:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext; + wire [0:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_2; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_3; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_4; + wire [0:0] _zz_memory_MulDivIterativePlugin_div_result_5; + wire [32:0] _zz_memory_MulDivIterativePlugin_rs1_2; + wire [0:0] _zz_memory_MulDivIterativePlugin_rs1_3; + wire [31:0] _zz_memory_MulDivIterativePlugin_rs2_1; + wire [0:0] _zz_memory_MulDivIterativePlugin_rs2_2; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire _zz_when; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire [51:0] memory_MUL_LOW; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [31:0] execute_MEMORY_VIRTUAL_ADDRESS; + wire [31:0] memory_MEMORY_STORE_DATA_RF; + wire [31:0] execute_MEMORY_STORE_DATA_RF; + wire decode_DO_EBREAK; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire [31:0] decode_SRC2; + wire [31:0] decode_SRC1; + wire decode_SRC2_FORCE_ZERO; + wire [1:0] decode_BRANCH_CTRL; + wire [1:0] _zz_decode_BRANCH_CTRL; + wire [1:0] _zz_decode_to_execute_BRANCH_CTRL; + wire [1:0] _zz_decode_to_execute_BRANCH_CTRL_1; + wire [1:0] _zz_memory_to_writeBack_ENV_CTRL; + wire [1:0] _zz_memory_to_writeBack_ENV_CTRL_1; + wire [1:0] _zz_execute_to_memory_ENV_CTRL; + wire [1:0] _zz_execute_to_memory_ENV_CTRL_1; + wire [1:0] decode_ENV_CTRL; + wire [1:0] _zz_decode_ENV_CTRL; + wire [1:0] _zz_decode_to_execute_ENV_CTRL; + wire [1:0] _zz_decode_to_execute_ENV_CTRL_1; + wire decode_IS_CSR; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire decode_IS_MUL; + wire [1:0] _zz_execute_to_memory_SHIFT_CTRL; + wire [1:0] _zz_execute_to_memory_SHIFT_CTRL_1; + wire [1:0] decode_SHIFT_CTRL; + wire [1:0] _zz_decode_SHIFT_CTRL; + wire [1:0] _zz_decode_to_execute_SHIFT_CTRL; + wire [1:0] _zz_decode_to_execute_SHIFT_CTRL_1; + wire [1:0] decode_ALU_BITWISE_CTRL; + wire [1:0] _zz_decode_ALU_BITWISE_CTRL; + wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire [1:0] decode_ALU_CTRL; + wire [1:0] _zz_decode_ALU_CTRL; + wire [1:0] _zz_decode_to_execute_ALU_CTRL; + wire [1:0] _zz_decode_to_execute_ALU_CTRL_1; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + wire [1:0] execute_BRANCH_CTRL; + wire [1:0] _zz_execute_BRANCH_CTRL; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire [1:0] memory_ENV_CTRL; + wire [1:0] _zz_memory_ENV_CTRL; + wire [1:0] execute_ENV_CTRL; + wire [1:0] _zz_execute_ENV_CTRL; + wire [1:0] writeBack_ENV_CTRL; + wire [1:0] _zz_writeBack_ENV_CTRL; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + wire execute_IS_MUL; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_decode_RS2; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_decode_RS2_1; + wire [1:0] memory_SHIFT_CTRL; + wire [1:0] _zz_memory_SHIFT_CTRL; + wire [1:0] execute_SHIFT_CTRL; + wire [1:0] _zz_execute_SHIFT_CTRL; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_decode_SRC2; + wire [31:0] _zz_decode_SRC2_1; + wire [1:0] decode_SRC2_CTRL; + wire [1:0] _zz_decode_SRC2_CTRL; + wire [31:0] _zz_decode_SRC1; + wire [1:0] decode_SRC1_CTRL; + wire [1:0] _zz_decode_SRC1_CTRL; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire [1:0] execute_ALU_CTRL; + wire [1:0] _zz_execute_ALU_CTRL; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire [1:0] execute_ALU_BITWISE_CTRL; + wire [1:0] _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire [1:0] _zz_decode_BRANCH_CTRL_1; + wire [1:0] _zz_decode_ENV_CTRL_1; + wire [1:0] _zz_decode_SHIFT_CTRL_1; + wire [1:0] _zz_decode_ALU_BITWISE_CTRL_1; + wire [1:0] _zz_decode_SRC2_CTRL_1; + wire [1:0] _zz_decode_ALU_CTRL_1; + wire [1:0] _zz_decode_SRC1_CTRL_1; + reg [31:0] _zz_decode_RS2_2; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_MEMORY_STORE_DATA_RF; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire memory_MEMORY_ENABLE; + wire [31:0] memory_MEMORY_VIRTUAL_ADDRESS; + wire execute_MEMORY_FORCE_CONSTISTENCY; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_MANAGMENT; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; + wire [31:0] decode_PC; + wire [31:0] decode_INSTRUCTION; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + reg decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + wire IBusCachedPlugin_forceNoDecodeCond; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_isPaging; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_isPaging; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + reg _zz_when_DBusCachedPlugin_l393; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; + wire CsrPlugin_inWfi /* verilator public */ ; + reg CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + reg CsrPlugin_allowEbreakException; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg BranchPlugin_inDebugNoFetchFlag; + reg IBusCachedPlugin_injectionPort_valid; + reg IBusCachedPlugin_injectionPort_ready; + wire [31:0] IBusCachedPlugin_injectionPort_payload; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l134; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l134_1; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l161; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l243; + wire IBusCachedPlugin_injector_decodeInput_valid; + wire IBusCachedPlugin_injector_decodeInput_ready; + wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_pc; + wire IBusCachedPlugin_injector_decodeInput_payload_rsp_error; + wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + wire IBusCachedPlugin_injector_decodeInput_payload_isRvc; + reg _zz_IBusCachedPlugin_injector_decodeInput_valid; + reg [31:0] _zz_IBusCachedPlugin_injector_decodeInput_payload_pc; + reg _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error; + reg [31:0] _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + reg _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc; + wire when_Fetcher_l323; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l332; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l332_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l332_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l332_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire when_Fetcher_l332_4; + reg IBusCachedPlugin_injector_nextPcCalc_valids_5; + wire when_Fetcher_l332_5; + reg [31:0] IBusCachedPlugin_injector_formal_rawInDecode; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + reg dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_rValid; + reg dataCache_1_io_mem_cmd_rData_wr; + reg dataCache_1_io_mem_cmd_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_rData_size; + reg dataCache_1_io_mem_cmd_rData_last; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire when_Stream_l368; + reg dBus_rsp_regNext_valid; + reg dBus_rsp_regNext_payload_last; + reg [31:0] dBus_rsp_regNext_payload_data; + reg dBus_rsp_regNext_payload_error; + reg [31:0] DBusCachedPlugin_rspCounter; + wire when_DBusCachedPlugin_l308; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; + wire dataCache_1_io_cpu_flush_isStall; + wire when_DBusCachedPlugin_l350; + wire when_DBusCachedPlugin_l366; + wire when_DBusCachedPlugin_l393; + wire when_DBusCachedPlugin_l446; + wire when_DBusCachedPlugin_l466; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire [31:0] writeBack_DBusCachedPlugin_rspRf; + wire [1:0] switch_Misc_l210; + wire _zz_writeBack_DBusCachedPlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; + wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire when_DBusCachedPlugin_l492; + wire [32:0] _zz_decode_BRANCH_CTRL_2; + wire _zz_decode_BRANCH_CTRL_3; + wire _zz_decode_BRANCH_CTRL_4; + wire _zz_decode_BRANCH_CTRL_5; + wire _zz_decode_BRANCH_CTRL_6; + wire _zz_decode_BRANCH_CTRL_7; + wire _zz_decode_BRANCH_CTRL_8; + wire [1:0] _zz_decode_SRC1_CTRL_2; + wire [1:0] _zz_decode_ALU_CTRL_2; + wire [1:0] _zz_decode_SRC2_CTRL_2; + wire [1:0] _zz_decode_ALU_BITWISE_CTRL_2; + wire [1:0] _zz_decode_SHIFT_CTRL_2; + wire [1:0] _zz_decode_ENV_CTRL_2; + wire [1:0] _zz_decode_BRANCH_CTRL_9; + wire when_RegFilePlugin_l63; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_2; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_decode_SRC1_1; + wire _zz_decode_SRC2_2; + reg [19:0] _zz_decode_SRC2_3; + wire _zz_decode_SRC2_4; + reg [19:0] _zz_decode_SRC2_5; + reg [31:0] _zz_decode_SRC2_6; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_decode_RS2_3; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + reg [0:0] execute_MulPlugin_delayLogic_counter; + wire when_MulPlugin_l65; + wire when_MulPlugin_l70; + wire [1:0] switch_MulPlugin_l87; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + reg [31:0] execute_MulPlugin_withOuputBuffer_mul_ll; + reg [33:0] execute_MulPlugin_withOuputBuffer_mul_lh; + reg [33:0] execute_MulPlugin_withOuputBuffer_mul_hl; + reg [33:0] execute_MulPlugin_withOuputBuffer_mul_hh; + wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; + reg [32:0] memory_MulDivIterativePlugin_rs1; + reg [31:0] memory_MulDivIterativePlugin_rs2; + reg [64:0] memory_MulDivIterativePlugin_accumulator; + wire memory_MulDivIterativePlugin_frontendOk; + reg memory_MulDivIterativePlugin_div_needRevert; + reg memory_MulDivIterativePlugin_div_counter_willIncrement; + reg memory_MulDivIterativePlugin_div_counter_willClear; + reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext; + reg [5:0] memory_MulDivIterativePlugin_div_counter_value; + wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; + wire memory_MulDivIterativePlugin_div_counter_willOverflow; + reg memory_MulDivIterativePlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; + reg [31:0] memory_MulDivIterativePlugin_div_result; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_MulDivIterativePlugin_rs2; + wire _zz_memory_MulDivIterativePlugin_rs1; + reg [32:0] _zz_memory_MulDivIterativePlugin_rs1_1; + reg [1:0] CsrPlugin_misa_base; + reg [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle; + reg [63:0] CsrPlugin_minstret; + wire _zz_when_CsrPlugin_l965; + wire _zz_when_CsrPlugin_l965_1; + wire _zz_when_CsrPlugin_l965_2; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire when_CsrPlugin_l922; + wire when_CsrPlugin_l922_1; + wire when_CsrPlugin_l922_2; + wire when_CsrPlugin_l922_3; + wire when_CsrPlugin_l935; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l959; + wire when_CsrPlugin_l965; + wire when_CsrPlugin_l965_1; + wire when_CsrPlugin_l965_2; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l993; + wire when_CsrPlugin_l993_1; + wire when_CsrPlugin_l993_2; + wire when_CsrPlugin_l998; + reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l1004; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1032; + wire when_CsrPlugin_l1077; + wire [1:0] switch_CsrPlugin_l1081; + reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1129; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire when_CsrPlugin_l1142; + wire when_CsrPlugin_l1149; + wire when_CsrPlugin_l1150; + wire when_CsrPlugin_l1157; + wire when_CsrPlugin_l1167; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + wire switch_Misc_l210_1; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1189; + wire when_CsrPlugin_l1193; + wire [11:0] execute_CsrPlugin_csrAddress; + wire execute_BranchPlugin_eq; + wire [2:0] switch_Misc_l210_2; + reg _zz_execute_BRANCH_DO; + reg _zz_execute_BRANCH_DO_1; + wire [31:0] execute_BranchPlugin_branch_src1; + wire _zz_execute_BranchPlugin_branch_src2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; + reg [31:0] _zz_execute_BranchPlugin_branch_src2_6; + wire [31:0] execute_BranchPlugin_branch_src2; + wire [31:0] execute_BranchPlugin_branchAdder; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + wire when_DebugPlugin_l225; + reg DebugPlugin_haltedByBreak; + reg DebugPlugin_debugUsed /* verilator public */ ; + reg DebugPlugin_disableEbreak; + wire DebugPlugin_allowEBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_when_DebugPlugin_l244; + wire when_DebugPlugin_l244; + wire [5:0] switch_DebugPlugin_l267; + wire when_DebugPlugin_l271; + wire when_DebugPlugin_l271_1; + wire when_DebugPlugin_l272; + wire when_DebugPlugin_l272_1; + wire when_DebugPlugin_l273; + wire when_DebugPlugin_l274; + wire when_DebugPlugin_l275; + wire when_DebugPlugin_l275_1; + wire when_DebugPlugin_l295; + wire when_DebugPlugin_l298; + wire when_DebugPlugin_l311; + reg DebugPlugin_resetIt_regNext; + wire when_DebugPlugin_l331; + wire when_Pipeline_l124; + reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; + reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; + reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; + reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; + reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; + reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + wire when_Pipeline_l124_10; + reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_11; + reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_12; + reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_13; + reg memory_to_writeBack_MEMORY_ENABLE; + wire when_Pipeline_l124_14; + reg [1:0] decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_15; + reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_16; + reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_17; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_19; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_20; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_21; + reg decode_to_execute_MEMORY_WR; + wire when_Pipeline_l124_22; + reg execute_to_memory_MEMORY_WR; + wire when_Pipeline_l124_23; + reg memory_to_writeBack_MEMORY_WR; + wire when_Pipeline_l124_24; + reg decode_to_execute_MEMORY_MANAGMENT; + wire when_Pipeline_l124_25; + reg decode_to_execute_SRC_LESS_UNSIGNED; + wire when_Pipeline_l124_26; + reg [1:0] decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_27; + reg [1:0] decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_28; + reg [1:0] execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_29; + reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_30; + reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_31; + reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_32; + reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_33; + reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_34; + reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_35; + reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_36; + reg decode_to_execute_IS_CSR; + wire when_Pipeline_l124_37; + reg [1:0] decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_38; + reg [1:0] execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_39; + reg [1:0] memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_40; + reg [1:0] decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_41; + reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_42; + reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_43; + reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_44; + reg [31:0] decode_to_execute_SRC1; + wire when_Pipeline_l124_45; + reg [31:0] decode_to_execute_SRC2; + wire when_Pipeline_l124_46; + reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_47; + reg decode_to_execute_CSR_READ_OPCODE; + wire when_Pipeline_l124_48; + reg decode_to_execute_DO_EBREAK; + wire when_Pipeline_l124_49; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_50; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_51; + (* keep , syn_keep *) reg [31:0] execute_to_memory_MEMORY_VIRTUAL_ADDRESS /* synthesis syn_keep = 1 */ ; + wire when_Pipeline_l124_52; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_53; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_54; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + wire when_Pipeline_l124_55; + reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_56; + reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_57; + reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_58; + reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_59; + reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_60; + reg execute_to_memory_BRANCH_DO; + wire when_Pipeline_l124_61; + reg [31:0] execute_to_memory_BRANCH_CALC; + wire when_Pipeline_l124_62; + reg [51:0] memory_to_writeBack_MUL_LOW; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + reg [2:0] switch_Fetcher_l365; + wire when_Fetcher_l381; + wire when_Fetcher_l401; + wire when_CsrPlugin_l1277; + reg execute_CsrPlugin_csr_3860; + wire when_CsrPlugin_l1277_1; + reg execute_CsrPlugin_csr_769; + wire when_CsrPlugin_l1277_2; + reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1277_3; + reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1277_4; + reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1277_5; + reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1277_6; + reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1277_7; + reg execute_CsrPlugin_csr_832; + wire when_CsrPlugin_l1277_8; + reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1277_9; + reg execute_CsrPlugin_csr_835; + wire [1:0] switch_CsrPlugin_l723; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + wire when_CsrPlugin_l1310; + wire when_CsrPlugin_l1315; + `ifndef SYNTHESIS + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [47:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [47:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [47:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [47:0] _zz_execute_to_memory_ENV_CTRL_1_string; + reg [47:0] decode_ENV_CTRL_string; + reg [47:0] _zz_decode_ENV_CTRL_string; + reg [47:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [47:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; + reg [47:0] memory_ENV_CTRL_string; + reg [47:0] _zz_memory_ENV_CTRL_string; + reg [47:0] execute_ENV_CTRL_string; + reg [47:0] _zz_execute_ENV_CTRL_string; + reg [47:0] writeBack_ENV_CTRL_string; + reg [47:0] _zz_writeBack_ENV_CTRL_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_execute_ALU_CTRL_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [47:0] _zz_decode_ENV_CTRL_1_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [47:0] _zz_decode_ENV_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_9_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [47:0] decode_to_execute_ENV_CTRL_string; + reg [47:0] execute_to_memory_ENV_CTRL_string; + reg [47:0] memory_to_writeBack_ENV_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + `endif + + reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == ShiftCtrlEnum_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 3'b001); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz_io_cpu_flush_payload_lineId = _zz_io_cpu_flush_payload_lineId_1; + assign _zz_io_cpu_flush_payload_lineId_1 = (execute_RS1 >>> 6); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_decode_SRC1_1 = 3'b100; + assign _zz__zz_decode_SRC1_1_1 = decode_INSTRUCTION[19 : 15]; + assign _zz__zz_decode_SRC2_4 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1 = memory_MulDivIterativePlugin_div_counter_willIncrement; + assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext = {5'd0, _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1}; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_MulDivIterativePlugin_rs2}; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator = {_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_MulDivIterativePlugin_div_result_1 = _zz_memory_MulDivIterativePlugin_div_result_2; + assign _zz_memory_MulDivIterativePlugin_div_result_2 = _zz_memory_MulDivIterativePlugin_div_result_3; + assign _zz_memory_MulDivIterativePlugin_div_result_3 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_memory_MulDivIterativePlugin_div_result) : _zz_memory_MulDivIterativePlugin_div_result)} + _zz_memory_MulDivIterativePlugin_div_result_4); + assign _zz_memory_MulDivIterativePlugin_div_result_5 = memory_MulDivIterativePlugin_div_needRevert; + assign _zz_memory_MulDivIterativePlugin_div_result_4 = {32'd0, _zz_memory_MulDivIterativePlugin_div_result_5}; + assign _zz_memory_MulDivIterativePlugin_rs1_3 = _zz_memory_MulDivIterativePlugin_rs1; + assign _zz_memory_MulDivIterativePlugin_rs1_2 = {32'd0, _zz_memory_MulDivIterativePlugin_rs1_3}; + assign _zz_memory_MulDivIterativePlugin_rs2_2 = _zz_memory_MulDivIterativePlugin_rs2; + assign _zz_memory_MulDivIterativePlugin_rs2_1 = {31'd0, _zz_memory_MulDivIterativePlugin_rs2_2}; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz__zz_execute_BranchPlugin_branch_src2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_3,_zz_IBusCachedPlugin_jump_pcLoad_payload_2}; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00001013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hfc00307f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00005033; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; + assign _zz__zz_decode_BRANCH_CTRL_2 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz__zz_decode_BRANCH_CTRL_2_1 = 32'h00000004; + assign _zz__zz_decode_BRANCH_CTRL_2_2 = (decode_INSTRUCTION & 32'h00000058); + assign _zz__zz_decode_BRANCH_CTRL_2_3 = 32'h00000040; + assign _zz__zz_decode_BRANCH_CTRL_2_4 = ((decode_INSTRUCTION & 32'h10003050) == 32'h00000050); + assign _zz__zz_decode_BRANCH_CTRL_2_5 = (|{_zz_decode_BRANCH_CTRL_8,(_zz__zz_decode_BRANCH_CTRL_2_6 == _zz__zz_decode_BRANCH_CTRL_2_7)}); + assign _zz__zz_decode_BRANCH_CTRL_2_8 = (|{_zz__zz_decode_BRANCH_CTRL_2_9,_zz__zz_decode_BRANCH_CTRL_2_10}); + assign _zz__zz_decode_BRANCH_CTRL_2_11 = {(|_zz_decode_BRANCH_CTRL_7),{(|_zz__zz_decode_BRANCH_CTRL_2_12),{_zz__zz_decode_BRANCH_CTRL_2_13,{_zz__zz_decode_BRANCH_CTRL_2_15,_zz__zz_decode_BRANCH_CTRL_2_18}}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_6 = (decode_INSTRUCTION & 32'h10403050); + assign _zz__zz_decode_BRANCH_CTRL_2_7 = 32'h10000050; + assign _zz__zz_decode_BRANCH_CTRL_2_9 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz__zz_decode_BRANCH_CTRL_2_10 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz__zz_decode_BRANCH_CTRL_2_12 = _zz_decode_BRANCH_CTRL_7; + assign _zz__zz_decode_BRANCH_CTRL_2_13 = (|((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_14) == 32'h02004020)); + assign _zz__zz_decode_BRANCH_CTRL_2_15 = (|(_zz__zz_decode_BRANCH_CTRL_2_16 == _zz__zz_decode_BRANCH_CTRL_2_17)); + assign _zz__zz_decode_BRANCH_CTRL_2_18 = {(|{_zz__zz_decode_BRANCH_CTRL_2_19,_zz__zz_decode_BRANCH_CTRL_2_21}),{(|_zz__zz_decode_BRANCH_CTRL_2_23),{_zz__zz_decode_BRANCH_CTRL_2_28,{_zz__zz_decode_BRANCH_CTRL_2_31,_zz__zz_decode_BRANCH_CTRL_2_33}}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_14 = 32'h02004064; + assign _zz__zz_decode_BRANCH_CTRL_2_16 = (decode_INSTRUCTION & 32'h02004074); + assign _zz__zz_decode_BRANCH_CTRL_2_17 = 32'h02000030; + assign _zz__zz_decode_BRANCH_CTRL_2_19 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_20) == 32'h00005010); + assign _zz__zz_decode_BRANCH_CTRL_2_21 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_22) == 32'h00005020); + assign _zz__zz_decode_BRANCH_CTRL_2_23 = {(_zz__zz_decode_BRANCH_CTRL_2_24 == _zz__zz_decode_BRANCH_CTRL_2_25),{_zz__zz_decode_BRANCH_CTRL_2_26,_zz__zz_decode_BRANCH_CTRL_2_27}}; + assign _zz__zz_decode_BRANCH_CTRL_2_28 = (|(_zz__zz_decode_BRANCH_CTRL_2_29 == _zz__zz_decode_BRANCH_CTRL_2_30)); + assign _zz__zz_decode_BRANCH_CTRL_2_31 = (|_zz__zz_decode_BRANCH_CTRL_2_32); + assign _zz__zz_decode_BRANCH_CTRL_2_33 = {(|_zz__zz_decode_BRANCH_CTRL_2_34),{_zz__zz_decode_BRANCH_CTRL_2_36,{_zz__zz_decode_BRANCH_CTRL_2_39,_zz__zz_decode_BRANCH_CTRL_2_41}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_20 = 32'h00007034; + assign _zz__zz_decode_BRANCH_CTRL_2_22 = 32'h02007064; + assign _zz__zz_decode_BRANCH_CTRL_2_24 = (decode_INSTRUCTION & 32'h40003054); + assign _zz__zz_decode_BRANCH_CTRL_2_25 = 32'h40001010; + assign _zz__zz_decode_BRANCH_CTRL_2_26 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); + assign _zz__zz_decode_BRANCH_CTRL_2_27 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); + assign _zz__zz_decode_BRANCH_CTRL_2_29 = (decode_INSTRUCTION & 32'h00000064); + assign _zz__zz_decode_BRANCH_CTRL_2_30 = 32'h00000024; + assign _zz__zz_decode_BRANCH_CTRL_2_32 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz__zz_decode_BRANCH_CTRL_2_34 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_35) == 32'h00002000); + assign _zz__zz_decode_BRANCH_CTRL_2_36 = (|{_zz__zz_decode_BRANCH_CTRL_2_37,_zz__zz_decode_BRANCH_CTRL_2_38}); + assign _zz__zz_decode_BRANCH_CTRL_2_39 = (|_zz__zz_decode_BRANCH_CTRL_2_40); + assign _zz__zz_decode_BRANCH_CTRL_2_41 = {(|_zz__zz_decode_BRANCH_CTRL_2_42),{_zz__zz_decode_BRANCH_CTRL_2_47,{_zz__zz_decode_BRANCH_CTRL_2_56,_zz__zz_decode_BRANCH_CTRL_2_58}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_35 = 32'h00003000; + assign _zz__zz_decode_BRANCH_CTRL_2_37 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz__zz_decode_BRANCH_CTRL_2_38 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz__zz_decode_BRANCH_CTRL_2_40 = ((decode_INSTRUCTION & 32'h00004048) == 32'h00004008); + assign _zz__zz_decode_BRANCH_CTRL_2_42 = {(_zz__zz_decode_BRANCH_CTRL_2_43 == _zz__zz_decode_BRANCH_CTRL_2_44),(_zz__zz_decode_BRANCH_CTRL_2_45 == _zz__zz_decode_BRANCH_CTRL_2_46)}; + assign _zz__zz_decode_BRANCH_CTRL_2_47 = (|{_zz__zz_decode_BRANCH_CTRL_2_48,{_zz__zz_decode_BRANCH_CTRL_2_49,_zz__zz_decode_BRANCH_CTRL_2_51}}); + assign _zz__zz_decode_BRANCH_CTRL_2_56 = (|_zz__zz_decode_BRANCH_CTRL_2_57); + assign _zz__zz_decode_BRANCH_CTRL_2_58 = {(|_zz__zz_decode_BRANCH_CTRL_2_59),{_zz__zz_decode_BRANCH_CTRL_2_70,{_zz__zz_decode_BRANCH_CTRL_2_83,_zz__zz_decode_BRANCH_CTRL_2_97}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_43 = (decode_INSTRUCTION & 32'h00000034); + assign _zz__zz_decode_BRANCH_CTRL_2_44 = 32'h00000020; + assign _zz__zz_decode_BRANCH_CTRL_2_45 = (decode_INSTRUCTION & 32'h00000064); + assign _zz__zz_decode_BRANCH_CTRL_2_46 = 32'h00000020; + assign _zz__zz_decode_BRANCH_CTRL_2_48 = ((decode_INSTRUCTION & 32'h00002040) == 32'h00002040); + assign _zz__zz_decode_BRANCH_CTRL_2_49 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_50) == 32'h00001040); + assign _zz__zz_decode_BRANCH_CTRL_2_51 = {(_zz__zz_decode_BRANCH_CTRL_2_52 == _zz__zz_decode_BRANCH_CTRL_2_53),{_zz__zz_decode_BRANCH_CTRL_2_54,_zz_decode_BRANCH_CTRL_4}}; + assign _zz__zz_decode_BRANCH_CTRL_2_57 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); + assign _zz__zz_decode_BRANCH_CTRL_2_59 = {(_zz__zz_decode_BRANCH_CTRL_2_60 == _zz__zz_decode_BRANCH_CTRL_2_61),{_zz_decode_BRANCH_CTRL_5,{_zz__zz_decode_BRANCH_CTRL_2_62,_zz__zz_decode_BRANCH_CTRL_2_65}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_70 = (|{_zz_decode_BRANCH_CTRL_5,{_zz__zz_decode_BRANCH_CTRL_2_71,_zz__zz_decode_BRANCH_CTRL_2_74}}); + assign _zz__zz_decode_BRANCH_CTRL_2_83 = (|{_zz__zz_decode_BRANCH_CTRL_2_84,_zz__zz_decode_BRANCH_CTRL_2_85}); + assign _zz__zz_decode_BRANCH_CTRL_2_97 = {(|_zz__zz_decode_BRANCH_CTRL_2_98),{_zz__zz_decode_BRANCH_CTRL_2_101,{_zz__zz_decode_BRANCH_CTRL_2_106,_zz__zz_decode_BRANCH_CTRL_2_110}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_50 = 32'h00001040; + assign _zz__zz_decode_BRANCH_CTRL_2_52 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_BRANCH_CTRL_2_53 = 32'h00000040; + assign _zz__zz_decode_BRANCH_CTRL_2_54 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_55) == 32'h00000040); + assign _zz__zz_decode_BRANCH_CTRL_2_60 = (decode_INSTRUCTION & 32'h00000040); + assign _zz__zz_decode_BRANCH_CTRL_2_61 = 32'h00000040; + assign _zz__zz_decode_BRANCH_CTRL_2_62 = (_zz__zz_decode_BRANCH_CTRL_2_63 == _zz__zz_decode_BRANCH_CTRL_2_64); + assign _zz__zz_decode_BRANCH_CTRL_2_65 = {_zz__zz_decode_BRANCH_CTRL_2_66,_zz__zz_decode_BRANCH_CTRL_2_68}; + assign _zz__zz_decode_BRANCH_CTRL_2_71 = (_zz__zz_decode_BRANCH_CTRL_2_72 == _zz__zz_decode_BRANCH_CTRL_2_73); + assign _zz__zz_decode_BRANCH_CTRL_2_74 = {_zz__zz_decode_BRANCH_CTRL_2_75,{_zz__zz_decode_BRANCH_CTRL_2_77,_zz__zz_decode_BRANCH_CTRL_2_80}}; + assign _zz__zz_decode_BRANCH_CTRL_2_84 = _zz_decode_BRANCH_CTRL_6; + assign _zz__zz_decode_BRANCH_CTRL_2_85 = {_zz__zz_decode_BRANCH_CTRL_2_86,{_zz__zz_decode_BRANCH_CTRL_2_88,_zz__zz_decode_BRANCH_CTRL_2_91}}; + assign _zz__zz_decode_BRANCH_CTRL_2_98 = {_zz_decode_BRANCH_CTRL_5,_zz__zz_decode_BRANCH_CTRL_2_99}; + assign _zz__zz_decode_BRANCH_CTRL_2_101 = (|{_zz__zz_decode_BRANCH_CTRL_2_102,_zz__zz_decode_BRANCH_CTRL_2_103}); + assign _zz__zz_decode_BRANCH_CTRL_2_106 = (|_zz__zz_decode_BRANCH_CTRL_2_107); + assign _zz__zz_decode_BRANCH_CTRL_2_110 = {_zz__zz_decode_BRANCH_CTRL_2_111,{_zz__zz_decode_BRANCH_CTRL_2_113,_zz__zz_decode_BRANCH_CTRL_2_124}}; + assign _zz__zz_decode_BRANCH_CTRL_2_55 = 32'h00400040; + assign _zz__zz_decode_BRANCH_CTRL_2_63 = (decode_INSTRUCTION & 32'h00004020); + assign _zz__zz_decode_BRANCH_CTRL_2_64 = 32'h00004020; + assign _zz__zz_decode_BRANCH_CTRL_2_66 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_67) == 32'h00000010); + assign _zz__zz_decode_BRANCH_CTRL_2_68 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_69) == 32'h00000020); + assign _zz__zz_decode_BRANCH_CTRL_2_72 = (decode_INSTRUCTION & 32'h00002030); + assign _zz__zz_decode_BRANCH_CTRL_2_73 = 32'h00002010; + assign _zz__zz_decode_BRANCH_CTRL_2_75 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_76) == 32'h00000010); + assign _zz__zz_decode_BRANCH_CTRL_2_77 = (_zz__zz_decode_BRANCH_CTRL_2_78 == _zz__zz_decode_BRANCH_CTRL_2_79); + assign _zz__zz_decode_BRANCH_CTRL_2_80 = (_zz__zz_decode_BRANCH_CTRL_2_81 == _zz__zz_decode_BRANCH_CTRL_2_82); + assign _zz__zz_decode_BRANCH_CTRL_2_86 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_87) == 32'h00001010); + assign _zz__zz_decode_BRANCH_CTRL_2_88 = (_zz__zz_decode_BRANCH_CTRL_2_89 == _zz__zz_decode_BRANCH_CTRL_2_90); + assign _zz__zz_decode_BRANCH_CTRL_2_91 = {_zz__zz_decode_BRANCH_CTRL_2_92,{_zz__zz_decode_BRANCH_CTRL_2_93,_zz__zz_decode_BRANCH_CTRL_2_95}}; + assign _zz__zz_decode_BRANCH_CTRL_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_100) == 32'h00000020); + assign _zz__zz_decode_BRANCH_CTRL_2_102 = _zz_decode_BRANCH_CTRL_5; + assign _zz__zz_decode_BRANCH_CTRL_2_103 = (_zz__zz_decode_BRANCH_CTRL_2_104 == _zz__zz_decode_BRANCH_CTRL_2_105); + assign _zz__zz_decode_BRANCH_CTRL_2_107 = (_zz__zz_decode_BRANCH_CTRL_2_108 == _zz__zz_decode_BRANCH_CTRL_2_109); + assign _zz__zz_decode_BRANCH_CTRL_2_111 = (|_zz__zz_decode_BRANCH_CTRL_2_112); + assign _zz__zz_decode_BRANCH_CTRL_2_113 = (|_zz__zz_decode_BRANCH_CTRL_2_114); + assign _zz__zz_decode_BRANCH_CTRL_2_124 = {_zz__zz_decode_BRANCH_CTRL_2_125,{_zz__zz_decode_BRANCH_CTRL_2_128,_zz__zz_decode_BRANCH_CTRL_2_136}}; + assign _zz__zz_decode_BRANCH_CTRL_2_67 = 32'h00000030; + assign _zz__zz_decode_BRANCH_CTRL_2_69 = 32'h02000020; + assign _zz__zz_decode_BRANCH_CTRL_2_76 = 32'h00001030; + assign _zz__zz_decode_BRANCH_CTRL_2_78 = (decode_INSTRUCTION & 32'h02002060); + assign _zz__zz_decode_BRANCH_CTRL_2_79 = 32'h00002020; + assign _zz__zz_decode_BRANCH_CTRL_2_81 = (decode_INSTRUCTION & 32'h02003020); + assign _zz__zz_decode_BRANCH_CTRL_2_82 = 32'h00000020; + assign _zz__zz_decode_BRANCH_CTRL_2_87 = 32'h00001010; + assign _zz__zz_decode_BRANCH_CTRL_2_89 = (decode_INSTRUCTION & 32'h00002010); + assign _zz__zz_decode_BRANCH_CTRL_2_90 = 32'h00002010; + assign _zz__zz_decode_BRANCH_CTRL_2_92 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); + assign _zz__zz_decode_BRANCH_CTRL_2_93 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_94) == 32'h00000004); + assign _zz__zz_decode_BRANCH_CTRL_2_95 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_96) == 32'h0); + assign _zz__zz_decode_BRANCH_CTRL_2_100 = 32'h00000070; + assign _zz__zz_decode_BRANCH_CTRL_2_104 = (decode_INSTRUCTION & 32'h00000020); + assign _zz__zz_decode_BRANCH_CTRL_2_105 = 32'h0; + assign _zz__zz_decode_BRANCH_CTRL_2_108 = (decode_INSTRUCTION & 32'h00004014); + assign _zz__zz_decode_BRANCH_CTRL_2_109 = 32'h00004010; + assign _zz__zz_decode_BRANCH_CTRL_2_112 = ((decode_INSTRUCTION & 32'h00006014) == 32'h00002010); + assign _zz__zz_decode_BRANCH_CTRL_2_114 = {(_zz__zz_decode_BRANCH_CTRL_2_115 == _zz__zz_decode_BRANCH_CTRL_2_116),{_zz_decode_BRANCH_CTRL_4,{_zz__zz_decode_BRANCH_CTRL_2_117,_zz__zz_decode_BRANCH_CTRL_2_119}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_125 = (|(_zz__zz_decode_BRANCH_CTRL_2_126 == _zz__zz_decode_BRANCH_CTRL_2_127)); + assign _zz__zz_decode_BRANCH_CTRL_2_128 = (|{_zz__zz_decode_BRANCH_CTRL_2_129,_zz__zz_decode_BRANCH_CTRL_2_131}); + assign _zz__zz_decode_BRANCH_CTRL_2_136 = {(|_zz__zz_decode_BRANCH_CTRL_2_137),{_zz__zz_decode_BRANCH_CTRL_2_140,_zz__zz_decode_BRANCH_CTRL_2_142}}; + assign _zz__zz_decode_BRANCH_CTRL_2_94 = 32'h0000000c; + assign _zz__zz_decode_BRANCH_CTRL_2_96 = 32'h00000028; + assign _zz__zz_decode_BRANCH_CTRL_2_115 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_BRANCH_CTRL_2_116 = 32'h0; + assign _zz__zz_decode_BRANCH_CTRL_2_117 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_118) == 32'h00002000); + assign _zz__zz_decode_BRANCH_CTRL_2_119 = {(_zz__zz_decode_BRANCH_CTRL_2_120 == _zz__zz_decode_BRANCH_CTRL_2_121),(_zz__zz_decode_BRANCH_CTRL_2_122 == _zz__zz_decode_BRANCH_CTRL_2_123)}; + assign _zz__zz_decode_BRANCH_CTRL_2_126 = (decode_INSTRUCTION & 32'h00000058); + assign _zz__zz_decode_BRANCH_CTRL_2_127 = 32'h0; + assign _zz__zz_decode_BRANCH_CTRL_2_129 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_130) == 32'h00000040); + assign _zz__zz_decode_BRANCH_CTRL_2_131 = {(_zz__zz_decode_BRANCH_CTRL_2_132 == _zz__zz_decode_BRANCH_CTRL_2_133),(_zz__zz_decode_BRANCH_CTRL_2_134 == _zz__zz_decode_BRANCH_CTRL_2_135)}; + assign _zz__zz_decode_BRANCH_CTRL_2_137 = {(_zz__zz_decode_BRANCH_CTRL_2_138 == _zz__zz_decode_BRANCH_CTRL_2_139),_zz_decode_BRANCH_CTRL_3}; + assign _zz__zz_decode_BRANCH_CTRL_2_140 = (|{_zz__zz_decode_BRANCH_CTRL_2_141,_zz_decode_BRANCH_CTRL_3}); + assign _zz__zz_decode_BRANCH_CTRL_2_142 = (|(_zz__zz_decode_BRANCH_CTRL_2_143 == _zz__zz_decode_BRANCH_CTRL_2_144)); + assign _zz__zz_decode_BRANCH_CTRL_2_118 = 32'h00006004; + assign _zz__zz_decode_BRANCH_CTRL_2_120 = (decode_INSTRUCTION & 32'h00005004); + assign _zz__zz_decode_BRANCH_CTRL_2_121 = 32'h00001000; + assign _zz__zz_decode_BRANCH_CTRL_2_122 = (decode_INSTRUCTION & 32'h00004050); + assign _zz__zz_decode_BRANCH_CTRL_2_123 = 32'h00004000; + assign _zz__zz_decode_BRANCH_CTRL_2_130 = 32'h00000044; + assign _zz__zz_decode_BRANCH_CTRL_2_132 = (decode_INSTRUCTION & 32'h00002014); + assign _zz__zz_decode_BRANCH_CTRL_2_133 = 32'h00002010; + assign _zz__zz_decode_BRANCH_CTRL_2_134 = (decode_INSTRUCTION & 32'h40000034); + assign _zz__zz_decode_BRANCH_CTRL_2_135 = 32'h40000030; + assign _zz__zz_decode_BRANCH_CTRL_2_138 = (decode_INSTRUCTION & 32'h00000014); + assign _zz__zz_decode_BRANCH_CTRL_2_139 = 32'h00000004; + assign _zz__zz_decode_BRANCH_CTRL_2_141 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz__zz_decode_BRANCH_CTRL_2_143 = (decode_INSTRUCTION & 32'h00005048); + assign _zz__zz_decode_BRANCH_CTRL_2_144 = 32'h00001008; + always @(posedge io_systemClk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_1) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + InstructionCache_b62b14ffe6bb44e5a817b8d08e286c6b IBusCachedPlugin_cache ( + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0]), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0]), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + DataCache_b62b14ffe6bb44e5a817b8d08e286c6b dataCache_1 ( + .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i + .io_cpu_execute_address (dataCache_1_io_cpu_execute_address[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (memory_MEMORY_VIRTUAL_ADDRESS[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0]), //i + .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isFiring (writeBack_arbitration_isFiring ), //i + .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData[31:0] ), //i + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i + .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i + .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i + .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i + .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i + .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i + .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i + .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i + .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM[3:0] ), //i + .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_cpu_flush_payload_singleLine (dataCache_1_io_cpu_flush_payload_singleLine ), //i + .io_cpu_flush_payload_lineId (dataCache_1_io_cpu_flush_payload_lineId[5:0] ), //i + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_regNext_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_regNext_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_regNext_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_regNext_payload_error ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + always @(*) begin + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_5) + 2'b00 : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = DBusCachedPlugin_redoBranch_payload; + 2'b01 : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = CsrPlugin_jumpInterface_payload; + default : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = BranchPlugin_jumpInterface_payload; + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) + 2'b00 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; + 2'b01 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; + 2'b10 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; + default : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) + 1'b0 : _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; + default : _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(decode_BRANCH_CTRL) + BranchCtrlEnum_INC : decode_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : decode_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : decode_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_BRANCH_CTRL) + BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_BRANCH_CTRL) + BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_BRANCH_CTRL_1) + BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_memory_to_writeBack_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_memory_to_writeBack_ENV_CTRL_string = "EBREAK"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_memory_to_writeBack_ENV_CTRL_1) + EnvCtrlEnum_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + EnvCtrlEnum_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_memory_to_writeBack_ENV_CTRL_1_string = "EBREAK"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "??????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_execute_to_memory_ENV_CTRL_string = "EBREAK"; + default : _zz_execute_to_memory_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_ENV_CTRL_1) + EnvCtrlEnum_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + EnvCtrlEnum_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_execute_to_memory_ENV_CTRL_1_string = "EBREAK"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "??????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + EnvCtrlEnum_NONE : decode_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : decode_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : decode_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : decode_ENV_CTRL_string = "EBREAK"; + default : decode_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_decode_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_string = "EBREAK"; + default : _zz_decode_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_decode_to_execute_ENV_CTRL_string = "EBREAK"; + default : _zz_decode_to_execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ENV_CTRL_1) + EnvCtrlEnum_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + EnvCtrlEnum_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_decode_to_execute_ENV_CTRL_1_string = "EBREAK"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "??????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_SHIFT_CTRL_1) + ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_SHIFT_CTRL_1) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + AluCtrlEnum_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_CTRL) + AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_CTRL) + AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_CTRL_1) + AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + BranchCtrlEnum_INC : execute_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : execute_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : execute_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_execute_BRANCH_CTRL) + BranchCtrlEnum_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : _zz_execute_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + EnvCtrlEnum_NONE : memory_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : memory_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : memory_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : memory_ENV_CTRL_string = "EBREAK"; + default : memory_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_memory_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_memory_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_memory_ENV_CTRL_string = "EBREAK"; + default : _zz_memory_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + EnvCtrlEnum_NONE : execute_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : execute_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : execute_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : execute_ENV_CTRL_string = "EBREAK"; + default : execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_execute_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_execute_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_execute_ENV_CTRL_string = "EBREAK"; + default : _zz_execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + EnvCtrlEnum_NONE : writeBack_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : writeBack_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : writeBack_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : writeBack_ENV_CTRL_string = "EBREAK"; + default : writeBack_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_writeBack_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_writeBack_ENV_CTRL_string = "EBREAK"; + default : _zz_writeBack_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_memory_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_execute_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + Src2CtrlEnum_RS : decode_SRC2_CTRL_string = "RS "; + Src2CtrlEnum_IMI : decode_SRC2_CTRL_string = "IMI"; + Src2CtrlEnum_IMS : decode_SRC2_CTRL_string = "IMS"; + Src2CtrlEnum_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_SRC2_CTRL) + Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_string = "RS "; + Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + Src1CtrlEnum_RS : decode_SRC1_CTRL_string = "RS "; + Src1CtrlEnum_IMU : decode_SRC1_CTRL_string = "IMU "; + Src1CtrlEnum_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + Src1CtrlEnum_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC1_CTRL) + Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_string = "RS "; + Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + AluCtrlEnum_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_execute_ALU_CTRL) + AluCtrlEnum_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_BRANCH_CTRL_1) + BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_ENV_CTRL_1) + EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_1_string = "EBREAK"; + default : _zz_decode_ENV_CTRL_1_string = "??????"; + endcase + end + always @(*) begin + case(_zz_decode_SHIFT_CTRL_1) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_BITWISE_CTRL_1) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC2_CTRL_1) + Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_CTRL_1) + AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC1_CTRL_1) + Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC1_CTRL_2) + Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_CTRL_2) + AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC2_CTRL_2) + Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_BITWISE_CTRL_2) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_SHIFT_CTRL_2) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_ENV_CTRL_2) + EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_2_string = "EBREAK"; + default : _zz_decode_ENV_CTRL_2_string = "??????"; + endcase + end + always @(*) begin + case(_zz_decode_BRANCH_CTRL_9) + BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_9_string = "INC "; + BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_9_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_9_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_9_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_9_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + AluCtrlEnum_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + EnvCtrlEnum_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : decode_to_execute_ENV_CTRL_string = "EBREAK"; + default : decode_to_execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + EnvCtrlEnum_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : execute_to_memory_ENV_CTRL_string = "EBREAK"; + default : execute_to_memory_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + EnvCtrlEnum_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : memory_to_writeBack_ENV_CTRL_string = "EBREAK"; + default : memory_to_writeBack_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + BranchCtrlEnum_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : decode_to_execute_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + `endif + + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = _zz_execute_BRANCH_DO_1; + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = execute_MulPlugin_withOuputBuffer_mul_hh; + assign execute_MUL_HL = execute_MulPlugin_withOuputBuffer_mul_hl; + assign execute_MUL_LH = execute_MulPlugin_withOuputBuffer_mul_lh; + assign execute_MUL_LL = execute_MulPlugin_withOuputBuffer_mul_ll; + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign execute_MEMORY_VIRTUAL_ADDRESS = dataCache_1_io_cpu_execute_address; + assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; + assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; + assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_SRC2 = _zz_decode_SRC2_6; + assign decode_SRC1 = _zz_decode_SRC1_1; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_BRANCH_CTRL_2[27]; + assign decode_IS_RS2_SIGNED = _zz_decode_BRANCH_CTRL_2[26]; + assign decode_IS_RS1_SIGNED = _zz_decode_BRANCH_CTRL_2[25]; + assign decode_IS_DIV = _zz_decode_BRANCH_CTRL_2[24]; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign decode_IS_MUL = _zz_decode_BRANCH_CTRL_2[23]; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_BRANCH_CTRL_2[17]; + assign decode_MEMORY_MANAGMENT = _zz_decode_BRANCH_CTRL_2[16]; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_decode_BRANCH_CTRL_2[13]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_BRANCH_CTRL_2[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_BRANCH_CTRL_2[11]; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_decode_BRANCH_CTRL_2[30]; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PC = decode_to_execute_PC; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_RS2_USE = _zz_decode_BRANCH_CTRL_2[15]; + assign decode_RS1_USE = _zz_decode_BRANCH_CTRL_2[5]; + always @(*) begin + _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1189) begin + _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; + end + end + + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @(*) begin + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; + end + end + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; + end + end + end + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2_1; + end + end + end + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2; + end + end + end + end + + always @(*) begin + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; + end + end + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; + end + end + end + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2_1; + end + end + end + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2; + end + end + end + end + + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; + always @(*) begin + _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin + case(memory_SHIFT_CTRL) + ShiftCtrlEnum_SLL_1 : begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; + end + ShiftCtrlEnum_SRL_1, ShiftCtrlEnum_SRA_1 : begin + _zz_decode_RS2_1 = memory_SHIFT_RIGHT; + end + default : begin + end + endcase + end + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2_1 = memory_MulDivIterativePlugin_div_result; + end + end + + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_decode_SRC2 = decode_PC; + assign _zz_decode_SRC2_1 = decode_RS2; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_SRC1 = decode_RS1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_BRANCH_CTRL_2[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_BRANCH_CTRL_2[20]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = decode_to_execute_SRC2; + assign execute_SRC1 = decode_to_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_iBusRsp_output_payload_rsp_inst); + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_BRANCH_CTRL_2[10]; + if(when_RegFilePlugin_l63) begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = (|{((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}}); + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusCachedPlugin_l492) begin + _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; + end + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) + 2'b00 : begin + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; + end + default : begin + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; + end + endcase + end + end + + assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign memory_MEMORY_VIRTUAL_ADDRESS = execute_to_memory_MEMORY_VIRTUAL_ADDRESS; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign decode_MEMORY_ENABLE = _zz_decode_BRANCH_CTRL_2[4]; + assign decode_FLUSH_ALL = _zz_decode_BRANCH_CTRL_2[0]; + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(when_IBusCachedPlugin_l256) begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(when_IBusCachedPlugin_l244) begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(when_IBusCachedPlugin_l239) begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; + end + end + + always @(*) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; + end + end + + assign decode_PC = IBusCachedPlugin_injector_decodeInput_payload_pc; + assign decode_INSTRUCTION = IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @(*) begin + decode_arbitration_haltItself = 1'b0; + if(when_DBusCachedPlugin_l308) begin + decode_arbitration_haltItself = 1'b1; + end + case(switch_Fetcher_l365) + 3'b010 : begin + decode_arbitration_haltItself = 1'b1; + end + default : begin + end + endcase + end + + always @(*) begin + decode_arbitration_haltByOther = 1'b0; + if(when_HazardSimplePlugin_l113) begin + decode_arbitration_haltByOther = 1'b1; + end + if(CsrPlugin_pipelineLiberator_active) begin + decode_arbitration_haltByOther = 1'b1; + end + if(when_CsrPlugin_l1129) begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @(*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_when) begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed) begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + always @(*) begin + decode_arbitration_flushNext = 1'b0; + if(_zz_when) begin + decode_arbitration_flushNext = 1'b1; + end + end + + always @(*) begin + execute_arbitration_haltItself = 1'b0; + if(when_DBusCachedPlugin_l350) begin + execute_arbitration_haltItself = 1'b1; + end + if(when_MulPlugin_l65) begin + execute_arbitration_haltItself = 1'b1; + end + if(when_CsrPlugin_l1193) begin + if(execute_CsrPlugin_blockedBySideEffects) begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + always @(*) begin + execute_arbitration_haltByOther = 1'b0; + if(when_DBusCachedPlugin_l366) begin + execute_arbitration_haltByOther = 1'b1; + end + if(when_DebugPlugin_l295) begin + execute_arbitration_haltByOther = 1'b1; + end + end + + always @(*) begin + execute_arbitration_removeIt = 1'b0; + if(CsrPlugin_selfException_valid) begin + execute_arbitration_removeIt = 1'b1; + end + if(execute_arbitration_isFlushed) begin + execute_arbitration_removeIt = 1'b1; + end + end + + always @(*) begin + execute_arbitration_flushIt = 1'b0; + if(when_DebugPlugin_l295) begin + if(when_DebugPlugin_l298) begin + execute_arbitration_flushIt = 1'b1; + end + end + end + + always @(*) begin + execute_arbitration_flushNext = 1'b0; + if(CsrPlugin_selfException_valid) begin + execute_arbitration_flushNext = 1'b1; + end + if(when_DebugPlugin_l295) begin + if(when_DebugPlugin_l298) begin + execute_arbitration_flushNext = 1'b1; + end + end + end + + always @(*) begin + memory_arbitration_haltItself = 1'b0; + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @(*) begin + memory_arbitration_removeIt = 1'b0; + if(BranchPlugin_branchExceptionPort_valid) begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed) begin + memory_arbitration_removeIt = 1'b1; + end + end + + assign memory_arbitration_flushIt = 1'b0; + always @(*) begin + memory_arbitration_flushNext = 1'b0; + if(BranchPlugin_branchExceptionPort_valid) begin + memory_arbitration_flushNext = 1'b1; + end + if(BranchPlugin_jumpInterface_valid) begin + memory_arbitration_flushNext = 1'b1; + end + end + + always @(*) begin + writeBack_arbitration_haltItself = 1'b0; + if(when_DBusCachedPlugin_l466) begin + writeBack_arbitration_haltItself = 1'b1; + end + end + + assign writeBack_arbitration_haltByOther = 1'b0; + always @(*) begin + writeBack_arbitration_removeIt = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid) begin + writeBack_arbitration_removeIt = 1'b1; + end + if(writeBack_arbitration_isFlushed) begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + always @(*) begin + writeBack_arbitration_flushIt = 1'b0; + if(DBusCachedPlugin_redoBranch_valid) begin + writeBack_arbitration_flushIt = 1'b1; + end + end + + always @(*) begin + writeBack_arbitration_flushNext = 1'b0; + if(DBusCachedPlugin_redoBranch_valid) begin + writeBack_arbitration_flushNext = 1'b1; + end + if(DBusCachedPlugin_exceptionBus_valid) begin + writeBack_arbitration_flushNext = 1'b1; + end + if(when_CsrPlugin_l1032) begin + writeBack_arbitration_flushNext = 1'b1; + end + if(when_CsrPlugin_l1077) begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @(*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(when_CsrPlugin_l935) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(when_CsrPlugin_l1032) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(when_CsrPlugin_l1077) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(when_DebugPlugin_l295) begin + if(when_DebugPlugin_l298) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + if(DebugPlugin_haltIt) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(when_DebugPlugin_l311) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + assign IBusCachedPlugin_forceNoDecodeCond = 1'b0; + always @(*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if(when_Fetcher_l243) begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + if(IBusCachedPlugin_injector_decodeInput_valid) begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @(*) begin + _zz_when_DBusCachedPlugin_l393 = 1'b0; + if(DebugPlugin_godmode) begin + _zz_when_DBusCachedPlugin_l393 = 1'b1; + end + end + + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; + assign CsrPlugin_inWfi = 1'b0; + always @(*) begin + CsrPlugin_thirdPartyWake = 1'b0; + if(DebugPlugin_haltIt) begin + CsrPlugin_thirdPartyWake = 1'b1; + end + end + + always @(*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(when_CsrPlugin_l1032) begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(when_CsrPlugin_l1077) begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1032) begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; + end + if(when_CsrPlugin_l1077) begin + case(switch_CsrPlugin_l1081) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + always @(*) begin + CsrPlugin_forceMachineWire = 1'b0; + if(DebugPlugin_godmode) begin + CsrPlugin_forceMachineWire = 1'b1; + end + end + + always @(*) begin + CsrPlugin_allowInterrupts = 1'b1; + if(when_DebugPlugin_l331) begin + CsrPlugin_allowInterrupts = 1'b0; + end + end + + always @(*) begin + CsrPlugin_allowException = 1'b1; + if(DebugPlugin_godmode) begin + CsrPlugin_allowException = 1'b0; + end + end + + always @(*) begin + CsrPlugin_allowEbreakException = 1'b1; + if(DebugPlugin_allowEBreak) begin + CsrPlugin_allowEbreakException = 1'b0; + end + end + + always @(*) begin + BranchPlugin_inDebugNoFetchFlag = 1'b0; + if(DebugPlugin_godmode) begin + BranchPlugin_inDebugNoFetchFlag = 1'b1; + end + end + + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (((IBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hf8000000) || ((IBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hfa000000)); + assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusCachedPlugin_mmuBus_busy = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (((DBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hf8000000) || ((DBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hfa000000)); + assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusCachedPlugin_mmuBus_busy = 1'b0; + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}} != 3'b000); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[1]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[2]; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_4; + always @(*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid) begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid) begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); + always @(*) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + assign when_Fetcher_l134 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l134_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end + if(IBusCachedPlugin_jump_pcLoad_valid) begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + always @(*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid) begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid) begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + + assign when_Fetcher_l161 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @(*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_mmuBus_busy) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if(when_IBusCachedPlugin_l267) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; + end + end + + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = (IBusCachedPlugin_externalFlush || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if(IBusCachedPlugin_injector_decodeInput_valid) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + if(when_Fetcher_l323) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign when_Fetcher_l243 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign IBusCachedPlugin_iBusRsp_output_ready = ((1'b0 && (! IBusCachedPlugin_injector_decodeInput_valid)) || IBusCachedPlugin_injector_decodeInput_ready); + assign IBusCachedPlugin_injector_decodeInput_valid = _zz_IBusCachedPlugin_injector_decodeInput_valid; + assign IBusCachedPlugin_injector_decodeInput_payload_pc = _zz_IBusCachedPlugin_injector_decodeInput_payload_pc; + assign IBusCachedPlugin_injector_decodeInput_payload_rsp_error = _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error; + assign IBusCachedPlugin_injector_decodeInput_payload_rsp_inst = _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + assign IBusCachedPlugin_injector_decodeInput_payload_isRvc = _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc; + assign when_Fetcher_l323 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l332 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l332_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l332_2 = (! (! IBusCachedPlugin_injector_decodeInput_ready)); + assign when_Fetcher_l332_3 = (! execute_arbitration_isStuck); + assign when_Fetcher_l332_4 = (! memory_arbitration_isStuck); + assign when_Fetcher_l332_5 = (! writeBack_arbitration_isStuck); + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_5; + assign IBusCachedPlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); + always @(*) begin + decode_arbitration_isValid = IBusCachedPlugin_injector_decodeInput_valid; + case(switch_Fetcher_l365) + 3'b010 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b011 : begin + decode_arbitration_isValid = 1'b1; + end + default : begin + end + endcase + if(IBusCachedPlugin_forceNoDecodeCond) begin + decode_arbitration_isValid = 1'b0; + end + end + + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @(*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; + always @(*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(when_IBusCachedPlugin_l239) begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(when_IBusCachedPlugin_l244) begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(when_IBusCachedPlugin_l256) begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + always @(*) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(when_IBusCachedPlugin_l244) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(when_IBusCachedPlugin_l256) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); + always @(*) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l368) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign when_DBusCachedPlugin_l308 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; + assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD; + always @(*) begin + case(execute_DBusCachedPlugin_size) + 2'b00 : begin + _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; + end + endcase + end + + assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign dataCache_1_io_cpu_flush_payload_singleLine = (execute_INSTRUCTION[19 : 15] != 5'h0); + assign dataCache_1_io_cpu_flush_payload_lineId = _zz_io_cpu_flush_payload_lineId[5:0]; + assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); + assign when_DBusCachedPlugin_l350 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); + assign when_DBusCachedPlugin_l366 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); + assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = memory_MEMORY_VIRTUAL_ADDRESS; + assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + always @(*) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if(when_DBusCachedPlugin_l393) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; + end + end + + assign when_DBusCachedPlugin_l393 = (_zz_when_DBusCachedPlugin_l393 && (! dataCache_1_io_cpu_memory_isWrite)); + always @(*) begin + dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_arbitration_haltByOther) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b0; + end + end + + assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); + assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; + assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; + always @(*) begin + DBusCachedPlugin_redoBranch_valid = 1'b0; + if(when_DBusCachedPlugin_l446) begin + if(dataCache_1_io_cpu_redo) begin + DBusCachedPlugin_redoBranch_valid = 1'b1; + end + end + end + + assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; + always @(*) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + if(when_DBusCachedPlugin_l446) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_mmuException) begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_redo) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + end + end + end + + assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; + always @(*) begin + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(when_DBusCachedPlugin_l446) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; + end + if(dataCache_1_io_cpu_writeBack_mmuException) begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; + end + end + end + + assign when_DBusCachedPlugin_l446 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign when_DBusCachedPlugin_l466 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); + assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; + assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; + assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; + assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; + always @(*) begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; + writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; + writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; + end + + assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; + assign switch_Misc_l210 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; + end + + assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; + end + + always @(*) begin + case(switch_Misc_l210) + 2'b00 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; + end + 2'b01 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; + end + default : begin + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; + end + endcase + end + + assign when_DBusCachedPlugin_l492 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_decode_BRANCH_CTRL_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_BRANCH_CTRL_4 = ((decode_INSTRUCTION & 32'h00000018) == 32'h0); + assign _zz_decode_BRANCH_CTRL_5 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_BRANCH_CTRL_6 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_BRANCH_CTRL_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_decode_BRANCH_CTRL_8 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00100050); + assign _zz_decode_BRANCH_CTRL_2 = {(|{_zz_decode_BRANCH_CTRL_6,(_zz__zz_decode_BRANCH_CTRL_2 == _zz__zz_decode_BRANCH_CTRL_2_1)}),{(|(_zz__zz_decode_BRANCH_CTRL_2_2 == _zz__zz_decode_BRANCH_CTRL_2_3)),{(|_zz_decode_BRANCH_CTRL_8),{(|_zz__zz_decode_BRANCH_CTRL_2_4),{_zz__zz_decode_BRANCH_CTRL_2_5,{_zz__zz_decode_BRANCH_CTRL_2_8,_zz__zz_decode_BRANCH_CTRL_2_11}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_BRANCH_CTRL_2[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_BRANCH_CTRL_2[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_BRANCH_CTRL_2[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_BRANCH_CTRL_2[19 : 18]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_BRANCH_CTRL_2[22 : 21]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_BRANCH_CTRL_2[29 : 28]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; + assign _zz_decode_BRANCH_CTRL_9 = _zz_decode_BRANCH_CTRL_2[32 : 31]; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL_9; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_2) begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_2) begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_2) begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + AluBitwiseCtrlEnum_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @(*) begin + case(execute_ALU_CTRL) + AluCtrlEnum_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; + end + AluCtrlEnum_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; + end + default : begin + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; + end + endcase + end + + always @(*) begin + case(decode_SRC1_CTRL) + Src1CtrlEnum_RS : begin + _zz_decode_SRC1_1 = _zz_decode_SRC1; + end + Src1CtrlEnum_PC_INCREMENT : begin + _zz_decode_SRC1_1 = {29'd0, _zz__zz_decode_SRC1_1}; + end + Src1CtrlEnum_IMU : begin + _zz_decode_SRC1_1 = {decode_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_decode_SRC1_1 = {27'd0, _zz__zz_decode_SRC1_1_1}; + end + endcase + end + + assign _zz_decode_SRC2_2 = decode_INSTRUCTION[31]; + always @(*) begin + _zz_decode_SRC2_3[19] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[18] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[17] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[16] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[15] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[14] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[13] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[12] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[11] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[10] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[9] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[8] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[7] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[6] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[5] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[4] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[3] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[2] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[1] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[0] = _zz_decode_SRC2_2; + end + + assign _zz_decode_SRC2_4 = _zz__zz_decode_SRC2_4[11]; + always @(*) begin + _zz_decode_SRC2_5[19] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[18] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[17] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[16] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[15] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[14] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[13] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[12] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[11] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[10] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[9] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[8] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[7] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[6] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[5] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[4] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[3] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[2] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[1] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[0] = _zz_decode_SRC2_4; + end + + always @(*) begin + case(decode_SRC2_CTRL) + Src2CtrlEnum_RS : begin + _zz_decode_SRC2_6 = _zz_decode_SRC2_1; + end + Src2CtrlEnum_IMI : begin + _zz_decode_SRC2_6 = {_zz_decode_SRC2_3,decode_INSTRUCTION[31 : 20]}; + end + Src2CtrlEnum_IMS : begin + _zz_decode_SRC2_6 = {_zz_decode_SRC2_5,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_decode_SRC2_6 = _zz_decode_SRC2; + end + endcase + end + + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == ShiftCtrlEnum_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; + _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; + _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; + _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; + _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; + _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; + _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; + _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; + _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; + _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; + _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; + _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; + _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; + _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; + _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; + _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; + _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; + _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; + _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; + _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; + _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; + _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; + _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; + _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; + _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; + _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; + _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; + _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; + _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; + _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; + _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; + _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; + end + end + + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); + assign when_MulPlugin_l65 = ((execute_arbitration_isValid && execute_IS_MUL) && (execute_MulPlugin_delayLogic_counter != 1'b1)); + assign when_MulPlugin_l70 = ((! execute_arbitration_isStuck) || execute_arbitration_isStuckByOthers); + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) + 2'b01 : begin + execute_MulPlugin_aSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_aSigned = 1'b1; + end + default : begin + execute_MulPlugin_aSigned = 1'b0; + end + endcase + end + + always @(*) begin + case(switch_MulPlugin_l87) + 2'b01 : begin + execute_MulPlugin_bSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_bSigned = 1'b0; + end + default : begin + execute_MulPlugin_bSigned = 1'b0; + end + endcase + end + + assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; + assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; + assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; + assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; + assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; + assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; + assign memory_MulDivIterativePlugin_frontendOk = 1'b1; + always @(*) begin + memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin + memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @(*) begin + memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; + if(when_MulDivIterativePlugin_l162) begin + memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == 6'h21); + assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement); + always @(*) begin + if(memory_MulDivIterativePlugin_div_counter_willOverflow) begin + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; + end else begin + memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_memory_MulDivIterativePlugin_div_counter_valueNext); + end + if(memory_MulDivIterativePlugin_div_counter_willClear) begin + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; + end + end + + assign when_MulDivIterativePlugin_l126 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); + assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted = memory_MulDivIterativePlugin_rs1[31 : 0]; + assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31]}; + assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator); + assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder : _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1); + assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); + assign _zz_memory_MulDivIterativePlugin_div_result = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_MulDivIterativePlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_MulDivIterativePlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_MulDivIterativePlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_MulDivIterativePlugin_rs1_1[31 : 0] = execute_RS1; + end + + always @(*) begin + CsrPlugin_privilege = 2'b11; + if(CsrPlugin_forceMachineWire) begin + CsrPlugin_privilege = 2'b11; + end + end + + assign _zz_when_CsrPlugin_l965 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l965_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l965_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(CsrPlugin_selfException_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(BranchPlugin_branchExceptionPort_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(DBusCachedPlugin_exceptionBus_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + end + if(writeBack_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign when_CsrPlugin_l922 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l922_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l922_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l922_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l935 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l959 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l965 = ((_zz_when_CsrPlugin_l965 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l965_1 = ((_zz_when_CsrPlugin_l965_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l965_2 = ((_zz_when_CsrPlugin_l965_2 && 1'b1) && (! 1'b0)); + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_lastStageWasWfi = 1'b0; + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + assign when_CsrPlugin_l993 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l993_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l993_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l998 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(when_CsrPlugin_l1004) begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException) begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign when_CsrPlugin_l1004 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @(*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException) begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @(*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException) begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @(*) begin + CsrPlugin_xtvec_mode = 2'bxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign when_CsrPlugin_l1032 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1077 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == EnvCtrlEnum_XRET)); + assign switch_CsrPlugin_l1081 = writeBack_INSTRUCTION[29 : 28]; + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1129 = (|{(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == EnvCtrlEnum_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == EnvCtrlEnum_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_XRET))}}); + assign execute_CsrPlugin_blockedBySideEffects = ((|{writeBack_arbitration_isValid,memory_arbitration_isValid}) || 1'b0); + always @(*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_3860) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_769) begin + if(execute_CSR_WRITE_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_768) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_833) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_832) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_835) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1310) begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(when_CsrPlugin_l1315) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @(*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if(when_CsrPlugin_l1149) begin + if(when_CsrPlugin_l1150) begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @(*) begin + CsrPlugin_selfException_valid = 1'b0; + if(when_CsrPlugin_l1142) begin + CsrPlugin_selfException_valid = 1'b1; + end + if(when_CsrPlugin_l1157) begin + CsrPlugin_selfException_valid = 1'b1; + end + if(when_CsrPlugin_l1167) begin + CsrPlugin_selfException_valid = 1'b1; + end + end + + always @(*) begin + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(when_CsrPlugin_l1142) begin + CsrPlugin_selfException_payload_code = 4'b0010; + end + if(when_CsrPlugin_l1157) begin + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = 4'b1000; + end + default : begin + CsrPlugin_selfException_payload_code = 4'b1011; + end + endcase + end + if(when_CsrPlugin_l1167) begin + CsrPlugin_selfException_payload_code = 4'b0011; + end + end + + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + assign when_CsrPlugin_l1142 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign when_CsrPlugin_l1149 = (execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_XRET)); + assign when_CsrPlugin_l1150 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1157 = (execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_ECALL)); + assign when_CsrPlugin_l1167 = ((execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_EBREAK)) && CsrPlugin_allowEbreakException); + always @(*) begin + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(when_CsrPlugin_l1310) begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @(*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(when_CsrPlugin_l1310) begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l210_1 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l210_1) + 1'b0 : begin + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; + end + default : begin + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1189 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1193 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign switch_Misc_l210_2 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l210_2) + 3'b000 : begin + _zz_execute_BRANCH_DO = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_DO = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_DO = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_DO = execute_SRC_LESS; + end + endcase + end + + always @(*) begin + case(execute_BRANCH_CTRL) + BranchCtrlEnum_INC : begin + _zz_execute_BRANCH_DO_1 = 1'b0; + end + BranchCtrlEnum_JAL : begin + _zz_execute_BRANCH_DO_1 = 1'b1; + end + BranchCtrlEnum_JALR : begin + _zz_execute_BRANCH_DO_1 = 1'b1; + end + default : begin + _zz_execute_BRANCH_DO_1 = _zz_execute_BRANCH_DO; + end + endcase + end + + assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == BranchCtrlEnum_JALR) ? execute_RS1 : execute_PC); + assign _zz_execute_BranchPlugin_branch_src2 = _zz__zz_execute_BranchPlugin_branch_src2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + assign _zz_execute_BranchPlugin_branch_src2_2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[19] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[18] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[17] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[16] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[15] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[14] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[13] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[12] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[11] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; + end + + always @(*) begin + case(execute_BRANCH_CTRL) + BranchCtrlEnum_JAL : begin + _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_1,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + end + BranchCtrlEnum_JALR : begin + _zz_execute_BranchPlugin_branch_src2_6 = {_zz_execute_BranchPlugin_branch_src2_3,execute_INSTRUCTION[31 : 20]}; + end + default : begin + _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + end + endcase + end + + assign execute_BranchPlugin_branch_src2 = _zz_execute_BranchPlugin_branch_src2_6; + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; + assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; + assign when_DebugPlugin_l225 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)); + assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak)); + always @(*) begin + debug_bus_cmd_ready = 1'b1; + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l267) + 6'h01 : begin + if(debug_bus_cmd_payload_wr) begin + debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; + end + end + default : begin + end + endcase + end + end + + always @(*) begin + debug_bus_rsp_data = DebugPlugin_busReadDataReg; + if(when_DebugPlugin_l244) begin + debug_bus_rsp_data[0] = DebugPlugin_resetIt; + debug_bus_rsp_data[1] = DebugPlugin_haltIt; + debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; + debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; + debug_bus_rsp_data[4] = DebugPlugin_stepIt; + end + end + + assign when_DebugPlugin_l244 = (! _zz_when_DebugPlugin_l244); + always @(*) begin + IBusCachedPlugin_injectionPort_valid = 1'b0; + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l267) + 6'h01 : begin + if(debug_bus_cmd_payload_wr) begin + IBusCachedPlugin_injectionPort_valid = 1'b1; + end + end + default : begin + end + endcase + end + end + + assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; + assign switch_DebugPlugin_l267 = debug_bus_cmd_payload_address[7 : 2]; + assign when_DebugPlugin_l271 = debug_bus_cmd_payload_data[16]; + assign when_DebugPlugin_l271_1 = debug_bus_cmd_payload_data[24]; + assign when_DebugPlugin_l272 = debug_bus_cmd_payload_data[17]; + assign when_DebugPlugin_l272_1 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l273 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l274 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l275 = debug_bus_cmd_payload_data[18]; + assign when_DebugPlugin_l275_1 = debug_bus_cmd_payload_data[26]; + assign when_DebugPlugin_l295 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign when_DebugPlugin_l298 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign when_DebugPlugin_l311 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign when_DebugPlugin_l331 = (DebugPlugin_haltIt || DebugPlugin_stepIt); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_14 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_16 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_17 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_28 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_31 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_33 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_34 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_35 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_37 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_38 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_39 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; + assign when_Pipeline_l124_40 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_59 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_60 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck); + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + always @(*) begin + IBusCachedPlugin_injectionPort_ready = 1'b0; + case(switch_Fetcher_l365) + 3'b100 : begin + IBusCachedPlugin_injectionPort_ready = 1'b1; + end + default : begin + end + endcase + end + + assign when_Fetcher_l381 = (! decode_arbitration_isStuck); + assign when_Fetcher_l401 = (switch_Fetcher_l365 != 3'b000); + assign when_CsrPlugin_l1277 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_9 = (! execute_arbitration_isStuck); + assign switch_CsrPlugin_l723 = CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_CsrPlugin_csrMapping_readDataInit[12 : 11] = CsrPlugin_mstatus_MPP; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_1 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_1[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_1[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_1[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_2[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_2[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_2[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; + if(execute_CsrPlugin_csr_773) begin + _zz_CsrPlugin_csrMapping_readDataInit_3[31 : 2] = CsrPlugin_mtvec_base; + _zz_CsrPlugin_csrMapping_readDataInit_3[1 : 0] = CsrPlugin_mtvec_mode; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_4[31 : 0] = CsrPlugin_mepc; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; + if(execute_CsrPlugin_csr_832) begin + _zz_CsrPlugin_csrMapping_readDataInit_5[31 : 0] = CsrPlugin_mscratch; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_6[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_7[31 : 0] = CsrPlugin_mtval; + end + end + + assign CsrPlugin_csrMapping_readDataInit = ((((32'h0 | _zz_CsrPlugin_csrMapping_readDataInit) | (_zz_CsrPlugin_csrMapping_readDataInit_1 | _zz_CsrPlugin_csrMapping_readDataInit_2)) | ((_zz_CsrPlugin_csrMapping_readDataInit_3 | _zz_CsrPlugin_csrMapping_readDataInit_4) | (_zz_CsrPlugin_csrMapping_readDataInit_5 | _zz_CsrPlugin_csrMapping_readDataInit_6))) | _zz_CsrPlugin_csrMapping_readDataInit_7); + assign when_CsrPlugin_l1310 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1315 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + IBusCachedPlugin_fetchPc_pcReg <= 32'hf9000000; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; + _zz_IBusCachedPlugin_injector_decodeInput_valid <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + dBus_rsp_regNext_valid <= 1'b0; + DBusCachedPlugin_rspCounter <= 32'h0; + _zz_2 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + memory_MulDivIterativePlugin_div_counter_value <= 6'h0; + CsrPlugin_misa_base <= 2'b01; + CsrPlugin_misa_extensions <= 26'h0041101; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_mcycle <= 64'h0; + CsrPlugin_minstret <= 64'h0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + switch_Fetcher_l365 <= 3'b000; + end else begin + if(IBusCachedPlugin_fetchPc_correction) begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_output_fire) begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if(when_Fetcher_l134) begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_output_fire_1) begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(when_Fetcher_l134_1) begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(when_Fetcher_l161) begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + end + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + end + if(decode_arbitration_removeIt) begin + _zz_IBusCachedPlugin_injector_decodeInput_valid <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_output_ready) begin + _zz_IBusCachedPlugin_injector_decodeInput_valid <= (IBusCachedPlugin_iBusRsp_output_valid && (! IBusCachedPlugin_externalFlush)); + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if(when_Fetcher_l332) begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(when_Fetcher_l332_1) begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(when_Fetcher_l332_2) begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(when_Fetcher_l332_3) begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(when_Fetcher_l332_4) begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; + end + if(when_Fetcher_l332_5) begin + IBusCachedPlugin_injector_nextPcCalc_valids_5 <= IBusCachedPlugin_injector_nextPcCalc_valids_4; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; + end + if(iBus_rsp_valid) begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + end + if(dataCache_1_io_mem_cmd_valid) begin + dataCache_1_io_mem_cmd_rValid <= 1'b1; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_rValid <= 1'b0; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + end + dBus_rsp_regNext_valid <= dBus_rsp_valid; + if(dBus_rsp_valid) begin + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); + end + _zz_2 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring) begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(when_CsrPlugin_l922) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if(when_CsrPlugin_l922_1) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if(when_CsrPlugin_l922_2) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if(when_CsrPlugin_l922_3) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(when_CsrPlugin_l959) begin + if(when_CsrPlugin_l965) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(when_CsrPlugin_l965_1) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(when_CsrPlugin_l965_2) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l993) begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if(when_CsrPlugin_l993_1) begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if(when_CsrPlugin_l993_2) begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(when_CsrPlugin_l998) begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump) begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(when_CsrPlugin_l1032) begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(when_CsrPlugin_l1077) begin + case(switch_CsrPlugin_l1081) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l965_2,{_zz_when_CsrPlugin_l965_1,_zz_when_CsrPlugin_l965}} != 3'b000) || CsrPlugin_thirdPartyWake); + if(when_Pipeline_l151) begin + execute_arbitration_isValid <= 1'b0; + end + if(when_Pipeline_l154) begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(when_Pipeline_l151_1) begin + memory_arbitration_isValid <= 1'b0; + end + if(when_Pipeline_l154_1) begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(when_Pipeline_l151_2) begin + writeBack_arbitration_isValid <= 1'b0; + end + if(when_Pipeline_l154_2) begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(switch_Fetcher_l365) + 3'b000 : begin + if(IBusCachedPlugin_injectionPort_valid) begin + switch_Fetcher_l365 <= 3'b001; + end + end + 3'b001 : begin + switch_Fetcher_l365 <= 3'b010; + end + 3'b010 : begin + switch_Fetcher_l365 <= 3'b011; + end + 3'b011 : begin + if(when_Fetcher_l381) begin + switch_Fetcher_l365 <= 3'b100; + end + end + 3'b100 : begin + switch_Fetcher_l365 <= 3'b000; + end + default : begin + end + endcase + if(execute_CsrPlugin_csr_769) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30]; + CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0]; + end + end + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; + case(switch_CsrPlugin_l723) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b11; + end + default : begin + end + endcase + end + end + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; + end + end + end + end + + always @(posedge io_systemClk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_output_ready) begin + _zz_IBusCachedPlugin_injector_decodeInput_payload_pc <= IBusCachedPlugin_iBusRsp_output_payload_pc; + _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error <= IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst <= IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc <= IBusCachedPlugin_iBusRsp_output_payload_isRvc; + end + if(IBusCachedPlugin_injector_decodeInput_ready) begin + IBusCachedPlugin_injector_formal_rawInDecode <= IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(dataCache_1_io_mem_cmd_ready) begin + dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; + dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + dBus_rsp_regNext_payload_last <= dBus_rsp_payload_last; + dBus_rsp_regNext_payload_data <= dBus_rsp_payload_data; + dBus_rsp_regNext_payload_error <= dBus_rsp_payload_error; + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + execute_MulPlugin_delayLogic_counter <= (execute_MulPlugin_delayLogic_counter + 1'b1); + if(when_MulPlugin_l70) begin + execute_MulPlugin_delayLogic_counter <= 1'b0; + end + execute_MulPlugin_withOuputBuffer_mul_ll <= (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + execute_MulPlugin_withOuputBuffer_mul_lh <= ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + execute_MulPlugin_withOuputBuffer_mul_hl <= ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + execute_MulPlugin_withOuputBuffer_mul_hh <= ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + if(when_MulDivIterativePlugin_l126) begin + memory_MulDivIterativePlugin_div_done <= 1'b1; + end + if(when_MulDivIterativePlugin_l126_1) begin + memory_MulDivIterativePlugin_div_done <= 1'b0; + end + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin + memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; + memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; + if(when_MulDivIterativePlugin_l151) begin + memory_MulDivIterativePlugin_div_result <= _zz_memory_MulDivIterativePlugin_div_result_1[31:0]; + end + end + end + if(when_MulDivIterativePlugin_l162) begin + memory_MulDivIterativePlugin_accumulator <= 65'h0; + memory_MulDivIterativePlugin_rs1 <= ((_zz_memory_MulDivIterativePlugin_rs1 ? (~ _zz_memory_MulDivIterativePlugin_rs1_1) : _zz_memory_MulDivIterativePlugin_rs1_1) + _zz_memory_MulDivIterativePlugin_rs1_2); + memory_MulDivIterativePlugin_rs2 <= ((_zz_memory_MulDivIterativePlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_MulDivIterativePlugin_rs2_1); + memory_MulDivIterativePlugin_div_needRevert <= ((_zz_memory_MulDivIterativePlugin_rs1 ^ (_zz_memory_MulDivIterativePlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(CsrPlugin_selfException_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + end + if(BranchPlugin_branchExceptionPort_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + end + if(DBusCachedPlugin_exceptionBus_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(when_CsrPlugin_l959) begin + if(when_CsrPlugin_l965) begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(when_CsrPlugin_l965_1) begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(when_CsrPlugin_l965_2) begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(when_CsrPlugin_l1032) begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException) begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if(when_Pipeline_l124) begin + decode_to_execute_PC <= _zz_decode_SRC2; + end + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= execute_PC; + end + if(when_Pipeline_l124_2) begin + memory_to_writeBack_PC <= memory_PC; + end + if(when_Pipeline_l124_3) begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if(when_Pipeline_l124_4) begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if(when_Pipeline_l124_5) begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if(when_Pipeline_l124_6) begin + decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; + end + if(when_Pipeline_l124_7) begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if(when_Pipeline_l124_8) begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; + end + if(when_Pipeline_l124_9) begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if(when_Pipeline_l124_10) begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if(when_Pipeline_l124_11) begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if(when_Pipeline_l124_12) begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if(when_Pipeline_l124_13) begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if(when_Pipeline_l124_14) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; + end + if(when_Pipeline_l124_15) begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if(when_Pipeline_l124_16) begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if(when_Pipeline_l124_17) begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if(when_Pipeline_l124_18) begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if(when_Pipeline_l124_19) begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if(when_Pipeline_l124_20) begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if(when_Pipeline_l124_21) begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if(when_Pipeline_l124_22) begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if(when_Pipeline_l124_23) begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if(when_Pipeline_l124_24) begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if(when_Pipeline_l124_25) begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if(when_Pipeline_l124_26) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; + end + if(when_Pipeline_l124_27) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; + end + if(when_Pipeline_l124_28) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; + end + if(when_Pipeline_l124_29) begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if(when_Pipeline_l124_30) begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if(when_Pipeline_l124_31) begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if(when_Pipeline_l124_32) begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if(when_Pipeline_l124_33) begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if(when_Pipeline_l124_34) begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if(when_Pipeline_l124_35) begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if(when_Pipeline_l124_36) begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if(when_Pipeline_l124_37) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; + end + if(when_Pipeline_l124_38) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; + end + if(when_Pipeline_l124_39) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; + end + if(when_Pipeline_l124_40) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; + end + if(when_Pipeline_l124_41) begin + decode_to_execute_RS1 <= _zz_decode_SRC1; + end + if(when_Pipeline_l124_42) begin + decode_to_execute_RS2 <= _zz_decode_SRC2_1; + end + if(when_Pipeline_l124_43) begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if(when_Pipeline_l124_44) begin + decode_to_execute_SRC1 <= decode_SRC1; + end + if(when_Pipeline_l124_45) begin + decode_to_execute_SRC2 <= decode_SRC2; + end + if(when_Pipeline_l124_46) begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if(when_Pipeline_l124_47) begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if(when_Pipeline_l124_48) begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if(when_Pipeline_l124_49) begin + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; + end + if(when_Pipeline_l124_50) begin + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; + end + if(when_Pipeline_l124_51) begin + execute_to_memory_MEMORY_VIRTUAL_ADDRESS <= execute_MEMORY_VIRTUAL_ADDRESS; + end + if(when_Pipeline_l124_52) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; + end + if(when_Pipeline_l124_53) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; + end + if(when_Pipeline_l124_54) begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if(when_Pipeline_l124_55) begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if(when_Pipeline_l124_56) begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if(when_Pipeline_l124_57) begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if(when_Pipeline_l124_58) begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if(when_Pipeline_l124_59) begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if(when_Pipeline_l124_60) begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if(when_Pipeline_l124_61) begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if(when_Pipeline_l124_62) begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if(when_Fetcher_l401) begin + _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst <= IBusCachedPlugin_injectionPort_payload; + end + if(when_CsrPlugin_l1277) begin + execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); + end + if(when_CsrPlugin_l1277_1) begin + execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); + end + if(when_CsrPlugin_l1277_2) begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if(when_CsrPlugin_l1277_3) begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if(when_CsrPlugin_l1277_4) begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if(when_CsrPlugin_l1277_5) begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if(when_CsrPlugin_l1277_6) begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if(when_CsrPlugin_l1277_7) begin + execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); + end + if(when_CsrPlugin_l1277_8) begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if(when_CsrPlugin_l1277_9) begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; + end + end + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; + end + end + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; + end + end + if(execute_CsrPlugin_csr_832) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; + end + end + end + + always @(posedge io_systemClk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready) begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); + if(writeBack_arbitration_isValid) begin + DebugPlugin_busReadDataReg <= _zz_decode_RS2_2; + end + _zz_when_DebugPlugin_l244 <= debug_bus_cmd_payload_address[2]; + if(when_DebugPlugin_l295) begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @(posedge io_systemClk) begin + if(debugCd_logic_outputReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_debugUsed <= 1'b0; + DebugPlugin_disableEbreak <= 1'b0; + end else begin + if(when_DebugPlugin_l225) begin + DebugPlugin_godmode <= 1'b1; + end + if(debug_bus_cmd_valid) begin + DebugPlugin_debugUsed <= 1'b1; + end + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l267) + 6'h0 : begin + if(debug_bus_cmd_payload_wr) begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(when_DebugPlugin_l271) begin + DebugPlugin_resetIt <= 1'b1; + end + if(when_DebugPlugin_l271_1) begin + DebugPlugin_resetIt <= 1'b0; + end + if(when_DebugPlugin_l272) begin + DebugPlugin_haltIt <= 1'b1; + end + if(when_DebugPlugin_l272_1) begin + DebugPlugin_haltIt <= 1'b0; + end + if(when_DebugPlugin_l273) begin + DebugPlugin_haltedByBreak <= 1'b0; + end + if(when_DebugPlugin_l274) begin + DebugPlugin_godmode <= 1'b0; + end + if(when_DebugPlugin_l275) begin + DebugPlugin_disableEbreak <= 1'b1; + end + if(when_DebugPlugin_l275_1) begin + DebugPlugin_disableEbreak <= 1'b0; + end + end + end + default : begin + end + endcase + end + if(when_DebugPlugin_l295) begin + if(when_DebugPlugin_l298) begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; + end + end + if(when_DebugPlugin_l311) begin + if(decode_arbitration_isValid) begin + DebugPlugin_haltIt <= 1'b1; + end + end + end + end + + +endmodule + +module BufferCC_3_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_dataIn, + output io_dataOut, + input io_systemClk, + input debugCd_logic_outputReset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge io_systemClk or posedge debugCd_logic_outputReset) begin + if(debugCd_logic_outputReset) begin + buffers_0 <= 1'b1; + buffers_1 <= 1'b1; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module BufferCC_2_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_dataIn, + output io_dataOut, + input io_systemClk, + input io_asyncReset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge io_systemClk or posedge io_asyncReset) begin + if(io_asyncReset) begin + buffers_0 <= 1'b1; + buffers_1 <= 1'b1; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module StreamFifo_3_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_push_valid, + output io_push_ready, + input [7:0] io_push_payload_data, + output io_pop_valid, + input io_pop_ready, + output [7:0] io_pop_payload_data, + input io_flush, + output [8:0] io_occupancy, + output [8:0] io_availability, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [7:0] _zz_logic_ram_port0; + wire [7:0] _zz_logic_pushPtr_valueNext; + wire [0:0] _zz_logic_pushPtr_valueNext_1; + wire [7:0] _zz_logic_popPtr_valueNext; + wire [0:0] _zz_logic_popPtr_valueNext_1; + wire _zz_logic_ram_port; + wire _zz_io_pop_payload_data; + wire [7:0] _zz_io_availability; + reg _zz_1; + reg logic_pushPtr_willIncrement; + reg logic_pushPtr_willClear; + reg [7:0] logic_pushPtr_valueNext; + reg [7:0] logic_pushPtr_value; + wire logic_pushPtr_willOverflowIfInc; + wire logic_pushPtr_willOverflow; + reg logic_popPtr_willIncrement; + reg logic_popPtr_willClear; + reg [7:0] logic_popPtr_valueNext; + reg [7:0] logic_popPtr_value; + wire logic_popPtr_willOverflowIfInc; + wire logic_popPtr_willOverflow; + wire logic_ptrMatch; + reg logic_risingOccupancy; + wire logic_pushing; + wire logic_popping; + wire logic_empty; + wire logic_full; + reg _zz_io_pop_valid; + wire when_Stream_l1037; + wire [7:0] logic_ptrDif; + reg [7:0] logic_ram [0:255]; + + assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; + assign _zz_logic_pushPtr_valueNext = {7'd0, _zz_logic_pushPtr_valueNext_1}; + assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; + assign _zz_logic_popPtr_valueNext = {7'd0, _zz_logic_popPtr_valueNext_1}; + assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); + assign _zz_io_pop_payload_data = 1'b1; + always @(posedge io_systemClk) begin + if(_zz_io_pop_payload_data) begin + _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_1) begin + logic_ram[logic_pushPtr_value] <= io_push_payload_data; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_pushing) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willIncrement = 1'b0; + if(logic_pushing) begin + logic_pushPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willClear = 1'b0; + if(io_flush) begin + logic_pushPtr_willClear = 1'b1; + end + end + + assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 8'hff); + assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); + always @(*) begin + logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); + if(logic_pushPtr_willClear) begin + logic_pushPtr_valueNext = 8'h0; + end + end + + always @(*) begin + logic_popPtr_willIncrement = 1'b0; + if(logic_popping) begin + logic_popPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_popPtr_willClear = 1'b0; + if(io_flush) begin + logic_popPtr_willClear = 1'b1; + end + end + + assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 8'hff); + assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); + always @(*) begin + logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); + if(logic_popPtr_willClear) begin + logic_popPtr_valueNext = 8'h0; + end + end + + assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); + assign logic_pushing = (io_push_valid && io_push_ready); + assign logic_popping = (io_pop_valid && io_pop_ready); + assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); + assign logic_full = (logic_ptrMatch && logic_risingOccupancy); + assign io_push_ready = (! logic_full); + assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); + assign io_pop_payload_data = _zz_logic_ram_port0[7 : 0]; + assign when_Stream_l1037 = (logic_pushing != logic_popping); + assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); + assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; + assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + logic_pushPtr_value <= 8'h0; + logic_popPtr_value <= 8'h0; + logic_risingOccupancy <= 1'b0; + _zz_io_pop_valid <= 1'b0; + end else begin + logic_pushPtr_value <= logic_pushPtr_valueNext; + logic_popPtr_value <= logic_popPtr_valueNext; + _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); + if(when_Stream_l1037) begin + logic_risingOccupancy <= logic_pushing; + end + if(io_flush) begin + logic_risingOccupancy <= 1'b0; + end + end + end + + +endmodule + +module StreamFifo_2_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_push_valid, + output io_push_ready, + input io_push_payload_kind, + input io_push_payload_read, + input io_push_payload_write, + input [7:0] io_push_payload_data, + output io_pop_valid, + input io_pop_ready, + output io_pop_payload_kind, + output io_pop_payload_read, + output io_pop_payload_write, + output [7:0] io_pop_payload_data, + input io_flush, + output [8:0] io_occupancy, + output [8:0] io_availability, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [10:0] _zz_logic_ram_port0; + wire [7:0] _zz_logic_pushPtr_valueNext; + wire [0:0] _zz_logic_pushPtr_valueNext_1; + wire [7:0] _zz_logic_popPtr_valueNext; + wire [0:0] _zz_logic_popPtr_valueNext_1; + wire _zz_logic_ram_port; + wire _zz__zz_io_pop_payload_kind; + wire [10:0] _zz_logic_ram_port_1; + wire [7:0] _zz_io_availability; + reg _zz_1; + reg logic_pushPtr_willIncrement; + reg logic_pushPtr_willClear; + reg [7:0] logic_pushPtr_valueNext; + reg [7:0] logic_pushPtr_value; + wire logic_pushPtr_willOverflowIfInc; + wire logic_pushPtr_willOverflow; + reg logic_popPtr_willIncrement; + reg logic_popPtr_willClear; + reg [7:0] logic_popPtr_valueNext; + reg [7:0] logic_popPtr_value; + wire logic_popPtr_willOverflowIfInc; + wire logic_popPtr_willOverflow; + wire logic_ptrMatch; + reg logic_risingOccupancy; + wire logic_pushing; + wire logic_popping; + wire logic_empty; + wire logic_full; + reg _zz_io_pop_valid; + wire [10:0] _zz_io_pop_payload_kind; + wire when_Stream_l1037; + wire [7:0] logic_ptrDif; + reg [10:0] logic_ram [0:255]; + + assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; + assign _zz_logic_pushPtr_valueNext = {7'd0, _zz_logic_pushPtr_valueNext_1}; + assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; + assign _zz_logic_popPtr_valueNext = {7'd0, _zz_logic_popPtr_valueNext_1}; + assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); + assign _zz__zz_io_pop_payload_kind = 1'b1; + assign _zz_logic_ram_port_1 = {io_push_payload_data,{io_push_payload_write,{io_push_payload_read,io_push_payload_kind}}}; + always @(posedge io_systemClk) begin + if(_zz__zz_io_pop_payload_kind) begin + _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_1) begin + logic_ram[logic_pushPtr_value] <= _zz_logic_ram_port_1; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_pushing) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willIncrement = 1'b0; + if(logic_pushing) begin + logic_pushPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willClear = 1'b0; + if(io_flush) begin + logic_pushPtr_willClear = 1'b1; + end + end + + assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 8'hff); + assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); + always @(*) begin + logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); + if(logic_pushPtr_willClear) begin + logic_pushPtr_valueNext = 8'h0; + end + end + + always @(*) begin + logic_popPtr_willIncrement = 1'b0; + if(logic_popping) begin + logic_popPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_popPtr_willClear = 1'b0; + if(io_flush) begin + logic_popPtr_willClear = 1'b1; + end + end + + assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 8'hff); + assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); + always @(*) begin + logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); + if(logic_popPtr_willClear) begin + logic_popPtr_valueNext = 8'h0; + end + end + + assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); + assign logic_pushing = (io_push_valid && io_push_ready); + assign logic_popping = (io_pop_valid && io_pop_ready); + assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); + assign logic_full = (logic_ptrMatch && logic_risingOccupancy); + assign io_push_ready = (! logic_full); + assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); + assign _zz_io_pop_payload_kind = _zz_logic_ram_port0; + assign io_pop_payload_kind = _zz_io_pop_payload_kind[0]; + assign io_pop_payload_read = _zz_io_pop_payload_kind[1]; + assign io_pop_payload_write = _zz_io_pop_payload_kind[2]; + assign io_pop_payload_data = _zz_io_pop_payload_kind[10 : 3]; + assign when_Stream_l1037 = (logic_pushing != logic_popping); + assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); + assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; + assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + logic_pushPtr_value <= 8'h0; + logic_popPtr_value <= 8'h0; + logic_risingOccupancy <= 1'b0; + _zz_io_pop_valid <= 1'b0; + end else begin + logic_pushPtr_value <= logic_pushPtr_valueNext; + logic_popPtr_value <= logic_popPtr_valueNext; + _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); + if(when_Stream_l1037) begin + logic_risingOccupancy <= logic_pushing; + end + if(io_flush) begin + logic_risingOccupancy <= 1'b0; + end + end + end + + +endmodule + +module TopLevel_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_config_kind_cpol, + input io_config_kind_cpha, + input [11:0] io_config_sclkToogle, + input [1:0] io_config_mod, + input [0:0] io_config_ss_activeHigh, + input [11:0] io_config_ss_setup, + input [11:0] io_config_ss_hold, + input [11:0] io_config_ss_disable, + input io_cmd_valid, + output reg io_cmd_ready, + input io_cmd_payload_kind, + input io_cmd_payload_read, + input io_cmd_payload_write, + input [7:0] io_cmd_payload_data, + output io_rsp_valid, + output [7:0] io_rsp_payload_data, + output [0:0] io_spi_sclk_write, + output reg io_spi_data_0_writeEnable, + input [0:0] io_spi_data_0_read, + output reg [0:0] io_spi_data_0_write, + output reg io_spi_data_1_writeEnable, + input [0:0] io_spi_data_1_read, + output reg [0:0] io_spi_data_1_write, + output reg io_spi_data_2_writeEnable, + input [0:0] io_spi_data_2_read, + output reg [0:0] io_spi_data_2_write, + output reg io_spi_data_3_writeEnable, + input [0:0] io_spi_data_3_read, + output reg [0:0] io_spi_data_3_write, + output [0:0] io_spi_ss, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [0:0] _zz_outputPhy_dataWrite_3; + wire [2:0] _zz_outputPhy_dataWrite_4; + wire [2:0] _zz_outputPhy_dataWrite_5; + reg [1:0] _zz_outputPhy_dataWrite_6; + wire [1:0] _zz_outputPhy_dataWrite_7; + wire [2:0] _zz_outputPhy_dataWrite_8; + reg [3:0] _zz_outputPhy_dataWrite_9; + wire [0:0] _zz_outputPhy_dataWrite_10; + wire [2:0] _zz_outputPhy_dataWrite_11; + wire [3:0] _zz_inputPhy_dataRead; + wire [3:0] _zz_inputPhy_dataRead_1; + wire [3:0] _zz_inputPhy_dataRead_2; + wire [3:0] _zz_inputPhy_dataRead_3; + wire [3:0] _zz_inputPhy_dataRead_4; + wire [3:0] _zz_inputPhy_dataRead_5; + wire [3:0] _zz_inputPhy_dataRead_6; + wire [8:0] _zz_inputPhy_bufferNext; + wire [10:0] _zz_inputPhy_bufferNext_1; + reg [11:0] timer_counter; + reg timer_reset; + wire timer_ss_setupHit; + wire timer_ss_holdHit; + wire timer_ss_disableHit; + wire timer_sclkToogleHit; + reg fsm_state; + reg [2:0] fsm_counter; + reg [2:0] _zz_fsm_counterPlus; + wire [2:0] fsm_counterPlus; + reg fsm_fastRate; + reg fsm_isDdr; + reg [2:0] fsm_counterMax; + reg fsm_lateSampling; + reg fsm_readFill; + reg fsm_readDone; + reg [0:0] fsm_ss; + wire when_SpiXdrMasterCtrl_l739; + wire when_SpiXdrMasterCtrl_l742; + wire when_SpiXdrMasterCtrl_l749; + wire when_SpiXdrMasterCtrl_l751; + wire when_SpiXdrMasterCtrl_l758; + wire when_SpiXdrMasterCtrl_l764; + wire when_SpiXdrMasterCtrl_l781; + reg [0:0] outputPhy_sclkWrite; + wire [0:0] _zz_io_spi_sclk_write; + wire when_SpiXdrMasterCtrl_l796; + reg [3:0] outputPhy_dataWrite; + reg [2:0] outputPhy_widthSel; + reg [2:0] outputPhy_offset; + wire [7:0] _zz_outputPhy_dataWrite; + wire [7:0] _zz_outputPhy_dataWrite_1; + wire [7:0] _zz_outputPhy_dataWrite_2; + wire when_SpiXdrMasterCtrl_l839; + wire when_SpiXdrMasterCtrl_l839_1; + reg [1:0] io_config_mod_delay_1; + reg [1:0] inputPhy_mod; + reg fsm_readFill_delay_1; + reg inputPhy_readFill; + reg fsm_readDone_delay_1; + reg inputPhy_readDone; + reg [6:0] inputPhy_buffer; + reg [7:0] inputPhy_bufferNext; + reg [2:0] inputPhy_widthSel; + wire [3:0] inputPhy_dataWrite; + reg [3:0] inputPhy_dataRead; + reg fsm_state_delay_1; + reg fsm_state_delay_2; + wire when_SpiXdrMasterCtrl_l861; + reg [3:0] inputPhy_dataReadBuffer; + + assign _zz_outputPhy_dataWrite_4 = (_zz_outputPhy_dataWrite_5 >>> 0); + assign _zz_outputPhy_dataWrite_5 = (outputPhy_offset - fsm_counter); + assign _zz_outputPhy_dataWrite_7 = (_zz_outputPhy_dataWrite_8 >>> 1); + assign _zz_outputPhy_dataWrite_8 = (outputPhy_offset - fsm_counter); + assign _zz_outputPhy_dataWrite_10 = (_zz_outputPhy_dataWrite_11 >>> 2); + assign _zz_outputPhy_dataWrite_11 = (outputPhy_offset - fsm_counter); + assign _zz_inputPhy_dataRead = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_1 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_2 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_3 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_4 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_5 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_6 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[1 : 0]}; + assign _zz_inputPhy_bufferNext_1 = {inputPhy_buffer,inputPhy_dataRead[3 : 0]}; + always @(*) begin + case(_zz_outputPhy_dataWrite_4) + 3'b000 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[0 : 0]; + 3'b001 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[1 : 1]; + 3'b010 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[2 : 2]; + 3'b011 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[3 : 3]; + 3'b100 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[4 : 4]; + 3'b101 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[5 : 5]; + 3'b110 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[6 : 6]; + default : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[7 : 7]; + endcase + end + + always @(*) begin + case(_zz_outputPhy_dataWrite_7) + 2'b00 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[1 : 0]; + 2'b01 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[3 : 2]; + 2'b10 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[5 : 4]; + default : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[7 : 6]; + endcase + end + + always @(*) begin + case(_zz_outputPhy_dataWrite_10) + 1'b0 : _zz_outputPhy_dataWrite_9 = _zz_outputPhy_dataWrite_2[3 : 0]; + default : _zz_outputPhy_dataWrite_9 = _zz_outputPhy_dataWrite_2[7 : 4]; + endcase + end + + always @(*) begin + timer_reset = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l739) begin + timer_reset = timer_sclkToogleHit; + end else begin + if(!when_SpiXdrMasterCtrl_l758) begin + if(when_SpiXdrMasterCtrl_l764) begin + if(timer_ss_holdHit) begin + timer_reset = 1'b1; + end + end + end + end + end + if(when_SpiXdrMasterCtrl_l781) begin + timer_reset = 1'b1; + end + end + + assign timer_ss_setupHit = (timer_counter == io_config_ss_setup); + assign timer_ss_holdHit = (timer_counter == io_config_ss_hold); + assign timer_ss_disableHit = (timer_counter == io_config_ss_disable); + assign timer_sclkToogleHit = (timer_counter == io_config_sclkToogle); + always @(*) begin + _zz_fsm_counterPlus = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + _zz_fsm_counterPlus = 3'b001; + end + 2'b01 : begin + _zz_fsm_counterPlus = 3'b010; + end + 2'b10 : begin + _zz_fsm_counterPlus = 3'b100; + end + default : begin + end + endcase + end + + assign fsm_counterPlus = (fsm_counter + _zz_fsm_counterPlus); + always @(*) begin + fsm_fastRate = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_fastRate = 1'b0; + end + 2'b01 : begin + fsm_fastRate = 1'b0; + end + 2'b10 : begin + fsm_fastRate = 1'b0; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_isDdr = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_isDdr = 1'b0; + end + 2'b01 : begin + fsm_isDdr = 1'b0; + end + 2'b10 : begin + fsm_isDdr = 1'b0; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_counterMax = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + fsm_counterMax = 3'b111; + end + 2'b01 : begin + fsm_counterMax = 3'b110; + end + 2'b10 : begin + fsm_counterMax = 3'b100; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_lateSampling = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_lateSampling = 1'b1; + end + 2'b01 : begin + fsm_lateSampling = 1'b1; + end + 2'b10 : begin + fsm_lateSampling = 1'b1; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_readFill = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l739) begin + if(when_SpiXdrMasterCtrl_l742) begin + fsm_readFill = 1'b1; + end + end + end + end + + always @(*) begin + fsm_readDone = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l739) begin + if(when_SpiXdrMasterCtrl_l742) begin + fsm_readDone = (io_cmd_payload_read && (fsm_counter == fsm_counterMax)); + end + end + end + end + + assign io_spi_ss = (~ (fsm_ss ^ io_config_ss_activeHigh)); + always @(*) begin + io_cmd_ready = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l739) begin + if(when_SpiXdrMasterCtrl_l749) begin + if(when_SpiXdrMasterCtrl_l751) begin + io_cmd_ready = 1'b1; + end + end + end else begin + if(when_SpiXdrMasterCtrl_l758) begin + if(timer_ss_setupHit) begin + io_cmd_ready = 1'b1; + end + end else begin + if(!when_SpiXdrMasterCtrl_l764) begin + if(timer_ss_disableHit) begin + io_cmd_ready = 1'b1; + end + end + end + end + end + end + + assign when_SpiXdrMasterCtrl_l739 = (! io_cmd_payload_kind); + assign when_SpiXdrMasterCtrl_l742 = ((timer_sclkToogleHit && (((! fsm_state) ^ fsm_lateSampling) || fsm_isDdr)) || fsm_fastRate); + assign when_SpiXdrMasterCtrl_l749 = ((timer_sclkToogleHit && (fsm_state || fsm_isDdr)) || fsm_fastRate); + assign when_SpiXdrMasterCtrl_l751 = (fsm_counter == fsm_counterMax); + assign when_SpiXdrMasterCtrl_l758 = io_cmd_payload_data[7]; + assign when_SpiXdrMasterCtrl_l764 = (! fsm_state); + assign when_SpiXdrMasterCtrl_l781 = ((! io_cmd_valid) || io_cmd_ready); + always @(*) begin + outputPhy_sclkWrite = 1'b0; + if(when_SpiXdrMasterCtrl_l796) begin + case(io_config_mod) + 2'b00 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + 2'b01 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + 2'b10 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + default : begin + end + endcase + end + end + + assign _zz_io_spi_sclk_write[0] = io_config_kind_cpol; + assign io_spi_sclk_write = (outputPhy_sclkWrite ^ _zz_io_spi_sclk_write); + assign when_SpiXdrMasterCtrl_l796 = (io_cmd_valid && (! io_cmd_payload_kind)); + always @(*) begin + outputPhy_widthSel = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + outputPhy_widthSel = 3'b000; + end + 2'b01 : begin + outputPhy_widthSel = 3'b001; + end + 2'b10 : begin + outputPhy_widthSel = 3'b010; + end + default : begin + end + endcase + end + + always @(*) begin + outputPhy_offset = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + outputPhy_offset = 3'b111; + end + 2'b01 : begin + outputPhy_offset = 3'b111; + end + 2'b10 : begin + outputPhy_offset = 3'b111; + end + default : begin + end + endcase + end + + always @(*) begin + outputPhy_dataWrite = 4'bxxxx; + case(outputPhy_widthSel) + 3'b000 : begin + outputPhy_dataWrite[0 : 0] = _zz_outputPhy_dataWrite_3; + end + 3'b001 : begin + outputPhy_dataWrite[1 : 0] = _zz_outputPhy_dataWrite_6; + end + 3'b010 : begin + outputPhy_dataWrite[3 : 0] = _zz_outputPhy_dataWrite_9; + end + default : begin + end + endcase + end + + assign _zz_outputPhy_dataWrite = io_cmd_payload_data; + assign _zz_outputPhy_dataWrite_1 = io_cmd_payload_data; + assign _zz_outputPhy_dataWrite_2 = io_cmd_payload_data; + always @(*) begin + io_spi_data_0_writeEnable = 1'b0; + case(io_config_mod) + 2'b00 : begin + io_spi_data_0_writeEnable = 1'b1; + end + 2'b01 : begin + if(when_SpiXdrMasterCtrl_l839) begin + io_spi_data_0_writeEnable = 1'b1; + end + end + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l839_1) begin + io_spi_data_0_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_1_writeEnable = 1'b0; + case(io_config_mod) + 2'b01 : begin + if(when_SpiXdrMasterCtrl_l839) begin + io_spi_data_1_writeEnable = 1'b1; + end + end + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l839_1) begin + io_spi_data_1_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_2_writeEnable = 1'b0; + case(io_config_mod) + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l839_1) begin + io_spi_data_2_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_3_writeEnable = 1'b0; + case(io_config_mod) + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l839_1) begin + io_spi_data_3_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_0_write = 1'bx; + case(io_config_mod) + 2'b00 : begin + io_spi_data_0_write[0] = (outputPhy_dataWrite[0] || (! (io_cmd_valid && io_cmd_payload_write))); + end + 2'b01 : begin + io_spi_data_0_write[0] = outputPhy_dataWrite[0]; + end + 2'b10 : begin + io_spi_data_0_write[0] = outputPhy_dataWrite[0]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_1_write = 1'bx; + case(io_config_mod) + 2'b01 : begin + io_spi_data_1_write[0] = outputPhy_dataWrite[1]; + end + 2'b10 : begin + io_spi_data_1_write[0] = outputPhy_dataWrite[1]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_2_write = 1'bx; + case(io_config_mod) + 2'b10 : begin + io_spi_data_2_write[0] = outputPhy_dataWrite[2]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_3_write = 1'bx; + case(io_config_mod) + 2'b10 : begin + io_spi_data_3_write[0] = outputPhy_dataWrite[3]; + end + default : begin + end + endcase + end + + assign when_SpiXdrMasterCtrl_l839 = (io_cmd_valid && io_cmd_payload_write); + assign when_SpiXdrMasterCtrl_l839_1 = (io_cmd_valid && io_cmd_payload_write); + always @(*) begin + inputPhy_bufferNext = 8'bxxxxxxxx; + case(inputPhy_widthSel) + 3'b000 : begin + inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[0 : 0]}; + end + 3'b001 : begin + inputPhy_bufferNext = _zz_inputPhy_bufferNext[7:0]; + end + 3'b010 : begin + inputPhy_bufferNext = _zz_inputPhy_bufferNext_1[7:0]; + end + default : begin + end + endcase + end + + always @(*) begin + inputPhy_widthSel = 3'bxxx; + case(inputPhy_mod) + 2'b00 : begin + inputPhy_widthSel = 3'b000; + end + 2'b01 : begin + inputPhy_widthSel = 3'b001; + end + 2'b10 : begin + inputPhy_widthSel = 3'b010; + end + default : begin + end + endcase + end + + assign when_SpiXdrMasterCtrl_l861 = (! fsm_state_delay_2); + always @(*) begin + inputPhy_dataRead = 4'bxxxx; + case(inputPhy_mod) + 2'b00 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead[1]; + end + 2'b01 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead_1[0]; + inputPhy_dataRead[1] = _zz_inputPhy_dataRead_2[1]; + end + 2'b10 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead_3[0]; + inputPhy_dataRead[1] = _zz_inputPhy_dataRead_4[1]; + inputPhy_dataRead[2] = _zz_inputPhy_dataRead_5[2]; + inputPhy_dataRead[3] = _zz_inputPhy_dataRead_6[3]; + end + default : begin + end + endcase + end + + assign io_rsp_valid = inputPhy_readDone; + assign io_rsp_payload_data = inputPhy_bufferNext; + always @(posedge io_systemClk) begin + timer_counter <= (timer_counter + 12'h001); + if(timer_reset) begin + timer_counter <= 12'h0; + end + io_config_mod_delay_1 <= io_config_mod; + inputPhy_mod <= io_config_mod_delay_1; + fsm_state_delay_1 <= fsm_state; + fsm_state_delay_2 <= fsm_state_delay_1; + if(when_SpiXdrMasterCtrl_l861) begin + inputPhy_dataReadBuffer <= {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + end + case(inputPhy_widthSel) + 3'b000 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + 3'b001 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + 3'b010 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + default : begin + end + endcase + end + + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + fsm_state <= 1'b0; + fsm_counter <= 3'b000; + fsm_ss <= 1'b0; + fsm_readFill_delay_1 <= 1'b0; + inputPhy_readFill <= 1'b0; + fsm_readDone_delay_1 <= 1'b0; + inputPhy_readDone <= 1'b0; + end else begin + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l739) begin + if(timer_sclkToogleHit) begin + fsm_state <= (! fsm_state); + end + if(when_SpiXdrMasterCtrl_l749) begin + fsm_counter <= fsm_counterPlus; + if(when_SpiXdrMasterCtrl_l751) begin + fsm_state <= 1'b0; + end + end + end else begin + if(when_SpiXdrMasterCtrl_l758) begin + fsm_ss[0] <= 1'b1; + end else begin + if(when_SpiXdrMasterCtrl_l764) begin + if(timer_ss_holdHit) begin + fsm_state <= 1'b1; + end + end else begin + fsm_ss[0] <= 1'b0; + end + end + end + end + if(when_SpiXdrMasterCtrl_l781) begin + fsm_state <= 1'b0; + fsm_counter <= 3'b000; + end + fsm_readFill_delay_1 <= fsm_readFill; + inputPhy_readFill <= fsm_readFill_delay_1; + fsm_readDone_delay_1 <= fsm_readDone; + inputPhy_readDone <= fsm_readDone_delay_1; + end + end + + +endmodule + +//StreamFifo_b62b14ffe6bb44e5a817b8d08e286c6b replaced by StreamFifo_b62b14ffe6bb44e5a817b8d08e286c6b + +module StreamFifo_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_push_valid, + output io_push_ready, + input [7:0] io_push_payload, + output io_pop_valid, + input io_pop_ready, + output [7:0] io_pop_payload, + input io_flush, + output [7:0] io_occupancy, + output [7:0] io_availability, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [7:0] _zz_logic_ram_port0; + wire [6:0] _zz_logic_pushPtr_valueNext; + wire [0:0] _zz_logic_pushPtr_valueNext_1; + wire [6:0] _zz_logic_popPtr_valueNext; + wire [0:0] _zz_logic_popPtr_valueNext_1; + wire _zz_logic_ram_port; + wire _zz_io_pop_payload; + wire [6:0] _zz_io_availability; + reg _zz_1; + reg logic_pushPtr_willIncrement; + reg logic_pushPtr_willClear; + reg [6:0] logic_pushPtr_valueNext; + reg [6:0] logic_pushPtr_value; + wire logic_pushPtr_willOverflowIfInc; + wire logic_pushPtr_willOverflow; + reg logic_popPtr_willIncrement; + reg logic_popPtr_willClear; + reg [6:0] logic_popPtr_valueNext; + reg [6:0] logic_popPtr_value; + wire logic_popPtr_willOverflowIfInc; + wire logic_popPtr_willOverflow; + wire logic_ptrMatch; + reg logic_risingOccupancy; + wire logic_pushing; + wire logic_popping; + wire logic_empty; + wire logic_full; + reg _zz_io_pop_valid; + wire when_Stream_l1037; + wire [6:0] logic_ptrDif; + reg [7:0] logic_ram [0:127]; + + assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; + assign _zz_logic_pushPtr_valueNext = {6'd0, _zz_logic_pushPtr_valueNext_1}; + assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; + assign _zz_logic_popPtr_valueNext = {6'd0, _zz_logic_popPtr_valueNext_1}; + assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); + assign _zz_io_pop_payload = 1'b1; + always @(posedge io_systemClk) begin + if(_zz_io_pop_payload) begin + _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_1) begin + logic_ram[logic_pushPtr_value] <= io_push_payload; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_pushing) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willIncrement = 1'b0; + if(logic_pushing) begin + logic_pushPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willClear = 1'b0; + if(io_flush) begin + logic_pushPtr_willClear = 1'b1; + end + end + + assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 7'h7f); + assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); + always @(*) begin + logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); + if(logic_pushPtr_willClear) begin + logic_pushPtr_valueNext = 7'h0; + end + end + + always @(*) begin + logic_popPtr_willIncrement = 1'b0; + if(logic_popping) begin + logic_popPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_popPtr_willClear = 1'b0; + if(io_flush) begin + logic_popPtr_willClear = 1'b1; + end + end + + assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 7'h7f); + assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); + always @(*) begin + logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); + if(logic_popPtr_willClear) begin + logic_popPtr_valueNext = 7'h0; + end + end + + assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); + assign logic_pushing = (io_push_valid && io_push_ready); + assign logic_popping = (io_pop_valid && io_pop_ready); + assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); + assign logic_full = (logic_ptrMatch && logic_risingOccupancy); + assign io_push_ready = (! logic_full); + assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); + assign io_pop_payload = _zz_logic_ram_port0; + assign when_Stream_l1037 = (logic_pushing != logic_popping); + assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); + assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; + assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + logic_pushPtr_value <= 7'h0; + logic_popPtr_value <= 7'h0; + logic_risingOccupancy <= 1'b0; + _zz_io_pop_valid <= 1'b0; + end else begin + logic_pushPtr_value <= logic_pushPtr_valueNext; + logic_popPtr_value <= logic_popPtr_valueNext; + _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); + if(when_Stream_l1037) begin + logic_risingOccupancy <= logic_pushing; + end + if(io_flush) begin + logic_risingOccupancy <= 1'b0; + end + end + end + + +endmodule + +module UartCtrl_b62b14ffe6bb44e5a817b8d08e286c6b ( + input [2:0] io_config_frame_dataLength, + input [0:0] io_config_frame_stop, + input [1:0] io_config_frame_parity, + input [19:0] io_config_clockDivider, + input io_write_valid, + output reg io_write_ready, + input [7:0] io_write_payload, + output io_read_valid, + input io_read_ready, + output [7:0] io_read_payload, + output io_uart_txd, + input io_uart_rxd, + output io_readError, + input io_writeBreak, + output io_readBreak, + input io_systemClk, + input systemCd_logic_outputReset +); + localparam UartStopType_ONE = 1'd0; + localparam UartStopType_TWO = 1'd1; + localparam UartParityType_NONE = 2'd0; + localparam UartParityType_EVEN = 2'd1; + localparam UartParityType_ODD = 2'd2; + + wire tx_io_write_ready; + wire tx_io_txd; + wire rx_io_read_valid; + wire [7:0] rx_io_read_payload; + wire rx_io_rts; + wire rx_io_error; + wire rx_io_break; + reg [19:0] clockDivider_counter; + wire clockDivider_tick; + reg clockDivider_tickReg; + reg io_write_thrown_valid; + wire io_write_thrown_ready; + wire [7:0] io_write_thrown_payload; + `ifndef SYNTHESIS + reg [23:0] io_config_frame_stop_string; + reg [31:0] io_config_frame_parity_string; + `endif + + + UartCtrlTx_b62b14ffe6bb44e5a817b8d08e286c6b tx ( + .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i + .io_configFrame_stop (io_config_frame_stop ), //i + .io_configFrame_parity (io_config_frame_parity[1:0] ), //i + .io_samplingTick (clockDivider_tickReg ), //i + .io_write_valid (io_write_thrown_valid ), //i + .io_write_ready (tx_io_write_ready ), //o + .io_write_payload (io_write_thrown_payload[7:0] ), //i + .io_cts (1'b0 ), //i + .io_txd (tx_io_txd ), //o + .io_break (io_writeBreak ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + UartCtrlRx_b62b14ffe6bb44e5a817b8d08e286c6b rx ( + .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i + .io_configFrame_stop (io_config_frame_stop ), //i + .io_configFrame_parity (io_config_frame_parity[1:0] ), //i + .io_samplingTick (clockDivider_tickReg ), //i + .io_read_valid (rx_io_read_valid ), //o + .io_read_ready (io_read_ready ), //i + .io_read_payload (rx_io_read_payload[7:0] ), //o + .io_rxd (io_uart_rxd ), //i + .io_rts (rx_io_rts ), //o + .io_error (rx_io_error ), //o + .io_break (rx_io_break ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_config_frame_stop) + UartStopType_ONE : io_config_frame_stop_string = "ONE"; + UartStopType_TWO : io_config_frame_stop_string = "TWO"; + default : io_config_frame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_config_frame_parity) + UartParityType_NONE : io_config_frame_parity_string = "NONE"; + UartParityType_EVEN : io_config_frame_parity_string = "EVEN"; + UartParityType_ODD : io_config_frame_parity_string = "ODD "; + default : io_config_frame_parity_string = "????"; + endcase + end + `endif + + assign clockDivider_tick = (clockDivider_counter == 20'h0); + always @(*) begin + io_write_thrown_valid = io_write_valid; + if(rx_io_break) begin + io_write_thrown_valid = 1'b0; + end + end + + always @(*) begin + io_write_ready = io_write_thrown_ready; + if(rx_io_break) begin + io_write_ready = 1'b1; + end + end + + assign io_write_thrown_payload = io_write_payload; + assign io_write_thrown_ready = tx_io_write_ready; + assign io_read_valid = rx_io_read_valid; + assign io_read_payload = rx_io_read_payload; + assign io_uart_txd = tx_io_txd; + assign io_readError = rx_io_error; + assign io_readBreak = rx_io_break; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + clockDivider_counter <= 20'h0; + clockDivider_tickReg <= 1'b0; + end else begin + clockDivider_tickReg <= clockDivider_tick; + clockDivider_counter <= (clockDivider_counter - 20'h00001); + if(clockDivider_tick) begin + clockDivider_counter <= io_config_clockDivider; + end + end + end + + +endmodule + +module StreamArbiter_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_inputs_0_valid, + output io_inputs_0_ready, + input io_inputs_0_payload_last, + input [0:0] io_inputs_0_payload_fragment_source, + input [0:0] io_inputs_0_payload_fragment_opcode, + input [31:0] io_inputs_0_payload_fragment_address, + input [5:0] io_inputs_0_payload_fragment_length, + input [31:0] io_inputs_0_payload_fragment_data, + input [3:0] io_inputs_0_payload_fragment_mask, + input [0:0] io_inputs_0_payload_fragment_context, + input io_inputs_1_valid, + output io_inputs_1_ready, + input io_inputs_1_payload_last, + input [0:0] io_inputs_1_payload_fragment_source, + input [0:0] io_inputs_1_payload_fragment_opcode, + input [31:0] io_inputs_1_payload_fragment_address, + input [5:0] io_inputs_1_payload_fragment_length, + input [31:0] io_inputs_1_payload_fragment_data, + input [3:0] io_inputs_1_payload_fragment_mask, + input [0:0] io_inputs_1_payload_fragment_context, + output io_output_valid, + input io_output_ready, + output io_output_payload_last, + output [0:0] io_output_payload_fragment_source, + output [0:0] io_output_payload_fragment_opcode, + output [31:0] io_output_payload_fragment_address, + output [5:0] io_output_payload_fragment_length, + output [31:0] io_output_payload_fragment_data, + output [3:0] io_output_payload_fragment_mask, + output [0:0] io_output_payload_fragment_context, + output [0:0] io_chosen, + output [1:0] io_chosenOH, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire [3:0] _zz__zz_maskProposal_0_2; + wire [3:0] _zz__zz_maskProposal_0_2_1; + wire [1:0] _zz__zz_maskProposal_0_2_2; + reg locked; + wire maskProposal_0; + wire maskProposal_1; + reg maskLocked_0; + reg maskLocked_1; + wire maskRouted_0; + wire maskRouted_1; + wire [1:0] _zz_maskProposal_0; + wire [3:0] _zz_maskProposal_0_1; + wire [3:0] _zz_maskProposal_0_2; + wire [1:0] _zz_maskProposal_0_3; + wire io_output_fire; + wire when_Stream_l621; + wire _zz_io_chosen; + + assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); + assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; + assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; + assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); + assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); + assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; + assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; + assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); + assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); + assign maskProposal_0 = _zz_maskProposal_0_3[0]; + assign maskProposal_1 = _zz_maskProposal_0_3[1]; + assign io_output_fire = (io_output_valid && io_output_ready); + assign when_Stream_l621 = (io_output_fire && io_output_payload_last); + assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); + assign io_output_payload_last = (maskRouted_0 ? io_inputs_0_payload_last : io_inputs_1_payload_last); + assign io_output_payload_fragment_source = (maskRouted_0 ? io_inputs_0_payload_fragment_source : io_inputs_1_payload_fragment_source); + assign io_output_payload_fragment_opcode = (maskRouted_0 ? io_inputs_0_payload_fragment_opcode : io_inputs_1_payload_fragment_opcode); + assign io_output_payload_fragment_address = (maskRouted_0 ? io_inputs_0_payload_fragment_address : io_inputs_1_payload_fragment_address); + assign io_output_payload_fragment_length = (maskRouted_0 ? io_inputs_0_payload_fragment_length : io_inputs_1_payload_fragment_length); + assign io_output_payload_fragment_data = (maskRouted_0 ? io_inputs_0_payload_fragment_data : io_inputs_1_payload_fragment_data); + assign io_output_payload_fragment_mask = (maskRouted_0 ? io_inputs_0_payload_fragment_mask : io_inputs_1_payload_fragment_mask); + assign io_output_payload_fragment_context = (maskRouted_0 ? io_inputs_0_payload_fragment_context : io_inputs_1_payload_fragment_context); + assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); + assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); + assign io_chosenOH = {maskRouted_1,maskRouted_0}; + assign _zz_io_chosen = io_chosenOH[1]; + assign io_chosen = _zz_io_chosen; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + locked <= 1'b0; + maskLocked_0 <= 1'b0; + maskLocked_1 <= 1'b1; + end else begin + if(io_output_valid) begin + maskLocked_0 <= maskRouted_0; + maskLocked_1 <= maskRouted_1; + end + if(io_output_valid) begin + locked <= 1'b1; + end + if(when_Stream_l621) begin + locked <= 1'b0; + end + end + end + + +endmodule + +module FlowCCByToggle_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_input_valid, + input io_input_payload_last, + input [0:0] io_input_payload_fragment, + output io_output_valid, + output io_output_payload_last, + output [0:0] io_output_payload_fragment, + input jtagCtrl_tck, + input io_systemClk, + input debugCd_logic_outputReset +); + + wire inputArea_target_buffercc_io_dataOut; + reg inputArea_target; + reg inputArea_data_last; + reg [0:0] inputArea_data_fragment; + wire outputArea_target; + reg outputArea_hit; + wire outputArea_flow_valid; + wire outputArea_flow_payload_last; + wire [0:0] outputArea_flow_payload_fragment; + reg outputArea_flow_m2sPipe_valid; + reg outputArea_flow_m2sPipe_payload_last; + reg [0:0] outputArea_flow_m2sPipe_payload_fragment; + + BufferCC_1_b62b14ffe6bb44e5a817b8d08e286c6b inputArea_target_buffercc ( + .io_dataIn (inputArea_target ), //i + .io_dataOut (inputArea_target_buffercc_io_dataOut), //o + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i + ); + initial begin + `ifndef SYNTHESIS + inputArea_target = $urandom; + outputArea_hit = $urandom; + `endif + end + + assign outputArea_target = inputArea_target_buffercc_io_dataOut; + assign outputArea_flow_valid = (outputArea_target != outputArea_hit); + assign outputArea_flow_payload_last = inputArea_data_last; + assign outputArea_flow_payload_fragment = inputArea_data_fragment; + assign io_output_valid = outputArea_flow_m2sPipe_valid; + assign io_output_payload_last = outputArea_flow_m2sPipe_payload_last; + assign io_output_payload_fragment = outputArea_flow_m2sPipe_payload_fragment; + always @(posedge jtagCtrl_tck) begin + if(io_input_valid) begin + inputArea_target <= (! inputArea_target); + inputArea_data_last <= io_input_payload_last; + inputArea_data_fragment <= io_input_payload_fragment; + end + end + + always @(posedge io_systemClk) begin + outputArea_hit <= outputArea_target; + if(outputArea_flow_valid) begin + outputArea_flow_m2sPipe_payload_last <= outputArea_flow_payload_last; + outputArea_flow_m2sPipe_payload_fragment <= outputArea_flow_payload_fragment; + end + end + + always @(posedge io_systemClk) begin + if(debugCd_logic_outputReset) begin + outputArea_flow_m2sPipe_valid <= 1'b0; + end else begin + outputArea_flow_m2sPipe_valid <= outputArea_flow_valid; + end + end + + +endmodule + +module DataCache_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output reg io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isFiring, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + input [31:0] io_cpu_writeBack_storeData, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output io_cpu_writeBack_exclusiveOk, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output io_cpu_flush_ready, + input io_cpu_flush_payload_singleLine, + input [5:0] io_cpu_flush_payload_lineId, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_size, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [21:0] _zz_ways_0_tags_port0; + reg [31:0] _zz_ways_0_data_port0; + wire [21:0] _zz_ways_0_tags_port; + wire [9:0] _zz_stage0_dataColisions; + wire [9:0] _zz__zz_stageA_dataColisions; + wire [0:0] _zz_when; + wire [3:0] _zz_loader_counter_valueNext; + wire [0:0] _zz_loader_counter_valueNext_1; + wire [1:0] _zz_loader_waysAllocator; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [5:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [5:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [5:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_ways_0_tagsReadRsp_valid_1; + wire _zz_ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire when_DataCache_l642; + wire when_DataCache_l645; + wire when_DataCache_l664; + wire rspSync; + wire rspLast; + reg memCmdSent; + wire io_mem_cmd_fire; + wire when_DataCache_l686; + reg [3:0] _zz_stage0_mask; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + wire stage0_isAmo; + wire when_DataCache_l771; + reg stageA_request_wr; + reg [1:0] stageA_request_size; + reg stageA_request_totalyConsistent; + wire when_DataCache_l771_1; + reg [3:0] stageA_mask; + wire stageA_isAmo; + wire stageA_isLrsc; + wire [0:0] stageA_wayHits; + wire when_DataCache_l771_2; + reg [0:0] stageA_wayInvalidate; + wire when_DataCache_l771_3; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_stageA_dataColisions; + wire [0:0] stageA_dataColisions; + wire when_DataCache_l822; + reg stageB_request_wr; + reg [1:0] stageB_request_size; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + wire when_DataCache_l824; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + wire when_DataCache_l821; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + wire when_DataCache_l821_1; + reg [31:0] stageB_dataReadRsp_0; + wire when_DataCache_l820; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + wire when_DataCache_l820_1; + reg [0:0] stageB_dataColisions; + wire when_DataCache_l820_2; + reg stageB_unaligned; + wire when_DataCache_l820_3; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + wire when_DataCache_l820_4; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_waitDone; + wire stageB_flusher_hold; + reg [6:0] stageB_flusher_counter; + wire when_DataCache_l850; + wire when_DataCache_l856; + reg stageB_flusher_start; + wire stageB_isAmo; + wire stageB_isAmoCached; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + wire [31:0] stageB_requestDataBypass; + reg stageB_cpuWriteToCache; + wire when_DataCache_l926; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + wire when_DataCache_l995; + wire when_DataCache_l1004; + wire when_DataCache_l1009; + wire when_DataCache_l1020; + wire when_DataCache_l1032; + wire when_DataCache_l991; + wire when_DataCache_l1066; + wire when_DataCache_l1075; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [3:0] loader_counter_valueNext; + reg [3:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire when_DataCache_l1090; + wire loader_done; + wire when_DataCache_l1118; + reg loader_valid_regNext; + wire when_DataCache_l1122; + wire when_DataCache_l1125; + reg [21:0] ways_0_tags [0:63]; + reg [7:0] ways_0_data_symbol0 [0:1023]; + reg [7:0] ways_0_data_symbol1 [0:1023]; + reg [7:0] ways_0_data_symbol2 [0:1023]; + reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_ways_0_datasymbol_read; + reg [7:0] _zz_ways_0_datasymbol_read_1; + reg [7:0] _zz_ways_0_datasymbol_read_2; + reg [7:0] _zz_ways_0_datasymbol_read_3; + + assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_when = 1'b1; + assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; + assign _zz_loader_counter_valueNext = {3'd0, _zz_loader_counter_valueNext_1}; + assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @(posedge io_systemClk) begin + if(_zz_ways_0_tagsReadRsp_valid) begin + _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; + end + end + + always @(*) begin + _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; + end + always @(posedge io_systemClk) begin + if(_zz_ways_0_dataReadRspMem) begin + _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @(posedge io_systemClk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(when_DataCache_l645) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + _zz_2 = 1'b0; + if(when_DataCache_l642) begin + _zz_2 = 1'b1; + end + end + + assign haltCpu = 1'b0; + assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; + assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; + assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; + assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2]; + assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + assign when_DataCache_l642 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); + assign when_DataCache_l645 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); + always @(*) begin + tagsReadCmd_valid = 1'b0; + if(when_DataCache_l664) begin + tagsReadCmd_valid = 1'b1; + end + end + + always @(*) begin + tagsReadCmd_payload = 6'bxxxxxx; + if(when_DataCache_l664) begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 6]; + end + end + + always @(*) begin + dataReadCmd_valid = 1'b0; + if(when_DataCache_l664) begin + dataReadCmd_valid = 1'b1; + end + end + + always @(*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(when_DataCache_l664) begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + end + end + + always @(*) begin + tagsWriteCmd_valid = 1'b0; + if(when_DataCache_l850) begin + tagsWriteCmd_valid = 1'b1; + end + if(when_DataCache_l1066) begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_done) begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @(*) begin + tagsWriteCmd_payload_way = 1'bx; + if(when_DataCache_l850) begin + tagsWriteCmd_payload_way = 1'b1; + end + if(loader_done) begin + tagsWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @(*) begin + tagsWriteCmd_payload_address = 6'bxxxxxx; + if(when_DataCache_l850) begin + tagsWriteCmd_payload_address = stageB_flusher_counter[5:0]; + end + if(loader_done) begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 6]; + end + end + + always @(*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(when_DataCache_l850) begin + tagsWriteCmd_payload_data_valid = 1'b0; + end + if(loader_done) begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); + end + end + + always @(*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done) begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); + end + end + + always @(*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done) begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + end + end + + always @(*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache) begin + if(when_DataCache_l926) begin + dataWriteCmd_valid = 1'b1; + end + end + if(when_DataCache_l1066) begin + dataWriteCmd_valid = 1'b0; + end + if(when_DataCache_l1090) begin + dataWriteCmd_valid = 1'b1; + end + end + + always @(*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_way = stageB_waysHits; + end + if(when_DataCache_l1090) begin + dataWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @(*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + end + if(when_DataCache_l1090) begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 6],loader_counter_value}; + end + end + + always @(*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; + end + if(when_DataCache_l1090) begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; + end + end + + always @(*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_when[0]) begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end + end + if(when_DataCache_l1090) begin + dataWriteCmd_payload_mask = 4'b1111; + end + end + + assign when_DataCache_l664 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + always @(*) begin + io_cpu_execute_haltIt = 1'b0; + if(when_DataCache_l850) begin + io_cpu_execute_haltIt = 1'b1; + end + end + + assign rspSync = 1'b1; + assign rspLast = 1'b1; + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign when_DataCache_l686 = (! io_cpu_writeBack_isStuck); + always @(*) begin + _zz_stage0_mask = 4'bxxxx; + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_stage0_mask = 4'b0001; + end + 2'b01 : begin + _zz_stage0_mask = 4'b0011; + end + 2'b10 : begin + _zz_stage0_mask = 4'b1111; + end + default : begin + end + endcase + end + + assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign stage0_isAmo = 1'b0; + assign when_DataCache_l771 = (! io_cpu_memory_isStuck); + assign when_DataCache_l771_1 = (! io_cpu_memory_isStuck); + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_isAmo = 1'b0; + assign stageA_isLrsc = 1'b0; + assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign when_DataCache_l771_2 = (! io_cpu_memory_isStuck); + assign when_DataCache_l771_3 = (! io_cpu_memory_isStuck); + assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); + assign when_DataCache_l822 = (! io_cpu_writeBack_isStuck); + always @(*) begin + stageB_mmuRspFreeze = 1'b0; + if(when_DataCache_l1125) begin + stageB_mmuRspFreeze = 1'b1; + end + end + + assign when_DataCache_l824 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign when_DataCache_l821 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l821_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l820 = (! io_cpu_writeBack_isStuck); + assign stageB_consistancyHazard = 1'b0; + assign when_DataCache_l820_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l820_2 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l820_3 = (! io_cpu_writeBack_isStuck); + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (|stageB_waysHits); + assign stageB_dataMux = stageB_dataReadRsp_0; + assign when_DataCache_l820_4 = (! io_cpu_writeBack_isStuck); + always @(*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(!when_DataCache_l1004) begin + if(io_mem_cmd_ready) begin + stageB_loaderValid = 1'b1; + end + end + end + end + end + if(when_DataCache_l1066) begin + stageB_loaderValid = 1'b0; + end + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @(*) begin + io_cpu_writeBack_haltIt = 1'b1; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l991) begin + if(when_DataCache_l995) begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(when_DataCache_l1004) begin + if(when_DataCache_l1009) begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end + end + if(when_DataCache_l1066) begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + + assign stageB_flusher_hold = 1'b0; + assign when_DataCache_l850 = (! stageB_flusher_counter[6]); + assign when_DataCache_l856 = (! stageB_flusher_hold); + assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[6]); + assign stageB_isAmo = 1'b0; + assign stageB_isAmoCached = 1'b0; + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + assign stageB_requestDataBypass = io_cpu_writeBack_storeData; + always @(*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(when_DataCache_l1004) begin + stageB_cpuWriteToCache = 1'b1; + end + end + end + end + end + + assign when_DataCache_l926 = (stageB_request_wr && stageB_waysHit); + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @(*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(when_DataCache_l1004) begin + if(when_DataCache_l1020) begin + io_cpu_redo = 1'b1; + end + end + end + end + end + if(when_DataCache_l1075) begin + io_cpu_redo = 1'b1; + end + if(when_DataCache_l1122) begin + io_cpu_redo = 1'b1; + end + end + + always @(*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache) begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + end + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @(*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l991) begin + io_mem_cmd_valid = (! memCmdSent); + end else begin + if(when_DataCache_l1004) begin + if(stageB_request_wr) begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if(when_DataCache_l1032) begin + io_mem_cmd_valid = 1'b1; + end + end + end + end + end + if(when_DataCache_l1066) begin + io_mem_cmd_valid = 1'b0; + end + end + + always @(*) begin + io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(!when_DataCache_l1004) begin + io_mem_cmd_payload_address[5 : 0] = 6'h0; + end + end + end + end + end + + assign io_mem_cmd_payload_last = 1'b1; + always @(*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(!when_DataCache_l1004) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end + end + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + always @(*) begin + io_mem_cmd_payload_size = {1'd0, stageB_request_size}; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(!when_DataCache_l1004) begin + io_mem_cmd_payload_size = 3'b110; + end + end + end + end + end + + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + assign when_DataCache_l995 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); + assign when_DataCache_l1004 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign when_DataCache_l1009 = ((! stageB_request_wr) || io_mem_cmd_ready); + assign when_DataCache_l1020 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign when_DataCache_l1032 = (! memCmdSent); + assign when_DataCache_l991 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + always @(*) begin + if(stageB_bypassCache) begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; + end + end + + assign when_DataCache_l1066 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign when_DataCache_l1075 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); + always @(*) begin + loader_counter_willIncrement = 1'b0; + if(when_DataCache_l1090) begin + loader_counter_willIncrement = 1'b1; + end + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 4'b1111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @(*) begin + loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); + if(loader_counter_willClear) begin + loader_counter_valueNext = 4'b0000; + end + end + + assign loader_kill = 1'b0; + assign when_DataCache_l1090 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign loader_done = loader_counter_willOverflow; + assign when_DataCache_l1118 = (! loader_valid); + assign when_DataCache_l1122 = (loader_valid && (! loader_valid_regNext)); + assign io_cpu_execute_refilling = loader_valid; + assign when_DataCache_l1125 = (stageB_loaderValid || loader_valid); + always @(posedge io_systemClk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if(when_DataCache_l771) begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; + end + if(when_DataCache_l771_1) begin + stageA_mask <= stage0_mask; + end + if(when_DataCache_l771_2) begin + stageA_wayInvalidate <= stage0_wayInvalidate; + end + if(when_DataCache_l771_3) begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; + end + if(when_DataCache_l822) begin + stageB_request_wr <= stageA_request_wr; + stageB_request_size <= stageA_request_size; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(when_DataCache_l824) begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; + end + if(when_DataCache_l821) begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; + end + if(when_DataCache_l821_1) begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; + end + if(when_DataCache_l820) begin + stageB_wayInvalidate <= stageA_wayInvalidate; + end + if(when_DataCache_l820_1) begin + stageB_dataColisions <= stageA_dataColisions; + end + if(when_DataCache_l820_2) begin + stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); + end + if(when_DataCache_l820_3) begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; + end + if(when_DataCache_l820_4) begin + stageB_mask <= stageA_mask; + end + loader_valid_regNext <= loader_valid; + end + + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + memCmdSent <= 1'b0; + stageB_flusher_waitDone <= 1'b0; + stageB_flusher_counter <= 7'h0; + stageB_flusher_start <= 1'b1; + loader_valid <= 1'b0; + loader_counter_value <= 4'b0000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_fire) begin + memCmdSent <= 1'b1; + end + if(when_DataCache_l686) begin + memCmdSent <= 1'b0; + end + if(io_cpu_flush_ready) begin + stageB_flusher_waitDone <= 1'b0; + end + if(when_DataCache_l850) begin + if(when_DataCache_l856) begin + stageB_flusher_counter <= (stageB_flusher_counter + 7'h01); + if(io_cpu_flush_payload_singleLine) begin + stageB_flusher_counter[6] <= 1'b1; + end + end + end + stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start) begin + stageB_flusher_waitDone <= 1'b1; + stageB_flusher_counter <= 7'h0; + if(io_cpu_flush_payload_singleLine) begin + stageB_flusher_counter <= {1'b0,io_cpu_flush_payload_lineId}; + end + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); // DataCache_b62b14ffe6bb44e5a817b8d08e286c6b.scala:L1077 + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("ERROR writeBack stuck by another plugin is not allowed"); // DataCache_b62b14ffe6bb44e5a817b8d08e286c6b.scala:L1077 + end + `endif + `endif + if(stageB_loaderValid) begin + loader_valid <= 1'b1; + end + loader_counter_value <= loader_counter_valueNext; + if(loader_kill) begin + loader_killReg <= 1'b1; + end + if(when_DataCache_l1090) begin + loader_error <= (loader_error || io_mem_rsp_payload_error); + end + if(loader_done) begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end + if(when_DataCache_l1118) begin + loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; + end + end + end + + +endmodule + +module InstructionCache_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [31:0] _zz_banks_0_port1; + reg [21:0] _zz_ways_0_tags_port1; + wire [21:0] _zz_ways_0_tags_port; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [6:0] lineLoader_flushCounter; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; + reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l513; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [3:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [5:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire when_InstructionCache_l401; + wire [9:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [5:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; + reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + wire when_InstructionCache_l459_1; + reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; + reg decodeStage_hit_error; + reg [31:0] banks_0 [0:1023]; + reg [21:0] ways_0_tags [0:63]; + + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge io_systemClk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @(posedge io_systemClk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; + end + end + + always @(posedge io_systemClk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid) begin + _zz_2 = 1'b1; + end + end + + always @(*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin + lineLoader_fire = 1'b1; + end + end + end + + always @(*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(when_InstructionCache_l338) begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(when_InstructionCache_l342) begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush) begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[6]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 6],6'h0}; + assign io_mem_cmd_payload_size = 3'b110; + assign when_Utils_l513 = (! lineLoader_valid); + always @(*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if(when_Utils_l513) begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[11 : 6] : lineLoader_flushCounter[5 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 6],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data[31 : 0]; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 4'b1111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[11 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[11 : 6]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[21 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = (|fetchStage_hit_hits_0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 4'b0000; + end else begin + if(lineLoader_fire) begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire) begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid) begin + lineLoader_valid <= 1'b1; + end + if(io_flush) begin + lineLoader_flushPending <= 1'b1; + end + if(when_InstructionCache_l351) begin + lineLoader_flushPending <= 1'b0; + end + if(io_mem_cmd_fire) begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire) begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid) begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 4'b0001); + if(io_mem_rsp_payload_error) begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @(posedge io_systemClk) begin + if(io_cpu_fill_valid) begin + lineLoader_address <= io_cpu_fill_payload; + end + if(when_InstructionCache_l338) begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); + end + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[6]; + if(when_InstructionCache_l351) begin + lineLoader_flushCounter <= 7'h0; + end + if(when_InstructionCache_l435) begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if(when_InstructionCache_l459) begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + end + if(when_InstructionCache_l459_1) begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if(when_InstructionCache_l459_2) begin + decodeStage_hit_error <= fetchStage_hit_error; + end + end + + +endmodule + +module UartCtrlRx_b62b14ffe6bb44e5a817b8d08e286c6b ( + input [2:0] io_configFrame_dataLength, + input [0:0] io_configFrame_stop, + input [1:0] io_configFrame_parity, + input io_samplingTick, + output io_read_valid, + input io_read_ready, + output [7:0] io_read_payload, + input io_rxd, + output io_rts, + output reg io_error, + output io_break, + input io_systemClk, + input systemCd_logic_outputReset +); + localparam UartStopType_ONE = 1'd0; + localparam UartStopType_TWO = 1'd1; + localparam UartParityType_NONE = 2'd0; + localparam UartParityType_EVEN = 2'd1; + localparam UartParityType_ODD = 2'd2; + localparam UartCtrlRxState_IDLE = 3'd0; + localparam UartCtrlRxState_START = 3'd1; + localparam UartCtrlRxState_DATA = 3'd2; + localparam UartCtrlRxState_PARITY = 3'd3; + localparam UartCtrlRxState_STOP = 3'd4; + + wire io_rxd_buffercc_io_dataOut; + wire _zz_sampler_value; + wire _zz_sampler_value_1; + wire _zz_sampler_value_2; + wire _zz_sampler_value_3; + wire _zz_sampler_value_4; + wire _zz_sampler_value_5; + wire _zz_sampler_value_6; + wire [2:0] _zz_when_UartCtrlRx_l139; + wire [0:0] _zz_when_UartCtrlRx_l139_1; + reg _zz_io_rts; + wire sampler_synchroniser; + wire sampler_samples_0; + reg sampler_samples_1; + reg sampler_samples_2; + reg sampler_samples_3; + reg sampler_samples_4; + reg sampler_value; + reg sampler_tick; + reg [2:0] bitTimer_counter; + reg bitTimer_tick; + wire when_UartCtrlRx_l43; + reg [2:0] bitCounter_value; + reg [6:0] break_counter; + wire break_valid; + wire when_UartCtrlRx_l69; + reg [2:0] stateMachine_state; + reg stateMachine_parity; + reg [7:0] stateMachine_shifter; + reg stateMachine_validReg; + wire when_UartCtrlRx_l93; + wire when_UartCtrlRx_l103; + wire when_UartCtrlRx_l111; + wire when_UartCtrlRx_l113; + wire when_UartCtrlRx_l125; + wire when_UartCtrlRx_l136; + wire when_UartCtrlRx_l139; + `ifndef SYNTHESIS + reg [23:0] io_configFrame_stop_string; + reg [31:0] io_configFrame_parity_string; + reg [47:0] stateMachine_state_string; + `endif + + + assign _zz_when_UartCtrlRx_l139_1 = ((io_configFrame_stop == UartStopType_ONE) ? 1'b0 : 1'b1); + assign _zz_when_UartCtrlRx_l139 = {2'd0, _zz_when_UartCtrlRx_l139_1}; + assign _zz_sampler_value = ((((1'b0 || ((_zz_sampler_value_1 && sampler_samples_1) && sampler_samples_2)) || (((_zz_sampler_value_2 && sampler_samples_0) && sampler_samples_1) && sampler_samples_3)) || (((1'b1 && sampler_samples_0) && sampler_samples_2) && sampler_samples_3)) || (((1'b1 && sampler_samples_1) && sampler_samples_2) && sampler_samples_3)); + assign _zz_sampler_value_3 = (((1'b1 && sampler_samples_0) && sampler_samples_1) && sampler_samples_4); + assign _zz_sampler_value_4 = ((1'b1 && sampler_samples_0) && sampler_samples_2); + assign _zz_sampler_value_5 = (1'b1 && sampler_samples_1); + assign _zz_sampler_value_6 = 1'b1; + assign _zz_sampler_value_1 = (1'b1 && sampler_samples_0); + assign _zz_sampler_value_2 = 1'b1; + BufferCC_b62b14ffe6bb44e5a817b8d08e286c6b io_rxd_buffercc ( + .io_dataIn (io_rxd ), //i + .io_dataOut (io_rxd_buffercc_io_dataOut), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_configFrame_stop) + UartStopType_ONE : io_configFrame_stop_string = "ONE"; + UartStopType_TWO : io_configFrame_stop_string = "TWO"; + default : io_configFrame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_configFrame_parity) + UartParityType_NONE : io_configFrame_parity_string = "NONE"; + UartParityType_EVEN : io_configFrame_parity_string = "EVEN"; + UartParityType_ODD : io_configFrame_parity_string = "ODD "; + default : io_configFrame_parity_string = "????"; + endcase + end + always @(*) begin + case(stateMachine_state) + UartCtrlRxState_IDLE : stateMachine_state_string = "IDLE "; + UartCtrlRxState_START : stateMachine_state_string = "START "; + UartCtrlRxState_DATA : stateMachine_state_string = "DATA "; + UartCtrlRxState_PARITY : stateMachine_state_string = "PARITY"; + UartCtrlRxState_STOP : stateMachine_state_string = "STOP "; + default : stateMachine_state_string = "??????"; + endcase + end + `endif + + always @(*) begin + io_error = 1'b0; + case(stateMachine_state) + UartCtrlRxState_IDLE : begin + end + UartCtrlRxState_START : begin + end + UartCtrlRxState_DATA : begin + end + UartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + if(!when_UartCtrlRx_l125) begin + io_error = 1'b1; + end + end + end + default : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l136) begin + io_error = 1'b1; + end + end + end + endcase + end + + assign io_rts = _zz_io_rts; + assign sampler_synchroniser = io_rxd_buffercc_io_dataOut; + assign sampler_samples_0 = sampler_synchroniser; + always @(*) begin + bitTimer_tick = 1'b0; + if(sampler_tick) begin + if(when_UartCtrlRx_l43) begin + bitTimer_tick = 1'b1; + end + end + end + + assign when_UartCtrlRx_l43 = (bitTimer_counter == 3'b000); + assign break_valid = (break_counter == 7'h68); + assign when_UartCtrlRx_l69 = (io_samplingTick && (! break_valid)); + assign io_break = break_valid; + assign io_read_valid = stateMachine_validReg; + assign when_UartCtrlRx_l93 = ((sampler_tick && (! sampler_value)) && (! break_valid)); + assign when_UartCtrlRx_l103 = (sampler_value == 1'b1); + assign when_UartCtrlRx_l111 = (bitCounter_value == io_configFrame_dataLength); + assign when_UartCtrlRx_l113 = (io_configFrame_parity == UartParityType_NONE); + assign when_UartCtrlRx_l125 = (stateMachine_parity == sampler_value); + assign when_UartCtrlRx_l136 = (! sampler_value); + assign when_UartCtrlRx_l139 = (bitCounter_value == _zz_when_UartCtrlRx_l139); + assign io_read_payload = stateMachine_shifter; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + _zz_io_rts <= 1'b0; + sampler_samples_1 <= 1'b1; + sampler_samples_2 <= 1'b1; + sampler_samples_3 <= 1'b1; + sampler_samples_4 <= 1'b1; + sampler_value <= 1'b1; + sampler_tick <= 1'b0; + break_counter <= 7'h0; + stateMachine_state <= UartCtrlRxState_IDLE; + stateMachine_validReg <= 1'b0; + end else begin + _zz_io_rts <= (! io_read_ready); + if(io_samplingTick) begin + sampler_samples_1 <= sampler_samples_0; + end + if(io_samplingTick) begin + sampler_samples_2 <= sampler_samples_1; + end + if(io_samplingTick) begin + sampler_samples_3 <= sampler_samples_2; + end + if(io_samplingTick) begin + sampler_samples_4 <= sampler_samples_3; + end + sampler_value <= ((((((_zz_sampler_value || _zz_sampler_value_3) || (_zz_sampler_value_4 && sampler_samples_4)) || ((_zz_sampler_value_5 && sampler_samples_2) && sampler_samples_4)) || (((_zz_sampler_value_6 && sampler_samples_0) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_1) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_2) && sampler_samples_3) && sampler_samples_4)); + sampler_tick <= io_samplingTick; + if(sampler_value) begin + break_counter <= 7'h0; + end else begin + if(when_UartCtrlRx_l69) begin + break_counter <= (break_counter + 7'h01); + end + end + stateMachine_validReg <= 1'b0; + case(stateMachine_state) + UartCtrlRxState_IDLE : begin + if(when_UartCtrlRx_l93) begin + stateMachine_state <= UartCtrlRxState_START; + end + end + UartCtrlRxState_START : begin + if(bitTimer_tick) begin + stateMachine_state <= UartCtrlRxState_DATA; + if(when_UartCtrlRx_l103) begin + stateMachine_state <= UartCtrlRxState_IDLE; + end + end + end + UartCtrlRxState_DATA : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l111) begin + if(when_UartCtrlRx_l113) begin + stateMachine_state <= UartCtrlRxState_STOP; + stateMachine_validReg <= 1'b1; + end else begin + stateMachine_state <= UartCtrlRxState_PARITY; + end + end + end + end + UartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l125) begin + stateMachine_state <= UartCtrlRxState_STOP; + stateMachine_validReg <= 1'b1; + end else begin + stateMachine_state <= UartCtrlRxState_IDLE; + end + end + end + default : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l136) begin + stateMachine_state <= UartCtrlRxState_IDLE; + end else begin + if(when_UartCtrlRx_l139) begin + stateMachine_state <= UartCtrlRxState_IDLE; + end + end + end + end + endcase + end + end + + always @(posedge io_systemClk) begin + if(sampler_tick) begin + bitTimer_counter <= (bitTimer_counter - 3'b001); + end + if(bitTimer_tick) begin + bitCounter_value <= (bitCounter_value + 3'b001); + end + if(bitTimer_tick) begin + stateMachine_parity <= (stateMachine_parity ^ sampler_value); + end + case(stateMachine_state) + UartCtrlRxState_IDLE : begin + if(when_UartCtrlRx_l93) begin + bitTimer_counter <= 3'b010; + end + end + UartCtrlRxState_START : begin + if(bitTimer_tick) begin + bitCounter_value <= 3'b000; + stateMachine_parity <= (io_configFrame_parity == UartParityType_ODD); + end + end + UartCtrlRxState_DATA : begin + if(bitTimer_tick) begin + stateMachine_shifter[bitCounter_value] <= sampler_value; + if(when_UartCtrlRx_l111) begin + bitCounter_value <= 3'b000; + end + end + end + UartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + bitCounter_value <= 3'b000; + end + end + default : begin + end + endcase + end + + +endmodule + +module UartCtrlTx_b62b14ffe6bb44e5a817b8d08e286c6b ( + input [2:0] io_configFrame_dataLength, + input [0:0] io_configFrame_stop, + input [1:0] io_configFrame_parity, + input io_samplingTick, + input io_write_valid, + output reg io_write_ready, + input [7:0] io_write_payload, + input io_cts, + output io_txd, + input io_break, + input io_systemClk, + input systemCd_logic_outputReset +); + localparam UartStopType_ONE = 1'd0; + localparam UartStopType_TWO = 1'd1; + localparam UartParityType_NONE = 2'd0; + localparam UartParityType_EVEN = 2'd1; + localparam UartParityType_ODD = 2'd2; + localparam UartCtrlTxState_IDLE = 3'd0; + localparam UartCtrlTxState_START = 3'd1; + localparam UartCtrlTxState_DATA = 3'd2; + localparam UartCtrlTxState_PARITY = 3'd3; + localparam UartCtrlTxState_STOP = 3'd4; + + wire [2:0] _zz_clockDivider_counter_valueNext; + wire [0:0] _zz_clockDivider_counter_valueNext_1; + wire [2:0] _zz_when_UartCtrlTx_l93; + wire [0:0] _zz_when_UartCtrlTx_l93_1; + reg clockDivider_counter_willIncrement; + wire clockDivider_counter_willClear; + reg [2:0] clockDivider_counter_valueNext; + reg [2:0] clockDivider_counter_value; + wire clockDivider_counter_willOverflowIfInc; + wire clockDivider_counter_willOverflow; + reg [2:0] tickCounter_value; + reg [2:0] stateMachine_state; + reg stateMachine_parity; + reg stateMachine_txd; + wire when_UartCtrlTx_l58; + wire when_UartCtrlTx_l73; + wire when_UartCtrlTx_l76; + wire when_UartCtrlTx_l93; + reg _zz_io_txd; + `ifndef SYNTHESIS + reg [23:0] io_configFrame_stop_string; + reg [31:0] io_configFrame_parity_string; + reg [47:0] stateMachine_state_string; + `endif + + + assign _zz_clockDivider_counter_valueNext_1 = clockDivider_counter_willIncrement; + assign _zz_clockDivider_counter_valueNext = {2'd0, _zz_clockDivider_counter_valueNext_1}; + assign _zz_when_UartCtrlTx_l93_1 = ((io_configFrame_stop == UartStopType_ONE) ? 1'b0 : 1'b1); + assign _zz_when_UartCtrlTx_l93 = {2'd0, _zz_when_UartCtrlTx_l93_1}; + `ifndef SYNTHESIS + always @(*) begin + case(io_configFrame_stop) + UartStopType_ONE : io_configFrame_stop_string = "ONE"; + UartStopType_TWO : io_configFrame_stop_string = "TWO"; + default : io_configFrame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_configFrame_parity) + UartParityType_NONE : io_configFrame_parity_string = "NONE"; + UartParityType_EVEN : io_configFrame_parity_string = "EVEN"; + UartParityType_ODD : io_configFrame_parity_string = "ODD "; + default : io_configFrame_parity_string = "????"; + endcase + end + always @(*) begin + case(stateMachine_state) + UartCtrlTxState_IDLE : stateMachine_state_string = "IDLE "; + UartCtrlTxState_START : stateMachine_state_string = "START "; + UartCtrlTxState_DATA : stateMachine_state_string = "DATA "; + UartCtrlTxState_PARITY : stateMachine_state_string = "PARITY"; + UartCtrlTxState_STOP : stateMachine_state_string = "STOP "; + default : stateMachine_state_string = "??????"; + endcase + end + `endif + + always @(*) begin + clockDivider_counter_willIncrement = 1'b0; + if(io_samplingTick) begin + clockDivider_counter_willIncrement = 1'b1; + end + end + + assign clockDivider_counter_willClear = 1'b0; + assign clockDivider_counter_willOverflowIfInc = (clockDivider_counter_value == 3'b111); + assign clockDivider_counter_willOverflow = (clockDivider_counter_willOverflowIfInc && clockDivider_counter_willIncrement); + always @(*) begin + clockDivider_counter_valueNext = (clockDivider_counter_value + _zz_clockDivider_counter_valueNext); + if(clockDivider_counter_willClear) begin + clockDivider_counter_valueNext = 3'b000; + end + end + + always @(*) begin + stateMachine_txd = 1'b1; + case(stateMachine_state) + UartCtrlTxState_IDLE : begin + end + UartCtrlTxState_START : begin + stateMachine_txd = 1'b0; + end + UartCtrlTxState_DATA : begin + stateMachine_txd = io_write_payload[tickCounter_value]; + end + UartCtrlTxState_PARITY : begin + stateMachine_txd = stateMachine_parity; + end + default : begin + end + endcase + end + + always @(*) begin + io_write_ready = io_break; + case(stateMachine_state) + UartCtrlTxState_IDLE : begin + end + UartCtrlTxState_START : begin + end + UartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + io_write_ready = 1'b1; + end + end + end + UartCtrlTxState_PARITY : begin + end + default : begin + end + endcase + end + + assign when_UartCtrlTx_l58 = ((io_write_valid && (! io_cts)) && clockDivider_counter_willOverflow); + assign when_UartCtrlTx_l73 = (tickCounter_value == io_configFrame_dataLength); + assign when_UartCtrlTx_l76 = (io_configFrame_parity == UartParityType_NONE); + assign when_UartCtrlTx_l93 = (tickCounter_value == _zz_when_UartCtrlTx_l93); + assign io_txd = _zz_io_txd; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + clockDivider_counter_value <= 3'b000; + stateMachine_state <= UartCtrlTxState_IDLE; + _zz_io_txd <= 1'b1; + end else begin + clockDivider_counter_value <= clockDivider_counter_valueNext; + case(stateMachine_state) + UartCtrlTxState_IDLE : begin + if(when_UartCtrlTx_l58) begin + stateMachine_state <= UartCtrlTxState_START; + end + end + UartCtrlTxState_START : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_state <= UartCtrlTxState_DATA; + end + end + UartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + if(when_UartCtrlTx_l76) begin + stateMachine_state <= UartCtrlTxState_STOP; + end else begin + stateMachine_state <= UartCtrlTxState_PARITY; + end + end + end + end + UartCtrlTxState_PARITY : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_state <= UartCtrlTxState_STOP; + end + end + default : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l93) begin + stateMachine_state <= (io_write_valid ? UartCtrlTxState_START : UartCtrlTxState_IDLE); + end + end + end + endcase + _zz_io_txd <= (stateMachine_txd && (! io_break)); + end + end + + always @(posedge io_systemClk) begin + if(clockDivider_counter_willOverflow) begin + tickCounter_value <= (tickCounter_value + 3'b001); + end + if(clockDivider_counter_willOverflow) begin + stateMachine_parity <= (stateMachine_parity ^ stateMachine_txd); + end + case(stateMachine_state) + UartCtrlTxState_IDLE : begin + end + UartCtrlTxState_START : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_parity <= (io_configFrame_parity == UartParityType_ODD); + tickCounter_value <= 3'b000; + end + end + UartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + tickCounter_value <= 3'b000; + end + end + end + UartCtrlTxState_PARITY : begin + if(clockDivider_counter_willOverflow) begin + tickCounter_value <= 3'b000; + end + end + default : begin + end + endcase + end + + +endmodule + +module BufferCC_1_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_dataIn, + output io_dataOut, + input io_systemClk, + input debugCd_logic_outputReset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + initial begin + `ifndef SYNTHESIS + buffers_0 = $urandom; + buffers_1 = $urandom; + `endif + end + + assign io_dataOut = buffers_1; + always @(posedge io_systemClk) begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + + +endmodule + +module BufferCC_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_dataIn, + output io_dataOut, + input io_systemClk, + input systemCd_logic_outputReset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + buffers_0 <= 1'b0; + buffers_1 <= 1'b0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/sapphire_define.vh b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/sapphire_define.vh new file mode 100644 index 0000000..c60c9f4 --- /dev/null +++ b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/sapphire_define.vh @@ -0,0 +1,45 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2022.1.196 +// IP Version: 2.2 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + diff --git a/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/sapphire_tmpl.v b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/sapphire_tmpl.v new file mode 100644 index 0000000..4b3fc22 --- /dev/null +++ b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/sapphire_tmpl.v @@ -0,0 +1,76 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +sapphire u_sapphire( +.io_systemClk ( io_systemClk ), +.jtagCtrl_enable ( jtagCtrl_enable ), +.jtagCtrl_tdi ( jtagCtrl_tdi ), +.jtagCtrl_capture ( jtagCtrl_capture ), +.jtagCtrl_shift ( jtagCtrl_shift ), +.jtagCtrl_update ( jtagCtrl_update ), +.jtagCtrl_reset ( jtagCtrl_reset ), +.jtagCtrl_tdo ( jtagCtrl_tdo ), +.jtagCtrl_tck ( jtagCtrl_tck ), +.system_spi_0_io_data_0_read ( system_spi_0_io_data_0_read ), +.system_spi_0_io_data_0_write ( system_spi_0_io_data_0_write ), +.system_spi_0_io_data_0_writeEnable ( system_spi_0_io_data_0_writeEnable ), +.system_spi_0_io_data_1_read ( system_spi_0_io_data_1_read ), +.system_spi_0_io_data_1_write ( system_spi_0_io_data_1_write ), +.system_spi_0_io_data_1_writeEnable ( system_spi_0_io_data_1_writeEnable ), +.system_spi_0_io_data_2_read ( system_spi_0_io_data_2_read ), +.system_spi_0_io_data_2_write ( system_spi_0_io_data_2_write ), +.system_spi_0_io_data_2_writeEnable ( system_spi_0_io_data_2_writeEnable ), +.system_spi_0_io_data_3_read ( system_spi_0_io_data_3_read ), +.system_spi_0_io_data_3_write ( system_spi_0_io_data_3_write ), +.system_spi_0_io_data_3_writeEnable ( system_spi_0_io_data_3_writeEnable ), +.system_spi_0_io_sclk_write ( system_spi_0_io_sclk_write ), +.system_spi_0_io_ss ( system_spi_0_io_ss ), +.io_apbSlave_0_PADDR ( io_apbSlave_0_PADDR ), +.io_apbSlave_0_PENABLE ( io_apbSlave_0_PENABLE ), +.io_apbSlave_0_PRDATA ( io_apbSlave_0_PRDATA ), +.io_apbSlave_0_PREADY ( io_apbSlave_0_PREADY ), +.io_apbSlave_0_PSEL ( io_apbSlave_0_PSEL ), +.io_apbSlave_0_PSLVERROR ( io_apbSlave_0_PSLVERROR ), +.io_apbSlave_0_PWDATA ( io_apbSlave_0_PWDATA ), +.io_apbSlave_0_PWRITE ( io_apbSlave_0_PWRITE ), +.io_asyncReset ( io_asyncReset ), +.io_systemReset ( io_systemReset ), +.system_uart_0_io_txd ( system_uart_0_io_txd ), +.system_uart_0_io_rxd ( system_uart_0_io_rxd ) +); diff --git a/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/sapphire_tmpl.vhd b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/sapphire_tmpl.vhd new file mode 100644 index 0000000..a8c601e --- /dev/null +++ b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/sapphire_tmpl.vhd @@ -0,0 +1,118 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// +------------- Begin Cut here for COMPONENT Declaration ------ +COMPONENT sapphire is +PORT ( +io_systemClk : in std_logic; +jtagCtrl_enable : in std_logic; +jtagCtrl_tdi : in std_logic; +jtagCtrl_capture : in std_logic; +jtagCtrl_shift : in std_logic; +jtagCtrl_update : in std_logic; +jtagCtrl_reset : in std_logic; +jtagCtrl_tdo : out std_logic; +jtagCtrl_tck : in std_logic; +system_spi_0_io_data_0_read : in std_logic; +system_spi_0_io_data_0_write : out std_logic; +system_spi_0_io_data_0_writeEnable : out std_logic; +system_spi_0_io_data_1_read : in std_logic; +system_spi_0_io_data_1_write : out std_logic; +system_spi_0_io_data_1_writeEnable : out std_logic; +system_spi_0_io_data_2_read : in std_logic; +system_spi_0_io_data_2_write : out std_logic; +system_spi_0_io_data_2_writeEnable : out std_logic; +system_spi_0_io_data_3_read : in std_logic; +system_spi_0_io_data_3_write : out std_logic; +system_spi_0_io_data_3_writeEnable : out std_logic; +system_spi_0_io_sclk_write : out std_logic; +system_spi_0_io_ss : out std_logic_vector(0 to 0); +io_apbSlave_0_PADDR : out std_logic_vector(15 downto 0); +io_apbSlave_0_PENABLE : out std_logic; +io_apbSlave_0_PRDATA : in std_logic_vector(31 downto 0); +io_apbSlave_0_PREADY : in std_logic; +io_apbSlave_0_PSEL : out std_logic; +io_apbSlave_0_PSLVERROR : in std_logic; +io_apbSlave_0_PWDATA : out std_logic_vector(31 downto 0); +io_apbSlave_0_PWRITE : out std_logic; +io_asyncReset : in std_logic; +io_systemReset : out std_logic; +system_uart_0_io_txd : out std_logic; +system_uart_0_io_rxd : in std_logic); +END COMPONENT; +---------------------- End COMPONENT Declaration ------------ + +------------- Begin Cut here for INSTANTIATION Template ----- +u_sapphire : sapphire +PORT MAP ( +io_systemClk => io_systemClk, +jtagCtrl_enable => jtagCtrl_enable, +jtagCtrl_tdi => jtagCtrl_tdi, +jtagCtrl_capture => jtagCtrl_capture, +jtagCtrl_shift => jtagCtrl_shift, +jtagCtrl_update => jtagCtrl_update, +jtagCtrl_reset => jtagCtrl_reset, +jtagCtrl_tdo => jtagCtrl_tdo, +jtagCtrl_tck => jtagCtrl_tck, +system_spi_0_io_data_0_read => system_spi_0_io_data_0_read, +system_spi_0_io_data_0_write => system_spi_0_io_data_0_write, +system_spi_0_io_data_0_writeEnable => system_spi_0_io_data_0_writeEnable, +system_spi_0_io_data_1_read => system_spi_0_io_data_1_read, +system_spi_0_io_data_1_write => system_spi_0_io_data_1_write, +system_spi_0_io_data_1_writeEnable => system_spi_0_io_data_1_writeEnable, +system_spi_0_io_data_2_read => system_spi_0_io_data_2_read, +system_spi_0_io_data_2_write => system_spi_0_io_data_2_write, +system_spi_0_io_data_2_writeEnable => system_spi_0_io_data_2_writeEnable, +system_spi_0_io_data_3_read => system_spi_0_io_data_3_read, +system_spi_0_io_data_3_write => system_spi_0_io_data_3_write, +system_spi_0_io_data_3_writeEnable => system_spi_0_io_data_3_writeEnable, +system_spi_0_io_sclk_write => system_spi_0_io_sclk_write, +system_spi_0_io_ss => system_spi_0_io_ss, +io_apbSlave_0_PADDR => io_apbSlave_0_PADDR, +io_apbSlave_0_PENABLE => io_apbSlave_0_PENABLE, +io_apbSlave_0_PRDATA => io_apbSlave_0_PRDATA, +io_apbSlave_0_PREADY => io_apbSlave_0_PREADY, +io_apbSlave_0_PSEL => io_apbSlave_0_PSEL, +io_apbSlave_0_PSLVERROR => io_apbSlave_0_PSLVERROR, +io_apbSlave_0_PWDATA => io_apbSlave_0_PWDATA, +io_apbSlave_0_PWRITE => io_apbSlave_0_PWRITE, +io_asyncReset => io_asyncReset, +io_systemReset => io_systemReset, +system_uart_0_io_txd => system_uart_0_io_txd, +system_uart_0_io_rxd => system_uart_0_io_rxd); +------------------------ End INSTANTIATION Template --------- diff --git a/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/settings.json b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/settings.json new file mode 100644 index 0000000..594e31f --- /dev/null +++ b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/settings.json @@ -0,0 +1,156 @@ +{ + "args": [ + "-o", + "sapphire", + "--base_path", + "/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "soc", + "name": "efx_soc", + "version": "2.2" + } + ], + "conf": { + "HexFile_PathEnable": "0", + "HexFile_Path": "", + "APBSlave0_Size": "65536", + "DEVKIT_CUSTOM": "sapphireBoard_rev0", + "LDSize": "124", + "LDStackSize": "4", + "DEVKIT": "2", + "DEBUG": "1", + "SOFT_TAP": "0", + "TAP_COUNT": "0", + "TAP_SEL": "8", + "Frequency": "50", + "PeriFrequencyEnable": "0", + "PeriFrequency": "50", + "UART2_INT_ID": "3", + "TEST": "0", + "Base_M_AXIS": "3774873600", + "APBSlave0": "1", + "APBSlave2": "0", + "Base_M_IO": "4160749568", + "APBSlave1": "0", + "APBSlave3": "0", + "USER_1_INTR_ID": "17", + "USER_1_INTR": "0", + "USER_0_INTR_ID": "16", + "USER_0_INTR": "0", + "USER_2_INTR": "0", + "USER_2_INTR_ID": "22", + "USER_3_INTR": "0", + "USER_3_INTR_ID": "23", + "USER_4_INTR": "0", + "USER_4_INTR_ID": "24", + "USER_5_INTR": "0", + "USER_5_INTR_ID": "25", + "USER_6_INTR": "0", + "USER_6_INTR_ID": "26", + "USER_7_INTR": "0", + "USER_7_INTR_ID": "27", + "APBSlave4": "0", + "CustomInstruction": "0", + "ATMEXT": "0", + "CMREXT": "0", + "FPEXT": "1", + "FPU": "0", + "LINUX": "0", + "ICACHEWAY": "1", + "DCACHEWAY": "1", + "CpuCount": "1", + "ICacheSize": "4096", + "DCacheSize": "4096", + "Cache": "1", + "DDR": "0", + "DDR_AXI4": "0", + "DDRWidth": "128", + "DDRSize": "3758096384", + "OCRSize": "32768", + "AXISlave": "0", + "AXISlaveSize": "16777216", + "GPIO1_INT_ID1": "15", + "GPIO1_INT_ID0": "14", + "GPIO0_INT_ID1": "13", + "GPIO0_INT_ID0": "12", + "GPIO0": "0", + "GPIO0Width": "4", + "GPIO1Width": "8", + "GPIO1": "0", + "UART0_INT_ID": "1", + "IOSize": "4096", + "UART0_M_Addr": "4096", + "UART1_M_Addr": "8192", + "UART2_M_Addr": "12288", + "SPI0_M_Addr": "24576", + "SPI1_M_Addr": "16384", + "SPI2_M_Addr": "20480", + "I2C0_M_Addr": "40960", + "I2C1_M_Addr": "45056", + "I2C2_M_Addr": "49152", + "GPIO0_M_Addr": "53248", + "GPIO1_M_Addr": "57344", + "APBSlave0_M_Addr": "1048576", + "APBSlave1_M_Addr": "2097152", + "APBSlave2_M_Addr": "3145728", + "APBSlave3_M_Addr": "4194304", + "APBSlave4_M_Addr": "5242880", + "UART0": "1", + "UART2": "0", + "UART1_INT_ID": "2", + "UART1": "0", + "SPI2": "0", + "SPI2DW": "8", + "SPI2SS": "1", + "SPI1_INT_ID": "5", + "SPI1": "0", + "SPI1DW": "8", + "SPI1SS": "1", + "SPI0_INT_ID": "4", + "SPI0": "1", + "SPI0DW": "8", + "SPI0SS": "1", + "I2C2_INT_ID": "10", + "ADDR_Scheme": "0", + "I2C2": "0", + "I2C1": "0", + "SPI2_INT_ID": "6", + "I2C1_INT_ID": "9", + "I2C0_INT_ID": "8", + "I2C0": "0", + "AXIMasterWidth_1": "32", + "AXIMaster_1": "0", + "AXIMasterWidth": "32", + "AXIMaster": "1", + "USER_TIMER0": "0", + "USER_TIMER0_CNT_WIDTH": "12", + "USER_TIMER0_PS_WIDTH": "8", + "USER_TIMER0_INT_ID": "19", + "USER_TIMER0_M_Addr": "61440", + "USER_TIMER1": "0", + "USER_TIMER1_CNT_WIDTH": "12", + "USER_TIMER1_PS_WIDTH": "8", + "USER_TIMER1_INT_ID": "20", + "USER_TIMER1_M_Addr": "65536", + "USER_TIMER2": "0", + "USER_TIMER2_CNT_WIDTH": "12", + "USER_TIMER2_PS_WIDTH": "8", + "USER_TIMER2_INT_ID": "21", + "USER_TIMER2_M_Addr": "69632" + }, + "output": { + "external_generator": [], + "external_source": [ + "/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip/sapphire/sapphire_tmpl.v", + "/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip/sapphire/sapphire.v", + "/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip/sapphire/sapphire_define.vh", + "/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip/sapphire/sapphire_tmpl.vhd" + ], + "external_script": [], + "external_embedded_sw": [] + }, + "sw_version": "2022.1.196", + "generated_date": "2022-08-08T02:57:54.948573" +} \ No newline at end of file diff --git a/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v new file mode 100644 index 0000000..d8f0f2f --- /dev/null +++ b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v @@ -0,0 +1,14093 @@ +// Generator : SpinalHDL v1.7.1-SNAPSHOT git head : 2aaf6e4d1af9719ce8d12a973793990e489d8055 +// Component : EfxSapphireSoc + +`timescale 1ns/1ps + +module EfxSapphireSoc ( + input io_systemClk, + input io_asyncReset, + input jtagCtrl_tck, + output reg io_systemReset, + input jtagCtrl_tdi, + input jtagCtrl_enable, + input jtagCtrl_capture, + input jtagCtrl_shift, + input jtagCtrl_update, + input jtagCtrl_reset, + output jtagCtrl_tdo, + output system_uart_0_io_txd, + input system_uart_0_io_rxd, + output [15:0] io_apbSlave_0_PADDR, + output [0:0] io_apbSlave_0_PSEL, + output io_apbSlave_0_PENABLE, + input io_apbSlave_0_PREADY, + output io_apbSlave_0_PWRITE, + output [31:0] io_apbSlave_0_PWDATA, + input [31:0] io_apbSlave_0_PRDATA, + input io_apbSlave_0_PSLVERROR, + output [0:0] system_spi_0_io_sclk_write, + output system_spi_0_io_data_0_writeEnable, + input [0:0] system_spi_0_io_data_0_read, + output [0:0] system_spi_0_io_data_0_write, + output system_spi_0_io_data_1_writeEnable, + input [0:0] system_spi_0_io_data_1_read, + output [0:0] system_spi_0_io_data_1_write, + output system_spi_0_io_data_2_writeEnable, + input [0:0] system_spi_0_io_data_2_read, + output [0:0] system_spi_0_io_data_2_write, + output system_spi_0_io_data_3_writeEnable, + input [0:0] system_spi_0_io_data_3_read, + output [0:0] system_spi_0_io_data_3_write, + output [0:0] system_spi_0_io_ss +); + + reg system_cores_0_logic_cpu_dBus_rsp_valid; + wire system_cores_0_logic_cpu_dBus_rsp_payload_error; + wire system_cores_0_logic_cpu_debug_bus_cmd_payload_wr; + wire system_cores_0_logic_cpu_iBus_rsp_payload_error; + wire bufferCC_5_io_dataOut; + wire bufferCC_6_io_dataOut; + wire system_cores_0_logic_cpu_dBus_cmd_valid; + wire system_cores_0_logic_cpu_dBus_cmd_payload_wr; + wire system_cores_0_logic_cpu_dBus_cmd_payload_uncached; + wire [31:0] system_cores_0_logic_cpu_dBus_cmd_payload_address; + wire [31:0] system_cores_0_logic_cpu_dBus_cmd_payload_data; + wire [3:0] system_cores_0_logic_cpu_dBus_cmd_payload_mask; + wire [2:0] system_cores_0_logic_cpu_dBus_cmd_payload_size; + wire system_cores_0_logic_cpu_dBus_cmd_payload_last; + wire system_cores_0_logic_cpu_debug_bus_cmd_ready; + wire [31:0] system_cores_0_logic_cpu_debug_bus_rsp_data; + wire system_cores_0_logic_cpu_debug_resetOut; + wire system_cores_0_logic_cpu_iBus_cmd_valid; + wire [31:0] system_cores_0_logic_cpu_iBus_cmd_payload_address; + wire [2:0] system_cores_0_logic_cpu_iBus_cmd_payload_size; + wire system_hardJtag_debug_logic_jtagBridge_io_ctrl_tdo; + wire system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_valid; + wire system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_last; + wire [0:0] system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_fragment; + wire system_hardJtag_debug_logic_jtagBridge_io_remote_rsp_ready; + wire system_hardJtag_debug_logic_debugger_io_remote_cmd_ready; + wire system_hardJtag_debug_logic_debugger_io_remote_rsp_valid; + wire system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_error; + wire [31:0] system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_data; + wire system_hardJtag_debug_logic_debugger_io_mem_cmd_valid; + wire [31:0] system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address; + wire [31:0] system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_data; + wire system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_wr; + wire [1:0] system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_size; + wire bufferCC_7_io_dataOut; + wire bmbDecoder_4_io_input_cmd_ready; + wire bmbDecoder_4_io_input_rsp_valid; + wire bmbDecoder_4_io_input_rsp_payload_last; + wire [0:0] bmbDecoder_4_io_input_rsp_payload_fragment_opcode; + wire [31:0] bmbDecoder_4_io_input_rsp_payload_fragment_data; + wire bmbDecoder_4_io_outputs_0_cmd_valid; + wire bmbDecoder_4_io_outputs_0_cmd_payload_last; + wire [0:0] bmbDecoder_4_io_outputs_0_cmd_payload_fragment_opcode; + wire [31:0] bmbDecoder_4_io_outputs_0_cmd_payload_fragment_address; + wire [1:0] bmbDecoder_4_io_outputs_0_cmd_payload_fragment_length; + wire [31:0] bmbDecoder_4_io_outputs_0_cmd_payload_fragment_data; + wire [3:0] bmbDecoder_4_io_outputs_0_cmd_payload_fragment_mask; + wire bmbDecoder_4_io_outputs_0_rsp_ready; + wire system_fabric_exclusiveMonitor_logic_io_input_cmd_ready; + wire system_fabric_exclusiveMonitor_logic_io_input_rsp_valid; + wire system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_last; + wire [0:0] system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_opcode; + wire [31:0] system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_data; + wire [0:0] system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_context; + wire system_fabric_exclusiveMonitor_logic_io_output_cmd_valid; + wire system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_last; + wire [0:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_opcode; + wire [31:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_address; + wire [5:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_length; + wire [31:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_data; + wire [3:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_mask; + wire [0:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_context; + wire system_fabric_exclusiveMonitor_logic_io_output_rsp_ready; + wire system_fabric_iBus_bmb_decoder_io_input_cmd_ready; + wire system_fabric_iBus_bmb_decoder_io_input_rsp_valid; + wire system_fabric_iBus_bmb_decoder_io_input_rsp_payload_last; + wire [0:0] system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_opcode; + wire [31:0] system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_data; + wire system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_valid; + wire system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_last; + wire [0:0] system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; + wire [31:0] system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; + wire [5:0] system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; + wire system_fabric_iBus_bmb_decoder_io_outputs_0_rsp_ready; + wire system_bridge_bmb_arbiter_io_inputs_0_cmd_ready; + wire system_bridge_bmb_arbiter_io_inputs_0_rsp_valid; + wire system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_last; + wire [0:0] system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_data; + wire [0:0] system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_context; + wire system_bridge_bmb_arbiter_io_inputs_1_cmd_ready; + wire system_bridge_bmb_arbiter_io_inputs_1_rsp_valid; + wire system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_last; + wire [0:0] system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_data; + wire system_bridge_bmb_arbiter_io_output_cmd_valid; + wire system_bridge_bmb_arbiter_io_output_cmd_payload_last; + wire [0:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_source; + wire [0:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_address; + wire [5:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_length; + wire [31:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_data; + wire [3:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_mask; + wire [0:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_context; + wire system_bridge_bmb_arbiter_io_output_rsp_ready; + wire system_bridge_bmb_decoder_io_input_cmd_ready; + wire system_bridge_bmb_decoder_io_input_rsp_valid; + wire system_bridge_bmb_decoder_io_input_rsp_payload_last; + wire [0:0] system_bridge_bmb_decoder_io_input_rsp_payload_fragment_source; + wire [0:0] system_bridge_bmb_decoder_io_input_rsp_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_decoder_io_input_rsp_payload_fragment_data; + wire [0:0] system_bridge_bmb_decoder_io_input_rsp_payload_fragment_context; + wire system_bridge_bmb_decoder_io_outputs_0_cmd_valid; + wire system_bridge_bmb_decoder_io_outputs_0_cmd_payload_last; + wire [0:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_source; + wire [0:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; + wire [5:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; + wire [31:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; + wire [3:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask; + wire [0:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; + wire system_bridge_bmb_decoder_io_outputs_0_rsp_ready; + wire system_bridge_bmb_decoder_io_outputs_1_cmd_valid; + wire system_bridge_bmb_decoder_io_outputs_1_cmd_payload_last; + wire [0:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_source; + wire [0:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; + wire [5:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; + wire [31:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; + wire [3:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask; + wire [0:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; + wire system_bridge_bmb_decoder_io_outputs_1_rsp_ready; + wire system_ramA_logic_io_bus_cmd_ready; + wire system_ramA_logic_io_bus_rsp_valid; + wire system_ramA_logic_io_bus_rsp_payload_last; + wire [0:0] system_ramA_logic_io_bus_rsp_payload_fragment_opcode; + wire [31:0] system_ramA_logic_io_bus_rsp_payload_fragment_data; + wire [3:0] system_ramA_logic_io_bus_rsp_payload_fragment_context; + wire system_bridge_bmb_unburstify_io_input_cmd_ready; + wire system_bridge_bmb_unburstify_io_input_rsp_valid; + wire system_bridge_bmb_unburstify_io_input_rsp_payload_last; + wire [0:0] system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_source; + wire [0:0] system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_data; + wire [0:0] system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_context; + wire system_bridge_bmb_unburstify_io_output_cmd_valid; + wire system_bridge_bmb_unburstify_io_output_cmd_payload_last; + wire [0:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_address; + wire [1:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_length; + wire [31:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_data; + wire [3:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_mask; + wire [3:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_context; + wire system_bridge_bmb_unburstify_io_output_rsp_ready; + wire system_bridge_bmb_unburstify_1_io_input_cmd_ready; + wire system_bridge_bmb_unburstify_1_io_input_rsp_valid; + wire system_bridge_bmb_unburstify_1_io_input_rsp_payload_last; + wire [0:0] system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_source; + wire [0:0] system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_data; + wire [0:0] system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_context; + wire system_bridge_bmb_unburstify_1_io_output_cmd_valid; + wire system_bridge_bmb_unburstify_1_io_output_cmd_payload_last; + wire [0:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_address; + wire [1:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_length; + wire [31:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_data; + wire [3:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_mask; + wire [3:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_context; + wire system_bridge_bmb_unburstify_1_io_output_rsp_ready; + wire system_bmbPeripheral_bmb_decoder_io_input_cmd_ready; + wire system_bmbPeripheral_bmb_decoder_io_input_rsp_valid; + wire system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_last; + wire [0:0] system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode; + wire [31:0] system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context; + wire system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid; + wire system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last; + wire [0:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; + wire [23:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; + wire [1:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; + wire [31:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask; + wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; + wire system_bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready; + wire system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid; + wire system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last; + wire [0:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; + wire [23:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; + wire [1:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; + wire [31:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask; + wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; + wire system_bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready; + wire system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid; + wire system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last; + wire [0:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode; + wire [23:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address; + wire [1:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length; + wire [31:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_mask; + wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context; + wire system_bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready; + wire system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid; + wire system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last; + wire [0:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode; + wire [23:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address; + wire [1:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length; + wire [31:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_mask; + wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context; + wire system_bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready; + wire system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid; + wire system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last; + wire [0:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode; + wire [23:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address; + wire [1:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length; + wire [31:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_mask; + wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context; + wire system_bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready; + wire system_clint_logic_io_bus_cmd_ready; + wire system_clint_logic_io_bus_rsp_valid; + wire system_clint_logic_io_bus_rsp_payload_last; + wire [0:0] system_clint_logic_io_bus_rsp_payload_fragment_opcode; + wire [31:0] system_clint_logic_io_bus_rsp_payload_fragment_data; + wire [3:0] system_clint_logic_io_bus_rsp_payload_fragment_context; + wire [0:0] system_clint_logic_io_timerInterrupt; + wire [0:0] system_clint_logic_io_softwareInterrupt; + wire [63:0] system_clint_logic_io_time; + wire system_uart_0_io_logic_io_bus_cmd_ready; + wire system_uart_0_io_logic_io_bus_rsp_valid; + wire system_uart_0_io_logic_io_bus_rsp_payload_last; + wire [0:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode; + wire [31:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_data; + wire [3:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_context; + wire system_uart_0_io_logic_io_uart_txd; + wire system_uart_0_io_logic_io_interrupt; + wire system_spi_0_io_logic_io_ctrl_cmd_ready; + wire system_spi_0_io_logic_io_ctrl_rsp_valid; + wire system_spi_0_io_logic_io_ctrl_rsp_payload_last; + wire [0:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; + wire [31:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data; + wire [3:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context; + wire [0:0] system_spi_0_io_logic_io_spi_sclk_write; + wire [0:0] system_spi_0_io_logic_io_spi_ss; + wire [0:0] system_spi_0_io_logic_io_spi_data_0_write; + wire system_spi_0_io_logic_io_spi_data_0_writeEnable; + wire [0:0] system_spi_0_io_logic_io_spi_data_1_write; + wire system_spi_0_io_logic_io_spi_data_1_writeEnable; + wire [0:0] system_spi_0_io_logic_io_spi_data_2_write; + wire system_spi_0_io_logic_io_spi_data_2_writeEnable; + wire [0:0] system_spi_0_io_logic_io_spi_data_3_write; + wire system_spi_0_io_logic_io_spi_data_3_writeEnable; + wire system_spi_0_io_logic_io_interrupt; + wire io_apbSlave_0_logic_io_input_cmd_ready; + wire io_apbSlave_0_logic_io_input_rsp_valid; + wire io_apbSlave_0_logic_io_input_rsp_payload_last; + wire [0:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode; + wire [31:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_data; + wire [3:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_context; + wire [15:0] io_apbSlave_0_logic_io_output_PADDR; + wire [0:0] io_apbSlave_0_logic_io_output_PSEL; + wire io_apbSlave_0_logic_io_output_PENABLE; + wire io_apbSlave_0_logic_io_output_PWRITE; + wire [31:0] io_apbSlave_0_logic_io_output_PWDATA; + wire [29:0] _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address; + wire [6:0] _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask_1; + reg debugCd_logic_inputResetTrigger; + reg debugCd_logic_outputResetUnbuffered; + reg [11:0] debugCd_logic_holdingLogic_resetCounter; + wire when_ClockDomainGenerator_l77; + reg debugCd_logic_outputReset; + wire debugCd_logic_inputResetAdapter_stuff_syncTrigger; + reg systemCd_logic_inputResetTrigger; + reg systemCd_logic_outputResetUnbuffered; + reg [5:0] systemCd_logic_holdingLogic_resetCounter; + wire when_ClockDomainGenerator_l77_1; + reg systemCd_logic_outputReset; + wire system_cores_0_iBus_cmd_valid; + wire system_cores_0_iBus_cmd_ready; + wire system_cores_0_iBus_cmd_payload_last; + wire [0:0] system_cores_0_iBus_cmd_payload_fragment_opcode; + wire [31:0] system_cores_0_iBus_cmd_payload_fragment_address; + wire [5:0] system_cores_0_iBus_cmd_payload_fragment_length; + wire system_cores_0_iBus_rsp_valid; + wire system_cores_0_iBus_rsp_ready; + wire system_cores_0_iBus_rsp_payload_last; + wire [0:0] system_cores_0_iBus_rsp_payload_fragment_opcode; + wire [31:0] system_cores_0_iBus_rsp_payload_fragment_data; + wire system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_valid; + reg system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready; + wire system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_last; + wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_opcode; + wire [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_address; + wire [5:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; + wire [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_data; + wire [3:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_mask; + wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_context; + wire system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_valid; + wire system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_ready; + wire system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_last; + wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_opcode; + wire [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_data; + wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_context; + wire system_cores_0_logic_cpu_dBus_Bridge_withoutWriteBuffer_busCmdContext_isWrite; + reg [5:0] _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; + wire when_DataCache_l532; + reg system_cores_0_debugReset; + wire system_cores_0_iBus_connector_decoder_cmd_valid; + wire system_cores_0_iBus_connector_decoder_cmd_ready; + wire system_cores_0_iBus_connector_decoder_cmd_payload_last; + wire [0:0] system_cores_0_iBus_connector_decoder_cmd_payload_fragment_opcode; + wire [31:0] system_cores_0_iBus_connector_decoder_cmd_payload_fragment_address; + wire [5:0] system_cores_0_iBus_connector_decoder_cmd_payload_fragment_length; + wire system_cores_0_iBus_connector_decoder_rsp_valid; + wire system_cores_0_iBus_connector_decoder_rsp_ready; + wire system_cores_0_iBus_connector_decoder_rsp_payload_last; + wire [0:0] system_cores_0_iBus_connector_decoder_rsp_payload_fragment_opcode; + wire [31:0] system_cores_0_iBus_connector_decoder_rsp_payload_fragment_data; + reg _zz_system_cores_0_iBus_connector_decoder_rsp_ready; + wire system_cores_0_iBus_cmd_combStage_valid; + wire system_cores_0_iBus_cmd_combStage_ready; + wire system_cores_0_iBus_cmd_combStage_payload_last; + wire [0:0] system_cores_0_iBus_cmd_combStage_payload_fragment_opcode; + wire [31:0] system_cores_0_iBus_cmd_combStage_payload_fragment_address; + wire [5:0] system_cores_0_iBus_cmd_combStage_payload_fragment_length; + wire _zz_system_cores_0_iBus_rsp_valid; + reg _zz_system_cores_0_iBus_rsp_valid_1; + reg _zz_system_cores_0_iBus_rsp_payload_last; + reg [0:0] _zz_system_cores_0_iBus_rsp_payload_fragment_opcode; + reg [31:0] _zz_system_cores_0_iBus_rsp_payload_fragment_data; + wire when_Stream_l368; + wire system_cores_0_dBus_connector_decoder_cmd_valid; + wire system_cores_0_dBus_connector_decoder_cmd_ready; + wire system_cores_0_dBus_connector_decoder_cmd_payload_last; + wire [0:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_opcode; + wire [31:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_address; + wire [5:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_length; + wire [31:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_data; + wire [3:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_mask; + wire [0:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_context; + wire system_cores_0_dBus_connector_decoder_rsp_valid; + wire system_cores_0_dBus_connector_decoder_rsp_ready; + wire system_cores_0_dBus_connector_decoder_rsp_payload_last; + wire [0:0] system_cores_0_dBus_connector_decoder_rsp_payload_fragment_opcode; + wire [31:0] system_cores_0_dBus_connector_decoder_rsp_payload_fragment_data; + wire [0:0] system_cores_0_dBus_connector_decoder_rsp_payload_fragment_context; + wire system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid; + wire system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_ready; + wire system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_last; + wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_opcode; + wire [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_address; + wire [5:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_length; + wire [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_data; + wire [3:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_mask; + wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_context; + reg system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid; + reg system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_last; + reg [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_opcode; + reg [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_address; + reg [5:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_length; + reg [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_data; + reg [3:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_mask; + reg [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_context; + wire when_Stream_l368_1; + wire system_hardJtag_debug_logic_mmMaster_cmd_valid; + wire system_hardJtag_debug_logic_mmMaster_cmd_ready; + wire system_hardJtag_debug_logic_mmMaster_cmd_payload_last; + wire [0:0] system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_opcode; + wire [31:0] system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address; + wire [1:0] system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_length; + wire [31:0] system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_data; + wire [3:0] system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask; + wire system_hardJtag_debug_logic_mmMaster_rsp_valid; + wire system_hardJtag_debug_logic_mmMaster_rsp_ready; + wire system_hardJtag_debug_logic_mmMaster_rsp_payload_last; + wire [0:0] system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_opcode; + wire [31:0] system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_data; + reg [3:0] _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask; + wire system_hardJtag_debug_bmb_connector_decoder_cmd_valid; + wire system_hardJtag_debug_bmb_connector_decoder_cmd_ready; + wire system_hardJtag_debug_bmb_connector_decoder_cmd_payload_last; + wire [0:0] system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_opcode; + wire [31:0] system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_address; + wire [1:0] system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_length; + wire [31:0] system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_data; + wire [3:0] system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_mask; + wire system_hardJtag_debug_bmb_connector_decoder_rsp_valid; + wire system_hardJtag_debug_bmb_connector_decoder_rsp_ready; + wire system_hardJtag_debug_bmb_connector_decoder_rsp_payload_last; + wire [0:0] system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_opcode; + wire [31:0] system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_data; + wire system_fabric_iBus_bmb_cmd_valid; + reg system_fabric_iBus_bmb_cmd_ready; + wire system_fabric_iBus_bmb_cmd_payload_last; + wire [0:0] system_fabric_iBus_bmb_cmd_payload_fragment_opcode; + wire [31:0] system_fabric_iBus_bmb_cmd_payload_fragment_address; + wire [5:0] system_fabric_iBus_bmb_cmd_payload_fragment_length; + wire system_fabric_iBus_bmb_rsp_valid; + wire system_fabric_iBus_bmb_rsp_ready; + wire system_fabric_iBus_bmb_rsp_payload_last; + wire [0:0] system_fabric_iBus_bmb_rsp_payload_fragment_opcode; + wire [31:0] system_fabric_iBus_bmb_rsp_payload_fragment_data; + wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [31:0] system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [5:0] system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire system_cores_0_debugBmb_cmd_valid; + wire system_cores_0_debugBmb_cmd_ready; + wire system_cores_0_debugBmb_cmd_payload_last; + wire [0:0] system_cores_0_debugBmb_cmd_payload_fragment_opcode; + wire [7:0] system_cores_0_debugBmb_cmd_payload_fragment_address; + wire [1:0] system_cores_0_debugBmb_cmd_payload_fragment_length; + wire [31:0] system_cores_0_debugBmb_cmd_payload_fragment_data; + wire [3:0] system_cores_0_debugBmb_cmd_payload_fragment_mask; + wire system_cores_0_debugBmb_rsp_valid; + wire system_cores_0_debugBmb_rsp_ready; + wire system_cores_0_debugBmb_rsp_payload_last; + wire [0:0] system_cores_0_debugBmb_rsp_payload_fragment_opcode; + wire [31:0] system_cores_0_debugBmb_rsp_payload_fragment_data; + wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [5:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + reg _zz_io_input_rsp_ready; + wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_valid; + reg system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready; + wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_last; + wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_opcode; + wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_address; + wire [5:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_length; + wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_data; + wire [3:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_mask; + wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_context; + reg system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + reg system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + reg [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + reg [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + reg [5:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + reg [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + reg [3:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_mask; + reg [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid; + wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_ready; + wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_last; + wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_opcode; + wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_address; + wire [5:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_length; + wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_data; + wire [3:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_mask; + wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_context; + reg system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid; + reg system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_last; + reg [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_opcode; + reg [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_address; + reg [5:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_length; + reg [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_data; + reg [3:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_mask; + reg [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_context; + wire when_Stream_l368_2; + wire _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + reg _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + reg _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + reg [0:0] _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + reg [31:0] _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + reg [0:0] _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire when_Stream_l368_3; + wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [7:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire system_cores_0_logic_cpu_debug_bus_cmd_fire; + reg system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext; + wire system_fabric_dBusCoherent_bmb_cmd_valid; + wire system_fabric_dBusCoherent_bmb_cmd_ready; + wire system_fabric_dBusCoherent_bmb_cmd_payload_last; + wire [0:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_opcode; + wire [31:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_address; + wire [5:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_length; + wire [31:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_data; + wire [3:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_mask; + wire [0:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_context; + wire system_fabric_dBusCoherent_bmb_rsp_valid; + wire system_fabric_dBusCoherent_bmb_rsp_ready; + wire system_fabric_dBusCoherent_bmb_rsp_payload_last; + wire [0:0] system_fabric_dBusCoherent_bmb_rsp_payload_fragment_opcode; + wire [31:0] system_fabric_dBusCoherent_bmb_rsp_payload_fragment_data; + wire [0:0] system_fabric_dBusCoherent_bmb_rsp_payload_fragment_context; + wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [31:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [5:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + wire [0:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [0:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_fabric_dBusCoherent_bmb_connector_decoder_cmd_valid; + wire system_fabric_dBusCoherent_bmb_connector_decoder_cmd_ready; + wire system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_last; + wire [0:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_opcode; + wire [31:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_address; + wire [5:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_length; + wire [31:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_data; + wire [3:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_mask; + wire [0:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_context; + wire system_fabric_dBusCoherent_bmb_connector_decoder_rsp_valid; + wire system_fabric_dBusCoherent_bmb_connector_decoder_rsp_ready; + wire system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_last; + wire [0:0] system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_opcode; + wire [31:0] system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_data; + wire [0:0] system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_context; + wire system_fabric_exclusiveMonitor_output_connector_decoder_cmd_valid; + wire system_fabric_exclusiveMonitor_output_connector_decoder_cmd_ready; + wire system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_last; + wire [0:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_opcode; + wire [31:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_address; + wire [5:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_length; + wire [31:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_data; + wire [3:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_mask; + wire [0:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_context; + wire system_fabric_exclusiveMonitor_output_connector_decoder_rsp_valid; + wire system_fabric_exclusiveMonitor_output_connector_decoder_rsp_ready; + wire system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_last; + wire [0:0] system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_opcode; + wire [31:0] system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_data; + wire [0:0] system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_context; + wire system_fabric_dBus_bmb_cmd_valid; + wire system_fabric_dBus_bmb_cmd_ready; + wire system_fabric_dBus_bmb_cmd_payload_last; + wire [0:0] system_fabric_dBus_bmb_cmd_payload_fragment_opcode; + wire [31:0] system_fabric_dBus_bmb_cmd_payload_fragment_address; + wire [5:0] system_fabric_dBus_bmb_cmd_payload_fragment_length; + wire [31:0] system_fabric_dBus_bmb_cmd_payload_fragment_data; + wire [3:0] system_fabric_dBus_bmb_cmd_payload_fragment_mask; + wire [0:0] system_fabric_dBus_bmb_cmd_payload_fragment_context; + wire system_fabric_dBus_bmb_rsp_valid; + wire system_fabric_dBus_bmb_rsp_ready; + wire system_fabric_dBus_bmb_rsp_payload_last; + wire [0:0] system_fabric_dBus_bmb_rsp_payload_fragment_opcode; + wire [31:0] system_fabric_dBus_bmb_rsp_payload_fragment_data; + wire [0:0] system_fabric_dBus_bmb_rsp_payload_fragment_context; + wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [31:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [5:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + wire [0:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [0:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_fabric_iBus_bmb_cmd_m2sPipe_valid; + wire system_fabric_iBus_bmb_cmd_m2sPipe_ready; + wire system_fabric_iBus_bmb_cmd_m2sPipe_payload_last; + wire [0:0] system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_opcode; + wire [31:0] system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_address; + wire [5:0] system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_length; + reg system_fabric_iBus_bmb_cmd_rValid; + reg system_fabric_iBus_bmb_cmd_rData_last; + reg [0:0] system_fabric_iBus_bmb_cmd_rData_fragment_opcode; + reg [31:0] system_fabric_iBus_bmb_cmd_rData_fragment_address; + reg [5:0] system_fabric_iBus_bmb_cmd_rData_fragment_length; + wire when_Stream_l368_4; + wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid; + wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready; + wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last; + wire [0:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address; + wire [5:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length; + wire [31:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data; + wire [3:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask; + wire [0:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context; + wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid; + wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready; + wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last; + wire [0:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data; + wire [0:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context; + wire system_bridge_bmb_cmd_valid; + wire system_bridge_bmb_cmd_ready; + wire system_bridge_bmb_cmd_payload_last; + wire [0:0] system_bridge_bmb_cmd_payload_fragment_source; + wire [0:0] system_bridge_bmb_cmd_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_cmd_payload_fragment_address; + wire [5:0] system_bridge_bmb_cmd_payload_fragment_length; + wire [31:0] system_bridge_bmb_cmd_payload_fragment_data; + wire [3:0] system_bridge_bmb_cmd_payload_fragment_mask; + wire [0:0] system_bridge_bmb_cmd_payload_fragment_context; + wire system_bridge_bmb_rsp_valid; + wire system_bridge_bmb_rsp_ready; + wire system_bridge_bmb_rsp_payload_last; + wire [0:0] system_bridge_bmb_rsp_payload_fragment_source; + wire [0:0] system_bridge_bmb_rsp_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_rsp_payload_fragment_data; + wire [0:0] system_bridge_bmb_rsp_payload_fragment_context; + wire system_bridge_bmb_cmd_s2mPipe_valid; + reg system_bridge_bmb_cmd_s2mPipe_ready; + wire system_bridge_bmb_cmd_s2mPipe_payload_last; + wire [0:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_source; + wire [0:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_address; + wire [5:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_length; + wire [31:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_data; + wire [3:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_mask; + wire [0:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_context; + reg system_bridge_bmb_cmd_rValid; + reg system_bridge_bmb_cmd_rData_last; + reg [0:0] system_bridge_bmb_cmd_rData_fragment_source; + reg [0:0] system_bridge_bmb_cmd_rData_fragment_opcode; + reg [31:0] system_bridge_bmb_cmd_rData_fragment_address; + reg [5:0] system_bridge_bmb_cmd_rData_fragment_length; + reg [31:0] system_bridge_bmb_cmd_rData_fragment_data; + reg [3:0] system_bridge_bmb_cmd_rData_fragment_mask; + reg [0:0] system_bridge_bmb_cmd_rData_fragment_context; + wire system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid; + wire system_bridge_bmb_cmd_s2mPipe_m2sPipe_ready; + wire system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_last; + wire [0:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_source; + wire [0:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_address; + wire [5:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_length; + wire [31:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_data; + wire [3:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_mask; + wire [0:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_context; + reg system_bridge_bmb_cmd_s2mPipe_rValid; + reg system_bridge_bmb_cmd_s2mPipe_rData_last; + reg [0:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_source; + reg [0:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_opcode; + reg [31:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_address; + reg [5:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_length; + reg [31:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_data; + reg [3:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_mask; + reg [0:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_context; + wire when_Stream_l368_5; + wire system_bmbPeripheral_bmb_cmd_valid; + wire system_bmbPeripheral_bmb_cmd_ready; + wire system_bmbPeripheral_bmb_cmd_payload_last; + wire [0:0] system_bmbPeripheral_bmb_cmd_payload_fragment_opcode; + wire [23:0] system_bmbPeripheral_bmb_cmd_payload_fragment_address; + wire [1:0] system_bmbPeripheral_bmb_cmd_payload_fragment_length; + wire [31:0] system_bmbPeripheral_bmb_cmd_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_cmd_payload_fragment_mask; + wire [3:0] system_bmbPeripheral_bmb_cmd_payload_fragment_context; + wire system_bmbPeripheral_bmb_rsp_valid; + wire system_bmbPeripheral_bmb_rsp_ready; + wire system_bmbPeripheral_bmb_rsp_payload_last; + wire [0:0] system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; + wire [31:0] system_bmbPeripheral_bmb_rsp_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_rsp_payload_fragment_context; + wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [23:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + wire [3:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [14:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + wire [3:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [3:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + reg _zz_io_bus_rsp_ready; + wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_valid; + wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_ready; + wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_last; + wire [0:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_opcode; + wire [14:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_address; + wire [1:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_length; + wire [31:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_data; + wire [3:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_mask; + wire [3:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_context; + wire _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + reg _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + reg _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + reg [0:0] _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + reg [31:0] _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + reg [3:0] _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire when_Stream_l368_6; + wire _zz_io_input_rsp_ready_1; + wire system_bmbPeripheral_bmb_cmd_combStage_valid; + wire system_bmbPeripheral_bmb_cmd_combStage_ready; + wire system_bmbPeripheral_bmb_cmd_combStage_payload_last; + wire [0:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_opcode; + wire [23:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_address; + wire [1:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_length; + wire [31:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_mask; + wire [3:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_context; + wire _zz_system_bmbPeripheral_bmb_rsp_valid; + reg _zz_system_bmbPeripheral_bmb_rsp_valid_1; + reg _zz_system_bmbPeripheral_bmb_rsp_payload_last; + reg [0:0] _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; + reg [31:0] _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_data; + reg [3:0] _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_context; + wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [15:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [3:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + reg _zz_timerInterrupt; + reg _zz_softwareInterrupt; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [3:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire _zz_io_bus_rsp_ready_1; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last; + wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode; + wire [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address; + wire [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length; + wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data; + wire [3:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context; + reg system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire; + reg system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + reg [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + reg [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + reg [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + reg [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + reg [3:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + wire _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + reg _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + reg _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + reg [0:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + reg [31:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + reg [3:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire [1:0] system_uart_0_io_interrupt_plic_gateway_priority; + reg system_uart_0_io_interrupt_plic_gateway_ip; + reg system_uart_0_io_interrupt_plic_gateway_waitCompletion; + wire when_PlicGateway_l21; + wire [1:0] system_spi_0_io_interrupt_plic_gateway_priority; + reg system_spi_0_io_interrupt_plic_gateway_ip; + reg system_spi_0_io_interrupt_plic_gateway_waitCompletion; + wire when_PlicGateway_l21_1; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [3:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last; + wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode; + wire [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address; + wire [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length; + wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data; + wire [3:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context; + reg system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire; + reg system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + reg [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + reg [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + reg [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + reg [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + reg [3:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [15:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [3:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_bmbPeripheral_bmb_withoutMask_cmd_valid; + wire system_bmbPeripheral_bmb_withoutMask_cmd_ready; + wire system_bmbPeripheral_bmb_withoutMask_cmd_payload_last; + wire [0:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode; + wire [23:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address; + wire [1:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length; + wire [31:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context; + wire system_bmbPeripheral_bmb_withoutMask_rsp_valid; + wire system_bmbPeripheral_bmb_withoutMask_rsp_ready; + wire system_bmbPeripheral_bmb_withoutMask_rsp_payload_last; + wire [0:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode; + wire [31:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context; + wire system_bmbPeripheral_bmb_withoutMask_cmd_valid_1; + wire system_bmbPeripheral_bmb_withoutMask_cmd_ready_1; + wire system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_1; + wire [0:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1; + wire [23:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1; + wire [1:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1; + wire [31:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1; + wire [3:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1; + wire system_bmbPeripheral_bmb_withoutMask_rsp_valid_1; + wire system_bmbPeripheral_bmb_withoutMask_rsp_ready_1; + wire system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_1; + wire [0:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1; + wire [31:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1; + wire [3:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1; + wire system_plic_logic_bmb_cmd_valid; + wire system_plic_logic_bmb_cmd_ready; + wire system_plic_logic_bmb_cmd_payload_last; + wire [0:0] system_plic_logic_bmb_cmd_payload_fragment_opcode; + wire [21:0] system_plic_logic_bmb_cmd_payload_fragment_address; + wire [1:0] system_plic_logic_bmb_cmd_payload_fragment_length; + wire [31:0] system_plic_logic_bmb_cmd_payload_fragment_data; + wire [3:0] system_plic_logic_bmb_cmd_payload_fragment_context; + wire system_plic_logic_bmb_rsp_valid; + wire system_plic_logic_bmb_rsp_ready; + wire system_plic_logic_bmb_rsp_payload_last; + wire [0:0] system_plic_logic_bmb_rsp_payload_fragment_opcode; + wire [31:0] system_plic_logic_bmb_rsp_payload_fragment_data; + wire [3:0] system_plic_logic_bmb_rsp_payload_fragment_context; + reg system_plic_logic_bus_readHaltTrigger; + wire system_plic_logic_bus_writeHaltTrigger; + wire system_plic_logic_bus_rsp_valid; + wire system_plic_logic_bus_rsp_ready; + wire system_plic_logic_bus_rsp_payload_last; + wire [0:0] system_plic_logic_bus_rsp_payload_fragment_opcode; + reg [31:0] system_plic_logic_bus_rsp_payload_fragment_data; + wire [3:0] system_plic_logic_bus_rsp_payload_fragment_context; + wire _zz_system_plic_logic_bmb_rsp_valid; + reg _zz_system_plic_logic_bus_rsp_ready; + wire _zz_system_plic_logic_bmb_rsp_valid_1; + reg _zz_system_plic_logic_bmb_rsp_valid_2; + reg _zz_system_plic_logic_bmb_rsp_payload_last; + reg [0:0] _zz_system_plic_logic_bmb_rsp_payload_fragment_opcode; + reg [31:0] _zz_system_plic_logic_bmb_rsp_payload_fragment_data; + reg [3:0] _zz_system_plic_logic_bmb_rsp_payload_fragment_context; + wire when_Stream_l368_7; + wire system_plic_logic_bus_askWrite; + wire system_plic_logic_bus_askRead; + wire system_plic_logic_bmb_cmd_fire; + wire system_plic_logic_bus_doWrite; + wire system_plic_logic_bmb_cmd_fire_1; + wire system_plic_logic_bus_doRead; + wire system_cores_0_externalInterrupt_plic_target_ie_0; + wire system_cores_0_externalInterrupt_plic_target_ie_1; + wire [1:0] system_cores_0_externalInterrupt_plic_target_threshold; + wire [1:0] system_cores_0_externalInterrupt_plic_target_requests_0_priority; + wire [2:0] system_cores_0_externalInterrupt_plic_target_requests_0_id; + wire system_cores_0_externalInterrupt_plic_target_requests_0_valid; + wire [1:0] system_cores_0_externalInterrupt_plic_target_requests_1_priority; + wire [2:0] system_cores_0_externalInterrupt_plic_target_requests_1_id; + wire system_cores_0_externalInterrupt_plic_target_requests_1_valid; + wire [1:0] system_cores_0_externalInterrupt_plic_target_requests_2_priority; + wire [2:0] system_cores_0_externalInterrupt_plic_target_requests_2_id; + wire system_cores_0_externalInterrupt_plic_target_requests_2_valid; + wire _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority; + wire [1:0] _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1; + wire _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2; + wire _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3; + reg [1:0] system_cores_0_externalInterrupt_plic_target_bestRequest_priority; + reg [2:0] system_cores_0_externalInterrupt_plic_target_bestRequest_id; + reg system_cores_0_externalInterrupt_plic_target_bestRequest_valid; + wire system_cores_0_externalInterrupt_plic_target_iep; + wire [2:0] system_cores_0_externalInterrupt_plic_target_claim; + reg [1:0] _zz_system_uart_0_io_interrupt_plic_gateway_priority; + reg [1:0] _zz_system_spi_0_io_interrupt_plic_gateway_priority; + reg system_plic_logic_bridge_claim_valid; + reg [2:0] system_plic_logic_bridge_claim_payload; + reg system_plic_logic_bridge_completion_valid; + reg [2:0] system_plic_logic_bridge_completion_payload; + reg system_plic_logic_bridge_coherencyStall_willIncrement; + wire system_plic_logic_bridge_coherencyStall_willClear; + reg [0:0] system_plic_logic_bridge_coherencyStall_valueNext; + reg [0:0] system_plic_logic_bridge_coherencyStall_value; + wire system_plic_logic_bridge_coherencyStall_willOverflowIfInc; + wire system_plic_logic_bridge_coherencyStall_willOverflow; + wire when_PlicMapper_l122; + reg [1:0] _zz_system_cores_0_externalInterrupt_plic_target_threshold; + reg system_plic_logic_bridge_targetMapping_0_targetCompletion_valid; + wire [2:0] system_plic_logic_bridge_targetMapping_0_targetCompletion_payload; + reg _zz_system_cores_0_externalInterrupt_plic_target_ie_0; + reg _zz_system_cores_0_externalInterrupt_plic_target_ie_1; + reg system_cores_0_externalInterrupt_plic_target_iep_regNext; + wire system_bmbPeripheral_bmb_withoutMask_cmd_valid_2; + wire system_bmbPeripheral_bmb_withoutMask_cmd_ready_2; + wire system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_2; + wire [0:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2; + wire [23:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2; + wire [1:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2; + wire [31:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2; + wire [3:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2; + wire system_bmbPeripheral_bmb_withoutMask_rsp_valid_2; + wire system_bmbPeripheral_bmb_withoutMask_rsp_ready_2; + wire system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_2; + wire [0:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2; + wire [31:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2; + wire [3:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2; + wire system_bmbPeripheral_bmb_withoutMask_cmd_valid_3; + wire system_bmbPeripheral_bmb_withoutMask_cmd_ready_3; + wire system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_3; + wire [0:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3; + wire [23:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3; + wire [1:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3; + wire [31:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3; + wire [3:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3; + wire system_bmbPeripheral_bmb_withoutMask_rsp_valid_3; + wire system_bmbPeripheral_bmb_withoutMask_rsp_ready_3; + wire system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_3; + wire [0:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3; + wire [31:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3; + wire [3:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3; + wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [21:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [3:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_bmbPeripheral_bmb_withoutMask_cmd_valid_4; + wire system_bmbPeripheral_bmb_withoutMask_cmd_ready_4; + wire system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_4; + wire [0:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4; + wire [23:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4; + wire [1:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4; + wire [31:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4; + wire [3:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4; + wire system_bmbPeripheral_bmb_withoutMask_rsp_valid_4; + wire system_bmbPeripheral_bmb_withoutMask_rsp_ready_4; + wire system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_4; + wire [0:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4; + wire [31:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4; + wire [3:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4; + wire when_BmbSlaveFactory_l71; + + assign _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address = (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address >>> 2); + assign _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask_1 = ({3'd0,_zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask} <<< system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address[1 : 0]); + BufferCC_2 bufferCC_5 ( + .io_dataIn (1'b0 ), //i + .io_dataOut (bufferCC_5_io_dataOut), //o + .io_systemClk (io_systemClk ), //i + .io_asyncReset (io_asyncReset ) //i + ); + BufferCC_3 bufferCC_6 ( + .io_dataIn (1'b0 ), //i + .io_dataOut (bufferCC_6_io_dataOut ), //o + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset) //i + ); + VexRiscv system_cores_0_logic_cpu ( + .dBus_cmd_valid (system_cores_0_logic_cpu_dBus_cmd_valid ), //o + .dBus_cmd_ready (system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready ), //i + .dBus_cmd_payload_wr (system_cores_0_logic_cpu_dBus_cmd_payload_wr ), //o + .dBus_cmd_payload_uncached (system_cores_0_logic_cpu_dBus_cmd_payload_uncached ), //o + .dBus_cmd_payload_address (system_cores_0_logic_cpu_dBus_cmd_payload_address[31:0] ), //o + .dBus_cmd_payload_data (system_cores_0_logic_cpu_dBus_cmd_payload_data[31:0] ), //o + .dBus_cmd_payload_mask (system_cores_0_logic_cpu_dBus_cmd_payload_mask[3:0] ), //o + .dBus_cmd_payload_size (system_cores_0_logic_cpu_dBus_cmd_payload_size[2:0] ), //o + .dBus_cmd_payload_last (system_cores_0_logic_cpu_dBus_cmd_payload_last ), //o + .dBus_rsp_valid (system_cores_0_logic_cpu_dBus_rsp_valid ), //i + .dBus_rsp_payload_last (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_last ), //i + .dBus_rsp_payload_data (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_data[31:0]), //i + .dBus_rsp_payload_error (system_cores_0_logic_cpu_dBus_rsp_payload_error ), //i + .timerInterrupt (_zz_timerInterrupt ), //i + .externalInterrupt (system_cores_0_externalInterrupt_plic_target_iep_regNext ), //i + .softwareInterrupt (_zz_softwareInterrupt ), //i + .debug_bus_cmd_valid (system_cores_0_debugBmb_cmd_valid ), //i + .debug_bus_cmd_ready (system_cores_0_logic_cpu_debug_bus_cmd_ready ), //o + .debug_bus_cmd_payload_wr (system_cores_0_logic_cpu_debug_bus_cmd_payload_wr ), //i + .debug_bus_cmd_payload_address (system_cores_0_debugBmb_cmd_payload_fragment_address[7:0] ), //i + .debug_bus_cmd_payload_data (system_cores_0_debugBmb_cmd_payload_fragment_data[31:0] ), //i + .debug_bus_rsp_data (system_cores_0_logic_cpu_debug_bus_rsp_data[31:0] ), //o + .debug_resetOut (system_cores_0_logic_cpu_debug_resetOut ), //o + .iBus_cmd_valid (system_cores_0_logic_cpu_iBus_cmd_valid ), //o + .iBus_cmd_ready (system_cores_0_iBus_cmd_ready ), //i + .iBus_cmd_payload_address (system_cores_0_logic_cpu_iBus_cmd_payload_address[31:0] ), //o + .iBus_cmd_payload_size (system_cores_0_logic_cpu_iBus_cmd_payload_size[2:0] ), //o + .iBus_rsp_valid (system_cores_0_iBus_rsp_valid ), //i + .iBus_rsp_payload_data (system_cores_0_iBus_rsp_payload_fragment_data[31:0] ), //i + .iBus_rsp_payload_error (system_cores_0_logic_cpu_iBus_rsp_payload_error ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i + ); + JtagBridgeNoTap system_hardJtag_debug_logic_jtagBridge ( + .io_ctrl_tdi (jtagCtrl_tdi ), //i + .io_ctrl_enable (jtagCtrl_enable ), //i + .io_ctrl_capture (jtagCtrl_capture ), //i + .io_ctrl_shift (jtagCtrl_shift ), //i + .io_ctrl_update (jtagCtrl_update ), //i + .io_ctrl_reset (jtagCtrl_reset ), //i + .io_ctrl_tdo (system_hardJtag_debug_logic_jtagBridge_io_ctrl_tdo ), //o + .io_remote_cmd_valid (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_valid ), //o + .io_remote_cmd_ready (system_hardJtag_debug_logic_debugger_io_remote_cmd_ready ), //i + .io_remote_cmd_payload_last (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_last ), //o + .io_remote_cmd_payload_fragment (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_fragment), //o + .io_remote_rsp_valid (system_hardJtag_debug_logic_debugger_io_remote_rsp_valid ), //i + .io_remote_rsp_ready (system_hardJtag_debug_logic_jtagBridge_io_remote_rsp_ready ), //o + .io_remote_rsp_payload_error (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_error ), //i + .io_remote_rsp_payload_data (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_data[31:0]), //i + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ), //i + .jtagCtrl_tck (jtagCtrl_tck ) //i + ); + SystemDebugger system_hardJtag_debug_logic_debugger ( + .io_remote_cmd_valid (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_valid ), //i + .io_remote_cmd_ready (system_hardJtag_debug_logic_debugger_io_remote_cmd_ready ), //o + .io_remote_cmd_payload_last (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_last ), //i + .io_remote_cmd_payload_fragment (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_fragment), //i + .io_remote_rsp_valid (system_hardJtag_debug_logic_debugger_io_remote_rsp_valid ), //o + .io_remote_rsp_ready (system_hardJtag_debug_logic_jtagBridge_io_remote_rsp_ready ), //i + .io_remote_rsp_payload_error (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_error ), //o + .io_remote_rsp_payload_data (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_data[31:0]), //o + .io_mem_cmd_valid (system_hardJtag_debug_logic_debugger_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (system_hardJtag_debug_logic_mmMaster_cmd_ready ), //i + .io_mem_cmd_payload_address (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address[31:0]), //o + .io_mem_cmd_payload_data (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_wr (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_size (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_size[1:0] ), //o + .io_mem_rsp_valid (system_hardJtag_debug_logic_mmMaster_rsp_valid ), //i + .io_mem_rsp_payload (system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_data[31:0] ), //i + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i + ); + BufferCC_4 bufferCC_7 ( + .io_dataIn (1'b0 ), //i + .io_dataOut (bufferCC_7_io_dataOut ), //o + .io_systemClk (io_systemClk ), //i + .system_cores_0_debugReset (system_cores_0_debugReset) //i + ); + BmbDecoder bmbDecoder_4 ( + .io_input_cmd_valid (system_hardJtag_debug_bmb_connector_decoder_cmd_valid ), //i + .io_input_cmd_ready (bmbDecoder_4_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_length[1:0] ), //i + .io_input_cmd_payload_fragment_data (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_mask[3:0] ), //i + .io_input_rsp_valid (bmbDecoder_4_io_input_rsp_valid ), //o + .io_input_rsp_ready (system_hardJtag_debug_bmb_connector_decoder_rsp_ready ), //i + .io_input_rsp_payload_last (bmbDecoder_4_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (bmbDecoder_4_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (bmbDecoder_4_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_valid (bmbDecoder_4_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i + .io_outputs_0_cmd_payload_last (bmbDecoder_4_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_opcode (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_address[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_length (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_0_cmd_payload_fragment_data (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_mask (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_0_rsp_valid (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i + .io_outputs_0_rsp_ready (bmbDecoder_4_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i + .io_outputs_0_rsp_payload_fragment_opcode (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i + .io_outputs_0_rsp_payload_fragment_data (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0]), //i + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i + ); + BmbExclusiveMonitor system_fabric_exclusiveMonitor_logic ( + .io_input_cmd_valid (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid ), //i + .io_input_cmd_ready (system_fabric_exclusiveMonitor_logic_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_address[31:0]), //i + .io_input_cmd_payload_fragment_length (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_length[5:0] ), //i + .io_input_cmd_payload_fragment_data (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_context ), //i + .io_input_rsp_valid (system_fabric_exclusiveMonitor_logic_io_input_rsp_valid ), //o + .io_input_rsp_ready (_zz_io_input_rsp_ready ), //i + .io_input_rsp_payload_last (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_context ), //o + .io_output_cmd_valid (system_fabric_exclusiveMonitor_logic_io_output_cmd_valid ), //o + .io_output_cmd_ready (system_fabric_exclusiveMonitor_output_connector_decoder_cmd_ready ), //i + .io_output_cmd_payload_last (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_length[5:0] ), //o + .io_output_cmd_payload_fragment_data (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_data[31:0] ), //o + .io_output_cmd_payload_fragment_mask (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_mask[3:0] ), //o + .io_output_cmd_payload_fragment_context (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_context ), //o + .io_output_rsp_valid (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_valid ), //i + .io_output_rsp_ready (system_fabric_exclusiveMonitor_logic_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_data[31:0] ), //i + .io_output_rsp_payload_fragment_context (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_context ) //i + ); + BmbDecoder_1 system_fabric_iBus_bmb_decoder ( + .io_input_cmd_valid (system_fabric_iBus_bmb_cmd_m2sPipe_valid ), //i + .io_input_cmd_ready (system_fabric_iBus_bmb_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_fabric_iBus_bmb_cmd_m2sPipe_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_length[5:0] ), //i + .io_input_rsp_valid (system_fabric_iBus_bmb_decoder_io_input_rsp_valid ), //o + .io_input_rsp_ready (system_fabric_iBus_bmb_rsp_ready ), //i + .io_input_rsp_payload_last (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_valid (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (system_bridge_bmb_arbiter_io_inputs_1_cmd_ready ), //i + .io_outputs_0_cmd_payload_last (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0]), //o + .io_outputs_0_cmd_payload_fragment_length (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //o + .io_outputs_0_rsp_valid (system_bridge_bmb_arbiter_io_inputs_1_rsp_valid ), //i + .io_outputs_0_rsp_ready (system_fabric_iBus_bmb_decoder_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_last ), //i + .io_outputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //i + .io_outputs_0_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_data[31:0] ) //i + ); + BmbArbiter system_bridge_bmb_arbiter ( + .io_inputs_0_cmd_valid (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid ), //i + .io_inputs_0_cmd_ready (system_bridge_bmb_arbiter_io_inputs_0_cmd_ready ), //o + .io_inputs_0_cmd_payload_last (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last ), //i + .io_inputs_0_cmd_payload_fragment_opcode (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode ), //i + .io_inputs_0_cmd_payload_fragment_address (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address[31:0]), //i + .io_inputs_0_cmd_payload_fragment_length (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length[5:0] ), //i + .io_inputs_0_cmd_payload_fragment_data (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data[31:0] ), //i + .io_inputs_0_cmd_payload_fragment_mask (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask[3:0] ), //i + .io_inputs_0_cmd_payload_fragment_context (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context ), //i + .io_inputs_0_rsp_valid (system_bridge_bmb_arbiter_io_inputs_0_rsp_valid ), //o + .io_inputs_0_rsp_ready (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready ), //i + .io_inputs_0_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_last ), //o + .io_inputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_opcode ), //o + .io_inputs_0_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_data[31:0] ), //o + .io_inputs_0_rsp_payload_fragment_context (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_context ), //o + .io_inputs_1_cmd_valid (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_valid ), //i + .io_inputs_1_cmd_ready (system_bridge_bmb_arbiter_io_inputs_1_cmd_ready ), //o + .io_inputs_1_cmd_payload_last (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_last ), //i + .io_inputs_1_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //i + .io_inputs_1_cmd_payload_fragment_address (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_1_cmd_payload_fragment_length (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //i + .io_inputs_1_cmd_payload_fragment_data (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ), //i + .io_inputs_1_cmd_payload_fragment_mask (4'bxxxx ), //i + .io_inputs_1_rsp_valid (system_bridge_bmb_arbiter_io_inputs_1_rsp_valid ), //o + .io_inputs_1_rsp_ready (system_fabric_iBus_bmb_decoder_io_outputs_0_rsp_ready ), //i + .io_inputs_1_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_last ), //o + .io_inputs_1_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //o + .io_inputs_1_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_data[31:0] ), //o + .io_output_cmd_valid (system_bridge_bmb_arbiter_io_output_cmd_valid ), //o + .io_output_cmd_ready (system_bridge_bmb_cmd_ready ), //i + .io_output_cmd_payload_last (system_bridge_bmb_arbiter_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_source (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_source ), //o + .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_length[5:0] ), //o + .io_output_cmd_payload_fragment_data (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_data[31:0] ), //o + .io_output_cmd_payload_fragment_mask (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_mask[3:0] ), //o + .io_output_cmd_payload_fragment_context (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_context ), //o + .io_output_rsp_valid (system_bridge_bmb_rsp_valid ), //i + .io_output_rsp_ready (system_bridge_bmb_arbiter_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (system_bridge_bmb_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_source (system_bridge_bmb_rsp_payload_fragment_source ), //i + .io_output_rsp_payload_fragment_opcode (system_bridge_bmb_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (system_bridge_bmb_rsp_payload_fragment_data[31:0] ), //i + .io_output_rsp_payload_fragment_context (system_bridge_bmb_rsp_payload_fragment_context ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbDecoder_2 system_bridge_bmb_decoder ( + .io_input_cmd_valid (system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid ), //i + .io_input_cmd_ready (system_bridge_bmb_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_last ), //i + .io_input_cmd_payload_fragment_source (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_length[5:0] ), //i + .io_input_cmd_payload_fragment_data (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_context ), //i + .io_input_rsp_valid (system_bridge_bmb_decoder_io_input_rsp_valid ), //o + .io_input_rsp_ready (system_bridge_bmb_rsp_ready ), //i + .io_input_rsp_payload_last (system_bridge_bmb_decoder_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_context ), //o + .io_outputs_0_cmd_valid (system_bridge_bmb_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (system_bridge_bmb_unburstify_1_io_input_cmd_ready ), //i + .io_outputs_0_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_source ), //o + .io_outputs_0_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0]), //o + .io_outputs_0_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //o + .io_outputs_0_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_0_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_context ), //o + .io_outputs_0_rsp_valid (system_bridge_bmb_unburstify_1_io_input_rsp_valid ), //i + .io_outputs_0_rsp_ready (system_bridge_bmb_decoder_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (system_bridge_bmb_unburstify_1_io_input_rsp_payload_last ), //i + .io_outputs_0_rsp_payload_fragment_source (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_source ), //i + .io_outputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_opcode ), //i + .io_outputs_0_rsp_payload_fragment_data (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_data[31:0] ), //i + .io_outputs_0_rsp_payload_fragment_context (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_context ), //i + .io_outputs_1_cmd_valid (system_bridge_bmb_decoder_io_outputs_1_cmd_valid ), //o + .io_outputs_1_cmd_ready (system_bridge_bmb_unburstify_io_input_cmd_ready ), //i + .io_outputs_1_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_last ), //o + .io_outputs_1_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_source ), //o + .io_outputs_1_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //o + .io_outputs_1_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[31:0]), //o + .io_outputs_1_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[5:0] ), //o + .io_outputs_1_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_1_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_1_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_context ), //o + .io_outputs_1_rsp_valid (system_bridge_bmb_unburstify_io_input_rsp_valid ), //i + .io_outputs_1_rsp_ready (system_bridge_bmb_decoder_io_outputs_1_rsp_ready ), //o + .io_outputs_1_rsp_payload_last (system_bridge_bmb_unburstify_io_input_rsp_payload_last ), //i + .io_outputs_1_rsp_payload_fragment_source (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_source ), //i + .io_outputs_1_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_opcode ), //i + .io_outputs_1_rsp_payload_fragment_data (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //i + .io_outputs_1_rsp_payload_fragment_context (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_context ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbOnChipRam system_ramA_logic ( + .io_bus_cmd_valid (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_valid ), //i + .io_bus_cmd_ready (system_ramA_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_address[14:0]), //i + .io_bus_cmd_payload_fragment_length (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_mask (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_mask[3:0] ), //i + .io_bus_cmd_payload_fragment_context (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_context[3:0] ), //i + .io_bus_rsp_valid (system_ramA_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (_zz_io_bus_rsp_ready ), //i + .io_bus_rsp_payload_last (system_ramA_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_ramA_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_ramA_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_ramA_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbUnburstify system_bridge_bmb_unburstify ( + .io_input_cmd_valid (system_bridge_bmb_decoder_io_outputs_1_cmd_valid ), //i + .io_input_cmd_ready (system_bridge_bmb_unburstify_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[5:0] ), //i + .io_input_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_context ), //i + .io_input_rsp_valid (system_bridge_bmb_unburstify_io_input_rsp_valid ), //o + .io_input_rsp_ready (system_bridge_bmb_decoder_io_outputs_1_rsp_ready ), //i + .io_input_rsp_payload_last (system_bridge_bmb_unburstify_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_context ), //o + .io_output_cmd_valid (system_bridge_bmb_unburstify_io_output_cmd_valid ), //o + .io_output_cmd_ready (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i + .io_output_cmd_payload_last (system_bridge_bmb_unburstify_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_length[1:0] ), //o + .io_output_cmd_payload_fragment_data (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_data[31:0] ), //o + .io_output_cmd_payload_fragment_mask (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_mask[3:0] ), //o + .io_output_cmd_payload_fragment_context (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_context[3:0] ), //o + .io_output_rsp_valid (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i + .io_output_rsp_ready (system_bridge_bmb_unburstify_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0] ), //i + .io_output_rsp_payload_fragment_context (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context[3:0]), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbUnburstify system_bridge_bmb_unburstify_1 ( + .io_input_cmd_valid (system_bridge_bmb_decoder_io_outputs_0_cmd_valid ), //i + .io_input_cmd_ready (system_bridge_bmb_unburstify_1_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //i + .io_input_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_context ), //i + .io_input_rsp_valid (system_bridge_bmb_unburstify_1_io_input_rsp_valid ), //o + .io_input_rsp_ready (system_bridge_bmb_decoder_io_outputs_0_rsp_ready ), //i + .io_input_rsp_payload_last (system_bridge_bmb_unburstify_1_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_context ), //o + .io_output_cmd_valid (system_bridge_bmb_unburstify_1_io_output_cmd_valid ), //o + .io_output_cmd_ready (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i + .io_output_cmd_payload_last (system_bridge_bmb_unburstify_1_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_length[1:0] ), //o + .io_output_cmd_payload_fragment_data (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_data[31:0] ), //o + .io_output_cmd_payload_fragment_mask (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_mask[3:0] ), //o + .io_output_cmd_payload_fragment_context (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_context[3:0] ), //o + .io_output_rsp_valid (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i + .io_output_rsp_ready (system_bridge_bmb_unburstify_1_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0] ), //i + .io_output_rsp_payload_fragment_context (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context[3:0]), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbDecoder_3 system_bmbPeripheral_bmb_decoder ( + .io_input_cmd_valid (system_bmbPeripheral_bmb_cmd_combStage_valid ), //i + .io_input_cmd_ready (system_bmbPeripheral_bmb_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_bmbPeripheral_bmb_cmd_combStage_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_address[23:0] ), //i + .io_input_cmd_payload_fragment_length (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_length[1:0] ), //i + .io_input_cmd_payload_fragment_data (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_context[3:0] ), //i + .io_input_rsp_valid (system_bmbPeripheral_bmb_decoder_io_input_rsp_valid ), //o + .io_input_rsp_ready (_zz_io_input_rsp_ready_1 ), //i + .io_input_rsp_payload_last (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context[3:0] ), //o + .io_outputs_0_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_4 ), //i + .io_outputs_0_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[23:0]), //o + .io_outputs_0_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_0_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_0_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context[3:0] ), //o + .io_outputs_0_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_4 ), //i + .io_outputs_0_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 ), //i + .io_outputs_0_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 ), //i + .io_outputs_0_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4[31:0] ), //i + .io_outputs_0_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4[3:0] ), //i + .io_outputs_1_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid ), //o + .io_outputs_1_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready ), //i + .io_outputs_1_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last ), //o + .io_outputs_1_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //o + .io_outputs_1_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[23:0]), //o + .io_outputs_1_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_1_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_1_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_1_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context[3:0] ), //o + .io_outputs_1_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid ), //i + .io_outputs_1_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready ), //o + .io_outputs_1_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last ), //i + .io_outputs_1_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode ), //i + .io_outputs_1_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data[31:0] ), //i + .io_outputs_1_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context[3:0] ), //i + .io_outputs_2_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid ), //o + .io_outputs_2_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_1 ), //i + .io_outputs_2_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last ), //o + .io_outputs_2_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode ), //o + .io_outputs_2_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address[23:0]), //o + .io_outputs_2_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_2_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_2_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_2_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context[3:0] ), //o + .io_outputs_2_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_1 ), //i + .io_outputs_2_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready ), //o + .io_outputs_2_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 ), //i + .io_outputs_2_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 ), //i + .io_outputs_2_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1[31:0] ), //i + .io_outputs_2_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1[3:0] ), //i + .io_outputs_3_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid ), //o + .io_outputs_3_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_2 ), //i + .io_outputs_3_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last ), //o + .io_outputs_3_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode ), //o + .io_outputs_3_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address[23:0]), //o + .io_outputs_3_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_3_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_3_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_3_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context[3:0] ), //o + .io_outputs_3_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_2 ), //i + .io_outputs_3_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready ), //o + .io_outputs_3_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 ), //i + .io_outputs_3_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 ), //i + .io_outputs_3_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2[31:0] ), //i + .io_outputs_3_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2[3:0] ), //i + .io_outputs_4_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid ), //o + .io_outputs_4_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_3 ), //i + .io_outputs_4_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last ), //o + .io_outputs_4_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode ), //o + .io_outputs_4_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address[23:0]), //o + .io_outputs_4_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_4_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_4_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_4_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context[3:0] ), //o + .io_outputs_4_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_3 ), //i + .io_outputs_4_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready ), //o + .io_outputs_4_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 ), //i + .io_outputs_4_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 ), //i + .io_outputs_4_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3[31:0] ), //i + .io_outputs_4_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3[3:0] ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbClint system_clint_logic ( + .io_bus_cmd_valid (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i + .io_bus_cmd_ready (system_clint_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[15:0]), //i + .io_bus_cmd_payload_fragment_length (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_context (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[3:0] ), //i + .io_bus_rsp_valid (system_clint_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_bus_rsp_payload_last (system_clint_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_clint_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_clint_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_clint_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o + .io_timerInterrupt (system_clint_logic_io_timerInterrupt ), //o + .io_softwareInterrupt (system_clint_logic_io_softwareInterrupt ), //o + .io_time (system_clint_logic_io_time[63:0] ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbUartCtrl system_uart_0_io_logic ( + .io_bus_cmd_valid (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i + .io_bus_cmd_ready (system_uart_0_io_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[5:0]), //i + .io_bus_cmd_payload_fragment_length (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_context (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[3:0]), //i + .io_bus_rsp_valid (system_uart_0_io_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (_zz_io_bus_rsp_ready_1 ), //i + .io_bus_rsp_payload_last (system_uart_0_io_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_uart_0_io_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_uart_0_io_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o + .io_uart_txd (system_uart_0_io_logic_io_uart_txd ), //o + .io_uart_rxd (system_uart_0_io_rxd ), //i + .io_interrupt (system_uart_0_io_logic_io_interrupt ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbSpiXdrMasterCtrl system_spi_0_io_logic ( + .io_ctrl_cmd_valid (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i + .io_ctrl_cmd_ready (system_spi_0_io_logic_io_ctrl_cmd_ready ), //o + .io_ctrl_cmd_payload_last (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i + .io_ctrl_cmd_payload_fragment_opcode (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i + .io_ctrl_cmd_payload_fragment_address (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[11:0]), //i + .io_ctrl_cmd_payload_fragment_length (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i + .io_ctrl_cmd_payload_fragment_data (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i + .io_ctrl_cmd_payload_fragment_context (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[3:0] ), //i + .io_ctrl_rsp_valid (system_spi_0_io_logic_io_ctrl_rsp_valid ), //o + .io_ctrl_rsp_ready (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_ctrl_rsp_payload_last (system_spi_0_io_logic_io_ctrl_rsp_payload_last ), //o + .io_ctrl_rsp_payload_fragment_opcode (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode ), //o + .io_ctrl_rsp_payload_fragment_data (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data[31:0] ), //o + .io_ctrl_rsp_payload_fragment_context (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context[3:0] ), //o + .io_spi_sclk_write (system_spi_0_io_logic_io_spi_sclk_write ), //o + .io_spi_data_0_writeEnable (system_spi_0_io_logic_io_spi_data_0_writeEnable ), //o + .io_spi_data_0_read (system_spi_0_io_data_0_read ), //i + .io_spi_data_0_write (system_spi_0_io_logic_io_spi_data_0_write ), //o + .io_spi_data_1_writeEnable (system_spi_0_io_logic_io_spi_data_1_writeEnable ), //o + .io_spi_data_1_read (system_spi_0_io_data_1_read ), //i + .io_spi_data_1_write (system_spi_0_io_logic_io_spi_data_1_write ), //o + .io_spi_data_2_writeEnable (system_spi_0_io_logic_io_spi_data_2_writeEnable ), //o + .io_spi_data_2_read (system_spi_0_io_data_2_read ), //i + .io_spi_data_2_write (system_spi_0_io_logic_io_spi_data_2_write ), //o + .io_spi_data_3_writeEnable (system_spi_0_io_logic_io_spi_data_3_writeEnable ), //o + .io_spi_data_3_read (system_spi_0_io_data_3_read ), //i + .io_spi_data_3_write (system_spi_0_io_logic_io_spi_data_3_write ), //o + .io_spi_ss (system_spi_0_io_logic_io_spi_ss ), //o + .io_interrupt (system_spi_0_io_logic_io_interrupt ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbToApb3Bridge io_apbSlave_0_logic ( + .io_input_cmd_valid (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i + .io_input_cmd_ready (io_apbSlave_0_logic_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[15:0]), //i + .io_input_cmd_payload_fragment_length (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i + .io_input_cmd_payload_fragment_data (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_context (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[3:0] ), //i + .io_input_rsp_valid (io_apbSlave_0_logic_io_input_rsp_valid ), //o + .io_input_rsp_ready (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_input_rsp_payload_last (io_apbSlave_0_logic_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (io_apbSlave_0_logic_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (io_apbSlave_0_logic_io_input_rsp_payload_fragment_context[3:0] ), //o + .io_output_PADDR (io_apbSlave_0_logic_io_output_PADDR[15:0] ), //o + .io_output_PSEL (io_apbSlave_0_logic_io_output_PSEL ), //o + .io_output_PENABLE (io_apbSlave_0_logic_io_output_PENABLE ), //o + .io_output_PREADY (io_apbSlave_0_PREADY ), //i + .io_output_PWRITE (io_apbSlave_0_logic_io_output_PWRITE ), //o + .io_output_PWDATA (io_apbSlave_0_logic_io_output_PWDATA[31:0] ), //o + .io_output_PRDATA (io_apbSlave_0_PRDATA[31:0] ), //i + .io_output_PSLVERROR (io_apbSlave_0_PSLVERROR ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + initial begin + debugCd_logic_holdingLogic_resetCounter = 12'h0; + debugCd_logic_outputReset = 1'b1; + end + + always @(*) begin + debugCd_logic_inputResetTrigger = 1'b0; + if(debugCd_logic_inputResetAdapter_stuff_syncTrigger) begin + debugCd_logic_inputResetTrigger = 1'b1; + end + end + + always @(*) begin + debugCd_logic_outputResetUnbuffered = 1'b0; + if(when_ClockDomainGenerator_l77) begin + debugCd_logic_outputResetUnbuffered = 1'b1; + end + end + + assign when_ClockDomainGenerator_l77 = (debugCd_logic_holdingLogic_resetCounter != 12'hfff); + assign debugCd_logic_inputResetAdapter_stuff_syncTrigger = bufferCC_5_io_dataOut; + always @(*) begin + systemCd_logic_inputResetTrigger = 1'b0; + if(bufferCC_6_io_dataOut) begin + systemCd_logic_inputResetTrigger = 1'b1; + end + if(bufferCC_7_io_dataOut) begin + systemCd_logic_inputResetTrigger = 1'b1; + end + end + + always @(*) begin + systemCd_logic_outputResetUnbuffered = 1'b0; + if(when_ClockDomainGenerator_l77_1) begin + systemCd_logic_outputResetUnbuffered = 1'b1; + end + end + + assign when_ClockDomainGenerator_l77_1 = (systemCd_logic_holdingLogic_resetCounter != 6'h3f); + assign system_cores_0_iBus_cmd_valid = system_cores_0_logic_cpu_iBus_cmd_valid; + assign system_cores_0_iBus_cmd_payload_fragment_opcode = 1'b0; + assign system_cores_0_iBus_cmd_payload_fragment_address = system_cores_0_logic_cpu_iBus_cmd_payload_address; + assign system_cores_0_iBus_cmd_payload_fragment_length = 6'h3f; + assign system_cores_0_iBus_cmd_payload_last = 1'b1; + assign system_cores_0_logic_cpu_iBus_rsp_payload_error = (system_cores_0_iBus_rsp_payload_fragment_opcode == 1'b1); + assign system_cores_0_iBus_rsp_ready = 1'b1; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_valid = system_cores_0_logic_cpu_dBus_cmd_valid; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_last = system_cores_0_logic_cpu_dBus_cmd_payload_last; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_opcode = (system_cores_0_logic_cpu_dBus_cmd_payload_wr ? 1'b1 : 1'b0); + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_address = system_cores_0_logic_cpu_dBus_cmd_payload_address; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_data = system_cores_0_logic_cpu_dBus_cmd_payload_data; + always @(*) begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'bxxxxxx; + case(system_cores_0_logic_cpu_dBus_cmd_payload_size) + 3'b000 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h0; + end + 3'b001 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h01; + end + 3'b010 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h03; + end + 3'b011 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h07; + end + 3'b100 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h0f; + end + 3'b101 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h1f; + end + 3'b110 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h3f; + end + default : begin + end + endcase + end + + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_mask = system_cores_0_logic_cpu_dBus_cmd_payload_mask; + assign system_cores_0_logic_cpu_dBus_Bridge_withoutWriteBuffer_busCmdContext_isWrite = system_cores_0_logic_cpu_dBus_cmd_payload_wr; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_withoutWriteBuffer_busCmdContext_isWrite; + always @(*) begin + system_cores_0_logic_cpu_dBus_rsp_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_valid; + if(when_DataCache_l532) begin + system_cores_0_logic_cpu_dBus_rsp_valid = 1'b0; + end + end + + assign when_DataCache_l532 = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_context[0]; + assign system_cores_0_logic_cpu_dBus_rsp_payload_error = (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_opcode == 1'b1); + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_ready = 1'b1; + assign system_cores_0_iBus_cmd_combStage_valid = system_cores_0_iBus_cmd_valid; + assign system_cores_0_iBus_cmd_ready = system_cores_0_iBus_cmd_combStage_ready; + assign system_cores_0_iBus_cmd_combStage_payload_last = system_cores_0_iBus_cmd_payload_last; + assign system_cores_0_iBus_cmd_combStage_payload_fragment_opcode = system_cores_0_iBus_cmd_payload_fragment_opcode; + assign system_cores_0_iBus_cmd_combStage_payload_fragment_address = system_cores_0_iBus_cmd_payload_fragment_address; + assign system_cores_0_iBus_cmd_combStage_payload_fragment_length = system_cores_0_iBus_cmd_payload_fragment_length; + assign system_cores_0_iBus_cmd_combStage_ready = system_cores_0_iBus_connector_decoder_cmd_ready; + always @(*) begin + _zz_system_cores_0_iBus_connector_decoder_rsp_ready = system_cores_0_iBus_rsp_ready; + if(when_Stream_l368) begin + _zz_system_cores_0_iBus_connector_decoder_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! _zz_system_cores_0_iBus_rsp_valid); + assign _zz_system_cores_0_iBus_rsp_valid = _zz_system_cores_0_iBus_rsp_valid_1; + assign system_cores_0_iBus_rsp_valid = _zz_system_cores_0_iBus_rsp_valid; + assign system_cores_0_iBus_rsp_payload_last = _zz_system_cores_0_iBus_rsp_payload_last; + assign system_cores_0_iBus_rsp_payload_fragment_opcode = _zz_system_cores_0_iBus_rsp_payload_fragment_opcode; + assign system_cores_0_iBus_rsp_payload_fragment_data = _zz_system_cores_0_iBus_rsp_payload_fragment_data; + assign system_cores_0_iBus_connector_decoder_cmd_valid = system_cores_0_iBus_cmd_combStage_valid; + assign system_cores_0_iBus_connector_decoder_rsp_ready = _zz_system_cores_0_iBus_connector_decoder_rsp_ready; + assign system_cores_0_iBus_connector_decoder_cmd_payload_last = system_cores_0_iBus_cmd_combStage_payload_last; + assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_opcode = system_cores_0_iBus_cmd_combStage_payload_fragment_opcode; + assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_address = system_cores_0_iBus_cmd_combStage_payload_fragment_address; + assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_length = system_cores_0_iBus_cmd_combStage_payload_fragment_length; + always @(*) begin + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_ready; + if(when_Stream_l368_1) begin + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready = 1'b1; + end + end + + assign when_Stream_l368_1 = (! system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid); + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_last = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_last; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_opcode = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_opcode; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_address = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_address; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_length = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_length; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_data = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_data; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_mask = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_mask; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_context; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_ready = system_cores_0_dBus_connector_decoder_cmd_ready; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_valid = system_cores_0_dBus_connector_decoder_rsp_valid; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_last = system_cores_0_dBus_connector_decoder_rsp_payload_last; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_opcode = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_opcode; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_data = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_data; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_context = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_context; + assign system_cores_0_dBus_connector_decoder_cmd_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid; + assign system_cores_0_dBus_connector_decoder_rsp_ready = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_ready; + assign system_cores_0_dBus_connector_decoder_cmd_payload_last = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_last; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_opcode = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_opcode; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_address = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_address; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_length = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_length; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_data = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_data; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_mask = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_mask; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_context; + assign system_hardJtag_debug_logic_mmMaster_cmd_valid = system_hardJtag_debug_logic_debugger_io_mem_cmd_valid; + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_last = 1'b1; + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_length = 2'b11; + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_opcode = (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_wr ? 1'b1 : 1'b0); + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address = {_zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address,2'b00}; + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_data = system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_data; + always @(*) begin + case(system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_size) + 2'b00 : begin + _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b0001; + end + 2'b01 : begin + _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b0011; + end + default : begin + _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b1111; + end + endcase + end + + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask_1[3:0]; + assign system_hardJtag_debug_logic_mmMaster_rsp_ready = 1'b1; + assign jtagCtrl_tdo = system_hardJtag_debug_logic_jtagBridge_io_ctrl_tdo; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_valid = system_hardJtag_debug_logic_mmMaster_cmd_valid; + assign system_hardJtag_debug_logic_mmMaster_cmd_ready = system_hardJtag_debug_bmb_connector_decoder_cmd_ready; + assign system_hardJtag_debug_logic_mmMaster_rsp_valid = system_hardJtag_debug_bmb_connector_decoder_rsp_valid; + assign system_hardJtag_debug_bmb_connector_decoder_rsp_ready = system_hardJtag_debug_logic_mmMaster_rsp_ready; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_last = system_hardJtag_debug_logic_mmMaster_cmd_payload_last; + assign system_hardJtag_debug_logic_mmMaster_rsp_payload_last = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_last; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_opcode = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_opcode; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_address = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_length = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_length; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_data = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_data; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_mask = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask; + assign system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_opcode = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_opcode; + assign system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_data = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_data; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_ready = bmbDecoder_4_io_input_cmd_ready; + assign system_hardJtag_debug_bmb_connector_decoder_rsp_valid = bmbDecoder_4_io_input_rsp_valid; + assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_last = bmbDecoder_4_io_input_rsp_payload_last; + assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_opcode = bmbDecoder_4_io_input_rsp_payload_fragment_opcode; + assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_data = bmbDecoder_4_io_input_rsp_payload_fragment_data; + assign system_fabric_iBus_bmb_cmd_valid = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_iBus_bmb_cmd_ready; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_iBus_bmb_rsp_valid; + assign system_fabric_iBus_bmb_rsp_ready = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_fabric_iBus_bmb_cmd_payload_last = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_iBus_bmb_rsp_payload_last; + assign system_fabric_iBus_bmb_cmd_payload_fragment_opcode = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_fabric_iBus_bmb_cmd_payload_fragment_address = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_fabric_iBus_bmb_cmd_payload_fragment_length = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_rsp_payload_fragment_opcode; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_iBus_bmb_rsp_payload_fragment_data; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_cores_0_iBus_connector_decoder_cmd_valid; + assign system_cores_0_iBus_connector_decoder_cmd_ready = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_cores_0_iBus_connector_decoder_rsp_valid = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_cores_0_iBus_connector_decoder_rsp_ready; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_cores_0_iBus_connector_decoder_cmd_payload_last; + assign system_cores_0_iBus_connector_decoder_rsp_payload_last = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_opcode; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_address; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_length; + assign system_cores_0_iBus_connector_decoder_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_cores_0_iBus_connector_decoder_rsp_payload_fragment_data = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_valid = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid || system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_last = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_opcode = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_address = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_length = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_data = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_mask = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_mask : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_context = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context); + always @(*) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l368_2) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l368_2 = (! system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_last = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_last; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_opcode = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_opcode; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_address = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_address; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_length = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_length; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_data = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_data; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_mask = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_mask; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_context = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_context; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_ready = system_fabric_exclusiveMonitor_logic_io_input_cmd_ready; + always @(*) begin + _zz_io_input_rsp_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + if(when_Stream_l368_3) begin + _zz_io_input_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368_3 = (! _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid); + assign _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_cores_0_debugBmb_cmd_valid = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_cores_0_debugBmb_cmd_ready; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_cores_0_debugBmb_rsp_valid; + assign system_cores_0_debugBmb_rsp_ready = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_cores_0_debugBmb_cmd_payload_last = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_cores_0_debugBmb_rsp_payload_last; + assign system_cores_0_debugBmb_cmd_payload_fragment_opcode = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_cores_0_debugBmb_cmd_payload_fragment_address = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_cores_0_debugBmb_cmd_payload_fragment_length = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_cores_0_debugBmb_cmd_payload_fragment_data = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_cores_0_debugBmb_cmd_payload_fragment_mask = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_cores_0_debugBmb_rsp_payload_fragment_opcode; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_cores_0_debugBmb_rsp_payload_fragment_data; + assign system_cores_0_logic_cpu_debug_bus_cmd_payload_wr = (system_cores_0_debugBmb_cmd_payload_fragment_opcode == 1'b1); + assign system_cores_0_logic_cpu_debug_bus_cmd_fire = (system_cores_0_debugBmb_cmd_valid && system_cores_0_logic_cpu_debug_bus_cmd_ready); + assign system_cores_0_debugBmb_cmd_ready = system_cores_0_logic_cpu_debug_bus_cmd_ready; + assign system_cores_0_debugBmb_rsp_valid = system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext; + assign system_cores_0_debugBmb_rsp_payload_last = 1'b1; + assign system_cores_0_debugBmb_rsp_payload_fragment_opcode = 1'b0; + assign system_cores_0_debugBmb_rsp_payload_fragment_data = system_cores_0_logic_cpu_debug_bus_rsp_data; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbDecoder_4_io_outputs_0_cmd_valid; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbDecoder_4_io_outputs_0_rsp_ready; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbDecoder_4_io_outputs_0_cmd_payload_last; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_opcode; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_address[7:0]; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_length; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_data; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_mask; + assign system_fabric_dBusCoherent_bmb_cmd_valid = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_dBusCoherent_bmb_cmd_ready; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_dBusCoherent_bmb_rsp_valid; + assign system_fabric_dBusCoherent_bmb_rsp_ready = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_fabric_dBusCoherent_bmb_cmd_payload_last = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_dBusCoherent_bmb_rsp_payload_last; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_context; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_valid = system_fabric_dBusCoherent_bmb_cmd_valid; + assign system_fabric_dBusCoherent_bmb_cmd_ready = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_ready; + assign system_fabric_dBusCoherent_bmb_rsp_valid = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_valid; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_ready = system_fabric_dBusCoherent_bmb_rsp_ready; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_last = system_fabric_dBusCoherent_bmb_cmd_payload_last; + assign system_fabric_dBusCoherent_bmb_rsp_payload_last = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_last; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_address; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_length; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_mask; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_context; + assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_context; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_valid = system_fabric_exclusiveMonitor_logic_io_output_cmd_valid; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_ready = system_fabric_exclusiveMonitor_logic_io_output_rsp_ready; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_last = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_last; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_opcode = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_opcode; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_address = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_address; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_length = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_length; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_data = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_data; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_mask = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_mask; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_context = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_context; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_cores_0_dBus_connector_decoder_cmd_valid; + assign system_cores_0_dBus_connector_decoder_cmd_ready = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_cores_0_dBus_connector_decoder_rsp_valid = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_cores_0_dBus_connector_decoder_rsp_ready; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_cores_0_dBus_connector_decoder_cmd_payload_last; + assign system_cores_0_dBus_connector_decoder_rsp_payload_last = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_address; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_length; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_mask; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_context; + assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_valid; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_valid = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_ready; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_last; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_last = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_opcode; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_address; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_length; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_data; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_mask; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_context; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_opcode = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_data = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_context = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_fabric_dBus_bmb_cmd_valid = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_dBus_bmb_cmd_ready; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_dBus_bmb_rsp_valid; + assign system_fabric_dBus_bmb_rsp_ready = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_fabric_dBus_bmb_cmd_payload_last = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_dBus_bmb_rsp_payload_last; + assign system_fabric_dBus_bmb_cmd_payload_fragment_opcode = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_fabric_dBus_bmb_cmd_payload_fragment_address = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_fabric_dBus_bmb_cmd_payload_fragment_length = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_fabric_dBus_bmb_cmd_payload_fragment_data = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_fabric_dBus_bmb_cmd_payload_fragment_mask = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign system_fabric_dBus_bmb_cmd_payload_fragment_context = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_dBus_bmb_rsp_payload_fragment_opcode; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_dBus_bmb_rsp_payload_fragment_data; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_fabric_dBus_bmb_rsp_payload_fragment_context; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_valid; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_ready = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_valid = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_fabric_exclusiveMonitor_output_connector_decoder_rsp_ready; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_last; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_last = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_opcode; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_address; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_length; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_data; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_mask; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_context; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_opcode = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_data = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_context = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + always @(*) begin + system_fabric_iBus_bmb_cmd_ready = system_fabric_iBus_bmb_cmd_m2sPipe_ready; + if(when_Stream_l368_4) begin + system_fabric_iBus_bmb_cmd_ready = 1'b1; + end + end + + assign when_Stream_l368_4 = (! system_fabric_iBus_bmb_cmd_m2sPipe_valid); + assign system_fabric_iBus_bmb_cmd_m2sPipe_valid = system_fabric_iBus_bmb_cmd_rValid; + assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_last = system_fabric_iBus_bmb_cmd_rData_last; + assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_opcode = system_fabric_iBus_bmb_cmd_rData_fragment_opcode; + assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_address = system_fabric_iBus_bmb_cmd_rData_fragment_address; + assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_length = system_fabric_iBus_bmb_cmd_rData_fragment_length; + assign system_fabric_iBus_bmb_cmd_m2sPipe_ready = system_fabric_iBus_bmb_decoder_io_input_cmd_ready; + assign system_fabric_iBus_bmb_rsp_valid = system_fabric_iBus_bmb_decoder_io_input_rsp_valid; + assign system_fabric_iBus_bmb_rsp_payload_last = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_last; + assign system_fabric_iBus_bmb_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_opcode; + assign system_fabric_iBus_bmb_rsp_payload_fragment_data = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_data; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid = system_fabric_dBus_bmb_cmd_valid; + assign system_fabric_dBus_bmb_cmd_ready = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready; + assign system_fabric_dBus_bmb_rsp_valid = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready = system_fabric_dBus_bmb_rsp_ready; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last = system_fabric_dBus_bmb_cmd_payload_last; + assign system_fabric_dBus_bmb_rsp_payload_last = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode = system_fabric_dBus_bmb_cmd_payload_fragment_opcode; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address = system_fabric_dBus_bmb_cmd_payload_fragment_address; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length = system_fabric_dBus_bmb_cmd_payload_fragment_length; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data = system_fabric_dBus_bmb_cmd_payload_fragment_data; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask = system_fabric_dBus_bmb_cmd_payload_fragment_mask; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context = system_fabric_dBus_bmb_cmd_payload_fragment_context; + assign system_fabric_dBus_bmb_rsp_payload_fragment_opcode = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode; + assign system_fabric_dBus_bmb_rsp_payload_fragment_data = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data; + assign system_fabric_dBus_bmb_rsp_payload_fragment_context = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context; + assign system_bridge_bmb_cmd_valid = system_bridge_bmb_arbiter_io_output_cmd_valid; + assign system_bridge_bmb_rsp_ready = system_bridge_bmb_arbiter_io_output_rsp_ready; + assign system_bridge_bmb_cmd_payload_last = system_bridge_bmb_arbiter_io_output_cmd_payload_last; + assign system_bridge_bmb_cmd_payload_fragment_source = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_source; + assign system_bridge_bmb_cmd_payload_fragment_opcode = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_opcode; + assign system_bridge_bmb_cmd_payload_fragment_address = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_address; + assign system_bridge_bmb_cmd_payload_fragment_length = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_length; + assign system_bridge_bmb_cmd_payload_fragment_data = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_data; + assign system_bridge_bmb_cmd_payload_fragment_mask = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_mask; + assign system_bridge_bmb_cmd_payload_fragment_context = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_context; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready = system_bridge_bmb_arbiter_io_inputs_0_cmd_ready; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid = system_bridge_bmb_arbiter_io_inputs_0_rsp_valid; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_last; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_opcode; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_data; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_context; + assign system_bridge_bmb_cmd_ready = (! system_bridge_bmb_cmd_rValid); + assign system_bridge_bmb_cmd_s2mPipe_valid = (system_bridge_bmb_cmd_valid || system_bridge_bmb_cmd_rValid); + assign system_bridge_bmb_cmd_s2mPipe_payload_last = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_last : system_bridge_bmb_cmd_payload_last); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_source = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_source : system_bridge_bmb_cmd_payload_fragment_source); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_opcode = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_opcode : system_bridge_bmb_cmd_payload_fragment_opcode); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_address = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_address : system_bridge_bmb_cmd_payload_fragment_address); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_length = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_length : system_bridge_bmb_cmd_payload_fragment_length); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_data = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_data : system_bridge_bmb_cmd_payload_fragment_data); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_mask = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_mask : system_bridge_bmb_cmd_payload_fragment_mask); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_context = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_context : system_bridge_bmb_cmd_payload_fragment_context); + always @(*) begin + system_bridge_bmb_cmd_s2mPipe_ready = system_bridge_bmb_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l368_5) begin + system_bridge_bmb_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l368_5 = (! system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid); + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid = system_bridge_bmb_cmd_s2mPipe_rValid; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_last = system_bridge_bmb_cmd_s2mPipe_rData_last; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_source = system_bridge_bmb_cmd_s2mPipe_rData_fragment_source; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_opcode = system_bridge_bmb_cmd_s2mPipe_rData_fragment_opcode; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_address = system_bridge_bmb_cmd_s2mPipe_rData_fragment_address; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_length = system_bridge_bmb_cmd_s2mPipe_rData_fragment_length; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_data = system_bridge_bmb_cmd_s2mPipe_rData_fragment_data; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_mask = system_bridge_bmb_cmd_s2mPipe_rData_fragment_mask; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_context = system_bridge_bmb_cmd_s2mPipe_rData_fragment_context; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_ready = system_bridge_bmb_decoder_io_input_cmd_ready; + assign system_bridge_bmb_rsp_valid = system_bridge_bmb_decoder_io_input_rsp_valid; + assign system_bridge_bmb_rsp_payload_last = system_bridge_bmb_decoder_io_input_rsp_payload_last; + assign system_bridge_bmb_rsp_payload_fragment_source = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_source; + assign system_bridge_bmb_rsp_payload_fragment_opcode = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_opcode; + assign system_bridge_bmb_rsp_payload_fragment_data = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_data; + assign system_bridge_bmb_rsp_payload_fragment_context = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_cmd_valid = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_bmbPeripheral_bmb_cmd_ready; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_bmbPeripheral_bmb_rsp_valid; + assign system_bmbPeripheral_bmb_rsp_ready = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_bmbPeripheral_bmb_cmd_payload_last = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_bmbPeripheral_bmb_rsp_payload_last; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_address = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_length = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_data = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_mask = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_context = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_bmbPeripheral_bmb_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_bmbPeripheral_bmb_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bridge_bmb_unburstify_io_output_cmd_valid; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bridge_bmb_unburstify_io_output_rsp_ready; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bridge_bmb_unburstify_io_output_cmd_payload_last; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_address[23:0]; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_mask; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_context; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_valid = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_ready; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_last = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_opcode = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_address = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_length = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_data = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_mask = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_context = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_ready = system_ramA_logic_io_bus_cmd_ready; + always @(*) begin + _zz_io_bus_rsp_ready = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + if(when_Stream_l368_6) begin + _zz_io_bus_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368_6 = (! _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid); + assign _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bridge_bmb_unburstify_1_io_output_cmd_valid; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bridge_bmb_unburstify_1_io_output_rsp_ready; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bridge_bmb_unburstify_1_io_output_cmd_payload_last; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_opcode; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_address[14:0]; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_length; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_data; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_mask; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_context; + assign system_bmbPeripheral_bmb_cmd_combStage_valid = system_bmbPeripheral_bmb_cmd_valid; + assign system_bmbPeripheral_bmb_cmd_ready = system_bmbPeripheral_bmb_cmd_combStage_ready; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_last = system_bmbPeripheral_bmb_cmd_payload_last; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_opcode = system_bmbPeripheral_bmb_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_address = system_bmbPeripheral_bmb_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_length = system_bmbPeripheral_bmb_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_data = system_bmbPeripheral_bmb_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_mask = system_bmbPeripheral_bmb_cmd_payload_fragment_mask; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_context = system_bmbPeripheral_bmb_cmd_payload_fragment_context; + assign system_bmbPeripheral_bmb_cmd_combStage_ready = system_bmbPeripheral_bmb_decoder_io_input_cmd_ready; + assign _zz_io_input_rsp_ready_1 = (! _zz_system_bmbPeripheral_bmb_rsp_valid_1); + assign _zz_system_bmbPeripheral_bmb_rsp_valid = _zz_system_bmbPeripheral_bmb_rsp_valid_1; + assign system_bmbPeripheral_bmb_rsp_valid = _zz_system_bmbPeripheral_bmb_rsp_valid; + assign system_bmbPeripheral_bmb_rsp_payload_last = _zz_system_bmbPeripheral_bmb_rsp_payload_last; + assign system_bmbPeripheral_bmb_rsp_payload_fragment_opcode = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_rsp_payload_fragment_data = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_rsp_payload_fragment_context = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_context; + assign system_uart_0_io_txd = system_uart_0_io_logic_io_uart_txd; + assign io_apbSlave_0_PADDR = io_apbSlave_0_logic_io_output_PADDR; + assign io_apbSlave_0_PSEL = io_apbSlave_0_logic_io_output_PSEL; + assign io_apbSlave_0_PENABLE = io_apbSlave_0_logic_io_output_PENABLE; + assign io_apbSlave_0_PWRITE = io_apbSlave_0_logic_io_output_PWRITE; + assign io_apbSlave_0_PWDATA = io_apbSlave_0_logic_io_output_PWDATA; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_clint_logic_io_bus_cmd_ready; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_clint_logic_io_bus_rsp_valid; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_clint_logic_io_bus_rsp_payload_last; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_clint_logic_io_bus_rsp_payload_fragment_opcode; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_clint_logic_io_bus_rsp_payload_fragment_data; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_clint_logic_io_bus_rsp_payload_fragment_context; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_uart_0_io_logic_io_bus_cmd_ready; + assign _zz_io_bus_rsp_ready_1 = (! _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1); + assign _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign when_PlicGateway_l21 = (! system_uart_0_io_interrupt_plic_gateway_waitCompletion); + assign when_PlicGateway_l21_1 = (! system_spi_0_io_interrupt_plic_gateway_waitCompletion); + assign system_spi_0_io_sclk_write = system_spi_0_io_logic_io_spi_sclk_write; + assign system_spi_0_io_data_0_writeEnable = system_spi_0_io_logic_io_spi_data_0_writeEnable; + assign system_spi_0_io_data_0_write = system_spi_0_io_logic_io_spi_data_0_write; + assign system_spi_0_io_data_1_writeEnable = system_spi_0_io_logic_io_spi_data_1_writeEnable; + assign system_spi_0_io_data_1_write = system_spi_0_io_logic_io_spi_data_1_write; + assign system_spi_0_io_data_2_writeEnable = system_spi_0_io_logic_io_spi_data_2_writeEnable; + assign system_spi_0_io_data_2_write = system_spi_0_io_logic_io_spi_data_2_write; + assign system_spi_0_io_data_3_writeEnable = system_spi_0_io_logic_io_spi_data_3_writeEnable; + assign system_spi_0_io_data_3_write = system_spi_0_io_logic_io_spi_data_3_write; + assign system_spi_0_io_ss = system_spi_0_io_logic_io_spi_ss; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_spi_0_io_logic_io_ctrl_cmd_ready; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_spi_0_io_logic_io_ctrl_rsp_valid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_spi_0_io_logic_io_ctrl_rsp_payload_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = io_apbSlave_0_logic_io_input_cmd_ready; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = io_apbSlave_0_logic_io_input_rsp_valid; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = io_apbSlave_0_logic_io_input_rsp_payload_last; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = io_apbSlave_0_logic_io_input_rsp_payload_fragment_data; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = io_apbSlave_0_logic_io_input_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_withoutMask_cmd_valid = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_rsp_ready = system_bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_cmd_ready = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_bmbPeripheral_bmb_withoutMask_rsp_valid = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address[15:0]; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_1; + assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_1; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1[5:0]; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + always @(*) begin + system_plic_logic_bus_readHaltTrigger = 1'b0; + if(when_PlicMapper_l122) begin + system_plic_logic_bus_readHaltTrigger = 1'b1; + end + end + + assign system_plic_logic_bus_writeHaltTrigger = 1'b0; + assign _zz_system_plic_logic_bmb_rsp_valid = (! (system_plic_logic_bus_readHaltTrigger || system_plic_logic_bus_writeHaltTrigger)); + assign system_plic_logic_bus_rsp_ready = (_zz_system_plic_logic_bus_rsp_ready && _zz_system_plic_logic_bmb_rsp_valid); + always @(*) begin + _zz_system_plic_logic_bus_rsp_ready = system_plic_logic_bmb_rsp_ready; + if(when_Stream_l368_7) begin + _zz_system_plic_logic_bus_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368_7 = (! _zz_system_plic_logic_bmb_rsp_valid_1); + assign _zz_system_plic_logic_bmb_rsp_valid_1 = _zz_system_plic_logic_bmb_rsp_valid_2; + assign system_plic_logic_bmb_rsp_valid = _zz_system_plic_logic_bmb_rsp_valid_1; + assign system_plic_logic_bmb_rsp_payload_last = _zz_system_plic_logic_bmb_rsp_payload_last; + assign system_plic_logic_bmb_rsp_payload_fragment_opcode = _zz_system_plic_logic_bmb_rsp_payload_fragment_opcode; + assign system_plic_logic_bmb_rsp_payload_fragment_data = _zz_system_plic_logic_bmb_rsp_payload_fragment_data; + assign system_plic_logic_bmb_rsp_payload_fragment_context = _zz_system_plic_logic_bmb_rsp_payload_fragment_context; + assign system_plic_logic_bus_askWrite = (system_plic_logic_bmb_cmd_valid && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b1)); + assign system_plic_logic_bus_askRead = (system_plic_logic_bmb_cmd_valid && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b0)); + assign system_plic_logic_bmb_cmd_fire = (system_plic_logic_bmb_cmd_valid && system_plic_logic_bmb_cmd_ready); + assign system_plic_logic_bus_doWrite = (system_plic_logic_bmb_cmd_fire && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b1)); + assign system_plic_logic_bmb_cmd_fire_1 = (system_plic_logic_bmb_cmd_valid && system_plic_logic_bmb_cmd_ready); + assign system_plic_logic_bus_doRead = (system_plic_logic_bmb_cmd_fire_1 && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b0)); + assign system_plic_logic_bus_rsp_valid = system_plic_logic_bmb_cmd_valid; + assign system_plic_logic_bmb_cmd_ready = system_plic_logic_bus_rsp_ready; + assign system_plic_logic_bus_rsp_payload_last = 1'b1; + assign system_plic_logic_bus_rsp_payload_fragment_opcode = 1'b0; + always @(*) begin + system_plic_logic_bus_rsp_payload_fragment_data = 32'h0; + case(system_plic_logic_bmb_cmd_payload_fragment_address) + 22'h000004 : begin + system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_uart_0_io_interrupt_plic_gateway_priority; + end + 22'h001000 : begin + system_plic_logic_bus_rsp_payload_fragment_data[1 : 1] = system_uart_0_io_interrupt_plic_gateway_ip; + system_plic_logic_bus_rsp_payload_fragment_data[4 : 4] = system_spi_0_io_interrupt_plic_gateway_ip; + end + 22'h000010 : begin + system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_spi_0_io_interrupt_plic_gateway_priority; + end + 22'h200000 : begin + system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_cores_0_externalInterrupt_plic_target_threshold; + end + 22'h200004 : begin + system_plic_logic_bus_rsp_payload_fragment_data[2 : 0] = system_cores_0_externalInterrupt_plic_target_claim; + end + 22'h002000 : begin + system_plic_logic_bus_rsp_payload_fragment_data[1 : 1] = system_cores_0_externalInterrupt_plic_target_ie_0; + system_plic_logic_bus_rsp_payload_fragment_data[4 : 4] = system_cores_0_externalInterrupt_plic_target_ie_1; + end + default : begin + end + endcase + end + + assign system_plic_logic_bus_rsp_payload_fragment_context = system_plic_logic_bmb_cmd_payload_fragment_context; + assign system_cores_0_externalInterrupt_plic_target_requests_0_priority = 2'b00; + assign system_cores_0_externalInterrupt_plic_target_requests_0_id = 3'b000; + assign system_cores_0_externalInterrupt_plic_target_requests_0_valid = 1'b1; + assign system_cores_0_externalInterrupt_plic_target_requests_1_priority = system_uart_0_io_interrupt_plic_gateway_priority; + assign system_cores_0_externalInterrupt_plic_target_requests_1_id = 3'b001; + assign system_cores_0_externalInterrupt_plic_target_requests_1_valid = (system_uart_0_io_interrupt_plic_gateway_ip && system_cores_0_externalInterrupt_plic_target_ie_0); + assign system_cores_0_externalInterrupt_plic_target_requests_2_priority = system_spi_0_io_interrupt_plic_gateway_priority; + assign system_cores_0_externalInterrupt_plic_target_requests_2_id = 3'b100; + assign system_cores_0_externalInterrupt_plic_target_requests_2_valid = (system_spi_0_io_interrupt_plic_gateway_ip && system_cores_0_externalInterrupt_plic_target_ie_1); + assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority = ((! system_cores_0_externalInterrupt_plic_target_requests_1_valid) || (system_cores_0_externalInterrupt_plic_target_requests_0_valid && (system_cores_0_externalInterrupt_plic_target_requests_1_priority <= system_cores_0_externalInterrupt_plic_target_requests_0_priority))); + assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1 = (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_priority : system_cores_0_externalInterrupt_plic_target_requests_1_priority); + assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 = (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_valid : system_cores_0_externalInterrupt_plic_target_requests_1_valid); + assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 = ((! system_cores_0_externalInterrupt_plic_target_requests_2_valid) || (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 && (system_cores_0_externalInterrupt_plic_target_requests_2_priority <= _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1))); + assign system_cores_0_externalInterrupt_plic_target_iep = (system_cores_0_externalInterrupt_plic_target_threshold < system_cores_0_externalInterrupt_plic_target_bestRequest_priority); + assign system_cores_0_externalInterrupt_plic_target_claim = (system_cores_0_externalInterrupt_plic_target_iep ? system_cores_0_externalInterrupt_plic_target_bestRequest_id : 3'b000); + assign system_uart_0_io_interrupt_plic_gateway_priority = _zz_system_uart_0_io_interrupt_plic_gateway_priority; + assign system_spi_0_io_interrupt_plic_gateway_priority = _zz_system_spi_0_io_interrupt_plic_gateway_priority; + always @(*) begin + system_plic_logic_bridge_claim_valid = 1'b0; + case(system_plic_logic_bmb_cmd_payload_fragment_address) + 22'h200004 : begin + if(system_plic_logic_bus_doRead) begin + system_plic_logic_bridge_claim_valid = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + system_plic_logic_bridge_claim_payload = 3'bxxx; + case(system_plic_logic_bmb_cmd_payload_fragment_address) + 22'h200004 : begin + if(system_plic_logic_bus_doRead) begin + system_plic_logic_bridge_claim_payload = system_cores_0_externalInterrupt_plic_target_claim; + end + end + default : begin + end + endcase + end + + always @(*) begin + system_plic_logic_bridge_completion_valid = 1'b0; + if(system_plic_logic_bridge_targetMapping_0_targetCompletion_valid) begin + system_plic_logic_bridge_completion_valid = 1'b1; + end + end + + always @(*) begin + system_plic_logic_bridge_completion_payload = 3'bxxx; + if(system_plic_logic_bridge_targetMapping_0_targetCompletion_valid) begin + system_plic_logic_bridge_completion_payload = system_plic_logic_bridge_targetMapping_0_targetCompletion_payload; + end + end + + always @(*) begin + system_plic_logic_bridge_coherencyStall_willIncrement = 1'b0; + if(when_PlicMapper_l122) begin + system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; + end + if(when_BmbSlaveFactory_l71) begin + if(system_plic_logic_bus_askWrite) begin + system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; + end + if(system_plic_logic_bus_askRead) begin + system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; + end + end + end + + assign system_plic_logic_bridge_coherencyStall_willClear = 1'b0; + assign system_plic_logic_bridge_coherencyStall_willOverflowIfInc = (system_plic_logic_bridge_coherencyStall_value == 1'b1); + assign system_plic_logic_bridge_coherencyStall_willOverflow = (system_plic_logic_bridge_coherencyStall_willOverflowIfInc && system_plic_logic_bridge_coherencyStall_willIncrement); + always @(*) begin + system_plic_logic_bridge_coherencyStall_valueNext = (system_plic_logic_bridge_coherencyStall_value + system_plic_logic_bridge_coherencyStall_willIncrement); + if(system_plic_logic_bridge_coherencyStall_willClear) begin + system_plic_logic_bridge_coherencyStall_valueNext = 1'b0; + end + end + + assign when_PlicMapper_l122 = (system_plic_logic_bridge_coherencyStall_value != 1'b0); + assign system_cores_0_externalInterrupt_plic_target_threshold = _zz_system_cores_0_externalInterrupt_plic_target_threshold; + always @(*) begin + system_plic_logic_bridge_targetMapping_0_targetCompletion_valid = 1'b0; + case(system_plic_logic_bmb_cmd_payload_fragment_address) + 22'h200004 : begin + if(system_plic_logic_bus_doWrite) begin + system_plic_logic_bridge_targetMapping_0_targetCompletion_valid = 1'b1; + end + end + default : begin + end + endcase + end + + assign system_cores_0_externalInterrupt_plic_target_ie_0 = _zz_system_cores_0_externalInterrupt_plic_target_ie_0; + assign system_cores_0_externalInterrupt_plic_target_ie_1 = _zz_system_cores_0_externalInterrupt_plic_target_ie_1; + assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_2; + assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_2; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_2; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2[11:0]; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_3; + assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_3; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_3; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3[15:0]; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_plic_logic_bmb_cmd_valid = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_plic_logic_bmb_cmd_ready; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_plic_logic_bmb_rsp_valid; + assign system_plic_logic_bmb_rsp_ready = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_plic_logic_bmb_cmd_payload_last = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_plic_logic_bmb_rsp_payload_last; + assign system_plic_logic_bmb_cmd_payload_fragment_opcode = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_plic_logic_bmb_cmd_payload_fragment_address = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_plic_logic_bmb_cmd_payload_fragment_length = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_plic_logic_bmb_cmd_payload_fragment_data = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_plic_logic_bmb_cmd_payload_fragment_context = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_plic_logic_bmb_rsp_payload_fragment_opcode; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_plic_logic_bmb_rsp_payload_fragment_data; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_plic_logic_bmb_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_4; + assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_4; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_4; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4[21:0]; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_plic_logic_bridge_targetMapping_0_targetCompletion_payload = system_plic_logic_bmb_cmd_payload_fragment_data[2 : 0]; + assign when_BmbSlaveFactory_l71 = 1'b1; + always @(posedge io_systemClk) begin + if(when_ClockDomainGenerator_l77) begin + debugCd_logic_holdingLogic_resetCounter <= (debugCd_logic_holdingLogic_resetCounter + 12'h001); + end + if(debugCd_logic_inputResetTrigger) begin + debugCd_logic_holdingLogic_resetCounter <= 12'h0; + end + debugCd_logic_outputReset <= debugCd_logic_outputResetUnbuffered; + end + + always @(posedge io_systemClk) begin + if(when_ClockDomainGenerator_l77_1) begin + systemCd_logic_holdingLogic_resetCounter <= (systemCd_logic_holdingLogic_resetCounter + 6'h01); + end + if(systemCd_logic_inputResetTrigger) begin + systemCd_logic_holdingLogic_resetCounter <= 6'h0; + end + systemCd_logic_outputReset <= systemCd_logic_outputResetUnbuffered; + end + + always @(posedge io_systemClk) begin + io_systemReset <= systemCd_logic_outputReset; + if(_zz_system_cores_0_iBus_connector_decoder_rsp_ready) begin + _zz_system_cores_0_iBus_rsp_payload_last <= system_cores_0_iBus_connector_decoder_rsp_payload_last; + _zz_system_cores_0_iBus_rsp_payload_fragment_opcode <= system_cores_0_iBus_connector_decoder_rsp_payload_fragment_opcode; + _zz_system_cores_0_iBus_rsp_payload_fragment_data <= system_cores_0_iBus_connector_decoder_rsp_payload_fragment_data; + end + if(system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready) begin + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_last <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_last; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_opcode <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_opcode; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_address <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_address; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_length <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_data <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_data; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_mask <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_mask; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_context <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_context; + end + if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_mask <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_last <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_last; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_opcode <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_opcode; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_address <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_address; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_length <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_length; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_data <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_data; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_mask <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_mask; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_context <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_context; + end + if(_zz_io_input_rsp_ready) begin + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_last; + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_opcode; + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_data; + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_context; + end + if(system_fabric_iBus_bmb_cmd_ready) begin + system_fabric_iBus_bmb_cmd_rData_last <= system_fabric_iBus_bmb_cmd_payload_last; + system_fabric_iBus_bmb_cmd_rData_fragment_opcode <= system_fabric_iBus_bmb_cmd_payload_fragment_opcode; + system_fabric_iBus_bmb_cmd_rData_fragment_address <= system_fabric_iBus_bmb_cmd_payload_fragment_address; + system_fabric_iBus_bmb_cmd_rData_fragment_length <= system_fabric_iBus_bmb_cmd_payload_fragment_length; + end + if(system_bridge_bmb_cmd_ready) begin + system_bridge_bmb_cmd_rData_last <= system_bridge_bmb_cmd_payload_last; + system_bridge_bmb_cmd_rData_fragment_source <= system_bridge_bmb_cmd_payload_fragment_source; + system_bridge_bmb_cmd_rData_fragment_opcode <= system_bridge_bmb_cmd_payload_fragment_opcode; + system_bridge_bmb_cmd_rData_fragment_address <= system_bridge_bmb_cmd_payload_fragment_address; + system_bridge_bmb_cmd_rData_fragment_length <= system_bridge_bmb_cmd_payload_fragment_length; + system_bridge_bmb_cmd_rData_fragment_data <= system_bridge_bmb_cmd_payload_fragment_data; + system_bridge_bmb_cmd_rData_fragment_mask <= system_bridge_bmb_cmd_payload_fragment_mask; + system_bridge_bmb_cmd_rData_fragment_context <= system_bridge_bmb_cmd_payload_fragment_context; + end + if(system_bridge_bmb_cmd_s2mPipe_ready) begin + system_bridge_bmb_cmd_s2mPipe_rData_last <= system_bridge_bmb_cmd_s2mPipe_payload_last; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_source <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_source; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_opcode <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_opcode; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_address <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_address; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_length <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_length; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_data <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_data; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_mask <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_mask; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_context <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_context; + end + if(_zz_io_bus_rsp_ready) begin + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_ramA_logic_io_bus_rsp_payload_last; + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_ramA_logic_io_bus_rsp_payload_fragment_opcode; + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_ramA_logic_io_bus_rsp_payload_fragment_data; + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_ramA_logic_io_bus_rsp_payload_fragment_context; + end + if(_zz_io_input_rsp_ready_1) begin + _zz_system_bmbPeripheral_bmb_rsp_payload_last <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_last; + _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_opcode <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode; + _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_data <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data; + _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_context <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context; + end + _zz_timerInterrupt <= system_clint_logic_io_timerInterrupt[0]; + _zz_softwareInterrupt <= system_clint_logic_io_softwareInterrupt[0]; + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + if(_zz_io_bus_rsp_ready_1) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_uart_0_io_logic_io_bus_rsp_payload_last; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_data; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_context; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + if(_zz_system_plic_logic_bus_rsp_ready) begin + _zz_system_plic_logic_bmb_rsp_payload_last <= system_plic_logic_bus_rsp_payload_last; + _zz_system_plic_logic_bmb_rsp_payload_fragment_opcode <= system_plic_logic_bus_rsp_payload_fragment_opcode; + _zz_system_plic_logic_bmb_rsp_payload_fragment_data <= system_plic_logic_bus_rsp_payload_fragment_data; + _zz_system_plic_logic_bmb_rsp_payload_fragment_context <= system_plic_logic_bus_rsp_payload_fragment_context; + end + system_cores_0_externalInterrupt_plic_target_bestRequest_priority <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1 : system_cores_0_externalInterrupt_plic_target_requests_2_priority); + system_cores_0_externalInterrupt_plic_target_bestRequest_id <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_id : system_cores_0_externalInterrupt_plic_target_requests_1_id) : system_cores_0_externalInterrupt_plic_target_requests_2_id); + system_cores_0_externalInterrupt_plic_target_bestRequest_valid <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 : system_cores_0_externalInterrupt_plic_target_requests_2_valid); + system_cores_0_externalInterrupt_plic_target_iep_regNext <= system_cores_0_externalInterrupt_plic_target_iep; + end + + always @(posedge io_systemClk) begin + system_cores_0_debugReset <= system_cores_0_logic_cpu_debug_resetOut; + end + + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + _zz_system_cores_0_iBus_rsp_valid_1 <= 1'b0; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid <= 1'b0; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid <= 1'b0; + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + system_fabric_iBus_bmb_cmd_rValid <= 1'b0; + system_bridge_bmb_cmd_rValid <= 1'b0; + system_bridge_bmb_cmd_s2mPipe_rValid <= 1'b0; + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b0; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + system_uart_0_io_interrupt_plic_gateway_ip <= 1'b0; + system_uart_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; + system_spi_0_io_interrupt_plic_gateway_ip <= 1'b0; + system_spi_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + _zz_system_plic_logic_bmb_rsp_valid_2 <= 1'b0; + _zz_system_uart_0_io_interrupt_plic_gateway_priority <= 2'b00; + _zz_system_spi_0_io_interrupt_plic_gateway_priority <= 2'b00; + system_plic_logic_bridge_coherencyStall_value <= 1'b0; + _zz_system_cores_0_externalInterrupt_plic_target_threshold <= 2'b00; + _zz_system_cores_0_externalInterrupt_plic_target_ie_0 <= 1'b0; + _zz_system_cores_0_externalInterrupt_plic_target_ie_1 <= 1'b0; + end else begin + if(_zz_system_cores_0_iBus_connector_decoder_rsp_ready) begin + _zz_system_cores_0_iBus_rsp_valid_1 <= system_cores_0_iBus_connector_decoder_rsp_valid; + end + if(system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready) begin + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_valid; + end + if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_valid; + end + if(_zz_io_input_rsp_ready) begin + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= system_fabric_exclusiveMonitor_logic_io_input_rsp_valid; + end + if(system_fabric_iBus_bmb_cmd_ready) begin + system_fabric_iBus_bmb_cmd_rValid <= system_fabric_iBus_bmb_cmd_valid; + end + if(system_bridge_bmb_cmd_valid) begin + system_bridge_bmb_cmd_rValid <= 1'b1; + end + if(system_bridge_bmb_cmd_s2mPipe_ready) begin + system_bridge_bmb_cmd_rValid <= 1'b0; + end + if(system_bridge_bmb_cmd_s2mPipe_ready) begin + system_bridge_bmb_cmd_s2mPipe_rValid <= system_bridge_bmb_cmd_s2mPipe_valid; + end + if(_zz_io_bus_rsp_ready) begin + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= system_ramA_logic_io_bus_rsp_valid; + end + if(system_bmbPeripheral_bmb_decoder_io_input_rsp_valid) begin + _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b1; + end + if((_zz_system_bmbPeripheral_bmb_rsp_valid && system_bmbPeripheral_bmb_rsp_ready)) begin + _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b0; + end + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + if(system_uart_0_io_logic_io_bus_rsp_valid) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b1; + end + if((_zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready)) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + end + if(when_PlicGateway_l21) begin + system_uart_0_io_interrupt_plic_gateway_ip <= system_uart_0_io_logic_io_interrupt; + system_uart_0_io_interrupt_plic_gateway_waitCompletion <= system_uart_0_io_logic_io_interrupt; + end + if(when_PlicGateway_l21_1) begin + system_spi_0_io_interrupt_plic_gateway_ip <= system_spi_0_io_logic_io_interrupt; + system_spi_0_io_interrupt_plic_gateway_waitCompletion <= system_spi_0_io_logic_io_interrupt; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + if(_zz_system_plic_logic_bus_rsp_ready) begin + _zz_system_plic_logic_bmb_rsp_valid_2 <= (system_plic_logic_bus_rsp_valid && _zz_system_plic_logic_bmb_rsp_valid); + end + if(system_plic_logic_bridge_claim_valid) begin + case(system_plic_logic_bridge_claim_payload) + 3'b001 : begin + system_uart_0_io_interrupt_plic_gateway_ip <= 1'b0; + end + 3'b100 : begin + system_spi_0_io_interrupt_plic_gateway_ip <= 1'b0; + end + default : begin + end + endcase + end + if(system_plic_logic_bridge_completion_valid) begin + case(system_plic_logic_bridge_completion_payload) + 3'b001 : begin + system_uart_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; + end + 3'b100 : begin + system_spi_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; + end + default : begin + end + endcase + end + system_plic_logic_bridge_coherencyStall_value <= system_plic_logic_bridge_coherencyStall_valueNext; + case(system_plic_logic_bmb_cmd_payload_fragment_address) + 22'h000004 : begin + if(system_plic_logic_bus_doWrite) begin + _zz_system_uart_0_io_interrupt_plic_gateway_priority <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; + end + end + 22'h000010 : begin + if(system_plic_logic_bus_doWrite) begin + _zz_system_spi_0_io_interrupt_plic_gateway_priority <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; + end + end + 22'h200000 : begin + if(system_plic_logic_bus_doWrite) begin + _zz_system_cores_0_externalInterrupt_plic_target_threshold <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; + end + end + 22'h002000 : begin + if(system_plic_logic_bus_doWrite) begin + _zz_system_cores_0_externalInterrupt_plic_target_ie_0 <= system_plic_logic_bmb_cmd_payload_fragment_data[1]; + _zz_system_cores_0_externalInterrupt_plic_target_ie_1 <= system_plic_logic_bmb_cmd_payload_fragment_data[4]; + end + end + default : begin + end + endcase + end + end + + always @(posedge io_systemClk) begin + if(debugCd_logic_outputReset) begin + system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext <= 1'b0; + end else begin + system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext <= system_cores_0_logic_cpu_debug_bus_cmd_fire; + end + end + + +endmodule + +module BmbToApb3Bridge ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [15:0] io_input_cmd_payload_fragment_address, + input [1:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_context, + output io_input_rsp_valid, + input io_input_rsp_ready, + output io_input_rsp_payload_last, + output [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output [3:0] io_input_rsp_payload_fragment_context, + output [15:0] io_output_PADDR, + output [0:0] io_output_PSEL, + output io_output_PENABLE, + input io_output_PREADY, + output io_output_PWRITE, + output [31:0] io_output_PWDATA, + input [31:0] io_output_PRDATA, + input io_output_PSLVERROR, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire bmbBuffer_cmd_valid; + reg bmbBuffer_cmd_ready; + wire bmbBuffer_cmd_payload_last; + wire [0:0] bmbBuffer_cmd_payload_fragment_opcode; + wire [15:0] bmbBuffer_cmd_payload_fragment_address; + wire [1:0] bmbBuffer_cmd_payload_fragment_length; + wire [31:0] bmbBuffer_cmd_payload_fragment_data; + wire [3:0] bmbBuffer_cmd_payload_fragment_context; + reg bmbBuffer_rsp_valid; + reg bmbBuffer_rsp_ready; + wire bmbBuffer_rsp_payload_last; + reg [0:0] bmbBuffer_rsp_payload_fragment_opcode; + wire [31:0] bmbBuffer_rsp_payload_fragment_data; + wire [3:0] bmbBuffer_rsp_payload_fragment_context; + wire io_input_rsp_isStall; + wire _zz_io_input_cmd_ready; + wire bmbBuffer_rsp_m2sPipe_valid; + wire bmbBuffer_rsp_m2sPipe_ready; + wire bmbBuffer_rsp_m2sPipe_payload_last; + wire [0:0] bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; + wire [31:0] bmbBuffer_rsp_m2sPipe_payload_fragment_data; + wire [3:0] bmbBuffer_rsp_m2sPipe_payload_fragment_context; + reg bmbBuffer_rsp_rValid; + reg bmbBuffer_rsp_rData_last; + reg [0:0] bmbBuffer_rsp_rData_fragment_opcode; + reg [31:0] bmbBuffer_rsp_rData_fragment_data; + reg [3:0] bmbBuffer_rsp_rData_fragment_context; + wire when_Stream_l368; + reg state; + wire when_BmbToApb3Bridge_l46; + + assign io_input_rsp_isStall = (io_input_rsp_valid && (! io_input_rsp_ready)); + assign _zz_io_input_cmd_ready = (! io_input_rsp_isStall); + assign io_input_cmd_ready = (bmbBuffer_cmd_ready && _zz_io_input_cmd_ready); + assign bmbBuffer_cmd_valid = (io_input_cmd_valid && _zz_io_input_cmd_ready); + assign bmbBuffer_cmd_payload_last = io_input_cmd_payload_last; + assign bmbBuffer_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign bmbBuffer_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign bmbBuffer_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign bmbBuffer_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign bmbBuffer_cmd_payload_fragment_context = io_input_cmd_payload_fragment_context; + always @(*) begin + bmbBuffer_rsp_ready = bmbBuffer_rsp_m2sPipe_ready; + if(when_Stream_l368) begin + bmbBuffer_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! bmbBuffer_rsp_m2sPipe_valid); + assign bmbBuffer_rsp_m2sPipe_valid = bmbBuffer_rsp_rValid; + assign bmbBuffer_rsp_m2sPipe_payload_last = bmbBuffer_rsp_rData_last; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_opcode = bmbBuffer_rsp_rData_fragment_opcode; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_data = bmbBuffer_rsp_rData_fragment_data; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_context = bmbBuffer_rsp_rData_fragment_context; + assign io_input_rsp_valid = bmbBuffer_rsp_m2sPipe_valid; + assign bmbBuffer_rsp_m2sPipe_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = bmbBuffer_rsp_m2sPipe_payload_last; + assign io_input_rsp_payload_fragment_opcode = bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = bmbBuffer_rsp_m2sPipe_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = bmbBuffer_rsp_m2sPipe_payload_fragment_context; + always @(*) begin + bmbBuffer_cmd_ready = 1'b0; + if(!when_BmbToApb3Bridge_l46) begin + if(io_output_PREADY) begin + bmbBuffer_cmd_ready = 1'b1; + end + end + end + + assign io_output_PSEL[0] = bmbBuffer_cmd_valid; + assign io_output_PENABLE = state; + assign io_output_PWRITE = (bmbBuffer_cmd_payload_fragment_opcode == 1'b1); + assign io_output_PADDR = bmbBuffer_cmd_payload_fragment_address; + assign io_output_PWDATA = bmbBuffer_cmd_payload_fragment_data; + always @(*) begin + bmbBuffer_rsp_valid = 1'b0; + if(!when_BmbToApb3Bridge_l46) begin + if(io_output_PREADY) begin + bmbBuffer_rsp_valid = 1'b1; + end + end + end + + assign bmbBuffer_rsp_payload_fragment_data = io_output_PRDATA; + assign when_BmbToApb3Bridge_l46 = (! state); + assign bmbBuffer_rsp_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign bmbBuffer_rsp_payload_last = 1'b1; + always @(*) begin + bmbBuffer_rsp_payload_fragment_opcode = 1'b0; + if(io_output_PSLVERROR) begin + bmbBuffer_rsp_payload_fragment_opcode = 1'b1; + end + end + + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + bmbBuffer_rsp_rValid <= 1'b0; + state <= 1'b0; + end else begin + if(bmbBuffer_rsp_ready) begin + bmbBuffer_rsp_rValid <= bmbBuffer_rsp_valid; + end + if(when_BmbToApb3Bridge_l46) begin + state <= bmbBuffer_cmd_valid; + end else begin + if(io_output_PREADY) begin + state <= 1'b0; + end + end + end + end + + always @(posedge io_systemClk) begin + if(bmbBuffer_rsp_ready) begin + bmbBuffer_rsp_rData_last <= bmbBuffer_rsp_payload_last; + bmbBuffer_rsp_rData_fragment_opcode <= bmbBuffer_rsp_payload_fragment_opcode; + bmbBuffer_rsp_rData_fragment_data <= bmbBuffer_rsp_payload_fragment_data; + bmbBuffer_rsp_rData_fragment_context <= bmbBuffer_rsp_payload_fragment_context; + end + end + + +endmodule + +module BmbSpiXdrMasterCtrl ( + input io_ctrl_cmd_valid, + output io_ctrl_cmd_ready, + input io_ctrl_cmd_payload_last, + input [0:0] io_ctrl_cmd_payload_fragment_opcode, + input [11:0] io_ctrl_cmd_payload_fragment_address, + input [1:0] io_ctrl_cmd_payload_fragment_length, + input [31:0] io_ctrl_cmd_payload_fragment_data, + input [3:0] io_ctrl_cmd_payload_fragment_context, + output io_ctrl_rsp_valid, + input io_ctrl_rsp_ready, + output io_ctrl_rsp_payload_last, + output [0:0] io_ctrl_rsp_payload_fragment_opcode, + output [31:0] io_ctrl_rsp_payload_fragment_data, + output [3:0] io_ctrl_rsp_payload_fragment_context, + output [0:0] io_spi_sclk_write, + output io_spi_data_0_writeEnable, + input [0:0] io_spi_data_0_read, + output [0:0] io_spi_data_0_write, + output io_spi_data_1_writeEnable, + input [0:0] io_spi_data_1_read, + output [0:0] io_spi_data_1_write, + output io_spi_data_2_writeEnable, + input [0:0] io_spi_data_2_read, + output [0:0] io_spi_data_2_write, + output io_spi_data_3_writeEnable, + input [0:0] io_spi_data_3_read, + output [0:0] io_spi_data_3_write, + output [0:0] io_spi_ss, + output io_interrupt, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready; + wire ctrl_io_rsp_queueWithOccupancy_io_pop_ready; + wire ctrl_io_cmd_ready; + wire ctrl_io_rsp_valid; + wire [7:0] ctrl_io_rsp_payload_data; + wire [0:0] ctrl_io_spi_sclk_write; + wire [0:0] ctrl_io_spi_ss; + wire [0:0] ctrl_io_spi_data_0_write; + wire ctrl_io_spi_data_0_writeEnable; + wire [0:0] ctrl_io_spi_data_1_write; + wire ctrl_io_spi_data_1_writeEnable; + wire [0:0] ctrl_io_spi_data_2_write; + wire ctrl_io_spi_data_2_writeEnable; + wire [0:0] ctrl_io_spi_data_3_write; + wire ctrl_io_spi_data_3_writeEnable; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; + wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy; + wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; + wire ctrl_io_rsp_queueWithOccupancy_io_push_ready; + wire ctrl_io_rsp_queueWithOccupancy_io_pop_valid; + wire [7:0] ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_occupancy; + wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_availability; + wire factory_readHaltTrigger; + wire factory_writeHaltTrigger; + wire factory_rsp_valid; + wire factory_rsp_ready; + wire factory_rsp_payload_last; + wire [0:0] factory_rsp_payload_fragment_opcode; + reg [31:0] factory_rsp_payload_fragment_data; + wire [3:0] factory_rsp_payload_fragment_context; + wire _zz_io_ctrl_rsp_valid; + reg _zz_factory_rsp_ready; + wire _zz_io_ctrl_rsp_valid_1; + reg _zz_io_ctrl_rsp_valid_2; + reg _zz_io_ctrl_rsp_payload_last; + reg [0:0] _zz_io_ctrl_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_ctrl_rsp_payload_fragment_data; + reg [3:0] _zz_io_ctrl_rsp_payload_fragment_context; + wire when_Stream_l368; + wire factory_askWrite; + wire factory_askRead; + wire io_ctrl_cmd_fire; + wire factory_doWrite; + wire io_ctrl_cmd_fire_1; + wire factory_doRead; + wire [31:0] mapping_cmdLogic_writeData; + reg mapping_cmdLogic_doRegular; + reg mapping_cmdLogic_doWriteLarge; + reg mapping_cmdLogic_doReadWriteLarge; + wire mapping_cmdLogic_streamUnbuffered_valid; + wire mapping_cmdLogic_streamUnbuffered_ready; + wire mapping_cmdLogic_streamUnbuffered_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_payload_read; + wire mapping_cmdLogic_streamUnbuffered_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_payload_data; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write; + reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; + reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; + wire when_Stream_l368_1; + wire ctrl_io_rsp_toStream_valid; + wire ctrl_io_rsp_toStream_ready; + wire [7:0] ctrl_io_rsp_toStream_payload_data; + reg _zz_io_pop_ready; + reg _zz_io_pop_ready_1; + reg mapping_interruptCtrl_cmdIntEnable; + reg mapping_interruptCtrl_rspIntEnable; + wire mapping_interruptCtrl_cmdInt; + wire mapping_interruptCtrl_rspInt; + wire mapping_interruptCtrl_interrupt; + reg _zz_io_config_kind_cpol; + reg _zz_io_config_kind_cpha; + reg [1:0] _zz_io_config_mod; + reg [11:0] _zz_io_config_sclkToogle; + reg [11:0] _zz_io_config_ss_setup; + reg [11:0] _zz_io_config_ss_hold; + reg [11:0] _zz_io_config_ss_disable; + reg [0:0] _zz_io_config_ss_activeHigh; + wire [1:0] _zz_io_config_kind_cpol_1; + + TopLevel ctrl ( + .io_config_kind_cpol (_zz_io_config_kind_cpol ), //i + .io_config_kind_cpha (_zz_io_config_kind_cpha ), //i + .io_config_sclkToogle (_zz_io_config_sclkToogle[11:0] ), //i + .io_config_mod (_zz_io_config_mod[1:0] ), //i + .io_config_ss_activeHigh (_zz_io_config_ss_activeHigh ), //i + .io_config_ss_setup (_zz_io_config_ss_setup[11:0] ), //i + .io_config_ss_hold (_zz_io_config_ss_hold[11:0] ), //i + .io_config_ss_disable (_zz_io_config_ss_disable[11:0] ), //i + .io_cmd_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid ), //i + .io_cmd_ready (ctrl_io_cmd_ready ), //o + .io_cmd_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind ), //i + .io_cmd_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read ), //i + .io_cmd_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write ), //i + .io_cmd_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data[7:0]), //i + .io_rsp_valid (ctrl_io_rsp_valid ), //o + .io_rsp_payload_data (ctrl_io_rsp_payload_data[7:0] ), //o + .io_spi_sclk_write (ctrl_io_spi_sclk_write ), //o + .io_spi_data_0_writeEnable (ctrl_io_spi_data_0_writeEnable ), //o + .io_spi_data_0_read (io_spi_data_0_read ), //i + .io_spi_data_0_write (ctrl_io_spi_data_0_write ), //o + .io_spi_data_1_writeEnable (ctrl_io_spi_data_1_writeEnable ), //o + .io_spi_data_1_read (io_spi_data_1_read ), //i + .io_spi_data_1_write (ctrl_io_spi_data_1_write ), //o + .io_spi_data_2_writeEnable (ctrl_io_spi_data_2_writeEnable ), //o + .io_spi_data_2_read (io_spi_data_2_read ), //i + .io_spi_data_2_write (ctrl_io_spi_data_2_write ), //o + .io_spi_data_3_writeEnable (ctrl_io_spi_data_3_writeEnable ), //o + .io_spi_data_3_read (io_spi_data_3_read ), //i + .io_spi_data_3_write (ctrl_io_spi_data_3_write ), //o + .io_spi_ss (ctrl_io_spi_ss ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + StreamFifo_2 mapping_cmdLogic_streamUnbuffered_queueWithAvailability ( + .io_push_valid (mapping_cmdLogic_streamUnbuffered_valid ), //i + .io_push_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready ), //o + .io_push_payload_kind (mapping_cmdLogic_streamUnbuffered_payload_kind ), //i + .io_push_payload_read (mapping_cmdLogic_streamUnbuffered_payload_read ), //i + .io_push_payload_write (mapping_cmdLogic_streamUnbuffered_payload_write ), //i + .io_push_payload_data (mapping_cmdLogic_streamUnbuffered_payload_data[7:0] ), //i + .io_pop_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid ), //o + .io_pop_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready ), //i + .io_pop_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind ), //o + .io_pop_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read ), //o + .io_pop_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write ), //o + .io_pop_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data[7:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy[8:0] ), //o + .io_availability (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability[8:0] ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + StreamFifo_3 ctrl_io_rsp_queueWithOccupancy ( + .io_push_valid (ctrl_io_rsp_toStream_valid ), //i + .io_push_ready (ctrl_io_rsp_queueWithOccupancy_io_push_ready ), //o + .io_push_payload_data (ctrl_io_rsp_toStream_payload_data[7:0] ), //i + .io_pop_valid (ctrl_io_rsp_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (ctrl_io_rsp_queueWithOccupancy_io_pop_ready ), //i + .io_pop_payload_data (ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data[7:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (ctrl_io_rsp_queueWithOccupancy_io_occupancy[8:0] ), //o + .io_availability (ctrl_io_rsp_queueWithOccupancy_io_availability[8:0] ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + assign factory_readHaltTrigger = 1'b0; + assign factory_writeHaltTrigger = 1'b0; + assign _zz_io_ctrl_rsp_valid = (! (factory_readHaltTrigger || factory_writeHaltTrigger)); + assign factory_rsp_ready = (_zz_factory_rsp_ready && _zz_io_ctrl_rsp_valid); + always @(*) begin + _zz_factory_rsp_ready = io_ctrl_rsp_ready; + if(when_Stream_l368) begin + _zz_factory_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! _zz_io_ctrl_rsp_valid_1); + assign _zz_io_ctrl_rsp_valid_1 = _zz_io_ctrl_rsp_valid_2; + assign io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid_1; + assign io_ctrl_rsp_payload_last = _zz_io_ctrl_rsp_payload_last; + assign io_ctrl_rsp_payload_fragment_opcode = _zz_io_ctrl_rsp_payload_fragment_opcode; + assign io_ctrl_rsp_payload_fragment_data = _zz_io_ctrl_rsp_payload_fragment_data; + assign io_ctrl_rsp_payload_fragment_context = _zz_io_ctrl_rsp_payload_fragment_context; + assign factory_askWrite = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign factory_askRead = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign io_ctrl_cmd_fire = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); + assign factory_doWrite = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign io_ctrl_cmd_fire_1 = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); + assign factory_doRead = (io_ctrl_cmd_fire_1 && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign factory_rsp_valid = io_ctrl_cmd_valid; + assign io_ctrl_cmd_ready = factory_rsp_ready; + assign factory_rsp_payload_last = 1'b1; + assign factory_rsp_payload_fragment_opcode = 1'b0; + always @(*) begin + factory_rsp_payload_fragment_data = 32'h0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + factory_rsp_payload_fragment_data[31 : 31] = (! ctrl_io_rsp_queueWithOccupancy_io_pop_valid); + factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + end + 12'h004 : begin + factory_rsp_payload_fragment_data[8 : 0] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; + factory_rsp_payload_fragment_data[24 : 16] = ctrl_io_rsp_queueWithOccupancy_io_occupancy; + end + 12'h00c : begin + factory_rsp_payload_fragment_data[16 : 16] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; + factory_rsp_payload_fragment_data[0 : 0] = mapping_interruptCtrl_cmdIntEnable; + factory_rsp_payload_fragment_data[1 : 1] = mapping_interruptCtrl_rspIntEnable; + factory_rsp_payload_fragment_data[8 : 8] = mapping_interruptCtrl_cmdInt; + factory_rsp_payload_fragment_data[9 : 9] = mapping_interruptCtrl_rspInt; + end + 12'h058 : begin + factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + end + default : begin + end + endcase + end + + assign factory_rsp_payload_fragment_context = io_ctrl_cmd_payload_fragment_context; + always @(*) begin + mapping_cmdLogic_doRegular = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doRegular = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + mapping_cmdLogic_doWriteLarge = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h050 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doWriteLarge = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + mapping_cmdLogic_doReadWriteLarge = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h054 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doReadWriteLarge = 1'b1; + end + end + default : begin + end + endcase + end + + assign mapping_cmdLogic_streamUnbuffered_valid = ((mapping_cmdLogic_doRegular || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_write = (((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[8]) || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_read = ((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[9]) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_kind = (mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[11]); + assign mapping_cmdLogic_streamUnbuffered_payload_data = mapping_cmdLogic_writeData[7:0]; + assign mapping_cmdLogic_streamUnbuffered_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready = (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid || mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data); + always @(*) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; + if(when_Stream_l368_1) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l368_1 = (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready = ctrl_io_cmd_ready; + assign ctrl_io_rsp_toStream_valid = ctrl_io_rsp_valid; + assign ctrl_io_rsp_toStream_payload_data = ctrl_io_rsp_payload_data; + assign ctrl_io_rsp_toStream_ready = ctrl_io_rsp_queueWithOccupancy_io_push_ready; + always @(*) begin + _zz_io_pop_ready = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + if(factory_doRead) begin + _zz_io_pop_ready = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + _zz_io_pop_ready_1 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h058 : begin + if(factory_doRead) begin + _zz_io_pop_ready_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign ctrl_io_rsp_queueWithOccupancy_io_pop_ready = (_zz_io_pop_ready || _zz_io_pop_ready_1); + assign mapping_interruptCtrl_cmdInt = (mapping_interruptCtrl_cmdIntEnable && (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid)); + assign mapping_interruptCtrl_rspInt = (mapping_interruptCtrl_rspIntEnable && ctrl_io_rsp_queueWithOccupancy_io_pop_valid); + assign mapping_interruptCtrl_interrupt = (mapping_interruptCtrl_rspInt || mapping_interruptCtrl_cmdInt); + assign io_spi_sclk_write = ctrl_io_spi_sclk_write; + assign io_spi_data_0_writeEnable = ctrl_io_spi_data_0_writeEnable; + assign io_spi_data_0_write = ctrl_io_spi_data_0_write; + assign io_spi_data_1_writeEnable = ctrl_io_spi_data_1_writeEnable; + assign io_spi_data_1_write = ctrl_io_spi_data_1_write; + assign io_spi_data_2_writeEnable = ctrl_io_spi_data_2_writeEnable; + assign io_spi_data_2_write = ctrl_io_spi_data_2_write; + assign io_spi_data_3_writeEnable = ctrl_io_spi_data_3_writeEnable; + assign io_spi_data_3_write = ctrl_io_spi_data_3_write; + assign io_spi_ss = ctrl_io_spi_ss; + assign io_interrupt = mapping_interruptCtrl_interrupt; + assign mapping_cmdLogic_writeData = io_ctrl_cmd_payload_fragment_data[31 : 0]; + assign _zz_io_config_kind_cpol_1 = io_ctrl_cmd_payload_fragment_data[1 : 0]; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + _zz_io_ctrl_rsp_valid_2 <= 1'b0; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b0; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= 1'b0; + mapping_interruptCtrl_cmdIntEnable <= 1'b0; + mapping_interruptCtrl_rspIntEnable <= 1'b0; + _zz_io_config_ss_activeHigh <= 1'b0; + end else begin + if(_zz_factory_rsp_ready) begin + _zz_io_ctrl_rsp_valid_2 <= (factory_rsp_valid && _zz_io_ctrl_rsp_valid); + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b1; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b0; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; + end + case(io_ctrl_cmd_payload_fragment_address) + 12'h00c : begin + if(factory_doWrite) begin + mapping_interruptCtrl_cmdIntEnable <= io_ctrl_cmd_payload_fragment_data[0]; + mapping_interruptCtrl_rspIntEnable <= io_ctrl_cmd_payload_fragment_data[1]; + end + end + 12'h030 : begin + if(factory_doWrite) begin + _zz_io_config_ss_activeHigh <= io_ctrl_cmd_payload_fragment_data[0 : 0]; + end + end + default : begin + end + endcase + end + end + + always @(posedge io_systemClk) begin + if(_zz_factory_rsp_ready) begin + _zz_io_ctrl_rsp_payload_last <= factory_rsp_payload_last; + _zz_io_ctrl_rsp_payload_fragment_opcode <= factory_rsp_payload_fragment_opcode; + _zz_io_ctrl_rsp_payload_fragment_data <= factory_rsp_payload_fragment_data; + _zz_io_ctrl_rsp_payload_fragment_context <= factory_rsp_payload_fragment_context; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; + end + case(io_ctrl_cmd_payload_fragment_address) + 12'h008 : begin + if(factory_doWrite) begin + _zz_io_config_kind_cpol <= _zz_io_config_kind_cpol_1[0]; + _zz_io_config_kind_cpha <= _zz_io_config_kind_cpol_1[1]; + _zz_io_config_mod <= io_ctrl_cmd_payload_fragment_data[5 : 4]; + end + end + 12'h020 : begin + if(factory_doWrite) begin + _zz_io_config_sclkToogle <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h024 : begin + if(factory_doWrite) begin + _zz_io_config_ss_setup <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h028 : begin + if(factory_doWrite) begin + _zz_io_config_ss_hold <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h02c : begin + if(factory_doWrite) begin + _zz_io_config_ss_disable <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + default : begin + end + endcase + end + + +endmodule + +module BmbUartCtrl ( + input io_bus_cmd_valid, + output io_bus_cmd_ready, + input io_bus_cmd_payload_last, + input [0:0] io_bus_cmd_payload_fragment_opcode, + input [5:0] io_bus_cmd_payload_fragment_address, + input [1:0] io_bus_cmd_payload_fragment_length, + input [31:0] io_bus_cmd_payload_fragment_data, + input [3:0] io_bus_cmd_payload_fragment_context, + output io_bus_rsp_valid, + input io_bus_rsp_ready, + output io_bus_rsp_payload_last, + output [0:0] io_bus_rsp_payload_fragment_opcode, + output [31:0] io_bus_rsp_payload_fragment_data, + output [3:0] io_bus_rsp_payload_fragment_context, + output io_uart_txd, + input io_uart_rxd, + output io_interrupt, + input io_systemClk, + input systemCd_logic_outputReset +); + localparam UartStopType_ONE = 1'd0; + localparam UartStopType_TWO = 1'd1; + localparam UartParityType_NONE = 2'd0; + localparam UartParityType_EVEN = 2'd1; + localparam UartParityType_ODD = 2'd2; + + reg uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready; + wire uartCtrl_1_io_write_ready; + wire uartCtrl_1_io_read_valid; + wire [7:0] uartCtrl_1_io_read_payload; + wire uartCtrl_1_io_uart_txd; + wire uartCtrl_1_io_readError; + wire uartCtrl_1_io_readBreak; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_availability; + wire uartCtrl_1_io_read_queueWithOccupancy_io_push_ready; + wire uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid; + wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload; + wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_occupancy; + wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_availability; + wire [0:0] _zz_bridge_misc_readError; + wire [0:0] _zz_bridge_misc_readOverflowError; + wire [0:0] _zz_bridge_misc_breakDetected; + wire [0:0] _zz_bridge_misc_doBreak; + wire [0:0] _zz_bridge_misc_doBreak_1; + wire [7:0] _zz_busCtrl_rsp_payload_fragment_data; + wire [19:0] _zz_bridge_uartConfigReg_clockDivider; + wire [19:0] _zz_bridge_uartConfigReg_clockDivider_1; + wire busCtrl_readHaltTrigger; + wire busCtrl_writeHaltTrigger; + wire busCtrl_rsp_valid; + wire busCtrl_rsp_ready; + wire busCtrl_rsp_payload_last; + wire [0:0] busCtrl_rsp_payload_fragment_opcode; + reg [31:0] busCtrl_rsp_payload_fragment_data; + wire [3:0] busCtrl_rsp_payload_fragment_context; + wire _zz_io_bus_rsp_valid; + reg _zz_busCtrl_rsp_ready; + wire _zz_io_bus_rsp_valid_1; + reg _zz_io_bus_rsp_valid_2; + reg _zz_io_bus_rsp_payload_last; + reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_bus_rsp_payload_fragment_data; + reg [3:0] _zz_io_bus_rsp_payload_fragment_context; + wire when_Stream_l368; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire io_bus_cmd_fire; + wire busCtrl_doWrite; + wire io_bus_cmd_fire_1; + wire busCtrl_doRead; + reg [2:0] bridge_uartConfigReg_frame_dataLength; + reg [0:0] bridge_uartConfigReg_frame_stop; + reg [1:0] bridge_uartConfigReg_frame_parity; + reg [19:0] bridge_uartConfigReg_clockDivider; + reg _zz_bridge_write_streamUnbuffered_valid; + wire bridge_write_streamUnbuffered_valid; + wire bridge_write_streamUnbuffered_ready; + wire [7:0] bridge_write_streamUnbuffered_payload; + reg bridge_read_streamBreaked_valid; + reg bridge_read_streamBreaked_ready; + wire [7:0] bridge_read_streamBreaked_payload; + reg bridge_interruptCtrl_writeIntEnable; + reg bridge_interruptCtrl_readIntEnable; + wire bridge_interruptCtrl_readInt; + wire bridge_interruptCtrl_writeInt; + wire bridge_interruptCtrl_interrupt; + reg bridge_misc_readError; + reg when_BusSlaveFactory_l335; + wire when_BusSlaveFactory_l341; + reg bridge_misc_readOverflowError; + reg when_BusSlaveFactory_l335_1; + wire when_BusSlaveFactory_l341_1; + wire uartCtrl_1_io_read_isStall; + reg bridge_misc_breakDetected; + reg uartCtrl_1_io_readBreak_regNext; + wire when_UartCtrl_l155; + reg when_BusSlaveFactory_l335_2; + wire when_BusSlaveFactory_l341_2; + reg bridge_misc_doBreak; + reg when_BusSlaveFactory_l371; + wire when_BusSlaveFactory_l373; + reg when_BusSlaveFactory_l335_3; + wire when_BusSlaveFactory_l341_3; + wire [1:0] _zz_bridge_uartConfigReg_frame_parity; + wire [0:0] _zz_bridge_uartConfigReg_frame_stop; + wire when_BmbSlaveFactory_l71; + `ifndef SYNTHESIS + reg [23:0] bridge_uartConfigReg_frame_stop_string; + reg [31:0] bridge_uartConfigReg_frame_parity_string; + reg [31:0] _zz_bridge_uartConfigReg_frame_parity_string; + reg [23:0] _zz_bridge_uartConfigReg_frame_stop_string; + `endif + + + assign _zz_bridge_misc_readError = 1'b0; + assign _zz_bridge_misc_readOverflowError = 1'b0; + assign _zz_bridge_misc_breakDetected = 1'b0; + assign _zz_bridge_misc_doBreak = 1'b1; + assign _zz_bridge_misc_doBreak_1 = 1'b0; + assign _zz_busCtrl_rsp_payload_fragment_data = (8'h80 - bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy); + assign _zz_bridge_uartConfigReg_clockDivider_1 = io_bus_cmd_payload_fragment_data[19 : 0]; + assign _zz_bridge_uartConfigReg_clockDivider = _zz_bridge_uartConfigReg_clockDivider_1; + UartCtrl uartCtrl_1 ( + .io_config_frame_dataLength (bridge_uartConfigReg_frame_dataLength[2:0] ), //i + .io_config_frame_stop (bridge_uartConfigReg_frame_stop ), //i + .io_config_frame_parity (bridge_uartConfigReg_frame_parity[1:0] ), //i + .io_config_clockDivider (bridge_uartConfigReg_clockDivider[19:0] ), //i + .io_write_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //i + .io_write_ready (uartCtrl_1_io_write_ready ), //o + .io_write_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0]), //i + .io_read_valid (uartCtrl_1_io_read_valid ), //o + .io_read_ready (uartCtrl_1_io_read_queueWithOccupancy_io_push_ready ), //i + .io_read_payload (uartCtrl_1_io_read_payload[7:0] ), //o + .io_uart_txd (uartCtrl_1_io_uart_txd ), //o + .io_uart_rxd (io_uart_rxd ), //i + .io_readError (uartCtrl_1_io_readError ), //o + .io_writeBreak (bridge_misc_doBreak ), //i + .io_readBreak (uartCtrl_1_io_readBreak ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + StreamFifo bridge_write_streamUnbuffered_queueWithOccupancy ( + .io_push_valid (bridge_write_streamUnbuffered_valid ), //i + .io_push_ready (bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready ), //o + .io_push_payload (bridge_write_streamUnbuffered_payload[7:0] ), //i + .io_pop_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (uartCtrl_1_io_write_ready ), //i + .io_pop_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy[7:0] ), //o + .io_availability (bridge_write_streamUnbuffered_queueWithOccupancy_io_availability[7:0]), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + StreamFifo uartCtrl_1_io_read_queueWithOccupancy ( + .io_push_valid (uartCtrl_1_io_read_valid ), //i + .io_push_ready (uartCtrl_1_io_read_queueWithOccupancy_io_push_ready ), //o + .io_push_payload (uartCtrl_1_io_read_payload[7:0] ), //i + .io_pop_valid (uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready ), //i + .io_pop_payload (uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (uartCtrl_1_io_read_queueWithOccupancy_io_occupancy[7:0] ), //o + .io_availability (uartCtrl_1_io_read_queueWithOccupancy_io_availability[7:0]), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(bridge_uartConfigReg_frame_stop) + UartStopType_ONE : bridge_uartConfigReg_frame_stop_string = "ONE"; + UartStopType_TWO : bridge_uartConfigReg_frame_stop_string = "TWO"; + default : bridge_uartConfigReg_frame_stop_string = "???"; + endcase + end + always @(*) begin + case(bridge_uartConfigReg_frame_parity) + UartParityType_NONE : bridge_uartConfigReg_frame_parity_string = "NONE"; + UartParityType_EVEN : bridge_uartConfigReg_frame_parity_string = "EVEN"; + UartParityType_ODD : bridge_uartConfigReg_frame_parity_string = "ODD "; + default : bridge_uartConfigReg_frame_parity_string = "????"; + endcase + end + always @(*) begin + case(_zz_bridge_uartConfigReg_frame_parity) + UartParityType_NONE : _zz_bridge_uartConfigReg_frame_parity_string = "NONE"; + UartParityType_EVEN : _zz_bridge_uartConfigReg_frame_parity_string = "EVEN"; + UartParityType_ODD : _zz_bridge_uartConfigReg_frame_parity_string = "ODD "; + default : _zz_bridge_uartConfigReg_frame_parity_string = "????"; + endcase + end + always @(*) begin + case(_zz_bridge_uartConfigReg_frame_stop) + UartStopType_ONE : _zz_bridge_uartConfigReg_frame_stop_string = "ONE"; + UartStopType_TWO : _zz_bridge_uartConfigReg_frame_stop_string = "TWO"; + default : _zz_bridge_uartConfigReg_frame_stop_string = "???"; + endcase + end + `endif + + assign io_uart_txd = uartCtrl_1_io_uart_txd; + assign busCtrl_readHaltTrigger = 1'b0; + assign busCtrl_writeHaltTrigger = 1'b0; + assign _zz_io_bus_rsp_valid = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); + assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready && _zz_io_bus_rsp_valid); + always @(*) begin + _zz_busCtrl_rsp_ready = io_bus_rsp_ready; + if(when_Stream_l368) begin + _zz_busCtrl_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! _zz_io_bus_rsp_valid_1); + assign _zz_io_bus_rsp_valid_1 = _zz_io_bus_rsp_valid_2; + assign io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; + assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; + assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; + assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; + assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; + assign busCtrl_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign busCtrl_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign io_bus_cmd_fire_1 = (io_bus_cmd_valid && io_bus_cmd_ready); + assign busCtrl_doRead = (io_bus_cmd_fire_1 && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign busCtrl_rsp_valid = io_bus_cmd_valid; + assign io_bus_cmd_ready = busCtrl_rsp_ready; + assign busCtrl_rsp_payload_last = 1'b1; + assign busCtrl_rsp_payload_fragment_opcode = 1'b0; + always @(*) begin + busCtrl_rsp_payload_fragment_data = 32'h0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + busCtrl_rsp_payload_fragment_data[16 : 16] = (bridge_read_streamBreaked_valid ^ 1'b0); + busCtrl_rsp_payload_fragment_data[7 : 0] = bridge_read_streamBreaked_payload; + end + 6'h04 : begin + busCtrl_rsp_payload_fragment_data[23 : 16] = _zz_busCtrl_rsp_payload_fragment_data; + busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; + busCtrl_rsp_payload_fragment_data[31 : 24] = uartCtrl_1_io_read_queueWithOccupancy_io_occupancy; + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_interruptCtrl_writeIntEnable; + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_interruptCtrl_readIntEnable; + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_interruptCtrl_writeInt; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_interruptCtrl_readInt; + end + 6'h10 : begin + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_misc_readError; + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_misc_readOverflowError; + busCtrl_rsp_payload_fragment_data[8 : 8] = uartCtrl_1_io_readBreak; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_misc_breakDetected; + end + default : begin + end + endcase + end + + assign busCtrl_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; + always @(*) begin + _zz_bridge_write_streamUnbuffered_valid = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + if(busCtrl_doWrite) begin + _zz_bridge_write_streamUnbuffered_valid = 1'b1; + end + end + default : begin + end + endcase + end + + assign bridge_write_streamUnbuffered_valid = _zz_bridge_write_streamUnbuffered_valid; + assign bridge_write_streamUnbuffered_payload = io_bus_cmd_payload_fragment_data[7 : 0]; + assign bridge_write_streamUnbuffered_ready = bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + always @(*) begin + bridge_read_streamBreaked_valid = uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid; + if(uartCtrl_1_io_readBreak) begin + bridge_read_streamBreaked_valid = 1'b0; + end + end + + always @(*) begin + uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready = bridge_read_streamBreaked_ready; + if(uartCtrl_1_io_readBreak) begin + uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready = 1'b1; + end + end + + assign bridge_read_streamBreaked_payload = uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload; + always @(*) begin + bridge_read_streamBreaked_ready = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + if(busCtrl_doRead) begin + bridge_read_streamBreaked_ready = 1'b1; + end + end + default : begin + end + endcase + end + + assign bridge_interruptCtrl_readInt = (bridge_interruptCtrl_readIntEnable && bridge_read_streamBreaked_valid); + assign bridge_interruptCtrl_writeInt = (bridge_interruptCtrl_writeIntEnable && (! bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid)); + assign bridge_interruptCtrl_interrupt = (bridge_interruptCtrl_readInt || bridge_interruptCtrl_writeInt); + always @(*) begin + when_BusSlaveFactory_l335 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l335 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l341 = io_bus_cmd_payload_fragment_data[0]; + always @(*) begin + when_BusSlaveFactory_l335_1 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l335_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l341_1 = io_bus_cmd_payload_fragment_data[1]; + assign uartCtrl_1_io_read_isStall = (uartCtrl_1_io_read_valid && (! uartCtrl_1_io_read_queueWithOccupancy_io_push_ready)); + assign when_UartCtrl_l155 = (uartCtrl_1_io_readBreak && (! uartCtrl_1_io_readBreak_regNext)); + always @(*) begin + when_BusSlaveFactory_l335_2 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l335_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l341_2 = io_bus_cmd_payload_fragment_data[9]; + always @(*) begin + when_BusSlaveFactory_l371 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l371 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l373 = io_bus_cmd_payload_fragment_data[10]; + always @(*) begin + when_BusSlaveFactory_l335_3 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l335_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l341_3 = io_bus_cmd_payload_fragment_data[11]; + assign io_interrupt = bridge_interruptCtrl_interrupt; + assign _zz_bridge_uartConfigReg_frame_parity = io_bus_cmd_payload_fragment_data[9 : 8]; + assign _zz_bridge_uartConfigReg_frame_stop = io_bus_cmd_payload_fragment_data[16 : 16]; + assign when_BmbSlaveFactory_l71 = ((io_bus_cmd_payload_fragment_address & (~ 6'h03)) == 6'h08); + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + _zz_io_bus_rsp_valid_2 <= 1'b0; + bridge_uartConfigReg_clockDivider <= 20'h0; + bridge_uartConfigReg_clockDivider <= 20'h00035; + bridge_uartConfigReg_frame_dataLength <= 3'b111; + bridge_uartConfigReg_frame_parity <= UartParityType_NONE; + bridge_uartConfigReg_frame_stop <= UartStopType_ONE; + bridge_interruptCtrl_writeIntEnable <= 1'b0; + bridge_interruptCtrl_readIntEnable <= 1'b0; + bridge_misc_readError <= 1'b0; + bridge_misc_readOverflowError <= 1'b0; + bridge_misc_breakDetected <= 1'b0; + bridge_misc_doBreak <= 1'b0; + end else begin + if(_zz_busCtrl_rsp_ready) begin + _zz_io_bus_rsp_valid_2 <= (busCtrl_rsp_valid && _zz_io_bus_rsp_valid); + end + if(when_BusSlaveFactory_l335) begin + if(when_BusSlaveFactory_l341) begin + bridge_misc_readError <= _zz_bridge_misc_readError[0]; + end + end + if(uartCtrl_1_io_readError) begin + bridge_misc_readError <= 1'b1; + end + if(when_BusSlaveFactory_l335_1) begin + if(when_BusSlaveFactory_l341_1) begin + bridge_misc_readOverflowError <= _zz_bridge_misc_readOverflowError[0]; + end + end + if(uartCtrl_1_io_read_isStall) begin + bridge_misc_readOverflowError <= 1'b1; + end + if(when_UartCtrl_l155) begin + bridge_misc_breakDetected <= 1'b1; + end + if(when_BusSlaveFactory_l335_2) begin + if(when_BusSlaveFactory_l341_2) begin + bridge_misc_breakDetected <= _zz_bridge_misc_breakDetected[0]; + end + end + if(when_BusSlaveFactory_l371) begin + if(when_BusSlaveFactory_l373) begin + bridge_misc_doBreak <= _zz_bridge_misc_doBreak[0]; + end + end + if(when_BusSlaveFactory_l335_3) begin + if(when_BusSlaveFactory_l341_3) begin + bridge_misc_doBreak <= _zz_bridge_misc_doBreak_1[0]; + end + end + case(io_bus_cmd_payload_fragment_address) + 6'h0c : begin + if(busCtrl_doWrite) begin + bridge_uartConfigReg_frame_dataLength <= io_bus_cmd_payload_fragment_data[2 : 0]; + bridge_uartConfigReg_frame_parity <= _zz_bridge_uartConfigReg_frame_parity; + bridge_uartConfigReg_frame_stop <= _zz_bridge_uartConfigReg_frame_stop; + end + end + 6'h04 : begin + if(busCtrl_doWrite) begin + bridge_interruptCtrl_writeIntEnable <= io_bus_cmd_payload_fragment_data[0]; + bridge_interruptCtrl_readIntEnable <= io_bus_cmd_payload_fragment_data[1]; + end + end + default : begin + end + endcase + if(when_BmbSlaveFactory_l71) begin + if(busCtrl_doWrite) begin + bridge_uartConfigReg_clockDivider[19 : 0] <= _zz_bridge_uartConfigReg_clockDivider; + end + end + end + end + + always @(posedge io_systemClk) begin + if(_zz_busCtrl_rsp_ready) begin + _zz_io_bus_rsp_payload_last <= busCtrl_rsp_payload_last; + _zz_io_bus_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; + _zz_io_bus_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; + _zz_io_bus_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; + end + uartCtrl_1_io_readBreak_regNext <= uartCtrl_1_io_readBreak; + end + + +endmodule + +module BmbClint ( + input io_bus_cmd_valid, + output io_bus_cmd_ready, + input io_bus_cmd_payload_last, + input [0:0] io_bus_cmd_payload_fragment_opcode, + input [15:0] io_bus_cmd_payload_fragment_address, + input [1:0] io_bus_cmd_payload_fragment_length, + input [31:0] io_bus_cmd_payload_fragment_data, + input [3:0] io_bus_cmd_payload_fragment_context, + output io_bus_rsp_valid, + input io_bus_rsp_ready, + output io_bus_rsp_payload_last, + output [0:0] io_bus_rsp_payload_fragment_opcode, + output [31:0] io_bus_rsp_payload_fragment_data, + output [3:0] io_bus_rsp_payload_fragment_context, + output [0:0] io_timerInterrupt, + output [0:0] io_softwareInterrupt, + output [63:0] io_time, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire [31:0] _zz_logic_harts_0_cmp; + wire [31:0] _zz_logic_harts_0_cmp_1; + wire [31:0] _zz_logic_harts_0_cmp_2; + wire [31:0] _zz_logic_harts_0_cmp_3; + wire factory_readHaltTrigger; + wire factory_writeHaltTrigger; + wire factory_rsp_valid; + wire factory_rsp_ready; + wire factory_rsp_payload_last; + wire [0:0] factory_rsp_payload_fragment_opcode; + reg [31:0] factory_rsp_payload_fragment_data; + wire [3:0] factory_rsp_payload_fragment_context; + wire _zz_io_bus_rsp_valid; + reg _zz_factory_rsp_ready; + wire _zz_io_bus_rsp_valid_1; + reg _zz_io_bus_rsp_valid_2; + reg _zz_io_bus_rsp_payload_last; + reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_bus_rsp_payload_fragment_data; + reg [3:0] _zz_io_bus_rsp_payload_fragment_context; + wire when_Stream_l368; + wire factory_askWrite; + wire factory_askRead; + wire io_bus_cmd_fire; + wire factory_doWrite; + wire io_bus_cmd_fire_1; + wire factory_doRead; + reg [63:0] logic_time; + reg [63:0] logic_harts_0_cmp; + reg logic_harts_0_timerInterrupt; + reg logic_harts_0_softwareInterrupt; + wire [63:0] _zz_factory_rsp_payload_fragment_data; + wire when_BmbSlaveFactory_l71; + wire when_BmbSlaveFactory_l71_1; + wire when_BmbSlaveFactory_l71_2; + wire when_BmbSlaveFactory_l71_3; + + assign _zz_logic_harts_0_cmp_1 = io_bus_cmd_payload_fragment_data[31 : 0]; + assign _zz_logic_harts_0_cmp = _zz_logic_harts_0_cmp_1; + assign _zz_logic_harts_0_cmp_3 = io_bus_cmd_payload_fragment_data[31 : 0]; + assign _zz_logic_harts_0_cmp_2 = _zz_logic_harts_0_cmp_3; + assign factory_readHaltTrigger = 1'b0; + assign factory_writeHaltTrigger = 1'b0; + assign _zz_io_bus_rsp_valid = (! (factory_readHaltTrigger || factory_writeHaltTrigger)); + assign factory_rsp_ready = (_zz_factory_rsp_ready && _zz_io_bus_rsp_valid); + always @(*) begin + _zz_factory_rsp_ready = io_bus_rsp_ready; + if(when_Stream_l368) begin + _zz_factory_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! _zz_io_bus_rsp_valid_1); + assign _zz_io_bus_rsp_valid_1 = _zz_io_bus_rsp_valid_2; + assign io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; + assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; + assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; + assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; + assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; + assign factory_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign factory_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign factory_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign io_bus_cmd_fire_1 = (io_bus_cmd_valid && io_bus_cmd_ready); + assign factory_doRead = (io_bus_cmd_fire_1 && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign factory_rsp_valid = io_bus_cmd_valid; + assign io_bus_cmd_ready = factory_rsp_ready; + assign factory_rsp_payload_last = 1'b1; + assign factory_rsp_payload_fragment_opcode = 1'b0; + always @(*) begin + factory_rsp_payload_fragment_data = 32'h0; + case(io_bus_cmd_payload_fragment_address) + 16'h0 : begin + factory_rsp_payload_fragment_data[0 : 0] = logic_harts_0_softwareInterrupt; + end + default : begin + end + endcase + if(when_BmbSlaveFactory_l71) begin + factory_rsp_payload_fragment_data[31 : 0] = _zz_factory_rsp_payload_fragment_data[31 : 0]; + end + if(when_BmbSlaveFactory_l71_1) begin + factory_rsp_payload_fragment_data[31 : 0] = _zz_factory_rsp_payload_fragment_data[63 : 32]; + end + end + + assign factory_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; + assign _zz_factory_rsp_payload_fragment_data = logic_time; + assign io_timerInterrupt[0] = logic_harts_0_timerInterrupt; + assign io_softwareInterrupt[0] = logic_harts_0_softwareInterrupt; + assign io_time = logic_time; + assign when_BmbSlaveFactory_l71 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'hbff8); + assign when_BmbSlaveFactory_l71_1 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'hbffc); + assign when_BmbSlaveFactory_l71_2 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'h4000); + assign when_BmbSlaveFactory_l71_3 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'h4004); + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + _zz_io_bus_rsp_valid_2 <= 1'b0; + logic_time <= 64'h0; + logic_harts_0_softwareInterrupt <= 1'b0; + end else begin + if(_zz_factory_rsp_ready) begin + _zz_io_bus_rsp_valid_2 <= (factory_rsp_valid && _zz_io_bus_rsp_valid); + end + logic_time <= (logic_time + 64'h0000000000000001); + case(io_bus_cmd_payload_fragment_address) + 16'h0 : begin + if(factory_doWrite) begin + logic_harts_0_softwareInterrupt <= io_bus_cmd_payload_fragment_data[0]; + end + end + default : begin + end + endcase + end + end + + always @(posedge io_systemClk) begin + if(_zz_factory_rsp_ready) begin + _zz_io_bus_rsp_payload_last <= factory_rsp_payload_last; + _zz_io_bus_rsp_payload_fragment_opcode <= factory_rsp_payload_fragment_opcode; + _zz_io_bus_rsp_payload_fragment_data <= factory_rsp_payload_fragment_data; + _zz_io_bus_rsp_payload_fragment_context <= factory_rsp_payload_fragment_context; + end + logic_harts_0_timerInterrupt <= (logic_harts_0_cmp <= logic_time); + if(when_BmbSlaveFactory_l71_2) begin + if(factory_doWrite) begin + logic_harts_0_cmp[31 : 0] <= _zz_logic_harts_0_cmp; + end + end + if(when_BmbSlaveFactory_l71_3) begin + if(factory_doWrite) begin + logic_harts_0_cmp[63 : 32] <= _zz_logic_harts_0_cmp_2; + end + end + end + + +endmodule + +module BmbDecoder_3 ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [23:0] io_input_cmd_payload_fragment_address, + input [1:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_mask, + input [3:0] io_input_cmd_payload_fragment_context, + output reg io_input_rsp_valid, + input io_input_rsp_ready, + output reg io_input_rsp_payload_last, + output reg [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output reg [3:0] io_input_rsp_payload_fragment_context, + output reg io_outputs_0_cmd_valid, + input io_outputs_0_cmd_ready, + output io_outputs_0_cmd_payload_last, + output [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output [23:0] io_outputs_0_cmd_payload_fragment_address, + output [1:0] io_outputs_0_cmd_payload_fragment_length, + output [31:0] io_outputs_0_cmd_payload_fragment_data, + output [3:0] io_outputs_0_cmd_payload_fragment_mask, + output [3:0] io_outputs_0_cmd_payload_fragment_context, + input io_outputs_0_rsp_valid, + output io_outputs_0_rsp_ready, + input io_outputs_0_rsp_payload_last, + input [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input [31:0] io_outputs_0_rsp_payload_fragment_data, + input [3:0] io_outputs_0_rsp_payload_fragment_context, + output reg io_outputs_1_cmd_valid, + input io_outputs_1_cmd_ready, + output io_outputs_1_cmd_payload_last, + output [0:0] io_outputs_1_cmd_payload_fragment_opcode, + output [23:0] io_outputs_1_cmd_payload_fragment_address, + output [1:0] io_outputs_1_cmd_payload_fragment_length, + output [31:0] io_outputs_1_cmd_payload_fragment_data, + output [3:0] io_outputs_1_cmd_payload_fragment_mask, + output [3:0] io_outputs_1_cmd_payload_fragment_context, + input io_outputs_1_rsp_valid, + output io_outputs_1_rsp_ready, + input io_outputs_1_rsp_payload_last, + input [0:0] io_outputs_1_rsp_payload_fragment_opcode, + input [31:0] io_outputs_1_rsp_payload_fragment_data, + input [3:0] io_outputs_1_rsp_payload_fragment_context, + output reg io_outputs_2_cmd_valid, + input io_outputs_2_cmd_ready, + output io_outputs_2_cmd_payload_last, + output [0:0] io_outputs_2_cmd_payload_fragment_opcode, + output [23:0] io_outputs_2_cmd_payload_fragment_address, + output [1:0] io_outputs_2_cmd_payload_fragment_length, + output [31:0] io_outputs_2_cmd_payload_fragment_data, + output [3:0] io_outputs_2_cmd_payload_fragment_mask, + output [3:0] io_outputs_2_cmd_payload_fragment_context, + input io_outputs_2_rsp_valid, + output io_outputs_2_rsp_ready, + input io_outputs_2_rsp_payload_last, + input [0:0] io_outputs_2_rsp_payload_fragment_opcode, + input [31:0] io_outputs_2_rsp_payload_fragment_data, + input [3:0] io_outputs_2_rsp_payload_fragment_context, + output reg io_outputs_3_cmd_valid, + input io_outputs_3_cmd_ready, + output io_outputs_3_cmd_payload_last, + output [0:0] io_outputs_3_cmd_payload_fragment_opcode, + output [23:0] io_outputs_3_cmd_payload_fragment_address, + output [1:0] io_outputs_3_cmd_payload_fragment_length, + output [31:0] io_outputs_3_cmd_payload_fragment_data, + output [3:0] io_outputs_3_cmd_payload_fragment_mask, + output [3:0] io_outputs_3_cmd_payload_fragment_context, + input io_outputs_3_rsp_valid, + output io_outputs_3_rsp_ready, + input io_outputs_3_rsp_payload_last, + input [0:0] io_outputs_3_rsp_payload_fragment_opcode, + input [31:0] io_outputs_3_rsp_payload_fragment_data, + input [3:0] io_outputs_3_rsp_payload_fragment_context, + output reg io_outputs_4_cmd_valid, + input io_outputs_4_cmd_ready, + output io_outputs_4_cmd_payload_last, + output [0:0] io_outputs_4_cmd_payload_fragment_opcode, + output [23:0] io_outputs_4_cmd_payload_fragment_address, + output [1:0] io_outputs_4_cmd_payload_fragment_length, + output [31:0] io_outputs_4_cmd_payload_fragment_data, + output [3:0] io_outputs_4_cmd_payload_fragment_mask, + output [3:0] io_outputs_4_cmd_payload_fragment_context, + input io_outputs_4_rsp_valid, + output io_outputs_4_rsp_ready, + input io_outputs_4_rsp_payload_last, + input [0:0] io_outputs_4_rsp_payload_fragment_opcode, + input [31:0] io_outputs_4_rsp_payload_fragment_data, + input [3:0] io_outputs_4_rsp_payload_fragment_context, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire [3:0] _zz_logic_rspPendingCounter; + wire [3:0] _zz_logic_rspPendingCounter_1; + wire [0:0] _zz_logic_rspPendingCounter_2; + wire [3:0] _zz_logic_rspPendingCounter_3; + wire [0:0] _zz_logic_rspPendingCounter_4; + reg _zz_io_input_rsp_payload_last_3; + reg [0:0] _zz_io_input_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_input_rsp_payload_fragment_data; + reg [3:0] _zz_io_input_rsp_payload_fragment_context; + wire logic_input_valid; + reg logic_input_ready; + wire logic_input_payload_last; + wire [0:0] logic_input_payload_fragment_opcode; + wire [23:0] logic_input_payload_fragment_address; + wire [1:0] logic_input_payload_fragment_length; + wire [31:0] logic_input_payload_fragment_data; + wire [3:0] logic_input_payload_fragment_mask; + wire [3:0] logic_input_payload_fragment_context; + reg io_input_cmd_rValid; + wire logic_input_fire; + reg io_input_cmd_rData_last; + reg [0:0] io_input_cmd_rData_fragment_opcode; + reg [23:0] io_input_cmd_rData_fragment_address; + reg [1:0] io_input_cmd_rData_fragment_length; + reg [31:0] io_input_cmd_rData_fragment_data; + reg [3:0] io_input_cmd_rData_fragment_mask; + reg [3:0] io_input_cmd_rData_fragment_context; + wire logic_hitsS0_0; + wire logic_hitsS0_1; + wire logic_hitsS0_2; + wire logic_hitsS0_3; + wire logic_hitsS0_4; + wire logic_noHitS0; + wire io_input_cmd_fire; + reg logic_hitsS1_0; + reg logic_hitsS1_1; + reg logic_hitsS1_2; + reg logic_hitsS1_3; + reg logic_hitsS1_4; + wire io_input_cmd_fire_1; + reg logic_noHitS1; + wire _zz_io_outputs_0_cmd_payload_last; + wire _zz_io_outputs_1_cmd_payload_last; + wire _zz_io_outputs_2_cmd_payload_last; + wire _zz_io_outputs_3_cmd_payload_last; + wire _zz_io_outputs_4_cmd_payload_last; + reg [3:0] logic_rspPendingCounter; + wire logic_input_fire_1; + wire io_input_rsp_fire; + wire logic_cmdWait; + wire when_BmbDecoder_l56; + reg logic_rspHits_0; + reg logic_rspHits_1; + reg logic_rspHits_2; + reg logic_rspHits_3; + reg logic_rspHits_4; + wire logic_rspPending; + wire logic_rspNoHitValid; + reg logic_rspNoHit_doIt; + wire io_input_rsp_fire_1; + wire when_BmbDecoder_l60; + wire logic_input_fire_2; + wire when_BmbDecoder_l60_1; + wire logic_input_fire_3; + reg logic_rspNoHit_singleBeatRsp; + wire logic_input_fire_4; + wire logic_input_fire_5; + reg [3:0] logic_rspNoHit_context; + wire logic_input_fire_6; + wire _zz_io_input_rsp_payload_last; + wire _zz_io_input_rsp_payload_last_1; + wire [2:0] _zz_io_input_rsp_payload_last_2; + + assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); + assign _zz_logic_rspPendingCounter_2 = (logic_input_fire_1 && logic_input_payload_last); + assign _zz_logic_rspPendingCounter_1 = {3'd0, _zz_logic_rspPendingCounter_2}; + assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign _zz_logic_rspPendingCounter_3 = {3'd0, _zz_logic_rspPendingCounter_4}; + always @(*) begin + case(_zz_io_input_rsp_payload_last_2) + 3'b000 : begin + _zz_io_input_rsp_payload_last_3 = io_outputs_0_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_0_rsp_payload_fragment_context; + end + 3'b001 : begin + _zz_io_input_rsp_payload_last_3 = io_outputs_1_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_1_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_1_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_1_rsp_payload_fragment_context; + end + 3'b010 : begin + _zz_io_input_rsp_payload_last_3 = io_outputs_2_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_2_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_2_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_2_rsp_payload_fragment_context; + end + 3'b011 : begin + _zz_io_input_rsp_payload_last_3 = io_outputs_3_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_3_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_3_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_3_rsp_payload_fragment_context; + end + default : begin + _zz_io_input_rsp_payload_last_3 = io_outputs_4_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_4_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_4_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_4_rsp_payload_fragment_context; + end + endcase + end + + assign logic_input_fire = (logic_input_valid && logic_input_ready); + assign io_input_cmd_ready = (! io_input_cmd_rValid); + assign logic_input_valid = io_input_cmd_rValid; + assign logic_input_payload_last = io_input_cmd_rData_last; + assign logic_input_payload_fragment_opcode = io_input_cmd_rData_fragment_opcode; + assign logic_input_payload_fragment_address = io_input_cmd_rData_fragment_address; + assign logic_input_payload_fragment_length = io_input_cmd_rData_fragment_length; + assign logic_input_payload_fragment_data = io_input_cmd_rData_fragment_data; + assign logic_input_payload_fragment_mask = io_input_cmd_rData_fragment_mask; + assign logic_input_payload_fragment_context = io_input_cmd_rData_fragment_context; + assign logic_noHitS0 = (! ({logic_hitsS0_4,{logic_hitsS0_3,{logic_hitsS0_2,{logic_hitsS0_1,logic_hitsS0_0}}}} != 5'h0)); + assign io_input_cmd_fire = (io_input_cmd_valid && io_input_cmd_ready); + assign io_input_cmd_fire_1 = (io_input_cmd_valid && io_input_cmd_ready); + assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 24'h3fffff)) == 24'hc00000); + always @(*) begin + io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS1_0); + if(logic_cmdWait) begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; + assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; + assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_0_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_1 = ((io_input_cmd_payload_fragment_address & (~ 24'h00ffff)) == 24'hb00000); + always @(*) begin + io_outputs_1_cmd_valid = (logic_input_valid && logic_hitsS1_1); + if(logic_cmdWait) begin + io_outputs_1_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_1_cmd_payload_last = logic_input_payload_last; + assign io_outputs_1_cmd_payload_last = _zz_io_outputs_1_cmd_payload_last; + assign io_outputs_1_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_1_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_1_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_1_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_1_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_1_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_2 = ((io_input_cmd_payload_fragment_address & (~ 24'h00003f)) == 24'h010000); + always @(*) begin + io_outputs_2_cmd_valid = (logic_input_valid && logic_hitsS1_2); + if(logic_cmdWait) begin + io_outputs_2_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_2_cmd_payload_last = logic_input_payload_last; + assign io_outputs_2_cmd_payload_last = _zz_io_outputs_2_cmd_payload_last; + assign io_outputs_2_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_2_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_2_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_2_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_2_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_2_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_3 = ((io_input_cmd_payload_fragment_address & (~ 24'h000fff)) == 24'h014000); + always @(*) begin + io_outputs_3_cmd_valid = (logic_input_valid && logic_hitsS1_3); + if(logic_cmdWait) begin + io_outputs_3_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_3_cmd_payload_last = logic_input_payload_last; + assign io_outputs_3_cmd_payload_last = _zz_io_outputs_3_cmd_payload_last; + assign io_outputs_3_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_3_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_3_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_3_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_3_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_3_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_4 = ((io_input_cmd_payload_fragment_address & (~ 24'h00ffff)) == 24'h100000); + always @(*) begin + io_outputs_4_cmd_valid = (logic_input_valid && logic_hitsS1_4); + if(logic_cmdWait) begin + io_outputs_4_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_4_cmd_payload_last = logic_input_payload_last; + assign io_outputs_4_cmd_payload_last = _zz_io_outputs_4_cmd_payload_last; + assign io_outputs_4_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_4_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_4_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_4_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_4_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_4_cmd_payload_fragment_context = logic_input_payload_fragment_context; + always @(*) begin + logic_input_ready = (({(logic_hitsS1_4 && io_outputs_4_cmd_ready),{(logic_hitsS1_3 && io_outputs_3_cmd_ready),{(logic_hitsS1_2 && io_outputs_2_cmd_ready),{(logic_hitsS1_1 && io_outputs_1_cmd_ready),(logic_hitsS1_0 && io_outputs_0_cmd_ready)}}}} != 5'h0) || logic_noHitS1); + if(logic_cmdWait) begin + logic_input_ready = 1'b0; + end + end + + assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); + assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); + assign logic_rspPending = (logic_rspPendingCounter != 4'b0000); + assign logic_rspNoHitValid = (! ({logic_rspHits_4,{logic_rspHits_3,{logic_rspHits_2,{logic_rspHits_1,logic_rspHits_0}}}} != 5'h0)); + assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); + assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); + assign when_BmbDecoder_l60_1 = ((logic_input_fire_2 && logic_noHitS1) && logic_input_payload_last); + assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_6 = (logic_input_valid && logic_input_ready); + always @(*) begin + io_input_rsp_valid = (({io_outputs_4_rsp_valid,{io_outputs_3_rsp_valid,{io_outputs_2_rsp_valid,{io_outputs_1_rsp_valid,io_outputs_0_rsp_valid}}}} != 5'h0) || (logic_rspPending && logic_rspNoHitValid)); + if(logic_rspNoHit_doIt) begin + io_input_rsp_valid = 1'b1; + end + end + + assign _zz_io_input_rsp_payload_last = (logic_rspHits_1 || logic_rspHits_3); + assign _zz_io_input_rsp_payload_last_1 = (logic_rspHits_2 || logic_rspHits_3); + assign _zz_io_input_rsp_payload_last_2 = {logic_rspHits_4,{_zz_io_input_rsp_payload_last_1,_zz_io_input_rsp_payload_last}}; + always @(*) begin + io_input_rsp_payload_last = _zz_io_input_rsp_payload_last_3; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_last = 1'b1; + end + end + + always @(*) begin + io_input_rsp_payload_fragment_opcode = _zz_io_input_rsp_payload_fragment_opcode; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_opcode = 1'b1; + end + end + + assign io_input_rsp_payload_fragment_data = _zz_io_input_rsp_payload_fragment_data; + always @(*) begin + io_input_rsp_payload_fragment_context = _zz_io_input_rsp_payload_fragment_context; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_context = logic_rspNoHit_context; + end + end + + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign io_outputs_1_rsp_ready = io_input_rsp_ready; + assign io_outputs_2_rsp_ready = io_input_rsp_ready; + assign io_outputs_3_rsp_ready = io_input_rsp_ready; + assign io_outputs_4_rsp_ready = io_input_rsp_ready; + assign logic_cmdWait = ((logic_rspPending && ((((((logic_hitsS1_0 != logic_rspHits_0) || (logic_hitsS1_1 != logic_rspHits_1)) || (logic_hitsS1_2 != logic_rspHits_2)) || (logic_hitsS1_3 != logic_rspHits_3)) || (logic_hitsS1_4 != logic_rspHits_4)) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 4'b1000)); + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + io_input_cmd_rValid <= 1'b0; + logic_rspPendingCounter <= 4'b0000; + logic_rspNoHit_doIt <= 1'b0; + end else begin + if(io_input_cmd_valid) begin + io_input_cmd_rValid <= 1'b1; + end + if(logic_input_fire) begin + io_input_cmd_rValid <= 1'b0; + end + logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); + if(when_BmbDecoder_l60) begin + logic_rspNoHit_doIt <= 1'b0; + end + if(when_BmbDecoder_l60_1) begin + logic_rspNoHit_doIt <= 1'b1; + end + end + end + + always @(posedge io_systemClk) begin + if(io_input_cmd_ready) begin + io_input_cmd_rData_last <= io_input_cmd_payload_last; + io_input_cmd_rData_fragment_opcode <= io_input_cmd_payload_fragment_opcode; + io_input_cmd_rData_fragment_address <= io_input_cmd_payload_fragment_address; + io_input_cmd_rData_fragment_length <= io_input_cmd_payload_fragment_length; + io_input_cmd_rData_fragment_data <= io_input_cmd_payload_fragment_data; + io_input_cmd_rData_fragment_mask <= io_input_cmd_payload_fragment_mask; + io_input_cmd_rData_fragment_context <= io_input_cmd_payload_fragment_context; + end + if(io_input_cmd_fire) begin + logic_hitsS1_0 <= logic_hitsS0_0; + logic_hitsS1_1 <= logic_hitsS0_1; + logic_hitsS1_2 <= logic_hitsS0_2; + logic_hitsS1_3 <= logic_hitsS0_3; + logic_hitsS1_4 <= logic_hitsS0_4; + end + if(io_input_cmd_fire_1) begin + logic_noHitS1 <= logic_noHitS0; + end + if(when_BmbDecoder_l56) begin + logic_rspHits_0 <= logic_hitsS1_0; + logic_rspHits_1 <= logic_hitsS1_1; + logic_rspHits_2 <= logic_hitsS1_2; + logic_rspHits_3 <= logic_hitsS1_3; + logic_rspHits_4 <= logic_hitsS1_4; + end + if(logic_input_fire_3) begin + logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); + end + if(logic_input_fire_5) begin + logic_rspNoHit_context <= logic_input_payload_fragment_context; + end + end + + +endmodule + +//BmbUnburstify replaced by BmbUnburstify + +module BmbUnburstify ( + input io_input_cmd_valid, + output reg io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_source, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [31:0] io_input_cmd_payload_fragment_address, + input [5:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_mask, + input [0:0] io_input_cmd_payload_fragment_context, + output io_input_rsp_valid, + input io_input_rsp_ready, + output io_input_rsp_payload_last, + output [0:0] io_input_rsp_payload_fragment_source, + output [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output [0:0] io_input_rsp_payload_fragment_context, + output reg io_output_cmd_valid, + input io_output_cmd_ready, + output io_output_cmd_payload_last, + output reg [0:0] io_output_cmd_payload_fragment_opcode, + output reg [31:0] io_output_cmd_payload_fragment_address, + output reg [1:0] io_output_cmd_payload_fragment_length, + output [31:0] io_output_cmd_payload_fragment_data, + output [3:0] io_output_cmd_payload_fragment_mask, + output [3:0] io_output_cmd_payload_fragment_context, + input io_output_rsp_valid, + output reg io_output_rsp_ready, + input io_output_rsp_payload_last, + input [0:0] io_output_rsp_payload_fragment_opcode, + input [31:0] io_output_rsp_payload_fragment_data, + input [3:0] io_output_rsp_payload_fragment_context, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire [3:0] _zz_buffer_last; + wire [0:0] _zz_buffer_last_1; + wire [11:0] _zz_buffer_addressIncr; + wire [11:0] _zz_buffer_addressIncr_1; + wire [11:0] _zz_buffer_addressIncr_2; + wire doResult; + reg buffer_valid; + reg [0:0] buffer_opcode; + reg [0:0] buffer_source; + reg [31:0] buffer_address; + reg [0:0] buffer_context; + reg [3:0] buffer_beat; + wire buffer_last; + wire [31:0] buffer_addressIncr; + wire buffer_isWrite; + wire io_output_cmd_fire; + wire [3:0] cmdTransferBeatCount; + wire requireBuffer; + reg cmdContext_drop; + reg cmdContext_last; + reg [0:0] cmdContext_source; + reg [0:0] cmdContext_context; + wire io_output_cmd_fire_1; + wire rspContext_drop; + wire rspContext_last; + wire [0:0] rspContext_source; + wire [0:0] rspContext_context; + wire [3:0] _zz_rspContext_drop; + wire when_Stream_l434; + reg io_output_rsp_thrown_valid; + wire io_output_rsp_thrown_ready; + wire io_output_rsp_thrown_payload_last; + wire [0:0] io_output_rsp_thrown_payload_fragment_opcode; + wire [31:0] io_output_rsp_thrown_payload_fragment_data; + wire [3:0] io_output_rsp_thrown_payload_fragment_context; + + assign _zz_buffer_last_1 = 1'b1; + assign _zz_buffer_last = {3'd0, _zz_buffer_last_1}; + assign _zz_buffer_addressIncr = (_zz_buffer_addressIncr_1 + 12'h004); + assign _zz_buffer_addressIncr_2 = buffer_address[11 : 0]; + assign _zz_buffer_addressIncr_1 = _zz_buffer_addressIncr_2; + assign buffer_last = (buffer_beat == _zz_buffer_last); + assign buffer_addressIncr = {buffer_address[31 : 12],(_zz_buffer_addressIncr & (~ 12'h003))}; + assign buffer_isWrite = (buffer_opcode == 1'b1); + assign io_output_cmd_fire = (io_output_cmd_valid && io_output_cmd_ready); + assign cmdTransferBeatCount = io_input_cmd_payload_fragment_length[5 : 2]; + assign requireBuffer = (cmdTransferBeatCount != 4'b0000); + assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign io_output_cmd_payload_last = 1'b1; + assign io_output_cmd_payload_fragment_context = {cmdContext_context,{cmdContext_source,{cmdContext_last,cmdContext_drop}}}; + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_address = buffer_addressIncr; + end else begin + io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + if(requireBuffer) begin + io_output_cmd_payload_fragment_address[1 : 0] = 2'b00; + end + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_opcode = buffer_opcode; + end else begin + io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_length = 2'b11; + end else begin + if(requireBuffer) begin + io_output_cmd_payload_fragment_length = 2'b11; + end else begin + io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length[1:0]; + end + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_context = buffer_context; + end else begin + cmdContext_context = io_input_cmd_payload_fragment_context; + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_source = buffer_source; + end else begin + cmdContext_source = io_input_cmd_payload_fragment_source; + end + end + + always @(*) begin + io_input_cmd_ready = 1'b0; + if(buffer_valid) begin + io_input_cmd_ready = (buffer_isWrite && io_output_cmd_ready); + end else begin + io_input_cmd_ready = io_output_cmd_ready; + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_valid = (! (buffer_isWrite && (! io_input_cmd_valid))); + end else begin + io_output_cmd_valid = io_input_cmd_valid; + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_last = buffer_last; + end else begin + cmdContext_last = (! requireBuffer); + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_drop = buffer_isWrite; + end else begin + cmdContext_drop = (io_input_cmd_payload_fragment_opcode == 1'b1); + end + end + + assign io_output_cmd_fire_1 = (io_output_cmd_valid && io_output_cmd_ready); + assign _zz_rspContext_drop = io_output_rsp_payload_fragment_context; + assign rspContext_drop = _zz_rspContext_drop[0]; + assign rspContext_last = _zz_rspContext_drop[1]; + assign rspContext_source = _zz_rspContext_drop[2 : 2]; + assign rspContext_context = _zz_rspContext_drop[3 : 3]; + assign when_Stream_l434 = (! (rspContext_last || (! rspContext_drop))); + always @(*) begin + io_output_rsp_thrown_valid = io_output_rsp_valid; + if(when_Stream_l434) begin + io_output_rsp_thrown_valid = 1'b0; + end + end + + always @(*) begin + io_output_rsp_ready = io_output_rsp_thrown_ready; + if(when_Stream_l434) begin + io_output_rsp_ready = 1'b1; + end + end + + assign io_output_rsp_thrown_payload_last = io_output_rsp_payload_last; + assign io_output_rsp_thrown_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_output_rsp_thrown_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_output_rsp_thrown_payload_fragment_context = io_output_rsp_payload_fragment_context; + assign io_input_rsp_valid = io_output_rsp_thrown_valid; + assign io_output_rsp_thrown_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = rspContext_last; + assign io_input_rsp_payload_fragment_source = rspContext_source; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = rspContext_context; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + buffer_valid <= 1'b0; + end else begin + if(io_output_cmd_fire) begin + if(buffer_last) begin + buffer_valid <= 1'b0; + end + end + if(!buffer_valid) begin + buffer_valid <= (requireBuffer && io_output_cmd_fire_1); + end + end + end + + always @(posedge io_systemClk) begin + if(io_output_cmd_fire) begin + buffer_beat <= (buffer_beat - 4'b0001); + buffer_address[11 : 0] <= buffer_addressIncr[11 : 0]; + end + if(!buffer_valid) begin + buffer_opcode <= io_input_cmd_payload_fragment_opcode; + buffer_source <= io_input_cmd_payload_fragment_source; + buffer_address <= io_input_cmd_payload_fragment_address; + buffer_context <= io_input_cmd_payload_fragment_context; + buffer_beat <= cmdTransferBeatCount; + end + end + + +endmodule + +module BmbOnChipRam ( + input io_bus_cmd_valid, + output io_bus_cmd_ready, + input io_bus_cmd_payload_last, + input [0:0] io_bus_cmd_payload_fragment_opcode, + input [14:0] io_bus_cmd_payload_fragment_address, + input [1:0] io_bus_cmd_payload_fragment_length, + input [31:0] io_bus_cmd_payload_fragment_data, + input [3:0] io_bus_cmd_payload_fragment_mask, + input [3:0] io_bus_cmd_payload_fragment_context, + output io_bus_rsp_valid, + input io_bus_rsp_ready, + output io_bus_rsp_payload_last, + output [0:0] io_bus_rsp_payload_fragment_opcode, + output [31:0] io_bus_rsp_payload_fragment_data, + output [3:0] io_bus_rsp_payload_fragment_context, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [31:0] _zz_ram_port0; + wire io_bus_rsp_isStall; + reg io_bus_cmd_valid_regNextWhen; + reg [3:0] io_bus_cmd_payload_fragment_context_regNextWhen; + wire [12:0] _zz_io_bus_rsp_payload_fragment_data; + wire io_bus_cmd_fire; + wire _zz_io_bus_rsp_payload_fragment_data_1; + wire [31:0] _zz_io_bus_rsp_payload_fragment_data_2; + reg [7:0] ram_symbol0 [0:8191]; + reg [7:0] ram_symbol1 [0:8191]; + reg [7:0] ram_symbol2 [0:8191]; + reg [7:0] ram_symbol3 [0:8191]; + reg [7:0] _zz_ramsymbol_read; + reg [7:0] _zz_ramsymbol_read_1; + reg [7:0] _zz_ramsymbol_read_2; + reg [7:0] _zz_ramsymbol_read_3; + + initial begin + $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol0.bin",ram_symbol0); + $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol1.bin",ram_symbol1); + $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol2.bin",ram_symbol2); + $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol3.bin",ram_symbol3); + end + always @(*) begin + _zz_ram_port0 = {_zz_ramsymbol_read_3, _zz_ramsymbol_read_2, _zz_ramsymbol_read_1, _zz_ramsymbol_read}; + end + always @(posedge io_systemClk) begin + if(io_bus_cmd_fire) begin + _zz_ramsymbol_read <= ram_symbol0[_zz_io_bus_rsp_payload_fragment_data]; + _zz_ramsymbol_read_1 <= ram_symbol1[_zz_io_bus_rsp_payload_fragment_data]; + _zz_ramsymbol_read_2 <= ram_symbol2[_zz_io_bus_rsp_payload_fragment_data]; + _zz_ramsymbol_read_3 <= ram_symbol3[_zz_io_bus_rsp_payload_fragment_data]; + end + end + + always @(posedge io_systemClk) begin + if(io_bus_cmd_payload_fragment_mask[0] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin + ram_symbol0[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[7 : 0]; + end + if(io_bus_cmd_payload_fragment_mask[1] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin + ram_symbol1[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[15 : 8]; + end + if(io_bus_cmd_payload_fragment_mask[2] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin + ram_symbol2[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[23 : 16]; + end + if(io_bus_cmd_payload_fragment_mask[3] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin + ram_symbol3[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[31 : 24]; + end + end + + assign io_bus_rsp_isStall = (io_bus_rsp_valid && (! io_bus_rsp_ready)); + assign io_bus_cmd_ready = (! io_bus_rsp_isStall); + assign io_bus_rsp_valid = io_bus_cmd_valid_regNextWhen; + assign io_bus_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context_regNextWhen; + assign _zz_io_bus_rsp_payload_fragment_data = (io_bus_cmd_payload_fragment_address >>> 2); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign _zz_io_bus_rsp_payload_fragment_data_1 = (io_bus_cmd_payload_fragment_opcode == 1'b1); + assign _zz_io_bus_rsp_payload_fragment_data_2 = io_bus_cmd_payload_fragment_data; + assign io_bus_rsp_payload_fragment_data = _zz_ram_port0; + assign io_bus_rsp_payload_fragment_opcode = 1'b0; + assign io_bus_rsp_payload_last = 1'b1; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + io_bus_cmd_valid_regNextWhen <= 1'b0; + end else begin + if(io_bus_cmd_ready) begin + io_bus_cmd_valid_regNextWhen <= io_bus_cmd_valid; + end + end + end + + always @(posedge io_systemClk) begin + if(io_bus_cmd_ready) begin + io_bus_cmd_payload_fragment_context_regNextWhen <= io_bus_cmd_payload_fragment_context; + end + end + + +endmodule + +module BmbDecoder_2 ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_source, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [31:0] io_input_cmd_payload_fragment_address, + input [5:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_mask, + input [0:0] io_input_cmd_payload_fragment_context, + output reg io_input_rsp_valid, + input io_input_rsp_ready, + output reg io_input_rsp_payload_last, + output reg [0:0] io_input_rsp_payload_fragment_source, + output reg [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output reg [0:0] io_input_rsp_payload_fragment_context, + output reg io_outputs_0_cmd_valid, + input io_outputs_0_cmd_ready, + output io_outputs_0_cmd_payload_last, + output [0:0] io_outputs_0_cmd_payload_fragment_source, + output [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output [31:0] io_outputs_0_cmd_payload_fragment_address, + output [5:0] io_outputs_0_cmd_payload_fragment_length, + output [31:0] io_outputs_0_cmd_payload_fragment_data, + output [3:0] io_outputs_0_cmd_payload_fragment_mask, + output [0:0] io_outputs_0_cmd_payload_fragment_context, + input io_outputs_0_rsp_valid, + output io_outputs_0_rsp_ready, + input io_outputs_0_rsp_payload_last, + input [0:0] io_outputs_0_rsp_payload_fragment_source, + input [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input [31:0] io_outputs_0_rsp_payload_fragment_data, + input [0:0] io_outputs_0_rsp_payload_fragment_context, + output reg io_outputs_1_cmd_valid, + input io_outputs_1_cmd_ready, + output io_outputs_1_cmd_payload_last, + output [0:0] io_outputs_1_cmd_payload_fragment_source, + output [0:0] io_outputs_1_cmd_payload_fragment_opcode, + output [31:0] io_outputs_1_cmd_payload_fragment_address, + output [5:0] io_outputs_1_cmd_payload_fragment_length, + output [31:0] io_outputs_1_cmd_payload_fragment_data, + output [3:0] io_outputs_1_cmd_payload_fragment_mask, + output [0:0] io_outputs_1_cmd_payload_fragment_context, + input io_outputs_1_rsp_valid, + output io_outputs_1_rsp_ready, + input io_outputs_1_rsp_payload_last, + input [0:0] io_outputs_1_rsp_payload_fragment_source, + input [0:0] io_outputs_1_rsp_payload_fragment_opcode, + input [31:0] io_outputs_1_rsp_payload_fragment_data, + input [0:0] io_outputs_1_rsp_payload_fragment_context, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire [6:0] _zz_logic_rspPendingCounter; + wire [6:0] _zz_logic_rspPendingCounter_1; + wire [0:0] _zz_logic_rspPendingCounter_2; + wire [6:0] _zz_logic_rspPendingCounter_3; + wire [0:0] _zz_logic_rspPendingCounter_4; + reg _zz_io_input_rsp_payload_last_1; + reg [0:0] _zz_io_input_rsp_payload_fragment_source; + reg [0:0] _zz_io_input_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_input_rsp_payload_fragment_data; + reg [0:0] _zz_io_input_rsp_payload_fragment_context; + wire logic_input_valid; + reg logic_input_ready; + wire logic_input_payload_last; + wire [0:0] logic_input_payload_fragment_source; + wire [0:0] logic_input_payload_fragment_opcode; + wire [31:0] logic_input_payload_fragment_address; + wire [5:0] logic_input_payload_fragment_length; + wire [31:0] logic_input_payload_fragment_data; + wire [3:0] logic_input_payload_fragment_mask; + wire [0:0] logic_input_payload_fragment_context; + wire logic_hitsS0_0; + wire logic_hitsS0_1; + wire logic_noHitS0; + wire _zz_io_outputs_0_cmd_payload_last; + wire _zz_io_outputs_1_cmd_payload_last; + reg [6:0] logic_rspPendingCounter; + wire logic_input_fire; + wire io_input_rsp_fire; + wire logic_cmdWait; + wire when_BmbDecoder_l56; + reg logic_rspHits_0; + reg logic_rspHits_1; + wire logic_rspPending; + wire logic_rspNoHitValid; + reg logic_rspNoHit_doIt; + wire io_input_rsp_fire_1; + wire when_BmbDecoder_l60; + wire logic_input_fire_1; + wire when_BmbDecoder_l60_1; + wire logic_input_fire_2; + reg logic_rspNoHit_singleBeatRsp; + wire logic_input_fire_3; + reg [0:0] logic_rspNoHit_source; + wire logic_input_fire_4; + reg [0:0] logic_rspNoHit_context; + wire logic_input_fire_5; + reg [3:0] logic_rspNoHit_counter; + wire [0:0] _zz_io_input_rsp_payload_last; + wire when_BmbDecoder_l81; + wire io_input_rsp_fire_2; + + assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); + assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); + assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; + assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; + always @(*) begin + case(_zz_io_input_rsp_payload_last) + 1'b0 : begin + _zz_io_input_rsp_payload_last_1 = io_outputs_0_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_source = io_outputs_0_rsp_payload_fragment_source; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_0_rsp_payload_fragment_context; + end + default : begin + _zz_io_input_rsp_payload_last_1 = io_outputs_1_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_source = io_outputs_1_rsp_payload_fragment_source; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_1_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_1_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_1_rsp_payload_fragment_context; + end + endcase + end + + assign logic_input_valid = io_input_cmd_valid; + assign io_input_cmd_ready = logic_input_ready; + assign logic_input_payload_last = io_input_cmd_payload_last; + assign logic_input_payload_fragment_source = io_input_cmd_payload_fragment_source; + assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign logic_input_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign logic_noHitS0 = (! ({logic_hitsS0_1,logic_hitsS0_0} != 2'b00)); + assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 32'h00007fff)) == 32'hf9000000); + always @(*) begin + io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); + if(logic_cmdWait) begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; + assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; + assign io_outputs_0_cmd_payload_fragment_source = logic_input_payload_fragment_source; + assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_0_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_1 = ((io_input_cmd_payload_fragment_address & (~ 32'h00ffffff)) == 32'hf8000000); + always @(*) begin + io_outputs_1_cmd_valid = (logic_input_valid && logic_hitsS0_1); + if(logic_cmdWait) begin + io_outputs_1_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_1_cmd_payload_last = logic_input_payload_last; + assign io_outputs_1_cmd_payload_last = _zz_io_outputs_1_cmd_payload_last; + assign io_outputs_1_cmd_payload_fragment_source = logic_input_payload_fragment_source; + assign io_outputs_1_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_1_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_1_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_1_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_1_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_1_cmd_payload_fragment_context = logic_input_payload_fragment_context; + always @(*) begin + logic_input_ready = (({(logic_hitsS0_1 && io_outputs_1_cmd_ready),(logic_hitsS0_0 && io_outputs_0_cmd_ready)} != 2'b00) || logic_noHitS0); + if(logic_cmdWait) begin + logic_input_ready = 1'b0; + end + end + + assign logic_input_fire = (logic_input_valid && logic_input_ready); + assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); + assign logic_rspPending = (logic_rspPendingCounter != 7'h0); + assign logic_rspNoHitValid = (! ({logic_rspHits_1,logic_rspHits_0} != 2'b00)); + assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); + assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); + assign when_BmbDecoder_l60_1 = ((logic_input_fire_1 && logic_noHitS0) && logic_input_payload_last); + assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); + always @(*) begin + io_input_rsp_valid = (({io_outputs_1_rsp_valid,io_outputs_0_rsp_valid} != 2'b00) || (logic_rspPending && logic_rspNoHitValid)); + if(logic_rspNoHit_doIt) begin + io_input_rsp_valid = 1'b1; + end + end + + assign _zz_io_input_rsp_payload_last = logic_rspHits_1; + always @(*) begin + io_input_rsp_payload_last = _zz_io_input_rsp_payload_last_1; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_last = 1'b0; + if(when_BmbDecoder_l81) begin + io_input_rsp_payload_last = 1'b1; + end + if(logic_rspNoHit_singleBeatRsp) begin + io_input_rsp_payload_last = 1'b1; + end + end + end + + always @(*) begin + io_input_rsp_payload_fragment_source = _zz_io_input_rsp_payload_fragment_source; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_source = logic_rspNoHit_source; + end + end + + always @(*) begin + io_input_rsp_payload_fragment_opcode = _zz_io_input_rsp_payload_fragment_opcode; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_opcode = 1'b1; + end + end + + assign io_input_rsp_payload_fragment_data = _zz_io_input_rsp_payload_fragment_data; + always @(*) begin + io_input_rsp_payload_fragment_context = _zz_io_input_rsp_payload_fragment_context; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_context = logic_rspNoHit_context; + end + end + + assign when_BmbDecoder_l81 = (logic_rspNoHit_counter == 4'b0000); + assign io_input_rsp_fire_2 = (io_input_rsp_valid && io_input_rsp_ready); + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign io_outputs_1_rsp_ready = io_input_rsp_ready; + assign logic_cmdWait = ((logic_rspPending && (((logic_hitsS0_0 != logic_rspHits_0) || (logic_hitsS0_1 != logic_rspHits_1)) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + logic_rspPendingCounter <= 7'h0; + logic_rspNoHit_doIt <= 1'b0; + end else begin + logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); + if(when_BmbDecoder_l60) begin + logic_rspNoHit_doIt <= 1'b0; + end + if(when_BmbDecoder_l60_1) begin + logic_rspNoHit_doIt <= 1'b1; + end + end + end + + always @(posedge io_systemClk) begin + if(when_BmbDecoder_l56) begin + logic_rspHits_0 <= logic_hitsS0_0; + logic_rspHits_1 <= logic_hitsS0_1; + end + if(logic_input_fire_2) begin + logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); + end + if(logic_input_fire_3) begin + logic_rspNoHit_source <= logic_input_payload_fragment_source; + end + if(logic_input_fire_4) begin + logic_rspNoHit_context <= logic_input_payload_fragment_context; + end + if(logic_input_fire_5) begin + logic_rspNoHit_counter <= logic_input_payload_fragment_length[5 : 2]; + end + if(logic_rspNoHit_doIt) begin + if(io_input_rsp_fire_2) begin + logic_rspNoHit_counter <= (logic_rspNoHit_counter - 4'b0001); + end + end + end + + +endmodule + +module BmbArbiter ( + input io_inputs_0_cmd_valid, + output io_inputs_0_cmd_ready, + input io_inputs_0_cmd_payload_last, + input [0:0] io_inputs_0_cmd_payload_fragment_opcode, + input [31:0] io_inputs_0_cmd_payload_fragment_address, + input [5:0] io_inputs_0_cmd_payload_fragment_length, + input [31:0] io_inputs_0_cmd_payload_fragment_data, + input [3:0] io_inputs_0_cmd_payload_fragment_mask, + input [0:0] io_inputs_0_cmd_payload_fragment_context, + output io_inputs_0_rsp_valid, + input io_inputs_0_rsp_ready, + output io_inputs_0_rsp_payload_last, + output [0:0] io_inputs_0_rsp_payload_fragment_opcode, + output [31:0] io_inputs_0_rsp_payload_fragment_data, + output [0:0] io_inputs_0_rsp_payload_fragment_context, + input io_inputs_1_cmd_valid, + output io_inputs_1_cmd_ready, + input io_inputs_1_cmd_payload_last, + input [0:0] io_inputs_1_cmd_payload_fragment_opcode, + input [31:0] io_inputs_1_cmd_payload_fragment_address, + input [5:0] io_inputs_1_cmd_payload_fragment_length, + input [31:0] io_inputs_1_cmd_payload_fragment_data, + input [3:0] io_inputs_1_cmd_payload_fragment_mask, + output io_inputs_1_rsp_valid, + input io_inputs_1_rsp_ready, + output io_inputs_1_rsp_payload_last, + output [0:0] io_inputs_1_rsp_payload_fragment_opcode, + output [31:0] io_inputs_1_rsp_payload_fragment_data, + output io_output_cmd_valid, + input io_output_cmd_ready, + output io_output_cmd_payload_last, + output [0:0] io_output_cmd_payload_fragment_source, + output [0:0] io_output_cmd_payload_fragment_opcode, + output [31:0] io_output_cmd_payload_fragment_address, + output [5:0] io_output_cmd_payload_fragment_length, + output [31:0] io_output_cmd_payload_fragment_data, + output [3:0] io_output_cmd_payload_fragment_mask, + output [0:0] io_output_cmd_payload_fragment_context, + input io_output_rsp_valid, + output io_output_rsp_ready, + input io_output_rsp_payload_last, + input [0:0] io_output_rsp_payload_fragment_source, + input [0:0] io_output_rsp_payload_fragment_opcode, + input [31:0] io_output_rsp_payload_fragment_data, + input [0:0] io_output_rsp_payload_fragment_context, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire memory_arbiter_io_inputs_0_ready; + wire memory_arbiter_io_inputs_1_ready; + wire memory_arbiter_io_output_valid; + wire memory_arbiter_io_output_payload_last; + wire [0:0] memory_arbiter_io_output_payload_fragment_source; + wire [0:0] memory_arbiter_io_output_payload_fragment_opcode; + wire [31:0] memory_arbiter_io_output_payload_fragment_address; + wire [5:0] memory_arbiter_io_output_payload_fragment_length; + wire [31:0] memory_arbiter_io_output_payload_fragment_data; + wire [3:0] memory_arbiter_io_output_payload_fragment_mask; + wire [0:0] memory_arbiter_io_output_payload_fragment_context; + wire [0:0] memory_arbiter_io_chosen; + wire [1:0] memory_arbiter_io_chosenOH; + wire [1:0] _zz_io_output_cmd_payload_fragment_source; + reg _zz_io_output_rsp_ready; + wire [0:0] memory_rspSel; + + assign _zz_io_output_cmd_payload_fragment_source = {memory_arbiter_io_output_payload_fragment_source,memory_arbiter_io_chosen}; + StreamArbiter memory_arbiter ( + .io_inputs_0_valid (io_inputs_0_cmd_valid ), //i + .io_inputs_0_ready (memory_arbiter_io_inputs_0_ready ), //o + .io_inputs_0_payload_last (io_inputs_0_cmd_payload_last ), //i + .io_inputs_0_payload_fragment_source (1'b0 ), //i + .io_inputs_0_payload_fragment_opcode (io_inputs_0_cmd_payload_fragment_opcode ), //i + .io_inputs_0_payload_fragment_address (io_inputs_0_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_0_payload_fragment_length (io_inputs_0_cmd_payload_fragment_length[5:0] ), //i + .io_inputs_0_payload_fragment_data (io_inputs_0_cmd_payload_fragment_data[31:0] ), //i + .io_inputs_0_payload_fragment_mask (io_inputs_0_cmd_payload_fragment_mask[3:0] ), //i + .io_inputs_0_payload_fragment_context (io_inputs_0_cmd_payload_fragment_context ), //i + .io_inputs_1_valid (io_inputs_1_cmd_valid ), //i + .io_inputs_1_ready (memory_arbiter_io_inputs_1_ready ), //o + .io_inputs_1_payload_last (io_inputs_1_cmd_payload_last ), //i + .io_inputs_1_payload_fragment_source (1'b0 ), //i + .io_inputs_1_payload_fragment_opcode (io_inputs_1_cmd_payload_fragment_opcode ), //i + .io_inputs_1_payload_fragment_address (io_inputs_1_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_1_payload_fragment_length (io_inputs_1_cmd_payload_fragment_length[5:0] ), //i + .io_inputs_1_payload_fragment_data (io_inputs_1_cmd_payload_fragment_data[31:0] ), //i + .io_inputs_1_payload_fragment_mask (io_inputs_1_cmd_payload_fragment_mask[3:0] ), //i + .io_inputs_1_payload_fragment_context (1'b0 ), //i + .io_output_valid (memory_arbiter_io_output_valid ), //o + .io_output_ready (io_output_cmd_ready ), //i + .io_output_payload_last (memory_arbiter_io_output_payload_last ), //o + .io_output_payload_fragment_source (memory_arbiter_io_output_payload_fragment_source ), //o + .io_output_payload_fragment_opcode (memory_arbiter_io_output_payload_fragment_opcode ), //o + .io_output_payload_fragment_address (memory_arbiter_io_output_payload_fragment_address[31:0]), //o + .io_output_payload_fragment_length (memory_arbiter_io_output_payload_fragment_length[5:0] ), //o + .io_output_payload_fragment_data (memory_arbiter_io_output_payload_fragment_data[31:0] ), //o + .io_output_payload_fragment_mask (memory_arbiter_io_output_payload_fragment_mask[3:0] ), //o + .io_output_payload_fragment_context (memory_arbiter_io_output_payload_fragment_context ), //o + .io_chosen (memory_arbiter_io_chosen ), //o + .io_chosenOH (memory_arbiter_io_chosenOH[1:0] ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + always @(*) begin + case(memory_rspSel) + 1'b0 : _zz_io_output_rsp_ready = io_inputs_0_rsp_ready; + default : _zz_io_output_rsp_ready = io_inputs_1_rsp_ready; + endcase + end + + assign io_inputs_0_cmd_ready = memory_arbiter_io_inputs_0_ready; + assign io_inputs_1_cmd_ready = memory_arbiter_io_inputs_1_ready; + assign io_output_cmd_valid = memory_arbiter_io_output_valid; + assign io_output_cmd_payload_last = memory_arbiter_io_output_payload_last; + assign io_output_cmd_payload_fragment_opcode = memory_arbiter_io_output_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = memory_arbiter_io_output_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = memory_arbiter_io_output_payload_fragment_length; + assign io_output_cmd_payload_fragment_data = memory_arbiter_io_output_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = memory_arbiter_io_output_payload_fragment_mask; + assign io_output_cmd_payload_fragment_context = memory_arbiter_io_output_payload_fragment_context; + assign io_output_cmd_payload_fragment_source = _zz_io_output_cmd_payload_fragment_source[0:0]; + assign memory_rspSel = io_output_rsp_payload_fragment_source[0 : 0]; + assign io_inputs_0_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b0)); + assign io_inputs_0_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_0_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_0_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_inputs_0_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; + assign io_inputs_1_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b1)); + assign io_inputs_1_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_1_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_1_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_output_rsp_ready = _zz_io_output_rsp_ready; + +endmodule + +module BmbDecoder_1 ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [31:0] io_input_cmd_payload_fragment_address, + input [5:0] io_input_cmd_payload_fragment_length, + output io_input_rsp_valid, + input io_input_rsp_ready, + output io_input_rsp_payload_last, + output [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output io_outputs_0_cmd_valid, + input io_outputs_0_cmd_ready, + output io_outputs_0_cmd_payload_last, + output [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output [31:0] io_outputs_0_cmd_payload_fragment_address, + output [5:0] io_outputs_0_cmd_payload_fragment_length, + input io_outputs_0_rsp_valid, + output io_outputs_0_rsp_ready, + input io_outputs_0_rsp_payload_last, + input [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input [31:0] io_outputs_0_rsp_payload_fragment_data +); + + + assign io_outputs_0_cmd_valid = io_input_cmd_valid; + assign io_input_cmd_ready = io_outputs_0_cmd_ready; + assign io_input_rsp_valid = io_outputs_0_rsp_valid; + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign io_outputs_0_cmd_payload_last = io_input_cmd_payload_last; + assign io_input_rsp_payload_last = io_outputs_0_rsp_payload_last; + assign io_outputs_0_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + +endmodule + +module BmbExclusiveMonitor ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [31:0] io_input_cmd_payload_fragment_address, + input [5:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_mask, + input [0:0] io_input_cmd_payload_fragment_context, + output io_input_rsp_valid, + input io_input_rsp_ready, + output io_input_rsp_payload_last, + output [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output [0:0] io_input_rsp_payload_fragment_context, + output io_output_cmd_valid, + input io_output_cmd_ready, + output io_output_cmd_payload_last, + output [0:0] io_output_cmd_payload_fragment_opcode, + output [31:0] io_output_cmd_payload_fragment_address, + output [5:0] io_output_cmd_payload_fragment_length, + output [31:0] io_output_cmd_payload_fragment_data, + output [3:0] io_output_cmd_payload_fragment_mask, + output [0:0] io_output_cmd_payload_fragment_context, + input io_output_rsp_valid, + output io_output_rsp_ready, + input io_output_rsp_payload_last, + input [0:0] io_output_rsp_payload_fragment_opcode, + input [31:0] io_output_rsp_payload_fragment_data, + input [0:0] io_output_rsp_payload_fragment_context +); + + + assign io_output_cmd_valid = io_input_cmd_valid; + assign io_input_cmd_ready = io_output_cmd_ready; + assign io_input_rsp_valid = io_output_rsp_valid; + assign io_output_rsp_ready = io_input_rsp_ready; + assign io_output_cmd_payload_last = io_input_cmd_payload_last; + assign io_input_rsp_payload_last = io_output_rsp_payload_last; + assign io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign io_output_cmd_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; + +endmodule + +module BmbDecoder ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [31:0] io_input_cmd_payload_fragment_address, + input [1:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_mask, + output reg io_input_rsp_valid, + input io_input_rsp_ready, + output reg io_input_rsp_payload_last, + output reg [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output reg io_outputs_0_cmd_valid, + input io_outputs_0_cmd_ready, + output io_outputs_0_cmd_payload_last, + output [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output [31:0] io_outputs_0_cmd_payload_fragment_address, + output [1:0] io_outputs_0_cmd_payload_fragment_length, + output [31:0] io_outputs_0_cmd_payload_fragment_data, + output [3:0] io_outputs_0_cmd_payload_fragment_mask, + input io_outputs_0_rsp_valid, + output io_outputs_0_rsp_ready, + input io_outputs_0_rsp_payload_last, + input [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input [31:0] io_outputs_0_rsp_payload_fragment_data, + input io_systemClk, + input debugCd_logic_outputReset +); + + wire [6:0] _zz_logic_rspPendingCounter; + wire [6:0] _zz_logic_rspPendingCounter_1; + wire [0:0] _zz_logic_rspPendingCounter_2; + wire [6:0] _zz_logic_rspPendingCounter_3; + wire [0:0] _zz_logic_rspPendingCounter_4; + wire logic_input_valid; + reg logic_input_ready; + wire logic_input_payload_last; + wire [0:0] logic_input_payload_fragment_opcode; + wire [31:0] logic_input_payload_fragment_address; + wire [1:0] logic_input_payload_fragment_length; + wire [31:0] logic_input_payload_fragment_data; + wire [3:0] logic_input_payload_fragment_mask; + wire logic_hitsS0_0; + wire logic_noHitS0; + wire _zz_io_outputs_0_cmd_payload_last; + reg [6:0] logic_rspPendingCounter; + wire logic_input_fire; + wire io_input_rsp_fire; + wire logic_cmdWait; + wire when_BmbDecoder_l56; + reg logic_rspHits_0; + wire logic_rspPending; + wire logic_rspNoHitValid; + reg logic_rspNoHit_doIt; + wire io_input_rsp_fire_1; + wire when_BmbDecoder_l60; + wire logic_input_fire_1; + wire when_BmbDecoder_l60_1; + wire logic_input_fire_2; + reg logic_rspNoHit_singleBeatRsp; + wire logic_input_fire_3; + wire logic_input_fire_4; + wire logic_input_fire_5; + + assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); + assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); + assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; + assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; + assign logic_input_valid = io_input_cmd_valid; + assign io_input_cmd_ready = logic_input_ready; + assign logic_input_payload_last = io_input_cmd_payload_last; + assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign logic_noHitS0 = (! (logic_hitsS0_0 != 1'b0)); + assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 32'h00000fff)) == 32'h10b80000); + always @(*) begin + io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); + if(logic_cmdWait) begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; + assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; + assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + always @(*) begin + logic_input_ready = (((logic_hitsS0_0 && io_outputs_0_cmd_ready) != 1'b0) || logic_noHitS0); + if(logic_cmdWait) begin + logic_input_ready = 1'b0; + end + end + + assign logic_input_fire = (logic_input_valid && logic_input_ready); + assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); + assign logic_rspPending = (logic_rspPendingCounter != 7'h0); + assign logic_rspNoHitValid = (! (logic_rspHits_0 != 1'b0)); + assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); + assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); + assign when_BmbDecoder_l60_1 = ((logic_input_fire_1 && logic_noHitS0) && logic_input_payload_last); + assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); + always @(*) begin + io_input_rsp_valid = ((io_outputs_0_rsp_valid != 1'b0) || (logic_rspPending && logic_rspNoHitValid)); + if(logic_rspNoHit_doIt) begin + io_input_rsp_valid = 1'b1; + end + end + + always @(*) begin + io_input_rsp_payload_last = io_outputs_0_rsp_payload_last; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_last = 1'b1; + end + end + + always @(*) begin + io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_opcode = 1'b1; + end + end + + assign io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign logic_cmdWait = ((logic_rspPending && ((logic_hitsS0_0 != logic_rspHits_0) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); + always @(posedge io_systemClk) begin + if(debugCd_logic_outputReset) begin + logic_rspPendingCounter <= 7'h0; + logic_rspNoHit_doIt <= 1'b0; + end else begin + logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); + if(when_BmbDecoder_l60) begin + logic_rspNoHit_doIt <= 1'b0; + end + if(when_BmbDecoder_l60_1) begin + logic_rspNoHit_doIt <= 1'b1; + end + end + end + + always @(posedge io_systemClk) begin + if(when_BmbDecoder_l56) begin + logic_rspHits_0 <= logic_hitsS0_0; + end + if(logic_input_fire_2) begin + logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); + end + end + + +endmodule + +module BufferCC_4 ( + input io_dataIn, + output io_dataOut, + input io_systemClk, + input system_cores_0_debugReset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge io_systemClk or posedge system_cores_0_debugReset) begin + if(system_cores_0_debugReset) begin + buffers_0 <= 1'b1; + buffers_1 <= 1'b1; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module SystemDebugger ( + input io_remote_cmd_valid, + output io_remote_cmd_ready, + input io_remote_cmd_payload_last, + input [0:0] io_remote_cmd_payload_fragment, + output io_remote_rsp_valid, + input io_remote_rsp_ready, + output io_remote_rsp_payload_error, + output [31:0] io_remote_rsp_payload_data, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output io_mem_cmd_payload_wr, + output [1:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload, + input io_systemClk, + input debugCd_logic_outputReset +); + + reg [66:0] dispatcher_dataShifter; + reg dispatcher_dataLoaded; + reg [7:0] dispatcher_headerShifter; + wire [7:0] dispatcher_header; + reg dispatcher_headerLoaded; + reg [2:0] dispatcher_counter; + wire when_Fragment_l346; + wire when_Fragment_l349; + wire [66:0] _zz_io_mem_cmd_payload_address; + wire io_mem_cmd_isStall; + wire when_Fragment_l372; + + assign dispatcher_header = dispatcher_headerShifter[7 : 0]; + assign when_Fragment_l346 = (dispatcher_headerLoaded == 1'b0); + assign when_Fragment_l349 = (dispatcher_counter == 3'b111); + assign io_remote_cmd_ready = (! dispatcher_dataLoaded); + assign _zz_io_mem_cmd_payload_address = dispatcher_dataShifter[66 : 0]; + assign io_mem_cmd_payload_address = _zz_io_mem_cmd_payload_address[31 : 0]; + assign io_mem_cmd_payload_data = _zz_io_mem_cmd_payload_address[63 : 32]; + assign io_mem_cmd_payload_wr = _zz_io_mem_cmd_payload_address[64]; + assign io_mem_cmd_payload_size = _zz_io_mem_cmd_payload_address[66 : 65]; + assign io_mem_cmd_valid = (dispatcher_dataLoaded && (dispatcher_header == 8'h0)); + assign io_mem_cmd_isStall = (io_mem_cmd_valid && (! io_mem_cmd_ready)); + assign when_Fragment_l372 = ((dispatcher_headerLoaded && dispatcher_dataLoaded) && (! io_mem_cmd_isStall)); + assign io_remote_rsp_valid = io_mem_rsp_valid; + assign io_remote_rsp_payload_error = 1'b0; + assign io_remote_rsp_payload_data = io_mem_rsp_payload; + always @(posedge io_systemClk) begin + if(debugCd_logic_outputReset) begin + dispatcher_dataLoaded <= 1'b0; + dispatcher_headerLoaded <= 1'b0; + dispatcher_counter <= 3'b000; + end else begin + if(io_remote_cmd_valid) begin + if(when_Fragment_l346) begin + dispatcher_counter <= (dispatcher_counter + 3'b001); + if(when_Fragment_l349) begin + dispatcher_headerLoaded <= 1'b1; + end + end + if(io_remote_cmd_payload_last) begin + dispatcher_headerLoaded <= 1'b1; + dispatcher_dataLoaded <= 1'b1; + dispatcher_counter <= 3'b000; + end + end + if(when_Fragment_l372) begin + dispatcher_headerLoaded <= 1'b0; + dispatcher_dataLoaded <= 1'b0; + end + end + end + + always @(posedge io_systemClk) begin + if(io_remote_cmd_valid) begin + if(when_Fragment_l346) begin + dispatcher_headerShifter <= ({io_remote_cmd_payload_fragment,dispatcher_headerShifter} >>> 1); + end else begin + dispatcher_dataShifter <= ({io_remote_cmd_payload_fragment,dispatcher_dataShifter} >>> 1); + end + end + end + + +endmodule + +module JtagBridgeNoTap ( + input io_ctrl_tdi, + input io_ctrl_enable, + input io_ctrl_capture, + input io_ctrl_shift, + input io_ctrl_update, + input io_ctrl_reset, + output io_ctrl_tdo, + output io_remote_cmd_valid, + input io_remote_cmd_ready, + output io_remote_cmd_payload_last, + output [0:0] io_remote_cmd_payload_fragment, + input io_remote_rsp_valid, + output io_remote_rsp_ready, + input io_remote_rsp_payload_error, + input [31:0] io_remote_rsp_payload_data, + input io_systemClk, + input debugCd_logic_outputReset, + input jtagCtrl_tck +); + + wire flowCCByToggle_1_io_output_valid; + wire flowCCByToggle_1_io_output_payload_last; + wire [0:0] flowCCByToggle_1_io_output_payload_fragment; + wire system_cmd_valid; + wire system_cmd_payload_last; + wire [0:0] system_cmd_payload_fragment; + wire system_cmd_toStream_valid; + wire system_cmd_toStream_ready; + wire system_cmd_toStream_payload_last; + wire [0:0] system_cmd_toStream_payload_fragment; + (* async_reg = "true" *) reg system_rsp_valid; + (* async_reg = "true" *) reg system_rsp_payload_error; + (* async_reg = "true" *) reg [31:0] system_rsp_payload_data; + wire io_remote_rsp_fire; + wire jtag_wrapper_ctrl_tdi; + wire jtag_wrapper_ctrl_enable; + wire jtag_wrapper_ctrl_capture; + wire jtag_wrapper_ctrl_shift; + wire jtag_wrapper_ctrl_update; + wire jtag_wrapper_ctrl_reset; + reg jtag_wrapper_ctrl_tdo; + reg [1:0] jtag_wrapper_header; + wire [1:0] jtag_wrapper_headerNext; + reg [0:0] jtag_wrapper_counter; + reg jtag_wrapper_done; + reg jtag_wrapper_sendCapture; + reg jtag_wrapper_sendShift; + reg jtag_wrapper_sendUpdate; + wire when_JtagTapInstructions_l183; + wire when_JtagTapInstructions_l186; + wire jtag_writeArea_ctrl_tdi; + wire jtag_writeArea_ctrl_enable; + wire jtag_writeArea_ctrl_capture; + wire jtag_writeArea_ctrl_shift; + wire jtag_writeArea_ctrl_update; + wire jtag_writeArea_ctrl_reset; + wire jtag_writeArea_ctrl_tdo; + wire jtag_writeArea_source_valid; + wire jtag_writeArea_source_payload_last; + wire [0:0] jtag_writeArea_source_payload_fragment; + reg jtag_writeArea_valid; + reg jtag_writeArea_data; + wire when_JtagTapInstructions_l209; + wire jtag_readArea_ctrl_tdi; + wire jtag_readArea_ctrl_enable; + wire jtag_readArea_ctrl_capture; + wire jtag_readArea_ctrl_shift; + wire jtag_readArea_ctrl_update; + wire jtag_readArea_ctrl_reset; + wire jtag_readArea_ctrl_tdo; + reg [33:0] jtag_readArea_full_shifter; + wire when_JtagTapInstructions_l209_1; + + FlowCCByToggle flowCCByToggle_1 ( + .io_input_valid (jtag_writeArea_source_valid ), //i + .io_input_payload_last (jtag_writeArea_source_payload_last ), //i + .io_input_payload_fragment (jtag_writeArea_source_payload_fragment ), //i + .io_output_valid (flowCCByToggle_1_io_output_valid ), //o + .io_output_payload_last (flowCCByToggle_1_io_output_payload_last ), //o + .io_output_payload_fragment (flowCCByToggle_1_io_output_payload_fragment), //o + .jtagCtrl_tck (jtagCtrl_tck ), //i + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i + ); + assign system_cmd_toStream_valid = system_cmd_valid; + assign system_cmd_toStream_payload_last = system_cmd_payload_last; + assign system_cmd_toStream_payload_fragment = system_cmd_payload_fragment; + assign io_remote_cmd_valid = system_cmd_toStream_valid; + assign system_cmd_toStream_ready = io_remote_cmd_ready; + assign io_remote_cmd_payload_last = system_cmd_toStream_payload_last; + assign io_remote_cmd_payload_fragment = system_cmd_toStream_payload_fragment; + assign io_remote_rsp_fire = (io_remote_rsp_valid && io_remote_rsp_ready); + assign io_remote_rsp_ready = 1'b1; + assign jtag_wrapper_headerNext = ({jtag_wrapper_ctrl_tdi,jtag_wrapper_header} >>> 1); + always @(*) begin + jtag_wrapper_sendCapture = 1'b0; + if(jtag_wrapper_ctrl_enable) begin + if(jtag_wrapper_ctrl_shift) begin + if(when_JtagTapInstructions_l183) begin + if(when_JtagTapInstructions_l186) begin + jtag_wrapper_sendCapture = 1'b1; + end + end + end + end + end + + always @(*) begin + jtag_wrapper_sendShift = 1'b0; + if(jtag_wrapper_ctrl_enable) begin + if(jtag_wrapper_ctrl_shift) begin + if(!when_JtagTapInstructions_l183) begin + jtag_wrapper_sendShift = 1'b1; + end + end + end + end + + always @(*) begin + jtag_wrapper_sendUpdate = 1'b0; + if(jtag_wrapper_ctrl_enable) begin + if(jtag_wrapper_ctrl_update) begin + jtag_wrapper_sendUpdate = 1'b1; + end + end + end + + assign when_JtagTapInstructions_l183 = (! jtag_wrapper_done); + assign when_JtagTapInstructions_l186 = (jtag_wrapper_counter == 1'b1); + always @(*) begin + jtag_wrapper_ctrl_tdo = 1'b0; + if(when_JtagTapInstructions_l209) begin + jtag_wrapper_ctrl_tdo = jtag_writeArea_ctrl_tdo; + end + if(when_JtagTapInstructions_l209_1) begin + jtag_wrapper_ctrl_tdo = jtag_readArea_ctrl_tdo; + end + end + + assign jtag_wrapper_ctrl_tdi = io_ctrl_tdi; + assign jtag_wrapper_ctrl_enable = io_ctrl_enable; + assign jtag_wrapper_ctrl_capture = io_ctrl_capture; + assign jtag_wrapper_ctrl_shift = io_ctrl_shift; + assign jtag_wrapper_ctrl_update = io_ctrl_update; + assign jtag_wrapper_ctrl_reset = io_ctrl_reset; + assign io_ctrl_tdo = jtag_wrapper_ctrl_tdo; + assign jtag_writeArea_source_valid = jtag_writeArea_valid; + assign jtag_writeArea_source_payload_last = (! (jtag_writeArea_ctrl_enable && jtag_writeArea_ctrl_shift)); + assign jtag_writeArea_source_payload_fragment[0] = jtag_writeArea_data; + assign system_cmd_valid = flowCCByToggle_1_io_output_valid; + assign system_cmd_payload_last = flowCCByToggle_1_io_output_payload_last; + assign system_cmd_payload_fragment = flowCCByToggle_1_io_output_payload_fragment; + assign jtag_writeArea_ctrl_tdo = 1'b0; + assign when_JtagTapInstructions_l209 = (jtag_wrapper_header == 2'b00); + assign jtag_writeArea_ctrl_tdi = jtag_wrapper_ctrl_tdi; + assign jtag_writeArea_ctrl_enable = 1'b1; + assign jtag_writeArea_ctrl_capture = ((jtag_wrapper_headerNext == 2'b00) && jtag_wrapper_sendCapture); + assign jtag_writeArea_ctrl_shift = (when_JtagTapInstructions_l209 && jtag_wrapper_sendShift); + assign jtag_writeArea_ctrl_update = (when_JtagTapInstructions_l209 && jtag_wrapper_sendUpdate); + assign jtag_writeArea_ctrl_reset = jtag_wrapper_ctrl_reset; + assign jtag_readArea_ctrl_tdo = jtag_readArea_full_shifter[0]; + assign when_JtagTapInstructions_l209_1 = (jtag_wrapper_header == 2'b01); + assign jtag_readArea_ctrl_tdi = jtag_wrapper_ctrl_tdi; + assign jtag_readArea_ctrl_enable = 1'b1; + assign jtag_readArea_ctrl_capture = ((jtag_wrapper_headerNext == 2'b01) && jtag_wrapper_sendCapture); + assign jtag_readArea_ctrl_shift = (when_JtagTapInstructions_l209_1 && jtag_wrapper_sendShift); + assign jtag_readArea_ctrl_update = (when_JtagTapInstructions_l209_1 && jtag_wrapper_sendUpdate); + assign jtag_readArea_ctrl_reset = jtag_wrapper_ctrl_reset; + always @(posedge io_systemClk) begin + if(io_remote_cmd_valid) begin + system_rsp_valid <= 1'b0; + end + if(io_remote_rsp_fire) begin + system_rsp_valid <= 1'b1; + system_rsp_payload_error <= io_remote_rsp_payload_error; + system_rsp_payload_data <= io_remote_rsp_payload_data; + end + end + + always @(posedge jtagCtrl_tck) begin + if(jtag_wrapper_ctrl_enable) begin + if(jtag_wrapper_ctrl_capture) begin + jtag_wrapper_done <= 1'b0; + jtag_wrapper_counter <= 1'b0; + end + if(jtag_wrapper_ctrl_shift) begin + if(when_JtagTapInstructions_l183) begin + jtag_wrapper_counter <= (jtag_wrapper_counter + 1'b1); + jtag_wrapper_header <= jtag_wrapper_headerNext; + if(when_JtagTapInstructions_l186) begin + jtag_wrapper_done <= 1'b1; + end + end + end + end + jtag_writeArea_valid <= (jtag_writeArea_ctrl_enable && jtag_writeArea_ctrl_shift); + jtag_writeArea_data <= jtag_writeArea_ctrl_tdi; + if(jtag_readArea_ctrl_enable) begin + if(jtag_readArea_ctrl_capture) begin + jtag_readArea_full_shifter <= {{system_rsp_payload_data,system_rsp_payload_error},system_rsp_valid}; + end + if(jtag_readArea_ctrl_shift) begin + jtag_readArea_full_shifter <= ({jtag_readArea_ctrl_tdi,jtag_readArea_full_shifter} >>> 1); + end + end + end + + +endmodule + +module VexRiscv ( + output dBus_cmd_valid, + input dBus_cmd_ready, + output dBus_cmd_payload_wr, + output dBus_cmd_payload_uncached, + output [31:0] dBus_cmd_payload_address, + output [31:0] dBus_cmd_payload_data, + output [3:0] dBus_cmd_payload_mask, + output [2:0] dBus_cmd_payload_size, + output dBus_cmd_payload_last, + input dBus_rsp_valid, + input dBus_rsp_payload_last, + input [31:0] dBus_rsp_payload_data, + input dBus_rsp_payload_error, + input timerInterrupt, + input externalInterrupt, + input softwareInterrupt, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output iBus_cmd_valid, + input iBus_cmd_ready, + output reg [31:0] iBus_cmd_payload_address, + output [2:0] iBus_cmd_payload_size, + input iBus_rsp_valid, + input [31:0] iBus_rsp_payload_data, + input iBus_rsp_payload_error, + input io_systemClk, + input systemCd_logic_outputReset, + input debugCd_logic_outputReset +); + localparam ShiftCtrlEnum_DISABLE_1 = 2'd0; + localparam ShiftCtrlEnum_SLL_1 = 2'd1; + localparam ShiftCtrlEnum_SRL_1 = 2'd2; + localparam ShiftCtrlEnum_SRA_1 = 2'd3; + localparam BranchCtrlEnum_INC = 2'd0; + localparam BranchCtrlEnum_B = 2'd1; + localparam BranchCtrlEnum_JAL = 2'd2; + localparam BranchCtrlEnum_JALR = 2'd3; + localparam EnvCtrlEnum_NONE = 2'd0; + localparam EnvCtrlEnum_XRET = 2'd1; + localparam EnvCtrlEnum_ECALL = 2'd2; + localparam EnvCtrlEnum_EBREAK = 2'd3; + localparam AluBitwiseCtrlEnum_XOR_1 = 2'd0; + localparam AluBitwiseCtrlEnum_OR_1 = 2'd1; + localparam AluBitwiseCtrlEnum_AND_1 = 2'd2; + localparam AluCtrlEnum_ADD_SUB = 2'd0; + localparam AluCtrlEnum_SLT_SLTU = 2'd1; + localparam AluCtrlEnum_BITWISE = 2'd2; + localparam Src2CtrlEnum_RS = 2'd0; + localparam Src2CtrlEnum_IMI = 2'd1; + localparam Src2CtrlEnum_IMS = 2'd2; + localparam Src2CtrlEnum_PC = 2'd3; + localparam Src1CtrlEnum_RS = 2'd0; + localparam Src1CtrlEnum_IMU = 2'd1; + localparam Src1CtrlEnum_PC_INCREMENT = 2'd2; + localparam Src1CtrlEnum_URS1 = 2'd3; + + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + wire dataCache_1_io_cpu_execute_isValid; + wire [31:0] dataCache_1_io_cpu_execute_address; + wire dataCache_1_io_cpu_memory_isValid; + reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; + reg dataCache_1_io_cpu_writeBack_isValid; + wire dataCache_1_io_cpu_writeBack_isUser; + wire [31:0] dataCache_1_io_cpu_writeBack_storeData; + wire [31:0] dataCache_1_io_cpu_writeBack_address; + wire dataCache_1_io_cpu_writeBack_fence_SW; + wire dataCache_1_io_cpu_writeBack_fence_SR; + wire dataCache_1_io_cpu_writeBack_fence_SO; + wire dataCache_1_io_cpu_writeBack_fence_SI; + wire dataCache_1_io_cpu_writeBack_fence_PW; + wire dataCache_1_io_cpu_writeBack_fence_PR; + wire dataCache_1_io_cpu_writeBack_fence_PO; + wire dataCache_1_io_cpu_writeBack_fence_PI; + wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; + wire dataCache_1_io_cpu_flush_valid; + wire dataCache_1_io_cpu_flush_payload_singleLine; + wire [5:0] dataCache_1_io_cpu_flush_payload_lineId; + wire dataCache_1_io_mem_cmd_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_writeBack_exclusiveOk; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_size; + wire dataCache_1_io_mem_cmd_payload_last; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [13:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [7:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [1:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [2:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_4; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [25:0] _zz_io_cpu_flush_payload_lineId; + wire [25:0] _zz_io_cpu_flush_payload_lineId_1; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; + wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_1; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_2; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_3; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_4; + wire _zz__zz_decode_BRANCH_CTRL_2_5; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_6; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_7; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_8; + wire _zz__zz_decode_BRANCH_CTRL_2_9; + wire _zz__zz_decode_BRANCH_CTRL_2_10; + wire [26:0] _zz__zz_decode_BRANCH_CTRL_2_11; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_12; + wire _zz__zz_decode_BRANCH_CTRL_2_13; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_14; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_15; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_16; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_17; + wire [22:0] _zz__zz_decode_BRANCH_CTRL_2_18; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_19; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_20; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_21; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_22; + wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_23; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_24; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_25; + wire _zz__zz_decode_BRANCH_CTRL_2_26; + wire _zz__zz_decode_BRANCH_CTRL_2_27; + wire _zz__zz_decode_BRANCH_CTRL_2_28; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_29; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_30; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_31; + wire _zz__zz_decode_BRANCH_CTRL_2_32; + wire [18:0] _zz__zz_decode_BRANCH_CTRL_2_33; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_34; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_35; + wire _zz__zz_decode_BRANCH_CTRL_2_36; + wire _zz__zz_decode_BRANCH_CTRL_2_37; + wire _zz__zz_decode_BRANCH_CTRL_2_38; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_39; + wire _zz__zz_decode_BRANCH_CTRL_2_40; + wire [15:0] _zz__zz_decode_BRANCH_CTRL_2_41; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_42; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_43; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_44; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_45; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_46; + wire _zz__zz_decode_BRANCH_CTRL_2_47; + wire _zz__zz_decode_BRANCH_CTRL_2_48; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_49; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_50; + wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_51; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_52; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_53; + wire _zz__zz_decode_BRANCH_CTRL_2_54; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_55; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_56; + wire _zz__zz_decode_BRANCH_CTRL_2_57; + wire [12:0] _zz__zz_decode_BRANCH_CTRL_2_58; + wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_59; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_60; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_61; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_62; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_63; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_64; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_65; + wire _zz__zz_decode_BRANCH_CTRL_2_66; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_67; + wire _zz__zz_decode_BRANCH_CTRL_2_68; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_69; + wire _zz__zz_decode_BRANCH_CTRL_2_70; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_71; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_72; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_73; + wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_74; + wire _zz__zz_decode_BRANCH_CTRL_2_75; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_76; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_77; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_78; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_79; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_80; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_81; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_82; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_83; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_84; + wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_85; + wire _zz__zz_decode_BRANCH_CTRL_2_86; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_87; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_88; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_89; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_90; + wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_91; + wire _zz__zz_decode_BRANCH_CTRL_2_92; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_93; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_94; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_95; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_96; + wire [9:0] _zz__zz_decode_BRANCH_CTRL_2_97; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_98; + wire _zz__zz_decode_BRANCH_CTRL_2_99; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_100; + wire _zz__zz_decode_BRANCH_CTRL_2_101; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_102; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_103; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_104; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_105; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_106; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_107; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_108; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_109; + wire [6:0] _zz__zz_decode_BRANCH_CTRL_2_110; + wire _zz__zz_decode_BRANCH_CTRL_2_111; + wire _zz__zz_decode_BRANCH_CTRL_2_112; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_113; + wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_114; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_115; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_116; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_117; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_118; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_119; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_120; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_121; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_122; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_123; + wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_124; + wire _zz__zz_decode_BRANCH_CTRL_2_125; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_126; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_127; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_128; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_129; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_130; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_131; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_132; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_133; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_134; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_135; + wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_136; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_137; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_138; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_139; + wire _zz__zz_decode_BRANCH_CTRL_2_140; + wire _zz__zz_decode_BRANCH_CTRL_2_141; + wire _zz__zz_decode_BRANCH_CTRL_2_142; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_143; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_144; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_decode_SRC1_1; + wire [4:0] _zz__zz_decode_SRC1_1_1; + wire [11:0] _zz__zz_decode_SRC2_4; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_decode_RS2_2; + wire [31:0] _zz__zz_decode_RS2_2_1; + wire [5:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext; + wire [0:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_2; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_3; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_4; + wire [0:0] _zz_memory_MulDivIterativePlugin_div_result_5; + wire [32:0] _zz_memory_MulDivIterativePlugin_rs1_2; + wire [0:0] _zz_memory_MulDivIterativePlugin_rs1_3; + wire [31:0] _zz_memory_MulDivIterativePlugin_rs2_1; + wire [0:0] _zz_memory_MulDivIterativePlugin_rs2_2; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire _zz_when; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire [51:0] memory_MUL_LOW; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [31:0] execute_MEMORY_VIRTUAL_ADDRESS; + wire [31:0] memory_MEMORY_STORE_DATA_RF; + wire [31:0] execute_MEMORY_STORE_DATA_RF; + wire decode_DO_EBREAK; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire [31:0] decode_SRC2; + wire [31:0] decode_SRC1; + wire decode_SRC2_FORCE_ZERO; + wire [1:0] decode_BRANCH_CTRL; + wire [1:0] _zz_decode_BRANCH_CTRL; + wire [1:0] _zz_decode_to_execute_BRANCH_CTRL; + wire [1:0] _zz_decode_to_execute_BRANCH_CTRL_1; + wire [1:0] _zz_memory_to_writeBack_ENV_CTRL; + wire [1:0] _zz_memory_to_writeBack_ENV_CTRL_1; + wire [1:0] _zz_execute_to_memory_ENV_CTRL; + wire [1:0] _zz_execute_to_memory_ENV_CTRL_1; + wire [1:0] decode_ENV_CTRL; + wire [1:0] _zz_decode_ENV_CTRL; + wire [1:0] _zz_decode_to_execute_ENV_CTRL; + wire [1:0] _zz_decode_to_execute_ENV_CTRL_1; + wire decode_IS_CSR; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire decode_IS_MUL; + wire [1:0] _zz_execute_to_memory_SHIFT_CTRL; + wire [1:0] _zz_execute_to_memory_SHIFT_CTRL_1; + wire [1:0] decode_SHIFT_CTRL; + wire [1:0] _zz_decode_SHIFT_CTRL; + wire [1:0] _zz_decode_to_execute_SHIFT_CTRL; + wire [1:0] _zz_decode_to_execute_SHIFT_CTRL_1; + wire [1:0] decode_ALU_BITWISE_CTRL; + wire [1:0] _zz_decode_ALU_BITWISE_CTRL; + wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire [1:0] decode_ALU_CTRL; + wire [1:0] _zz_decode_ALU_CTRL; + wire [1:0] _zz_decode_to_execute_ALU_CTRL; + wire [1:0] _zz_decode_to_execute_ALU_CTRL_1; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + wire [1:0] execute_BRANCH_CTRL; + wire [1:0] _zz_execute_BRANCH_CTRL; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire [1:0] memory_ENV_CTRL; + wire [1:0] _zz_memory_ENV_CTRL; + wire [1:0] execute_ENV_CTRL; + wire [1:0] _zz_execute_ENV_CTRL; + wire [1:0] writeBack_ENV_CTRL; + wire [1:0] _zz_writeBack_ENV_CTRL; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + wire execute_IS_MUL; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_decode_RS2; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_decode_RS2_1; + wire [1:0] memory_SHIFT_CTRL; + wire [1:0] _zz_memory_SHIFT_CTRL; + wire [1:0] execute_SHIFT_CTRL; + wire [1:0] _zz_execute_SHIFT_CTRL; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_decode_SRC2; + wire [31:0] _zz_decode_SRC2_1; + wire [1:0] decode_SRC2_CTRL; + wire [1:0] _zz_decode_SRC2_CTRL; + wire [31:0] _zz_decode_SRC1; + wire [1:0] decode_SRC1_CTRL; + wire [1:0] _zz_decode_SRC1_CTRL; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire [1:0] execute_ALU_CTRL; + wire [1:0] _zz_execute_ALU_CTRL; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire [1:0] execute_ALU_BITWISE_CTRL; + wire [1:0] _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire [1:0] _zz_decode_BRANCH_CTRL_1; + wire [1:0] _zz_decode_ENV_CTRL_1; + wire [1:0] _zz_decode_SHIFT_CTRL_1; + wire [1:0] _zz_decode_ALU_BITWISE_CTRL_1; + wire [1:0] _zz_decode_SRC2_CTRL_1; + wire [1:0] _zz_decode_ALU_CTRL_1; + wire [1:0] _zz_decode_SRC1_CTRL_1; + reg [31:0] _zz_decode_RS2_2; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_MEMORY_STORE_DATA_RF; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire memory_MEMORY_ENABLE; + wire [31:0] memory_MEMORY_VIRTUAL_ADDRESS; + wire execute_MEMORY_FORCE_CONSTISTENCY; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_MANAGMENT; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; + wire [31:0] decode_PC; + wire [31:0] decode_INSTRUCTION; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + reg decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + wire IBusCachedPlugin_forceNoDecodeCond; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_isPaging; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_isPaging; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + reg _zz_when_DBusCachedPlugin_l393; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; + wire CsrPlugin_inWfi /* verilator public */ ; + reg CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + reg CsrPlugin_allowEbreakException; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg BranchPlugin_inDebugNoFetchFlag; + reg IBusCachedPlugin_injectionPort_valid; + reg IBusCachedPlugin_injectionPort_ready; + wire [31:0] IBusCachedPlugin_injectionPort_payload; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l134; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l134_1; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l161; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l243; + wire IBusCachedPlugin_injector_decodeInput_valid; + wire IBusCachedPlugin_injector_decodeInput_ready; + wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_pc; + wire IBusCachedPlugin_injector_decodeInput_payload_rsp_error; + wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + wire IBusCachedPlugin_injector_decodeInput_payload_isRvc; + reg _zz_IBusCachedPlugin_injector_decodeInput_valid; + reg [31:0] _zz_IBusCachedPlugin_injector_decodeInput_payload_pc; + reg _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error; + reg [31:0] _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + reg _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc; + wire when_Fetcher_l323; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l332; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l332_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l332_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l332_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire when_Fetcher_l332_4; + reg IBusCachedPlugin_injector_nextPcCalc_valids_5; + wire when_Fetcher_l332_5; + reg [31:0] IBusCachedPlugin_injector_formal_rawInDecode; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + reg dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_rValid; + reg dataCache_1_io_mem_cmd_rData_wr; + reg dataCache_1_io_mem_cmd_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_rData_size; + reg dataCache_1_io_mem_cmd_rData_last; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire when_Stream_l368; + reg dBus_rsp_regNext_valid; + reg dBus_rsp_regNext_payload_last; + reg [31:0] dBus_rsp_regNext_payload_data; + reg dBus_rsp_regNext_payload_error; + reg [31:0] DBusCachedPlugin_rspCounter; + wire when_DBusCachedPlugin_l308; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; + wire dataCache_1_io_cpu_flush_isStall; + wire when_DBusCachedPlugin_l350; + wire when_DBusCachedPlugin_l366; + wire when_DBusCachedPlugin_l393; + wire when_DBusCachedPlugin_l446; + wire when_DBusCachedPlugin_l466; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire [31:0] writeBack_DBusCachedPlugin_rspRf; + wire [1:0] switch_Misc_l210; + wire _zz_writeBack_DBusCachedPlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; + wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire when_DBusCachedPlugin_l492; + wire [32:0] _zz_decode_BRANCH_CTRL_2; + wire _zz_decode_BRANCH_CTRL_3; + wire _zz_decode_BRANCH_CTRL_4; + wire _zz_decode_BRANCH_CTRL_5; + wire _zz_decode_BRANCH_CTRL_6; + wire _zz_decode_BRANCH_CTRL_7; + wire _zz_decode_BRANCH_CTRL_8; + wire [1:0] _zz_decode_SRC1_CTRL_2; + wire [1:0] _zz_decode_ALU_CTRL_2; + wire [1:0] _zz_decode_SRC2_CTRL_2; + wire [1:0] _zz_decode_ALU_BITWISE_CTRL_2; + wire [1:0] _zz_decode_SHIFT_CTRL_2; + wire [1:0] _zz_decode_ENV_CTRL_2; + wire [1:0] _zz_decode_BRANCH_CTRL_9; + wire when_RegFilePlugin_l63; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_2; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_decode_SRC1_1; + wire _zz_decode_SRC2_2; + reg [19:0] _zz_decode_SRC2_3; + wire _zz_decode_SRC2_4; + reg [19:0] _zz_decode_SRC2_5; + reg [31:0] _zz_decode_SRC2_6; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_decode_RS2_3; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + reg [0:0] execute_MulPlugin_delayLogic_counter; + wire when_MulPlugin_l65; + wire when_MulPlugin_l70; + wire [1:0] switch_MulPlugin_l87; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + reg [31:0] execute_MulPlugin_withOuputBuffer_mul_ll; + reg [33:0] execute_MulPlugin_withOuputBuffer_mul_lh; + reg [33:0] execute_MulPlugin_withOuputBuffer_mul_hl; + reg [33:0] execute_MulPlugin_withOuputBuffer_mul_hh; + wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; + reg [32:0] memory_MulDivIterativePlugin_rs1; + reg [31:0] memory_MulDivIterativePlugin_rs2; + reg [64:0] memory_MulDivIterativePlugin_accumulator; + wire memory_MulDivIterativePlugin_frontendOk; + reg memory_MulDivIterativePlugin_div_needRevert; + reg memory_MulDivIterativePlugin_div_counter_willIncrement; + reg memory_MulDivIterativePlugin_div_counter_willClear; + reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext; + reg [5:0] memory_MulDivIterativePlugin_div_counter_value; + wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; + wire memory_MulDivIterativePlugin_div_counter_willOverflow; + reg memory_MulDivIterativePlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; + reg [31:0] memory_MulDivIterativePlugin_div_result; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_MulDivIterativePlugin_rs2; + wire _zz_memory_MulDivIterativePlugin_rs1; + reg [32:0] _zz_memory_MulDivIterativePlugin_rs1_1; + reg [1:0] CsrPlugin_misa_base; + reg [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle; + reg [63:0] CsrPlugin_minstret; + wire _zz_when_CsrPlugin_l965; + wire _zz_when_CsrPlugin_l965_1; + wire _zz_when_CsrPlugin_l965_2; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire when_CsrPlugin_l922; + wire when_CsrPlugin_l922_1; + wire when_CsrPlugin_l922_2; + wire when_CsrPlugin_l922_3; + wire when_CsrPlugin_l935; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l959; + wire when_CsrPlugin_l965; + wire when_CsrPlugin_l965_1; + wire when_CsrPlugin_l965_2; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l993; + wire when_CsrPlugin_l993_1; + wire when_CsrPlugin_l993_2; + wire when_CsrPlugin_l998; + reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l1004; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1032; + wire when_CsrPlugin_l1077; + wire [1:0] switch_CsrPlugin_l1081; + reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1129; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire when_CsrPlugin_l1142; + wire when_CsrPlugin_l1149; + wire when_CsrPlugin_l1150; + wire when_CsrPlugin_l1157; + wire when_CsrPlugin_l1167; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + wire switch_Misc_l210_1; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1189; + wire when_CsrPlugin_l1193; + wire [11:0] execute_CsrPlugin_csrAddress; + wire execute_BranchPlugin_eq; + wire [2:0] switch_Misc_l210_2; + reg _zz_execute_BRANCH_DO; + reg _zz_execute_BRANCH_DO_1; + wire [31:0] execute_BranchPlugin_branch_src1; + wire _zz_execute_BranchPlugin_branch_src2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; + reg [31:0] _zz_execute_BranchPlugin_branch_src2_6; + wire [31:0] execute_BranchPlugin_branch_src2; + wire [31:0] execute_BranchPlugin_branchAdder; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + wire when_DebugPlugin_l225; + reg DebugPlugin_haltedByBreak; + reg DebugPlugin_debugUsed /* verilator public */ ; + reg DebugPlugin_disableEbreak; + wire DebugPlugin_allowEBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_when_DebugPlugin_l244; + wire when_DebugPlugin_l244; + wire [5:0] switch_DebugPlugin_l267; + wire when_DebugPlugin_l271; + wire when_DebugPlugin_l271_1; + wire when_DebugPlugin_l272; + wire when_DebugPlugin_l272_1; + wire when_DebugPlugin_l273; + wire when_DebugPlugin_l274; + wire when_DebugPlugin_l275; + wire when_DebugPlugin_l275_1; + wire when_DebugPlugin_l295; + wire when_DebugPlugin_l298; + wire when_DebugPlugin_l311; + reg DebugPlugin_resetIt_regNext; + wire when_DebugPlugin_l331; + wire when_Pipeline_l124; + reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; + reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; + reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; + reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; + reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; + reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + wire when_Pipeline_l124_10; + reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_11; + reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_12; + reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_13; + reg memory_to_writeBack_MEMORY_ENABLE; + wire when_Pipeline_l124_14; + reg [1:0] decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_15; + reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_16; + reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_17; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_19; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_20; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_21; + reg decode_to_execute_MEMORY_WR; + wire when_Pipeline_l124_22; + reg execute_to_memory_MEMORY_WR; + wire when_Pipeline_l124_23; + reg memory_to_writeBack_MEMORY_WR; + wire when_Pipeline_l124_24; + reg decode_to_execute_MEMORY_MANAGMENT; + wire when_Pipeline_l124_25; + reg decode_to_execute_SRC_LESS_UNSIGNED; + wire when_Pipeline_l124_26; + reg [1:0] decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_27; + reg [1:0] decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_28; + reg [1:0] execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_29; + reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_30; + reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_31; + reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_32; + reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_33; + reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_34; + reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_35; + reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_36; + reg decode_to_execute_IS_CSR; + wire when_Pipeline_l124_37; + reg [1:0] decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_38; + reg [1:0] execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_39; + reg [1:0] memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_40; + reg [1:0] decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_41; + reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_42; + reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_43; + reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_44; + reg [31:0] decode_to_execute_SRC1; + wire when_Pipeline_l124_45; + reg [31:0] decode_to_execute_SRC2; + wire when_Pipeline_l124_46; + reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_47; + reg decode_to_execute_CSR_READ_OPCODE; + wire when_Pipeline_l124_48; + reg decode_to_execute_DO_EBREAK; + wire when_Pipeline_l124_49; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_50; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_51; + (* keep , syn_keep *) reg [31:0] execute_to_memory_MEMORY_VIRTUAL_ADDRESS /* synthesis syn_keep = 1 */ ; + wire when_Pipeline_l124_52; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_53; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_54; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + wire when_Pipeline_l124_55; + reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_56; + reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_57; + reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_58; + reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_59; + reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_60; + reg execute_to_memory_BRANCH_DO; + wire when_Pipeline_l124_61; + reg [31:0] execute_to_memory_BRANCH_CALC; + wire when_Pipeline_l124_62; + reg [51:0] memory_to_writeBack_MUL_LOW; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + reg [2:0] switch_Fetcher_l365; + wire when_Fetcher_l381; + wire when_Fetcher_l401; + wire when_CsrPlugin_l1277; + reg execute_CsrPlugin_csr_3860; + wire when_CsrPlugin_l1277_1; + reg execute_CsrPlugin_csr_769; + wire when_CsrPlugin_l1277_2; + reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1277_3; + reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1277_4; + reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1277_5; + reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1277_6; + reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1277_7; + reg execute_CsrPlugin_csr_832; + wire when_CsrPlugin_l1277_8; + reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1277_9; + reg execute_CsrPlugin_csr_835; + wire [1:0] switch_CsrPlugin_l723; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + wire when_CsrPlugin_l1310; + wire when_CsrPlugin_l1315; + `ifndef SYNTHESIS + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [47:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [47:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [47:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [47:0] _zz_execute_to_memory_ENV_CTRL_1_string; + reg [47:0] decode_ENV_CTRL_string; + reg [47:0] _zz_decode_ENV_CTRL_string; + reg [47:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [47:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; + reg [47:0] memory_ENV_CTRL_string; + reg [47:0] _zz_memory_ENV_CTRL_string; + reg [47:0] execute_ENV_CTRL_string; + reg [47:0] _zz_execute_ENV_CTRL_string; + reg [47:0] writeBack_ENV_CTRL_string; + reg [47:0] _zz_writeBack_ENV_CTRL_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_execute_ALU_CTRL_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [47:0] _zz_decode_ENV_CTRL_1_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [47:0] _zz_decode_ENV_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_9_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [47:0] decode_to_execute_ENV_CTRL_string; + reg [47:0] execute_to_memory_ENV_CTRL_string; + reg [47:0] memory_to_writeBack_ENV_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + `endif + + reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == ShiftCtrlEnum_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 3'b001); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz_io_cpu_flush_payload_lineId = _zz_io_cpu_flush_payload_lineId_1; + assign _zz_io_cpu_flush_payload_lineId_1 = (execute_RS1 >>> 6); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_decode_SRC1_1 = 3'b100; + assign _zz__zz_decode_SRC1_1_1 = decode_INSTRUCTION[19 : 15]; + assign _zz__zz_decode_SRC2_4 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1 = memory_MulDivIterativePlugin_div_counter_willIncrement; + assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext = {5'd0, _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1}; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_MulDivIterativePlugin_rs2}; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator = {_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_MulDivIterativePlugin_div_result_1 = _zz_memory_MulDivIterativePlugin_div_result_2; + assign _zz_memory_MulDivIterativePlugin_div_result_2 = _zz_memory_MulDivIterativePlugin_div_result_3; + assign _zz_memory_MulDivIterativePlugin_div_result_3 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_memory_MulDivIterativePlugin_div_result) : _zz_memory_MulDivIterativePlugin_div_result)} + _zz_memory_MulDivIterativePlugin_div_result_4); + assign _zz_memory_MulDivIterativePlugin_div_result_5 = memory_MulDivIterativePlugin_div_needRevert; + assign _zz_memory_MulDivIterativePlugin_div_result_4 = {32'd0, _zz_memory_MulDivIterativePlugin_div_result_5}; + assign _zz_memory_MulDivIterativePlugin_rs1_3 = _zz_memory_MulDivIterativePlugin_rs1; + assign _zz_memory_MulDivIterativePlugin_rs1_2 = {32'd0, _zz_memory_MulDivIterativePlugin_rs1_3}; + assign _zz_memory_MulDivIterativePlugin_rs2_2 = _zz_memory_MulDivIterativePlugin_rs2; + assign _zz_memory_MulDivIterativePlugin_rs2_1 = {31'd0, _zz_memory_MulDivIterativePlugin_rs2_2}; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz__zz_execute_BranchPlugin_branch_src2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_3,_zz_IBusCachedPlugin_jump_pcLoad_payload_2}; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00001013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hfc00307f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00005033; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; + assign _zz__zz_decode_BRANCH_CTRL_2 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz__zz_decode_BRANCH_CTRL_2_1 = 32'h00000004; + assign _zz__zz_decode_BRANCH_CTRL_2_2 = (decode_INSTRUCTION & 32'h00000058); + assign _zz__zz_decode_BRANCH_CTRL_2_3 = 32'h00000040; + assign _zz__zz_decode_BRANCH_CTRL_2_4 = ((decode_INSTRUCTION & 32'h10003050) == 32'h00000050); + assign _zz__zz_decode_BRANCH_CTRL_2_5 = (|{_zz_decode_BRANCH_CTRL_8,(_zz__zz_decode_BRANCH_CTRL_2_6 == _zz__zz_decode_BRANCH_CTRL_2_7)}); + assign _zz__zz_decode_BRANCH_CTRL_2_8 = (|{_zz__zz_decode_BRANCH_CTRL_2_9,_zz__zz_decode_BRANCH_CTRL_2_10}); + assign _zz__zz_decode_BRANCH_CTRL_2_11 = {(|_zz_decode_BRANCH_CTRL_7),{(|_zz__zz_decode_BRANCH_CTRL_2_12),{_zz__zz_decode_BRANCH_CTRL_2_13,{_zz__zz_decode_BRANCH_CTRL_2_15,_zz__zz_decode_BRANCH_CTRL_2_18}}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_6 = (decode_INSTRUCTION & 32'h10403050); + assign _zz__zz_decode_BRANCH_CTRL_2_7 = 32'h10000050; + assign _zz__zz_decode_BRANCH_CTRL_2_9 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz__zz_decode_BRANCH_CTRL_2_10 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz__zz_decode_BRANCH_CTRL_2_12 = _zz_decode_BRANCH_CTRL_7; + assign _zz__zz_decode_BRANCH_CTRL_2_13 = (|((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_14) == 32'h02004020)); + assign _zz__zz_decode_BRANCH_CTRL_2_15 = (|(_zz__zz_decode_BRANCH_CTRL_2_16 == _zz__zz_decode_BRANCH_CTRL_2_17)); + assign _zz__zz_decode_BRANCH_CTRL_2_18 = {(|{_zz__zz_decode_BRANCH_CTRL_2_19,_zz__zz_decode_BRANCH_CTRL_2_21}),{(|_zz__zz_decode_BRANCH_CTRL_2_23),{_zz__zz_decode_BRANCH_CTRL_2_28,{_zz__zz_decode_BRANCH_CTRL_2_31,_zz__zz_decode_BRANCH_CTRL_2_33}}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_14 = 32'h02004064; + assign _zz__zz_decode_BRANCH_CTRL_2_16 = (decode_INSTRUCTION & 32'h02004074); + assign _zz__zz_decode_BRANCH_CTRL_2_17 = 32'h02000030; + assign _zz__zz_decode_BRANCH_CTRL_2_19 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_20) == 32'h00005010); + assign _zz__zz_decode_BRANCH_CTRL_2_21 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_22) == 32'h00005020); + assign _zz__zz_decode_BRANCH_CTRL_2_23 = {(_zz__zz_decode_BRANCH_CTRL_2_24 == _zz__zz_decode_BRANCH_CTRL_2_25),{_zz__zz_decode_BRANCH_CTRL_2_26,_zz__zz_decode_BRANCH_CTRL_2_27}}; + assign _zz__zz_decode_BRANCH_CTRL_2_28 = (|(_zz__zz_decode_BRANCH_CTRL_2_29 == _zz__zz_decode_BRANCH_CTRL_2_30)); + assign _zz__zz_decode_BRANCH_CTRL_2_31 = (|_zz__zz_decode_BRANCH_CTRL_2_32); + assign _zz__zz_decode_BRANCH_CTRL_2_33 = {(|_zz__zz_decode_BRANCH_CTRL_2_34),{_zz__zz_decode_BRANCH_CTRL_2_36,{_zz__zz_decode_BRANCH_CTRL_2_39,_zz__zz_decode_BRANCH_CTRL_2_41}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_20 = 32'h00007034; + assign _zz__zz_decode_BRANCH_CTRL_2_22 = 32'h02007064; + assign _zz__zz_decode_BRANCH_CTRL_2_24 = (decode_INSTRUCTION & 32'h40003054); + assign _zz__zz_decode_BRANCH_CTRL_2_25 = 32'h40001010; + assign _zz__zz_decode_BRANCH_CTRL_2_26 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); + assign _zz__zz_decode_BRANCH_CTRL_2_27 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); + assign _zz__zz_decode_BRANCH_CTRL_2_29 = (decode_INSTRUCTION & 32'h00000064); + assign _zz__zz_decode_BRANCH_CTRL_2_30 = 32'h00000024; + assign _zz__zz_decode_BRANCH_CTRL_2_32 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz__zz_decode_BRANCH_CTRL_2_34 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_35) == 32'h00002000); + assign _zz__zz_decode_BRANCH_CTRL_2_36 = (|{_zz__zz_decode_BRANCH_CTRL_2_37,_zz__zz_decode_BRANCH_CTRL_2_38}); + assign _zz__zz_decode_BRANCH_CTRL_2_39 = (|_zz__zz_decode_BRANCH_CTRL_2_40); + assign _zz__zz_decode_BRANCH_CTRL_2_41 = {(|_zz__zz_decode_BRANCH_CTRL_2_42),{_zz__zz_decode_BRANCH_CTRL_2_47,{_zz__zz_decode_BRANCH_CTRL_2_56,_zz__zz_decode_BRANCH_CTRL_2_58}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_35 = 32'h00003000; + assign _zz__zz_decode_BRANCH_CTRL_2_37 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz__zz_decode_BRANCH_CTRL_2_38 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz__zz_decode_BRANCH_CTRL_2_40 = ((decode_INSTRUCTION & 32'h00004048) == 32'h00004008); + assign _zz__zz_decode_BRANCH_CTRL_2_42 = {(_zz__zz_decode_BRANCH_CTRL_2_43 == _zz__zz_decode_BRANCH_CTRL_2_44),(_zz__zz_decode_BRANCH_CTRL_2_45 == _zz__zz_decode_BRANCH_CTRL_2_46)}; + assign _zz__zz_decode_BRANCH_CTRL_2_47 = (|{_zz__zz_decode_BRANCH_CTRL_2_48,{_zz__zz_decode_BRANCH_CTRL_2_49,_zz__zz_decode_BRANCH_CTRL_2_51}}); + assign _zz__zz_decode_BRANCH_CTRL_2_56 = (|_zz__zz_decode_BRANCH_CTRL_2_57); + assign _zz__zz_decode_BRANCH_CTRL_2_58 = {(|_zz__zz_decode_BRANCH_CTRL_2_59),{_zz__zz_decode_BRANCH_CTRL_2_70,{_zz__zz_decode_BRANCH_CTRL_2_83,_zz__zz_decode_BRANCH_CTRL_2_97}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_43 = (decode_INSTRUCTION & 32'h00000034); + assign _zz__zz_decode_BRANCH_CTRL_2_44 = 32'h00000020; + assign _zz__zz_decode_BRANCH_CTRL_2_45 = (decode_INSTRUCTION & 32'h00000064); + assign _zz__zz_decode_BRANCH_CTRL_2_46 = 32'h00000020; + assign _zz__zz_decode_BRANCH_CTRL_2_48 = ((decode_INSTRUCTION & 32'h00002040) == 32'h00002040); + assign _zz__zz_decode_BRANCH_CTRL_2_49 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_50) == 32'h00001040); + assign _zz__zz_decode_BRANCH_CTRL_2_51 = {(_zz__zz_decode_BRANCH_CTRL_2_52 == _zz__zz_decode_BRANCH_CTRL_2_53),{_zz__zz_decode_BRANCH_CTRL_2_54,_zz_decode_BRANCH_CTRL_4}}; + assign _zz__zz_decode_BRANCH_CTRL_2_57 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); + assign _zz__zz_decode_BRANCH_CTRL_2_59 = {(_zz__zz_decode_BRANCH_CTRL_2_60 == _zz__zz_decode_BRANCH_CTRL_2_61),{_zz_decode_BRANCH_CTRL_5,{_zz__zz_decode_BRANCH_CTRL_2_62,_zz__zz_decode_BRANCH_CTRL_2_65}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_70 = (|{_zz_decode_BRANCH_CTRL_5,{_zz__zz_decode_BRANCH_CTRL_2_71,_zz__zz_decode_BRANCH_CTRL_2_74}}); + assign _zz__zz_decode_BRANCH_CTRL_2_83 = (|{_zz__zz_decode_BRANCH_CTRL_2_84,_zz__zz_decode_BRANCH_CTRL_2_85}); + assign _zz__zz_decode_BRANCH_CTRL_2_97 = {(|_zz__zz_decode_BRANCH_CTRL_2_98),{_zz__zz_decode_BRANCH_CTRL_2_101,{_zz__zz_decode_BRANCH_CTRL_2_106,_zz__zz_decode_BRANCH_CTRL_2_110}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_50 = 32'h00001040; + assign _zz__zz_decode_BRANCH_CTRL_2_52 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_BRANCH_CTRL_2_53 = 32'h00000040; + assign _zz__zz_decode_BRANCH_CTRL_2_54 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_55) == 32'h00000040); + assign _zz__zz_decode_BRANCH_CTRL_2_60 = (decode_INSTRUCTION & 32'h00000040); + assign _zz__zz_decode_BRANCH_CTRL_2_61 = 32'h00000040; + assign _zz__zz_decode_BRANCH_CTRL_2_62 = (_zz__zz_decode_BRANCH_CTRL_2_63 == _zz__zz_decode_BRANCH_CTRL_2_64); + assign _zz__zz_decode_BRANCH_CTRL_2_65 = {_zz__zz_decode_BRANCH_CTRL_2_66,_zz__zz_decode_BRANCH_CTRL_2_68}; + assign _zz__zz_decode_BRANCH_CTRL_2_71 = (_zz__zz_decode_BRANCH_CTRL_2_72 == _zz__zz_decode_BRANCH_CTRL_2_73); + assign _zz__zz_decode_BRANCH_CTRL_2_74 = {_zz__zz_decode_BRANCH_CTRL_2_75,{_zz__zz_decode_BRANCH_CTRL_2_77,_zz__zz_decode_BRANCH_CTRL_2_80}}; + assign _zz__zz_decode_BRANCH_CTRL_2_84 = _zz_decode_BRANCH_CTRL_6; + assign _zz__zz_decode_BRANCH_CTRL_2_85 = {_zz__zz_decode_BRANCH_CTRL_2_86,{_zz__zz_decode_BRANCH_CTRL_2_88,_zz__zz_decode_BRANCH_CTRL_2_91}}; + assign _zz__zz_decode_BRANCH_CTRL_2_98 = {_zz_decode_BRANCH_CTRL_5,_zz__zz_decode_BRANCH_CTRL_2_99}; + assign _zz__zz_decode_BRANCH_CTRL_2_101 = (|{_zz__zz_decode_BRANCH_CTRL_2_102,_zz__zz_decode_BRANCH_CTRL_2_103}); + assign _zz__zz_decode_BRANCH_CTRL_2_106 = (|_zz__zz_decode_BRANCH_CTRL_2_107); + assign _zz__zz_decode_BRANCH_CTRL_2_110 = {_zz__zz_decode_BRANCH_CTRL_2_111,{_zz__zz_decode_BRANCH_CTRL_2_113,_zz__zz_decode_BRANCH_CTRL_2_124}}; + assign _zz__zz_decode_BRANCH_CTRL_2_55 = 32'h00400040; + assign _zz__zz_decode_BRANCH_CTRL_2_63 = (decode_INSTRUCTION & 32'h00004020); + assign _zz__zz_decode_BRANCH_CTRL_2_64 = 32'h00004020; + assign _zz__zz_decode_BRANCH_CTRL_2_66 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_67) == 32'h00000010); + assign _zz__zz_decode_BRANCH_CTRL_2_68 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_69) == 32'h00000020); + assign _zz__zz_decode_BRANCH_CTRL_2_72 = (decode_INSTRUCTION & 32'h00002030); + assign _zz__zz_decode_BRANCH_CTRL_2_73 = 32'h00002010; + assign _zz__zz_decode_BRANCH_CTRL_2_75 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_76) == 32'h00000010); + assign _zz__zz_decode_BRANCH_CTRL_2_77 = (_zz__zz_decode_BRANCH_CTRL_2_78 == _zz__zz_decode_BRANCH_CTRL_2_79); + assign _zz__zz_decode_BRANCH_CTRL_2_80 = (_zz__zz_decode_BRANCH_CTRL_2_81 == _zz__zz_decode_BRANCH_CTRL_2_82); + assign _zz__zz_decode_BRANCH_CTRL_2_86 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_87) == 32'h00001010); + assign _zz__zz_decode_BRANCH_CTRL_2_88 = (_zz__zz_decode_BRANCH_CTRL_2_89 == _zz__zz_decode_BRANCH_CTRL_2_90); + assign _zz__zz_decode_BRANCH_CTRL_2_91 = {_zz__zz_decode_BRANCH_CTRL_2_92,{_zz__zz_decode_BRANCH_CTRL_2_93,_zz__zz_decode_BRANCH_CTRL_2_95}}; + assign _zz__zz_decode_BRANCH_CTRL_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_100) == 32'h00000020); + assign _zz__zz_decode_BRANCH_CTRL_2_102 = _zz_decode_BRANCH_CTRL_5; + assign _zz__zz_decode_BRANCH_CTRL_2_103 = (_zz__zz_decode_BRANCH_CTRL_2_104 == _zz__zz_decode_BRANCH_CTRL_2_105); + assign _zz__zz_decode_BRANCH_CTRL_2_107 = (_zz__zz_decode_BRANCH_CTRL_2_108 == _zz__zz_decode_BRANCH_CTRL_2_109); + assign _zz__zz_decode_BRANCH_CTRL_2_111 = (|_zz__zz_decode_BRANCH_CTRL_2_112); + assign _zz__zz_decode_BRANCH_CTRL_2_113 = (|_zz__zz_decode_BRANCH_CTRL_2_114); + assign _zz__zz_decode_BRANCH_CTRL_2_124 = {_zz__zz_decode_BRANCH_CTRL_2_125,{_zz__zz_decode_BRANCH_CTRL_2_128,_zz__zz_decode_BRANCH_CTRL_2_136}}; + assign _zz__zz_decode_BRANCH_CTRL_2_67 = 32'h00000030; + assign _zz__zz_decode_BRANCH_CTRL_2_69 = 32'h02000020; + assign _zz__zz_decode_BRANCH_CTRL_2_76 = 32'h00001030; + assign _zz__zz_decode_BRANCH_CTRL_2_78 = (decode_INSTRUCTION & 32'h02002060); + assign _zz__zz_decode_BRANCH_CTRL_2_79 = 32'h00002020; + assign _zz__zz_decode_BRANCH_CTRL_2_81 = (decode_INSTRUCTION & 32'h02003020); + assign _zz__zz_decode_BRANCH_CTRL_2_82 = 32'h00000020; + assign _zz__zz_decode_BRANCH_CTRL_2_87 = 32'h00001010; + assign _zz__zz_decode_BRANCH_CTRL_2_89 = (decode_INSTRUCTION & 32'h00002010); + assign _zz__zz_decode_BRANCH_CTRL_2_90 = 32'h00002010; + assign _zz__zz_decode_BRANCH_CTRL_2_92 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); + assign _zz__zz_decode_BRANCH_CTRL_2_93 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_94) == 32'h00000004); + assign _zz__zz_decode_BRANCH_CTRL_2_95 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_96) == 32'h0); + assign _zz__zz_decode_BRANCH_CTRL_2_100 = 32'h00000070; + assign _zz__zz_decode_BRANCH_CTRL_2_104 = (decode_INSTRUCTION & 32'h00000020); + assign _zz__zz_decode_BRANCH_CTRL_2_105 = 32'h0; + assign _zz__zz_decode_BRANCH_CTRL_2_108 = (decode_INSTRUCTION & 32'h00004014); + assign _zz__zz_decode_BRANCH_CTRL_2_109 = 32'h00004010; + assign _zz__zz_decode_BRANCH_CTRL_2_112 = ((decode_INSTRUCTION & 32'h00006014) == 32'h00002010); + assign _zz__zz_decode_BRANCH_CTRL_2_114 = {(_zz__zz_decode_BRANCH_CTRL_2_115 == _zz__zz_decode_BRANCH_CTRL_2_116),{_zz_decode_BRANCH_CTRL_4,{_zz__zz_decode_BRANCH_CTRL_2_117,_zz__zz_decode_BRANCH_CTRL_2_119}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_125 = (|(_zz__zz_decode_BRANCH_CTRL_2_126 == _zz__zz_decode_BRANCH_CTRL_2_127)); + assign _zz__zz_decode_BRANCH_CTRL_2_128 = (|{_zz__zz_decode_BRANCH_CTRL_2_129,_zz__zz_decode_BRANCH_CTRL_2_131}); + assign _zz__zz_decode_BRANCH_CTRL_2_136 = {(|_zz__zz_decode_BRANCH_CTRL_2_137),{_zz__zz_decode_BRANCH_CTRL_2_140,_zz__zz_decode_BRANCH_CTRL_2_142}}; + assign _zz__zz_decode_BRANCH_CTRL_2_94 = 32'h0000000c; + assign _zz__zz_decode_BRANCH_CTRL_2_96 = 32'h00000028; + assign _zz__zz_decode_BRANCH_CTRL_2_115 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_BRANCH_CTRL_2_116 = 32'h0; + assign _zz__zz_decode_BRANCH_CTRL_2_117 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_118) == 32'h00002000); + assign _zz__zz_decode_BRANCH_CTRL_2_119 = {(_zz__zz_decode_BRANCH_CTRL_2_120 == _zz__zz_decode_BRANCH_CTRL_2_121),(_zz__zz_decode_BRANCH_CTRL_2_122 == _zz__zz_decode_BRANCH_CTRL_2_123)}; + assign _zz__zz_decode_BRANCH_CTRL_2_126 = (decode_INSTRUCTION & 32'h00000058); + assign _zz__zz_decode_BRANCH_CTRL_2_127 = 32'h0; + assign _zz__zz_decode_BRANCH_CTRL_2_129 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_130) == 32'h00000040); + assign _zz__zz_decode_BRANCH_CTRL_2_131 = {(_zz__zz_decode_BRANCH_CTRL_2_132 == _zz__zz_decode_BRANCH_CTRL_2_133),(_zz__zz_decode_BRANCH_CTRL_2_134 == _zz__zz_decode_BRANCH_CTRL_2_135)}; + assign _zz__zz_decode_BRANCH_CTRL_2_137 = {(_zz__zz_decode_BRANCH_CTRL_2_138 == _zz__zz_decode_BRANCH_CTRL_2_139),_zz_decode_BRANCH_CTRL_3}; + assign _zz__zz_decode_BRANCH_CTRL_2_140 = (|{_zz__zz_decode_BRANCH_CTRL_2_141,_zz_decode_BRANCH_CTRL_3}); + assign _zz__zz_decode_BRANCH_CTRL_2_142 = (|(_zz__zz_decode_BRANCH_CTRL_2_143 == _zz__zz_decode_BRANCH_CTRL_2_144)); + assign _zz__zz_decode_BRANCH_CTRL_2_118 = 32'h00006004; + assign _zz__zz_decode_BRANCH_CTRL_2_120 = (decode_INSTRUCTION & 32'h00005004); + assign _zz__zz_decode_BRANCH_CTRL_2_121 = 32'h00001000; + assign _zz__zz_decode_BRANCH_CTRL_2_122 = (decode_INSTRUCTION & 32'h00004050); + assign _zz__zz_decode_BRANCH_CTRL_2_123 = 32'h00004000; + assign _zz__zz_decode_BRANCH_CTRL_2_130 = 32'h00000044; + assign _zz__zz_decode_BRANCH_CTRL_2_132 = (decode_INSTRUCTION & 32'h00002014); + assign _zz__zz_decode_BRANCH_CTRL_2_133 = 32'h00002010; + assign _zz__zz_decode_BRANCH_CTRL_2_134 = (decode_INSTRUCTION & 32'h40000034); + assign _zz__zz_decode_BRANCH_CTRL_2_135 = 32'h40000030; + assign _zz__zz_decode_BRANCH_CTRL_2_138 = (decode_INSTRUCTION & 32'h00000014); + assign _zz__zz_decode_BRANCH_CTRL_2_139 = 32'h00000004; + assign _zz__zz_decode_BRANCH_CTRL_2_141 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz__zz_decode_BRANCH_CTRL_2_143 = (decode_INSTRUCTION & 32'h00005048); + assign _zz__zz_decode_BRANCH_CTRL_2_144 = 32'h00001008; + always @(posedge io_systemClk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_1) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0]), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0]), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i + .io_cpu_execute_address (dataCache_1_io_cpu_execute_address[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (memory_MEMORY_VIRTUAL_ADDRESS[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0]), //i + .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isFiring (writeBack_arbitration_isFiring ), //i + .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData[31:0] ), //i + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i + .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i + .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i + .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i + .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i + .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i + .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i + .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i + .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM[3:0] ), //i + .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_cpu_flush_payload_singleLine (dataCache_1_io_cpu_flush_payload_singleLine ), //i + .io_cpu_flush_payload_lineId (dataCache_1_io_cpu_flush_payload_lineId[5:0] ), //i + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_regNext_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_regNext_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_regNext_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_regNext_payload_error ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + always @(*) begin + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_5) + 2'b00 : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = DBusCachedPlugin_redoBranch_payload; + 2'b01 : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = CsrPlugin_jumpInterface_payload; + default : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = BranchPlugin_jumpInterface_payload; + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) + 2'b00 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; + 2'b01 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; + 2'b10 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; + default : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) + 1'b0 : _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; + default : _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(decode_BRANCH_CTRL) + BranchCtrlEnum_INC : decode_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : decode_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : decode_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_BRANCH_CTRL) + BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_BRANCH_CTRL) + BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_BRANCH_CTRL_1) + BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_memory_to_writeBack_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_memory_to_writeBack_ENV_CTRL_string = "EBREAK"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_memory_to_writeBack_ENV_CTRL_1) + EnvCtrlEnum_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + EnvCtrlEnum_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_memory_to_writeBack_ENV_CTRL_1_string = "EBREAK"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "??????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_execute_to_memory_ENV_CTRL_string = "EBREAK"; + default : _zz_execute_to_memory_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_ENV_CTRL_1) + EnvCtrlEnum_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + EnvCtrlEnum_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_execute_to_memory_ENV_CTRL_1_string = "EBREAK"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "??????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + EnvCtrlEnum_NONE : decode_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : decode_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : decode_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : decode_ENV_CTRL_string = "EBREAK"; + default : decode_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_decode_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_string = "EBREAK"; + default : _zz_decode_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_decode_to_execute_ENV_CTRL_string = "EBREAK"; + default : _zz_decode_to_execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ENV_CTRL_1) + EnvCtrlEnum_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + EnvCtrlEnum_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_decode_to_execute_ENV_CTRL_1_string = "EBREAK"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "??????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_SHIFT_CTRL_1) + ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_SHIFT_CTRL_1) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + AluCtrlEnum_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_CTRL) + AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_CTRL) + AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_CTRL_1) + AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + BranchCtrlEnum_INC : execute_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : execute_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : execute_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_execute_BRANCH_CTRL) + BranchCtrlEnum_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : _zz_execute_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + EnvCtrlEnum_NONE : memory_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : memory_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : memory_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : memory_ENV_CTRL_string = "EBREAK"; + default : memory_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_memory_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_memory_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_memory_ENV_CTRL_string = "EBREAK"; + default : _zz_memory_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + EnvCtrlEnum_NONE : execute_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : execute_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : execute_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : execute_ENV_CTRL_string = "EBREAK"; + default : execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_execute_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_execute_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_execute_ENV_CTRL_string = "EBREAK"; + default : _zz_execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + EnvCtrlEnum_NONE : writeBack_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : writeBack_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : writeBack_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : writeBack_ENV_CTRL_string = "EBREAK"; + default : writeBack_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_writeBack_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_writeBack_ENV_CTRL_string = "EBREAK"; + default : _zz_writeBack_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_memory_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_execute_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + Src2CtrlEnum_RS : decode_SRC2_CTRL_string = "RS "; + Src2CtrlEnum_IMI : decode_SRC2_CTRL_string = "IMI"; + Src2CtrlEnum_IMS : decode_SRC2_CTRL_string = "IMS"; + Src2CtrlEnum_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_SRC2_CTRL) + Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_string = "RS "; + Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + Src1CtrlEnum_RS : decode_SRC1_CTRL_string = "RS "; + Src1CtrlEnum_IMU : decode_SRC1_CTRL_string = "IMU "; + Src1CtrlEnum_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + Src1CtrlEnum_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC1_CTRL) + Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_string = "RS "; + Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + AluCtrlEnum_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_execute_ALU_CTRL) + AluCtrlEnum_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_BRANCH_CTRL_1) + BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_ENV_CTRL_1) + EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_1_string = "EBREAK"; + default : _zz_decode_ENV_CTRL_1_string = "??????"; + endcase + end + always @(*) begin + case(_zz_decode_SHIFT_CTRL_1) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_BITWISE_CTRL_1) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC2_CTRL_1) + Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_CTRL_1) + AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC1_CTRL_1) + Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC1_CTRL_2) + Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_CTRL_2) + AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC2_CTRL_2) + Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_BITWISE_CTRL_2) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_SHIFT_CTRL_2) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_ENV_CTRL_2) + EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_2_string = "EBREAK"; + default : _zz_decode_ENV_CTRL_2_string = "??????"; + endcase + end + always @(*) begin + case(_zz_decode_BRANCH_CTRL_9) + BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_9_string = "INC "; + BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_9_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_9_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_9_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_9_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + AluCtrlEnum_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + EnvCtrlEnum_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : decode_to_execute_ENV_CTRL_string = "EBREAK"; + default : decode_to_execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + EnvCtrlEnum_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : execute_to_memory_ENV_CTRL_string = "EBREAK"; + default : execute_to_memory_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + EnvCtrlEnum_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : memory_to_writeBack_ENV_CTRL_string = "EBREAK"; + default : memory_to_writeBack_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + BranchCtrlEnum_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : decode_to_execute_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + `endif + + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = _zz_execute_BRANCH_DO_1; + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = execute_MulPlugin_withOuputBuffer_mul_hh; + assign execute_MUL_HL = execute_MulPlugin_withOuputBuffer_mul_hl; + assign execute_MUL_LH = execute_MulPlugin_withOuputBuffer_mul_lh; + assign execute_MUL_LL = execute_MulPlugin_withOuputBuffer_mul_ll; + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign execute_MEMORY_VIRTUAL_ADDRESS = dataCache_1_io_cpu_execute_address; + assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; + assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; + assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_SRC2 = _zz_decode_SRC2_6; + assign decode_SRC1 = _zz_decode_SRC1_1; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_BRANCH_CTRL_2[27]; + assign decode_IS_RS2_SIGNED = _zz_decode_BRANCH_CTRL_2[26]; + assign decode_IS_RS1_SIGNED = _zz_decode_BRANCH_CTRL_2[25]; + assign decode_IS_DIV = _zz_decode_BRANCH_CTRL_2[24]; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign decode_IS_MUL = _zz_decode_BRANCH_CTRL_2[23]; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_BRANCH_CTRL_2[17]; + assign decode_MEMORY_MANAGMENT = _zz_decode_BRANCH_CTRL_2[16]; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_decode_BRANCH_CTRL_2[13]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_BRANCH_CTRL_2[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_BRANCH_CTRL_2[11]; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_decode_BRANCH_CTRL_2[30]; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PC = decode_to_execute_PC; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_RS2_USE = _zz_decode_BRANCH_CTRL_2[15]; + assign decode_RS1_USE = _zz_decode_BRANCH_CTRL_2[5]; + always @(*) begin + _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1189) begin + _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; + end + end + + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @(*) begin + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; + end + end + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; + end + end + end + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2_1; + end + end + end + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2; + end + end + end + end + + always @(*) begin + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; + end + end + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; + end + end + end + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2_1; + end + end + end + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2; + end + end + end + end + + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; + always @(*) begin + _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin + case(memory_SHIFT_CTRL) + ShiftCtrlEnum_SLL_1 : begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; + end + ShiftCtrlEnum_SRL_1, ShiftCtrlEnum_SRA_1 : begin + _zz_decode_RS2_1 = memory_SHIFT_RIGHT; + end + default : begin + end + endcase + end + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2_1 = memory_MulDivIterativePlugin_div_result; + end + end + + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_decode_SRC2 = decode_PC; + assign _zz_decode_SRC2_1 = decode_RS2; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_SRC1 = decode_RS1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_BRANCH_CTRL_2[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_BRANCH_CTRL_2[20]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = decode_to_execute_SRC2; + assign execute_SRC1 = decode_to_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_iBusRsp_output_payload_rsp_inst); + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_BRANCH_CTRL_2[10]; + if(when_RegFilePlugin_l63) begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = (|{((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}}); + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusCachedPlugin_l492) begin + _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; + end + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) + 2'b00 : begin + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; + end + default : begin + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; + end + endcase + end + end + + assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign memory_MEMORY_VIRTUAL_ADDRESS = execute_to_memory_MEMORY_VIRTUAL_ADDRESS; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign decode_MEMORY_ENABLE = _zz_decode_BRANCH_CTRL_2[4]; + assign decode_FLUSH_ALL = _zz_decode_BRANCH_CTRL_2[0]; + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(when_IBusCachedPlugin_l256) begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(when_IBusCachedPlugin_l244) begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(when_IBusCachedPlugin_l239) begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; + end + end + + always @(*) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; + end + end + + assign decode_PC = IBusCachedPlugin_injector_decodeInput_payload_pc; + assign decode_INSTRUCTION = IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @(*) begin + decode_arbitration_haltItself = 1'b0; + if(when_DBusCachedPlugin_l308) begin + decode_arbitration_haltItself = 1'b1; + end + case(switch_Fetcher_l365) + 3'b010 : begin + decode_arbitration_haltItself = 1'b1; + end + default : begin + end + endcase + end + + always @(*) begin + decode_arbitration_haltByOther = 1'b0; + if(when_HazardSimplePlugin_l113) begin + decode_arbitration_haltByOther = 1'b1; + end + if(CsrPlugin_pipelineLiberator_active) begin + decode_arbitration_haltByOther = 1'b1; + end + if(when_CsrPlugin_l1129) begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @(*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_when) begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed) begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + always @(*) begin + decode_arbitration_flushNext = 1'b0; + if(_zz_when) begin + decode_arbitration_flushNext = 1'b1; + end + end + + always @(*) begin + execute_arbitration_haltItself = 1'b0; + if(when_DBusCachedPlugin_l350) begin + execute_arbitration_haltItself = 1'b1; + end + if(when_MulPlugin_l65) begin + execute_arbitration_haltItself = 1'b1; + end + if(when_CsrPlugin_l1193) begin + if(execute_CsrPlugin_blockedBySideEffects) begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + always @(*) begin + execute_arbitration_haltByOther = 1'b0; + if(when_DBusCachedPlugin_l366) begin + execute_arbitration_haltByOther = 1'b1; + end + if(when_DebugPlugin_l295) begin + execute_arbitration_haltByOther = 1'b1; + end + end + + always @(*) begin + execute_arbitration_removeIt = 1'b0; + if(CsrPlugin_selfException_valid) begin + execute_arbitration_removeIt = 1'b1; + end + if(execute_arbitration_isFlushed) begin + execute_arbitration_removeIt = 1'b1; + end + end + + always @(*) begin + execute_arbitration_flushIt = 1'b0; + if(when_DebugPlugin_l295) begin + if(when_DebugPlugin_l298) begin + execute_arbitration_flushIt = 1'b1; + end + end + end + + always @(*) begin + execute_arbitration_flushNext = 1'b0; + if(CsrPlugin_selfException_valid) begin + execute_arbitration_flushNext = 1'b1; + end + if(when_DebugPlugin_l295) begin + if(when_DebugPlugin_l298) begin + execute_arbitration_flushNext = 1'b1; + end + end + end + + always @(*) begin + memory_arbitration_haltItself = 1'b0; + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @(*) begin + memory_arbitration_removeIt = 1'b0; + if(BranchPlugin_branchExceptionPort_valid) begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed) begin + memory_arbitration_removeIt = 1'b1; + end + end + + assign memory_arbitration_flushIt = 1'b0; + always @(*) begin + memory_arbitration_flushNext = 1'b0; + if(BranchPlugin_branchExceptionPort_valid) begin + memory_arbitration_flushNext = 1'b1; + end + if(BranchPlugin_jumpInterface_valid) begin + memory_arbitration_flushNext = 1'b1; + end + end + + always @(*) begin + writeBack_arbitration_haltItself = 1'b0; + if(when_DBusCachedPlugin_l466) begin + writeBack_arbitration_haltItself = 1'b1; + end + end + + assign writeBack_arbitration_haltByOther = 1'b0; + always @(*) begin + writeBack_arbitration_removeIt = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid) begin + writeBack_arbitration_removeIt = 1'b1; + end + if(writeBack_arbitration_isFlushed) begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + always @(*) begin + writeBack_arbitration_flushIt = 1'b0; + if(DBusCachedPlugin_redoBranch_valid) begin + writeBack_arbitration_flushIt = 1'b1; + end + end + + always @(*) begin + writeBack_arbitration_flushNext = 1'b0; + if(DBusCachedPlugin_redoBranch_valid) begin + writeBack_arbitration_flushNext = 1'b1; + end + if(DBusCachedPlugin_exceptionBus_valid) begin + writeBack_arbitration_flushNext = 1'b1; + end + if(when_CsrPlugin_l1032) begin + writeBack_arbitration_flushNext = 1'b1; + end + if(when_CsrPlugin_l1077) begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @(*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(when_CsrPlugin_l935) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(when_CsrPlugin_l1032) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(when_CsrPlugin_l1077) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(when_DebugPlugin_l295) begin + if(when_DebugPlugin_l298) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + if(DebugPlugin_haltIt) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(when_DebugPlugin_l311) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + assign IBusCachedPlugin_forceNoDecodeCond = 1'b0; + always @(*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if(when_Fetcher_l243) begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + if(IBusCachedPlugin_injector_decodeInput_valid) begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @(*) begin + _zz_when_DBusCachedPlugin_l393 = 1'b0; + if(DebugPlugin_godmode) begin + _zz_when_DBusCachedPlugin_l393 = 1'b1; + end + end + + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; + assign CsrPlugin_inWfi = 1'b0; + always @(*) begin + CsrPlugin_thirdPartyWake = 1'b0; + if(DebugPlugin_haltIt) begin + CsrPlugin_thirdPartyWake = 1'b1; + end + end + + always @(*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(when_CsrPlugin_l1032) begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(when_CsrPlugin_l1077) begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1032) begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; + end + if(when_CsrPlugin_l1077) begin + case(switch_CsrPlugin_l1081) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + always @(*) begin + CsrPlugin_forceMachineWire = 1'b0; + if(DebugPlugin_godmode) begin + CsrPlugin_forceMachineWire = 1'b1; + end + end + + always @(*) begin + CsrPlugin_allowInterrupts = 1'b1; + if(when_DebugPlugin_l331) begin + CsrPlugin_allowInterrupts = 1'b0; + end + end + + always @(*) begin + CsrPlugin_allowException = 1'b1; + if(DebugPlugin_godmode) begin + CsrPlugin_allowException = 1'b0; + end + end + + always @(*) begin + CsrPlugin_allowEbreakException = 1'b1; + if(DebugPlugin_allowEBreak) begin + CsrPlugin_allowEbreakException = 1'b0; + end + end + + always @(*) begin + BranchPlugin_inDebugNoFetchFlag = 1'b0; + if(DebugPlugin_godmode) begin + BranchPlugin_inDebugNoFetchFlag = 1'b1; + end + end + + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (((IBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hf8000000) || ((IBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hfa000000)); + assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusCachedPlugin_mmuBus_busy = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (((DBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hf8000000) || ((DBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hfa000000)); + assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusCachedPlugin_mmuBus_busy = 1'b0; + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}} != 3'b000); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[1]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[2]; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_4; + always @(*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid) begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid) begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); + always @(*) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + assign when_Fetcher_l134 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l134_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end + if(IBusCachedPlugin_jump_pcLoad_valid) begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + always @(*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid) begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid) begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + + assign when_Fetcher_l161 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @(*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_mmuBus_busy) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if(when_IBusCachedPlugin_l267) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; + end + end + + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = (IBusCachedPlugin_externalFlush || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if(IBusCachedPlugin_injector_decodeInput_valid) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + if(when_Fetcher_l323) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign when_Fetcher_l243 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign IBusCachedPlugin_iBusRsp_output_ready = ((1'b0 && (! IBusCachedPlugin_injector_decodeInput_valid)) || IBusCachedPlugin_injector_decodeInput_ready); + assign IBusCachedPlugin_injector_decodeInput_valid = _zz_IBusCachedPlugin_injector_decodeInput_valid; + assign IBusCachedPlugin_injector_decodeInput_payload_pc = _zz_IBusCachedPlugin_injector_decodeInput_payload_pc; + assign IBusCachedPlugin_injector_decodeInput_payload_rsp_error = _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error; + assign IBusCachedPlugin_injector_decodeInput_payload_rsp_inst = _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + assign IBusCachedPlugin_injector_decodeInput_payload_isRvc = _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc; + assign when_Fetcher_l323 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l332 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l332_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l332_2 = (! (! IBusCachedPlugin_injector_decodeInput_ready)); + assign when_Fetcher_l332_3 = (! execute_arbitration_isStuck); + assign when_Fetcher_l332_4 = (! memory_arbitration_isStuck); + assign when_Fetcher_l332_5 = (! writeBack_arbitration_isStuck); + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_5; + assign IBusCachedPlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); + always @(*) begin + decode_arbitration_isValid = IBusCachedPlugin_injector_decodeInput_valid; + case(switch_Fetcher_l365) + 3'b010 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b011 : begin + decode_arbitration_isValid = 1'b1; + end + default : begin + end + endcase + if(IBusCachedPlugin_forceNoDecodeCond) begin + decode_arbitration_isValid = 1'b0; + end + end + + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @(*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; + always @(*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(when_IBusCachedPlugin_l239) begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(when_IBusCachedPlugin_l244) begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(when_IBusCachedPlugin_l256) begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + always @(*) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(when_IBusCachedPlugin_l244) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(when_IBusCachedPlugin_l256) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); + always @(*) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l368) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign when_DBusCachedPlugin_l308 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; + assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD; + always @(*) begin + case(execute_DBusCachedPlugin_size) + 2'b00 : begin + _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; + end + endcase + end + + assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign dataCache_1_io_cpu_flush_payload_singleLine = (execute_INSTRUCTION[19 : 15] != 5'h0); + assign dataCache_1_io_cpu_flush_payload_lineId = _zz_io_cpu_flush_payload_lineId[5:0]; + assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); + assign when_DBusCachedPlugin_l350 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); + assign when_DBusCachedPlugin_l366 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); + assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = memory_MEMORY_VIRTUAL_ADDRESS; + assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + always @(*) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if(when_DBusCachedPlugin_l393) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; + end + end + + assign when_DBusCachedPlugin_l393 = (_zz_when_DBusCachedPlugin_l393 && (! dataCache_1_io_cpu_memory_isWrite)); + always @(*) begin + dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_arbitration_haltByOther) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b0; + end + end + + assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); + assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; + assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; + always @(*) begin + DBusCachedPlugin_redoBranch_valid = 1'b0; + if(when_DBusCachedPlugin_l446) begin + if(dataCache_1_io_cpu_redo) begin + DBusCachedPlugin_redoBranch_valid = 1'b1; + end + end + end + + assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; + always @(*) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + if(when_DBusCachedPlugin_l446) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_mmuException) begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_redo) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + end + end + end + + assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; + always @(*) begin + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(when_DBusCachedPlugin_l446) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; + end + if(dataCache_1_io_cpu_writeBack_mmuException) begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; + end + end + end + + assign when_DBusCachedPlugin_l446 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign when_DBusCachedPlugin_l466 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); + assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; + assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; + assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; + assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; + always @(*) begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; + writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; + writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; + end + + assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; + assign switch_Misc_l210 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; + end + + assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; + end + + always @(*) begin + case(switch_Misc_l210) + 2'b00 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; + end + 2'b01 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; + end + default : begin + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; + end + endcase + end + + assign when_DBusCachedPlugin_l492 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_decode_BRANCH_CTRL_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_BRANCH_CTRL_4 = ((decode_INSTRUCTION & 32'h00000018) == 32'h0); + assign _zz_decode_BRANCH_CTRL_5 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_BRANCH_CTRL_6 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_BRANCH_CTRL_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_decode_BRANCH_CTRL_8 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00100050); + assign _zz_decode_BRANCH_CTRL_2 = {(|{_zz_decode_BRANCH_CTRL_6,(_zz__zz_decode_BRANCH_CTRL_2 == _zz__zz_decode_BRANCH_CTRL_2_1)}),{(|(_zz__zz_decode_BRANCH_CTRL_2_2 == _zz__zz_decode_BRANCH_CTRL_2_3)),{(|_zz_decode_BRANCH_CTRL_8),{(|_zz__zz_decode_BRANCH_CTRL_2_4),{_zz__zz_decode_BRANCH_CTRL_2_5,{_zz__zz_decode_BRANCH_CTRL_2_8,_zz__zz_decode_BRANCH_CTRL_2_11}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_BRANCH_CTRL_2[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_BRANCH_CTRL_2[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_BRANCH_CTRL_2[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_BRANCH_CTRL_2[19 : 18]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_BRANCH_CTRL_2[22 : 21]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_BRANCH_CTRL_2[29 : 28]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; + assign _zz_decode_BRANCH_CTRL_9 = _zz_decode_BRANCH_CTRL_2[32 : 31]; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL_9; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_2) begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_2) begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_2) begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + AluBitwiseCtrlEnum_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @(*) begin + case(execute_ALU_CTRL) + AluCtrlEnum_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; + end + AluCtrlEnum_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; + end + default : begin + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; + end + endcase + end + + always @(*) begin + case(decode_SRC1_CTRL) + Src1CtrlEnum_RS : begin + _zz_decode_SRC1_1 = _zz_decode_SRC1; + end + Src1CtrlEnum_PC_INCREMENT : begin + _zz_decode_SRC1_1 = {29'd0, _zz__zz_decode_SRC1_1}; + end + Src1CtrlEnum_IMU : begin + _zz_decode_SRC1_1 = {decode_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_decode_SRC1_1 = {27'd0, _zz__zz_decode_SRC1_1_1}; + end + endcase + end + + assign _zz_decode_SRC2_2 = decode_INSTRUCTION[31]; + always @(*) begin + _zz_decode_SRC2_3[19] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[18] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[17] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[16] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[15] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[14] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[13] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[12] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[11] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[10] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[9] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[8] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[7] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[6] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[5] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[4] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[3] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[2] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[1] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[0] = _zz_decode_SRC2_2; + end + + assign _zz_decode_SRC2_4 = _zz__zz_decode_SRC2_4[11]; + always @(*) begin + _zz_decode_SRC2_5[19] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[18] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[17] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[16] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[15] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[14] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[13] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[12] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[11] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[10] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[9] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[8] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[7] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[6] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[5] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[4] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[3] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[2] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[1] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[0] = _zz_decode_SRC2_4; + end + + always @(*) begin + case(decode_SRC2_CTRL) + Src2CtrlEnum_RS : begin + _zz_decode_SRC2_6 = _zz_decode_SRC2_1; + end + Src2CtrlEnum_IMI : begin + _zz_decode_SRC2_6 = {_zz_decode_SRC2_3,decode_INSTRUCTION[31 : 20]}; + end + Src2CtrlEnum_IMS : begin + _zz_decode_SRC2_6 = {_zz_decode_SRC2_5,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_decode_SRC2_6 = _zz_decode_SRC2; + end + endcase + end + + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == ShiftCtrlEnum_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; + _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; + _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; + _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; + _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; + _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; + _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; + _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; + _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; + _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; + _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; + _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; + _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; + _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; + _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; + _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; + _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; + _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; + _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; + _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; + _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; + _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; + _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; + _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; + _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; + _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; + _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; + _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; + _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; + _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; + _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; + _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; + end + end + + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); + assign when_MulPlugin_l65 = ((execute_arbitration_isValid && execute_IS_MUL) && (execute_MulPlugin_delayLogic_counter != 1'b1)); + assign when_MulPlugin_l70 = ((! execute_arbitration_isStuck) || execute_arbitration_isStuckByOthers); + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) + 2'b01 : begin + execute_MulPlugin_aSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_aSigned = 1'b1; + end + default : begin + execute_MulPlugin_aSigned = 1'b0; + end + endcase + end + + always @(*) begin + case(switch_MulPlugin_l87) + 2'b01 : begin + execute_MulPlugin_bSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_bSigned = 1'b0; + end + default : begin + execute_MulPlugin_bSigned = 1'b0; + end + endcase + end + + assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; + assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; + assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; + assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; + assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; + assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; + assign memory_MulDivIterativePlugin_frontendOk = 1'b1; + always @(*) begin + memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin + memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @(*) begin + memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; + if(when_MulDivIterativePlugin_l162) begin + memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == 6'h21); + assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement); + always @(*) begin + if(memory_MulDivIterativePlugin_div_counter_willOverflow) begin + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; + end else begin + memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_memory_MulDivIterativePlugin_div_counter_valueNext); + end + if(memory_MulDivIterativePlugin_div_counter_willClear) begin + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; + end + end + + assign when_MulDivIterativePlugin_l126 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); + assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted = memory_MulDivIterativePlugin_rs1[31 : 0]; + assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31]}; + assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator); + assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder : _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1); + assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); + assign _zz_memory_MulDivIterativePlugin_div_result = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_MulDivIterativePlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_MulDivIterativePlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_MulDivIterativePlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_MulDivIterativePlugin_rs1_1[31 : 0] = execute_RS1; + end + + always @(*) begin + CsrPlugin_privilege = 2'b11; + if(CsrPlugin_forceMachineWire) begin + CsrPlugin_privilege = 2'b11; + end + end + + assign _zz_when_CsrPlugin_l965 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l965_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l965_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(CsrPlugin_selfException_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(BranchPlugin_branchExceptionPort_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(DBusCachedPlugin_exceptionBus_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + end + if(writeBack_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign when_CsrPlugin_l922 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l922_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l922_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l922_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l935 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l959 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l965 = ((_zz_when_CsrPlugin_l965 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l965_1 = ((_zz_when_CsrPlugin_l965_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l965_2 = ((_zz_when_CsrPlugin_l965_2 && 1'b1) && (! 1'b0)); + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_lastStageWasWfi = 1'b0; + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + assign when_CsrPlugin_l993 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l993_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l993_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l998 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(when_CsrPlugin_l1004) begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException) begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign when_CsrPlugin_l1004 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @(*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException) begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @(*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException) begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @(*) begin + CsrPlugin_xtvec_mode = 2'bxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign when_CsrPlugin_l1032 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1077 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == EnvCtrlEnum_XRET)); + assign switch_CsrPlugin_l1081 = writeBack_INSTRUCTION[29 : 28]; + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1129 = (|{(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == EnvCtrlEnum_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == EnvCtrlEnum_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_XRET))}}); + assign execute_CsrPlugin_blockedBySideEffects = ((|{writeBack_arbitration_isValid,memory_arbitration_isValid}) || 1'b0); + always @(*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_3860) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_769) begin + if(execute_CSR_WRITE_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_768) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_833) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_832) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_835) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1310) begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(when_CsrPlugin_l1315) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @(*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if(when_CsrPlugin_l1149) begin + if(when_CsrPlugin_l1150) begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @(*) begin + CsrPlugin_selfException_valid = 1'b0; + if(when_CsrPlugin_l1142) begin + CsrPlugin_selfException_valid = 1'b1; + end + if(when_CsrPlugin_l1157) begin + CsrPlugin_selfException_valid = 1'b1; + end + if(when_CsrPlugin_l1167) begin + CsrPlugin_selfException_valid = 1'b1; + end + end + + always @(*) begin + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(when_CsrPlugin_l1142) begin + CsrPlugin_selfException_payload_code = 4'b0010; + end + if(when_CsrPlugin_l1157) begin + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = 4'b1000; + end + default : begin + CsrPlugin_selfException_payload_code = 4'b1011; + end + endcase + end + if(when_CsrPlugin_l1167) begin + CsrPlugin_selfException_payload_code = 4'b0011; + end + end + + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + assign when_CsrPlugin_l1142 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign when_CsrPlugin_l1149 = (execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_XRET)); + assign when_CsrPlugin_l1150 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1157 = (execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_ECALL)); + assign when_CsrPlugin_l1167 = ((execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_EBREAK)) && CsrPlugin_allowEbreakException); + always @(*) begin + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(when_CsrPlugin_l1310) begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @(*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(when_CsrPlugin_l1310) begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l210_1 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l210_1) + 1'b0 : begin + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; + end + default : begin + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1189 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1193 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign switch_Misc_l210_2 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l210_2) + 3'b000 : begin + _zz_execute_BRANCH_DO = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_DO = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_DO = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_DO = execute_SRC_LESS; + end + endcase + end + + always @(*) begin + case(execute_BRANCH_CTRL) + BranchCtrlEnum_INC : begin + _zz_execute_BRANCH_DO_1 = 1'b0; + end + BranchCtrlEnum_JAL : begin + _zz_execute_BRANCH_DO_1 = 1'b1; + end + BranchCtrlEnum_JALR : begin + _zz_execute_BRANCH_DO_1 = 1'b1; + end + default : begin + _zz_execute_BRANCH_DO_1 = _zz_execute_BRANCH_DO; + end + endcase + end + + assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == BranchCtrlEnum_JALR) ? execute_RS1 : execute_PC); + assign _zz_execute_BranchPlugin_branch_src2 = _zz__zz_execute_BranchPlugin_branch_src2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + assign _zz_execute_BranchPlugin_branch_src2_2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[19] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[18] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[17] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[16] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[15] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[14] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[13] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[12] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[11] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; + end + + always @(*) begin + case(execute_BRANCH_CTRL) + BranchCtrlEnum_JAL : begin + _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_1,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + end + BranchCtrlEnum_JALR : begin + _zz_execute_BranchPlugin_branch_src2_6 = {_zz_execute_BranchPlugin_branch_src2_3,execute_INSTRUCTION[31 : 20]}; + end + default : begin + _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + end + endcase + end + + assign execute_BranchPlugin_branch_src2 = _zz_execute_BranchPlugin_branch_src2_6; + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; + assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; + assign when_DebugPlugin_l225 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)); + assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak)); + always @(*) begin + debug_bus_cmd_ready = 1'b1; + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l267) + 6'h01 : begin + if(debug_bus_cmd_payload_wr) begin + debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; + end + end + default : begin + end + endcase + end + end + + always @(*) begin + debug_bus_rsp_data = DebugPlugin_busReadDataReg; + if(when_DebugPlugin_l244) begin + debug_bus_rsp_data[0] = DebugPlugin_resetIt; + debug_bus_rsp_data[1] = DebugPlugin_haltIt; + debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; + debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; + debug_bus_rsp_data[4] = DebugPlugin_stepIt; + end + end + + assign when_DebugPlugin_l244 = (! _zz_when_DebugPlugin_l244); + always @(*) begin + IBusCachedPlugin_injectionPort_valid = 1'b0; + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l267) + 6'h01 : begin + if(debug_bus_cmd_payload_wr) begin + IBusCachedPlugin_injectionPort_valid = 1'b1; + end + end + default : begin + end + endcase + end + end + + assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; + assign switch_DebugPlugin_l267 = debug_bus_cmd_payload_address[7 : 2]; + assign when_DebugPlugin_l271 = debug_bus_cmd_payload_data[16]; + assign when_DebugPlugin_l271_1 = debug_bus_cmd_payload_data[24]; + assign when_DebugPlugin_l272 = debug_bus_cmd_payload_data[17]; + assign when_DebugPlugin_l272_1 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l273 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l274 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l275 = debug_bus_cmd_payload_data[18]; + assign when_DebugPlugin_l275_1 = debug_bus_cmd_payload_data[26]; + assign when_DebugPlugin_l295 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign when_DebugPlugin_l298 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign when_DebugPlugin_l311 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign when_DebugPlugin_l331 = (DebugPlugin_haltIt || DebugPlugin_stepIt); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_14 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_16 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_17 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_28 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_31 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_33 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_34 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_35 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_37 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_38 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_39 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; + assign when_Pipeline_l124_40 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_59 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_60 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck); + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + always @(*) begin + IBusCachedPlugin_injectionPort_ready = 1'b0; + case(switch_Fetcher_l365) + 3'b100 : begin + IBusCachedPlugin_injectionPort_ready = 1'b1; + end + default : begin + end + endcase + end + + assign when_Fetcher_l381 = (! decode_arbitration_isStuck); + assign when_Fetcher_l401 = (switch_Fetcher_l365 != 3'b000); + assign when_CsrPlugin_l1277 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_9 = (! execute_arbitration_isStuck); + assign switch_CsrPlugin_l723 = CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_CsrPlugin_csrMapping_readDataInit[12 : 11] = CsrPlugin_mstatus_MPP; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_1 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_1[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_1[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_1[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_2[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_2[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_2[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; + if(execute_CsrPlugin_csr_773) begin + _zz_CsrPlugin_csrMapping_readDataInit_3[31 : 2] = CsrPlugin_mtvec_base; + _zz_CsrPlugin_csrMapping_readDataInit_3[1 : 0] = CsrPlugin_mtvec_mode; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_4[31 : 0] = CsrPlugin_mepc; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; + if(execute_CsrPlugin_csr_832) begin + _zz_CsrPlugin_csrMapping_readDataInit_5[31 : 0] = CsrPlugin_mscratch; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_6[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_7[31 : 0] = CsrPlugin_mtval; + end + end + + assign CsrPlugin_csrMapping_readDataInit = ((((32'h0 | _zz_CsrPlugin_csrMapping_readDataInit) | (_zz_CsrPlugin_csrMapping_readDataInit_1 | _zz_CsrPlugin_csrMapping_readDataInit_2)) | ((_zz_CsrPlugin_csrMapping_readDataInit_3 | _zz_CsrPlugin_csrMapping_readDataInit_4) | (_zz_CsrPlugin_csrMapping_readDataInit_5 | _zz_CsrPlugin_csrMapping_readDataInit_6))) | _zz_CsrPlugin_csrMapping_readDataInit_7); + assign when_CsrPlugin_l1310 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1315 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + IBusCachedPlugin_fetchPc_pcReg <= 32'hf9000000; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; + _zz_IBusCachedPlugin_injector_decodeInput_valid <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + dBus_rsp_regNext_valid <= 1'b0; + DBusCachedPlugin_rspCounter <= 32'h0; + _zz_2 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + memory_MulDivIterativePlugin_div_counter_value <= 6'h0; + CsrPlugin_misa_base <= 2'b01; + CsrPlugin_misa_extensions <= 26'h0041101; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_mcycle <= 64'h0; + CsrPlugin_minstret <= 64'h0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + switch_Fetcher_l365 <= 3'b000; + end else begin + if(IBusCachedPlugin_fetchPc_correction) begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_output_fire) begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if(when_Fetcher_l134) begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_output_fire_1) begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(when_Fetcher_l134_1) begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(when_Fetcher_l161) begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + end + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + end + if(decode_arbitration_removeIt) begin + _zz_IBusCachedPlugin_injector_decodeInput_valid <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_output_ready) begin + _zz_IBusCachedPlugin_injector_decodeInput_valid <= (IBusCachedPlugin_iBusRsp_output_valid && (! IBusCachedPlugin_externalFlush)); + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if(when_Fetcher_l332) begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(when_Fetcher_l332_1) begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(when_Fetcher_l332_2) begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(when_Fetcher_l332_3) begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(when_Fetcher_l332_4) begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; + end + if(when_Fetcher_l332_5) begin + IBusCachedPlugin_injector_nextPcCalc_valids_5 <= IBusCachedPlugin_injector_nextPcCalc_valids_4; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; + end + if(iBus_rsp_valid) begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + end + if(dataCache_1_io_mem_cmd_valid) begin + dataCache_1_io_mem_cmd_rValid <= 1'b1; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_rValid <= 1'b0; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + end + dBus_rsp_regNext_valid <= dBus_rsp_valid; + if(dBus_rsp_valid) begin + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); + end + _zz_2 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring) begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(when_CsrPlugin_l922) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if(when_CsrPlugin_l922_1) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if(when_CsrPlugin_l922_2) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if(when_CsrPlugin_l922_3) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(when_CsrPlugin_l959) begin + if(when_CsrPlugin_l965) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(when_CsrPlugin_l965_1) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(when_CsrPlugin_l965_2) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l993) begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if(when_CsrPlugin_l993_1) begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if(when_CsrPlugin_l993_2) begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(when_CsrPlugin_l998) begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump) begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(when_CsrPlugin_l1032) begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(when_CsrPlugin_l1077) begin + case(switch_CsrPlugin_l1081) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l965_2,{_zz_when_CsrPlugin_l965_1,_zz_when_CsrPlugin_l965}} != 3'b000) || CsrPlugin_thirdPartyWake); + if(when_Pipeline_l151) begin + execute_arbitration_isValid <= 1'b0; + end + if(when_Pipeline_l154) begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(when_Pipeline_l151_1) begin + memory_arbitration_isValid <= 1'b0; + end + if(when_Pipeline_l154_1) begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(when_Pipeline_l151_2) begin + writeBack_arbitration_isValid <= 1'b0; + end + if(when_Pipeline_l154_2) begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(switch_Fetcher_l365) + 3'b000 : begin + if(IBusCachedPlugin_injectionPort_valid) begin + switch_Fetcher_l365 <= 3'b001; + end + end + 3'b001 : begin + switch_Fetcher_l365 <= 3'b010; + end + 3'b010 : begin + switch_Fetcher_l365 <= 3'b011; + end + 3'b011 : begin + if(when_Fetcher_l381) begin + switch_Fetcher_l365 <= 3'b100; + end + end + 3'b100 : begin + switch_Fetcher_l365 <= 3'b000; + end + default : begin + end + endcase + if(execute_CsrPlugin_csr_769) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30]; + CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0]; + end + end + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; + case(switch_CsrPlugin_l723) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b11; + end + default : begin + end + endcase + end + end + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; + end + end + end + end + + always @(posedge io_systemClk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_output_ready) begin + _zz_IBusCachedPlugin_injector_decodeInput_payload_pc <= IBusCachedPlugin_iBusRsp_output_payload_pc; + _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error <= IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst <= IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc <= IBusCachedPlugin_iBusRsp_output_payload_isRvc; + end + if(IBusCachedPlugin_injector_decodeInput_ready) begin + IBusCachedPlugin_injector_formal_rawInDecode <= IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(dataCache_1_io_mem_cmd_ready) begin + dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; + dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + dBus_rsp_regNext_payload_last <= dBus_rsp_payload_last; + dBus_rsp_regNext_payload_data <= dBus_rsp_payload_data; + dBus_rsp_regNext_payload_error <= dBus_rsp_payload_error; + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + execute_MulPlugin_delayLogic_counter <= (execute_MulPlugin_delayLogic_counter + 1'b1); + if(when_MulPlugin_l70) begin + execute_MulPlugin_delayLogic_counter <= 1'b0; + end + execute_MulPlugin_withOuputBuffer_mul_ll <= (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + execute_MulPlugin_withOuputBuffer_mul_lh <= ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + execute_MulPlugin_withOuputBuffer_mul_hl <= ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + execute_MulPlugin_withOuputBuffer_mul_hh <= ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + if(when_MulDivIterativePlugin_l126) begin + memory_MulDivIterativePlugin_div_done <= 1'b1; + end + if(when_MulDivIterativePlugin_l126_1) begin + memory_MulDivIterativePlugin_div_done <= 1'b0; + end + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin + memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; + memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; + if(when_MulDivIterativePlugin_l151) begin + memory_MulDivIterativePlugin_div_result <= _zz_memory_MulDivIterativePlugin_div_result_1[31:0]; + end + end + end + if(when_MulDivIterativePlugin_l162) begin + memory_MulDivIterativePlugin_accumulator <= 65'h0; + memory_MulDivIterativePlugin_rs1 <= ((_zz_memory_MulDivIterativePlugin_rs1 ? (~ _zz_memory_MulDivIterativePlugin_rs1_1) : _zz_memory_MulDivIterativePlugin_rs1_1) + _zz_memory_MulDivIterativePlugin_rs1_2); + memory_MulDivIterativePlugin_rs2 <= ((_zz_memory_MulDivIterativePlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_MulDivIterativePlugin_rs2_1); + memory_MulDivIterativePlugin_div_needRevert <= ((_zz_memory_MulDivIterativePlugin_rs1 ^ (_zz_memory_MulDivIterativePlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(CsrPlugin_selfException_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + end + if(BranchPlugin_branchExceptionPort_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + end + if(DBusCachedPlugin_exceptionBus_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(when_CsrPlugin_l959) begin + if(when_CsrPlugin_l965) begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(when_CsrPlugin_l965_1) begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(when_CsrPlugin_l965_2) begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(when_CsrPlugin_l1032) begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException) begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if(when_Pipeline_l124) begin + decode_to_execute_PC <= _zz_decode_SRC2; + end + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= execute_PC; + end + if(when_Pipeline_l124_2) begin + memory_to_writeBack_PC <= memory_PC; + end + if(when_Pipeline_l124_3) begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if(when_Pipeline_l124_4) begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if(when_Pipeline_l124_5) begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if(when_Pipeline_l124_6) begin + decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; + end + if(when_Pipeline_l124_7) begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if(when_Pipeline_l124_8) begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; + end + if(when_Pipeline_l124_9) begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if(when_Pipeline_l124_10) begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if(when_Pipeline_l124_11) begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if(when_Pipeline_l124_12) begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if(when_Pipeline_l124_13) begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if(when_Pipeline_l124_14) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; + end + if(when_Pipeline_l124_15) begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if(when_Pipeline_l124_16) begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if(when_Pipeline_l124_17) begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if(when_Pipeline_l124_18) begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if(when_Pipeline_l124_19) begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if(when_Pipeline_l124_20) begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if(when_Pipeline_l124_21) begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if(when_Pipeline_l124_22) begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if(when_Pipeline_l124_23) begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if(when_Pipeline_l124_24) begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if(when_Pipeline_l124_25) begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if(when_Pipeline_l124_26) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; + end + if(when_Pipeline_l124_27) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; + end + if(when_Pipeline_l124_28) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; + end + if(when_Pipeline_l124_29) begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if(when_Pipeline_l124_30) begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if(when_Pipeline_l124_31) begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if(when_Pipeline_l124_32) begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if(when_Pipeline_l124_33) begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if(when_Pipeline_l124_34) begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if(when_Pipeline_l124_35) begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if(when_Pipeline_l124_36) begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if(when_Pipeline_l124_37) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; + end + if(when_Pipeline_l124_38) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; + end + if(when_Pipeline_l124_39) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; + end + if(when_Pipeline_l124_40) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; + end + if(when_Pipeline_l124_41) begin + decode_to_execute_RS1 <= _zz_decode_SRC1; + end + if(when_Pipeline_l124_42) begin + decode_to_execute_RS2 <= _zz_decode_SRC2_1; + end + if(when_Pipeline_l124_43) begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if(when_Pipeline_l124_44) begin + decode_to_execute_SRC1 <= decode_SRC1; + end + if(when_Pipeline_l124_45) begin + decode_to_execute_SRC2 <= decode_SRC2; + end + if(when_Pipeline_l124_46) begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if(when_Pipeline_l124_47) begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if(when_Pipeline_l124_48) begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if(when_Pipeline_l124_49) begin + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; + end + if(when_Pipeline_l124_50) begin + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; + end + if(when_Pipeline_l124_51) begin + execute_to_memory_MEMORY_VIRTUAL_ADDRESS <= execute_MEMORY_VIRTUAL_ADDRESS; + end + if(when_Pipeline_l124_52) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; + end + if(when_Pipeline_l124_53) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; + end + if(when_Pipeline_l124_54) begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if(when_Pipeline_l124_55) begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if(when_Pipeline_l124_56) begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if(when_Pipeline_l124_57) begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if(when_Pipeline_l124_58) begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if(when_Pipeline_l124_59) begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if(when_Pipeline_l124_60) begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if(when_Pipeline_l124_61) begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if(when_Pipeline_l124_62) begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if(when_Fetcher_l401) begin + _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst <= IBusCachedPlugin_injectionPort_payload; + end + if(when_CsrPlugin_l1277) begin + execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); + end + if(when_CsrPlugin_l1277_1) begin + execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); + end + if(when_CsrPlugin_l1277_2) begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if(when_CsrPlugin_l1277_3) begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if(when_CsrPlugin_l1277_4) begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if(when_CsrPlugin_l1277_5) begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if(when_CsrPlugin_l1277_6) begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if(when_CsrPlugin_l1277_7) begin + execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); + end + if(when_CsrPlugin_l1277_8) begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if(when_CsrPlugin_l1277_9) begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; + end + end + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; + end + end + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; + end + end + if(execute_CsrPlugin_csr_832) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; + end + end + end + + always @(posedge io_systemClk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready) begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); + if(writeBack_arbitration_isValid) begin + DebugPlugin_busReadDataReg <= _zz_decode_RS2_2; + end + _zz_when_DebugPlugin_l244 <= debug_bus_cmd_payload_address[2]; + if(when_DebugPlugin_l295) begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @(posedge io_systemClk) begin + if(debugCd_logic_outputReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_debugUsed <= 1'b0; + DebugPlugin_disableEbreak <= 1'b0; + end else begin + if(when_DebugPlugin_l225) begin + DebugPlugin_godmode <= 1'b1; + end + if(debug_bus_cmd_valid) begin + DebugPlugin_debugUsed <= 1'b1; + end + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l267) + 6'h0 : begin + if(debug_bus_cmd_payload_wr) begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(when_DebugPlugin_l271) begin + DebugPlugin_resetIt <= 1'b1; + end + if(when_DebugPlugin_l271_1) begin + DebugPlugin_resetIt <= 1'b0; + end + if(when_DebugPlugin_l272) begin + DebugPlugin_haltIt <= 1'b1; + end + if(when_DebugPlugin_l272_1) begin + DebugPlugin_haltIt <= 1'b0; + end + if(when_DebugPlugin_l273) begin + DebugPlugin_haltedByBreak <= 1'b0; + end + if(when_DebugPlugin_l274) begin + DebugPlugin_godmode <= 1'b0; + end + if(when_DebugPlugin_l275) begin + DebugPlugin_disableEbreak <= 1'b1; + end + if(when_DebugPlugin_l275_1) begin + DebugPlugin_disableEbreak <= 1'b0; + end + end + end + default : begin + end + endcase + end + if(when_DebugPlugin_l295) begin + if(when_DebugPlugin_l298) begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; + end + end + if(when_DebugPlugin_l311) begin + if(decode_arbitration_isValid) begin + DebugPlugin_haltIt <= 1'b1; + end + end + end + end + + +endmodule + +module BufferCC_3 ( + input io_dataIn, + output io_dataOut, + input io_systemClk, + input debugCd_logic_outputReset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge io_systemClk or posedge debugCd_logic_outputReset) begin + if(debugCd_logic_outputReset) begin + buffers_0 <= 1'b1; + buffers_1 <= 1'b1; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module BufferCC_2 ( + input io_dataIn, + output io_dataOut, + input io_systemClk, + input io_asyncReset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge io_systemClk or posedge io_asyncReset) begin + if(io_asyncReset) begin + buffers_0 <= 1'b1; + buffers_1 <= 1'b1; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module StreamFifo_3 ( + input io_push_valid, + output io_push_ready, + input [7:0] io_push_payload_data, + output io_pop_valid, + input io_pop_ready, + output [7:0] io_pop_payload_data, + input io_flush, + output [8:0] io_occupancy, + output [8:0] io_availability, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [7:0] _zz_logic_ram_port0; + wire [7:0] _zz_logic_pushPtr_valueNext; + wire [0:0] _zz_logic_pushPtr_valueNext_1; + wire [7:0] _zz_logic_popPtr_valueNext; + wire [0:0] _zz_logic_popPtr_valueNext_1; + wire _zz_logic_ram_port; + wire _zz_io_pop_payload_data; + wire [7:0] _zz_io_availability; + reg _zz_1; + reg logic_pushPtr_willIncrement; + reg logic_pushPtr_willClear; + reg [7:0] logic_pushPtr_valueNext; + reg [7:0] logic_pushPtr_value; + wire logic_pushPtr_willOverflowIfInc; + wire logic_pushPtr_willOverflow; + reg logic_popPtr_willIncrement; + reg logic_popPtr_willClear; + reg [7:0] logic_popPtr_valueNext; + reg [7:0] logic_popPtr_value; + wire logic_popPtr_willOverflowIfInc; + wire logic_popPtr_willOverflow; + wire logic_ptrMatch; + reg logic_risingOccupancy; + wire logic_pushing; + wire logic_popping; + wire logic_empty; + wire logic_full; + reg _zz_io_pop_valid; + wire when_Stream_l1037; + wire [7:0] logic_ptrDif; + reg [7:0] logic_ram [0:255]; + + assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; + assign _zz_logic_pushPtr_valueNext = {7'd0, _zz_logic_pushPtr_valueNext_1}; + assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; + assign _zz_logic_popPtr_valueNext = {7'd0, _zz_logic_popPtr_valueNext_1}; + assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); + assign _zz_io_pop_payload_data = 1'b1; + always @(posedge io_systemClk) begin + if(_zz_io_pop_payload_data) begin + _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_1) begin + logic_ram[logic_pushPtr_value] <= io_push_payload_data; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_pushing) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willIncrement = 1'b0; + if(logic_pushing) begin + logic_pushPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willClear = 1'b0; + if(io_flush) begin + logic_pushPtr_willClear = 1'b1; + end + end + + assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 8'hff); + assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); + always @(*) begin + logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); + if(logic_pushPtr_willClear) begin + logic_pushPtr_valueNext = 8'h0; + end + end + + always @(*) begin + logic_popPtr_willIncrement = 1'b0; + if(logic_popping) begin + logic_popPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_popPtr_willClear = 1'b0; + if(io_flush) begin + logic_popPtr_willClear = 1'b1; + end + end + + assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 8'hff); + assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); + always @(*) begin + logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); + if(logic_popPtr_willClear) begin + logic_popPtr_valueNext = 8'h0; + end + end + + assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); + assign logic_pushing = (io_push_valid && io_push_ready); + assign logic_popping = (io_pop_valid && io_pop_ready); + assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); + assign logic_full = (logic_ptrMatch && logic_risingOccupancy); + assign io_push_ready = (! logic_full); + assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); + assign io_pop_payload_data = _zz_logic_ram_port0[7 : 0]; + assign when_Stream_l1037 = (logic_pushing != logic_popping); + assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); + assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; + assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + logic_pushPtr_value <= 8'h0; + logic_popPtr_value <= 8'h0; + logic_risingOccupancy <= 1'b0; + _zz_io_pop_valid <= 1'b0; + end else begin + logic_pushPtr_value <= logic_pushPtr_valueNext; + logic_popPtr_value <= logic_popPtr_valueNext; + _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); + if(when_Stream_l1037) begin + logic_risingOccupancy <= logic_pushing; + end + if(io_flush) begin + logic_risingOccupancy <= 1'b0; + end + end + end + + +endmodule + +module StreamFifo_2 ( + input io_push_valid, + output io_push_ready, + input io_push_payload_kind, + input io_push_payload_read, + input io_push_payload_write, + input [7:0] io_push_payload_data, + output io_pop_valid, + input io_pop_ready, + output io_pop_payload_kind, + output io_pop_payload_read, + output io_pop_payload_write, + output [7:0] io_pop_payload_data, + input io_flush, + output [8:0] io_occupancy, + output [8:0] io_availability, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [10:0] _zz_logic_ram_port0; + wire [7:0] _zz_logic_pushPtr_valueNext; + wire [0:0] _zz_logic_pushPtr_valueNext_1; + wire [7:0] _zz_logic_popPtr_valueNext; + wire [0:0] _zz_logic_popPtr_valueNext_1; + wire _zz_logic_ram_port; + wire _zz__zz_io_pop_payload_kind; + wire [10:0] _zz_logic_ram_port_1; + wire [7:0] _zz_io_availability; + reg _zz_1; + reg logic_pushPtr_willIncrement; + reg logic_pushPtr_willClear; + reg [7:0] logic_pushPtr_valueNext; + reg [7:0] logic_pushPtr_value; + wire logic_pushPtr_willOverflowIfInc; + wire logic_pushPtr_willOverflow; + reg logic_popPtr_willIncrement; + reg logic_popPtr_willClear; + reg [7:0] logic_popPtr_valueNext; + reg [7:0] logic_popPtr_value; + wire logic_popPtr_willOverflowIfInc; + wire logic_popPtr_willOverflow; + wire logic_ptrMatch; + reg logic_risingOccupancy; + wire logic_pushing; + wire logic_popping; + wire logic_empty; + wire logic_full; + reg _zz_io_pop_valid; + wire [10:0] _zz_io_pop_payload_kind; + wire when_Stream_l1037; + wire [7:0] logic_ptrDif; + reg [10:0] logic_ram [0:255]; + + assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; + assign _zz_logic_pushPtr_valueNext = {7'd0, _zz_logic_pushPtr_valueNext_1}; + assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; + assign _zz_logic_popPtr_valueNext = {7'd0, _zz_logic_popPtr_valueNext_1}; + assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); + assign _zz__zz_io_pop_payload_kind = 1'b1; + assign _zz_logic_ram_port_1 = {io_push_payload_data,{io_push_payload_write,{io_push_payload_read,io_push_payload_kind}}}; + always @(posedge io_systemClk) begin + if(_zz__zz_io_pop_payload_kind) begin + _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_1) begin + logic_ram[logic_pushPtr_value] <= _zz_logic_ram_port_1; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_pushing) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willIncrement = 1'b0; + if(logic_pushing) begin + logic_pushPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willClear = 1'b0; + if(io_flush) begin + logic_pushPtr_willClear = 1'b1; + end + end + + assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 8'hff); + assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); + always @(*) begin + logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); + if(logic_pushPtr_willClear) begin + logic_pushPtr_valueNext = 8'h0; + end + end + + always @(*) begin + logic_popPtr_willIncrement = 1'b0; + if(logic_popping) begin + logic_popPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_popPtr_willClear = 1'b0; + if(io_flush) begin + logic_popPtr_willClear = 1'b1; + end + end + + assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 8'hff); + assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); + always @(*) begin + logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); + if(logic_popPtr_willClear) begin + logic_popPtr_valueNext = 8'h0; + end + end + + assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); + assign logic_pushing = (io_push_valid && io_push_ready); + assign logic_popping = (io_pop_valid && io_pop_ready); + assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); + assign logic_full = (logic_ptrMatch && logic_risingOccupancy); + assign io_push_ready = (! logic_full); + assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); + assign _zz_io_pop_payload_kind = _zz_logic_ram_port0; + assign io_pop_payload_kind = _zz_io_pop_payload_kind[0]; + assign io_pop_payload_read = _zz_io_pop_payload_kind[1]; + assign io_pop_payload_write = _zz_io_pop_payload_kind[2]; + assign io_pop_payload_data = _zz_io_pop_payload_kind[10 : 3]; + assign when_Stream_l1037 = (logic_pushing != logic_popping); + assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); + assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; + assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + logic_pushPtr_value <= 8'h0; + logic_popPtr_value <= 8'h0; + logic_risingOccupancy <= 1'b0; + _zz_io_pop_valid <= 1'b0; + end else begin + logic_pushPtr_value <= logic_pushPtr_valueNext; + logic_popPtr_value <= logic_popPtr_valueNext; + _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); + if(when_Stream_l1037) begin + logic_risingOccupancy <= logic_pushing; + end + if(io_flush) begin + logic_risingOccupancy <= 1'b0; + end + end + end + + +endmodule + +module TopLevel ( + input io_config_kind_cpol, + input io_config_kind_cpha, + input [11:0] io_config_sclkToogle, + input [1:0] io_config_mod, + input [0:0] io_config_ss_activeHigh, + input [11:0] io_config_ss_setup, + input [11:0] io_config_ss_hold, + input [11:0] io_config_ss_disable, + input io_cmd_valid, + output reg io_cmd_ready, + input io_cmd_payload_kind, + input io_cmd_payload_read, + input io_cmd_payload_write, + input [7:0] io_cmd_payload_data, + output io_rsp_valid, + output [7:0] io_rsp_payload_data, + output [0:0] io_spi_sclk_write, + output reg io_spi_data_0_writeEnable, + input [0:0] io_spi_data_0_read, + output reg [0:0] io_spi_data_0_write, + output reg io_spi_data_1_writeEnable, + input [0:0] io_spi_data_1_read, + output reg [0:0] io_spi_data_1_write, + output reg io_spi_data_2_writeEnable, + input [0:0] io_spi_data_2_read, + output reg [0:0] io_spi_data_2_write, + output reg io_spi_data_3_writeEnable, + input [0:0] io_spi_data_3_read, + output reg [0:0] io_spi_data_3_write, + output [0:0] io_spi_ss, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [0:0] _zz_outputPhy_dataWrite_3; + wire [2:0] _zz_outputPhy_dataWrite_4; + wire [2:0] _zz_outputPhy_dataWrite_5; + reg [1:0] _zz_outputPhy_dataWrite_6; + wire [1:0] _zz_outputPhy_dataWrite_7; + wire [2:0] _zz_outputPhy_dataWrite_8; + reg [3:0] _zz_outputPhy_dataWrite_9; + wire [0:0] _zz_outputPhy_dataWrite_10; + wire [2:0] _zz_outputPhy_dataWrite_11; + wire [3:0] _zz_inputPhy_dataRead; + wire [3:0] _zz_inputPhy_dataRead_1; + wire [3:0] _zz_inputPhy_dataRead_2; + wire [3:0] _zz_inputPhy_dataRead_3; + wire [3:0] _zz_inputPhy_dataRead_4; + wire [3:0] _zz_inputPhy_dataRead_5; + wire [3:0] _zz_inputPhy_dataRead_6; + wire [8:0] _zz_inputPhy_bufferNext; + wire [10:0] _zz_inputPhy_bufferNext_1; + reg [11:0] timer_counter; + reg timer_reset; + wire timer_ss_setupHit; + wire timer_ss_holdHit; + wire timer_ss_disableHit; + wire timer_sclkToogleHit; + reg fsm_state; + reg [2:0] fsm_counter; + reg [2:0] _zz_fsm_counterPlus; + wire [2:0] fsm_counterPlus; + reg fsm_fastRate; + reg fsm_isDdr; + reg [2:0] fsm_counterMax; + reg fsm_lateSampling; + reg fsm_readFill; + reg fsm_readDone; + reg [0:0] fsm_ss; + wire when_SpiXdrMasterCtrl_l739; + wire when_SpiXdrMasterCtrl_l742; + wire when_SpiXdrMasterCtrl_l749; + wire when_SpiXdrMasterCtrl_l751; + wire when_SpiXdrMasterCtrl_l758; + wire when_SpiXdrMasterCtrl_l764; + wire when_SpiXdrMasterCtrl_l781; + reg [0:0] outputPhy_sclkWrite; + wire [0:0] _zz_io_spi_sclk_write; + wire when_SpiXdrMasterCtrl_l796; + reg [3:0] outputPhy_dataWrite; + reg [2:0] outputPhy_widthSel; + reg [2:0] outputPhy_offset; + wire [7:0] _zz_outputPhy_dataWrite; + wire [7:0] _zz_outputPhy_dataWrite_1; + wire [7:0] _zz_outputPhy_dataWrite_2; + wire when_SpiXdrMasterCtrl_l839; + wire when_SpiXdrMasterCtrl_l839_1; + reg [1:0] io_config_mod_delay_1; + reg [1:0] inputPhy_mod; + reg fsm_readFill_delay_1; + reg inputPhy_readFill; + reg fsm_readDone_delay_1; + reg inputPhy_readDone; + reg [6:0] inputPhy_buffer; + reg [7:0] inputPhy_bufferNext; + reg [2:0] inputPhy_widthSel; + wire [3:0] inputPhy_dataWrite; + reg [3:0] inputPhy_dataRead; + reg fsm_state_delay_1; + reg fsm_state_delay_2; + wire when_SpiXdrMasterCtrl_l861; + reg [3:0] inputPhy_dataReadBuffer; + + assign _zz_outputPhy_dataWrite_4 = (_zz_outputPhy_dataWrite_5 >>> 0); + assign _zz_outputPhy_dataWrite_5 = (outputPhy_offset - fsm_counter); + assign _zz_outputPhy_dataWrite_7 = (_zz_outputPhy_dataWrite_8 >>> 1); + assign _zz_outputPhy_dataWrite_8 = (outputPhy_offset - fsm_counter); + assign _zz_outputPhy_dataWrite_10 = (_zz_outputPhy_dataWrite_11 >>> 2); + assign _zz_outputPhy_dataWrite_11 = (outputPhy_offset - fsm_counter); + assign _zz_inputPhy_dataRead = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_1 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_2 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_3 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_4 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_5 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_6 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[1 : 0]}; + assign _zz_inputPhy_bufferNext_1 = {inputPhy_buffer,inputPhy_dataRead[3 : 0]}; + always @(*) begin + case(_zz_outputPhy_dataWrite_4) + 3'b000 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[0 : 0]; + 3'b001 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[1 : 1]; + 3'b010 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[2 : 2]; + 3'b011 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[3 : 3]; + 3'b100 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[4 : 4]; + 3'b101 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[5 : 5]; + 3'b110 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[6 : 6]; + default : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[7 : 7]; + endcase + end + + always @(*) begin + case(_zz_outputPhy_dataWrite_7) + 2'b00 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[1 : 0]; + 2'b01 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[3 : 2]; + 2'b10 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[5 : 4]; + default : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[7 : 6]; + endcase + end + + always @(*) begin + case(_zz_outputPhy_dataWrite_10) + 1'b0 : _zz_outputPhy_dataWrite_9 = _zz_outputPhy_dataWrite_2[3 : 0]; + default : _zz_outputPhy_dataWrite_9 = _zz_outputPhy_dataWrite_2[7 : 4]; + endcase + end + + always @(*) begin + timer_reset = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l739) begin + timer_reset = timer_sclkToogleHit; + end else begin + if(!when_SpiXdrMasterCtrl_l758) begin + if(when_SpiXdrMasterCtrl_l764) begin + if(timer_ss_holdHit) begin + timer_reset = 1'b1; + end + end + end + end + end + if(when_SpiXdrMasterCtrl_l781) begin + timer_reset = 1'b1; + end + end + + assign timer_ss_setupHit = (timer_counter == io_config_ss_setup); + assign timer_ss_holdHit = (timer_counter == io_config_ss_hold); + assign timer_ss_disableHit = (timer_counter == io_config_ss_disable); + assign timer_sclkToogleHit = (timer_counter == io_config_sclkToogle); + always @(*) begin + _zz_fsm_counterPlus = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + _zz_fsm_counterPlus = 3'b001; + end + 2'b01 : begin + _zz_fsm_counterPlus = 3'b010; + end + 2'b10 : begin + _zz_fsm_counterPlus = 3'b100; + end + default : begin + end + endcase + end + + assign fsm_counterPlus = (fsm_counter + _zz_fsm_counterPlus); + always @(*) begin + fsm_fastRate = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_fastRate = 1'b0; + end + 2'b01 : begin + fsm_fastRate = 1'b0; + end + 2'b10 : begin + fsm_fastRate = 1'b0; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_isDdr = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_isDdr = 1'b0; + end + 2'b01 : begin + fsm_isDdr = 1'b0; + end + 2'b10 : begin + fsm_isDdr = 1'b0; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_counterMax = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + fsm_counterMax = 3'b111; + end + 2'b01 : begin + fsm_counterMax = 3'b110; + end + 2'b10 : begin + fsm_counterMax = 3'b100; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_lateSampling = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_lateSampling = 1'b1; + end + 2'b01 : begin + fsm_lateSampling = 1'b1; + end + 2'b10 : begin + fsm_lateSampling = 1'b1; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_readFill = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l739) begin + if(when_SpiXdrMasterCtrl_l742) begin + fsm_readFill = 1'b1; + end + end + end + end + + always @(*) begin + fsm_readDone = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l739) begin + if(when_SpiXdrMasterCtrl_l742) begin + fsm_readDone = (io_cmd_payload_read && (fsm_counter == fsm_counterMax)); + end + end + end + end + + assign io_spi_ss = (~ (fsm_ss ^ io_config_ss_activeHigh)); + always @(*) begin + io_cmd_ready = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l739) begin + if(when_SpiXdrMasterCtrl_l749) begin + if(when_SpiXdrMasterCtrl_l751) begin + io_cmd_ready = 1'b1; + end + end + end else begin + if(when_SpiXdrMasterCtrl_l758) begin + if(timer_ss_setupHit) begin + io_cmd_ready = 1'b1; + end + end else begin + if(!when_SpiXdrMasterCtrl_l764) begin + if(timer_ss_disableHit) begin + io_cmd_ready = 1'b1; + end + end + end + end + end + end + + assign when_SpiXdrMasterCtrl_l739 = (! io_cmd_payload_kind); + assign when_SpiXdrMasterCtrl_l742 = ((timer_sclkToogleHit && (((! fsm_state) ^ fsm_lateSampling) || fsm_isDdr)) || fsm_fastRate); + assign when_SpiXdrMasterCtrl_l749 = ((timer_sclkToogleHit && (fsm_state || fsm_isDdr)) || fsm_fastRate); + assign when_SpiXdrMasterCtrl_l751 = (fsm_counter == fsm_counterMax); + assign when_SpiXdrMasterCtrl_l758 = io_cmd_payload_data[7]; + assign when_SpiXdrMasterCtrl_l764 = (! fsm_state); + assign when_SpiXdrMasterCtrl_l781 = ((! io_cmd_valid) || io_cmd_ready); + always @(*) begin + outputPhy_sclkWrite = 1'b0; + if(when_SpiXdrMasterCtrl_l796) begin + case(io_config_mod) + 2'b00 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + 2'b01 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + 2'b10 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + default : begin + end + endcase + end + end + + assign _zz_io_spi_sclk_write[0] = io_config_kind_cpol; + assign io_spi_sclk_write = (outputPhy_sclkWrite ^ _zz_io_spi_sclk_write); + assign when_SpiXdrMasterCtrl_l796 = (io_cmd_valid && (! io_cmd_payload_kind)); + always @(*) begin + outputPhy_widthSel = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + outputPhy_widthSel = 3'b000; + end + 2'b01 : begin + outputPhy_widthSel = 3'b001; + end + 2'b10 : begin + outputPhy_widthSel = 3'b010; + end + default : begin + end + endcase + end + + always @(*) begin + outputPhy_offset = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + outputPhy_offset = 3'b111; + end + 2'b01 : begin + outputPhy_offset = 3'b111; + end + 2'b10 : begin + outputPhy_offset = 3'b111; + end + default : begin + end + endcase + end + + always @(*) begin + outputPhy_dataWrite = 4'bxxxx; + case(outputPhy_widthSel) + 3'b000 : begin + outputPhy_dataWrite[0 : 0] = _zz_outputPhy_dataWrite_3; + end + 3'b001 : begin + outputPhy_dataWrite[1 : 0] = _zz_outputPhy_dataWrite_6; + end + 3'b010 : begin + outputPhy_dataWrite[3 : 0] = _zz_outputPhy_dataWrite_9; + end + default : begin + end + endcase + end + + assign _zz_outputPhy_dataWrite = io_cmd_payload_data; + assign _zz_outputPhy_dataWrite_1 = io_cmd_payload_data; + assign _zz_outputPhy_dataWrite_2 = io_cmd_payload_data; + always @(*) begin + io_spi_data_0_writeEnable = 1'b0; + case(io_config_mod) + 2'b00 : begin + io_spi_data_0_writeEnable = 1'b1; + end + 2'b01 : begin + if(when_SpiXdrMasterCtrl_l839) begin + io_spi_data_0_writeEnable = 1'b1; + end + end + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l839_1) begin + io_spi_data_0_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_1_writeEnable = 1'b0; + case(io_config_mod) + 2'b01 : begin + if(when_SpiXdrMasterCtrl_l839) begin + io_spi_data_1_writeEnable = 1'b1; + end + end + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l839_1) begin + io_spi_data_1_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_2_writeEnable = 1'b0; + case(io_config_mod) + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l839_1) begin + io_spi_data_2_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_3_writeEnable = 1'b0; + case(io_config_mod) + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l839_1) begin + io_spi_data_3_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_0_write = 1'bx; + case(io_config_mod) + 2'b00 : begin + io_spi_data_0_write[0] = (outputPhy_dataWrite[0] || (! (io_cmd_valid && io_cmd_payload_write))); + end + 2'b01 : begin + io_spi_data_0_write[0] = outputPhy_dataWrite[0]; + end + 2'b10 : begin + io_spi_data_0_write[0] = outputPhy_dataWrite[0]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_1_write = 1'bx; + case(io_config_mod) + 2'b01 : begin + io_spi_data_1_write[0] = outputPhy_dataWrite[1]; + end + 2'b10 : begin + io_spi_data_1_write[0] = outputPhy_dataWrite[1]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_2_write = 1'bx; + case(io_config_mod) + 2'b10 : begin + io_spi_data_2_write[0] = outputPhy_dataWrite[2]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_3_write = 1'bx; + case(io_config_mod) + 2'b10 : begin + io_spi_data_3_write[0] = outputPhy_dataWrite[3]; + end + default : begin + end + endcase + end + + assign when_SpiXdrMasterCtrl_l839 = (io_cmd_valid && io_cmd_payload_write); + assign when_SpiXdrMasterCtrl_l839_1 = (io_cmd_valid && io_cmd_payload_write); + always @(*) begin + inputPhy_bufferNext = 8'bxxxxxxxx; + case(inputPhy_widthSel) + 3'b000 : begin + inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[0 : 0]}; + end + 3'b001 : begin + inputPhy_bufferNext = _zz_inputPhy_bufferNext[7:0]; + end + 3'b010 : begin + inputPhy_bufferNext = _zz_inputPhy_bufferNext_1[7:0]; + end + default : begin + end + endcase + end + + always @(*) begin + inputPhy_widthSel = 3'bxxx; + case(inputPhy_mod) + 2'b00 : begin + inputPhy_widthSel = 3'b000; + end + 2'b01 : begin + inputPhy_widthSel = 3'b001; + end + 2'b10 : begin + inputPhy_widthSel = 3'b010; + end + default : begin + end + endcase + end + + assign when_SpiXdrMasterCtrl_l861 = (! fsm_state_delay_2); + always @(*) begin + inputPhy_dataRead = 4'bxxxx; + case(inputPhy_mod) + 2'b00 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead[1]; + end + 2'b01 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead_1[0]; + inputPhy_dataRead[1] = _zz_inputPhy_dataRead_2[1]; + end + 2'b10 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead_3[0]; + inputPhy_dataRead[1] = _zz_inputPhy_dataRead_4[1]; + inputPhy_dataRead[2] = _zz_inputPhy_dataRead_5[2]; + inputPhy_dataRead[3] = _zz_inputPhy_dataRead_6[3]; + end + default : begin + end + endcase + end + + assign io_rsp_valid = inputPhy_readDone; + assign io_rsp_payload_data = inputPhy_bufferNext; + always @(posedge io_systemClk) begin + timer_counter <= (timer_counter + 12'h001); + if(timer_reset) begin + timer_counter <= 12'h0; + end + io_config_mod_delay_1 <= io_config_mod; + inputPhy_mod <= io_config_mod_delay_1; + fsm_state_delay_1 <= fsm_state; + fsm_state_delay_2 <= fsm_state_delay_1; + if(when_SpiXdrMasterCtrl_l861) begin + inputPhy_dataReadBuffer <= {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + end + case(inputPhy_widthSel) + 3'b000 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + 3'b001 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + 3'b010 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + default : begin + end + endcase + end + + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + fsm_state <= 1'b0; + fsm_counter <= 3'b000; + fsm_ss <= 1'b0; + fsm_readFill_delay_1 <= 1'b0; + inputPhy_readFill <= 1'b0; + fsm_readDone_delay_1 <= 1'b0; + inputPhy_readDone <= 1'b0; + end else begin + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l739) begin + if(timer_sclkToogleHit) begin + fsm_state <= (! fsm_state); + end + if(when_SpiXdrMasterCtrl_l749) begin + fsm_counter <= fsm_counterPlus; + if(when_SpiXdrMasterCtrl_l751) begin + fsm_state <= 1'b0; + end + end + end else begin + if(when_SpiXdrMasterCtrl_l758) begin + fsm_ss[0] <= 1'b1; + end else begin + if(when_SpiXdrMasterCtrl_l764) begin + if(timer_ss_holdHit) begin + fsm_state <= 1'b1; + end + end else begin + fsm_ss[0] <= 1'b0; + end + end + end + end + if(when_SpiXdrMasterCtrl_l781) begin + fsm_state <= 1'b0; + fsm_counter <= 3'b000; + end + fsm_readFill_delay_1 <= fsm_readFill; + inputPhy_readFill <= fsm_readFill_delay_1; + fsm_readDone_delay_1 <= fsm_readDone; + inputPhy_readDone <= fsm_readDone_delay_1; + end + end + + +endmodule + +//StreamFifo replaced by StreamFifo + +module StreamFifo ( + input io_push_valid, + output io_push_ready, + input [7:0] io_push_payload, + output io_pop_valid, + input io_pop_ready, + output [7:0] io_pop_payload, + input io_flush, + output [7:0] io_occupancy, + output [7:0] io_availability, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [7:0] _zz_logic_ram_port0; + wire [6:0] _zz_logic_pushPtr_valueNext; + wire [0:0] _zz_logic_pushPtr_valueNext_1; + wire [6:0] _zz_logic_popPtr_valueNext; + wire [0:0] _zz_logic_popPtr_valueNext_1; + wire _zz_logic_ram_port; + wire _zz_io_pop_payload; + wire [6:0] _zz_io_availability; + reg _zz_1; + reg logic_pushPtr_willIncrement; + reg logic_pushPtr_willClear; + reg [6:0] logic_pushPtr_valueNext; + reg [6:0] logic_pushPtr_value; + wire logic_pushPtr_willOverflowIfInc; + wire logic_pushPtr_willOverflow; + reg logic_popPtr_willIncrement; + reg logic_popPtr_willClear; + reg [6:0] logic_popPtr_valueNext; + reg [6:0] logic_popPtr_value; + wire logic_popPtr_willOverflowIfInc; + wire logic_popPtr_willOverflow; + wire logic_ptrMatch; + reg logic_risingOccupancy; + wire logic_pushing; + wire logic_popping; + wire logic_empty; + wire logic_full; + reg _zz_io_pop_valid; + wire when_Stream_l1037; + wire [6:0] logic_ptrDif; + reg [7:0] logic_ram [0:127]; + + assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; + assign _zz_logic_pushPtr_valueNext = {6'd0, _zz_logic_pushPtr_valueNext_1}; + assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; + assign _zz_logic_popPtr_valueNext = {6'd0, _zz_logic_popPtr_valueNext_1}; + assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); + assign _zz_io_pop_payload = 1'b1; + always @(posedge io_systemClk) begin + if(_zz_io_pop_payload) begin + _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_1) begin + logic_ram[logic_pushPtr_value] <= io_push_payload; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_pushing) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willIncrement = 1'b0; + if(logic_pushing) begin + logic_pushPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willClear = 1'b0; + if(io_flush) begin + logic_pushPtr_willClear = 1'b1; + end + end + + assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 7'h7f); + assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); + always @(*) begin + logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); + if(logic_pushPtr_willClear) begin + logic_pushPtr_valueNext = 7'h0; + end + end + + always @(*) begin + logic_popPtr_willIncrement = 1'b0; + if(logic_popping) begin + logic_popPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_popPtr_willClear = 1'b0; + if(io_flush) begin + logic_popPtr_willClear = 1'b1; + end + end + + assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 7'h7f); + assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); + always @(*) begin + logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); + if(logic_popPtr_willClear) begin + logic_popPtr_valueNext = 7'h0; + end + end + + assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); + assign logic_pushing = (io_push_valid && io_push_ready); + assign logic_popping = (io_pop_valid && io_pop_ready); + assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); + assign logic_full = (logic_ptrMatch && logic_risingOccupancy); + assign io_push_ready = (! logic_full); + assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); + assign io_pop_payload = _zz_logic_ram_port0; + assign when_Stream_l1037 = (logic_pushing != logic_popping); + assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); + assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; + assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + logic_pushPtr_value <= 7'h0; + logic_popPtr_value <= 7'h0; + logic_risingOccupancy <= 1'b0; + _zz_io_pop_valid <= 1'b0; + end else begin + logic_pushPtr_value <= logic_pushPtr_valueNext; + logic_popPtr_value <= logic_popPtr_valueNext; + _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); + if(when_Stream_l1037) begin + logic_risingOccupancy <= logic_pushing; + end + if(io_flush) begin + logic_risingOccupancy <= 1'b0; + end + end + end + + +endmodule + +module UartCtrl ( + input [2:0] io_config_frame_dataLength, + input [0:0] io_config_frame_stop, + input [1:0] io_config_frame_parity, + input [19:0] io_config_clockDivider, + input io_write_valid, + output reg io_write_ready, + input [7:0] io_write_payload, + output io_read_valid, + input io_read_ready, + output [7:0] io_read_payload, + output io_uart_txd, + input io_uart_rxd, + output io_readError, + input io_writeBreak, + output io_readBreak, + input io_systemClk, + input systemCd_logic_outputReset +); + localparam UartStopType_ONE = 1'd0; + localparam UartStopType_TWO = 1'd1; + localparam UartParityType_NONE = 2'd0; + localparam UartParityType_EVEN = 2'd1; + localparam UartParityType_ODD = 2'd2; + + wire tx_io_write_ready; + wire tx_io_txd; + wire rx_io_read_valid; + wire [7:0] rx_io_read_payload; + wire rx_io_rts; + wire rx_io_error; + wire rx_io_break; + reg [19:0] clockDivider_counter; + wire clockDivider_tick; + reg clockDivider_tickReg; + reg io_write_thrown_valid; + wire io_write_thrown_ready; + wire [7:0] io_write_thrown_payload; + `ifndef SYNTHESIS + reg [23:0] io_config_frame_stop_string; + reg [31:0] io_config_frame_parity_string; + `endif + + + UartCtrlTx tx ( + .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i + .io_configFrame_stop (io_config_frame_stop ), //i + .io_configFrame_parity (io_config_frame_parity[1:0] ), //i + .io_samplingTick (clockDivider_tickReg ), //i + .io_write_valid (io_write_thrown_valid ), //i + .io_write_ready (tx_io_write_ready ), //o + .io_write_payload (io_write_thrown_payload[7:0] ), //i + .io_cts (1'b0 ), //i + .io_txd (tx_io_txd ), //o + .io_break (io_writeBreak ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + UartCtrlRx rx ( + .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i + .io_configFrame_stop (io_config_frame_stop ), //i + .io_configFrame_parity (io_config_frame_parity[1:0] ), //i + .io_samplingTick (clockDivider_tickReg ), //i + .io_read_valid (rx_io_read_valid ), //o + .io_read_ready (io_read_ready ), //i + .io_read_payload (rx_io_read_payload[7:0] ), //o + .io_rxd (io_uart_rxd ), //i + .io_rts (rx_io_rts ), //o + .io_error (rx_io_error ), //o + .io_break (rx_io_break ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_config_frame_stop) + UartStopType_ONE : io_config_frame_stop_string = "ONE"; + UartStopType_TWO : io_config_frame_stop_string = "TWO"; + default : io_config_frame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_config_frame_parity) + UartParityType_NONE : io_config_frame_parity_string = "NONE"; + UartParityType_EVEN : io_config_frame_parity_string = "EVEN"; + UartParityType_ODD : io_config_frame_parity_string = "ODD "; + default : io_config_frame_parity_string = "????"; + endcase + end + `endif + + assign clockDivider_tick = (clockDivider_counter == 20'h0); + always @(*) begin + io_write_thrown_valid = io_write_valid; + if(rx_io_break) begin + io_write_thrown_valid = 1'b0; + end + end + + always @(*) begin + io_write_ready = io_write_thrown_ready; + if(rx_io_break) begin + io_write_ready = 1'b1; + end + end + + assign io_write_thrown_payload = io_write_payload; + assign io_write_thrown_ready = tx_io_write_ready; + assign io_read_valid = rx_io_read_valid; + assign io_read_payload = rx_io_read_payload; + assign io_uart_txd = tx_io_txd; + assign io_readError = rx_io_error; + assign io_readBreak = rx_io_break; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + clockDivider_counter <= 20'h0; + clockDivider_tickReg <= 1'b0; + end else begin + clockDivider_tickReg <= clockDivider_tick; + clockDivider_counter <= (clockDivider_counter - 20'h00001); + if(clockDivider_tick) begin + clockDivider_counter <= io_config_clockDivider; + end + end + end + + +endmodule + +module StreamArbiter ( + input io_inputs_0_valid, + output io_inputs_0_ready, + input io_inputs_0_payload_last, + input [0:0] io_inputs_0_payload_fragment_source, + input [0:0] io_inputs_0_payload_fragment_opcode, + input [31:0] io_inputs_0_payload_fragment_address, + input [5:0] io_inputs_0_payload_fragment_length, + input [31:0] io_inputs_0_payload_fragment_data, + input [3:0] io_inputs_0_payload_fragment_mask, + input [0:0] io_inputs_0_payload_fragment_context, + input io_inputs_1_valid, + output io_inputs_1_ready, + input io_inputs_1_payload_last, + input [0:0] io_inputs_1_payload_fragment_source, + input [0:0] io_inputs_1_payload_fragment_opcode, + input [31:0] io_inputs_1_payload_fragment_address, + input [5:0] io_inputs_1_payload_fragment_length, + input [31:0] io_inputs_1_payload_fragment_data, + input [3:0] io_inputs_1_payload_fragment_mask, + input [0:0] io_inputs_1_payload_fragment_context, + output io_output_valid, + input io_output_ready, + output io_output_payload_last, + output [0:0] io_output_payload_fragment_source, + output [0:0] io_output_payload_fragment_opcode, + output [31:0] io_output_payload_fragment_address, + output [5:0] io_output_payload_fragment_length, + output [31:0] io_output_payload_fragment_data, + output [3:0] io_output_payload_fragment_mask, + output [0:0] io_output_payload_fragment_context, + output [0:0] io_chosen, + output [1:0] io_chosenOH, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire [3:0] _zz__zz_maskProposal_0_2; + wire [3:0] _zz__zz_maskProposal_0_2_1; + wire [1:0] _zz__zz_maskProposal_0_2_2; + reg locked; + wire maskProposal_0; + wire maskProposal_1; + reg maskLocked_0; + reg maskLocked_1; + wire maskRouted_0; + wire maskRouted_1; + wire [1:0] _zz_maskProposal_0; + wire [3:0] _zz_maskProposal_0_1; + wire [3:0] _zz_maskProposal_0_2; + wire [1:0] _zz_maskProposal_0_3; + wire io_output_fire; + wire when_Stream_l621; + wire _zz_io_chosen; + + assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); + assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; + assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; + assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); + assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); + assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; + assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; + assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); + assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); + assign maskProposal_0 = _zz_maskProposal_0_3[0]; + assign maskProposal_1 = _zz_maskProposal_0_3[1]; + assign io_output_fire = (io_output_valid && io_output_ready); + assign when_Stream_l621 = (io_output_fire && io_output_payload_last); + assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); + assign io_output_payload_last = (maskRouted_0 ? io_inputs_0_payload_last : io_inputs_1_payload_last); + assign io_output_payload_fragment_source = (maskRouted_0 ? io_inputs_0_payload_fragment_source : io_inputs_1_payload_fragment_source); + assign io_output_payload_fragment_opcode = (maskRouted_0 ? io_inputs_0_payload_fragment_opcode : io_inputs_1_payload_fragment_opcode); + assign io_output_payload_fragment_address = (maskRouted_0 ? io_inputs_0_payload_fragment_address : io_inputs_1_payload_fragment_address); + assign io_output_payload_fragment_length = (maskRouted_0 ? io_inputs_0_payload_fragment_length : io_inputs_1_payload_fragment_length); + assign io_output_payload_fragment_data = (maskRouted_0 ? io_inputs_0_payload_fragment_data : io_inputs_1_payload_fragment_data); + assign io_output_payload_fragment_mask = (maskRouted_0 ? io_inputs_0_payload_fragment_mask : io_inputs_1_payload_fragment_mask); + assign io_output_payload_fragment_context = (maskRouted_0 ? io_inputs_0_payload_fragment_context : io_inputs_1_payload_fragment_context); + assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); + assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); + assign io_chosenOH = {maskRouted_1,maskRouted_0}; + assign _zz_io_chosen = io_chosenOH[1]; + assign io_chosen = _zz_io_chosen; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + locked <= 1'b0; + maskLocked_0 <= 1'b0; + maskLocked_1 <= 1'b1; + end else begin + if(io_output_valid) begin + maskLocked_0 <= maskRouted_0; + maskLocked_1 <= maskRouted_1; + end + if(io_output_valid) begin + locked <= 1'b1; + end + if(when_Stream_l621) begin + locked <= 1'b0; + end + end + end + + +endmodule + +module FlowCCByToggle ( + input io_input_valid, + input io_input_payload_last, + input [0:0] io_input_payload_fragment, + output io_output_valid, + output io_output_payload_last, + output [0:0] io_output_payload_fragment, + input jtagCtrl_tck, + input io_systemClk, + input debugCd_logic_outputReset +); + + wire inputArea_target_buffercc_io_dataOut; + reg inputArea_target; + reg inputArea_data_last; + reg [0:0] inputArea_data_fragment; + wire outputArea_target; + reg outputArea_hit; + wire outputArea_flow_valid; + wire outputArea_flow_payload_last; + wire [0:0] outputArea_flow_payload_fragment; + reg outputArea_flow_m2sPipe_valid; + reg outputArea_flow_m2sPipe_payload_last; + reg [0:0] outputArea_flow_m2sPipe_payload_fragment; + + BufferCC_1 inputArea_target_buffercc ( + .io_dataIn (inputArea_target ), //i + .io_dataOut (inputArea_target_buffercc_io_dataOut), //o + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i + ); + initial begin + `ifndef SYNTHESIS + inputArea_target = $urandom; + outputArea_hit = $urandom; + `endif + end + + assign outputArea_target = inputArea_target_buffercc_io_dataOut; + assign outputArea_flow_valid = (outputArea_target != outputArea_hit); + assign outputArea_flow_payload_last = inputArea_data_last; + assign outputArea_flow_payload_fragment = inputArea_data_fragment; + assign io_output_valid = outputArea_flow_m2sPipe_valid; + assign io_output_payload_last = outputArea_flow_m2sPipe_payload_last; + assign io_output_payload_fragment = outputArea_flow_m2sPipe_payload_fragment; + always @(posedge jtagCtrl_tck) begin + if(io_input_valid) begin + inputArea_target <= (! inputArea_target); + inputArea_data_last <= io_input_payload_last; + inputArea_data_fragment <= io_input_payload_fragment; + end + end + + always @(posedge io_systemClk) begin + outputArea_hit <= outputArea_target; + if(outputArea_flow_valid) begin + outputArea_flow_m2sPipe_payload_last <= outputArea_flow_payload_last; + outputArea_flow_m2sPipe_payload_fragment <= outputArea_flow_payload_fragment; + end + end + + always @(posedge io_systemClk) begin + if(debugCd_logic_outputReset) begin + outputArea_flow_m2sPipe_valid <= 1'b0; + end else begin + outputArea_flow_m2sPipe_valid <= outputArea_flow_valid; + end + end + + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output reg io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isFiring, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + input [31:0] io_cpu_writeBack_storeData, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output io_cpu_writeBack_exclusiveOk, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output io_cpu_flush_ready, + input io_cpu_flush_payload_singleLine, + input [5:0] io_cpu_flush_payload_lineId, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_size, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [21:0] _zz_ways_0_tags_port0; + reg [31:0] _zz_ways_0_data_port0; + wire [21:0] _zz_ways_0_tags_port; + wire [9:0] _zz_stage0_dataColisions; + wire [9:0] _zz__zz_stageA_dataColisions; + wire [0:0] _zz_when; + wire [3:0] _zz_loader_counter_valueNext; + wire [0:0] _zz_loader_counter_valueNext_1; + wire [1:0] _zz_loader_waysAllocator; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [5:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [5:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [5:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_ways_0_tagsReadRsp_valid_1; + wire _zz_ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire when_DataCache_l642; + wire when_DataCache_l645; + wire when_DataCache_l664; + wire rspSync; + wire rspLast; + reg memCmdSent; + wire io_mem_cmd_fire; + wire when_DataCache_l686; + reg [3:0] _zz_stage0_mask; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + wire stage0_isAmo; + wire when_DataCache_l771; + reg stageA_request_wr; + reg [1:0] stageA_request_size; + reg stageA_request_totalyConsistent; + wire when_DataCache_l771_1; + reg [3:0] stageA_mask; + wire stageA_isAmo; + wire stageA_isLrsc; + wire [0:0] stageA_wayHits; + wire when_DataCache_l771_2; + reg [0:0] stageA_wayInvalidate; + wire when_DataCache_l771_3; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_stageA_dataColisions; + wire [0:0] stageA_dataColisions; + wire when_DataCache_l822; + reg stageB_request_wr; + reg [1:0] stageB_request_size; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + wire when_DataCache_l824; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + wire when_DataCache_l821; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + wire when_DataCache_l821_1; + reg [31:0] stageB_dataReadRsp_0; + wire when_DataCache_l820; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + wire when_DataCache_l820_1; + reg [0:0] stageB_dataColisions; + wire when_DataCache_l820_2; + reg stageB_unaligned; + wire when_DataCache_l820_3; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + wire when_DataCache_l820_4; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_waitDone; + wire stageB_flusher_hold; + reg [6:0] stageB_flusher_counter; + wire when_DataCache_l850; + wire when_DataCache_l856; + reg stageB_flusher_start; + wire stageB_isAmo; + wire stageB_isAmoCached; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + wire [31:0] stageB_requestDataBypass; + reg stageB_cpuWriteToCache; + wire when_DataCache_l926; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + wire when_DataCache_l995; + wire when_DataCache_l1004; + wire when_DataCache_l1009; + wire when_DataCache_l1020; + wire when_DataCache_l1032; + wire when_DataCache_l991; + wire when_DataCache_l1066; + wire when_DataCache_l1075; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [3:0] loader_counter_valueNext; + reg [3:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire when_DataCache_l1090; + wire loader_done; + wire when_DataCache_l1118; + reg loader_valid_regNext; + wire when_DataCache_l1122; + wire when_DataCache_l1125; + reg [21:0] ways_0_tags [0:63]; + reg [7:0] ways_0_data_symbol0 [0:1023]; + reg [7:0] ways_0_data_symbol1 [0:1023]; + reg [7:0] ways_0_data_symbol2 [0:1023]; + reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_ways_0_datasymbol_read; + reg [7:0] _zz_ways_0_datasymbol_read_1; + reg [7:0] _zz_ways_0_datasymbol_read_2; + reg [7:0] _zz_ways_0_datasymbol_read_3; + + assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_when = 1'b1; + assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; + assign _zz_loader_counter_valueNext = {3'd0, _zz_loader_counter_valueNext_1}; + assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @(posedge io_systemClk) begin + if(_zz_ways_0_tagsReadRsp_valid) begin + _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; + end + end + + always @(*) begin + _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; + end + always @(posedge io_systemClk) begin + if(_zz_ways_0_dataReadRspMem) begin + _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @(posedge io_systemClk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(when_DataCache_l645) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + _zz_2 = 1'b0; + if(when_DataCache_l642) begin + _zz_2 = 1'b1; + end + end + + assign haltCpu = 1'b0; + assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; + assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; + assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; + assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2]; + assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + assign when_DataCache_l642 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); + assign when_DataCache_l645 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); + always @(*) begin + tagsReadCmd_valid = 1'b0; + if(when_DataCache_l664) begin + tagsReadCmd_valid = 1'b1; + end + end + + always @(*) begin + tagsReadCmd_payload = 6'bxxxxxx; + if(when_DataCache_l664) begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 6]; + end + end + + always @(*) begin + dataReadCmd_valid = 1'b0; + if(when_DataCache_l664) begin + dataReadCmd_valid = 1'b1; + end + end + + always @(*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(when_DataCache_l664) begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + end + end + + always @(*) begin + tagsWriteCmd_valid = 1'b0; + if(when_DataCache_l850) begin + tagsWriteCmd_valid = 1'b1; + end + if(when_DataCache_l1066) begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_done) begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @(*) begin + tagsWriteCmd_payload_way = 1'bx; + if(when_DataCache_l850) begin + tagsWriteCmd_payload_way = 1'b1; + end + if(loader_done) begin + tagsWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @(*) begin + tagsWriteCmd_payload_address = 6'bxxxxxx; + if(when_DataCache_l850) begin + tagsWriteCmd_payload_address = stageB_flusher_counter[5:0]; + end + if(loader_done) begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 6]; + end + end + + always @(*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(when_DataCache_l850) begin + tagsWriteCmd_payload_data_valid = 1'b0; + end + if(loader_done) begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); + end + end + + always @(*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done) begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); + end + end + + always @(*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done) begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + end + end + + always @(*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache) begin + if(when_DataCache_l926) begin + dataWriteCmd_valid = 1'b1; + end + end + if(when_DataCache_l1066) begin + dataWriteCmd_valid = 1'b0; + end + if(when_DataCache_l1090) begin + dataWriteCmd_valid = 1'b1; + end + end + + always @(*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_way = stageB_waysHits; + end + if(when_DataCache_l1090) begin + dataWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @(*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + end + if(when_DataCache_l1090) begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 6],loader_counter_value}; + end + end + + always @(*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; + end + if(when_DataCache_l1090) begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; + end + end + + always @(*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_when[0]) begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end + end + if(when_DataCache_l1090) begin + dataWriteCmd_payload_mask = 4'b1111; + end + end + + assign when_DataCache_l664 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + always @(*) begin + io_cpu_execute_haltIt = 1'b0; + if(when_DataCache_l850) begin + io_cpu_execute_haltIt = 1'b1; + end + end + + assign rspSync = 1'b1; + assign rspLast = 1'b1; + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign when_DataCache_l686 = (! io_cpu_writeBack_isStuck); + always @(*) begin + _zz_stage0_mask = 4'bxxxx; + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_stage0_mask = 4'b0001; + end + 2'b01 : begin + _zz_stage0_mask = 4'b0011; + end + 2'b10 : begin + _zz_stage0_mask = 4'b1111; + end + default : begin + end + endcase + end + + assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign stage0_isAmo = 1'b0; + assign when_DataCache_l771 = (! io_cpu_memory_isStuck); + assign when_DataCache_l771_1 = (! io_cpu_memory_isStuck); + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_isAmo = 1'b0; + assign stageA_isLrsc = 1'b0; + assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign when_DataCache_l771_2 = (! io_cpu_memory_isStuck); + assign when_DataCache_l771_3 = (! io_cpu_memory_isStuck); + assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); + assign when_DataCache_l822 = (! io_cpu_writeBack_isStuck); + always @(*) begin + stageB_mmuRspFreeze = 1'b0; + if(when_DataCache_l1125) begin + stageB_mmuRspFreeze = 1'b1; + end + end + + assign when_DataCache_l824 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign when_DataCache_l821 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l821_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l820 = (! io_cpu_writeBack_isStuck); + assign stageB_consistancyHazard = 1'b0; + assign when_DataCache_l820_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l820_2 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l820_3 = (! io_cpu_writeBack_isStuck); + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (|stageB_waysHits); + assign stageB_dataMux = stageB_dataReadRsp_0; + assign when_DataCache_l820_4 = (! io_cpu_writeBack_isStuck); + always @(*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(!when_DataCache_l1004) begin + if(io_mem_cmd_ready) begin + stageB_loaderValid = 1'b1; + end + end + end + end + end + if(when_DataCache_l1066) begin + stageB_loaderValid = 1'b0; + end + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @(*) begin + io_cpu_writeBack_haltIt = 1'b1; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l991) begin + if(when_DataCache_l995) begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(when_DataCache_l1004) begin + if(when_DataCache_l1009) begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end + end + if(when_DataCache_l1066) begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + + assign stageB_flusher_hold = 1'b0; + assign when_DataCache_l850 = (! stageB_flusher_counter[6]); + assign when_DataCache_l856 = (! stageB_flusher_hold); + assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[6]); + assign stageB_isAmo = 1'b0; + assign stageB_isAmoCached = 1'b0; + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + assign stageB_requestDataBypass = io_cpu_writeBack_storeData; + always @(*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(when_DataCache_l1004) begin + stageB_cpuWriteToCache = 1'b1; + end + end + end + end + end + + assign when_DataCache_l926 = (stageB_request_wr && stageB_waysHit); + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @(*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(when_DataCache_l1004) begin + if(when_DataCache_l1020) begin + io_cpu_redo = 1'b1; + end + end + end + end + end + if(when_DataCache_l1075) begin + io_cpu_redo = 1'b1; + end + if(when_DataCache_l1122) begin + io_cpu_redo = 1'b1; + end + end + + always @(*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache) begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + end + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @(*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l991) begin + io_mem_cmd_valid = (! memCmdSent); + end else begin + if(when_DataCache_l1004) begin + if(stageB_request_wr) begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if(when_DataCache_l1032) begin + io_mem_cmd_valid = 1'b1; + end + end + end + end + end + if(when_DataCache_l1066) begin + io_mem_cmd_valid = 1'b0; + end + end + + always @(*) begin + io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(!when_DataCache_l1004) begin + io_mem_cmd_payload_address[5 : 0] = 6'h0; + end + end + end + end + end + + assign io_mem_cmd_payload_last = 1'b1; + always @(*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(!when_DataCache_l1004) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end + end + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + always @(*) begin + io_mem_cmd_payload_size = {1'd0, stageB_request_size}; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(!when_DataCache_l1004) begin + io_mem_cmd_payload_size = 3'b110; + end + end + end + end + end + + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + assign when_DataCache_l995 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); + assign when_DataCache_l1004 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign when_DataCache_l1009 = ((! stageB_request_wr) || io_mem_cmd_ready); + assign when_DataCache_l1020 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign when_DataCache_l1032 = (! memCmdSent); + assign when_DataCache_l991 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + always @(*) begin + if(stageB_bypassCache) begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; + end + end + + assign when_DataCache_l1066 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign when_DataCache_l1075 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); + always @(*) begin + loader_counter_willIncrement = 1'b0; + if(when_DataCache_l1090) begin + loader_counter_willIncrement = 1'b1; + end + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 4'b1111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @(*) begin + loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); + if(loader_counter_willClear) begin + loader_counter_valueNext = 4'b0000; + end + end + + assign loader_kill = 1'b0; + assign when_DataCache_l1090 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign loader_done = loader_counter_willOverflow; + assign when_DataCache_l1118 = (! loader_valid); + assign when_DataCache_l1122 = (loader_valid && (! loader_valid_regNext)); + assign io_cpu_execute_refilling = loader_valid; + assign when_DataCache_l1125 = (stageB_loaderValid || loader_valid); + always @(posedge io_systemClk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if(when_DataCache_l771) begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; + end + if(when_DataCache_l771_1) begin + stageA_mask <= stage0_mask; + end + if(when_DataCache_l771_2) begin + stageA_wayInvalidate <= stage0_wayInvalidate; + end + if(when_DataCache_l771_3) begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; + end + if(when_DataCache_l822) begin + stageB_request_wr <= stageA_request_wr; + stageB_request_size <= stageA_request_size; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(when_DataCache_l824) begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; + end + if(when_DataCache_l821) begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; + end + if(when_DataCache_l821_1) begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; + end + if(when_DataCache_l820) begin + stageB_wayInvalidate <= stageA_wayInvalidate; + end + if(when_DataCache_l820_1) begin + stageB_dataColisions <= stageA_dataColisions; + end + if(when_DataCache_l820_2) begin + stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); + end + if(when_DataCache_l820_3) begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; + end + if(when_DataCache_l820_4) begin + stageB_mask <= stageA_mask; + end + loader_valid_regNext <= loader_valid; + end + + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + memCmdSent <= 1'b0; + stageB_flusher_waitDone <= 1'b0; + stageB_flusher_counter <= 7'h0; + stageB_flusher_start <= 1'b1; + loader_valid <= 1'b0; + loader_counter_value <= 4'b0000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_fire) begin + memCmdSent <= 1'b1; + end + if(when_DataCache_l686) begin + memCmdSent <= 1'b0; + end + if(io_cpu_flush_ready) begin + stageB_flusher_waitDone <= 1'b0; + end + if(when_DataCache_l850) begin + if(when_DataCache_l856) begin + stageB_flusher_counter <= (stageB_flusher_counter + 7'h01); + if(io_cpu_flush_payload_singleLine) begin + stageB_flusher_counter[6] <= 1'b1; + end + end + end + stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start) begin + stageB_flusher_waitDone <= 1'b1; + stageB_flusher_counter <= 7'h0; + if(io_cpu_flush_payload_singleLine) begin + stageB_flusher_counter <= {1'b0,io_cpu_flush_payload_lineId}; + end + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); // DataCache.scala:L1077 + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("ERROR writeBack stuck by another plugin is not allowed"); // DataCache.scala:L1077 + end + `endif + `endif + if(stageB_loaderValid) begin + loader_valid <= 1'b1; + end + loader_counter_value <= loader_counter_valueNext; + if(loader_kill) begin + loader_killReg <= 1'b1; + end + if(when_DataCache_l1090) begin + loader_error <= (loader_error || io_mem_rsp_payload_error); + end + if(loader_done) begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end + if(when_DataCache_l1118) begin + loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; + end + end + end + + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [31:0] _zz_banks_0_port1; + reg [21:0] _zz_ways_0_tags_port1; + wire [21:0] _zz_ways_0_tags_port; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [6:0] lineLoader_flushCounter; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; + reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l513; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [3:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [5:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire when_InstructionCache_l401; + wire [9:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [5:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; + reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + wire when_InstructionCache_l459_1; + reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; + reg decodeStage_hit_error; + reg [31:0] banks_0 [0:1023]; + reg [21:0] ways_0_tags [0:63]; + + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge io_systemClk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @(posedge io_systemClk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; + end + end + + always @(posedge io_systemClk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid) begin + _zz_2 = 1'b1; + end + end + + always @(*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin + lineLoader_fire = 1'b1; + end + end + end + + always @(*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(when_InstructionCache_l338) begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(when_InstructionCache_l342) begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush) begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[6]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 6],6'h0}; + assign io_mem_cmd_payload_size = 3'b110; + assign when_Utils_l513 = (! lineLoader_valid); + always @(*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if(when_Utils_l513) begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[11 : 6] : lineLoader_flushCounter[5 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 6],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data[31 : 0]; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 4'b1111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[11 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[11 : 6]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[21 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = (|fetchStage_hit_hits_0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 4'b0000; + end else begin + if(lineLoader_fire) begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire) begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid) begin + lineLoader_valid <= 1'b1; + end + if(io_flush) begin + lineLoader_flushPending <= 1'b1; + end + if(when_InstructionCache_l351) begin + lineLoader_flushPending <= 1'b0; + end + if(io_mem_cmd_fire) begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire) begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid) begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 4'b0001); + if(io_mem_rsp_payload_error) begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @(posedge io_systemClk) begin + if(io_cpu_fill_valid) begin + lineLoader_address <= io_cpu_fill_payload; + end + if(when_InstructionCache_l338) begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); + end + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[6]; + if(when_InstructionCache_l351) begin + lineLoader_flushCounter <= 7'h0; + end + if(when_InstructionCache_l435) begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if(when_InstructionCache_l459) begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + end + if(when_InstructionCache_l459_1) begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if(when_InstructionCache_l459_2) begin + decodeStage_hit_error <= fetchStage_hit_error; + end + end + + +endmodule + +module UartCtrlRx ( + input [2:0] io_configFrame_dataLength, + input [0:0] io_configFrame_stop, + input [1:0] io_configFrame_parity, + input io_samplingTick, + output io_read_valid, + input io_read_ready, + output [7:0] io_read_payload, + input io_rxd, + output io_rts, + output reg io_error, + output io_break, + input io_systemClk, + input systemCd_logic_outputReset +); + localparam UartStopType_ONE = 1'd0; + localparam UartStopType_TWO = 1'd1; + localparam UartParityType_NONE = 2'd0; + localparam UartParityType_EVEN = 2'd1; + localparam UartParityType_ODD = 2'd2; + localparam UartCtrlRxState_IDLE = 3'd0; + localparam UartCtrlRxState_START = 3'd1; + localparam UartCtrlRxState_DATA = 3'd2; + localparam UartCtrlRxState_PARITY = 3'd3; + localparam UartCtrlRxState_STOP = 3'd4; + + wire io_rxd_buffercc_io_dataOut; + wire _zz_sampler_value; + wire _zz_sampler_value_1; + wire _zz_sampler_value_2; + wire _zz_sampler_value_3; + wire _zz_sampler_value_4; + wire _zz_sampler_value_5; + wire _zz_sampler_value_6; + wire [2:0] _zz_when_UartCtrlRx_l139; + wire [0:0] _zz_when_UartCtrlRx_l139_1; + reg _zz_io_rts; + wire sampler_synchroniser; + wire sampler_samples_0; + reg sampler_samples_1; + reg sampler_samples_2; + reg sampler_samples_3; + reg sampler_samples_4; + reg sampler_value; + reg sampler_tick; + reg [2:0] bitTimer_counter; + reg bitTimer_tick; + wire when_UartCtrlRx_l43; + reg [2:0] bitCounter_value; + reg [6:0] break_counter; + wire break_valid; + wire when_UartCtrlRx_l69; + reg [2:0] stateMachine_state; + reg stateMachine_parity; + reg [7:0] stateMachine_shifter; + reg stateMachine_validReg; + wire when_UartCtrlRx_l93; + wire when_UartCtrlRx_l103; + wire when_UartCtrlRx_l111; + wire when_UartCtrlRx_l113; + wire when_UartCtrlRx_l125; + wire when_UartCtrlRx_l136; + wire when_UartCtrlRx_l139; + `ifndef SYNTHESIS + reg [23:0] io_configFrame_stop_string; + reg [31:0] io_configFrame_parity_string; + reg [47:0] stateMachine_state_string; + `endif + + + assign _zz_when_UartCtrlRx_l139_1 = ((io_configFrame_stop == UartStopType_ONE) ? 1'b0 : 1'b1); + assign _zz_when_UartCtrlRx_l139 = {2'd0, _zz_when_UartCtrlRx_l139_1}; + assign _zz_sampler_value = ((((1'b0 || ((_zz_sampler_value_1 && sampler_samples_1) && sampler_samples_2)) || (((_zz_sampler_value_2 && sampler_samples_0) && sampler_samples_1) && sampler_samples_3)) || (((1'b1 && sampler_samples_0) && sampler_samples_2) && sampler_samples_3)) || (((1'b1 && sampler_samples_1) && sampler_samples_2) && sampler_samples_3)); + assign _zz_sampler_value_3 = (((1'b1 && sampler_samples_0) && sampler_samples_1) && sampler_samples_4); + assign _zz_sampler_value_4 = ((1'b1 && sampler_samples_0) && sampler_samples_2); + assign _zz_sampler_value_5 = (1'b1 && sampler_samples_1); + assign _zz_sampler_value_6 = 1'b1; + assign _zz_sampler_value_1 = (1'b1 && sampler_samples_0); + assign _zz_sampler_value_2 = 1'b1; + BufferCC io_rxd_buffercc ( + .io_dataIn (io_rxd ), //i + .io_dataOut (io_rxd_buffercc_io_dataOut), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_configFrame_stop) + UartStopType_ONE : io_configFrame_stop_string = "ONE"; + UartStopType_TWO : io_configFrame_stop_string = "TWO"; + default : io_configFrame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_configFrame_parity) + UartParityType_NONE : io_configFrame_parity_string = "NONE"; + UartParityType_EVEN : io_configFrame_parity_string = "EVEN"; + UartParityType_ODD : io_configFrame_parity_string = "ODD "; + default : io_configFrame_parity_string = "????"; + endcase + end + always @(*) begin + case(stateMachine_state) + UartCtrlRxState_IDLE : stateMachine_state_string = "IDLE "; + UartCtrlRxState_START : stateMachine_state_string = "START "; + UartCtrlRxState_DATA : stateMachine_state_string = "DATA "; + UartCtrlRxState_PARITY : stateMachine_state_string = "PARITY"; + UartCtrlRxState_STOP : stateMachine_state_string = "STOP "; + default : stateMachine_state_string = "??????"; + endcase + end + `endif + + always @(*) begin + io_error = 1'b0; + case(stateMachine_state) + UartCtrlRxState_IDLE : begin + end + UartCtrlRxState_START : begin + end + UartCtrlRxState_DATA : begin + end + UartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + if(!when_UartCtrlRx_l125) begin + io_error = 1'b1; + end + end + end + default : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l136) begin + io_error = 1'b1; + end + end + end + endcase + end + + assign io_rts = _zz_io_rts; + assign sampler_synchroniser = io_rxd_buffercc_io_dataOut; + assign sampler_samples_0 = sampler_synchroniser; + always @(*) begin + bitTimer_tick = 1'b0; + if(sampler_tick) begin + if(when_UartCtrlRx_l43) begin + bitTimer_tick = 1'b1; + end + end + end + + assign when_UartCtrlRx_l43 = (bitTimer_counter == 3'b000); + assign break_valid = (break_counter == 7'h68); + assign when_UartCtrlRx_l69 = (io_samplingTick && (! break_valid)); + assign io_break = break_valid; + assign io_read_valid = stateMachine_validReg; + assign when_UartCtrlRx_l93 = ((sampler_tick && (! sampler_value)) && (! break_valid)); + assign when_UartCtrlRx_l103 = (sampler_value == 1'b1); + assign when_UartCtrlRx_l111 = (bitCounter_value == io_configFrame_dataLength); + assign when_UartCtrlRx_l113 = (io_configFrame_parity == UartParityType_NONE); + assign when_UartCtrlRx_l125 = (stateMachine_parity == sampler_value); + assign when_UartCtrlRx_l136 = (! sampler_value); + assign when_UartCtrlRx_l139 = (bitCounter_value == _zz_when_UartCtrlRx_l139); + assign io_read_payload = stateMachine_shifter; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + _zz_io_rts <= 1'b0; + sampler_samples_1 <= 1'b1; + sampler_samples_2 <= 1'b1; + sampler_samples_3 <= 1'b1; + sampler_samples_4 <= 1'b1; + sampler_value <= 1'b1; + sampler_tick <= 1'b0; + break_counter <= 7'h0; + stateMachine_state <= UartCtrlRxState_IDLE; + stateMachine_validReg <= 1'b0; + end else begin + _zz_io_rts <= (! io_read_ready); + if(io_samplingTick) begin + sampler_samples_1 <= sampler_samples_0; + end + if(io_samplingTick) begin + sampler_samples_2 <= sampler_samples_1; + end + if(io_samplingTick) begin + sampler_samples_3 <= sampler_samples_2; + end + if(io_samplingTick) begin + sampler_samples_4 <= sampler_samples_3; + end + sampler_value <= ((((((_zz_sampler_value || _zz_sampler_value_3) || (_zz_sampler_value_4 && sampler_samples_4)) || ((_zz_sampler_value_5 && sampler_samples_2) && sampler_samples_4)) || (((_zz_sampler_value_6 && sampler_samples_0) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_1) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_2) && sampler_samples_3) && sampler_samples_4)); + sampler_tick <= io_samplingTick; + if(sampler_value) begin + break_counter <= 7'h0; + end else begin + if(when_UartCtrlRx_l69) begin + break_counter <= (break_counter + 7'h01); + end + end + stateMachine_validReg <= 1'b0; + case(stateMachine_state) + UartCtrlRxState_IDLE : begin + if(when_UartCtrlRx_l93) begin + stateMachine_state <= UartCtrlRxState_START; + end + end + UartCtrlRxState_START : begin + if(bitTimer_tick) begin + stateMachine_state <= UartCtrlRxState_DATA; + if(when_UartCtrlRx_l103) begin + stateMachine_state <= UartCtrlRxState_IDLE; + end + end + end + UartCtrlRxState_DATA : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l111) begin + if(when_UartCtrlRx_l113) begin + stateMachine_state <= UartCtrlRxState_STOP; + stateMachine_validReg <= 1'b1; + end else begin + stateMachine_state <= UartCtrlRxState_PARITY; + end + end + end + end + UartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l125) begin + stateMachine_state <= UartCtrlRxState_STOP; + stateMachine_validReg <= 1'b1; + end else begin + stateMachine_state <= UartCtrlRxState_IDLE; + end + end + end + default : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l136) begin + stateMachine_state <= UartCtrlRxState_IDLE; + end else begin + if(when_UartCtrlRx_l139) begin + stateMachine_state <= UartCtrlRxState_IDLE; + end + end + end + end + endcase + end + end + + always @(posedge io_systemClk) begin + if(sampler_tick) begin + bitTimer_counter <= (bitTimer_counter - 3'b001); + end + if(bitTimer_tick) begin + bitCounter_value <= (bitCounter_value + 3'b001); + end + if(bitTimer_tick) begin + stateMachine_parity <= (stateMachine_parity ^ sampler_value); + end + case(stateMachine_state) + UartCtrlRxState_IDLE : begin + if(when_UartCtrlRx_l93) begin + bitTimer_counter <= 3'b010; + end + end + UartCtrlRxState_START : begin + if(bitTimer_tick) begin + bitCounter_value <= 3'b000; + stateMachine_parity <= (io_configFrame_parity == UartParityType_ODD); + end + end + UartCtrlRxState_DATA : begin + if(bitTimer_tick) begin + stateMachine_shifter[bitCounter_value] <= sampler_value; + if(when_UartCtrlRx_l111) begin + bitCounter_value <= 3'b000; + end + end + end + UartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + bitCounter_value <= 3'b000; + end + end + default : begin + end + endcase + end + + +endmodule + +module UartCtrlTx ( + input [2:0] io_configFrame_dataLength, + input [0:0] io_configFrame_stop, + input [1:0] io_configFrame_parity, + input io_samplingTick, + input io_write_valid, + output reg io_write_ready, + input [7:0] io_write_payload, + input io_cts, + output io_txd, + input io_break, + input io_systemClk, + input systemCd_logic_outputReset +); + localparam UartStopType_ONE = 1'd0; + localparam UartStopType_TWO = 1'd1; + localparam UartParityType_NONE = 2'd0; + localparam UartParityType_EVEN = 2'd1; + localparam UartParityType_ODD = 2'd2; + localparam UartCtrlTxState_IDLE = 3'd0; + localparam UartCtrlTxState_START = 3'd1; + localparam UartCtrlTxState_DATA = 3'd2; + localparam UartCtrlTxState_PARITY = 3'd3; + localparam UartCtrlTxState_STOP = 3'd4; + + wire [2:0] _zz_clockDivider_counter_valueNext; + wire [0:0] _zz_clockDivider_counter_valueNext_1; + wire [2:0] _zz_when_UartCtrlTx_l93; + wire [0:0] _zz_when_UartCtrlTx_l93_1; + reg clockDivider_counter_willIncrement; + wire clockDivider_counter_willClear; + reg [2:0] clockDivider_counter_valueNext; + reg [2:0] clockDivider_counter_value; + wire clockDivider_counter_willOverflowIfInc; + wire clockDivider_counter_willOverflow; + reg [2:0] tickCounter_value; + reg [2:0] stateMachine_state; + reg stateMachine_parity; + reg stateMachine_txd; + wire when_UartCtrlTx_l58; + wire when_UartCtrlTx_l73; + wire when_UartCtrlTx_l76; + wire when_UartCtrlTx_l93; + reg _zz_io_txd; + `ifndef SYNTHESIS + reg [23:0] io_configFrame_stop_string; + reg [31:0] io_configFrame_parity_string; + reg [47:0] stateMachine_state_string; + `endif + + + assign _zz_clockDivider_counter_valueNext_1 = clockDivider_counter_willIncrement; + assign _zz_clockDivider_counter_valueNext = {2'd0, _zz_clockDivider_counter_valueNext_1}; + assign _zz_when_UartCtrlTx_l93_1 = ((io_configFrame_stop == UartStopType_ONE) ? 1'b0 : 1'b1); + assign _zz_when_UartCtrlTx_l93 = {2'd0, _zz_when_UartCtrlTx_l93_1}; + `ifndef SYNTHESIS + always @(*) begin + case(io_configFrame_stop) + UartStopType_ONE : io_configFrame_stop_string = "ONE"; + UartStopType_TWO : io_configFrame_stop_string = "TWO"; + default : io_configFrame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_configFrame_parity) + UartParityType_NONE : io_configFrame_parity_string = "NONE"; + UartParityType_EVEN : io_configFrame_parity_string = "EVEN"; + UartParityType_ODD : io_configFrame_parity_string = "ODD "; + default : io_configFrame_parity_string = "????"; + endcase + end + always @(*) begin + case(stateMachine_state) + UartCtrlTxState_IDLE : stateMachine_state_string = "IDLE "; + UartCtrlTxState_START : stateMachine_state_string = "START "; + UartCtrlTxState_DATA : stateMachine_state_string = "DATA "; + UartCtrlTxState_PARITY : stateMachine_state_string = "PARITY"; + UartCtrlTxState_STOP : stateMachine_state_string = "STOP "; + default : stateMachine_state_string = "??????"; + endcase + end + `endif + + always @(*) begin + clockDivider_counter_willIncrement = 1'b0; + if(io_samplingTick) begin + clockDivider_counter_willIncrement = 1'b1; + end + end + + assign clockDivider_counter_willClear = 1'b0; + assign clockDivider_counter_willOverflowIfInc = (clockDivider_counter_value == 3'b111); + assign clockDivider_counter_willOverflow = (clockDivider_counter_willOverflowIfInc && clockDivider_counter_willIncrement); + always @(*) begin + clockDivider_counter_valueNext = (clockDivider_counter_value + _zz_clockDivider_counter_valueNext); + if(clockDivider_counter_willClear) begin + clockDivider_counter_valueNext = 3'b000; + end + end + + always @(*) begin + stateMachine_txd = 1'b1; + case(stateMachine_state) + UartCtrlTxState_IDLE : begin + end + UartCtrlTxState_START : begin + stateMachine_txd = 1'b0; + end + UartCtrlTxState_DATA : begin + stateMachine_txd = io_write_payload[tickCounter_value]; + end + UartCtrlTxState_PARITY : begin + stateMachine_txd = stateMachine_parity; + end + default : begin + end + endcase + end + + always @(*) begin + io_write_ready = io_break; + case(stateMachine_state) + UartCtrlTxState_IDLE : begin + end + UartCtrlTxState_START : begin + end + UartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + io_write_ready = 1'b1; + end + end + end + UartCtrlTxState_PARITY : begin + end + default : begin + end + endcase + end + + assign when_UartCtrlTx_l58 = ((io_write_valid && (! io_cts)) && clockDivider_counter_willOverflow); + assign when_UartCtrlTx_l73 = (tickCounter_value == io_configFrame_dataLength); + assign when_UartCtrlTx_l76 = (io_configFrame_parity == UartParityType_NONE); + assign when_UartCtrlTx_l93 = (tickCounter_value == _zz_when_UartCtrlTx_l93); + assign io_txd = _zz_io_txd; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + clockDivider_counter_value <= 3'b000; + stateMachine_state <= UartCtrlTxState_IDLE; + _zz_io_txd <= 1'b1; + end else begin + clockDivider_counter_value <= clockDivider_counter_valueNext; + case(stateMachine_state) + UartCtrlTxState_IDLE : begin + if(when_UartCtrlTx_l58) begin + stateMachine_state <= UartCtrlTxState_START; + end + end + UartCtrlTxState_START : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_state <= UartCtrlTxState_DATA; + end + end + UartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + if(when_UartCtrlTx_l76) begin + stateMachine_state <= UartCtrlTxState_STOP; + end else begin + stateMachine_state <= UartCtrlTxState_PARITY; + end + end + end + end + UartCtrlTxState_PARITY : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_state <= UartCtrlTxState_STOP; + end + end + default : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l93) begin + stateMachine_state <= (io_write_valid ? UartCtrlTxState_START : UartCtrlTxState_IDLE); + end + end + end + endcase + _zz_io_txd <= (stateMachine_txd && (! io_break)); + end + end + + always @(posedge io_systemClk) begin + if(clockDivider_counter_willOverflow) begin + tickCounter_value <= (tickCounter_value + 3'b001); + end + if(clockDivider_counter_willOverflow) begin + stateMachine_parity <= (stateMachine_parity ^ stateMachine_txd); + end + case(stateMachine_state) + UartCtrlTxState_IDLE : begin + end + UartCtrlTxState_START : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_parity <= (io_configFrame_parity == UartParityType_ODD); + tickCounter_value <= 3'b000; + end + end + UartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + tickCounter_value <= 3'b000; + end + end + end + UartCtrlTxState_PARITY : begin + if(clockDivider_counter_willOverflow) begin + tickCounter_value <= 3'b000; + end + end + default : begin + end + endcase + end + + +endmodule + +module BufferCC_1 ( + input io_dataIn, + output io_dataOut, + input io_systemClk, + input debugCd_logic_outputReset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + initial begin + `ifndef SYNTHESIS + buffers_0 = $urandom; + buffers_1 = $urandom; + `endif + end + + assign io_dataOut = buffers_1; + always @(posedge io_systemClk) begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + + +endmodule + +module BufferCC ( + input io_dataIn, + output io_dataOut, + input io_systemClk, + input systemCd_logic_outputReset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + buffers_0 <= 1'b0; + buffers_1 <= 1'b0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule diff --git a/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol0.bin b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol0.bin new file mode 100644 index 0000000..c68d3c6 --- /dev/null +++ b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol0.bin @@ -0,0 +1,8192 @@ +10010111 +10010011 +00010011 +00010011 +10010011 +00010011 +01100011 +10000011 +00100011 +00010011 +10010011 +11100011 +00010011 +10010011 +01100011 +00100011 +00010011 +11100011 +11101111 +11101111 +01101111 +01100111 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01101111 +00110111 +10110111 +00010011 +10000011 +10110011 +11100011 +00010011 +00100011 +01100111 +00010011 +00100011 +10110111 +00010011 +00100011 +00100011 +00100011 +00100011 +00100011 +00110111 +10110111 +00010011 +10000011 +10110011 +11100011 +10110111 +10010011 +00110111 +00100011 +00010011 +10110111 +10000011 +10110011 +11100011 +10110111 +10010011 +00100011 +00010011 +11101111 +00110111 +10110111 +00010011 +10000011 +10110011 +11100011 +10110111 +10010011 +00100011 +10110111 +00000011 +10110111 +10010011 +00110011 +10110111 +10000011 +10110011 +11100011 +00110111 +10110111 +00010011 +10000011 +10110011 +11100011 +10110111 +10010011 +00100011 +00010011 +11101111 +00010011 +11101111 +00010011 +11101111 +00010011 +11101111 +00010011 +11101111 +00110111 +00110111 +10110111 +10110111 +00010011 +00010011 +00010011 +10000011 +10110011 +11100011 +00100011 +10000011 +10010011 +11100011 +00000011 +10010011 +00100011 +01100011 +00110111 +10110111 +00010011 +10000011 +10110011 +11100011 +10110111 +10010011 +00100011 +00001111 +00010011 +00010011 +00010011 +00010011 +00010011 +00010011 +10000011 +00110111 +00010011 +01100111 +10010011 +01101111 +00010011 +00100011 +00100011 +00010011 +00010011 +00110011 +00100011 +00100011 +00010011 +01100011 +10010011 +10000011 +10010011 +00010011 +11100111 +11100011 +00010011 +00010011 +00110011 +00010011 +01100011 +10010011 +10000011 +10010011 +00010011 +11100111 +11100011 +10000011 +00000011 +10000011 +00000011 +00010011 +01100111 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol1.bin b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol1.bin new file mode 100644 index 0000000..3951424 --- /dev/null +++ b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol1.bin @@ -0,0 +1,8192 @@ +10000001 +10000001 +10000001 +10000101 +10000101 +10000110 +11111100 +00100010 +10100000 +00000101 +10000101 +11101000 +10000101 +10000101 +01111000 +00100000 +00000101 +01101100 +01110000 +01110000 +00000000 +10000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000111 +01000110 +00000111 +10100111 +11110111 +10001100 +01100101 +10100000 +10000000 +00000001 +00100110 +01000111 +00000111 +10100100 +10100000 +10100010 +10100100 +10100110 +00000111 +01000110 +00000111 +10100111 +11110111 +10001100 +00010111 +10000111 +00000111 +10100000 +00000111 +01000110 +10100111 +11110111 +10001100 +00010111 +10000111 +10100000 +00000101 +11110000 +00000111 +01000110 +00000111 +10100111 +11110111 +10001100 +00010111 +10000111 +10100000 +11000111 +10100111 +01010111 +10000111 +00000111 +11000110 +10100111 +00000111 +11011100 +00000111 +01000110 +00000111 +10100111 +11110111 +10001100 +00010111 +10000111 +10100000 +00000101 +11110000 +00000101 +11110000 +00000101 +11110000 +00000101 +11110000 +00000101 +11110000 +00000110 +10000111 +00000110 +01000111 +00000110 +00001000 +00000111 +10100101 +11110101 +10001100 +10100000 +10100101 +11010101 +10001100 +10100101 +10000101 +10000000 +10011010 +00000111 +01000110 +00000111 +10100111 +11110111 +10001100 +00010111 +10000111 +10100000 +00010000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00100000 +00000011 +00000001 +00000000 +10000110 +11110000 +00000001 +00100100 +00100000 +10000100 +10001001 +00001001 +00100110 +00100010 +01011001 +00001110 +00000100 +00100111 +10000100 +00000100 +10000000 +00011000 +10000100 +10001001 +00001001 +01011001 +00001110 +00000100 +00100111 +10000100 +00000100 +10000000 +00011000 +00100000 +00100100 +00100100 +00101001 +00000001 +10000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol2.bin b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol2.bin new file mode 100644 index 0000000..93fa610 --- /dev/null +++ b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol2.bin @@ -0,0 +1,8192 @@ +00000000 +10000001 +01000001 +11000001 +11000001 +01000001 +11000101 +00000101 +01010101 +01000101 +01000101 +11000101 +01000001 +10000001 +10110101 +00000101 +01000101 +10110101 +10010000 +01010000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +10000000 +00000001 +00000001 +11110111 +01000110 +11100111 +00000111 +00000101 +10100110 +00000000 +00000001 +00010001 +00000001 +00100000 +00000111 +11100111 +11100111 +11100111 +11100111 +00000001 +00000001 +11110111 +01000110 +11100111 +00000111 +00000000 +00000111 +00000001 +11110110 +11110111 +00000001 +01000110 +11100111 +00000111 +00000000 +00000111 +11110110 +10110000 +11011111 +00000001 +00000001 +11110111 +01000110 +11100111 +00000111 +00000000 +00000111 +11110110 +10110000 +10000111 +00000000 +00000111 +11110111 +10110000 +10000110 +11110111 +00000111 +00000001 +00000001 +11110111 +01000110 +11100111 +00000111 +00000000 +00000111 +11110110 +10110000 +10011111 +10000000 +00011111 +00000000 +10011111 +00000000 +00011111 +00000000 +10011111 +00000001 +00000000 +00000000 +00000001 +11110110 +00000000 +00000111 +01000111 +11000101 +00000101 +00000111 +01000111 +00000101 +00000101 +00000111 +00010110 +10100110 +11100101 +00000001 +00000001 +11110111 +01000110 +11100111 +00000111 +00000000 +00000111 +11110110 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11000001 +00000000 +00000001 +00000011 +00000101 +00011111 +00000001 +10000001 +00100001 +11000001 +11000001 +10001001 +00010001 +10010001 +00101001 +00001001 +00000000 +00000100 +00010100 +01000100 +00000111 +10011001 +11000001 +11000001 +10001001 +00101001 +00001001 +00000000 +00000100 +00010100 +01000100 +00000111 +10011001 +11000001 +10000001 +01000001 +00000001 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol3.bin b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol3.bin new file mode 100644 index 0000000..5c4a759 --- /dev/null +++ b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol3.bin @@ -0,0 +1,8192 @@ +00000000 +01100100 +10001001 +10000000 +10000000 +10000001 +00000000 +00000000 +00000000 +00000000 +00000000 +11111110 +10000001 +10000001 +00000000 +00000000 +00000000 +11111110 +01011000 +00111011 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000010 +00000000 +11111000 +11111111 +00000000 +00000000 +11111110 +00010000 +00000000 +00000000 +11111111 +00000000 +11111000 +00000000 +00000000 +00000010 +00000010 +00000010 +00000010 +00000000 +11111000 +11111111 +00000000 +00000000 +11111110 +00000000 +10000000 +00000000 +00000000 +11111111 +11111000 +00000000 +00000000 +11111110 +00000000 +10001000 +00000000 +00001010 +11110110 +00000000 +11111000 +11111111 +00000000 +00000000 +11111110 +00000000 +10000000 +00000000 +11111000 +11111111 +00000000 +11100010 +00000000 +11111000 +11111111 +01000000 +11111110 +00000000 +11111000 +11111111 +00000000 +00000000 +11111110 +00000000 +10001000 +00000000 +00000000 +11101111 +00000011 +11101111 +00000000 +11101110 +00000000 +11101110 +00000000 +11101101 +00000000 +11111001 +11111001 +11111000 +11111111 +00100000 +11000000 +00000000 +00000000 +11111110 +00000001 +00000000 +00000001 +11111110 +00000000 +00000000 +00000000 +00000100 +00000000 +11111000 +11111111 +00000000 +00000000 +11111110 +00000000 +10000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111001 +00000001 +00000000 +00000000 +11111000 +11111111 +00000000 +00000001 +10000000 +10000000 +01000000 +00000000 +00000000 +01000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111110 +10000000 +10000000 +01000000 +01000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111110 +00000000 +00000000 +00000000 +00000000 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/soc_config b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/soc_config new file mode 100644 index 0000000..d77dacb --- /dev/null +++ b/fpga/ip/gTSE/T120F324_devkit/ip/sapphire/source/soc_config @@ -0,0 +1,23 @@ +--ramHex "/projects/SSE/kmlau/install/efinity/2022.1/ipm/ip/efx_soc/efx_soc/generator/bootloader/bootloader_32K.hex" +--cpuCount 1 +--spi name=system_spi_0_io,address=0x014000,interruptId=4,width=8,ssCount=1 +--Fpu false +--uart name=system_uart_0_io,address=0x010000,interruptId=1 +--L1I true +--dCacheSize 4096 +--axiAEnable false +--onChipRamSize 0x8000 +--iCacheWays 1 +--apbSlave name=io_apbSlave_0,address=0x100000,size=65536 +--ddrAEnable false +--iCacheSize 4096 +--onChipRamAddress 0xf9000000 +--Atomic false +--PeripheralClock false +--softTap false +--customInstruction false +--apbBridgeAddress 0xf8000000 +--L1D true +--Linux false +--dCacheWays 1 +--systemFrequency 50000000 diff --git a/fpga/ip/gTSE/T120F324_devkit/mac_pat_gen.v b/fpga/ip/gTSE/T120F324_devkit/mac_pat_gen.v new file mode 100644 index 0000000..64c5fed --- /dev/null +++ b/fpga/ip/gTSE/T120F324_devkit/mac_pat_gen.v @@ -0,0 +1,241 @@ +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / +// / / .' / +// __/ /.' / +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* +`timescale 1 ns / 1 ns +module mac_pat_gen +( +//Globle Signals +input clk, +input rstn, +//Control Interface +input pat_gen_en, +input [15:0] pat_gen_num,//When value is 0, it's infinite mode +input [15:0] pat_gen_ipg, +//MAC Protocol Signals +input [47:0] dst_mac, +input [47:0] src_mac, +input [15:0] mac_dlen, +//AXI4-Stream Interface +input rclk, +input rrstn, +input [7:0] rdata, +input rvalid, +input rlast, + +output reg [7:0] tdata, +output reg tvalid, +output reg tlast, +input tready +); + +// Parameter Define +localparam IDLE = 2'h0; +localparam PAT_IPG = 2'h1; +localparam PAT_GEN = 2'h2; + +// Register Define +reg pat_gen_en_dl1; +reg pat_gen_en_dl2; +reg [1:0] cur_state; +reg [1:0] next_state; +reg pat_en; +reg infinite_en; +reg [15:0] num_cnt; +reg [15:0] ipg_cnt; +reg [15:0] pat_cnt; + +reg [15:0] pat_gen_num_r; +reg [15:0] pat_gen_ipg_r; +reg [47:0] dst_mac_r; +reg [47:0] src_mac_r; +reg [15:0] mac_dlen_r; + +// Wire Define + +/*----------------------------------------------------------------------------------*\ + The main code +\*----------------------------------------------------------------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) begin + pat_gen_num_r <= 16'h0; + pat_gen_ipg_r <= 16'h0; + dst_mac_r <= 48'h0; + src_mac_r <= 48'h0; + mac_dlen_r <= 16'h0; + end + else begin + pat_gen_num_r <= pat_gen_num; + pat_gen_ipg_r <= pat_gen_ipg; + dst_mac_r <= dst_mac; + src_mac_r <= src_mac; + mac_dlen_r <= mac_dlen; + end +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + begin + pat_gen_en_dl1 <= 1'h0; + pat_gen_en_dl2 <= 1'h0; + end + else + begin + pat_gen_en_dl1 <= pat_gen_en; + pat_gen_en_dl2 <= pat_gen_en_dl1; + end +end + +/*----------------------- FSM Region ----------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + cur_state <= IDLE; + else + cur_state <= next_state; +end + +always @(*) + begin + case(cur_state) + IDLE : + if(pat_en == 1'b1) + next_state = PAT_GEN; + else + next_state = IDLE; + + PAT_IPG : + if((pat_en == 1'b1) || ((ipg_cnt == pat_gen_ipg_r) && (infinite_en == 1'b0) && (num_cnt == 16'h0))) + next_state = IDLE; + else if(ipg_cnt == pat_gen_ipg_r) + next_state = PAT_GEN; + else + next_state = PAT_IPG; + + PAT_GEN : + if((tlast == 1'b1) && (tready == 1'b1)) + next_state = PAT_IPG; + else + next_state = PAT_GEN; + + default : + next_state = IDLE; + endcase + end + +/*----------------------- Generator Control Region ----------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + pat_en <= 1'h0; + else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) + pat_en <= 1'h1; + else if((cur_state == IDLE) && (pat_en == 1'b1)) + pat_en <= 1'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + infinite_en <= 1'h0; + else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1) && (pat_gen_num_r == 16'h0)) + infinite_en <= 1'h1; + else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) + infinite_en <= 1'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + num_cnt <= 16'h0; + else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) + num_cnt <= pat_gen_num_r; + else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1) && (num_cnt != 16'h0)) + num_cnt <= num_cnt - 1'b1; +end + +/*----------------------- Pattern Counter Region ----------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ipg_cnt <= 16'h0; + else if(cur_state == PAT_IPG) + ipg_cnt <= ipg_cnt + 1'b1; + else + ipg_cnt <= 8'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + pat_cnt <= 16'h0; + else if(cur_state != PAT_GEN) + pat_cnt <= 16'h0; + else if(tready == 1'b1) + pat_cnt <= pat_cnt + 1'b1; +end + +/*----------------------- Pattern Generator Region ----------------------------*/ + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + tvalid <= 1'b0; + else if((cur_state == PAT_GEN) && (pat_cnt == 16'h0) && (tready == 1'b1)) + tvalid <= 1'b1; + else if((tready == 1'b1) && (tlast == 1'b1)) + tvalid <= 1'b0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + tdata <= 8'h0; + else if((cur_state == PAT_GEN) && (tready == 1'b1) && (pat_cnt <= 16'd14)) + case(pat_cnt[3:0]) + 4'd0 : tdata <= dst_mac_r[5*8 +: 8]; + 4'd1 : tdata <= dst_mac_r[4*8 +: 8]; + 4'd2 : tdata <= dst_mac_r[3*8 +: 8]; + 4'd3 : tdata <= dst_mac_r[2*8 +: 8]; + 4'd4 : tdata <= dst_mac_r[1*8 +: 8]; + 4'd5 : tdata <= dst_mac_r[0*8 +: 8]; + 4'd6 : tdata <= src_mac_r[5*8 +: 8]; + 4'd7 : tdata <= src_mac_r[4*8 +: 8]; + 4'd8 : tdata <= src_mac_r[3*8 +: 8]; + 4'd9 : tdata <= src_mac_r[2*8 +: 8]; + 4'd10 : tdata <= src_mac_r[1*8 +: 8]; + 4'd11 : tdata <= src_mac_r[0*8 +: 8]; + 4'd12 : tdata <= mac_dlen_r[15:8]; + 4'd13 : tdata <= mac_dlen_r[7:0]; + 4'd14 : tdata <= 8'h0;//MAC First Data + default : tdata <= tdata + 1'b1; + endcase + else if((cur_state == PAT_GEN) && (tready == 1'b1)) + tdata <= tdata + 1'b1; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + tlast <= 1'b0; + else if((tready == 1'b1) && (cur_state == PAT_GEN) && (pat_cnt == mac_dlen_r+16'd13)) + tlast <= 1'b1; + else if(tready == 1'b1) + tlast <= 1'b0; +end + +endmodule diff --git a/fpga/ip/gTSE/T120F324_devkit/mac_rx2tx.v b/fpga/ip/gTSE/T120F324_devkit/mac_rx2tx.v new file mode 100644 index 0000000..14508a7 --- /dev/null +++ b/fpga/ip/gTSE/T120F324_devkit/mac_rx2tx.v @@ -0,0 +1,139 @@ +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / +// / / .' / +// __/ /.' / +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* +`timescale 1 ns / 1 ns +module mac_rx2tx +( +//Globle Signals +// +//Receive AXI4-Stream Interface +input rx_axis_clk, +input rx_axis_rstn, +input [7:0] rx_axis_mac_tdata, +input rx_axis_mac_tvalid, +input rx_axis_mac_tlast, +input rx_axis_mac_tuser, +output reg rx_axis_mac_tready, +//Transmit AXI4-Stream Interface +input tx_axis_clk, +input tx_axis_rstn, +output reg [7:0] tx_axis_mac_tdata, +output reg tx_axis_mac_tvalid, +output reg tx_axis_mac_tlast, +output reg tx_axis_mac_tuser, +input tx_axis_mac_tready +); +// Parameter Define + +// Register Define + +// Wire Define +wire [9:0] u1_data; +wire u1_wrreq; +wire u1_rdreq; +wire [9:0] u1_q; +wire u1_empty; +wire u1_almfull; +wire [10:0] u1_wrcnt; + +/*----------------------------------------------------------------------------------*\ + The main code +\*----------------------------------------------------------------------------------*/ + +/*----------------------- Rx Clock Region ----------------------------*/ +assign u1_almfull = (u1_wrcnt >= 2045); + +always @(posedge rx_axis_clk or negedge rx_axis_rstn) +begin + if(rx_axis_rstn == 1'b0) + rx_axis_mac_tready <= 1'b0; + else if(u1_almfull == 1'b1) + rx_axis_mac_tready <= 1'b0; + else + rx_axis_mac_tready <= 1'b1; +end + +/*----------------------- Fifo 1 Region ----------------------------*/ +DC_FIFO #( + .FIFO_MODE ("ShowAhead" ), + .DATA_WIDTH (10 ), + .FIFO_DEPTH (2048 ) +) +u1 +( + //System Signal + .Reset (!rx_axis_rstn ), + //Write Signal + .WrClk (rx_axis_clk ), + .WrEn (u1_wrreq ), + .WrDNum (u1_wrcnt ), + .WrFull ( ), + .WrData (u1_data ), + //Read Signal + .RdClk (tx_axis_clk ), + .RdEn (u1_rdreq ), + .RdDNum ( ), + .RdEmpty (u1_empty ), + .RdData (u1_q ) +); + +assign u1_data = {rx_axis_mac_tuser,rx_axis_mac_tlast,rx_axis_mac_tdata}; +assign u1_wrreq = (rx_axis_mac_tvalid == 1'b1) && (rx_axis_mac_tready == 1'b1); +assign u1_rdreq = (u1_empty == 1'b0) && ((tx_axis_mac_tvalid == 1'b0) || (tx_axis_mac_tready == 1'b1)); + +/*----------------------- Tx Clock Region ----------------------------*/ + +always @(posedge tx_axis_clk or negedge tx_axis_rstn) +begin + if(tx_axis_rstn == 1'b0) + tx_axis_mac_tvalid <= 1'b0; + else if(u1_rdreq == 1'b1) + tx_axis_mac_tvalid <= 1'b1; + else if(tx_axis_mac_tready == 1'b1) + tx_axis_mac_tvalid <= 1'b0; +end + +always @(posedge tx_axis_clk or negedge tx_axis_rstn) +begin + if(tx_axis_rstn == 1'b0) + tx_axis_mac_tdata <= 8'h0; + else if(u1_rdreq == 1'b1) + tx_axis_mac_tdata <= u1_q[7:0]; + else if(tx_axis_mac_tready == 1'b1) + tx_axis_mac_tdata <= 8'h0; +end + +always @(posedge tx_axis_clk or negedge tx_axis_rstn) +begin + if(tx_axis_rstn == 1'b0) + tx_axis_mac_tlast <= 1'b0; + else if(u1_rdreq == 1'b1) + tx_axis_mac_tlast <= u1_q[8]; + else if(tx_axis_mac_tready == 1'b1) + tx_axis_mac_tlast <= 1'b0; +end + +always @(posedge tx_axis_clk or negedge tx_axis_rstn) +begin + if(tx_axis_rstn == 1'b0) + tx_axis_mac_tuser <= 1'b0; + else if((u1_rdreq == 1'b1) && (u1_q[8] == 1'b1)) + tx_axis_mac_tuser <= u1_q[9]; + else if(tx_axis_mac_tready == 1'b1) + tx_axis_mac_tuser <= 1'b0; +end + +endmodule diff --git a/fpga/ip/gTSE/T120F324_devkit/reg_apb3.v b/fpga/ip/gTSE/T120F324_devkit/reg_apb3.v new file mode 100644 index 0000000..3447897 --- /dev/null +++ b/fpga/ip/gTSE/T120F324_devkit/reg_apb3.v @@ -0,0 +1,333 @@ +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / +// / / .' / +// __/ /.' / +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* +`timescale 1 ns / 1 ns +module reg_apb3#( + parameter ADDR_WTH = 10 +) +( +//Globle Signals +// +//APB3 Slave Interface +input s_apb3_clk, +input s_apb3_rstn, +input [ADDR_WTH-1:0] s_apb3_paddr, +input s_apb3_psel, +input s_apb3_penable, +output reg s_apb3_pready, +input s_apb3_pwrite,//0:rd; 1:wr; +input [31:0] s_apb3_pwdata, +output reg [31:0] s_apb3_prdata, +output wire s_apb3_pslverror, +//Cfg Space Registers +//--Example Registers Field +output reg mac_sw_rst, +output reg axi4_st_mux_select, +output reg pat_mux_select, +output reg udp_pat_gen_en, +output reg mac_pat_gen_en, +output reg [15:0] pat_gen_num, +output reg [15:0] pat_gen_ipg, +output reg [47:0] pat_dst_mac, +output reg [47:0] pat_src_mac, +output reg [15:0] pat_mac_dlen, +output reg [31:0] pat_src_ip, +output reg [31:0] pat_dst_ip, +output reg [15:0] pat_src_port, +output reg [15:0] pat_dst_port, +output reg [15:0] pat_udp_dlen, +output reg [1:0] clkmux_sel +); +// Parameter Define + +// Register Define +reg [ADDR_WTH-3:0] loc_addr; +reg loc_wr_vld; +reg loc_rd_vld; + +// Wire Define + +/*----------------------------------------------------------------------------------*\ + The main code +\*----------------------------------------------------------------------------------*/ +//apb3 interface +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + loc_addr <= {ADDR_WTH-2{1'b0}}; + else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0)) + loc_addr <= s_apb3_paddr[2+:ADDR_WTH-2]; +end + +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + loc_wr_vld <= 1'b0; + else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) + loc_wr_vld <= 1'b1; + else + loc_wr_vld <= 1'b0; +end + +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + loc_rd_vld <= 1'b0; + else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b0)) + loc_rd_vld <= 1'b1; + else + loc_rd_vld <= 1'b0; +end + +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + s_apb3_pready <= 1'b0; + else if((loc_wr_vld == 1'b1) || (loc_rd_vld == 1'b1)) + s_apb3_pready <= 1'b1; + else + s_apb3_pready <= 1'b0; +end + +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + s_apb3_prdata <= 32'h0; + else if(loc_rd_vld == 1'b1) + begin + case(loc_addr) + //Example Registers Field + 'h080 : s_apb3_prdata <= {31'h0,mac_sw_rst}; + 'h081 : s_apb3_prdata <= {30'h0,pat_mux_select,axi4_st_mux_select}; + 'h082 : s_apb3_prdata <= {30'h0,mac_pat_gen_en,udp_pat_gen_en}; + 'h083 : s_apb3_prdata <= {pat_gen_ipg,pat_gen_num}; + 'h084 : s_apb3_prdata <= pat_dst_mac[31:0]; + 'h085 : s_apb3_prdata <= {16'h0,pat_dst_mac[47:32]}; + 'h086 : s_apb3_prdata <= pat_src_mac[31:0]; + 'h087 : s_apb3_prdata <= {16'h0,pat_src_mac[47:32]}; + 'h088 : s_apb3_prdata <= {16'h0,pat_mac_dlen}; + 'h089 : s_apb3_prdata <= pat_src_ip; + 'h08a : s_apb3_prdata <= pat_dst_ip; + 'h08b : s_apb3_prdata <= {pat_dst_port,pat_src_port}; + 'h08c : s_apb3_prdata <= {16'h0,pat_udp_dlen}; + 'h08d : s_apb3_prdata <= {30'h0,clkmux_sel}; + endcase + end +end + +assign s_apb3_pslverror = 1'b0; + +/*----------------------------------------------------------------------------------*\ + Register Space -- Example Registers Field +\*----------------------------------------------------------------------------------*/ +//loc_addr = 0x080; axi_addr = 0x200; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + mac_sw_rst <= 1'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h080)) + begin + mac_sw_rst <= s_apb3_pwdata[0]; + end +end + +//loc_addr = 0x081; axi_addr = 0x204; RW; +//[axi4_st_mux_select] 0:pat tx mode; 1:rx2tx loopback mode; +//[pat_mux_select] 0:udp pat; 1:mac pat; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + axi4_st_mux_select <= 1'h0; + pat_mux_select <= 1'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h081)) + begin + axi4_st_mux_select <= s_apb3_pwdata[0]; + pat_mux_select <= s_apb3_pwdata[1]; + end +end + +//loc_addr = 0x082; axi_addr = 0x208; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + udp_pat_gen_en <= 1'h0; + mac_pat_gen_en <= 1'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h082)) + begin + udp_pat_gen_en <= s_apb3_pwdata[0]; + mac_pat_gen_en <= s_apb3_pwdata[1]; + end +end + +//loc_addr = 0x083; axi_addr = 0x20c; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + pat_gen_num <= 16'h0; + pat_gen_ipg <= 16'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h083)) + begin + pat_gen_num <= s_apb3_pwdata[15:0]; + pat_gen_ipg <= s_apb3_pwdata[31:16]; + end +end + +//loc_addr = 0x084; axi_addr = 0x210; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + pat_dst_mac[31:0] <= 32'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h084)) + begin + pat_dst_mac[31:0] <= s_apb3_pwdata[31:0]; + end +end + +//loc_addr = 0x085; axi_addr = 0x214; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + pat_dst_mac[47:32] <= 16'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h085)) + begin + pat_dst_mac[47:32] <= s_apb3_pwdata[15:0]; + end +end + +//loc_addr = 0x086; axi_addr = 0x218; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + pat_src_mac[31:0] <= 32'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h086)) + begin + pat_src_mac[31:0] <= s_apb3_pwdata[31:0]; + end +end + +//loc_addr = 0x087; axi_addr = 0x21c; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + pat_src_mac[47:32] <= 16'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h087)) + begin + pat_src_mac[47:32] <= s_apb3_pwdata[15:0]; + end +end + +//loc_addr = 0x088; axi_addr = 0x220; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + pat_mac_dlen <= 16'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h088)) + begin + pat_mac_dlen <= s_apb3_pwdata[15:0]; + end +end + +//loc_addr = 0x089; axi_addr = 0x224; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + pat_src_ip <= 32'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h089)) + begin + pat_src_ip <= s_apb3_pwdata[31:0]; + end +end + +//loc_addr = 0x08a; axi_addr = 0x228; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + pat_dst_ip <= 32'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08a)) + begin + pat_dst_ip <= s_apb3_pwdata[31:0]; + end +end + +//loc_addr = 0x08b; axi_addr = 0x22c; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + pat_src_port <= 16'h0; + pat_dst_port <= 16'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08b)) + begin + pat_src_port <= s_apb3_pwdata[15:0]; + pat_dst_port <= s_apb3_pwdata[31:16]; + end +end + +//loc_addr = 0x08c; axi_addr = 0x230; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + pat_udp_dlen <= 16'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08c)) + begin + pat_udp_dlen <= s_apb3_pwdata[15:0]; + end +end + +//loc_addr = 0x08d; axi_addr = 0x234; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + clkmux_sel <= 2'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08d)) + begin + clkmux_sel <= s_apb3_pwdata[1:0]; + end +end + + +/*----------------------------------------------------------------------------------*\ + Register Space -- The End +\*----------------------------------------------------------------------------------*/ + +endmodule diff --git a/fpga/ip/gTSE/T120F324_devkit/rgmii_2_rmii.v b/fpga/ip/gTSE/T120F324_devkit/rgmii_2_rmii.v new file mode 100644 index 0000000..e7a1f19 --- /dev/null +++ b/fpga/ip/gTSE/T120F324_devkit/rgmii_2_rmii.v @@ -0,0 +1,206 @@ +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / +// / / .' / +// __/ /.' / +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`timescale 1 ns / 1 ns +module rgmii_2_rmii ( + input clk_50m, //50Mhz refclock + input rst_n, + //conduit + input [2:0] eth_speed, + //rgmii interface + input [3:0] rgmii_txd, + input rgmii_tx_ctl, + output wire [3:0] rgmii_rxd, + output wire rgmii_rx_ctl, + output reg rgmii_rxc, + //rmii interface + output wire rmii_clk, + output reg [1:0] rmii_txd, + output reg rmii_txen, + input [1:0] rmii_rxd, + input rmii_crsdv +); + +wire [3:0] rxd_c; +wire rx_ctl_c; +reg [3:0] rxd_r; +reg rx_ctl_r; +reg rmii_crsdv_r, shift_en; +reg [4:0] txd_cnt, rxd_cnt; +reg [3:0] rxd_shiftreg; +reg [1:0] shift2; +reg [19:0] shift20; +reg [1:0] rx_ctl_p2; +reg [19:0] rx_ctl_p20; + +assign rmii_clk = ~clk_50m; //create 180deg phaseshift + +/*--------------- TX path ---------------------*/ +always @(posedge clk_50m or negedge rst_n) +begin + if (!rst_n) begin + txd_cnt <= 5'd0; + end + else if (rgmii_tx_ctl) begin + if (((eth_speed == 3'h2) && txd_cnt == 5'd1) || + ((eth_speed == 3'h1) && txd_cnt == 5'd19)) begin + txd_cnt <= 5'd0; + end + else begin + txd_cnt <= txd_cnt + 5'd1; + end + end +end + +always @(posedge clk_50m or negedge rst_n) +begin + if (!rst_n) begin + rmii_txen <= 1'b0; + end + else begin + rmii_txen <= rgmii_tx_ctl; + end +end + +always @(posedge clk_50m or negedge rst_n) +begin + if (!rst_n) begin + rmii_txd <= 2'b00; + end + else begin + if ((eth_speed == 3'h2) && txd_cnt == 5'd0) begin + rmii_txd <= rgmii_txd[1:0]; + end + else if ((eth_speed == 3'h2) && txd_cnt == 5'd1) begin + rmii_txd <= rgmii_txd[3:2]; + end + + if ((eth_speed == 3'h1) && txd_cnt == 5'd0) begin + rmii_txd <= rgmii_txd[1:0]; + end + else if ((eth_speed == 3'h1) && txd_cnt == 5'd10) begin + rmii_txd <= rgmii_txd[3:2]; + end + end +end +/*------------------ end of TX path ------------------------*/ + +/*------------ RX path ------------------*/ +always @(posedge clk_50m or negedge rst_n) +begin + if (!rst_n) begin + rxd_cnt <= 5'd0; + end + else if (rmii_crsdv) begin + if (((eth_speed == 3'h2) && rxd_cnt == 5'd1) || ((eth_speed == 3'h1) && rxd_cnt == 5'd19)) begin + rxd_cnt <= 5'd0; + end + else begin + rxd_cnt <= rxd_cnt + 5'd1; + end + end +end + +always @(posedge clk_50m or negedge rst_n) +begin + if (!rst_n) begin + rxd_shiftreg <= 4'd0; + end + else if (rmii_crsdv) begin + if (eth_speed == 3'h2 || ((eth_speed == 3'h1) && (rxd_cnt == 5'd0 || rxd_cnt == 5'd10))) begin + rxd_shiftreg <= {rmii_rxd, rxd_shiftreg[3:2]}; + end + end +end + +always @(posedge clk_50m or negedge rst_n) +begin + if (!rst_n) begin + shift2 <= 2'b1; + shift20 <= 20'b1; + end + else begin + shift2 <= {shift2[0],shift2[1]}; + shift20 <= {shift20[18:0],shift20[19]}; + end +end + +always @(posedge clk_50m or negedge rst_n) +begin + if (!rst_n) begin + rgmii_rxc <= 1'b0; + end + else begin + if ((eth_speed == 3'h2 && shift2[1]) || (eth_speed == 3'h1 && (shift20[10]))) begin + rgmii_rxc <= 1'b1; + end + else if ((eth_speed == 3'h2 && shift2[0]) || (eth_speed == 3'h1 && (shift20[0]))) begin + rgmii_rxc <= 1'b0; + end + end +end + +always @(posedge clk_50m or negedge rst_n) +begin + if (!rst_n) begin + rx_ctl_p2 <= 2'd0; + rx_ctl_p20 <= 20'd0; + end + else begin + rx_ctl_p2 <= {rmii_crsdv , rx_ctl_p2[1]}; + rx_ctl_p20 <= {rmii_crsdv, rx_ctl_p20[19:1]}; + end +end + +/*---- shift rxd & rx_ctl so that they are not edge align with rgmii_rxc ----*/ +assign rxd_c = (rxd_cnt == 5'd0) ? rxd_shiftreg : rxd_r; +assign rx_ctl_c = (eth_speed == 3'h2) ? rx_ctl_p2[0] : rx_ctl_p20[0]; + +always @(posedge clk_50m or negedge rst_n) +begin + if (!rst_n) begin + rxd_r <= 4'd0; + rx_ctl_r <= 1'd0; + rmii_crsdv_r <= 1'd0; + end + else begin + rxd_r <= rxd_c; + rx_ctl_r <= rx_ctl_c; + rmii_crsdv_r <= rmii_crsdv; + end +end + +always @(posedge clk_50m or negedge rst_n) +begin + if (!rst_n) begin + shift_en <= 1'd0; + end // to detect if rmii_crsdv assert at the posedge of rgmii_rxc, delay rgmii_rxd & rgmii_rx_ctl if they are aligned with rgmii_rxc + else if (rmii_crsdv && ~rmii_crsdv_r) begin + if (((eth_speed == 3'h2) && shift2[0]) || ((eth_speed == 3'h1) && shift20[11])) begin + shift_en <= 1'd1; + end + else begin + shift_en <= 1'd0; + end + end +end + +assign rgmii_rxd = shift_en ? rxd_r : rxd_c; +assign rgmii_rx_ctl = shift_en ? rx_ctl_r : rx_ctl_c; +/*--------------------------------------------------------*/ +/*------------------ end of RX path ------------------------*/ +endmodule \ No newline at end of file diff --git a/fpga/ip/gTSE/T120F324_devkit/temac_ex.peri.xml b/fpga/ip/gTSE/T120F324_devkit/temac_ex.peri.xml new file mode 100644 index 0000000..bbc0cdc --- /dev/null +++ b/fpga/ip/gTSE/T120F324_devkit/temac_ex.peri.xml @@ -0,0 +1,131 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/ip/gTSE/T120F324_devkit/temac_ex.v b/fpga/ip/gTSE/T120F324_devkit/temac_ex.v new file mode 100644 index 0000000..15d4a24 --- /dev/null +++ b/fpga/ip/gTSE/T120F324_devkit/temac_ex.v @@ -0,0 +1,563 @@ +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / +// / / .' / +// __/ /.' / +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* +`timescale 1 ns / 1 ns +//`include "header.v" // use JTAG hard block +module temac_ex +( +//Globle Signals +//----pll_0 +input clk, +input clk_125m, +input pll_0_locked, +input sw6, +output wire pll_rstn, + +//TEMAC PHY RGMII Interface +output wire [3:0] rgmii_txd_HI, +output wire [3:0] rgmii_txd_LO, +output wire rgmii_txc_HI, +output wire rgmii_txc_LO, +input [3:0] rgmii_rxd_HI, +input [3:0] rgmii_rxd_LO, +`ifdef TITANIUM + output wire rgmii_tx_ctl_HI, + output wire rgmii_tx_ctl_LO, + input rgmii_rx_ctl_HI, + input rgmii_rx_ctl_LO, + input mux_clk, + output [1:0] mux_clk_sw, +`else + input rgmii_rxc, + output wire rgmii_tx_ctl, + input rgmii_rx_ctl, +`endif +//TEMAC PHY Ctr Interface +output wire phy_rstn, +//hardware Jtag Interface +`ifndef SIM_MODE +`ifndef SOFT_TAP +input jtag_inst1_TCK, +input jtag_inst1_TDI, +output wire jtag_inst1_TDO, +input jtag_inst1_SEL, +input jtag_inst1_CAPTURE, +input jtag_inst1_SHIFT, +input jtag_inst1_UPDATE, +input jtag_inst1_RESET, +`else +//software Jtag Interface +input io_jtag_tms, +input io_jtag_tdi, +output wire io_jtag_tdo, +input io_jtag_tck, +`endif + +//Debug Signals +//output wire [1:0] debug_led +output wire system_uart_0_io_txd, +input system_uart_0_io_rxd, +`endif + +output system_spi_0_io_sclk_write, +output system_spi_0_io_data_0_writeEnable, +input system_spi_0_io_data_0_read, +output system_spi_0_io_data_0_write, +output system_spi_0_io_data_1_writeEnable, +input system_spi_0_io_data_1_read, +output system_spi_0_io_data_1_write, +output system_spi_0_io_ss, + +//TEMAC PHY MDIO Interface +input phy_mdi, +output wire phy_mdo, +output wire phy_mdo_en, +output wire phy_mdc +); +// Parameter Define +`include "gTSE_define.svh" + +// Register Define + +// Wire Define +wire clk_50m; +wire clk_50m_rstn; +wire mac_reset; +wire proto_reset; +wire mac_rstn; +//AXI4-Stream Interface +wire rx_axis_clk; +wire [7:0] rx_axis_mac_tdata; +wire rx_axis_mac_tvalid; +wire rx_axis_mac_tlast; +wire rx_axis_mac_tuser; +wire rx_axis_mac_tready; +wire tx_axis_clk; +wire [7:0] tx_axis_mac_tdata; +wire tx_axis_mac_tvalid; +wire tx_axis_mac_tlast; +wire tx_axis_mac_tuser; +wire tx_axis_mac_tready; +wire [7:0] udp_tx_axis_mac_tdata; +wire udp_tx_axis_mac_tvalid; +wire udp_tx_axis_mac_tlast; +wire udp_tx_axis_mac_tready; +wire [7:0] mac_tx_axis_mac_tdata; +wire mac_tx_axis_mac_tvalid; +wire mac_tx_axis_mac_tlast; +wire mac_tx_axis_mac_tready; +wire [7:0] pat_tx_axis_mac_tdata; +wire pat_tx_axis_mac_tvalid; +wire pat_tx_axis_mac_tlast; +wire pat_tx_axis_mac_tuser; +wire pat_tx_axis_mac_tready; +wire [7:0] loop_tx_axis_mac_tdata; +wire loop_tx_axis_mac_tvalid; +wire loop_tx_axis_mac_tlast; +wire loop_tx_axis_mac_tuser; +wire loop_tx_axis_mac_tready; +//RiscV APB3 Interface +wire [15:0] apb3_paddr; +wire apb3_psel; +wire apb3_penable; +wire apb3_pready; +wire apb3_pwrite; +wire [31:0] apb3_pwdata; +wire [31:0] apb3_prdata; +wire apb3_pslverror; +//Mac APB3 Interface +wire [9:0] mac_apb3_paddr; +wire mac_apb3_psel; +wire mac_apb3_penable; +wire mac_apb3_pready; +wire mac_apb3_pwrite; +wire [31:0] mac_apb3_pwdata; +wire [31:0] mac_apb3_prdata; +wire mac_apb3_pslverror; +//Ex APB3 Interface +wire [9:0] ex_apb3_paddr; +wire ex_apb3_psel; +wire ex_apb3_penable; +wire ex_apb3_pready; +wire ex_apb3_pwrite; +wire [31:0] ex_apb3_pwdata; +wire [31:0] ex_apb3_prdata; +wire ex_apb3_pslverror; +//AXI4-Lite Interface +wire [9:0] axi_awaddr; +wire axi_awvalid; +wire axi_awready; +wire [31:0] axi_wdata; +wire axi_wvalid; +wire axi_wready; +wire [1:0] axi_bresp; +wire axi_bvalid; +wire axi_bready; +wire [9:0] axi_araddr; +wire axi_arvalid; +wire axi_arready; +wire [1:0] axi_rresp; +wire [31:0] axi_rdata; +wire axi_rvalid; +wire axi_rready; +//Cfg Space Registers +wire mac_sw_rst; +wire axi4_st_mux_select; +wire pat_mux_select; +wire udp_pat_gen_en; +wire mac_pat_gen_en; +wire [15:0] pat_gen_num; +wire [15:0] pat_gen_ipg; +wire [47:0] pat_dst_mac; +wire [47:0] pat_src_mac; +wire [15:0] pat_mac_dlen; +wire [31:0] pat_src_ip; +wire [31:0] pat_dst_ip; +wire [15:0] pat_src_port; +wire [15:0] pat_dst_port; +wire [15:0] pat_udp_dlen; + +//TSE DDIO +`ifdef TITANIUM + wire rgmii_rxc; + + assign rgmii_rxc = mux_clk; +`else + wire rgmii_rx_ctl_LO; + wire rgmii_rx_ctl_HI; + wire rgmii_tx_ctl_LO; + wire rgmii_tx_ctl_HI; + + assign rgmii_tx_ctl = rgmii_tx_ctl_HI | rgmii_tx_ctl_LO ; + assign rgmii_rx_ctl_HI = rgmii_rx_ctl ; + assign rgmii_rx_ctl_LO = rgmii_rx_ctl ; +`endif +/*----------------------------------------------------------------------------------*\ + The main code +\*----------------------------------------------------------------------------------*/ +assign pll_rstn = 1; +/*----------------------- Clock Region -----------------------*/ +//In full throughput usecase, rx_axis_clk and tx_axis_clk should be set to 125Mhz or above. +//In this example design, these clocks are set to 50Mhz because the UDP/MAC pattern generator has +//high combi logic and couldn't meet timing at 125Mhz. +assign rx_axis_clk = clk;//clk_125m; +assign tx_axis_clk = clk;//clk_125m; + + +/*----------------------- Reset Region -----------------------*/ +//assign pll_0_reset = 1'b0; +assign clk_50m = clk; +assign phy_rstn = sw6; +assign clk_50m_rstn = pll_0_locked; +assign mac_reset = ~pll_0_locked; +assign proto_reset = mac_sw_rst; +assign mac_rstn = ~(mac_reset || proto_reset); + +/*----------------------- MCU Module ----------------------------*/ +`ifndef SIM_MODE +sapphire u_mcu +( +//user custom ports + //SOC + .io_systemClk (clk_50m ), + .io_asyncReset (1'b0 ), + .system_uart_0_io_txd (system_uart_0_io_txd ), + .system_uart_0_io_rxd (system_uart_0_io_rxd ), + .system_spi_0_io_sclk_write (system_spi_0_io_sclk_write ), + .system_spi_0_io_data_0_writeEnable (system_spi_0_io_data_0_writeEnable ), + .system_spi_0_io_data_0_read (system_spi_0_io_data_0_read ), + .system_spi_0_io_data_0_write (system_spi_0_io_data_0_write ), + .system_spi_0_io_data_1_writeEnable (system_spi_0_io_data_1_writeEnable ), + .system_spi_0_io_data_1_read (system_spi_0_io_data_1_read ), + .system_spi_0_io_data_1_write (system_spi_0_io_data_1_write ), + .system_spi_0_io_ss (system_spi_0_io_ss ), + .jtagCtrl_tck (jtag_inst1_TCK ), + .jtagCtrl_tdi (jtag_inst1_TDI ), + .jtagCtrl_tdo (jtag_inst1_TDO ), + .jtagCtrl_enable (jtag_inst1_SEL ), + .jtagCtrl_capture (jtag_inst1_CAPTURE ), + .jtagCtrl_shift (jtag_inst1_SHIFT ), + .jtagCtrl_update (jtag_inst1_UPDATE ), + .jtagCtrl_reset (jtag_inst1_RESET ), +//APB3 Master Interface + .io_apbSlave_0_PADDR (apb3_paddr ), + .io_apbSlave_0_PSEL (apb3_psel ), + .io_apbSlave_0_PENABLE (apb3_penable ), + .io_apbSlave_0_PREADY (apb3_pready ), + .io_apbSlave_0_PWRITE (apb3_pwrite ), + .io_apbSlave_0_PWDATA (apb3_pwdata ), + .io_apbSlave_0_PRDATA (apb3_prdata ), + .io_apbSlave_0_PSLVERROR (apb3_pslverror ) +); +`endif + +assign apb3_pready = (apb3_paddr[9] == 1'b0) ? mac_apb3_pready : ex_apb3_pready; +assign apb3_prdata = (apb3_paddr[9] == 1'b0) ? mac_apb3_prdata : ex_apb3_prdata; +assign apb3_pslverror = (apb3_paddr[9] == 1'b0) ? mac_apb3_pslverror : ex_apb3_pslverror; + +assign mac_apb3_paddr = apb3_paddr[9:0]; +assign mac_apb3_psel = (apb3_paddr[9] == 1'b0) ? apb3_psel : 1'b0; +assign mac_apb3_penable = apb3_penable; +assign mac_apb3_pwrite = apb3_pwrite; +assign mac_apb3_pwdata = apb3_pwdata; + +assign ex_apb3_paddr = apb3_paddr[9:0]; +assign ex_apb3_psel = (apb3_paddr[9] == 1'b1) ? apb3_psel : 1'b0; +assign ex_apb3_penable = apb3_penable; +assign ex_apb3_pwrite = apb3_pwrite; +assign ex_apb3_pwdata = apb3_pwdata; + +apb3_2_axi4_lite#( + .ADDR_WTH (10 ) +) +u_apb3_2_axi4_lite +( +//Globle Signals + .clk (clk_50m ), + .rstn (clk_50m_rstn ), +//APB3 Slave Interface + .s_apb3_paddr (mac_apb3_paddr ), + .s_apb3_psel (mac_apb3_psel ), + .s_apb3_penable (mac_apb3_penable ), + .s_apb3_pready (mac_apb3_pready ), + .s_apb3_pwrite (mac_apb3_pwrite ), + .s_apb3_pwdata (mac_apb3_pwdata ), + .s_apb3_prdata (mac_apb3_prdata ), + .s_apb3_pslverror (mac_apb3_pslverror ), +//AXI4-Lite Master Interface + .m_axi_awaddr (axi_awaddr ), + .m_axi_awvalid (axi_awvalid ), + .m_axi_awready (axi_awready ), + .m_axi_wdata (axi_wdata ), + .m_axi_wvalid (axi_wvalid ), + .m_axi_wready (axi_wready ), + .m_axi_bresp (axi_bresp ), + .m_axi_bvalid (axi_bvalid ), + .m_axi_bready (axi_bready ), + .m_axi_araddr (axi_araddr ), + .m_axi_arvalid (axi_arvalid ), + .m_axi_arready (axi_arready ), + .m_axi_rresp (axi_rresp ), + .m_axi_rdata (axi_rdata ), + .m_axi_rvalid (axi_rvalid ), + .m_axi_rready (axi_rready ) +); + +reg_apb3#( + .ADDR_WTH (10 ) +) +u_reg_apb3 +( +//Globle Signals +// +//APB3 Slave Interface + .s_apb3_clk (clk_50m ), + .s_apb3_rstn (clk_50m_rstn ), + .s_apb3_paddr (ex_apb3_paddr ), + .s_apb3_psel (ex_apb3_psel ), + .s_apb3_penable (ex_apb3_penable ), + .s_apb3_pready (ex_apb3_pready ), + .s_apb3_pwrite (ex_apb3_pwrite ), + .s_apb3_pwdata (ex_apb3_pwdata ), + .s_apb3_prdata (ex_apb3_prdata ), + .s_apb3_pslverror (ex_apb3_pslverror ), +//Cfg Space Registers +//--Example Registers Field + .mac_sw_rst (mac_sw_rst ), + .axi4_st_mux_select (axi4_st_mux_select ), + .pat_mux_select (pat_mux_select ), + .udp_pat_gen_en (udp_pat_gen_en ), + .mac_pat_gen_en (mac_pat_gen_en ), + .pat_gen_num (pat_gen_num ), + .pat_gen_ipg (pat_gen_ipg ), + .pat_dst_mac (pat_dst_mac ), + .pat_src_mac (pat_src_mac ), + .pat_mac_dlen (pat_mac_dlen ), + .pat_src_ip (pat_src_ip ), + .pat_dst_ip (pat_dst_ip ), + .pat_src_port (pat_src_port ), + .pat_dst_port (pat_dst_port ), + .pat_udp_dlen (pat_udp_dlen ), + .clkmux_sel (mux_clk_sw ) +); + +//generate if (PATTERN_TYPE == 0) begin //UDP +// +//assign mac_tx_axis_mac_tdata = 8'h0; +//assign mac_tx_axis_mac_tvalid = 1'b0; +//assign mac_tx_axis_mac_tlast = 1'b0; + +/*----------------------- The Ethernet Pattern Module -----------------------*/ +udp_pat_gen u_udp_pat_gen +( +//Globle Signals + .clk (tx_axis_clk ), + .rstn (mac_rstn ), +//Control Interface + .pat_gen_en (udp_pat_gen_en ), + .pat_gen_num (pat_gen_num ), + .pat_gen_ipg (pat_gen_ipg ), +//MAC Protocol Signals + .dst_mac (pat_dst_mac ), + .src_mac (pat_src_mac ), +//IP Protocol Signals + .src_ip (pat_src_ip ), + .dst_ip (pat_dst_ip ), +//UDP Protocol Signals + .src_port (pat_src_port ), + .dst_port (pat_dst_port ), + .udp_dlen (pat_udp_dlen ), +//AXI4-Stream Interface + .rclk (rx_axis_clk ), + .rrstn (mac_rstn ), + .rdata (rx_axis_mac_tdata ), + .rvalid (rx_axis_mac_tvalid ), + .rlast (rx_axis_mac_tlast ), + .tdata (udp_tx_axis_mac_tdata ), + .tvalid (udp_tx_axis_mac_tvalid ), + .tlast (udp_tx_axis_mac_tlast ), + .tready (udp_tx_axis_mac_tready ) +); +//end +//else begin //MAC +// +//assign udp_tx_axis_mac_tdata = 8'h0; +//assign udp_tx_axis_mac_tvalid = 1'b0; +//assign udp_tx_axis_mac_tlast = 1'b0; + +mac_pat_gen u_mac_pat_gen +( +//Globle Signals + .clk (tx_axis_clk ), + .rstn (mac_rstn ), +//Control Interface + .pat_gen_en (mac_pat_gen_en ), + .pat_gen_num (pat_gen_num ), + .pat_gen_ipg (pat_gen_ipg ), +//MAC Protocol Signals + .dst_mac (pat_dst_mac ), + .src_mac (pat_src_mac ), + .mac_dlen (pat_mac_dlen ), +//AXI4-Stream Interface + .rclk (rx_axis_clk ), + .rrstn (mac_rstn ), + .rdata (rx_axis_mac_tdata ), + .rvalid (rx_axis_mac_tvalid ), + .rlast (rx_axis_mac_tlast ), + .tdata (mac_tx_axis_mac_tdata ), + .tvalid (mac_tx_axis_mac_tvalid ), + .tlast (mac_tx_axis_mac_tlast ), + .tready (mac_tx_axis_mac_tready ) +); +//end +//endgenerate + +axi4_st_mux u_pat_mux +( +//Globle Signals + .mux_select (pat_mux_select ),//0:udp pat; 1:mac pat; +//Mux In 0 Interface + .tdata0 (udp_tx_axis_mac_tdata ), + .tvalid0 (udp_tx_axis_mac_tvalid ), + .tlast0 (udp_tx_axis_mac_tlast ), + .tuser0 (1'b0 ), + .tready0 (udp_tx_axis_mac_tready ), +//Mux In 1 Interface + .tdata1 (mac_tx_axis_mac_tdata ), + .tvalid1 (mac_tx_axis_mac_tvalid ), + .tlast1 (mac_tx_axis_mac_tlast ), + .tuser1 (1'b0 ), + .tready1 (mac_tx_axis_mac_tready ), +//Mux Out Interface + .tdata (pat_tx_axis_mac_tdata ), + .tvalid (pat_tx_axis_mac_tvalid ), + .tlast (pat_tx_axis_mac_tlast ), + .tuser (pat_tx_axis_mac_tuser ), + .tready (pat_tx_axis_mac_tready ) +); + +/*----------------------- The Tx AXI4 St Mux Module -----------------------*/ +axi4_st_mux u_tx_axi4st_mux +( +//Globle Signals + .mux_select (axi4_st_mux_select ),//0:pat; 1:rx2tx loopback; +//Mux In 0 Interface + .tdata0 (pat_tx_axis_mac_tdata ), + .tvalid0 (pat_tx_axis_mac_tvalid ), + .tlast0 (pat_tx_axis_mac_tlast ), + .tuser0 (pat_tx_axis_mac_tuser ), + .tready0 (pat_tx_axis_mac_tready ), +//Mux In 1 Interface + .tdata1 (loop_tx_axis_mac_tdata ), + .tvalid1 (loop_tx_axis_mac_tvalid ), + .tlast1 (loop_tx_axis_mac_tlast ), + .tuser1 (loop_tx_axis_mac_tuser ), + .tready1 (loop_tx_axis_mac_tready ), +//Mux Out Interface + .tdata (tx_axis_mac_tdata ), + .tvalid (tx_axis_mac_tvalid ), + .tlast (tx_axis_mac_tlast ), + .tuser (tx_axis_mac_tuser ), + .tready (tx_axis_mac_tready ) +); + +/*----------------------- The Tri-mode Ethernet MAC core -----------------------*/ +gTSE u_tsemac +( +//Globle Signals + .mac_reset (mac_reset ), + .proto_reset (proto_reset ), + .tx_mac_aclk (clk_125m ), + .rx_mac_aclk ( ), + .eth_speed ( ), +//Receive AXI4-Stream Interface + .rx_axis_clk (rx_axis_clk ), + .rx_axis_mac_tdata (rx_axis_mac_tdata ), + .rx_axis_mac_tvalid (rx_axis_mac_tvalid ), + .rx_axis_mac_tlast (rx_axis_mac_tlast ), + .rx_axis_mac_tstrb (), + .rx_axis_mac_tuser (rx_axis_mac_tuser ), + .rx_axis_mac_tready (rx_axis_mac_tready ), +//Transmit AXI4-Stream Interface + .tx_axis_clk (tx_axis_clk ), + .tx_axis_mac_tdata (tx_axis_mac_tdata ), + .tx_axis_mac_tvalid (tx_axis_mac_tvalid ), + .tx_axis_mac_tlast (tx_axis_mac_tlast ), + .tx_axis_mac_tstrb (1'b1 ), + .tx_axis_mac_tuser (tx_axis_mac_tuser ), + .tx_axis_mac_tready (tx_axis_mac_tready ), + //--RGMII Interface + .rgmii_txd_HI (rgmii_txd_HI ), + .rgmii_txd_LO (rgmii_txd_LO ), + .rgmii_tx_ctl_HI (rgmii_tx_ctl_HI ), + .rgmii_tx_ctl_LO (rgmii_tx_ctl_LO ), + .rgmii_txc_HI (rgmii_txc_HI ), + .rgmii_txc_LO (rgmii_txc_LO ), + .rgmii_rxd_HI (rgmii_rxd_HI ), + .rgmii_rxd_LO (rgmii_rxd_LO ), + .rgmii_rx_ctl_HI (rgmii_rx_ctl_HI ), + .rgmii_rx_ctl_LO (rgmii_rx_ctl_LO ), + .rgmii_rxc (rgmii_rxc ), + //AXI4-Lite Interface + .s_axi_aclk (clk_50m ), + .s_axi_awaddr (axi_awaddr ), + .s_axi_awvalid (axi_awvalid ), + .s_axi_awready (axi_awready ), + .s_axi_wdata (axi_wdata ), + .s_axi_wvalid (axi_wvalid ), + .s_axi_wready (axi_wready ), + .s_axi_bresp (axi_bresp ), + .s_axi_bvalid (axi_bvalid ), + .s_axi_bready (axi_bready ), + .s_axi_araddr (axi_araddr ), + .s_axi_arvalid (axi_arvalid ), + .s_axi_arready (axi_arready ), + .s_axi_rresp (axi_rresp ), + .s_axi_rdata (axi_rdata ), + .s_axi_rvalid (axi_rvalid ), + .s_axi_rready (axi_rready ), + //MDIO Interface + .Mdo (phy_mdo ), + .MdoEn (phy_mdo_en ), + .Mdi (phy_mdi ), + .Mdc (phy_mdc ) +); + +/*----------------------- User Interface Loopback Module ----------------------------*/ +mac_rx2tx u_mac_rx2tx +( +//Globle Signals +// +//Receive AXI4-Stream Interface + .rx_axis_clk (rx_axis_clk ), + .rx_axis_rstn (mac_rstn ), + .rx_axis_mac_tdata (rx_axis_mac_tdata ), + .rx_axis_mac_tvalid (rx_axis_mac_tvalid ), + .rx_axis_mac_tlast (rx_axis_mac_tlast ), + .rx_axis_mac_tuser (rx_axis_mac_tuser ), + .rx_axis_mac_tready (rx_axis_mac_tready ), +//Transmit AXI4-Stream Interface + .tx_axis_clk (tx_axis_clk ), + .tx_axis_rstn (mac_rstn ), + .tx_axis_mac_tdata (loop_tx_axis_mac_tdata ), + .tx_axis_mac_tvalid (loop_tx_axis_mac_tvalid ), + .tx_axis_mac_tlast (loop_tx_axis_mac_tlast ), + .tx_axis_mac_tuser (loop_tx_axis_mac_tuser ), + .tx_axis_mac_tready (loop_tx_axis_mac_tready ) +); + +endmodule + diff --git a/fpga/ip/gTSE/T120F324_devkit/temac_ex.xml b/fpga/ip/gTSE/T120F324_devkit/temac_ex.xml new file mode 100644 index 0000000..e56c1a9 --- /dev/null +++ b/fpga/ip/gTSE/T120F324_devkit/temac_ex.xml @@ -0,0 +1,92 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/ip/gTSE/T120F324_devkit/timing.sdc b/fpga/ip/gTSE/T120F324_devkit/timing.sdc new file mode 100644 index 0000000..f4e30be --- /dev/null +++ b/fpga/ip/gTSE/T120F324_devkit/timing.sdc @@ -0,0 +1,53 @@ +################################## Clock Constraints ########################## +create_clock -period 20.00 clk +create_clock -period 8.00 clk_125m +create_clock -waveform {2.00 6.00} -period 8.00 clk_125m_90deg +create_clock -period 8.00 rgmii_rxc +create_clock -period 100.00 [get_ports {jtag_inst1_TCK}] + +#################################################################################################################################### +# Timing Mode Constrains +#################################################################################################################################### +set_clock_groups -exclusive -group {clk} -group {clk_125m} -group {clk_125m_90deg} -group {rgmii_rxc} -group {jtag_inst1_TCK} + +# GPIO Constraints +#################### +set_input_delay -clock rgmii_rxc -max 6.168 [get_ports {rgmii_rxd_LO[0] rgmii_rxd_HI[0]}] +set_input_delay -clock rgmii_rxc -min 3.084 [get_ports {rgmii_rxd_LO[0] rgmii_rxd_HI[0]}] +set_input_delay -clock rgmii_rxc -max 6.168 [get_ports {rgmii_rxd_LO[1] rgmii_rxd_HI[1]}] +set_input_delay -clock rgmii_rxc -min 3.084 [get_ports {rgmii_rxd_LO[1] rgmii_rxd_HI[1]}] +set_input_delay -clock rgmii_rxc -max 6.168 [get_ports {rgmii_rxd_LO[2] rgmii_rxd_HI[2]}] +set_input_delay -clock rgmii_rxc -min 3.084 [get_ports {rgmii_rxd_LO[2] rgmii_rxd_HI[2]}] +set_input_delay -clock rgmii_rxc -max 6.168 [get_ports {rgmii_rxd_LO[3] rgmii_rxd_HI[3]}] +set_input_delay -clock rgmii_rxc -min 3.084 [get_ports {rgmii_rxd_LO[3] rgmii_rxd_HI[3]}] +set_output_delay -clock_fall -clock clk_125m_90deg -max -4.700 [get_ports {rgmii_txc_LO rgmii_txc_HI}] +set_output_delay -clock_fall -clock clk_125m_90deg -min -2.571 [get_ports {rgmii_txc_LO rgmii_txc_HI}] +set_output_delay -clock clk_125m -max -4.700 [get_ports {rgmii_txd_LO[0] rgmii_txd_HI[0]}] +set_output_delay -clock clk_125m -min -2.571 [get_ports {rgmii_txd_LO[0] rgmii_txd_HI[0]}] +set_output_delay -clock clk_125m -max -4.700 [get_ports {rgmii_txd_LO[1] rgmii_txd_HI[1]}] +set_output_delay -clock clk_125m -min -2.571 [get_ports {rgmii_txd_LO[1] rgmii_txd_HI[1]}] +set_output_delay -clock clk_125m -max -4.700 [get_ports {rgmii_txd_LO[2] rgmii_txd_HI[2]}] +set_output_delay -clock clk_125m -min -2.571 [get_ports {rgmii_txd_LO[2] rgmii_txd_HI[2]}] +set_output_delay -clock clk_125m -max -4.700 [get_ports {rgmii_txd_LO[3] rgmii_txd_HI[3]}] +set_output_delay -clock clk_125m -min -2.571 [get_ports {rgmii_txd_LO[3] rgmii_txd_HI[3]}] + +# LVDS RX GPIO Constraints +############################ +set_input_delay -clock rgmii_rxc -max 6.100 [get_ports {rgmii_rx_ctl}] +set_input_delay -clock rgmii_rxc -min 3.050 [get_ports {rgmii_rx_ctl}] +set_output_delay -clock clk_125m -max -5.210 [get_ports {rgmii_tx_ctl}] +set_output_delay -clock clk_125m -min -2.480 [get_ports {rgmii_tx_ctl}] + +# LVDS Rx Constraints +#################### + +# JTAG Constraints +#################### +set_output_delay -clock jtag_inst1_TCK -max 0.111 [get_ports {jtag_inst1_TDO}] +set_output_delay -clock jtag_inst1_TCK -min 0.053 [get_ports {jtag_inst1_TDO}] +set_input_delay -clock_fall -clock jtag_inst1_TCK -max 0.267 [get_ports {jtag_inst1_CAPTURE}] +set_input_delay -clock_fall -clock jtag_inst1_TCK -min 0.134 [get_ports {jtag_inst1_CAPTURE}] +set_input_delay -clock_fall -clock jtag_inst1_TCK -max 0.231 [get_ports {jtag_inst1_SEL}] +set_input_delay -clock_fall -clock jtag_inst1_TCK -min 0.116 [get_ports {jtag_inst1_SEL}] +set_input_delay -clock_fall -clock jtag_inst1_TCK -max 0.321 [get_ports {jtag_inst1_SHIFT}] +set_input_delay -clock_fall -clock jtag_inst1_TCK -min 0.161 [get_ports {jtag_inst1_SHIFT}] diff --git a/fpga/ip/gTSE/T120F324_devkit/udp_pat_gen.v b/fpga/ip/gTSE/T120F324_devkit/udp_pat_gen.v new file mode 100644 index 0000000..e5626c3 --- /dev/null +++ b/fpga/ip/gTSE/T120F324_devkit/udp_pat_gen.v @@ -0,0 +1,497 @@ +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / +// / / .' / +// __/ /.' / +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* +`timescale 1 ns / 1 ns +module udp_pat_gen +( +//Globle Signals +input clk, +input rstn, +//Control Interface +input pat_gen_en, +input [15:0] pat_gen_num,//When value is 0, it's infinite mode +input [15:0] pat_gen_ipg, +//MAC Protocol Signals +input [47:0] dst_mac, +input [47:0] src_mac, +//IP Protocol Signals +input [31:0] src_ip, +input [31:0] dst_ip, +//UDP Protocol Signals +input [15:0] udp_dlen, +input [15:0] src_port, +input [15:0] dst_port, +//AXI4-Stream Interface +input rclk, +input rrstn, +input [7:0] rdata, +input rvalid, +input rlast, + +output reg [7:0] tdata, +output reg tvalid, +output reg tlast, +input tready +); + +// Parameter Define +localparam VER = 4'h4;//IPv4 +localparam IHL = 4'h5;//Internet Header Length +localparam TOS = 8'h0;//Type Of Service +localparam FLG = 3'h0;//Flags +localparam TTL = 8'h40;//Time To Live +localparam PTC = 8'h11;//UDP Protocol + +localparam IDLE = 3'h0; +localparam UDP_CHKSUM = 3'h1; +localparam IP_CHKSUM = 3'h2; +localparam PAT_IPG = 3'h3; +localparam PAT_GEN = 3'h4; + +// Register Define +reg [2:0] cur_state; +reg [2:0] next_state; +reg pat_gen_en_dl1; +reg pat_gen_en_dl2; +reg [31:0] src_ip_r; +reg [31:0] dst_ip_r; +reg [15:0] src_port_r; +reg [15:0] dst_port_r; +reg pat_en; +reg infinite_en; +reg [15:0] num_cnt; +reg [15:0] udp_chksum_cnt; +reg [3:0] ip_chksum_cnt; +reg [15:0] ipg_cnt; +reg [15:0] pat_cnt; +reg [15:0] udp_len; +reg [15:0] udp_chksum_num; +reg [7:0] udp_data_h; +reg [7:0] udp_data_l; +reg [16:0] udp_chksum_r; +reg [15:0] udp_chksum; +reg [15:0] ip_len; +reg [15:0] ip_id; +reg [12:0] ip_ofs; +reg [16:0] ip_chksum_r; +reg [15:0] ip_chksum; + +reg [15:0] pat_gen_num_r; +reg [15:0] pat_gen_ipg_r; +reg [47:0] dst_mac_r; +reg [47:0] src_mac_r; +reg [15:0] udp_dlen_r; + +// Wire Define +/*----------------------------------------------------------------------------------*\ + The main code +\*----------------------------------------------------------------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) begin + pat_gen_num_r <= 16'h0; + pat_gen_ipg_r <= 16'h0; + dst_mac_r <= 48'h0; + src_mac_r <= 48'h0; + udp_dlen_r <= 16'h0; + end + else begin + pat_gen_num_r <= pat_gen_num; + pat_gen_ipg_r <= pat_gen_ipg; + dst_mac_r <= dst_mac; + src_mac_r <= src_mac; + udp_dlen_r <= udp_dlen; + end +end + +/*----------------------- FSM Region ----------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + cur_state <= IDLE; + else + cur_state <= next_state; +end + +always @(*) + begin + case(cur_state) + IDLE : + if(pat_en == 1'b1) + next_state = UDP_CHKSUM; + else + next_state = IDLE; + + UDP_CHKSUM : + if(udp_chksum_cnt == udp_chksum_num) + next_state = IP_CHKSUM; + else + next_state = UDP_CHKSUM; + + IP_CHKSUM : + if(ip_chksum_cnt == 4'd9) + next_state = PAT_GEN; + else + next_state = IP_CHKSUM; + + PAT_IPG : + if((pat_en == 1'b1) || ((ipg_cnt == pat_gen_ipg_r) && (infinite_en == 1'b0) && (num_cnt == 16'h0))) + next_state = IDLE; + else if(ipg_cnt == pat_gen_ipg_r) + next_state = IP_CHKSUM; + else + next_state = PAT_IPG; + + PAT_GEN : + if((tlast == 1'b1) && (tready == 1'b1)) + next_state = PAT_IPG; + else + next_state = PAT_GEN; + + default : + next_state = IDLE; + endcase + end + +/*----------------------- Generator Control Region ----------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + begin + pat_gen_en_dl1 <= 1'h0; + pat_gen_en_dl2 <= 1'h0; + end + else + begin + pat_gen_en_dl1 <= pat_gen_en; + pat_gen_en_dl2 <= pat_gen_en_dl1; + end +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + begin + src_ip_r <= 32'h0; + dst_ip_r <= 32'h0; + src_port_r <= 16'h0; + dst_port_r <= 16'h0; + end + else + begin + src_ip_r <= src_ip; + dst_ip_r <= dst_ip; + src_port_r <= src_port; + dst_port_r <= dst_port; + end +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + pat_en <= 1'h0; + else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) + pat_en <= 1'h1; + else if((cur_state == IDLE) && (pat_en == 1'b1)) + pat_en <= 1'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + infinite_en <= 1'h0; + else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1) && (pat_gen_num_r == 16'h0)) + infinite_en <= 1'h1; + else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) + infinite_en <= 1'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + num_cnt <= 16'h0; + else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) + num_cnt <= pat_gen_num_r; + else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1) && (num_cnt != 16'h0)) + num_cnt <= num_cnt - 1'b1; +end + +/*----------------------- UDP Protocol Region ----------------------------*/ + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + udp_len <= 16'h0; + else + udp_len <= udp_dlen_r + 16'd8; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + udp_chksum_num <= 16'h0; + else if(udp_dlen_r[0] == 1'b1) + udp_chksum_num <= udp_dlen_r[15:1] + 16'd10; + else + udp_chksum_num <= udp_dlen_r[15:1] + 16'd9; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + begin + udp_data_h <= 8'h0; + udp_data_l <= 8'h0; + end + else if(cur_state == IDLE) + begin + udp_data_h <= 8'h0; + udp_data_l <= 8'h1; + end + else if((cur_state == UDP_CHKSUM) && (udp_chksum_cnt >= 16'h9)) + begin + udp_data_h <= udp_data_h + 8'h2; + udp_data_l <= udp_data_l + 8'h2; + end +end + +//udp checksum calculate +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + udp_chksum_r <= 17'h0; + else if(cur_state == IDLE) + udp_chksum_r <= 17'h0; + else if(cur_state == UDP_CHKSUM) begin + if (udp_chksum_cnt <= 16'd8) begin + case(udp_chksum_cnt[3:0]) + 4'd0 : udp_chksum_r <= udp_chksum_r[15:0] + src_ip_r[31:16] + udp_chksum_r[16]; + 4'd1 : udp_chksum_r <= udp_chksum_r[15:0] + src_ip_r[15:0] + udp_chksum_r[16]; + 4'd2 : udp_chksum_r <= udp_chksum_r[15:0] + dst_ip_r[31:16] + udp_chksum_r[16]; + 4'd3 : udp_chksum_r <= udp_chksum_r[15:0] + dst_ip_r[15:0] + udp_chksum_r[16]; + 4'd4 : udp_chksum_r <= udp_chksum_r[15:0] + 16'h11 + udp_chksum_r[16]; + 4'd5 : udp_chksum_r <= udp_chksum_r[15:0] + udp_len + udp_chksum_r[16]; + 4'd6 : udp_chksum_r <= udp_chksum_r[15:0] + src_port_r + udp_chksum_r[16]; + 4'd7 : udp_chksum_r <= udp_chksum_r[15:0] + dst_port_r + udp_chksum_r[16]; + 4'd8 : udp_chksum_r <= udp_chksum_r[15:0] + udp_len + udp_chksum_r[16]; + default : udp_chksum_r <= 17'h0; + endcase + end + else begin + if(udp_chksum_cnt == udp_chksum_num) + udp_chksum_r <= udp_chksum_r[15:0] + udp_chksum_r[16]; + else if((udp_chksum_cnt == udp_chksum_num-1) && (udp_dlen_r[0] == 1'b1)) + udp_chksum_r <= udp_chksum_r[15:0] + {udp_data_h,8'h0} + udp_chksum_r[16]; + else + udp_chksum_r <= udp_chksum_r[15:0] + {udp_data_h,udp_data_l} + udp_chksum_r[16]; + end + end +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + udp_chksum <= 16'h0; + else + udp_chksum <= ~udp_chksum_r[15:0]; +end + +/*----------------------- IP Protocol Region ----------------------------*/ +//IP Frame Total Length +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ip_len <= 16'h0; + else + ip_len <= udp_len + 16'd20; +end + +//IP Frame Identification +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ip_id <= 16'h0; + else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1)) + ip_id <= ip_id + 1'b1; +end + +//IP Frame Fragment Offset +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ip_chksum <= 16'h0; + else + ip_chksum <= ~ip_chksum_r[15:0]; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ip_ofs <= 13'h0; +end + +//ip checksum calculate +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ip_chksum_r <= 16'h0; + else if(cur_state == IDLE) + ip_chksum_r <= 16'h0; + else if(cur_state == IP_CHKSUM) begin + case(ip_chksum_cnt) + 4'd0 : ip_chksum_r <= ip_chksum_r[15:0] + {VER,IHL,TOS} + ip_chksum_r[16]; + 4'd1 : ip_chksum_r <= ip_chksum_r[15:0] + ip_len + ip_chksum_r[16]; + 4'd2 : ip_chksum_r <= ip_chksum_r[15:0] + ip_id + ip_chksum_r[16]; + 4'd3 : ip_chksum_r <= ip_chksum_r[15:0] + {FLG,ip_ofs} + ip_chksum_r[16]; + 4'd4 : ip_chksum_r <= ip_chksum_r[15:0] + {TTL,PTC} + ip_chksum_r[16]; + 4'd5 : ip_chksum_r <= ip_chksum_r[15:0] + src_ip_r[31:16] + ip_chksum_r[16]; + 4'd6 : ip_chksum_r <= ip_chksum_r[15:0] + src_ip_r[15:0] + ip_chksum_r[16]; + 4'd7 : ip_chksum_r <= ip_chksum_r[15:0] + dst_ip_r[31:16] + ip_chksum_r[16]; + 4'd8 : ip_chksum_r <= ip_chksum_r[15:0] + dst_ip_r[15:0] + ip_chksum_r[16]; + 4'd9 : ip_chksum_r <= ip_chksum_r[15:0] + ip_chksum_r[16]; + endcase + end + else if(cur_state == PAT_IPG) + ip_chksum_r <= 16'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ip_chksum <= 16'h0; + else + ip_chksum <= ~ip_chksum_r[15:0]; +end + +/*----------------------- Pattern Counter Region ----------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + udp_chksum_cnt <= 16'h0; + else if(cur_state == UDP_CHKSUM) + udp_chksum_cnt <= udp_chksum_cnt + 1'b1; + else + udp_chksum_cnt <= 16'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ip_chksum_cnt <= 4'h0; + else if(cur_state == IP_CHKSUM) + ip_chksum_cnt <= ip_chksum_cnt + 1'b1; + else + ip_chksum_cnt <= 4'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ipg_cnt <= 16'h0; + else if(cur_state == PAT_IPG) + ipg_cnt <= ipg_cnt + 1'b1; + else + ipg_cnt <= 8'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + pat_cnt <= 16'h0; + else if(cur_state != PAT_GEN) + pat_cnt <= 16'h0; + else if(tready == 1'b1) + pat_cnt <= pat_cnt + 1'b1; +end + +/*----------------------- Pattern Generator Region ----------------------------*/ + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + tvalid <= 1'b0; + else if((cur_state == PAT_GEN) && (pat_cnt == 16'h0) && (tready == 1'b1)) + tvalid <= 1'b1; + else if((tready == 1'b1) && (tlast == 1'b1)) + tvalid <= 1'b0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + tdata <= 8'h0; + else if((cur_state == PAT_GEN) && (tready == 1'b1) && (pat_cnt <= 16'd42)) + case(pat_cnt[5:0]) + 6'd0 : tdata <= dst_mac_r[5*8 +: 8]; + 6'd1 : tdata <= dst_mac_r[4*8 +: 8]; + 6'd2 : tdata <= dst_mac_r[3*8 +: 8]; + 6'd3 : tdata <= dst_mac_r[2*8 +: 8]; + 6'd4 : tdata <= dst_mac_r[1*8 +: 8]; + 6'd5 : tdata <= dst_mac_r[0*8 +: 8]; + 6'd6 : tdata <= src_mac_r[5*8 +: 8]; + 6'd7 : tdata <= src_mac_r[4*8 +: 8]; + 6'd8 : tdata <= src_mac_r[3*8 +: 8]; + 6'd9 : tdata <= src_mac_r[2*8 +: 8]; + 6'd10 : tdata <= src_mac_r[1*8 +: 8]; + 6'd11 : tdata <= src_mac_r[0*8 +: 8]; + 6'd12 : tdata <= 8'h08; + 6'd13 : tdata <= 8'h00; + 6'd14 : tdata <= {VER,IHL}; + 6'd15 : tdata <= TOS; + 6'd16 : tdata <= ip_len[15:8]; + 6'd17 : tdata <= ip_len[7:0]; + 6'd18 : tdata <= ip_id[15:8]; + 6'd19 : tdata <= ip_id[7:0]; + 6'd20 : tdata <= {FLG,ip_ofs[12:8]}; + 6'd21 : tdata <= ip_ofs[7:0]; + 6'd22 : tdata <= TTL; + 6'd23 : tdata <= PTC; + 6'd24 : tdata <= ip_chksum[15:8]; + 6'd25 : tdata <= ip_chksum[7:0]; + 6'd26 : tdata <= src_ip_r[3*8 +: 8]; + 6'd27 : tdata <= src_ip_r[2*8 +: 8]; + 6'd28 : tdata <= src_ip_r[1*8 +: 8]; + 6'd29 : tdata <= src_ip_r[0*8 +: 8]; + 6'd30 : tdata <= dst_ip_r[3*8 +: 8]; + 6'd31 : tdata <= dst_ip_r[2*8 +: 8]; + 6'd32 : tdata <= dst_ip_r[1*8 +: 8]; + 6'd33 : tdata <= dst_ip_r[0*8 +: 8]; + 6'd34 : tdata <= src_port_r[15:8]; + 6'd35 : tdata <= src_port_r[7:0]; + 6'd36 : tdata <= dst_port_r[15:8]; + 6'd37 : tdata <= dst_port_r[7:0]; + 6'd38 : tdata <= udp_len[15:8]; + 6'd39 : tdata <= udp_len[7:0]; + 6'd40 : tdata <= udp_chksum[15:8]; + 6'd41 : tdata <= udp_chksum[7:0]; + 6'd42 : tdata <= 8'h0;//UDP First Data + default : tdata <= tdata + 1'b1; + endcase + else if((cur_state == PAT_GEN) && (tready == 1'b1)) + tdata <= tdata + 1'b1; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + tlast <= 1'b0; + else if((tready == 1'b1) && (cur_state == PAT_GEN) && (pat_cnt == ip_len+16'd13)) + tlast <= 1'b1; + else if(tready == 1'b1) + tlast <= 1'b0; +end + +endmodule diff --git a/fpga/ip/gTSE/Testbench/DaulClkFifo.v b/fpga/ip/gTSE/Testbench/DaulClkFifo.v new file mode 100644 index 0000000..7d34961 --- /dev/null +++ b/fpga/ip/gTSE/Testbench/DaulClkFifo.v @@ -0,0 +1,498 @@ + +`timescale 1ns/100ps + +module DC_FIFO +# ( + parameter FIFO_MODE = "Normal" , //"Normal"; //"ShowAhead" + parameter DATA_WIDTH = 8 , + parameter FIFO_DEPTH = 512 , + + parameter AW_C = $clog2(FIFO_DEPTH), + parameter DW_C = DATA_WIDTH , + parameter DD_C = 2**AW_C + ) +( + //System Signal + input Reset , //System Reset + //Write Signal + input WrClk , //(I)Wirte Clock + input WrEn , //(I)Write Enable + output [AW_C-1:0] WrDNum , //(O)Write Data Number In Fifo + output WrFull , //(I)Write Full + input [DW_C -1:0] WrData , //(I)Write Data + //Read Signal + input RdClk , //(I)Read Clock + input RdEn , //(I)Read Enable + output [AW_C-1:0] RdDNum , //(O)Radd Data Number In Fifo + output RdEmpty , //(O)Read FifoEmpty + output [DW_C-1 :0] RdData //(O)Read Data +); + +//Define Parameter +/////////////////////////////////////////////////////////////// + localparam TCo_C = 0 ; + + reg [1:0] WrClkRstGen = 2'h3; + reg [1:0] RdClkRstGen = 2'h3; + + always @( posedge WrClk or posedge Reset) + begin + if (Reset) WrClkRstGen <= # TCo_C 2'h3; + else + begin + WrClkRstGen[0] <= # TCo_C 1'h0; + WrClkRstGen[1] <= # TCo_C (&RdClkRstGen); + end + end + + wire WrClkRst = WrClkRstGen[1]; + + /////////////////////////////////////////////////// + always @( posedge RdClk or posedge Reset) + begin + if (Reset) RdClkRstGen <= # TCo_C 2'h3; + else + begin + RdClkRstGen[0] <= # TCo_C 1'h0; + RdClkRstGen[1] <= # TCo_C (&WrClkRstGen); + end + end + + wire RdClkRst = RdClkRstGen[1]; + + /////////////////////////////////////////////////// + wire FifoWrEn = WrEn; + wire [AW_C :0] WrAddrCnt ; + wire [AW_C :0] FifoWrAddr ; + wire FifoWrFull ; + + FifoAddrCnt # ( .CounterWidth_C (AW_C)) + U1_WrAddrCnt + ( + //System Signal + .Reset ( WrClkRst ) , //System Reset + .SysClk ( WrClk ) , //System Clock + //Counter Signal + .ClkEn ( FifoWrEn ) , //(I)Clock Enable + .FifoFlag ( FifoWrFull ) , //(I)Fifo Flag + .AddrCnt ( WrAddrCnt ) , //(O)Address Counter + .Addess ( FifoWrAddr ) //(O)Address Output + ); + + /////////////////////////////////////////////////// + reg [DW_C-1:0] FifoBuff [DD_C-1:0]; + + always @( posedge WrClk) + begin + if (WrEn & (~WrFull)) + begin + FifoBuff[FifoWrAddr[AW_C-1:0]] <= # TCo_C WrData; + end + end + + /////////////////////////////////////////////////// + + /////////////////////////////////////////////////// + wire FifoEmpty ; + wire FifoRdEn ; + + wire [AW_C :0] RdAddrCnt ; + wire [AW_C :0] FifoRdAddr ; + + FifoAddrCnt #( .CounterWidth_C (AW_C)) + U2_RdAddrCnt + ( + //System Signal + .Reset ( RdClkRst ) , //System Reset + .SysClk ( RdClk ) , //System Clock + //Counter Signal + .ClkEn ( FifoRdEn ) , //(I)Clock Enable + .FifoFlag ( FifoEmpty ) , //(I)Fifo Flag + .AddrCnt ( RdAddrCnt ) , //(O)Address Counter + .Addess ( FifoRdAddr ) //(O)Address Output + ); + + /////////////////////////////////////////////////// + reg [DW_C-1 :0] FifoRdData ; + + always @( posedge RdClk) + begin + if (FifoRdEn) FifoRdData <= # TCo_C FifoBuff[FifoRdAddr[AW_C-1:0]]; + end + + /////////////////////////////////////////////////// + assign RdData = FifoRdData ; //(O)Read Data + + reg [AW_C:0] WrRdAddr = {AW_C+1{1'h0}}; + + always @( posedge WrClk) + begin + if (WrClkRst) WrRdAddr <= # TCo_C {AW_C+1{1'h0}} ; + else WrRdAddr <= # TCo_C FifoRdAddr [AW_C:0] ; + end + + /////////////////////////////////////////////////////////// + wire [AW_C-1:0] WrRdAHex; + wire [AW_C-1:0] WrWrAHex; + + GrayDecode #(AW_C) WRAGray2Hex (WrRdAddr [AW_C-1:0] , WrRdAHex[AW_C-1:0]); + GrayDecode #(AW_C) WWAGray2Hex (FifoWrAddr [AW_C-1:0] , WrWrAHex[AW_C-1:0]); + + /////////////////////////////////////////////////////////// + reg [AW_C-1:0] WrAddrDiff; + + always @( posedge WrClk) + begin + if (WrFull) WrAddrDiff <= # TCo_C {AW_C{1'h1}} ; + else WrAddrDiff <= # TCo_C (WrWrAHex - WrRdAHex) ; + end + + /////////////////////////////////////////////////////////// + assign WrDNum = WrAddrDiff[AW_C-1:0]; //(O)Data Number In Fifo + + reg [AW_C:0] WrRdAddrReg = {AW_C+1{1'h0}}; + + always @( posedge WrClk) + begin + if ( WrClkRst) WrRdAddrReg <= # TCo_C {AW_C+1{1'h0}} ; + else WrRdAddrReg <= # TCo_C WrRdAddr[AW_C : 0] ; + end + + /////////////////////////////////////////////////////////// + reg RdAddrChg = 1'h0; + reg WrFullClr = 1'h0; + + always @( posedge WrClk) + begin + if ( WrClkRst) RdAddrChg <= # TCo_C 1'h0 ; + else RdAddrChg <= # TCo_C (FifoWrFull & (WrRdAddr[AW_C-1:0] != WrRdAddrReg[AW_C-1:0])); + end + + always @( posedge WrClk) + begin + if ( WrClkRst) WrFullClr <= # TCo_C 1'h0 ; + else WrFullClr <= # TCo_C (FifoWrFull & RdAddrChg); + end + + /////////////////////////////////////////////////////////// + reg RdAHighNext = 1'h0; + + wire RdAHighRise = (~WrRdAddrReg[AW_C-1]) & WrRdAddr[AW_C-1]; + + always @( posedge WrClk) + begin + if (WrClkRst ) RdAHighNext <= # TCo_C 1'h0 ; + else if (RdAHighRise) RdAHighNext <= # TCo_C (~WrRdAddr[AW_C]) ; + end + + /////////////////////////////////////////////////// + wire FullCalc = (WrAddrCnt[AW_C-1:0] == WrRdAddr[AW_C-1:0]) + && (WrAddrCnt[AW_C ] != (WrRdAddr[AW_C-1] ? WrRdAddrReg[AW_C] : RdAHighNext) ); + + /////////////////////////////////////////////////// + reg FullFlag = 1'h0; + + always @( posedge WrClk) + begin + if (WrClkRst) FullFlag <= # TCo_C 1'h0; + else if (FullFlag) FullFlag <= # TCo_C (~WrFullClr); + else if (FifoWrEn) FullFlag <= # TCo_C FullCalc; + end + + assign FifoWrFull = FullFlag; + + /////////////////////////////////////////////////// + assign WrFull = FifoWrFull ; //(I)Write Full + + reg [AW_C :0] RdWrAddr = {AW_C+1{1'h0}}; + + always @( posedge RdClk) + begin + if (RdClkRst ) RdWrAddr <= # TCo_C {AW_C+1{1'h0}} ; + else RdWrAddr <= # TCo_C FifoWrAddr [AW_C:0] ; + end + + /////////////////////////////////////////////////////////// + wire [AW_C-1:0] RdWrAHex; + wire [AW_C-1:0] RdRdAHex; + + GrayDecode # (AW_C) RWAGray2Hex (RdWrAddr [AW_C-1:0] , RdWrAHex[AW_C-1:0] ); + GrayDecode # (AW_C) RRAGray2Hex (FifoRdAddr [AW_C-1:0] , RdRdAHex[AW_C-1:0] ); + + /////////////////////////////////////////////////////////// + reg [AW_C-1:0] RdAddrDiff; + + always @( posedge RdClk) + begin + if (RdEmpty ) RdAddrDiff <= # TCo_C {AW_C{1'h0}} ; + else RdAddrDiff <= # TCo_C (RdWrAHex - RdRdAHex) ; + end + + /////////////////////////////////////////////////////////// + assign RdDNum = RdAddrDiff[AW_C-1:0]; //(O)Data Number In Fifo + + reg [AW_C:0] RdWrAddrReg = {AW_C+1{1'h0}}; + + always @( posedge RdClk) + begin + if (RdClkRst) RdWrAddrReg <= # TCo_C {AW_C+1{1'h0}} ; + else RdWrAddrReg <= # TCo_C RdWrAddr [AW_C:0] ; + end + + /////////////////////////////////////////////////////////// + reg WrAddrChg = 1'h0; + reg EmptyClr = 1'h0; + + always @( posedge RdClk) + begin + if (RdClkRst) WrAddrChg <= # TCo_C 1'h0 ; + else WrAddrChg <= # TCo_C FifoEmpty & (RdWrAddr[AW_C-1:0] != RdWrAddrReg[AW_C-1:0]); + end + always @( posedge RdClk) + begin + if (RdClkRst) EmptyClr <= # TCo_C 1'h0; + else EmptyClr <= # TCo_C (FifoEmpty & WrAddrChg); + end + + /////////////////////////////////////////////////////////// + reg WrAHighNext = 1'h0; + + wire WrAHighRise = (~RdWrAddrReg[AW_C-1]) & RdWrAddr[AW_C-1]; + + always @( posedge RdClk) + begin + if (RdClkRst) WrAHighNext <= # TCo_C 1'h0 ; + else if (WrAHighRise) WrAHighNext <= # TCo_C (~RdWrAddr[AW_C]); + end + + /////////////////////////////////////////////////////////// + wire EmptyCalc = (RdAddrCnt[AW_C-1:0] == RdWrAddr[AW_C-1:0]) + && (RdAddrCnt[AW_C ] == (RdWrAddr[AW_C-1] ? RdWrAddrReg[AW_C] : WrAHighNext)); + + /////////////////////////////////////////////////////////// + reg EmptyFlag = 1'h1; + + always @( posedge RdClk) + begin + if (RdClkRst) EmptyFlag <= # TCo_C 1'h1; + else if (EmptyFlag) EmptyFlag <= # TCo_C (~EmptyClr); + else if (FifoRdEn) EmptyFlag <= # TCo_C EmptyCalc; + end + + assign FifoEmpty = EmptyFlag; + + /////////////////////////////////////////////////////////// + reg EmptyReg = 1'h0; + + always @( posedge RdClk ) + begin + if (RdClkRst) EmptyReg <= # TCo_C 1'h1; + else if (FifoRdEn) EmptyReg <= # TCo_C FifoEmpty; + end + + /////////////////////////////////////////////////////////// + assign RdEmpty = (FIFO_MODE == "ShowAhead") ? EmptyReg : FifoEmpty; //(O)Read FifoEmpty + + reg RdFirst = 1'h0; + + always @( posedge RdClk) + begin + if (FIFO_MODE == "ShowAhead") + begin + if (RdClkRst) RdFirst <= # TCo_C 1'h0 ; + else if (RdFirst) RdFirst <= # TCo_C 1'h0 ; + else if (EmptyClr) RdFirst <= # TCo_C RdEmpty ; + end + else RdFirst <= # TCo_C 1'h0 ; + end + + /////////////////////////////////////////////////////////// + assign FifoRdEn = RdEn || RdFirst ; + + /////////////////////////////////////////////////////////// + +//666666666666666666666666666666666666666666666666666666666 + +endmodule + +//////////////// DaulClkFifo ////////////////////////////// + +///////////////// FifoAddrCnt ///////////////////////////// + +module FifoAddrCnt +# ( + parameter CounterWidth_C = 9 , + parameter CW_C = CounterWidth_C + ) +( + //System Signal + input Reset , //System Reset + input SysClk , //System Clock + //Counter Signal + input ClkEn , //(I)Clock Enable + input FifoFlag , //(I)Fifo Flag + output [CW_C:0] AddrCnt , //(O)Address Counter + output [CW_C:0] Addess //(O)Address Output +); + +//Define Parameter +/////////////////////////////////////////////////////////// +localparam TCo_C = 1; + + wire [CW_C-1:0] GrayAddrCnt; + wire CarryOut; + + GrayCnt #(.CounterWidth_C (CW_C)) + U1_AddrCnt + ( + //System Signal + .Reset ( Reset ), //System Reset + .SysClk ( SysClk ), //System Clock + //Counter Signal + .SyncClr ( 1'h0 ), //(I)Sync Clear + .ClkEn ( ClkEn ), //(I)Clock Enable + .CarryIn ( ~FifoFlag ), //(I)Carry input + .CarryOut ( CarryOut ), //(O)Carry output + .Count ( GrayAddrCnt ) //(O)Counter Value Output + ); + +/////////////////////////////////////////////////////////// + reg CntHighBit; + + always @( posedge SysClk ) + begin + if (Reset) CntHighBit <= # TCo_C 1'h0; + else if (ClkEn) CntHighBit <= # TCo_C CntHighBit + CarryOut; + end + +/////////////////////////////////////////////////////////// + reg [CW_C:0] AddrOut; //(O)Address Output + + always @(posedge SysClk) + begin + if (Reset) AddrOut <= # TCo_C {CW_C{1'h0}}; + else if (ClkEn) AddrOut <= # TCo_C FifoFlag ? AddrOut : AddrCnt; + end + +/////////////////////////////////////////////////////////// + assign AddrCnt = {CntHighBit , GrayAddrCnt} ; //(O)Address Counter + assign Addess = AddrOut ; //(O)Address Output + +//111111111111111111111111111111111111111111111111111111111 + +endmodule + +/////////////////// FifoAddrCnt ////////////////////////// + +module GrayCnt +# ( + parameter CounterWidth_C = 9 , + parameter CW_C = CounterWidth_C + ) +( + //System Signal + input Reset , //System Reset + input SysClk , //System Clock + //Counter Signal + input SyncClr , //(I)Sync Clear + input ClkEn , //(I)Clock Enable + input CarryIn , //(I)Carry input + output CarryOut , //(O)Carry output + output [CW_C-1:0] Count //(O)Counter Value Output +); + +//Define Parameter +/////////////////////////////////////////////////////////// +localparam TCo_C = 1; + + wire [CW_C:0 ] CryIn ; + wire [CW_C-1:0] CryOut ; + + reg [CW_C-1:0] GrayCnt; + + assign CryIn[0] = CarryIn; + + genvar i; + generate + for(i=0;i1) ? 1'h0: 1'h1 ; + else if (SyncClr) GrayCnt[i] <= # TCo_C (i>1) ? 1'h0: 1'h1 ; + else if (ClkEn) GrayCnt[i] <= # TCo_C GrayCnt[i] + CryIn[i]; + end + + ////////////// + if (i==0) + begin + assign CryOut[0] = GrayCnt[0] && CarryIn; + assign CryIn [1] = ~GrayCnt[0] && CarryIn; + end + else + begin + assign CryOut[i ] = CryOut[ 0] && (~|GrayCnt[i:1]); + assign CryIn [i+1] = CryOut[i-1] && GrayCnt[i ] ; + end + end + + endgenerate + + wire GrayCarry = CryOut[CW_C-2]; + +/////////////////////////////////////////////////////////// + reg CntHigh = 1'h0; + + always @( posedge SysClk) + begin + if (Reset) CntHigh <= # TCo_C 1'h0; + else if (ClkEn) CntHigh <= # TCo_C (CntHigh + GrayCarry); + end + +/////////////////////////////////////////////////////////// + assign Count = {CntHigh , GrayCnt[CW_C-1:1]} ; //(O)Counter Value Output + assign CarryOut = CntHigh & GrayCarry ; //(O)Carry output + +/////////////////////////////////////////////////////////// + +//111111111111111111111111111111111111111111111111111111111 + +endmodule + +////////////////////// GrayCnt //////////////////////////// + +module GrayDecode +# ( + parameter DataWidht_C = 8 + ) +( + input [DataWidht_C-1:0] GrayIn, + output [DataWidht_C-1:0] HexOut +); + + //Define Parameter + /////////////////////////////////////////////////////////////// + parameter TCo_C = 1; + + localparam DW_C = DataWidht_C; + + /////////////////////////////////////////////////////////////// + reg [DW_C-1:0] Hex; + + integer i; + + always @ (GrayIn) + begin + Hex[DW_C-1]=GrayIn[DW_C-1]; + for(i=DW_C-2;i>=0;i=i-1) Hex[i]=Hex[i+1]^GrayIn[i]; + end + + assign HexOut = Hex; + + /////////////////////////////////////////////////////////////// + +endmodule + + + diff --git a/fpga/ip/gTSE/Testbench/ODDR.v b/fpga/ip/gTSE/Testbench/ODDR.v new file mode 100644 index 0000000..d78b0da --- /dev/null +++ b/fpga/ip/gTSE/Testbench/ODDR.v @@ -0,0 +1,159 @@ +`timescale 1 ps / 1 ps + +`celldefine + +module ODDR (Q, C, CE, D1, D2, R, S); + + output Q; + + input C; + input CE; + input D1; + input D2; + input R; + input S; + + parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; + parameter INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D1_INVERTED = 1'b0; + parameter [0:0] IS_D2_INVERTED = 1'b0; + + parameter SRTYPE = "SYNC"; + parameter ROC_WIDTH = 100000; + + localparam MODULE_NAME = "ODDR"; + + pulldown P1 (R); + pulldown P2 (S); + + reg GSR; + reg q_out = INIT, qd2_posedge_int; + + wire c_in,delay_c; + wire ce_in,delay_ce; + wire d1_in,delay_d1; + wire d2_in,delay_d2; + wire gsr_in; + wire r_in,delay_r; + wire s_in,delay_s; + + assign gsr_in = GSR; + assign Q = q_out; + + initial begin + GSR = 1'b1; + #(ROC_WIDTH) + GSR = 1'b0; + end + + initial begin + + if ((INIT != 0) && (INIT != 1)) begin + $display("Attribute Syntax Error : The attribute INIT on %s instance %m is set to %d. Legal values for this attribute are 0 or 1.", MODULE_NAME, INIT); + #1 $finish; + end + + if ((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE")) begin + $display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on %s instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE or SAME_EDGE.", MODULE_NAME, DDR_CLK_EDGE); + #1 $finish; + end + + if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin + $display("Attribute Syntax Error : The attribute SRTYPE on %s instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", MODULE_NAME, SRTYPE); + #1 $finish; + end + + end // initial begin + + + always @(gsr_in or r_in or s_in) begin + if (gsr_in == 1'b1) begin + assign q_out = INIT; + assign qd2_posedge_int = INIT; + end + else if (gsr_in == 1'b0) begin + if (r_in == 1'b1 && SRTYPE == "ASYNC") begin + assign q_out = 1'b0; + assign qd2_posedge_int = 1'b0; + end + else if (r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin + assign q_out = 1'b1; + assign qd2_posedge_int = 1'b1; + end + else if ((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin + deassign q_out; + deassign qd2_posedge_int; + end + else if (r_in == 1'b0 && s_in == 1'b0) begin + deassign q_out; + deassign qd2_posedge_int; + end + end // if (gsr_in == 1'b0) + end // always @ (gsr_in or r_in or s_in) + + + always @(posedge c_in) begin + if (r_in == 1'b1) begin + q_out <= 1'b0; + qd2_posedge_int <= 1'b0; + end + else if (r_in == 1'b0 && s_in == 1'b1) begin + q_out <= 1'b1; + qd2_posedge_int <= 1'b1; + end + else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin + q_out <= d1_in; + qd2_posedge_int <= d2_in; + end +// CR 527698 + else if (ce_in == 1'b0 && r_in == 1'b0 && s_in == 1'b0) begin + qd2_posedge_int <= q_out; + end + end // always @ (posedge c_in) + + + always @(negedge c_in) begin + if (r_in == 1'b1) + q_out <= 1'b0; + else if (r_in == 1'b0 && s_in == 1'b1) + q_out <= 1'b1; + else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin + if (DDR_CLK_EDGE == "SAME_EDGE") + q_out <= qd2_posedge_int; + else if (DDR_CLK_EDGE == "OPPOSITE_EDGE") + q_out <= d2_in; + end + end // always @ (negedge c_in) + + assign delay_c = C; + assign delay_ce = CE; + assign delay_d1 = D1; + assign delay_d2 = D2; + assign delay_r = R; + assign delay_s = S; + + assign c_in = IS_C_INVERTED ^ delay_c; + assign ce_in = delay_ce; + assign d1_in = IS_D1_INVERTED ^ delay_d1; + assign d2_in = IS_D2_INVERTED ^ delay_d2; + assign r_in = delay_r; + assign s_in = delay_s; + + +//*** Timing Checks Start here + + specify + + (C => Q) = (100:100:100, 100:100:100); + (posedge R => (Q +: 0)) = (0:0:0, 0:0:0); + (posedge S => (Q +: 0)) = (0:0:0, 0:0:0); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // ODDR + +`endcelldefine + diff --git a/fpga/ip/gTSE/Testbench/aldec/gTSE.sv b/fpga/ip/gTSE/Testbench/aldec/gTSE.sv new file mode 100644 index 0000000..69de231 --- /dev/null +++ b/fpga/ip/gTSE/Testbench/aldec/gTSE.sv @@ -0,0 +1,9845 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.288.2.10 +// IP Version: 7.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _4c19f37180ff465ca20760e199a0613f +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module gTSE +( + input mac_reset, + input proto_reset, + output rx_mac_aclk, + input tx_mac_aclk, + output [2:0] eth_speed, + input rx_axis_clk, + output rx_axis_mac_tuser, + output rx_axis_mac_tlast, + output rx_axis_mac_tvalid, + input rx_axis_mac_tready, + input tx_axis_clk, + input tx_axis_mac_tvalid, + input tx_axis_mac_tlast, + input tx_axis_mac_tuser, + output tx_axis_mac_tready, + output [3:0] rgmii_txd_HI, + output [3:0] rgmii_txd_LO, + output rgmii_tx_ctl_HI, + output rgmii_tx_ctl_LO, + output rgmii_txc_HI, + output rgmii_txc_LO, + input [3:0] rgmii_rxd_HI, + input [3:0] rgmii_rxd_LO, + input rgmii_rx_ctl_HI, + input rgmii_rx_ctl_LO, + input rgmii_rxc, + input s_axi_aclk, + output [7:0] rx_axis_mac_tdata, + input [7:0] tx_axis_mac_tdata, + input [0:0] tx_axis_mac_tstrb, + output [0:0] rx_axis_mac_tstrb, + output MdoEn, + output Mdo, + input Mdi, + output Mdc, + input [9:0] s_axi_araddr, + output s_axi_arready, + input s_axi_arvalid, + input [9:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_awvalid, + input s_axi_bready, + output [1:0] s_axi_bresp, + output s_axi_bvalid, + output [31:0] s_axi_rdata, + input s_axi_rready, + output [1:0] s_axi_rresp, + output s_axi_rvalid, + input [31:0] s_axi_wdata, + output s_axi_wready, + input s_axi_wvalid +); +`IP_MODULE_NAME(efx_mac1gbe) +#( + .VERSION (16), + .TXFIFO_EN (1'b1), + .RXFIFO_EN (1'b1), + .TXFIFO_DTH (4096), + .RXFIFO_DTH (4096), + .PHY_INTF_MODE (0), + .AXIS_DW (8), + .RGMII_RXC_EDGE (1'b1), + .RGMII_TXC_DLY (1'b1), + .INTER_PACKET_GAP (6'd12), + .MTU_FRAME_LENGTH (16'd1518), + .MAC_SOURCE_ADDRESS (48'd0), + .ENABLE_BROADCAST_FILTERING (1'b1), + .LOOPBACK_EN (1'b1), + .APBIF (1'b0), + .FAMILY ("TITANIUM") +) +u_efx_mac1gbe +( + .mac_reset ( mac_reset ), + .proto_reset ( proto_reset ), + .rx_mac_aclk ( rx_mac_aclk ), + .tx_mac_aclk ( tx_mac_aclk ), + .eth_speed ( eth_speed ), + .rx_axis_clk ( rx_axis_clk ), + .rx_axis_mac_tuser ( rx_axis_mac_tuser ), + .rx_axis_mac_tlast ( rx_axis_mac_tlast ), + .rx_axis_mac_tvalid ( rx_axis_mac_tvalid ), + .rx_axis_mac_tready ( rx_axis_mac_tready ), + .tx_axis_clk ( tx_axis_clk ), + .tx_axis_mac_tvalid ( tx_axis_mac_tvalid ), + .tx_axis_mac_tlast ( tx_axis_mac_tlast ), + .tx_axis_mac_tuser ( tx_axis_mac_tuser ), + .tx_axis_mac_tready ( tx_axis_mac_tready ), + .rgmii_txd_HI ( rgmii_txd_HI ), + .rgmii_txd_LO ( rgmii_txd_LO ), + .rgmii_tx_ctl_HI ( rgmii_tx_ctl_HI ), + .rgmii_tx_ctl_LO ( rgmii_tx_ctl_LO ), + .rgmii_txc_HI ( rgmii_txc_HI ), + .rgmii_txc_LO ( rgmii_txc_LO ), + .rgmii_rxd_HI ( rgmii_rxd_HI ), + .rgmii_rxd_LO ( rgmii_rxd_LO ), + .rgmii_rx_ctl_HI ( rgmii_rx_ctl_HI ), + .rgmii_rx_ctl_LO ( rgmii_rx_ctl_LO ), + .rgmii_rxc ( rgmii_rxc ), + .s_axi_aclk ( s_axi_aclk ), + .rx_axis_mac_tdata ( rx_axis_mac_tdata ), + .tx_axis_mac_tdata ( tx_axis_mac_tdata ), + .tx_axis_mac_tstrb ( tx_axis_mac_tstrb ), + .rx_axis_mac_tstrb ( rx_axis_mac_tstrb ), + .MdoEn ( MdoEn ), + .Mdo ( Mdo ), + .Mdi ( Mdi ), + .Mdc ( Mdc ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arready ( s_axi_arready ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awready ( s_axi_awready ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rready ( s_axi_rready ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_wready ( s_axi_wready ), + .s_axi_wvalid ( s_axi_wvalid ) +); +endmodule + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +MKHWLtljMm7kaIKwqUK8B5EM2QxPAoxLfX2cJIpcD8uU6akTM8tOaCCq3fMfRLOr +SMgTjMO8gkEDhuWpeeY3zc0UfPumTQ7/0MePhALxq2YkHeE6xpzjoV214ddWs2SZ +ngn3y/T3JwvOLSP8v3chWxTaLfsv781pmyiWaW2ANcnxLKss63esqdwxjuAKGa1E +t4Pkivr+Y4WTlOFhRJLNNWs96MemiTmFKpo0yfpF8JoeM118sL8OZxdN3uFAYRGY +JjRQnM2MKtMN/trj8aMlCDTmFBKh76B5x+WVJ6FpZzMTtC43cHm6IFdKP5cbozNi +q6qjblAU3CRV8RZn8/HoCg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 8512 ) +`pragma protect data_block +98jMY7pxEJ1JvjZ+eQeniKqSLGmDGbOWaPlk/M955KVX5c7n52LdyGStmuY7dCab +g8NTjE4+i09IRpDefPfyaaym1A06mlsbgp5oN38HenFxix5N+5lsp6E2EaTLm4oH +7GDWIAlrO0Rorv99pM9hODxx75Tmgiz1ywqbDqgiuo3oWipJR3YXgdYPgznscawv +0a8JAbX0UdR9aZHXXiXQDCZJHgj2/it+QjnWX1Q75OPdfTrxyz5yDIONvuntVpOS +0gpyMnWeE7wUYngpHInfOu3RPe4kJH5MWO8Lm6i014WAkLaP4COgeuVJYWCa3uVH +VuL+f7qX0NKz4E1al6xmD5XKrCVMHB8UyUJT8+UvAvLOPnH1T1wXi/yqNzhnou07 +VbGqh3Fj2j2vsuHkWStudct6oNx1w/8aUFPUOIbP8r1UKjkGywzvePKqAOU4j94H +eVwJGXoCkWl6Nu9pjYzBZg40bq4U2TzpLNRdX9AvfzmxrtT/a1H/Z/xAIBeaUqE+ +etH8yvIExe2f3Fjz3CDLLgGOb1ZfQWo6BiLzruG1S/DgjXMO/eU77W1RhBwjnrP8 +q35CHK871v6WHTeOTcgz+BZoHd6WFJu1OdEqbYDQ0eI/TRgyl/HESMbEiYjoPJ12 +8rOZb6SYe3LdVazc68v5bPK0bXOayM1Bm42Y5PLmRdZXG6NrvFSGwEgvKz8afoFP +BsHAYSQhI2d30MzT1lvpSAIQ1OzCWMVJnLogLlmAC/8Zu9i/3qZEaGBNvN4N55/b +lZ/mJJERQnO9yMwXAR3kVNuPY9bRJlFARqwQfSspgpAaesGn/pKmYZkpuA+HCQDC +ClvrQLqOzzI6NVhT2vvGyYgraLjEk9JaiCGFLr5tjLhZG3MjvdcoKdnZ/JIhUX4m +x7OMl8u9VwvvJzYe3qU29vzaCaAxVp3DW9ZnHLylrb99WOJNI/z8+O7o9UyzyEMZ +jYHSB2A2ik3xQE3xVhtYzF+pGUdNQNDYyVsvvbL/tTvVHV96hUQWf2podem7bz67 +90NLUxTBbu93cLtjmSh1fhUNPxaUsK3aHdXZNzX+J/Sl3sx8E1EzmQdCbNhSUj5N +zzK9bagUGB362CKpJLpDMj4ZOthYEtE9zUBeqjlR4KwY//ZWt4lcT5Ml8FFUQ/89 +HQFBHJRfbvsFMAFZXA3IpIgmc3kwy3l3JEvRcq5NUn0QRiMPKE7SR8e9KnFTiW6a +AAI/yiStOuhkiRnQyjfv45cC7C7cTnJ+hFCDQoWfVYE1ODFAq2o/0C+Y4GmE65OS ++s+yYMWsJ94WRdUlH+rRw2Z19SthSw1APlaF3MmEDZRQzy2ugRXTUof6fPIPaXaB +y0f3r/C7cXkmMIejHT37G+30K+NrmqOp4rnRKQvu4nXkJyI1REvktSaUwovBsHSd +zz/E7I5sHx4g+HFq5oJO3N0s8wpKFvnXilwx9eumZLN2a1YY+GZbiUhQlaPoUegu +W32XZUQitt+vb+nqVcUPLmLT4htyCLbMOwhr0yoKoRlfub0UoH7TNHKEK7HFs7uM +VQfHsWGuitPBSXwdVmtU1HR8XkYpNJQ4umlLwT/wCdtx+NoWD76CRzEQBdML7iG7 +yU0F4CV0oFp2sjxpcUJKUxvhLbD7+L8P49tzrm0rKCV4apGyLIiqzIKpWixgvuZW +VS05TUIdhlCDUDvb34h1sEr9Se8EOEAKbiAWVQfg22v+rDlKr2AGK7RaAFsaRV2E +bGB1lkqARCOy5PYSxGCYguyaI7ulJoU9WFUwzicsjruUV+LAYGl0SkpiagSMlK4Z +5nMRi/TgakUNaQKXH58tha6WDahMQVZH8f7rSrZ/zKDBSEs/2DSQh2mRWBM6kK0t +SGxu7YpJ4tqxtW7DV6cNKow2S0sUgN0rqTVGpym3CeqH+7Nx1UMOMyWUyZFRqSM3 +RW2kV06GbgRyRjLLWNFBqZb+BinZu7Dd7RRg8LcrTEl1cTkVklkoxKa7KXdbWmk0 +vlXPfc1jODnUwjWYzN+xo93YUvhnLbrG5omxfFiQho95NauP5SSIxSCsH3z8Vm66 +Ctbh5EwS5TueyQRNGQeGnumUZMAyyxdZElkvWUubCkw+XcEbdff2jxZyyiV4rldI +lR2maqidWu51MfCMo4ddr1MCapi+EGBwacKrr30+4NIY7P9Mfvk1th90Y5pBgxXq +BSbSSTcjBjmydfxIfXVzacwf+tnUI3jHzMkcnuLeD3GMsqXgaseSz5DAsENZ14pa +YyA87fomltfOl4eT5M9gx/ja11reiyv8xvstB/DOdNhrkfXZtM95fZTWol9Yc5Jb +MS0RHtkWuoR6IRan0k9ds6YKiCsG0yuvetZqNduCPOcIeS0OuqZYzhLEbifoeKN3 +oM72QleNFxVhn86irf0lJBu90I34KCP0xF1J/9+CN3nQB5/Gr7NbtCebp8Z601S7 +mKHR2p6jj2YAWl5G8zP/Lf68W+n6xxLBQOtf4AaJ+xU6ZZrTNPK4rxpqgQcACNk7 +eEvsgVZBPXPnRAaPkM+Csv5xBW9VOKVS/n9B+OMRCzYUoJ/lH9ilF81WNhi+G/M4 +x1OHycLXpJQjl9azOb6K/SLTfIO/O0DKoENYa9dxYDiUpCvVUp0Q9OC7oC/V4GNa +RH0Je8YaAx87JskGF0cqH4n37lnrXsRL1BrYc9Hu6T/IwHdwzPJvQwgoD8Q+FWGO +uFq7/R+QjFzrvl3IM/ZnTJOoX8W0wqWzP8nYzmKd6ApBRQ4ZlbyRu9F6nzlhg1Xi +NljKuF0nuAuoy7juhhUkK2069tNqakr2F+PkRzCreWRr7BzzQvhbUH8+Lhl3xeP/ +M/ujj8Y39b+zYKJ5SQaQFBVkQUglbOjk2BXjvkZ5EatUk6D62EK7APUrwh34Hawd +4etMGVMBE131M5TVpNNYdr0JAQfgEWwj1hS6L+ImfRfe56JLZox8GDR9rtjvbRpc +6lzIf+t+JQRf6ACySoA/kpHx9pOmcGoRETiRXVT8eE+NwoUI1xWD4iUTMh6hS6En +pmpcnch8yU9WJ1JUyDiKzH1tDrzphXk8jmQmwBakLSQ9CNHpgJJP5us1sz3Xyrov +hdWWabwJHbxGWwMfWo7jIPLncsb8hCqgLel9IipdB4X02ZNKq98CkvB1ZwAnNDDl +CuWloOuH475TkU80jQXZdDZMpU3Kxm02FTMN10v1coRYtN5ZJMlwCR8G5HKAOzI+ +hYqgeCyUCX9EvsKeEL9YuS0nPmJbEBruin8b6vrQMmKjF2JGMeS8RLHyHJ9LMdQ/ +Gux8N/YwVSEyo3LfaoilvermyfRVLQYYVmEUVwTR3U0vQ0UAx/IiuWSC+7AP1X9F +3rqKTV3Fx2moZkWje1CFO8l2wm0n7fjokjK2Vh9jmRR0h116loQAU4zkbx0bFRsE +uCbaqs5mFVJRCKxwl/gr+nNQmtE37k88vF4UHuTvu8xhMw+YqH9ivCmzxmd37geL +A1Wbq4C/WkWUhAEz6561i5G6KucjbU0Tv3zVYN4b5jDMd5xAIhYwX/0FCnc7y5li +nYgF8CIuZ3I3EL2hpDGeSILwYkPF9POSc3fgbCiFWQIIAa8Z9jASaFbGJh6sEO4H +6esLG16KgLYvjxBBjfdK1vaItshVMSN2SSh4lN21Wb4v5DUA3RqcbVEb0baCeXPF +/j9ZY/OYA4AXBYT2byFsWSno9NTNoTssfdm63fHVC4IvwtLECox6ynlc4Qh4K8DW +BDqFUOJ4kGXdeuNrc+1z00oNptdCx5Rg3ab3Jaz+2ajcVz6qcTadZ2aHi8sLeTHM +f+2fGo3raPyYFsqITNFE/s56T7FaKzEHDMgrj+t4atk+Ou4rb9ELvzk0ExOqpYib +Vy5ft7KYJ/LeGKE/K6lS4WkJikTeCDpK/gwy4ZapsHnedXqDa2i0P0i1EJdIb7an +JdHZXlsjJQM7lt3b7XsQrapbCExOyeFNoDUPF4ETUuTxK3GuumwAyruTdsu1X9iT +XfTZCgtg/rodsp9HllB3biQbDCJ3tmP8XenyMyxHteEQsPf+zSd0QZO3ghC2Yp+h +8WXdaxQstw7Jq8+HGaFl7S2ThK2yvBPdkSSOHmVnhNWvZ35842FHc+aphYYUb7Pl +A0h4mt5KeX4hn1wV13vCzKVGVzhwCnrEIc1xbAQcHwoUiYzBzJ7RkRo5+me1o+a5 +Im+hyIUn/+046o/Mo8n/e9uYLRwxjNXaJ68+aw9hFb1IWYGvsm+M9Xou7m2fvap9 +sbim6IG9+MJNK4PyUY6ZxltfyQXKFBCzSD80/3HI9MXCoPc9znfy1UkonC5G+oCT +AgqRtmB073P8cvFu2UOEm0WltTm/6jCbF01oTMOYopfLLVpK08Sddj1NzXEIkK8F +3ftYZpb2oYG+5shU704KQlKjetXgfITc7Qc8aiQ50wbnR45A4y7rtbJQKm8pwk0c +naDnn13/2yL+AQNg6lj6OvuIVvmbGsmtJw08h4bZdUp2FO3ITWpoxfn+jk76sX68 +5aOh/tUunQibffy9ZAYFXNSVqM9XNYsR3FqbWc8U8QDF/BURfDwYYNcWYkHafjq0 +9WZTgTgnx2DfjFDXonk5SA+OItBQpp8PObxHjqknoEExQ6enJ7RR1MsCVkVdHS00 +oi80puFxYY2rACmIgvA6cXSIDdNeg1ubCSbMwiymgOUyXYo093UaCLd2YzPWqrzT +IyEj6AaBxNwmWbO1/u7F2w/mJVGu1KTu4LtcIVxvK0hEG9dmUAC44Q1w1BMEYTLU +ZyLuD4jPeM7AlsR+jhnpegJcAA/XwSHKC+jHSKC5liE6yH097D2tkd9dl8znnQcb +sTWGD5pvIbMDPjqCMxZAzDK0qCpyqEwGPKnEaGFQAn5mbPUpkgWcAp4ncp+CYjPr +Nc2lz+gwdEerk657dN7lwrL2i12GYYXVWhXxfERy1A9QVLKOTv9o19rS8tKlPjgx +Wo9OpiMVmIiXh0tVeOyf3nnhtHrFhUUdhrfrlRSOT6TPtRy82y3q/9I6algSYEx8 +otjKPy/QujS3+46VDjrm9tlNq9q+/6vAoQGNZg1myI2HHqFH7yVYD/Iu6EcClf6T +BgM7zNXYBuk58u+tnNc1I+JtL38pjIwonBg2T0Brav5leIJ7hC7MEtAYRoN3srkx +5RZbrKh6rv19iynO028x48fPAikVIeKRoQRsQ5xkZXtMJQh4fJVVcQxsUkhIdlOU +vBpeVH6xX72YMJcKRyVCb5blPblMyWUxbaxZdsmAh/B2buPQcUp0T8LxJH3OQLj1 +7Huxq3d8CQG7jX5mre32uUF1Za6qSyRn5zCxI20cECRvjUD+ejbFWjz/qGGAWEKe +7b0I0/TolPteeGMCI3Gql4W1EFu67JzGm3Eud7zRPKrOAEnbyH2QHTgF6BJg7bTD +ORUWk1GCGM2xtFa7xQ0ijPxLuQAjF6KMep3iClQoOks+NWKnZlHio+0DPSm8g9wP +Jpe/uToFRm/5054IyfVN4VlSj3ZNfOCtuycAPxYTGrQuKzsLnHQck9IfHmkLPZiF +pcUWCNfCx7uLWcidV9PmOWb6klb/OnngcOg3OEgT3o+BLz0wn2okaBMvurmnC5Sh +jPhY5E+4xjruiWDE/W3SSJY5x0erKtNxbXITlRlM69C9MmmIxx9vKGXyhETU8D4v +lOeAZfv9ILdDOwBixM4UltwgoQxlNko3zZ5bnEx3p/vgoUODqSBCpD1Q41edyK8i +B4322QrvGkWXGhwgiQLKPogtY0QnfFyZFfd92dKgM+GdJil0bVki+d3bgk3g8B25 +7MFFfsynIebposlFAkCI2ESPVkVbPum7Yug9mF12kG+5NtIjrYiC1sxZB9qntiIK +f7GTEkVAqf+FjKBFG6mqSrypy/s+18e7QrQ5bVyXDffU0qNJd0W4a9pZhOsYf2oZ +ZzJjF4YhZTfkG+z7Q5sDlKzUvw0MXmCtGJJ3slEDgNlMQeWmcovte5nMEVmd5+oM +IroJHwv1qU3qKfa5YftpSLKWhkFVyiPGPJttiVZrL4Lg1UnxNUWNw3qwesCf6Gfr +37aFA1fM6fbQoig/iDV/9ynYlSFgMVx4f4JBM9bKdR3oe5Ko5hIr7P852vqD5VAI +aLAxuP2FrClkiL7pk7si73R0OXo/BVnFLXV9JQ18amj1FlYzx8wlFfR2y1lGOuZt +RBjpbWTUf7gM38vhKC/Vl1LsHxEWMivtRqnuzEnEmeZQAw4ghtKSv3oJDFimHRmL +S5rRXk8JnuGQiELJ5r6tWoZd2zOEHuvnlQc9A+t9Uhi83uYLxgDxnJ1WYqZLMry0 +PiNq4s4hnWS8tZT1yfSyA6fBT6yTBBD0USRls/2IiX99jAh25bgWP6i0aeDCxIyW ++qYVQyaxMXSeMbLnaiyhwH2uyHqSIeGGYq8/Pf7CJ85doW/FqepR8jvOfzseYWE8 +FW8O/Wm3QdjUfAIQRMXdLDxNYgaCIjsdCRkekzin3VgAIesn1mUOOxdlWaWd5Als +XS9HAbp/gQDy9qAugZDzxY5fm0TV+tAUDB9Q5XEW+/G+2Szfg7KumxrJHSuJXuPF +5hiqQpJwqx5wrz80amxUSjUh9t+NF6hBL2lRtSAc+xhyWTKMyAr+oHv25Z+3tDe5 +5Ow75TXGCWxXHzdTEPOF/l/IN6MD+aQMOJ10go7UcXfmVwkSPuh/Hq5Sy4qKUAg/ +Z+VwNXY9zdKVnjSaK18wx+SPQGo09cJ9TaU+BwBHvhe8qcYd9L39LvHIShg0E01J +s1BEur97sMkmt4QCDtm11v8EU1K5Tq3QshuEJuHGCDVFiR6JHt1EgmWp9eqNv4LP +R/Et4TniFm/ULbpgbI+9OZCJS42tiRZYY8MgWTuCQ3zC82aX1lc2SJPQ324Xj3AM +TeE26yUBTpKRXMgMUZ9PvNCCkJBwpaTqpqDxqFWdOZL/DeneYL+rYFQ4vgNbRDGd +6axHUEzWCvO5MKQjB9pFNPz8+8UlR/13D2qd9og+wDLjSWk1kkA7GoBa+fsDDzCq +adHoTvZoLAG25wrB0o+NoEeluABNy8WhE9BsE6RcFZYzOWWOho+4SbCPHQIxOu44 +NBFs7MIvmXVKtH4B+YB2emRZUZPWN84aHo0dwJ1CTGZnu9Ko0fKlSlbA0I3hJ4Je +6igMHQefhtBgCWn0CyDt1wgIMubEELTa9sSJZ9R753lPM1EPnjnJEETZUJHDvSDq +o1tXiL4dN1qlx7g83YOUENLiuaYrAIKq+qNU7xsrnGyTrUCsircuJoIvJr0NVRNH +Cv3xGkR+BLyaVF09LquzXBH/FshLWv77NPAR5wowG462y9nWqqNH3GDsaCzwWbzC +Gcj/h9cenA/V0fKMGcoEB6IfRBUi4JWW50ARdaesEbyIICPKiNGh8u6/rjK1/fyg +Y/q2ZKZ2FsmcTU/XFSMhpuGuFGrDsXBnfIUbTxda+lITJyiU1yL26XTCktZvWzMs +vlOyZYBVJ9883MgN0rjEhkpHgzmQy2U4ROzsDb3tpTiJ1k092TExwwrCd80F1q/J +g6pthQci9XM4b8gOYovpvgMbMTRkUZvvfY0XxIRP20s5/PH++7ajFeM0NHlw/2pZ +L9xfOoX8uxnI1JKVa50wcLM+Jlf5bHFRnC7Ug9AXeo2Smymix8uV353TxclaqSE1 +dEcEcR3U4PEw80L0EeOJo9ev43PxOOadbPoqo/MA27uaqD0RSIWH33s091t1a49C +L9CaIS3GZO3u1LfPn/HWJkDv3dmkfNKHK/hyENZ/QPJgWKfCmo5ZlGCrAbbZPHYh +tZky9WahfXIho7N/Nr4P8kOedeiL7TxVmdbFQPekmz9Rs+GBegQ0FV+fWFUGeOJf +Y2xVjM9z5cQow1SYOV22XiW/PUoJnZNtvq4/VfYgBJEX47hedmXY5jSWqdmeW3kL +uz8+hHp3sWgEeETCvpHWLNgDn6VJqP5cePahCwtQp0WrJl3V19Bfbnc0u3v+Ik8t +C8twY/uIjN1yfD3m7kcd2PlxGp9i9oC6U8NC+OxMSb3Fe0Tu8iFswy3t+Ke3m/VM +TuwxUaT1/EOMyYw9APu4/MLMQqgzlTr1WeD0J7EHyL3O6aeFlpzQ7tbb3lZ9AdVf +fDbFQiD8dkt6x2MQLTCDTwXE7Zw+aS3FBJvBFKjyykiWL9s/yZxS9v/gCisRnpK4 +4A9XuSd0rZ8TgJyFOzVo/j8Uv6nL4StM6zaFLo4NQAypPyxBY9TmGVXkX7oY9Aqt +3BQZsCJ93fPNEHWefsbo8UKMy5Tm2bimG173WGbJV1jzxUQtDfis93izE6GOMKdy ++slknTMvzjkzuFe22DJzg74Ux2cwMWKDpIrl2abz5K1OfAhYCC/TuNcwg5pzbtQm +e312tIsaXFbYhI50oaowCkoVLStWWOaQD9xIE1CFti9QI1hnOA8HOQG5Trwu3HqT +/6pq2QaiWnD1zMfWTwcKkKAs3Fc3OTDPaNx0J+o1e4GQafUkPQmrsYDGmVhnQ+Vc +gAHN3zAvOAnngH9QDrP32ZtOR7S/+qXvinc1K0ipf+fWOmdCVfHZEPVe0bHvl8d6 +hxgxxiot92oOQkkvcaAPzBvx0gdIr/rGUba697r+o1k/sczgsWI1ZbyeslehZpmv +xKj99xIzaaPIggGGy8Lo+O/hOXOSvaykkBp07dmcdmX5VJ9o/HqaVrTyq9HSrV2v +MXMdoRNDMJRUrPQ112mqAmgrItdp/F6SDE8K8x2lolrgYKnhGUa5cyJQ34riDSz0 +I6Av+Wv9C7zLomYJFx0EDqc6DD0Vc0auOjkXLALwf4hqXWKetnVxBMWikOH/uQvp +mTPMJm7WYA/d5z5BJsZD4Oxw+ejRg8xUl6kOouWKg1EiwfkP5Zm9b71VX5MLqaUW +t1o7KTiRfr5H6OztB56Ww7V9xznR+wjtbrHMK+JSssOzIbONXmTIHWspAHZ4cRTj +bIm7s1gPn+RzP8MPNJlNg0bHyaWDmW4LMTgYpa9/brSFuMlrp6uwGVd0tPYnH7q5 +7Y5aRLFQGhZk6dqfBRX8TfwyeeBAr2QD/C0+a6U1ekX7vDuoXqFGraw+YCSBCtQ1 +tzKL28UF/EliTv06Bcl2Afm8MALIxvKAw0WqnKPbAfcw49bS9FR++SIxcUHMA/0q +pbr+wW9Wz5FFGEHsb4DdHorwkpyRxJzl4tP7tr4w2v/C3pWQdWF7zJWFNuA7N08K +Bcvm9uVarlmev2g/WHKpniydE5mnacDIFHNwt102RcBA6gA9oOFxtMUNMfUnMWU0 +IdLHcNg/ycCRBi7dfjjMTkNRZLsxvnN7269NJ4KeDFVdMoHB0K4o0b+CajdXyIL6 +YCmpk86P3TLe3mwpFTGk3UF5Jqsh2Cqo9FalGh9nqyQtBXx7cAyZD/f5gCaX3pcQ +mxyNth5kbeTANYhPnoRC0X7UAbfSxeMsNZ9tFUqk50tcCQzjgc2pf1yBgCpj3HLX +hkp3FBKZsbpUT59CkVy7EhhQhcGz+JPWqEkPfnseCu8gDeRose66R4H95ZSDkyga +7zE5QVqjVlU45oGGm7qrMkjqe+2YX5D7dy2pPYck5t/IAL11/c8hLRr4gOx50JhM +8jzSoSQ88mhangZnyIv0Wwkv5xmSatOgqeWXFmINURFFHDdmo/TpjjOf9ubGgGwE +nhH8Mj9H4uIsW6cEshWvL24pkeLXIcz4y8IpZbSATJuU7e9PR08MVgGRvCjIOlIS +Khu2y8YBJrPFbpy7rSV76IDo9Vjj6qADWaMl4d+OjfEzKdYRCAa5eRBsXB50FkBX +J39jwFVYNfkCYUz+Fdx0Sdzp6L7kwAzoJfRuCeL21BvsQ6nG/M5oda8EQRhMHt6T +nwe6BB5HDWsrh7DF8L7lBucO9b0cSuQAYfhkIQKrt8jk0c5TO+DBfoPfCWQb6yV+ +JbOyJvs24rZYjBF2OFEjozoQMZ3CLgAUgHt/v1+jubiFajhsOrR305CAuxVd7ERy +m1WGaSJ0mqyE2Rwx3CUNrnKmo5L07pPf5kX0Pf61ScaTjWFDaKsyDvho1gVicQ5a +0LuaYBMjLhlHu+xj8S1N1nHpymCtmz+a45bZwtzcnmkyxW9SKYQtDJR8yOBoo2Gp +AfrXhRATe0Wmg6H/G3E9MCAUWK9rW75NolqWai1QnNfOqHDAaQz8r5v8oZCCRkCc +dMmLnW6ttLglqF6+36OZDMPVrMkZrwuLk0EzbyDtd7Odm1j/2AmMJQ+yVm06Oo9W +iRb+1DrsNpguHldCnlR4Fz1pWdve8UCvm9c7N/Sv3vMMUI3YpfbA+sb1xwIq5+JU +syQRisTt45frrF4nMTfMPALrschVgYy2Xk9E82Y4chTfD5K3f4BK7PANhiwXPOH/ +W8R4Dcpc00nZ3eJni48Wu+/n6KYQud8ic4l+R/9AY+Y3qRw341aurSthTsP3k8vE +AfbQU6sQP92LzN7TQ2uqNn/i+GGrk9/xLWGks57GWsyVPfMJmjohPa7sUd+J79lz +O/yBgYOZLMPE5HtqBVOAcWZ3qpIK4qPYYCV2LOtGyfuUXR3R9yDsc55RcL51OX3d +YVxv2C2qrf+xNnlhz0JImOYaugUOYTgHC+FPetGAqTVdGpag3I+xcijTd/ZktA35 +qsNeGlUEWpPCSBg6MCm2UKUHpeOCke5ZpL4Q3oEvwaK4U6STOthGM0scT06Ien8F +skVLyBa/4JE6gfWT+nKQ2GGqmMcd4yFEpj7yx/5NajrXhORzjfLKK46GhkmXzAE2 +5dMLH5oBmH7cSYs9jExINMAUHgjpKcB0qj90FBILm2EVsEfAL+GUwT2oBSAiA9Aw +nownDjLWMDRuDtGHN5UuqYQIQyzkIP2W2LxASIdlCHFuiQ7WVBdDTtc0Mh3QUZpc +7cnP/CqXMQAtxyjdMiUtyaby4qfujfUOUSMhPy4yExvU61ej+sbQ2T1YaW0AJtVy +NbtoCtawUApzkx8UhEuF8Xkbx5g+lUCguc59xjG3ycG5Nolt4zlFWtKnTCL6auS1 +8GcoP4NIbsmg5X0zRPw0Dq+UnxIM5mxgZCuIq3srwveSvo92iyCOyf8wPKQAe5YY +DKGqm7NqKz+CNRkmShDR5Oog4l3weQZleKMFUZ2xxvBcxqvjPgNpALEtBuotq7yG +vQFjwJYj1Xxc1bi57CyZkWFrTInFxc11dASiPfDd3N99CWC3jX7/vEzKvL8WwDUT +nc880Ln57vPhJ+yGlnibIWkvFfeU+xRB+QZ5/ISkoQFG4YOYwjHmuW0xRkpXL+3y +DPiwzNWTsh088RvIfl7ka96SCft3cPSW4Xj4dnKGqlfFpILbxL7tCUc+cNZ1vl59 +fmWowf6r++oQzdGNCwC3PHYSSYPp/nLLPQ8bdOD7znW3h0/lxpLXdzevANxDt6Fe +efI5V6Qput3fH857O6KfcA== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +sJoun9hXsaBjoXd5vq4p0WrRiBOmYRz7dLZcqHre9vcVYQPlTOAqH0akQ6/PLAvo +b9EUQM/9bTYotLNHFDMfXIxqXF7xhnq3mOzPkpjLwLd10+G18u3FajkaV7bI0IAW +oAt4VExdspy9hXF3QLCwQvl+uXjg6B9tfkQ9lRE9Lt8c2s17Xx07Kvbp1zl7vyZg +jIzh1M8YJu5XWmIzLuCFgslf9Kr91eatrzMfWF2L1/8ZSvGiwK0dx68laecFUI5B +EnV0j0+orVdTEn15qN5+MomveXhwUi6euoryiKOhEuwxQPwJgWJdLJFjc2PGdHKK +NsgFLAx5GqkU+UrV2n2SXQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 448 ) +`pragma protect data_block +VQEpSYyrqyMy0d6e5MIzq762bzEojUES6yynx1aA5YDeKe6T5+dbMqPYRoy2ZpgY +1pDSzeqP4kI9eLLRgGkBdiK45om6VD11yNVwjrQMTGqbPqFazzhwUBUoSB7JwcAD +uC1FXbWkLYXBlKP+jolNB7dno1fTrg9L/nOmBI1I8OVyjmP4bvnXN45GNXRtvVMX +y0zkEfl9r7gQWPbQ4ywNu1WiReEE9uKWaSlhmunbfKrHkR+WQoexuhfV8DZ0hZyQ +MVmGaG4hL0IiKUoIKKwz/5nkAFBSQg9XQgwniu/4pwNJbvB2ps4oRE+CkkabddOd +REXQ3xbluJgS/j9unThBmb1sg08axrYBcQT5C9BQTNxLnKH3jAJtkhB32EUR7K8Y +VFSV9qT4ZiPutIB+jlDZKcQXzDvwTKs2/UovSgdwdL0fDYh8N6iTXamqVKfKR41O +IrzRJLOlQ7Zb4WUDyft5RB/ZA77Gaeeo8xXAfHgbLIe4KM8m05Mx3dOixwdPKOf4 +Iivkxru9/M6xHtIkk7Sb3gYK6gcWfW5av9qpewcpb9BqBDlFGVg8BqlxkhxKymHd +rzVfVgBqmYYmXoH399QOsQ== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +h07AONsTLlxUVOuPlT8XRZHZulcIPjI5IlCVE57voQcoylYjcYlec6S5UHg4gef0 +KagslBKEtX4SBcosPVrVrw3xKbkRoW2OrahVzxsru597XKu7PRdb8MZ96PsJavzN +tdgLf54Xf5Ya8oqvlMrbmHSj+vVnFC+AqKvIp7XrFpYla22SC4RENMPZltjegEZu +vLTTClkxA4XzNVJjS+RNXjMnUscfzBmMKXRWZ9QFgA4yEJ5BZidIbatzYW3aLyXs ++jIeuJjAO35ZhJozFu/FkqDptxBpy8zvkLY3GpiwNCnetBHMPm5/Yyc5c1525c/g +ako3dDZN6Kobgs5dVRe0xQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 6192 ) +`pragma protect data_block +yd2FI2Caiow0cA4NVeMtmNji6mCZ2DlqmPPmHPTwsBJo74MHmwyaSsyNBlIJjNam +ZjzFUH+NJiCMsSXTNDwZEH2DYBfHPwDl0oJC4sQqQLvtwogCii5PUuVNLTjyjepV +fbgcxwhRRjJMATFd/bxevj4hmAjLXAdS2gz4roHKI28y2+oTivT4sgyWcp3rTJK4 +B7QBbnslto4/rAMSb42yAHRdB2dczjEnG1m7UQ0Zw0FxyIQAr6OslFbG+zQU16zb +dDA8+OovMqzJfxmb58Y8q2kraIScEWYdvRyxsZQVYgd8cAn+heR5G9GZ1+kWD2+y +YdjDUsGSmgjuAwRXdsPvOy68BjDnBDvgdtluLdGU6EheeoYQl74ghaLXGdkWPmRX +xS8VQzx4ZuPDdf9Fokl12gflQjACt/P19jSLW6oJIxhvsQ4snMVNXxB8Z4AR4P3Y +ZXQ9BHl3oDTdP7n3PXBtAx7+HhIpWyL20QSechD8qImEMPoRpkuYz5TjDc3brNpf +SHhhfut5AoKAg1J+Ob1jQ/d8kv6iggfVPC+Ej/zp3d9J352UPytNw4PwDkec4Ey8 +BcP78D+iGNepH/E4KBP1Do7iMixyb/w8vD4l4SiYBBufbTwz4VrgOsnuF8kzFG/Z +/JofsNpWECXLkrMremvtlkZdxEk9p3wd4Kuf7iT7xrwFQz2KrIGBro0SGGa9NxJs +5ElS2oUvXIR+J9VXHfEhD5FVH8/Z7GJLOWVIGY/K96z/i0etunV848fQleVK/Ezb +omCurOi2Qx0jW+febzCtMiUUhbpI0kWnN4leE3OBEprQmlUspoq2TyysHqBEKFJQ +rSleCMSHfyNkWyJB9YPTrRmu/ayPwjZ/zxTzgnZt5z5BzL/ztakmQZoCU8MhyBpi +BhEKppuqu+xLgcoU3tUz9bxV1+vx3nicWUOVROVk0T6L6odzeXZ5YQPD525edSgO +IwFhLU1Sw9XOBiPZ7yA7PmzBb73pqaRzHtRMRMkTpBQqGsg7FUcG6kKV389M8Fwo +QQ8KyEiM+MSHlGPe0MVONS+5/lVHmsXx3RqGztwMC3eG0kWtccP6cOAMHLS481yM +xTwot7erY7oHGnvfKVA3VZUd615ZlPYd65SZ4KIYKDW2QcvpEjrhcntsIJIzDdq7 +ChsQ9qV2hSxJ2nQxrr0HyF3sU2wL9wOQqrbCkyGgNk742bbDQh22qvtzY7yPgPG6 +XkwS6a2g+Vlr/Gb0p0CPrVRUimHNAdwxCgzj0Imi0ddmQINJWQyG6lDixGmkiib+ +cecH6lR2YNIsxLE56Umnonlp6g/Zq13x04yIm5F6TEXweFZE9EYD/cLwfAviWgka +1cL92gENSy+CFZ+VZb7h8nESYSFKrGeUFIHlh0Shhc/D6RAXiBmjpWqNnuRPhhig +Ce1VFqqTslB0joqBP1IlOT8ZdQhSzzyGdHvHdO17MS/b5BpbFB1ocnW+Q6cHUH6Y +eZOQQCUzzE/7JZr7J7mPtC8y/Y1mHPt1Tls65bmNPtztvajvaQcaW/w+NVaaW/HF +X5q5hZsQ2ONPCQnrD0ZyQShCOsPeIwd3KNu0LjnZQRrfsv4jwLkI01x0k9txuokE +/IWuKn8OefP+l9t5g1EnnyKOl4fCBVOZ3j6lRFlgM7NBfpSiSW6JpHEeGRt1Qzg2 +HDP+eakvnBSFFeEdqvX5gX8DU8ouf7jGZ6SKTdtyXSKghPfteQkEpQpYf6Sv5l1+ +r7NISxX5gLD+CaocDH10c06qC+HkL57Unt4fYali8Xzkp796HG1Rc+80fdk8PhsD +P+gP9kLTmZk+IlpOVUfNecb56lb0fWntSgChb99r3GWUojvcDhYbn0Pqy715jTqi +CvL2byXx1hRL6XaDgH2UBffAiadTQdwXwOHh9WrwCMtViBJbz3K4UvExA5N5WKHs +y4bc/BYI9xjuUdU8fAXsoxAs37aqhdhGh+0CuPHgv2nu1ZJQndRcD1mIkJfUo5YO +MDErfoHbeMnCaQmRAky7tDCAKJUcO5X7bSf7O72/7KWl9u4vGz2kr5p44Rhph3w8 +Qk6xzzBm0kv2hxLgYKNm9IaDU+GyhMVmtBaxbsVZtmtGx4nBGeeYuP3qLBRwCYJS +1LoTNuFKEV4DAcqDM58MqVQayv+EUv8dNJ1c6/i4+qCmhynfqSCkXpaiL/CuXPIV +qPHOCwJvhlnqEolGYz7Q6wAzvZa2RJBJVZc1571e7txzAsJr1KC0vfyZ38V7itRT ++jV8pwko9v3LBmJcYw2q1xdRD9ZIVSysXsCH53ajTyacOUWWO47bABQloPFALiei +/UBgzSmiRlZItPhFv2kyo55KatIo4NrEPNDvRBI7Y+ynrswdf81rFt4FMNNrYeRk +Wd4Bmr9x4Z4I3/MNHUhIekQkHo4Qpu5UO7a/0MUmNje0qkQpLabR0y8lGXEpGKav +NnKk+wFnWne31KeGOrMKyYUj9kgEctqbtxICvAbz5ZgUU+dWSQpsENNPguiyQ55I +BJaNyvb3H1L/x5m5Ddu9NTx4F6MkzfnHeSx96tcf+PAuy7tr+UQ96WXvMBIiP2wb +fGAsvKvkzrEFSDQQeNfGZclxXZpzn17LIL+Cf8ibE8v5KPipCc1QmEAmD0p/FnM1 +Nl5kE34bKdorUESRTIviv86LsVYwIGABjs2GaGp0PAZFwueiquEZfAjeuVa9Yu8X +YbMVgQhtt5uX9T1CypGzViGQ1dgJeUJvAtmHQRpXUso21u1/VjFSzS5AuuPSzqR1 +idCJdACgOz4+ohmjZrfsxE6FVkA15HwWMRhzCiASuEkvVYWqBWiSOFlgpyc2Q6xY +FBV57InZMKgfA94fvy8u3ng4FpSMf+B57uUxhT22hJBYXnQfFgP+O/HjNs5Zm/In +jszqu1Ov6FKOn73kD/9VmJq5R3IRmpfI15A5vOT8FEizK+I0xEYDeBwl0u0GB+Bu +h+6x9C+N3rzfKx0V+jFCeIASUAp288Gw8VkfCG6nPDXGa9FKVWMCdtmsI5Zpw7Da +DykSehy5/wWjMJhEqVVhffywM7yYSWTvboSatwjo9MIN6Yp64ZZ3gNTeFULVBC07 +wecKiwI/dADhRuHOqO5todr09rmJa7sTZuE41NyZP2YirygMYUNoCqNYpi6Hc2x8 +yl5ClX6VctXAG/WDT7hIG/9xRdHhzn88nbX1nTpJjMsir/quW1Re2IEYwOKGiQMV +pXM0rGpz9Yzro+BzpNfcXnT3O1XwxSY/gdfggqIE4dFajeLLGjpo8bwYiDlwXoJR +FLN0p9AoQfVn5sPM2rz/5Zvu6th+iGkzBlEgxpGCa4GsTPb/eyMLyFgHxf+Te82e +M7xBSYCJ+LMHZqNk+f4SJLKFlESxRSaKBX8IQ5XSvQZRQvGFIIpMWsj3XOVU9VlJ +txElj5yqRT8Dpd5gXI7mUY96XWz2a6H8/aae0Lo4w8ktC3l+H/rCiUX4z/FtUBCA +GkBAYHfiIQIOavA/uIDZgxhw/1NoD61CzaPGo0a8J09mBrqMXcA9Abp7p9P4G3CN +a0Q4Kc22dUsguDp3+5EDf78wf+LNY/vV/Yz6XcumD3NAqIopiInI4CbbhWXjhzI2 +hDPCYn5BwTvw6qK/jS69gPabGgKD4yLfclkDSJyJtrmMtsLNvalbCrLHl35fxW8Y +diwn8BlsZl3vaSC7tP49u1fLWfDDfRT3q5AsIaG7m0ni8PtAfV5p+qPNC1HEMYEx +VTRHQIchPPpmHWndswtaPaRhVsq5oXlTqXqFMZyH3DJFHV88b10XNFr+tUgSoaXS +EnJioPySUrlY+gsywfTf+YwAWKVfj96uczYhZ2LZasItw48tFhoqq9AGN80OXfBf +xAjFcZM3IRZ7nuUZ52/nNv3jVM4dVYMAER7n6foPUrD67iJfcfSjoAicJGxRWO0k +5bGbMWpQY8O7FAgzd0hePBXSfdxW+h6cCQVaUIWotlnkEf5Rcte3envm4AgxQxLT +JYAUxeEmtuPru1QPyzeQmOxyCOP+ioX0vTwdA/StEFvfBnqVZGlt/KrLcnl5X0de +tptU8WjT+jJdrgMPUnTQudWdDL1Z41uzNJxUZwyXBZDjPczNhTyyITyDr17KjrLR +ZLhBBNNeiOm1gCubvtLNRzNE2H3QhoAgROVsVDfXmQzAhgrpSc0kWpf5CT2rAE++ +H4F7FdBLYRh8pMMlN3hC3dcafetmjUeg11T1sF6uhH9jJvcNNCazv87yRZBBfdHF +0sElRkbw2qKK6TZVGaGGxlKl+kP6I9bQG2HrllEpVu7250d3EVcv6T+UA50bC9iG +xDwUO0pD3H2MCr6nVJpgTvuxaxK9ktpJHAjc0H9Wd7879vjm25gjLcwJ4Iuuu259 +KZ1139mc2U16acN1WKXxAe+iSmKqEJYdlA353nknd0ygsXZ8v5qCs9kAewyJdKMa +yjKNbEzu1vT8bJ72WoN7LQdlRGJXND7D7EpoYUiPcXFEgCf0eMsJshxnwwWJHvmJ +Fp87i55hnvV/wT0rwlNeYJEfn6N/DLZE34Qg+EA/bURZCB+WezRQLVvlg7OVZTqz +RZO/0Zlf/FmIU2rwqvt+i8DOW7Mip9/96kLGN6/SHktROJjp+d9rcFai27TbWAUl +EA85l7UYshc/hJLXtwOi0eDNuaOuIAJvvUz3q2p7b2kcOoKR3b/CMi5x4e8+2n8t +QJjCnXpJS74iHqbAj6VfdJqOEgGHYX7AOh6d7pB7u3Si+N6YpRZ4tk3g8DQtQfqf +gn3SQ4JvYU3Xk29COJbd3AzXk7UGP3N/yLtUzlhHIwCLBS9b9+/A5SKd36S4+FVY +CXk5QZM6E3bbSx35IycaqXNpy2/5FwvURmpUTEXE8XjYjUKC7R9rvGgN04p8NsEF +sM8jEcC3Yh0RO1Tno5f5kPT8o9Z5p0n72hCHZ6IeLOY7iZCAxbItM9K2k+LyerXE +mxQRMOyyEDpJdS73W7I9R9/EfwWL3pyh6psTDPTXJwR/zeDL3ich7oUeQjauriKI +BrXhzTjIDBhd/ByAe9hhT/99E/2Hq9NQfLKnXsEULpVOeI5k3COrk0ylaCIa2nUQ +wGJ9WtNUZs3aecQ3ixLUI+O7hONdzezNoXyH4zQYSKZUOQWkHY7C9xSVOIUHltQG +PTJbvf5VUr+7FXw5JgO9ietdCo4Dts6AoNxycFYFF9Q333YrKfTr+FXnpvroG3h+ +0HuckiiPuHzSMIzyaJvtIgcO+3YJU/nv7GTjpOtRXU1GPxvkmXIwku+3QnqDh87N +7GNGo3H8AHNHqqee3zpcT2ELzldVoaNbKy1wg364KvtchS1Js8WLYvu1ICjsenVf +ONBh0ds72HWgA+dH+oBayB+UY6/huBCRE5PGzqsEloLhPlXX8xVby4XBndgcS9uZ +KJEC9djwirA7uo1bqmU9lNelyc4X2nuftIu4L4D8Z03iXlGf+pGd1V1b+V+vO92G +//QsCxFh6CyJ+U7YlWMjdhy1YgT0GSUAOiK9OpO0spVwnusZnCCMXWmhAxYKO4Ra +cuca1INjX3dWS5cZDpZG8Td1jmDjLgI4Oz9s7RYFSB0BpAWMEodDJSKeRS+kZW2s +Q4Wk1MicXQAGy8CQfBZKCw7qP1SJGCM6pdjtdhD4oUuLTiDO3ri0TL275MVeWCMN +DH9zFN6j61cKctyjUp0dJKAgFVWO9a9fVEaPvBbTqc2h9LJHjL20rxaMcxDbjzzI +Tjgog+VtlWdpm2RXnqf1bxRxvTxKB8e35A/UptqxPkpxlcamlayuyMs42ZJP/JOT +owrFvE5RyACmZ/i88VoNFoqlhb27W9F/zLBZCYOToIFn/gRXigakXHJDY3+9XaSR +AYZWXWQ2z4U3hBR28TW7FK7GzBhMvvoR5fYx5xvHzAiZA5iEfOlKooku4gk+cOuZ +OGVXI7NsXDwiZVJTvDlfmFSoyS0lHGgaNBXgf60uTJU6qXEX7nvsP/ksFuump71a +B9LxjMi7+HRQyhcel1la4bBKDdVwwa5YWFpXtSydxmmxW9R9UnbOR522z+/y+tjK +3uLZpjYATBWwLtaLFQuGosmzZ4bWAo1Q66h+VVHVRn+cguhdqU6m/7Ui2p/6o4Xi +p7Pu8ynJFZGk9MTdBb2Vgv+4c22DqJKwyKNfT7mybBavcYMz37l097Q37G3zkYSO +U0S9ZUcDYG9uEQQFojecpG4nG0E+OET8Kr1Al1Mdnao/js5X5GEJnkR2+DKs5XRY +3lQcsKt+gFGM0xymZ/hCB7O8dlwZosCx4K1Il6JBBhWij+IuKEB7/iADzvt2Q7WQ +jyuPJTV3R7X6Ep8bjpeKIWVIuJd8jb7YVa3yJw4OyOWVGirrjATtWvaBNsExmfHP +at9v22Kw5i36PplcNFpO8qPqbc+Xlepq4Hh6NKL49TMyZWE3tt95YEVLwHZcsFgo +daZRmfI87Z8ixt5M2DDTqoKvVJQ+I/atKfbGytImDT1r5y3SZ96hCZApmpx+LBwh +Re/MZ7Ums7sj66B3NkR3NQHhewAUdCk0ExE9Q2XlrDPGlTQ4KBlxp/SiQgkuydp7 +4ByoelqcB2OoGwub4N4rH/geQufxBITKrTPWRxerNrNN/ruNoJOzVxL++54C/1eF +42arGQOJuxPBucNs2rtTJ8RN/KXoBGAn+hbP0mo7avYFskpwTCYoCvqzSOgFlHRT +HLH6eNHMNt2b5rh1MgbNwxIgJdaUwYWoXtqMuexyt7jg3cNONWKecCg/pB8iGfWw +bnk/jfYEUNA+gkYO3mVYkpowFOe4aTww79PcelDiBC9ImKYkpc5x56GXT7ZdNyzE +19VcPv3o+zmyHFGvYpZ1dqhahfpx0Iy8WIygUmwRiI4SaIogrFmVOJ0KrMEKT/ro +FIuiP3pJa9bxGzqJK6J1I3ZLb0W69Z7mux16Txve15EeJAQAFWJHMSPGx5mCabDF +jDbfRI8+N806DhQInT9kVB0nIpioXUQ1CEmfJUQPp4sUP9P8G8Tti6BjAAdd4254 +TTcj5zacai07NV2ZKkcMVkhDc4udjZtR6dZKnZRwpW4y4yQbiJkOPlefIPL2USat +hPT7ivxbRSbwWvaIKowdtyHCOsvPbi1YjH/4qtBEfmIvyNDZ4i+Q4OZ38lzv3A9l +9MIjgseW0BicKT/kYcFsnlqCXj3/brHXpyxSRtnCfZH3K88IbJqzPeWGB7PmfacL +5Dsoz7KIRan9HGk/7n7Ra8it6G0QY7TR4Zwdaf0MKikmVNQm05yqaBh3Za4SWw/f +JvyCjQC3ZOJmB/E87c8Zj8u+4kcOqmiu72l/Q7ByGOy9YTL0sPy5o9tSfBeo0Guy +KaXzCqQ7EGnuLiweWpvTu1T/+xO8WxaGtXGrBdmHHPoVp/ywS1dZojFqjS/4cR/k +R4P2JpBEtFSmIgE75tqNUtqkNt9YB1wL+beaLbuTHaVAJ1f1JpvSwb8kZqeX0VVz +P88QxG9bxvbINS1nih4/An8pvVY2Dzh0zLoGiT34OhcRQJN4dljpp7jWugPBgoge +TWXRFJls12fTzD+LPujkvT9w0GdygT7mQgKeCSgdWVMQNoTyujDtdgbqoTj8fiPq +sfHrvQ6gzvMmatSH4JLTAJwdiWPTzOFhbVRAm6Ld24aE/69BI6vYQw4XwjdZXU5q +lFwrhgE0HutDyxN9VyzpD1Yp+Q0oDSxFVh3oeaC8ctCZG/rPQts80ZTPa7ed5qIp +gbDdU4d5/FnLjTx/b8653kWA2Y8737HDsSzldoQJJLVQpZxS+VaBxs69zeea85KF +rV9wzk/KdTDVtezT4c90rtLVAwVIwx1AZoaVxAlKuwCMscuLUPdAIojmj7dy8Zgd +t+9T0d1u4QTBIB6yveNxHxsUzQCWWxV+kdL98sjySruydTFQxOe8itZJpfSlGmjm +XxaoLdHgkgesr5NNfkvSulOC1O7UUiABBs80jmgSm0WEXZf3NPUM0/t79GFf80mB +DrEMzVp5MEW9JNFPz62cqg/dZeuqkhu1tlDxt5FXVENWpsGkFFKDqotrTtvKLWpi +xwYocWFwlbeiOxhQIBWtf+zybdUne2eArKuabD+Z6pLXOhlGdOYxr19Vn1TkY892 +CJyQEhCjhBKx+n0p1/OFU84A1oLRKh3mXTM5lFqmnRtVlFQVyY7Bf61gLIvQarol +0+egWv/oaHFSjkLpkTCNswC1HGgrMSu4jIJtkYmadfts3m4WKf9uk2UQcjQSiT1v +qCTsslHzAQzSFb62OkA61cWbbjFAscy85+7gNBackN9bSl4K+r9rZUXCZDZSUKB6 +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +SF6jRX5MbN1KbFm1wuYk5J3Ovoq4vxkJqESI6Lrz2iEvnMS6GgkGXQXWjHgiisJ7 +yeAGiWNDQuLR6MWZCgtUohyFVU5eVKvERRAf9nVBSJBjfh09WftAIdSadBWiV5fx +fxFuUL6SPamPNpCdkO2W2FOSvEEMSqyOalaIk65mCV4mOJyRYzm96tMhjOizDFlt +4AxCGA0kys+jln4Q5Dpo2Zsu5AbVIIDlHF6kqtCRkH4DLpbo2ByxXzHHXZvTdpbT +X92OXbfcUawSFeXO6LqrcEOuVN+X8nzaArA+w+nL5rWhNDZN/nCqvwPNE7I5nukd +Ei2KoM+M5Wo95QuqKU74Aw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1152 ) +`pragma protect data_block +FVnbUs5RJWbO4aJIvIqCuSa9rRE3WgP2KsRWQvunl5MVjQ6us8TfajzoDBQQlXOr +UrzPRf8jcH5Ge3JHkIIQFf7+TuupWW/oi338I4wB5u+kxkF7Cv2BQf3+5J5xF3xj +ZKlAxC2BLIojcgSliK+kpNl/TFnhg2A4dVB2uq+Me1YS11Py8fPTSxEAOgl05QoB +cjIH5OJO9lr25DDpttC0lhvM8AKmBiGT23mG63iyQfhgEfIrL06z4zjw2unfA5sJ +kkj0TbaZy78ZtXVm6yTZdfRPbph+eEJUOCZLMR11MSTTJlGV1VfOpIPYD7sRCt3T +7HmUapmMGJ8KEc+0cYi0o3COUuk1HFyfsVdExdwY5UVCGQUpFPQFLoqvQLHwvJ/7 +m1enhwlroWnEsCvBs49VNb9BaWwvIaH3E1jT4HcKS+xuhD5/B5PJWvJBZP41ssmu +d/ysmQfO5QYWX3rZMek2SJxdriT5qSY9I8N6CPS88wOMes6VkC+yVXr8XkvKZRxB +/y56JNCZbpGUEFF7gp0IC9BaP8qdM5XNdkuwARFNnvwp4bij1bErdk1EoWE/bmFY +8ZjiuSDr7rqiAwCr07Ydj7nwbOiUpudG6qqkKLbvu777qKFmOhq/jOJWwo1ja2CO +VUQERDaqwiEbJPVWPEBC1mrYPhQWC2jdYXPCeVc/dSTlFqsCxBgWlu8fy1Hk0Jm4 +l0CBQXF2Lckg00cNysHM8LLCSmlKNqn6wXqjeBKwUr71m9lVtusx+vsDg9hE0iRv +xles3Nl7I87JpNocis56zGYEwJSXj5GWfDLdAFx32OArPZHZgZa9F8vMQO4VyUV9 +JyJRXBdmNVZKghOrrlUksPSlSEs2ZIuSqTd3yxrC16AujHfCBQgCyI0KHJL43h5M +R3l19pU/NAxT76ypQ0jmrwIMVDpDOTZEZMOQDrERzDpOHSQ80GJsWE42RazSfYai +1NbWS1yphkXvCsEdpm939DfRxArZ/wIjvuigZinHajDfEFgM0WFNRW6dVpTuLcOf +r46q7tg30WFEVPivojMOjto2Eb/nd/GRC4bcVR3If+dvU+hHufAcpRPMShC/zwwL +IUPXp+dKFRiOQ8kTitir2lfE9M9a37ioZZK8hzHuFjueugspI0P2Fs0d4vxxlPmH +61TVmLcYmDQpsXnTGHSQNTm6qF6s13pFUcZw3aY1lNNN+sn38RxrD3bGjcxyvJ40 +qobwiHhATqS8/j7JM1kdFqOPnNX29xTA0kYMvYie1TLmzKqeFM5R1xB9TqlIPzyz +aCGNEN1fDnvVQkrM0ZP8tmG8q7iPXXvrvh6clLe8f/aYdo2T5TSww/hSnb6325pM +j2FRgBYVrchFb9aBCmGGoDvc1A/7Nc6+wNRpps/wDvGcUN41TPyZIRmEAoluwwpn +MvcESNGKGoB+gFwd1SdsreIwTo6uPiT4QlgdbbQ6RwYYeSZIWOZBo9NkhK6ebLSU +il0NYDxK8g2uEMRnQefBxfshN9xuIiy1eKgef0JCKvvnWdU50dLd3y2HcMzCcfUl +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +aolNkchrHQdmf62Vo9Z1dgP0MtOYoRaBWW72TEEQ6JVJYPWBBRjaO8khH/Z8oasr +nAt/W+xy88PFXSJezzJXyWx65EvvU8/+aXYHwr5KugLXmFdBQoWoFUb+DwN8muhK +Ikytq2rL9li9q4mNyW32tSsKIPcqi0v4Zf9+wgrklH/XUtBmycjvls+noGdRVa+G +t06I+WZ4Rmdx6Bl74XCV29VQUj8i1xc4Q6zBymcQrCQOhc9uP0gYGbk4pyEHO7OJ +FBfq42AexS2wgmTmdEX64M3Tw0ILbqaLd3YHTgwKlUyDsmfaEbaK1UqBS9/f3XWP +pRjsuHm1RjnY5XhVBsZyFQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 8208 ) +`pragma protect data_block +a6jx+jJhdxnW3Rpu82IhCtDN4rDxnSi+pHcMIhINP07QeDUC9DUcLE6W0WFxSABB +5XUGcvygT/fw2CJ9AEHWJboQgJeDHPw8crtL1RYsVuZ9Rj8dgjyEnDtosOOr7OSw +I+vfCDj2VS9cKPQi5kKVmD3tWASnyoFQ+JqHYXUG1I+DjYe/uNkcqCkuMTWuK7IT +8uGwvjOudEeChmB5fZTnGzsTQOIc5O2ItC70qi/nqsckaaC4RZs6L2Tkio/RCAyz +lKVfc/qt3bWdLS2xX26JYhTA8xU+eivyiLCC/L6Z56sCxYsy6K7IiqpbzPvEUxW7 +djKHx+uHS5uI7KNfyz65sCTM52fgslMIW8DfWCnOtm7Lz1Gea9KSmWicTa2Dm3nE +L93ECevgSqtJ2adeZvDpT5FM+zvxJ+7R4JqNm4wJIdiWQh21RjDGmMqD8w4CXIOR +dHfRD8VzkvgwL4/klUhx1KJyNwdXvpDlBXVMQSOV28soe5vKgyDlQ8I1FWRrhSKy +4VMl95/IGIaiTEG7pSDXraBL7fmRCsc+uMwJ23FpshTRl+gXiaVbenOUbw1wNi6k +00c7OnimqNpdWV1N7sOII/ASqr/ssrA2o9iD6DohPe/tJRaSQhfMIgWYODfi5pli +63nGU7QkmjwgSMGJgDz1eqpIeFkeQkc/DJuUUVoSl0jKbAsHnhi0zkggd4zSluXv +/dAi7owo0O3jY0o9oHXcC5+czZMTDuhe+Ll8/kDCSAgpPAbzgCBvKIM0ScIa5Nsa +IZ73XXmMYy4pjy0UCLxb+PEbTxv+9bq7PqjwCrc7K3GvhQBfU4Hp2pOQ480d+NI0 +xGxuI47HyO7g9MfK1LYk4zIQdhxQvpSHRuT7sBkavw4vR1AmsDWDc0Wyu80rIDEk +jJhtoRQ3ffVVd1XH35TzoautGcjQnG0rADBIUQ/G4oYJ9cOQtr13aW8AhaMeGTji +xhefzJrKmytE11iuqRW0UdbW0EtN65ZcR1yPiVFAx9g/ub+myXAtWoJk5Z7AwORV +bGaenqvG+hhzwSYWuRSgW0GL/eGaEQVk1reL2CEoudQSsdFJOrAnhB0Vhi/5ORZF +rWVIA8JKZi6s1/Exv3xAY0vbqv+U8TLdikMzLNKXJyKZkdE4l+xv6L+rRcdWrikL +e+hwjtTXtAwdPXLqKY9Jx0IumoCc5Xif+nzZUicPCAC7mT8e3ZTmFU+CCzW5TU/J +Wk9wkXx9GTrErRaNHiittI56u6JAbiXfiaMQsnFeBpvNwm6c51PLBloBw5FKnzwf +51AowX+bzePTVo5WxnWupkJceJmbvcCWEDB+SvpqO6HHALIDJBMxwporDR7FUmUt +iPqwC2kP/AoSNeWu3SAB+vj1yUHCcS2tQKHU30z9osUDpjp78W26+L4bAu6/nzoc +v8YRDydcU9TJMn3T/XJUV4u5/iNxzxhxrfifOQM7HA5yFXByMOfObr1KBp6+7Cbw +tUOS0+ZT0/4YXfe2IkHw058lvwqiinoS40m5LqTg8C8DPBW5iIu0bCRtIw4tT65c +IBlYa2OUUr+ZoDFIUp/81uOy9r/9XaHkOW1yk0DY1yBzBD+WIs6c3viMIEJCGeNx +lXTozsi8AR1BwPN/aJKld6ImZ/Wni12BT+XLVX3VcMFzNlbDMQJxHyLSUIDbnQ/n +PhX1U4jlgaIJUcEvf1NSrhQCjUSZSuEmqdz9Y8K7AN/jgmbvY2cMZtX3GFluPMV1 +4PHGb2DvfKf6j9im7nTDzyXBQN3RgJfBhL2cG4bl3D9AD9DThd8WdaCpe8NdY/l+ +oqRPJxYyUytrI/oqeImFbvlZ6wfiFepfsVvIB0HB6oHkpNeRoK7Nri8D37BNT0JD +sJ6mjpUbLQhWg8A9HwGz6+eXQTMfwJLT+fSMqAP7mMNWPHdIkiPt3UM9FS4gjiPG +GJUCclBwSNc4gETpqttiQqVqESLACr0JjG+ABhdtPf4VOCqeMJNfw1eEqrOOB6ub +qD2RrSQdM4sCyl9RPDn6Rv6VwaA5Q1+h3Tjw2Wwb58vbuXA31G+tbpwq/yH/fRdk +fg0PzwFf4Q8rDlsGxB/ys3n3OlkFYSIe4UzE04E0xbZ/G9BBEo7cPHaYLUGSQEk7 +dXDahpHOGhsci0INwxcLcFZQGdzZttmTZ7b+8vI1tGfUpHJ6bTFH1Pj43fDTRnns +z1IjCTAoRxPxxlDaLULEKIk/DGvK+QIUTa90TI/0/YUBBeQQ89XfQW4rq3JPPvDn +ZtptepRR8Z90ZnSOu0GfLrcgwdFvDwI8U0aggL6QHN6U0L4SM2G6PnirA+I5EOul +BrObk00XeBgZi6KSVXKjzM1hgDTDUy+eGRWvs9CkdpoqQTjF8L1ty9r93/R813aT +fz2VBCIIiNAJRL+AtWgzP10DIjV5Y5Wv+Nh7uNKcPjGbNsUxjpa0lMVfY/ufRt+N +FzayVe3kFKJVL7wJo8qcGYPwiKLeHhQnoDXCiaLY8OrMNwa9PHwNEpVbQo3+sx7V +zAb9/iQZMwNE44zPuTTn9Wi3t+L7QOYjtmSp0BUwXYhSnN4xvx7MqOuahOfbE3wU +lUQnclDXE+jppTX76MXde2nrrAUqrohOzRuvyIoKXH8VRGBKEIxnQ7Ygih82rJRZ +HMumWxzM/MNA5xiwQngj/wRardgZXE7I0Tkj12aT5RJ5eJt4Q6EPUGWcAnIz3Gbc +AHTUtwfBZgCVyJsuLNGbtCSEtoescE0x07rpMKBKjkqUBtLSsidtFB3WIvscbC5X +7MTLyKz+oEBOk51hmNM5JxmE4FSyv7W6X7qvK9SFs0mE3AINMyz5TLYjvHCJA3ft +3wRQJi8dxhaa34T4HknULuskQKuyLmz53exbqOn0tymPMyWTB61NtwOc8QWwyYkQ +qshWLcES9R/gvhcetNcXqeZ6QzowJ3E5ZJ5jX7eySA4Fv7LypAZ2RDamigDo3/iD +zEZNtj2B2TOKkxvt5XcjgitUFNEn84lG5cTnHwSaj95zCuYXdKG3GWgA0uZCQQ5j +0jwZrf/0nu4itKkphNrIoO4JDsD8Ndvmfsi9q4o53WzCsA6dTJXc2Qrq3YjD1O5P +NZlHESreoj8NOiPmkMInfUpF+Q5X8mDCycf7S8kjsu6Wp0Nz6ubLbiITg8ZFvagY +d7+Ct1H6CXJCJXMzt8gbHWvOLoy/Y1O3kBMRJXpBrh8/93NRxLMO/QBeJQkAZbbL +ycunLYbcUCG4qCWjWivcmjyEWryNBBlusWGEog/lVgeZPSBKy+B97VolIjeEkGkh +/J2ouWpqe0pEACiNyFZObsTtdr3D3hASIJhuJl/NOdN1HXIyOaUc5bgTIz9DUAP1 +0HQ70JdCNTdeMrXZFGmH+yrAN67K4d66p6tD4p8mbjZQB5xIHJ+u9PwR/po23+ru +3Mrg1cDdgeW+JkA4St+VYegwVVXiblZ95Zgl/nxS5Nwa+duUs+Rfvo9J+Xj4xygx +4GtNvBSxAK7v4nAOsWrFnZ6BnIos2RcbBZGZ8SC6NnQurtQ3yK3gUIG5FSJxhsfg +lDz0V1/DXe8J/5NqqWJCNVji++Z738NW6r69GPgQy+lHjZfx2DJzSVwHzwVnrdII +Lgv/s3iwZqw00lxXTyU78VLeWHJJ88A114ym+0uw0J3MU24O7bveHQF3OYN+pfgB +Tr1tkHmE8AE6oXTqtVcHr9wLvaDmc2m1R/K2jXCrP0zwHslr4wO+8ckiq27bS5NB +9lh7nS+BWeNh5FRi4s34Hsxur5xY2wS6NbYI6hqXwQWUO/HIe/LpQzaCwmv3aMJR +D6p9wYWvLNy40e3ENJTvsqEeOHA3R0NputuCpP4DoxHdCT5f0czRvr3aoJzzCE6Z +wtygIUd16rdPnRiFNip8Xvu+GxgaW982jD3r6ug8hsLERioUqagEcRxAB9Tr9Ety +PXtupnyynKSPH1GnXlv+6bUheDWZzHp5FSCcjAdOzqtIg8SDCoK6QO9qGZQb8WAp +K4lo4HCQ7+ZIl4O/TKKYXvsyiNxDU36m/RSrIR42EBQ1EP7hlY/mHYEv4YE23bnl +LZ9plpJ6ULQfGYY6eG8tMV2hLNXrmeebRMDfdhDkRC1q081vCgby06PJuHylk6na +mWjeETluEPxaq8Bjtnp7BRq3Feks2vgMl9UHQ65Zj1RYDI1H6XfcpzlxyYTj7DUR +23K2pLSuT3a014DhH/wAa9iYRPXGHFvweIrsl4Z3d51/aIX+6MJ/0Th7HsInlYlz +dVNjsWoipSB806OBS1xY0gMxxdeOCm/EVocGRNPiITEPco3nqkDkql4fciVt166U +JBtnkR86lzc4NtORF8AUbOWzTv6q+S1a762rPI+Uc2npjqEakafenbtfmZlwtBYP +WitHo+pltbOW5Z3o+7Uu/PwiBjffeHE7qux+fXHYR5L7WluBaTY6LsUjXW5YtxI0 +1HREwjZv4Jxl/P3TEAXEtOZSE2Q/gjk3lNsLHJQJ6UE0RUVKI5TTci9L8mr0Aoh9 +ocg+VmUVbRV9iTH+W5olkuopd4uoWm29GXvWZ1oNYhPTv/rnbDETNkSOBrP5Q+UK +OqtISfKXVwDEHQJSD0QAWLhgJHLYaXb14xh+DbNRzKRqpoZa/9+IqFqSNtDkDrpa +hEedgQFKZyQFvoHypH0WJEXyED7IgQuHoyXoHvGVdEMlmRvGC5g3qYtfY18yvvW9 +n3g3s7pI6rXlTzaNNS6b5xMBZyZV4CIky0W26YPzoqzMkCYVsjVLtUg71dxLKief +tTnFS0wSFCHhZOPUu8EPSCp23a9zzZr6PiMf0ueTjAfS7ugcB7W29JtilRfnobuE +rrr52iXlDuRutzSB06WEvMWZFvNjrw/fUudcXQjCyn7JZta7BmNBZh0qYEmeAITP +e6LpNr6MVtGSRttmo65Gmf7U/bFrux6mHDjHU7To2Y3unwStXMYLlwKuRZPpVPy4 +ycKEHcQmV0+IgeybnequeSeltrkaYzFDXzNrmYn/hD0SnHul7b+ms5Xilq/aoFWp +pOKLMh0l9c2gHiqA8Gu2W/4DhB8e7aCddGLJiN4gIS4lfMR1/aiFYF9wH9+87T39 +jUl5BP+F/ExYtVZDFYHKiavH9ey8kyefSq3/BXbG3Lxo+xmFIH4qOf9g4pCugFEt +d5lUIQdtiX25aAu0+/HcMcHpodpPFBGFSfFHnEoA34SWtA4gZZwTlXez3hsIuFhO +0SooaG/n7hVV5xqJB6NXCZoJnZ9iMJe0opKtB3hP0XmluGfa2Z8dfF0C2dNvJLlG +eRtRfTIE1Hv8BdtsBbhaxdygEn4JaO+0k+VZ58nLeQOOpvmeN66DbDy2h+Cw+v8i +mlrry/8syy8nslc3mEQUzgOe8h/DWBSZLo5MFMObvKFQ13D+wOlH2Jo4gyDvO42T +xZfvyfikC0NNnrr5bHoS6EjnY+1FvrIaX/pHxyAy7pzTaP5qyCm5dEdwCwbG84SK +8leF2Lme7PCS30IG8th8muxiXi9P2ipbadcB2y1/fYqgpeIPw1kYU3owuKb/0/SF +lcgzu21ihDCFZijAGY7NiwEEDNskxkboHJIwH7HVtC4q/s5uNYgCtIPUjS4E+tNe +km4AdNdpgNtsZVgDcLDcKNl3KDYM6kySocJn4wCYoOjksyNoWJiUszhmaea5qxqI +Pfwv1oosd4ba3HfT4bKvzz445FnPEgi/7yfudBy9Tc79HNDF+M496KJGP9iIiluE +8fLX8g0PNzQT1OyV86wSDhyzhK8eGJEvG96jL4g4wGVYLaFRq9iw2POBxNqaNg+H +Ta4JbTW90Qw1gcX4xpx49JSkGUsdRccIlM7wYVGFlvdLlDuO3WdHXQGxrHz9RayP +3J660gi8R7x66n+BzYV9d+ihlpGUoqZDmEvQ2IglV8+l5IkraB3/OL3WOMcpj7bH +Dz53bocuwuOn4jcPykns1WqA0l3WKGHQHucB44ju2HvXB4kwzGqPt07hBqYCDLXF +DNoLSJlp5ID78FinDWQREG2dUt8mFXp+vwZnN5gPc6AKgXIZe0rBVIGC3ekdq6So +6F46opQu72jyiaKVpK+m7RLeE3x/uHTyQpP+IXhTbjHcRP3whNWbj5T1h1XruXpy +2YnP2ugGdDjqic7Z5kffUFp2iZe+QBAVokzU31afEjEDga8LMWp26znaL5f77rwV +9JQuSlqvUI81QktY5wDSbZ1jNbl3bJNJgymDmejbBBv5rWCrzZbu+C78K6BslXud +KRLifbiAT7q/D3T+ChTl1l9sAP6oAguwEzFhcVQ69kbHcpxh+b+0HDIqPTM5YJuR +aYUxjx3HX6UDWOocyh4jxFx5kxaxx+zMS+QaTQW19Vizsfn1+yz2RaKv/fsIgHU/ +qOAD3qje7gltHhQNnc9c9vL9qWwESqAELRBapj608hwxspScjuhnjhzk7l6VEb90 +xEbdI9tYvOa+0zRiwtHf/FZGIRjj2oOzy4N+LyOwAxJBYfa2oYNxWeFzL73+Zlbb +rzwM7MXGDk1Huparm0xaXc7n0vxPLGFb/7GBIhMugNr4Qxn0MVVxCT44acR+HKW+ +eQFi6C79PgIkzAS7GKxvYR8N9FRIFh9h98V0+ppN0a/xq3Y9Rcw5366DVvtrEMFf +FM7EbO7N7nprzcET4YpHNJ/mmEtjOYLVi6eie9D/l/gDlSrm0vCCTq1jupRPBPqZ +crtZUEdVKHAKmj9S0iRz2+tl7mOcxsGuVwRlq6ZW6c1FpY0Xoej2gkH9XrRtwBXT +tNS3HDvoQr2MhT3N7rMK9R9rfxVQDQrDbbxI6/ghe+6DKckib6XRjpdE2NNXWW2S +5yY6a4hAuspbuDz3r3k9ZwT1izAAmIA0B+WeyIRRAGVGLmG3mzrmeF3Vrb6NRbH7 +Uw6AxQedRO7nd+1lsr48fTeqD6805XnN75UDAiGbT4C3mIVAybj2XaQd2B2M5Poo +X9a1SySPa+ww9iKE0nDXLQYlkPlgz3ohdkBpmvG5iFFKJ02EDKgtFTvHwQi8nb5Q +huIdH5xgiIvcv+oaKD1GYQ7Q6t3EXBRi6gK63f9ePvI1g/F+yLAYftPdMf3gCLWZ +WyRdU9+loqLFoL1YoUx1vOvf73bLRexmptjrdFz5i9zDOi+E5EclZ+PnOf0ntAC7 +ve55sSUX/vQ5Bj0Ax1Ehc4E6lyWTjIe93GZlItGb6/Dm56OLAmKpLLSnTpJaOqUU +xRj7Ee6A0IssaJG24vifhkZSXbcw2mP/omZOWRPg5eklGskLWLy6vPzAnXPXLhHt +o4rmCZn2/FWmJZzsSrmyNSQSyFnvL9thTyGs7zOTgC6iktk6zN6PZb0nhfdhb7Hh +Zv38TwYKctTkip2PWqrPXJYlIyotR+2kC6qq1w1hqWGZCnRgGxSDjKNqDSN3p3Xj +mCbl+2GgUEkJmwE7xuRPJm7VdZPc5hr7kn+Gus4/8tVsbcAILELbURoN5dHr4ffR +A9Uyw1PLOMlZRLf+sCdajkupjGItPji2XGDN+0apq3NQyOTVLj5/VrP0A4TaH9/l +wfj7g2U2JmMerDrJf4r3frpQq8SkdUZZgZuKEQ2cTixAbXPS23lqSJAr6/leBH3y +hkUXSTa3ZkJUedU25B8UmeOQjr71DOahYHajI9zAJ0d7zS+Bd3KXI83AkYFkCZjC +bRmDr4Ce0iQZcupdaqyamyUqLnSL8va8xXp0hG/pqEYi703eFi8s2BH6ZHDLB2Ja +j9W8jP0bDC9A/l+wreC61bqh7oyfabUkn0k78mM8vYbUUUdeXHuwFQ3MmCc0vqTO +5mZK3xgYX10F1QBcAWZyV/QKQtSV7ewXLHbrg/Lc1Jozwm3dExg3FibvqwPpXEeM +8OOYPtg0yxQm2ycRG1kxZUjoKksHh+He68sUAKJsoYsXYVUHXXpjVOl4vhncZBlm +Uy4kTEzsKNExROy55hz+4zb4vqpTThwETu4R4vnlJl4qQDAxH9Z3r0TmQW1oyAA+ +psBIVWnepy+pZP+lyCcpPv08LCDqQ0zM9aqabN+NQfWCc+WLtLlRSS2RKHnFwBAA ++QGmgYqDpYN5wY3+8LBRXslqjuB4lyFHXJreSeVcXwtXZt0qUWjy8AyB4U1xV6kt +M7UC/f05UQGfDZ/2XJEsafw2/qqBkdDbuA3aG8BxGAWeQ3pBOtElJ5yvdcUIwSjb +olFtkKMgyf7PkrZ7UkhoNW0PuZUecSqqJV7yTflQSCkj2R/r5dITF2FXVcvEiJkn +SmoipCJ4xfsJyX1bmoPViUANXV6E6bSJ74T+9UaOM7YAM05lxcqSA6H0v6R+O/2h +Ayl+l8SNubltQucM96J4omYsbjD3fvVHKgaB0tDBW2AgbMNpPeo6YBKxS9CuvVCI +Z3L5MS2MTRdeteAlrpoQdfcfwtGUc1KAs/4YM3cmogFdr469QQL3iQfgfaLULhOz +DXrmqEG9ZuMCzAS6U/nlCsJVXsk9TfteLXVMehLTnvim1F6T7URJ3l5N+2gs9Wxu ++muiojkcwkutqTZTAXP4W7FTHAP/mI8/RGcn72fQ2UnGmNRlGqPIS4n6gHyPDpIh +ACdgoJhPs9zqB4HymPn+pygn98LgV2xSyIQ1sEa+WzBs7FRInWHfXG1v5G65K2Gm +0vghMypnGUDFF7jx8c2K2pLRkJI6LuyuPuyf0Pf6mvdAYN0t5h2pKKximYiw1BaV +Ji0ng4VvP2qgMPgiXT5cnQROOuKpsXDfV3YtL4u8N/4KRwHg10pt91lh2h1hbMgY +CT/0oLEtDfKGC2lY6Hgj7sjbV5bkz+2eD2KhWqYKrIrVBAlfaYzbjCrxcLrY9dJC +4MW0ccBsXYPe9Y3ZvqOvWFwUdZPF8+GhxRV3BIUClUFsSnocsknO61Zku4/cdX5u +HEh79MX830m1dUXXIYMIjjihmlTrvw6WDMXNp+l9AVFT9+Ev0mW4V5J3smSE9sB0 +04+0JLAlDY1+hUGki63xP+dRX+Tf0cqblxPeplc2NKqSLJnd6Es2pmPSsfYCI0y8 +DI35c/Q+Iflj+2U/lWNrpuoVPe1g0QQUAXHIeWfwH+ryLGf9m1v2ZHJE1Pu2n2gt +rMADDZ0oSi3DW4EWXfSJgUNccgfi9wn2nN4/3aAeEu6nHYwgdsGVZeD0T8bxj/gW +wU02M+EZWJCAbynAVePl7ABTGR4kX/7QxPIIBg/Eg66zGtKGRlsUxv2GggmgGsEm +BFMPobdHXNM6Nu1P7OzFHAeemLsjf2rNL9J7eWoTYMYV1vZZvkw+aVHz4IC2X59V +lbhWFnzfr4aUrEOWjK42Ib/PBvjGf81UZ35wUhEpKFmT0iW3MaZSe4vB6tjnrM73 +FPXfJ7SIJfY+oJ1C+uArKonWLfmi75SbmKkiU1SxpCuFtaaR8W3lrUzG246gGm/Y +wYbp/8Q9rW/OgrmmYs+NrH5tjWNihwcmMdNMH7V4JH0Ew8bnouHgCblM6VA4O0RL +cQuT7erRvJg21qVx7gPcigWhqTXfWSNYFWBvhHbU3s+yw7bbAQt+BH6ONYXasuXx +cBQ0z1TeHNoKOJL2a4vD1gA7I7+iqo+UnhwjZpgeQPoALPMeMiT+9H1GqqZ5zcgv +FE14VeSZ00mLzfbJAiptLIAAN8PWI+Xi2Imd8QwqU7/70GeolJiJ75scbX7neK5V +Ua+CCWMbHVL+QifcTfRBeRfPcBfqTb0GU4yl185qD+muZkLfOMkkiFwUgDQGRy7T +0OZoLnOS5HcEp6sL9+t6/LmbI32Y+rCcPnP3V66Y+fKmeiZYukPohYZf23ev3ng7 +sU/dN8NLa1SNLPiwFyx/wUtPS6mHIOfnC3GJ8fvPIKYjwR8JCbRIyXro9DsJyPhJ +ociZuLucV9J5zmlmQMbWQPFM80OmRh/LSkJXrqxidrcv2WRcaXM39UUnoM5AwLmY +EuCcyTjH1+Z3nV+8rjkcPIsckCtrmh58oloKEDMZAGF/zxkgOdn8ViRIfEeLZFSd +eVu/yXyF7xae7dkFp4D2RHIwpVHawEzfW6Mb/YQL9cUf+zdl/ph78I+HppX9E7rJ +17IoDUr3lCnygxxRFdAHY2A9L3+NiGbgiMQKvrXSLbl8CDFwQefz9OJoaLRlRHxT +RGEoaK/+yM0rwU44tMjPCSHglYeZXldEPxQ1JGFNg/SRkOQuHIDLoplNF34znC7H +6sicUemRTww62jV+gdwkVNbuTuZNi6rBkXaAVqdMsnBVGaw4HPdyJmenQxg0JyBc +9bLgrHIpGyJ0J7Y7kD6R/5NtgBobe7N21ayaSz2n8VTimJ6xsco7L6m/PzmDfMqt +ibQC1GicEDgAB2dtcO6tzd3Opd0GzAP0qs/Gc41NfI98w7q7FppUjNoEL0pULmwF +qwu55tMvonW0gwo2gsz8+KJcVpa3Yh77NIcbeFh2/V2Ki5pFeH65B1LjRfLqUEp9 ++kBtmwZgmKksLJ2i/62zh9t46FJJXN1q/w5vNioQqRl3RsvMNsYRnZ9/6wsLpCv9 +Gp6OAMo3eDYh/bKhk+QsFU+thyW5bZXwMuAyty7gIR0+BBP5VtoXyCDUrQHlJDzO +6nkxycNWS58NrxJHAa+5Wsa70UKUceINtt/1obdRiS6qeaN733jsrSksYMT83xaN +ehWrgFHhhfThQbqZ5tm4uJO1S/aCzUhRaitKYN3uWKu446IhR/daKY/esqJvi484 +GnNizsuAHdvOywMyLoTsp32dos4PrFaSqF5D5V0thx3CV0cTxckLXYJ+7XOnOAi7 +dOXs2PFfhFy5CTGX2Y08KxaXG3y6HU1/jMLbB5MwaSqRHZI4VXfCyzmlwKmaL/cS +2jthwLm3M3R/QpoTjHPVeO0aH0KzWmjltZLy9Ezt7r4UfuelHVt/09Rctj6D53Yp +95nSelSGZnXddi3uGY4cV1/XQipyCVlPf9I+eY8b6xvZV9m68alW8W6lL6rl3dAe +6C9TejbmMaMGEUO5jhjMZjUareb4YXa2NoiLv28VRKhdKlhkiLeLn1WtJy9m3BP2 +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +YE2kAOrL4lpJYzbOGvwVsCIUVQOUtbCEDF8bhBb6qm5AayzRmcPL25FFvnq7UAQ1 +uB3C658d0USynAoyfE1U4QQb1oURV6Hntl4FB7UVcquRD04cnlV2TxvDYdS0JbcR +7vCuwcLQ4Qte69nkRwXoGW47I8lU9Xm4LMbqKbIO/H3kwcGjabId4a9VWNoR9NUd +PqnLp9omCj724zHA/CeFacgIJ5WhxXKQvnlZsQiVyvLnVMe4kfyh3xvKd6+yFOFv +VarMWNpp0pgGSfBec1WQY1kFJu4x4xVdGdW+rciXNMqIap22sQQ5VR6o674a1ze9 +ohiUaQrLxx8AEBjSHL5u5Q== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1680 ) +`pragma protect data_block +26ATNUwJBh0ERNEcYuEZLNE2VR9F6dwubFMZn6V94RpIq6yn+q6LS2FXjj2KJGzD +JS3I3g/f2ZRWtySljkRc1KscNbsRLollG3vzaxGk3AU9rhiwcR59Tlek/gi1zf+a +vnB5tGGsg/c4cWAMVJbV8PKUWDGiLi3FajdMtoeQ2/2ujxLHGwEFdRxz09sXoYCg +hiNsoVdheY4BAOvOLN7agW1NGEwfKvGK6YnR7MfJjD8SCKZtfWK96BiVdMe4jEBk +IxiAIvyt7SZzIWNyt7jgB9BTja5HfYz5PATIZLxTsR1vzC7haJVEB65PkGjQUR3/ +U2Zldx0O/LqWBkWZ2dgAqOiWXE5Lmg5pDcEXj6SMQhqLHFr4O22HhF+qZY9TzKAD +k+/2hq55JUUgaFg2fLL9gsLQ79QxMYZXBOV4PJvxozL/ZyOUNyJKljT/cAnQjuAx +/A/wFPZS2U7hr1eV7gSw2UkOJS8B2bKGEWjoSCXP+t/3q70eNQOsyHFoqe3yFYas +omQFQ26FhNOR4U+bTsWem4PMJtaCxNoeTmQdA+0xt2conseTJQvKJvIe/TC8Fwjv +GrJaqE9OJt3DgLbraKI7YuWqCKQeCFgX9xxu53qHShYH4o4/yz8YQwQ8aAes+i04 +vrOggaK7jZeVqvXF/w/DU1qKW3fLOFsJNx6Yk7RWzUws4XbXcMe1wgxYdqOVXWtf +n11gKa8wpuCFSUYxEmiTaT7pHuZ0MYr1b1a5jHnG1PceUccgnfn0vtBd776DMiCt +aiXDaRumupAAtZA45drytSlVrDzAdNskqYDJZOBjgtlSSEkCYZb9vjUwYSArd7vD +ruA+q9Zgw7s/e7XW3JDxCmHBnfTaJ1u94W6SVn8boaaAQUVUzNWy1oFPt4VvpPlE +QH1DWGZFprytzSFxtrJ6+8fluY/fjnrwwCzgebzG62tjURpzaFzE+6a7198k7pzW +9FF3/oVJqgOi9It4NOpB3cT8MIJtUitQFZwPQjdWkjWYhG65WeqFRXw4v6YTpeTe +x80pzs95SQWA6B8wr+PNJrAa0uBmEoZKqlmS4peMdo0Z1dDJUYgeRlEoYoIckddP +8y/RcBXYdX4jVjwBDd88c4H0p9ml8x/rnBp1xLSGMgQor3wPC766aRrAN7+obXap +4s7wiIeUAAYwfVan+3J7FTGhoct175a1AasCDArorcMzLB/T8grYUtm7fr/Aas+D +qRwPmJAiqHN6NTTzMo8J+fmoKdlT4/+nbQTEWP0sjfqcTMnmbjuEq0+xsmj43PL4 +Cbk77wZQhunlfwkkeb0TVO9ALPiITttoWxL7wDugGVyngguDNqpownLQCRHkwVEO +KZstlkOj8+H/tssBIUD8QiYYnQ8PiDBZ7GAQREeQMnwaYoBu9uVYKYiR7A3CzUZu +e1msPU/w8OUKAHEWTUNMBR5gqF+bJb2SzJKiHGrwrK7Q/soDyE5GTCCgoDrFSIub +hslvLTZAa8psCYs3QGtoK3fqZcJwbhl+Vt0lwWnm8lDoYXMJU/xIaH9L2cizDmIu +FstjphugMNLC2waVJbewafS9D9lUrcC2I6AOD163dpnphIxSeVyFhAlQZKEzPOQm +FQZLdhNJFxXszxpUDs9WZbDwPs8V7yTQPslW/EEyiYswri6B4miUpNZVoSzjasFY +963palnwgAb63ENM3qlsYc+61aEOxshrurZ1PaPUAJfyiESBXemDcZ4t3gIDkBiN +Wi8zKUSGnOCjh7by4pX5U++lr0bTU7OcqAuxYEJvjxFdCiDfOAL8bzK8EdvVuOHQ +s6X0dURl2g9zx0HrmCMTy9Gp0zPr0ncz0quyrmLLa5mGXZz603vwg5kMLoTE1zgT +d/bO2AZTchrwVIw7IU26KSxopJ5NEk9fl28c6yqemCaohURa0mpF9m+lFna2l0PO +VszF83++mGHZxD/B3SpAMEnYv0d6uV560E5j32UdE5d5VkUEpMUNtSZJNgyq6RN0 +5vNg8srxsy2rG3nDhpc8Ir4nYm73n6rl0rUBkUwQGb/s3D5QzE3lTpnbzznjA9oW +vm7qHy3ZV79Ty/hn4UBNC7xRiJeHarTxe3aQX7KeZhZKGXdCo4TBFGWZ/iKI4lUx +ofx1MCriuWy7ZKVAPqU5qIrbn3GMC1aiY3tsUIsv6dK4NkiZrovlOdhPIT01B52H +YULlKeHm04FtXfb3Z96XBsyV46X+1rCkv30JpKquKlNnp6c6hfpXKK0WWVeiczzo +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +Clh2+96y2UaAIMsOT1iQd0b4LgP6cUyq8ikdSaopI2xdvmHpy4MCZw5eH+3bsiRS +sIEJcXd7mTNOXDmXhErDaFesKLkcq6yObhPVwNralwLNFz2QMabsWP3pK2FVtkYI +fj4egCCAY9GcswHvNDiOf7clwh4nxs+SsNQqWgn4+e03w80+KoCR7ntVbJvNn7Ru +R4Awd91Y3QAh4vNgZAPy9FhwFh529f3cC1dTuK4Ub0ZWgGquypgjleCIisw4zCvg +FHeGKwJ0ypkTUqj3xiglECEaa4kDPmUqRioVyK8ierOu3UdHSjUZ9hAN96tvKAZs +H0Frv1cvk6PU6a5SMhm8lQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1872 ) +`pragma protect data_block ++FF2ryBPFKhElPRjRPlL94Ht1qyO12X9daQ9C99SM0WbaOTEIqV0p/mmSwo7XdNq +gPyOyDn2mYFJ5Ilb72QyTCdI0y5pnAVoN2wYyhlvtVZhEDTMkVvgmFCmkgSwP7cM +yzGP5HP9OuOS40nO2pFs5iKDvfcKXWtExe42+mtlYGf48INkKp2bHVRIts9uGh+G +nnqPIZuE3py6Ju23I2d35DdwqO/3AV2MOkjFqiWii4B4uT/uInhNTufGLrA8+P0N +WeYJFyIjPX5JPjpYxIAZw+aVuR6pfD0QqPCCxm2jr49DAKsaZtMnBAbQIz38PHaZ +jEToXCuCiAtkLBHcn9PN5PS8HsplbfguTJ0CY/sOvBS6VqCbdoT8Y4lrQpcWvohd ++BhXiJFEMCQ98F1KgLzrdUNmfroOuVwUuzzkkA0bIuJHqUx1f3+vw42RSNBr4zAS +ASwtMbvKbyIN3n4QQeB+rppOS3yrp8NrNcK2xyOSxnsGX+GKsphHbn+8Tz5XKgrJ +WLMi/AmfYiXmv2NXchFp8ELBERHtEo2/4z389iThqwkcqUVrDUlSH4GkhovsGylj +3heghHehw9Ibfys9ZUMpakpZla7LyLbzekJxuXRGAODLu+qiebcZa/idcTV0tcOq +AdE798kou3CdCIdfyeiY9oC35S0rfA07uOA/zvVceoCNZw8oR+iJLBM4zj1LR/qH +0p/7vd81jwDlBOxKYNt2+hmSGzqwgZGkd+49sthGCZtUt5RXR2KPuj1vIwfq32TF +55ow2akOzG5ObW4f6YNNC3f8poq1/O3Vo0SqAx3ccwarGTJ+dZiiM0ucl6YxEtSz +ND9Ez9tWI3BHdSQmjlgOEnsEsoD1B1Jirh/BIClIyB2osigAPCvyqp1xD0IahWeg +cAOWdCrj2WKZpsd7CdZuDie87OWnWiXGR5zfZWVXpqT3qW8M244zcoOZAggHGuXh +ffjFd71jo44drv7OOZ95yMXltL2IXNfkpt6Sv/vP80P5wOv3A4q8bj7KYD7MG47w +dN+U/ZnchN0AeoY5yWeY1HVyiDBIPWJC8B50hId/N5nbSf07wSUoRcLY0JwbheWx +ibGRQCjP/NDX3wtrqQMo1cRIVjPd0HcqYeFrQy72UARUI8RUYUQwlfKi3Aw0CaT5 +ywRd/Y2dpURZriBkvgGVDglhUBD7rNAhUpUtY5U23CuuhLhY764CLxphgdFs5bkv +MONDF2xps/zvh8GA26WixN4tHD4NPeth5fxqcx3sTuYa5mH3q2QQvEfFyxUt9uRS +3V2/sZtXu9paziifAaEVy8fd50ipIXiUG0fUHlVkrpchpXF4x3KpxyN/aNLtgxyx +IvAxMHnI81iyb/pnCWyBVer+kDuGYkqs/wXwT5Z6Pl/y7w76ITS7WUSXGUecFuV4 +IjtJHaHF3TLEZpl9vzsC9LbpKPiMBAGEIiewV98VXLIs/3iActQJ8K9g8ZgJmElR +ZIvPTHQKTyPn+zyuD+9XZeDtx9/h93O661F8Rt8cxk6CrYHwFIfu9SDh4g5iP/4/ +u0FPT3ozRoBwjjMpKT1K20NOe0ybSxJqsJnk5TFjSZVGLcrQxSvSKupi31zDr8sg +Upfc7mWpYzg21J9oVrXXHFc1lRzZRzMMxZAX+Pk5PvM7Hhe5+bumLWIuS9kvq8jS +cuanW36GhbTIy52itg5NiY27riMFfxfPSdi7nqQ8kuPffSc+KkiNiTshklNa6k2b +MHUH1ejbbNwKGyrr6hgt/3nPFa708KECEcQ9AGrXJaPWQ+cwuw0264ruAl2FzgJE +B9En2+GAGXrxsAJ00v3KNt7D5YJ1DIksGkzBh9XWclt5rtD7AgKS2gXBYlrwvh0K +QokmIku0nRTuIoc/WluYMLZKqCWrRL2jm7r9duhGOepYI8FlVbj2zHjNniwC5PLN +9Cvy58hmG1Z6gj2O0v7eFudoLH4MgKywUF8eP9hhqv3m/5qu2ftfDd/ipyodZFiP +ijNPQZyxplBubafG0W7FLPir7d4nRTl0MpUfQKjAcEJ1qsnTp9iiFp5lCY4ZtESu +DS1I4s1QbFmNd1IHT7MPuu9KHPJHRpPBcVQBLE2VW2YY8eZ/aVWwv6uMWf9BbNMl +NcMjxnEBx9RgP5ZXCq2sa+EG/z0GxkpS0jBulYgz1Rq8G5PlaPHIUuUElokeamHV +wI2lJwG7FA91UrGxOUEE76PabAZEBdtbFBmWGnYtzTAsKFHmtr6Jg+yq5A05rEru +OXxmJVsUJyWuzeSwtLtjeYcYIi5HrYHdzhojcj6inmmxk8UdKEQqr+o/93+YDEH9 +ac1c7TvoyANVJBmnsyGUJ94zoCf1z9YPBf0sZF24QetIjrNIaI4skW5CN8jVZrzP +ca6D6QlzaU7MR6KZavqsEOX1M/D0wbA+CxtkhRtcEMc4hkwcpFL3AyUgu2c9YIp3 +PbijWvq+kgGNPaahydqMP7PhZeaOIyKzogXmzbLXaUhJ/G+gczS6YdqBMqHXYlmt +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +LE2+LFfgwm6au8Qed7luh0VjcDc+B3kA1Ir8num5KBRVTiIzuKhCP9/7nz6ao596 +bhXmMC4XEva1VPhmJ8sO5e6zRy0FI9xAkDssejY7vLm8R5tJ7VZpvpLFCSx/5wKw +3wWXcxoZR1+PJk4dJ+QV4eKQ7AyeGiwI8DtallapnaG3wjj6w0efefqk8LCOmJI8 +behEHZOLQ/5Qpbyxwm0fdcGc0iZ6RspvMpZvEAL+ao2MBxITzF6OuflDziN9nI+3 +y4ixJYyFEAT5NSelcIU7gXzJ+0KaGrTGh1cAqPoimqI4gIC3zaVWjwCU16v7PFTz +rz/Vvf25iwmBk7v5U7qx1g== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 2656 ) +`pragma protect data_block +QhqXslTzgnkGEgHGFjDLyiolpnRzI2jYjYsmFe9KtqCxwFExOiG1NIxTknOXbUvh +aXAKMit6YPaEPHPG7Rieul9mKjgDdkKlbNG6mqDFpZO8VNumtGG2vp/ScoiRunwn +fTCn74+AfGiWYVTOKxtHC27HLiWs4FVv8zoPZzRTOtDls2ImQST+nQl+4CNxj99C +PORt251BwFl8yZcElj3JERD3se9TkKcbnn7u5ZhIOBnlNpf0quHLEAhvH30C/yz7 +v3pl+J6nFV7nurpjDFeTdeM52wefSsd+pwVgTCY7nJPbgUKeqves2ngkkrNk0Qkq +KoxNhA6PvCxDEqbEKEM0OMPX5n2OqcnoGpKxMy8tAyF/TwCtA3s+ODJTqiKu+tUg +OMmmDMi5JDiAb9J8H+R0utEcHORkCpYiSrVwHE9li6epCfDNedmhNJq7uRaOmdaW +46RcBGOQnQXRwlWsUTC8RbnQkvTHROYLgXjpZ7qNwwNjeVE/aLjPkip5CZltn6hI +2MwIhRUpsXlKjbx8mvPmFR7GucSJlRsJfYDL6lVl9EQYvxbJSe0WJzXRUmn2dtdw +M3BK5cpe3Ji/MrVKULHAq8Ny5iseGF7JSj4TvzSwI117X49rnZKNGyaw69jqRUB5 +AuEcMRPHy8aUdiU1KSFCj/Yw5dgwa5gLIHowmVm+HnY0QpXxVOWosQ9oJedyrXWD +NNEfKSXhnyh+J5bt8Xd5cGiCsDF2bCgqzTkrpavZ+bp6ICva5P0JNJuWShhVidfV +HyXF7r+xlkovrV9YmVe5MQioyRJPaeYhH4VFeQxl3uVND1HYoo1iwnmQUG/O89Ct +R8YBPnRkdsdxkUiT8V9OXKBiS/DbBgyip1KZyIrQXHWiG8YbCAuzy70PqUHmVspm +YlAiN6EcJfB6y6YLhIaQS4oYJuAOz2XEVGaWtwT24EUOiMi1VtCJ9zmckyq3fNI2 +DHMzD/diYUI9TfskUYjfUrv583zodnBiHAvO53k7/aIuClinrklXA0TNk9lZJtoV +6/O/S0F/DUxjh6lCewdxvGgY6QDyiY8F0amvvVpJSo3wWW2PbrMUrFjoHglW5ipa +iLDG+c0huDn06ZEet9nC+9Md/Z4EdGB9qn/hA1HZqC2lpPMH7aZnbPGda9j644AZ +b8MPRcT/jut7NxcY3kbhTsq6SIv+W+xhwafcE3WMPWhK81PygCOT9fQW2ZzJ0bEm +zELUpVr/YVvwr/yh4Sgo7ezoOr4Lu7tPc67L6aRdNmzZdE95pC7PyYHVrEWpqtkj +Mq4AwChzrxP+Hn2K0/h9CuVf7Mh4WYXq93B8IHcvF3ZYxgwKH1Q/FfX8ewXQJXeZ +oPsmmZ24D7L3vkV6lMudscL9+4YFdBvBwy8cyAb0D5Y1/krMwR5d9XeNpwIX/lwj +fJTwJPVDzjlVscd2IeQbolRoOwCJFhUrPiYRfrsK20oFaB5p+UPVsyGMjbfEvw9h +Nj+su/UJZlFWLrSIpfNI0G/U0AMYv7IQgnipJQN8rUzm2kPJvhH/Nx1tB1443mU0 +svTZjQXXY16vUu2p4BC0fWtVeREL1yQT53cOoi6Cu8dPArHuxp1JpIUx3daUnJCl +JkJ8R7zJwKnVmCHmyFAvszSral4aFBgj8gZgLgCUBJAsvIfIs/5280xggGG7y1vN +c1u2LGwYO7opOJVSjjHLv0g0KfEvtFyCws1aZRoevUTDtkSHuvxYxebyeAtB/x7k +69tU0a6hfMC1C+39F/zhfIZW5YDUKR2Ml1MgYWn3grPZUsw6H1yu9BXT02vhhntF +TfXNNcfNTJNZqwverllUZ8oV0GAJjVE6s+u2OozQeSALOSMHT79ZgGetp7GhVOgV +R0tyS+LBt9DUTMPaWYe6fwbL1vS+/qONocrfeOJU1C2rk7JbZIjCWjbyLniYG0MC +u7wdSila2z0vtWPGSsCtWm4pTYH7Xh4RmgF5fdfXr5ugZcqOvFkx2xZ43j0WDFyo +JKI+4T8ynYpSywiwjfutUcT+Z8uvDmwy83VT9J72eCUFmieg5Ey4J4EJYpcfVb40 +ydUPSO0lvXCPLbG1gKxKAmcW/6uWR8EwCpQgXghEQ5knbZsqyCBHRvq1t8qTOBAP +0ec9wz5Qz/JCFFuFnqtea356X8kIQHhYiOyPQiiWhxHseqkfFzc2bFgxB1cu28lD +OJrckJx2wuEvQehZAOQ8H1nGgxLdTXnzW0PkSr4balxwT2/dSYO5ZI77iwuSbMpY +xRsrxzGqwva8EZCfZ7nA3dBmhm/3pUyiV57qQKGMSfAfzOgiGTCg7Ijdc/Ly5OjN +iGAXc76Tm+E4ZNXRb3tmHTmps/kCwu2iYAbE2mwIvz8nUZcZGRCuJqcLtNC/xt19 +rfn7gGpu1IKNIci/ZhkkpJg6J/cUxb3xFDyc5VsmPJaPkrQ90zw+XbgDEQGBJuNG +kmbdp54gVYyXnHfi8rZsX1zApPcSrvtNUnJiEVWl5Y2z4+rV96HO0KRWCcV1sgNG +Z6hUCoiyD/fijkxgGVduGol1LWjNb/LsVqh70fuL/CTZgb0OJrfGgNvvQoG3p1f8 +6pH4qh/S9EFueAl4qHCQfQ7ikDRyqJo/chRYbuIDqwjMAoGk/C/vBaQS6JjnjpQm +i5WVQKXgMfocednye3yu2smD3G+qd9c2RVJNUAov0mPK7cScYj51c4PDcwzSSGbn +9kSIuwlc/t4I8FZ9kf68BM9u00J8vgrRjHAuaO5QIJnzjnwzsSLqfQtm3lsSVHod +Ui0wLGTkeAaiEnMNBM9nwRJyzSn9gszDCeaclidsptxyOHMPq6014IAzUdIsHEUV +XqQ8+G7cwmUXuKwk8dcxfRA332QEU34Sj9YWGnuyF/QcRVWoVFEZDN0lnWKCxYLQ +2IC2giagOaWwuOkTybJTp7HnDJ/QMtYocOjoIG7aVOHjaKiBbKYQYgIleEJqiewI +7vkL/7JBydeKuU7IIcDXJWneljzbOD+YOn11jAyYb3h1suSYOYCLKwU2VpibLAFJ +fe9x0TyUDqhXepAtkMX+/ch2Ihn1zwPkOBVx2pIzviF+oGkkbq22RgP0P1SKe+C1 +K+ylwfE0TcKPKOzDLeqpxfkylcOzn8nXb+kkjOD8q1vcN4H2w9IRNTUH6jA8X/Ua +xR2aYfZsGUs2P31w8s2IMjiolr396FI9uisk54tQOEjSa1MZRubiHhA1b83nQtn4 +u54EmCw/DLG/SdAnEMK6/jQ1F8BM7OWjpNHu3hv7SZPrBAaLXd6JiuE+9+qxl7hW +eereg8KEx/wKv529cnv+i+nzsjSBg0eym/O9ZnkIA5a1xooIdJe8izoEig1leAst +Ao8zJqa0mHX2GXOEad62TSzzDkiqjr7AkFpMLxRqmrp411FDoUfLqqYXWgLNHsEJ +T2M8fB3gDH7WFYjT8S5qJQi55K+AxI07KOW6zZxH1EeWgfuWx1P6qMXD93EQEpPN +qUH4WLO59a5T4QVO3/3l1M4o4v08iF9pcPJlrBX2IT03wgeyFOko+k00CHq+r3Px +xRFznbHeMXrJzICpc1qpNg== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +a9hy4rxBrnfw+wxP50p3JnUR+YJ9+SQjya3L9r3erHPvT0IB1/j6iUYV2UN0bWvo +slhWQdYOx1GoBstYG2navdEMBM1ksTWHFLFWZPJ8ttxrSSiPvCG+xsAf4fHUEoxf +FnAG65tM4DRbdjUOKOcqR+OZW/S1VHDt11jO4HIVRc25PAbPViCji5Os5GNVet3J +G7F8KtMTbVJHqamQ0NPuY6ndxvsW8w9g3nuLQjWI+H7MLiJKtUnjJArfK0/wKAY4 +nFsxLy0eSD+CLtVbao9QAWtOqZlWzD0FwO4PqQDtVYngsrhjYpzk6mTCzIwBlMZT +fr+ElYHlgyghsDTuN+QRtg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 16720 ) +`pragma protect data_block +8upiWK6lq8vrvGkMb1XU7RyY+I2bQE3fPjKYsfaAtIlIcixj7CcX+r/nx19SUjOR +5EmweJL/IHojH0EAd1jMpdBD1kXJcA/wiy2b/HazXnORDvyMwCsNkx63/cv3Ghba +1hNmT1Yq0DnOpXRNQbvsUPpuzQ1AFL42A2KXginlkEoy59/m0B7sIse8FPijpVNZ +IWce/IwOiWGLPa3Ivm8k5NZtDs7bOkC1+bTut8Jfp+h6x1LHMW81mU74u6TjsB5H +jVZvf2peUwkp7CoLQ7iPpN5Cyr7kbj6hhp5CZNUKdK0zAzFEejbqEnN6/CHKMuI3 +W8fWWVtsGNA0vYGaMUqBm0Wp5/ER57Y5ZHYm/VL/VuE1sM6+5BUcx/t0Sqs/yExu +eYc5Y9qXpFgJYnaypT5v3xXj5/xfc5OV3x6GiGiokz6ZnWDyxnEHdjRqpOo+8gRr +hT9REnDojW+sVwX2PA7bUmxkavCpKIPo8zgCdAsU7SDO4hWw4xSwY4ejTQv1Idmw +3SACUWoIK3n+agdmQPxn7hCDGsrSSY3zaNE5kOZ9AgfRVMcLcTbysDDguzrEFNJc +r1iBhnwinqDNAuh3ytpN/NMr5bx3MiaN4ttfRdJ9H7mpDJATEDjkYOtnYrw+pYj+ +z90hOLkgJ7GjcyfYwZ8315RoGpoKGvIb/oz3SkfNi7q//di0d2S8+9M2h7OkNsNC +RN6NJki7P/hq1I4px4ZRGJkQdAa/iZipCyT3XtXlFPlFzFbgUWUrWnZLjMzaMEXo +GSpu+httr+e/ZyY9f2mcV4n+NivwIcpQ6Pn1DHgT9cZr0x2hs/cI6z40WtMbbeYH +UW2zEKX5grGSf3xu04d/htqQrSD8OP4WfyJNP/0myBnJdGn0v8YldONYi/tLlnx3 +HuT4fHLwqoJgXsPRqjakE2WTKNdXNqbnggZoURhC+qC7ulWGa5L8PFDCjuWddBna +1otEBuWEzpd2qIuzYnQqb5EaX49Iwr019pPElgeyl4qcF2J+nNDf8CGLLQLnGz6/ +1k7EyF2YWW5Pz4XYUwfsRQUJx3oKrTOopyt5ilarf2rFDmQeFte/NWD9GICbpDXa +kG4Y+Rto5aHvQpIdg2Y0/XTbqeGLwlWYOB02U17EGtLG05mokTR9BoR6lOVWGvcg +EE0EjvcsgruDxaDNMP5qO2mIv52lfA9UCmV2e238j8XFCEGTGJYd+FthXOAqabhF +d6O+OVwuR2rxobEPGdwrj8HKP7ZFh/XGNL7c18bcTIwqzYmKLR3P9109xhiozyHN +hQu4cj3Js+EJ99y/J5IEncdXu2jhR3MYi0PJJKd3Hn7qgsV1AsgR/4Mamg+fUYJu +Cup28IrNkS9uf2rXthL4tW18wUum/OuFuUR1E293ffKavnEJSfS+jJuh1P6vkTrj +t7DYBGbmHddirDfw7lLUjNC7YjtR42ZMS7Wz+QQ8OBgmf8tqzxcQxW8V/SwBm8X9 +B/+dELKL3EcemEVrZFskLNsArubjKKMt4W/1Y0RaR9SaA0/MB4ts3V4im3I4s2bb +W8zXwcqivdkAeGjmDakh+G3bAwCKmiuV0wmOjnpkuWhBwJihSipgjJxZJmF+LVa6 +TECjJKIZ1mICoiTzV2ywelCZJwQ2Bnp5B2w7GWQTYJ6aW2TsuUQdK7VcQ8tPE1Cg +x2p1U+AKfklQ7tjw1bUhspnScnjs86evSySFL135NSXKtDg7sGUaTeiIqUYcPZvp +TclcewTGKjrCXynwPjguEvtN9JoDfJT3Bf0kl7n+2m1mTDmcGtRwSerkw5qmQHFB +LMqwTpqdPBzL4GjY/fqnsawxKA0UN+nET55/5qE5K2qRMZyaBIE5Z8Bu5YfXyXfA +wT2JENXWq98/CLoMd8/tRmsUb8P3Ht8zooxvjamDHOXGAH9nhLalPuX5+73XGSav +5nO77HG7hVLhYwjrDNXUfdyuFQUd/DyL2TcGa1QmD/oCYF1bKF5j1J6gibdV2GnI +aQgZ0zuq7Y5TGA1HMhH9rgEd4WRV3rij0h2S0Q9NYlMCSFX0glxoaUquiD874jsl +lRcd/6E6Ywr7YhxBPbNW9pgt1cNWr9821P/JBQgsmOMk/FkXnSQBVjEV2U9gLpFh +vnzVHHC+o83UwZD+nujghVya6OdY8TwLVQWv+lowtWsn5ZUxqNt7L6u3ioJxc18L +EKGWjkBE1IvLdqFEu/NvhHi+hE/YHUwAiitJ0PHb++H1hk/JTxBSfvlNTwFdp58X +h4f8TZqut1WSw4044szwyzhhyD+VMWGZuEugxmkg3EnMJ6HoArq8zVb1Ol1YnMec +3HHxQJk7CHeBkvudzoV2Bu7sAu5TiUa2IiQphQAK+JDoMuHaRtxl/x6WjEeCU3pz +pneYHkcUY3S0r/Aid6HaGbw2RdURgR4dfSABUH2sgMZpMBw14wxQhhsM3ncBNEmY +U3TKc0ebNd1dx0DWD1P/cQqRq4X6i+z4fF3uLzpJJ5Z81l68kQmC/encqIqVDRj8 +AC3mCuLkHArzjK5r+EK/LC7mPwrJF/pvxM+0mPIu7+zkpNMaB3Y0XrnEgjRXTkzK +Gyqq2kiFQw2hB6XhZuh8/Sl+/FyrhVq1Ydo1s8JYwFAgUI/s4Y5+NrEaXnx8DSFA +h8J/P+qOiqZ/tWAxdfb/IjuuaZ7jT/7I9VC19HLeSFPaD9JMrbEN+qi8ob1oLfCI +LHJcgiFQrAPs8d/6p3yuC7B4tCzqYpbdCEAzzQUSnHMSIgIXhD+Fd8zVoDjuxx8j +hM9Gmb/lG1pf/2PPeCRV2ByfR4Z9G+Uh4oFnJV4GM+WmyjlcdrLJJ1a88pAebZNu +LReoX3SPopwzpDKVlFeq1C1Uw8O+IrNzGLZcRQcBLaOdHKM1poh6dQgZW8hcan+y +vI88PskCGS2MGI2gZnW01NUE7C3cEpNaes7Mom2G05vINcbQ1Yp7wl+UD3rzwNtV +POa6w6Iolytbyq9QnBHicrGtda0uR2YGkNIy883eIW8JP806VxsOkuKR8tVyLQE/ +Et1Oid7uIe8N+fJIcGOru3x7Bv6yD6twrqFuX5p21GlYjkdzL1/o6FjCOb9RAP09 +kDhDRw5/y8UCPDd8wMS5fQHw/XkEZxOqzVMWoqKhcPsn5sDyas5Kouv8USVZhKwM +QNe18c0y9c+W6Qkv7IwiiPXdombhBQLO80bUfc3Jo/9tB1xfjA6DnmAQwU2BaaDP +SgQxyHrmj4MSU5XntalaBpMCFmsJWJHZ0dsa5n2OfY61Td3MaDfHjgivLy9oh+LB +T8axLWLUCoJUTXYGXeRZ92bYFB4NxXNl23Y4i9khSYAbTmTrTkzwyKJStA8CCXaM +dzf9iqnbzJUz8mdzp813VaONGNGpDKekTp8mIGXLgtEMgZgTSQoR5wN93bt5FXVN +Y7SeRsv92Jiea07/7l1Z5oEwQ9OolL1DsWX6YpLCUkOsIkKtME5UCAHeHVbdULgD +9FhLqNhH/zdPDqnMInsuXVTuochBelH+DcxVGYKQ1hdKdZ+EnLoE+kI0tg9AP1pC +UIf9AkPuKAcOqW3PM++KW3kxkZap0e8RTvwBdyXGPGvQ4anTqAbcxHq3VfWuOESG +xjKwfI59ZeRqBGjNGd9DjwWzHFsbCsH3g7WpT3UZcXuNvONwsfajCSdnt+D1INCW +/MWDasVg3R+pp+tifo7mFlQIQ6zb+WZIVaFDt4upqc1CRV2N5wsgddVjEGLgzojw +zGgMy9D7EUaCZbcPPChVU8pkTVoUb+936aN7Y2qxOncIhLk66RrSRPz0OND2hEm4 +PDm16zd4GOASZ+RlLkkaI6wisv9PsxV+FoaKREl6R13NvM73CPUGtnmkTUYXmM9y +l9TGC/qTvX7xp0BJ6uKzi4PpTiMxj0QbXGylss88UeDMTmJc9fro9q1dKwaGAul5 +g+qWaOHPfWWrlG3tiGB/sDaJkwVC4YPLzSaYw4UhROlN3Bq78n3QSTNMBI3l9t5t +tQY5ZltWgCRUsoxlyd4azOdMhw331M8JcfcTAhBu6RUqvAnQscBNA9JD99NpQiJo +hRBAngU+wtH4kHrL5RhweB76v+OA3bT4Uxo3fCBcoF5ImvipnLnp234uh7QfmwEF +ps4X4lx+7kQw6X1uqF7lJpTjERIEob0u9cj4tIaoL2e1Y2mJVFydNdp/pyigyBcC +e9wXKaLLsEh1mbvAmg2GJAu63N/IbI4jcbMLixIHKFWL18ZulF8ko4f6ccW1STOQ +g1MOAYBHraQZlogos97LF/5O5VDjMpdUsBcry5Yem8WwZ1VQWLJN4xCQHQd9qelJ +2g2XwkDzSLnW2UTfKr+wr/fV1Hdyjgyw1xCc0t/dn7p2CZPMghA1HyQyLgKDix5e +ZViqZ1NySOrJDkXG8LV7kWOz9BeOKAsZ4Z3A8Xqcr9H4yX9xqIf/6AUZ0ROPHJMh +JD0HY2gUXS4Ha0SPW3WlTI8P78ZG9fn64Y7daXh2vEXcLqJzPKC48ps+JfE5yDpu +qgpZcezC+jNO96ZKJ9R/43tJBXEFAUsqsLvXxnTW11GHwjuQX3nKyyo1moMs9dx3 +Ae7d47mNe2MiFIyz7NTKR3/pGRtGrjGNaGYbBN1MherfVpQFylrs7J3sJxPNXOt/ +85IBi0FzbcOgc6pZTU3vBL8k3rEH4Ji2AaOnRAx83se2tQgPHYeGymlcxW1Q9iwt +W1ZPIm7EnTz6mmRmPoBoFaLOR1WZwUAcXVk2OphaeWP+ndA1bqEt5SSVUeJwTBV6 +hJsb+yz7x1a0QOqGAC4l+zBTBhzwnQ3Z4gPnrThNuxGEetNWXcXvqwzRqbF3rq3W +su6lq9/XSZ1B+h9oP379iE2nVT8OHR5m7mgV+CglbJTJ0XYkWDQDT/xygrZoO7uB +VJw3ADBCnXUPjhP95YhZQ9ync0/Zw9g0G0DDekx7JIHcwte8ZMJ3aSGafVhJ8hsn +hDl1fjXXME1EF649abc+YZY/xpWaVY88wOPPJXcHzxAPd3yTRbApBm0A2Kr9SwOd +TW4i2saxSLQtm3F1KJ8GsJHQlaWzIcnDhvoYUL7KdYNNfUh+ks++3AThUcJVhhlA +0xJuAE6o93zCoeglYR2KsjufAhoHpqhHnknxYkRrrcHFFmjYO3LrAZ8uAD0QSv+x +AHpA3IJXnHb7rfW4s4tlbg5fBEMZ84lOEX7LCtpfzldB9l/9WU9kX4MQ4ReXxyjJ +SK8LsgRlKAVDLu+lvos1pAWtUubJ3IHeopjgbs4UVPiQ1SG69R6tvF/GMQ827FXJ +iMBLyIlZTwcxHvI2jUZrdiLqrqcEBQTJ3JlBGcqJwXKLF1GO56R8k7tiTmApJhFh +d8RAqoto9uoYHO0yCSIQhoHJCKDDAZdveQzQWqeRA3iL/J7gbJ5XlE/Bsd4aNBfL +62HE9c1mlpkjC+Im8vjjtLNMK05WvwqLackXgaPIzaVcTAIdDHct24ZBnlMIhPSH +KcH+KXjNiqZ6n8D+Si15MTJcJd2eL6HFQoOaOlILxbpLwGD6z9TbPs0zKiJ6rQaH +JHd8VBbNGFuWbC/QHHAIC0nIgKKsKSBTCHyfYZ8uEc/bfrAo7IvDao2yJfYLZwhk +FBED+q0DLKN52H/jQ0VEi52KhEonDZLhKKxiohtCvgCfsws0m9kg+q+Z3kx3BWoe +O2Av13m1M67x77wM57//LoCW3Fu+yXXMWiEZ08hlHaeqoNLyU+tHJvt4lusKTpxu +egJdGwz9ca96p01MgnOI26IW6iCcRM4V5AVJEmoFiP0NG1pX6AAko6idGSZq20+/ +DLOBpasihFigSdMX78+geppXjRWK1CuQNlletx39GgTJ23UFyazp53d5xj2DdgjZ +AQZAh1Um+/UHgOmWDyaMPyzaHYy1JoysYbXwRWBFjp2HAEDSSmtOxfKZgbHZ0G2J +uVSkKacWnmbpOEz+z0Hj6BXTsFtPmO0PjzALy5Jj9MkAf7+vhDYHC+S+X6odXBqS +OuwANqj8PtEO+nItPgQNXbPlJqWON6kS5AjIdWSGF/FLaNv50ykVf1gA3lxcqU0Z +6hiqksY0yTgeB08W0cv1lwawXdY6zEjkOIzsOeqscwnHVyTMdhJFBMom0TTwC/5a +ZxVN0FaBqvalnYj/22Ju91tKIxFxJ2h4eyfF3xN/0km3kMn57J9hjCVrW9jopPWU +tTwEPY5HBwQ1MWWDyqK4PI96HhL6ER8pjSl6eWIrHHnuHHf0UtXKbY7f2rY0PRJ+ +wEmOjj6nkJPF3MgUKK16gH3qGJS3A4yxWDmzl/yhnmGGvho/HtHVLbz6oYG1MrTt +tPsKeu3m82wK9CoUKIvP6cJWwZI4OvRF37JCHIesfI73GRWYizpfhDzCoeYk06yB +IOXOhWrZ8CEaP+mTWPgZVDqvQw9oKLiqopmMaoG6PNg+/S3xhIHBXqM2l7gz1C/r +M0Dt+VIA5vmXQ0td7CLXt7zxlz4MVW5sDMQuWChghiiYylvA9OYo0gukprqnE3rc +uV4bhf6dOQFbF8ZclWjZJRuU0p+bVbOtDcB4o5Tbxfxcj+h1R6k61baC/6Vowo7f +Ab9C07x+MIIz7oXnzIx0Il6mG81c1RjCFLGggGMWTIQ3CrzTBVoMcMuKeNcJyz0d +AF8Qv7rLJU/9fs09m+DTQFiZGdBaiGyHvZoXUIk24oRegZA73E+2vM1ZdYzAFuYl +Q7tUR1zax3pYPvOsqklEpuHJ7o6qsvvW3YWbHrs6JgKwkUGOSfDwArZ1CqmKlY1u +abWlQiUDpvTK2hH88aQLN7YhUnNutOi14aCa9boNcPOw1Pm2aPCTMEOf04dIg1zm +gAQfNcMmEzl/flJ3J2sf9xgo0L+dMqL2/6SyBes69qScxeHfpGXGkt+ia0K3nOLF +MoiFSgko157yO+0rmoWTlkAc2dGWmwFnrT+n1mq0S3MAYf2Rq4g50+2/5nRznY6s +0qosVUm3GXTm13d3EoAuCnkdAT3CCQ/hazpIOTaZtGyg3fXCt7kxqgLsP4zyKhUB +JbQuDf7vwNO/hRLbKou0hGmmvQNa69uNjMEbSE4XcQVsOB0XXetmjOwiFMnCzp71 +CAmvzFgko9dEGx4rZrhDhyrGdJSzGDKTSiY4blMTY3GIBnrIie6tM5DiO1JZJ3Jy +rLNTa0X2DI+nVnfE0RR5sLEWjuwmDreW1Ny4eRYwgNmqRhl27oMeD9d+Y1Da+MBK +bASK6S75/N474R085CjOfozL5ab+UuVySEuQanx8L0MuHH7VZSil48FtfHvxROom +4zVuJpZ4oD3bJjwfiCRszgyyGb3O1UCizL/oC0OTUS2BpJcmWq8DU2ULcEl6AAuC +cBYp0kcuK3U9vou0sxdfGv+h0Sdnqn/uxuu91QSiMY6mO59ghXQFmKXhNRYSV4fD +m7mnrvBxxsk06yg1L5KVamFUlFX1FQXnU4ieZKyrwzy1ouK4zi1PR95CfYCRpTMl +OQyJsdv3dDqdXJNJ91tq6qFEj3kzPuvv0gsbbB855giMpYEvJwQmADL12fO1RZMI +nZyd+Kg8NQeAMZzfIuo/FlBX5mSnQ5vjX+At0vb8eSVcnWGG6YiyVTFocCKXu1RR +zWnGLVLEKagfmdLgP0HHOuaZ1sqBW6gwNVMX64hU7/XMb4AFkBpY0vwoXiEAx05k +prRSgiI6V5kVKm39sQXOtHawQiZfWVgdG8Wpq3JVswwq7vye+XCXZB5fajIU5Qsy +RhKujKRruELsQav0jHyhDh4AVUY7OGwO+QJdB8Lz2DIESLITplXoMfoB3x4M3l+p +kidvN59QZN6QLxPg8MG6Q9+KDDiHxYvze4Wk2Gz+nWsR2hextpunoHVFP1X4xn1W +L4VE6p+BJ/x++K70Qv1fjTqwSCVN3sdu6LcTE9vgdaRy2CX7Va6DyYPXcx+y/XOh +93uZVUU0pajYw3PKANGWOEQJPM5kTX2FtSvdFMehD7cA4RtgdotpAjvcfJczY1qo +WLCHSigwZQN6ApDkprKZQv9IaOm9HqFI2zZlG+xgWhrbIxTwThq5BA9O+a0uwhk7 +rw2p/Q5rwiGw5zPgbn8HGqRl5XgmKcdligrFXU4FQDzslXGXEjSRo/ZxdTMiOi6w +qK0gzgjiAfs4aKdx9PbPCyA/QHz+t3twonM2Lh/WccukPSMRihLn4+kc49WIz6nA +CbLQuyeOyrFRK9iM8xMSurgZBWAWf47jdPwCWvP4GOn35Eky9+LPSc595o/O49y8 +SwLL74WQe6JS0U0LmF8mWiYHMdoV+Ad+v2Kpqdo9ATh7+Tfi8WWLMEdY8Zz7is8w +/jLWTdzZRPWrv/3c2VveBgya7r90/RhivrlSFt44sz+tBEsGEPmiUr7Senpoo3tR +DW8hBCG7W3TBjU6HtsAkJ6vRMXw9Co0pvUEePjSLMcOIE3p4+qTsJMPXk/dyaRjc +IRbxBifYJdaneIDrHWaMI9uJuX6ejMeQsAP75uhnxMkLKgCMaPg7Pj40mvGIzeyo +lIDOzkFwXojVJYE5Usu2kNR5l8sAhvl6K0PThs4kkokyzEIuHh/hmhYMBEeN1RYG +ujq85hfek8jLqEEt0ziVeM3NkcJdmE+cHmzDKtLnAI43SL3FfK5KX9QjaXyzL0oG +4A+hzQeP0CvvXlc3LdFXuA8jqleWehhuL1kXslmbwhfKCmfagi2vvjzAC830/72N +B0TX/5frxnWs5p1rlTKZEIsrgWViI6TJH2Z3jh2OTjfeL8XjG9SktEZKFYGGh7xb +TarC3roVpXP7tOAELHhs5Sl0BsFDCT7k/1+YavRryCQPslZz3KG4hzBz/M5QM8gM +pLNbpQqoZSq0Tsjv/NjvPKZdtlA8qkdMvKr1uPCGfQCRCS6vEKPFebkFjuaLx6x/ +WKUNABt5Ut4Q2NFVyvDu2NkkXQuQJpyYiZBbID5SPSJcT9cShe6QQ3kL0Uo32GzM +YjE/5WH6kCslPD57RMNQFJXkkRGxZwezjf/MFWJSa1o5w1k3MO3SD6UMe29019um +PBUG47Bijd/kjAB+oHhiJpyfnDYGKN0QzYlaYRhurodlrxL9qyEiNs9uOWB4JiLq +BCTAwf7sifsUT0O+WrXCoFJGQ7LeVNYYqbJBj1a8FeJiMG6nxmOTc6ipcvNDnvSD +0lrF2v1OlG3pXd3X8xyB9OYxyUV84/kPRPhweSKzmyqKl/rN2ZEKRQ69kMMR5pFF +PVolouXHOKuP7pSA4TgMm/xn2bQ7EtTnLgevpOpmBM+2MHjkGYGrvXiuyFw0YM3n +Ymv4gBX3j/RDKLQnP5e6Xrep0UokN2GinS0vjCeufJXq1inV4nEmJ3qgA7Dh3R5+ +zysSeck0jSC6Ijp3/L3/Meh/q9+sYIVTnT27dSwlwZ2oiCz7c/pJUIz/3Ip5y3n8 +AdZiLhuZ61XXvvyqE15Gm+gUckIbI5h83Gf+2m7ztwEAPPMzUaMXnmr9DGvo3Edm +jvollOh6dswSWILfvLIJl6Rf88x/ExCXRSslDVb3jIPeM53m4xkeFs0st8y/1H6W +a5J3hwuUANi1B+Ib3RJWRs3Xv2g6LmbVKS71gK7LswaqjslhXCgyqKAc8Vslu8p0 +XehlGY6si48U5agCERcvXga9pa8q7hdwBwFSlPEKNZJiJh/Xy6JYkRmCjEz9Vd+B +4hjRK0dA++Cq7+S7oM8ScjIWBA3pvaTHPDDi35fd02+l3ClJysek4A3t/ygV1zxS +XUbQ41Ns1J5YTcnvFC48q+K5zn6L71TuUtDVvQpco0ghi8HESPCBuDWmsGpmI8k8 +NLtWSUlQ4Np6qFNVHf90y6v+vWPFElEFBO9WtvikPUwyRWRhgsP0IqtcO39PlevQ +Xjm7/z5Cc0/ZQ4Ke6jb9aGYns/4VEDELjAQdluXh0rLPNN+n1q/l9Tyj7Y2lYoKk +QblRj4Va1CHZpiwbM1mJ/8/rxNgJnmXCwb1HaJ0eW7D6zM0lZ6MNOzZTYfnyuCYD +QHVfuf853a5MwzeVDb2L6ugktkwXSDPnA9QUu+kQKFpLxIUtJIiH/8GbQpgxQR6o +ZIG3cl10rbImmevHGzXKyWTqZJNYR6QdL7f3epVqtCclN5bpm0tVPwxnVwaonnYf +NOoi5JRpWa8qxByrltniWVejxcbxVzowS9By8w+VgKbAm4rpkKrp57VE63DQMttq +uF48C+F3Pn59p8ZdX8FITpS/cBBSUY9oNGC2bUJWbLSLGRBAMN3vQPRJYHTfs0Gt +4i5BRD5CnGCJ0YQx4myME+j+6RIML/GvxAID/8DPsvxSvIxbtzsomgxZ4SZHABmn +UzaZVB8vNi2zyewFBM2/8pZyGWKKtVq2ho1DX9NTD9wdyeX2S2woXbubZZqPd94X +yB+j9m3n2Zf7Pz5lYhrezH/Z2siHn9rRKT+TLiSwuCH9URqjkjgUJdEQ1i0qcI8G +pgNV/nywVcd2dk5oCSeB8KouRVxoOmxpx83dj4EXuS9KhibpnZtyZGX8KgX3Qcay +ix+sEXsCskIPjQ3gCTbd0iJXrYuUU4Du5LQXwk+tBTAtr7sjiO3MTWT+mduUL8mH +H52NK5r3CjejK1f5y8qXkJFmiUrrVvvSZGT7PGKv0tUEZgIj1FVheJx1znzK1VZp +FeAkwFd+tcr6RDRuDG4ktnl1iEReIaTdFj6tjHgWvPN9VlEzRWwqLFseCwhPg04J +qp+W7jjVZTZSfPhY3pHJUw+RkyNVoIB3G1yFOspqI1UqgUKA/vQUo0y+wUueFWb8 +9sDzi+tJ+F2hXcfTGD0GOfJc9IDTqnn6rbYRGL3mJC2ckV+6IIkmQ7+DcvzecUFY +oOuovBxwgMa6Z5ZUwTvJCWNtiUIg1SyN3uGQC+9NhH7BJhzE0cwFw68D6EgmPp5y +wrnAHYbLCgOOypEk8pMUHtPlrXM1VQ7/kd0uQl1tJdO8nW+NubC3p3NdiEc20y2r +lr3NKdXmONEDVhmrUNSKWlg+RavWhG/IcgaO1KU3zyA0YvLndnT3yJ9+wAQhNwhu +eQlgRSZhATCnqunMbeKlBY25c4Ss/oLnj6aDwiTr3MwUIRWIta/0acg2X7zSdOm8 +/p0uP8Q1bj2WFVVz+6JLf0eXcWIR4yt0MaTvEdpAAcD7JTd69dvE8s28eJ1x+Amd +7kBnXogXbjt0MiLIutkwxvQj+UQKcdVq0txvC9MSgCCeW9JfZ7Y4fRlHi946DDls +v6NZP9TCvJ8XAAgcfppQ/fGDTqi6ewzcmVRJ+J/zWFhbM5dQA5S+pVvG0sShCElI +nc1WYGMqtkPY5nFdXOxWp2ErffaoDguODSnNNnzqTLpY8Leza0S4GcGFFJpzf9E1 +Jf4j9y0YXUkLN33mbXKimjOu6w+Mq9T8PGx7lhtvXwDf0lw5QOWCaZnyLGM6slbt +6RcoPIyeEusSAST62kWyjEoAloqJo2sXKVMBOK3S3kmD9gl99WWodvG5QrWFAqyD +Y/+bwa4lN2I9CS+gWho/wlwcuyUMrpLM7sjPG65Q0Wbqy9KH4vJh2bIvB6ZIP/cQ +uo3Dav0/hiuIKvvIrClBn2Zn/Ns5odbaeK1bTaqHKoUkbf6/y2cP0ZdHFDVV3uuf +MIpBi1K4j/hQXetjjg7QJKMuqZUh7VBlfkwtoAVtFb80aToQEuzaT/J/a8e2OmCe +iRzvrJBbutTqTfynADAuUvvRJynP6YZCfrp42JVOqpyr66aQ/LX+bVwl4UowQCcD +P0z0phgVPeryyF2MUFNULTvbsNPi1e+kaXYbeAv3Xwtnef3lTJDFkMq9RHADW7K1 +ZvNzrk26Qr2jQIJPxX70tfyUGsUabEURtk3TcxHZrLFAk1nAq9+IYAH/wXDscw41 +YI+/SEkPcU6+6u/cqvFLUvm/EHP3hBj4u7ozX6ERGuU7Co63TdHMpqJJyKjB91Sz +IoDLR3l9uhoLUCGyXNLSuk0kny7k+7UUhV075XQkOV6BA1FM0feOMPrpFEishuKN +5yIK+XU3B7QZsSTErRjoDD7hRW6O2tuM8Wwp6rkpvhmG9zZ9fNZL7hxqQf34IOSz +2O1wMlMt5Ges9kM6dLyl6zF9kTziVYL5tT9Pj1wRMFZBknDQtGwT0az7E70SEVzb +3g31snn3BwNzjpqZN0cacXt0l8mT9lxCEh+tjSpJi3SFrUVWS1YafZaz2h+R7YYj +3IwxyMLDtkR9ZM8B7+l7Zwc//WYa14k2rVZQ1j5qpUIGZHj4pKzkI/IOeqGseLnA +ZtGxzUtezQ3SY9Ca2+tvUhLVcs2hL9kwXas3cJNu+GEftQ7k475EkQ1mlaghagvU +Y2lYT6W+y8UhSkageaP9BJUJhJ8cvKTqyAKITS5b99GVf4K/3LwSOrCNsG9efBMg +gjGdn9sEmcy/7t2ns2C5jpIPfy1ssp9J5ghOuSHjakM6N+O+sq1DE51OAforJF/W +PWNE2F9TpPyJVFpqjLgCTpQJBhl7METP95q5ogWNK5yxKY6RugPt1ofFL5z9cgiI +xck3twSsxk885/Y8O/l6845gU8Tc0qhxIeQ6Izo7WKK39066J/l6l9q22p7UVk67 +poXeEKkYmiXw+gK6xqMxGNO/3XNLVLVRZuBEYR+G3YhdafBb1kPoBQHRbSLtMPJ8 +wCBVJSeeXndBpRrr1ZMvA/OOLdMw4crvMAqC7MMvnhxAEvxhc+BHkocr+aXrMVnc +Zo7995NlE4Mj3g6Gmbu9qWpNyTe31Q6BwfplxNynTil6mqh7S8i5P/HM073JS6V6 +4OjGZU5tdDAQzyf16xkTLSVKF1Z9laooDgzxyEyTbhWH299T4EWY5XwdmvbLeGuc +eU6IHZy5atVl2ZEVGTCPaITodIqUkAu+EW7RtnB+DrPsILkkfJROl4bxJqDe+ML2 +gl3N46pVFk2nwpc9FlpwwmLFE0V289tW851rSKkF5djYhyGw0veYaySoV3kp28KR +TEHEoRVhd6W788zDt42rzbV9t3hgmxD3WP096s1s4OZfY74KH62uL4R0jaVTpaO0 +hRJqeQslVVTPR51MKPmgKMFT4s77Sgf+8HvbV0zqRicDDUftAnJnCB9U/6ntDEen +oajjkEPzOGHOpiaU5Av5jnIqYuu5ZVtSWyT3QmJh/Ao1U4yQKFORgpu3iDZmgYlo +ZaOWER/ZQU9RF7XA5Y7FIp07TZ5eaxUE/ssrS8mE+LsNzbW9sjVNIIZZmZr/UsPt +zKFzhDr24N7QeoU1G6ERGThfJ6+7lEIip/s8uLZYFDF8ufUxk1TZN1Mlxw/x5XSl +YI5ugiK4RcPV1igxUUP27/VZsP8rA0YoSJdHnCYrADgk1MM6piifpFyVkQjKS2BB +N9NgOFc4KMf6/yNM5uEfNJVz1KKZu0SfpE8GUpIrfKNtrVDrEZo7ecjSBv6jobo7 +RxYlE3zJqA3HhAy4OzfCdj6AgtGMOiPm8i72LwQ++5YAjXlZjs+o1FfED74WoCzm +fjwo4WY4SexrjVm59NcW4CtydN2weDvz4HV3Ldao1hXkS9dvSe0W525QbegXh8uj +R6MU5BVXFjwRI8lDD+Nm/mOpMxL/vp84PpDm9X533bBBtF8jdKStAuPjn6ZamA+X +9SEbKUEiLP3rTrpN2NBGbJD4b8+vRHIFcXzpXboueLOlr8x9hh9onotSorUj0080 +0jiY4P62/YE5WzjcnHJm2v+x/hbM9L6w+FLRNEbbQIwlDvXfpTKotCfcT0/Flxmd +C7MYAr1ulHlr2vkQYeB5Xgu0N1rAymoDIuhSIrLGBX+SEVMKVHUOC1BiBGI0nW9R +5/wbv5pA+1iak9s4HQ0D+LNKBuWi0WJrjFMVMHW0PHBfenow0a8HRMawDJjGp+7b +OUJWx7Y2V7GtzP/AI2M48Sg7LpSEjUPNMn0W/ISxGf2K72GxosheqEGUnu1NXvU+ +dC/Pmc+8TR/i0hf3ZIlmLkOMh3y/ACq4rpApzmJXCx6fgndnchrDXLqdDt3kjh71 +nEL2DmHq6goWbBXe3lvmKbPrlwLNnU8fPskQcufhGGTUMqQD0uSTkCqtRqtKbuLG ++iGH9wRmkyyyTaqmt7Q7SzM//+Tj7hOIzlNj1MYijt7KsetO/zJy2BzSpzN9JiAA +un8BHS66S0xqN240xo+nENYeWzMv85yB9mwNzbMxXcCWvCArUeuoltHetGesKCo7 +jPPX7EYI0t/XquXIg3e5byYPGa8/108L6KEpdAtWCA7eqsXCDgaDr/9i2FZLQKfg +L0FUx9hjfNCZ8BovvF/f3bi/uVf+NPVftqY9hjsvUeOtlmsCDZdG4sDiV4S1OnMi +W5V2gETyeXBDTzt4BWYfo6Bn/eAD0RXB00vDhHahqyvnHMxVaxrjHnJoN0lzdahf +JSVofyVR9orWXBgsarjZwl6IT8wfWgtHcsXTbYspIE8OKUxaxU3EqWShjXNn1dNg +EcAbG9n3JGwEtIufarOvQpkuSpdBG3GoCmKLzQcAn+a4WcfYEUSDWOJsl9H8Q0N+ +LuhFU/XwC08+sXkmeCwbXxVGzthiynnKrLSWuD0irI74g/aAQIuchHAQPO+nfehw +obqaeX2aPAFJbhDktT3i/UProTlvT+fiWrgRSQ6RyR4ykTmTiiDicHEwjsMH4xsh +QdFOQ5CFpV0DRdnvhAXl00iWjFRnUHuGTqIGGru3WeA9IY8ZsqvanFHfdGDo60/Y +5Bdo9C8BWbAIur3gE9hKRA9pL1N9Tu44bKXGydOBwlF0OIIR3aJlAyyyVN9ZyKZ7 +2Zn4SrLgduYbOHc/X2lUPIa2/zs6z/kbzboZU/RbD8x0vXLVu9HcJqRofz+jv+tL +R5pVW8ib9mZmYZr1ee111szXthRPfYuwyNcScRJfaJsa+wUu/mEueAeWNIKirK5e +9QEgZZcCptNjObREVBJm3keEtE0wb6Z3DaolVTEu+o61aPUhnykKRGIRQtBsyCu6 +heBzhPPtt8sSRI+kXVj/ByRqTlquRl2ghtJZLiEGEtt0yldG8diEnvEhkBJHPHkm +kWWoLWKesE88owLi+ITBIUgb5J38Rw/y8+Q665BWYdrBTTo3NCBPF4+rarmjNHsN +lFEaOTbCdWK7uIFjOWVLgVu4v11Kihi4x/Z8Zccsdk0pOR81cmYuQGE4H9Y9WsKF +Nom3QiACPhgaWugvBpkWQXo2ai/+1bZoobfsJLtoSvL5TnTddmarAXcfHpXnmVVL +V2JpM9S3p1NCcvxdRX7R/ddXLjsuwpfA8LgzDxm1jZLjNAoDRmTMH03vupIqm1JH +zoS0+pZoDoDXVGdSf4TubgxUO039T8fxj6J64hlnv6DP1B9YIssJaMrCWpixsLbs +nTFitEjmpkvqifCzTt90004ZEskB0YAi1Gzt2TleGliB83dHw1atOu0XQTfEkYYR +PHRaua6/GRrc3d3MukCfhMQ1oJ+fEwlpUUX7jeYSjFhHyGI0SqtLmwyo1ffaHlLY +puZhIS0yZfL3LCD2Q/scjrBu8Mh6ZRao0xOyZHVNLVa2p/WRbnTsCngoTQptK8l3 +p7JpKH5hx1Xk4EyyapHLMfJ3CLZ8Of3bjT8FgYVtkVFGHwyunRzvT54JPBupqx/x +f2GcWfEW8L7WkaQwQg8MaIm43dEdCNZjyB8DGUluQavp8nmgXOTb0THku8c+LeAX +yy1oZMmGVlSfRt8q/CXDbw72eONaV8HJ0IUcJc74aMH+faF53h5M5NFDOKWll8SR +jJAnUBmUD9OTSnT/9RPtVDS5D5RjPbpzpJDy9ucQBtAZzX6QBw9iRqlQCCgZuM1o +F7DE2lZAvbUo/3Owlj1QgWJcyBnvvIEjAPX9UX2+rr0Pp8Ck0GJzTjxfd0XyEYO/ +XYmvMFF0pC8UqhYKC733EHAW/0QgP1u6GVZAhw2+cTrzz6H1zDhHvXRvYVCZKNXf +ZIzRuaevke82rigBg22aUJBFAN7ySEa6yRCXz8uydr+sw8oG9V/hJIul77VVywKx +J+YlIqowDiM3h6eacugwTl4h0nMUjN728OV0ci/9pkRuGeJTO+doAGLhO7go2wpx +sR+J+m9SboftiCFQwLjTPRX8OMq9HoYGgkPC6xXJp79N0gnWzxO96oJkJAhCX8Js +R4b09JHvQ1UtQjMe38i7cJH7hHQwMUtAxJzQXgghXBGRGr+jZv22t0RdqaktO0IS +4Ruy120buEdFXSPegoi/zX2v7Th+EZ70QGvM3iF713kMUMwVFllTCUZad8oxYSg6 +l4ETqi44kwLwuIzAe+ffOFe+aV8vdCnwKsai4NVUYosNzYFottVuvGiUVzRd9/aZ +QS6XOwFUJ5Zg6oImL2KtO9OXUgeZq8PiSs5ZvwCGEO7vraDpD5VhTEbxD4YiKAzI +4kTUeKTm77cUWt3uvecuqhJq7Do7oQvzIm/PFwcJjy6uI7e4MPJlulbuy3UKMLcc +AeuuRXsbx8tUhDUqd//UAiET91rZTvteDwWwwgl5Xn3HfgVc1NdS9dCmKFam76Lt +8t8WKzqj4yncQS6MHaI09+5kC5zKuQkUV22AZtWC5X2AiIJIa144dEgzK+zMU1vH +SzsRpJhdCRMX/PUbVMqrMJkqmcKNVNfcDnEQubjzwsF+jSIkaYAVlr1dNUdwRvon +vW5i8fBoQk1yINjURGfOwAiM15wxDq9FuD8JHRWlvgjvfIL1Ob64flHQs5vvXavp +SMvTb7HbXM70gsrAZMvIK9hIbRx0SWWzRxxp51Z5hnzAd0fUC//oluqN0iDEJiy7 +j+0t4mST758T0LcSAD1i/RcrwQYVK9tksBlDDDaWBY9eTcjF0HeBJMqdI0iKMzYZ +u1DfwnS95QnHR6Ps8CcOui2SFrcDtv1BWuQu2zmiFenrMhm08j9CRm4MCW0vWeVG +TA6GhmdmypCkHM7zW5QEw9229qpU9c23hD/eFpMu/9A8yiwd33lX05LvXwKkc4mJ +t6HjTVOzfJDvHYx4FZF47A83CGuoACxqj+4LQZv5M/x0LlHWOBqRT1UoKoWZXp38 +LXTTX3v2HvilQo08zQljYAkf2ox+1FUosX5Avaus5mxSq49Kp77vgFOAeSbGCtcq +qs2LqfDznMwmEB0PCqIAljMB00VFLhVb5ShBWdYGlpbIk5/16qrKRGuQdC1dSKhf +aMzFyZ0OvmGqxH9RlIua4vib1ZLZgbzHRkF2pDP154u1SSO27J46gX6JqKUVATzp +hptAaUWNq7NkY1aagte51oeqUsN5SlNl/l5GFTIITY5v3bOdf/YDNNDInSLhNEh/ +6obWrTni/FU5KY9py0mhNDEspXZtGHjzhkSdV/DKVabyqvQ1KjutkmUlZFx/lwot +XRAKvArq2OFcCoOAbevZXF1bKjMaGEJ8N5MqO5WsnP+ntdeeiQiXr1sOdAOvQ01n +/4FfP9HAjeYx+POGPj2QX01Iq0EEEt4Ug1WAlFf/0XbCjol5lu/aLFClNW/U5Aya +B/4zW/ATWsYvvGcZMV5U5Mn42ZE5JFeM3tqA4JAV0Orx08A7neJ9fMcofDG5BkLC +W5vNb3QBvzcSDPlSS9IyBWb3+pPNJii2EkW55WQ+pcdXVNUB2lygOW8SW5NTLho2 +vM3yQMLq7BfZjx2DGWDjW5Sp0GWYlXGJgKHBRo3vDugp5MiGhMTUN2QE6QgWcDNt +F/snbfX+gX96kIsWX6pgIZq0dKPMelNO1Es1ujYAJ4GSfh0MKA88jiXIMD0Yh4Tk +E4km3pHdSsh7Fo+n+3NXENW28J2p6U0rzWO8ddJIZvwIcER+1VWUIZBeRmx0wW1z +uVcII9fJZ/0rgXjQsgSzzr8Ki7/ZphoapiuNPXSAfp4HHdW0pJiYMEPpDtEMusO7 +wArBHqO5K+bud/APsOcqFT+g2sxbWavzW2pZAmkxLCbQdb724W0214/14s3DCEs+ +aC1iNe+7+j0X9AtVopCZjf37i+H4o0ydkwBrfnLlj1F2bPkdc5EzswW2Uee7I5v6 +Eo6RSbYm0ROl6Ckzs++0e73G/RjRv4X+XMTPxkfUrEfi/NXa8lPsCDFixtI4v67l +wWAuO1T5+QMNY6GsphXTYZho4GZa3d20vb0CKPiaXCjODLH20e8NhUVEoAxoEAft +VTg1GXVciXQEnh1Wo6LFaXyr9eZ31ObfrGAeF6gTH6xCOGgQklkV6peeI6W/WnvQ +J9P7ET7jmckzuOtSY35etGoK+a+GP79QpZFHewhuFRLa6eTy5/bK88mlQGaEvUpK +dyRwE5BIb6QtM3f/BEJ2r7QySWiUj2r4qyUvg0uUS6tRIHwSSFAewckw5tM57jKf +7kZbz4BDQCfUI7xa1gMVzGWUxVIQJ3+y8+zgT6XVSvWGfx9BJwWEY0XpBON+c4A2 +XboH/L3+kBxkWAQ9QjqkVYoGwLumlon3jdkENf66dbkfWb2+wWMG4bIPKVbHBUlS +10r756lTtFy4ZiJF4Hqn0SdwD5We2WXR/tJYqMyxaL8tDF8XDcoQleYOBFe/BEpr +az52bFVns2yLbbnI6IUatcmdWDsj5GwopAC1A6ELmlKnBiHSncn6WDyCkWbyBCEb +OWKLJ7AS7bgcS/+wYXRJR6zn2zh+/T0KvMnXVuQ03Pcebn5HAUjwM8g3Ly2UUGTH +QTaVadeejPtMz8pu5169TXb4d5EMJyJEowqwZ8er6Q5KBJixAt3/IIsXGNCcX/Sw +ZQujnSIbHd9qR0ObkfCOZN3+zIuIIwNcIlnu9KxIrIvdjQESI9UzVLj/2f03AU+n +VVCUIutZAbKh6XeKYStOxHCd/T8X26HOTw2gwJEc7yVEAK8GV5Ikz/lnxDvKtCE6 +ICiXeUFUNxFlhP9Bi2NiwSnmQBiRVNaSOEoNPV46nRKy6BjX8hhaJU0yUDFd9g9a +lWwdgdEpDdxBOKoUDzl6phJcrcVWiEB938uiQ0cDRAoBvZEqkF7sag71M03sM2+L +kUW3S7+SYcyFXwHKb7EHAhvloOPLgeA3tEFpr17fyUr3lSewv0jFvOnJqG28ASRk +0qyeOS/OUL/tLzlNMWYf/bY07PFi6XDKxfoceJWegnrTm0DoExXs19iVprzAXKcX +VidAwAomNQuFShRRbZWDRPCHxL+5DxRWdMuIP1v6hZuAQfgHhPdOpoppqtLUNmfg +xwOJO6poDRhfW61hyDV7Lc+VEHAsbjzeXlQIz+zwAHaIen6fchYPaKnqLaTCpsBF +41mkSl+fSF3KH5VFUVspNTR9jcn/APx9zYyGBSvO96vGqhJp60AFkEiEzMT0dvt9 +/yRFfbdHV4a4fB5rPwItMEBWahn8QoAoe4SUBYiYEK2K2nMfR3M1IrI/tYBESevA +HNU1aCJeZ37pGsOyauV1zP39ksS2g7grYwpdPF67A9HRpjEFOz5ptyKqFO3i9BIM +8PzJcxz+duC636RYENdvs4zl5zJUv2kOTe0zQvEa775jFxy1J0PR3qA9rA6WPK9H +6t9ZwPAgo2Jo9p8K1Bu17v6oq2hO4cVVfzV5pzxu8+xKGCZwqoyouMJiVbqK7RW/ +zXw/n+NlJ8E7vawIjvphEE4cgXU8Cs+Ln4J+n9oQR16mfRkncLs3pcIbLdIjdo3J +ReU8TqtmPbGaCbKm/IycOa5DDN4s5uR3NGV5bQ0CF09iShUbrPf3nfelthRUf+OJ +CDlj1ViIguV/rnxyZo4ryQuiJh5ZPSjNJ+i6M0ozA/36HV7SSU7n9WjekICaDYs7 +bLUH8hdXmTHoZu3H+KjSBn2bfgMfyUnjwHpww2EOiCRLYjV4yOZSdizeS/CDjEaw +6pQ68H/0q5QdBD8VZ6jmPZTLTybLaRuG0DRZNvt9FCkEP0lUN3ad/Ch9+5Afi19n +owvW6P16GXreUknnsvdUCVd2zN1PItl/YHznyNs7kdiSAIMJpDB7dm6ZchYWt9HZ +AN9yntIlZ26tITq2npJRSje+MeQ94YB/DsAnGqzfeYYXnXVWLM/vcEIjE2+Onogo +FL9VfWfZDLKDU0UnFRTgndxIldjxadyo5bUrAm1VUzIbQgURAtWeaAoBXxM8tY8W +PbhGhx2hjXZx8WXrzclW5ZRDE2s31+uESD9s89IqBACtC7oE1jiIXb2nyYm+Y+BB ++q4QQKVLCEHAv5RNwV4R41dTrfHip0MYnL/sFFxq7EMFG9RmwkstoyhTOndnX9N0 +cK09TtazcorJG7/KlLhsgZcL/tVosGkMCee6jX/LpQS6FX0W9wN/Me0U8I4UEyEq +9sPo9iNhQMqzS2U8INmHQX8MT/CzysGbOzlla3QKsDthXZ1c2Yrwt9HpmhZBk7If +306klC7RlmXgfdYQ/0A3R5ebWL3Uxhh6cVj83DQnaj+uDBV4BMBqJPqquwTwd9zf +/rAjWKETQhfjH8l/f2iefrnV+nRMXXL/Rfy2zhFvhibQGx1/lBiuwhIqMi4Aucnj +68MzKIHGaclJLLJI9F+XJVV8IO+vk3nNtQhR/wPuXa1fpL3djIJI0CRNYpC5xDq/ +Id5rdIBkaF8+2vkdBTOZ5b7lcY9fRXg+asc6TO3lDkku31/l7MMO8xjDv7dDMgOR +qV73GRPm7dQoG3bulWWlL5nFy6YxlBlVytflGEOL8E3lreryZVdgbdJ2GNITYSFP +omeeinTyAQtSmqEhVZgZs9SjNAKQkeyCyBxh+cC1XcpT0BFfD93PLF6HRFscu5XG +RqWeslr+oaZXd+016B0xoKpQRHbzBprQXoRUe6FBAH2hRos5iYv2qvubhzSEl8Zi +qKiVIiJr2L9KwOgOXs3jqh5IG0U2+BTeB1Ycsl16EtwN00V8PfATzOZrCKH9s0YD +ybestfMiViDwx85sDV3/84jIdGg5xm9oIfQHMtjuKgV//rItVXfRCYxl2ZtrUbEl +k67gpPQfiMS6KIINtJ8fyTggLZNeAvYj/oGxnF2B3WWlxiO8FGAKBpYH3eyHh+1x +dw2B9TX8LOUUApZ+EZa4VopKxDYZkGgz3pyx0+5oTARNWBGnjnnrWfcCFrUH4AHU +SkPRMLlcEb0b28duQv/CZ5bw8YCSly2ywwFrsSFHnk1pNY4oELs7Ba7gBgWe2Tv5 +kchBMY8JBUzIJ5eHCCUmbbwF93ggVWeN0eXzLdZ0TLvFmQ/YnsQKolnVDmbecGkM +PrHYgWIlKE1G3vanzjLs1zVhA0fo0q1mftGBy76LxZgKYxw7Rp6iEZAISdQBsI1h +713m6xH/lNP7a5v7bCSIEPNiZf3r2rCZQuVGOw8X5ejPRUTGk+gcRlhzHO7Tepfz +/EtxDZ9ollBtp4JpU2NqrbEYyFktAVrtzwg6whf/yyXmd57KgYZQBl/9R8amA6NS +WUV6WWzjauHPLdbDSSKcCDKYRPiU+g8PjyG8MLcxY3iPA4nrFBIZqIDfY95Grn1g +NGH1ubK7pE99ENeb9IbzLaUiSgasS2fVRnIUKTOshUBpzjCLL4kS9YhGKqAxSpSn +FhBhOKLGO/qIdV5GrLb78xXxkYPzC4/OMA4lTBQGmv4zyj+YeHMswqRcwJJdnC5u +9FGxA0oqi0rOXA6WpqMrZC984qwZaRi3kGUrYG5vaMBSxkFPvvYAa6W9mo/xoJvT +5EgLWn/+zRg+eu/5AFcslG5j8cRpZleP8nybkwpOrn+l+r//Bppt/B+o7qXffhXW +vjtYZvB3dZI6VaIqhsI6yiQYCEny0J0jdON1XmpsMDZKSRfZ0O0sgoQPcN/HPmen +/FQCb4ky5HWEp7d/4l5V0tc0hKgMUY0e8F+OwBAB9qSpOQv7wdPbI9GqukZkDaEJ +IuJqSoB7q5V7VotCYWfLJjSAyRtv88mXwuAnXyidsUDeTIJtIZO9FgLfwgv+N+uk +hneSKCae0/9t6WX8sPOMgmZ2Mi3EyrtmpIUtz6zBtiOTv2+jEtCpGmn4pVV1XDzn +ljR0ANU6/qLRUlwabjdwsC/ySlLPjahf67o816EMhJkrSkOCN5qC53bKDCx6umq9 +vEnrqbBQbeO5Dk5PusqWpXhr86EZXRopGH1LAxsISO8UKE2s6FakLSty1utufLM2 +Q5V0ZnXp6/2kyITWoPIU45hlTFsMzPI4jN/UGx2uhmKl5Bm6J8V8xMpZhy+BHyYE +G7dlHrNsC9QTvVQUedW9iGynEBFTizp0gnrhBUF7tcG3X+y0Cq6vx7sLDKnSQ9rA +ZqhrCi7eyZJWmU8cqFgTn4jY01sUi9MFqEqRZk+Eh9Wuh6iCgISDRyzJ9e7hxH8E +gN+3L9b75QWg7cacb6bp40lAReYJgKKR1LWQO2SgZo6VpnBvexBkOhIIIqX5YG+g +/Q2MhjU4aDpED2pVFFD9HdHoaT8GwdZMP1b3rNjIWgF3wV3FbEpsDhSWZ5yMGjXh +ZD+zja0IiaGxqTf/YHShjGQbb7Knk7PO9j2T7LxXjgWoWtmeHRWr1D2FY4Puq/v5 +Pk+CU9d4Pl3z24mJTJ8TpA== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +n9rncH1gli54i44OkRckXrPS5/bYes/awIWcV3RmnEBDP3AcPLSKHOEOZge8ZOyN +wVltadJ2zhaR1pxa1g+6VALvUtvzm+YTBZ3pwQi49ZgPt5/wPep+O/POaCQYq+Ah +x7LGg4e/LzfBv0lRKkcuaea6bHM6A7u0nmr63ytA86LQEL7lABH27sO8NaE0/M5j +DqKGhEYFJSP2Yxpfcc1/3ht3x4Fqhlo+joo6gt+mQm+VUsy5T+U2YN+NQtNZ5J1K +XlAJoqKUJUxgRRd9KJhaVDOBzstJxb66ts5wP2FMr84GZrdw/QQJb8Z+K7VB/H7q +o/xuf13FxxHZIa1S404mhg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 19056 ) +`pragma protect data_block +mcGX/XrhhAetb2qiw8MmgWavoO4JPBy0CYURSItQTnxNSH1+dcurY1/Y/CgUT5og +yW+fx/M3tBmbrC0uCbS+7av3vxOPRXz487IuX0gNlCA7EratTXAr/vo2Sq0Sv3y3 +zXzacFO3Vf5mWRdbpCqje+bzLRpNFEiIwVeDMgBrIBxuP76VwIXxc2zjjqKOyVkd +FRpIfRbiwqK//vHW/qo7wiA53vo7VUVOpXeLgpO0FGRlXWVF3WLp3WAo/mapEQh5 +h7wkf7GxHfgLeLUgPdGyB/XnoBbNM9iXYAF4jT7ZAxQ2FH354gviOh/bwKjCRPS4 +HQu5n7ByQ4NOp1X+GrC20ltEyK46B04+BddIISK1ZlM5pjE1B76E4ztKVjOzLx/w +74F77rT+ImAwR14RmuYh6IBtDl86cY7e+UVXTyKgHtP2HkC5pds+S82N+xQx8mbg +iyvRu/MtkUufYkmh0uMu8dRNN9BGP5qk/KOYHvW9cSrfQh5Qke6MLiOdyyP+W30L +RRW1mhLBoR/ZSzFy73e9xrizrBj3ek9VWP0WVyacHpmjZ4+Y4bKpC2jxXYJNh3Ni +VSWIOu/burQSiCiQu6GKcSDNpvTWCAM5EhbRwrB0MiNAAWfmZtRZ5OGG4Oy+mOhD +LaKYJpYXfZfVZU2aXC62wWmAc3zRUCd2eFIP/NpoyUxdTGrmVL3FN25yzpkp92p9 +vLsjB/9QdmscfmZ90rtBoCZn1gxi9RSZ9m75uPELtoTzJ5objT0ZapOgPnv1a7Qf +WMT+A0Im1F6zBeeBZdgX3XzYn9f2gFV5Gq+vtVIQPAWqkG4mSsUuWKB2ikQCB5Mg +lkTYW5CLyhdWrnTJmmcAii5I1Q//peA9gYuUTbAyf8eJZMCn580n2fcM6XttOpdB +buMEuQsvFiJvNpU/CJFhDfHOl3O4tWv9vk8JOK2EzSv1HTOUu6PmVYUle8gmGXvu +K0y+k+3QCHccwe7ic3zNKvGHwYlLH+ru7OVBXDPS4zRBfpR9Qd2QyAjjgEBougr1 +6raEgViQyU7Fy2M61PjXqSBYH9JhqL+b9B6ILGBeDN9SBHrnowPHMNzTJlOC5K3b +xDqOfWJu2qcN+2wVD1YYX8ayrJHtbAFsYZ6mlvulJwENgVz7dtdl0+1JCpD+czA1 ++qgbW5vyFBs+4R7fue4mUIfKX7olm77d3wrUP5oByo3WDQ2TxjU+JQPzYBgggyZv +U8sqLjsFTpy1UI4BYny/0SqAngb5c1bU09nd0YQaACN8neyJa4hPMChHbIGNLBFy ++k5yJ5m/9e2PRy5D+qGN62PPpauF1vnJLdTNH6MzMKtLbaXIZfHD7r2OSSQUCcPE +EbFod5kYTsRNtQzr81A3B0xgc1NjB+u9xsEbmxk+0zZiIJZIOQ5oZLFk/YCTKRGY +VGfSMSGDDQbmaUIIA36TGfejUG9CRu5Bs2Y+690Jb0w4olFMYDIk1HUGM57hCTRv +XyhA0V+ronFst7b4VL17UrgsNM9ocS9VufG8u918BqeNJZ/tAoXLpXC82IUEHSS7 +9gaFZln2lFFj7PGOyW95AR3lAI+ZTq3/4b9I+4O6396zm3scgC29GwCITlsldtTW +KVKmO8ruK295oe4doSNr83wBBQ7t9xuLihrFay+s+ELeEGRpNGpk02yMfXAuryB0 +kJ1m9L7pLnEKwvi+b6zkCnLRWfENNooDMS+zHcdiWl/zs+yrem7zSROnfCSz4CNJ +EfCSRIVgIarvF8H3O7/bLdgryhxclAKPjSBnGes3rpBXyfh+Da/gfFpdrsb8taMn +x4XRTinfYCzyzWd4pphlpr98QvyvmFXJmde5bKSCzioSLzy9QWy3GakbXy2IUZyF +YFP1nobZzPDnQ8PUbbrtdzQYxKWuhZZlg9e9IgyS9hSCMuHYf22ikPtQRivpN+e1 +B/l15J384RuaXuKwPV6s/pZZkewqtW/Qoqh8oCan6RtguO4ilajlCeEOiBDSlubE +nlxiNoTm09k/IEh+6Y7/xSV2MTgZvh3yB/lJ5bAeQipxFXes14r6PZ19+d6zDVV0 +5nl12crcTBZnswcKO0owTR3Hk3kG56dUaOR6u45hZTjJrynn0psFUzvcFDzehIWO +UIvmp8wQZcHGphOVU9NxxfnL+IqqjHwtE2dhtLn2Sd+zbjaZMdsIW9m1fDMMTvrW +sbpYXjkd087wTQLuX9f1lz6Qg8fNyvsh3zuLT3sZKTbyilG7crcaoNLdJFZBzqZk +uq77sxirhL8+n1q+w9TAy5p5MLr2TfAkkDYAOWZKiuo1aZC7jKp/R2bQMyvzynIL +vaFmuKxlGaW8mEhIta02G7ki3s1Q927YY2l/dO+JiVxDhpRYwIIDRBn0nUc/0uGV +Vi9bz7IDbHI5yeN3ocTa4Knz35nbO5U/mWxegeyo8FcnlPv2w/vdMMMAt+cZthE8 +3BlgLjIjv2gIeErmyzAi5jaVpo14/C+oO/lebHKGstvv6JqXYeeDAM2vs5esPGYb +ZHdviVTZseZlmEgHtHbSg/WXxnpDVZLZiu8dlEDheo+RPGlrtH6m9KCan9dE5F3z +VWhPa9AJZxo4PYtLnxkk8rYn3Yxr3srlQ90BDRbg5xqgPmIuY8ptzuwQnyjI36n1 +RLlbry9eEz3z9jammPDLUOnDi9TD4YoA/+0ZcFfIer+q7+Lf+vSrz8/ngfUsurnE +ZBOUvHDptUJ2LJexc4oypXHMJmsKF+2NZLbWNQk8s6IiiNdDGb1j5YZrN0r/6BxP +vdfp7JCTFQYq4mEc9mOU25VTsUERWS/OOI9o6NjJPs47jqrqqACxDKaAEJAs1gHC +R1y5wKkYB/QBXJI5o6yQuPwb2kEALXe68k+sWiRI7eFUhBIfJXoiep80MHk9cmq6 +ZahY+VMd8y20Gqdg9p/Rk++1LaMhe+woJM5D+SDhkwx1om1XOlWoEMhWU1MvMwFT +2RZuB96JxrbaNDvKC4gj5npVwpZ9huEPbp1P1THYaoHMPcuTJBHEr6Q0FmtXOkbL +dXczKJnF7236Tjo/n3+dgAth+uXlAJfiU+KRkpwjOLeX/hnztV2q9yex8VQGNSKp +OW8972T1q+Kvq3yHLn2/uz/qqCbp0NJIIvA4/XM0RqokYRVQwLQ7QEtjVbPYDndi +h4ZMPHplYo3VM2Q4wJEIl4enOnbuI1Fxi8WHZDU21Atd6kweMPgZYu4+MEL+g3Eb +OP2M7nAKoTOa6209SkF2FHgkTJOXIebkkRdJNVSJ6hb+9uZYQh6Yko1YXB/9AYVk +vcBD3Qh2EKcYfZhRG3zEdz3ag+tBDTLhUQ9XOd5hYwAAH6GDXzL9mSns/yvigYXK +bkLMLGghXRt5i/6uVY/6a1D/Dtkmo7gwZxQ1d01au80JPfDtyn+AT2c+vmzlMj7J +cVw79INKkA4JzndoGS6Dp3oRimL1pvqH7jpNYjbExkdg+nUbIyktBgyTU1m//veY +5adl+eec3x3+aeMw38IAD4tThtTOCmxI1otYSX3F7TRzsHTvEVM7CAiJ+7nigtdb +pYCHoAcqM4nn6ZHGzjpR/bmOO0f55PojGPLIaTaEOduG+bUBMNVjx4zdpyaS21iC +nhf8jsiEBDv2vHJHSGfQktnKeOkK+AtARZIgv9rUcXtnZdOPIEm7uL7e/OunHIeM ++i0LVM20oc/ZVoDyXcNXAPzXfEwmzG9au3Ku2W6/1frtBIIxwLidj8uxLSfPAp4h +FhhzT/0ejM5ZsIxux7+rYGRX3KNCZRBmhEqAEXk0EzhwNxiFVkFM2xTE4TuYt6Bz +mfAxSm8p41+pLLW5BgIvlLEUTpYrkJRFeEXcJ/xyYNoQ63fuX2C+SNdEM7oOKoXl +/tL69NAGHUlPXkQay6eunWtmQnuuU/Bi8o7UdrxKywq/qEGV9tSyGxr2XrFHKTYx +9iJQ0ag4nh86x67gv9gkZIQk7Xz7cqsFYMqrLD+1Zm7d5iyb9v4gSI4GpxZIp4+t +pyYRs5AsdKOaS+tjJnJgWE2CWjk/LTpmfv0QEcMxABWFXpweL/O6OD0ui0sBC4ed +j5/IXsx9nq3m8CfeiAOTdfPB8xlMEJLten60f0YmcFYMDaqmgZcIlpUiesZJtMAP +pzuv3pvtZs9ds424u68lho8TKsSJ1eWqXnqYBJIeacvp3N/HixZtBfp3wB+1BnR1 +kFNTeVyzpl/h4RrNMsh37C5JL813iPjiKvT1iVzJ60sKk7j4mZPlcw4rdoodOpGh +ouukQaVPnR7AgItzIwJiAavilC36oTetkypnV0Vne4Qy0CHVGqDwJEIJ1mazaR9s +rySudWJZiDeKPqeeWoZC8SE4PIbKsQ4BHjKFbn3O2Ap2i8Snyf5RWKYjA0fUc35b +ARtbUFnECb9jTYGELA5lwhldN829/VS0LOv183uZkJJ0imXXJcyHwEqD7d7yJtsC +ZLrauGokIgWeZW8LwHR4C27uuzMOe/oYkD3eBH1qlCgrn9aLPurUqvlWemb7KVBG +8/Q2IEpGiCb+5E3yIa1qJsHfB/B+XLQBwLGoYEnI0fHOAU2Oqsw1nouZ0f3WYPeg +0fgool2n438A47ACE2R2UJF58doGuG9Yz6/pdp1QN7NHhshmFBZEIi31OWyy7s8s +4rplelF44C9FT/gPYUxNGpmTDSp2jAF4NtFQELImkxsiZf/ZTc1dkTyuOkFL9/J0 +vvkhO2gF5WJ3q/7JZ8H7tpG/49jw1fsmU2Nx3ktEtcGz84MqWOUSYrPpFoN1T6b2 +MIJ0psPnmZdwo19azJEN7pxkLHCPYUUDcfGOJvl32rcLbgSZkmnEnqMmCDVJtngl +gamMBvDneARoot9R/5V6s3gygoXVMVdyW8WPRtoB5RC9PnbduL6WpqauxNVL7DNm +ScxtW6Bm38OoopM0kbqCkWnAJT+LL0GqMI0QHU2XxYGqL1WOi0SB5N3PmoWy/upA +c72y4/4OAcEodJ9+J53SKzPbi/ziHVG4E98PSUvoOas0AE8cUhpsRLls2S5J3GcX +3zt/kYzZUkVE+Ro4eUen/90dtOVsxttPXNzWOXOrhjrW9p1fLZLoL6v+XdkeAF2u +32imTr8vX41JDKItYu9PboFNmeCqhBxXMnQbA+B94v0hW97tmqTGfoasyenM8Qiy +DErMKSZr7lO7uq6BkDuFyYO5Z5sHM/rUgT2pV4QivU7Y8I5lTiTdb5yJp9YMRuVA +S9GbtLyULfNAwdYw2x9ITAsHIElLpdonFOO14ZG1UqLlPSo1pq48pVvWooXQa2YH +p+giniNOdzNtY5Z6TcnsTyitL98In9ruxiJCZpsT7SXko3Gbbwd6yx8k9JxCu70P +1t40Q6WjFCZ/Os2Rw5U8pNo90MXFX+QgKO27jWAGMHBOYryux21xl/pZdyP9cya+ ++vDS4hATsUzxBHuJ2A0x9+fhyFM4ivd6TD4BPrcvvnEjdsAtOimYHwNYWZWkYlkU +qvA0WbRBUXV1zGyPgoyHCjIvijwtsg8GwCIefJi3e25p2VhzpWYYLyAo396fBAXW +HZdYly5YOBSf2nS95+YwWjD/4C0jGDyuHzaMYNKvVfPvoricGPJc0tsO5bvjoOKv +s+04oISKmmMYWjNWS9ZeGXJt4sDrDldOq8T8YG7nLFXU0R4EeZYoZ1ZbZ/WcJStk +l7+Req7mQ0csfGiqcim3x9dRx+ZEBMJyMUTJvXeg1T0cZm8ZcD1DyRi17TP2KKDE +mLoi38OjGdlquXJGhXpSR9HjzrdbtBoP7Pch1UDTLUKDhq/cK2Islj6ccF4LwtS/ +oQ4tzTYuMCFXNoJody2klrKxP70+PsRQD1zV752xF+V9W1SVE99IwbgbXfL0umrw +U373T6JmTEqqFtKzYcPUfVMMTqH4jqCuMSLvBwiS7OzERDHUxpTRspH29WRonY8m +5tyjdEAAqu2jH6snJ8M43za2cnaHMZWan/Yu7vFXafVYagKUhxIFNPjSPq41jCDg +rS7AGFbGMRqqXmgFLOGSQQd0hFzy8dKVSh3/HseMwPNqUyDfyOPB3wyanBVKEo4P +jtWoJOKl16OJWmGHzlXRIxrrl4HYNbcAZP8Gy6YNmSV1EgnHJntpl8XgVXwcwL0n +GWZiuVoFwL/ZpYkSHSSvyWCK49nUSZZ90yKhaLNkAl3dIHu+EK+ln69cjd46pJAc +pUZCB/sS3iTQt499e1xV83pkYtnRu7f1BWT4P2kArl6ZP/FOd7RWnoJueOPMJp/x +SAnMgqBPlJwDqBtthC+dB38yIbStgNK64+/EykAoXe2UaytAqZSIF06tugty2eM3 +pOcsYjgFBtXl+fiN5RxUzyEhBoVKBsV6OAgI4V4Qjj+/HZ51/bKIpJWwQHH43WHY +UNIppDpARY8ibQRMRJqYOoEyEzayyeW79t7PZoP0DGjXAb1p05lgiPoy2QpFvaHV +rhnpoUklXNpbWh5OwlzwZckupIKdT0+jPZVZOfK54Lw8gmgC6rKAA8IhcugEw0+w +SW4vkol9+yS3uMPGBxlbcbPgC6dtqZstrrR/GyK1GrDiQP2IrwiXNICRKNTjIQSp +OTKzBb/MpNHWFGnKU8p6q3PK6JOz1IJWyCKcK21IAVdT0VbAu5WWgme3dnad06Ie +dVF86Bax99wQm1dNtnToHwTEMjRkiE6s8reyRHIUPD+Ax6EvMUEgzaJYli5Xz9oC +tlgKAgTYVHge95NEGkYGMRbb0xuJoAe/yXlbjpmg6fomzsfqrocMovfN8TOVysli +71GyBqtmWlnyp9y9P9WGSJQBmNSxJlYA1ZKdw3LHR4gWAK3ITlTlZZl/Gefnpg6k +Ib1uV7/tQpkTnUInttn6vORx40NnVIUPtqi3MgEWYHtaTFeknH9xOnuqAvEnZXby +SjPE22tpwRW1VyDIfT63vE/e3Ba12mSqCLXCkxfmc0EVUw10T9ejeNvxwhGrRdoT +3E2nsCL/6DvgKVo5qk3mBTq6W9XZK/2M6DrzvuN1D6lBllOype4U+z5weVcHQCCZ +FjaCAg9Inshlv/zMRAempWbK96mcxFacwVKdUmDb9GuVnshho74myEhW8LYqIWLA +3D80mc61a/phTXsyMpF7mkex+wNsHojlyESEjBZDZP77AJRHWAxeuCpo6j6Yk5FB +JKB3L778M3kwhdDis9eHURtnl5t26NupK8HFlvo5yZD7fgkB2TkaATN7eJXuHfS2 +KogoDC6Ps1HsHlQokL5eGahSXZG1NpuA9a2QT1vY1xp7WFJOW5zdU5VMj1wV8oPX +czwKrbdGdB55MumThVUKDPEOXyYMFw5wwMi97I9TNEUkY0UsABZgMATTq+wzZS/M +9mVuHEhJSxCSxlXtDFwDm0TEBxkNnI95Kd2jYyc08l9QpgZdAeCwcTD9WLJEn+pY +11qBiUpj/ht1+aQ8TZi4yDW0Z+uQAU5euM/oaxDMhxvZsTAwYegyob9hwLX/o9t8 +ezSZxlLBMy8ndabkgiVXVrO8q0XzYT2a2pMRl0CIiDjSL/J2crD766G3VB+z2tg7 +4pjP3Vpm7J2yyN5YYsLSszOZU0GOmTpLDEuf7jPDCog/HXNojAYx0TQO/0VJy6d1 +zsIKpMYYBs1W7d2+twYoMyIyEOc4u3upTemWUL/hoWJim4fX5zHdYb6NuBmi6nfv +jvnzxuvXE80YAt9jCFTTITKEv141/bS+yM92H+K7lf4SWckH3yxBesON7+svDM3W +78ZulaWsQ4XldqY/pWRXdkBV2qHN56YrG4AoOFgEoDpRfTEcIQ4evd7DL6RiOks+ +x5ekRs7iNughwFjv9SpdY8yHy0BHAI83Dq3VNNmfJ9F048LytyUFTlr95oVNiZ1k +DMN0lkvhy+lVTdtasGHun2nTI3ppcN508I18e1cOZmkkX4y0z1uE6zTXaOgSK4UX +KHpEtvpi2ak/2aEZXeO3hzk7/yXtKJXhzovXk4hDtlMWC+TWhFi+AFO9aCSkFK82 +1yLIdqpdbNE9WEl6dmLhd7L6BzABMy5ax4XutzBHWADLKYSBphQd2kA1EYcMELQn +ELaXgi8jZ8MW78ZqxnMhBWldV72j7OhpNJowMZP6beBy0vTdxfHEzcQlkmG3XJE1 +KAHt1wGJBIWTV4WtZBKTgfAnKziC6TOPNFeiQN+X6aZ037i27+BQhm7vJqNqPJI8 +Ws0woaaOqESShLgfYKvc695dbvUDbbZzHj0lslLqNSSDEBO1Fre/RmamB3PLyYUs +gtZNMVFQZAmeAXb/pJNabrHK9EA7ivML70wHGHV9J1idSYayPOGH8THgFqNyNCBO +rKmitz1ipnrZL7VURivYMrKAMYmR4yU9J+eKSPjyMSJITJqBzzQ4rgWzZJxBKiV1 +DAQmjkJCpwRPIssPkJjMjmve93rAzu7xY9LsGuR700tqE8573NpRFEzevkvBHkZ2 +z2pjoKq+M9OcFnED1UGDPMgHgGrjkcA62QVrAYstV26TgDxoEWuXyB/qvutCtj2m +HPB4eyCwOpV89tApFc60roFixy3Cq1oQRLNbSwB9Cag1pz293/U06wn502UaHrYY +Qi/LPNIsvRADlIvisf/Cr9T8mGM2tYhG0NCBmejZRkzZn7Zi43Yl0zNG73nRlQEm +TpW/SIjn7JvganCLbwNx/YRH+4JzFgiEF/muJkx1ZleF0bG/aSCAlM0pSwgMFLHJ +YE+ebmn754KirNkhE06WJokHzLmlU72+ZT9PJd2kzYBwh6TWrQ7mpfRW2VyNfSUR +lTt0yxS8ZuMi2K+KeI2Hroh5UnLYEAyYm3Ks3Rocw+WEFQuI4gfmRkxHehC7Nedd +OGq4iu+XL27AvehFb89g+/bFXPxfZ9/CYZXdsmTXaO4pQDYtTNINjppUBltQRZm0 ++QCO4fft3/vkdy3dD1J4U8jcGz7AqZMluPLqVhsz0xAukg8oAjTv6zBemdHEpkqW +BWG8BGKsyvFqyAoG3rnZXJGHICioYAOBx93xfxmaAFoNQ6GZjzvoh6bGiudFVvgm +VWH237O6uJ6+wALATYpV1MtF7Flsvu1IKq+0J/JHZi1RR8VawBj0/jfgm6JZCmtp +WymNx+4UV41WF+hiU8p+yH0i44kHtkpcPmriiy6iHvXhiMltHmaj+Tfu+NUmmAOW +mYdyiXoZbHJ5kXehPGizRK4hVHKZtSFGvQxNeRTeqCSz8t+PIt9hGX1L3BwzWDNZ +wd51PHOS67IgCwBHorQp2vlPIqSYPL+zo02aEUXr+OV1BsxxBRWfOpRcAtZDL5WO +0cZNWJr5Par9LhsF89Y8BQ1Z7mJxQa1ObfdzPsNxpAk7RfhwvMpdEDZI4/hlbCZs +ElLGlxhOobXIBhf4TwI8LLde4f/nbAvAjYQFQeHw1elEe1IkhlR3dzVk4iuaHrej +71uw96nzT4giADoh2aA2a2HgLkeEmxJlLec/NUbxFuG05757SlOYPdslFCuCWkLM +hqKWy8nQ399oOnVgLDSDf7gpZ9Vp0Quz5tcu+7k83lFVJKIlSQ/ujjlQ1zgBwNHH +UjZB5HzNxA81Lysq/9u8zkLaCO2yi/7IDImVoxr+O4au7onuN1tSaaodVOwLKwdR +T3OQQBZSZt8SrciRL3xT50UJBipgoL2VotKVuVBesyV6jMY8j7Ge/YQqfbdIOK54 +OPEkQeA2LgSCOy9TbZgrGgtbNBFzWooEgvCVqUtJbfQh7n8n6vzpqOERaaAJIIR+ +ParjmWEmmVtIZjswCVojqlauBJfcXSp6NyyXE7hb7Bfj9vQwJHLi9TjGmYrpLZkp +BOKj9oeXZrzZZtd7mWaqKIGxi7+NhEhGdY7v/dlntkv2xuzAjt29tRhIwwxFzk+B +Xq3XNzJUj1PBsKn7lW7gg1lXArP5zzsdMdjntD6LAfR9lEvS88KXqls8fIjcOT6r +REYtR7yk8IynHcbQdALZiA+uIi89F2VXsmS2u2VOC9rH2315BOxcRJy6mNvNBnRQ +g5aQov0LFnILkavo6IUnrepvi2X48nw9WNaUGlyd5BLipfuE9Tp4ur460Uv8VVvE +pG5Z8WmAyWvGhGuVqQQacX4Q8N1nOQFnhgAjz/c9csP0yNgyldEuH77NZUhLtD4F ++DZwOWBD1Vd5R3cYjibD10cyxNH3/ZMHEym5IOYz0t/7xbFW6sliCUsb8AyifAll +BcyM+qaEo5z9vgzc4PSfY80sq7zortjHed9kcght6M9B5EZ8+rixvjpqaM2gLd+M +mSc3ENeCUTVduMeuVLZWa1HMNDnl96D1g+GRjyEfcIM1mOeEUGU4Lj9fkHnb+taI +KHHh5twwLBCv8LH4f0HWd0z3oB2CVZGMCFEf+yYgmn9e1i6MpZMvG4TUBGH8S9D5 +pgdLBhSSGVl28pw3sK2dJbbNkseSz8RGnItJzDoPULwKc1ZYK23RLh5qUGupPUc/ +Hi+zrxAlE8Vx6EA+D27UYZEGzFMUpkUA5X0w4okBN7HPi9n3CED1tcc0eU/VKRLN +kOSaMW8YPD1bO+vbQW6cJFn2++ULh8B5ySkKWkbd80IaIXE+I4DE58k5Yru3j7Hs +2AQhTBHIiLjji71mKgSSyEPgEU1WYbegtH2Xnhfj0Cx/gVnnDVCu47yPC6EnxHY9 +Qm5EZEfNgL8X/Y2HmU3vlNAZtBYZXxWEI3WSqwybxrUXASSlKJNskO9dftDZaTB1 +G0xkG0SK+Vw6fTMWmrI0cUdRItnLHMHxfocOkE0FuiNrDVlRrnAIb/os70zKhpOM +SmrxQuJF0He7H9wQmI8evQ9kMo/p8xrRhjSQYIHPVrKZCP+qEVqij1mRWIH8Wwgr ++LLwglySEch4Ct3dLwbZeCsQUHc9FMB/zmMD6+OTa0rLc1+uXS95Y4zBvNPTK4vm +NDoM2bsy2wVH8K8M9NNUyf6kRK7wUfYYc2dDosBKcEdJvMIRUK0w/ZiWlN1RQzP3 +1UfhRU72xIAgNHGWOHOBu/z7x3FLwN6uqlMEtYQ9G5Ry54y1E5O9+9ZUG22e2IYA +e04Bs1K2nOPDBt759Gf0tXMiANL0cBGSLTkQnlZVnAbbzso2K0AcCu2qkdBIwRq+ +KRMaBbbgjkE834CxRvZZP22Ce6V3Hyq8qgy2NzhO4nX9gv0HIYrsXeSY70gAvyXV +KkJdkwBwSpmeMNtVi+J4qfhi9XfrD8/nHLXHYuy254SN7T5r4i8FupE5UOe7iQhE +CjtI1UgF3FIwhr0YfnfZzFtHVpGsHhc9p2I3yHYNNMVW+NOmnzdfUQPEAzNOHuPl +R0csxM7jaRPBKWSFyU/hjKAe5eHfjDdeFxzDITCyG984ZqShMPb4yv30luFIjX1d +gcJrmIuz8bA+U/4PjS5tc31RNIcv4xdAAEhIZ6acUqp7zWfv1V5LG6NbaCl7wn3P +ZQ4hoBQKCQ0qlo/+bgeYnvmHQIbfO2/r1oSISAuh1sTFZQKmiJ+OOMFJ4Gj3lx2Z +OKXZ0oC1/PPsGea1zHwSK+Fy3JdBXfIGxBvJPRJZYHcvTg97ytTCfX83CZsKoDT7 +eQuKsTmQqBH8dthCYgUADKQ0WH8JhtdMii6MF0ubhIG6uV8N9+2xmW6kDZol5g7H +VVEb3LoMoB3eGtEEQzzYJgrySmk8lJ6ybVPSCmDEpLyvB9EYobnSfhL7FpgioorE +h+sUR5eTPTajEU0JKb2qzhrsanYK69cKi3tRABg7YsZmK9MXtKm3o8im9c1z3+w7 +RSCU5T9xe4RfkP2y459AyxKYtZPLc1bpE4EPLMZfpVhscfUyYMmWyKOqtSOJM08E +NUALN1dhuNeg/CQERekunANJtzR2OJxr2NVAibWD2ruZLR8X4Chlrz5fS6DTA4xs +T8PwTEq9Hppz7oHGF4cJsb0CB0NpOOqRKi3q/Yb3Sa+oZH6oTmzEOGCUH+MwZ53Q +Q6xGbiAa+tGRboaJ1xbBFUUiKZYIc8YBb/wyj1QcShxRwV+8MWKZ0XApr6lFN7Jq +YK1Ies9q/raPp4WukYel2cCgA3K78ipuUScmsKIiqkHYQmvnd2OavRI3CyyLagfY +LAFYVAXpVsfDgLlX59RreRgk5iSxaVwts1mpm7b0LHmtJCQev2I3zoG5/KIAe3Ja +Llyaw7QO751ft2D9Bay2ZrguOmHs3A5BXrWPpUhAe+GNk9grqoYnax7MDTwhsqo5 +v8vg23AdH+PhsHcP4ehN4a54Rglr23yOHE2vhXTt7a09TNktrv/Ra6jiufNliaMt +N14hE7d2Ops+O/73yoEHbigtwTaE6w/aGY1N17UYYyeNdDkhBCfBZWQvJeRv0HO5 +ROXGZzyg38er8rWsulXjewgRcVsjgTBbn0jf65haQ+39o/iIvSJ5xyIokLM4ckyi +9RFSA2zViUE4N0YmpebVZy46zPY8MXqUjhSag4Src6NQ7ePcG+kZDBh+LY8isZcP +cUFXhk3rFKnWSDLtA2IVgH4j2OWfKfCgAxJ4w7PgWXYugG4tr2ezlMa3QdVqu/VT +RTWtrxC95g67kLinr6XYi8l6yLOeV/oSur7x65oLMJ6Nq3tVeHBdEoWNlXH/QBJE +Zi61WvEPj/5CRkFFXqx9ZN5Uj/ZR1VrmhyBQQhawb6TExXutxZpdoMzZlklC3K0B +rEM3FpQSL07iIUcXpppD6JvxnobH3DmzRVDQgPVo/sqde4erdfPKjvNOA5NlhM21 +kcirBL5MryYDrj0EvvPpRrOYOxNodCcBrQ2GjGj+kJ/zOFq1RubrttDgfcQHOdOS +MTBJcgVT+cdFINySSbtlfMXstqEsatk7X9yohAJ7KnNvOSVyx5npteISDIJ2/uEC +0jPVjkbhIMpviyW2Kc/o3f5pYvghPGGdtp2Ep4awqrfwCAWyXFRrFrxEWtC8ESbq +I3kQC40W514abCx2/ihIiOQyjpO4kWHvVKokaKjePaIOZQJIp4awCrPO17wTtuiP +2i8pNRV4HabsvBmS95MALaEcs7rNlh7zyFrjc1msJQFnxTtEt2C1bObyNvJDfwhW +sNPyQX6hH0SNsX9lGBzDBbmBt06HSLZnDn64y5e6M/qZrCNXXwXPlP8BHzheST1W +T25i51Ri0sFWawpKaWZnOTToUHW25k2TXV/9Jx+cFGGzr8GN09t8JqONrzliFwHQ +Owc9VJDMVjYfJ2/LQbnszucPtoLoWzDECvzgBKlRbkSNpPi+HBcBme6DjpFMrPvU +ZpXmhGCgQKsAPcbuAiv8vba/XLVpGavWX4rUwXklJnvDXUj0FH5ma18di18CFkiV +g4Em+pYwZzETpJI1mPRZx5uaGQXKzQQvx9D+vZNqHcpYzdHXiXWqqS0Pov5PmjKb +Uq/BKloGK00lxGZL5fKrJKpvKIru7LUWr9JRTBFtobYjSZB0fbgEATHwI9GzRpf7 +chCaVvc3EaJsvGSbSm5+eb1pXjB1Wo1Iq8Lo84+oEHzdKVhAYBitF0K6aT/ZbVMa +Q3dH3BWYqCDEPqkcKdTNHCaQm9t4DpSYgsmXmRtx9s4QC4f5J69hTD1NyQaI1Fi1 +b9sPKYe7+xyqqFHo+Ar0oxJEg1+nEKH87sPlZhpKjrKqAbGWPer0mquEigzu/xt3 +LsujivvwPBczQgo4OijG6v3TbxmOd8ajfzTkJoiY0jGdLZvVsAIrO8OtiY05fgKh +4qwBwGSyUraCioEEz8Nxrsm+zJ8UPpqDW6WBqPze696ncxzlU3M+crZSZFmEHQ/6 +RVD3em+eqCOiH9mDyfTpoSwPv12BuA7GJ2iLNyOJKmYaukXFzAXvMAxRStLEdc8Q +StYw/dprqjSUTSH+5GV9IzAKpZNp6M823SdTkAKHebMn3D4CVarUHC2n2laKxl9V +PM2eSBErCmYavpOw90TqH/zYtEnYJvhf52xPw9uNevrVjagLJQwsn9RVGrYHozv4 +9CVUqk73Ap5LALPasih6B8yf5q2pxfUbaXwmzQ4pZr1BYKcdOJZAoIc1ylDKka8o +bHDBp1QfNHo1nAQStVY8SPKTUeqwh48doZEzFZ00gmC6k/Lb5REgWvW6VN80wwsU +ZRRRZKq+jgkUgTUFlxpoJ3vNCFze+oKTzo98go7d4ybzV+ojqPVDvahyoqm8ljS6 +zKs53uYU7YW9vgfjwnPx2nBkkQO7gbR7lE3LTUcXnNrQawH5C4d2h6AcWuq6SY2I +Oa2KwkiJgHnGNRKFlh0qsvcko0SGglp5cy0unRYgtqviFq6msY88YRqx0r9YBxsB +vDtelS+yiIkVZFxuI+ZGT1qY8FwfWca33ZzZC20eHsUE/mrLhkSc2BpJx14vP+5L +xwXaiooo8BgB4gZenZD3XgdzznIPpwwlyO0PVwfMw0W7xzYtUchGJJSPklO5VuXX +TkmRwSDog3IFDHLQX0VwOWRhzxXrH/zI0feR0KruLHZL7hlyHWiO5pCq6SNUBQMS +2C7CBpKrBvmKeKC4vi+VcWKkdkHgNiUKTxLVu2JXSWytKS4isEtFiAimfEB0ahzm +PHqYv5E4k+ExcugetEqYURVG6urCuq/r8m/CFHoWq/ixFIqhjFBvuB/yrlPHY5Mi +78rA45GYKiLXsLLDvYBOH4TPOw0/eJXGCtw/hZ/G/L+PQkUvgRUYQP2PO08NvvRE ++l9J/FOf+LNp+7W0JuMibNlkPXd0Zqr0yAIBmonWk1D2MxEYuh4woEgs4vZxIZ1h +BF6GWiRj1BuHR0/lEaVQTbLYCDpg/OzANCn9Y4Kea7f1/aA9ZAST44ynGNKJzqXj +fEbYhQZ6MKiq0HAFand4bKmEm3yG7k/5tzZNkuJXoW+lk2pQ8KfjiIk2nSc269z+ +ye78F3SxADqIVddE78QbFTioHNiR2yB8ew8WuvTekhdHFD/o1styNfFJe7rmXhN4 +0wkO0mzbX/SjbhM4mGJk+h1/d6a2+jYTaApg3VBaWBeUl/eqh6l5dkffOSaAfOm3 +2/b4XeAena559Kx8uD4WXk3Kkm5ySeFkZvZ4YVX76/JoXxCIKXyEkBUMSyhh1gH5 +NuW3xq5bCXNwEMcEKrZLr4WwZc/8kSmtCgEeUl1j5GqxRWOIhClJ0EuIvYYkb6Wv +KU/0A/0aBusZC/VFQoxZLS2yZbiWXnX3BI0RVxJWLiPlbez3Tqu07BWI9wLmRz9/ +JMpj6njt9DANTaon7AxZbaQ305hYQLtnyH8vDs+1/+sZq1026QEx/4rckk72nI27 +wFnZSsai/lSmUfit/NPaF5ESC63m0dd+HgKsKA3+83NJpY01fQrOupa/+TOA2hUT +2hJZneHwmWINk0mGGjHSUjAOGvINsX59muveuMT78jK6pcT7NQQgXv/8ujAGLkZ6 +ea2gVAzCMQ19X5Ma/3LS1fme+cSzFWBl3J3eSLBKcKV2NeDMppNt09H2QMVOVwY3 +uOox4uN4E1GGvSz+n/AtThWgRyGQREPHP9U0j8mMHRz58rW3X8ivoVgusCitJaxT +fVObmbQoSOA31b7iO+UqW6+s+qGMoH1+kw82NB1m94Zl7DBFWOosTow+/DBesqqW +lMJdU5r6FVjJm6DSNdzh2qRuojhfPeltjCIPt86apn1cnS3qQsFp1VagQNI7QG7h +ez3j447INjS1j1rpjSgQ/kMsmkoJ0IMOClFPaZhZDBVYfHJDYSZMXyg1r/Aau/Da +7oxWCQqLbBYTsfYg2g0eQQLe9UxX1c1F91W40+uT+Q3GRJAhuXbV4AgDn/byp2f6 +NobNWXLh11UnXXSnjFoC2c7NS4jr6lva0FnwJtdN85eI2QtCkL4Mx7n5nU4anirh +Q9RW4RPgH78RhfOSfrO4J0RQB/Q1/evcg2v0vvs89h6McoQMiLU9dNksVirRWPbn +KrPrO//0q1+NgS7IqrrgbhvyKA5sbAJitA1rTd2JXtgnxpcQDELGUjTm37tmCHfY +tseKqK9bnXYLJoY3VuLULWq2P5ry/WLn5PGOYHq8CIcVyK1yQdlwSQAXZa0qpGZE +sMVJtW9va0r+apumZJyCGZ5l/BLMxY7Y4RegDGKkif8MxqiXQzrhMCeLao0f2eY6 +SlAUuNWMcQ4ujGHcwzGG3TnujMOoIubZC+jjMNl6HUh6O4p/rv6UZ4T+Q52j7zBe +y2DG+vlIH+OdAAptt7bBDcVPCejqlmN8Wr+x7GBPmg4iVenSzwdl7xqV2ZMiOaNE +YekeqJE4kh+D5yGbfxGQrL6zixn3urGLvAp1IBdW81vErGBRSmIPMqZVSZTBBYMs +nGe6hKksqkOaFxMoOvZ5Tcx0E6LIqFBZ2aGBgQ663Kgtbefdcvmdgm13e9oIXqwx +5Aq1sH7wwfdzjJ0O94Jv1tmkX0aIVVpsZO883ei1HGYhQqHCnS47tvBnMH1uHkl3 +chFrl6Zjh9O7/d1TV7LlYLu3baoorLGlMcLLW1GByzWF0/So9QQ7xJP5njaswMAv +bHgQhdjh1oBV8EEqWlNC7XwkZJ7QLjYB3A6w6v4BSLVVnI5ysQbqaM0ZzSdF19xs +uyGJHkmaw/2OKyH3iqa9FplXWFE3nUtat/tqitcYNXXQ2k0RS1i4Nz3NXt57fsCr +nmB5m8HEPMzxNLEUnmJfJBaomgt90H+2tx0mZOxS6fWrFIitjouErLcTrA2UwH8n +VopFir0VSArltJD3V/ILOqRUQJyBOFzLTvZ3oDH1PXcUXRONSvpIhXGC6s7c/pGB +BqSsrXndh5nifCE1Uk8rHSuFXH0FGHhWY05Hc/GUPhYMpIovxeBnb3xq/3yX4/13 +trygERsAjUbPeyCdaqHeOMCt9QRdZTzkNir1LLjkeCDGAx/8xVFmqbs+rjdCIN0A +mt459syB62YTdDjMqN/ZvgXTQKm3k3Gi/q7AbgO4T6DNkMC6/QRMKtftrMJHxUsx +osBzVRNxqXaHpaDk81zVfpCW257OBnIf0dejqE4lgoQWUdFdVx+l8ei+hfOpdD9M +SUkNALzJiM8+9gAx92XrfzabXAAdwLe1otkmSAxY5u0kF6lxQAW1lXob18r3F1PQ +oxKJVp64Wdh81gWGiVEBemPfUKsK3vTfQdU5avsLamZtikr75Za0BSUp0Ne0oD0M +UmfHU1krnzw3v4Qn7uAyYYUhFV60mDACkNfQCJ86sX8t7/fC3AusmZDHQ2LHsSjB +mAimPYhJCl5RlX01c4BrfV1wge3RK/94NXbtvTiBh0b0xNGRbpiNlEJXlUzGlbS0 +AK2r/d3IG1u5Xp6RyUPdhZJfJhJinXY8SaNclBjZgYzxstEDBFxS6V/EjjBzmuJY +ELIr+9FxYSHkXlWPNtRmpyfDX3q5E7qVp314LQ5K7ePkZshMKs4vq+1tuge6Hr/A +4oS/7g4o+BJm3PagEZ6vv3KZxX8q/DNvNaFswteDZqsWM2VA/WvfGLZjKYFLdYBv +37eyi8p5BGnraJ9WSSWMRC/QLbRUllXrOnOrL4LZ616/JLAKMFeVDYHPbdhqMA/V +z1q8YONxD4NUNbJ4c/S90iNUT4539evb8Uu30cYJ4LDpUcz6Rep6jVfY8TBOsie6 +0rBkAtXVwA5Lbbquao74M9tpKmYv2p7Zr1P5/OE7sbLPk/lJd+Em3k10j/B2BNxx +9aWDnsNRdYi7+O7MHa5oOOnNYa4ATFvvNs/YUe/YgBFoIZ3Bch4+NVYIY9Agjf3X +k//KQx8QL7Tu+hAK0pt/X8Vi7y8lc3Gel2yOyq5DdlLoYLw9pd5H6TutI8JQHF1h +Kd25R2tH8qhYvCg8liuFG/fgZ5OEKMvkkcHrAaxlIjO/Y7MNqjQcZhUNiS61XPSo +is25pXA3EHmlb5sc5EGDAo4bCuHiUz8z0D7wdh0Il7oqOMQyNl9ANyLeTPusbXcI +YqHM67QpAcirHedY/2yplSX4qtptEnUxShpXG6gqS9WpmfZ0jW2wU3G9k3UYEWjw +t5u0QAlwsQTKBSR1Zj5ukknmiiHO9paUcqYz8/kQ/rQY+AIdyUGROnq/LvEgu/vu +dTrXPVMyEacl+E0TdQm+qFGN31ch1H101HuQLBpPGzXwQrkS1jW2nDC/EQg1HGUI +xczPV/WNKaEjXJ6qDFnhrLKeSIcHvIkuKL9Q0q0ORsQANWJe6y7PlaNBoclN/vja +CyM5vVnxkorjNndYE92Mfqb2aiq8vW6p3gjG4breFATjBTPTN6HTZanNqxsaCd85 +pJqgz0SUwJM1NY3IAS+KnjyjBmaGOVKXdSczdAEPO4LCGEJGr8s2rZU/4vcP9ag3 +r2KK8/wf6fPE+D7Ysw7eL1p+MGR3Ju+1VH0HvGhHy6/0JHJ8VIuLHVQQ64F69u+I +FlX1TMHDLH0av6l8aBau4X1L5zD0RSG4262GMahUu4St3SfehQXKCFN/8wXzCA9J +Ql3AQFoXN6toQEaI+885hz56UfosbUvI0Kb3YFyZvYCvoOcyiELyQsjwL35uko+I +2Qt+X6EVLFVayMMOOFaFG9nnx7cD9aSKf+P6iMIpBdmnVyJA5yxlYwBUm7aIwjhT +kFt2gAxlDMgN596FZUEiwO6LfwdUy1cHTuGtevluIkRI42C7SmMevSqbXYBPuZHs +m5So1RXFmHzt4ndRszgJ263di+gf+Vlt/qBoWGQ/+35nmVUxjITPobUSp6WHW2ZB +wHaDooMIW+0ZkH1vymPuJbPluRToejn9X1x+YjhPhPRNb6o03j5k9MxbmIukTAE6 +IP7996P8xaLq6RhaB5jSh6XhndaUVmX57ciztDwJOCfHJawCeFnAD35jft+2NbpI +XQgYxRH/HcyOHoo8TSAXvRGsC370CP2xtsnFixj5YwuUXGSyi3FCNfHsl7nTM5rK +2MeCc3Fc53gKkkWngdOdAOpJK648sZYFsCGQ8n/dQk0PhDME4ez1XLRzLgUSWSid +uGDICTxm6r+bYJz7QSkPPh+98DveXO8V0nxyibhwdPyUknay1CuYzb0YbPhirPYU +OIwco3QePPVZs/hoT8cGspl2vpy9ar9V/JYPkvStjN4U0fT/GVdJVXthVXEHIpRD +ZwFWiOAKbKUw8jX3Hwy774qYE03m8dhX2FY19NJ/OsaF42HUXs8rsi4/au8+bGbR +32f5WXKUbpCRGP4WJ+HBa8u2uvg9ulNisTgdC+mMDbC+EehijrxRSou5yf/Gv4KF +ggMYnm565F0lp1CA66xe3BM3IpRl0HUw5w+BGZlm5PTYC4vZjnqfXRqsSbPadi4E +EVTQ+2Y/8X4wD2WxAUVlnnbqK49F9p2FKIeX14pkcMviXrm0t3I7OfTP9YY/jhCd ++1u6VowgHXJWjC/gBYLXxtcmgTHoKl8OQCuvmOAQd8ROm9DhLyPuq5TvJlJ7FHkD +NjhtEz+AEA3m25aNGDezEyC+jD/l+P0cN2qW0YhGUdd/LUd1BKvN7kYe3szhM5Br +Vla7w/Hr9etgvHgD4zTQ9jU+ZoOGnOcq16AbSzzDm5+BNtIL/w0+k8nkzHAPGqHD +eYKhFlw/rERn6oR6iORxFUO8sus1AG1RRO1sTp4Uucj+6Mthkp/TSB44Q2HohkaQ +RhnBVXYlF43CcWIgvi9ci8t/uNsOmCyj/iYFLIUILYdXbHuV+6cjumV4oz/tPS6O +G1NgVva/gojZhhSw53LJnC//QK8z55aDkKWAOaq5yBjmjUNjbBJW0WEaPk4sx/zW +lh3uw44hAdWR/x5BamDJYPeni+mwXnzCSWoUyIRHQ2UEtI/RA9OVhQdt6xvFQHoV +I0HCdbR2LRvQYvS0E0d9CzkXCDq0vaUs1hHZioMEA69GzOSEUCpWv2/G48HnCYlk +6BLiqG6U1CA5xBoo1l5sbLgY/MPyBFqRQO6+I7cbPjflu6yxInRpRD2fyP3+Tb4A +2hJDSvXrBIPyVMZfShNePpY6P+fa84G1IxBV0ItO+bUNgTGxdh72uwnArdOI+yTJ +7ahyYIy2fxYpl7TMXAFzEi7wsWHMKm1ofpeVXMO8+5hIwRtGr3hUrfJoMXsP1mjs +zbEXwSVngqGuK6XJCfrP5rPXu55PXLQ4CpyipXHJXZTEhx042nQmR/a24vJzu8/9 +R8bV8K30oNtqPkcX993r03cVhuFDpCOGibM6gkSRW5ElV4rrJtJh3DgpRGE/AST3 +2VnwEOTbj8N8jA0KE/QUR8s606ojSAre7suk9w1ZblXPuif75wZpzCGzOTPHghOl +/OJROQcb8VzIW1pL83u9EQe4Qo3qcwEEpR5/eTPSUoUwjiYS0RVl2zKEoKJknQTW +QuTmN4Ap/EiRq/aQu47ObVI+h4SMxZ9rI+znQzvNhwh69b+ncCcllq11FG32UH4f +PXc6cONzYBSVTTA7pgEnu/uYgbaovaKqKFb754QB2DLg07v9cIGC9mJcaRtHJ+1u +aGVLFKYmcpXHqrN8eTCUPjGwlLyKX4Xvs9jftS2Ar2ysg1Ydh7Q+p2TTjJ7oWKRa +htYv/4R8S7mjmKGQH/TdDWmLQ4/wLlaqH26UEYMk11blrm5BZBbxxTvJDX8oS7Ei +ZFeci7VpYgKeA0imi2tpaYnY9BMsFEFRk4OYD4e5802ROMVc7X/LSjijKSqie2bu +nV3e1d7gXqFGzaXTzn53xadF4BdNBaJ1JoVGVePGl9xv9nngwqEwFC5zeTUivMef +nu1Ptw7alvZS4EE8NQPNMxdN5lt8EP3ValsQZJc6kfWj9Xak7k2dzR6NhoXBfNWZ +AEYL46wqJYDnyn1xTM2kn+tusDJZr3K2OWJdvPhe3YltmZjpl5DxKGvMwsTod/Dr +xjelzcUz7kbGCmdo5iBKCypUm1Hfh9yAQkHVyWO1Ddnf4orEnkvY07WRJwuiOF2b +ojDmvb0vRNkisX3by/2VQxrDGfrSVYllFzP5lYlE/4g//ZPScIKTpdMuBFeQusfZ +tUju/dUAJuRO4zOUzHq03l1nyZkbhu2JJ1LTL7twoGg7HSoDVvFgVpReKArG+Nl9 +mnYWEI59BJ76wS/P161ncfiBwj7A41TcJJY7M1eYbPveTl8OJDRMk+TYYsyAgPkA +FclOOLsBTgi2Kw+0CRd3g6kGG0rkWltXVqnPK3F3GwC8R2rZugqxeXL0JdGiddCG +x+Zs9Qj2xDlsTRsxqC1ngDc7LPFvn5MgYITwdnKxzoKZhAOWrM1K0HBmxPyP9bYY +JllBbVjmEqLB4Rq3+vIq+rrqjs2UtcjsVHZMZ5wUGyWKKa7SyTPqVks1+uvo/KsU +mdh7goZsJ12PBIQr4eGWdHP7bTV+DuUmaL5t0Dwt/cVxtRaF8TgrBc68/XPnVnKP +K63yIPbU54QP1eF7FJ0Qtmk5unRpOuTYnb+w90WDEsO6pV5t7eUwTdIQvcapOIEJ +1fApVzzg3E9BwLrLksTzIEdDEzngKX1+XKpWoDEgjdXW1dpeLnWED3MAkPZflpz1 +qJPwkV3vVg4JQ3ygh4IF7+bZnVIu0Ms0yOUTtgvVYS3dAbK7Xk2auwgEO7TaaySG +mIKsdsU6r0DSf/5g1FBjiRA3QaMww/FEl1dssfEypRKv09GdMVqAEPp2i6eEMDAr +DVyPITcSO5Tt8vfLkvJgtWiPSk4RfvUPL54gnuF4lO8Wa5ed7YfczykO4XCdnHVO +AozZyUFrPfvpdl3liCDOsNE9J3ZYtSkQJkI2Bm7wCqHuyeUl+vDrJg+AomGWQjIq +u/WyvxSbUijhKPFIObPERqJMJzQAokensd+20UYtN8ClfgcDSzSVGNCuW8qvoEKi +y/Edar7Gol2wEkNOtaw3XzzsDc36VJPP+ztsTenVakKqjS+7OMI+oG79GjWmWsKZ ++ZKmCXYvv0X2BtX6EqRRouMtareRmS9si1vYPGpnpO4S0yOMnYoRB2XSiJaUNZ4B +MPYfBzwY44wIBN+2D5YFQTuBia0KwhhDqKre6ucLJnYVGkbVOsNVRIr21OuaXcCs +rULeIISe3T62gZtPuSF/jEV9A7NC/YMZD0Vc8DPnJaGXlHDSWfqsckDa3+nkc5nk +K2Pxj8v9cHt9gdeza3fr4Q+ihR+bN0OOQGFCrABBEXYNX4mzxawzF1iQfsvmHqP2 +U78aAFEwbhqb2hVg9dXBqa2LyXc25tAjnOXDHh5luScAz6dnWSmRkKysBwWqar01 +kgr5BIGt8NMXWXzI8pGeadrN1VNK/mw2Iek06Nml9saAsmApV/nuLDBa1OXbvuAC +yqJWPFSOZ5FDMwLFV4PsXhqALfS2sp5VMsnHu0DxGJICyyav67ySEUr3ekeoVuL3 +6LcsIZ/W2qUg6lbOmRJ4YfmtWOdtdY+M3W9kFzThUcHcnmWo3jGU8rsGlvjmtucr +gTqYys9qwgOMPPCVO4lpAM0jk180lbuGvqhK+3prtkh8tljTx56qHPi57UuPKgr6 +TQsoj/SnDLvT5/7kBRTJgvzZ9Z9zaVZ23odJV9vtcs1v8ZFJJ5juDit93crzME3k +6Z0I+BxCuWt5aVJdsDfKZthfbfzRCKsq/iTlnkUUM9d0OReLidrqKRk//t8+dvzZ +JsJlYJWmx9xhJ7kZvn6CuWkmbc916VxDswDHijKc48vCBr3HMViSvbepGaYXg2Bh +kUgk3F8yw/UFemYN242vWQhIB9jxOBZI2RPCJtkZxLiaSJs6J0c8YQ7mX6hAOSML +oaoxEsKwUF5ofnLxCMpN0PdwpzyL7MDNmONxcdHPuaRctJosS0Lr/VfSdVCnAe/y +EI0J5pZfy6o/Zg0q3ycOUuw0RV0bAZnnncrbzs4diwkM0B50yYz0AKSXy9hQDFnI +lJhEcs3xm4VWAnz2kloGQkkV3/+otdvQy1Sw6aNlnRLjUucyLhhytXjuuO+rpuSf +cK/HA2JaiVf4Q4BDsFPg3ZCPX0BOwTEYDX9Z0wXI0XnM2h8iVxYcFmpHhRPnRJrr ++KHifY7JBuG/xySmPBvttVf1uq0X7MWkpu8V6dUqOvPV05sQBrgaLcgsMOLQGlmy +iV22YRYIOhbMbtLVqUD93BB2SkzttxHs3+2BaTd8VfOnKyp5zP3UjvhjDA3rnpv8 +yRfflxhVX8o6jgK6DFDLQpcPxMR/bHovCN7Dp5TFgGLIxcZBpOZa1QSwxUaI9r4k +lro1lZvx08AFmkK8yhlu0qqzZkfKacu4iE0/Xp/VMHq2OocM7fvx6IP6h7k1oIdc +qvU5tToxB1eRCKCC2M+ZlHNn4ansr44qEdtp3o4nZLYPtGi+IJKlGQQ76/R6UmjC +5kVMMLezn1VIhY3UViegSRb4eI8OaGMA8nYTN4bCiijtJGOWMcnQcPqIsIiwQatr +aSuRV2hLBWibG5NCTgu5vExGzNnv/LmoIuVQJik+QV1EKlnRDgpU/P+RjltcJKZ+ +THjZBELI+Afn/wBi1SO8w5dGISSsApvgZGZqBp5fKdtkWcba9bq+Ibg2CpAo8vGR +MxMvQdL5QPoQRfcFtg2Y7/mBbVa65xV9SYtUVD0+wa98SrJrT1lcx9oMP9MEU+LI +g9HCSSz7hbJ4Vqq6aKLkY8+24KR4IlwPozCrRieFIjnuwfMU1uY+Ni9Yj/EdA243 +pGaWu8q4RrkOm9UDQ/8No4lRZA57fp3NTJzSQeMvkG45UubR4rR4SCH6jGl/8icd +6IBwa5hKwYWAeLIpbotnNIQMhf2IsrMq8UMAgyTSuylrEi4gpOKbXn1VIk/tKlNe +4DgVa4CA1FGxbGK2tlYnATpCqNCk7L00rK2sTE9+zc6P63CQ6bIFDtmnpIUx6rdQ +5IVIQ/ib7KkDyo8PEbX+jwP/pSybN9Lxt2V6GIgIKb5+Y6mBpldxAUyQ/sAmjB47 +ZNt736Z9h+6kSpcRUEVK5dfQi8CO2mvPKHzG5KSFx8Ym6yv9sNwOLEWYvgtpl8tK +UObNccrfUMJDs6Cl9yfGPzGeZH/yGAw7v+7sNOWZo3WcjcDw94vooPHaeL76mtp4 +czMjdrgtIQQR6gnqXDrgFyEsSqdG1RXej9FBTn8mNYF7gIO/en3VoQXU08r9iH0C +WZ8dJP1tT4cIKJKzzIdfv0SIDs8mf7ZxHzi4U/34ChLquhIsfng1kVvFEcqPFI7S +yAhs8e+646lZUHoMj4YPKSP/UPCJP9gPVqCYLniJl1FhScSUKS0TWZcwwU86gvkl +vvZwbD6PA/Ht3s8OrX+OSyLtYr2tNEk0ao7cTwMPOJ0gbBjGaPX//2Pc6VXX8QeZ +v4AjXBOlOzlj/+2C0fUxHLx4MbesWSJntCb/r8eoyynOg/Yb0XSM/tcXmjxnG4Mt ++TqgerVSha0rDRsSjQewffuHz1Ivn5bNqKMtP5Yj4df+K37O414YrmjaRHOYkWnu +SyCMnOx5k3zJ8FPJK6X/QKQfL7+JUU1PthEkCl3qX3AiHa7VJdVEW86liQGGSqVv +DLbSyfVliVyRDSwCNZ4oXXpd3bH0fTKeaNZsct/ZXYhgeG6Ynejk+JUWmezNwDIX +EM3++bWMFnwpHkMiFKrdaGIKyNr+sqsCTFh3PkKrAoBdFX3nuNVQqjWWTc/l2Gmn +vy+XWmIQmbG18CMeE9vvX7p1Tb+JiFMRkFHfHZ0jJfoOHlIElhPcsWSp65cRQZ6N +4h6sZV54/Tf+UemVNrfR0leLo7V/Xr4e+N677bVojcUIW/PfkFSgDBF6D9+mkIeV +oqXabpuKqHXrWZUUez1Vy/Kyiks32TDSUrb2wtRlFvfqGdBDk4aU0TG2yLOrS2aG +R7hBo434Q2ntisjwLPdY4B23TS7VarHDDvs0LWHxoFIJR1qt0bfo2zP2stTL6WHf +6+NV2IlXKGv/AOKO5JibkHCqaHop1SxjJxivq2YvGDbyL+OHb3JW+7AyIaHQCEFr +E7xE7ljfvoxH6JmSEbDtZoQ/huc2NEAF7ooqPfQN0yh4GOaMwtBGS8GD9i9+Ftfy +3oAhFCKSAlDWB0yFWe1hvv9CI5DGVcss3ncM6C1TbGcv27U8FudurYhRobER4OrH +OrPmvqiemmi1pMxtaGymZaGz8TxvYR1BPHWA9wODh9R0vAz3sWzFsG0UYTWdHufr +WyGlti2+irJBkrotEKYgG6eVkKBSkGv2tC10NGw9tPhuqIydu7iIiEYsusLnBqCY +bDDbuisH9/DxGO3CByaYN1fUPqPXy0cCvcB8mh0nKJwDNPlC09S+CC+ksplKH42p +FYKCQzl2vm2JEeFkWHJaTq4USJBzwqFefY+t3cxoP7cWRGZKC3PFzHHOlcfFvrw4 +SIWZLpEbsiG5k+mMGGSbwTrWuKAHLXMxUwKZnYCzXW8PdLCj+hnqfdJgkfhDc8no +ZaeGp6DLJogCg2TlubDzds9GnxkFBze5kp61hUFK8ixmkvkE+f/P8jfjdftBkuAZ +CLxJ4pAfZ3K9Uo7KtOtj7GSO/betZsTuSzhUbveWrXAViMMV60CApshkDS+uxG3+ +oXueZ16aiCz70mmTTMxpSODAeuJjKlXPUQY8iG3+x8weEPRvqu5VHJ+K6WZa9van +iRTIDRIeXkpssPw3akpmwDf8y/5XtWw/0RAININVFFxLaQCbLpBJgmEJFdYWT1lM +cg43yzG38geUadEbGLym3V5VPs6X+olTD3rTGUmzf2b4bk4RjDk9pTIw+0IsFMRE +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +J7BOv0C5jXIeRnLfMOyapOQhyKpFxofs/IUotfm22gu2bHDwrkOZuNyLq83WUu2r +xh4uVd6vqtCoovwzd7WfItOCJ+X3O/rPN+iOMyUD4wUX35A1JlV+R91hVXXEJeJK +O80EKuSi1cjkL94t77Y+BP7umEmcNvaWc2GsIw/yQc6S7Haa3qdT5InDmDim3BIS +8ianCpIbGR5tK2EK3Dd1jXhcsqg63wXWm9ytRW/sXcbLdFEA4q4bAwtsavM1I4gY +2p9fZ2Lqm2N2rOQGPJV4YFUkwXWXjQGKOsaBYkwTWJIkJC4XggjFYhfOPFQhinMU +JpYvRNjOSlo9yPiIiUT90Q== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 36512 ) +`pragma protect data_block +1KZxstNKe1X3FW8BvRwLlLOIM3zSdhwPG2BEO5RT2Hx+LcIC4hTVWuBJOTR0W+xU +TimN+/zw3ZQ3TUuhBIf+5cViOaiE3T/00dPwc8zzP1bq56Ah2eFb8umxSnuypg5J +wPG/gtAZ9EGXsfJZO95JJW2NdlGZ5vQMoAC3BujdiXh/OLyj7utM24A0GPxZOk9i +Lldfu4LlJZUeXlVmUGFLNP8qnfGJjj3OjzIslsxWdrQfIUEIt+C16arwlvRHgDPm +jEo5gfYJ0fmU/HIf9JKMWqMu2TihPgKrAYbRwLn2sUETfjV0QhlZFIA9MRkVAi/0 +biDlTTzVB6K8ZiEvk6/CpT7d8d9ry0R4XNvOz77mTEHCSegPJ6ty/FYjrlUcT696 +W8YmdAR4AUb3Xzj9GH7yiqqoTUuU83WIAcd+YKrvNpGimbjNDjvus3Hsy2AXLEmz +FUXtKBxU9zWk4EODbG62PUMJLdyvNnmihmpb93kPhrH5xyy/sh5KApusmjG/RTCj +Rqmyl2ABvt0NUT5fCq7/k8tiKitSKHvPBh5310RN918/eTUGZ7023whYjNfqZRF/ +NSITcIwVxUOtFpLGahS63V48Wem7Z2U4XmKitjT8oymtamfOHLZ/zFmW4lLhRHsw +IwNcJgMLwtk1lqP8FJfKqLWNHXj04tpGsEmC85uWLlkziWy+iaXA78CrECGuBeYQ +pbUOQdFkBV8ym7SRW/SgupgTvPbIB0n4QHtwe7L1qz+w3Bc3bmSbX+DlVNV7PF47 +FQ+qQvR4/p9FNJ9ikl4fSUFKPfNxt2ARCQscCb70qo+GQ2I8bKxpVFQShZKuW2ir +6pTu1m5KoOQ4NhB6/GpwEE6i7huKCfhgkTUPHAEBuPxwNRrsMyC0zMUV1UlcIA65 +p8Hr52Ynp27kucQhX+L4VZPyvKbDvQk0u7SBUuZVS1OizcH02+5M9rGGDhGruT72 +klU0YbZDUh8CQAsLBlOoUAzggOwr8ya4KhM0wz5IKzheV84cTqgjY8z50RWu8paf +QdlTUTQSo9d9l4JmhNpc3HAv/qZRCP7Dwarx2uZfxG9m+LKE4cZYnzw4ocpMacSr +Sy3jhGhUazXuSa/4FU1HpIzRial4npm/p5+RezUSgPPDFZyQ7mGoKveqINsqu72M +sl4xXxDCB4neJtsHgIpMcAOJz8+ImhDJ5DW6m9BBgHO9Us5HCcx+CYNShKQJy41m +SkyZ0r3Vv1SaS5dKeXZ6SU8EpayHyoTuUE7dzcnEeapc4ipkWvl6eH4Ol6jJ25qY +46Q2zoOLWjyOwn/7IgtAT43ety6WXD4pS/+2m2ZKKKq5b0+S3swZK124XHHzv2sA +2kAgbFgMwlp7rQpCxn8DJ7TUGQBuuN9ByVxeqFbtHAs53KoyemV/+imsytpxmCEj +yka3+Jk1pHYLrRUVZoWdmbZiPMEy+Ov2WwCLitsnaOPeynzZ47+urpgUZ41u45Kn +kAOOB92jqGdlL2K2E0VoZxsXx8zqcfedStIdYT21k4YYrhrYmM8StdePNvAIgoLa +z1v1Oc3KGrnxkfJKX4BeUg5wuh73IF8YafGMX8L+PlkqnZt4Fr95UDq/S5vl2EUj +fcmnytkrXI+rL+fqG28RQFEAmeh/n+mJVS0X37/qgIrRDZKjoMKq8tfMHWmJilp4 +PPa2MtShZrJXeGhIrvv++o9hTe6Spj8uK26yG2EM1bzraQdtz4C0VAruE02uyo8U +VF7Bfpra5edLfiOhwgJLC584ihYYTJoaVOtmq17FoJOQ2tpmMJULf5/uW6VYgpUR +GjIXp9VT3rfHeOix76pV8GeF2bxJ7T6jSX7RdhM7jrwVogHXqauD5/YI64ktaAgs +2htt5zzF6DSMAuEieJ+Oh5Sqc6084oe7tSsm7jvhr5sSi2VKeLreaqkfvk6qAbWA +Fizel5vzRH0eA5kaH93Cv2k3XzYuG/iTdV3rhOBBK42DBHcCrePt792wdPJq3RVZ +iMbn3SzDyksVCX/TlSXlSVA9I5vdmjRMTiI3anhL3DHDftlWKAJMG17CuG6RiVRH +PesFN55fGP7Ds6O1JpTKkqpBfz66X7Egqwf8xNUhUj9RmDuKS+I0uUDipOj5qd3i +YWidVZSF7Svlm7wQsDvS0mmOUWl9vlUVaK2xB8GWjoPQUoZ/cfk60DuK8AOrGWVc +YHF0It5ZoLNENG42cY5iFDC3cceZIMdFKcGPzG/VZuirIP2s+2PTZkmVosSawNRx +obGa35pwplr6F6A6Mvhq2J81PFSrEqsrRvi7JoeLoCOwy4G8h3V0rWLMv0hUvWmA +65kBrW627yUT1g4gapwQzNHcu6mtFZsh2Y9vvUjOFsfZYB9K3Q9i6FlG7/uFM9HF +efWS+Znoo6c1YwKSb0t5poWoeIUF3oS55accL+sgMr+wI77zU5xEniG3d4xGPaoY +pjWY8C37h4ix/DQfKnP5ZTMehJ60KwQiUlo3AJ+tp7syO50VTE/EiIRo3TshL7o3 +ZcZGYRQCnfz1xVogHLo5Hoj9KpWr83d41VNeh50sf9bLWHw7PWygyBRLlfZMJhnq +hcP869YHAe2EaGF+go9UWPK0NSTjD3i8TkhNeJMYyGYn9Nd6hrKL0wzV4TnoIJYl +StIwUiUx3rvFDJAxdqewKqWmrto7yGGpQtseU0p8gJrQFbvGCFJ8Za7AzWoWFvSX +1V/V7RYmM9W9LZeaI4/6rFODI+PPIU1nqRNt9ITOQOwf7JyJj3Q+v0xgdjP7EhEy +aHPTMY9CVERvx7jUtPGg+K1DB0pmZw5BxUhzDwPIeD61iU+xQDud9e4/bm7ikQl8 +Ppi0QkZHPC3f7oSoFRvMdpUdR5pGgtHNIFgyHvvDVfDTxtIk+BRFUy3Joxoc6hcp +4OtD1XKwjT+R4FYDFFTl2OdLz9ZDeOUhU8V8gIcuuLSs9YBppOSeeq9eO2PAF224 +dJPzodaMpoE/FEp9Jk8EbatR8N119VuS64rA3UzqBwwLpjYHUDh1+/iJeak9BHA0 +ul+7GvHl+eZB3PqetOpTc2oxytATSF4C6UXU0IAfSyEde4ihFMmROrOWh9ARgM/D +d0HO1iThPZ8bRMxqfmreNZSHgu7w/nVbfMxMCM7scIxtpF28aP4HT+sK36apVbRa +LR7+r1VVplZznFGbwU8vnWgUSlFLwgcOBb1jdI2A/1f6VzUdc6WrtI+zdgpfR6ai +Qf5EFcm6lD0L1bD2J2+pFyAa2Nou/MRNNBKd5Iwz638S6cySDgE9iEHIhJz1L9tT +LcN2XJ6D03DJdp0JNyh834k1LCJunVctsB2bpCa9b/e2ON3/0ElnLm2aXeBKiRD2 +fbQNIMOQtzGYTiiyoWUn3PscJWyyXtMtOuyuh7qjYYHhFo04MWOuvOA/UHIJXA6P +5YLt3eZHRyhqdvPY2lgh+h7UxbLth5RMhB/DPiuy0A5rJSPxcqrouleCh71Bv/06 +0Vf1ZRClnNSev78CGl3P7DMxCISVgz3XcW/RMazJdX+5LvP7xtoIlgMGRr0iLAOP +AuFr7aJmgif1+e6Wk1vsk93BbY8TkBb0GJ+M1Svhq1P9fuUyA2ejHftel3W5q3qs +0Vwn16vIGM5lMP4gBC4G4wgHo7Dq6iX0ZeaWIKCTuyfooi5QclA0ARWS9R6HxO// +9duzvTk0YNbFrqi8P3VA0sFfe2ON1IodXifTaWKAM19Mvb+VqALPhz4lz/CiRn8T +HX4wIvaixlUsY+3Zs4K0eErwf4r8aXh/Og7u3Tw6oT6qxcIq/QX6cmNbdWBzFxwF +KmOw6Fz5hvLUl0qcPFFKKOGOcZBDjo5kLjFsceH/Ib8BPvoOoVDZCOD9DZWQy2uZ +RqRvOlKLdsozc5VWw34Kz0ZueoWYBkl3mxiGOcJ0PAePk0PGmPXRbtaKHuuojbcU +mwZDYM0fmF9sVQ0ydoj1iibCsntoIlG0YiVJTDxttddGpRkbCvhv9QcUCoMHRIdl +w4nR0HOR+xbTXfjqxQdvEeNtEPC4bIdUj1siP47onEHlROonvzLjcNau9lurEvfo +dahszLJaprn9g0UcQxCx19pAkQBvOc8nw1gZwU/I31s4HSw8TiUreuizbKUbg+28 +7bGE9ANMpo0Ms9mnxsQ3lAvHhXXj6yQfh72vNefvRojxcBYgz1u1pfp05NNu9epf +v1aPYTJh944r5lHllxqbidQWDJw50OBCfWgj+zJqMl2/U1oNeplNOGGD9k0jbWhE +/Xw+yvgqMme0KhdmSkArO7oFA0qe7xKC2DE+JtpExaOvpOnqfqnKBev0LjzSm6U7 +lkIBABd2fbwTVABERPZpGz/tQFPvIUNig10ZlTtSBYR0GEyFbFXlAQRBZfRIBvbN +eyiUatQq3+fzg5x4VoQOaqFF2URl0J83RL9kDmtKeNXK1PyBM9SRh1EyLNJUNL3M +J/5U6KhrJzC89YHR9sAz7TwIlnaRZsKhU2HxaGWGl8elINnorVOkbkGAbKlxv2Qs +FsUCytwgIsE6lVtoORfxs26w4Sks+cXn5qGGwL66YiLJAii8x28tlCuQVsAtpPJf +V/IBWSxq5VCC1+WYfi9PuYER/BD/13sEUBBH3nSzGUfzsEmv9X1QujkHVoF8Sxiw +aoMXdhrUWFQ0oWpfh5PeCtr+cjUZi1nkfOEte+LB/y/Z+P+CQL6rjM0lyColxzMG +MS3YjKjMBlwR022jCgjFCVAEx0FLHtN3oehnjymvWkpRIdPG1d3nthSfTELh2OMn +QDfUwIL1BFe03VndNQWNGjfYXD8lty7IKv3JD2vy7O3+DHJfC5EJblxpLxRqCRzS +F/MstdDNquRHCh949lAVofZsUCXwNlgcjlE81A87Gas8LAgY4VTexcdPLNGMpC4f +8aTWqTq1AAm/eaHr4kkfAYHA3zspKJD72VJbBiCvEx1WqcluLK4qgas8OL+ZlmQV +QYYi+7gOkrK7m2EJY9M6aHJURdE+ZyZa7qrrYhnID2eweF3yXIYtZZvuJHLKlkmR +AiRqHu61wGJ43FbJkb8XBJih3S4TedAAQBb5XhnY9/o0ZXB7+1+DDdd0Ort5D9ys +1IU8YElMdIaDNEvWopvsd9rxilBWYg+mgo3tgU2HKzKx1HuuA4mXdP+UQQUHPpaH +TWrzJ2hLPYAyJraznZAcFnGDjAFhqQ99dJvjSwtHObTSghCg0t9lQzj8nfof1eaO +AkNqgLz9jCfe52H8SftvRp9FCgKJXeSrwtOSOJDRNCmCHyZnAYmkDvYRgA/0lzkD +SBsD+za0lKLAkJDxVZA4HdJJg5/YffZr81WqPGY9cfcdQESA2XznrWZLTeX+uYUm +dD50dEdMK2sycsnyLMwuv4a9hWpN3HZIAahs+wcYfgTNORA0Kth4Bx5EdnH8OuSZ +0Vb2W42PMjlx+gfDoaGHyHKsFshYtJVprF7BO/yppP58IpYHG+NozTalsHPlMAqd +jgROOF71mqLH20YYYyJktPZCve4RSsGfT9/AeOHHGRgaf98XRCb/5o4LTM8CV53F +TH2XH7PtUwwWCTPY2AXkmiF1KY6mZkH1E+38wG4l1MLPJwCQx7ZLCQDbSHfy6Z+I +uKCXBUxZqrgqSx4jA7tBIvnrTUK4ef6EMX59ExpPzB8OEKHhRA+onPGI9dPLIIGy +kyJWZHv72KSjfAWdMqnOPY7cxRDlSQkVMk73/JtrZ3ygOKTzC8KibN8r9d5wBMjC +Ba/pTrHyt5PZ3KdV7/I0w0WVUrCKRF2b6mf6Yr83MONBfh+ZvQ11581X6TzPhj48 +c4siPi3NZi1I+/KQHTYMugOOu0BkrxtwBeKXCr9he7WLXTzj6qjEmjqqx5vwCxNj +4ZYCWvP3W4452Br+5+mBHl5cWA3vmOKQWmPnfalEasU9hHaactnwDjEN6TG0pVqT +Ls5WsvC7dBb8dlPg3S0NqhMg0G6xQnEV9T00ZhCLkY4G6WJrgD0z6qii7IzF866d +d60l6u4k+fFkajPb/gq66v+WUEk0YkDDlICfXU3sAfes1CgBOGY+ne3YnWVJs5d1 +NjA990al78sXfdNzV5cUgvvzAogCk6qhPKZkp87bWQ/YYQQC5iJJ76aXETW8+nfE +j9bvkkrdncRP4mD0g+NRtnlySm1KulaB16x+QpH7QMkPbEOOB5pDpmJyyuBoAePG +yjuaFXiMsUN6qGQWh5YcMWvxprD4w+wxcScV+c1v+/jwe9iwOV+gTghk3JVxCftb +HvqvODafVVR6Cle66EpPhK/qqEp9hEaImZQwaVhyS85oZGa2gxMDw94VU5Xs371G +H8ysNYg/a71PDM+j4PmnPKunExkrJfk9ouxNWAnSyJQOmRBMnHOnJIA/mtofWxoO +ScrGE5UkCkFgHk9+x/GFuT73WasBeyGA+OuaN9f8dB73JNIV+uZOTJGrD8CdStR8 +lOh6uslwlAOebkHZHcQMG7wOs1fvq5NRYivJgcmQzwYsbbCCL9/q/y9g54g99JVk +E0bGq+7xq0QOgscnhAx8Jh4G2Y8L6Prv/fwhF/BwZLicMWkVQpUa3X6j2A13lpdu +46nC9cyyqrouBCio0gi73BuYn5E7woE7sVDfz+hjfPZ258iCardQRSmLKkCJd/Yu +65E8iFiLLMZQmalfFgWuYSJFvUdXNig9AFQ1h//wakMwlI8fnEj+sdX+y/bega6e +yzSMP6j9G+7uCwwiZeczQ9r9sY8id2a/LwkyMmQ9V6/Is/gDmsLkQFZLxIlNOS5m +gVDZ7LKIqS1D7jDgc5ERWRtLi6+MJ0r/0TfkFv0NTu22hopNc9PR/8en4ej37T54 +i2ColNVeS6PihzLcqLGJxlVuNMbzhWi2zQL0JiuqGhlsAuh+fXqRDr94pn72Fueu +UuM9BtQXndiDVNR6xLQBWnT+6OOPdfSbFRwxHqXUclmfpTDvG9ThTo5llzlo3c1s +WMD3rLbaWq2c10SqQFUGXBXhzmngurekQ9Lvhi/ATILC5aMJyB9pzzZw4vEPGq1f +qr+djHjz98sJivPo2OZQMMdemm3Qd3kcdrho+gxpHTuRWuWRuM+vzxDWENDOc95d +/UQjXcvzgkbVCcGDHlIIUkgFd8v0yveMXblBmIQWFhzkpyU7IBT6wxLJZfHcAjIo +5T1yUJ0lFzFLCoUVuTwT37kRcm+jjnFP4Bnw/63ecOhBNai5rssJzZLPt7jq1cne +CLOpVIyRz0yQIvPczlkOs9jQLBKcKmlH2wzx1PV5BbJQCBjxIY+U8bqqahzXAVcO +G711iKIjpzg42I7G5H/dI26wxDuUV6BVZt2r5pB6BLpE8cPTy6ULMKX/iJErCTRj +vccqKdzuqGo76Fm/ScHBohJgc+8hASctauG1+s23cyaZgirIFdZyWqYJIIgf6PEM +iofnDqeRVr0OjjUKn0CAFt/WySE5Xig0TNb6OD45mQpnL4plzwNygaMBUuuMzLXt +w0DmwTyTajaBWHVAOYckHd8nqj7VUZlT8MOrtmRPHMoBqASZk2TLsA8pWq5D34vD +wYhVmLf2svgVqckOhygSWtukiLz1znxqJcQOVrQWGLD+TKl66f+TEvxkSNUKBiGt +l6cmsOF2KIoRhwfMoPIG2AGnwSyw2m0vpcwsAEEqAxFomOHevZqyibIDWH3wN24x +t5MT/jM5lFgr+nxjrCgfUlr9RnjJnMx0T2Cb/R4Cd+eMVuUUWEfMGpjwbZeJh3Hn +sSG58fk/PDcCjYMDWGPcfB31ftm9aPInOmb1xOYLMUntw2rnL1hz6sHQ3i+O0SF8 +u8Dd9IwHG/FbYTPoIIA++HhsUYnMbJVxKnmLA6e2m8gHT8dJ4bjkqm4t/yTnSwi1 +heydCDZxkCulBOF6BuxJQJ2g1aHp3SPMbYeGpjKlb6puUp4Yrvq7aIijUyUYRXaC +xoMJx/ClSuNQVsEVyz7CPDD6TOhagfW4W7kcVe2BGKQQ8tj5wjyKyAKExxKPUqRB +8n7wozcgQ65QsNbVhwl64rlxykTIfHSPnDNvFRsmM0UXaYd56A/83JdWD1JVE+jx +i9S8vZ9TtcyDvwoJkytPGtHZFKUn/YsSQnz2LgJBNfNCxtas8wpfTEStAshKl8Ky +Kg2wbuJSDMhq38QlBlaorcLWdM8tHuzFEnxdxnkotb2z82bCcuVaOgCjhXfG8Oa4 +LL1t7c09od6tMe77WxobZ3A7osAvMKMrkV/Yxhv95pvk6GdBullAZ7AWkPUfZICW +/9wLDY2vaV0YNMrEHl0FMM8IQX2gUZdXp7tFZPL0lxmxMfJWfj5KiDOGSCPuWMtO +PkYzA00BfScE4PxrrZz13cAGtHUsMggBHj6e4zgK88pmV8Q1oo8l0sHC2pHM3ZJ6 +VGj8TCP0SWQlyBJA28kba0Shs16XKWA7TP/+mvp/9zP1HECRluRPIwHv9P7TFu1y +suKlKoq2wosnc0A/or/nmEG+gyvY/i1ihKxLMaUGIpjKGT0i0YemaSA/GgoqEzNv +Qb2QZDscoFtWXBYPwUeENgxKmhNYzaoXEzOWa3ek8S4msq9UZZ8vrYd7is8WRmpE +bbYqaGFoalM0u2ebbgZ+ep3WVFyHKjwJx28119vXhhjK0FtsG8CuUsbC79M49iXq +5VAxFK7fUuchODd0rqLUKcXmuEwRjFlkOMi3V4u/j34iTCzHNIaMkacaS/1vl2lT +BqQMhQMBDCGxffdBat8RIT2OJ7a5NjQ4KIP8egJ9fAlYiSi0n41Fo/VaRjsMhI0U +WJE9G7k0qXJxc40uNK6qbQcjcYngVdI8rVUHAsUuP7ERomlLIcZCq5H0tEbe9lBL +Yr16ebWSTxJ9euHDBvfMMIf6G1rJus4rqlTjUOjUBNIF6jtosGQLY2IrwQYKqb0g +h3Up9JNGAeJm+crgOGBpND1Mad/FWL/+g1rFIMtpB8uWcyehJeAwB0zIRLYfrP4m +H0qR70srhXqVP0n0PMIF9C9Zf917793ibePgXWbbNTjY9wSJhwpiSnMsLhZWITKi +pWi4j1lTnAD8h6mJkrASop17QvnVEZWgxbTiLcRBQBg6INXqG8szK2sGao7mDOOk +OcUb+Dso7UrMPHjC6W+5CHrOo2MvAtkmkVMHIsF2Pw341jWczBvrCfwdPRr4Zwak +EYyVM/fIlsVF05AsA4r9UOeBVqOYPhkZrymp8qI7tVIoyCVDyQb87PfH8pe+NlhQ +izdkK0ayeklQkdrDZuYskUMT6yt35HSlL6D3UB1Dtspjx7N3YpAFGmSDdnMnrZ66 +gux/Hqz0Y0ODEdK4R/J4ktAg3IM0+67eM3q4KDGvs60XhEuF/iC7HZPvLeWb29s/ +GMsjfR33BdTrOb1NFT8CFG3V1dWs+8zHz4HC5vzcFj9Y7Rr99gSuZpHUSVB8R4Xp +coT0fAwUhYSHsytZeoGPe0cIPad6Qf/0HmtCZUDEBnGBMj9e/7bhogwbVP2TpjMi +r3ILWfdXrpEv14d2qVPSUzmj/N0/PBnOfA8hLid0QZ0yFQAQvzP+xty88NTPbKcC +1ANBtJ7D9HUCVkJSykqoLt1tD13TKe5JjoNRQ/VieSLPG72KUqzZPsMTHqpT7eFp +yC2UXrVu2tRc21thaoKzDsSlchyw8XQIhJl3ztKkC5PozNvFB26RujT4BYPsvtPq +jfZaQOHXgqL/7eEzHptPqrPke7Ch53UR5Rpj89RhAztkvqFfey1F/3bzjr075kIO +0cFArzM6OJVuKbvpFZOIEml4jebNrqmuH553j6440nuR6UtwC/pKDYMfNHU4Cf3e +9WRpTIQ58qpg24dl/7xkCvOabMtX5D57pLtlvaIvBC6zCiyoQlnZB3eKErgjHJFw +81q+Nrh2DY7mgGjnOZ24HdCXil+N05vq6aggMN5vs3SJPPu7Nd20/S4sE5JjWx3x +OZVqK6Ku5Cyq1HF4Ani2fGmTnuTqaz64bjbtG4E0DcvWBBAOGliOG/VBRE2a2/LD +cm5ZdicTIRMQUXrWvOZRhfdyZSRtwBxiPMEy3htBgqn2GsqgN01eXEJlBsQJyC/T +WFer8G2Wrw7GJQ0CwO3lg1KYy2ZiQki9vJueO7RqH2ORf3XWOJDTr9i2TQ7Lyor9 +x1zpxQmGINTQz3kLZoXcNuS8kzPe2cjbGgOPp5pnKNOY/QStzf1Itw20sHBJU9wW +VEnTd08sxMX02UPHnC71mD+w9Xe5eFV2TVMIUDYOQjcVMb3yUYPqohfIVONcCdEj +jnbC+9A16MnbP4FeozQ40gBtVvcQLZRZ31L4HnrATnOetIpIUabmY8u/Z9heC8xQ +EnDPDv6ZpatSxY1Z8Xi7ZO9DT8eaWVp7jBR4Jw+RtiPrOZ6xt2NUIK7yRvWBOdxM +obkobo71TuaOosdePgjlhbao8uP0SCXXFjeQZq2Rxk4yPOp5qiE8tn+O6rYuXTGd +L6pIxfSVzXeSs+R+C+70qpLmaxV947cALtry3I+QMCOviwk8tR6KqUL3Q9sSmUfg +8AZToJXC6xvbw2aP32pcL1mWrNDIGHGi5uUhbGyYBfZqGmRaYlM7yBPL3juSpcNq +rwSgelFBCSnKEJqj0vlygy9rHztYpYzQuRF3YUpNp9EenRN1ANA2Qlmdeit+F2ST +yI3FM6UL59QZa4LR5tq+6DT0k/rhbPCKwRVt1uDgkB6pCReU+F2ouRFFE/h8l2/q +BxsiKPDSr0t6+TWlBUIpgXC+AfLVqZJ94S73Lzw0XrI7D2IqUld8+KOFZHPZ5Pm9 +VjILJvo4LCx5Nrf7k3xHYB3gSSITB+MKODzVYqKmjRky+fZqwpk0cG5copiIkWem +IH+FRQfKg4C99XFui8BSXo70WBCyHCTvMW8SBDQRGEI+cZsSqf4drs2X0tvqpXVr +s080Hq8Y9WAPj/mMZLYfY1T070HBAU+ryzMSv21hOsdeD4xcLY+hWEvtQXuVf0UV +nNgoqDLz2LezWo/5iAfaH62GuGidFgx/joHe5zpmt53NGAAdi153ywYw6rYYMsnG +xH/zRK+KU7ewDQu+En+4jxnnlLyI+aA8EMMNVDC1JYFsEamXT/BwYCacmEzEDLAG +TrqypA9DTbEp6+E5JsCaRP39loKE77NZDezsrVb+atA/qIFjW11rZQGNhERDtcKJ +40DXWmxsMJZAIkW/v/3Q1tW2Krr9kYHPsjNERd9o/ioGSqZXQVXBIeF7SWHLRSMn +aE+R3fFTqTGDPTiQzrQIJYu9KlHSRa7BLpwiL5sfSHOF9I85UhgP/M3zKrd5HJN0 +w5ya75/B+E8Ps1G/Dikhi+XxzQtWZQEV/P2Tz2Gc2y8vN56BVkrYAOj0ZgjJBqF2 +5LRT5zfDigsoS4nDMkk0kqSGKV2J6vnu/Z86Z2f7ZSPNfjgshTWZ9lzmLBRiYJgk +JQWNFb2+04XKFEdPgmQsIgOKns2I8d3MV3iD2oEHEOSssCRuy1/WmhXf96Vefg9X +qdPgSxIYwCRSN9IxG7TRusTsRzG1OOxbyPVaAIfzmahJX5jsnIZZ3Gs1XYW77n77 +DI6Tzcu8hiETq+laRCmF3VnwNzapGWSBufwlbSSnTAsCLCwd/Yc6xZUnZZ1qCGeH +FTqKZRBB1faBm3yTnSww+2rtgrPsNX28qfgBCLxLCoWPtqkeZrrhBdbviDKPqYmD +OKRBR9wL1Hak0hLHWs2ANzXN3wKqQmxnCjeFh9HhRTAETPAquqlmp7+Ib4jJb6Qo +sce106xVQTqRIWhxVzykJDFt1/8TzD0ozEECuyIiJgxoqPFix0su+b6D2WtAgd0O +WoPaRKKnB37AWJzolZcYbjUMe3mhTDMGNdztEUGuNHgrZ3kt1ZAuVD15AlEqJP3E +Pa8ATnzVRjf9gWzxFHYGDpoLmbpY1chPmyUG/ay2QQ8qei/TrJFLIP8+8mPrhQaj +9/bSruwG39cfgsn3AFAPUttjgoWBsxnQLDx86l1eW5+JUm+0ZYOLWRtq99QRuds0 +b1ft6Lm2AzGonrKVj0UO6PpYumcVkgBdsLDw7+b/x9rbuWtUG9LO0/gq9ko1hRkP +A1Ke/3NRooTLdN+KDkLo15uhxvmgNhedXpZOmnmwz+n8OEWiZN44Gzg4rAeA2OOb +mX1uJXHoGF8Fnd/MIQsiFuXaX33rk3gaGXzuJfXKe5IaNWjewT3AK+KJr1pXwOKK +7fuQfdYCakuihC+FxtK93eY4VkYtx8wovKfikDdBfVCg+zuSH5BinmtQOUy0XNCp +tkIgWokLGHldwa377zOrg5TNWcCvJ6lTe1q/nk9yVOZoymNNOTl6AIwYb9CbIUtL +VfK+dAgblBf9OEeqcmDST/75b01CD5O3A7Rrn18XAuUFCzWhCUVrDjbKrZZWJZnb +IVPbJOP749vspZcGYCvjQReG3kh03TRcBzIdICOXjd4khCdPPYhn6MNf0vZmfK5b +WsAWRG9bOvQHv+Py5ScAgt5gBV4JIGIBjX7RUxWYMEVu7w021d54OXNuYQ/Mj0Wy +D0nwVrtXrgE/J5315mSW5mCw26KDWmolAYDBE/qKljXL8Ik1G3bcwOF6qWlZrCVG +/BCDtN0Ern/R0lzVCVD4/58fQNmjUsxMiuzGR4mCUy6fCTfjTk+CbAC6fyUA6edW +WSRHI+wuIF1hY7ixpfxeXrudTCJ1cKX1LcqkATnAf6FLbz2MHFiGKfmXmNImo2b3 +sJlcwQESvXzFJcpZ5+kwrvWko08ak/3SftnDVeiQwGTfLl1PpzuSdBVfqdhZApN1 +ydrxGgYcchdBvziMvxrRp0/VvXMU7cXI8lCEd/pcX0jXPTIvoKsRqpDxlG6f7jBV +N6kXN0FRUelLeAvWj29Mj9FxuoFSPGnEYxywNYM8xeQsSR9z8Xan6yjSlooQ//QS +3BnDwcsYF0INsyWZT+HYskWH43qtKhdTYxkxofkXduJH+K7+9GSaq760GT1CUaSV +/T31U2vtadq+DDIVi40YjDnSjk6nCuemtzqb56MSmvMGx3x3ibG0vVcXGu9hATSf ++Du/iWbjPCrJpKZ0VcwcizDtf6HsMoTN97rk8bA7cF4gwRpB5oeGni9+FnFEqxdI +DHP7y+cn0zh1nfq2RtX2rTaudUuAENZmm9T4YQhrvvo6v1zbZmH/LcyGLyHEr9Vd +ideKTyHzt30u5Ny783gRV4zSlwkKaUwWMgrYSV72StzPf9dUBY5X1B+2U/SRjfDn +dETGoPFPfabTSXpcFX+7vDhpqneFbxNihJwq1wf1TJKbuPQ6cuGDacqWluqe3n2k +XdF9mkqJp2AsFVB51PltPwEdwSLm6dtHxniQAsjCrG3int7SSjmuwRYPo+7w9m0K +dNj2pmalltajy2nhXkNw0WUa9wyGkKopy6atUhzBNyqXr5wA3JzD07rqrfVniaia +xeaLvVQ7Ty47JPGTyV/TmU7LifyhMtQYY0Jb2zc8pzkWGYh0TeSCZhaneEsgPlmF +qVGqCf6ewOaT+drTcHchL9hWDOkI79yvJrEQ1Vzm2J97f1dIeoR1xCGBNxhl//nm +QV2zY0b7D5zG+igRqUg41oinzh9g4wVP/U9OMvYTF5RKtG1RGD9lF/JuFqyZZXD2 +MQxeKXQ7nBBRDvkRhjzWInn5d4rST82m6ZDRicZWbcHTIlqTaRncpZP9C+RZjRMr +s1vEE5E8aWK4JuXfMimrb8txrEiWc/Oea1RFRXs028ax7E6VNQQn7HbE2se22pi8 +MT/5W9D3pbgds/wW8CsbrRi2jqoCb1D/rUsN22lvk9U2hhE9qqUVxWg9ybceMbin +amK2Ez8qYPcNSuqRGzZT7dURWErdKlgj93PEQxsR9M8ZisaJ51PDeFis/6BcdQo8 +tcJw9KzVJHO1iEkU+PpKExHOqdtQGrMrmVsgsGkLTMnR3ELk1MZIBc37qFAxzI/w +6M+G8CwH9iaidiBVEqDm14TZxywyl9IcdzWwzHjSOepoFbpi1TD40Xykn5SZN69s +WMrjJQamHvpTWgreeIQgKr8jUDqAdylr8Cp7uOg2YIbq9QseCA1uOVMKArrQ2rNX +lvVdYeycGOr3jHqqnrUQKk+bsMfvKNDG0BdPZgAVM+l2txwZXPjNqZD/nFUue6M5 +5gU6gMZc8D8jC+6EoslIfvWbmNA0Y5fmtfFeVScZtpFeCZk7eNANWISbPbefK9Zl +V7HZVSRpbAkV9uV5BiA8bpJmqVLToTNMTliOeiqwr0PNNMLCG+LiTPiWP/G7P7kh +6X+CKecck0EGctR/ojJD438+QU9PhSU/B5CSrZPUP3LADyTQnQjpCNf8Oe+ZyBtX +pSo9qsN8PmQnRXKtUacQWeGQJbRjoMk40hWRDcowgThPib6XM7ZcYWH2vnYSZpdJ +Opd/7voD6K9gmtYXsmdNbRB9DU8ilYG84G3+ldX0g3hmGHhU0Ebw7+E4uhrlb2lo +0fLMSXO494JIEoAVsYnNSm94EpLde7QXJNQrJ/lxzo0XGAtLB+ubgJNPdqGAhuuM +jAZd1wSY+xQ5zCf0yZI6dV4xVBots8jsagyngAAqFeJr8EcSS7qYNvnAnPEYty6e +5vNVVoStiT3MQlr6I9pf3NC96dkwn2v1bFPKS7xfP6wt8clAJmvUzheOZ8zSnUvl +AvqmPfqO3dGs872ikSU/urh3TYwG4KWaRBWpKqTldH9dG2XiohEvO8hoXz+U1baq +OP0q+/Jee2Yzrlzagt3xWG9ATF06SLGuvZdBbhRPAX1vIDlrmo3HROZODVHC33Cd +o6oAT60+uMUqg0MRdjyJyysiJxshCjjQi/dKLAnG2jWjCnpHyhFaJCcfxfTH6LfA +qw7OIZk6yNL4DChUxCiH+2FXMXC1cX6Co+uLxlvx8slSopFNr+u4XkrQpXmFJflZ +0jTEwwtul/cEWL+Yktq7Za2KmEBYROCXZDfTdRpvy9hMF6qidv7lau8ubqHghkTO +9QocBA0ih8yhyEX+mRKiubUSZYHRY7MSTCtTuqaCxwF2Oz6X98um1pGX9omVtkc0 +FeoBcEw8te+xQG0RFJm6XdCRoeSIGqkdPTNMdgZV1yQ9w6lVr4XZrxzj3ttVT5Bb +3bBfFnv5S3PsoskoDCZuP0pmcCVuxbVGWqSxAP3uFIQUAV/5iIP8ojJG226YBF9/ +TrRBbU9JmJe8qYA7V/j30pkC5Gl5EosGgTBRsJbgJ+P0bRWcWR0Hu1MskiP7Oa4z +JPN8o44rHHbYY7TPsLZeGqyvH+tjz5hU49IHpzadP5vGACxWnsdygYKJo9RAocga +IHdQL7w6M6KXxrHBq9gUt/J5HIBdT6cSkrpd13MJnglzDEjRlhpAxU+uv95yVrMC +HWP6F6lgCCKdjfPNSs5uZnBpCP6DXdFBgJoLzYdT0Mr7aBDaMD3Z8v71wdfzbFNs +4/J8ZhRzIkysu/7NibgUY81dUGU/a4gmz+3iuia82SfSymAPYZcQNs9n7STQsfj6 +CTaKZ567ocPwdVnPKJ1F/xV+O9hpBpaz+sJfrqJvQYIDe4DAlyRd46HHFbaRXkQ6 +XUDHZWW3YRXpwMcTC5S8hAdGOp+8468WS2r065NMdphOBWB3YKDCvTO4JkhAy6rP +jodQrjFg+q99d2c0zZvvBqu952IqbyamRdEi1h7dgVfZFMSh9HQIyb6eI4y54uI7 +C9hrYCciWKOXcZxVXcy9sCBn5rKwDt7NpCao7+jY21TodzkPHZwUe8LRJEppJEy/ +mRBVCBQ/hZ+hl9QxKFmf57gCV3teF+Dg6Kz9IKetcG0SkI35Sfi22vbC5ezC7ISD +y5NGdRLw35IF+vUvp+PEq/OOqMLsotD5UGQU86prCX5iqmzV/AiJln1KOQIJkPgN +nANdiWFvv/a9aGDe/sfy2YHjq35yAjMoEeQjdgx+Adq6wanAWrO0O3HIc/FFqegJ +zFz9IvVFQFRF4s2RGoyOJe3UHJde8b93691f0SRFUzuwwSgDVhkPSwZT5Hjy/+Tf +1UJTfnHrkT5E1AU8hXsKPi55faC45GWGtF51DeFTlXLGt09RMzxC8a8S0tEJ3rjT +9SgYdhp87Z7CIVWnyVv99L20EIyyvojOv3AHBVgooF7m1khC4U50yvjDeNGbu5SO +FB44y0TKWywkPe2CWCz5IGmUzk+sarLBcgz/6ouxvEYkwC06SpK4aHSk2b4PVKSA +QeTTRMxY2++T1fYu6mx3T45eOiAbMoYihMcbnVe833U2H5XcELOI2q97f5Cbq+DA +uQL+gtbEp8JW4Et1zRgCMQEwrZBIMC2x76Lo+ZD3B5Np9QmAqyRIFLtU5JtMFDod +k/jyZr/KXpuSPU4GTfVvobVGRW3Z7MeCeF2SG+eRsvxfdAiL7XYO/oohSUbdOpzL +ZPWZDJnEtxzxmxFo8RHjN1rB7WX4/W9qQE2TyRSchkhmusD77PfEw4p+awJ5TybP +cfyfcXH2MJBQ8qrA33+IWjfNc/qSyR3CBYwIxx7GiVCrXbczNQ4pknlpHpvG01wZ +zhLEQQ/AR8NC9vg6lUDnS1PKNrQ1YWTvQzcOE3McirDyOUhuQ6YhK2jLM+D3f9I9 +bNWryN/Qj8cbA3jeKABDyTeICbZeugrhd3KwLqiRz/uaFJArNhLI2Ce5vO7JsV+A +Sxu3XuQssDgAjwDztVybAOVb7syGlJ8Lbe+uUf/9kqErbMhcPj7t23b+pfe0XoaM +ZsF2F9e4rBcYJw1UW/BsrhPRNn3ivzPrGNx2KB7+rtlKo++XhQDHXlX9MiVW87Mt +UNVaz2RrD0/vklV6Ru/XsvZydlwAyEetGfQd4Q5OjcWcKZ9x4tnGekoDFZD84f95 +LOMhg/TJvss4Yw60+Rzgc5Tr6ijB9MoZy9aa4h0Vv4FONWT15Q4g6FFua4cwIyC+ ++PzVKZ1CaqkcPChpjo1lq7QoyjR3WLHmtMFgGcPP6STtN4tvjl/wcc7K8WtYUyqe +kdBiEL39vNkI/fAw/aPz9EEaba9igee+0QsFjLKp0SCJxnjnd5fk6WWrQzY4D/b8 +aIKWJ5b8t3VvyhYxR23ZJBQLcvSGpfnrzXLcCD2qXz2V1RsHmYSxUALXygsgNUvX +2YFxAxVgto/l6FgoAHzpbdGNd8pKYGUxCU5CohRziIlq4DK6ygQF7dFtadnoUt3/ +EIeAx99ZF+5rJ2M+AKu7YAlTxFml6376in9oVcxQTxRuVSQpYStfcoYK2nUDl3Wo +Un7Z/Yyiq3fbREMErB1MLZEiLplkEvLia3azF4sO7QZZ0+Qqys1S8Uwm2dHSnSxp +TRi3GULdNRmfe+Ul2+916xizW435Mhai3otBW9U071QlqWvN+U3ziZu77JWdQVH5 +48BNI7dLsVXah0jK8ehgA9HrwHH6kSd1Dj4s3VONpIUs3oQYHHv6McgkKxNA5elI +Q0Ihx6MBKUqHY2nDiPAC37/jDw1qRxkuVFoxSfMKbC9k/DE7nVXqrRtjipC1ztDy +/kQNTiQgWLy75rkzfbzQQYG6ivVx6IzY9fT/fs3NCPYb5OYrZOpFEING1UWqQ/ty +NhsCgWXfk24DogKUTU6yqVkLx9A8DlGAd+9lnhEz8EotucguN+IWi1w5bK5prF2g +5E8K/lt9khSBB06AmtwgV2SxYWnKjewNMWf+7Zw4LogPlsVrmoAnYenNZm3BJMcW +4pzF1kksTXO0e4DKH8vNJU44//mAmiOiuHFpVMp2j8GNUYo1EkVHRRnwjrZeQ4JM +Teqia/n8hunPMnPkGDBNtSPyX/lA7oISyXW1Lx0pXcR3Jw+dC/tN/8g9qafPCaeV +aEP+qO4JaS3as0zxTjHFVM93g/gXVzwzsua8rA0Q+m0RfP4zqM6AHArSkb84qHCN +KK19XQqIt0hY6nSkrEAYLlrqQ4eaYA9nlApBRycv+wgSGNpbB2qohCmb/cxMeRrS +d2qOu16jg2nJwG+qsdHqAyD1zCMG/NwrpsphMXzCfdpEi7IteLiQwgdGoyXCgvGu +5sY6jJ92R3awrwWapIoHyV/CrhNmQhFnvneDHvS8jtAg+MH9TABpgkuQvWACK/5t +uZMJwq/Qls23LWyBs1KhQXvEtj75VyD4lpH/CtGHfYtpkZfZmpFbPMJWrTkYhVXK +XvGsyT8XcJKaqhYUjW7ytaYeAs1dBF+tVwZTmbYPcVj/tIjcFD8Gf5BV2iOkrODM +SYVIeA8vEhXIneaeOnl71gKH9DDTw3nFnpRF/Qz/GlxWMKsyROQ/w1Bm8faPyNTE +ld0kLeyNySGgbzNX0ol689Yt/1lmdD1WkGC7YmR7LnOQnApyqirCGowlsMb4i2ej +Mmj7LGO+mbSuzpo6Laoym8U5WShyl0NTucn+L5orQkLXnVS2YRaTK0GNHIl9Np+s +JU3hMnOCcRf2r0QJgw7kwnZE3iF3vj1x089/KlFlK3qyNkjPVi7xA87JDqebaFOs +yHtNJsL69EIdckEs10wjmCK6Gk8+6fZpDOVhwIPDSAd/RoXe+3PPSY/x+W6E3qSR +2AlIaJPnEAnuBnPKRCMQlqhzGNZZ9428BVZxSglNg7m7Vp7G2Z1t3jpjYmu53lpE +elrkc2vZc2bpfGdZv6OSyfA4eyiqxbPfkxItUYVnNNy6RZcEwXNMguO+SsaoZdzW +YD522WRJcJw6akmypxS6yuIYpWCGyBq/RSmwO2VKdu3tXaOuN2xhgSjyXf9RkDFX +lZTTmiAdP6gKd6zkHqRhHhcJUhsm8B6aTfRqaeviDmCndifKcwVcWTmIHADB2c+x +J2qmazpU7USJU8dfUAj1NDy/ttAcmiOXHd0muixJvitDlIeP8R05Konx3ZTT+zFi +ZsutWuMXls9rNNRY9QoscGammrvKfXSqWa1sCB96jSXWxfqZ79P8rqNYvThI4JQw +H/2JlFx4YIbeIbYmNh9UE/vfRq56FIfVi5W5jwEwN6exTm1IqOUP4vafUZMprdMz +oH9xLwNgu9D643NZZRkg68dkf+GRFXIP4yZ/jzeXCJFRAOMPHD9rDltTyRL7CMXa +gu7P/O4+VWvk/sUtP6SIohg2oQNSIbNq2suSOKiZUIC4LmfD6EzMdoAXxVBCHyLn +bcdqSDrBg+wMOZv5ddTv3dAhWOA29jbotlYG1FZkXAh2VpIfg7aj5vEoQXqr85JE +F/Q3h7sZRsE0lG6msKWgAu/wRUdUy7hH1EMY55V5jYl439AGGOmJEPmAMqbiCeCN +WdHI3YvYye2duQ316rBEB6okyQ/2xwKlEWjTvCwExXbKan6MWX0/MN+BTC7C+rec +t7nTpdkv7dop8KDUqFwNKZI0aWRia6pVATonuB3khOo7lV9pRTfGZd7KsCeLT3Vc +PRuVQFR6/SDkefc9mDrU0zgYepLvfWo8pxmlCI4K0AzXyJDGRKuIwCXRQ8k9TJQT +nan5fj0ywUtK27ZIXteCN3r7nTEBrsx6cyMBT5/ArKerQu72SStbE3iIf4fEPheB +mferdSQah5v9JdbO45yMdXmBdN8yHFV4NBEI2hIRXjhzn47rkCCfxPNQF03VM4RI +Qpkvaj7akqG+5TsGopsYtINz5WsNz1C0BrW0gFRg0FEkLYyUQj5HxTZwgu3cKNb6 +yk382WfC2F870FOLHMKdlksOd8R5GR72A0/XO99Ub8E97Ps3rBlh3LgNDdACswJp +5Kc1rb6dBQ8ZoBNbwRE4jL7Tt97Me6dQ4lHyyHlgoQ7+ktkT44gq/RsKmccubGg+ +Xkmwaeq7+x09P73QO3DMdRlBi/rNMp1gpuTkmRJ65tPgypVuSMj6QHHD4Bqkkhvr +ZdoOXq+ZYx0ojLN8CrRTVPz+EAQhF4K3Z78rU2S7H7aPdRXMz46lXHO7KzxuoWtt +YN6pVY8lHciCZJrOC409nqR5ewxJS8uxI89hkLh3wG/jx/Inns4MZh2OYqKHimJ4 +dK4ZJpp3bzQ+3GatyL50eRIiwQCWckzkw2JFiaTAQ8Zcyzh09jIGXFfht3rT+67y +yx6PFASKgyjtmGuM0A2CxnOT51NG4gGOuMnPfkRpG1W5inwe9a1J+8KQqCPqA/jz +TOct8GzZfWbvy+mwj5uVMBScPdFPN+QC7vg0GfJWJZ/SIOL8Y8Vc7HEvoQ/BPmsZ +nFYsnI+LU9VBa6Xi3TYrgxa2dqd8W/Zqz3nyYzgjeuBqPpNq/X+27YKgyCu7hIK1 +hUEh+NkPUbkf/8cpvcZy77UsRGztRAGQs2j2T98PrQVemGqgyupqKOgH6MWwUjui +6M4O3h2UXcZfe8CYhjApveblYJqb070Vnc9xjzCypfVMbMON/E0DK3KM53lPCjso +fzL5Zo62D+7sDvxDSvH+WcJr/IMG6aV8ElocaXuNd+5SwBYOGhln/rLIXVcoW1Ui +JAMKiJTBU9IlysvrqXuWddyCz6UNJpY0DB9oahKAZdhrdzolnflR6PShIOhTZuAK +fWrSQlcOYR26yNg4zG+BhVFQzGsgw8i1P4N7gxbhE3DFtZPf8AIVLvx6UpF9iRYO +dLzKJ2iju24anjBbpWuyJGMtPvHmUAHyVz7lT8PCuZHDzdyUfuDs0f11skLOoTz9 +sF//d+QnSpqVwptuyemjRJWGnfjSmq+OIhmStdLpS4Mf/GuhW6AO+Ina5008mWEq +abYKI+x+DdrxVbVAKd0uPMSRYsWtvE9sTG8LZcnrQ4KvKy1bl8sWifab6XcMQMPm +qwDqPfi+qMBG6R0uIxOdu2KUp5c1jrfGZy7fX198v0IQt1SJGvjCsZ5rLrVAAnHC +aVYPgX3/0CCIiEbZ0CwHBlV7x2+k2EultGZu35aslRs1NySLabko3v2m5ifyRdDm +FAom52izhuEGKYrlwPBsiOC+TTLC3O3ItMr8dA7IZwU7fv+kGuWajYn5nEHGOwNz +Z/SGWHyV/KJrueJ/9gMRLtqwQ3TfGbUYcjUEb140cCWpzBCtxTX84KdbHxYwHMlN +NeVfacNUFviukVGN+OxEvUcgke/94Mkl5rn6twe7zMNjr8zTDxQfi2wlQdhA0TqW +/hhIyU1wxUTzLLm5UXSQJMBnfAo17dToieiQZUXbANaKKsuXBYD0gWwP2pm+W/12 +JyOcy7oLYunjJZ38a7UyhnxQcAddNnmAyi1o1Oh8YzBym5/nYcXAzMVbkSMpZfGg +liJTQtakH7yjQNADu7FRetOXumaFpWv6xlkLy86guWYI0AkPRjA4qpxqmT9gqFe6 +foTVKAEiz7c5y8ODca9/iSYFnbucOvgvIFowKmlClmFtshiVgyXALLk7dA7tP6uA +RPwGsGm8alHrpN7FPcPV2qZOi2k57+rDrUIRzUsSXkCnAbxU7oauUC70TfBh/+kq +Jggy73Er8Pb/yELMbRbr/efpKxbBp3th3J636daVRoZ5IYp8LaiJnbssOAH/Zvz0 +QLPVDLnQF8W6XQy8WaSoeBkhapYYL7hpU0JKvyqkckkxmVPhW+dqZOjav0bD477V +8PTBi+8j5dS6CWeAESSrcpcFeYDBdf4hIJ4XzFiqMDD9nQse5bepEV5tJo/l9gxp +3YWC2frWDVDF8FVI7E09XhhDOM7uXQMK6wQyB9kLwmqo0BgxRcwCI1JqqSILv81h +MlUxsTihVyF8YvB16yKY7jCeZnD4S2BsRtrPXZ3cYp6RSzCW3Cu7DS0LRpt6a2US +2wpLxW3KXoLVoKVEtElyr0JkpJqN8aGQu7j8RKe1LhVyfUAgf2Va+v7cANk8XQX+ +ZMVLeSWwKlOmeZc6hmUOsJir+01iDLocCY2WfcV17VBDPfpGy6W3TxrYyqGdrrQ0 +Elbz2ljbJPbZqzn2UsEA9BYchJPchK18p1FsH7uYE4ycUXwraIEO+H/uCAeKqsog +nMYM58B6VaAd5EH2njsy86Mc4n48mCjVLjK39H6gOM27hxZ5QGbCFfDlk8Wh1N6L +M6JW0aQRNj6NzTGOvRyZScN8qWjAN3ohhB5fAH8tI8/QMktXv2qpdOeW59CEqhhM +YGk1Hmfg9dCZ1RW8xfRChbvLys/6cd2zEMSpO5bEcSG2b1GbIvD0Z1r9l5QYcotw +bNWZ+olKd67pqwvz/MxgFpRQjLXGD0o9YLNowiv7wVVR37d/oD5aTdI9KKVh5yx1 +/J5zcXZli/2u/4hjYvFZCqgFPUZZYKSn+ivBrVfe4ezaY4Yf64xywbnx4Civ/KdU +jNeRDdw7EdCNnid9uj5p6DtWm5raFWySiTxQmyvuErZvTmUUwksOCy0A8Jva4lMs +ypn2NYifqe4lqIpzHtKYKPsJMN6dpnkZBMfOggTPlyTCp8xcN1RVbuC0diXhYZX4 +rWJc2ydytp8rTOxWEtSPtf8XUdCttd4QGhpCX00PGRnHsCJ8rXpOPIHoKzGpIq6f +JUJTbvtonC1EjpcMVDZ88/Xiv5MBO3SJRDXowtJ5xgD9tXMi4/p/A14mAm11MUYA +2Ov4ID9DR8rVnNTV0qwssGogicO/KEyM+zqxJ27qBLxYDzmrHHLgFkWILpcrc8GU +OYbzJER3ckTTzCLqD/mbQZl7zcaQFHgdsbwvO3n6yUCmvPeI016FcaB/hoyiWxHR +VUqdmazf85eIi2SkW/ep0KHhRMXyOR14icDmCQsEBn3Pgn1xJ/wp7jAMtVZgdzIK +wi8F3bXrgBO/d+BdiMjIT10LCmDK3Jnidt8TpmVeFINPCfFII5Em0ecFIVIYqtAT +eN2Isr/TIsEZoLs73T0wnlMo7miR4opH2NDpXnBdeazIgh4Zfp5eXUB0qUiwYeYi +z1AheWl6bvmR1wpWnJ1WPfF6ACRK9ILGB9RtezHaMvhriiIMYv0y9y5kSBQL7bFZ +P4jtpIQaUe4STWaeIVgxUaYqRUGkRabxcXpic/wUNfj/zxbRrLXV4zVnyhiyVFQE +THmwk2h0cNO5y30EDnyJng5Kr3vunZUuUN/lYVlraOjy5I5PK1ZzWvCi4Y/5+2AD +NYDuu9I2Uqwj0XGe2twpA66PKx7Aq5kc29YXsbamHpGvqeKwzxhtdZfdb9L2RjnG +UzU6gpk8Wq+tDYnFTx+queqrvFyVxBoD2Q1S/LrFe+OOrzchf2pbka/+Y2viS6Hr +l2/JoLcZlGfD4Zmndbrz4zwhwyAGwQ2h8ZUINjr6klvX1GWWeeofvHxdXjz88phE +6XBJw8kVb7ud5aAcwFcUt++VLDNst5Ld8a/y5F896sJtLFdrOqFDBu/Hfovs+nIr +G9S5insoEWnBGBgVaHBu0zrYLqAq3B0wRIw2D/QB/kaswrm4xCotz0Z/wURB9q89 +GtLVxeTi/gn2ldMmp+taVA8OvzdaM1m1JXPqqkANon0LN9FUTlkkSZk9LPV+o/iH +V0RGXViRzQsvRBKGae3RDiLJIwXB4oKqkOfRQmDQgp4e1bcXxOjQC1xPK/ASx7tL +xwCyGnqChwYj33YFMj1zwkJbP17AplLdn5Q5O/eW8rcUWlvA4Us+Ij3U0UdJkcTN +C+8JvZqvlIqTd7Dk+3F11mzmhzNd21wi79GmLcoWzorgcXuV9xNiw2zVVgm7fC5x +PTLhhgn73r3NxBNQin7vPqgFOT5rTlAwHz3fMeBY3thIMIKp9BW+b1s1CY48pZ6/ +USsVhnuZL1XJj33P42AQbV8nJ55ljb9/qounDyjbvZz9ZziM9ZEGJhUE6xQojAPn +Z0WcIMgVI7Q83V3u9Jxd0xQ35XeftRTXrZSpIekTmrGyaSXI0UDf/Kj+3fNA9o/L +euWxbmf/oA1Ixb30lneSykzR7i4tJCDNKMv+1GCHGGXsYvFowLtTLwSRe4THkpgT +EaqBXyV8mhd7YNZ7S8KSh6tOvx6emozmVcG2rBcknG9mihOF6Dt8HWRh64udxOib +bki1lz4PyT38FHDfV0XwC/YVHQblJdKdOKojPzi6LAr812JxE/04SEZcvAf4ctcq +bgNVpczRZgDvNGL/4mEjbJjrSYarx7nCod++ndYzcStVC5xf/r5F7nOHsqGTePni +WXeyZshoHRkF2yPVlp7ytHE7efE6ykEvUvFp32981P+LCehyu2Dxxx2D+bufixtk +EZSEKiDgbbGitcZtO93qbQPNjZPX4GT84zuhn8O3661Q8mcVEck7Vc8uBOkVoBL5 +Vwtvl2c3lnybeOn561rgaQeHiGMykugvBQvnDCNjArJ5eh7PW6z+VwUj3wmWuJq+ +K3wEtanFk6G/IlGtmECWUjvgc0DmGqtmB3ETgefFNlqHS6kxbur0hEod2IMVqaf0 +YVUOtSqbINOLJdsSTH8Z2yiTymSE/xnOjX3f6SdorCmu0g1MpJm8wV7DRvYmMlEL +gnOxNYGAC/fQH4ez/e//B+U4h/b5J4ehbvVtrJ+HIAnzMrjl48Icf5yMtbCdgUG+ +ig6KS2yWSUYbSCJdMua52pIS/L4Y9boH9yl9gyNc7nOjD4Y3c39ag2m3uJBJeDkt +0msyUl5ZOS43V9S16B+IOB2sQ8bbSJtSQOJQV2CY4m8VP0J4g0NRjHBC43J1R7ae +dopfV1tToSLK0nqgMeClnNXC2ixerbl3QzsfkO8xgByowXzTvj7iQcHI/sOaKLHS +BtweeRBFuI9+eDV/N9XHzvFprUEPOgAJSVUC1acTQUyai5M59paYROQJo8cLtZJY +4Z2c3JA1Q+G79GH/IuG+3JHBtDiJtwvQtmzUbXmXp4emsUAsGwR/giBToDlVEkDo +zWDAT/Wzl+FgXrHeVZExGpI5b4c8waXE5qvFdALYr7EIp1RZbcxc8odRvwFZ/Edt +bb1JXUaob7wPe3fWjhwL/RkDQYcDUzWSP97wET+ciM9sdaznPXUPynP1uYMaP6Za +zv4xvm5AFN9jKJbsus1Ii2UfojT1fmP5oGqg/3OuQhVJcBIewp28nDEbgAe14aZB +txG17eOVm/x3KRqbSRaAgUYmB3EbVRuHOAwe2uWZTg4jABqS6a4Kp1zYcX6Q3+gO +9XvMf8MgWjy8wxQ62mPkWtJ/Sf6H1vHF22xZYpUPTbkw9jtmVIb3IbAW4ovLeWiK +l3N+ZN2fU773RpoKjmW5lMH11cx8Fwxdt4QTrChuU6lou4HXAYCuQuEKlpvEyWuv +NrvHlX/hetC8ctsVe6cLiOnfRx2pj9IeQkFsKgHk0BxP639Otlib2GXaYH8PKSNJ +jy3JMlcyoNukfcU/zCyTx/EHOa7fMijr/9w+2PwOhC9jIuW4bLXNjS/aYgRDLY39 +t7he7+s+KWKWF3R7eYMNED5tBABjrMrbtmsm2APMT/Vq92sZbqvJicfcSTEyDeDq +T6oHRL8zeWbb9kwgmGfyO8PbyHUCoI17OUVltyfJmJxt1SH4jIj0z5uTCD4mnd0p +qZqY1JxEMDYcB99XCY66IfRr8CSdg4T+AcGFVcIx8/g8QMELS7derJTyl4CFopSb +L79JdynPrBOGelK1GhHosOomeqx7eBxSCMWX/UIai3FCjHZagNtfXrQBZGOGwVi7 +yh06Xk+eHGAGYpE8lSwkvubBRaqjsA8LoczprOrvAuZTThxAXC2xxnYQX3u/1R0X +pvOXF4UGAJBl3hfRrsFiLDLf21unfo5B13HWGoNwVhPXSlMn0ulhrPl7GziN9c6O +1Cc2HzHS7Rqm1NoO1rjCmVrP9Gso9vWQwG2+nCZ0Gy5Tj5Ozi7tbwmPXBq9Xt9jH +8+CP36Xv0eCoZIh/i2oj0xuJcgIKOcNbnAsR/hVN13O9E6Ar9xR3MgIkmX+0NpCa +FeZopq4emPBjBbNzaPIU0xbTYUS9UNf+ia5eWp3JYuLruZXjUAISnG2sL5WU6hO1 +hvZmwAkoag8ZCRwu0tw8H47qDgDtA/1rY0XeG1OqYxWY/vogkO+gXYsMHASHSBgw +1CV/9HLTpG7S6JQe45ZoY+88QR2d3VIBzgJ4JRrK+iu7qhtT0nO1lFOceupkeTCY +a31K5w/k6MRyeWAdVxiLF9GG3Fi28EQ2wYCU7ZRPTW7dUDC+QmAEgDcVNVlL5s+4 +BTpiFdr6HNFCzzL7DIeqbmhRbMCC/rp/eRDdh3PVGs7nUPb6AbvktAhEGe6cgH71 +6K5YR7hgMfdXwNFae627StCNhPo6uX/kxawSmJ92XJETE91MhLlr0oBzPrTQGZht +c88EKvwWAoUzoJxecP/0DbEwguOIkAtcmd1er72ig0O5VUm2FS1HLy8tTT1Izw9k +uj0qWeOLNwlUNSDb66VMx3uG2B1q/P/ZTBOQOYaBkoZC7x4XPJIiOvUnD5KZp6Mw +5CwSepvDm3NuuKPtgE8QH2rPmoUsH7MGhYAPBopXw+roeRGk8iIySsKfbkfBmN2I +DIoRcsRtYdrYWgpSmRaJaU8LJ9nJIYmyZFcOxTtP1BMBjec/uO6FVtxYKLasp5Z8 +RVHxfdwDgbmAdFeD8iLJPQPkO486QFopWNLebpFodUqUUKz/BEwvm4DKgx2uveFZ +nOjcbaIhdQeKl4Bqxkt4dihCaTj/upQIvscfnukRQzr1O5gsxBzZ+MUVdBsezfGL +DnICLXtyPVUV4PbSws1GGnmr1cNKPInlF5SGcw2LndahhfbhCaTdKfbFTINL9VgV +jTH2HBLK65SVtgPSeeWPEReZUSyzTyepN1YoX/dSxTjeaxpQW8kNaiLdtqQv1pTz +Lfh3jyrHU8LgXZoAATgchmiIQLOStjfCVyMiaaxvJ2MkbdCFO5oYjbwSHKhz1I1P +R6fLxcxsUHQJht0tt10zGli7xXcxJGF/tzxvxbEJimaT508LGrpjLPqzK6Ldowjt +Uj4XVB753wm4tBDUL0oVdCWmC4fFN9QlFudDY3/G0s8FHlObyLGJWUJZoeL9MOet +/7ec7Zu2KUuiKtabmYIko1U07/DqOldfLCfq/9soMn8yMUCRjXkb4saEgMXg4jAo +vdl50fd0Rrz0tpMEiVMK4C6lwRiGM5fQposrgEeDIib8/NjP3A8QeJeGKWqfXQLF +SGoJ/oeqzjaFH1tZXv9nk9/3LUCy2jXlIrI5Y59fi/fbouA4+ggedGwesMur1kT+ +GHJPwRT3vRmRENe890a2Je3zV1MehQchwGSziqum8Hm/dd05DF4N7agKIc2Xowfl +AudZP8rzjRCCARAK/Y966AXq8hWEkAR0I8S0+T7oEM/nvUydDHQgKJUnG7u4LLlN +WBt3FijP1+UsB2vYyxLp1UBCFn00faMWw5xchjsDGTE4wCbarykI2o1bsA8f/0Pt +n1+D8eSK09/m5xyaZNEaKSEqXrAxqrLekN95q+/lz+eiK2+1JviJZ8r5VWbhSh31 ++LpOzEp69uY7vItKo/+tyW3K0MFm3oNgCvsQC+rC3C6Q6l7Mx1BoZSGB5hVF8f9f +AJ4E8hP+T/31npDnPLki7EhcI4A7zd7hTLdJh5wiOU4/6+wR2kOZ8htxmEH7WaDc +BJ6o91P2Ir0+9b2YXXdawwSthdMadhP34ClEBPIMRkrNHIVe0T6tD44IwtlLtTB0 +tGumHCGPMnaUBhEcaWxSop9JWqRdTtx5ffaVbXIdZ2HbMkmbybtc2Knqq5KQzw8a +paX5f2/AzgVQzRcDp5hmqf2uRZnq57RvUCnjmIVnGcNCIV/59/WFAxd8/++Chs+o +UNyFgdY7zLXZk8R/2Z/Vfqp2mjWAdUClR51l2q7V599B5mooLwxTf0t09bZLOala +kSCyEDD0yVUS906Ia+R6kOn3GHMnMdBJamh39izGHuKyBaalHFfPo35wbWm4HjOs ++WvvX0p6GUVZd4tO111jnYy0/CmRsN1qyzK+aOPr7YliVC7hsNg8NYnkbcq86dpq +ZXe2+LwlGrsWloODvbKDrHjt5NcdJ/xl+aJqZVVYMYb/34T+zGBsxHH+Wm/yvy2B +yGgCTLEfeGo1jY/Pdc33M0oUyEKTPZvZZ50QBPY/M9A2AE16VpPtJO74kzI56sCP +qGdNCLUJoA197atCbavsScvCXYm/Gl2z3ytCQuix/LeENhvwo811JHWNDq//F2mL +48YNlziXdcnp8h3NCvoTifZnbyx62R7zhnKAmpy92bcmzPvC0vXPVgrKeIzLRMeC +OBfhqXnJ0LN4XU7V/6ZYHl+29gONZ3a9C3HPX3BD4j3tF0lUP7hdt8TpAGinAghq +geeFkOtFnWawon8xR8/MwUnsXSLNI98VnPMtCzw++sh3tiBvUsuQANtPyHb8SFwg +ZnwsfOhlSS77c6d7OY1Bnu4twC8CqJzzxBaYCQhhHfZyMtTLp4j9IQv/LiEMB4hQ +GKoh42tqqY531n5lcsXeoaL3m07BjRXGapuQQtSf/YnuHNvQa5sNtSmHTd8hnQaX +0q70lmv7oXaXjC6mMeaLaIVD/qd3YwEhMOsAPHcXfYa8BxbTrg05qtt2Ra4ZOG0T +oIrg2mNt7J+6SggkWovjrOOnMcqiz+haeipdJ0QDb2frk8QTN9dh8fSsQRpjg1Xe +yOhEYeM/Bn0tSpy/xbHOQWEQPNGYLEVazKEPEXltVedg3o5nT3fuEG14IHtRzvnv +lSYy2A++Qbex4QcvqUevJwpciKJM8mqJxqdGcpryqhQKMkPxazuVbcPITAYeK7E3 +yqbb/FGGIdw0ZaGTLiF9yiVeucuyEFtVsdtELjaf98zTfYPHbWB6pXcrpECbBrH8 +A6EQTKx32OT2JWTyC5PziwK15bzcLyUI0VYWqzwlicHb8biJfuV7Q3rp6Wht9ioS +Pz/5UiNYW3oTI5khX6hHwbk4ub+oZkJpm67iqVxyZv1g8XAVc69Iuxr5OMNW9sES +hT7Zz8+JYQOVEvMIPe1KZV1pncB84XpGz+ZbGFcDRwOgBeJ9rgF+5H2sogVt2fjs +7RTHysUywFQuWigwZaen4WyPDTKE2ai8Iv97xcVyAb+/Xzh0gGyi07g/Wdx9X0K1 +YrTc/BepW/UGLD2aVieK0VPbOLdk523QetWWcPgoFFmtzk/ypGaXA9Vdej1O4joW +E1SyDKIy0oX/yx4urVwYlUCNcL1XHcdIk4YltULLj3tlDzNrNT6RDAk7ZRQ/gfmh ++j/eGwaXtaH9libwHlVOVDW7g8YigPda3ED8dc7QXDBTV409nay7lkxJRMJln3e5 +1DbThnyvYAYGV34acUCJpU9knlsOw69m+fEQDY8F9xZyCtVsEsGL39B30EvgYWNG +CB6IPXmh0JhZjaStixwUiQ8dxDObhNDG0YRQtZAte6f39MDJ+diOQl9a4FcHtl2C +JT6JTlkA5Jb1S9T78neDmbkGNDsLnSRJsZPch61VlpepvbOZc+aM7p+owmhzlWCL +ZKEbg4qs1VqNIqywDJx0PO7/pBJPfmrbBI557spC6ax0x4qPTA/K3zINBefPhcFO +aghiRZm+R8La2CHYQ1Kta6iBp+g4NMErsyRjqhEZ8fPpBEbGPgGwGcm9DO89Oj0m +iLp38vz8f5F6fiF7qVyZHdRt32QAzQR6LMNNBshJE2eNsnDTjtTHgYHVSJSTmHa7 +kXpVD9I7hnVah6yfqNjmor0DegPPLqeL6/7v5V9TPTBgIj17ohPoa2zVPl4w5kvp +4LVsImDfvM0IV1ApQyERC/tqIIsER0XtjM7CIBqPLt2Q9ppQVL0JtF4YWaw9egvr +mZqaPTUSq0XT/ZmsK+3FUgxpDfXlZ9iu0MsFDWuT5rfunv1n+jErT7lbr5CzsmHk +eLvbGs4l/5FuQzBWKFDCox9BQjv+HmhZI3T8tSTvHcnAJIN+AnvYYRKu2E8xqxjj +SR0p7qtFcUrpfbgssTb0V36rSmebRzMAeSQ6ASi5tIe2freB0roDaQHtv55E306G +oRg5bFO7/dUOGWf4wSxkHYbPcaZNmjJaYU3P+dJGbsGDY1iiEUuno7bgDG3FP2GV +1o2xqsqRRQpSrtc/7+AWeTvf7qy960rFZsxP/5O7wnxfZnbUDS/wWNtV048PGOAH +7d372eXIg/t6iFZTm2b+YgNXA3LjCzEcexe+CYn1huXks+GRBHGnU3+qtbniPouP +m6pM3RkOSSPArdsnv7/Z4R0dp3k+5srdNmJs01cLeq48fSqYI4I9kQXc1W47OfKp +IU/tXMwweXDWTrLbtSZrbueWooWKAA1DlESnjfW0R3E2tXlX8svenkz7Tjsm20fW +0MQClWWGayQa4Ie7sij3r3hJ7c36wdLHxCrMczekUubWu+B7QT7ha3MJ42TJ5y9y +5UYVZzEThJNNrTvRBkuZXF2rSWOLzTprmexDq32vvQHy/CrXDqffQa8m5fgrJWpv +W072VO3ENb93VK+5UdowZKRBORFZ5663wVWGxk+Ii5+z+Ma6yoomPd9GeMRSnMhl +BCqu2tyEx3KC7hUdN61usZSexJrcSQIA7dI6+hNRiWlp2oNeHqyuK8oPOnQC5ugy +u68LEvTJ75qdybrXa29ZK+YHr3f/mfN6dcVvSYqPTnCZsLzKXsxlhUzjzC3PrB6J +EZdLePHV97eYQ51DHZoqaGqAIWadLAhkhXjXL8JL/5gqJt4g/IkTAq36MlRMUzbw +aedeZjTDyxT7uKDz9R9J+5fhhcY0xQlZW335u0QCkSlY0FmDxO7146R8HirDVmmz +L2JGmDZZj2070ILgpAfHp1LF5uXdX2/509Z1Rtvnv3QNCEzdHPigEt64BooJOp30 ++sM/GWfQ3jJms8abfgBRfw/vsFrvbJylkRx95HotjgTHSNcZeg6HOpG2OKw8uOAF +boWHEawEKoVAwz0co+BNSwCHdqFmKS58knG3Xf23eA7m86CplPTLr09UIZg5eR2C +0oXJUHixHy5Orn3ZzOB6U7MNw+WMN4LpP/iqwJ1hf/cV1MIIr61hQjT4DuBZ/rhK +CRFO0vn4aBKy0ZRggqM/zVs9v1FZ4oNVOL/VS6HzLo8kRJO4mTX0UwD6qRKz6XBr +2xjkJWXMPOmbbIgVM5Bn+1L1NQ8vXgY/eTnMta5+UWqyZe1wW8JPxU7RbJMyPdfa +sHmyGU/wBRbYXQ8JIA+0VDaaJnvyGKfa815LvK1zLa7EJblIQixoFFJhblJlDxWT +LH+MqCuTK6az2lqs1LYeMX2L+YqJ4x5iyd4Vv8b1Tz8+bupZwtbd67gKWfm2IzZP +x8aXAJkMnYgrWe+qMCLk/KPbe+dZ4krwCDER5gmUtnbZqtgO/N5PnLo3Mt9V1gW4 +bmox/plPvodzx1a5RhtBSLIsBwfQm80KO1jKrj1k0m9vvIwMXBXfPf794GZx2+UJ +qNqhvGbIu7Ogze0Bu+WgBLFTJIxa6pNFjDXwzRut9QlBKx9FghpuikfjRTylJ/zF +GEr9KpUyJPfaz98umT6I49Tnv2t9GzCTAzOawCD2hbcFqgaXIwCBkE2lHnZaxWiQ +ZlpZTGYHko1QYVPcnnnJrN3Zd6tzukqoVT21D406qli/sin90wmS13HQGshh6iiH +QPGXkt2zVVAnww/+U/67RQgVcrIclZrp1KP1s2tkngS7z7DtXQV2W74QIzE/344a +hVFRTxCUbONgn7V4JH4t56aDsgP9jhzutFdvfwQZv7C8591F5LcFnlcLiGI1ZbLv +NoQVJPwJhSGP2mt+xOf/0GmxKQD0P+dF4Uwxw7JK3AxsKVgRf/wrNNEQotLi+Qjb +wizX+qhDbzGHrnQ0GWfVkOp+8DOldamGsgrmboR7YsB+rsFOgIfpBUeoJRwifyqA +kQEdP1vSqFHJmcgEIi0H+Ao5EXme3QZYTBIZDJTHN4MiTot8J8kveR+cFp29D2qX +4omxm5bP6SemEMV0MIpHTecqCr4wCJqNwTxmfQ1KaN2FbZ3e6HXlXwSJAJ/7WHD6 +MaVRoNhTC5RG9ElmvUqX9uRHsg5iGS7DtBM2A0NncSL+EwSSz1fEN+XdRSy+8/2e +qUfQrJjJqRlsqBp+0/ybk8eu636QPtVBRiYvP74vS3CBhL9jVW7oTpK+smjNpAT3 +0YKXgTzfZM0M1s0TcDFukzdp+SGS/nC44nYfDNM9fJ4dGzWHfi0EYB6pBqSVN9DV +fBrgd0vLYzkuQewldNOb662sbtKPVZpmtm/iduB044wqT82UpCPlbBlCZsSfONXH +/E8jMjPnc1iJGjokYdU7pFMBOrRMlZqApNw25lxBeloZUavd0TJg/Irkyiggz7ew +jSZMFj4zbYX40INeDvG4PSzYxKTvCMpysj5Wc2CJXgDbjRuWVN4pLf/qjp99+XRF +BD7SsNnm5K8nXiXy1fq9SGrR3OCRPVGfxbhRk7exEeW3lpo2a1qbpCNur5BooiMc +cEoyBhobbghLZCsg73iR/uhLHu9PrB8tkxQuO16E3VMHT4LseZKcLI6ZzWVMrusB +5juXi6qIcyv6ZYqHPrLIs2hpW4+EiFWvlums1cOHt5EoRFvmpXWgkrx97vp7CtXj +HXLIj+2AK3rAcb53tUB3X9arXAmKKX0cic/bSczF+bL/eTPTjxotGVq/BhsJWz5X +sv98nvzhOXbYzQfMnfkD+8ylgbP7ucMNoJPtUDp+1w1ePuoNWe/Mx69gMC2UZxGK +cOx+UZSS4UbGvORjINU4axu5jmUasssb1mrT0gkKty/PK3o71+Stk8WdFo/o414R +MIB1rnxiV+Co7I7ALiijE6jeOMHClszvsSCegu+zaPC07OML5L5zC5GBtLiWZFoM +RhhU5amMK3y4mYNX3DC0Yisik8hkCsLIJngN+ziTqCnbr/e7ZNF3POCfQmrbSWAJ +HgSVJWJRY+mrpf3FS931C0EEXjHNC+7VBcUKvebID0PgRpSzmMrxb7IjBwN42wqp +8WAevI9b5/G52RhY6bJniTfua9pxgS9uLGON6YHy2e/b9MZDzWbpyXuJDVkN/C6Q +zTvN2y9FuQThSv9QOvMytMATSVBrYC7AE0+y4IZ9mEoEq6sXQ/4THRY8ZBCwT7WX +6Ce7OUH8tmaNhKIDgrgKnsyOQ0PSnMSs4xnPOIhe33QYEyoKWGdn2wK+IdFmpoR4 +nNAWkVX98hElDA3gDe9df0KW1Jmz628bi5PNumtxWdzvtEJBrG2wX3MFohKiVOmT +du0HftlAcisLAhmcpRrSozxn9cy+ewufm8vAEBQ2kHNtgZqH0V24zwL5g3zN2TiJ +hI1Ow5pZRFbbDPGrC9lt7ZJW0UkJ/gjpXUZMK03TqVNNJGR/FetNLZy7mhxWHBCq +Mmjw0FCQ4KuOaTzUUNyNqubZ8ZJvGPwEEq7PGq9H+kQ+vyKXhNXsP6W47kZEIKgs +JdVHvO2LaNIT0HYpEGbksvcgUKOzJGDXSzD6AqaF+14GPje3NqEioqjQyBYQr+s8 +ZftE8bJEgmzCRmGLjVE5KzKM/oehgRT1RsxVqCWMClFxAhNkZ1VlU7VNwhE3JpQA +6L08WNz3TyJjc8VsF7kx3SFeXYldX4N+NP0jWKEuqtAjORXBq6XR4O1QOR6HbCBT +8wOYBU7eDAYJ7wWfGgjuV6RhZwduhJNnLmjC+IDIomGNb+eIBYyCFEJXBd4HtPDH +N8CF2PbGlamp8073ycBCgec8Rr8reDTtdXzBGzAeoEnemTwX4PZBBfQuGGp+oFl1 +3Hfz7HausW0n9BflARRcQgaCIfPb8VMB4vw2XbaANcR03n8X/dROxNWhhnpmwsLO +WzvAcF0FPtmGN5mclot6XiIFY3Um1i6kqCYl4SHkXzxSjlZyeU34Jlfz3uJ3vuCD +5tzHd4x6wLbztF8OuexILY9YtOtx0MFOoco5XBG47IPAPKq1I0BNAqk0BcsUi+79 +SzbTIwpxY5XUPdDGmFJ7xZiaEbEjwSXZt9cOf1FNMTJw38fc0SmgIu/in30qIwIZ +eARC83U6aR/k9hsixLJ0UisheFyFvEAo/GDgMPFXXPvkEq3C+6b6yWxXAQY2SpTh +BlKyvUVt7BgCK9xD2IEWcE7tl3WVxJ7ER4gkcb4D6emYLuMOuO0xBQlh9maTRoL7 +KuuTG+Jaqp28TLXy6LXM0D7blbZMtDH0NKT8MIg8qVTmhMXu7lEOX7GmkKXNDLWX +dP+hIPepzWaPlIl1pbCTLjsPwqZ4xExpHgKXwpTFwwgSI96RC3S2rDs1a1chlcTn +zZfhvv/m5lVPtCdBkcK9hpAnlRRHeSUcLC5wE734iyFgu8VCTG7ED4A8Nl4adyfV ++LFxMJzsmCW+UWhvmzi4LOKmOzxAYEEp0aYDaHocR3FA+g4Wzs0EV2AjBqbfg6gk +TCcKqrANcwC1IMSXgLbJOyPf+tvpJ1ngb8I76DvKsImzTtG320dHY4jTZIzcRsz2 +XsbxYbi4HZ3aNt5iCzUdE3jCnQSZAluoVRzCpCbBSnOuLLY6y3dARzXrLEyItgk8 +UEDMCW5u8a3V0QpxQPg0mdJpx0Fx7yP/5eRMyzOfoO2nzpXX9pXM7P1k3kbA3OQ2 +ZDoU/w6FI4Exg4hZ6QqEVJJaQecQtOLeKW4hBreMR+2jrzTLnRYV8UZOfTBYgR2t +76DBmCsjJTY7Z7P3BgFSrQsgh6Et0wWy87+vVhp2UoS1Biebmuark1NwnHdDqic5 +wO7Kix4axjAWGFKxYnLMV2Cjw/C+Ia1kctLysuS25251f2LeKVXEC0lSkdyMUPkg +USiFXSrEjJFayifI0Ab3SMYJiR7Lhp1vddrDNlc6miQIy0qUac24JyqKG7MLvP3o +5dABs/Ho9bTsap2mCR8JwdMD6TfVVrlI8DIcx9CWrikfbAuc1nrVQ8XLOda6FvJ7 +JYYeaDehMPxvqsYfoIE+SwwND7g/jL1CR7FJh3+FRpdHACox07jr7sDSwzLbaA9T +/Wc3FyP2HtB7d7vFfMbBZQbTtsSnbcWgC6F24exfPtwFxKA7yAgZ4HCctwlBNP3L +1C+beZowzBiaIWLTW8l03WXBy6K3PqnMJrj6Uj9EgC8I0EH7QEGZdTZhtyUPr2DR +SocOg/aS9jevODj1bnnbCFJ2KZ/Yprul/Umxvsi9I6W4AueKLcfTCna8HYagD5s8 +Rh03+4QGGWCjkSNFZcOKZ7OvdhaYI/Gily8xfvL4Yen/OGXASHZLzu2vgExDzth7 +maNNZVvuahd8pFEdKLgcZQH9FvxyoxiGA0MmL7rH3EDOCn4bT50a7XGPLuIfkise +oWT9iOC1Q99YTU/rW2MyvvV9uvBci6C3zrAURPVtuBfElP7OzePJ5De1FTbLfuzr +Vhlca33ceGF7kUiBb5vGbEU2IPlkY5Z0gL/owr3V+SI/qgg2Rq58/TgktqyNE5qa +BbOruow6D96+O/upB5brL9FpCUVaZj21GuWpEnoE/nQp6NslJaeKjRwMocDr1hPR +ZmsKl62dxu56crtX8k9sCcABR6HbF8Hex1ltJGsYTKGC9fXInoWvtQG+NhM/eIhx +x4W7BE4JTVNXsDtT4dMdle832FYaK36f0SNVUi1mSWsKdHTlroL9bH3osfBrAm+9 +R/dEeDs972QEtWPUq1dYoOXAV+tpc5LvawK5/z75BdnfzY4ZdiyoFypR0ToMgtFY +Xe+rCbxNwCjIUSPYDHji5KgaML1dFfnqEbpB2E/vq+o0PYiHp0ufFVnabsXi1b6s +P2iFipaTWluJnzdv69NUtIP/Z1InPqWwQ5e0mqnYpZQpnjmKwp5vJTdO04qNNBAS +i3PNBr97ywZaiyBOmS7U6tkM/K/F5AuhiFtk9y/dykLobeGAexe3IG6TmcICs1Ga +fLrR10EHjRJGmiBItw7PnPqPQEbd1Mk6MRzDK00mkPahqzaZHXsWRgjGPXt+G4ML +b4lKhhBZTaPMWTXBVLzWowVa9ZlI7GcvoGeKdmLlhRFGeTRS3bCsKdw3Kak6uPgL +LSCY+ivC9V0UQvslCIq3Bc9lQt3b/l08Erkck3S8Ykh73QAyN2lVg2tZnCbUwKwv +xL1bmiyKWwmyVmN2RmeQ+BRSmHF28wo4yEfU9C6JQLA9RSoj/CsPCe4R7Mo/5EeQ +G7IkLtTiIGIO4P7uejpul6YKBaHRllI7fs4et0iGU4NUvAPEu4NKnORFoLKZjIJC +poMEhOO+EQqZDLvsBSYoluI+pJP8x+LSPFlNEXsmFggdLg9fGeJnL5bh0c8dSfoH +NcdGFs5A+2kgYNu43UMRky2gRXLjyXHSWxxUkLHm4i6ArQygB/3zNtXDxNJE3/Bm +9LQrh3sQSRPeDR9UAJtF3idmC5H8TBHKXOgT8dlRCIErGtYw3OLY/wQKiixtUt/j +1KtWTZUbJCfcJSSEhPRx6LodEHEp6+C5Inh6wub7SUW4xhjRa8/WX+g0KE5EZfoo +EiGIuNh2rwo1pAm00+nyzS9pH6En+PmWFcM1DOvuy7b+jLCm5BWvU63/8lPSipLZ +kalh/kr9kSAVijSkvm1eY9DYDyvkZHOrknMNeenpi6q/JOXkiX/0IXyqNDL+ux2T +jvBP7wiFlnkso/seqpCHfVb52yyz8qczSVVZNULl6A6EjVrhzRWzscogH33lLMJv +xA1UopvSwlOGHIPS3l0vRbZVQoi8OE/0eT5nQ4BoBu3UblccKoR0bFAcfCIKCWUj +4umjglYozfMF87CgVXM2EEoTeKARdUrsxosUm7FkO6BaDPzCcVbBLghG+ZNEaaLp +FWe5bn7v+NgELMno8atVXGamLzqTDuBtOl+wQ9Ew+QbWLYcCf+QvjnGmuGQv0GVN +C1kdZ1Cmb8r3kewQ2VtyWLEaA9rhQycn6GoP62CTGOlHNBijvKthAAQqCTXKfpLT +fgHfROLqaEkCBPfJuipP5E8vF4gWp2Mi8BA5JhnSYj4+EyEehodj0QZ9StyKVWJL +CgeHPG3GYx7q7iPaNidDa4CXmpP2eUYk8qOci8Oj8bWu0WZHqBwDhFTeOHvV/WKV +0bFTlOihYzJx5hHSVWL5LIu4dEojvR5TkmZZ60rYMQWviQvjQO/u6PHvAnDmFSck +yfD1PzcUbhgXEsM2Zf5zt4qut5Q375uywhaAVO7vBxCHZo+UjTMJpLPDQQOnmsNJ +onphouJweombuJWb0W+RWPXQiEBTyTJ7rDwPwMM8sfhFfscXiear5Mn4YgpbG5NM +ihLZ5a5ui8vUpU4FDCRL76CBZ2RNcmWiQZ0DEd5FRw3EDgGLcOSldZ9nvfOS3sFr +cy5OFK6hrzp6mQ+4PynidhXklYE/eHEHxIHOgTCii8Ac1/APxbQpRmRfUfHX1zZX +M1qR/UBpWtGWPmq4xAqTccU3Vgrv4mBTocFvKWvSil6dBGIP6dHW5uicfVbR9Nk1 +uJ1R+5WpJsVhWL4kA6miRw96KuRjt+W2QgvN5D8uAciWc7es5WLXdL0Uq1Fdu25X +ZLL0AKC4XfQO67Lv4Tv3B7vHFKg5anvZvXltjAy6swBD9wNrO1wc+7upEprMk4U3 +lHDZ72iTJIsUGOE0zIePLVVOS10qE1H0d5vx4ra7VOsNoc/8ndOGFEUNcRKQZhkp +mm3Qxp/1PucpCrq66mmqlbgJOonqKoX5S/r133vPd082TlBVQlUxMXzu8R4vcjXz +UoQlXktpdRYwtI91DAAsyhqX+WgevoFMhflXkyDNVr3Feffz5ANXW3U723GvgI4Y +BSzjy9fL3EOvHW9T+44AUzzJXbBUaV8gHA1HqhmlDteLvULVlxnrp8oGwPXlkLPr +k1YcBFAXTR98UnEPf+57KihD3rwMJLrVtAFEjz8u186P8lseXY89RdaTXOeBuT35 +rcIosrExhW/DbRnnooLG+AP2nKkv0BULUFgZhrDZxUezKKtt5ovmN9iiFuh3LeYG +kx5rRV1zACMIHFLnBoYjccGHlORuLzoxjL2kkOaya7HzSJ784931TOYvdeqr7doV +aZTtFOJgI4o49Q/bTKD9Yy+jYCr/cQ8zbN4lj3zqFKeDn51RQ+eMjOeTKoDtNaws +pSiJLiqF/SIc94XwiJKyMW6M2VL1AuUST8uZaDCuzX8G+isKB+U5fgmItdub99Ix +RRtKhwbFghlZ896Jvy0s/gMdqdz7DBscIoPwo+2NuYmZRk9Pm6q0CdI8l4B8JGV7 +UUpAIVAF9BdXE/nJTYwbNA5zteWWlkwxEVyC+oVI4hX+QIGqz+sYvzgP4QwDuZvB +i3RNAl8GpcdOs3hZmWym5Mm5kjsrItVgEEzvfVb7C5aVk1MntdkCG8WBmgSQPtuW +3tn3Da6kUwvxkq8ZXaqlTHHs/vCZS5z+yLMJ6Wqfj45HdAwO9rQ87hk91OO+L85o +wX5BqpM3q02PgyxSr2i04fa7tHeBpKeqab0Sly04KXYoX0jTrRU4po5Ace+kmxea +wOnMRnYg/yaUbHoLVMymnzJo8KTLPhuxC64YVTkvCF24OeeyJ/sX2h9RlMcoQpmA +D2+7FF8F3GJSciJQMHyr0QrzRjXeAJfcyaf110nLFIP3x5k24Qp5yKT2wNgHoJMK +ialDe2HKwf8sRv60E8s1wiJLXt/+TbKnrZYosBwixGvtKDdH5wpuivA2LqJ08Cp/ +W8zauQ+hRQL1jattkYKzkJH8qmYkZGn6VCjfbc4+Ye9zSGkMYsu+wCgw3ZS/SyED +4kqK9BE+M5EsxdJDMKC0KIG5u6w1vY/yi8mN56TdKd4xGiXfrSMSFAuNENJfQ5i4 +5QkMWLzsQQH+CqQPebS8+JD/NjjA57rdI2MTw/q0iKlwbKAimQytg0f/Ms2lWd5o +tiD0z3JowT0895vOhZ0sEiW2tgk1uZVZXqvNb/eGI+ijnNzGMP2bJxrxmgC2AiIM +nZNUlEVdulFPomuN+H76eewI8x78ASPNId4dBEReWBVJOlERsDGzcABHO8nUMBGZ +N6QU2pUkx6HLUPLqBLWVk3ygyCRC7u9gFgfaGGloOQPHR/Xq5NhxC8+HkYL/x+4Q +77iHHxAEF0b7PkGuIsHlwGSxc5Fbl8+TX7eMnF2agdXVrwQdGUKUnEf3elS1rMjd +8W9sWuMFVGVawN0+tTlfSiDVAxHF/ObyRg9zhRdAj24Wwt1k1RcoNhrlLdYX7/FB +B1xlWbGpxbhYqIqZNNZJbA5pya6oQPyJzdMroFk/XcE3qFh/QKT0m2bzMyzD1AVj +Cbo4BxqkSSp++EFuO1L9Acyziqo3jACHRefY2g/o/otv/9twTlCOvWLnAApcCP9j +Z+QopVU+jPR7B2f80RlGkhHuNEb3VOAViJt4h7pVehI2wUNQzgvhRXXl4uzX1ef+ +cwn1RIgJ4wElyHoQrJrMPLPMCi5iFxEHizQM/zobaUZhtWJldNKjcp5qtRlPBXrq ++4ujBYKArS7XTWFQcOF3ifgMIxdtix62AQS2jnOUgKeir0OKPqLyLGF4fPol5DR8 +4f9/Hb83YTORaHw9ZaoLiVVyrP4aGXSJFLrpesDWOteVPADsZM5X+o8GRyH+TJQz +yRUlw48hUJOWfYe9mK1eHfoScs1oea0U/FxLgNOQP+ZjsiaH0NZ3G2ijE99+H28R +6/7yZ/8wEusKrN034G4RQFviGxFetFsgfUxaAdRZCiMN/0PLwErJwrEU57uxwNsx +HViU6gbe32q5o3zJnxrmClob/oMy+wscJVLFzLzv71tWu93sEZUCrnyV8Om4xU3S +cYySxPxBPeh1ZElDZ1rwvuykPhuciwFAofzKOMO0UEIiyLV6hf+vker3WHKtgKpz +VEcorDZh41FFVMO+Cs9WVKrNIhy9xClpjeRJCwDe+aDAARiG+AR6Ja8pZh0UBCUe +MhGOXJVCg7PLRCJIDgHvsCwwpA/E4CZpRtmxaUp+jprUEBwMjaR7ZTvVPBFDJqhi +J1ekW+k8P4fhA6JowRckViMPC2sRSfRl6UpbcCdsCNT6xFRVX2QxD0l2vtYA+3pX +09kXiJOGUd62y3hCdSXgAIPeDolB71Pz5ococF4yj8pYJMYVDl/JA/wV/vBetGsq +mMXqXbcoYPkJAcNIJ5FM0HWDFxtvkxwB0M+XdyKUPH/fOAjEihNL/03nuXcm3gjp +Ybwk63rLlg1G65P0vFTrql/zywftawRhBTzsH52pV4HeabsKVgEjWfqcJvpHF03l +rTtc81H/cucCNXMUTDxEtoLUDKceshHSYLagCRv5iM/CXFqjtZ2mOPPSjtgcSzS/ +0MDgOEBP6qSjYuFStoOeUOnBaLaDSp4lifPqfoVsEqCFcPOYj8SP1YCOEGn7A0hN +o/+rxh9kdq5u7/5xdzDBhdd1cJZ+JRyzguPQu1ZE+6/+wPhmmHOLE6nsrnng97/Y +kitb1miOtiIm8zTqIKmx2O1zfvYObB1PfprRPyT4xYTLukDaeOgd7hP3C4Me2t0M +uZtNSNLWwpx91/Oo1euYNcJ8H3qrl5zqcVVnH0AXSJQrlymGb35qVHqA7KURtF+w ++651YF9M572mQ1DrqalbyMQznYI4SrLovoKPrRGLP92Qd89V/olONKhahE0rTdX/ +PGZVsNqcgfcHIVvJIMBhXVSWwt6+YOuublHZxSonT0TrL2g2zgQOPCVjmrJneQpo +bGBQHGNAnXDBHU44fehCN6wmL52vCTI/mqUr4TITYInPlloyhrHo/LjR3TMv1V3I +WHqTzDysQEBUyf9L/25DL7J92HMZy5YFRXKJX+Tu1cerkVJRvL0gbFVm6S4pm0Am +/ZOnBmeEFyZ7cEcd77h5yqM+Abdhv/UmVgi0DLFED0WCIn1LKjegfBRO11rK0xVV +bD2OiN98SmUMyaDLOOVdx4JT/qy9bu5Fa/rcRDSIR96HaiVTkGKhvHKiSiZvpe2j +ikui0UugG5u65zXnVloHkUF94wkOEdUr7x5275ZqsYPqnekEngmRgjkhyioCIM4N +0hSwMeviRARzNTejHo4E1KDYhAMC37HrNv6u/CXLOJfAuIuQHhHGVqn2hNiAF4aL +SLY5AmSpVr6S2PqJgV+wDbwgnAvHHjoVUHKySGFqyLxxH+dpdYs3qmDzbRibpE6q +WC+WS3uAUvyivjdMzp02BtVZddPBgf8eGF1xYs0Fr797BzBBRVxCmlhT4LmlA8iH +HTbqDx2PN/YOOquO5yeS1BbMOdmMM35k9WEpcvlfLYxvBO57m+217s/1josYiWCQ +lIBQaptMwTgT6Tu+CSYg/fnO9m34z2JV1cChqlawZ4fnRvDVl8Me9ZYdZmoi80dY +UpZZF08x2PbIl6TbsDLhbqO9WOkfUToulgIyOiv7qPlUUssOE3cy4prZ7CiDXF+7 +5N9dGCm9T3LIXqC2tJ1OAhHfcWenDi54immg7TLNDi3cXUcEKUdRGBg7ksICIUxA ++nra5wHqyoM7oKUxsTn5NiIYQiLOWDZtyPZjUJspJ5s61qWpmxG1GQJmvMa/WsTj +1zCJMWWOzxNCRy80mIdB2l2awwrLXQPp/Z+3hPOfRqqUFJztq0yPTsyll3GlI/ZI +BpIhggBzNLM/j2E/meJKHFxw3TE9M3KW46JvstL9JIciSeNVh3Pfi9+MpxAhYhoT +TjQwjvsIYIGOL+5LiG5CnQihh0TUInNarlItXx2WKlOk1WDOOcNlRW7M5HIhUr7n +xxPXZZPMnQHrrVz1/j+GI+3f1Z/aMy8KMZWx+OoTNQ/i7IdLkUK5qGICrEB840AZ +TYuxYVJ4+nu0tKs3/alecVdJbom+fc6WsK6aXktOwIswd6/5sWP8Y+INUQLFFOlG +vASRDX6oU8DUOfceYEZbxV25LqzlOpoTZ6O984+fevxsyAxHaWF4sLrI3GcHPlzx +rMQaXskEHJxBpTVdw34qbkgWzqKQY56O74Ko9n3HRye1bDJtOyprLoVAN+zQHB4v +Jmw5Ifb/NdAPdPGUb06Yf7ySi7blbpnGWqlg2JXklAyM/fzOTIu+bGoSL69l6jP9 +SVukc/c1fTH5/0B3CMByrThr2Aq97CsGdXAqPw+TUKDj93Q+EtQDb893xJEd2t0X +9O+QhPjaLTPdhkjviiylT4VNm2t8XZsnaVoHK2gxfhF72ciLoTXUmAFkm9BoLN/O +cVRiuu/JGhF8ZjbDkbEZszmXSGIiRMzTLuOTbN7w1zBJPhauCA2ugy8PmO/KHlJj +fcN/ANK7l0sq3q6aNG9CyAwG18P3SeMcixPB8/q8uCitjyme7fnDKbo+UExHnOM8 +nUtAj9PCmfkTjptjnKtIMBEaS6x9vbCZGtuZIXqPBOYW6YNN0dyx4+jZvbKVs5co +HQY3SOD1x/KZ5TjBUAR7PD7PFY0n1Cpp/fZObttZg9jRGqgte1xgLfulQojhFoPW +kQOHqNCP35Q7vcbsM/vNZmQO24RXd8y8sajqlfMGriaG+O/WccwqQu+oXsxYOBYS +S8V8m7GSMrbgDV5zQd2FhcErFxYil9A53OQyGrGOBxBJWiwmbB0novpNJtxPUwg8 +wm4CqwMXxCsLJmPNGAFNlZxzVL/5GK7CMpjzH1kLscfGLHCoGY2cd2ahwgPLe3Io +f6tnU4peCvohbX5KerPzRyPKmBCtOnbq7G2ueeWpjG9a8+dKoFKuXLIisAY8VjLq +yNi1XxqEWdHSz4lmPNzL3NDK/U88ZVwUIqUSCc7pQLFDK48/7yoz+oJWmBUyH5YH +irKeWq1eW0G//yAoarxCX5gsGUkYTo1Xq/szR9/nJ8MMP6lVh80PO30GV30DuNuS +hMoAvv2DbUY2Qf4+gdOYp8YCiHznPqpHf18yDUuvaT33OFNqsY0pSLu+oFV4DJm6 ++FyvLePiJDq4csi164d3u3AXuBHYJ0vMRxn1Qpwd0hxtDg4NPgp95HR3QQhntwC5 +Mm74xttcnaEYdepP0fpUPd2eP19HrvQF2xFyNs91nOO0+mFiIyYIp+9NwfwIZmzx +v07w7ufCSxF0fLw8T4NgjoTd8gRM8pz3bUFSTyvNhH8BV6eWoXt5jSuCVzPoTVOs +ZkhRXNXFhP6I0eTPdzNh2AflI4BKRYcHK40FhwGDdyOxkXxo4t94UnS7He05MdwH +SA/qASJT6ObF6whm1bZ4WZXLvdxYSzEcA5YwrP1oKguqQN+gN3/5VaCqB9hQQdne +jbf1nGd+1SkkZJNXFElp/sZ/OOq33OkPilaFir0OZ33P3avo603ezaVqMyuMnEwk +1k1oL7F/RHqbit8PbQ+Vsm8zVNBYy01hY0sWuDcBLSDYaRvz6LRNqKiriz7HVkjy +LlJoCaIbfYd5uPaxyQMh8HrHNtzzk59DqiVvvDkK8+jwANZm1vvvxnEwDqKpE73I +YEeFHZ3YpBZomD82bYx9C3h1itV5GNwpgfh5fObLFSelfADclhbQFtHtb0/BqVt1 +1Amk9iy71BS7MaMUp3fB7qyjgrhLEu9M7GTfWni/89AQ7KDIMg0LLWYOkF3Lpt6Z +EHvz6iaGeXPjwaRBD1hY4jnSPsq+aVNiZddxLDvoY6XMu8J/kf6O38GwCP62iVxK +UVUgOuFjITtkT6LpsoGeV5xKzXncdVpSf87hcGiQyUnB7/Ktz2VKnl7ZvK2otz8f +Mc8CNnxvhgVV0nVf/vzkQMW/9y/PA8Xlojf2YLdWbwtnS0DqPH3mES2S7lBnouBx +EoiQawNVoXX3vW/1SppaV7gYJ9n3UuwEstuV+NmuKGmVBWKHKpviDgG+pox6jrUN +f5pISV/ewtH/XAFBTqWun8f3aoCykuWRSR6TMMvoPTxU4W6COqFd0zIVmImU1Coi +1WwAAj0PqQq7yFKQSlO3d+wLjF0YrcDUVfYEe9TocVUW8hJ+ziNs4GeBN4onW+d5 +XVn09IM84OYgu6eO0XkwjR/UON1GOkD4gxDz4YSY2z6AEhMSuBDd1xaMyRZId/rK +wuCU4w5LR3bcGZkiMCKELJ74EPwcTneoYUgjphimYnwDtI33CtMeH0Nw2EZ2FzTS +uhqlpzCOzmrN/FSpmJNBJN5zcRaRzM3dNEYurkv1k8sSZw0WkZP75RVAbnfdIBob +/Z0oIvWLKUjDMUKzsUuXzC96JKVQK5wwk+S2/47oFTW8chMtQ+6xPmGp+EaJIyhQ +zsO7jtI3/VmWpaRZcCE39LnxDo4Iy7ORK7kZ1aZBiJiUfJKJyxV0Kjlqvvybo698 +sSSKw4FBdAwZfsGtqUemgC77dUcGve2ifB5EMXm/emNYj/ek5bZ0lbr7fUGVKPib +zVIizbycd+Lm1mKZapORHvNs0XUTpRaR/bZYarepsRriNXhRxXZKA5UISx/vtJnt +wrSHU1dloe5FFol9sJcy4aHEtsEbGNFIT9Hgt4DFmB1S2rSC1lJisTE5INhmyZ45 +EyMnsdFDj94x5+v72YcA9ze7a6K38T1usDobe1FKWTPlU0TOa0mj3z8pK8wSJXKF +oOmh4g+EeZRctUjzP9QE9KQB2p9qPIbvi0Q5F5R/zDLVyA9nKxEq7huzNT/eftEy +r1lpsW+XHBsD9aAL88mM/1h6vcquocoTVk1tNSsUzvrm/zCqG1j/G6tlstP/vLmu +HhfwALpdoVg3//DdMIAh5T52uBXEoe18fRAj5u+hgYWLIcYC0eZOtSnjSy+EJ7rX +SYNwrBSdxXcMXm6o/X9xNxA18GFt/qRFu98iuIe6zKQJlv202gWm5ZVy9DNGFwx9 +7pBSTTXA53aaFQKLtEbIP81Ibxp2Ompgr617G93i5w46+Sm6T0U7utfTQG9meWGf +OrzMgaNV1+vPNMAwm8fHeSU9VngVB0eB4kZeXEek/Gw5LWAdl1OW0eOCvODamgLa +KxwbtL+pmKvLsyUJOY7c5jAbis07Kb6t1StnNPd+HzdEDim8AGTAtiLO+ZrxA4OZ +u4Vz7H9VYPpSjf/merXHqBLNfDkfmF1G5yPWu0LQhFMXykXTzNe/O6IfSTJw6/be +e0pmeraDfZITzPpJaeh7xKDjS1prStWzcKjGy+/ymqjDFT8WeaJtkkqY+lzqfQK+ +BEVm59Kv0URG8/AuM1yZTTGPzMzgkJGmfCY76faJRE5DX1eeaKVfcIHnmXB58zsj +86H1h0skFWAJrCYyVBF7sd/pKCAIszmELH4moEwUbXUi7dbwjyp24skrGwnJ/71P +rbIj5k5R32Buwga7h9Wz4YWHhSU+EB0FfzVIdGQEUrQPGng2MKQF6gJ7JyOIqpUt +/XgpbThMRFIrWNJXAHt66noNb2nhLG6b8BXehD87SJ72UJ6GKqYSPnOKXhRCUHjy ++Aoku3khE0w5cM7MQnszqw2IuLqb8gOwuRFAjfwNxB1gHz6cqkJmc4Nrp1Ejf8Et +XqY5lR9g/cXQt+GqdkfmrRTOVsPk0k57D9bRNjyM/J4OvO07te2kI+iRP/skmibI +qlnHM0HjR5e9mNkObI8Z0lDSpR+JlA7LPB5UUNav9rzlP0un4dUfMw2GW5ZoUfbY +RUkx/C6crufutsUvzRdV/80G7L67CyAhCe+I4Kg9kxPXFnJxESxaqRGXaXUCc6mN +8fFNA287gyLA+j4yz4GssuoE8jdgUwOwFjs6lher9D2jonh9UAvE+1ztIoSbDbVc +B3PEL930pqS1gOSIM7hcsy+PvTT+5mFiD86KeczsOSd0A3elvngl4nxPxxbZXX/k +sAvyYVbTTQ86XIu6ZdWg5Xxq+a3+EKQY3iWPd9eAuAudA+9J2RghNxoz4S597zSw +mg+Qm4Kd3s3HPhf/ikLQ6i2ayhvWPkd94p5O4LSXt9eq44nEYiexTtxf7nUQLiTQ +0+QmUEzGQRrLWtyVfn9t9QddxuMZCFVuJW8bBu6DSVB+GFEZ7yffsx3EVCb/gdqC +4rpthbJn+d8aj6FvsAWFuwcpcWTIXJiOkvMccKkg7ymoJs75vTn5aNKZOxCZM/sy +2Ixcm3YAu40KfALZJ+BeZcGeSZZsrAW5hNhnNtSrokiSx++SvNQWcqUV7EjEdlQz +nfUBE8cQF3c+uq51Xmy9d5IUO1cTPEzEKVRn9gwx2Pmj+lT5eko6BF7bcTAdHFgI +SeBQNaQ/MrCde5jt9wyYIBYtc2SQu5mmWA+v5Yogpb9Y3pnyItX6fnJkYDP9015a +PdLMcsfhKUZFfCzW0rf0AzFB5S9UgkBQSaRkXDC61EyyRuj2R+mS8IQE8+CSUi++ +8MyzJa1D+r9sMTRz03BuZLdranUige/zOUkypJeRIgBVnDsx9rHDbODnVwd8tS7P +cdjkANc1Jr9mcc3aw/a2ZJWG7PyZU3WaeljpArI4bgPayrd+CxVuewJ1/8Qyt2tF +MiQRZX0Ip2uuwXh3hxNchD2xkxr0wlyboD+DkfouK7Z3WrIVc7QlKW7fPnUJZOmF +wV/iWleGoU//VVEtEvnLwQ4DcxK3J1+qW2BuVIKsEtoiHU/8S1V8wnfeGgRp2i3l +QnRs1JuqXpaXpByLJweoo00wNOn7Ea2vSe1jxSflD1533IrbJ1YDR5F284zAwB8G +o1lRbOWaIueqPUH7JAa/otsxtQG3ZDbCw3+T9QkBHRQ+JG8rhZggy6fVm86eOqyC +RR5UOSYP0/vaM7THLZOhM0/l81763XnlK2jLjFQ0tbeTPh+KTW++k7+9B4OjEJ1C +kwfwrY2Muh9xOGTs2AW0/aGzKd+ZfzArrSInhyursWlw1LN+/CFcQwaZuDMN/wjS +Yw/WH/dlH9qxFRLXoKcREh/E0t9fiveEC7cPBrDEhxuZ/NXCxIldynmZsT00DFQM +8+R5d8TvMZI4VlPD9gAXE0dXqCvaMcKbSvRF36MqeL4LG+QrOFyGq2IMaW8SjdLz +I0Yim1j++tLYpZV1VvOGyuMcCUL4UFjg9JmMhyN3hJsuI7mW5vHd8YRyG2whkdR3 +1pdjt0HIsaofXFujWHvzlfcoHN+jvfxFK/XSvQoJkMVbt9U/4HR7z6XLVkFvF5c4 +w3pOOEojQkHoqymYYU45txKHLiu4m6AK2ky8kbzqkVBtQZkgYmTBpU3Crkg48bwQ +aEtRMfPwWRLINKem8PG8JMtyT18cYheZy37ZxicXm+TeeVsXgFRH7oAbefdMDw73 +Ik5L7dScflJmXPhl/U99K55/4S8M2BzqTr5HrFuLwq4hfDNPy4ciebbzBU5tCzsB +hxREmPlMjdwwApnkcRUVc+hhdqdatGRH8B9MJUOkOw0+Vty1hXtjma27rM60ynXO +t8Dc7RTHuP+irHDTmoP6LLxSVIOewgobRSql47Rv2QpsTPxQ2XliNf3qUGwX+Y5B +BU7rYsc295CkKBfol7mdQRrnBa0Rcgu/YeY2ZM0K3THP0H6fvWuISQ4CcFE5dXQj +mf3IAxny/eVDqRzrIAO5I+aAsNAzO+MTIDsNSv5qLTxqFCdgWz4oBqc59/tlXZz1 +cqLsclBUf4fTDSgzWgDga0oWr0E4nakAKjNpT/MRy2/tqHP+P4CqmoFjjWkpdvyz +/gd5Ihr6tPSjvgEQ5wXZ0T8gMkMutjhvPTobyemtwGSk8Q6fpdExTLLucrmWKu1E +8/xdl4W4ghRE11s7o1F4mIq3zAV8Kmqfh/JsQHjSjIrswcUNPrMluFDMW0//nHZB +I5Bm/nl3Q/8DvNCaYN9t+/BPt1jsIz3I8JvK1LtFciBVnDDX+7iIdVVPeb3+khuy +H455pLLfcJyudnNvxewccLgj23cGHa5s8lHYcgHVH4aAVJxbko4aS0w5HXXmwMoG +NcackxzfHsqU7CT3cY1fYW2Tp4Jt36gP9q+Co08aTKveXpyno3H3AG5z1LNPTh30 +8saV0i6pVclWWMm0By+fbkbv2RLcgyQJLg+Wb2U0rHlkoXf68io61uPzOAwIn72M +RlM14jv3VO3yJo8Dg1gLKw3P+v5hChsnN5XhK+bm/wxh2i1wvdnvcoHP7hm48M+K +e2RrpEKLf93FNOpC8cKkxk8XrNI+RcV2bQKYhlTiAg/YjDtM2glqzXcshWHssVcz +jVb0/L3K0QQLu4VTmVzdKXMowC5L5ywQ4UfsUV3tBzMVv+XZsYlW89vv2hvM9Z3B +uXaULBO4oY8B1MSubdc8hMZh2lfO/a77ot6g19orgEF1sY2FV9k+00PlAXzr2nfH +d0+u4LZnM/eQEafEauspuGm3rakjWs8WFdSISd3jSCfJS2EBEfaKK/ouUS//CE6M +4MriFCxdA4BNjampfIsCvlc0wvj5woGuQmYIvYyPv+46Em4+MayFNkVyZcZYNYu8 +vf1nWgM4vFn3j2yO4qqYlhZpsn58padF/fgs4K+ErHRbgO6AhgLToKY3w3lghXH5 +nqEEdUVLdg5l4gvU9q6Dfo7T+CJ2sJEJdYlE/q3f9IzwjvzaWIjuHuuDjU2v/g2m +6ZSrqg23a+FEe7fANfEc5Pj+Mgb/UED0nW4ZouXBqfc2vjpN9L3W+z3udBffrNJs +H2rvsLf1s2IuLlyVMXiZ9Z7ZsP4Of+VoCH4BZL2cqG1fSlF35FMU8JeTZL/X0pZv +ptrbplnYc7gigY05qFYDPs0kx/22Sn2H6RxgmG0COcLL6xFK1HX4WYPOs7FD9PDl +3i37/CyBWNQM2Yk+BrBSBI/uhh57FlrUlE6dyiy1vwd3gE7Sr6JchbUcTEKXiL/Z +VoWwb8YpeXd6VzndOF+y9w8MUV0OYkYuROaL1Ijy1NIHYYTziNSFvO49U7iGhmJL +fOEU5ZsESXl1O5d7yHj5zqrX+fXjUDIqUJKU+j3aRJg+iSTAN/bTZvxRuuBY/VV2 +NJQQuN33aHY+H29sAyR6iUaPv2HqifTIlqp/EP3P1Wdz2kqN94ZBKuRSUSMvxCdr +vosl9NcMUvIBBnD2hsPrw7wvyBx5X2gUB95KaiBezwneIBHfwP6muPEOBcxRu+CN +IUtdAbejFPV/lNJH4DjHm6jL1WIic4vrleKiv1odcQu8m1ClcP/tXV7qIaAyndlw +3TMUjUYiZnP3U58H42b2/H1vaOTgX0PTaK5/nSCMIg5zyFv8a7vWJ1J0tVpR5irH +0OLxyI8iRkfInAb9kwwhkVAp3eEpKZlseKhziSVQ4IFN6yajbw+j5KVOmMhb2/gQ +rXzQeq+kPKFODLnH4O5JH/scGCfzhvAyzltl31OXC6w+7HD3TtyFT3RMlnqV1EDL +zKgnVViRyD2O02xrW0R5m8MlZImza74JFq/VRMJfIUpuDhxhYJfy00cF9K/FHR2P +pFJX+dGybQJg3GER4k3t+GvAaYSX/CAIDixMGHLN6tk= +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +KOhIlvaBdXECsKrbEVJUzh/U26bIKVYacE93lWLn0xKG9BPuUScZRg86anjHyYc3 +BakNe+PgnuJEVToYQFkSSg7dilv1sC1y3A1esk/m/agSm1sZPAp9NXn71CeNtLyq +eXW4+sYrPhCz9ARfu35HctyMw0hohs0d9BUvwOVui0XQVxf6T5Lo83B5XREJlGet +fRnVqNWfzxTOM12vqIQowKKuvxhX1eIWMAY5THDVP0MYXaPzVt/tPmSCOAoMK+x3 +fVIwwzPHHpF0DPmvj8JSmJmlaTew2n5hkYU31ogV1dVyjnJqPSvggbb2bB4YHnWr +Ej/zH846G4MmCJDO+yZDLw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 6832 ) +`pragma protect data_block ++Z6uDxWxa1wZTJu8JY0TOi0egG8tzyyv0sjD0EG87Bcp2nM7oduZcHHRJ1oDveP2 +RW9+KmUvkvqdDjOvmYDaD61UT3NntqmZ+s85cV3fobe34onhe24Fp0ZsM6+2EU/P +2FRL8FdGE3PtEpSkCfcrb6Pe5nlr/FzeLll97Cm0E5ePUrLFBetyS3AU/cLzcZay +4h5s0RlvECzY6AjfWNKCPDVC31f/w77E7R6tWgnSPohEO32oFywC1EfnUwGWiTqT +3fM7iqZye9S/LbaOvgXeDwXGY/ck2oLU+xOIKyja4vioUJgrwohYF2FJOUYooupQ +YzCEETEp6KomFEeP3tB6VNAO83V3TRCSvY8TbnA/pjBYU6BixrUQGVXCl/OFIStp +UF7C5Wcu8FiVbfTQPg/R+buRms6R5kyIVKjI+unvmpgk65710peaBHKRmHuO/1oR +GdMdA+oTTkHtw5J0Pfl/oeYuL6C4EV4gd7VsCoA9646uDmaz5aDWSHvY7To5QUMn +Ytz0OqN0hpYqDkSFgOhJzYujm6vylYst/nGeon9jFCbEXeD3Ubc7MaDPDx+A2jm5 +LnWFUNQ6PDvkiLdyKc/2mr1jNybCvgFVTx+SzWbIAMHyS7yQ/IWLmGGqNiB2Ola/ +JMXCY8qDO4zRD79o+Y8ZYNSKfqzG8axxUrqtQ+hh2hFozVZedHtLwXtVOREj0FpN +HluCfag0fg9DrOiH+uqIZ0m6f1ZOpkCHfdIhyXY3uxyWhG8jxPjKVqSwnbZnGroq +C70nTs3wDrgdkPyA06lCjZv7mQ+OPgeO8XlltQmryrCXqgaygCQAh2cmTJCMji7c +EAXhwAHC6i1SiNvvvHunG4m3c++K+jRIEEbilzFjIbb64oDiMXyENwKkQkz7LTl4 +K94feZw26P99GN8GMzHP/nfiNuLJ5d5K11wSFIkbhQ0kvKI0fWm4bfIoZ/o4A5QA +BczXs8cnCmoCOt82+q4x1Jk45uu8sxTRhyA8QSkiL9ZUoXvQ2YcLgd6f9uEBwMk9 +uC88WEPyMyrHW6eH4nZrhLUQ8EQiO7qmD6BO2HuzdQ7LxrIuDppYudLar489PC+Y +Dj8U0D2ZK/DczxlSDE4reDNsnUKK7NkynwkmNkcpj+krhSLypvXXoXXzeoHcd1HH +DJPqwCs2WupgtxWmU7XO7WvMRSek461pC1jMnWEET41UMjEnDFRxFSI50H2KdwIA +2x+W6vR4y4epQ5qifJZ8gsHQzuNNEqcpI6NbHCthViMGVHbAGwMlJidNiIZ1mLdT +GrOn1igXtOuLTwweyZkJ7rK1XtxBDXbzJYWE/ZzODhN5NLHyluoxSY+6l+Mp98p+ +BUixPGYkQBDpZS3XvvRS20KmVV9TlTBhW1zxoWPUkMABeevIVq4Yt310tigiMzyG +gi0XcUqYCPP68/+mDf35Xn8KkrjjJKGoHsP3KJ4kjBGrHRsWpqVzy88Xzl/IJ6XM ++pJ/9WFxSzrIJ3SuBi9FP3b6nlpm7vLpJpriDd41ArX8KiCtA8fLfvCkgBTrJBNu +sWMSG7EMrb1hatF9B9aKzparts2N8MuJFFVYkZYbJPuniSZ1iDtp5AsaK/ixdxDT +HaHEaCkmYJXllE744dH3wgO21AaSPWZUz1JYoixN4jYdzk5+7O7P919Ste0ISYBM +hgg+ZWSZ3YC2tgyFLPc9zSZI/w716g7tc7W59HEsFEQSSe+hV74TJ3RlL4RE4qoh +834RUYQLrMIeu40ETyVODMhpgrwKxqlxsEHq2SQabwI3DwOczbmWFpcZ4kHyMN9l +asLpKI75qC6IyHyVMsEEIpdPaapL8oocU9lJ9mtClvj+GtvSiaL0p8JnAZ2BPeGB +j4qquqkNJCJ/bTXQM70Q5Yd3oo9AZZkASk+W5OymKunRvmOMl5ik8qRX4yRuivIe +kKisziShVvVQgo+qX9aDfH+NQxaSjulYJgpvvwZw/4cp4FC6lzrF87ABwwx1QdXn +z4/ofpGYnTaQFou+t1vR63/1yfJmNOkqU2mL4Cv8o6ccVmSdQao1RW3BNWq6SGUC +Waef8i1BnkhjXa2HqpyqoVhJiLvFl8hC5RuYXbj8p1zjgxOOj5GNahvqR5JjsmTy +lCvEG2m3oZ7S/1Nul7kAbzlHqRc7CLER73Kr7iqtaoIg5gvKZYEDgpZAvnM9uL3u +2H7uKXCdRwzX4HSo4oHU1x+ztI1kkSc5xIS0T+uULPQ359Fk75NbVcOm3gJ1H4wR +kfRTCrY5Sa7vOy0PCXcpm6KFMC+1dOdEL2kU0wqn6nh1OP6QwFuKksqGnDWpCUWZ +ioqL67GOz65iMWq/rTCSu0oSnct72T3XpYnBpcZzbi1zvacm4Hil4WgdXOPN3vGs +13yeJSjDnS2l6juCCC9x+Hsvkqyc6ze/NSNkRdZbHdR+s/+c3NAvxG35juZx8VFw +NBeWOj/FxSU8u3pAqI71Y9JEuuQbYIBYoMQ7EGzoGOEfAAJUqqanrLpTpktvwrnL +OnAYaUda4j6OcB3p4FvtAexVD6hr2Z4Mr9ft/KElXAbhmf7XXgdF6UqIL4ufY2JR +v14T3obqLDqyWWbyyehrPladybB3OiWtoPjjStwMUMw7YlsaqkQHonkfCWWtWnjM +9XIXF/PQ4Drlj5eie7KfSPANokXBQI7mBo6aonTAfLcn0QmT0zGvcCo7fJ1dr8tp +N3nCodcUWs1q1aEw6leENhG0IMaPKz+X5H9mAK5ALK/vjc3BI1rkukbEMIX6RnsV +dcBZO+pFpMJXsdc1gZFW2nt/lg9a9NsmPbis8op9XujBtiXnxYlzuWfBgLm/erb3 +scwMWYgXq7WRl7iUNfYWKyBZDnYHXpx60T9+dmsMJ5/WPQZOeEM2AzMKne98vV/7 +C+XGz/O3nnJR6UyMvP9ykN4kh1i0lQTILqJhZbDYFP738Hc063/+a5hZGPwUpr5R +PiudrXhf4AC/Upy5LHDC7VM109Td1LY+i1Ljs+VM6/+MmEwiS2MvL2xFlPf2fMvp +Hw/x68jauT1R6/yY5k22tlu7YrHlNzcfIRye0U26OZJnxvKNGCeJIy9noBIJGnMJ ++Q1MovsTIT35dwP5qrfNL3fEekq5EkCfo9LtxJ/3CJixuQlgT26iYlmsW0RaoLVq +lxH0FeAwXNU1Xyzcm/sA6mAr02B7ShQpKszjubi6At7TvKfs6bpwqlDtdWHPH3AR +liR4vZXhmDg0vyGZ6sTrE2kCsffJX1zB+ghUmKrUwd/sYhM7sIRukwhCl+PNDSqK +RBtlKaZYvbTly2IQ7Czixb9Tz1XuaT6j5eFEU1UxVQXw+Zo4eMwTaH65ukCglubf +51Pe9Kta9Yk9astwS0UJmZAZG4iOyzrgqrAkT6vZS/Ca7k//BthNCVACazcMqBAN +aLwg0X76izcihj56VE4WP4zgLuTn4SQ3M/tT+0fNCR2V2WOnSDbZzWpHb2daBZRu +ezKGkH9W0+3sD2XOBVjDvhfsLEAKMA/JVxdTkPWDcYjmLkLH5JW5zcSFvR44IL5N +RNu8OYLpWrWbAEs6WTIGhkLYeHV5xUG8Mine1lOeXVkVYX7TZSaqtfm7INiYhUhS +5D4DeOAfRHR2ArfympsSwnCFOmL8CxUmagnQvXtBtuUmdWm7BwiDA5CJaNUJj17O +nwl6+ju5cN4l+sqix8b7x5SOyj9DqcExy+37EFH9m6BGnA9Ao/XJ9VCNHtMPeX7g +G9tht//Mwh7aE0tj1UmmjyWVB3Om/nJWxfeqsamG0OGjFSMmI6benaYsaFbqLFap +OBLwMInkfcWHYaGhG36M2Sw07OTEqTz0sUvHDj5lAkClWQ7JMXRis8eWHwHautrt +JEwzZO6uZDCC2Ae9M9iiTBY3paT+pZZJVizVXYr+pjYHYWP+fqbHFaplE9g8RBhX ++EWIijTcA57zciFxswtERAJ/f+KPiQOW8w5sD+IqGwv72x+6tjdbVlOrCFdDW5YQ ++oU+mJdHFr+mr4NUG0MsFMNM6wTw5Lxdty1udDNCMGPpn8TwQp0B2E/yPvnr9F2V +t6/vBmfkeo8I8yc6RZhTb48IDgp9Cxb+rAvCDhc5GMxuSwCR/8p76Sfth7XZ+DHg +oW//E5dbm6Y11fLEFwjqHt567U+SV90VdjH42VWe23LTvgPYrd6WJ7JLB5MLDSXr +C7pH87FcEXt0iMb9VhwGrP7DBdC8W/RykDmN3zMLBeT2+MpSeRR8dy6/i7UiteO7 +S/5uziQIwXM1oQL/gnEhqHvq5+kYydyw+QpSnPoo86LMLIz+1JWpUvF7ZgcPBYDo +I8iMf7Fr5ji3uqNKaoarbvpIeWJ/znz81yMXWIHcYxNpcC0zpxBBxRX7n4oLNyIT +qPEXDb1MPPcyd/cuQ4xE5yEpvMiUBB49fATH6idDrJpNG17YyD7JYsrcupUudwUz +927j3HC7T8XuMEYxDqRT9DP+Ozfvrx2V6/vTQT6P+CrCEVrkqXDvBq3jMXXhq26x +qQbT/HgpwxsMLjjakhrrb0beAa21RcgmA5fvlm19vte85liFKmaVnYR4WOiX1b1K +dhfRawYVC9MIpn5c3iWe89YIAUaDNNIPB7mGhJmOQOpNNj7xiKT51UllKvpclyzz +HnaP/9/wtAOsAFwh4nRr3tyEasFkZ0QyThDi3fy5zcbYuaqO+BCo1m/E0wYCiCPi +zi/I0kQh9pncWmHlctKuTS1GUB+kH1lrq9nbcsn4ST7pFBFkpZP2kGUZLGODyh1s +yVhk9gU9jdMuiD2yDoGShAvkxqNDbnRHtXJGH2yHHWH+ZKOiztx3EnOQ3gNYDbi7 +h+nUjobHycqDM/HC7buy2+nwc4m1ahywNrNH+uTOC1/J0PYrvn0He1Aa257YDkj1 +RZUNLkwWyaAy2Pdxj2eqbGJsgd3Y4xFGXG4ox5t7MITSQ51cfXhJBsmzi06IHmcP +IPxgty6L2qP0i9Jnb2MvNEdOp1XVp5vOvP5ZYlwVVY9C7FHQKLR9oGDsJrb8z1V5 +Ddt0UVs3R9a5+Rih9yS22L5OZ02ToUpNNc53QDF66p4s9vLqPfk06P5mKpYoVqBf +r1kk4Iwh7VE5KR+VNjq9O5y7v5reDEU839I3PMe7Y4+vKSEOlqk8Xt5dzJLOf+HI +vIXTVBHNC/AzcJ2LJ5ha0C/DZoydH9SygJOzKzhFXfk4SVn6TiRIQy3g2lUzstQP +XsKhNQLv6OrC/kns2o02vWO6+TBbUOMSMfIbUyr62eXBjHGzuVebN4peCfXIyYf+ +311I5q+5yRWVpAnzF9WzfOU3lW/h9ZhP0YBkPHCw+QVrm2G59EcnIZOD7cMAZel7 +Eq5cowuhxdO1zifE0HOhpm36KoMYAdVb/ZSMwUTPM5gDCyeUtsKa7HKZyVaEvrRR +qAlaD+9KvjZwNC/UM6esDVACBNSm4fLO3k9JEH7fKAGwZqxk6A9+JyegifXaj5Cy +01/768/C2w6n905O0JWWAKdA23BN0Dqo7waBeXw6Wno6/+VIQoIyd7v5/WKlCcoK +RYMcd7lXdZ2ACaaChaUpofUHaAEpICortAQIBpwwvAVgyg1pQCgPL4NjEZJKb3hT +ri0ODa8Ey5P8wwWbkcdYljhd2sBIxkCgjB9AyGTe1Jgr/mheXrfUwT7C2kAzhCFL +y+Ock+FEKIAWBybSSpiG0u22581VdL+QLp8lC6Cny9krLoorj9bgYfRHDHGmD6gq +zeTAmHUFWauvfjAb5UQxcZGwohEuJvuy33iYQZ8ufo7/pHUMeQ8yUl3GGyo++INf +BfiK6zVWYny+mlGFXUyZtRCydxZhVdbU3nIOn92+8arakSPLbmupGpAcGTYk8RPZ +bU+492olfgFeTNaXabgJiDl/lOttp/YOxsLTy3OTavLrbbPtjWLTaCdbE8ovCx6p +VQgRiagWQFH/QS8IFTkoAcIOHcoKDAEAg2mVj4TiSQ/bsV+QBuI7G5hw/pxkn8u4 +IJERNRe+AoVzvJMHjtPOyg0iQXpeZwXmvBM+2uACAB7p8fG0Mufu4yMcTDClLgj0 +aw84TOk4tWoJkaUTNHJRjCo2xmpFJd1xlb4WvNKjCT/9us+pxm44reLpjb/BuMUe +zUb+/XeIOKNsp00G89hhGKN2DNJ29EZVnr14fuNA9iEA90DBkt8QSLHvRgv5kL0w +7EPRx7SqhnQJc8/S9DIgym0g41cTAk5PcZxuo4ZadYGVX9wsEDidGIRR6dXE3dh0 +AWM3j9VYYRMAnG1L87G81HpElm5xTwg5orhUU3Gy5tmBXxug8rPCciD93xchPI7H +06qlzFi7X63D1H6aIphRLAkKLJ206Di1GbadHf7270I3jDZjr+Hx50EaGhlLiZa5 +COOXlldh867CsDFLjNrsJeauBOC35t8OJRxV2FfKT8HckmpiuEqQA5pvQlzsY0BZ +b/jq/K8y1IgLBv3cBSm13IrAssfgfs4vbaAWMrJzyz+M2if8BLOnf/3WOYu3xYFc +YOccwFqwYjoh1XIwSQGTGdOE+cwL2E72gzSA+OnypciK3h+1sUsdtcWn5iCvECLi +1gh/iofvVYfoZVvdbo3T8RAWa7va1gnQaaCu2UOquvTdGZ4v7q3p79fZr94crTLf +qHpNkZMfMc+Dc6VrTxW3K5iUdrxx7TUJWM2bPz9Nq7zzAccZJvkG8ps/MEI6+UxU +/KulE0Wc+aV0f72rDhfsgZQl/vDpbvOgIvyYVhbEaStgTGDBqS8yBccR1CpvrlRN +zY4nVU7joq1xmed+sILDx0P4WR6yNm9sfzhoqqnrmjZslfhqv/vH/zxfAFlcNuu5 +Z2tx3IfWDl/aG2mjT4fIRkjbWl79XKBwIi587y/aPqeWa2WD17Xtn4rTtYjoWQcw +uGm2vZyto9XWJrstm1C+ZozdV575Gu81eYv4pl2lFfbMOTL/zuwczz3yRlQsCE4d +hf8O32M+NiWAbgWLNc2RizBXwVIxDBB5UtVU+oba7kxt6tZDYgczJVqAeiJzJ6Xu +5yRAVuAdj/LhfnshwSwA14UcxEhOwD6MR5ODpFzXdKJ89/JEgUYSE1HfqU78dSkm +JEJWis0bQBs7KyC1ga5l7TSrQTcE2n1XNJ32B0FiUlQ6CwthN+t6Rv3KKjI1Hyak +7+FclI3KNTqO4N0D9fiQu7S5UkaHFa6UwkoL90Vm1KNwY2PgT4kQeynJXZoOEAWS +yM4LQNlMiOPUoQoUrRKY1RvaX7l43a4r2/NfnttLQTbhB86s9Y4Ab5ykt5Up0mEm +MYiheqHLe2JGtm+2Q/3k4yuNh8LRQsqj9fIIrmkJqrFAgZDijg+kkzLqxBcwbR6z +gAHLOFrIPBypJAk3sPc7I01Kmy2BZFJxWwBad7w0jLCKGXBQABtVVgxdenVLzLmE +zm0bHFNv1H32XlEIc+n1ReqFfpiW7pd15qAODmAXiF0TlJNA4UcA7F3O2zHQsMIM +N/w7TbQophdLRd+GSzG0vBQcnGJ/jLzp+/jJyfZsqh0e/1sPJlDDNOhndXaoSt/1 +0mkrXygR3F6KWUUV3RbveMBkJ3t0ZBR9KbX71UbNNCFeXB2sKlIvA5D/3zCCu0NG +fnCpRhSSBwLImHHQFjmntSVbdg6jEqkmGAs5Rtx/39/h4W3LqbdJqXDQTmA+AtGl +LPHarvOaMHqdM2TQSPW05jbdrG/66IFb2jjq6BRJ4GLIuU4IsopP5sjX1juEDiIA +cMb+6hyGCyXj7mrME0457sbeO7kcLj9ALvcWz1Qgka2ODf776E8ZRH7fj/16fwLM +WjZKnVW8Xh+uaJEfBpaCILymd1DTqEX/F6baPsD3ShpxrF0pLqQd6QuwVu6lduBL ++iY4VzEl+sHLwDSIgM83bVoEBNOnNvXZwAr1EVfoeSuuaKuvLsmkRqAjdnlsFDpS +eSX4oxM5/1bEDqegqnifq/J35xDuumXkVtBwge+soHFD3yAu7VgJbSoYItTYTDi4 +sjLJQCsLk/iixRFgKWuEL4IdbhViSumCgLhv6me2JH16/hurP6Aq+50OPnLlu4/r +7Kzk2nwPH5617NIGnlgIGtDeAgLJat9/vg1kNbygTtEJQZN+idJwcUOuT/Jk5VwI +j1BdjKgX4sH6KNt1+RnY1QYpcrLGeA96H9NuGSi8yEboxrqKtzZ+rhUBkXBDsJbE +RjSMTUMilfttlg/b/KAR456NKSuLTIABoGZnyUr8HeTr1RuyPja7xwxo0XO+Ywpr +fmPOnW/dbhgCpPYLJ4CxdxAveSsmy6iCZQp5nl5B0GnXXKoYwK4KIKdIB0j9LpXC +XyV8owSlvzGa8it2r2ymJCYBQi0EdrEEEuAw6n8QgUMUUMrEEC06lV1valyK25ZE +03fr/QuOrXFmLz1WtCRlTnvhzTbxPz7Qub+PUFxEa+Ua8eeBJDNsGGCBkW3q58+6 +eZHN2IMVVm44+aE7Oaycv4nYtqhlSf3ySoWGnDMIJLiL/aaQD32XcC6GmpgP5LTA +jeDHk7LwOr0lzd5dpvPpm9qxRl9Xn6gmwDhU6ErNjldLt1EENgiSE+tdFjTMzQ0r +yyM+NDX5nHKGVCHQl7DD6JsYquqc27fahSFKnjOUlKIMusNi9LEVFD7E5hcLLjk8 +YCodEc1RQ+5XRjZ44l8hpBEeh2POPSklz5ytk4AS58ah4YTqTWSJW7uVcMfR5jDo +mZ0xHq0LOLYUQf/vS/5uMJdRFx2H9/7E0F/OZpzgCJdSXYiTPYnKOVKrACgbFV4Y +54WhmiqPSd4rHPAh63pVpqsK4HxMp2kFrkzdBQdjsX0g3wBmE2F4+97xSYAEDODt +X4pvxaVhzVbkBi1q+ifxDAoD0LWkwQN8aPXqyfIe3zWWMgJ9AiazxqdqK8EAv3g/ +cyZugRbtF/jqi5ceeUlmoJLNq6x6jXGB+lLjbD83zWcPP438hGReL62/N2EWIFrn +zgViEpcU+aThU0rtX7xXtuo7NMZRtvR5EV60q1JlEartQ8eGTA1UyWKa8XckB3O+ +tH8lY/ZsUHsb/Lb+EoTD4ZiNV5MWEbwKMzxXZ3DBiTdlZGtIm+m66tL8YhSJhF7v +VpBQLB0aC52wSccllNxvIdARpOn3IqtXjTK09szIaMfLJGxEa1s1VXtY1RKd3qcy +hSop+iugpeLj8cyBhVf+qQ== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +EeWN16FcGe9oBJ5oEU+ohgRhhPUxTnyYnwj6pG7yWCXXIFJ/c/Z2IFC6YMj5VV6P +BLyZALNjwaoSRWibW3QAq5qvNT7j0LDbK5BiD3kYMK2NM1ttc5RJe8nvvjIGZf/4 +QOgUPzxqMONvaitGcZqFkFRF4F2r32UTAF83wa/GXK2EVl27GpYipuMHfblqQc1T +0P1I+cdkyrOYVdn1Qa81Iz3uywJPy936keWhYnoBKnsgr368YKmcgYSRTKkT/tBw +MxLMmX96CeZt3TRFQHv4gfRxBPY8acA1UBgUTmeIGRMIn6vrYpV8wxIugIJFqVcC +hrVjUIFq33bxM4i1U0TwRQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 29968 ) +`pragma protect data_block +YhKy5e/Okr/GJ/vg9eBL0014mggpRjiJvYYOMd4xhuzrh41ain74Svo2q+UD8cs/ +Mgo4yRLBR27zxN0hMpPvEvXU1NBuBn6CvfUvQsiF1ETmF6vIlRHIJN/fz1SU4nPK +CEt8qslpdwoYcLUhTEmEGSH7UV6AnX4Beex90z4Wt8QTKeSbED0/+Kfkp8OSM6pB +inyfFunoVhJXn3TQfEBuAbD9zrwjI6d44tDPFbNzuO/XksRBI2/b5c5aKzCUiGNJ +et8jKCEIQ1vRD1t6YRBxsR5j3oyfeTnLcEZOLBeE5J7aWyNLqXnkI9kX/bkvlCMa +ac8Uad3JiuC2j0yqWxwCVCA9lK6To+lbdmSjW2rvUxj+1V7PdxTolb72R1fQl+Eb +WcI4849SvJEyfpsCw3+ia6EHrV8Hg+5dhoxr58pBjNPbfAqdq/+xzyEHcoA892pr +4j75oDhO6RlKHKgBPWCpBvUie6eTkqAigHG+gKqililZ9+YMV785rvVd4b6OKA4B +Nt81k9zd2kIwBIOaBBBPS9HC8xq7f3gaaWBbsvYXh+7xmxU/vS+powEfXaoi9NuS +dpLNKxxXvl4Tu23EZ3yB5kK2H9CFiAuhLtmK6oIcjBhzTsPhN5aDRWm0RcPDoQi9 +Jpjn2v17Xbf4t9x3B+hP2cY4Lgs8ufKwUOM6zu1asfz5mTp2e4End+TdQFegwlXv +dnAEsds989Dyd1oc2gPe4POuzAlMsmb/2OMkIkaKRITs6uDT4RWiUBHAqw3iXLaZ +LvXEcWT3HAsZoQvhMs0GJD4f8mX+bxph68c6LauCe486sMP7RLJTUZRNVrnvIVxy +8bOL4ut8xkDDvgcy9onN6mSE0A7WsdN7J2u1/Z6j9wK2QA22wqYhBlGZr73Hew+o +G8PQ7GipS0MFq2FzwmFVGBwTIBppGWtIx1lWGDI6b8FVH5OPxJUb8s5/cdyTPEDn +eh5eCTVWaUkeqln7/z9nOhHWWCNcTGAOX5yPc6uZrFwwjL+uogudpf4W5V8qWkcW +eTlPx1XfqVRTBgY7FDF2ZYvSLEgCjZ7Uhsli4ltLMQnh1OvLeFGFeI/SCNR2uTMh +67EoUV/rd9Qqzc+kbj7jhq4bNzfXFq9Xqx2JawGeDUAoCEhC8IXsxlkFDYXA0U14 +iWf6e6T/Bh2QvAt+jtd884yAg8lX4SqVdme1ZU/5m55OYHXKRZInzfp9yuGLGsN+ +s85+KHpbjDJcWnzVUWus+83S0j9mZRTiK7YkTI2jmAGALs1+lGeIYR97wDnXQsQs +NvkMAETgwhlYZMypZehs+Kvc6SLHwR/imnCnxOmtOzIcTK5wg7n2OZkjsfgAv4ct +Mv82yhpDfDivUVFpm0dVK+ug/+SmxlGcfTt7Pc/akKGbdO9IF3oXZE+uMUnLVauJ +jCdrMpaNxEAWp170d1/Fcxi8ur3RdyRMLFvXfraOBYyTYvSRVnMpxG7AbQwo6zQ6 +Di0nzskQnjgN+OSTqoklEY8q3jJqPvWFub6Y+BdiOE0pwzMyGPDdz0xvkWo+9ptI +hT3dNnZLIeF/iLWixfYCdySuJP+1nGUClFI9Yf7e0lo0WBplGpOMMIem+Ype4DWy +B/ynfnRRbDMxyNlNKHZiuQaTFVaWe2vUlHHwizM0A0sevVnndECYDw4AHfVwlmkI +H9LKRQxDkROygusPvLAvwuLRufF+x8DFR0WBN9heUOOnnNe8/WjA/GuQXEBwAEL9 +POJlZItMy/B7UqSpILzLu24iSBSbWzJ8RrORDqS/w5Zkm/hPKBnzcBJ8CgJfo1EJ +TuhsMqHIA942JCKPkaZIw/7Uqt3bY5LvtFnpOZh0RGLX3QyCsepbO+y3SD+fC+4K +SZ1GIGa/0Idu930MznqLr6VIQlqRqyDn3GotstGjF9uEZWeEgaOHeL2Tz293hTdW +e+Q14WC1HFcw98hdma0c4AUb6VRaMOeR8a9iTGy085vwRIfHBl/1plQLs1gpTDWb +JR3/d9DfmkFlzvjiZZqygB8OVFrpnLAblGhVqee2QChVDmhUf8fOzdxb+nVz3/B4 +fKkOR7OWyFZwwZH8z2RbpghaOmfpmCbiJiDysnRUTitX3P1UNz57qIscz6Wwgwm+ ++29+mfi1t/ammoVQblW2iVLRyNYE5PPpigAJrXrKXJk4GtFFLIkxlhlFdYj03O+N +mPTG8xBk1pX1aKmyIJRAPhD2eKZK17bxTNxYdnPr768jmIZVvw42AHhjRGXftd4v +2exlKLtTpfeFZZp8rDhbmGM6lv2P9rWhvCEKYd2u6VQBCXY1I03x5wXIXEFnaCGX +SCqgHBkn9UxtjD8J2BPj0QYbdRl4uJiqR3ibygJki1bBgSjnf52kn6l4TWhnUdnK +Z0VrqsIr/XoTiTSojNBeVrEsgnqIkrW2gom+pfdg8IkExmCp9EBV50ZtaeXp4cva +lL3ufCYITxE3uqdjyrKalzDoVmxw9J1+minW7/MhusLcne8H+qMCLRNuvObxtV0o +aS7SauYsN10hU74PBo4e+m9+IQlQzw2y2sOhYZl4pQnzn5TabU8FXf+1fuur9E/q +BQ3BS+8OYNr+SSwIb89nWp6/lL5DUFYu8pM1YSLIzjwWNWt5yIXhW0nzezTiAY8E +rB58+hlgtNtaud9EKz+AszwPGF2d0FTfKhOgQMiOn55jU21eKAjD0JLCKbOrNCuj +388ngu73uA8JnVabVQYCLHzTp6KpSq3y1z/Dp5M4Eupc7IdZdanSrVMSWvLxxWG/ +Lwu2Fvm90HXz55oBNDNve5/OB4tgUT2D/OyjS0sbFv+Zi9Oz/duPXJf8+nOWX7Vo ++9t3awynRyodYitp1O9dDQhvJ7bOKcwHMh2Jy95v8zZq7lHz6w2GL8DbEX5wetLK +eagFFkbZf7V2gLi5qXkRGYS1Nfa6t4s2AJqp/w1KhJFGwqnNfMhOkH9Ibki1J2mL +n/TOvCC67ggx36BrUOmQw0rI/a3da8+ffQaoigRYP97ZhsZp8TJnWyX/evNzcvrV +T7Zgs+pVBd/tnUC/v+DcZT7rEccWm1rEd5mSwZHQK8tCsuoMppBknv620hN5DWJn +h0RJmpxPQqk2u0ShH2Yl/BjwdPcxXqACNoJGhE/hmBBonQAzwA2ZOwSYWDhECCXv +g8F+pcyuP+ltwVuzIpn6tflcOSfd234g6DumdhsGSgfVRnnI+611KgBYvrXcDJyN +g1HOh3g1Zm/9eSuCl9lviOFoNoAj3U2uubOSktYznKuk1QVysp2oQJcjko/oPNAR +8YO6B8dMVtQVc007zQ8BkmrTVOZNyeBWNuXgDdvIhS8fB8wdjvoT+jqazuES4NQe +BxgrzppR7uy9KJSbG6idAPemBiePnIIOVlJsx+M0Sd8vlNCYp96jbFbHNeU2f9rC +SBdeyMS7IscVkXtInu4zEVqLRpKaKqwDAVXptgldky8swPlwNh/Gn+vrmfM47vFC +Y8hwdNG6DzvuxwoDWHdvjSid3vLAWHYkfJ0lFFrVVgX2rkEskJRdLRje86ok0qcD +uorGb44AuPxOpsFwdlpvviIPGdllh1wrnrY8Bc04XIZn8ebHfRFYDMBBGGOSVoBi +2FApfTObACXCmwrenYMX2FUn5r+LnJ9xyW5+jcko53+7MzQyQv7lfOMJHnEyMC5Q +Ug5UWJdSjCaYIkvBEboL8CSbOmqv+BJJ5yAT9qIYqOXfRXnOJavDbrJ7twbvnxNE +noclo35kgGD46kcHePm+DtMnG6b0VJgPYufpq947HeNpSosLfgAAFWfWtZ3f2a7W +LRHkLf/gGOIeNAKl8MwnhYqHuulrrftyLIUXmsuJnf5KFSVKRIsfueJgWUwWJ57q +knTLCb8ncMFnTQrWR6e6STdkxqe65m9WnDeCidKBYI41SjmaVSipthAbDbxe9lAE +WcaB2cFmpeVP0N3wSqwyttn3mArbjxPeMAVE/8Ci01rR7idAZhL7Q8KCWNRsYFkb +ZWNmpmZVmP3Bfo1cmRVc+k2EblQjtfObS72aeG+rACg9LMRVUpEzjkopafo1Kveg ++9KMvfRdpYVLkKw2om25ag/eVeKpBEPXJZLG3wI9OjYAUlgGN7B3LsGTEaaVvKiQ +l4Zdd67giE6lvYNXpo1285uhpjg0fp7Ul7+tCWPQfhxHqInAuKLOcyhhQKzrH0AI +F9JDV7dgo9x6mbE7FmHsy01XDWLTqBJ5DdeV0NUcimVDSJf6YB9KjmCJAiE/KnxO +S/42kHj9DGnW+8Rubs7WM6StdHEwOMnGmsnkMXFEfCHw0dwXUiKknfB8XnO5paiQ +f/xRgUjFJDNoAvbkZ/HxvH94WY+JIjynPnoGt5PFQXmJVOXDIyDkyuLB0wmpvj23 +JodosVqjQBHGDptRofrXsxgYeHmOnEJSdprbZLGQXbJBCuXBlL2BjgUbYzOljZ7s +hkDkBqy3rIJIflkwvBiZMRXlakxLug7o/8T+mdK3rxqHQnS+fXUYSqm+iZ73AxRr +RoLsexIWkpPCMdj+BBI0MmgqyWjJWIyLwX4Joejbncq7LmI6gbRGw/SO9oAmHbN+ +BrVXKu0JiaHn2BEoqOVZw98tqL+uHp5nEuPlRWsAPYlUexDfVCs3n6aKWu113xzC +6IgbcCAYZ2raXM81GrIrjb8HP7tR/3vg47AkMYAPG5aNZI56IwDRvkQViK/WFKJl +kmuq78MxQRcIDxQBgbOz/Wco4+WueLC0BTcTx4rxSSzkXSC/TNOuUBFJH8OkMpli +aGDkHaKCfRkCh/MjVy/awO9WnD4YVIyVoPSRiCgtDjZtSCYBTQWGbNCBoc+1Oy0/ +prfWDRU8lHe6/wC3KooT9NNjgb6dQc05oz5iGOK2YS2Zyx1PJxhYkLkv5lUU7GwB +/FwaVoCjbhWDg7l89qfBU9Y7dGcRi2TTY4Axj7A8G3UaViy/xSCyOeLQkjmI3tuz +wo+26gf6I6DA9z6ellzzT0azms9Guo0vEdvVNrBw5QKdM0cHmyu/vFMCAg1/Vd1L ++N/s+AoZpnO7gRX6e+uw8hDo07/fwYJwCGW5ohkIkHKxOr46zKq4sytke8/60wih +y6le+ZE2m/kqe4N3G5PS95izCPLgSvvWpNyp4nuX0TxRdLERgIo+D5sezDix6M4W +UjnsQRay/Wx9vRpDrU842CrWubQVoEc/AgrHTPjxULoD0CsNpCpgmq/dkdjTLH/+ +nDtyaIKdHMRGQAtRDzOoRJ2BYmdugtkWTvwsOvAsPKlyEygcafs5E5QcuZCE0Tq0 +kf+dIiC0jTgPgioE/uirnXar3BnN99YV+JUBidLXFnGkFwBb++zUJuQEn8Ub7ZVh +6O94COyXn7jeZXj6bLkai7w//0tSmoGveISL6Vgb0rCIHyY6byZ6SUGoyWuvoL64 +R+Ad9lc6mRyQbcE7H3/FdH7h7HckrWT+XGui9J2fxZAVxdM5lDEJ2cC9nAZh3rPQ +Ms1MbOC1unZr36iVhjf61Fs5c/BqDt/Ozm/chZP5QQdymbXC7ivAvAmxA6Mcl+2G +U6Xg+D0maveo12JO8gv8YT6/+egYm93jsd84iTobnWfegawXJoI+BQO9s2nZeofp +k60qjaNbMYAs0xxjGOTXax+1QfGuKO44pR8Drd+xTdOmqsraWNfo9DUtyrMgZHVS +ZMmyf0ETPgjnWGScOpgMmHXqOnW7fl1EF8aO+Q7OAu7WXg5qmgiTf/AlL6rMibLx +FQrA24PvK9ie+wUONJcpP5N4k4qgdQjzDlm20iHERWzvNopuiA5N8P4H9c0cSU84 +nulOiycTftWZ4R3EBs9MHMqPp6aY+bWGiOLH+LU+XgiBhfS81/RrxgTnMkzvNTTh +vZu7pVygkMNQo389Oq3PomS2oyPUq016TO0Jp5H4uWA7tZgFSEYLKyUpUeVKged8 +NOBu5WRjNwJ9QsWdPIqt2+mvfztEc8gmCWjxovSfa8Cvya13Kgg/TYJ+2CgSX2T3 +Pe2AqMy3dUfwnRbJ3vjVQBAs7b86rNryphzayzpQEuXIdSEPEJutKUqMawZt86bJ +YnQYxkJ0IiXBEL8uxzoZYql/1mAO8+B3Rcg63Tv5aH6jh4Sr26KyXM5yKq+kKMBK +yOVCHxIaL0Nlp1P+X4eJmQZldqVhwgqyoAOXCTgQL4rMBwwcAEqi2kghdEEKWaOX +1jwKCkeCHCtXI/Vaog9KmvMHOrRNvR4GVdgOPgAYV9ruhmmFjcI2uyxMrItf7mxk +aG1T06W3+I+NHm4HrMssWzX6AwiyNIQ25jbKLELUWdr+oG2qVMY5rURMGt4PJgM7 +I/pBH68LVZ5js34n5ZyjqAJpCbM8SG9HXTGs5EiNdm2azC5Jhpz2E0kPxhtAjGrf +04ZPJHM1jncG8PwGD9RWDOpjn32KdqhFfWQE12WXXShINuMgfaRxhbILeRPrvE9i +hpVef2Fd5cGaoXxNmiRRFOAu0oD4qcbZ9qBKSNkSFi6ogls98zGzE1Xov94dVw+u +E84wNTlVkpKkqknNLuZS78lQJaxy4tiNR9lvvdMmBgPBMxB/SFh4r8ON9iz4jjt1 +z2+bGFM3ciXFHGMLe1+W+PsdDRFPy9Y0JNQDzVyjSioqT1RTXABccbhfURUaWVbc +4FtBuIUX62m+DLYe/0Dmn92ekRmgUqgeTZG9FneoD8Xr+R+UCIQwFIduTY9XyhTn +eTIa+bGzq49bTFfJPRxKHmvYCuHdxcg1j3l1Ie33xPBd3213ArA/67UbyyWEqpPJ +A2GLUwCJDjK7eMt5nMnVDoeEtEU92FkmGSNQklTNQstjFeLbx6CzzLT2mAHI9x3x +jDoFCbWYm0juWw7f2QZrNLz3/HwiP08udtMMoKkKVYs4dfQBwr8XDbH7+tQXoweo +rwY3zv893PYI+0G/Zw6Cn/rBseHENAyjvozUO3Fhz+A/i8FN5eH9OLUlLQNFypZH +oM6eqdP2rtSed8cK8/GRVpqR2jQ3heH32E2s8pWrL/YdPd1JlrV+UWpbjLO55LVG +GQe08zBeZyD4ris7oL5l2xHLcLEvTA3EtpYAdFEvm4BcELO970Gox6uMIROaY3re +b0h7OcMdmFri0o07E3YdSAJ0fDMCrw75tDSRb6nWNkeITLiYFfCP7uKvCIMmhJ6P ++/+ysDn1CIggLsVvRtq1GH/sqs7zDjampB912d1Eke7W1P7GpXxXkqHfa00csK0+ +ffrYCA+fwJ/11vGechmpWxNCeBKjeVnGR7iyp8F+NH1OiKmDiza+thzuecQd0DHj +REy1872+K+DuKF/P3C0j0QAWkBOd7/ha1+38RjK6yNj6hVNWsfh9uDMPCRyjR/4W ++BD6UZSTfpZs0Dhsdc7sMhCCdtLslJn4puVvR/Q36dgUVx7va9saYzdiBMTJJXIx +qW0Rpv20qZX/nYRy6xCRZfX2+78neGS4lhs2s7hLjz0zZZvOg4yj5s4wjM+c7ysv +wl/OJUydsCQ3NgDArbeJywBLx8v75ODLBu2TfRA4/PO9JnoXbIhJnXtWHvaTP3BN +2/EIahgXo3mnTs70FIVMQ0FO3cI7MhkbJF+vse/846CDjbGVRivel3ZV2qMvGnr7 +/V+tBqJzlcjJ4zuXlYH61dKGMwd6/XrZGRT2PuprjYHGq/BT/9pr/cMho4o9VJIe +Cf2JpQLiA2DF4h80yCQYer60TwaFGBJMTp6xIxU9zf5tX7o5yV5nrjsYwWyo9nmQ +fLZuLuaS13PubhkZO7eFMwL+WQ89DZXo0shBuC/CDrU+fcH8XI8Qif7FaTfYZI6h +SmQGihnbAZRpbTOb+2qBPBb13N6OOR9cSD5exx8kag9KCExTlJ5C8wHuY4jssgrP +BTUQFJ0jQnLp7UX2Y0T9C6HRJiLK5hlWWWX/JmcNJgTVm2dLKb7hzUayL46kNFCM +uVdg3Yjo7pyxn+49Sv0LsZjPyafFzdWJrKtAULWa75uqwh0ugx9IC/zMIyLNupi6 +pThGdVZtqiSOf+/VfWoZeqzrsu9GcO6122snCgqZLQm2aJTln3VWk9abZUaeFCUm +Sk4vH7IOSCSmB4uaQoEzSYSCYP1IC8W1Y/eUhrF8QqLOtwlP6p7AbUO0acpn1qwM +sTRML3KPSD2u8Nu1Dq+hw4PTEVrPoUZM5/Xr95NF267JcCDM03ozX8NvN2v2VNPm +dx4zhc68blIvjwFNLb9ORoZHAO3NCw0r7z0N5coSLYr09lDmacyBXW8z9YPkn2pC +5f5RznCOAfIbiTbH+6zqBJngiJFkk6Ie2JgfJYFyN/UXFnPatNDVRjG2QVjonbIQ +GhxcQtWDK1R9dJK3In2Z4F/pwpflorZl4KBKCwI1U4ThBGZzWpob8rLBYdTyvTcm +X7BVFxlBCwcl69h8fUkctX12da1t4831Fe/idnJoc84jj1aRbbuMin9QAmmXShrq +GQjo3dwcSPCpf5Wd3LymhQoD4YDbkSIJNKPLy0A3VrU6O4dbgqv0L1y5X4rWtUQU +Ao/Eb+tP8grQS++RSzu10N4xXfndskuKbrVMiS1DqDZYShwl3Abl31oLYCWUgEph +IDvfjvrS0R42IEbDe7m97HOl4Ml8gVuFcMYf6Og6kyYag0x1bcm+dVqBtkhs4xu5 +gNzLtmlm4JQ/VKkaQcap15/GfDZb8Jl7kL20k9El4DM13z4Z0tv2AU2rMtKR4x2/ +LLsukkbFS2ajg4Hu3KKuXuLef07IVOCb44jn+GG6LRZEJ1hLwMrR0z63bQIi8mXj +kc40TtAbhDYXwWmqlDS8YjV/eKQ6hEjSgffhyOCZVCeoh+hbCvza7JFIDx4zPNCz +G31lWY78xS3M7qH0xPU1owVt9LPPElmHRwXZFZZLgyCcxv4x5vw5ZaNEZHO2pYPA +qBbPJ1EoLuMEZnmBEJgck0JNFW6isHMOhL8p3W8x5qFjK+v/Ze+CHhJeum6Br/Qa +FR57mePVNXQU3GNdSoO8RMnqYsHOfk//z9QRjabcLxWzqNz7xybmlGrCqq1m65qW +RITDKmU6AUK4WZW48CekvowL6yBvLy472moNKXFWYckDnpCCl27RwEWzDPkC5AUB +I6MztSfBEhDuRH1cliEpHHmirKeNBTaUSrrOsLAhib/CvZY2CQzkzxhCFpDrjMgE +/36rl6CVwvC+o4G0rW7oi6L/AwieB42x6ih30XG1R2eJ7t8x6ip6hbHYXK+SzcmL +yQu49J9FAfK9nxZvO6IkBsGe2O28JrOMxfBniScZ02SzUQ+rmG5T6wx28fcDwgCV +OfmlXo7fepHGuTTV+7P6iuxWoqgWdmLSh1WUhEA5w/X7kB/Hmr1ivAT8xzChGsyO +fvVl5CLA/RUd4OQTtAyakC9ueK1E16OxbjBqG7IbQP47Zn+HHIUduhPnCjPr0Osw +kmuzxlCxGY2TchxEZo7mVRzzZeaw5euA91Ucw9HCOy6rt9Fb523UitbRPLO8+ZUo +0X+5c5n5u2kJEsqFcK7ymufSva0HYsirP9E3NMQNQdPYA6QMIsJh62n9kjPpL93f +OkkW/3IDYqS//vAP81lBk+EeSvrRBeGYTQS272RnCmWbIk4EwhzVUEHBkqpNgXCl +DRGY0dRe/86kjTYVqkBWXlhze1EPK8HMBo7rX+AAlIq/z7yEvlFGbgVFSgHorGq3 +4FaZj1LpLekro68AwPHUu/OT7vOanbPn5MGCMDHmH+qZ5BLh3ZT12ROox6OLuNX5 +PpphYGBNcauSOHecC/0cjp7sbDFaf2hx82oimHI1vSgsV+XfoV+3AidtTKklYSbF +k2jmANyjBJddmBflW/1YxQN81+OuilrSuidYpJSFdiAs+W/RIIszXo1cfZfv9Aru +l1+HROlAP/N99ByvpwaYcgKeUhSAVyifi9yapYdkiU7tdGJbUgXjtJ+ly9WwiW69 +L6cPutPV7QRlTJ+Y+hM9xJOy8JshDlS1wE0fMRwIVteZ7TfXgBOujrhlUhjyhMNA +ABtf34gAXoiD8LRb+bghl4ymKCwcL7VbiJb8R00+eyyPZqYDT+Yc4+LYR2L+J8MK +KLX0n9BlAn9UmBs16bVX6o0vJjyXIE53twKIfnhGlc2ggNdsCZzfbr3LC+7HpswP +TYNOyJPm0dtnrXFYKR+CjPKb1hVtL5i30v8wRb0yl/NnUaYZ0TWkD0/qTrz/EPHu +01IaLh6QdksoJ5NY1KsAO3W6J0JeKP+lhX70NEfucbuQoq8gejVIJHREd3I8D/qN +SzgeC3X00UyuudPXVwjvgqlDpgHQgUcFCnL7x2WfqIrFr3OX95Yfnh4jmHKJxQ/Y +zGXpUHy8xGV87n71KhzRKeIMnC/gn7IutOZ2dGho9PPxMv2pitcRx04TBaN8KnNs +Qw8zF6ljz0iUe1ctAoJQQ0nBMioIfYukVZGT4nQASNBsURs8QiKD9ftKlZnYr/ZE +RzkHRqF/fHJ+aXR9hE1ujUUDBaEL6V4TV0BXIKFyS7jXILNsKuTk0Q1v1RT0JOKJ +VNRP0TzUuD2FFPQ9ePzoMI1SxDwZQlQPGajKxDBAukNQVHf8bwYbbBbp7Ze89AcB +wjVvlqeLoKFzJt8pekoq0jPTGu8HL019NFWwCkx5+AQl5A6wMqRA5sjKbBctH394 +Rq0x7sonjGiHnssYi9vsZ4Zky1LDKnl0I6B5ABpx0ZxokVqYYrmEyRoGXkDnKmSV +ofyNZvVNBIj8STmGF7mmvcaihIxCYHKvukxSYNfLVH1ijWRWvaHSOVApTInpOO+J +0CqhxL8tv/hwAfmeyVWSGdfUAjV5+vNr3yMWhXPSpRGMKARuJQ72tdQzSf3Gvcgh +CMOOrpNWhWS+/qCC+gAXhu/e8suA2zI4j5GD8XS/tcoGh2UCZnu503o7RNdvscpC +2TlRtu/8cRsBfIiMqnyXP+K92s7HLVYcK6nDlO4uIB5lcRMn58WcAC5AOZtl+cR5 +nzrIma3pacHV4V+UxbsBVms5PNBe6DcsT9iON5Be1a2OsJDqIFvcMmlvD6GpzAnN +/VMF+l/24CCrPBVLm+WuyM08euPnDZTt0nEjca8ibGagChkw9hbQ5ta+21fzK63d +q+yM4YltPbe/xHSD6XfpCLBSSBrywcum+S9hxmPL5tiZ2VpNcVOAB9PVSvcFq4jt +s/cT2u/al8cyJbWTaL0ac7tI4uiwZX4Fxw7S0/xful5oaiThAQv0M66CNf92KoJG +J7tWWU9NhHXurNLuYmthgedWUMjHbkPHE1AqExhsOT++atTH6ywb5weaI0wbmpO+ +st7Jv3ukaLvat/0jm43bQ+Q2Cw4L1olu0mE89RwnAS7aXqsOUZ26ZI3GL/y1kiI3 +lCNTV3+MnDii3YIVP826kIqdN15q40Re76XbSeQ0xGMb2lLGPOpV4P8TrQTjcdl7 +dOZuA1TQ0Sp23MCViaDB2BPgNl0iJ5a5OT7/Xiq4CE8i+2EvKDk0xzF1tq/2GV+a +iziTPgtRZQMke4ieyLdfuBXAaqlYBvlYwPHu3yUjeo0OjKF8FSGCOB0U9uZx9Fs6 +YXnoDdB0so6/YMQecSe9nJ6CAcOBG4l7d+6dRk/ioLZOS7jlwhX6aG//ocM0qMGS +vvTL0WN6Goe5q2slQKqMNijNWickYuzKKrf/cpIEWwCgIGCf4jyPEhEFXFaYSnT0 +Ky4OztaiZ4H+UQPQbOjWwaCzz3G8LOaFwFh4EPP+/5C6TpkuQ2b8TvrNXhAMz2BP +8DJ3Ce4OTj4peKQL3oqf8S9mUhoQ/q1pi6olDgI/kAFvi6Kn5oKMhkIU7xGrxYI1 ++z5wIzNbR7AltrkkNY01k2QRJ+KG99W0zKZriZgWwMtYUgYzhLZOA4C6aX+5JB91 +KoQj+RwIqhH851RKTsHuyPHtXkHFLDRF4qC28pEXXYgHGbwyHbm0oRdkzG5gdFRG +cDs3KA7ssDJsZ0bZevoFNkBFaNpt9HbJy3Zz0oNw94kG9dGZhX0CFr/rx6XbPO09 +qkYMMnKaUA+cxV+/xI8qU4n1ns2x/YO1Xw6uLiqwk95a4hD/w3IzM8aPtpH1hDbE +e+BccZyxZ7S2/+h6xHHvRNQEf6gM2RQAEFQNMGYBOQSifV7Unuh1qAT9LgA1gyiA +IbFPRjXl7GnAHesrXj/i8T36d13tbVLunj7r0f0x9MqVmBdXWvEb7UWB1eRbKRVQ +Ds9KSwNmdqRzbTuSBiBQh1taOZpdFl5Fg9ZNtakylPeZm2DtoDe5HxiHODp/IUBq +MhqbvWSqPnjkzw3Hu9Z0v7M0FdaBy+WtUVUL1T14vcZkeP2eLUpIHc1LXRzBd08W +wWjuLPG3tXhBsnlkWrJfFyxBQy1b6XX3gD0p9H4wtcnZ0OYOGX6l/DJqjievuLwY +CmVkDSLh4I6z/kb/gkJn8Tk4O1pKuFi8CBgUXgHB7pLfiX92wWLenhbpd8V1NYKY +q4fJVMDaT0+N0YwW/RBclUFBR5fzVuroWO3M/kF3mCUQTYEfPFq1GTwj/m/91yW8 +FlKYiSBAgWzzT5yD9ZnjQYfXrUYoqDB1EmUT3EoTgEjRCc2moQ/HdQl0OkhbsKwi +417XfF8y/UiJSdb1ep//aMFoKa2KEOolycNnh7VwREApl4QsobkEJGRpl5g2akMM +DThOBUH8rVJl2oJkFYUKQtFCcwNXHPr+qKYugMqoYc8vQPhYMBWk8s0pxpOVcFrs +HmqTomKtrVOuplWDcfcGluEWrhYiGA72LGFh7k8e/IkLik4c3uKfIHm81eWH0zyc +0fxOa5xqSvUonTSluCiuf4gyQXyhjqi2B+lhOCvci3+TY6FWJYNu4fuZQ5qhPOe/ +aYzSfh8MYwOC138piwuI8J/JtA0pLprMg1u+0t4Ym8eCEikKrYYOspyPbTcbk7F0 +ZTPkn/h8JXIyZhsss3g3QX3/R4ZYJtD9wbTFUt4wdxSYFdQYDEVjs+hwb8WDUD9E ++sKhscXOe6RfUcT6B+Tgk8BMh/7XdWRTpsZ9SM9ahIQgATWUg2JhBnPyEwTuoZN2 +ImOvY7p2qxrzjND1uof92AKR1+3cvNv0YJO+kbyyfJjr55kkheyZqm9DL4DbemI4 +9w/LlTQVF/g8JX0B1yZ1xBiJdG64aWRMqTVfpWiwKSFc/EWMNTdO2Og04qAnyPoT +ufP6OLbyI4I9MIqQpkC2N15QJwBYmjswQ5oKwqs0unkRaVJ3xaEr5XQeqbpAOHT+ +m78RnA6KOGXFdcP3/pRBHuCQWhlNrVi7rVhfuoqqydvYprt5edvTIrClQuHJGeMu +woMuHC01vXlhNUzmOoP5RRtQHeUs7Z2xaAl6XoxmzBc59FZteEY58tabW5vOs8uw +qzyV9VPLJ7Zcg6WwnJi5gNIS5cXmOv+kxAiLpgeKIL8TSXClfatnJnGVSURrKuf4 +aB94P6j8oE1yc3+dRSC8BQIJyM9QOFvGlyG3FIZvcC+owNUrOhi0AahUmqCO6CMB +AU5nH80j7WC3Oo8c8kbsA2qhXpbI7xmZZr5iNW8UTVLvVTBrvEa+c4kLMudNtATu +7dqkHiPOd6u46/yiwgKoiaRBPJ8xGziVPW7SG948yA3qnd+4D1NMLIrRp6CdhiRA +dr6xenUduGXlVbi/XVAfi/djx7GT20tllIJ/opNfw2TshnBwjz9Lvxvrtjfjp1/f +Mg9RPLmN9iFjsEg94w1hu8hdbxQwiDaAOBLmeDtt+uk7Yee0b2ECcTlAOWE+o0KH +NMf64VMiQHTn4x7O0pnhUNWrJQJUB+6awt66SYuEgMKaD2/Ey8nkdoulVM5xat0q +G01aaT+PVkCr7UWBlZYPDN+FsxuPYwZJqXqTxbgSZXBRD8fY25Izz/8hAw4ec42g +U0l1ltkkQrgyKZy+R1uzc5dDEe77k9/QbbUSgFobiMwYkV3FVPM5+PLJJ8uVPfdF +G0NF5RP/uVcOX/uFPwixF3d48vOBj8GeVolpRR3HkYOIK6FcHxi0NYQtr5L/6Cgj +bQyIVH53qIWwhGabHAVJQuXeR2I3zo+Qhz2CPvgjE2+ZFfut075ZXKReDOYNxUZK +brmimCK8PMvbr4XKgYJ6YtJacYqsG275xoSeveVPKMGex0mkCL3vVQ5XoloIIgOQ +PH0ciWzOiBOttEMUajlAlzZ8S04zKKC0KJipvbyvebdsJO6WDk2mA8YwSIcORU7o +QHkzifQjkGA/Xq+B2JP7blw49T0CkFvSbU8W75OvMPSs9RGzxGtPSJlxU9v3c8KP +NlkxF34ZAV4xFWuF42vxPOA5EbT1nCVu5fLDiJ6l4QNTWnq6aNwM2ITnH57fvcgY +5qxDVLvyxpILEX1UZdRG8dEtzxznTQB7F+9DnFZ5aPKZFl2bM4113vdPA5MhDpns +H3GfJQ+uW27BKylj7cTJPiPFW1sOSF6QRePXgPkF0E9Ny4bO0IsH40GPpD6AGeLN +1iexGmvrEfd0ongHRKqMGW2tUTl/qZFgzmTXMOE/R7adhw04JRiix2KdS3pnixAU +ASuO0U0LWJ9rNDVy/YRIryNVKxmk+HqiTBygYyxoIbK6Nxw7axCBlnW7PXHF7agf +fC0yRtb4FNqly/Xe7AADaOrMG9MQD7HbmFNRvi/4J2FHk+29MkJIkVFcfDh+wQNY +LWLgbRUd4jSHCwafm5pu2GvKsKLUKBu5cUGChJIR+kxkq7gkQ3uwqsAKWPTc7l28 +4j0LEqS3+zr5X4+BRhAYQjPEtZxNS18awX2UYRj/gIOqg8PoqoTpIGGJ/iAM4ntU +a9jH3zxQrtrOStdjHIz/Tio46KOOyESYUooKnvB0QYEtSvu39JME1nZ+/P2TKfqC +SoQmjFy2Bw8WYslyrGmbtHWYaqtQROjXe+wiKlql1MqslQHVWymL2CPxqWJF3nkc +hV+Ij8geZODKviks6Tr36hGxhnSHtKlJa5mHQW0XEpnoFNskZuK8jGjD9LXtTJTL +iTxL1it717z/FYDcljNzg3XqFmjSC265EZPLU/l62HZlU0x9sj1aqM6Ea7bqQDJ0 +YrVxy1CPEwx9FJL1fvUOShqx6C2DPAE2t6w7LHwef4Hw9+WICAzDGYl0NQy1wBoQ +xCTfS1+vNaeaBH2ff5G1UAD4D69Ny97POUDOKqYjQG80cGbojBYdCaAUq4T/GlLu +24zvyMP781AoSJ/Ypv+26anN9kg6SiAyhjDJhZbn0cpMjoVlBmqHiwJ8DPNbyq0D +wwcPxsbj3+jRTct7Hnt4B7hK8hKyTxNv8J9a8KZb+PMvkmFh7GldJW7Sk3Ai8IKY +81cEeEJ5ih8Z/DjWBYr9g6fGuxA/htrcP9nIkvnYMJw8yOy2dKHdau1CZ1162fbR +L+zbgaAP+FQamTP/lb2HSuuWyLVQU4sr/O/v+mVeOfwx8HRh6QGod54BB66T3JMm +hI/6j9eVG7ti7qCoZ3oWGlbVFzvN+niSCwd0xlkgcTGQGvWEwn+g/hP9klnVlQt4 +tiMq60y2dpwPjsr+8+aAjyT4QD/JGJCGlA8XezMwpY0k59kk9VQjurUZD6cKOQd3 +supNOkiFMoIr9jf91qpY8Tt7FPZHTMfqDkzkNS4CNc8WaA4IgKEiRCOjOuWqhaFb +GPIFqyddm9SwNjfQlB30/zIc3vn1gvjE+00vGJSJGNHmX7Qwm/nqYA/zr7toLz6c +3rY7mV5j3ib3Wwdv98Hw61cJE45Y59Guf1O7B+4YAKkzS9rWJLemzvZevEbT/UK/ +EEyOeAQ1k7n1IBUAtIHuCYb3qKlasQgcACDqQ85Q7g0cGL2OnJUW7zw4AZUvMynj +xaiapxWNFRhwnN0Mh3iQQRAtPgfjs76K7UagKH9ypRTP4lYb0y3CDmT4mIdVI9uT +nKqzhxQRgIeJQqJSXpOgS4oTomSeBliG+ZRXDZZTVJSIHdSFbVSpyPMDmEXpXIJ8 +OYzMWBT/jjlcyczhb3gzLcrmq1Sn/F9h7oFDGDiWyBfVO0cN2k/7ZMBxYTEe8hul +EC1//eLqVcQRXaHQAq9LWEtYiyMbgSIaONK1s3OcbvYfTDczSOaOPpn0jAPbh9n1 +kteV+smvsdCIQvcCF5DQPP0d4UK5NF5d1zUi7fXtYzuW2NDDfsms7veVXIlwHGfl +EWAKN1iP8Pql2g4J3IxQNJw8pQkLtM22rLUFr97pBV3lNIb+wPp1NFEO4Dn/gyvY +sDARB/i8nFB+kQEZkHk05Lq8FRfV9m1ZhXc6ybeZviLff7eD8FIaS9Fg5whSihyy +hFvkj2H/LbMHZNfgj3ror7SQKAnlQt3aIomD3ytf34vm7uZgbD3lrdug136kRtRg +iX6TtQzPb6xX36P4jVW3L3HUlaUwDO+lKA5eScIoEUsYYXgGMCkvnwK/zNa2xnum +UWdynov2iHykz2F8GqO8QS89Y/G39FPICkFQgv3mvhpIifPBtaUoCeEuln3FcJIz +zksw0av14YxC5RDeSpbU2GySaSk6PgirXWSBnKy6+s4X5zeL6C4GHIoJgBP/j0lK +KfbesEdde0BnyFtjy4rxD3H183wD8ky9S0ScmyE7fVViI1A4+SNexOE2PW9/F7Ta +iIheBFBPi3XimOxMCFogncXeL6TFRKAEOgnc9scfEbjKWu/BVr9dv3GOMSy36xAs +BgzBhnL06uIkXvrXy8xVpSX0hB3IGOhxncfwnVmdF85LBCdk166lDQJGBoecKYBX +ckb2Ec2WmrI3iC6KDjwNApyGdrAZ9kbrXRqv6TrTWBNhPahvGFvZWUUyNqV6fbXj +FasbcaVZXRCQ0/2pTB4bmPrMQzAoVM3FLHVOZIAlqUcT09BiS0APm7GWryH/uOc/ +4IulEaXzD1xHWsX/sxyKkBW9FC7TIqZ5I7JBXBjs9YWvmR/6lhuAszS33nuVSU0F +SOVAq9Pw7SWEKhy3oyHodHIIKDT8b778SfShgpGdQbGEKICOm/x4RJWiBHY6gdNf +2TH3kU6Po0B6UisQjNJjtD5tpuErxQa0yPzFEmwiKVJn9YnJpn8GNZ8G1NVmoX+O +WEY+IPrzqHFSBuHt7T2KLh+aXbRjTf7H59SwWZnaP4tZxKes1pa2gpx5rg3FuUOM +Cd0Wrrd/B1CTX7/l+hqm6U/rf1utCrg3EqEPAR4AWYtSdTvk4BNzP1dqV7yrJ+ZI +h31O4Ph3gA46HqOKbhBBzMUqxHzvkziUM6G+DjpZNg4eVz7/Q9yPRcTv1fhmOiBa +Yym8lolOuq6CrvkAeGttgNELtLA5dWRTDmxRL8txx+Fji6SKzF6o0M/MOvYXK99N +nqAMFovODYajClL7ZHjjhwwCIc1zfxrI/S+dLBoTbnfhqUOiKm+ND1QPeA3P58XP +1wBkxlcsWrI4W2/lwW9JQBFS8XNM8MU7df4/ROehxRRwEzzqMoYpT6Nadp/vBRqo +301F/gDwlTkaAUoHCtieJnIhuldJxyNExF83moAhwM21BGOjxHzBYC0C94Wnf1vM +9dyFgIc9fmOzYyOzlJfRhjpZ5HrgHR2cQ/cdpgElQOFyyEfDinIhCrVAfTSQtnzI +6KnAmhWV2QpdYHMnBzKJt9Ndy1b4tlL49Snolx/6YES5O68lGeHerfauKW8dEE9Z +wEsBjQ2+ZhgLQuG4smO3rPImz3gg+ZeqiJPdwGZBUI3gjUX3blU3SZOa7SFVfKV0 +ars3r9+8hguxM4/R/1KU1okoakHPScvCdJH63qtJqrkYtjYAhsCF65JEWFZPesGm +bETSrFg0lX9GAaRVls5zItyfT+qn0KuTMZGn1SavSKnyAwJHQq2JqLdpccB2h6zJ +5HiPSXQUgt28aJERpSxJJF44I+wFL9BZlyliGU6KlCI0D0un7HXESbMcZJn/imPm +qsIUX7b+A+1eUVAEny6KwRWza/fcverw/s4XvJx+6oxlIPkxrE6jNGicVRlfisco +oWUAKJxitKr8qAe5XGQKZAMS0SNYLZIm5NLsq1NzUNOzN5W03O3XeTRbKKp2LC3x +c+cO/s0iJRs9NPMJMMIVajgpJ7TzN6OSrkV6c5qQOb5421vu4VSiF/nHQVFPOrMv +oSscLUj3pDly6t9Y6A89+FYeTys0SVkLd6cbRff4eKPkSkLi0L8CfeVye9P0P8be +rmkjgJQQAJyI3TTyW79aJku3O2EC1yxQ7Xkg58N1uYO1quwhWyuFIc+vmQG8uU6F +mbJgSEiRpbzcim4SLMZ7gh6MiJGXFyRvCNPBVhvU5b56V8Dn8cyprtu9LWw5wRDk +GFWF+HKGQEO9Z9LBzGRyBexsHUSPAAmYi0A4vOTw/O61WmLXmrQp8jnXFgL1Gp6x +6zDuXTAjpCXUOZfOA+S7gu+rPXsVkilDbWkukwuu572tQ9Qz9mxUrahGX6WU2iVX +GWX7PmtBsYEOw6uuyCztmfem8+AGlNWzqiecVx3MAMS9Byx4aauRgyjxQoNswaoU +Wl2JFBixIoiHgGlZhasgvTw5w7mrDNmHPYvNsxi703jWhJUkO3pULKelBEtrhPSw +pcNGca5yzzbQiaE02X71S6vLi3AIds5LhQijcLcupeAOApjO24Dub+NEmDDsmC+T +h3wLvoeX17kuq2WVQcCrSUpqVLrtLuMT09ECNb23ZmUzfdSW/omjfamzRE/TohSn +Q1aQGyE1U23yJKS+D63/1kplmVK/JgwAOknAlhS9tZmBvu8umB11rqnPYUobBCnR +dW+iJsGyRLJxP5yJytptEzRUShHSH/V41C56RPVLhJh1RgVbRrFB7ai1dtOizCSt +PjsIRObBtMPVFnIWy3TBYLT8V5wtD/HbPr9fDPYw3vYSHqTuwzfoc0wqHUFWp2Cf +m9LKshhcpdwWM9SxE6ZnscxhMBQEl/O1myBZXFv8mBQkNtWsyguhWqAdxpGVxBYT +Lt3GR97Jd4q3PBzyw+WZ41gKdNj00EP8f/+BOlrKzmNXQSYyF6UGm38nb49AdORb +K7icdXK6XkdKTkUjdei4OxHxre/hNa3ABg5nkSXOxnSyRdhoHaT0PMqWLrMc9OFO +eaj3vxQ0lQZIb9PR1rPeffvKowVYuxoE3SjISFy3CrIdkuGfpSLt04ZlKviDxxsJ +UsTjbpi3FnUToOLH1ntGSZifmgsVrAfYcGfFjGw95N5YtXUHcsa+vz+TeiRoWAsO +GDdmQxh2y/zRBWbAMSGTYylXm5V3f12ps5I4NnVFrhAsyp3oZW9epXxFwi4t/yJ2 +GAVUnTwmE6a50Jmr3ktCJZmDJBrLtpJrpk0MVhyv+tmBY947XFjIpsjB564ltc6T +urjM3kNWR120kgwzWyfpPxnW1C7Xz5rklO4fnfbBoK861+JLkQPpCxjajyDvLUly +J5nfZjwTpg0zkiUM0elTfLeGgDYTDa90b7qI7gshIhulgL65ubxRGoZm00BWeM0d +ZSVmyofVr7+2mx1Vqa+SSYzlcGSNEg+alOKQacuC8yYiasoCcYympEM/JB3Czd0H ++2K5rMSObJwRBlKkJTdBlBN5YGnbbj4OpkCPd4qvy+/3O2NyrzdouIdlIu/iqpEu +cJc50Uim6fkJ81XTFNsbSCI2CUOz/5IP0eGklA+a7sfwcR2VTDgQ6xt1ju9tFX1g +sg3UL9nxLIu1PK5l8a7WMmT+grsf6QWZYGufQM0po4snNxYPoH0I1HvgLZrzuH+K +uiO3rAwBKoProgOpayBEfdIDyNzHsjltaeE4/8SLL91XEa5aZBoJ9BTQqXLKa4Mo +Nk9tmi+x+3q1w8w6OIzSrTxA+2FeDD1iG+jNISxWwxCdde70kFfiMXLu5NJ3EwDE +0jVgoWOaDnRLLHje0LkJWnXd4uX9wOcz8FyVKZjMflNY4uOLkTuFiP5UwKIUYQLI +ALle0FpoZbuYlgtfJgSaM4+53oFVLYu4Gq7oZIQyrHwoHrazor0daCYYZkrYT1yv +Pun0OhugWZ1Lu8JZmGWFxKzGRduyReQabo3KN8hOGijvN6/xq+NzmQacC1I7e9s8 +cr5nyD/7PNbbW6+oiiNlEICk2/3sZu1/+fQFHO4RNrNGNShb2HBgzd7ykJcAR6af +xN9iEOvNOZ4Od+0wevIIbsOKnbR+Pjdz2wFSORJqL2iVxJwNsLV2mXzFkQ/Gahaj +NYQEHFlafk7Ow9YeS38cd9EWRa5SdfIz1TkMwqtvH5Y5gBOHDetWX9nrCNrKErcy +QdI8JIkVRwvqKDLWkItGVwekYaPijsx1Wol2uber19tPOO/1AsTz4luLsKOTQWP/ +Car+mJJDEHQ+TgXA9ZKIW0/iLTLyDZof+yYBVIM5xbcCtmttVK3qIsmeaMmaOcs7 +ozUiTylaMSPDXK0/LvabbhDywU249Ve+IvceaynFR25rD0peRP+5YCF3og7TW618 +rWx0WChnNg8q4PrNbqqTqlK0xkzqWuEoucBnsI6aJ0zudsgsKz5sF3rp6deUVPox +rj2a/iIDr8pt9/BSc66Vis6yYs13CZEK59qQZaPd3frM3Xj0Vq80oUY7FiZMsF+F +zn6x44m9/erMU9JbZdwM8fbj0/xv5uhIcLGt/L95l8xF3iXOh3AYOee1HwRyXAjF +IfOm5HJ3NYQoAgFTB/Ycc01I8lhemnikFt8+hqa/p0MUNG1vwjZmJPPjUnaYtT0K +wiMW8D8uqivaBSOFEkvIyVBK7cpu18iTJhtw+Yt8+yQ5cpBg8kTC1vlBArJwC+9D +PnnbzeQtQgG5O9V7HTEMq686P+iw+Vg8EG7UELeXcY9F5kv7qCWiZpSvp+SG9QZ0 +eMlrYEYZYasBOMDhHNMGsXNYOQH/v0SJeUJqBgDCy5EGSg6kW3eOWTswx4um9sM4 +jFsnxUJl8Y4RBtxiwCZoU7sbslQYjzD8f/qZbwzjcEN+Q9zgKWihLkcu8EbdZJP/ +E3w5d800Ayg6qZqr1DsvY3D9ohh90493076vLfBC0HD9GwIprBrym+HSEKc9VHRp +JcAxzl5F5j3FD0c6+Gd9NmhOgk1Fm4b+JEAlOlvC8LOF+bf4eXkmwfK2+nt+7Hvh +GP1Rtizf6CzZAIcZmOhIwOaUN5uckCmSAV8Q0lS4HapSA/I3FFHs4/O6ej5C6Ppp +CbaDLUlymeDr6PIXI7BtFf5rnxN3p7hb03fBmJZYY+0e6D9xorBU/yBQULNJKnlR +XsZL8SW6vlTxLbvQNWMpS7a/jeWrrDseeoRY0t01Wn8xRm78rVkfNkOpIQDzkTn5 +qiMbNcVyVGnUJSIgP5awT2CWP6lslAG8HCPsS4dGwm6wgmewuutmHdZIlJKMI2Zv +zMrHf5Xto9GmuMLBmqdmcLsrE74+cKs1eLtQqX7Ssf/o3bdOjP3hQrq+PdDYp3WH +v9YyNyUJygzUvH0npswoaQdVaZ8bsOdm/qPSeUs7YkfMLIqNswLwZrDkzYo2HwIb +3ZQV0Mw7t0P+U1Zr6Lxlo87YgACJnkj8TrmNfs5xi7+MLMyViPMeX9TF7CbcEd7V ++nRdfJxHK/uLtE5fz3cBiiNwaLvnKCODGKcrjmKiwXj0gIJKz/G0cqshYkxDj240 +olJibnwnJpkCUtNjCY9lYjYn03jCDUCwXi+0Lt8PlHfTOKSaJR1Up0j1voS8+yg9 +5SLQSdEswZUnAiRDFribv08afsOeDHlc2tFo3LaLHaMNDaM9MhK89LM+N876W5pP +NvRmsdMp8S1MSP2Tbt9oWFZMUyl44V7rCw4tOVEzj9C43u0M2Ql7RW2v0s3Vvf7u +ZX0azYywBUO8jjNUkMLTdBcYQrI5YQJsJSdAosN7ftb226a975p2gGD3BNKJ9xKp +wk41DJTdtfJf8/DlzoBSrnoOcscTocEPAJrSG2Uf1UTq/KZC4IYvLwgQ7vM0JZw3 +spFdAlfj8HCBBHHJD2Z/as67JHrpG53mcOKLC8ZmMt0BQMzwZMFyJ9yYampdarWF +p93viQWrJeeon2JBEgAiyZg6Y6oIUxs6Og7UL4Z6Fok6os5LB7ftt98048kim57f +zYdi9jPfyXI0M9Qn30Ew4qv+daKbEw5kB5mQ9EiXhoubvt8/YGP6Ujt3z52CWjkU +3Usix2qJbzISydzVzl3zFNRfgD7KZ+CggbqVQjyfmCX8JK3wgnCDBBnNAa9+wAnc +aoCmd9vjuna6PWyY9nk3OgprBUWCPnnEfKnueMq3du43XsZdlKXRBWvrbMTO2aFY +DR07S0SipN02Ca2cGgPycVNnpw1WnWBRzxyW0VSIxjlg3yRoRPGvmD09pwGwwQH0 +lxhsNikGEDpZrLGM7LWZ2dnAC/bbZYdrFGR3ttsAGUQZ/EiAlDK01MYeSm42LVmL +6YAsxN5Y0U7lDQNENtLALEWKkPkVAqwUZWoPbVjr5kDqHS51WNjLeN3Ueb42VNzi +u1qWFjZHXBrJPwmb+GGDvlfac+C9pqeVRyi/Fc4rsdpJIx5Q97FZilrKpU/qL5mm +8sx8ZIqEHl8SmD15K7wVe+unqrmITnPAWfwrctVD/EHtC0A507a5kU0/mIcqRswE +sXPVG6GdeyQuXCZYSHYTjRnGhKN3bFq3aJUtnMhehJNBcifVJZeXmAkViCI5gCT6 +me0jD1GolQ3zcBj5LDhUjXacJcGxq2qdzGs4BZZ3tRaEnDvIRm4pi0yAZZKYP4GL +ydchDzxfGX+puVplarmcfgKk873ZoIT2KLJjPxqLeOqyyFZJ9plwW82HW5XO93ia +K6eqsX9qPGezoq1+UdNNTJW9XC2PwdprGfT+tMe2ST+lhVO7PET31kmKWXOIr4jW +g23XyfJpCW+W8cKUv7WYXP+I47b2Wt8vOhq+z1psSBBwq6HyV3zksObWE+nb3FG0 +UUADjuRIbBWusuPGxJw/JatSliyUf6Qq1vF6cVQ045PuYXmV2LC1wiBgdCznGxdu +uJyD+uviD9nYHC0Jfy9t5SINdTKHREY7jCMFZ23YQqSyyb8/QPtSb7sG4W8g/eZb +q7rirgQ6bzZlfkHz60Xt/KijRFDo/Qfh+DUyl4cHdBJbMlgBQoNqyN9LaS73S/0E +rZftKR2t2RfEM23iCSncDNsxVfcKDEHTdc7F/bDSKu7pOFiaHTiNWjCZwT4MkJqF +Ca633MyqN4/MpX1e5nyfS3/3N953yxD1mci7sMTR75kOOIpy5oo/oOFq2jT754Z9 +g1UoKWENVM1JY/T/Vtn2nHdPWhix3yVW5BFDisLx3LuQyNJhiUiAY1keYjW8LJqy +j6sqvdISVdk4o+dsoH/SKdh233l/2bY//bBf2z/yRDmnK2FV54rEbndATRQTk8mw +B7SPqhT9smTyHXWpdC8RTO4h2E5y2XwJ39ChA/FMIBqQJJFGQr3N0ZHIoBwMAm2R +y7ZZ5TLNwsPDWdJW19WUPY6GzCh6HDOa/YJjq1voyQZPAB0duyp+j7sgF2PWpmxa +oupeFHtfmwbFuuYNxHHpDBWO1Z1hAW1WvXM5ecI+vXkxKCKdDzQH91RwAqiGSgiD +k+N05id19WNeZC4gM+ANC5bW+PRwYsF6mLxbserAD5oAwfpPKWonvX67+pzueK55 +qVWq1/mMH9KWcfQMARVrKxDLyu6P78qFU4hR3w/Er4RQdeXh8uTZu7nwOcL9UQrR +bNXIEVxY5udUlUC5Xabt6t0ottrxQ+cIgnaXI4Xisu/591p2Ir/u1R12/I2rzfhH +6TnM/M64woujGqY8SemaOwGqPQReD8WRDwpH2oGAp7N8NpWIbC3wuMD6N9RUrFFG +42As7KF7HBKamjCDNK++1K/iDFzMQXV+FbD32BVmNwHjEyNTRUP7n4FQvmQ5IOYb +taarbexT4Ipa93xSXwLyFatYPJ+e+85siaPA0vagJF3VxSYEmLz1SrwmqIYAgSAG +gWs+iMx9FDhQZvyG6jtXSjk9LXiCpEVWYXhp2zqOVOTVWqqYbqO2V5jvaVrzmzuC +/sSHGJcDMM1c9X8UdKTMSD7741usb83fGtNEn0Saxj/nJdwue0JhW41Uf54evBu7 +JwromkonaGOQLbxxmx9pgItmR1csjqcn79SduhKf65O4vWCRACskNKCYjBxEThr+ +Umt9Cv5+P8hVUVsO15botf3dATIEEZ7CcL/g+Qc2NgNFkuzwACE9KEYb9iVLq0Vp +uQoBaSgr9uDLwMKUmH02MPdTMRn5H01/V3+2Vu3R1OxECW++vnITlnmOtEkS+Kac +4s56DraRIfHq8sqMUxpn59ncoMMCXSWVvVC+I2d3X6gLikKcUbrsSOWXrtm1WTU+ +gMcwD/m3Pm4m/9K2NEkqEp2NjH5uoxcapcVyXus90Tp2ESbz9ThoLhj+6ta7MmYE +puj8hNrBDYI3Y8sE7gA6ajztH78oPgC0nKaTIWczgXAtbW2jrzZcBamlvz5TSvKZ +ke7yK47Oc6LN8jlahwC/8ktolhkbNQCkX3DJAhJ7Xxl1clXKDlmdD61pzjwleEWc +59VxWDh5e7aWSbDlcdGhRFPzURzvA/MMcOIS8twUxBEGj7pSBa2lEy0NaGZKd2aw +N3wIwkt6sIT113boyj21sUQl5nGr31oEA1BZnhywrSSrUJlXqc0a7SFl7kbGJeZd +jWQMsuN1JtFVh3Cr5iCZJd1rDmNtY52f77miJVWO32XxyZJ32PXxwXfS2lHAHDZU +7QMGYVsPI0D9gVL24X4ZUinkLEjF0dmdC+uOTXlVTLydH4cCD59h/KUzYp6L+BT1 +fXZvkH5u6nu8kHovilwRP3/hQrFvEigBQJ4JE3Z1B3P8pHvmn3VsqUNVhVAJzZo8 ++7xBKK3ywjO9gwgmpkcpyd9smv5yuBLZZgm6ft8slVX0VVxCfyEwf+RgfGTSxym/ +hVCRdKji27nteF7twRvQdxnQWdOmhMNeP6g9KQTZmaBIB9acdxeI8Pnc15imP2ZP +ID6okR0Z0vdbL44ANpY11Ky1W7KpXeJaKQKPJR45y84ffjOBKXMaD4ged6FjfBUN +OaB6GXorhHlIGA3G3ytKPF/guH5+msHibZ0gNdYGgNeElkYQvmWv8E6fVpyq/3sk +VsjzalJ1rYhmY85bniQIG86w13/TMUaEd8q3HFig5fm5RCJpHm2oMmZyCklBqC7n +qO4ccufLJ7truSn4tZ9YF6vwuKig7NbLxjvMPRZq6su/iOJVcuMXMLRBw2p/pwg4 +dKXkcL0ecdNZ1pNrl6srcoHyLhdLvt1XTEtJU0M2Jag7eVCHrlJzwzZ8zivxw0i3 +Uz31nORmSTPEU2rDW1Mmx/c+3fhGPE9Vcfzym1q56o2Fi36lzwfjRfXT1/hoDbLa +seMSBJNWF9sMKbd7QcCa1kV2QBRUbowDYQ5fLTcthXOAgYINYu7dBkNm1CBwUNON +eJsYInBIwst6z0r6Bthj6BpJmXCXWK+pRBM0V1jFLbn+LcrWvUD1br/0Dlva9xqF +PGsigBm0y0unsHMYcVqJVQzWDrPCIOywjDwmXPysFT6tTzjQEeMQ8OyJ5mYULd4a +3UT9X/D73u2Kgh1B5GcVeMgeS7huyIWIbVPKuOmu9BnOkX0ThTa4NXH+scx2x172 +x9KqqJpAZYg5TfRllyg81lhuB0oUGb/luqTgoVvpKoO/UxWHr70IlC/xmKTsIuW3 +8DP5PXdTenLvVbrd78WzPEvaccOd5LyCMQ+aSZl081r87MfG2x4OEcHCv2CzUTjX +qDB+xneP84C7j8zh563RzdLtdiYzv1htEpDV9ktaFFs6zsba1nisfuNKSXFagaLR +4dRfjYONzFcmigimAdXG3LinMj/hwn/PQeP6Q/vTfyVTKTMhU5M/s3u+HngszDtq +hoLQqUo55Y75/B4fyseJWmSrs+XTPV+yscd4WgtIeOxQT3wWIRQFO3jbnHbzSvnB +M/zqKlsWVkTf9957++o+j4eppnHMDYxbBxRZS2k3rpSzrYn1hm3ZSxDTL/x0Sk8O +DgC0wATJ4Rf2ukwj074hrK/VTVX9UzU4gY0dgagb6I47RWVLd5NwHfpX0dFmgM2s +3KtXv0BuymKf68of7funngXbSMcWml38jkJowRChhHvXsgfLb1lS5Lm/aNEKYACt +VGB0h4si7Er8EGzaVOweVelIdjfPG7cGMWVdvPFH/0KgH50uOQQQG786wGM8xTaY +fj9Q4JkyfaudgLVsdFk5xbV7vNL1MFPAwGrLF7iwQGPc8YXbjH7tSYTXhNXGz1yM ++11lCQvjMmr5W9UncrQtDN8qDO4HDXCMSD7wsA63cs6zv+p0BadkeZ/C5YE2zHBg +nr0QFHLXK+avz6StWqTw14kONkz50nTie8bNyK/ogYTn9RctU+mXCsm2k2+fjX6A +FDN5BUBMjixzxDELW2Wt9em84SuLcZbzEiQcMLFDH5EQ+XpHZQo2Jmv2JobmPVH5 +90PvHu39cVUWPDxqtclLxg9Lg3eoB1CPUxVsQCn3FwdN4tlKCmxVwaTyIFOpE9mz +cWhXJ20o6MWffQpf6rT9i39U5Gel/pTa1ALZlJejaQ1jeyeaGUImmB3iEBW4o/z2 +a/hdQDaJeC3ATxOS00krf9pvCXEGzn7lwByIqbGwcB1kcCL25iwe/uC4lwn/W/24 +rBOA+Xp72LMZJkn0xwhFDUmctPAo7ZHyjCudnZ3eWvwv7UPfB0/+DMa4/xE4LQlz +MPK2//tMHH2T7kTKERAVcxgrs2mnWUCrw4Ilnwm0Mca60BO1uPGt5rC7Wr/qQGvk +sMDaNqSvz5pc+fzRj1372NOqMCPHvGm3pMdaxZ8oF8TO3Qxm+VjE4bEDCyxWAhBk +LgrWCUSWonvZE212shd0C6wfGfXNXHJBLmRXGts56wpztbTk/CTbYrPWuHlgYxKf +JP0uOTVnwhc1Xwv8qh+7KqsgQySTRwQo10m9blQubzeUwe/wsYMGomnA3h/mlUlw +pBljz3f/J43R+ZjPyCbdzdQeSnMAUo6uEZJ7e/GGwx9ztr8HOk6vTM6ggHDr25hS +4UQk64s2TeRAM20EYFQablZOaMqbA9v5ny6/Td6VZ/krb4TrUg9b8DjFmp9utusz +rZbBehJD6+DWFUi8n7KHfsZHEZR7lp/vVWqi2lnp65bWEpbuyly4TOANEztGTIGJ +H/4vSrHhhRIqjJfCwRbgCI8VqFmGMUjUcz3p+U0hf5qa7Sccq3gAF01zvO7QTxAs +7bkuTyLDeVgE4+S0GH2iifHRQP1v8EopNSwSi2xXGCtUo2co3ClbTUUDMDkGTJxg +SDuseIkN3GBcM7hXmF/8wpXpgrx9NgMEcULjmmzpwvkjDilMCWPSM+kYKN6vGZ9p +Q7hfGhGMNWEetWFz8+pSSsiVRW5cXfnXufZmwSM0CFl8R0VwmZc0+MHlSNhHKT5z +3+y0FwFlLpewTXeh/bVRH3+6K6bYcBldhCwu07QVpKfG4sFDU9/2IQvLfK2/lsQZ +4bUCfvAq3h3zLU+CpTGMMxDs9+NoAvorScWgHPWwuQN8Z/WvQy7YE1ge44kmPc37 +q2eCHvEPdHM4RV5y1+6LPonurX7Q1p4zhr+tlpLDTN2P7c4XDdTbYD5xx0vjJmQO +s1GSzUXW6aRXyvNzh46qwnBBaD2bfTaPwS8H0ZwpGFcQUVT2HnzWxJ1GeAs3L+X4 +EXrQDiyctsF739coOr3wTwahHC2Us2t5WSyBeL9ALksyR4JAs1tgjBQlZ4/oi7On +qXbKJTrLec5aqA0jh28D2BTCjUHmNs48qGxapYlO87T0pdzIDDudtK5UibBWtePU +8N2h16wpTMcFAONzIs2VZYqpMMIAqWTy2sTDrnr6B/Zv/qcH6rKHA/mOyYLF4iy7 +ELD0Q1rEg6lnwj/gBYmOwuQpqon296sjcAIuoFbhnnn9PLkG092FpgMx+QLNJ1if +sVoRb8ewRlXlqe0o/5juFMSruhM5+GPjJAdCRkpfwFBHRivNGQsTpnVK4G86YEUC +cnN93R+xhHF1wh5hhe6Sc9k+i4Rxih6snUsQGofTf17EPKrM0pVfnWYEE4n8a2tG +LrJ33749EAG6uYLuN2WMKdX7E32vInVQAWHdB/cMBJXzAap8wyUN9oZkMgNyrlFB +PmYgaSPfbY4mgKCd1Dy7ITqF2AqZ52vBk1JHI6V+enTKiLBFC7OQqjWqTJUeq8ZQ +TS3oDbmCydc+K8DnPl1DjMl+Fy8FiPSi7ss/szQQwE5MT+y4L/pgII7kjIbEO0nh +mCFl9ysiQNttiPoAqItEjY7kOlIhhXn6gmWloDAFz/HLmhg1+rKamXdE4ZVjfpmE +kQKlKYf9xhvtTBIiiIcmT5VUbLZ1kKRIec/cOj0k5X9dIcIbkzHpLUcolChcTzIO +dGc7KUn/do0N2xAnwj4hZaxBuUeXkwXvHERRtfgzttnyuYw6p2K5isOg47nPwGj7 +9eMZ6RgqxYLbSIUKD0rEAYhv+JSDu1ct8MKod6tobpBZnEfUZBaRXt2qoywb2wff +sc486j51dDSrfhqXUDy9+TkApb+e64ZGLV1OME+ZIz6CXbURGlf4JuQV6vxiEK09 +UB4hWTcByuXeYp8rJmhZvDTGbanEsV+6HLAF3H2pviCC3qeMfy4dtRaHbWP9jYIk +TQc2CLLuDruj/Y0JIpmaJsruZzFUZavJg8+H+vnBb8dXJxUeG8tQs/y9lpERbVFi +E0LcSpvjRaPKgDGWZqHZgriaFzBlZ0OBwnlBmiHkGyCobUZg9wNXSgiWLcRotCE8 +naMz+C5+qpq59dXW9Txo+6eqWUEONRCyAt3ChjO9GdbgLqnBwp2bJFnatUhI+CzR +x09Yz4ut1WTAUpkfn78dPdkZJqMWecRnGhkXos1Sc6xjLbRSmDD7fcFV2S51zbZd +0V+s9vu3U2XfKNW3Ezyzo1k3VneH2c26LhBO4xOlyk7oRSxBbN9tphdr0IAWnyTW +om083I9GxK+d3BC0uvf7zi/+53mZhRnuen/+dMBxuK0mm3vXZ2Ofy308jI6niwOP +HtEYNz7GhEAq05GwbcXZgDBIcIv6ux/5mvQ8927//eZIj+ZQEe6tSO1+cnv5yzpE +Oqtmdhk4JM7QG0a2jOQCpqkFplcKFKJNUFhB37DHSCMJv0WSjrvwp4p+38R7kasx +K832lv8ZTmppGoqSVWYTmaKCOWqmlavv6BGI2M96WjSnbVdBFJVXgW2AYDKWVjTo +KwxId+WxzGf19/feoK6/uYwKno5QHf3XLMplFMh3G+waRpf4xmTbeS61wdd3/txv +Yao1bJuDqZJza4SKQOPsFXi7g38wQGx3emTO90rOuzkI0MN2UTQuvdNa8cRJdGpj +YbwHHOcOjrW0LUjFUO6TZws0Q/adv6L+I80bWgmUgfpgX5VuNyKvZe2oAQJXGuy6 +ILtyUUnhHn9X1nSHxCPNkJiRg0nzrzSCx917p4To0jcINXlqeFuVuWBlZKFZtRN/ +weaxLGNKnVOvTtoj7wHMvziFTJ0kCTKoahw3rQj/9l2SuZ9gcjiVHi6wb3EG21YS +0eFEjRHMPGdOwVoH9QLGRxzHnzd9SbfuXyj/l5scpw6A6qjIKDKGQH4LxoXpCOIK +Y7jJrSBE4vERzo6WyECYGPh+Dn/aIiQI3LSnSH1Jv1PLcqCyuoClPZF4R4pRCq1M +yZ9IPiRZWvTj3XZLnNXfnu//2Na/Dh9k0tLt+LJtr4T6zfnzJFVzZPorWwnRGRX5 +j/aKmd20Tet3BBpxRNSpsSdXdrN0Z56G0oP/3CgXVMuENaxbhxpup9tRDHu3g1GI ++JU8IBcaoYCP7D4ay/RzkyML3GPjdmOCdcdtpRm9IzHzFUFelmp3XfwzWBldsAZB +HsUJfUZdiMXAZ0qv2fNrOsg7XeloUajeCG0ScO7VIX5kghYqd0opHJbzJG/6gH6U +HIil2scCbHijZD8owLTvU5UfSGHEidPycW3AHWRk6LLQ8wYF8AngFKGuX3YjCTc5 +ST7So65TPGsq9tPLDtRHf3Rt3zmfdj9FNOsWpW9M1+Qsd3pwq5BL2idmHpSLx9ME +EJVbynnPai3o0Fy/ydW9Oo7y7aXCUAH13z0CTsHnOG3Us041n4Gvok/3VrDg1qQ+ +Qv0E0y+X5QhF7/463tEQ+6TcX24ldnPhXxqgGVZ7NQ+K8QA1tjVymC42aCJj5ogL +Aex1ElmbCUFpz55CATNOCrhwL9LB8KHfrxYTGAnc5+AlJozMP6vyb9tKv7opNXH0 +MeadxTyT3E3i1/w4Q5PKxSMtiIDUANbSvYG/p8k7NILl1oosWDshK3en30xA3Dbu +BFDp/h3Frx7FAzTNYpQMv0g3OxOaWpCjydLg/ZHRFPaXuSpbLVh68Pp8HPzNYYVt +zwWP1+XbajkXt877/yoTU4Gds8//Qu8Yc8SkZpWolimCIHG5OGgC+btH7mPRfqj9 +ks+21zNCcchTUNHt7M0LTwBtjVerrg2xm/qgWQHamstH8wdCrf+sMmpsqg/L3GMO +Z4ZXR2KIJrB6Sx/ob7mTe+DJLYXdlUU55YGACP09GZ5NxNUEVy1Ep2Th4bxlESOk +y14L/dNqin+essZGx3FEyQexscAGYf44RvgJ7Y5ter2SJqumbO/Tc+jFdBGjtyfl +8+6OhNXXiFAfcpKPasMfiWULnM+aRecqw4YxVbG5vq7GH7bS9bwQ80/cB+MVYzl2 +yBw7wWlrbQ+yh7Fk+xJ65J3PLPhjTYAWcqCTMblFy8+GLvGxVHdXhQNQHvK4LiPa +bTuDgjPqL5Nt1J4HcFrzp3hxb/hSUNg40v/hSeVV9+KSWbhkKx8v4xP0YW/8qZkx +aU46bmrTep7XeNz3HxYVOW2wfndOcAWVzJNoYoXZvQDZykBJ8okgsx6Rvujvwcdg +I6svGLrZc/qUJeW0NoUbKpByu85vUP4IdbacocZsKt9787ZpMBNAjpZCLBNnS4II +Ka2rhl/f8kFpyhpy8t9rzcWdkhUyvqEYFNlkW7jkJozquvJHsaxa4EbM2hd41fY5 +PylxmYFWm9rzk24R1k60cu9296awWuws13YCHyRv/FHUjINvf+Z54NkSVAoFZ0Nq +YwhPeeyXORhJ2Nb8IOAgDRvnXEUbfEe0V8MkCML8fw2YrfY1vUnNFnUwUJNMtWMi +j4M7xVseV6BRTAYOj/8zdY5aaJTm3CUKZfhcJdtoN0zEWorq1FaeTq578oDMbliS +2UCNWTWnCLoD2yil2RpknkpGDWhhAY/3bZIRkSnrRIXp1ETU30Nfqbgl0Lpbi3j8 +PTNEccY2/Nu9rM9xFbhcRgHo8/75KNQg6TZ5thuHTWYDizqe5HpUmypwIMJGI0n2 +GNkH99wnW1hz6d+Jpo03XBbA+y1PkNjFndIlEiK4OWm5z4xVA5pKmYQTt4L9oe3R +HqKlA1FgPHQoUmeuFk5OPLO0/L+qijyXhT60HdiNhhf/rdyq513ROkcSluKn7kyj +q01MM12zvbkbHjWy48b5ZYy5ILYEB6qMZcyytrk8DrrbSOhsCPaOXmeV7QdFbll1 +RK1puJWa2OG5DI5C+VP1q8iKWMV0nVASpjNxVbVvBjC9K/VFNi+uaygpAJDxK7al ++/vwN37vo4FlHmg67a4V0gaQY/wONw7Z8dsEt2hjN2aS0ooHQrSB5zgMXXcLpylU ++kxvqlZIKev0Hk+upGXq7DF4YWIbiJUilpLOCXIVk5Te3QuRsdWs0DTunYJ/UpJt +0WWXhdUz1OhxJ//uJUHwzVjV/piWMXNbtUIsxNT97Bu/meGVIIDO5HlarRADv5ss +CPWO5rlX9DdfJtN/OQehCy24nmXPId1RqXyN1FCfCsxiHBXlAr2stCOg96KhYySq +XILg4pQyXtB9+2Py0c1l8tnMBNtrcqcVYDcHZIW+kNUxXXTuXGSXOkDDESYAI96S +/WLFcpa/4Ew6Iy1nbpA35YRJv2/laHtsj8+Q/w1d4qml/57cAIXVLs/bxvs/2Ky+ +vZKYDKW9HTqVO26qVlI0XOSgcw5SRlpBOKkqkYBMF5YGZ/Crn4wYpAJ3Xj4m4gHy +jL8hxW8uAl1yhzamtHON9q9dAz3UxyIH/9VWZVFzEhxJck3fbrfVfhFCCUaqZ7WG +0knM42hbWZ6Clzyh9wQRUUyQQHPgv4X6G7Ayd8jRCWoeBuDh/rN0R8W+9DJ+x9bz +sNAyRjBSEPdMWRyeKFtwa/TU6WmJ8jqHrIhZp4uO3ZQM5WNr7OvxG3EfY2KEnje2 +Qe6SsqFm5MIiI4tTpB3d4boq882gZ9R76aM8Hv2+pgzPW0oJuaCZdHf2kHTqY+S1 +Pn4ELWNFCNRwvWGuV8RHzOfsReFMDw7EqKRie8oXiqVxFsseXvcutjhs7p9AcbFx +MY99dpI/J9LW6h60ba4vKLBRx8gFW7ERq3CNEcYDhQuBzUCMimziWTuePN55hF2H +nNJegGd/hKXN7UpQZ5FYEX/hpRuYFHYwNRlwiEpWEm6mRMkVEbKipOJ7P0Z/4jwq +eeTr7LCU4kFAgJxb3wUKG06iPOecKWu3IH9CB6Ar8yEZUo4zXeGIDW5+iOidHRQK +8+8YUjZ+cnn1t8CywxGSM2BqXVDG4dk4f7ZmDm8oEpLGngu1Lv1AapuA1Bz/8hmT +jWc5rW7ECB+t3lSTHkgJP1hzBjPuWe68IlfK/stYVmW1JQ28yr1OAIyGdEwF4RHr +l9KlKObrEV4qiIEFZsv4dt9a6qaWG3Ry1qkf//P+OzfQkBO9/HE+ZPt3VoTXaNAb +v14clSMXEhG/vVzfSk8tMFZqfVrwAkNIKsesoidiSodzQEepRyZI11NbDEWhdfYq +J0+O6q52QXQQU/0ybtQPhwtSs3VmbkkqwiUqvQ2e3VN/WCdtVoCvhLhXh0gCtlx9 +r1bK1SbR+AUofAMotUdCV/Gr1BFnZsVbgE1vK+dUEJY6WTs9ockAA2xmFAd2GzhA +ui/aN+/hmxrAc4/cShnA06RolO0TIOfX9onHtvdF3bmZhdmBitSel+dmtsmL5kwF +InvpS2tQYFbceEsEAPIForw8tuHXAFoNrKCJiVlS67hQzmbKMA6Z4BDOG0j1nn2p +TB2UlgSWvNhwzAZkCaqvoOEyJLqXxiqT9VeVFUhKrBD9MYwFw03kMRvhLm421mM5 +HX8ZyQwdfZAHZ06rK31lMzHG3RpjY3imUTiGSN3mVPfBkFMFHszqg/qGiBCq2yd7 +HRUrJZMSq876kzZI2Dudp3TzshXAeVA+sS3gP8aKECQpWTGRsfCTL03pD6/MZnWs +QO1WFjWnLHM0NT2yPlBFRPOVhKj2BETYmIN0A4BLTfxInfGLUG9P2l46kCoNAKwm +WINq9OXJBdJ4diSG2TIr6vjuJV2TmTXMDP4B+JUTb6QKC9Zi/SOxuR/0A7R1TURr +MrYa0/ufJtrvzpCNZ1COGsNhAkRnr9nK8oZ9Hiu5jCVBrG0esMrF/KVy+TeBZKNi +1aY0KCocu+lf5Z+o992iybEbOUNRETzo/rIBmBiW+9TDRW4Lyc8rV5BD16bXtN/8 +ru8WvTNCfujKwBWCyWqLPsKhh4Te7CSODjRC8r0JDMf9rN1a9AGuxET4pp80ExZF +bGJ1K9skktu3p9NaMt1R9QUu3DP6D3d6mVFzSoedPVoF9rSYXi4iAsOBrXLzaCiX +zcMILwSX8kpg98h6QMRP+Ve6XbxwEXvvaFi6uNlY+Usrgf4Tzh2wnJBVkfJ8BeD7 +1vAgRNwsMkk2m2pNAeb/fI4g5JDqHaR89+op5XkAtcEVY29jVVBzb9YKFFxsgKUR +aBzViN+dauxjxAWDTd1c2LDKTFym4gOU5wzMgLyL6L7MlGubdVhmfkE62E8AJVJY +p0EczG014Nmr5KIUFTstCruH+bRsgAYYIyOwTSalqqbUUP3stkJ2KZIPn3GVZGcW +neEgqVdKD83Fm+eUcgIBkwbL9OTWRE4TmDOJ16qSAr8u6+Z4yg191nzYxpnGuBBr +kXjMVmLj75KNYmwVa40VFE153/KE0n4q2xSqgooLpWAswS6Gqk7lkZQsiXBTqh6Z +gyt2XEmsL6zPMW/+kG/4P3zwWIJacui7FhaWZwXWgSKMkBPujjjW2547cMUnPXQE +xjTh++jtb9LlNKS8dNRw3aSgU13OKymJ62AWHZrtz35nJ3PdYWOzWoB2C8SJn7Ym +z0Lww5SjxI8dLTMgIvuBSpeWSt7PeLD+rLwdNNQkkdqAc95R9tkC91EIFkkK2DgI +sifL05yobnCx184z7eBzLYYHjC9nFRTEl1fYqeKwiMi2EUQ4mWtgrJDDJXTeoitw +6z9quSnJygRWEa1g2//+juCuqg/PZoXWYlOFAsrLy8FegB4IuFAAyMJwSF0dY3D3 +RNbGsTx0p91yy1faCzWzC+EjZJ2BMm+ekYHRVyj0n+BUbyck0+4g6OHkLK01WPHX +lPmUKwB45QxFy5rJQ1GuSTXlZf4UMWJkkdQHKtuLDoMfN0SueVYsMWxby+oqzDHC +xtahwpWwyXhbbd+T3u1izeOdFlqiMDVbzHhPgiO64xr00NRNxiVbxZPdbN53m1HS +v8PDve3pmlBP9+Y+fT/eQimL76oURSAKXrP81gzW4Jw6pbHBqjYOiC1PaLs1mh1B +V29VU1YszBvkQUPbz9dNw2V9CBhwsRGjyMO8lMhUTWqZtgXHrDdFdjkOHEp8Q6sB +JT3vT0VlaacdLMEQblQ2W0O9VLF95SH4D8wEbShe13K1pBKXdz3mG5QwVLI+E3Ra +sk+YyDu6xuGW3SXlWcaeRigxR/hXfpbX9Yc0aCnxvcrR7TwJN5PAkJhCCG0NuinW +bzUizSjBgZcZAg6duOk/AyTgtGKXZW4KiSXBLLuxQiSZh0wW8RdvvfFmbTdxvMV3 ++wqWt8NontbB0X6eNSuV8n61tVoEjn1KDgJTNCDCmYZjzoXaGq79hZDgz5QmxgRz +PwpV+snEms0t+XW1eT1ibPiRm6Q5JBBmt4WeyC6Q6+J11WP/QKqcCGnLLS9/YgMP +kEzozLm+Ny0HezrocSHpl4akP0syBfeU4XT/MSXJiRK08cp7c1aykDVQl5ikPM3/ +JNi1blzWS8KQxR2484wS1Sv/S2aRag61Rfwe3yu5q/iq9NeX17P94jeLU+WHG9X9 +9/trB37LWAq0t9TzA25gVztHBj+2NHboMTE3eIufuSeNjnPGCgU4BQTOyeaGL3xy +OcGUoO66B8ik+pc4Wc4WmtDk4rcm81wbvhtG8UpR/8k9ZsZfvV4hmKsvottZI+Oz +vn+oyCBx0KP4IcTnDoc6Rdubb/KqlHGS6/CTKLtNlWPPpqA/5+AMPyg3twBB021l +kwFSf+EFcbAsd3rMHLCWTw7EhmRs/5HdeQg7U01iIhvL1zmoZ5s9/WV8Lscm0hqO +XK0JupF5ScEY+U/5dD83IRPVgrxM7x1GO1tXEbjNcayA2JGlOq+jPcMLL6HrD+M/ +Gy3CyarGxTIO4HEt9W7X+z/i9qBJTc+CjuPHlSm4zAc9XdZ0rV7Q1e2zOoIXvIO8 +h5bjSeXTJl5XnI5m+FGuYetyENyVg31kTU6R8T9xpUY0uOWQqs4IYYFeNIO2I783 +UGRF6PeAf3+WjgyCpRGL5LWCtix1NjPSwChbedyAkI0dTPTNvSI3MkuoZezacj5I +HBN2zimoMbt69ZjjSWp6b5qEZi2ey1Pb/1nsbpusyVX5huA25wu7IG4HT48FWHBE +JFsL/rz86JqD3viGovCcKfv89O/RYOeMMc4I6xOAE5jRofF9IsZU3y7FMeFePyNE +cNcWFZ24aibHvuBGeHQ/ExxZvspNbDTOp1GDUK1MWEL5/E7o8HxYzZXSQYhysF14 +7tgiyQ6v2IXsTAwrnl1nFplRfVLt6vvJ7ICE3gdCVXLe6cjlPmX4050TIWTXwf/4 +O9jdyThmM0vJOlcWoOZco+giLRsI9KoMDcx3ct1ztfxfw/CniKx7oHSq5wuIbvXL +PxFrmF0KOcWqeYeOVYXgCyPvm2dOADNnJHX0cQ3dizHZag/ykH5Uhh/pt4irtn8j +tnYwU2H6seAyqUkexezdhfdX7rUnK469erGu4/agX/MLCSZM07HAXYahvgtMjwZz +MTMBR+/XBeWTuhyJ21NRB4e3q3VNZ62pCzIQRN4haNnRre+y/1qCEE6sOoCr8DYv +nQZ5sKQZdYjeg0mj2/cKyKaAErXtmN8IqPqSykCf0UUWdB7kKG/x+LOSwOzk5iva +ylSw7r0crY+iXv1rynGBAc/FkbDlEX2XjckKVJE7OmzD5wX1bzTl1hoGAKlAU6nT +YCiNXbeDVAxDBbyZNXo+Gwb0y5ll3aPxRLxNdQAstwoMKoj8o3pWxcrmg1CP+XZf +yoC63cwI1tRh2uTm8YYmoNZUBiZkWFAwY4n+ukpMOmGGubFhqAgdyC42rdL9Hz0p +QKooRpk9JDCGyeR2P9jYGio51Fown8HL/R7ouk6Y2+prgRoVkP4eyvVGtJ4Yx2ye +Mt4OZEzllZXrXZrKiDlCV7JCwaXDTxWIVH6SdceC9ehBZinJ5lHSgiX1vptAVoja +SHF4PDQrVGoR+j6oJRNAko/Pru+eYGgImjCRBkoSqZ63pRco9dCDQfr9HFclWYmW +1jbzERoFEXXAhKKOExtvVVYQyv4xXWVtHbXJJuCpEGGl4kVubjIiZmK1bmJ+kh8A +ZCGijYHvac6eU8fyPziCT8b540YbvODlm/a2kBrjsg2Ak4px4bk6VfYjPVEcxnwa +Aj1ymUC+VqxAS45Y1Dgqr8HPhDa9Y6Exgx7rUaQ2kN8FF5iaX4BNf195qltvFZdm +KtXIm+OGtFftX142vGcqp76WyGY03mBWWtTtK8GwXKJZNIRsF2W5HRDm60HYfGjW +UiYP6gDa7vnRqUWWnbVsIhoKKTkgqeBgnQbkrT2q7WHyPwSt2+DLqJsTCHdNyNNC +1cD6A2lL0C0s0bKKSIHwLOgaSqwRjp6AL0cz32Av/TJsYqOqqDGOj89v+wMZz+GK +wDUlMuU4Ex26EQNACsukjVZq919eMKhCoSEfgy6UFnrytfmPPbagT1ouUFQgjX8b +4rUfFTqJhy2upBx5dmPVfG194BkF0axY9lBGcE8Mv87i2c4OutrUWDBMQKOlV3hg +f85xIq2GInu3aBvqwtSrB/tnoz+J65gt+xXhyp+SFx+7EtzqTBRS4PQNwkkHhVjf +3kzi3gx0klr/ivMECRe4tQcFsePRmXbR5kO80bDXZP97ByskNp2h+JTA43NXQuut +rjC5QlhkolzH6VHDVtXewLqZeVBJGWHuUpzxeNcHQGrOU3D4MdOgsgOPUBkmq5QK +Cu4OV91f62bwoPTsmZFr7zoYBX/CBVPl4K6X3dGAv2JrVW2ggqSyN93Jy/sg+CLu +p1/brvkJM1HhU+IiagHKjzIXKN0OwuFGvtVmuPIR2KhGxZbZRcOhBdS9+gbfFNco +1ZPtegIumcCV7QEwkiQJzdte3+yKZnX1aVbmKN1lBCYkj9FPngK+bSZCgq9lUswj +4DJdPYYozsdiNimg7lR05Kob0wpGyNkCQetRUD6MzwanDRmjUes3qmG9sZ8olcRT +hBJLi5XkG3xOxhmvx4wYUTcHM1DF+XwtSgAM5tzN8uBH4UGdJFArHb4nCGmpvB7G +ZemwNxkTZ2pHJu1EKZlGm17gHcy4gpyOfukOn1FsMkCcumXXbfDIsKpVIBZfB3uD +6vinlA9HUOBBq8K6IpEBc8op8E9dsBT1VCo+iczuljblMh4p7yK2bvCbF7YbtP0a +JtWCbam0vvSA+Y5mfC+KxuzyMfk69TbWp0f7yYixXsWiXxUYIQb59Qd2Lzq6chrP +0zhvmQcYZzXP0abepP0PL3UKmYEEdFeREebaTRSzxfJeXdZOZMuKPmuFKyWY7zvS +apho7L9f45L0r9z2Ja4vUq7urcukidF0MW46Bz4Jo9PFKYiILU5KYV01QWWwHv/K +7tqw2TKuOA+86TeZ/RNMn8098z9pMlOaqV2omRVSEfI8eSCORTgXZCzCVAiW15cZ +06TWipAxAGtdFF3h+vnBNy+igsKUvT4l9snSHOXoHFaNz/hblpP15WX6em4QvMuV +OH7CuQSeV8mboXkYpxkHwb7hvesNINgQb4h2RVzpzLPsRi6fsGLaTTmzhmA6vvPT +uEgpTAaXRGBG5fZ4yq8Ufm6yZgOzGN2MpyL8+rmRmeubvfWyBJrPKPDQN2jAq/TU +su2qoVu1EC+/2fosYCF+BNhEA+j5nhFrpkFwz2YlYGXem1yXn2d3gypD6dhzL5t9 +liYxtatgyzj5AhK6YNzXblNgVVHsUG2oLVFHV5KKejRxxIMt++VUrYU32ZA4WjB0 +70omn9x5qw9wscTPAS4MIXCDT5W08yyp8CRLbbVNtyquafcmQw/4jjd4qa9W5wbB +PomqGWhpU3R5PZ9gSCLR9GVebKSehAaeicq7nlJGPgoAW6LErIgGpV7um6kQ05TX +hi9KUAtaDVDwt6ho1sJnzV2OJn2XQO5H4UZnnDfj9G1ORRuBUDnBj4kLn/3Fq9aU +5ZND6q7ity8BHU/DsDgybw62A0SA9HfVmACtGwNZEvlggXVVdzyf3M3GA1K6DrgX +ryFQ4WwKPzsuolF5KZ7qMtyMT9h+l1Eqp8H6pex7n3hBTZSZ4NXArtbLSV/qVj0H +ymV4CNRMsQTPbb6fThhEiRb+5l7wORpJx/tj760z7edlWrpJ6P28MGsbnavcJqio +uuu3UcQigu6DW4Tk8fR6BAkS7OFFo84P8QDNksepdHVHh1rNAch7aXwkDd/0tr7w +8dOMXlQrZ+W0QW/XU1X6AQu/VVQoz0bZK9cux/5iSjFnwG8roJ7A/RbJMut6KmOV +P0Xyvt5I9QMYfYJHwGgu+5nUwXhPQhRIZWCX06l6OveT9RYntNtt8u20TMrMHfdD +UsUtwNyngeNnqnOwrzaEFG5gEoTrLRzrWtMREBxdV8RbLzMj/J/IFceOR7W6NfNZ +OzsNWJC1rtux+zH0zkZFWnrVmQS79n3EvDFUIHaa93hArKCgCAFTPwdesNCtAiJx +mUgZ2g+HxDf/giKy4sa004L7flCviQOmPI6179tTZPXOJEXEu1J7w9b5ZP011P8D +LW8/VyND9a3G//u7v1R9oLWE5bUDossYI9QbnKURKqiWY8x+hh2fRpfrSeYw1oKX +Jw5ETuHzsEf553Yi7OR89MqUgEf1bVPHDKG2I7vuJ6IrrjT/wH8StLPy+bhbxnTL +DtZFbcSGIlspqLYUKovSWgbRhN/6iUYdvfBdY95cRPwbplCjpzcfBVRCVr53SAax +3gDIjDc1nj1enWfHRnghKD8MzstfbacHM9kwk+66FUbYOWUM0O2s+Lw5phzl0/7h +3u6oRRVRAA+d00rpm0b5dDRLYDRDRqYph9zb8cP3pt7cCWrulX4kvO1GcXokFzre +ZT4bPj+zMx5MxBtegw+/ZhEGAqrZ3p21DaHmNZE2A6W6oWtaUOU3yHdJmmc9J5yP +Ur83rFrX5SvbnATInXAJ33i/2ZJTEyRE2ekAsdW62ezL+N6jiWdocH042C5yV/mT +ZBPjJd3y7SgkiSz3RpZJQqKSJj7aUFSCKXEUCgGk4DfasGK2vgE5F53soG8QVgZY +CEhWgE4KJMXsJcqnie5UzHnxUFarAWcfr78Px+x88NbHXyrrRfhJte+f0JCEwqB0 +/64JWkt19DbEV2iNADixsmzIpW01UdsbB2B0vMHpC3IZPRNxg4jr5B0ZeYE0eERb +ULBxWxD83rS+eBpd/qyfAaCHj8u2hX2mOSO4aLhe37rd3GCsXnePLuxnLKtwg3XM +XKW5bjCie+yxTkmGRoUF2xX+s87PVOC666U4+UQFOKWXyul3Sy3HiOk+fGuBX59u +zbDX2VEKz4roUsRvhoKxScM7fO6dkPtNUayTsGFt7GXlJS2s/vVO8fsD9Ciec9x3 +ggJUgqK/yoLBjY9gZ4kiRJLVf+s4q8XbNIbnpJw1gbBJ0x+4FkUnKCnNOAS7BiG1 +CmIG0COajvJ6XpRXo0KpkZoxCaKhwC7dJawtLfr1ZvH/qwpPL/T22pbSaJWIOf1A +x5T8ARhJwoGA0MtMSqhQDNSneuRmy3GG6d5gjvjIliu/Wfdab6/YZ1y2Fbc62DJW +vRQnjb9i3K6OwuyM/WSLtMHKvBBb4UXhPhi0EcmJVRvrxEm8/1B3IYJvKGKuobZU +ZOoR4FMT2HlcKf/Ya0Q+jnuzHED7CNM0clsZoSFGI7QGJgZE/SPJtvuWBI8uvOT+ +YEGEJPC3s9MpByV9Pt6KFA== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +jKKARVQzpBjsnhGaDRXS2of402Denlp/BDQ9Ty1CjdBDB11vyj07ShZzg/yf0s46 +4i5BSgiNZFP60ULPBKuj9srpwLgZ+4wnvjoUZO7miHerzd4i2Se96DGrDU1ASNJ1 +2zoboipgmNHRUSy6NhrrTjto32IJYxYYdkc+zABhsGGglKjcw3DhZbYM0P21JD9N +6bHb47pm6JAl2t0zF7TNEzG2xZO30CBLIrxT3iqWtJ+UMI7oP+zOgzEa2Hz9dQfu +T/OoYZ+a8/GBNciE6fy3/VsrK3sm4wMF9rlkKl9YLLHSilEdRHKlmFypuvhVMvfB +eHN3u9By19hM6nPHSv0Rfw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 50592 ) +`pragma protect data_block +4m24W//DII3zKN+0WX7EsAbd2xWEk0dIIOQUygyMQ0Nxgsn9lQUFYqtTqYuJG17v +u02W5k269HUkmsBRurnFPolpAz4iyfTxiBhELJZ+Q1DDU3H/s+DAjrMbnzUDxntW +h7jLk6TnUa2ApvNA2RJPym4fM8On128cWrjeRPx4wIycJb7Dn9xUZp3PhBhgihEf +Km837CEaIgHbbFj3k5v5Ig380L8U3jTnCd8oP3/KjIfb1FA27il+jZ7IbQyWA19l +yIGBzTvoQCUDuHhuD7a/B7bXCsxWlknapRwx+2m/0XPZHVs/ipV7RNge+OzK2825 +nFVpuXASx09tX7xOt0/oMcO3EW6wmNeFKQJE07Ipf5o5G3Pv05wlDs4Yly7eiaL8 +V+hoJEsnCSTzm4Bmu9ntP6B7QNH84ZUO6u6Scmq8cQDnypzoa6NpituwCTFjANLQ +MQmZQ88BTtm6czXEpNZZyrv8C1F6MtwB3c18vtOs9Watgp42sJsIqFGXynHfbsfS +XSEny8RgZCBWtIihBb32qugVjNEXQo0tokiftS+iO3BCXUEx6neXG6xwB1eH4KVW +fsubzGjIkiJcdzh9x3x/ZOz6UvEwQFtrKogvv1kAjBwDMdh5mf0vZrJ7bXbgIA4t +mFLRC2vS1Uvv12SIrLSHH+wbaM1qcKs9XxmP8OHRihV6B0dv4zlyiJRJuHSkDXYw +d+3AKkGfPKeivP3JIITbcYpwYk1BINhQRbJ4U9grT88cCGBPHWXviPTYva8tk49U +WSOk8zP233kI5Xt7cYv+HLV5MtXlrvbX6ZBk/cXLWwQH7AgCJEHyxcUkCT9NZB5F +qMTzrOHGgbRzBv3769aZrYwPDWxLxbbSg2pNS26p/fjbFpaiGwh1h1x8BO3TI5AO ++28TXrN/vBZ1aOYO9N8+CY3lwTNwV5ZECgQk2MZoDMb0IT4iwg6wnizH73qC8aYZ +6CuskLBOMRIJZLO0T/KkYvol70Cnr7p00nQe0PYdY3Mj3qo6Ar0LZqyYBclz9IOf +gae/d9hfuE2IootgxsiXOacoWXiuwSXNCsPTkuznMMk40yXu/w1qv56yU3FakkUW +LivOpimVM6oPPHLTUvQudS/IOSjD0fH5i4yyu/LirWr5+GXi16JEArW22ywX52ji +/XD76yydsVJ5ct3/2CCxl8eaFCHFLDQvFQW/p1s2BMSSJJr+cr+5rlic9i/LEmlb +FibyKFmcYqhNztKRPDQj2//9ScKUucBqSznD3m+yKwYzwYag1y9f7Dq1xRNtfXcX +G14xRGdK0rKFGusnsx77iqBgRYL6UvvNww4Hl3IyOIbn9Dg9NWaR36rAg9qHwos/ +Zk3dl9NKAtKtXfm+SLWBx2wJPd80seY+bmjd/CyQh2gf+oPHWYaZapubfPPUwN3W +AEn7dMzT//buqZPz1QoFrkh5NXCNTRu/hHLLmqImrcuCgDejdakO3SSJV3u3zK+Y +TxnM75sIcaNh+TIxy1GyDGcWwkEOGgsvubR5KcPdpDNThUYbaFVw7XbUTyOG2oOF +jwccSYiuL2T6hdADIyuWJJhiwYYPBRUnTFR7ku49rbjeEFdzJsmLp2mvbDi1iM7F +YjNcEanP6Ex99HOU/aLoJhaudg8FXpqCbjBwId8hil+uNqyqHAs8zjMgEIrY1+0E +RV/CuFGezGrBWeyUEOSFdyTnWiR2yl5fkyHb1EIt11Z4eUcvfNbftayeXtBXIbnx +zUb1Q+HaOo1ZMCBY1R9rvZ8n0wcuJPvegxbYsrwtHrnnqNHb26umoCNGgei9Yi/a +BtzOEB61FwAI6gNuI6frii0ojJxIaiUAk6fcNeiuxQcfUKjuzedipiVrBDGvDyoJ +FEAk9bP0Zga65uFIPvpFLNJT0kOWGisA7X6TGbrjoBHxTm+e28dJCnztSwHfEpdW +BiJJAjxRbNZSSLHl/xfanHdOxMr+oS4MVdhAM9iISzHGcNny0Jd7W9RLOOBG7r/D +45LNd33swnLxW0+G9iMzyY+lsLiZINRfnnkdc268tXYB+sRTT/OU5FTkC06wFdw5 +7XBR0VbopfcvFdiVVblzUuHGho7uWyTFtJra7wId2aC6LLrhiG5VMArIevX/0zYr +Pgh+aLca6K7rGlzbYhfiIfV+n3HxtQzzM2hhmr9aJO/tlEaPoimsL1Ob7gsSCuY/ ++JMl0xsuIhTrvY1UIDgRz9//I0xV2ScqlfzKD+G3MZxTOzyANtJLzdLtDcpg0nZM +HwTZYUxqyismpAvbXmpHJPjDKx+6fDXDQuwlXi4TUbhW7Wjca8OaOJncYR3teNcv +ozIwOorHJC3V/a8VrAXskXUbIhRLELxjd2f7ZqIpHr+Bw+YzL0KlkhBKzJM79Ac0 +QRbYx12dSmDOd/BQg5x4ZFo8ThWmue1+UDeXir2RNxqN1oTLE01DQlusCFtXGNAF +AWuprLAZVSmhht6HqcNagDdcLOKBH+kiI/H0rW0g27GzjNqUXuDl6BbliGI5RnKz +h762ba4MgoKN7LEVjuxBPDQGPMN4FwMdMtn8DCX4PR6V5Py8eiPwk5qmlx6ELZg8 +YxwtfY1efUBUl29X/Zweo2c9C0dXPFlww0rCixVY+lzCRJfuv+qMN8do/R9oQH83 +LpbbH51ZM3e+ZBBf7Dc7gnjCJm9AYPoYpeRxXItPEwxk6BaBMOPNs7jnLSLkHNEr +W07Gk1Z635yl8pTP962y2YJ5zpJ7fcdhwM+LnaephLMkGhRSTMoePNKKdV/2bToJ +MMn9iNC31dWEskE0tXMu7uMAc264lTtwfuidr8q1IifZtIeB6TKKwEjP4HOfTv67 +Vv9NogUAfz9NaS78QEX0zdDTyHpH3zH/lUyGbN/0KaWJeX61Cq3J9JsE5g4V+rZg +4v77YuNULL2ueRI1FbFrkOI3eO7xt8zihGox5wzbrJXyZJ0wVZIFBlDIFmqDqrdV +nVRULdrFeB3PBAy0JihathZw/l/rwdWL+bEcbF80REQ6V75k4wyluGDe2v9xX7ea +MVQsoJRGK28Tbv/qupm9jonoI8hNNv2MMcMryR+VaZEk01/jJnV64jPEQIPz3rwB +cvfmpb2/rcZVoMg3oet4UxGZKoBHE2lBqSPkpdIx/XDF/XjXNGKJUqtDcYcQgSxr +XQoHFQCXd+HVE3EOeGeKQRGvvsWtYK/5dqOq0m0g+BbHCN938lc5Zgp08gBV38Bb +M9aFGj6R38nq6i+RMyALF9lYNhdHWgw3smKNf2woEf5WEQuTb+1fedtqqJFUTyBh +tUXwuxlChVj/3eWVOaafijfbA3laZuGxTR6qyzsdFMowiCozHLjVeF52pXD9g9Ub +9+YH0JDgidw+SiNoxF8ZIV0lN2F6e5utKf1xPU0Px+MSkxaVBtY0NudrarmHVNhs +GGzogTFy55nITmABUbTt1aeObAEDh9GJsxLAHtJ13zcrIQvCKjUfEnIi0EkHSolb +OrScPtvmqHViXThFn0sgZCliuoVfEQZufF+0v0jnB67NRJfR3rlHnzvOkQtfM/u5 +kst1bTbUob8ah+D/e1qent8utuIKmTincf4hNw14CG+daxISUtTtTPwvun1ZK96W +od8aiQyp5Krm2FR5fcD7bErZgam/X1nNNS8lqbwp0I41o7dloDCRpL1tZyqBzfXq +XiTvRLWqgNU4NGkoAHSqS3h3+Ddkrv/C5qPDtmp8Qz+NGgdftoQaQPssJzXWSfKG +g8UW8i/Y0WPv28iXmbJzYgIxJljD4cDv9UzjLZGYJz4bGyI/e7Bl43ZSnCyuvot+ +wxYwpUhu0wTLZIJzE1VAso7DMcgNpTgWeXRP50ELAngbGzfjzGpGQYt5cyId9has +7SzLrt5nbxz8ohifleilFCBxpdGA5k4bqUI8bmGtpDDos0RAVtF+xtFOuhEs1Ief +fGBCPL1c/c7e/aAaEqrL80bou4PjcoqKN/nyjBtY7+wmubrxF2PZPodz6shH7ADG +o74uU7YdhMOWGKQWVGaxIjCnROZnjpS7xtAl4EYz6xI0cLFNj2huG2pn6Bib7k6R +EKPIZ8EaGYFH2l2MbG1Zza3V+oy2zVOhxWfntTemH8LjFEgcW5/fVtYAVNO4D0c6 +2omr+E+MqG2PgJlrhpmpsAo6HtpZBaC/zuHy41m4MLmCYaFxGkgqaLg8cacPisH/ +FM/sx0UkokXMy8/nXKTm7j6CCba8cZtGROJZglAsGWnSv2uouuIFovlS7VHloDEq +X5QyQBniTPxwgkkZeoU6fARB5YzJbSntNfqkimWExwA4GTiZM/wi0etc2a/mPvZl +Yy2GQ6NujlU9/gJm+yi+unBEI9oFwdjDscg5P2qUQRHbVnDQCbSWOXIrUFd5huuo +ekcqcQRFlauzqwvlj1rRvFFp2CyLa1IVs2HH3QTV53YKn2skGyDE0ZC7W/2h9VRu +tAvrgP9aZMbk846awt6EAMyA5um1ksRfx52gk3OL+JV/vHRmz2P8sBE3hUEfs2K8 +4UeiFrALve4v1joLiRaWCrCLQ1V/cvjDzH8naP9WdFHXaPvOJSiFKjJcsm9wr3VZ +DVcLZyjIbZeMoAw/uyLqCiPkumUEltrCcVsuf9Qssw5l4UrVGsBncoDhXHoKdGDw +rHhP+NUTq06U7KDfaNTjoc4kRAoj1Gbky7WY0IA0zKlp05pn3HNssR0en1SDV9Qw +EP4lcYu9ZB0HxaPfIsJvrG44rHOgNPSQmGhPQq4ntcvXZa1GOCVjVU5fSynYRukJ +aHFINWKaiPCY/w369O3lSSKExWya1A+Jv98VRambsuJnkUyJF8Z5W69627vuEHUn +VfYyCZjENzXxKSMXW11+d0F0ev2P71bVGhvJzzyJf3rFTf54HXUoX36ykebuxJ+E +zOqxudOM9QEXNf69i6YRV1FVYOT7TDL7npkPw3DU+uBtbDb3eqb+llKYGC5jWRxd +fxrF7uemDIs1K6Ae7CB5fzCGJ9ob9DtSj/2uilO7cXqmUGwLojtF4T08zNK+ADLe +G4TNJaHrs4vbU0ZjIgaTasWZ+TfQdlUg1K/7qj7+dFEUQwWf96sxA7z+AkBfbMab +YFfJEd+VzAcwoMv7BISkYTSyTkyc4aXw2PUO9J/1uo646lufIlDHJjkuA6kWmyMe +auEJxTofcJd6UhVhbdQSNqnZj+g+lMyZIQ2VCxrh39mUabM5iJ7JCEclrCweiBua +ECaYC0PeFOIdzmKmqd0R/8cbYZli5ZLnqXSzE+vz/BdopPpu29+xgASNqMKzOdPl +EZP7HMekl9OkCyH9QgrtIWB2r1WovgmqozF6tt6JDbkttSIFBAdrdhTMo6fJnOlF +WhXPayo0KzDho/dOAWO6ZFle5TJLXysJLzsvVKOD5KkyGtYhIjSoIswCboz6dWFA +5n/iYbxd4kiR47MXjI/CamRuR+6PAtdBRoH7epJrpb+zSRzsifO2/VJvaTuMyD1Z +yzDWOdHsMaxdoZDKxo4mvFB4EV0WtDgRjRXfNBK+wag85Cy+gCCr7VXlp2qw2HnM +qOOZmj2Cw0xehYI1oLWJ4L/flYtWkZIF9ne991E/EEtnDWybcRDSP8ZzG0LTa6kg +Jn1msYL3y95wxAY8MKZB7Q6TGz14+mVy+qdIR+AWWSsiEbdZTk8caVrk5LPGckRD +8VGZpMBWYarkxDEiclEpqRoXcvgPKq4mjUJO3IGMN80Yi8JjkPd7eA9wrMFnaf9j +hM4TYLS/OWPQmwLggBFZQ1hWJBe3nwvual4dxosQK3xXPuihgKc6fJscob521sI2 +79S+AATaDSnhHawputPsZpIzEULQWzNE2+UvPcES8H7k384Gl3LoqIoyinfzvPHu +7XfSpIJnldNUkP9DTtDtutSzQWIURH4lSItblbcqnPgjPV6XEVG9z9BdUGSn7qZe +jyGE3eMAywA80B3yseDaVgz5sTm0+bp8rehdbXbkOPyQJtR3Xay8t6UkYb0LFeUC +QJU66RTGQ5PXN62jIBWrny/BX5/Kb3mHBTLx5uTArILU+xmAinpQ2TbSsJRXxNrk +ClyW6GO7t1tRr37Ep50uWy4+uYM471+BLH4oz893J8C06who3sExTMQMyx1fwAhI +vk/rus0KtsILJTzn++YEX8LQ/AJ0U2nEGFy09arufWfdDv48WSo+FE+aGhf4mB3m +wecz/FN3aOLe9RaX3Wb/+odpoo+iAokC/x5yaWsw5s5WA8CkutkQYCQMWZRGZ3GN +ok64qejpSggczq8KoWNjiofxcZZmQR462VDEh1uv8uRU3NXFx4+GqGQecm0TAbcQ +kMxhdPL2kCoiGF/TAcdEfe2pZVQy94IezTGB7pPnWkhoKxu3+udQ6t/aCQ5m7DiR +iOpjRs3p/qzG2df8LCpjDFdRmgZqmTkfbQA2aOQ2onrMHAmKyxlCOkmaDd5QB4yv +QA79PJp/TUAktRqnM+yhfGN2u6+y2TJCdP+JUPcYvkCijccYkCoBOMWUVbW8JlmN +rSXGa5nNdQvOU7IGdB2GBkuajxnjo/qqD7l/RfI8xAAhYD7PindaP9VNKb5sd3if +OEcAsFV9iytnayZKGoBuRdsN+TZtMrRhXFUi/zATtUzS+Fu4MSiqlLQECbukGJVi +OfC0seM1s51tWF7d0lZUr17LkEWmUex+olkiuQdN6vcyI9UVhSTiAIKhmVtq2I6U +YZplo8c25ql6nKXyNR+/0ehMblqVC5S3mDb+YjzSgMwaqHNbUaJFMvdeuo/lQ0WN +d5AfNdLzROH9PtO40k57SYirgHG5awoILZS3yKcKLF1WN4ll/Ea9cs9mSBZXwhkA +YqktWKoT5rvH2YiGXbvny2Uy1d7jYpKZPoviOxlZVJvKAM1kLZ3fh5dytkRTSPV9 +iawvoZw+lr8d8u0eZnYnxumBXtmD0szTacCRbt2GTvDrcCkZxH6o0/PivSbIgdpX +GdzLf+7yfrBLsQMT4fXKxrApA6xAJ79XvgEiec+NAE+K9YMMyFcQJIpPgsfcXQrF +cMP0UPL82/UXvEFTwQuKzfcb23tiX/V51L49qUYqNp2AGobTBH6EOFNG5G7m86Zn ++e2loaDdbL9UdKfTexBFsNAJ3vd3E2K/rj2Q+N3K2PYPSXm0QDe7ayMpYt3gjwNQ +TbsDu6zsz1YuYytA+gqdvTgBStHunYTf6aEKYm8x5LAvNh4jG/mnaPh6ikJ+vfdi +XMG3Y/hsakE3uw1Cv80lxTk6Z1EsNtYuBaQcEGrKDfb4yLYU6//zoDXURxYg35uL +UUZ+o9JhgujYf3rQRv43UaxRvPeEYLs1aXBCZmCXeF1wIt4CU9op+Q4Op8xnO/b9 +IydBe6SQt02K4XqDrAkCNjsAOiTMmIWVqk+6s+if5NdewjqHY9Czd/xjxr+YvhIf +yHBLkSNPOb6GUcPGeYkQDdQShMhEq/Lq/F64l/YhZSMf60v3+ouNpPpwU6TAenLK +IJ50OPPhOG1XmHtzBnmNHGek+EWIdsajABXmkt2Qtf0S4H1oxxZxxQaHj+wNejQ3 +2zICiQuVb5L2HGPZ+GIx26gKu0ik4/0XDs+lr4x7Mad7S4aJFOqYbbLL2FQ08OUZ +IQ6Y3OYD5nyV5+QaFm6uU0yvKOxw0BKawnc+/wKU6AazmdXfQsiXOgQOyIszyka0 +ms+vwtl1XOxe+sSO1fXLvzM2SydXCMWA4Cv+2NNsfm3ntQXuq0jb0aYPqrW4z/0J +Pe6A6NPofc8pObK5nhwIZns3u3yTD/GvYxnVB9xUEZSeGRRxXzG9zLyR5tiRG66h +TSy8nfd6tfeSAdmglVfyuovLthQN/2Kx5ofZxFwFtplqcybhFlZowjMKZgvLOemf +eHy26QcrNH4vzikqaONNVlmawI79Nvv7vD/e90EQ2DuR3o9nl1m8KjiZZR5f+wDg +HTdJDcYx39nU+PseSHQKClcPUmSi2owcYV61Rp28xxYUpVRptdDIAltGSKTQSqYG +GeUAGiTN92eOQVOdaWZTV+6kHDuAYkokNWG0ALVO6ju8Qp97UgZceUG0IGqZ7uD1 +n6M8BNePhgHhjsniyWjq9/APNgsGFMl9j/a7iTNad2RUxlJ+xYZAvipUgIyS7Gxj +cMmz2tK37+bvNtGvdmyVHk7RgCuOch8GQKtdJ6QcqvqHRaQwf2JuIG2uskyFQB/0 +v1ng2JjpWpiOU0VhXJpri7XkFeKUItd+dIAQ9SK66TjUbYT8okAEBVNkjTF/B5At +OaEMIqrNhF3pcO4lQKKAAKDYxFBHM/DPZMTFFdBn0f0lPBGVgLMvf34dU4UoF6Ph +dQv1RKosOjk/fztwnZsGZpGR1+jpqo6crW0iJZRvW7yCEx9YQY6PMezcjngxtfRM +CL/nBoWgF8pcn60fvEfuvnOvaO2kFnV6axNPH/NmbnXrOGepdD5RLs4XVE5JIK0d +87ruDpfuzGKk0kO3HtH6EcY9Wg1HEZJTh4YJ+VT6xOX+5WAJIkt7NcVMXxLxpfyv +Zv9zXIFjq9GbHR98P/qzgo7dBWcmvr1gz5rCGn1582ygul+GkjxlSbWmsas8HWp4 +aCwX1W03R9hWMICIYQzu1hclr8U+/VjxyZzm1G33V2Vvjv3r06SpKSo4lN0FPWt5 +9kJt4rq+vZSwBYKGLc2YxVViKCR7/lZVfGLNd1FzoXy6X4OG81EW8V9KTt+RNXkK +VmW0c78yw5hCYykOxC53b6rxu97zTBnJJL/3yz+SColSbg2Ti732zNGuPL6gDelB +816413Js1jDs2zpx6hPV6YdF4j5mN6z4m3+nSShvUtoI5M1k+P2oYVnBuLrHyDNb +Tizng340rJ9U6zffZ2IP7A1cQtTitICOBbv1tG/cUo9qYVlR+H7elWsY2JB0L0Od +M3A155vJwgU/p+QbO7+MgH6WzM6nvhIu6BvkKzsql4y6VU3TYVP+NzHzuNrEmtZz +t8uttfuV/BSVuoITGOSWV+nenGy9MgF78mDeRTeMKnus9f7ebFuKfz8Q2p2uMs9N +RqkNRgaY/RrDeslKu5ajfDRa9/0k5PaLxfj0W26YUKjF1VR0+dGpyirhogAVw/j3 +zurj/UGYQHCFNh+4LPT4c9vYJzo3EOqSdnHyFq+NoI9GA6NJJAF3hbo9FnnpbGya +h172r7OyT1B66joucKMMGWiNKc4zyT53vDURpeQMRE3As3gFzYx2Qh7KfOcp8SeK +CvJKuCRE4T6wEb8lSnsS1Oz0E6j7zC6oYyt9oCu1AT/XCNnGf/v0nzLifIuU2/UI +FVVSM/PKD/1PECPTvr6WxZ31upS2DLsEQYXMBmnFxeol7kbaksZJFFxqHSFpKfai +X1UoL3jJQzuEbFhxFs8ioVnlfOnZ90YdX6AsYvXStyVJGESaEnPQr71ih7hTOssc +GfbP3zB29kArsMsA/dkh8mRtyoGqKxmGmGGsD20rdK/rNt9AybDT8ug8omEioZEq +QnloxFriZt9sUaGMizsE7yj8GdEpCoUZlBNGUE4pyzXKTHARNnVmmeoHOuUhV3co +qd9N2yBhN5Ajq8IRVqLGrB9MRxUg4E18VyXwNxLNY/XqDA7gjbzYw9FkHB5L7m4Y +q38yagawfRKu4sResFqy9nC1i+hT9xoEpvaxjdP+3X6agQJMT5yIJnI7/yUItbY8 +1si1UatwBidXqZFgWkhDpt0c3SjX2dtURb7Jf/pDJbqShMmS/MT9KEBnlxPULAUq +oomvkKTy7xuowGY5xp+Xd6HtItPiUGkjUbNx5iWFBG0HxDrTBNw2ErUDdPN7S/0R +4S9OGJinkZJ0NwHmwy0wPi/bbUAV2FDG9GvuAwtHiQ5QImgrz/MOKVV85IhuA67L +uu+WpOU8n79W1EqwrzvW4m7abD74vTiBBPCDTzPNfEKZBccZE3YMMYGnPM4kyr+K +VnqnP6jap1jPA3bwFTv/ZiINqzAUUMQ71ce0gu0oTxBLtOI3EJGr5c1VGoXFZLSj +5/6OQej6K4+MmzzGDTRBzYDSXEubzVvNoU9uVIXo61XuBJ5A8Zz1QP2QyLMshPmX +GGZFhE+cJ/vdmex5XcR8bLjTjy9RPu0G3nlqieFW14EwlH1m1BfYeIMaYAAWnvgA +yu8/L9a9Pd09fqFGPkrwuxzjlHxyczIksi6U7aeTGYKLWKrorGPfYL53sTFWvRoD +V4g8y/Zi9Ht6sea6wNOu1E50csEwMvUA+LVOSnXLvwKVSGqs1o5VsCdfUQ2YeUuq +68sYaPFIdg4NkySYN/aNKf42rqdZ44dZKXgVKR13p24VjIZgKipNhKAk9AGQ0XM0 +3OYFceNkYpt/hn0Q7n0j59O9lFpG7vTRXresTFVl5ThkM0h5FGB/ihbFEV/kkmlP +kFfPBUsnXQ4YvWURHQm8F70GcN6HdNvd7Og76aHOZS2d/QiiRcFASyh1KOV3byUi +HcxTtXEci7DJkcZOxK+DgfLbQokhqdPKjh2eJl531D/1IjDqHQpJC2XBmLeFSgpu +0TuoU6HF61D0PXGLkK2I3GJi6zbFUjmH+wSeY7bMvVQD64x2D0WtdJnv9WlF2r36 +Ht8mnVPty7kTm9KvaNKVOWC4RVg5fbWvbPGTYzyf1aZmjwsdw2E8I62AXPm6Ucdt ++8P+d8NBjTvdPdyKrFcKPmzNsuWA2N0j9kaZgxPiCvb9a3COOWTWd8etN3t6eHXv +Sdf1LfHCC9ZITQtAyPCB5kKKv49ykbZuNUfvmvnOj4uuX9mIXW45Dw/2TN3Va3A0 +enNd/mbwWnuXvvdHMS6TMz2bgzlr4D9NpsAx8jSQYZPZBbRHvRhtoV36cHjxokUc +roDPTYyhDvNMFjgs018r+WbYPWcccM4YE8f+xKXsXu/iMZ/kJM+q2dTXOeddENiC +lMxIZFucQzkjBsHBEkTnHQHE8ai68HgbTCFY6beIhjw1l/YuZSty/UPG0g0Shb2v +nwq4+1/XhOeFoJbE4/qum9eRg6EkZRrtVuqU0cPfLyM7rQTmGFSVesD10iKzjHxo +RPuzTNN7QAnQs0iBaX0bUBJwkWCE9eQ7eN86kCMWQQ3+ftxhDt8wk9fNO2CYv+mw +Zx4C3/6+ZjkZ/UTI3tMMqv3YeoaoqlQzSZKUWfJV+6e0T0ZabAw2pB4gyBd815g1 +jckrVThLt/4SEoOvhMXq507+d2NIEdDqNGd6US0gHxzw6G8Rmd0K6Hvq0hGHCyZs +2iU6MY91ix+ZeEFDn//l9ycJNTN3Y5dnWUA3PudAP2vrs4DmqE7pZJy4XQqkLD/n +3VqUWfTsJJC7xBIebwf7ouM0Oy8/euQ+JDlgd6q8j0iH5GKgAcHqWtrfs771XSTh +Gv0wQ71uGDar02HWCNivHeI9xTiYl9b2+NR5hVHFubmbYFflzaeS5ukI1IAg1dh3 +jntXj3e/MCe3jc1BiYTJbkqqh/uEe6zzrq6pCCLL8ABUIVkA3UkD+17O371FQLQ6 +HmfFl/a2VnePJbveKHn4xBvkHchixxGvGl9hHNmMsqQQ0Sw4LjoZj14vxj+YDKf2 +CN6a17LzwS060QXn/AylE5DhCCVz2qVIEhyEsE3soOMwT5fd7UHh4MYjrTskoKa+ +3OW7dEZtvDCca3oICIkBTFpHVLVjta5ApW1Y84LD3tuSLAXXn4U/nkP32/sndka4 +QWDnljzogrJywHJfpINcKO1btRsquNZAg52ULyEIJqVaXVd2MtaR/nYbFYbsquGv +6VbiChev4mb0hcETfeXmqNG6Hai7MKmKo2R3fXgm8au3qhKQv4GRdN1jl12Cg3F9 +B4AxhjinN2Nur+VgU8a16LaHvkUCxAvfM66F5aLEaZUvhUG/4xcEN5/W5AZ90LMF +jawtRzOyJa19prQteTsE7adkQwPAWAYPtmoQry5fw4RRkCduhUMJCPmvxfwFMhj3 +iy9R0DgZ/f0QI+Tyho+t1BjkGp5uYiD04H4j2nItEm6639RTETuAFzyTf67C492T +mnujYeGKri+zvH2KSBQooJxX8CUM9BKEclZLxPr7Aak821+kLPMkhBNH/1+ypafk +KPIQDbNBII7WIFlG4gdsoRxXDUH8QG0nrUMVywsRiFToZmU4DMOtPe2kIAFESxMb +TtCSTGowQgaKKZ2daUVc6BrJuv6zjUx6b0Z3vo2I0uy4qNxkKfIWr+hQaJIF9J5V +XCT/le2+M3Zgl0PnvlIzMI9cyxSGJO3E/6FM9dohQOEgqPp3WFk7u2it0zX/qCga +4skF5EeRe3P/ChXfCLWrkifSh8MQfvH3B25ZNgFNNxqMGo4lezdhszhdxe/Q3w+b +qG4c2ih3ZnGgphueR8RzkCMmdtI9roodXq9MOwaTqKzF0Io0+bAwJ4U93WLR8GP1 +10DFs2Zq6A8OYj2JksUFlN1Kbk0H5UDR837M4Wejw2WgMsiUx3zNyTM3zLYS6lgJ +VaHlZraSe19KADN1mN3ZMEkbWNptnXv9cQYYBg1OJd2GtLVpj+PeQ302GTudZDLV +l4J3D1wRWEuAKZtz7Y2GAYSp5Z/udbZqUYs7U/K5QM/8QW5PnvlslGN6Gp6p4ui+ +xr95DIJixyfLhjfHNNTe9CqTYeZOmgbQ22Miqs0WltC5SPCIXZztEz2Dopw7g9Mr +dVnqdFNEcTjZi8ot1xfVHegi0X0cdkCcmSsJoaaJlnag4aBuF4KmrtjtQIGC0caD +Ku/JAvY/40AZ6F+kHg8wAplAv+AisJ4cS3VqhBg504ui2rFKyRGHH6G0CZWTpkBT +WqFeAKNkv18Asu52EJMk7PRRPvlzQEp+izYpwRSAuON0V7v7uS7x/xMFG41E/SY9 +diL5QMHfcpeBMcX3b9upmXkqItdb5bcPvgCaHaXCotmqHfC3yLe76yJKHN5LFnuE +a9NeOR0I0yhR32qOdTAIp1blZqj6R9i3uXSNNGO41xQiQme6onNS62Fn7iTGsESS +VWQ3Yqcu3qFRu2HSlEWhhI2OsRAeOu0t7XV3gX4jL3b7wyiC91p1UyQs6ebwAfUq +/6x7EzsFdOfCNBj2861aXRy44dibVxzKruI1lm6Mmek6JtbG45m6xF1ac9kbxXPW +k0pGyWDRh5MdK1sT21Dt/zCKP8ORsuPKV/bJHR5MtHZg53hHvJWqQc+KH7uRCs4p +D+EiKpqPt8fTDcqXdGXiUtH0lz8Ds5iuHJsAuaf1IxjOuQBoiokRhtP77ZRdRBqF +eNAJIYl4533puTiQopO/g4g3NvljeXY+o4NlXFbtcZeyIiRHYDqBXge8cnybwwpE +8H5eABhREH9M2MjLQWhgBt6JR0k0N2PtVCY1mGmIZEVMCDZqRRZEuXRbmYhPKm++ ++DgGJal9ZD+ix9Goc1Q/TJiEdt7oRFTz6faC+AXpf7afy2mpK7qI2585kQ4n1LOG +M/fKEpGtkMxz//02ZIxoCxnNlwM56pDh+JQOZtQXOw+3OwxcSREHorbbXe3S+J5b +14QD2ad+V661J6PXmVA3RTUWzD/6HOuXrPx/z66X5ZGzFHQpayWyWSiz5IxUp67m +fvAecYaXbntMMpo6FhvMLQwKAjzwzuzD+Zn74K8yXfoiIzFQt9E6t0FKJWY/Zzuz +l0l5/wjl4QPuCq+87IrQK364REZycIBUm+D1G31XaTJ/FjiW3o67TvRJ+Nfknt11 +81uQ37g3GJ8yThnkTBpmtpdr6YbtmWvY4Wyqinxp9mtJya48cMtNeDl++xPc1i9w +MNR/EB1sbKCkyquhi5GwtW/VnF1xdhGAdS/5MfArhX1zSkS/JcDqWLRLJVpL5o6+ +cH/h0PUa/rcM5XHRhZGbW7aZI8CkI0NbfaG6ZVCU3nP0yAsjxWyAhOze5SeohIkX +QK/f1FBeNQuezyf7IUfBD11jkydcB4Wmd8eL6sNRZcqCYEnIIM3HrXN7eUZM6sx+ +rLyabEi5RJYcTzE2J5rwvsPffP2J2fGtECY+c8roEi6/g4Xv4XGqLtrTHxe74uw5 +C7SbQN2b1yOpm2yf7LQf6+b8wa9xDSZGteoLZs1HxtUw8BWxRfEyacH17mym/+NG +D0Pi9iH0HNXX9H30frmS96B6PbhNMaA8cKt0BH7wcaBf5TlvQRaxX2LEJyQqv6Iz +Et6+krLyfZ+X+La4m0rRcOK7GG7OrJB6Axokd2KtjvOD2/SVDrXKnOeGkFONrDdG +mk/AtDbxOtklYDqUomGqf8o0ySsyK1EQhpNkxN8G4fVCNHj9/s1/X3t8+/SyOUqU +jgNcndY9a3yr67+Ru6oHrgWOg42NErqqwaEUAhL8QtcPQIAeytU3mRro+T5JRVmM +JsAGuwBlcUAumjmyoEygEpoOGzT340dvS1288/v8V+ImB2mj9sVb49x/MffJZs+L +DRsRP8eRLbzB7y7HW0N/IeGfyHrLiquNTfG4kPKddj6UfoGiKuHe8P5Ho6mZFD0D +s9+odNM+kWIRvQ4rpY92P/g3vZOdb/d6cjWtYEoDSX9a7LrSYqXt8vu0r8vEJAcV +u7Bsfaxyg21FpboafEKVWpa7O1fEbHVjHnbOnQh4QtZl3WEhxkiCdtJTbUW+vP5c +XMRyntorZnAgoL2SFlZj5fLsfVrHH9cKieN2k1cDsBjzfC/YQUl2+oCXtdiq/oXg +7s2VAxtbur6HxruM/PQqg7Vi+mmC2y435kyWuNs892LkdU57VDrw5W6ucsvGSImz +PWLqWeVGxw0k1iilLjomnIGMlWyRAiHBlrVv8CIiBSTwNh96Y+WUxxs+NIwc4+/a +IHTvPtpl4G/GqXbIOwTUfgYd1zAnQhOx1YKoA2aIy1xc9MWHM0gyBnNBBcrX5gap +eMTJ9aNVIMk3SlqANjuD9piIXLjyJi7qEKUWymAQ0LxUH4oExFSl12iUQqP3Oj1v +wRAoB5lIox27XlYvdvi+SGAM+bB9FKPZUTjtqfg0qkHKfNjBMPzjvRg++f2YKgxk +Ya1+Y1ub6CUdibjZyhcO4xVL39fjZ5nQXe/xoJ6ETGs1eT30Zcxf3RgltHXeFiaZ +vYX6+wr/g6RzEQQGVQbCVys1xoQ0w2YiLhEsiYWC9tQZXPZildbW0uKsVfB8ornq +DirXffqmvY3pczhU0ezQQTtNV12mtIb2x4r52NA5cg1cO6y3DYIMX0Z9dWdrt2Pj +2bl2nBxNFRvaajMxgx6Yf4kTRp9m/IT47SHzLtT1Tq8lei5bodWh4DenjoI6rjMj +QtyrSeeTs3XmqM+6omACMJWgsSQH0omH0rlRskg7jrEdThG0tBUrhXn11Q8rmO0z +XSAQTtUgLISTeevDzMpRtJehwdehnNQlRjuMf3K3a0QOIqKygy5Ml8gP3LQpHBLv +dQq4kdvfSy7DXYYtDRoqGMmrKNROfX1yYouaAvRSzko7j8sVjW0sDps8fHs8Vqt5 +xPc5qnBMV3NdoTAAnXq355GYBw3FTdqJDIBGmjf5hN/y82wQbMDN27jpE2PeYXX3 +D4qd2/WlO953BSYFSa5LpWt/3KkA0DzAstOGpx+G6TCo3r6qryzKOUtr6EX28hVQ +rE+y2xv0kpDAxL8Cx1+notkc7uxQ9dY7dv/+Cc8kQ6z8ckFgtEGiF4XnOfN7HmxD +JVwMuet37raKA49ZWOMm7ZGUNLyNp74l3cvjP27tkresAogj2nggdUL2VtUzdoPF +Jxj3dVBDD2uuY3Mr+IcNgOtIOq7r/tM7OZXK+PaqycnkADAD9RUPQjs3qYUKptkT +156pDqAy1cnmWAGJ7KHD7H/TV8z/Eg0QserbRoiPUPVicorOKUypQKs0X9dpanIe +oFIo4Jy947Doy6CJF8aqvS5mwAEb6WaPWGoln8T9EXjMezW10NDNC0u1Pkor6bhx +rnJ6w7FbenkJOxwh/k9yIwGZXs7akPEsFZjBBawByUSQtU9ivLA4PpLPRVJy6B9I +BgtEtGHL/mmA7Y7/AOCX0KAnwGKFSJLzSOoukGhvGExhQb8SdORhYQbMEePdeNSw +CX7AAiN9Usmfxz/NbdM8LoZiXTag5szuNk+YvtClfQzUqIPDUVM4XgVIch0XouTO +pjt+ZxGhGIdA72whAlDjDFURPXkxkmfcJvqOIRkshd+hUl4ERV1dQX3euAHRetPk +ipOWp2ybbH2CfXUCBBdI7mIeWIpm3L/SHLZLDvWp2OQ6/bZDfjFl09IpVvwCpRQU +8JJ9WDT0WyRurf54XL1yCS7oZdM49FllE3ud9ZHn35LUki4zxx967KGj00MYE+Ir +KEzSMgU+t/trgYaa8BiZOzfiLRh/zc/kpb2DdvGpxJT6cjorPgy8p12qrkKOne3d +SLsLRE7PobUha0che0SNVRiNHdpf0v4/bmhx20UDoYlQlkdl5SUZA49ISfndMgEu +41L9vS6wwx5aEboUpSkJE4VIYX9abjK9H3/qod1U4Fv7MA8f4McwjVnzFFWt0RR1 +5IECP/AurxUVu5f6mxBSgsVbZWjyU+Hboig/Y0fcRvd4Xcj4xTlq3IC+lvhLg6P2 +7xOr/99mBRiOyj3Ichm1EJKPBN95Lz9QV2u98Z4vxzNeC+d09quz5ivgL07Xj87u +NzOnx0cIKSoFWRjGf9wOuj3sAtgrOE4Ppzj2KAz01PtSuJNqAyfdj3cyvamMDYhx +ZVbJ+5V8/+J0I++IKcb7HgbqwW0Qds5L/LYAsQxolsmWSwWzuulASza5iwIwC0pL +nSGnKtU4iwpqIZAhEhqBNTfgt4pC81yqJAlj9htnqc1mI6IuIJHktG/l3q2qY/pb +IqA3+MEygsnwi83aHgD8Z5k6IzuzEu/Hz+vgonTOvHaORlBC3hV6RawfHzGBxEA7 +hiy9I6Pg4gASVdeUSsbLfjduyPo+Y3K/60dF13T4oiTji3SZa16EUa052RCVSXHe +qTacfPZsrwXqLRaglZkEhEXkyEiJAV3SOFb0AYuBTq7xsvc5vWMpON1y7NjjuEvI +SeDiqWwi0ll6h+HfRDq55I1F/tGLU9vA1dbi2UraOQZelRZcvzgELbp4gVtSeeOf +UgFvg72W0vMmeR6tITPM9ODKoGfgakjpAM7UoakF8Wf+ejZ+kTWKmsdW3cwZbhpG +qE/b3SNJ+f2dziFxEpXhnAJ6B6MM4HF2dw1a/beV+RkhjByo3gHwDlQs8fmlaMIK +31X1tWh1OYjtxaRCEKQg5zuvGvfkvPnbTt7n5eKl39yzaBYUm3soLX1KIMzcdapa +F+xTCqD2cEiRnO2iwjCCto7QDn8Nj/XBEylnyYdo1QLnnw7d9ZkjHS0mFdTE10Sk +rZEvPaIQvfG4CQLDC6tYYR5jzz8rk4sVowL+lYwu99dt/vDe815taiHssrpY30Vd +TiGZwWtJbqZQu8h8jO1mRSwCt0zmMZVj8cfx1fjZ0Onkws3TwDmmziDRjPCHJwYp +yAca0GKo75y9kriCdZgCsmW38Fe5806IKhoiFUVek4SuX9zafvdTPMBYtMqEudNu +k4aan7OO9Pm7t2fWIOQefUVub6EwIHE9de1qOZatyDB7WHm4z/QTtvxH/xsO3kY5 +VB6+mKAmOn2E/qMXcrswqjoNNKpWFMTH9DhhmvktzOwviPGcDrzo1x2wL895dFLY +6f862zJstqCxrV8j1yWc07vJtGx/FvsATqv12ZXUjHBgoShq0JAFBkqCh0Oq2VVx +6O95Yi1m2NjEGYqCQX4jMLLgotbg3c1hT+LrInyyQaQeG151iB4drNGc5wpA24dr +3zPkIRsPvD84CrC3+caggeWPtHypYKhNUo0hWlZVVdbyIOX3aX7MoPUa2IIIJQwM +aT8Tgd4OnOmShqgh3p+LZXKtjXkOZxSl9aLePWgTMpl3i1ripwBDx5HNmEjaz+fs +Gu7RbP/e/hO8ccdF+WFgk4+O7aKs7N/TEuYGG/lezpKaWFiKB16H282HRFsIyfZh +dMVpX9Y6gLHhQerPbkIVEBCIfzg9oz+baaaJF3ib3ZviTWBmxv16hH9plF25ycBc +7BN52ro5G7L61EMv/fU/3j+Qf2Yn10SHhGb9DWBx5zG2BpZ/bxsSR5XNZtPTTFD9 +IAVNjcFjT5GAZ1DZNTrPeYKSxMzdcDdwY82RjV84mtSh4cTvo8nERGnlt6Wy5Ilz +uHy4sVoOGZg6aO3KGnHVMIhLlhUShAWs9HWlyDN8tFnBCOsj/VcVrapMD0zcfnHF +G3lly7q2aPVEDkEqQJjy06YsNb9+4w//7G5lOTqNjXmWpwA/UwlJXuaKlV/SVYvN +9RLBI5wvQ60ahbm/A+SnZVKEQzoyfEO8HrTzdGiFttHQ5ojEwaqNllzQ5bhppNVH +CPaDcvuhsJqGV67uhTIRfK3T+NVsqqAv/pGVYME0DmkpAEQfeI+viVHStgGaKbap +flvXaQ0HPp9vwNnfNNEtjHaCy8ktKD8+tGJtsqjHdKP3Iasvc4iyF220pQGKZLAh +8dxqSsBrCHGOkOhaz0lR13E4iGktz8dVomUIJKXZCvBH3y2qTBId9N1az8wfWz2B +D5Ycg+3JygxRjWyBqaWxQgyDdgrMUoKPLRsX9H/aoSERrOublKtNhmFVROX3EMMO +ywkaRHLf8BImpD0mivNfRquUI274Hn3v+kUUBTbowCuq070tihNcAlkQ8rIleF1b +yEGF8i/xCRISH/qwjei457HFDMzfKRSYdeHHW44d0skCaZRvbOTMivFQNu/dKwmc +6VeOgoRo1BNogZTlmfRtJo55ROY3ax2eMeOdZHMD0/gSSKKN36oN/R8iJAOOBTsd +NLJGin/a/QZB4hwwsz6CIb/gfCeH+aXRkk2RwzbhFCyyza/k8miIbA9iklFNaJwa +pVhHvSHrgIgioA7YUycBMfwlLzPlShjJYL4gKHDX1SMA90JC53FURKGsXRFEPBCx +E/gBrXVqfAcSOefmXCUxyUv7ptMXal12Am3NZWr0n2HpqL3qw46mP4s+OIAcBBoZ +V4REsjg6wt18bt6L+n6GJM1W2ewObr0QuOSO8b4NZ5G0sG7h2aWZ//gX9qJ4To/3 +J+1ABx7iGOxkkStltNPKUOXGYf0l1CPFDkFyGXL4c8TZJ8/8JXIwwqGiPceYgGJa +Mm+5Q94dlRvYtvibnlgnVYMXzq1ZH84xTfItpt07xXz07OuNSFfM9qTf/GEB29bW +as/DJ0tim+gIXjPoorGG/O6TSoI1dqifNsJaz9OAYrLAZE8RHKf/f6cILJfAJK24 +FlQub4DgtrnWkiwWpTUjgCDcG1oNqaqmL9+qqzlR8MjRRPDHU1waJiYs8qOIW4vw +oA+o5DCBnJlk+ExOvYrFyU77DdFcHkNuUSITGbOJKJsLDoMP2Lztvb83650zdjQR +CyBVs1CeuU5RfPjlnhTNv0w6CeL8mkgJQRsJ5i/ACnbl03Kuw/ewv16N7ttEzFyO +2CPO+zaKNo8opXxSuSNhpD7+OlTHJMXWhuoGA8xWrcy17OC7KJ3Ips7IfI8NGlPz +YLPGoLFFSDz0E7zdR3RKqM94hHGdpkrm586jtzxViiGmY5fVAmbUDy5WsLLC3YUo +C6nKOqswrhUo0Q3fEwDnorpKG4l0VBaWUmek59r5WZZi75XMn7fDqh1CwXF380uZ +wWigg4YPMFWkHH7msBglIfK3/Pi65/kE7CgnzYrWV0aRaAov/Dc/Til/cGu1L9WN +pbFBUsaP8LGroNZ6F1lMSQFDAv/MZihdrjYCUWDtDAPZeLuLI6jzKiOhUO0T/YBa +mD0ebXdRan0P/+qvrvKexYho0JgDkTQrFG/LqTMrrVQN+hZJHotFFJ3MsBJnhxdE +diW+Rs5gHHEzkekgqj8gEZuLc/DckjeIa92FaDBK82omshgyjf8wGtdcRoOwo2HH +QpKpXG1LxGsWJ2yX8mpVD2kNaK3en/gIjEJAQlZf9Ck6U7dEXgclGKlFxKi58B6Z +vndOKdDs0KgQCJsm9z35dTKaz2vY1hfKOWgo+uSy/Y5T8cfjjyyI5Ul8wxeqgwWd +wZIWVSiczztEBe50BU0kpf4/kb9DwJ4DsuAHr1fmJCyN+FjcY2P6dc4eFHVr+lAa +vvmyoVJQaujq+gOWltf+/zzl4sF3C+0VA9BnDzuNiOJwnK2pId0uh4rCERFMzDCS +haBJXxt1MaiCgr0Ic/bR7hKixdTDWwD+rFQOJSGhLdV/ewYhnAFCAcld7Qv4qmQm +M99xUiXZ+xo2ECZ/G3KlqG2VQ4aEuOpB/tIlHGTiXZ9tk3G0WVP1DvVKN9+nW2hy +WxfKEfs3gI4bNwBILiH2e7LG4iW/1Z1daAR2S2h/ZiHwNRCsB1GtrVd4cJ08/yas +Lv8VmWhZiW4logghyVO1se494OCLeT96E2y7A/hBE3bDt8798tMIwxTMrewlZdUR +NGss0zSoEbt0PYnYNd8YZEjLILTUcR1kVsitc5YXGRdO1HRqE/S22JdOOhTavSBp +kEFE/ai0J9ol9GGu679BXddVp5QSsaCc6UbAgx0U5FTN71ZHt0ME/8cOavfXqTrv +6MKceHgiUqJaCsNd0+L5iRk0f8ci2zVa0E15QHb89Wc7EGIazw0Un5qdy54f1t/A +DqwVff0u/A3FUX2jiUQjDxtUOWctSnJxFvMmCII3YZcv79fC6SAE542p8x+izI8u +EXjXyrJQG+aFeDWKIyeeafdtwYxBM+Lf8taT+ddpujQh0q5/lhtxC2spr8aNH5Re +yPSHm3dKzfqpb3PD/SuPyAuKyFu9V8/73zl4TRQ1w3CivwlTw7voY3/7pN7LW7TC +xRG2qdUK3YimsFE1ndRrrDl/LK6CO2ldnffOUWOuskgsnbhgXnbqo3hajuf8zB3O +q7DMTFAnDHtoxGtbTyTXx1QycEt2JPtjpvQEOJ7b8nc1dTv3CuwTDR1s/kWFjQkd +xgWaYrZ0xl24YCYeWx/al2E0UMgxBMjwO1zOVlrJ99ioAO3abuBsU7Rw+H0z4VAV +7pRU+nFnHv8cgaZ48vtl3lDyj6t09iOXXej4NSqr4qODmh8YBldwYskHNDW4PMHP +ezU9244GLz8k8uAyvxsUNmkpZ6KKau8H0Z/c99iqLGaey8mOfhVbSLf9AOdck1oM +49+DToNSSzrlNfgeEcTkZNI8X5GMYnwJKDrrhJwWKHxNRko2Qhzle7qswIRv+TAA +blzaxl+RuHUb0mqC5F+Yb8cTbbFNNHI4ejtjW6d4ql4Y3ki6tVoxIe89+dMRY4tZ +/oV0JfsAiXagPVCD+ijuv/XWDFmIHTN4PCUHz/+gidUgtV0rJjtg7/Ely3CYvZB3 +wfYM6EiEBvQ4F+vLM249ISkWquHgCJ+ckaExE+4Jg9QL6Cl1Co9ebivT1oah24ac +WxQv0e0nRPaPN+NC+KPmRsX86U8lmVQxT0ZrARQ4/QzrPVh2KXKJ8Au3NuyHuXRz +vP+CmzgrFn5r1jPN19QzRYtXRecnV4kBBEC0kJ2HVrc0xnXSYnBVBBtrGCWu9UTw +aPkwjaRhiF0fA4fV1o0thMqlAjReD+LQAMgObDMweGOKSUyZAbzF/gMODkDzErfn +QBE2f5ljLusFC99Rc2T7UYzxEYLZ4LROFpKT8ETuNNK3CFSY9wuoJqsRbOh/Oegp +l26J5AQFGVKyxfrf+lP+AyzA3DMB+23Tmua6CPUubXOVXLQS5QsJDqzOiwf/7nYj +WAj+vqkjKGI/sK07vtFO7UZCIQ91jdGrzXZme4OOeasLXbbpleGhDvQTzVVQ6Bq1 +kUTmHb2Si7uBQt7iyeGtIwukUSZ20BbQHiQmauvTVwGnL1wF3Alruw5vNnu+aVL1 +KosuEjU6xb6SqdO8O+Ybe5F5Wafi13mLBE08rVyjXzDTusafIuwbMlQ0IHDTBakk +3QrEZv5g5ggNsKp5uahJ2Uy34B2B20WdTveyi7mVrvmiWrkl35MbPW9Bwf+qQ2f5 +wur24eQSgaMcteb+trS2tyYdj9l/AV/BzYVlmim1LmklUJJoLv9HxV9sFG3ksKhM +eN4/69i0gJcXY16o//rR/hDAOEFJfDhR+0W6G9bLdWxb92SISTa35DLqGZzCjLK/ +ulM8gUqRvginqn/dMkVyI8S9UzBVl58iPkGMY9Ntu+tAknX2I05hjpBJ8cBc8Y/3 +IFZZX3s3Z4u+eLKQlQUxZtYwo169AaFdhYB+WqFcTW3L78d5Pjm/EkCT81gxIFps +eGEYp+PuN0bxgZY+sGXVT0O7vWTOEhur51u8z088NGuDnZC2iCXuvA9a7GNnjfh5 +p2oj0IY8ZqZXigC3987UGyDMHsEoGhi75BENzKdyxoOF+iq98VeaZuU9fgll+Z5Y +ASvUtCEprZ/CZ0oHdVDcUbxoST/LBeoyD88rNaLabq+55iK1Q5iXvBFk4i0RpuKJ +9ZURhEt0lE+hdRxtGd+9qxUGMRIfyQx1eBB/+UDrilaYrbHvDyujSSq94skmEYZP +IG/sk9Y0n4gkGQxK1zPe0yDALl9wt9WzIfGrX4Rcz3v6ohyzcoe0zj46mnlJvGP2 ++vLh1LYdXzC5LUfW52EYW4JcPCVDMhK6KsH5TC144rTQUlHjgwoKRNv8kBoVguA/ +ur0Vimf2Nb1/V3Z5jKupVQO2F6HcNjvcJx7gRhb+Z+Fs0n4cabU+kMzp5reJaarM +IkThBz3EmxXX5FCsS1r7ATwKxXUcX0ry5YAYUeoR3HSrRYY64z0lCkHJuUzwydBU +Nbw1V/DF8+cOSHMfRgmsscAN3P2oCe5CGMnz4lPFgUZqGx+r4KPpM+hgdbmY8Q21 +oRx3OwU0vToJnhJfAna+zFWyUamoInV34d+Cg+0bs8NLVUMcEmGClF6xcgaFo1wP +qRi7WhsxbqhkFpTi19FRpOwkYrjuj/hOi5eVP6GSNX9zPLYlqFvwi5FBAVEF7QtA +MNRkf3GNvmadb7JDchn9Egv4YThEInP09uOMkofSSr6AUUyxLIuyE/FKbjQLeVAz +RaHFh2MSndwhICi0qbk9EpM/gjnq3f5jiT6opfRTj/ZKEtz7m0y7I7RZKwXhZ+hd +f0xp3SbRAwJ3DH16I0FqBoRUxJwGHeXel08Hns5lUWfCxwOzPYV+QLa2TJTiY9xy +ClUT5zrpcW2yf8th+vkneefi3LGvQjXXDod0zyze+Cp7cgR3vLJ1hg2e1qA0tnAl +gWPdNHbywMA9odCs5rUYyQj9Y7DJlSURu33ip0hwoq2gi+nCiOgeJaSGI2d8tJse +gpdf/jPiOHSgbKLGJBZ6ob0X/dT64UdnXCdUis5vZWbkAS+rZErWW56vBAjyimhB +nVImb4OPUT46XCM2Xp6gYnDFEmJIopoTNds2JR/tbJZfXFA82UO5w0YIxuO9epIG +ppIKgb5ZrlEjEiu3nzBDEzcHWjVqS+fFLyr7OIFc8cWjQd70ypQqv44mZ1qryMBm +uTrNi78Qfsr6GvN9bSnleiMiZ4zLGh1mEXTB0QR5rtRv3XHsi7kr+mRMKi+AjTzT +AieTpsuSrIjbVZQtca1r0QrHUuT1XmWw0NzGhBpqY7WfybMqjORXyLke/WnXZGWM +o+23zQmOJqqsiBBinUz6mvQ+ApT/IiqTcyprvZRpnSO34NftBonF2ydknx+3pdtQ +nqxcUKNC3Vi394g4GZlDQz2kVbgQqWC08g49VxXcdL1nJ8u5pqacYeZ3FHN18iVy +FLnVN3Vn9vdV16I0vlenK48Ii8nShTdmfjKaGCcSGsKab8PTAQ3pU0fuGkjERPkU +jnYCmJQu208Nslx6FQus3jwMa+HymjvnXh8xYn8BsFHsK3QmBIKo30Q7Rsv4QZaM +szi+Bneh80O+qXiw27xEMS+osdoyD6Mxx9sKJa18XLBr5lh8Lc5faVztOrNDDtIU +h8C4blTWtoc6FVleyWu7zVvgPTPcw3j8Afo6xRRJ/buhP5Xf0AtzG08Fdxq+CnET +vSTkBXZnVeKLvHXKQN4pvjB330omXCRonVf4tIqw+ghw0RxCOT9oE9fpPsT/YWOV +cNwRMTecuz75tx2dm7pxNuuaWoZMFT/qIHygTlLmURxEC4gRszJ+xvt/bYd28Vll +3TFjm2CelbTM4sFoEGeaKXnOSwsN+GtuzzQ13htvXk7LrUH2l46vnsGT9QSpEEie +GoNvepeBYyIs43Oyde7yvJcbyKn9p4woW1XabUYBloQ1s7bRBXoXAPTDOGRTNdGf +eNt4ACbjfNGJDVYIXmIeVXXExNbdP0ZfzZh+cBvFBtCHHVcbmlpO2xFhD8Pbl9HA +4Yb/Ny9VtU9fcJ6UI6SYCJYkzwpQ2HAV1lbuwDGUcFmDGO0lHWiDmfN2wnrn9bd5 +Z/YfU72BtLwFAsBy0nVblhDKJ+L4lnoJxHJSxk0lSYR2nmIv9F6dkHT9fFVytQDO +AmN51iYA9U1SidnLE9rucV9L/tZWMd20zp8yd6w3LNAq8eo22umHn/ee6Q2at7RH +ccZIe84XOy/bOTPRvI0qZH5fe1cxMHa+ImABvXI0rUXwpFtZap4zN7nUF5OtNnWw +mV1fbULp2ZsEELqbwiVSq0QDsGfywhJaI+xsWsl/hduKnyUVxb38IDj8hqtuxn33 +daqh1Ls3sNvUMrJ+UcA1eLAIgVpoNX7EXkYXGUBVHd8GN3n/BTs31mR7Ses8HRtS +nMsTLE4L2bjADEte24H6IUP94ZQ/yFcf/2RHYWdLLvjzr+jN8XsNf3CiaEePhwvg +lY/uKNffyCKEhG3HDW4PhguFNI71rQu1pMDz6enBcQhQQwC1o/XYJgrH+CxU596+ +MQ09zxnkMnzEC14noApGiL3LqRVgf6oGJJYssiRXM+VMGPYj8b0iCtzmU+UlfltW +Bljbkgu9gRMrd3zp4XIMAoZtEZvGNZKhx+wEzlgjzQ6rh1GhXW7S569L37KNT6r1 +eW4n+vmfyJWp1YE6SYoqzAfKRm6R7/Oaw5ls8lznZh3OVP5JyNUC0N8uJA3rlsF7 +P+84mAfETPtHzSozCTFz+5+WwmmEwaf8F7KFZCr104eHIVo7N4hJ6iNQpTBwWkm9 +PTJb+B8J5sYw0oset4jkOH+Kz1aLLwWUvdtZEGFgKDNp7Db+oXRPF/NbrYibo1oS +AIWH8VgywgRvmhSuO6SFp3omluAik7tCs4cqNPGTW6HG3Q2iJLMcOq5LZAqRfm6y +2Mpdasot7GQPXwO/0QLO8zBit+mF/hF3AP+P1ozmcft4vfZnXpgI7lQOoOSFCReK +cneGDxHKfyP3Lv+xjXr33vvf1bs/fBHfJnI6JD5CVJIaLo9sf5Jd//A9iXi6p+/p +i1We7KXWEkpZgANBXfLgTLjgal5tA3kRbppLyVONVki4NKzf4ZQ01P5d2lEzdUJC +lNln8H/K+MsLH9ljrUOmpGQ1z+sPKO6aEmVet0C0yTzoQyan+ZGWm66OemGzj83j +4NV19Xkgy9gP26wtNHJAYqhfrWiV5NnVb3/oaEZiSxoRHysnw8dJMJNQby7Oz9Ed +zDTz36QKxDRpI7H+mUxmqG7TlkRX02MwNvlw6t7+fcZ0dZFJo74gd/zQ0MoOhkFH +ax9XbAnJhyZrlIX5zEq4NNi2+VUs/URKWwOYSGNueLfcXZ9tLFXe8EINJ8lh7B5H +ksfFn+PmvO2o4WQ6ap6BlFzHZO/5AJnRTpmRCGl1Su54ByVyJUlhdvJi3xI9hu6K +V6BAhJmm4I67P5qCSsiHwt/HCw4UYN6vF5k1V78CqTboT9aQ6ZT5S/QnSFCOa65e +NS0sNzcRbSFFsEapwhgIP8IwKsweagnDpU/Xb70r3Hbvs0YGs63NNHfzU1qk0ew4 +u20YUqhyB+GXelisyfILRioJ7gGu5yFLJMIeqxmBk78vJB4YTwrVHuapHtwPWHcJ +GQaMIrpfB0QDFriikxpir5mdft+pyh16YdXDIJLIWU8VzI0g/IPkO4ZNLa+iLeax +0s61PURkOJPeGu5axzOIsobLU3HJHMkDgO7LFMOjAyqa98zogK1CLX32tJEgy0Xg +B9s5dXv7KmPcgDNj4LqghXhPFfC2P6I4+FPTN+h9VuUMKfAuFhSRCd2mYELlLVJq +LPP6CP3hZnwLS8MDM0kQTLowJ6j0frGwsiZhmuoCt9dyra6zn2NP92MzMMS6WKBh +QD6OJWUPOBSdgOYeyla0mQq2XJgxnEJ0wlvBZrm3RWyyzYfHbqDNiem2tngByeNY +VXm5alTX/6eAQ9CeZ+FOp2lLdO6FA0u1PfFunCMnTLvoTGJIyP2PqZiPrM8WTGAG +5qw/Mvx3r7pMrf8ks81Sy9sDJ6PorCEYhr4856JJijngdx9lRmDKfCDurdJs106C +5pmhISrsEB67U3s7eUVwe2zTq9gpIhywytL0Na68sUpOzzX61QDHrr436j6PT4I/ +FlreQvbvlUlaL7uZ69OwsagCOpE349o/NghfMg89HctgQS1S6u0j8Xbb+/R33RfE +Oej2YEqZEmSCvfh0mtIf+SzbbOZDV0z+q2lYxqEYfOw9P60Vm57i9Z+ArY+0/hcH +sv9CGimigcWZcYvCLnNuQbIQ3BFDg8AjpDwpz0WkCcIi/zyYfVCf+n7pFzktP4PC +f4DNnjDLjU3tvJFxEeQrWdn7faSKk3hjEgymmwe+CwmSRFHan5LMHbCdbWCJ3t2D +maS99k3ELqUkW0AhpiFgM1JQ7K6mOGrA7w9TmPhfgdmfGjOQX7EEIYXVD5h7uc6J +2VYGjUDNafH3qogzaz/nDNx2VDdhdfhbjWCLvC7Xgn5VkqvuzNOupdl0Da5lHf08 +NEDa6t16xIE8H/ge1ACh2TT9xGOJ2uWlVnSiKlCOZhB+Hoizu3SNMKoXp/y7y+0v +T3mUlTnvALQi9hg3P3cl0s1mB65wjrVI6qM2GJz5gMBCakZ7HDCAupsn9TSaw6L/ +F0cjnTndzSC76+Nb1D4R+CKQPr2TcgZgpp+S9LpvA6U/gAtKJuLqknjppvHf0stG +SfQ3HACKKL94RVGCtYaYyE/ikJUKm7Pzt3ZYODnzOAsi0/7ZgFOnw8HctOe95uea +z9kqBbw+dZ1XB+todhRyKMxT4bsepgjLBFy1La6jAZ6UDD8IvUYzNjecEIwlm23y +SKHKIjHarIgnmH1mn7uneTjt/7H8ENYXZ5LWCubV0nmTgr8nDQn/9ZinNq+GgFHw +REFl7qdMjm9kq71Ny/FiEiKp3HwRWjmDscERtwMiObGvkqLwViKCfpA40BkZWccG +Uumkf5wLsfCEImESW2LBBxtyN+sb/ti3UcvFXHOUwG7Gi4NEghwP3Q6Fd7F3AreP +Bl6D5C9P4/sachCmXkz1lc52VzNebZ9LBeXbb6yuT7BQP2ZY8w8TA+uvHK7opxPg +ICP5GssaxJCGJ9ijlClj6V5WzAPcLUS5yAHkelzLzssT3lgFUZQ3rJHtuYxb31j0 +gOKglLcERC5TVix5CN0CFScKSsXVLboab2iYPdkcyecYzreQkwrvowA3docq5et8 +VVOeLLYlNmGQH6idnd1ABW0tY6rDd0/GKmhDe3I0A8Ei/spBmVHKxM2h4AMJj0+5 +vFBSZjmXZNmQCCvn106W6LKPQ+6q6jHC0kZdGEMlDIJ1JtrOebg+msh2ozYHZYfc +LA/Secuxie5IOI9g+Eh1G8VAYSQmTPfhJnP+Ki9gd9vYptXkIqZNCGEd6rc5txrn +AZYOsC1K3M9/tEI0zXlgI/jZB09//T0MkRfoZgmVtf664cwgjd6PcWYtn7ceF6Bf +Lz6AwnQNb6r8dcc2fwq4N5x9/XtyyxeDbTLTEtCHStEjvZt2iMEg7s2Y73r7DVpf +KVW7aD/URvVwe7lIKdgJo3bExeCzV3ZMLqA2dn2AqWvXvvLLTKD8jsTAGM80URzE +U5HOfinHOuY18lRemCzijbYQEONLXI6ZPGxl5pjpZ4F2Qimfm5b7qSxVCDOASjiw +8T1O7aZCJ0ruyzL+1w5G02PofB8+6bMjrqWLln8RIixTojfH+6VS1elZiFenJMCA +2vAPzOkez3Eh8cOeHn/RJYqFEEYLeDYF48fG2WSlUu950vn848OKe1rmSjfemfPn +fVQk1tbYdLmjTtRYVXM13gkrCnfu9kpQUbTR6OBI4/V9jhrb5VBxfBna0gVpXDPX +MtjFT4XQdhAIose2C5Y0K3KqtGHvslF0PdVyYRaRscUSvW909KXXT9BX6X6mFVER +M7EXV1kpRLeQwPWz40fpXnY5IKjspVm3J4cYE7WSd4UeRuOfk1fIO4MWtKfH/MNh +PqmJddwh7+ilGslnl06iIOPU0uipY8lFaTnfBIsZbP2+lAc5ZKqPWoyNayANnxfp +JkcPE3z+MRSTAqx1S9LIgGnJeh9xxSnK8a0+C46BNT55uO1QEiQ0RW7V/VUA/Uh4 +/buPrhKC4JASVdrf3u0rzCABjcjHz3lXs5cE3N9+IYqifMpCSqtnI7/C/1WShAPu +/61tvUyZgBtvBi0bO0VxQGYoi47CwkOPvMKV8GWba7+y0G47fwWayVzAW4LU/gSs +UHvy7HUHZvWN18ZmibkpfGqo7p0oTh51rNDaRCLzhFGJYnvaKB3f5cZwDE7EiS+l +KDHixQZ3b5by9A8kWGb/z/uX0ANYaIEFr+uFlyTp9APhh9yjKFVGCPklOuwUWxqW +uTqBj7wJKCc9ENWMzxXmcCDvIaNMQxHNmY28HqmZ1ID33WMwVWzE4zACVioJ4dp/ +GMh8yTQidRQa0Yszbgoaw98ldQvMfDFjC2sIzNObwiiSYnkB6oFA36a/Yq0ajnx9 +RpGRXGhsolUDyCKVGegeUqrwN9D/IvQvPqXMcILX5ca/kuRT6VS1NRpyUs1W0qSs +n9CKlnH6bSPz6BngGyHvt1x4FOuFzpFFXOVnjKposMvuNLeQAECta6XPdEhVGLr2 +TKeOs5wCL7dVqn15msPufVEC1YtKJ9SFlFR2/8ADtGz2p/f24TF2h4Omii3HYbJ/ +7RG+zKtaHqORTYJQptq3a9ypxRYeii2muVR4ehXonUKhCnaXYzgy9sbrDlr3SpbA +b2jgDFdpeyWCtceSUNPhpVEn6XVumM84yNraf5su8A0TZRGS+LUlnQsN1VT4ei5w +tL7VmcaR3FNpI9xXXzYAHTVXxJkRUQcP95H/pjwcbnq3SNW81fTDjEwUu2S+42QU +xoNVV0F4U86qCwIhVExYc13e19ghp/tdR7RRminDpu3jBkF76eq7EC4tvrmZhhkU +vme55krgYZ9BZHQcoVVuAoMNhybmHF3Q66eA0Fs/EgXESsIOaZRCKWsroDTuGgX6 +ymdpOShHoRD/1ZZoAg0czaarT8w1bgJ9c779JMzNaLLNgLv5VmDuZX+g28cYw26R +Kqm3ztFtykajvY/G5QwB0SXysvPKMnSOgAOguHwzVNUgOpJ4o7mj6Nt9r+1rXkr/ +Pq/9OP+ZLMjv/thtL0NOpXg6wkBPvgFzlj/Bk/pHM9ITT4UvRIxWtEryxkc87Yit +lAV1IMwsXMWBvhiM2+JOxed9xhXXPxrwJjK+VZ3M981TyzBcD4SKmVI7/6G+A/px +lZM5xN2klc2I0h5Z/WJlVCl61KDIPztrhsRSZHvEOfdOTdXDE/UHjkGQk6xSy0gA +gVlIy4M3UXV5Qbau/jGpJWcMXegYrJ74KUnThfpxB720KUd65qEujOAx9J0aP3q+ +diQlsGz6Zpopcp6Wi6HJxyuKYuRZ1ZbXIu+JPvV41JTzOT0K22x0qSk9kWViwdLC +i6xK/RmmHEyvsnKgk5ylcQqjyoFkRDv+j4CEoe+MMjM8bhAd/+nSCkxKPSsJHr0c +wYE3QVXePJzv7KRsVXlZrYyRVR6pC60N6JVeSlYYtDzun/vxkQsTEG8BLCu2wz7m +Zif9vkPZj+IYOZe97zOIbTCD6phKcQhTJfr3dPtH9o48tZIUqL2otURPgW+PnQ02 +0eg9EjDbhtYfDCeYXMWxlZ4fXJXk9xgCTdjUZpVclV3X8EI71lxbjwXSB6l2ne/F +1/DQ6DHU1scbihN9mYw3/OPF3hFnUtiYcVOu2OKEox0sCOY6KRpWWeWitACYguVL +a1TylZboYruY47w9txVUsOi8esfgnZmHl4W+dh6ZmTuh5IdqODaTBUmN+pOK3eKC +FIxAKihwzzqPAChnOGe0anQpe1iUfbx64vCOZ79mWQqpj8bdTq/gXo/fcaYUn4DZ +zshWHVmsuBPJ3WVaSWTOdlVmB2qywprOzTRk0SIiPo8xYQAMBD6evM+Qqv0OJMKI +EMfJxZp+Sap18yqaz2lMVGcC75Q+pxHniYH7JLv44db84nbqAJcGFAE1e7v6YsHi +0CGeYmuJB1MSkd4TWLJGPx+7aKNbYOBNo6j7E7ctMjsnBBhYaT0n8E1r0hcJ59KD +/jcpAI7aTo7/FgQyd8iw7yWCz7u6OAgEqmbbFv4JDOwM1wuHCjmQ+7ZStz1cR3Du +HmvD+cqzpDOtrtR5c9Qa5+ok6hPRHtIXzBIgL+PF8BUR/r5ylDDsRicAbmPS54kw +xO/5QsZsWO6YnDh6KuF4n285Glf53aEwVaKSSKf9ZysBmkHnhG8EXa1KLO66b81k +Eh0LbKSyt2kDwkVHg8sKJwmCvAsWJ+gQZAeArNZnNb4jgv96CJ2Uem2lM8o4lR9T +kcAfBJTNHoM5Xu7s6BPxE9JFQMp6D39NHD//Me+N6QkaxlofcNAr/aO/GepUSGGT +kyrEIIrUHCV+3wg4Sa0t7AMzqtlWvGx6smgbUtGrCj/aJxpCLHNC3kvaLM6angJq +QH3gWIi8vutnEBpzGsyorjqpUZMR5hDFFxpsBbjqKG0rIHZfzE4tikCgmoScidyR +HzNBcFmyPly0ZFLrf0WgXEDNeG8PQfPlX9GWjA2paF01JmR87CRNLQMfQJt3v+Bf +j+ePd843zw9JzuAN58KbDx6Mrb+7cGSIkVlaDlAxD/H85PhXe8er2J1BOTh+NrVX +wdB7+AtcS/CLIyxbW8SOaDXOusnayoLuIrrnoBXqAq6QR7bpXXMjNpYBVSo1SZ+V +zp/dXvGp1QqdR1pb0BIvzqO8ZwJwsyxCvfesrA56jjRWBecVzCKbB++NCTxYNqsG +Y84JO2mrs7+ubEKW7t9Ea0YGV7I8fCXU0/GA5Yrzmx1akuVIrjqPa7jfYiq2J4NI +C/PbBeQRW+DtrMCU/aECIltpZ3GLWKe26ulmj2/G/QSv3EhaI/y+AcbIL3oVLhEw +56L871vJ8dZao0n3CdqAtNSXKrqzBseKVs6WI6hTcWFrouodgNrKHsLOJWHEeQcU +vL3d4YIYR6kl/LKPO6kbPz4ehvmbhFtco8o3SqXizNXszrxnBo4DNfYdSv+0PuxN +CxheRdOIj4eBZmI7civfh4p8X/yroy/k+NqlLLHkpUw4Q4G48insns/7W1LzHkNH +dKr/tGtZgdwOwZ/pEsPGbrc6NcuQUxcLIfDeo3M9Us3BVUwEu5exYWrlYNT+tVBR +HJEYqbzYcUVy2agyvjYNcKwTNMWqGohPOQG3AejFD/JM+Q0r+5s4QdcJiNA2I3dB +Fat04d0Z8avkY9Ki8MtCrGomaVdVUVWHfaU96dQvi0yuxzunHKqkF/dkfJyZfyn1 +cEEFpSiyNc90O5qnJoeKOBdbK+vGm8lBLglEae1jczn2Esc0NhrdrP4E7saj4l86 +SiNZ4AJ5tTjeEHHcJ0kFXK93G4MgTQ4H/ngmMvDi1XieePflV1reZlHXSElHYSBJ +wvwxcpJ4bazCYECT7i/j5fhvfI+pGd5Vl0AsAADNbtkkWqb2PSLv9x82hd+bucT8 +xGB+sFhuD7ZNNpsXU0ckPir8zGZnDT0uzBOw+5B1BhLgx9SXlaAZUZiMZNtKDTEB +qNLaP91xIlhT3f+wYK7rrtnmUOI0lENgtPP9k/rrIj3Sqb3ChoOtAXmIVV4ssycw +QUD3w0TKP5SYOESBYYFEN8cWyg0pFK9dFy18CxSGDCOmlPg7aQdd8jmwZD14/TQp +3erzRYiO2HOox46i3e1CoDTUSh/Z4iQEYynd59XKsYA33AXkySiMManotK3IQwxq +QoMii2Fdx661ZkgVIEn+Y9oc15tp4ubep/Hc8ZaucK029eIqMyebKED6ozo2l8ZQ +jS+/lGOPvGZvApLK9Cif54LUAHfDaYvtL29O+tae9w4vSVdmeIc6tECPHldlBz0D +hvCRs7ciZlwAbxN1suD+3R3L/8ZAA9PufL6yr6ppzuBIXA5zfHLgh39Hm1gfcQH9 +7xiuiObdNthOLpcohBAZOZgrLfReUkl0ojIMw1YPHVTswN1g2xDLvG/lcZCrO7zq +lAp81VcJOwFc4r/Oe+6GoWBltpxl/laN1LJuhsT1BJe7cny7aBtKi0s/h7rbsH8v +68rIk3RIyBMhYTU39IcGKAoEMwB+H/amk0XOFE4K7HfA3wE+iX9BJdbXhk1fVNig +u2iT0xgiUzq4XKYAh5+uxg6DRW1el8Rh98QRpxXkc12pvJ9QPOjhkNAW6AYp0fog +wnpW7JUN8XXOsVNWsUwB8c3ZCs7ClM/9G6oMuHvI9HAVsrjNKRRXVslQ1OW/BIUi +IcI52D+VaniJv1k2/FjpgBEaKsr3CB242yzZhWGPcjgLPx4LCyopLq4/J0IECbVk +2USn3UmbsMVahJrjvHfXZAHByAuSFx1kOupycKZZRWjIbHWKYN4WLxHyDsUY+uLv +/YKkc0DEXH8s6NPYup9gGAlyhejFFKHZoVQ2F/6j5M5hqkFqL4J9sLARCVVicCkp +/HbToC8bFK7lnVKtQ1Bjni8/EZAeNeuzEjoLBk5lglFhpY79IO5P7XnoPqWAQZNY +9B16yHLwUDCKSlH5HrzIGkRFbPNoz+tmRw65ajOdyUizF+dH1dghl9An5nekCqCN +QS6lYGZ9mIttofdyBod96pBqrlC4r5un5oOJMlaKH9p2EAHFLx/yuYZ+0LpyxgvH +e9CxCMvpXqLsN9vh54CeocfRL2rvzqwoP0DI6Yhxo4XQsh7ancSQHB/czBw0QmxU +QujLqXrbukt0fVDJ84CCR+7v41ATDdgae/rfYOLxFCSkgW+Xb1dnFS17+TslRHos +D8aFyJWb59At8KYuW6qteaCBdBlXvWGDoS3SR8ZggNyXDS+t/XMxLGYfy1XKmoBg +3cEwW7oxYaayu+BlHirEZ1ezOFaMeY6AYr8TGlBr4v6QB7/akuCGhpFtXUN4e04T +R43BqkpUC2CBBr02Rm/7TgH40rMqScdLzwWO0butgD62fqhXNhbyeL57vkhlKt2M +lg+WYhEtuAvn5C1tqLSB+NUskCpe6LIhZXNACheBujstLe6JBdkL6mtHzyrZxnZQ +H/zG1tgl0f72Dt/QGJ5hZrTLWxk5MSHgZFVNEOe/i0n8KKRQWHBvHJE5lAqSaD4X +gnIrERkkkppYJuoO25mNx0PXop3Xt6/guE7u5zr9mr/XMn0sfsKupnl50eBmXxon +tyNrc9xSy1sbuGQrAruzghkZj4uT2ojwM0t7qh7xXNgV/Ykuig0o+gEKu0XPlbx6 +lGXIILg/LAbPqY3fREEyaUHHAiuGxYHc9telMSN1tzdhJlzdrKo4NE5gACZUmFAf +2i+CjfrA/PtKi4ZP4WgkVqwxLG9jk/Sd0Lb4UgaQ2ZXhExIIOQGgwYUPQlIUUzy1 +vNqSo/qwjQIqAaDGIzsNv7XF7dWOs1hOZt5FvgP8sKbIRkJicGjrXsegragNPYhh +xw7Zfnwtrgi0mdJqNTvFI5V9KswQWvdLltqqyyU9FuqsM3Rax1yx3SWplrwmtNjv +ZyK4fedFPwBnYiR+rzoifhIJS3afuj7G2mtGEXcM+yE7BOJrJF3nZWoFuWfDojic +inDdXSsnaiXiqomtMc3tIJiK0p1qUjPnHeYP6o7hmAs+B924iM8BVjDHxLCteu1x +itH1lK+SGOdqDfyywV9Niz+V3shxbX0kH/eT5Y58eImJR+VqnpYCWWqTkaK4yAFE +UbmcyF+n6mzI8UzMZTbBSNOy4M2tcRpTJIeIFvGHXKEx6vM/U+peWgPkiA4l1L6+ +C+qo/PD9fyAugFniJ7zJL2jILWnNWRKq92ksZi+3h4ocX/XaTA2qJjMsuUn878F7 ++7kF+/HV2aiuYxu7n5Pjn3d8Pd3AfQQKknhAQqsFLt3WV+5JMUTyBFLvHOUo0D9t +LgFUs6hPdizA3Eyk6V5RJQ/StYqBLQAbkPjbib+9SgrTar/v0Twmvqcwm+vBudvZ +5yA0KLq+BSfVzUMBQ8eCnIO/Fr+zfJG5v+iuSLInv7WaFQOdSa9sl9asq4pFJjKT ++GxwbPGHGHytu4pcSQM/nQ1Vn5BeUDd3CmdO7sRw5fTiEKMp6FNnGtbaEpvU4HXe +z0Q3e0V5ZNkjGsvOU7KUffA4xKxZxH0AZjWmp2k2NeIvutveXAHlCGNATOK1zA+8 +IRl5ASkhybpK96htV/1sZXuj2+vy4sbtEv2BsnzMhRSPJVlpOJJMSjYZk8dk+gtw +uAN36jYPLZ7fog1mgxqnfHY0V453129OG1eCQy1Ye7R7c7s4KpvrD61D2zrPSg4S +U/mXTWe2+W31Q2L+wmndSszG1Y6ikgo+CCbcFNCKLQ10i+vlnJoMptJ3WbiTHY9b +pw60rag4tKauhsB7VcGLXsVCia0ylgoAEp7LLWP5FsKCnvxOvw0/14U6BBZqPix0 +7m/jMmGv+3Dt/si08FosrEoCXkASIYxJQYFvdOBhD7cFAOj8vzcZlkxGehAK0SYN +BMTw5gBdrrTkPazXC0Lh8Vfedy1ln5CUWEalf4ZDoGvmArxl0kVPPJAmgC8qV/Xe +b/tVIVCmoB4nWCtv9J25B4BDyKT3Tz42PsWJvQQbtOotGgCn9BGw8phqlJquCnR7 +KJRTl8MgPNdvaHi1uKAs1anXZbH5uk742b5qADX66gmu9VIOux0o5x2m8SU8cZDb +GYggvmEpa1G9eTkOxYAO3PLhICfa4tYKQ2AbWxxiqb7QTIQcHnrb9Ou2rPln88ve +RqsjOjg30A+WdOyzozIPfg7xRSvj/59b0qeLpMN1gYCgqE2Sx5pngmh0YJGcgp92 +V/8Ex7Gz76OdiZxEnHfAkQdlRyQgwhnvM1v/u4bEIeumNAgbB0Q71tf2XZXRi6kP +r9BF6AYEfWDbBCykgjqFnCAw3dOBWh8rzOBxVJUl7vgtmTb88c16g/Boz6Yo47rV +YG6QagPWhXIRnAnR9EVesGVSA17fLFsNIALi28CfzuzPcTYilJYhApyCooW75af3 +hc2slgWPIfd2iAcxn9FDWQV+s+OVHdO3NGURh8zaaKSr8T6fMf9lwg58XI8wVVUx +zDAy2ipzXctpDAq/3WezEwZGDIU2lnlwsaOdRUH75fVrxRK9PPuZIOAe5Va0Tleq +FRx+iL40jy3Bl+cfkulhxKxgGVUxpPygXPXmBObJFNj7M8r+9eTHGQJirmfJ7vuM +/aX10AiwM4+eMavYX+0qnR9mJOPNCbpSv8XRbGWtiDDhyJALb97gbhaV1ZHHObzJ +Fj2BMnoEcshQV/dKz7eRbWi1RTS+wGvqe2Lypgh09tWwGfgqJXRgWWbKMlX4aCEp +SLcp01JrgTcdL5H5N8mqJpH74Eakb5B4mEbZ5FamWF3BNCazJ5w7HQWgoubLfYgZ +qpuft6AkkjTzcdXQvhJ/OkQWu5Ku83PYVBlxa9bNX/BL+gkzRzIJH5mYUjKGVwBQ +zwodkCLwgtwCrjRgj4+8KrIq0awh37FB4uM6+m9eXNhO0gORR8dbFdJ/Lqpc/whC ++4MVhdfK/ayEgYA7yrsJvR3D5y3Wxcw4MyUJnJk29ZtNe05gLAOs//n3w8C4o3Pk +5ZKnMmHliS1JUP9WqVzef+nSI0kh44CTvx+OP0Z+Vm2xikrnXFLb7p/Cua7njMZP +Lce8wtoziJXpEpPBrHGM/VswWDZ335XA+mE9qghVYRNSHj0iX3oIHEaKDTrUCN3v +golAo1gC6SMVkkOsda8f8M8fwbAYpGBLV+8RCpX6NzJA7e1XSAFCHR+5Ow6sTaSa +3kjQwt6YJJZdllux/l/59sCUUyGSC96JgOyRC2gI6GAdZyQ5wS59x/mZ3ENLS0M3 +w7i0H5OVuTRPBIMlcbAJfV+ZmHWBY2KvUCBEK8JxIZXnmjoedfzhyV7/mwHTrokH +rsldSHk/3qtyoFnnIKqjfdd+D8vXKVWcGT+RpM3LGTZtU2v0FhVxwGzm9XMF8lek +3WmYHYmRSmp51AvB0j4gQCGipIX92qrriW6fvCeeoL5aFR9Sy7kWg6kWwi2p1RPk +KvIRHyXM2zqvNbeTHW/clYeD5HvxiXQvfB6IhaUJGqfiCc9bh8rc/MWaEwq5QcVv +SVhOZKbqsyGKl/d+WTHhs8H230a3AVfhiNnaFqgY9Qne0OimOZS8Ips490PxSAWw +fkIMZbvfYJ/HmwzGwj9C07Jau7hLSYE4HDOzoQAffEGqdspOVgeoHYkoS8B3UJW/ +4y374b/U/hh24kC+4C+A95auo0s3I8i7on9VFImNYSNwKZUDAhu0bGdbc83sGXbd +bza/WxCgpj4ZatWX95P463ThRAtsPztUp0mO/ntSdtxJKpf/Jpxd3xzOzZBtAL9e +Z/cwyzQER7JasY8NijFddGnTgH5mMhA+y6gxGlyjTPWRLeR7l62lutQz91m+Nl6a +LLeX++TOfYZHs1shWY31lI2+M6BONmsFx3ysrLu3wpcGvBw3VcDkBp4ya/cQvLiu +3RdNChY5m3dyZzkj23w0pwDVcRXsfRoKXcJmnr0qSSivJO4ZFLIWxYxYfQa6u6AD +R4pgnutlyIltIIMo1HdKE1CGQMLXHv0OYqhP8vl30goNDdfOq/IJcU4czjotipcl +8ACYJ6FpPK2dWrsdAGXw3aZC/YB/uOSwwgLYGUGZnpZr+VrElu6fGt3fchNkg6Yh +gjmYxL5zSlUEtgY2hDXDUapZ6rbRSR1UMIYCrUSAfoMOQNqQWk2YPJVuKW36ciVu +UIdDQPJXOURMqeOYSe0VfP1DkQeToll+qerjkMlXAlQt66FSHVd5mjORiehePMxk +du1Ola46wMZzS/dKNVdI5mQYB6JmbiA9fE7QcUCdVPh7vZlA7KBM1UMc+DzUpav7 +UAxyw4KcU1i6RAA1iqUukCuZNRtuhDqONBreOf3apaO3YgUb3qlCL2RaCqLrNOGh +4/2kdriTIkHm6YEUqH98YR/mPWCixZThXLK+snJUEMIv6pk+BuCKHGgLyDTLKvK7 +8uTW4I8AXqeSdkGwPDiW8oTNp4ECJ5sFVLtAYZa/LRB9QTHqcdmkI4m0rKR52MGd +AY4k5l4iX7JafS0vCUqfixJ9RqHjZYvYf5x08P8hTWpJVn1/ku/oZGMpXY5YkrKz +VQ6kFGFq//sraEbhyFheaRlk3mHVSjKV9i+lYxsIh0+q+8LqaRM4N14EoNgDnJm5 +yB2A5olpq1aeM3z17UeMt92zD7s/fK84q6wLgp1IATiTEXvwOR0vpujnwM2Dd8K3 +/MsavOSQ4D5C5Ojrj6GwzTaxtO6Q4UowDNi2X+DcbiOBdZ3hIiTpOOeJSLBWknjZ +3Z6UxHHuA2PtOzNgsTvWnR+0JlhicNazfUecpO7Ktj0B3aqy7byCle7im00pS28m +fmio4e+ezXxRhUraR6F7UH8jJDUZL2KZ9FZlkNOrSs9htzOSk6QxIuukmSHhzGcj +Y7aVihD11901GhVgP2qIk8u+eei5pLsbbblk5hpwsnA45ADKSAdYBlmsd9uNmm2j +54MKrBxXixYYPbPdHKHR38jAa4L5jl2hvjlBVURmYMaJVb1s/tyxM4E4hPKcex4q +Em9YE2ae6TjwSbsDdlKvL21zGnTfnXO87P/7uD7uBdl1mCTTstbHE8RFjgIRv/ZO +EP9v4UmJSTNtimC5pahG2UEbeqHWCP7mWoLMS2RDyTZIUbZfZ9asqwQyP1pUs6Nt +M2QC8nCIWzs39otY7nG8HjRv0nLTHXV7BEYyh/ZTKlLUdaQue8QItnxo4lWjABwb +vhF9BUsaIbjeeEXsjwDGjLxGOFmUaJMM4M+GRAVXiF2k6XQR63ra2DerWVN9HX7z +EIdKJs74+mB3g6NSaHhPBYB+h34zcnisKQV4PXm1+xo9nFKlaTU/MixAytzoanLW +w+HOr1P7ddPuu6g/DWDb4UKlqZXFdPuhxTj7ZIZVcDn3+hd5bHiEstCTqRkfzCRG +lWo7HCpx/sfgqkr3zWFQzZqgBp4yvzqdAZ/APEvMgfPTr4fMCM1JbRH8GLyy/uvv +/OJ01EPKE6+NIcucU2kp7RBDYalM9CjauaYsy9LcVhFsnc9PaaPXp6fFA8wcM2qe +UyEsxy82oDgHgzeUJYvA6cB1Q1Q0FXNgjC6gBKyJ6s3YfEljNGnFzvITKYA/DIyN +TUD2LDwuGnEbAc2+xrrccb3Wr6QfdMseh2FaN2nAsJoDsdxSLe9NVjrRHHkOSf25 +V95vaHpJheKYg3JjlAeegmb4XYb2oBRkTYKxFELyBl7hyLFZV1W/WWxh2SY2FU8+ +6dhMMR+lxlK8KDHX5a2aPcs77oeo3zpNdElHJ2aMYajY8x4TxhOLBvIkDlYqBUrr +3OJnu9hWNGm87XPiNKaSUyIlFKpcnHTQFxDhUbwF3gOZx/kYBU9AVTmhWcvZzZen +whIfzPojzxYiq5oJqxai/dKJI83U0Bytg0YPvZkp89fihWDF4qFALRhNC+9o6VRf +/btP0jcuzpKTC+wkVBmVo+AjCbyWeasoGL1IDnsxGpNOaJxwJuTAU2kmJrx6oTt/ +qAOWRjMtFhnHk7VkBPPuyj1+sFryfexpsdstF9QCGPtikiYbxhh376KzR1diKXBD +xW03nLLHLvSn4YPT9iuiRn9GN/w1Gql1IDXSxnapFwAjkxODMS5kixn8kzPGw9KI +r6IFiJLDM7zDQY7Ac+vYlkOrhTvfv6uybsUBIckVaTTuJXke300ytOWY4+WxKUKo +lH3+Y7SfPiSMjKRGRLV1agq2hZMBOI0GuvP8hA3fIs4pervSrTzCcogY80W15gB2 +0IWuTZ2d6uJ6sLKI8OPOFAXGJl+YyBtoGeql1yFyS90ilEhD6TbX45fDPSBG8NXt +Bp99oXH0JX4KnlWbZT+bfTl51J0L0K+woN63KbZ2TacL3NMjFfzSj7lzqTOqf22n +NGisBQt0zSUo2sHoXFSPhU6mwONB8LI4O+AAQV8YC2g0QLNh0nVL8M+hnG9EUCB7 +BDYKmvsfA27BJa6TpYlnm6wKp8i2/wG5Rnt0K03trqs8pZIo/nsEFHUCzJwcSnq2 +Q+5gJWicDbPB2CgguND3jBSCP4VWJfrMb9we2U46/OP2/1FVBeNQLL/IiF6xiAqK +8KdfP/RIOfvh0FgownhOOAwZLgpQQ/VQ+MjsLOLw50MgDeTc1x4+5zLuXfJziigS +KA5hrp12JOgkCYEj5mNVxiLcmWI5+zVGyoHyxT9C/e/BhMn7sAi7DSjgMnbOyjIo +Us1qDaPthCtHzIydf928sXSX1QXO8SHZ2pJ8wqXGBmAsrmQyn7HwapmlTgvxpgKl +7q2bgJXqG18Nxzb1hHFi64VZ3aoQHZbigEoxJ6a/eXEetmUJWRrnEHHn3E92eBwl +FLRZHx4jOJbtZmP4bgf9nSt5qpGuW2pBSoO83sKKMt5YvjbYWViQbLOursPEudCO +vHZvT87FnaV3SUbt6WCMtgxku3MJezRtWbSxQtycME8Q4kJxKH//Ej+8RSnARotm +VogX62F3kUuUzYEc+2x+oHBqBMEeFxKNqfbJ5RUHrmdWNwjRLjvGH+W6ccRgaTWz +j2tp4L1bbYrUPuI4rTzgdmu5InbvPe6q+P5UpNp6OmS9B3dFPNsav1eS9iKRMYkc +ttPNtJ3xqqqNQsf06UR0zbaeZad/gpCPLnsDJBX0PiRQ+MyGZSIRZSW3KOl+xIS6 +UB+z8GLHxaeHvbpE9R2NB615/BojFqS7hItBztkXQfjr5hZGkzg2j3ulDpD7IKMN +DfRnzPxZ5GqW8TqnOPyDN1Ndu9R57W/FMe4NnXofEqe0TO7Y1WpVdLN+7Pm/6tbe +acCT6hOkqzO9jKuU+Ioci7RQIqPB8CsUplbs0Hfdug1lS+uEdXhO/CVj4WbRhtUs +tFUUxPLEcMRAVXOtTZ+4fRhulNnb4wN/vb/PnNVkSnZKRyCYVlYijrCKs3CFjLAn +UR1Q3cmRgT69pQXhn0v1fBxEso3xAmWQb7xEJYPN72DZpGSKVhHpnVRkEpR0eX1e +caU965BD3Yt8VQmlTr836m311wCpXLu6YVdelf0aESxXdHKBthE7XRyjLxTrYLJ2 +M+L6enRgQeAGj4fINXKpYv75odB6uV4oRvgmcAcZGuqkIseNb+Giz2ku3YvQb4Id +vNkgYAosqETF8jSBil7e+y+B21mmUXHqvYIsslGOHLRJI8Mf7LilE9Yh/ndDJL3J +Rh6sK0h9THzU3vXxA2+BND+Hz6Ks/7HnfSlMp3+BImMDF/mH9QZw8SSAdHkbx/rD +KqeT/pqwdzInUK2+z9d0vLQAAkVql3/SLtnDSXfnWy5zVdI0GovO8zuNYxcMsULL +ykej1XU+7MFPh9tfFj0Q2tTNn32FMji3k+vfCDa7N3U82LoJUb5GYpqgqC5+gkHa +/QU4PM5cE4foLRIlsY19N8Y5ge4VX1HLMlKqFhygmYYHlRnRppZAdIj5Bbo/nY4u ++wO1bfOO4Yz3CI4AJbfnQ/OlI7wpOOKA4jlXTfRdx7EFB/Vv19jxvdAdnJsGtjO4 +1Am27OUvPosrjnaJoR103mc9GHNkC3/K/8Rf/PC3Rg9nwRnFDHttGz6wijDDIBkX +bwcwGOMqu/aXDPuaDZN4E9h8288t+AhIfddlZDhN1lZ42hPHyZeAtjmnETkMpw4j +5aLRag0ICBCwMzxDj+l759nJmj19ip1UrrRF2nRU3ksW0J0cF5vzFfDdvLATT+Cj +1LFpQfHWMRg6s9OW93e3qEVSyLrDSWodmOMH1EwyQ03TP6SkWvGEKYJRiK6wN91J +cV+efsM407I3036ChZtAAGmhsAx6sA9DbyDNKBeMRzRZO6CMx6YLmiqQLkXbexCQ +rUyX1IgWw3ffGu5tsxIv+q8xdLr9rcHi5rrPf+IwAvXBwUfhG8U/+KBm6gsdRe6D +9xoptNCB8HKWh+fzDlTVGCKMYN3dZ+vCa29hvM//KgZWliOMQXQx3p5itRTD26O6 +gb/5dfjbRK77L5GsxLuCLRFC8tDklZxEXt+w07IR4iRP9iqlANQD7oOxy3QC4Jlp +Hswo3mMWnA/JkruuYHR1GjyI4PIyW/XRDtqqdPvGwSpBhDbPrUQEGIKK03tNYezj +hWzvcJw33OdCx6LYh8rDpZxTs+s62rfW7a1Yf3rUCiLMNfWxfWDj+BfHg5udE7RL +/jhLecFq8EKchCF6yhGMtzDm7Q/aR0N/ZJQlUFkv/uVAC6tACeA6WWDwIinz7Agv +G92A3PpgvaaPekVe+Qo2PrJ7FA4hxfdV/7aVq5ow59vwRUnluA7s4gzgoVqbYd4g +Gq6pLa0Vkkjc1UYGJtPvx00SIC8dJFrqR2mjrbU4kOctZDMYJrHO2nGAmFB0eeCQ +msfmX/+85GGrFdSB89Oj/5crSKeNrlGsHKC+hLuXshI+6oUsseUhR4nnTnWwLn4c +xztRNf4umW5eIWNuybPhnsPaKMo77UBPExiUAvIy/yv3d2WwZ9+nHa2E4lpH50i3 +JtNuj5+EyoYMAAF/cM1wNPwzgdzZKeS+aGIN+hc/cvRiLECt3SoNNsaqBFpaiUSi +ndNKJUpKWEWTUc18+MRUWRha8bplIUHE9YCDh5ZXCJ+dbmUG5MhVX2OuOVSbzhE3 +4mZ1t+qevaV+QPrZHfe8T1SKqaH2T9Z5fScfC6KI/fr8Yd6igKssHaRHcvPXGh+D +UJZsqucjTpMD+PILyr/0vz49ciOiL80qdc43Oja/49ArAJ+3wSx8r2bdKQeLuw5N +mlcU4RUldKRrWAbB8YRVbC4SGYwNud52s5LQXqRDmL10aS1IQHIRvd3euvL4bf5z +sKzukMRutptNB6rjMajvi+9xNKFX5JkdATJ7mHZFsR5VbQfRrMfMTQccKh7W9Olj +czZRTXrAMqFb1n/eH+oZdtmzvI8Ugxz++GIVBBmndp87wkgRHil332zNE9yOsZ2G +ouCq4gCZ9FWvqrL4++nJSbRPTCR6348m4zmuGa8LjeQIJgm8j4cpzReEgZsnZ4u2 +Pqn54vGm6eAC5OTGimpsoGA9a2h0YhE84FWlO92DhIZU0rd2Y89YzcHL2A8sWcri +NHF1IL2mXY1GfvoqlWimM6bJXz3RlI1ItVA5dp82/6IhFLg5iYA8lIuf/ZQtJ3q/ +mH0t2dKJP3490PTDgSwKkfJ3yVFgcAkHhJqLCQIyTiXHMHg2Wkci1/Y5iIGi8zrt +h3/l+aeHWIGCzDy0uVadwIFtqgNi8w1rgqQoKW6yhw8uFcBqrNf9TgCmhlL8GcZo +GPJXQclsrP6ZvjK/99Jx/wmL2136DEi1bjMu8r94XRs4BOKMEvEnVYCbqBhzu/Be +R0Ug6eekR44b4tKB6WT4gNtKAdpWY7DplkW2MNuarsuNbjxYIkMlZ0pdNxGdv1EE +i+Ie2+en1LSKLu69zFhSpU/J3rGt4ZrXSNStkR34XNY1Ron1JL3P3GlcBZamZqBo +giejpB3cmc4xHd6DEYflFn/QPq0WkGzdRDLLEEkH5ueh+oA03n0hEtxT+kDS7JLV +8UyITonUWdYjlfggRH1COiVx8lNOOB+zk0/n7/coSadGKxlbS8wFuuXgP4mRA2Az +PM5kwm79By5cqSwkAoC3X3mSUJvMqINDN/bjQALH4z6B61qqhgRuq9oPAeoMWWZ8 +RzT2pg6J+81YioTiWDuKPne23sN1TRtQltSjC2y7eGQSg/741QYlag8M1uLV3JOb +6o6D6PEgxTA66D8UAGdoVHuNzlpkMOYO2pKtj1TOBKdnNOz7qKrgWUCyMsmTXARG +0dSnkuAYyu3ye8qbPh8oxYH+s2N4KpsdfIIgYqDmxbnyGRWFUeOk5hpEjQPcgZSJ +FQkfqfS5+Xg5BVSFQ7pp+E370rnALqsPCrZl8iyFnVMJeslUUNSyrRIhPnaIxbdE +ACTh0dQ2KrhrcX2/r43oKMfC4PovjzAGgDIQb8Lk2QAcPR2njTw2eQBXxlARm/UZ +o5/zx2E68tlwUJMI6mJ878v8Pdjzm2x45n2kCoixsW7rr5jgGUVRxt/GFpKMZ+Ru +YWKY/Xk4Q24VZOy8KGKear5M3/JaRXmz8IWXOtj0Dva2grR83fOJDzYWqhgJIRM9 +zesN//04f0FwVWrPJLlrxcvZNGtqjOnjyjl8B10P8JvRm/w+UmHCTTO8NG4OJV4Q +NRrDIJA4xOcDw860N73wN5PT4IvLGBZKIx5t/cuk68/oTR0wPd6WgR0tBfk94eoA +dK/zZknNnlWn5Kyqt85JNW/2801/oSMAaq357ihYlkDX5FNnTcceyyqyu1LWZgQE +FRwRtsfnJA/gZpivZ20FMDP4yhcr6RaFT/cRVe4rPuBSZkuoDvWg3o2ZSVZ4kKII +kF+hAINAy6lLNcxeLxaVlwPUver/t65KcNoIB5QMOWDv2k3Oc+lMLs8QkYFeO/In +EYIy4sHFsSDAT0OnBEGt8j0VI7xT3whXHa54CSFMqPpo6WcPDsmotpOGVc5sGozG +jyMdgxwkXZdG/a8L1CsMn2qvF50PiahZEWdGDb5Eyb3gb7zq70G7H8yjStpLMeIm +FaQVLNNj+LMdEnYo9tzGjqqHyf6o7el7F6jnC+1nqONlJS5AD8khBEXfjVZciIhb +YL0Gye3Lsr/Cnw5ec3F1rw+FJUmvYKkPCBw6lQ3HdGpfFDYjNizGwDDTy2f6QT6y +fQqGM9Ybh/hshdsoP8Sw6SU6xPSRghsuRaTiTTi4R+HKLH5oo7SAIUVpI6XoreHO +o2ri+y+Soo8MISJOlpMJgI4dIfyWlTU5GTIp+szULJ5kpLKg4Bb86l0d3u6EZ5QK +Bgz82K7Sj1qGAL5vwD+wKvVE4rYd3mmJbazEVNwRl8QmI5aZF1kV2memVhedSmKV +iOlWv/kO6e01N4c+AMxIJk5Quyg8IUkuV9IcTwrso63JU54pZYNkwlQfr1g9Ux8O +j57sB8hzfqAdX0d1uW9Vjq+mYp196LUxkWTCxE5mP/8rxNyFjaT0c+MKrbukESel +CUbJqx1LCeveqAwLkenPoC8lXRWuxXUwLlyPWjXOvHEn8xZMlb0aWvVBvK2ArqyR +tEXszqLaHbOobpiWdi3ZcK3ezgNW2z2f0h8Wpd5iw+Tv9N5McnG4o+lZmsYzOrMG +8RdN5+PU1cmV8hR7yler1peGwTjSoUoH+2RSOBDNoQS8+xuz1p603dGqBSlSgw52 +UdPfF1XWrcsgQvePHEgJWpCirrPkTrs3eQQWv38UtH+9WWcgEv3aM/PzW+STCWN5 +VjuQDPaNTYSoMMq4CiJEufx3N+/0Nc1vzCAGAdOP8RFuEsBQpYCQH56mJlAH8nki +0gFKgkftXMpKu5dIvS+D3o+4t2vd6aXBQAdaluIUsKoKSvyXUFfVyGg1fOY8xr2n +lPM7h8KZ1PbGWHozwu2WC/zHoS49tV9BxHOs3MpZZ7M5tXiiBsdWAzjysUkCDpzp +Pgln5e5L47IuTdLyzdup8rHnbg+aiWf5N2T7Hy9M0M3cka1GrbpVU6Csy3S2Ti4A +SYyt6bn/BszewP+2GZGuWVoAWy/E6QLME7AsidGSTw2sDiAtRiMSywYcfAZF5FDo +nKdo2SnahT+oHihQh5507ACu7IKdIeUnSX+Hn6+ii+3HpF6jmoJjjrO1Uh7t3JO/ +QTeJ3sFZckcap9EiBL5rtQLTMQvFyUhUXmk7KX7OTVc1E1rxmKPaTIBKQQJ1+D5t +P/pFR5hMmsdUcgHJRIMRFPHgQSr4OJV9e+p8W8IqZbH7t7wjfV9vjCKmKdtVk5dM +Y12XWm6ezxnq/dPHV1CoelQhkf90JkANt2Cs6yfBnOyZNCLtYGWSI/6skzE2EL9f +8hvPwI52Tifx0y/d15525NxTlvJJeEGUd4N/qHLwK7WU+M6RnzWo5kHrxuuEN4A6 +pxu5Ls/TcJ/nMhssNmNHv6K24YbdcqnXBXGCcui6ZDnKbxxuuYvPhCKAT+LMmle/ +68p6EDLZUdJ/K1ntbCaiNwJL8tPWYLDuQSp1vw4GWLuh5mghBm5G8v8xYUH5exUY +I5uVlGCy+EHj/Cuc6YFWXLsOQ6OXUT0QkYYC8t7akSUAxc8vb8Uxd0fP28xonpSb +rINDAndeeGXPlwaFRFwHOUoN7ZYd715mjspJDlB6FX1HSocBHPd6+L7rIjQetkwV +QRvlSOdgHcG4RghR5Lfyz6+uEkJswFletZrVmZGbVWMYzzf7TZqZR31dHsKsaK4n +KgkUuWtALYpiIkKsoQLvlmEkRFIgtNGQPADr3Bsxck1hG2AFtEjt+62PeRN2DD9z +qINb4R793WbdoYQXhjV+kYBBmeNTvQgzu+FgicXKTp026OvpW8JaiUxYQe6pfCqN +VOR3lhfHMAv8Fbh4jIZMTig9+RuggSu9HcLnbjEsZyT7/Njtv+qCnfiDTxG2x+8o +G6e1G5I9n7fse76Kokd8Tpd8QvGikOfAVxxL8l9ijiwX1MU3cHs5G4DzwTmEtw7M +/RjYSZP4D7vXVZQdQJhXj46rJ80XfU+XP52q6zYZAe50MXZ8cMYHm7Qn4Fiqw0et +cqezuox3XXqttKpjFPXXFM3Yc3yRDlOTm2rKmImbT2FCpdp5GzF2x4K1Z0OwC4ov +8DKEdpG1WBdr97tZUGSIFQWWBOVuOlNluoq1cyhv7MxjIDdPmjmgA5g/J1AUjMp4 +m2AOxvkWamuvjDxSXPTcpSCGn1r7vp7FwkS/qsEB5lPn/sSOl+tyj/n4RZwIYLpB +RzBo2CX4cA8tDmYpft1xqxy7Ihbp9+3w4GKGo5N4I6pOXhfSp3i8+PWfQK4M1VF6 +AoWzjmB9v0Tgz3U8C7bx5NFlyMkzXHfAa31f6jpqNdowDRUtPVnZV4oRmyWH6nNy +62OWhRmhOcsif19O14ecNZ4pouoVnsev+6EOcX2uahb4L/cAVjw7ZUHy+t55LMky +WsEd6aYd7pBm3MaBEOrd7GbDFKDLOJTPB9e9NaKbFGeYLfy7zZciF5Mz88y4bJs3 +wJe1PDvSRyOYohwxsJcI1dXGiuR2TeDcO+/Gikur/ZVAVfaXW6mKwVy+Z4BhJY6o +pLBffD1DZbpsbOtmOUrW7fcGGkhrVrnYcld7b1ayquw9G1o5mU7g6d7D2USwyhd2 +h0pvg+Bdj/t2W8RUubkBugQce37MKYO1AUsynEwEeZmx+sLUXwmZwi+wV21NyFT0 +f0r9Q3qAhAleg822J4q/NB+1hTPzAt9y6QFkrabRGonLNfRly6UXg4eFT8B/KbMJ +EQyW2Gpe8z8pm+4lUeEx2InIWrqUJn8CD1/gy0GJOrS56WNkWpQSvlJFPvYSHwBr +A+qpURlB/cgManLe06lAVzRwDiM7Mue+iMRA9pUHb0pOKen4fTVchIGKpASfK1wP +9jO2yhJeGl2Glus0Qxrcs/GtfkEIf5bP/XleZXSk15Uxx9qYpYyw6AARYcV5MFKA +qJv5EzNq84ZUmyB2DHzn5MJ24ZqA6nzQE/Ci217NYap2/vE2L2itSLknRCBXLb6x +1NmCWCqpXFrGqxjZLfdexd4KS33gP4giaYz8UiDsDxQhHNEThJvurnilzMVuM3wk +47R6P+7zvRfXmbqLut2eRsFYTcpIKENTWxryxhmnBARp7dv9hcHng9XfDn8VyMwb +9ck30SYhw5/FkynA2rHryggHdFbIA/pia4RdQZGAE1c0vBe0XGoCCKI2KqZ/pSjN +oAc/6cW4VtBYrLBRBhWfXa3DgkWy4zj3OsuMjJpiEemXbEV57rH4w+NhPpHL1UNs +9QaZfu0qNXbgtj0GgygjbcckiVf/cVJfPj9ocyXKYx7+JN9z8//kdW5k3rxC/cVs +8AQILgs8Jqds/1raAQw0cvP+6B8P5ex3htu4oSF6sgetrXLv5d8VJekYtLwOB4L1 +6Su43FtwSwd8DTkEwQFTeFEKp1CtHF2SMXmzJSFga+CGJqFL7okS+cVfO8tCND1C +AIBuiC+oEetUWZZ/ULT9qY8X+n0Jl2uqsW2o90HY9kw7QX2TNyCvQkfJfewj2onA +6QMrmTu8G9bo4uuYW1E75Y1tZL2ctf+diy+y2Yv5PFwhsZlyFy8BNa26aGQEPaO0 +xYXfoN81gKlZ2EwW1pW/zmGciVKdiS350Gv/gfDC62/wOMk4yfc0ZYqxc5LeOfEI +WZiynvMt9AktBIpfKt8YzQkq9V12kit+d+d9WIk1/qJZRUGfm8GOlDh7rR+NGQnl +pU825QuS1d3zgt0MdbbAoPWZjQD7e7ipM1VmByodEn1U531AyHMPPcpmeJftnZnn +9XGQLlcym7AAjwFm78ia3OTfrrzdCy5JaEtt3/HZS0N+0FnJ3I11S5B8+AGphZIY +HaX2ZiAJOwWxJhLYCslT6KD9/y5wmRNHiP83jf9w1BiNTD23g+czZ7FJyXnYfY8o +rMfmackQnRAubuNWORILKqBDkHCwkz+vQMOalZ8fHdUEQK1yISwh7/iVJ9EDYsab +yzRzOCmaCw+z6xe5IXNU7gxd/ZnwWgThBrFHOd5Oxt8X6rnGMSXvOqF1/6ch2eBO +lIyzOuCKcYyX/l/AMnaKLTMIFgqLueTSZETV/xOC8qSexUgaUfVIDoer/fbrxjtt +DqE84IfJY/cthMN9/hEwF7g2BWjtynPazaAIE/JcetPYzZTO3MA19InzMrMhPevb +nGw/HG27Wplhtz+/49NLc1b5fzUgUSqal3n5jWMctlfc1VmQIaMmquvuZ6zeP/Xc +ypo/1Zid4jcCRzVlDK4htF7VsD9DeiRE7BhWox/N6AzzlkWlLvj7hKs4MOmDr4dA +eiLrxZxo0kv9aU4XPDdtSp+vd1oHozO6mKcAwcF2c+WcgDW9VNCu2OTCaCB6hs8r +Rq4s28GjHFwWVx2VQ6vthggTUdjtBFu2WmZCMwTNXbb2OyxCovTdQUBpRSjpP2le +awZ5YkqjiJ/e628edrA3M/IHi+89YY7covFY1ZDMSxNVzvr3lQRUBzkQTz1JplB5 +AtAy0nFgjbAJUcT5HV7fSgWfeq9mmmyindhiWcK3iNViFpY4xe+V0dDJBnIl7tHT +gqs0xfoFoPYdou00cvnR4yEG6VX/HM6JGnUW6OC+KFNAKvS8Eas/zOUUh+tM0qq3 +kf1w9cJ1QH6mURjTChzbTuxkDt53I/qBGeCE3T9MMvPXPwmeFs6nACRntFeBsI3E +3pYNBlNrrAGXrAtRHyM2Rf7SGfTZ7zLG6txr1Oa0vFZrmk2MdBKJtDYTQUL5JGZm +Z3riwzuR/9A5Ehh5LLdpmRuRBe9qAr+XR4eFwL/pkvwZjOz3zbI7jVn9FDILkb+F +2fYSQvCfPBlCpLMh9YvtwfuUGgkf/5O78YWKidXiDXNs2x6o72+EhT+z6Qikppw9 +ptbu2iM/WocK3zCvJjl1qfl8FncaPK3zm2Hqhn7nCcr40JdD3l4gwwcpAcppGaOe +BgJgduNPS7isbPCjtgVOXv26rrLeqh86anfHDxSLtdVusXz9MJDO+7zfuvwJxiSr +UC9ude+NmcDrMPlGmDiCTwnwnbc/CPkUK70kmZHzMVCukvsopckdo1Fd79N9C2Nh +T29Wj2mHjlw7xgByRuecRCoLlDw2bl7+YCiLrjhzL2rk1VMBP8Gg+whsv0FanNtt +ACodCtpa+E0JCaOZ/+Sai4272Za7E6t0AdvlJLZlKeH0ItasKgC4Yo2+O4zuUFmm +br2Gb7y5br0Xbc0E0yNUSd2B2qsTfcWoRPuksBQo9iAF6cl2ZRZ6R9axJ+WSyWUX +q7LbscHDFBDsikHkfWPbR4qsFO2MMdRKZhRJKNr4+ZLlv8VmmzqD/d/tjCC4ZNIP +s1zYAXA2IiYLeGRyuatQW9cVw5HE4UcYbEPj7c1orq/sHAZ5WtKPnvbt33ckPRHm +85ZIQge+Ax/CGn35rKGf+tQeHoOj3+QmXPHDxQpMyQfDgpLS7sf1ZGhnK2CtjTOA +HAO/WzCbs0ySERlw3hO3MHg9qmjiZ/DaK19xD55VxnNMTxcHfEc5QolkLZZzMc5s +JMgVlqE8JxSswBQOR/gvLDHTcjPhypIwsiJUORs/3dX6+pAzoIf4rJjK06H5tkMk +fjbcV2h15DuofRzsObTlSPMLgJY7M6feIEEP62lw562JTC2mvqmXMzwwjwXDoEr2 +q+FIMxyG46fnEmE6anICpYqjRQ4aYeQMR9Gax3qs2KSFSs1rWS0f5Jg5R9IBk7p1 +nKptmjGp4/9aC6hPmcObkTUghGb41JBWo272HJP2GWiRoGfSx6BK3NhvKL9WSDQM +WsosZ4o40KXBU7A9dqiJQx/n4XOVtdtVNyNdqiRd4rg6Z1GmMvuV6dc3HepFX8eN +ftAZ0lydXkLlRZ+64MR/viwkgvZSd7DxQTH27Ss41EkG34l8aPXk9aQgTkT/GmD3 +qggp5d2l0k9bCsKsJKk3MzwKd1WcpLAZwi6JEoZ5gWTQPGqybrqC4N81o4aket5i +DdTW9KFoazY1QZ3iUe/Ct4q5fNN3SOCf3CWObaIw18h4oDfcfdx5/+6CsmdHyUv/ +tr/nftiWukFm75qN6NfQTlIGWUsWJsDa4TbjQYcuVUQrDhgMwxvICw8fnX6LJqeS +s4+63zIAmApbP4uMU+m4rDRjs5ubyYO2eMs6Mdtyxg3Zg4yj8ECIlljr0TVTnRTe +u687EWXdD8wHpaGrTbgoasdXJp98o7zqxABkMzpBx+o3lwsayvyI4TmD/+vRIo4Q +nFdjj8BOAFzx7RtTlNFbb5QpH3tXnrPaxUN7YgdbBVtpqlrXDK7aLXJJsceKBT4Q +sIAW0h83ZvBLlhBL7zxchPg+A8P9Wze8AWFfmvhKwYdrhwfqCaHPL6RFT4GdJwHr +RZBV0XkwPLYW+7kDiEZlRR1SAiU2Op06w9JgAqeK6mKkigWDtWNDNzPLTxUJYdyd +zB0ySyesBgctspvD2ASqKB+0ltMT8imD31Qv1XMUtoQ+Na9LMkB+lJTibdzsGlqh +hV+B0faGwGwm4Rd5cb+Anya9YXG0H5WJHZ987fdEe43bTdVSG7UIaUN8sgYScvbn +jyNwLwQJKnmR090h7RcVhBRKWQ87kQrE+4tHwkh8iTN2rfxBlEWJMmyaHXK2FyUP +UhSwTugbkcRzQAGWDmqjkdXqpWPG6AxJIxalvCEKdCKF59nfPRB3hy4tcpDaLJR6 +CkCuCqeJgbYq/PTsi/dAG6gWjaWykkn/a6b/UY33ybKg6vK12W4hUnffwVm037i7 +6bwB5svXzbaZc9WDgCAe2SIEmFK/ZxPJVAop6QKRbxF8Dn3KgKlrPiaNPkPCdBov +pmoLrWuqG1zF87hpZ1j/2K1reZ+b/Mip61oUajvCM1F94Omm+i5gUSDqBOgVtfxX +cO6yleK6BjxO3L6gV/J/cBy1boii+JdikpdOll/zzSMKT2sxpvVgT6YIHRtnnnxQ +n0byS6No0dfJVca3ivxcSJA/6joh3lYzqfNx606r5laN0ohtiUrUNZi2TzlVYs3o ++7AyasDci7GAAN5g6wTVTIC2NAPY94fjgcl1JGsOD8uEbVDpYCfiI1ykqHv9REmU +fPQnnnU6dwj0cV/ugTs5rUWTrghp2N7SIFH+rL+GT80Y3A1Wi/51WrI1xm3x9ZCQ +5YQRoUFTI1SapDtKpjMXSluQGDpqcEwvCkXnxAon0Vbcp1rOrpTD41lE00zwT2Tp +fYkyQTjNL7Bk8FaCoiCF2k3OS8cw/b23VpqfZj9rtCgPDdDStzIWys6ilkhMCU6R +MDwFNcPwD/mC35onp/xtKrFmKhCJCuEGON02vOr9k24vAFf1cSCSubsmyWY0QwC8 +LssSf9ekY77Z6KRbnWfA05Y9vsMqN6ieeEJeHIztn6qJd7ie/yOyNoTR0xdHfTGN +nfYifesPdjH9FzEIq/BMLnwEgz42418ENpzRqWyV5kNI3b287ydJ5uxPtBb9rFIO +4TlzfXtJmV9GU3m72V0s4Aj/lzc9+AVfj52GDIVPKzByx18dSpkNnLpxSOfv/a03 +gG+rp9jhcg6z3ScDQw4d20VPyfZ6y2yKTwoCOdB8hD/ba2F8lmLbjY4+FQEV5U4w +DI4IyZARoIxDWk+NpSFlULA1KhDa4bSBVPCPfqKmauYPiweSgJ/z7Sc+SMCOVL/N +se1we6LEOuiKkDjVFd3UxE1YUXEgsGQwIweJE7PGjxFfcPsMFr2X2u3fz8ofM99C +NryKR82USJ9Qu6zQU0fBMY+sGagc8non9q7EwKXg/fg3/iE/0PVratbhBSXBvPYz +2zp6SofRii/j7uk8bfSbTD6Ca/KSjzG8rHdmhamnQjzu4MvaOO+FAn8gLmkD5xxp +/ODgnSOJIXaGQR9P4oadjiA3wuSvAJ5IT8gU1ucXLouV0CyGZ1Yy/f1HgZ9J4Jgb +zEFTLdvKKn12wVdzVkwYhRCUQlMYjtUPaDqiI9kVS0LaH/Ac4GdgMVbTeqYjDbVd +oW3TxZGuyqo1/l/III96yIgEl0tkkie3+DBBMSBmqmYgKaR6YqwTpA2DOxlodiL7 +TiEFOeDORh/jOmUgh6sb7yMQ6BQnz9Y9qrdMGilXynU8ifjeprjI2r3sii+oBV0J +5kB3EmmEpJ6dMi/zJwO1r7BdRUDVKIfD5OQG5HymBsaNUkdng/2gFTE1zj7dLhZH +XvIefWMXSCUX/ZL9RtFHNWzEOxYvK+DcWpBTqE/7dayRZ8uDKqrNWUPJB2Fz/mgx +U4mmtOp7qYXBeCfky3FPi3jdIkhJiUKYHJyvwqTz9qy2sLVCsN+XcVOhkyW3g5dw +KGbKyTjksg8Bv/7qLaCB0WXM8zRZ7N1b0qVUdk7kIcieBPm2PQt3cueYmzJfNdUe +2l8Ki1iOnbbM/fkNC3n+lgm66wWtRfZ4EETOqHjjFUQhfZPF0RrctzzVnWEQuoqy ++sm7xC+8aqYSIrtCtKUgzWP0nXQb+bcy6BR81mQPbljtYd/KiREMF5Yw9aaabYBt +foNvMfao+AJUKrly5XqOGfenk/PM0l1+hjh+utgamCdvaZpizO9Jox65LgAAjpIf +Z47cuVlFvM0khDO2bO1vWMtKPrAfeRsne5Boc4Ii3yk/m0bkoSRb76XPSgepjlbG +EuCyZ23YcdV/05G1JN+vNwxBmBZGVeaeAQFnhIEgPZG6HRARkonXeYLnLnONaR6/ +WUonvH56VaAaTZqg742Gnty1XvFUuP7VTgYxuAZ9u1o/grtT7eEzB7LwcQXSrBxJ +V0NnC72SJEvLf9P/EiP681J7F4LU5JafoVlhu7bAf6RM1BRLhF4rV9M6dkBaQ1iT +ZyajjW3X9M78gbY/Lqa9ru+OGC9jmqDXDASuXbiyMag5kX38uYd3eD76XBGX0M8i +DdkCLkidFSslQc+UpAwvdyVfAcY5TpI/a57mcwJErXgmHBUjgjjKnl6wf/+t84VH +s4LYAMcWqy3xWv1V9qBgNUV4JeWif6Crj4TDHfI9FAkrs0I5ANbC6I1oIgS0n2Ov +gZl1SO97vpwCtZy9yQ0/ROXEYqyKclYS7//KReSuv0rrQwMpF7EFhBpIpPN6Lk+0 ++nd1PPx6SJCkbPv51YJUuzoERLkpO3G2x2rFCrKqfCI2ycwxPKJ60nQOn0fzhm81 +xgGGxCNLvVRpoOf1BmXfOzYA2+/5I2H5XMQpo7qb0Z4v3e35qGqRWTC8JW3zsnMN +6xtVsWrRSrFaggqUHWvJ0tJCujsTlGCLgHaOsU8bfVxhdB4G3Havrucs4onoFiyd +muavVG0umW//i6rpgWJYb6OkA+NM6vLeW3P0PT+Xr812IuufRU/cElcEUtwEvx60 +DJ6JA4UWDWJ+SPHv3F73krFx9lMOWoWqV78cFe9oyfJeV/4C+6qBCSJXLYuiKo51 +Mr18dmZWPSYVa4QO2sbcE/Dk6UZF3VsU6Ckb/nCCjpWnaqJ7Xkt+IQtP10Q2141I +olRrHVAWBfuFBq86HvfvTWC6vOtQdIRhOgv8Gri3hv1Ioj1gviol/IU+o8M9qZjK +MsWug1RZ3zGAfTmGTlaA1cm5aUwwN0gQcZGSRkLGjHakVKvCaE1k4zsk2jxkf6nk +HUDGIl49DjqrqQu4NAejpsJ+vgWeEb6iavRTNZ6TG56iWJbwYnxmNsZSBySul/i5 +bCqFN/6gNTMfx9J6GMW9381zX7cAeR/nEobzsMcEORbQf+xGVIKeaNrz1ByjJ82U +B9dsZiUPZJtG1TPUMZ/0m1eEzQ6VYeP88CYBC7PVprBBtpHMjQ/6Mkk4az2BjMtt +owKC7iLflUQhzOryfOPQ7n49UCnC5EEEEDr4DMuNETNqE+KdyR+vjI0QWQeAaJsH +kA0yZ/ADKjeVRJtnT6Sr5kCtrN3I1Kn3u1y+RsUawszUl/J66MWaT96nJ6hqiLxc +6cTq0ad2Wdp1luAbCIu46THXa7twCvWeROOsjLyyIWQoT+//Naj8vdxrdxQMt7Z9 +Mztnlt2ToWY3odgPqLSSz6h7Qt9+nmehOtTwXBJ7EnZoDDCk5Ue/FqGTMaItX+mk +dCFBUH4E81tYmgtU44M5Z5vxnCNgUnHVFvIRPqAP4nXeURNX7WEWI6nTos9QrtT4 +RuAQJdt02QTLAAVjtoi/WDGKQsGySjGC0sEu2fu6axL20ZeYgcWxCtyZbPfQzoF7 +qm92FItlHpO6Ffu84uOUj4kBiwXFe039i65H7nv1HBvZ8R0KueMM6Y3LHmqfKw6K +BkNHS0WIxnfytHR/y/J6GGJn1dnfcmRIH9h2MoG/PkMNPsnzuTZt7kCxYb1hb1ga +fo4WsdvGyAppAFmOdsoKG5CKIFwl1jTdiQxDR6C0nH6Ie4RiMsKLDKepTqrwCx6Q +DjSPUMQVQiqWHvEmt98Az0BMCOarRUkbqoeLLtt8+BLYIEOMeWGJ3IMCdOQOjrdk +L2B443OWqZHPA0UoCmh/Hu7xvf5x0am2PLLdt0wrRFGUTrI72DfbZPR3mqyoC6Qp +R/dirPxE3QTEA7wbATGLTnHS2jIm/QaFr9KCI71EBRVtZW2WObP0g9aEwL9fLQRB +9b7QivA2xMsOi+LpkTOw+IJqtuw7Z2hoOY8pDM8eunQpTFE6ONpRybP8f335PBcL +kndkNWU+0rPQUoCWlI7EQtZ/g+ippJ7zWQZrEAnC+27SQOm4NI6UbTE+Jtv2lJbn +wnl0kOmzpCmsdK3EQAEVBAZvBu93o/MxukEmAuniLp0LqrnCrhIORx2gaLddfNfM +Noo00OxGmp4PT13buU2v9svOtozDsl1lQ7rAXl5nR87qNvVW37q2L9z5g1sbZOj9 +LlPlzN7vZz181W6/cGF8ehCJNNU1IG2gO2dW01WB8T4ffTrwUOwQq+zbr1+Ezo3y +erexfbU0xkZvAzqkiqlDOQA8iLx07y4/qZikfoRD/46sUOUEZNhYowAPTgHlCROj +XU81z61nJ8fR52T8EF2V5fb6QNQJdY1WjQHmYmxZ238XQ8jU+iZDO/d9jnVvXAvT +6tsEO02F670rSz54GhXDuXfDMtswqmQbRBjnWxq5MJlwIcIRPAb8ktGIz3dEbWdA +3D6sNyDGcL37/ywwyqlEcANdbWRfbX2gXkb+/g+BP8uHYT32q+Cy5BwoEYrrmNyh +AN3pq4bEIc+LejKZoxEA454PnVHkv3rRwzY9DMM0NV3LuTv8iCwTGevSo3OUoHwH +8lQoZbeA5u8iajrQvi1WVsMymvlqhb4PnPLau8fwCNvyuuerKuNRvWFl9G93LQpB +qf0hHmUnBKj5IAGAubZQVlge3X3+b5oYeZvLgPGvJtLlN6GAJZjhQXjRw5pi0BTY +EODSFWUN/0Qx51ZhgbNTApLvlnGF0wUZ70+UNVRFSABCPDMk/QHb7KFILc0xNKEW +5AE5+wx0JcNPUs1CmGIBrB+NKSa/YgmztGV9QuvR/xEt5gmbSRaOGygEDK3cxTuo +bJxEZA3SHTKhIR9ItTEUwBELQRr5Kox4a7vbU6BCUDcttV5uM4QwghuNlcyYjMuN +di2523GL+bHTGDOWuh3Y1FirzwXXu51LYSCGcZiKosnj2S3u4hLKbiJqgXQ1TmQG +dH5A0JwyhPr1hzh4vFaw4rf9eST0lGax1OWYbHX25Zc3/N6jIZDPV0ZP3GxfBMzn +RF3Oq6RHX2sdILQSx/TnAasSwXeDbpSyJAs31yVA01B1Fc09ol5SvlVdtmO3/a+J +QrY3xACfiVAitreL+cIdmnYEsw7zVwPqP3rPaFersNhkNmM8hTvaG9iXrSCW0Vhs +nh+1UdwE4ulIK+smDXCVZoDE4uu9kmSTRNZ2IM3tpXPLUiX5dogcO85GnoB2LBVf +z1439/6tbxfZYdEQ9I7K3aBmhuN/i6hTWFqDuqm0Ja/xCQOYzEB7f7ZNEDJSmx82 +IHIzLqV5VJjyBgki6BBgTfTI2MYjXOmKNb6IKF10vuhLUQWMeSlrfVZPCM6FcBZg +6cKqD5fbjo9XJG7S65F0veHbyI7mA/OTE/5qIKacAWib4P1Fbwq/9YWHKPL19nrG +l4aUxAus20VGkfVI7Oajjb56sgxGIJ0XrD5nC3l2YdeESncBiHFDffRcZKGl3fKU +R/wEmDmXul9qVHQYQm8K1SgqtWgRq+Qvh2U2oOS2NGFo7r95FLFJUerVq/WQj2Zr +bYENZLDe+at7DxjV4tsLyWYYyuA/xCpmm7gExgybpB5b/4XxxH99by3LRPDiOKmr +d8TIeKVOc2QOlVJ8yF3MUDmk6HiW2jI/x+wCFKBBoG1Xgq5QiEyQ93WgGz69ZuOC +UpQBpSQwvyf7k0ItyCja0b5iQ1Sr7zXv2jwXYiWBR0UJC6WPa/VOZMrSPFw9SiS9 +EoUNbSw9hs3qNo/uDGM8WX/Hrvwqh1j5j+fCK+S6b2kN2pVW1rFm1KoJ8VLkp63u +LkRblJZEnSmuRfIjN+/h3tiyDGWFaaAsCnQlzn9BgUd92lQqIW4WJ5qjP6ArDKFZ +lbT9pL9imt8mq8yjD6xBI9lKD320M8TQKj1ut869EqHCRI7/yqmdHxJSIww0HlHh +qTtTyWbgDQPUl16crEIgvzX55YG1mAOf+FBG/SW5c7QMXuj3HYabwUab/KPmwDi6 +Ox+ewM3vmifoqbF9HPyFVUWO7VPKGVZJlLXCk43wuDWb2zsVKxc6ZngK5Uqztfhk +RgcGU8xX5PjjKsOWzTfhU8TaeGeAdlmQb99C8JYNsxZ2nIcsLTQOQqTjNu71FyNm +tLLGwU3sT1X4bsb/a9iUl03abpT6dXUGVstx3b5eGLUvqEzS8O+leuFjeGZ4fTcN +BQus7/ali8CCS/DE/2KAcvBeu3NjWW4z6uuwRRxD6iwE+/ZLokpHICjsZgRk91Bc +j3PMDxHnyWbRnR1r3SdRj8nFaFXEHxL0+sJ/rweTUzo6g9xQj6lTf3MnDSbE/Fx6 +M2gp1KqohkWxmkwlmEsb5K76yDlM5jhNsUqu6WO+vhZHl9MF5t0WJVlxp+M+Hrpm +Tw6DQamqcjk1t/SRBlEKO2Biraf+0dgM5S93eJ+WpZSSRwuks+7HF+cpwrNrbSz/ +D576UYz4OdOMEoxke41kewttM1KF9TuotZwf/Bc+KErozapZ/7xRS9LxtLdf5P6O ++aJTZqjG6gxSQo6yAhN46VT9A1MAa4EJS4FWqfVRyqTHoqxhNJ7guexaioMDZwuH +uB7R/L836vZuLnvTzfwV+y2djQdXhP0+OV4bCpCQAsywkThb7DPpFJl2Hc0CZcpQ +Yt5lv6Sxsc7ty28f+nJAZ/ZF5y4cdykJfCpKKmhryQRXd66fc0rK7JdRZQ3T7vfG +exAZyo7sqnI8xdj5ccBO1R3v6DNUnVr2sdZxZb9W+F4TrwPsBUXqecjZr8gEWgU1 +OUqA/ksWos8L1LIdcbkBVv7tIalNjfPvOFRzZOSO8T0S1ECKqMdYKx/cvOgKyzKP +GrCSEpkRijrHcBMIKG8Z2mbvAIjrvX7rn7XX+zLNbfUEh0UTiizcjPQL0mN3wskO +ANtnCUc5LTKjOHD+NvllagXrPKLYWXg7oMkPrARquh+ZtGioRXgAmHKa8b2MerQl +G/SkWA4X/eK6eYNsj/SZEKg5C9tBN6P9HyRhhImRKZ1b+7atRIFhVBJx/fOQPH7H +d3m8DN2d/wAaXghwDnkrmQAfaWNA7pA3NWjVePBxMRlOpoBCwkPTFCWQSx8fTUco +vj8zkksg373Fpo7IjUL0pKEJKQXk74FvcK3zbRpAkcLbjO5vZDEMKmc6B08tBYyH +AXAzKy00XHtl6UXNeBKAbKb5kSpBJht7+6+5J2vQ//gmELnOFaDMALADun81Ipl7 +BB2jHCiZVVS2nyqxhL+LQR/BYCPjtZRkHUE7XqEZs/opI0rTr/YbNingDIwu7PHe +NoFRbbSV6iTwel7IIgUfjLrW2S+ut3o4mjhuYZVSgdPNYc1Yum/syPStutUq4O2M +MmQYzOWZIzKGD5+TaO+QI59jm2hsBjwy9vBN6UfzpAmMcHpTZnejK1NDvslyrXGl +Qdp850QOTpIfHj0BczqTAURpzEcr5jevcOmeindS0AD+ri04VXG/sGwTjOQl3KFZ +voA9AzPOmnMVX95COEZrF+/Yk5psvY5Z4pw3z/jN8xWKWWsHysUUeekTQujy02Bv +64cTzNJOqymbhe4OC7AgN5La5LFvJSmyyC4WEYe95bGJSZQC6g9WaX4U+LkZHG2r +ERe947oqkiatk+DQJbPo/XbPnmxlpOpPlEaQ5j+8h3/97YEEllbXW3ZEmpunN52n +r8Z/BcMsPIy3U9PPuO9YFdatOWvutOaZBASW2TVYPRbMNRuF/Mhe5sKhfbCrWpIy +dz4nQek2q5gl6e//BqpJw5X+jltInhXTlPwQcpDZDyCXo5Snu4FuVMCX9R4Qrof9 +6jeIgcwESJTH1VkpoBUg4b9+Tbc0n8vgRey2cEy3ShQkxEhh8UArlA7x7p+hC3BX +ZRC6Wod1F/uqaj9Ryw2vZ5I6jzyeGUHD96+ld/pfiIMpCHMU3hekT+XRfsHI1TV+ +ZpewJvUpzeRoOhUDMnui+YzIY9+Ii5wZrlQ6/Fq6A0NjEYEQWWiXsEu0RiAJhdkx +5o/mZYiN63Z3oUzJ7bFfiqY5bHnylwOfF7cKlgXHewJztBzmO+OYTP/gZ4ZqkR5t +ywgtKH/yS0gGgp+42F98YesvzhC0roCPlBy9mo9A1CUBq9YZudWzlJtbb4mrHQnQ +qVoDneXogZdAzH9wXig52yZDUSDoqrBY2TNmn/DNCe3+E8Hq8F7LcSDtf7QW7QlN +HIdedoDFcfRrxxiYacETWd0Opiyfv7qwyCZ99P2c5TenBXl/RsC+B8y/3zPjomtS +t+ydsYtJlvYu3RUdVRU8hUpNEVG4nI3kFU1icWGvr3oabpPi+xtCSaetnky25bi3 +2+V53U0l/pq5KefmiXlDthRyyXjTz9sMPuai2pZQUG6o1Qph8u0Q2JjkCnplUdiU +RpRKxDkvxSCwUBN4WrMwepGg5X/wONzbBUeu9fEKyce2f4TKrLl+fHdQPyo0/Vfl +PAgFfYTUP/inI5+Am3gejTU/RAM22TRlGX4+xbCrh1ss1oDqpFFxzHcEImPl4nYk +eTKtrj5vTLoGR4007zO+tru6JDlx3GS53NH0rG/WFVbVXov2GU8qT9Lu8zPgxhqq +PLKBk5EgkpR3/ztli+EjNd+HDee3dfK9BUna695+9WNyUbswqDcZ1B23P6oW0wek +SEX7qpeAHdLzMELKittJl/dPIrm6SZa+VpGGPWNqYugaVRy6CNB1siwkMQcFmfrl +Fiz8pWGPtcm3T04bn/GOfmknAoxV1nqVB2Xe9Z7PxnN3RW5ZxLbCuO3LkKcDQd92 +EsriIJfts6BXukV6ar0N2KXZ/7o/SOSZ86hDwHXc9u2QcFsZo6nJhevazz1NPOvI +MfSInC/U8NUwFn7GLCZ50xzVBIusmithIGIVuGLu9STcuyNtm8eyIgRHJ63p8x0b +ED6pJy8Mk83xUNM+6qVJQMDieTXyvXnvYMAYb4/g6Wd/b8H2e/XhJUDxpzIWaxYE +VIp5tnuv0Fu8w+qiwwVjDr14EndUQmDbYsSiQ3EUVfeml8D31PvypxIvTeEnwanJ +xTE1QmodSSe6rrroucFwTEBSr33fOHfAj5vXwu8uQK+e9Rhr4fydcMW/5o4rb5Gs ++zRpE+LmFr4dMxnLfclgFDFKT2Nqp639Mb143ngw/zl6a0ZlG17NIdMgL1pCEDTP +8mdzR6vuU00VraldHEUBEKLbuWxT0+bLH5j9xu11rcvrTuC1m/O9OOugx0dH8Dpx +KKijQYuEcwxQtkIfTPchAS0H4zMCEt4T3LXc/Jvg6WFqCR+kgMoIOCziQ8GD5GwO +OAkuKePXffE6IiIoucyygnh07s99NSjcooXl8DVJOzHXPPEpHRGPvn+LC6BAqsOP +RQXf+ptcKmCPrPG67ToosImuc6ngX3t81sToCg3efasg6bcpPfRED7bGfyxYARhJ +8OyYsKBr2yK2+VQvW9Y3InGsfCGICmFgbbjU9dXtNlmbqtj+yuAMGOozwtUXlMS8 +lq2sNVMsxZbv0z7Q9nIQn72/p1ZnrTOhJ8ED8UtSMTOLPjILvvJZ2Wpe0AcpVAXT +iDeC5k4ulMkRdZl090RIKVu62kTHX5/kIp08sCr+e7rn4w3nIiAGvgsm41LQ715M +PaR/rpQ5s/QnzEokTop0j3l7jvBz3ClFcj3PkUMZzfJLQi2EtxxEqcTQXEzYRpx7 +1cU3qDlQSLOsbSy2TMozxI+tTnIRX4KeJv/FbFYXFSo7MfhTZ1Gh/PU/QSU2Pygb +W+bhpN5hxiHQnDFJ6YNp1UI//LikIPcmgrKbSXJWvNquPegQDFGnhpkwVcW152sF +GT3AYmccWvHD95frMMZf5CinMZxfLybDbLEsMeeNGlpgZroANcAY53eHTT6XRFOC +8OSBxfpUMTdzSzWVzKwjnSHc6Fa4Ev5rS/8rDLO74VfWyCtdyNXOy7/a9fP00/jx ++IIoF0B/RPADx67TkQ8yy2n/eR+jslW8H6pPCKso2RO5+TfhILEHQwi9BLZzEnuq +lnivVKQw9jHRIDPoaXw3kcSqoVV5L0pzmVYvzTSLXwvQM/1teYVuWwQCb0kH7E8t +gzzQAC7dmHEaETfC6whaqXDwivkKdw23ea5Vim6BxNvY/AWxdQl/xS3ydtS7WTV/ +n8Pld0MhB9hfvteyinUmF+6ot9dL0Aq1Kw4BKBaM+PngI7+m9h8472oeTJMW1b4b +Ft60tAYOIhKmQlbMQYkuiPIoMH50Zv3v5qcqfHzahqw1hql6UDagU46rshw/C91Z +PEjDJ8CLPWF4dDKHqpNcha6EogAzHnJnd0Z591eZwXZBBzNfl7tNfqoEseB1iBV5 +XttW+iJSx2CEVp/8vIiPzSrrPUvWxOuF7qzYscHVEslfsMZ+ZKxVnso056t+pdZ1 +VondwuB5pkSu3u2J6CI8emjEJXBO+rWEDnUGHFfdBalZMSOmenYcGG5Prxb7gOOU +wrw9VjRtzqR46d3SJNzz+18+wXSQ368+HIPP+vHvAtXFZRcnLuTxru6cmUgvPoZE +rwz61K+GYwfE34m7hLXTQrKou26RobY2Zw8mrpxkOtiDf3wp0P3nGqI6NwigIzvc +E9rrBgDAl3999TiSaPcqRfkjL7CL+7jRQSIazVKx8ZhPxD0Ewft7VAD2n+V6magq +sDglq8dxRTSkZT+2UEe1tvFvQaN2ICTXL0pFtqdiUOhjEsiQ1RDFXSscZQe+Rh27 +gxJRqrPSePpe3RGUq/bQly4xhCQql3RXBi2OLRoGCdS8kLaXFfSUVwK+vpQqWOAm +tzj+8xbvryxdPO7fg5gnu4fKgIbxQjvreQN92gch6csXPoAaGFKMYDBZcuaiXVly +G4kiyduF7t/wsMmp76+JkKI8oEy+atK/FLA3VOMh0dtDF8NBJg0oDGYijrbJLJZu +VvPLSusYxGMzuQI390MLy0PQUz67yEzh5TeFqWHJSvzfXujYIb8K3Tr3abx5IMiI +jsZvNYsUfWbGVOhzdcQ31b5Go6GK9HYDY2ioZcNChb0O8d3NQBcQ9PRX1lEqRcHc +JgMkPRvxImWB5CgF+bPO5qwfe1c5eTfm1y0WWSKpoVVRID8UblXqaOayYfm06szR +voCsqKat1ge9DRT6HHbt7IQf1azWrg6NRoaRm/vprTFG73zIDbEHHbbVe9YyZ8Wj +OSBDCuE6ZBc4mkje37mrgHBmm59siecdNkcI563NLpGsA7R5erU2c1h/HLcQv9jm +I0h8/vPODu5mL13uwU8/gW4CUyAgfEzscEU1AB29g4C5AqHfuMHkB+FCoRPh9NTt +xT2em9g/C1C8fX+JyNVBwJKeLgIO7KNi1VCvrPyx2ko2AT5cdvjpUnWmfYXb/ax5 +kRSO5FeNtDzrvKZuopLOTLoDpX68knYiWzgc1vWW6HfsrTdY47fNxs67r0A7XH9E +cJUur03PohWIvFU/cdZyTlitwTjk2e7WoyM6bS2f1ztvx1GPrwsXO3BI2zjIxEOt +rKDFhs4ud8mQbQF/9wzazhQerl3hKDTh3ho5g2+PQ2bRlTW3T2TkvDQ3k2M0oDZq +hAxRQWGuaBw2ddVIbZxtX/odynkEU+4zbhmk0QgJJ+zkYkF8yQJO29OiQRGThKDw +w72WJtb6HDyXpR5hk0jRa8GtzcNw/XHaOrbZNIFVYL0Z1Fg3LI0df5/0pmAqGlJE +4tE6x6S64dYwXy7GlqIK7YaZ1+if1Z614FRRz7v0uBPiTcVGobrteW3+0T0b9h0V +WOI1HBDdPkNRz+mmihHhMxEbx2HUrjMNAICMPJ2Wot5LyUkNxaeFeA34ig8wEagK +Y+twaE5h7Bq96iD7apyYBPxvxVz32HW5CIyCOKJhguMEGz0/wnUA49vEpqvu1hRx +Q9lXQeNP7IoLMubJZQgHgpUX+VUBDPL/E288MqXXOF0kg7K0gJkc0GeCleUAFCnR +Bi7yfsQ28KGw+Y6q7hDEiS/R3MC5yQ+6okNbl1BrpIUUS04/te3RCwUauyXQ4d/R +YU2E7Uuz3xPZUMCOEMks7OZwrWzUAPP/PjGHQ2W/3DIilcwHxKyGOrow02QXBwZU +C+Gflo+EzAmHMsJH0D32I+b46eWw1t7cNg3A0i2vGGxda1idd+32qKaP8OqJJf18 +w2VtEWvCxlmyahNC6dhmhgd9bqJ4lIWC2m03PvkmJ9gI9mPLoPy0++AkINvImVKF +Cna65HmR4PyBuuUnXaTdcKcLL4MxJ/N96HWdjW0oCyTNyBBgQA3H65yuAKQ5tLzT +2eP3VIW46F3gt7AQPpbAlayzhVpH6eDncNBRKXr7SsivyChRsWppEjvMqUaMRD92 +RI3bg59WgzI4lEFATIrPHl3nIPyjJi75DC6jer5VwybLqAINSMwGtZ3dr4KmGGQc +k8vL4xA6WXkA0//pj9OtrncZHv3TbVzl4dPlgqtHWvLHUL0um3MfW93E30R5TgPp +0f6CDCNANhwZEB75esM0Q9V7fzqR8YBZkSKlXF0nwv9wli4l6ktCiCnL5vGk7klF +4idzcWgEj9pBB/mHEAnhFVE/1BxVwH4rnf5Sjr4fHiPoqAmUm0h6XgxlQXRgyTXn +I5k0un+X5gjcPLV0ssqFPKfTKThP1OuP9ofP+ia1VUbbEpuqs2/T63U2Zc5DmLzy +pzj6IUhEko4JSLDvyBFwczMg532jC3gFOTvQvUEGhah93Rs7E4GHHIt8u8DP0z7t +Gilznm3vZJCHNKsi7oKlKUOIQPPH8WhLHqRwRGQxtilP9tv9aK/vj/k/Vc8iI/o6 +/s3iO4Gc3rndKvpURI5NoCho4CBm6f1Tl+cAS1cHcGREmgSUutorByXAl2dUttX4 +2p+YSlIDsZ5pTMpok0qHokms/uprhMTkH7YOvDGdI07rQ/ZPRC53FJ4oWPeTo7Ta +kFIO00MX1+K6+59v27zhaOssW7sKXGFswj6AaWWpiUHUOX7CVUjgHQq0x7qC3e0z +sil4ptvYzjjnXvb6a0QIWwWAAINawy3GMIlEzkk8PaJCfquIvG8aJvp0tpllwKcG +Naal++ySx4mFGtjzFZ0HEvzm5PksV3lzTnunSQPr3gRIZg3hT5T5tVGmc1pmr9dA +BDj5yFpR+mQhgsoppvK6W5gva0HC+BvBpD3OhW6Siy80qGFDJdB5YmrG3b9VTj2m +1OIrPla6bXYcabeJPT0v3QheGyz8V9nHYxIPpG7VoJv1EUXQKjYGgkz4pCm/+3Jj +iceOvQTespsgIYpqFLX04rPfUHqhaKLA3pwxKj+CHxAJ+rt2ExrAJ7bkF6Y7RvN+ +3cPlUiaNlVY7Xrq0qsnXKwITgNzuiIvw4i/BCIjUVMXs8WijsrJJ5j1yEN0eZR18 +7rXyZdHVXvEs/s3tIV64CCBodaQaqojOuTTbuxDGRZFNsfSmQnvRb47+jBBZ3Bdd +nLOJVt/E3Iqbu7RA/VYa9JSfcLTAz96s1dtpZiLkghcF4P4PjSXUwo5jT0TP90wc +XG+kmgzNP8cyt008AEx4iMyGB952PzAbsxj7jOq5sR1M8ZA2StBl3mu9NtJZu8xl +jxMBG8xOTXP4IkmJ4ib2w+qclX5Gv2Lu6A9aFhLIgHcfc/1msJuY7c2oNMCbnTHg +L3wiPsNsvn7v9StYOTrOvKws/uXdy+LReZiz2wQ6kr9o72ldRS3TZl8SstEPeLq2 +wbFVrZXQ8GgvYmyq0Jy4nI+9HCQXZYc/nknMGlhvTdVHo3QlWeBIpvXXh/etNzX/ +vYdaUbF6nWPnOr2rc8PV+HVg9oYxOHqic8ERi2RsbpjL+Ri+OTYoH7vttT0SCh2t +jqH523cPVJeBatMMks0vxfsk0lus8atKbxmFlKEcHXdKW3mggrQL0SSvZfMWUnzq +QwY70vBXtD+cWxNGpITJsvsoVfgXLKdBFxz2Wxg3qcITVdqlyg7SUvsJhQIW0qiB +ulsv7IRSs+v0aKgfMy5IohaHziA1PucOVRadKU3CMIjOCh/oov282TYnynGoOzkZ +MAL3Vhiw2PqlWMN/2Ui9srT39Xc3sltLyzKlV78jYy6SbkB46i7tSjRW0YA2ASqB +XX708TcnDQ0XtaTe1l47MTMbVpLqYO9XQZCt0z67u3JCvqrefLb5z9iSiavmltP7 +RFLa3Lc6EK8GJ43nMQlmDdSg664F29toIZJ302TBAwm3oKkF0K6F0UaK+mCxl6Ao +hgdLTqBJUezMEa+7dot1tNSNKGOPMjtj8N7c+E4g7U8KudMnAGrkOHh+jGQmy0ED +lCy/IoveL880v3uoxM2stBdZqIB0sFGxFBEhmNuFO7Uq5KDvt5SmS/vLEA1mIDfP +goDDQDB1AyZoiylaoDYqPQymmypJs81YziCh2SgISxKwWu6plvoelGRzKQKkMK3c +2rET44qZ79IZ8molizQ220udf8fN/z/kFCtXX9pPgyNv+44YVdDSP7mL93acD7zh +CmG6HdVUFRR5n4bulw3Bh9cHLiH4fbk7F/aH4kUdsj8nlnJFerD/7dMfgaIBI/Oh +9HhnsXq/Ussfj3t9GBeEHXGkn0Gqds4XJBJ03poMGkRHx7RusyVGgxKoG92yoLNH +sKYm3Ix06ruWGIOTpijWAKHHzhv/GHTH5pAHDK1g4GmQTGJsb/vWIBlDhRKvjCcQ +5yxSpCCSHdu2l4Z0IHuGPdiAS2ZyfoJXhLgJJDRkebkvm2gJcpZTgAduXeZ9CpU1 +gm/hkZxviZIsVRfC/AzjBg7GRP9D/CIm2CI9hg8QILzNC0ZzXVzSJOBNdgGNemVB +htSB9iWbG3W6Nn5rAe/paYLT5eGHoY+AHSXeco5RMrBBLSFBhNvDS/f/8xztKSpK +FZEV2mN5RAvWy678JKD5oiulikqxPPB5Vt6/zAF5h8QAViwmn2tSBpgXAzVyp24B +IfLv6BHAqAg2nanSZrSesixHkj9+fLcYSM3XZhPiQuIBf97mAMwv5xXRjbxQ8JO4 +CnJBarBBMhwjEvxVDLk3I+dV5iMRs3/XB6lQEOke0FFE8ZJSt1zYyzsjImHrib9x +uNQMUxx5SHCAdclWF+UyZIADdAJRFnz20a6LDmVDk38pFQUCe7WJeCz15rfBBTwH +ko7h0UtQpj4ENwu+weavAo1T5hcEGtMD9znaCzJK+JDjgSToe2SyWoBPTbRDAncu +4ShhmHRNgj9iLSPBRcPqfsAudfQVE0FHQQmaFfzSUNIBXW3rSjVy++LXDsZACLkD +VQGy71qXuZV8QBwUKnQViF2itL7Q6oz2Hme0BoBdcsjrJ/szZA4e266kXXNDCQmR +eOCWniur4vdSu+abDv30y32W4erv5i1Fn3n8z/2hk4sj32WwSHBrFGDoq5Jmp+s6 +IDkrxjoZ7tzAb/AK0krjNv7K4wIDTQfMJA8vT3jDAnAPwcgFp0QsTKdqo0uxVVo1 +dZRdDlVZKthcSW0qNpXvUZKSkI7rAOu4Qjq549FO96+TlhT7VmX0QSv/rnQ8IVmN +XuKvJP4NcLNBnLbikrIE334DOhiYuPHsijAiXUioGPfliYq1/R1yMBYB6KgfVuHJ +lbSdOqaXEkEI0myqmHt44uL8+XMdFHJBF8hFeoY3m4ICskxn69aDq55vn2hrtBXz +wiA/fhD3hfZ1pIom3bbOCAZIKfAu23wlcKlDrm8QaBZbR4x2ol9ZFYsWVfKbNyYs +EhvVBsduIFbXwJTifmvbCr9NcgAUhYBYLEIP7GGbsNtUUTonczulMLWE0mmKoY/A +N2d3xYI/N9Lrc9YQDwvvqkWxUmGXQvOrq8P/DHr6MWDG3LdtSqXKXRAwhtBEM7pf +GiPNtE2vE4d6sWkgBadrZ67oBJJN8INwC6++ce2TyV3Q/9bU3CCFMFeXSWVeuyWz +7mteFXQCX7N/DEVBxReQyTXNuaUMPXdTiAkGPn13jycMIFEzUA2X3aiNb2v4qdiF +ufGCvCCzu1z0NJJMGzEkKGsvGle3Ozx73le2J7JsSz5hU2Tb0Wy2X0HQG+1H3JxA +R+dRtVjlVVJP0jhtc7n+gMc7UYXxA0EVzrnEZgnKq4KfwlSEY69auxQfrlEG55Oo +YfMrWhmsConRnwGsygDQhNYPNqcY47zjS+FFY6m9G/3sbQOOgCtohWsKMNt1lRs5 +ZAmgJBsiNkl38KjlL7UCM/rtrptsSQv1f+s29O6hnCK+79zaliSVDWl5i+7Q2wX8 +7UVQYpTyjxTGfGe/uXnS61/oWPOqrPpT4Bt0QcfrneX55hztGVDtbl1k8ZV++f9e +V4Wthj4q/K8T4ADvSEvNDsImWl3uLCenlsOqGI5RoUx9+DH3Gc6rNkLausHrLWsV +vXVajncUuIY/MuTxPVwu0AktmTvICvE3DoO5woA64zFKa9gUT1g9qQwX1q3vVIeJ +M5pDEc9CZxv6hEb3YJOaDnNrXaH3kLzITIlmzaEONN6mcWCnSCgjgG26XrAVl2yG +NlzmG6llnf9Vx9bqQoJdG0XzLoQAj3Dwz0dt+tSyVVFZqdcWQn9f2eKE8FblYwjP +NvU0d6BUThLAfSe9qZcSx93aDbhN2awxgpn5sitS/nH3lqbX//jY8ZstScEv4Dnr +qPnEQLsVeynOy/ZemGNqvKMtRPgDM1pE8LOZdqySoWh/pxWK/c5NI5TkzBjqXZsv +sOsArRo/mfO7d1GW07e84cJ9SMK7PBTPnxROj/IfVnYvPtohgxoLOhfKStG71pUV +r84aQ0MoSuFfJhhityQfHbqc8yRCYiSKQaI46fufQTRbMLzbZVX2U6u512VeNGo/ ++m31Y7CfrhY9Fu6/zDgOvQzV9NMyNy7ekWeA4t4ZBaMVQl/oVEO50zwemDqcQuRQ +U1DgXj34kRQAk5DoS3hA9fknNHsQvvPduJpU9oT847K1BnCB+TTm8LrBEI6NL1o8 +8Pc+4472ZwRXDiguFsTkouVHXfKf0uOFNc7stKrrhqVeFkAnBSGod8/2VfvVNoVX +Ev40NWVEy/izcNbhNs84bgwbKrkUjMSHVydxBlILyO9xqzymen0JbQIeaOKBwdQZ +48s4VckJwYUtf9FWYGYDoVAC50+3le/US2rYhu5fY76PrVDXc0cw1MpcKFuMRIR5 +ql1/WIRsWcKguOAIBfZeBfbVzorOWaH26xcncdIDdSJHQjQ9rPh2pSFar7wFrGgt +sQCCXUGEDH06Fg4Nq3/l85mLNvkEGMjtBaV8xhE1vOuG9Ep7tSrR+wwQzfk6SRCW +/3ZaWwfw3e3vEIwUlDzZS8ZX9CWr5ix9awlRbKsW/KawkZR84oEnUZ+RzEmc5llC +ipr2pbhLHyw9kjKnYNEix518faz0OzAeXR7y3cRYgGWLvEuqAeOxIJHeAItYlMTv +9zjg3TEjt0XUbO7vlKXdrHzjUYhK0MLjnXPDD81mcDu9LKu9C+NsDGwhdi9jgoYs +1ChuAoHRrI17TjThcZyancR5QYWpK+zqDz+qNTEOQ4K1gTEgti7RxOlbfBAbWK97 +SIX4hM7OmnmsDOgSY4nWwBo35ud8CtQNnVaFubkYQQZ3+ngWoFOXV4h4VjrazAsV +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +IzMcge2JRDduYI2DRh0KHkEJU4gz02MPgjc2RDBL8iz3Dq4D9psMK+fMS6s9Hjoj +5ZInOPXpv4JtjohyVclxBgY+dsuotOPanGH2Cb+sLKLPGTEeosYSIfKzGmKBYmx9 +vQe21qVnWRRwWBudqVwVSVSAWLxLEV0O50OxgYF/kieN+2hl6xZ49mh2t6tcpr/9 +crcndWhYLWAyZdPl/f4agVcbX/g1TN2rDAAgR9DVuOJEC/u2OdTqvN85DqlD100O +ftD/3iDyjNM0Xn17m0UW4rxBJ1qzAt6uQ9Ccpl+HXf3Yhc4vxe8A7xtgM/PFZpmN ++MHciuZ8iljRLcc9QByyCg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 5088 ) +`pragma protect data_block +zC/xYWcf8zZCLGdo8fvzvA4Cfmo5QeWLxffNdB3fNO+IYm8qkyUydAEswNf++htr +w8/pcgKNTGwNYiX2SMp5GoncPUNcJDchplQdQex/7/4J4jcYDjuh4wLgma7S8CZz +63E5aC67hWhvcwipW3G2YMDOiquspOg3a2LTeAoOeqYo7+VClRWJWxATAeD4GJMA +pOnXzDjQkhiS9f17weNENLKUJfv9vy/gT2k7UtRbZgxST8Cn1BrUhvAp0G0YrVky +HOZiIitmuFff9/ElSy6EQ81iKfmcsIJCEHziYq1MIddOtZ9fod/ZrdRGfDVEZ/KE +wAg9EsdOjvktPzTIoYpm//kjBveL4CnbEW5H6dcKjBcx1GO3MdmOy/380CYKNq4e +dGBQJaQfVZeDHpib1Qpu5k02ZYYJtOV9ZQY1Wb8yTCc22/WvFYUE39kUZWAsF5Rj +hlXyfmYy9h4X68zy7DMn44DwS93kgpVqo8plYlri3y0v1EdMvurRfoXX0at7hGXe +Eq1mXTnP5tpZ6vPRTeWlwDqUpPZh0NVNLqhpItjHImnCQIjk3sEBdMVb474JNfvN +R41ap+Sn0s9hkPRElX7aM87ME9ugdQc8y3a4f/SrdTqjOl5nSoSwMWhAJABLfQrz +gLvyMP6pCvQcWslCHTfXzt90FoKGW76+c3yGZtK/OBbz727KeqzIH8/V5TjfmbJl ++oqgtpIzUPNFGAKapbiJ0TyAUNmJGGn43tSvbhd0FKrrT7suSF2EVMIlFtZCoX3c +P8Bxs/D2KJzHOHmYi8VVOoQ6DP59YZe6ptr2uggvwGUWlD1rEvZXeZ3vOzm/O/2W +UEm9cOomQR05sX9WcADVSvkokZnXH7yHtmA57iVB7UphRxi3leme4q5PQZRf2APJ +iZG3+04Akd/M+GUkp3h970osRywFUN+2M0eLaZghSAMocMa6XyZT8O5ufaP/c0vS +6gOctr8czd9ILH1xFv5QIBfYvbVuEj6NcQyObkQ7gGRl8nQ2XN30qkgRrZRlwhwc +79pE94LOptDN0melwE4z6f56wU33/eBm0NQcO9LOud7HXP4fEw3u2YocoChHa5JC +p9Wc6DIti6ej+4NaQ4wxh3vlC0CW9Qpqgv18MHTAH0S6zQxkvkX/V5ihqN3FdCMh +Z41Wp4BPYTZ9fj8Nh5OrJpbQdin0Ze0xghUNCv+HtKhoWsTi9ctfbvsxa9gQ7J4j +Ma5H0ZrzuvWrS+9IKoLqiaD/g0pE+lWmCm+dAA1Kzf1SzxQ6YYHufPjwYXURVuS+ +iQOGD78/c6ErsTF+wb+9q8k0Ef+7V1CMFtI2JQo8oAvJjw6XfN9y+gMBVFaSSNzY +VVxXyd7r654nF6EFecTG8o3s/gtKyzgq1Za5rOqb2Ze4NW1kWAdOEdKWL1AJbNM4 +rQiQkmJRC70aVnVJtwE+lvo3BeAGOXOR4KrXEUtKjYtuSVEQvot9W3P8TjFKxmaB +Gy7sBMQJUntX5WakRe9dTQ4zMSSEESbs71si+u/KkjLeMxNRrnWC5MgbZK/xpoVT +ZBEtR4bbFQUKWFf+wfB23h8BX2DwWyRan/tS6yljsvH7i41r7xJ2/wgHH/nRA547 +ibW1GGSLWBmvyrMQzkbpd4LpmFEJZyoybUNxwj1Orf3t45Lrgeh5jgoHGPWu16JY +gXdF9wNd5DzR/NRjqKj6zcjc7eEYTKIxMm2ndgnZz8AYQhbhZW8CpMfp7eSM5a6H +JmrhlpwqxIEUOHUZRyANREGZfXxFUvJu30WCOZqqe1/TjgqYtNJEfl3X32y5iJAz +xbVGLjgYatfvE6/Uskl/NxzQYUm6JMbg0v2B7WuAPlzJuOUzkOsw9BcpivBLpBaf +Bl5C/dlK8d19s4pooB1gsr15bhprNR8LqeDwCw3e4ItlzCNJu4kiMBXZNg05r0XV +pMahF4VgFKbMa0MFSdQaCsRxNOY3fpScFRdPaKf69xZ3ahq/N6SpKRGVkwy+KfdX +Sf3H+Nq2iOj1PQmkug/dK1iKTps110AFUn/mC/ROHKdbmqlpLW/gM5a/2zxj3XJC +Jp/3XzvuSeoUl29NH5GK374FERJ6vdOsGnBi1R7Uk2i3JixeylUzJ8lZGt7yhWX4 +117lZq1d3gIodecR+Cv3XFwmOkaePp5RCqOSkQhpeDyESXmfnG7rFtrNBEFYz+6Z +B13x6L/qG7LeIsVA9QFJNfpFFf83k2TwG1zE4vaJTwab7N/2UvRRpJSBKiYb+omH +lOMuwRM27NLIZb3LI5pe6T8a+6mfqlVFGLHX5V+4kma8CqX1E3EPbu1jfduYz/QE +4dvg8RW+5VEVy8YdX7awN/iUVVDXJBb6miWVLWlvapa9vWILp13rQU4D3Sdzn77e +oxieY6vPCtocbT0AzaqHap1iQwHvPX84GgvFN80Ejuvq/rJ6+YHZ+XwunX8/hThy +gImPZXCa4Oq6hwil72vQI+SmlgUZoXe/KRS5Kb7veg30sC+61vHwwmwbmpL9xpy1 +a33pvU1qJl8hX47U1LoFG5AOaS0bGdtJUtx/eqRKEHzxw3Da54/vk8adDQ2/Il5V +Ptk2kaGYMIFadkjP47LIpqfXVOR3OyCL0J3kYH54D81rqCkSpAEBOx8NI9izReec +zXut12B7IquWIe8GPrMp4kQv4EEMvBcsYT1e1VBnbui85mNU2PAXHbAfLm2LeZXb +rBdXQL5cfgYlkgJD3YYOOAogH6bzjDeERAIUvzjo1ZaJToqa/5+otymhx0+V7ZEb +6eAfvsatx0/6H+LlOnAE1R/QmOvekqoF4uTjpOCrWXmZG1u1QBwvu2k8uc3hfBAV +09KhryYDm01DAoJybu2aRmPnUfr789bAyVNfh3U7b1OW8/OV28tAzmy7UMOa4WZp +k2+C392MZ+T/IyJ5/NbV+pRE2i5mBNH/idtwpZjw6GKbUH1z8YVtcnBYxrFofb4q +sbnQjtre6o21ojIk6US/k16ssIy8fZh/NqLB5ygXSLEGOj/ksNcxPtjDOGL26f/+ +UBPCWJlIPvKYQzQG1NUyAVfXC9oO8CLvNx+MXAjvnWO0BsgOeHrejoMu4Qg/ZTEo +s8UE+3fzjrxm+qdFIci737IBpZhukLPYU3RgvaIxnJpNzqFA0HSecqcMb9b/spVG +kcmHG2XN296QApxiKTVy6o54NlDDRRZt5G/Hj/sMTKqfeg6hUhyYU4hSy7+me5ig +7av2iSsO67wfiyi2BTLgu6gVYCesRiq6fn6qEUqrPeQLAr+6mxqry7IuaJ6dJSo2 +nXPvH9RofaqLShdDoMueMyZ0bZxDDbD8jzMVBhvEDB9H0t1bxmLBlfRyq6SZejKV +XethtgRO1bA31FC9mPig/RgSMKsrHvCAz7DA7aqhBIAyhA0H7Ox+Xt6gf8lIxA70 +wHOci4fs1m2/MiIrXY/MB7dpoK7o2eyPJuxDXp3U2jQhHamklfzlu4fobQ88tHcq +h5h9htUwqXGYVplPMDFv8TSCwazSSFg9OBykImgEU5HQvWzAVhXV12oTvLZt4FIh +RDeBeB13dThmW+hrEhKg/AxCXFsBjXArpHLAtqsByUS/mv9E+FiHr4/gZEpOX6Ou +M2jQX3bwTBe9OKFhz0uFjauWgA49tC9nPGlSonxaSG40G4m76PE6tDOxNKfrxe9u +XWU5TUArWGVrKwi/b2WRFk6uB5ePix4VBcXKCyWcO/ieSaGk85wFOlKGdgatmOI9 +xURrf9uTqaK5Ml1X4WWXG2k6CEoYpAyzNS56ytcCQsALNU8TBa1tQkYcKuNxSJwX +2ZsC2PlGHm5atDHQmpvGolTH56g3RoOXrhpMsS4w9ZvkK9ScCmWXx2akd+qBvYti +i7EsnTlhPJ0WhFwZPePxgbDU5dd/ixOM0ml+qPj1xt6A/4i/9jbkGQ+AkQaNY+4H +/hEManBUCdJv2f3YOUxwXwlmhhcq7RbdD+wRrgBo8ek2R/FGTCMPzKPgIJD+7cm0 +USs/kYMDwCc70I+unagGbPWIAypZM8Zbd/lRqZxCAnm7/Aux2Fm1vwWNODPK5jAh +i0qEqymbUDP2ewUT13mzxzDshba5jzfs8mQlQRl3eDkB+nOOHu66hUrWe/FiO09r +x8nIVtSHZ28yxRav2jil7kUl9afSXrmMs6iUE1ZwG/JmxcL2MjOvMhUxjkLTy8ee +bNefgGUiSCoMm153BBf2KF8Xh5+F+jGTg2XaLfJ0ehryjwE1a4IwZUDIXur1xOKr +55qCR8czixRsNDtziAxmX++d3Jmt9XrrcWOFAxto9SL6jdCXCjZGoar9be2QSe14 +36Yw6q3pwSx2uJxDzysKYfaBsOVEMuGuwm+KpelTzaH/QuJc7VQ8TEsD34Sw8awP +L/Zj+mGoeZ5HtmyQVFIXUVDPd8ZQlH2sleiUYQD1GwMIvkIBNA1ujdARJVT6fW/C +o7cswuu8qxARojABI01AZUfZhHhrni+xMr9LTxBD3BMMdsbeqgMCe/DLqf/kjqQk +NxahT0dYXIRCs5bvk5SMbZXBNdH8GhnZ5vZkO0YSkjRhco+lBx9ncu75H6IcGCxH +dEpc6kbCAOPW9YPVvtvrGhdnjc0V6dAzbmOSjOoDH1V18uq9mNV422eAIQ5kbENK +zyAl8te/voKW2Mi8ENgoe+6cDLyEa09xQNiRijhLO9fUwd/8oRpLEuYLMFcCc4Pl +gnhiAxF26UhkH+8Rq4SjiAF6sWk5pwW+48JTVXTbz5QARsfc4kdQH7Y31rkN8HLL +vQTVQqgJbquNJhoweAcN4dB1hrOnk6qodd0yZZizi3zGNBP8wRp4n6K0rM2qwBzf +cwcNFJRwA9LsqbrM8lEhlfuz6T54W/ar+OPYw7ZTM4mz2yYk59Zt7UFSzoquUPRd +Xd1ErXaxVqgNfjB4z9AhrTE147Y0RP5wZNmoU5XamH7npuGTLRw3L1BpKO2M3wT1 +J6Pwtb/eG14gGVrgVB7DJpHYfDpg5QSPUjkkFMBOxxbe1+jXUlMRmhbcK94m+BeW +Fy1GQ+bEJGXVtQ+EteKZam/xUj0cdJ6CzOSLqpfM6zf+/zdYT0mECoIPYio8MNZB +mtX+QVh+/pp/FM/u4H/LTrqPraGZaMQEfqh87wRsXhDAynlkeW2ShIi/GmaRYP+H +NJH3h6Je598+wSG+o/KFX6/m2OfU3ZYakRrIYI+UBT6+qI82zwctqeZzL2nZvNX6 +3uLUAP7aHNBjddxOVg+9fG46+VHpqt0kMeCKDXXyykeE/wT/tqDzoiXHgNbPo6rq +yOh9nzfyklim0Y/mVBHcV+wsrdeTEOJGO7sjs7hr1HQQbPMuKZamzbbLBa31jE5f +dXK1OufQbyYcnEHVuyDMt6wFMqpCtjdZydJYgW4lv3aAm1wpzhvYTvfJatjHcxzo +nbhqAkqCvTfz1w8sCNyYy6Te2wWXPhYfj0IIJxhjzKJWD6GSxBnpvXYgPtOV+5xV +HHdHX0d0PS+ECPBtkooHM9vSyNmIV0BOnTZPmqLYs5t9jJHDjEaRswEv+2Pew8SS +LcpFL5Yq9009tkPm8EFiW6UElEcXwNmI77GoQgNj01R/q6H2a61+8K0oX+8kOJ89 +NuAn6iONzSbCYdy4OCnRDvfVFSIhC9ij4f2UxApAUVW+F0K+GoiZN1rGUcNp3pwn +ZlNbwZKM+agp0fnZavSG4rPMQNo9S9s4YEtqpUzgUlE0RIw41P+w6FFTK74k19cz +lIDSkMB0dILeooXzRm39a7dp0yT6M6X+YeePqRh97BE5hdg5PchDVRauZrhU6q0d +265GeDJsyCPmDqcrbmQcM2Ho4WtCELCkXmX+AGLxZFOYvZ8g5IiEq5Tec5xGDgK5 +kLuTw3jXZwz5oVjRkgJtz3bzhHkSrBr3wAAAjtnBftYOJvpMtjNeqoc/aOE58h49 +b/nlxDNmQL5pjm3N/deLApaIFusruWsP6rVGz8UnCMJfMVP6PLpCrjkNs7fcO4fW +aCDyvHs+/rYZpaNwnowx8gcduXeFcROyV0YqVX18Ul9pFPa/bZ8Fh/Lc/j+s3/3J +ABTvD0LwxDjZVbP5ZqAAgxsxqQOIhsLEqy6sw5sYM8kYOyqLk8tW0S2Vpetz0y2y +xujsOQ9I6Oyt9CroQsNJAxAErHtOmdUvsv3DxbhP2gwmb30iUHpYE/95IS9oZzO1 +2LOdoAMT4f435yXesIUuMIwYXuuJ86qtGRI/S4TL6ufDb2V7torh4CTzO3sGS2hY +Hz3bP3Ysn9jO5AKR9M7V/VRRKvt8iDfltZHif9Qeb4Clrw/r+ops1X27+DdnLY+l +NEU/KsVtRxAVBd3zzUK3mKAu019ODAZc5Zk3js2T29lWKTFwVtgFtPyUQHLVygYy +l0hfIjYQL+D9JGsU3J+zqjWeLkvFYHc1NxbtItInwkqdjBUCZ1oqSOvSf0eAoPNR +yFmb7f1HUauvqm5IPhCtle9WhKWsEjmMwt/Y0N6hY76TdO+MMmGz5hm1OrFVRx0K +qeZoEyB/a0HM1e17CobGXHUMGd3Q7mPBY8xTpZLaXgTdRXrJxHL42S72sVYDX9sA +k7oBG3ZpGjZgAeHCnSAg5Jj6K6cE+QLuiN86LgN8VeU4rl2WRXf9vBZupNCKyQft +RIh89JYJw+GADB3mqqvVa3VfqyHGX7EJhfZQZnTZmi/Xh8zlPO06paKUuMMxW1sC +3fgJspJeiOpR18mX5ZaEl4YbUshQuezlZoq+xYKQcDNzDLp2kkdhYpzFFWCKujTl +Dh2SoorAIdX7uQOrctqIukPHX1VQuH0NjaIQXcE2DQhK1xjf7HNJ1X62MuwTl3jK +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +dOPtwFtLMcPenaEyGyZsI+s2xj0m2PnKI0HIO0J37nXu9s/URaK6vVkiRIlFAGEc +jCfFmEwDYWhHhdcMMJEeZ4UbEKbS5VAoryHReu51Guj5uwrM85BA53UcCyiAZeLI +EdS3yjfRYJaaq8xYdFrHJ1KpIomCt44AcjX5LRkSbA5prRgzbc/21AHDJHFTEfKd +39Ax/IAlqD3WzO6qUtrvrSaM6Hg+cHV63JSv0MOKYpKgTCPKKoIOvv4+PRaqitlV +FIMIGL5XFDxZWTuv+pweh4TnT7/cGMYXUnBczH1SdsfG1UB9U2S01SifaQbG1Q2v +OupVr/2wpDbCfxGqLmdxhw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 5664 ) +`pragma protect data_block +w+3Ys/3cYEzxgh6mGd74Nv8Nbh4d+haY0IAO2kthrTsBC3lR7Y0ILXIGhJsCndbu +gyy4q5s3MHerBwrCkrGfGh91QNuyQX8nns1gNNdnp92ZQyVuAPOUh8lqelgvZMPx +LhNafsi6AC/pv5HB96G9z4qTfKzTgeDy9o6ouTA2xC3equpsYNOzNvzj1DrZuA6e +0M9t7HHkpJ+gu2gte6oxiLWUB11u+wH+7a5GBtYqUQPurKXuTrcW3mwTzfUSlK1q +cTKXlgrEneFaeN3zMDi/jTbC70VquuRWluoOdK1Jv2Oqtq8iYA5RgE7jWlu5ANh2 +ul7vdV+ZclnfkfuCTK/Uc4CGNrDP/IkfRBey5fB2vO/vBcpOLBDxO9LpsFQ2ayjX +7Y9yk0qfzXC85NhVX1ntHAyRveZ+I7q7vIG/1fq2VnsZ6qEFwvYVl1vUfSBIDfoV +1/bWKRok+bB2lvO0HfMTcLvSBlBIEu8nReLCAKy1lAiubnN0/L/IqQecVIYEwuUA +qR+eboXO1k+13UliJgcQRWPpTx/bVz+JOnvXBCH7arny9LdOiu8hP6rl8WZpEaTW +8OYNCtUDsoqz7q6ev3TdJKmpas7jvpU0H6nwkHGwRZEvSLt0UsVG7M8IXjAqbj6+ +TLsFHk/eZK92JqTtk+hPsK2D6A5/IY8W0HiF0qwI2sY7FC0XpJocG8v2x0Y2ovJQ +pRWjzujc6WnF53gVRfWfR5DoXoC1s08l+u1nBPxU9HXM2SlchJrcIbunavEXOvB+ +OplrbbmLTve9bIiez9AWwX+qfitMo0t6SGp45zpXScYuX/W7JMMe013T70xd8raw +dR0FmWrbU0r3aVgr0D1XCVikIna+CoTNLtUJ9ChiwY1/PlmLLUvAX54iOmtxs6pZ +K95sq7j2URGqBL525XByVvozU/vd0tfwvVIsz/EaRsTWdMIXItx1LHeJEX3Rh/zo +SMEUz76ycpZjz8i2DT2H+JaFihvVZsVlkSMH7/gYxeza5hYHGc3YZznKs4WggzB+ +46AlUEUlo8y2SEguP12jWxU2XxieMiSHwPhpWf+jJKDi18+bMU7/lPncjPO/WJJX ++mR60y4oTmtk88j2106mzfpLPpHniq+8eks4r6Fc6eOUHaIsCH5xnAq4TE56lvWA +eDuNIjz/N+sVC3WbPVQcT4Tn6gso8t/7JIxeVAuGGUMRBWEayid1Lr7AZPOFlUlg +fBffC8AVD62X8JdEb9ohTTtDKzR3Tv3Isod2K0z3MkmIdVPN2bc/M1rmsipKXoCW +SvMnaZnnKS0SmnySr9RPhPKdBzifOcTbzErzLeLdDTFPjajeJfPW5uPnPkultxfn +UEfk2MsKDA/i8/XCledhoJ+7n+kDxnEaIwMSBLTWvS28J+mRTE+97GxkrlY50PZI ++dAgm4DidIb46R3WPqZc6FOPidOjICZ/gMgDtPpB1U1+kEFIyu8GTVdAgJbe4u5D +QsCwXPVO+cLP1zb6e0uHzM3VA68PSZ+OQn4xQ8HPg2OHpPonzBiEYV3Kc6DVdTrY +MjJfwdmYFx1HK+0mCuQpCpuWq6+tvGQkcYRV2WiOzd+m8XO3E9MYwPLY3iQoQk+C +ws9EwxUHMxjD5ZPyrGhIQ3vS5achhP+08tvm4HOi2ldqB2WuuLhDDqw+3knQuNRe +BzCeI53ReL+ndEJeMVIMx1w1TDYA1gXN2wzvBtGqSo0CjyoDLmHymJGjTBark4yl +zECqCAK+k5ucNinUwVEXHwWQFCcCH+7ERHbwgxJF112RaXxpKhudax9HVoRV2878 +VBzFZx9FqLXbCBchsDHvjnQD9z3/jW3TsMfLz0jiCYqQBCpJ6LAv8px4sL5IwwWQ +n1K/kS7e5vI9SPgoru2rZ47joUCFo3mVmNrLKe1W6/lSvImRB7yDt5pqPa3D7+5f +3np1Xx4RMflNmvmCf0d+gRaNqh2VScEjMvpC83d8FhPE5c3bDZ1FUuj37h8fdsOl +6pQjtY68OnfeN7IHULQOmvVfRZO5IsURwtDFfud1nrtqYjkuFh4zz/MmXnIowPvb +lTryGMwfPwws2Jnp6tDInbEoQBC0Wl59y5EtbFjwscrVxfaSV8k1xN+0LC7h8GEy +ab1elXauMW9n35yrxOJWzry4l3+CGtaoPFPnRGq4W6xNjl7xNdRj/JAuGRU5n4J+ +SfI8h1VsA7xCI//URP5kWdUmyk7PHpGnYORhMhyiXQXsIL8EoUy3YzZn2nkwjha6 +zUy+P5dcCvMb39WSAkkB3xPfnvrxepjVD8WdqAms2RGTrrbLIVfYlsjN/2DjFQVh +zgrtrcLqwn1v44DYlYxZ4m4Lr1p0jUt+kR4O8tOGZwWCq+0tp0dsGgswvtbJfIe7 +5hZAwVej+jv/wjvhOMHip5Er0RHUs9CSg9QTV5wDAsB0Ne04WG1l2Rf8mH0i0WL3 ++LyI36jLu0MNXOaeDKKtsx7eJrsg6vAfIdlVbb/YW9RcUU0Ly5cHZKDSXxY4yxDC +10Qmj4kdD47iK5hSWObBjTuIWYyqtq1gb+kvcnc5Syn7oqI0V3QrmOMaNYbjY77i +6cCwMJ+by66EkqH/w85s9uEMws/sUHitlq8e0UUI84uQTmjeAHuw+IVkhAaJkTjC +wRh9NFf7WYyq3b0B91EJAlDzlc5XtTgEBHGjkaMPKsFXwA2HFdMJCIwcwMKyaSar +lCmsKyai+xpTFeCvkz99lKe4g7698ZWzkOSpJF5euKJRN2B863t03KDUtbAsDxvK +/XuYNpNR34YYsDVAw6TblO9w2gvP+XvNMRm2qQqftb7aFW3/7cSXzgJ9HwPbliOh +ou1Fn1V4mdDVttHO03r1OMAUE5BZw0Bk/xcDhuPG2aPpteq4ckMMbJHNTGeSrNU1 +i2sLrRnfkV+dMXvp3pMQ48+buz7HvBUBoFFV4giby5t9kPUkW12/ZYk8x1BX6BQn +3ioMxAfjlUsxpp+Uk2PCeKuqi7B6OaeOrJuU90s4W/EXjwE/HCw4KyxhPRgATGYj +AEHJRDh4xzm2qj10396SS9A4e2oIbQ7cQ8NhnZPRRs4FD/tnxccheskxZwuQFyyc +nmoAvwRX/IZ7Zh03Db3to0ItJ49v6cRdR2MoYcaxEi4gD9VD0GxGDVeD1BEhJ5z0 +QluHAuK1AGnsKb/SrIGk2a45Tpw7kl24PmmPFvmr7R8Kj6YgNOjKCoQJoVY7S88E +vCsMBI5HFlPLnrjYXUIJfoZNLDgCQ7Aba7V+lEUQZN5xeecA5WdWjj9gPUqnszFp +vDkICq+ISLxR4NZcIo7ZRoNpCXTYNmT9J/kokFsBcYJ+Hh4Ci6pLGnUb34eSsjA9 +jwcIkHgqFwTwDFUv063pQ4A5d90L8PrP44j0DGoDFpbwq+uxRFeQsjri9K5Kuqy2 +nR082Q7YIXOuYiS+fS5nTW/KbSUHdTPROgMDS79CEOv8BcjJW30qJiebQCzGIIvH +HrTRTm/EkwKaY42ThxcHXHON7S8wRf0v1N6m5zZ6W4uQCHidsX5MO2ojRs+ULM4H +KZnHnuq/vJXPKaB8vEQ7v686cMKp3r2hhZ3/LbQ9YBJ2oMmA9DFtEGBDeDccvhFL +ExSyHGCv6eLUiDp6xqS9Nq8rT4b8G3ZyPsw3giLNQySkzhnSbRZkYaQEOj9RnlRO +TV7eic1bW+wPwVQvQnzDsX+3JbXY5TRePP7+vTNh3mxFQABAD37TxewNGyv3vPlg +DfDODufBK0j/Ni/6USVmxw7LYX8nYxNZQ/MVS5gWVfurJCebbT4+sgoDVZp/QvZ/ +S8aQ8Jaj0ZQcWLIqGiVKr9KMkEB3g+b7DWYfXtjsizDd7QbjsJChERna2dqQWR1u +TgPiTVWpkteXu7YOOAoHA0XsXuBZlxZPR/rgLqrEOAo/X1FEia5FQP5R6go5TKM7 +lbAZdTT9C9FzflFIxhnQ/73J8fp+kjNnwNUQi1OZ5vwbI69vC6ZIe3+DWwknFNtc +7Xl4Jjf4vbi7QSZ1RM89BNJnGP/x8h9ySc7QK0nrn4fOCBL6hFQ1fdHL2KlW75aN +3Nzqyep1ss/bvDQhov3rgaKZYLqYCfwxP6DFJvm/KwFADF3zDsnJi4GN+V22Td5f +glb6dF3jV58GmXe+Q4uTgAsSVwM1XjOacFqSBeyAC0nLq+Wz+am8BiiPGD7URMFP +4rGX9spmmZXsgh1Mnl4JvDWgCVsM0Ap+t79bN8RVsBs+CiS3bTU0Lbp9XMdou5HR +qzSnONWZb1AeY95Qg/RwhQpDZ5EXm6dikbVCaEJNIRP6El0exhSO8FLKAC6vxdnp +pxG5X9bU65UmrFtDMK6crU+OdY+8NMoH1ULc/BITdGQfRgDK6EMofzFKOYTKbCYC +bf6ufOIgZJ+Hh71tCKBNx+woEQ0ExvHxS62ZIJr2/OBZUWGQ8nt/pqWlurIEIgzD +fe63dQJM+wDHqa6F+jZxvk55eftDYHaMcPV7burO1X8ATvDnd5WwAd+dsFiiNrWb +NBNnEEB6fZNF/CHbdyeBcW32inNdPH3PqgjJ3KnFFCJs1YbBsgSmV3UcASCPpYY5 +slPN+ZzRuAFPm35ZG6QRQFVUQuRBVZlUIcMcowBcgQed+tENxTx8XXBkzSzBPUMF +/POF3ApseOu8OtklEAG1xo+Q5RA6TkCbsSgzOxyuajIE4r6Yq6qRXZ0jOmlid5C2 +mzJtr8b6e2vTYhkLGelR4HUxvH26XkMF3YtDMKqKFma4JNGuCs0uLYenaf/D7djx +qVgaATfOi7I1ghAybOQpYZ2Vg04aaZiGuoEBlGSkIueTYQZmyCB8zgB3uco/+wCF +A+2ZyOBZ3U1UK9mqyRGq5bKqko1z0Af7/W8qTWiIO0n0in3gVJPtwv5LxtBYbukB +17afh7SzsFAjbxWl7ZPw40LYGj7bBMTGeJVLWjdFpQ7uuyW90Yo/em4GoEu6PX58 +TKikPGk1mqlkbIjPJgi8zX95OnijmY+r6Uy2JP9PepqICiknispRqnwx9cpuC+Yu +cQExQorioW0pm2FUZjanb8ARjJVdrUO9DKO58a42KdnRVILsJWWLHfi4dxRVFHnn +XtqD/cvJiu8+szekvUWBEQIMETTE0Ja0SKLyOjlnzJRj81RE3DxYgne6F3H7TOCx +Q4Zj3cVFvKpMnBOWg3eWyQaanQTS0Jq7oILwmY1KXdObODfjzgYHhZWSqs4iVmtO +0DhjkB0EnwJv9FhsUwHT1bIHRwFiYLCkSvz8zSZp8TLaTOl83rSdgxXp+NmwTiFq +ZJvZzgw4X34D0XWvyoqcZZWdSODoSx/eQO8xRnwaZCGt9exa2G9erTJXNIVjL3pK +SYeZ20+HJEHMA7PI5aRvvDgqgSqcm3Z7pHk4veHHU0PJRNLP6+Wz2TeTE9DdoOq7 +bxP6L3E+jOmFQHn3hhR80+Eisl1ykClkzX8WzZD9XLmQ8vOsLaoAUpYWzkozQHfi +aKm0rPeBXEuaT7gNAUoVoHGmCWgUROXaRKTAsNZkvslLGSJmCHS0FzSQfkjGbzi0 +vKKFQw8nId7CtrLk43PvXjkkcz2CvqoIaZX6zDhLHGMSax5yZTJAs7WiELe9u4mq +JhCAI++UPZmVugYOfsTYYgbEZCVejprKwWKF7t73nh8TM2DEGkeYAETTv1ulS9Q3 +z2cNWDd5CrOoZkAv0piJziG9S9WuJAnZukeVojBl2Hy+ET0IYQ240Gqb2/MZO1jx +s0X+gfplPJWQq39qBDWAj+5zC2oxdNg8BRRAZvmb6cPcFMnnZgNInn1IMf600wAG +8f8tX4Z8RktRep/y9/pK4HjIBcJrm89MDdhVWm2R1rq2A7U9sv0e39tjqgrrbbAi +2h0tk7N4GlPvh46aNHzkH3/SHKIklkiL/3i+51MY9/4W2XKsWIdpRfudIjskvxVh +KnRAiSWjI/J779CU/3kjCUguhi88usTDcqL9kzM6SZUu4apGmED5XSCu1XCtBQYD +5HrjLDD9BWR2okpJ4BBWNoAjR8cVn8iPAJbH7cIvsfloDXhkg7lVOXNz629ZvkEK +OAH0qgpR/uwsGS+jC1qdTr004ENMtnjfgM8D0jCh9F6FJlk9m1afzNEhp/8sF/k5 +QB34Gj+ke+YSpjxMcA275pD41u2ZpfIuORTokkdfYHESplsRwnnfhodMWBw8IQbX +2f6HqvWOYAxNlRhrG8/g4n/kv6kWz93sQX2B9or/maluYq7mdex0xYUBWboGycnO +4NpElQ0MBFT2W7805K1yB86DhF42YnBe/F6qSyBT5uLOLG0/3fvp3s/7ASmxmnb+ +z8pd3swTfNVsxd+T+xr37UFWbtsV/qVXzQwBEey9oFHXuTMlh3eTJ+NYtm/v1kBF +nclMrqzO04BLm/2NWLndlHHJOFhoZ8I3wyjknQRXWQWpqpWNin4hWlEWmxgc9BCn +Px5JSHlyY9B12SdCYq8WtpUBGC9Z4WhLirC6N4Yw0I1CwRuVXdr0KocdStfS01RU +4syDSSdBBZsN5tFAaCwnKL2V91k4914KkCE0FEEKqzmt9NYBTQGZvCOUjSYAlPSJ +30+JuE9H4GYaGL6OBDRc4WyCscnqQalR/d/UyIgYJsLamENlLAK6krPMjnIwqCVl +h0Ds3VbyBW4eArItC0OT7lEO3tqkgaz0Y51azK1OeSGW3Lpp0zL7wB9tr3OBkuDa +EzjMuoIXkIvk/7hCc7rMI1W/ifMmqHfAsTufICNyODrPNQbcZk936CTu6lpkG9jk +XYcX/c5jNRzF6/wK+fSgOesfy1C+FSHii7NOAjdyZGQ8kJgEfMDJR9NXaQhT4H71 +FMVXFOCRUyLND++EbMiNvWeWmhGmHgyJe5C+9xpwi+MtBu+J9UNAnr/C26N9IaLf +4B2n/mZ3F7yCLEWiOFk7S+jX3/UCisaG8ABc7BAbZ4RRLn7dnosraiohVBiWOmt6 +JsnR/eluEJW9cCNe239FP+sVb09Lb7zQ/SyPuSAiE3nFuN6cY8mQ57K4M5mD2BuP +cc7YwPIQ5otEyTjH1j8F7B5UlNk0prTHrwp4NHwbhlDKKAw+AsgDO4wDdYTWsppZ +XVU4jI1veAF7+obTiD7sGw3b5tEi7R0n6GnO4GBEc+tdYEtMHmxza6oNhZT23541 +hCO3EWoTZfUZUpVCGv1O5wCF63roWIokx2EgMUDmwMs3lQV0Uv5sDrVYb0KL2/F+ +vAe7xiacrrSYQTzhc6G1ZmsimtYfnIt2urO1mSb5FuPuy4JcGzOrWmOSqVrAuZT2 +xXZcDkqY9is4wmnzDQY6QBoTtlecrGRuLUDvmdA23yTSqwYr36XZkAAoonro9SAv +PqlLP3pUnIPHocFVo9Ud0CjW4m1nXdMpIWApDUZd/Ic082VIouTvr1tewFXMor6L +qaNUDn4H1OdphUzx8IwqOZAK3rSGwNyWPES4aIxxr2bcYsSnLT7xwW7NEQ/mbHYe +Pwl48lfAWM/525m3HPsYu45ch76Qf6OsMuZrmVIqUh5stjAjvKjBC5Y0wlb7HXIj +M/kmPOg3del7Bl8wclajmR9BAiH4f2pVNvj6MeGEZ4xjjUPiovs6IcYuAoDtyP82 +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +0EdYk8u9EcHvk5jqhjgohDTjVAeJT375Ef59f7yUuToa5zLARg+3ZhYxjn+3f2+f +GHrkhwUVyhyqbT8WjkrsEkbFOY+QQi4ZdA1Xj4Z//wG+fcEvjjatYv48Sz3YtuOH +QUP817ART1osb2GtW/StscEKBvMutLk+Snqv3QkHb4ev4y2y3KJtwzYaBBCh4HP3 +fctt1g52yiTQCFtcd+8R7WACRO21cZs0IoR+ctw1Kbk6yZBnnIAQYsMlvYYUNJFr +csfS25mNE9ui/mTPN9AcyuaJ2FfdK4erHR1Fdbr+BAa0sKHxg93I8QWo9O3iRy+5 +kVk8iGT9nN7Mv+IhhkiGAg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 3504 ) +`pragma protect data_block +EpUzHnZQ6MFzwaYdo8W13JVbZIgyghggaxTmb1JmEjhNwkKWhkMMC2Ks++6VLFEk +wYduO2xhSsY68DNAiD9BSCQO14ss6qzU2Qfp8bhG3qdWn4urrh/UgiT3LtrttRvB +WaDtTLoU08YRIi8SpN50pbk80kg6Q+u5OiJrUypY8/MCOE+A7R/CCyUX/sE1N2Vz +MYYc5oxFcnxfEvrLE48IdwDnImaeGHM6yJLyszgX7jq9rd+oo+eDcscHX9kbfoRM +NlBdtPyFUfkBHHI7+FRP7Bw1sqf1Sbs10VmMF/dS5Xtr/OlI1xfOJYckdOoRTino +ADlKD4tOg72Obe0RIXKIrVf2ogd8yZNkzcKqLX6Q8W0HBW7Sa3UL/QVw3W425BQq +uZYwmiNeyU8U1VP4rHQO3bl7D12IvkxV+AQPqmIOeYg299UEXWIFb2iELLLHaLg1 ++2c0X1N1Gmbs1aMtp/2WxxS3/AdsDbi8rsgAWMftd626UWTv6xblk4fmaTewH0EI +3+LYLrgcBVO0hMXXA9AEtUhgm0MO8idEPDCZUtmJEn67VoPNCo9zfXCfwNHICIZk +UMSs+J0ZkeV8MGKV+GSsZ1hGRNWculxlh3ck1jbvnTRwaohoG05VnH5Y+U8fpRHv ++qVOSV15H+e1OaGVVCOzjU9CxwglwoT8gzJ6aZ5Ed8rhvqgEXXUhB0fkrl+chVjq +j0YrFvEpTS2f0SolxVXc3YkIeiW03j+xQdTPsZUQqQ3L25fxZUaKMX4zlnRoOg6E +Pdnck/34hCYTlmLzpBC6lZQ4vnConKLioSwDyBX3q1zji5lmV/v2N+1NISVRkOHg +lk7Lp3ELDDtTSimEVwQsXlXiH/w+pzq1RH8gD4G/DgrRqt5Xg68SwiP5sFnqLKo3 +YJY80LnvRacrgYqxdGcM20XZTgAbEW5QIlmQK5CCI2UhaLpdcxedeHJViIOjtt2q +UcjLFONvXvgvxfaYTn/hGHwTllTc9F1LtNhGq7Bjk0BNtxABSCkAwzTobNufbDiL +VhEPF4Jl5vwoALSxrMwwjXk7T+ZHZ1mXixw5LK3NIgguPjGR4ucHnVKQHKYO+jZT +xhov7ZiDB/i5oAOMs9mkvw2sK4HtdxZRAkUwfDguhpLog2KY1TUk2J26H5QTUZiM +Z4pgvD94KYyVpGTuSFVVbKFAqtF4D3meT5lZiUD3KLFhZQP5bcc2V1FWpwoqiglx +H1hiFELCOV3eCjKBKIr6zxeExCxZStp9Lc4d/8//fKYCsaniUFCvVNcWPviou0F0 +VrN6F7ivv6jeKQpwxJTqnRIr+KGLAtjHCGapTn4HF5/zt61A82QyUjvWuUTfHMYa +gjXGw/2jdbzIQH03ZJ/Q1V7zrL4wTgJ6lA+qJmybllwGeJZ9qQVNGANAl6U8q+V2 +/YOI4RQZ7pn5oo+GHVh7c/nn8iKvwIvkHdsh8Ex8dRpWKS2faJyDeY/OEYf6MntI +FBb4tPULjWce1pkAMsMOJHlfVg5fCrC6JFR1do8pCNGRiItB9nNGVCGIH7fEWmPE +tb3Il6BrViT6bQWYPEVmtOLFk/8Z1suFb/BXhTIcRuIACbh+ltqrMc8Bcgsw44WQ +vqk1/88JsgUX3fhhEHRo/G/hABLoCDsoMgClgyUMdDm5xAeuKRA8ucIp+rJ5gigT +uTfFquKKJIEnI1tfGO9Y8d1K1GvLWfxlS3qZvAi3Ay5797cgWW+T8TzwwV4qp6Xl +uw6+gqxvzA7BL56QRTMx9eFukl62up1+l9/h0IU0AUgsVH74IwLGuo8yxP0oRTIP +v+6IzEFNa//Co/U9ZP8t4BnNvtWCp4igQjWwwnmNyUit7yVFSKYdZ4VHTtX8H/dO +VudR7B8yN48k5NnsHZsCoYcnCTwsYIWaZota3fdvtFfrvElyyaatxf6SzvY/sO2w ++lhEHxdcNW4vJUTHLdHYyc22oeO3mqzGJ2u3MJAe9b8140gK+P9CWKBF0HqfSzca +Bkiit284wt7cpxNFUJc7Z92E7gsXGbcG7hZZAGtRyANhHNlqPNm/OqRuPt8Kz5vr +sLlGz2gvKszxm9oE142ayYZeEQp5m2jZJkDxi3TZoL+0Yuf/AMrve+zOps/WtnNn +8+9CQcNx5fwj5jfQdzYjZ+pv/VafnbtvkMkuVzq9bc1923ijmXYPPA8UFtNuPe/F +kKo3z/xdRsy9sfETeJOZmY34KBIMnajB7CisFM76mBhd+4q6BqF+xx03RTjUSLvR +ATuGVl3qmCqw1uXKsFXQYdAWBMwD3wDgW0hoeVi/zreOMQVEx9MXtpZKYTURPhtP +1SfQGE9sZM2MqcLDfwhJ+fSp7+liA4nvfyN/1GITy+YGtPGXrron/mzvreoLqjWd +m/HAtB2yHZVNT9EjxsEdpZ3coRb9fIqnOusW1iVm5LeZPP7BnkRQIUIyLNJcR3HJ +kXyHbjPj9D98GFRr9QoCMljk+dD7ftGvXS7Rdpi0Kccd0mixKCQGEvRGTQdtWruX +LuzLymiFNd5w2C0V4YWda0WxYBrAa5sM2BpThMSFtQIopN0DqFAUfAAAX48E6NUn +UXLIeVb9QxHm3NQj1FLijG/K/S8WH3QMDDC5Yn2jsX5qi3GmHQXzbogCMx5yH2V5 +Oo7YOy+NhN6WV5aWJsn7HFX7HnOtECtnRr9mmEFJSdPKzcHEznhVS2P5b6MVfnNS +5aza71Zrb+I979EMXb5t67uIwPeGqLKBqBMprPR8NJHjCcvjo12yWDZablCgWJLl +ei3tC60rwu6oZJCRbKeNavhnB0uMUWSQo82h/9VGWR19/BLk0Qq294FNb30xktJH +7IECsJ5JvO6kg6uzBy5Hys1+q3DCa0Aj7x2nGyK1Gv/kf9EaI/lwrCFPhR9AiemQ +x+YfF4YX8D/ShWoWeujEREsdRwsMpnFTOMd8CIbye0Mrx/dhBxh7FbUO3WIH2ZM0 +4O+07yA/hwdVzS5tP+hT/BIAApL3TOvYDYMKOrLE8rlEGsjtL3lbX8aQJciN/7MH +ugmKt+aShUMoA9nXqeEgdjAtSoGay3rEQhJnM+zuLnrWVx6vfVnF359WpUm+at46 +ksCZnzM3UFHqUW7MoMtKnz80adnaONPZZQvVD4BcSqeCXV1pk1nMeSy+AuXXA61Y +1o8OLi6ijH6Xz1GDCAZ4NBm4uoasNT9PPd9z5zckLXZ7Bv6yLceIJtJfG1wSIkyJ +SAIxxdgEGKQbdBQ7IDTTCmJsBexAaAHt7+jR4sXRM2eW3lQu7uTxtJclwDcBQkRE +VgHXUB1IYKBbTCFkFssKkV0KdBpT3xyl40mzvtR8HHvorfcb8QAzsdVPRHoG1w1Z +1SRWwtCO/kIeJPGvK04ATG8+9QL0v0EYG1ik5ObuXguL950JwK3CijvGwZLFQ+D3 +xoYiwxFIob1fLIovO+91wltpwhbNzI/+B0EnXt5EPkfME/IsLWacKbxGsJnF8/Kc +YMVoBnLPswS1HkzJb0JuFFRdUneqp2fR9zJpiVesOTN4xsOzU2ApT6MPAKbaMFEK +/0M6yREqOJp4tEDo/Wul1EWWshtGZK2cnQ4YQxm+x0gH2WWSGxwnpi6WvO/rwk58 +MBYY9VxSdtItP6Yc7T/JdnSGa6m642IPswZQ6XzyrhQv8aj8UGj685hxyoGNDCHC +GT6IW9sNDcv6fgTvadM60RhdpI7IRgyskkEwYaqaiVmpu8uKG8V3f2xDb46Cfiww +XpOQBjDBCWQ7i7obuiCbYIDp2fRjDMcfGO393MXv0EqXqwDtHGT77+z9ACsLku3R +go7IUzHfxw8QhIoyPp7xb5IYk00gjcUOuJ0vzei+dY6HzMIlItHjUbDW7gQ9HCUQ +NfnTQp20rWDgEVkRGOJK+OQ0vayrK7vGdVohxKbDBije96ZMtQV8UnYB08QBwown +fnSIOyQHS2oGG9nOZTQqgkuoeUNa/Q6Ka2nIBx2CV6BK8xXGKDboZQ2vVREezub3 +4qUbVR44KwWQKFcYvGnDVf4QdeyvAL8r2Rgan9ijQOXbBR6bnnEbxf3k2qSHQ8xt +drEVJ9LqBPlwpLpNMBIbsLR3afs2THRL/GLml5z8P0GjUQQj1RofyfG45imohCXg +OdXnlrIIJqsI/CaV4AHwmArOyXnnTxCd2vfhRlJTEmFsvDMPobFYXdAziOG/749A +Lp1CAP0z3s8cPDpa4fqbIy3Stzkc1HY8aW2G3BiWU0Vf2A4RX5X2Pp2s1Co0B4q1 +ve8UtMMZXRwXYfZGIvq1RoAe/3/uotb/KbM1SvvMMY8tVPIg25Dqn616jyFJ3qIC +TJIrLaPjSF6YumUrirCkv0pPp7Um2mH2r3GOFdReM+TFv8kosTQJa6Jk1A57sVpF +zPCrN5Npx0B7omOSu3Z5NK1SVE8Wn9FUvqAoy/0waleuDR/35asisYFl/u4eOYO4 +Uq+54IxvLydKUrOggJfyO7vM/opnx8FG3KljOJZW2GArClk7ZlbsMa/iW9jGgrgD +pdASHRe8yF2LxbsJBkV0Y3irZgxRLP0ioUDnmcMYsI2NZBCsMpFT0ixuIw2aZvWI +e+atlpwrMq89SKertbVwncbLrUmcHUm3VRSjGj7l9oAiZHJinROODBx6qEVO2lvJ +perN0+ZYYJC5v+qyWIxbK1NFDEHA4gGtkmy+AcBOhxaHkChxp6Vr/dVoDCggfCLn +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +M8byHsCbrDGyP62CFo8IvTM3Ae5RZL5oFDkkznIjOqNMKx3MfffncMeFuVCbvra+ +Kz6I+7iwc1Fcj6DtkGGvxA4S/1nZs7iGAAvORqAF7HrKRZSfaVC5VZcuRSJzAH0i +Aewvp5YeFpmGEMBrIU4gGOOXU3vOpMTgE7Dg5mf6LqRWI784AXRaAJUNUlNSUHeI +IVbnj9YkS60Jui0wZjzP8PZtP4/xXmKdwe+gXbB/RrDoDgMx04/CnJYEJI/w+bEw +++9yzzLQxLrmwBIQWs2Zht7Nsmy21fpn0sEMQ1KcT+8EVhINv9qF4JLHeDQESCHJ +gODTw8hroSy9hCWlIflMfw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 31840 ) +`pragma protect data_block +5thCRcC0Ri4TQe7AWgUIP4KfBITUsWYD6kXfm/H/v583HctLMad7k5VlJiSTNFJs +I3SDS4IKr6jhB0mmMEd8mZdT5q2wIKrzYjLgIOPB1BnudVGS3efcTZyhDkY/jTLt +Xj/bs+iL5Kwnv4Q5SwAo44LWb8eo0VlSKEKRi8bz1E441x/XSEXl6u8zoNHsbHIE +nwTEgTZf/qA+GMwsbIm8wkywnuouG3R/RWz8eFe+qn1dsnKA/ELMWjmoxPtfvS22 +SvgcmNhTGhPszoLnENkuvQ9jX42/yo1TwH0/VhxFZdkPTkh/UbinSkQqTAyOivAd +mvKUzqJeVnAOsBrXW/SPKaKXXufPJSG+58DHq/tz+YwJBFca3LXxM9Q7ViQnwU2c +wOwgamYFaJevCuVnFeqRfMxJ0i8g7iEV/YZqzd9tTwNOo8ZZAhJz4joDNIOUs8Na +T0SvVkNY2XjbwZZjGspP5YrN29HmzdnU/J5LCTcHuNIrF/dV1SRHmp0HCcpnm5c8 +/43EUzQhpRWLb1k6LnHllDDJ4mpCQPw/b6SSczH9G3uL6wLNjyEjjDruWV9UXh1f +yiQgjIppRrwi4JLzNLuD8LFd+roEmqKzev7wAjm+fS6/zVEfqI6grgOU8g8NYQWS +MVbeJ+zyaSZ5gobSoHfGWR2POS2rW37xxVzjBrT8ekxskUX+FAh4T+3/AZhd2LeH +1blDIb08pHsxt/y85Id7Tma9iCQMJFMwYLtXDIO5JY66JdFIjFzltd2vnAdB1EIC +mfKw2GNfDFWVueU1SDC5DiF6TLddfuDDvuoKorZzlCYsychyWBgtWyQMlnvMqLo2 +zNW5CWAfDmGuxKNG8+3yoGuh+HrX1s0lZWicnW44TiVRETZ7BumdiBLNxrkvn6QF +SJaYOZx9McszJUKhLezuW+R7GmFOCGbUnBXr4V6Q3kniA2P7dnbWq56aAZ/Jciw3 +YWoSiNXF/2fyR7GTYJDS0zr//MAfBTClsV2Czf3iGde3f64v3g1tXUBzwTJ9aHS0 +xPmbzUOSnQLFp3mi6hMSmyG876dqs0ykLPa2MVcSv7db8pBsM5n3pJVpmfjOW+mY +4ceS4+4B+Qyj9RpNRovmFIaYd5KJ4DbzrxGsEyo8+fKypwnFmoxtLZksqUQwLFJw +3KPPNuiSU05oFXe7lsI1/NJWGGtuUcmahdxSjVcY9TrfQQNjqzXoX0VQanSDQ32c +hyUoY1psuTQPW4uHLDbB3XHPHcDAmi0ZsJ6p9T5K4DbJRHeSV1dr77mJ1C7zZHj+ +EMLc+w5w6N0Hd1u/ZjwgNaWiHTKC+UrUROFuJNZemb+dCwgbxgeKMx+jlXLAWY/r +ZG30qDOFVgvschkeIqEk65njkUBGottkfCJtk8LBsmjRnXxsISQbPqc8jMJuNClk +f+xFd/+FZ1ellduD/Za0bFlfqzuNmUpeLxTLut44G3NbWZ43RzpCxc3R3nH2e+N1 +OM4/WiZgCCTE+JcXroHio4BqNOzPVyxvwZte1ksS6YVyFgYd0mY+nF5NnHuNUY/D +gtPW/KS8QUamCMHDllxuMmWpi7WBo1dmg9SsZUMzzAAXiT2c5mfw3cGpe1vYV02w +lAAmgbAPnkuZzRl7KvU7eWCkQaQHgBSCi4es/Zj0kfI7CYOLGn04HibV5ljYlQgJ +UVxvsioCT/KyzMDzHOst1yyh8FDnin8aDorJPLM+6suJpajdijGyxNm8V8sv3mgK +JsiCJhpHfuwY3cShZEXTXy6V6/p30LVu79Lxd4ixTMQIIdJT6j9LMsJVe3uP10WG +hADEhGMDk5unCOZqhlHm5FeeG1pHUfrAiBKEgBokph8pYPe1ZdXgtiZokTLFcZwT +WmHSo5gY3zyrfJqCQ4e6Ts4JBcnXMnLLltAicHdWm2l7wMURQ3NIMrHDXlUW5zo4 +Dc3SV0MSYVhq+qkYocPOKeMRtVOtpWFuMTVp5yPBLQ64FQJqV97V/hvTTRydBUh4 +MGqymSyuH40DyxYfuFfeIh72zlYfqduk23SFxsteQdixAFX6Ubb0KdfrTSxkXtzw +/3u6XSK09YbUjGQJzxNBBnIqF8QUoU2NV3vq5a8ZR4s3/jyYXK0WLr+IcZA5V4ic +PmqzYayX0S1n7Yd8V/8f4kTU6fmuGEKmd2+GWKuSQQIcJH826MBzdSxNqqPQiYPn +2Fa2myNlqXCNF5JWngpg359UUDIJ1WB70VnVsB189c8qPnSEGOeVO8VNARGTR3aQ +56vGri85Br9wIGWSO1gh8nzmUVuLwvvjQFDFDG4DolPVQnVa71KnK569HY71evAn +pr4rM++p+yw+6akkLQT4aFk75QB3mMPR/QJU30ww9zC9Fzg2l54SJZwCE8Ojsr5n +2/F81txRkBIRS1SPcF23bzq5krReOqruLNydL9TksiqqIbt1oOnw+C/tIK+bPrHr +rj1v2QngX4zYQpv25BWCCDnWWo77MJ42u9m/WCh2b+ablSbW21hOxrKYHdFS/VWn +b8wFgQgg0J8sRsK6jhWIuOVnn/thuZGvCmYh+Xd3UWL04v8Dl6buPRIpoY6AmTv7 +JUgFcO7GJ0gytMY3n2ikIsxdTN1Vy53ifWhoPQ8EtXdrRnM2YvYHEWG/E89OtpIS +U0DFuQ7HUsOGxqkhUe/t3Jfm/BUJpJi6wtY8b69zIZc44wPR99mqxABnE8FMILG+ +R507cg2aNP4dfFj/LK9W8CsdWvqziTSxiVmRHImY37MrOjWFv0wFUrsgIr+upuif +kniyiiSZ837FKLsH0zhr3+EEM136hk7KSOCFbs2dcgUuoL6yCS1oxUUxjeRpPIkU +zIDY7sWjVnsxrIlfcs5YgTXq00uiLNkSfIHcW6hA2YzA969b98GprtcUjKJcvKP+ +WUPwB9A0NA7Xsr9RtT+35LQ+0DolmNfFqf02isCpYR4fcEcjn9NddeZzHrIFvrDf +e3fV4nUn2aelpURNJiB8wIrTXILdOJAVpDRCMz0LbY3kmPqxrc1Iakqy6zCrMxTH +KeM0avCVADYAhIU1B9KxOojy8LkHSn9PzzT5HF56n2+ob38IqPgPoslZJlxWVlpO +GmfdotVKfS+tq24dovpeLxemFqoPpdmftjmfshCnknlFVaDeD/S/fg5/Ioek7Is1 +Hl3fcwkLSEVZ2Dmn+6zTzgtNvdh93v0RmGYq5Z8bxr0/MkZEDvv48CYg8PQonk8P +WpfYvMOA5DtJplnX7mtqZ89HMSxqiUtzQYM5ZQabjk7Xd4ogvrIVSe3wzhIOf09z +ZYec+GetysUS+AcDmgbzSHbb/WWASymdqHzA5xMIKKMei8Tu7w1K3M2FxNjY+A4c +tP2mM+SKTVslHhmuaJ1pgT60J3UwoaYmmSYOnZPcMXFw5AgvbG+113/eOcgE1asi +ORAVRvOlngIVyqqRMMIPIzotytK/7eseO71dE40jlfhRrHN62WgH86/xNOxYxZY+ +4Iox0VAummI+XGbD5Nq69EhXabh/0zIERQZ5i9x+Nz+OKy6BhXCPChYA1F/ap9zV +ztZGOD+njsmxtNn85XybG3su4e0k5FLbrDTq/fxyRAEcJ9Z261lllJPDMAXd140H +rbWD9mx8/s3w1pfofsGAsnOIlpejI5aQy4oMKrippKxrl6ldMsAjqyoArgGAU6dN +NlotvSIaJxwG9/JSfPoEH0h3nrpFG6Sd2arWlL1Gn2FpnNTku4VC/gi/sQnT09C9 +srtWzVpZLucoK7LxxxM5EGzV8VyarLTeqkz/iep40k2VsG7Xp2eK+DDv1QmRcBBL +VeFlr4l0UBwSpLxKcJoZb6yLVSMulbKnahuillyeRUHgvFO7mqSBranfWirBq0Mt +F+sWRmMyRNmyxN8puHvtWXH8s8c9/7CrDHRQptAHSxE3bn7hEFqiEryvIG6UgZvJ +/kNnK9ekTBBCDAtq+pW0tKcUIUaZdnkot3qOch81g66dN3dr8h9n3Hvop6LKbVE1 +nTlszHAMQxMcZ1fDnD71wkNwM/Amht1Y+rtKsYcGqlR+8bB5poLQLK1R744SxyXj +JzldeUtoJV+sUH1Q4Bq+3UonOmv3o2hFbZNZR9Q320c81Vxtzd+8DP4smBFX2wvi +X58gFKOt5q/I0reCl62gicFBHkQKENpG18lMjRW7SCn+asJYcDc8Un0FnZy6rEFY +EYyciybtkArY9ncKaS0ssOSvFzL+spTOwmo55SzblJ8K2avk27AynDAM29k69Tyv +gFNX1zLr8q6OROW0ojxFivzlOwW+XM4UjiCM07t1S1oYVQw7Y9WiRs/GK+/gl7Ps +bPBKY2PAdJDtdHlwTKZH6kgqFuFIj9sKcDv5r3kkkVuAQFBrBuRDZKOnfZeGPvkS +K9sSye08pefXmZC0T9CMtozpOrQRtzD2H8CPcbjp+tvGIk54gLYdOgS0A+WBh3fO +zUltxuqwDLIJG5m53ZK8Epdo9LWXtpt+EENlGoj4u6omNxm0ntmWlltqLZGp+wkO +S+btU4et2vtVVcyvz0sHrQoyhFYnVPGamuvoWUa+5Wnu9Jj2wgXktNJpI7EWUufw +VFaPkvBOgzkv7P5m+4QMWI1Yy5pcMIM583bgVl1rIm4GaMekAeBwyUKfImk3UwpF +LT1mi9VgGvO6gRRorZiErdjpUxO352ESHnwtP4h9Qzys8neHsZLFENw8L24zh1Kk +DoiolEtBrv6IHjE9Ua3Ky+ZU5kbWzy+QZgKd2b8j5wOqSIxEdiESIRbx1zIH99gT +M8hPj57R0EH9zCALhss4FjcaFF/klZBtYgnXKjMJI8RWNECU+HWZH8YMQoszkePw +hY7YAxCmecnsqihVndxe65fwraR9WaoQZ+SHU8fY3Jtl1uCexMAveh3ewwb4yHVm +h8YzN+42DasOad3hZMOO7SUy0IimsNqzGHwS3HeHlz3sDwgjINeKCQOBATgKeGit +bpo+k2sc23FAgvyPnG3iEFBY+aPqzI2T232JanBELNWStqjg0jh8WXwka4UOJG/H +KhA2NouEqeXidEVeDFgsoauKOED2oeGKMK8rbbvLfhka7alLsjJ8KC4dUJiz3vFY +py4CXg/S0RxpkpSH6tySBJuZkob5pBOifapKmpX9FBwj3FkTxjygNkmhGjNkfEcx +qbR1S+PI/JgUqXhLP/T0M1Vry3/AK6EUMtE5MmF8UZ5RfKT+8oaLFFwjUQVcwpT8 +4T2hwrpZCwdO87z1WtfiB6yJ/0Ho0d5HE7CakHmMjM62lG6HaZbz1lWWyuW8gPPS +ntZwxPtP/fq9ijZ5dtrNPatX2K9G7KAyUyZYq9O6J9v4IrYqIDCr5o4FdpIPaJvi +7UVGOKclmYw9pukAFWPJWu7fSaI3e8aZAuOX1eB0sTeD3NEqI6NtWYB1GU2LylsK +R1UbaYpLOKsl34DFTWT+20ZApp1+xzucTlNQOIjgH/cKUNSadqhtkn0iYuOlYZHy +P3dM8ZhGohbRWHHxhyDfC3J1ayBU8zujRWD4ROGM+RAGOCPRm1Ifr0FlVaZfTQkS +w2IxTt3JiKwjBXUR8dsAVshhneCHMAYohed7CV3Zgk+Y3XRhHW1spF03kA+IsWPj +edrSlXDYg16v3UlwxOTdzEksqNZJZOgI2A/KSUmxBG8O/gCHax2RK8mbIug/ITam +B4NKo4LAB1ByNVtmm2K74m3PR6BAPiOc8i1l1hnoheHuTyMbzkwZssWQ6BebFEf4 +nZyFIu2tHUNN3AsDI5wMWB8RMbsWzk9xGIxcOh4hveXRQ/Bz/IrNuBY7eTe9o/lu +qTJ7SaWqeV6+tcL4dH4sqaOVLAULCaz+uVfI1yK8kVVey3k1CNL3S1CnvmHf+en3 +KzEFusS2bTo9WVmOSwwqx7l2sXB80aDfO8F6UNNyWaz7Wdb6Y50FoxkjJS+KxY0H +fYSiFrXiIaIZRPzIzOFWiIgCz1QRwvCZQ69wANHEZqomU1tjrHK1ImYEucrwRfLr +tbp0iw79cYN6nWJSQR9LkLLncQtiy6EjWeBx4ocDN4cw3Xd6iHvj0WguruKP5hG7 +Jgm7i1yWlu6nXyCIye/5KCIQD/VaB0vQzOQuwMV8nPL+ms7UMC2HkZfolz5X08YJ +6V0QdQ7i3RzR4c3FozP5sQ+y8OUQQ9Fu5voYGsewv73uOfRLqDs/9udondPJMeXx +PcgLUCBg3lB87qIQL3tsAUeLZlq300DH9D1h9Sb2PkkAGSKY/t/fpnIjO+0ZBrUA +Dfxv0qQjDliO4xjISGFfmCt/6sg3wn7dE6xyVSFCxPv4NTqNgoOCSKmOOqH9EdxB +7BuwWote+OZvowYKhYKjA53tRqdk6G9jbSGgcPXOuqtZulf8jyK89OcNBB3Tf5CY +Qiv4un3zLbj7jkfcqDcjx4JCNkjHxDvaumvknobSy1Vk4bfsVqISLG5vDaJ6ACIV +i0Dig4Eopo6LJ+weRnOmEm65pP/gaJs+LwX83lv81G+kEvTQpSqfuLqY8I+YIZtY +dQBbuJN5nMmfSfYkCUOTL4ecmBIGvgRzfCJMxA+/hWsTS/IfRe06qpxKB5lLPusY +43lYd3hu6JbY9zlji/+2Fbqy0uZCaCLE+Tkl3T9zE6HC/FbtVmxXm7/5E3xYu5bL +wyVEIVNiOeji7lx+zC9eFlSngY2+TEcLzsvV3dOA/zjJYYKVIKhnSW/KU7Iu/ViG +VNcadxZSJDx5kHgJipS1EwSRAniba/Qhhu58F3s9q9JcE/lnBah5n0PSaWKURr9K +kDo1RMz9NhC+S4R0NwqSXznywa+H89CSH+0Zy049bRO603558tRxz84rXZ53VkoI +tGEhxDpgBRXdudQc2B8+Xnpe0OOINjb3T4RfOmgruhToCyiZTi4J16yrMrAwjsbQ +DhnLFjC9M+nqT4heRXwAdnk+1hGuDroY012jg0rjC+MqBKKnICovNn0KODxg4Zgc +psQpJ2yy7OzzTKd+t4Oj8eBX954n8uW27REMh4ukpNfA420WGAVSjaRUor2jLHa2 +iUd4C/FSE15zLKspBETwSce3w0izwG3DX+w18KCVW/GsC9pasGsNPH5i6EPk7fu8 +2mWYdyCKST2NqnCSTo8vxj1PRl5H0X5sn8lFMyG6Y66Ix/3d/eo5Y7QHkLLiEDAl +EMitnKt7Bbv9UApRzZAnLsHhyD1GZy+OK1zGOENPCBPZTxv5XQbZGCtCxxgbQNTw +gDyTtVAi24/5ddxjoEVjmlbNCK83cJuTSJ8u5QwxQfqsNym8qf6jiwUvQaYHuJcX +HOmQiKsXGVYU/CxxK8Cbf+kbVV6/vd+PIUnW7GZT2I+FrXjAXpVTc5vgOKE0Rf4/ +QtVjY2UIkF45FcN8+yjDaTBvEsJWb/iu3f0gNfxjmHWQMirFcYSGe4OhxIv2Rrqv +CrvNR8ZXyTtXyJ4RkKWieCdIQept/IJnMGIhE9WrMPIaXrQi8CWfphDo1n4CYqGd +2sv0swUe2vieNygY9ob2vi+B3FM4baOP8U6giOU9nUYVspDBSg2g4qaLfSzbad1X +RvwRDtzvmehuV0yyRRCqBWpAvCESsCRy7S6BYC2pikuAO1EpFum00idaqeezSgUd +HGlf/WCNC4XG91AlGEyYv/SwRB3JfBFOfMC/GKaCNTAJ2ptYY4b6atcnVHPEQSUq +8pcf6S+wvxCZfupD+Y5ZEt0eW/+9z+FZn4IzU+tUhT+NQ+xV0qiW8Hv/bmXCYxor +s9PrCSkkeTVxO8YHvmy9vhUBb0CypOS2pKtBl/QqJNI+Ton1ohFMWclrcKuG5FKt +DUb7Kg2vji0dTAFoXUkyT7ZlXOIWCcPmMXQRIIPA7jlXG3Y5c7mrHlvoii92uYeu +1Ej8b6Bwq/oLaPOOe0dIsREOYkzh8cv4Vm5x8N2xexzkNxfoYxurQfAmOJOKjHFs ++K3Owo5SSlSmuB+kuvQXP6UFCRGdNgdo0RVER2MpR56MLcfq1VBSrONs15kq6LCr +3K3eKMZhkpr/XPsv6A432xHfRgRSPpdJ/XB6/scGoNKYvEnK/JVGa31srGTL/LyT +wrA0SM8gyPQQcQWgzweaq5PE8EEmdfM0sczstPbwzmwfOS18/Nga5vsYpz1xwqJm +RWJMJttM2noBZcP4jdJS3/A1ODlXhOc+vk8TY/NXtdZwQD4LNtmqR6CSvX44HLr8 +z5RgFLKfa0yJXOP+N6u8dxr/a/rOjhpjCQHsBFKugegPBzUZBNtYi+zqCfLnimlD +JI7YXFngNPSp7rZ0bNsGoTAuJXSbSM3qwvQRxWSRolSkW/hKjrByW9MInGM6fsWA +D7FPKuRhm4M15pwHBuZ2QuIzGoNz6bwrQMvp8/hqH7AmnLmp5mxrA0hrHbl0yjFC +szn16lc5BonqC0vxKgq+8MyMrTAQ2o/sKM3+ktT49K96ZD+7f35Qp9Qz2pL3lNga +uX3fsmpP6NcDQji3odcwHkCEILULIP03QfgkTnq+K2Xeg1VUnrjkY9/Uio3IZNl3 +LOydtQD+H1abKMrDRF3+p5q8wPYzskpMOjibcBgdIRt2KyMkVXI7dMYrr5qNpHpo +6nb5/OOTMZhMhzEO0rGwipilFJugSYf3RgAcMN+KNLyj77vuxWIcogN8DPvq/kgg +0Vc2e/oxKgmfx6cCZgCZ1aEwysXHBVGofAEQ6MjaAH86UDAJsfDUC58BYBhqzgFH +Fbw24/8wC+pnJB+17yaaCAHl9ejptLUHqXR5mvsRazGw1ik3saWhdiG/o46Y3JRF +QhpDGhaO2EMDoC4yrqeApGkZa0GZ9S4k4Qv03vFNEK86A0tkT7MKBmLz2LFU+ZTP +zWrLmip8FPbEL9Ga3YS0/Dnk4vVWBI1xVJW5o+Jmxxb5Fgh1zyBhq27Hr11Uq7eN +E5QUT9+5JHYEBT/hok8MX4eNDlewi8fLkk3tBVL0rTC0rsIrqvM8X0PpL6KaKI+T +/FF/Uho2kxkcvUpa85Bsh6EX5Kkyk8erf4+gAVFoh2MLHi+gNjvqkP/O8uZnlZup +YEM6kRrVtE6h5mAld24Cw1DjR3EUvtWsDxhaThkOI68d1Nu+I4ZPsob3iHvr5lHC +LoBh1PwezM7UwnTpySmjNMG7iLIlF4kVS+cDihZaMyxx4mU362GlY0BKTX9hYvTU +Re/3LmAkhEjdBDnmt2bW3PmtlJqhjy55kdqqoNfkdUR3BP/6ImiZGAzrnQcMarom +CNpxTIuJzHtjYhhIh/d0jEjPpLqmjzLQ4bHRJ1D9/ywBOJPnOUAAlEO1Gd3ktcoT +UoIlY65wOIF1ogswXrj50TnOw1jPDAubX8x1iu6YXEu3VWJHLOIPK/5HWqoyuJ9P +RvVmKbpyM7qPgf+osxDM1gfNimC0evkHu3XI4rBmZF5yUWkZmvoSjykHMUaPn15s +iT8dVsivcuPgMI/d0HDJkJc5kmeIEJCXD0p2ROrSssIDGla6Ur9bk0FbI7fTxm4s +OSG7RgCVPUyEUqeOal4NdWbvMSYJHWrYqSX8pmF+vFZGc325SXDwtW9x3byWiOr7 +DnEehT78Q8Qi3JvyzeTLp1xDF14kxRgtKr4zCVhbCHYC8heWN0nWViJqbOBwxNSf +EP116VHvtABeBqJTrCEp9nEspUb9B0XOMXNH/pFcEbTD3qz65vfeXcRiL/iOUOaw +vwr/xrsoHF/HnjVCb+GSvswVWqr6bGcXNZO9WOg6XaQUX0ib+k9UzFVFQcTuHYeF ++hVCDfvy3UGZO0gqwvFodYTqNqbxIbV8PxbmaRDuDkmoB7DV8bHMuBkisB60TDQN +NTLM0Ybf12Tte4J5kR5Ry8VY1+ezADhJK6xWRbs60V3uI4elBJE5eGwTqwSSCwDs +bGLupiuqEXMG3GFZx7pYw8NyM3sZtPZpCG2MVVYMPyCMt/8CUbA/YegRgpj1WvKn +vQ9h5618BGzYNilMt/CQ2jnjZFEho8Ger0s36kwb/SeikhyAyH262gMQndafXirQ +2fG++S30kyN0doREBqf+kcBAnokBX6jsg2zQRJ0jrCICKNu1u8jylSaxjQniMVzR +ffoDYjt9kdqA2Mnjj+eGHQ088XfszYE9IH9ZMgsp4Zbn5oY+HgsvQudO/BpYz7m+ +i+wbG26DoElZNPyv7hdrHfALzl9jlBqSmv8fbdb1R2kobsAIwXIldO8/2id6LCD2 +E3pU65rdbR/qcYv3SRaheev4L3De95qfRyiAtEsRDNj+ZpjSC9LbdLesLcHAwbrT +Uu2qiCXF86aczrNan7N3h4KTbEQ2jTPBCHSzAHrHXR3a0iK36bM0Tz7DJR7jk9L+ +N5IWaxqy1bwXmSbQw2NfyqeWC/IbSculVKNALzlBn1SSeiIa6+JAOWDfo+pH3nFi +h5I84BigY2xM6sxhoruo4a8tP5AG5nHdNOMBRq7DlWXPI+1uuwx2fOry/aOQXBgJ +XoJRrO3ARmhC5L3Or2D3mL3UwQ3V+Enz3IYG+kUSFJrJZ5yxi7qqacdPpLfVXmUI +SX5D60ULPqR6ZKS887r2j1inqxpkf3L6WwScfBRnYXtQg1RsO76ceoea2hHeS4G4 +gNS56oBV4GcSP/xhFjoobiipdJVCGqj1n1A73T2vnN8T5JKHu5SLVcpeMr53VqTS +M+aOZ8OJIp/hNWqS2KENI6MwekJFZsP9H0pUBMs6aL3KtG1/JBFRCdAKVLEKZzqj +czHq1D9+h4bkIDvBdY90tt+2CtD8ZHi4Eh36pOGe6K+fLfyNXW91/6hddNyyPYS+ +pktH86j9UaFMnd8VoHUQeYBuk1uYQEKMdrxhZIQLyKwQJZnH6YvajHJjxwqnYg+1 +Kr0dFP25zX40/FAyw+C8Tq7C9Qx7cNLE5+DfCSzh9qPCHHZmK57CAGacpKNjPIyF +Zbm1yC8wtVn33Nuejbg/lL4FR7IUtppcX1lhU8OOTD57NdXb7S2+Z0tuefBj1D6c +JL9yLOdvH8AcEDLwRtrkByIYSQbllW4W4rFJnVITUdFWWaP6CMUTqV5DCrbujMmm +LLLF61UZz6wTylXYi6ahprn/ar0pEunvln+a8T02qehFLsIyLjSyN86Q/hkTglVP +ILZB49WCWSSD1fjbhmjApLBYclhnIrl9dARz2EJYT42eFT86738H2pOWUsqWUPm8 +vzxWhlZWIjilVGCEy5mLdGJ1+R61CkFw/luMsP0RMqT1L86ixKo0yNc+07eMRSjP +zkoL1wbmnf5gnve1L7caOk7KiEKVeYsL8JYENoAeJAlAF3nRU5QvZQJZhlrKZWyC +Tb4GdUJzm+/zPCU47ynFcaPZ1OnkS+zQHkaAZKqWNVbDMNwu5/jDgBZn29vFICV8 +HMgcrXlNyy+gFkN9rm40XP87Q6VjhpY30PvFX9yHdcrEn36GGozlBo7SoYg+FfqH +awuGDFpVDMQvcZx0JLvBpgNYnxu7SHvop3TVDKlcUO80qYT/DZNjUcxzj1uSQRv7 +QbQWPpWaH/QqwxVFy9T+VCaF9g3LCysSlkBRQbgr+zhECVuEggLN8nagKqw7yv1U +yKotGp8FSzZZwQFQ9LfEsej+sZt7yAp0K+l6CXqBOx815vFGkOgKpcW8a5dMMv69 +2A3mAsK2GN7LcFHHa6Gc8YkM3KJE+8SNUqo2ycivzNpS3P7jZldPFIaPccU4qvWt +fq4O6CPlHuc8ZwR0w6RvrENk4wvc5tVumyFi4xfNTeWqxykElKV6zctU4oGxbMDv +oNJFQNGwDnOWg73c1He4SLRqgs0LvLcLvCz/JWxnF7jmeoJWBlHCtkFZJl4hbHub +kzNU1HCmD8K8FHcxNxwqtPewhbAGNrAS1yiS8YLWt4lIHpBWXw0Q0YD7a4eSnLGl +I0ktaoDyl7H7UqwFQHABf42/6abeXJIoveL1ecIPAAtitBX4DNbF1UcisIIkeEFS +DEnzaDxlexRYNnx5ZtsKrTRp3JsrI4iXgjxtC4z5ro2BZDgpFwrbZYKvhQkZXvrZ +KpXYlasbwRQNGqjTO1FmJ6HseerCd4O6O+iWryjYGv5JjO4aDPtXXpuCzaqX1bCZ +OAC8nipkJbwENFz7o/jwWMX5Y1eDv76kXhzRFtpjwm5oM5+ZNP0bYZ66pTXShl+3 +EBCMIZbo43ISGMpE4IEP8ztf7d8LQqpXl+9IhYDaCBN9kqazVL0g94KoXcNO7pmT +aaKFNXVG6hw5fJe4OK4lBgbdq7cVBS0byj6SbB0NmNGZx+lClVugV0jYD4Qw1v1b +HUj0AvaDz1sqIJYWo4RY2spjlgpsvVa2gPJTWqqi4EtYI6toE9LTVF1W+uvXh4Sx +rM0e/aRlMCktTQhWSlFbwwiLj0cJoRuRjuP2RPRaG0oWpoS3RluSovMXjDdzLgl5 +yu73XWpxlngtJ6NDERHc8EmoqdpA7smGzdZdu2ABnfCWiXio0EdiphFnxEmodqzD +MwD1SEfh/q3tLBuh8BPKGmXz4cgfLSd56YnrH7hhnzo2DNp264CNXAw48wf24UVC +61hgYKdOKfjPO/HtRXqPCWVZnhmL8fYog2gzDPg9smQvuxIzGoRhAL2gL6Ue/89Z +W9Vb0I5jJYqgDGuaabLLV1N2rkdCsGaZgn7FUbzArS4yQjpC4qXF7Tjbc+iage7H +5bGBsc6UULVR6cbOBsg/y0P/HC7tPsI6hST4YqH3qFsyTTxpmBcuFMXbhoZnnGtf +3mDcFL3LAXFDjJ5qxFX70PD3SdaU8GffIAJiioFGen2Q/xBxyTNKc+C5cUHP/mUa +N0aLLbeuxk7MfQ+QG+3EWR2AYvvdbXNeDzx3bCNo8ZF5cvsJH7AZQHiz6Sp+1Iou +LurlWuJHuyesL/dXEoX6UZtgFRFsl32oMOBHQAb0AWdUGq+X1KU6u1+RAWB9GPVK +m/PuhrCSkzqR5g5EQPvgWWfqTi+rFhffn17K/yVf414UbVdtRSsKnRQ/VjM9XD8n +b55Z9VFh9HGB7pvjWxLS8f29E6cseIgFlrf6b/Q3OECr5jRNLW3J/H2vqMc5HWCT +eN+85+xsImbrNAfCFcKikp5KnANC4+U5oabPocc1Ftl435+zDDRx4+dK+GXycdNF +au4oBlTjLxe8/ZQ9qVJrD+vgewZJoaA9mPielHyoso9+oblVP8Z2i8ESpWr2yMHF +22cq/LCNZEEax9M4AfD02pxS4dSuFzv9CbdH9rdqQNEiJHKDPgI7GprYid8O2ziy +52+pmgGCVAVRoiAH4HPoxb6UkXNoiGDk2DD0mSGo4yyljqVRmSUrhAFKhE5IsoZp +60Veav+rTln3dWj3JKx8CIvJjE344/HTv054awyTHosx0XQnVcjOhymRPaJnT0aE +6jFaEUCuAi1ZKnzpqqbO0m7Ls/IRMXDBT/8pUC31aKDCkkN+OJ8tnX97qnHHxYwX +6zN3H/17fbpdjKWVxgMmyQHJL+loggVPt8FaBG9pwxaghbvRW+VbzD+XGGCxNeP3 +Fo5JM8STKQEVFgBP/KnrUbxXMcpw5N2BA+roJbZdVz2wTxVApkoHyjkH8acDA5LD +8qrDHixFWefWm0tJEWlnoiZOIt5w5pDtjXwKF+JE+UyNDP1aFSgvugqnieeH/230 +z9uig3d6vKLN6R0kDT4SNYeVHEFJg96jV8CqzufbPL19CYOgdIEBFQhaQwZoEDDl +QUFQw9U5+pqmelfcg3Ty4kXE6xkfRgHeiBHs+91qmiGL/l7pTLyW6ubRe3q/O+D2 +ns91XUCmjeWbI0+jWCuHKmJv6O8cukQkxIQ/1gDIrIffZGpW0VNHgW4Nz1B50aSy +uC3vLFZ4LQA99Frj3MEZCnQoHwwfDsKcg5OZ6tx89p7A1ExSS/k8o/A/gII7qWR7 +/g49Oxagkgsf3xtyUmH1mqMf0TJZbD+3BomFz13EMgEUbsupDP6oSaYU0U7UQEAy +jM2KrsIlnZsDwSdEDTjXxTEAsTvwVkvJ61ftyEoIImRAXitbMns1Zj2qnCOv6Pcl +BKj6QveJgxka6FNjL/8NmZM+xzvoNvPRax6TjYdTr7eIIV9n66ksxiuI6+50sd5h +vHvwRwXZz3Sw19opEgdwNU06MoE/1/vcM79NdfCHN36gikosLk74GCr2O3Oob75A +Ygv3tOB66FsyPFauD3uvgpmK4HRCDiSHaAXlSVs52ID+0MyqpN3akmQQRGMm2rIq +mT2xEwojG2mnkCvYzpj7g8d+cRMZZ1c0wjHNY5+eZVi685CnfqPrmtCzDv5l0GK3 +e/ni3KWdpEN4isqoU3RxVlUTismB6pFz6TyQPEc/z69qYmxoLb3pUgC75VweoS62 +N4FXl6emW2DmPbpbhFXwTDCcfI1Zgrojvdu9gKZuO01LRe0t3V0MWZfH8K9vIZz5 +KbjxxlRiySKF/6ZQpYerflQbR0QY4KM/MLIbaDvzYlmxe6sTtcpYZ3MPvmJrcr9q +k1hCYjajdemZvGFQV3tXZM6mQugbT2ROJFVz7ltl3w5OBDEsji6xrFEdzrnJCZQL +DzZ3UXmOccUYZZltKQAjwXNc+TbMiVf2KRfcaxXgqZih5a0StVUEmsNvCek/5a+E +90pD12ukj1424lyHW1OzPwRJynf/tACj84o812ksuLFOp53yKP3pISV6fNXtoLk6 +XG/HyqBoidbsohH2vJRmTUhYR9fyf04rI1Dgp6ulfj0n72c6IKZfsidVUIdFSDZX +mcQ4Xsj75nuqbLMjLUAyiNFu5Hl9ZRvt5WLetnpIEmjNJwrqn96VmwjlgiFmwRAn +nBxWgXCIwIsR5bapOuQGL/QNecPOlMU7h78kB4aFRtLdgl2VLN3qr5HtSAQxKrAq +RjdlFhdmTN9E4tC3gwBj+COHx8ma+UWv3+5pink5pnBjpYPTEvngdu5taTBS6fVD +RzTl0IaCcUBByV0LYiRmRcIARjG0uATHCHrcx/BGeU9jl9nxLlz+p1MbthCGxTJl +9fOEi8oEvqndwH81aazLGkFdnlmLpFS80aWJid0166hboxbZVCZlvOy0PF3C+koS ++ZHq81EejHnOC3KLrDJ/5JXjFw9XSoksvRjT8bJG9541QDnxnQalaskU+j8zXaWV +rkU8Wt2ooy6i/R/8xEKZewNCtq8gq4M6svLvy0x76b/37LqT0agcOYeICEVhVpA6 +8gzNAReKm+lHebZpysnQgeS2vag4DyBV6xz20Arxvcz8nVzaPEJD6PAlki6zk8nE +yo6deikmZF0qamtJSDDy7HHCydIybibY5lA/C2sYcD9m1JJfL+EHEo1J38QmYbIC +iKSifp+3HF4i7L086KSf2DFMV8rS526HLZSAdKdQKgYgwXs9+jyji8RWizdsjerP +zvHar8EnyEONGHY/DrkngFfgN4kZS1Er/V+mE+gtYaOgPDEszIqprymMWMfcMnZb +Q8RrXGw9Lu2ak7AzF27/D2IW2mRNovbX/yyhpf/YWIyZFHN8KCHkqo2d8jtWPG90 +S4P3br0DH2/isVSdzoOg4Kh+M0czbNehU/ODC2CLLPhBI9oq/xQHUiH9H67wbRol +EBUWmUAX/SSyd3QB7Yll3ewsWZpWogPZ1gobI08SCmOXpU3zfLgI6y/prP5KWki9 +7v/zrPDDZDSkROOaCqQVIeUJT8w7XsTp5OFKGCSk4jomK0zOB1RB2GZ5Kp8ZEjVc +NanicyB9vbVxWPc5My0azEgBigQRQOXVAx4vSWHnkPtyfdf5TgOoCu5FpJJGxTVF +I1opylWwViZxhhmaTk3vL6vuL+hOOjlMPHohIaZWnqAflkLnL16skeSghLGpq6LP +NeR2BEcPqrhjgfrUdFCcIOD0RU0D3uD+FKievzycmmRYaXAJ5POTWNOXiji1p/Ol +eqUeguQeDqgOQwIwkqDtc/w+lcgWewNwn+byKkDrpEugc+2NhF7Sh34UJ4cIsNwv +NQKRov7P8nv26xzUjOrAhy8fOIMaDXnlgowzESgvOiye4+gg2y1lqYRF9ZpEZk3p +M8z9AWm5di16ptM7GKQEzXNK0+RHblHhA7frz8Kk92lTLPuVtAvQERUOGK95hZ3L +78Y73NWaGIioSd0BZDv/d6FGfS9rowTUjkw77TzL9C8rVLiyx2fTKueOYX16KQe3 +oZUBf3YprvjEwAxxA/NbJI4hCskJFsGdZIbNjVTxIwbSkBBBvJLg5Bik1v9STeM8 +e/1Ta1Z0By8QUupyf/wvOcL0Zi4HUUCbrkm9SiSy5KJDAv7uNhHV6zuSqShrdhdl +4orlgoLdL/0fsm5dSF2k2NFllbr+kYDZovPGmSk+4/tmyC4hjcVjaJb/nfuuB8ri +UagorVZ/FA12F20km5OqNzaECbQA2bzyn6sklj4sZA+Oan0Huzo3Z+4jNErTUlec +ARyLbsrNg5VKtka5GIyKSxwOwtpuwx2F4JPESIDPOL3aFltL0LgwMIt61h9K9pP+ +9M2snDpbFu2uMLcf3fDamIU09ts9S9o990f3itDAmNBbtWbsKmhHkvUzB1waQRH5 +lgwTnwLgZ+wUrVGcN4akH++sz7wt6DmXdxtfArfv2JGvHun+k0LLqyfB2cdSIDqg +67B5fTaCWoOISHdNzjGvRSHTfJVd/9Hmhe5r7r4DvgC4yVaIqL6albyH3JoGEe0i +8pBUwvuCJwJqA4VYvoUwRBKF562yAHclsbweNaMgKcyoGog2LtQz5khdr597CgGv ++ZUpEun0jfYr7+9ocNPf4oAtW7HCPnzB9IiB2bNbdWMKOrNxdVqafhBgxy0MvW0K +kyQ68IwVK+n4578gHcmLEChf75I0niUcrDExB/p1MpEUfglN3hkmiJ9xGTsGNV9u +9Cj6ZXGcpe4okxDEQuV97IOeZGcola60pBjuiOp3EMQyBV/5MH0TuxaRp9J3ejcq +Hl5uPz+UkeC6TJUMkpQ+2IEherPOemXpN8HuJfTgrVeZV79l8Hmc/7Tt7Wfyhha/ +eAPABXjMyrqeXKBkh7I/TNeqxWQbZT15MfUqXbcrL+2IQpYBduYOvr3RMkHGzUK1 +Lpbx2y6hHtzwodYWCTW9KVEo/xNSX+7VBMBNr5jEPsNptDQBFfSctld1yqVrlsaZ +QR3REHQqozO8bAPDkPv/Fgr5UrnKcUUc9QnyRJpKKHVq9sq7tNdvy17QW3/vXLvV +U2OZhwK1eAFZYm/98VQn+bX9mF6vo19EnOnb3lVqdg84ietmJ8Lwv8Ve2eIypiZI +1uLNec/8uriLS/TsXXANYfdGVblxOyxPNArmRaENaHVhBuBjzMnDdCVUMKX+EGpC +EVMKxHI+HPrGxU94Xy7U6O/dopzJONidGiOhY1wj3vNdwVpK8OORWqsZDUj+kn23 +E1umlZOE3ej5VTCcUkyxGHxZW6/EQsBj8a8hmRv6l1xVBf/bMrmUPap2BJKsqWkw +2C/DeDo1cUiYWhb1RLZ5zZWhnZdbGIrJOeF8ExudH3WDil7a0ssbAYzx5pheKevY +mrWMw778nvxtS2wrRLYKavfu5ZQK6dh9upfMLhwffJW5gi7hqX66cBFWFkXVUOSZ +Ar2pzG0JVOsScwfDh6MUD+PYhvBRxgGV6ciPAlHydXOCcETaxzpvjyqMxlwaexoP +FKav27dd2DTBTn5/F1y6suEhs3uvSDLse4AP6uGhN3NuOBs0CPyqnHUFNHyuCVl5 +fVpJpC16AJCrXramj4kTufNemIRmjLxs+xvVOSSCm2kF8C4doJj6CbnHeHzHrRM/ +LDdCZ46RSiZ66X4yl2IsnfpPDhVP9H7EFptn6mvnVGtt2poC7mJY9KKV/hRm0QpB +W4qeOlIKJvBE45279fm706+PbA7CK3mExSH4tkkGcF9WK4D02ErW8XePnXbPxbsG +3rDDURYNcgmkOnYKRad7dw79lNZUizGkzJWme6q/w0qZh2VUmfTZHwka/Q7KeSK9 +hM1upvMpzFzt3qnHLxasCpYwaU4v6fRcI6foJYQxELVZWJWwOohIwEP5m3ebGjHk +QXGEKKO8DQGEpG97LFckYykbcViMypQW82NK59xjnEymp9Q48F+iDbS5/Kfpcsg3 +6rEbKowmcyQDnvXrYnT9TeczpAncXbP+WMaY9Ca7lsxo4vFcPfD0zAAt+DX/qdxt +bkAFG9rzy9ohl05BpRyaap32BGkJZb63Y1EBddiDWEyooK7B+elyt45a2/FYaVsH +Zs0YqJYUPTbvYyVztbIWKHUeX/wXj45Zybt8/kAsGf5TBt2nDrO808ix65lLBXIf +u7alMTQX+OOZ/yxhz+6HL/fu5axqHnDnrwUwU7cP+qcYmeAFAlFkGUdm8SaJuhhW +AYfx0LPU60buKxVsXZj7Pqosiz9WS7mI79VitSg/j+rU12aBlDreoWz3gre/1yTU +Hn92d4c9SUziqRvKqoXwHZokd9kJiJRVAxzVjShy73ORUPuoaEK/mW+ccHB/mSdJ +i7nCi19bCpESce+YnoT78LKW0SFmTglf7cG6wO64xrvxIHgVx7nRAx7uQbQA5nCv +HbWWJHfFpzlajfV6Ar8fvuK6h4eOA2jQPMkpSRk5OGBCrQzGlDQ8yJx5PSlwGVrF +9xO7j3SVzUVn4XJcGSpPZaDtsxKKK5XJB50MzQ9/xMLuDwKXnECNkPFDqyDUwzC7 +wXpSVsnOYB5Q1Mva2sxhUB9VHnN05P63h+HcA/8QDhmM4TC8c0/RCIFrIuWMxQUf +o9CJCRW4OtbYDB3tJwxEdLeDo/MD77VhzfDj63LJZDrOQ99eOAi5CPMyaHGAVYRT +44v1UiQ493QSPDWAlX20b3DZ1RQRwz4GpfS9jZ5GC5ipTL021fp9XN/78KdXG4pA +leSX4VjyiqwQ6XLFu1yeZLXYYYaH6IJgiu1PmtA/7gsvBDp5zjv6wU6NYUdCYv5E +XU40JEB9K+Ph/PclSQ11OXvbpcCWKNTTv9v8VWauFIhoxwpKc+cem9sTEKT6sU4J +nG5O8wopTDLyo5Ki+n5qpHlsnXzSduZqQrxsFp/VCq8RyqCeycs3TgR4XcYJVz2B +SAvvDXZEynzJFwtQy0FVCbr5FRyHs0vfohtifNe+PQQXj2rwA7HEn0c/dG4MLh+I +5vLHCGs2cjTeVKY5R5tFmb9E5zh8B+crxfXcj5+0igsQWcZ5CMUKiKgdaSz5wuWL +25FDLxxFDBjhtDgyY5HVtZqRYMqh53jRPWClepsxYBWaE1TnfGAx5pSAQTXGvgXF +Cs9nZvT+VRhRFznJDMv+fQyCnMYVzmwRll7L7GWs38k/RvBXZYax2QPnGPHSl383 +wPnuviE2PKYXHUmAdkhuyLfd4T5Psn3gnUVDJQ76/4MF3DF1QP2Z5dYecBL4BCap +yvpJnTmPrCYh0ipsnMWtCFtBLBYn1YPUZeY8CAe5PjVa5SQ1G5bnEdiVmXwDDQBW +HhizPnp3V/LxdsLcnY6BnUcmymfVVSecENd0e1mjHbhi71sap7bVc210dRKDpnXg +28gKeKvZBMGhduwbqOFsy19ruwXb3oBdBjny0hUA5/gC/+QKOtxtbyfHYYpM1UuV +tbtebs49AxlMji67uj7rXJmb2JnZ6FMPr9B42sVZiGZMb5MiNyLCeRksqH5I/9q5 +EE9YRpNQX/VubgC02tdDkuE2ezTTInSufIoDCx8IQWgVOVNVfFyEpRpqyOZRxgZe +gOIo/ZMv/vF6ug+UgPlq1VPNsETQXiKjq38fNL4FHyWkbBQcPQZaNL/tcTawf3iH +bYJkbbxsbp8luOMiUuc/nILeahywgGMqv2Ak2PQd1r/7beQkXSaginVX5XeSBaK0 +wQ+xN/XaCce2WbrIgywv02NiGqfofu1S3svN2y4dAdpvXjbQPH6bbV2BxkMm/DU8 +vBsV1EdZ9HuY/Ea7tyaDCyWRhiMnCr3j/bIXIh2XgtifhHzD6M09j/0fgRgQrrQr +ZIQY+T8otYJomOUQX4u/6DA8+i9ESjnf9uhZLr9cfUehDLINWdPi21z+j1SW9Tmp +3QrvmthuwYfz28ez6ufvs4767U7hhwdXeITi0kTNAz/QI+teyx01Y8zLuUb5kVRM +pv7tTZyYiga+hNECvPfVnvu4p8RuMy4KQdjUSg5bTuwg/8wiZlmlJkI0AVQlTbNd +QLsunkVEnOwcQBvQfzNd5rTBzl36uKb2Ymkqzi9pwQ0ZJtk6TwZqvDKqhruMCGpS +pRGCgJeEj3bfMYz0/PKUGuLl52DwRrp9BGmpiDJAcXfuFNCfnBv2doqUKjJKBuqH +/hmFlKWUJQJ20ckOKkusTjwFo23WLNKO0yI8A9+NGodfx7wYVaS3tehFJvHRtT0u +Mg71XUdfgWYzuYLpgW5m4cNY7VLO7yI0O+1ja/SPh9ghVznYUhBC4IAIuXqb95gI +GUqCWNcV5GUKoM2ms4hDjfwBuLCJShY2V1RDfFQNpJ0OeJLIm58m+RXOzqefTEHq +5CwjrJkhHUZVc7iP1Sf2MeZUiz1vzMvzW40+o+1NrDo3+VjvE4xibqH+G7VjioZ+ ++laKhwwNJn0e1SB0zKJQeD49Knme/EuQuywahGCw8WrlgN6SS9FjH1CcFz7YUxxk +xSLltxHLt8vCJgmdSc3iU+PZiMcGMPkkK3tHRGFXcEMCzQxecitDVcLt/6UK7w3+ +DdbVHHtnWuWVp0335rDg/DE9r5d1wEK2NWLdP2CreTJqaNs6igIKfCY/t+p7Up/G +YnX9CWNb65XlZVTRd6/sPfaPgOvnwCZjJlVmWehtRH9IHJyQuHFGtAhwiHL7yhrb +ecriEOc7ReJfWcs7vJAxdwhSbj9M+/6odTSe6nipGGjwGfloBhczUPbQKxAYDTJ1 +QMuhKkMHXKQkVnQR+0MYWn0S9XrtZn0tnuzXB7PpKfKLPHPJ9yoOzPRMzD/J6QhZ +WHb0GgjGkF91bNPs+JAT7VrgRo0FTBO7fSrWQDIy792vKzW3BeirqVMlsoiqLPRr +HEdj7IntuKHb/iVKVm7Q+aE2tvkXJnro652zq4scawb7rnOSdxfs7IlYu7C8om2l +u795VEFqc4dCVH7g3iq5RtK9DSGfxE/TBL2bPRahLfDIW7Ty7Tx2Fs3X7wMyeYdP +tT8odsvhdZuthW9R8Ijhr7XaVRJndOukTKP2GgQ33zpLEGzyExPMfmdIFKaePGKE +PlPH4r+dbxijYxtHrSH07x01+dXx5VBMR2Ysj6O/SSAFi7is5czpC3a62/VlnuFo +m5uZEw6MrwKdhFDQXxkLG57evzL/8ATVHXaAXD2jIs64lptusWei/QtCaWT7fDIN +tY6w+hKo+6dUkHHWlxMtz8wCaXkvHoPLtCnQyJbqMBJ+7/TCB1j0EcyDWby3J9ob +guBZIBd2mqIvHEf2P4doYkoWwCOkYdLmlW35EsnYy2XtJ7+DxftoO3IMtpX7z5Fw +veFjTi0cCs7hk/CDvUK7FEJF6tjovYWXFq6GJEb2sQHU6V/Fjr1fdal5kiyDHJ1S +hkuwclasKr1zcsbrvh4aY/zcyNgDO5ZJp9Ns1EscSvmbeEUAgPnXOdq1td73HRDP +GGra+eF1LmEHXK5zYskSxr/EbvI0jWixcFgA/GjvEoW4QEnCJ4jyvstLZTNsKKj8 +FUXCbUZY4pnUrU9exJKTMvxc5WUXM9kzSAHtxsYh3eSST4rSpXr+NdYGkJMxdWra +xdpwvFCFUf6BcMoVzda/437xO6Dn0oYrAqF9tGhFC/qyiY3zeOzy4bRjk6u5zEnk +O+3hRDmhVjWlTZM2Kox2ebRTKOmtKrDQ+RDhdK++xuwn4pOFjEt6FD2Hv1SEusuz +g97230RTeM0FEa+wg+anSN3UhRAeWH7gQP9ur54xvZyh4IqUeQ5QSg7Fx49y7/OH +wv3ec4HEIh0eFF9sEULa9dLQosxscwwvk4okXo0ETz3RNAPimyAelG3p5nNgMzpv +iBiKPH2fGOWoTYgiX4Hdutiqem+YzM/7IIakETjVbt8U8tRBktRsE18RdJhO4HDE +SLdA4z2N5RjESUoCX+agIIJih2UK+6ESbhPsavdcpO0o3zL40rvhqQ0X437E4OfA +L4hXNlP+2rC5+4iCtctcqOHW2Wa6XVlKOQBQvdMi/BZGXHp2xi6syW91h6dl7UOf +eRLKvv8nD54aStxLe2qiXK/5zcQBIrr6WdgoB5zAKkkXOcEFwl+TwI+KemW52WRW +v2E+GtYLNcEJMK9OeF4NFFqNKi9+kzvXNJDBMGITrS+dMCbtSRXp89zsPayWne5h +hTuRRVsr8WvRVEdM79wvg+AnkFk3SjiH79Js0RiVhzTgnWICayRxRG1R1E1MYQad +RyrXbk6T/IPmOfUUVGVj4AEyjNbrUV8ouo4H8Gza37eXYC2OD+YazSArb4b8Vmkv +6bk6aSZ4/Jqpwkff+rmH93bwATqjJf1DPWqHkJPoAlnV+Ri2KC7GskgJ5KePsNBk ++vTvNF0+zgLFhhNOaooKTfP94SWUU+yP+nkVcEdAnsr/PvAMV2HUDpIrtHSG6YiM +tO0uuH2koeHi389Q4U6lcK75cXaTtHGjcFmsm34o59kdQlUvRLe99b4goxCWLyUz +3gEWhgXsPNtUcAQ/JjfjzhNc9g4Et1NPdku4BWZ+DKXKl+ON6AjlDikHqeiML2Ug +C6ubxMGuzxdMKEyx0U+iUHwga6nO8/52rISDzhB1nHhxBhzaZZtJmiAFvAtCk0jY +ySdTcS1NOTpXmHA3UwFP4MEePOMXU80DiD8NCHo0F3xfJF8whjBP/NQgItJFojSb +BR/CiMOfQJF6Ghchf1Q0mSuxknW0NlY6U7FWKDxAF2ObI6erBw6iZYgRQ2gDsyQa +1fSFjEPQ4+H7FaOlMVGg7trCRzejDwCH13dNek9zmiGJ5KdwgT41Qybb3+f+LYq4 +2YJAT/n13+l75cRqCHgo9Qg4kEecpD7xDNy0lFee52AC+ri5/a0F7eYmb2HnXmPF +vZil6h83BArp1KXNF+MOVXYS8hI0/HHJ56148Id6PUnuRHmE0ABulFCF6SXwkOMx +wFhIr4CmFpQH2jnmKz0PHEjsgdfXvmA2ojWFvXUKPQkqqz/5/iT2vea7Z5rbu7Fk +GgVitlo69tRN+m5lNdzPVTQDYCXRB25EabDmT0a6DdfqLi3m5p4yvZvc3nyUfjfg +QSxAFfmatyQo+iNmJAx80mufXBDd1L1aw5TXMFpxYzvrFyTdBEw7fCbInDPARMGg +Uh3W5SVmGtHSVIhwJQKHkj6yTvmh9dMyd5WXP5QN4zTolGBf0vs9o7spf7Z2i5L0 +i6HAD2Z694gv8YFsfbFXTOSz4QLP8vVl0gjGDMACN9uC2QqnScZWKcRtF2AASVAt +y52DurGmQKf89ZNIEZtJGUV0IRuAq8ZpSmsxMqrtL+Hp6wgZdqqlhAG/e+mHgKUR +Bm+QReb3r1840GHZ0IWRJ6uGD1/JVLy7ARcxW1+vvS0gshAU4ueGAx+vkXfQozqO +rWXmk2P69STRj6TtKlni9Wv/PdGMidz+azBdM7GcSWCniRtph1zCsC8ljU1EQvfr +L9pN5HF/kF8rSLMfzC+7XQqd+YlECUiAeSDFbdP3T0rVWu36UjU6yk0Dpeys/UwD +ZC2eQLRfDiFGMYEM1moLxMLf5gquCrMdTHbJtWMx+tUPhSfzix6bhdvi3Nxxs+5U +KTPn2OVuqDJ+faqZLoK2r74BwYUqsGVVnefvkha7nmkl+sPmzGPf6amszD+bWLG4 +e5BQWWtJ6DyZYJn8Ul5Rs8EiDC6pWulnrhXQqn5RMVTEGJhv+UcvY36SblRZtQlO +pprDqla1CJALxKWp75BNWwgMBGBtFIv0oJAPNuMfbWnojqyTCsIByGund6AqOl7w +eeR+nmfMpbUtp7mrnZNtVncjFPq4o1GPCU0uTiAdcV6rHGzfSees5VOdgrqs4OWd +V6+sNNOJl+9fUCWqviTHdWPwho8o/m5xYOpARfdu4KT9PqRZbrNaonssZaLujW+5 +Sm+zrsxiY1nXdspQPsxGYBg/9FyfYK8HUoqfaemmnsD4xpoqPOQn4Xe8cSAS4Cx1 +sCc+A+3gcDhoOLSF+Is427hLPrbCCwsme/SVAtDjo2u/FBp6Cx87m3VzRqg3kw/D +boZiZU507+Nbm5e0xyuaM9c3DwKjCMOClEBKSSS46asjLr5h1BWYAukx0zzzDKDR +ebsZQayVKxn8tWXCU/giMtPn50A3RFqNaSZdF4rkIRE4yqNEJ1ubx/zeUWMhQo+Z +x7QOaUcvG/lBRW2eFLBWwQbxctIjL/zCGt8kPOwnuZVKGuc+tkbDRNdwhl3AcGjj +hCcSPr46euaqZzqeUXmyXoIrvcSWP8SSDXIHxDBkJWkE74Qg/KTsqgDKEj0UAxmG +XYlj+1hdb8t01GWhl9zbaqBK9UbADWOaEcsiG0xoQzb7O46/iWMHLegDyjmcZkTs +abAO+sXpceGfaqrAqVQnxMrspgfteCL5w6sfMZlXWq+qlG/7RoMWzuWhh94ClP00 +K8UYbXFusjfRiuMEEtVRONpEwTEeKrPuJ5LueILKPzO9kzkaif+CadpJLQj4M3ly +DcafKz0dtLzpLRZlgPEjWIOTciZLdXEuc0pI57Hr/rbfMpRLKpU22W/tNEr8dG6H +YJxrJ82ePGOT7rABAyrC+FV3uUz4FyrYhjBNWBu3s2RqAzCfprn64ZMXe9qHYwGY +5imrteX7yi3+KnDzHpvug9c9OK7xtR/JCV0ZDlKPsMyGcdY/ira9EIYQcf9Z+W3q +i4/doCAOsn7NcJMMKW2rQGl8mYVqN8kgn0MPQddAfRAzXOsAF019rz6TSnuhtwXA +9lMXTbI0SPX7y1pfUkEY9moxI07WaJkbQ2CvVcuyDBvotMyV1KWszFdS/nHy9yd1 +wNPoNTnj+wfRWwphX4Ilg/PttwqxKx6sSnH8LIG2lXz0Y4Mf1+0h5QsdKTSjC0lG +k0hPtm5XwUhL8zlUWUTOjTyTLhMfydE5HIUVBdTsuWm26YSOxvBfw4ovEM7a0tiv +AwhsUfmbdS0O/24gIANTGlFZ8PhFAhBpOEFi4fhVuEnefyQSN0byHlmf3K9O1mY+ +2bVAcu07QrWWJyFxzvyOXfVqhaLvUAJ57hhbJ+DwdIdsawxj+4bPn+hDGGkzkFG3 +XDSR87wCTBgF9xv/5jgJguNFgZHq8ZWdOeEeZvtIQ65NBigTVjZZMt/Ik5r/YxR5 +ATXua1JpUjHEVEXBhNX+dzaUmpDzb/+JUXkKBQ/iOA6p7O7UErH+Q9iOehNLO5EV +sPYMFnhH5lW8Kw3Dn39Ay7Th2SkUO/jWp66IRGqovpCtVa5G6Rr6Hz2MvlYnqJS3 +AVtiW07lpX64B505MUmOlG1dMQRo6nhf40BGiRaPr9q3nK/iZhm4GotqeMOi+VRL +iNfUHyfXDop6gY8cwxLNbWBclZ4ENphPbPc3E9SQd9K0MiTptm/Z2FyShwvYm9BE +tWP0ivXrxckSglyOdRB8B9dlVMbnHyoEqKRPUlhcyhP84uCP+nxUQf9EGKerNzto +MOihxEuU6yRk+EaQi+a9iru6eg3veh0V4PaSZBD1NMYPL5Qs0HhHqkpLhgx+OktD +0UHzCebVyDnnTEDS0FueTU/BzJ0vaVYu0laYepi6kD7MaVZsHceqILLvc1HFHe3E +yHZlmLtUS9XjkvI52KqZEiYSqRWo5ipSN5S7KiN1njsF5gzmu/Pi1HSpZAZZyMb2 +TBzExEim6J1GTKvOq1TL48eUArcAqJd4guVsLGy2Obc+R601PBE9+cw8EpvIplqq +gfje5PFPQ3K9eBhh884iuai/gVX1Eoy5yvoN6RqwWHgmTVIvEzNnUxyUOUA9NQlM +VHQ63Hv1Pv3VnVYM17ESkYDg7myWpn18pRpct7y594R4UbS9h6Kvtf9LW6CUIvzJ +tZuDxDU0vvQ3fu2AUI1fdpLuen8Te6jbhd+eBlvBZscdaJLn2h5epcfPUGZR7ydC +Y0jrMluWz6mdIhxqfmQKu1A62g7352tsU5JKEHvAZZ5snruBhKC65I4/ndSQ1MKX +E2judXgscQSMnsR8l0VCU2cRdXrrMlKugXF/WUj32nXw6izMrMOPfiSe9egjNH3j +O2TIaUKCNRfaLbR80nRxVMJRhFCi+LQkx/AYaMoFqmi/KgGml7B9CQoe5MGSfL9x +UKKVFwj7/2bPEexRM+GZLJ0mufIUFdnsfWx+qZuRzmI9ONSfAqufj9tL9kmHa2xQ +E1TRuW0mXG49izzbdtTcPvJ00vJUUbPOFtMj7ikSa9ysDegqWoI/yiWGc3PGe1kw +QIUMyJg+qXN/03+d5f7D2piBDairp2X/MmNHuBsxt9oH4UPMZ3fd0XRbkwN/2b4B +4AKIQ3lcEIPDWJHXZ7dBL1vH1UOtZgCzwSW6bHRJ2kjn5CkSChNbWC0ht/qrB1vN +v8U2GnQVpo1PWFjcNHF73KslxobJXYnysfSFygKTJkE1XV42d9arge4ORYofM8ec +kTsa10NsfcO6+sI90ZvwPqxuQc//bvWBFeuwQ1iE2sbmNEAieLBC3eP9pK6XIsiY +2GLLplIIiwwUyrwZTDLp5NXQUiAmBuNNNFdWKRudnuog+z3J1sq/a/VPSnLTfW4w +VOWHg/6fejXafSvivRldL7TxG8VZO6PEW/Z/gdqUjeLSs0ZSVPseMVgSDvuho35f +Y4dd9WZtRINatIZAN0s9yj2huCuvUoiStvhjZ7zdUoP61OdG3XhflamuqFFDyey4 +baagVdSwFdhd94eZUJVAf3yBXNmgIrgVL2h7wcGAvToE05s4OmMrn62dzkZkOlvQ +T6MV/65towiNrvGkemjoeEdbkibrotYIUr25efOkaMITzOrLiOLED7NYBcS5cNA0 +oHW/3wyK5RARascC4+fC8KPhB2qGIGenwqVWgqIAjwFitVwOJZhMw/m8kwJ/N8Dx +02b+hJJ9sEWXIlc1x0Lj36RlNjqCJNEUv8IGGwT8ZYyWVbf42bvIu7AlGx5ZjEer +XTdGtgE6X68rvKhByt/0KUyAsC1z0wYHogv4IYQHcD7GDHe9pC5PnQvoWrt6WYUS +2IyxsmUMp8K6xbCRaPecRQEu4EFs4PkQyf3PcBfDzla33ulvdMau7FgTMXZ7J0ka +JhZ74pqOm2ObO3dThF24ZQltkXZX7rZkCkOgrqHj72wv9kHb1gqj3NoCCGGPsbRk +N3yIalMICQioNyS46pVRcTbQqj/KR0ALdNjY1KzmZ+b5oq3TpE28a0JQpbYd/xku +QkCjW1dcJGsEMTHBLn9Q+baIhzkv1qDYeX3+xUt+6S95nczm/rLM1ZOxTT8nsH6z +CWG0BI5aT6ECc9idTKPXIXNTD9gxpyX4vTcIIpniNi+Syn6NJCAfDPpDueYfUfAT +x9gtDYPZUVuePNFVHaVOUABzyDqmdCYI7V1aIHZkb59fq53VLaje2tVqBGCEE/Cb +JsG3DvwgBKZCYsObI7tzKOIARtAsS978Q1XXP5Y+zXiokL3IdHpkDHS5rGuL6Q3z +pOfuq56knL+VpSDWfNOmRn7clRyaGRXyp6VMz7HzV9nPqJO+litIkoHOvCfzwmZW +g2Q7x0BPtefOL8p/vqxe5ZY/17bYaKhr8i5fNQINNKMT+g6iuHETqXD8qvzFDn1I +6MAaU2LlPd3f7J//8OTr87P9sRQ814I+JpXwxfUvC7WaG9N+jb7L8B8+NNP76ttC +TtuHGJonxeMg/hyVCOY7kQ+FB8GyTYrYYkraaZC+jEVMO0+yaeXVfRM4KKVVbcqu +X7zN2RIRmnthC/+NxFhJotXBMAG7GHvzTSSHZ6lcUeZFq9bPA7eP7b4WDopE/VJu +ZdMAH14ZV1O5RgJYxCl0WiZZkNkEVlVNMjaoNnhGr3POw/psfbWoeLYodB1LPYzz ++b0FXhf38w9cUPl4ZaxrfBhyPoRM7S3PYHJgEFPhgoh9Te06NtmpZU1mVUT22flu +pArKv/yFo7OYglUwFCxhwHqxRWOAxzy5fzv7j5nuo8M2ZqKYrKy8u+XkII2wjZ1c +34RimT8vOIfCiYBAyaHqzoOzwgTfy/9pX/6OEjsgZUHDy5vpLsMdlbD/ZWA0Ul3y +owPnXCNM9yLrYdUCZLPuJO6x8r8pFmiJp4eok6MabgWqTVfGeP2yINCt3JvDMYk4 +++unEQ/zsamm2SJaBFQeG3nU6G0DkZGWt79wtjkl+W+M8uNt8xzP9pTj+NxUQQcc +We2mYGJYD2+cS2BjXeOYt33CR6lA1laMJoHZNtki3BYw5Z22sUfs1Cwfzj2Z14Vh +NJw8mY6ujZ9N0riokpe4xHXnjvzK46bxdQWl/1T2udrXXrLVTe/R/Wy8e1Rj6Hvd +HHMMwfxTTzwMPktSkAdSksjWZvhHNaiOW5mKrxVm4c5mLUUqsDHmIVHpaW+K8tba +XiMAqks6qwomtezMknU7Fgp4Ri0SstLi6ZL+D/YWxy4mtHlYIzS9jirAXWgeWgoi +SC40FMzLxf0q4h4cIyL/rtcFMYperNMqw6ylZ1U6Ei4GVfYAeTKo2nSElioJ0i6W +2yJ2AMLe5aaiByn+c4A5YwxBx9DdDBUlCZneIYRLGLK/NXwdcuq4O9jKXEEzFA5D +QjqoW3vuQIng2t8tgxlbmsKToLXR0fJoZHAfBOh/xDuVUcHMRwIU4G62/xItkhal +GTY77ciqoU+bUhKqgb0tuzfBpPcB2zxTrMwMjlvW5pvjdxpEK+YFNYcT7iQBxwZN +rR5Zoft++HRzr4Kn9ZljM1LZgPuQfpV8kjwCZtblJCV41P29hZWwOr5JiAkOFe9G +4zPD8RMYHE6sSD849NuLOuq1y3oY94QhbXUDUs/3BOUKO2aaapd/i8TMbOStSO0A +pVX9UE58lW5YIL08HjNjjMZMZDC/8BqbqzSohXozQErjP+oz8cG6uOrJK5ZlBq78 +EWmtRYIrUnny9gt4PkFhwOFn2f4+Hsc66Iifiegmh5fcY/jCuMdaIN6shNSBX487 +UcpNlWBvJp4oomXwd03CNkuKPQPplysj2V7Pf3i1tkQmkU0LdWpX6IuV+Q+LZLwh +Vg26zEi3SNZ44lUp7T1XsJFZuTpTK9FKIKL8A/P11nKIWwhUnOzIHjLLIompDDnb +AkcnRCnW0fSa4GRT39gY6ktKt+rFpDkciAlzbwxM+T919dlzVfcUZyVJOzbtT+7R +sdZ8NpChMI/Iy9Ff4YphPbd+hIJ+Qv4ui6/EPzmoHw7lQ005/42eP2f5Eh/Y5ovY +AmG6+1C81BGNGukTj3qobgJdcpYy/T6GrA1WWHGfbaDj03yvoCHNBFU/r1SiEPpp +CH+6H0xeECDDsMa0mKW2h+5WerWfA5K3Do6nrloQ21Nq8BcVqjdWGCyOjh99uq9i +iXlsLWjM3gCokJ9xYPbxNM+K3J/PUvRLiEKlQmzDsaCwn5lvk78S9Uk5LCW3rNwI +3zdbyU1L3x1Kn071EokI8b0Hwa7WuYumD+vhJNIrjDUgFCw1/xZhRfsLTOKZzKnK +3J4e3t8hQORx2zd7K7gou5LKO4S7cXgvvNXXreQpLGVwsMbp+L5I1qwYqzs423Jj +f31kHaAKkIow7BjZ0oApaKPfddN7pPmcuKY8MWYGTd/vivGxvLcbeBOenjcKQPgV +NBNlKJHzzOBLRM4m2vLPUPL9xp4LDM2sMsnhYh5DTWY/ndHnZFpYLlKFZOS1P2ja +k0ktgUzNQDQiK3/A/jA+nWX1/8SykZQvB6eTsd1HmFDIRy6R7mxvtcIiQMN+/1CG +NZd77ZdYlogTu5WzBXMsxu/BQW3friD0JlNwHmkDfWiwrHMsciBPUBA+ch+p+3qp +4MNKawrjn+1IJB7wOmmb9/o88boDDlrEqTQmBroVMaMfB8kflhkm05pmwidUIPQz +IeB75rqyazuVu2S1VWd5OhfxaF1iFnwvGuGVDCSEJAAmVMqJju+SP6OlfKan5ZL5 +K5VMzA8jzR5oTliUaovCfAkFl/m8yCNKbK5ez+q6Fd6F6y1jf2LFsZPsg/NshkvH +L5oKx7f2b84+NHlaJy7BCyaDsUNsJ6dgXZ5Gzsx1jEGzqK0isp9ECdkIKworTp5z +SDPjKlO4s7hAAK0mQfHu0H1Et3mYOnAqqJyV0Z8oG/p6P+y4yc8kyNN0Dqi4TYxX +fwY9Iotu1xmv9QsDWGG5pWw7x374GJ42ST17LQzD7XH2yY+vJTnHKcAM4uU0+BsV +ALkX0Ly6tsEKUnI8NFUrfhHQ6TeWS17oN9Xg2yHL7b997d6IH7Mha4ReaBKY0XHu +vi2QAAIjQIDEdPhdUOhjCPws81bGcbA86uMu0jVq/nRpPIxe+Tn3Hj4J/cUjcRWl +ypoXK2mjxHR/GOOQwJHbrXLy/pXjs+eO4OlSkiCiMjg3vb4n4iPYt6Sh6Jc7DXD3 +QN7OarSV0YkAZfi9wPqIhyIBo3uMPS1ds95OsIpmWNBu13DiuLYF0G+572boBbZn +uASiwiF3OXN1MhCgqQi+DuvONxCjDFAvtaCPeL0ud/8GmsV8JpujiM2dntZJdLaS +DaAHCu5AkatyqfV3hVBDze4UXb19BAPMggn1FfpDM6gyjqwQUMmzATT6qkSIFhhk +B0qGBXoUcy9sNvEziJ2UOU8VMru9YPLegjTostbUzGUL0hgdJXPDTyGSGVw7n23m +zxoJIMMf2/NLy0mBU8V6K8AvKJKLQrBWJtMrd3L1a/E8eX03rE7Y8InojcFWnk/b +iGrTYoez8BDoM/1RKdtYH2NLPS+7YCFqQ0T3jdrd8H15YSkvk3QFOA/OWd9yRSKq +4TUlJb+I8a5ir9Hd+5690oOhgIPi2N0zNf1d5GfKmR7CX2yEb66CDXEPDUgjOUiX +6HAijLSmuGkc2qCBTLFlNvpTEBzoOF7XzLz4qHmBp84MmA6souXgOXN3AmZGoJYF +S0g3IBAZH0rHXbknkDDoVxvoNJpDf2Ls1XA1ai5uFkn/zIZ6hFh4ervZwiBxIYO7 +aaVGgYrSJjaqyaq1ruuRyZorBIddcRSzJ+ZQBwTn2wEuDvFOWW5ibS2uQ0AUa7HY +ixejg9bRMfAligkf3ljww3kagoj+y2oqcw7VHcnpr0t4v7nxZtFqe/To3e56xzao +xhwjXzkvzo5KGQoDWNOWV5x3lxPbdJt0VwOu8YvdsNstgz4ZiZ7fMsIHTDAClQk2 +/oBud9lxPYyV2p9QEgul69u451ei0ZKiACmi5WQjxU6Yxo1ETkY/DhANAH6HSZzB +jw77tYIRgQBxH+MR/sVHNYGJITEu6av0XqDIHGhE/t2vxNHKKSqBFfA2FgBpx12g +Ja3o3NXvsJjNlmDlnbl6bkM7daG+XoYuVwvprn/jYhzNx4rzLEcS58mTCAXPWmeW +TR8juv2fFIBCO+1iTBkMNY2E0dNzts+mSWkw7WN0FKq096/VbcthWiEhQ0VsT+0s +uI76zxj6UG8uDMc+fq1a8sg07Frx98ofO3eV/GsRNQw5l5b3A5NBcJ5LBj7/OIbq +3NotACW7ttheQoEbYKrHCIlnBtNiIJS1YSRedgCk8KUWCbcu9yyDhnUV3KmUtRUT +sQE5vgAhYV5m31qPX6pQ7KxqBfQEyD69Wqw/toc1Wd+MlU1M5JVIQCQhoIMEw2xa +jsjouJNoqZnI02563V44XPJbY4IKmSvt24dQx3EBJ0yNESGIxsiVc6Hz4zUEyop/ +r+Bxo9FRlnnT+kgs7TJaKMgR2Ws3loT5SZ6B5SaEUTcNHRII0FZENTwNKeaO8+e0 +eVeqd4ufQirMvsp1NYNbCYOA/XrBtMlMHMCpC3CohiT3PkSrxQ9QC3E5nF5703eR +yRtKSFTWeNrOA7hOOKuvyHCXeZu66UlUS40xpY1wgL7bTQNQV+YFu1uNyPqGcqjV +FFLnzUQ45P2iQwQk72aQsHWGGyd4E1fqKxKIGwKOtVWCf7Q6Dm3Xx8xVydKox0m/ +tVWdzGSO9PrauRjMHZVb8noPuZgGcapRKB3/aU5vpCx5wFw7fZkFffYptPJqGmVh +qI722UljmJlmuh3mq571o6fUpJ/JU23AGr/t+tvKFa7hWJ5oZqWwx7LJHeTocjYs +VC6da6x2ObCUJe+0msUsy0q4fkkhhR0bW1Pds6f75ACERO5n+A0JQXyoBV4ZmhI3 +UunYwYzigp8QXRUjByJpEuXkn70/GWkrKizwQO+impqkU9U5n1Lt2dYvG/1vl030 +399/PMkH4LbHqogl2ZkTdTWsIBHfCOwMRWe82/ChavMI/D+IAnExn56Njd5o/qAz +jSsynaGgw/YyCGIg9/pmxOFqoNdXvhwH5LypfzVGl8bNMlekH+hwIiG0ofk3ekYk +6NY+tgjuyqRsAykEBvrm3m7Ek21tuQJrqYN8hlOu88dYHFu8Vv/5HSSXeY8O7M6j +FjVCS54+jyqW5//xfntNor7bhxZnGMVbfoWHy3iV5RkKdgnec3LdePOv1SiQgOp9 +yo/qTYbD38W/9rBuUJekywtMKxw5720xclBFcnqxr1a7J71bpSN0eSxMmNe/qeFm +HVz4jW2acgkWq6nA0dTA0w+rG3M0pxY53/8Wq4iIl8dyv9gjkE1spJkaAf8Eq8kg +i1GDttOdlD8bqKS91UDtS3ZW/yh6pu/VAafUSbaVgw4kOHSD0de2anJDUERrLXLV +wgeUBApfSUBPY1RNBWyVdSambpcfP6vE1IcqFGzk04UkQX9Gn0+vZL2foNXVMCjd +R2W5nLBAdnLpAgWvXLTvsYWj5nYOm64sEOb7UdOkLBSgaoKxeIhzGzQojjaV3quo +H076pm+Q+IGdO37tzxuwV+pvaSoY2aCYw1epP7ACtOCwH3sxReJ86drLIy3WRt9u +ZmDfg2+EFkxfKsoEdxsofPEwBNEG+U2I5TkdiptMXaZEB0kFY1l2FJG4UXcHvbTb +x/uHFwd8ud30+FsoXtSe/kFcksOdGbD57ed7tBxlYIgYBxxNmhU/yOmieQ2f/zFm +jiYEzfBPVAAJ9PLlbQl0M3fyZhB8Iwn4+YMnC72H6xxkbGk0gC9fHhDozcgNI7vp +/EO/cxr+njKWzrtiFxJ9qsUrY6T5LNsROJ+dPYf2lDKsOo5O9IZpPaiSHDmHn5nl +JV12pVxO+aBIED3ra/msAFF3dpgHjJ1lexcnaou4QCC+WfhCL7WXLqfG4Uhxgwro +XChb5+ni1x8CBTQlqX7/GzGRdoOglarJj9Ka2gVSSc1Xfef2OBIiidy83bewUDrW +7cJmEPXrGU0cxSDtzWi9n25XC4X0oHx+r7w6mrkmisQ/iPwNfKtWatJpUQkNu3p9 +oopRkBz28aGYjm6mb25tb/x7QDKFiQMMU6zxlNHjiUOSdNlJKGozu7PwlGTVhp2Y +UfZVmFaaOgU11g8EI6qLFlbyXfh9ENChLuW11yCANC0wL9Un2Vd7LzOkmRGjWuGM +PFXaYNvCT6D3yhKRWMRij+2rbzKJFCpgxz6iA9TIEZBK6QWRy+GSHf/vdygB9zlC +2XJnPuubwq0JfCUPAkz3voTu/M/+x+km7QeunOhn6uRhsCM9ELLtuafkJib44D2c +KN3sT5M6EL6S6f+F2aijU/MHolemxdwDKwCHX66lMzplEBzA+M6vn4dss7aJnnzc +Nr5FnoOcDcQleGpB8kD4f5uRa4TuF3XchtTx4n/n/CqGHfyUvi5Do+P7hDf0BrAq +E0W5Y+iWHxxmmzpWI6lte5Lru2NJeHbJjpdeI8PYMbkczSGqUkgo4J7La+cZIaQJ +DxStNs9nnX2mc/iwlJ4Jm9e5E0A7rREsWlEdZKIRcwqguL3zE52D9YBg9/x/CVEr +gADP2N8GypuvzhPSrrpzq+oLkoDkeyXtKdYVvTQpDKh185VsyiyQ9i5bNC+irlfL +HBG9G0gK2L2Bj8hVzLpfUeTTNuhsrsiRp1/s4oL3xb2LJHxNg0kJ85f7T8lArTEl +7leh4luvW+Z06miOJq9+0QBfFLgCt+TcudtFCoabHzT4AfnKHQPd6txVhabYOdKo +sv5rGrHKtEG/xmzK8rASS0SISAFHEclTgJpiOfRkOqy6BqKUbQ/+7QUxzYMx97Mr +46NupjDMi9bF4jFr/dVSVYGj92oF7JBNkklHigX/Xx9Z86sHwSuEnrzDQHRgu8cP +dppodcmktt6VZmq6+mFaRDyVVsw5CLI2KWWm2i/TdoGFL/0ohijKlevrG/yvIL3I +z2V8y1dQ0yEvbd3HwVKx0Py7bufN6GqCewPL3ZISsqJwSSAtWb4sBPPoSNN5lEn4 +PKQvKbNUXTwMftLnLxrFWvcIeJwY41nxBT8y8GnFgv/T+G0/wmgD8Tl0GUJKMJtB ++Ie6q081V3VTMRNF+Ce/EJxcPQQU+MvHxU/qiWjnMpL0VLJZ87ZfBEOpPaROb6rv +ukSzTkF4G/AKQxanRsjtXLfdS9tlAv2VBUN9U1pdbOWWzuWFWKKvPGsBL6fbjse5 +ZFE6r3vF+zQAygMWfs4Vj0yXXMHK2ZLSo6fJLdc92kq0YqeDfsftih73YPnzWmaQ +34seG+ZvJJWLjiRUKFNWHeXTiCg8zbJlTgqHcpC33GMCjtp3KreRDrfbFiYwyQ0g +KkaZDFKHFnm9HSHqgCeks7w19AXFYbtMX/ZvlLSILQca94UBq9rCtLfTvCW/ZfiV +fa+lIQjE95IMQQWI3m5jSa6VaKTWRhroTHzkLi3mR558cboV9na76hbW9uSnDbAK +X/YpfIqUtjKYWPFbFG2AwcAEzeqL2/IdlfnraNUtke2WirYQZ/6RY+uLB/zohVvP +FmPDLsdmaknOCweU7VG28/FBjaatt2G2unQQiIQ5rFxByGqV/qU0hyb3rbXmMa8f +ZbfppdaeV5kzyQvWo80WB2dljkpc1D6xHQQsRj66k1dBX6QDRUOTHpCQxeYi2AI8 +0NrUNpB8wiWNDgPE2v6NlIcsdH/2WUShf8R8sZw5iFFelBSOgxRLOdPXam9PF+zx +7+QD/Qd8eUhJ7MYI57ZEGCgVZ9N1jsHnMEWdrgSmDYXlN/fKkp5LdH4p8gFiDXSb +8sn8VWwHkZTOdY6mWeLcWhwrdLwZqswchAJYa4PkvKBbQ+wKRx6T/LYzyPxhTIUV +rwMTAQYBhi5cX2yjHONoNIZI7weo7cPlzaW0o1FcqM0eVTneJOHtQDu3D47hXr0P +QXesAYHITl53s9VTI55tmALAFwpIy9y+4ihPhRUOwXtEf14H7h8X2y4O+SShAwZz +OGp9OGXTIoFE7zk7TcvVCjHNtu8HtFVmj+Z2ul5mzk3lDlUpujJt0sICD3ygD2Fm +k6V10P61dbGv1ONDiar+JtIcP9jDO/wOCiP4IPJbUbao2fukGbmvBYYslIigYpl3 +wuw+5Jb+sISyj7kf32KcfeM/LDBG21Do0+X65891DAqHeh9u5vLFZmYoigM53NLI +Cu9byMB294IW+BWcO0gKTI9R0L68lWbaS8+oX810TZBc+YbX3CTN6ENZLmVTfQn5 +p7lhm4fUOVKsPjoyGtHDnuA9Rjovq//3X38sIzYeWs4VCn034lguiFLhgPCUfLgS +BTtejp2ck8kOocUBpD+0DHaS7sBnaNCP/mTNcO601kA2VDuHaDMhSHF1TYfxhODV +7vQD0k02GJzN4XBlmAK8YnLL80Fucn8ma+tFWc+X8UP7zkmzy1IIU0EygR87V5CS +gP+IUktSIiG35ZX1TTwgSe7FDaQnv61hlvBPLs0x9JfYKOgWkTCHR2qlSmzD4PG8 +/70W3ecFM+FUbpiM4SBo3JryqYJ0+yWwQLyiaNDyKmnXRT49tk64iMNXWl+kWdfG +/Fwz8Rk+za9XjQmAx95uYjVmyyCfETsPA/5DDcbI0td/MNYv2o0z6W5D7WmL9B1z +546pBdsshFPM7/hE4mB5X5y04zhizzbMb8Coo4fgpBb90VkNNAYQBi4UwJv9n+J1 +ldynub+0u6j3p/zcoYmMtpLw2gegR1ZXNPMxR9Qm1QIR0JVVSpxBRcf+K9mhzs8F +Ox8Ggv+Uhypjem2ZUMVSqb27S5WsuoIB1HjlwZ7coszki13/lQZEbEJNLuwbdOFD +pimdhfCi/ONo32XIhC8iY+4pXTnipBZggpOh/lQRl3M7GvLc+jCVZp3CkrfqiNEA +zIBILvW/ZunjXPDQsTlyKIwhP7XiDZ/Dz/lznY4+hD+R7sgW+9yafxS2eNJqgMp+ +dJbi7aGJ4FKazelznTs2CQJTD72yNw9sRTKlMC7N7pLkqC07dSWboyR+bTAs/TBd +OXtL2J0v2E8w3lNUe7nxiF6eF9+QEOToabFHMFb7n8s77c7l2qVQwkHbBQGqMk7H +3WrOJEGwm75Lo2hbc5NGRVl7j4El62WeyUMot75dw1wEoGESP6Fsu7sJe0z9zzU6 +Xw0bcCytDjEze44CfHdVYiXffvXuij8rHctQJ5o/G1mzBdkwN+XkLOYgTDFCm/sp +oTZPiCF3sk8kKhdGFbJq+o23ODlb5bLajR6Rm1s2ge+bjmSs5GDQaP5eeSgSpwYb +OGem4TEBk4QzOsqBB6zjf0kh/wWrIpIhA9xk9iXGPpd699kIkZDi5pf6h3qcvzUk +3s93MQUSKzruPOcr2yQVb7iGu0Gz2M/pv9/Mtp31pxAgnll55Z3BpTOOUaZEwgml +5TWepx8GCpW9OqEO+upsGbziFopo+C/do0DXSnm9/xnlwu/X30v2S7cqum28WvS5 +tXk0AsCk9YualDIfHcPO2Q60unalwJYldy15vvatVZuAV2mAptlTJN8ln+33WX5S +I13Mof/NpOMPtDH8ss2Oo/sSD/OV7XVMDXrW/PD9bqUoZ/iXmEjfWyz7XGL4ADaI +M6Lo/GGWEDHosY58NJ6CC88NCkUD6CFrGS80IaQ7AN0mVhiBXOZLioYb80oogLaV +cE5eP9l/iMzT0possC7ELFmu+/5+p8jC6iYsKqrEb4l3B8uAKNCqtfN/14dIwfqq +vO42q2T+t6DCbq3fOSd5GY/RNpIWLn/6dDK6FK4IEewXzwEtKHmQH4fDku5lk0JQ +bM9KwDH2W9VljdTYI7aIfH3Y42jlN4FSmUEb+DbF+scFvbJMfnBDOJgeHkDK3R6z +IoQQM1om9DLC5FNkg4TqOGYTwkfT97vt+d5tyV2ye7rcLE9hNm5F9yQHKItOOax6 +zPh0IKEHEG/4ku6KRqqrwja/xiZ7PyA5rnJ9ZH55WkLZQKugts5nzMJUvXp6z+MK +oQlJJtwvHo/1MrKFAfLpa7wy6Bc7Gqf9Yw+KSCqwth0NatUFzMRslP7Ml9bI2oWo +Spxhn5eDg57azij9TTf2sz3weRudL7GD7V5weVjTBHONnF1WMZL6GegKuBMsHlEv +YqdvS0vjx6z/oj1TMd0c7Lj0if5+KnzhQnqAC9xK2W45MyI+vbur4Qc3PedovOVh +0T5LaLUTa70dcEyY2qIFodC0/3U5OvQERCzDMEmLO9ZBYoqh/UMaDTkcUTTKt+7O +xoX8be8dbBwUVuy70ciSl20wpJV5XU9OuqR6XkFxGyl0EigAphwSBlcGWY4E12wT +i0ZBi4U2s07zcZ5B2lnUNgPmnKybBYgNK6wPfmiRvVh1U3TKXwDjwXyZGJ1cNzXD +WOZZYpZVzi370IwA2B+rgFB0zkpJ3DEzq/BFb7+HiY2N8cE7fPcdYXvRgTJ0cG61 +Gu2Pu8S44wS/yCKYVmwFOoAMZUTosIeZxZ74sa9kX+QnPst1lXIQdQXDu2DuxrLV +u/fy5qNv48nexKUo2rx1FRRYt3Alitcn5zZBx8V/4kKQ3JxbZltuCd32bd5aDo7a +TTrtQXFePjFgrFc/AlW3VQF59v94L2syU6iCU14N3w54iP4/Q2tmn13YmhPj/BRX +/fjibvBLmPCixUcUziY8qK1EhoF76vKGywyCzB2HeYx3D6xA5aonxhNmU2zBhDuh +gCHX04IDJpucUZlneo8aVoeE2pqJlQcBrypC70JcJQ57DFNoJ7ghgJHaf2OFoiZ2 +9wvGtFCQok8PidRGO4YENMSN30cMTUTVeGxJ4JoFenCwUo06MVpHQzJpqFP83ZKG +5x6oSJ+jKLjnG8VnZaDHUzaFFotkQBhPyV8EQ5eC4t6CkNbqmv9w/HE6wzIU1v1g +GlRdWUj6qjTrV9n1Qa9CCc7hpRq5JA15/IAHGtoCUlxIJiMBxVn8EZS59pDLhWs8 +0BIr0z8XvE8a0dd9/FgseTXY+iwqIstT2/G1oVNR1Gzs/UTV/BRdwNTfwXHmQXIy +pjgThWREzbp9bH5LDNiTxw3drvp2IaqueYTCi7Ye6s4QM2yxg86gtQzCz6VZQ0bO +ka+xi+Dp9pAuK3KEhivw9TjXnLzgO0ZE6QunxqNqaeazhRdjHi2Jppq4TeqOrHOC +b6H4k0NOfv67oL9c6QloPbph7cp7FLGXyxBvlnt9tlcVxG2NFJgJITY2i07PluPm +6hjnXLHhqXnLBqqXkpVma1vsi8g1OzfLySoJg6hInq9TMHUrX5/K8KPShl/3b+qm +6Hsw1bvtqYGcT1J1WeGzbl/7GvYsyCylYrPZXrvNxSPoHTaYWHGcf0OjJGK/mToy +RayS/hK66uXEIhBGN2aXKDh/r0tX7u8Ir9s+0vJiXtbUgFJBySnEIQ855/g16iWS +he4+YMME7/7nUs+lSDBuw0Ykp9okw8xYiWXb5igorLlgvsGaPMETbayvh7rki8gR +qyWwIuyemyDg53uvq3315wRwViKiBxJSaAEA6vRqda1TvfgUohRTll477QscN2Jv ++5YiYlAsAphxEilEiShu2DbAZkwu/fmGxIHEIrBv/U2weLh/ZgXpNTD/g+eqmHR/ +fQkkmuRzpKESs1OigcQHXXTpECZfQo76nIPZeT91w6EC8KT1IybER7D0DsuB+mur +uFGk1r0WEySv6EisY4KByDe7KklwxdkH/M2BzIrLAroXINzSCQfjOW8VYH2lzIX5 +h/6FhvDXKkrle3lt+wZgRqQMYFtu5gPC83xNvjHOKh8lzLwByQzwBzclpWbm4o5e +sq0gEBr9QVGWOo/geRkd+f1m47QW0b3yAoZM722MPe0K0AMzu5jsSOjkcubTzP/L +4IH17J4p1w7+g+4Qh/mdUvIOpy77Dk/TKGOyEXUFM5lmH/AQ5Yfl3WacSh5REzdf +MyZyKSOucvEKAaASf+jvTkFskHDahmJSuydKJ0G2gkYLFo40iBlnSGR7oFXpCnV8 +m4BNKiqo6uE6EM9HTzAVJbxQteVMIpvIRgUrR/EwWK6Ok4YciNDVJKfuaoyFlUeF +3tLF3maePfNlJPvDjSkRBC1lXhEFeCgbBlpee6Gc0Qr3PHIQyl9wt655L0EsEDbQ +0vQEAZd1d0xM7S9a06BM0iQ3S/LpB5Cp3VYustJMrcTp3J+VpjuRN95UxdwPikYX +Vj6fNd4OeZcBq3fJaKsIrs3eRHXUeXtvd7Tn3ejNTXR+AFS9uUwiyh2NRZFqEsoJ +E0x7EPc/WDWVZrW37uyC/+yZsvFdUcjs1vR0JM7GZADegDSJ7Sc+995hggaYKB2i +i7J2lxo5WHyuJH+HtD3EvIsjIvnNsNKdzf59OkGBOILC7tY4yq6nNw47GrjTa1IT +a7/Y5Wb9Yaov/r+6BT5ru9xY3tdAUQuhx4Ih1GhggUQlVIQXB357d0yW9U/eqKKf +eL+GRPmbtHk0L/Fkd2Fj26BHaaktnZ6QwDlG2vrNE4Hw+K08dip+LSmB/gtml3Z9 +ZYTY20xKEPFWfv6Nirp+7EvHluNB/ReBoo/TVUpe3QbwW/Y3330O8EXHqG/DyYOJ +1qE/OOX96hacpZ+le5iCr5jm1ydT0ZG1znmbgt/QVbp1d0ucbmlMY5WOj19k5Twr +YkSv8PESPSFzeZYiXVuiXrzbFP7v4kBWGuRdFN5+oUrXY5b+RlUhf86t69qF8V0r ++CpB8rdypexXvgwp4uy1ygxTsm/uTqiryBqdihOTPWoc0gQfTShqxuyi0lviLocC ++t+UeCRs0aOh0aSBSMI2BZtdv45R5+uLFdhKg7AGlSliv5yuBsxc5qocGfVKXTiO +Hijec/EoP8RnW9rZJQdmvRveLczvWV3ZSjAOCY5RZvekjnFvFSJvswt3pUT0IFg1 +uk3lTkaeFuSa/Z6Mz/NlfzwXtWKbOA3EelrTKxUbJGBSxLXGYyMsiuUn7WFBJxIZ +5bXTXgXBOgRy+2Ryyw9mkeeC6XtcjyxIEATF05m03eNM57xjkjGTKGvyEfs2iwAj +9NDh3p9aR11DoYj8YPmlLVYN3VZgrvOf/e6K91hZAv/FUvO2X63OQI1fFPZGGRsS +jwPn7xjIOgd2lmLnzE0xYANo9mMkIzL4zinPT0JQlMI7KBcswuP/0wSVg5TucgoN +B2fm+XDlqg0cex/7HenYc8KL1S9xSAE1zcnhjnrlLQvtI6HnUDbVRI/OKpMhVMba +VifOh08V0mEPGz/vAJWfAd24HuYrMViRqsvDJ9M09xrY4OyvCo1FVpd4ikIFmq3t +a3q2hVE2sOfMDi+8j0BiFMnA6g+S+WyZINjBpcNRNrkamISnA1nLDZDTfu2dEEG3 +XPEU45WuKZjtkr9WRSfDvwwqeziMGvNgNvho8xlVEisEBM3Q6VIi3BSU7C02H0V3 +vrpl8dJLXIfva3elToc0PM/ACTHwcRLu6MjiwhMbdRW1uj4jPQma3Sepv9xK7lab +yMbQr4wajTbNofCytvdjTTj7M0NXeZNRj7XerWDlroTsrTCfkhkUjFIKcSU4blzQ +Cx4UqxFQ7KRsk/T28NfT4Nz1mDW3rW57FsYdnlB+puAtDU1Y6UtlFkvGuaxxn+92 +J5iRW6S0tbLtNXUPV22Bc7k50cZavZa6WjVvrID/p+TY3+cq2MtBF30LQl3+70KK +hLsxPXtbGosv4PiyCSZq8xZ9j/LIo1zWLD6JfEpSQ2FXZZCwNry/jcPAAJ5/8F4x +1FTx10b/TNJlngPfzw0voN8kr5cQ8j6/ApVlR2eVLNUlqsj9K+hYS3u0f951AQkL +NynLXtdwJ1PmgLMlgwAwt60K16X5dvfLi4N5IuC9C/fDlePDjLXg2Ri7ArfcTflD +xOCz6r4TnY3Sw1SpnMVNdozseyvYIJDRFX2F2eKJXoYN9apBcJXM2hjj0WYse7d1 +/R9zI4Pb8EU37QSHlFhvVGarw92Cw+Ju7E7DaSFdZ6cmn8aoHOSkftJSeVKcYYMC +aWgsSODLZyzIAD1+XNsGPSSwqRxbfvuQ3PNl45FEBRNXxdfbjuw5RaXvMlE4qV+N +DjZdDDCNsaA9HBxnU70jgyzny3vWCFstp44Sx+NApLeWL/f0TkOFYP5tUFNmm5FD +N+LqIjR6asXkboU9A8KbUZGqyJ5DfsEOlqNPVgB4VqfxtMTdWAEnl0rSfhPFvJJT +XgrcfpDdB3WP2X8DOwvLRwoGF+AL4yiCa60txCSsDIaa4oOd5KWp5jieeJF/0/Vl +taivJLjRlVOG95Nnvur6sBhWU4wVcXyLPHRb10VDB4za4BTuHb3euhT7QAIiR+BK +1Rxl8ZeSdNkFKtrCrmo6+4R153kJ8RXY6aTnOy49VIDht0Fvk1k2rBnGPRbTdyf5 +cf1sQ988vihDCsTSuSR6zVjyUXnms+7O1S28gHJhuGclMdnaVBSfgbmtM0qtEKg2 +eCUryjqkEyTzgh+06TgL9wPkzEOOgbe5Rb8DMQh7OmYwedx68QqMz4W0gK6HGcZ5 +lT9tLYdBN8E0gFIhOma6cYzbBum+MeAtbr4uL1sUUjQPwudCmf9f+wIQAEkj4CbD +LN8FnCuqxToGQPYMDa2prI+c0qklW2LChJu+aDecs7hw5PptciV0bJTa06DSlIGn +3QknBQOt1hEECSBOXTzim+f9QiwiLDoVpNLcApURUGFRhG6yhfgSlxGu3j7Nf0/J +RSvEoY+T4pM/HUShM9QiXi1tFUmcoDMctOJfdy3aUwILnbM2Gv2MD8fNLTPWbPD3 +Z0fYR09dyXf0hrt36rDonu2rGG7hbVkU/fRlgbVIo7ex0vv7dWrzdvifBiqTvlUe +7yLPP09m0O4gU8ni3UyAwHZUwGpRF4MeDyt4aOB0kp+sVOjhzYD8+rRsHQ41Jqt8 +GbWmwSR1j/jdo1TreEY2YQpYxfGWMya7OuXYVozwHookyZbjTgSJ3s7WVl4D4195 +DD12CaVH5GbLZyziVPcac0ab5UGv6tBvEeDvKfqdSt0SRUYp61DNzr2z2K2jfdX2 +8g+DRtJ9Vn4vqO/u8qQm+A8YZSKay1W5nplamdMxMB4qDfxiX5nIXl+kh99zZrG3 +W/Gn39bajdOLQWDgf3N0zavbpOYYhw7Ci5Smvl78gWPFQDHD0U+1Zl3KV/MC134d +JRGp5mRq3U8okuTaCj8kDUQgXgbSch5vQkj8JB2zdHXHPCISnBOlOKYClSj/7g7o +mK4a7z1tte27d9fnrzKCLurwGTSvrX5Tg0Z/GKcFz3Ukl0KXKhoz8IqA1KvI4+Wu +8/nen+O16/Attdp5hS1RRDhLK74gA/WRbxYxw4CnPDkv9S3tS6L69Zgh2b5ARm8f +qF+pfuqrZ19/oOXQrl/5RacWsNUxVR+WsDLiT9dxcXucxq303L14w39n0PDYp8/g +pcvbL9TrOnR0FFUQ0WltDGNohS4lijJ8dYQf1JORSTEAFQpZQkxhpGajOY2bziIB +odGVCw643lAXsgmg0EE4bw== +`pragma protect end_protected + +//pragma protect end + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_top) # ( + parameter FAMILY = "TRION", // New Param + parameter SYNC_CLK = 0, + parameter BYPASS_RESET_SYNC = 0, // New Param + parameter SYNC_STAGE = 2, // New Param + parameter MODE = "STANDARD", + parameter DEPTH = 512, // Reverted (Equivalent to WDATA_DEPTH) + parameter DATA_WIDTH = 32, // Reverted (Equivalent to WDATA_WIDTH) + parameter PIPELINE_REG = 1, // Reverted (By default is ON) + parameter OPTIONAL_FLAGS = 1, // Reverted + parameter OUTPUT_REG = 0, + parameter PROGRAMMABLE_FULL = "STATIC_DUAL", // Set to "NONE" if not require this feature + parameter PROG_FULL_ASSERT = 27, + parameter PROG_FULL_NEGATE = 23, + parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature + parameter PROG_EMPTY_ASSERT = 5, + parameter PROG_EMPTY_NEGATE = 7, + parameter ALMOST_FLAG = OPTIONAL_FLAGS, + parameter HANDSHAKE_FLAG = OPTIONAL_FLAGS, + parameter ASYM_WIDTH_RATIO = 4, + parameter WADDR_WIDTH = depth2width(DEPTH), + parameter RDATA_WIDTH = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH), + parameter RD_DEPTH = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH), + parameter RADDR_WIDTH = depth2width(RD_DEPTH), + parameter ENDIANESS = 0, + parameter OVERFLOW_PROTECT = 1, + parameter UNDERFLOW_PROTECT = 1, + parameter RAM_STYLE = "block_ram" + +)( + input wire a_rst_i, + input wire a_wr_rst_i, + input wire a_rd_rst_i, + input wire clk_i, + input wire wr_clk_i, + input wire rd_clk_i, + input wire wr_en_i, + input wire rd_en_i, + input wire [DATA_WIDTH-1:0] wdata, + output wire almost_full_o, + output wire prog_full_o, + output wire full_o, + output wire overflow_o, + output wire wr_ack_o, + output wire [WADDR_WIDTH :0] datacount_o, + output wire [WADDR_WIDTH :0] wr_datacount_o, + output wire empty_o, + output wire almost_empty_o, + output wire prog_empty_o, + output wire underflow_o, + output wire rd_valid_o, + output wire [RDATA_WIDTH-1:0] rdata, + output wire [RADDR_WIDTH :0] rd_datacount_o, + output wire rst_busy +); + +localparam WR_DEPTH = DEPTH; +localparam WDATA_WIDTH = DATA_WIDTH; +localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH) ? 1 : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH*8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32; + +wire wr_rst_int; +wire rd_rst_int; +wire wr_en_int; +wire rd_en_int; +wire [WADDR_WIDTH-1:0] waddr; +wire [RADDR_WIDTH-1:0] raddr; +wire wr_clk_int; +wire rd_clk_int; +wire [WADDR_WIDTH :0] wr_datacount_int; +wire [RADDR_WIDTH :0] rd_datacount_int; + +generate + if (ASYM_WIDTH_RATIO == 4) begin + if (SYNC_CLK) begin + assign wr_clk_int = clk_i; + assign rd_clk_int = clk_i; + assign datacount_o = wr_datacount_int; + assign wr_datacount_o = {(WADDR_WIDTH+1){1'b0}}; + assign rd_datacount_o = {(RADDR_WIDTH+1){1'b0}}; + end + else begin + assign wr_clk_int = wr_clk_i; + assign rd_clk_int = rd_clk_i; + assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; + assign wr_datacount_o = wr_datacount_int; + assign rd_datacount_o = rd_datacount_int; + end + end + else begin + assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; + assign wr_datacount_o = wr_datacount_int; + assign rd_datacount_o = rd_datacount_int; + if (SYNC_CLK) begin + assign wr_clk_int = clk_i; + assign rd_clk_int = clk_i; + end + else begin + assign wr_clk_int = wr_clk_i; + assign rd_clk_int = rd_clk_i; + end + end + + if (!SYNC_CLK) begin + //(* async_reg = "true" *) reg [1:0] wr_rst; + //(* async_reg = "true" *) reg [1:0] rd_rst; + // + //always @ (posedge wr_clk_int or posedge a_rst_i) begin + // if (a_rst_i) + // wr_rst <= 2'b11; + // else + // wr_rst <= {wr_rst[0],1'b0}; + //end + // + //always @ (posedge rd_clk_int or posedge a_rst_i) begin + // if (a_rst_i) + // rd_rst <= 2'b11; + // else + // rd_rst <= {rd_rst[0],1'b0}; + //end + + + if (BYPASS_RESET_SYNC) begin + assign wr_rst_int = a_wr_rst_i; + assign rd_rst_int = a_rd_rst_i; + assign rst_busy = 1'b0; + end + else begin + `IP_MODULE_NAME(efx_resetsync) #( + .ACTIVE_LOW (0) + ) efx_resetsync_wr_rst ( + .clk (wr_clk_int), + .reset (a_rst_i), + .d_o (wr_rst_int) + ); + + `IP_MODULE_NAME(efx_resetsync) #( + .ACTIVE_LOW (0) + ) efx_resetsync_rd_rst ( + .clk (rd_clk_int), + .reset (a_rst_i), + .d_o (rd_rst_int) + ); + assign rst_busy = wr_rst_int | rd_rst_int; + end + + end + else begin + //(* async_reg = "true" *) reg [1:0] a_rst; + // + //always @ (posedge clk_i or posedge a_rst_i) begin + // if (a_rst_i) + // a_rst <= 2'b11; + // else + // a_rst <= {a_rst[0],1'b0}; + //end + wire a_rst; + + `IP_MODULE_NAME(efx_resetsync) #( + .ACTIVE_LOW (0) + ) efx_resetsync_a_rst ( + .clk (clk_i), + .reset (a_rst_i), + .d_o (a_rst) + ); + + if (BYPASS_RESET_SYNC) begin + assign wr_rst_int = a_rst_i; + assign rd_rst_int = a_rst_i; + assign rst_busy = 1'b0; + end + else begin + assign wr_rst_int = a_rst; + assign rd_rst_int = a_rst; + assign rst_busy = wr_rst_int | rd_rst_int; + end + end +endgenerate + +`IP_MODULE_NAME(efx_fifo_ram) # ( + .FAMILY (FAMILY), + .WR_DEPTH (WR_DEPTH), + .RD_DEPTH (RD_DEPTH), + .WDATA_WIDTH (WDATA_WIDTH), + .RDATA_WIDTH (RDATA_WIDTH), + .WADDR_WIDTH (WADDR_WIDTH), + .RADDR_WIDTH (RADDR_WIDTH), + .OUTPUT_REG (OUTPUT_REG), + .RAM_MUX_RATIO (RAM_MUX_RATIO), + .ENDIANESS (ENDIANESS), + .RAM_STYLE (RAM_STYLE) +) xefx_fifo_ram ( + .wdata (wdata), + .waddr (waddr), + .raddr (raddr), + .we (wr_en_int), + .re (rd_en_int), + .wclk (wr_clk_int), + .rclk (rd_clk_int), + .rdata (rdata) +); + +`IP_MODULE_NAME(efx_fifo_ctl) # ( + .SYNC_CLK (SYNC_CLK), + .SYNC_STAGE (SYNC_STAGE), + .MODE (MODE), + .WR_DEPTH (WR_DEPTH), + .WADDR_WIDTH (WADDR_WIDTH), + .RADDR_WIDTH (RADDR_WIDTH), + .ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), + .RAM_MUX_RATIO (RAM_MUX_RATIO), + .PIPELINE_REG (PIPELINE_REG), + .ALMOST_FLAG (ALMOST_FLAG), + .PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), + .PROG_FULL_ASSERT (PROG_FULL_ASSERT), + .PROG_FULL_NEGATE (PROG_FULL_NEGATE), + .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), + .PROG_EMPTY_ASSERT (PROG_EMPTY_ASSERT), + .PROG_EMPTY_NEGATE (PROG_EMPTY_NEGATE), + .OUTPUT_REG (OUTPUT_REG), + .HANDSHAKE_FLAG (HANDSHAKE_FLAG), + .OVERFLOW_PROTECT (OVERFLOW_PROTECT), + .UNDERFLOW_PROTECT (UNDERFLOW_PROTECT) +) xefx_fifo_ctl ( + .wr_rst (wr_rst_int), + .rd_rst (rd_rst_int), + .wclk (wr_clk_int), + .rclk (rd_clk_int), + .we (wr_en_i), + .re (rd_en_i), + .wr_full (full_o), + .wr_ack (wr_ack_o), + .rd_empty (empty_o), + .wr_almost_full (almost_full_o), + .rd_almost_empty (almost_empty_o), + .wr_prog_full (prog_full_o), + .rd_prog_empty (prog_empty_o), + .wr_en_int (wr_en_int), + .rd_en_int (rd_en_int), + .waddr (waddr), + .raddr (raddr), + .wr_datacount (wr_datacount_int), + .rd_datacount (rd_datacount_int), + .rd_vld (rd_valid_o), + .wr_overflow (overflow_o), + .rd_underflow (underflow_o) +); + +function integer depth2width; +input [31:0] depth; +begin : fnDepth2Width + if (depth > 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian + parameter RAM_STYLE = "block_ram" +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + always @ (posedge wclk) begin + for (i=0; i 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_resetsync) #( + parameter ASYNC_STAGE = 2, + parameter ACTIVE_LOW = 1 +) ( + input wire clk, + input wire reset, + output wire d_o +); + + +generate + if (ACTIVE_LOW == 1) begin: active_low + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (1), + .RST_VALUE (0) + ) efx_resetsync_active_low ( + .clk (clk), + .reset_n (reset), + .d_i (1'b1), + .d_o (d_o) + ); + end + else begin: active_high + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (0), + .RST_VALUE (1) + ) efx_resetsync_active_high ( + .clk (clk), + .reset_n (reset), + .d_i (1'b0), + .d_o (d_o) + ); + end +endgenerate + +endmodule + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_asyncreg) #( + parameter ASYNC_STAGE = 2, + parameter WIDTH = 4, + parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset + parameter RST_VALUE = 0, + parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance +) ( + input wire clk, + input wire reset_n, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + + + + + + + + + + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect author = "author-a" , author_info = "author-a-details" +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V +o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE +El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY +kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc +/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 +uYJaS5tuGEuFInBHa7oO8g== +`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 +fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa +rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq +PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL +DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w +K3OoKmk3zFeArSsql8B4/Q== +`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 ) +`pragma protect key_block +RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M +GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l +6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI= +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf +RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk +1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw +Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz +eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0 +2HflB1HYKxojQCcZU7qUgQ== +`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx +Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB +rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr +XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD +e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod +B2Zpo2FQ//YDRSAaEa9ksQ== +`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze +vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 +ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 +06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP +fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN +ZoPzFCMjGk5ZmMyIlytNCw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 ) +`pragma protect data_block +0d33xo/2RnBYy8BD6jq1J42m9u/75PA0owNvxlnr0TDOq7sF8XT6xouctVD1XQW2 +Ylwj0urY+dCJZku0aGRpcvb3H/nTlKVdEZOEl4QqB1gNGz/3mz75A3eudu5zgHEr +MaagjyQfDnoIqLWi1r5uTZrlS298IvNcGAJ+xXzpmkFmfG4Tk/5Jf2GPAPVtjREI +01kt8Go4CL1WNxBKcwm0xCiCchxvZ2oEtpERiC+7LUalgTJapIVoLFpvFv98229k +egvgF1KHNj0rAKedSG2Xo58TyA4iZXJJDdtgCxiKgu3Rimjno7l+ekApwmvx8n+p +yHkRGqetWfRhyE4A5q03RzOeSdA6NbCqijB3NPw/p58brAbA35rrjYpGIZXtZ4mU +De3As8VtD64nS2PRuf4/a2lIcDbwMjNTfMpN7iJfVBJ0/48tLHdetx592TLXenkF +GvAZ2yxoyBYzKctj4Keo+19Xp1UjVd3fr2MR3A7nmxLRKDA+upDxQ7ql8+pR7Moh +0b53/4Ri3Mkl+7EC1KXJNt2VbkZmcT7OAFIoPpibmcXS2R6DNVrhSKzfc2+TRM9r +mwRrJy9/R5RR+WGfw1S57Ho3wBPf4belj+Tfd7yhnwOVRXkTMq5M1BiigrGeeQ3q +z/hc1Kg8b/R+g7lnU0pqASnExPQW/DIMfH1RX75U68CAgaBAH22Vcbkoibp8sxyO +g18LefEh48UffnbpCKyv7SQ3LAdj+YO+KvvXHj1eW+CH7GA2lC5vt2be5Ah2/13H +bCeZ+srG6r7wmafy9MNNh8AgjUfZWwMnuJdCIcHTOfAncCd2B0T1Oza4VIkvnSl5 +60V34JXkfrGsNuHxwCF/sRSBbZUSpqig4ZGYHjOHldx2OANZQeUvLES3fwScYY5D +7SpR4ofVxIB/ev/+RXzvC3MNk1N0GT4F1XwokeeQIr/ilRETe/pFvEKttvviZ7uJ +uEVblS2v61DMXEgDavkbA0WdhMChPulwDvZtisWT4hCKRxfuBvNBtz0wH/WgRoX3 +aipWvPJG3G0xvO0u0EQVNdcxE+LZ7vyGF5HWEwKdQYDyhH+yVDeG+M/b08dU2aq4 +sG7dyygyVnzVbk2Lf0nCkGqKkUZUr05Zim0Wcflkhkqy348SOZ3xmEGuYAkzelLV +feQ+0ScsscFL5Cq4ETfFrN8GO8M5kkBN2ELs1MQecPRsgMCh0hcvd8IQrJTybQPW +aqwp9mgnFvS8AJ1ct+XgrAt8zgVnhaZGS9TKa6OWbr0U+SD5m+/pXjNsZA2dni6b +85/PmQeWeAarE/+EaJn/hlP6y3x3R3ItU8Itf6SB50LZ17LAhIRSIYsa7LBBNWOk +ngFHcGBCJnqTJv3hdVqa9cYipZ98XCa8dqrtAM5Rkxwd6H8KxXA+B+PWEz/cQWlb +szi9u5ufmyaJp6PWhklroQkPJEorUtF96X763itgtlAMHfkZglkElUD/gPlkXLtl +yquUmHqPK5D2pJDq0Q0jromE2yrr9fl3OI+eBehd2YBUivGKeaDFkPx7HbzWp9ok +9bT55H8VKYyF1awcjNND+WcXzm2WfvZHBDUJkRm7dnOQRvcX2RxlPRZSzAA3irVn +GFbHXD0RYn/dUR7Vy4kU68P5S5q4bUxD5vmUCN9vDoCivY7WCnlQCHQs3+iFblzP +A636C3dNQMSw0pjDisiZB63VczY8bivFh3cO82inNw5r2IZjvMB9XPhc4FHuIpfR +F7ptW0TUnO1MSDcZvCnjUfVSnHN22l2FM/P5oI1SbG3W+8YmxBvto8jwpES4ohOQ +YSECrvWkLklq68FVTzB7Tvg3JLdSy3TEKBuZE/ot0w/SXusFovOwd4aeiNDAmzwl +fQuCYHuJ0UKLaVNVAO4mw91PJODKCk2NYTr0ghOLovOXiMhUYtXZ+wFchXVkQKDI +B8BXjM7P+blhoOFA6AhRuCX4gZn0dP6m99qnyBJoxf1/FyfJXuklnPll93amUYUx +MzxNNTf7F08tnKQ8pTOk2mfFZnhA2MFn4XQ9FaGvtUrlJI8bvJTWiZFMF0eOJdIw +kzYOXEzKBjIdWW4rtTZmQJb7AOrznUpYdgTAPip/DQx6cg1+tZAVwhZPCjCsb5wa +em5hMtISQKDc92QrlU5O74OXe7641fzFRcKqy9AzwhZl+tmHk1uvpDkpsYiMa7Rk +YrbIjsKQV36PTqYPvxq1EiwYF8PMRf9FG8JZk85EZdM6QEGuehDHqFcZ+SlUb7/e +ji6GgjKxcZwaRREGKSOslcscHS6QNuGCF3iInqNCT4V2l7nboWOefMT2f1kmQOdE +szTFg563SQ8pu7ok3T3XNqUDi5ulvF+XGHDhcQ2hTkZ+xQ8dHFAWZdgzEGMXF2Lw +jU+ZRA2JULfjxOMIU2j9f+aGWmFx2PELMA5K5uOWYUQG2Fn04p1D6u8MEe7fIPeI +k7KH8j/Tumj+kG4t/lCrme6VM9u6A2NGddX1yH1NCejfophy3UWJg9wL/dNxzf6t +vXdm3rGPdZPWFgSIuGlmT03QZmWGPbs8qvkkUVAL37kMJP2r4L+PI00ZxbX8V5jp +GgYN1Rh+NSOwAcUEFCViRhFYC+Gi5eZ6AF6XDSU6qfjGsUKqJ9yrNx0Km6+SjpAK +7Zxblp7vweFVkJ7IESoFeB+vP8JNeoidbBPGEWo+2V08PgfGgjPEAA6pjj8uc0jC +SDFZ0sVrzvc66PZ5FxbI4g+VuXPJgyJsnQ/eHhPVTVTP3/oGMRVktNiJrkJYxAW7 +Sa/EJMjfXX+rMIWG5ssWLT6WfrojlHduEqJ9hJr24RZy514HHF8SMPRBLD6l1wd5 +07U/ChjFdy5qHn5Ce+lanjxnoxgvCsF3lMqoZ7e2bfzXakj7CxahwqRt6yeU0Q+/ +a8tvIJgHfdtOPw/r6HnSrzpdWzTx2e6/MEryHZqpMN63Lhakpjw1L7u3FD/rW40b +LGajigQ7Ql+cZmP7wYl+uSmTFIS6ZgXOc1ibb7yYxJwpeixPHL1iu5ltvriRiTZ6 +DMbbOjNpPuL7ie3AwgmwXwnpnTL6k/Rj2+ma3B7ImODBMkC4SLtTc0ynCcPAFZKA +Xh78wUAgt1T5Nm4XR555DBO7zPHX9rZzMLil4/j0RMDwn1gitmP2PSNFWsrXJG8p +C46kfpdqoM3Yf6HySlhsith6GW41sMF6imUXwahQQRw240HLW3N876LDe6bjTmgN +eIC7y/4NZk7OmpmP8udAEH+UsNfSGtKA8959AoJDr43XsWkOfccNWstu4sTXA5+w +pCALypmBMdholEsrW9DgsIgbgf2pcOAC9+mAjld+yyQ+UNdKRbmtRDHTztGmcVvw +Szip4YUuTM1tPzReucfm38gVFT7eo1qFQg/FJ4VgeYab7ku5OHuwZQmKyzng/t0U +A1lquVENVYQEIotBiOC7jQ1YTkTasGN4xoFgFTyKLFPyk8bl2/anzr1Fx0ieVGCx +2ipzG2JzIQf/FlHXaYrgkWiF817amty+KZp4/dCJtvDXxzOZKnBTVcjHXpqR1Ik+ +tdV+k+21tXZxP0rkG0yi4//2c5UiWGb0UegpemqutykLuT9tGjsqMuc5DaDH/8zk +wLTVfODT+HqN1/ZLqfq9VoAF5m/ujnPNt3wZcsjsAyBD153rW4Q2yVYMat0sFQN6 +XbNAeNBJZlO/aE1PfKBcSDFkJkPqRxlgdiE5B83/w1MP6Z4qwz7LJ8yTYM22xwRo +LIYpKq52yYMhJm42YeQxbBRTx0MyubCb+ompEVBF28Eh0vE98UAZj7t1szSweg99 +Wq6/4kxR2SQj8rFo2wrZe7ngsDmbIrMk2SinS6WmV4Mj+MBbPlmiuwB6NUV04Id1 +9enBBsJIfWt+PZJXyWkOoG/fOVBUxCY+CMCiab0qQ1EVdhggrdI30BgFqcLjfyD6 +/h5AqIzMGWrhWnap8WDEh1Ah6K9f2oCESSXO751sV5eK8jgl63FJMIVsnjVejxrl +Qa7PCXP3BO6Cnv896NBzAsddPq/AYBLHIC6eX3sTtOxTx52NsmJzoyUSJcAoA/QS +leHU1bLA2z+HGfMrkSzsuvXafmqr3B+PHfWdxrYzTxmVhMBPX/FvEU/gfxXGa6kj +niZYGue/Rk+zXL65ENgPwxiz0mm7QyQ6eMBMRovm6MGyIl/8obkOPygH+lhc+bgR +SNWLmxqjR2YABrKsUgCITQ6GK7VmVR3wOOwbZs+YW/0Yj2yzg7ESjaeqI40/OQFD +Ft2IHaURJPk6jl5vRrcCc0J0GCy7CK0BU14n+Nxfl2+CFRe4efoqZry/CmY2+S4M +p9OqgjUzHGSIbNRAXHf44nIAUjWYvijzzLSj9A7WY3TpYxgtqU8Wbf7SbWmw8RJV +pAYDHGmwHa8fL4Y9xEFF/WqmqWSL3g146i41MKWKY7lchvnWtc6yOgk+0geVFOpe +9BLs4TehFA/SueFC99S0Cxcxc0KMWXOKm0I3bI1CAlLje7wUcdI/pki33iqBLJlL +T2vz8ptPqfgAxDW0ZEvEYY/jfB+jCO0MKT7XK/LZNYSuEke3Y3CeuwZ/5IWkDcwy +7BArmDy7Hpw88le9ODL94mS1fUB8jsBaazeiXniZPNZjBkugt/ZAf4XYuoaGVPAM +DnRd8GW5eiDHFCEB42lpg9n7Ak8cXsSSlODCHeay2VtcQP1DEgwWdI5XdXE879gI +8lLU9bH2MfsxI2mNWCMv5immaioZJDorIVzyMGvIn3OcgqmhTU1owINUJf+Hm8Q7 +JfJq4m6t0J5eoKQH57uSGFkWRZ3dtp5QL3d5bBOMmorXUBzdrLt8wurvNke29bHD +UQdmANjayV8drYWAccZdPWyi9jNC/K31BTDI6RCpZdV3Wr5scOZdXWrl961jirm1 +g/2MGKxriuH2F4MRIh2vp3uS8PLbj4cHJv+5+LtLgs0lpdEMYAvJKDACRg68tDhY +XsF9lhHpcF5+tANOawRtnSvy/rlLn+A3wi7v8tnTZcLkocJ51c+nK5/Ij0YgUrA0 +eLrKNlJM78stswPWkvpBlAJ+G3D4Cw6P3XcJWrLyV3u79jf9PRJZmxMU/COGTmgQ +PJdXp90O3u2Pjdwhp4VdtBK2d/jTpk59j8xbQBavf5flZ+PzoLpd8NSt6GdPVJ5r +uVWvNy14pJXUsn+Tgxj+9Wp3vm5mofWtJAkEgr/Rfp7AVLLShJSd6vsbT7F2+TS/ +OMDv0XH92v1G4tqJ0rbxS1TnxX61+1sfjKlfIQdFR9gxLy71Tb705LQHBAw8vmSx +X6Uv+HbtPaEqRCF+pdvGsLNI2Seo6INA/mXqNpd6VPhfQHtp3bgV+Hxnlcc9lCiI +bCZq6KG4a6sVQHIZ3pZo7PQtoAo22niHvgZFoOVnBv+bu+blmvSV6gxCPoV8rwOe +/WD7YikHE7WVSq1SHtTIcbPv+K+1NKqZIiSCS2qDfJLgI7vH4zjIqibDhzGZTeKV +Km234SSlJ1OL4WQ5FtsxjednjUIAKqVe1auDiTzAKY28dwUkwGN/XXQ+EjrmxQuL +qIAT3WP49EeM+CQCp3D6Vxzm7Picq+RtwtbAXnnSQtvPcaSprODI089a0iR46Pp/ +4DLMUOLS+01HozXF1589YdqYep05No/Fp4eP2RdQxicYxK8d/OcvG7E8F1URVmAa +XdZxVa9caM3xYMWDZaiaOo6IZ+YM5VeZ4KxUblS1L1IlOnGOOZ3AiaLsHOh55ryc +Ei7EaFpheCmlTJyxUg8TdA== +`pragma protect end_protected + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ctl) # ( + parameter SYNC_CLK = 1, + parameter SYNC_STAGE = 2, + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter ASYM_WIDTH_RATIO = 4, + parameter RAM_MUX_RATIO = 1, + parameter PIPELINE_REG = 1, + parameter ALMOST_FLAG = 1, + parameter PROGRAMMABLE_FULL = "NONE", + parameter PROG_FULL_ASSERT = 0, + parameter PROG_FULL_NEGATE = 0, + parameter PROGRAMMABLE_EMPTY = "NONE", + parameter PROG_EMPTY_ASSERT = 0, + parameter PROG_EMPTY_NEGATE = 0, + parameter OUTPUT_REG = 0, + parameter HANDSHAKE_FLAG = 1, + parameter OVERFLOW_PROTECT = 0, + parameter UNDERFLOW_PROTECT = 0 +)( + input wire wr_rst, + input wire rd_rst, + input wire wclk, + input wire rclk, + input wire we, + input wire re, + output wire wr_full, + output reg wr_ack, + output wire wr_almost_full, + output wire rd_empty, + output wire rd_almost_empty, + output wire wr_prog_full, + output wire rd_prog_empty, + output wire wr_en_int, + output wire rd_en_int, + output wire [WADDR_WIDTH-1:0] waddr, + output wire [RADDR_WIDTH-1:0] raddr, + output wire [WADDR_WIDTH:0] wr_datacount, + output wire [RADDR_WIDTH:0] rd_datacount, + output wire rd_vld, + output reg wr_overflow, + output reg rd_underflow +); + +reg [WADDR_WIDTH:0] waddr_cntr; +reg [WADDR_WIDTH:0] waddr_cntr_r; +reg [RADDR_WIDTH:0] raddr_cntr; +reg rd_valid; + +wire [WADDR_WIDTH:0] waddr_int; +wire [RADDR_WIDTH:0] raddr_int; +wire rd_empty_int; +wire [WADDR_WIDTH:0] wr_datacount_int; +wire [RADDR_WIDTH:0] rd_datacount_int; + +assign waddr = waddr_cntr[WADDR_WIDTH-1:0]; +// NIC +wire [RADDR_WIDTH:0] ram_raddr; +assign raddr = (MODE == "FWFT") ? ram_raddr[RADDR_WIDTH-1:0] : raddr_cntr[RADDR_WIDTH-1:0]; +//assign raddr = raddr_cntr[RADDR_WIDTH-1:0]; +//assign wr_en_int = we & ~wr_full; +assign wr_en_int = OVERFLOW_PROTECT ? we & ~wr_full : we; + +assign wr_datacount = wr_datacount_int; +assign rd_datacount = ASYM_WIDTH_RATIO == 4 && SYNC_CLK ? wr_datacount_int : rd_datacount_int; + + +generate + if (MODE == "FWFT") begin + // NIC + //assign rd_en_int = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int); + //assign rd_empty = rd_empty_fwft; + + assign rd_en_int = 1'b1; + //assign rd_empty = rd_empty_int; + + //always @ (posedge rclk or posedge rd_rst) begin + // if (rd_rst) begin + // init_set <= 1'b1; + // end + // else if (~init_set & rd_empty) begin + // init_set <= 1'b1; + // end + // else if (~rd_empty_int) begin + // init_set <= 1'b0; + // end + // else if (rd_empty) begin + // init_set <= 1'b1; + // end + //end + // NIC + //always @ (posedge rclk or posedge rd_rst) begin + // if (rd_rst) begin + // rd_empty_fwft <= 1'b1; + // end + // else if (rd_en_int) begin + // rd_empty_fwft <= 1'b0; + // end + // else if (re) begin + // rd_empty_fwft <= 1'b1; + // end + //end + + //if (FAMILY == "TRION") begin + if (OUTPUT_REG) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid <= 1'b0; + end + else begin + rd_valid <= ~rd_empty; + end + end + assign rd_vld = rd_valid; + end + else begin + assign rd_vld = ~rd_empty; + end + + assign rd_empty = rd_empty_int; + end + else begin + assign rd_en_int = UNDERFLOW_PROTECT ? re & ~rd_empty_int : re; + assign rd_empty = rd_empty_int; + + if (OUTPUT_REG) begin + reg rd_valid_r; + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid_r <= 'h0; + rd_valid <= 'h0; + end + else begin + {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int}; + end + end + assign rd_vld = rd_valid; + end + else begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid <= 'h0; + end + else begin + rd_valid <= rd_en_int; + end + end + assign rd_vld = rd_valid; + end + end + + if (ALMOST_FLAG) begin + assign wr_almost_full = wr_datacount >= WR_DEPTH-1; + assign rd_almost_empty = rd_datacount <= 'd1; + end + else begin + assign wr_almost_full = 1'b0; + assign rd_almost_empty = 1'b0; + end + + if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + // NIC + //wr_ack <= wr_en_int & ~wr_overflow; + wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; + end + end + end + + if (OVERFLOW_PROTECT) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else begin + wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; + end + end + end + + if (UNDERFLOW_PROTECT) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else begin + rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + // NIC + else if (ASYM_WIDTH_RATIO == 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - raddr_int; + assign rd_datacount_int = waddr_int - raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + // NIC + //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_r <= 'h0; + end + else begin + waddr_cntr_r <= waddr_cntr; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + end + // NIC + //else if (rd_en_int) begin + else begin + //raddr_cntr <= raddr_cntr + 1'b1; + //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); + raddr_cntr <= ram_raddr; + end +end +// NIC +assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); + + +generate + if (SYNC_CLK) begin : sync_clk + if (MODE == "FWFT") begin + assign waddr_int = waddr_cntr_r; + assign raddr_int = raddr_cntr; + end + else begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr; + end + end + else begin : async_clk + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian + parameter RAM_STYLE = "block_ram" +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + always @ (posedge wclk) begin + for (i=0; i 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_resetsync) #( + parameter ASYNC_STAGE = 2, + parameter ACTIVE_LOW = 1 +) ( + input wire clk, + input wire reset, + output wire d_o +); + + +generate + if (ACTIVE_LOW == 1) begin: active_low + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (1), + .RST_VALUE (0) + ) efx_resetsync_active_low ( + .clk (clk), + .reset_n (reset), + .d_i (1'b1), + .d_o (d_o) + ); + end + else begin: active_high + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (0), + .RST_VALUE (1) + ) efx_resetsync_active_high ( + .clk (clk), + .reset_n (reset), + .d_i (1'b0), + .d_o (d_o) + ); + end +endgenerate + +endmodule + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_asyncreg) #( + parameter ASYNC_STAGE = 2, + parameter WIDTH = 4, + parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset + parameter RST_VALUE = 0, + parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance +) ( + input wire clk, + input wire reset_n, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + + + + + + + + + + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect author = "author-a" , author_info = "author-a-details" +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V +o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE +El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY +kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc +/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 +uYJaS5tuGEuFInBHa7oO8g== +`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 +fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa +rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq +PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL +DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w +K3OoKmk3zFeArSsql8B4/Q== +`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 ) +`pragma protect key_block +RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M +GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l +6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI= +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf +RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk +1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw +Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz +eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0 +2HflB1HYKxojQCcZU7qUgQ== +`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx +Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB +rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr +XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD +e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod +B2Zpo2FQ//YDRSAaEa9ksQ== +`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze +vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 +ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 +06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP +fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN +ZoPzFCMjGk5ZmMyIlytNCw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 ) +`pragma protect data_block +0d33xo/2RnBYy8BD6jq1J42m9u/75PA0owNvxlnr0TDOq7sF8XT6xouctVD1XQW2 +Ylwj0urY+dCJZku0aGRpcvb3H/nTlKVdEZOEl4QqB1gNGz/3mz75A3eudu5zgHEr +MaagjyQfDnoIqLWi1r5uTZrlS298IvNcGAJ+xXzpmkFmfG4Tk/5Jf2GPAPVtjREI +01kt8Go4CL1WNxBKcwm0xCiCchxvZ2oEtpERiC+7LUalgTJapIVoLFpvFv98229k +egvgF1KHNj0rAKedSG2Xo58TyA4iZXJJDdtgCxiKgu3Rimjno7l+ekApwmvx8n+p +yHkRGqetWfRhyE4A5q03RzOeSdA6NbCqijB3NPw/p58brAbA35rrjYpGIZXtZ4mU +De3As8VtD64nS2PRuf4/a2lIcDbwMjNTfMpN7iJfVBJ0/48tLHdetx592TLXenkF +GvAZ2yxoyBYzKctj4Keo+19Xp1UjVd3fr2MR3A7nmxLRKDA+upDxQ7ql8+pR7Moh +0b53/4Ri3Mkl+7EC1KXJNt2VbkZmcT7OAFIoPpibmcXS2R6DNVrhSKzfc2+TRM9r +mwRrJy9/R5RR+WGfw1S57Ho3wBPf4belj+Tfd7yhnwOVRXkTMq5M1BiigrGeeQ3q +z/hc1Kg8b/R+g7lnU0pqASnExPQW/DIMfH1RX75U68CAgaBAH22Vcbkoibp8sxyO +g18LefEh48UffnbpCKyv7SQ3LAdj+YO+KvvXHj1eW+CH7GA2lC5vt2be5Ah2/13H +bCeZ+srG6r7wmafy9MNNh8AgjUfZWwMnuJdCIcHTOfAncCd2B0T1Oza4VIkvnSl5 +60V34JXkfrGsNuHxwCF/sRSBbZUSpqig4ZGYHjOHldx2OANZQeUvLES3fwScYY5D +7SpR4ofVxIB/ev/+RXzvC3MNk1N0GT4F1XwokeeQIr/ilRETe/pFvEKttvviZ7uJ +uEVblS2v61DMXEgDavkbA0WdhMChPulwDvZtisWT4hCKRxfuBvNBtz0wH/WgRoX3 +aipWvPJG3G0xvO0u0EQVNdcxE+LZ7vyGF5HWEwKdQYDyhH+yVDeG+M/b08dU2aq4 +sG7dyygyVnzVbk2Lf0nCkGqKkUZUr05Zim0Wcflkhkqy348SOZ3xmEGuYAkzelLV +feQ+0ScsscFL5Cq4ETfFrN8GO8M5kkBN2ELs1MQecPRsgMCh0hcvd8IQrJTybQPW +aqwp9mgnFvS8AJ1ct+XgrAt8zgVnhaZGS9TKa6OWbr0U+SD5m+/pXjNsZA2dni6b +85/PmQeWeAarE/+EaJn/hlP6y3x3R3ItU8Itf6SB50LZ17LAhIRSIYsa7LBBNWOk +ngFHcGBCJnqTJv3hdVqa9cYipZ98XCa8dqrtAM5Rkxwd6H8KxXA+B+PWEz/cQWlb +szi9u5ufmyaJp6PWhklroQkPJEorUtF96X763itgtlAMHfkZglkElUD/gPlkXLtl +yquUmHqPK5D2pJDq0Q0jromE2yrr9fl3OI+eBehd2YBUivGKeaDFkPx7HbzWp9ok +9bT55H8VKYyF1awcjNND+WcXzm2WfvZHBDUJkRm7dnOQRvcX2RxlPRZSzAA3irVn +GFbHXD0RYn/dUR7Vy4kU68P5S5q4bUxD5vmUCN9vDoCivY7WCnlQCHQs3+iFblzP +A636C3dNQMSw0pjDisiZB63VczY8bivFh3cO82inNw5r2IZjvMB9XPhc4FHuIpfR +F7ptW0TUnO1MSDcZvCnjUfVSnHN22l2FM/P5oI1SbG3W+8YmxBvto8jwpES4ohOQ +YSECrvWkLklq68FVTzB7Tvg3JLdSy3TEKBuZE/ot0w/SXusFovOwd4aeiNDAmzwl +fQuCYHuJ0UKLaVNVAO4mw91PJODKCk2NYTr0ghOLovOXiMhUYtXZ+wFchXVkQKDI +B8BXjM7P+blhoOFA6AhRuCX4gZn0dP6m99qnyBJoxf1/FyfJXuklnPll93amUYUx +MzxNNTf7F08tnKQ8pTOk2mfFZnhA2MFn4XQ9FaGvtUrlJI8bvJTWiZFMF0eOJdIw +kzYOXEzKBjIdWW4rtTZmQJb7AOrznUpYdgTAPip/DQx6cg1+tZAVwhZPCjCsb5wa +em5hMtISQKDc92QrlU5O74OXe7641fzFRcKqy9AzwhZl+tmHk1uvpDkpsYiMa7Rk +YrbIjsKQV36PTqYPvxq1EiwYF8PMRf9FG8JZk85EZdM6QEGuehDHqFcZ+SlUb7/e +ji6GgjKxcZwaRREGKSOslcscHS6QNuGCF3iInqNCT4V2l7nboWOefMT2f1kmQOdE +szTFg563SQ8pu7ok3T3XNqUDi5ulvF+XGHDhcQ2hTkZ+xQ8dHFAWZdgzEGMXF2Lw +jU+ZRA2JULfjxOMIU2j9f+aGWmFx2PELMA5K5uOWYUQG2Fn04p1D6u8MEe7fIPeI +k7KH8j/Tumj+kG4t/lCrme6VM9u6A2NGddX1yH1NCejfophy3UWJg9wL/dNxzf6t +vXdm3rGPdZPWFgSIuGlmT03QZmWGPbs8qvkkUVAL37kMJP2r4L+PI00ZxbX8V5jp +GgYN1Rh+NSOwAcUEFCViRhFYC+Gi5eZ6AF6XDSU6qfjGsUKqJ9yrNx0Km6+SjpAK +7Zxblp7vweFVkJ7IESoFeB+vP8JNeoidbBPGEWo+2V08PgfGgjPEAA6pjj8uc0jC +SDFZ0sVrzvc66PZ5FxbI4g+VuXPJgyJsnQ/eHhPVTVTP3/oGMRVktNiJrkJYxAW7 +Sa/EJMjfXX+rMIWG5ssWLT6WfrojlHduEqJ9hJr24RZy514HHF8SMPRBLD6l1wd5 +07U/ChjFdy5qHn5Ce+lanjxnoxgvCsF3lMqoZ7e2bfzXakj7CxahwqRt6yeU0Q+/ +a8tvIJgHfdtOPw/r6HnSrzpdWzTx2e6/MEryHZqpMN63Lhakpjw1L7u3FD/rW40b +LGajigQ7Ql+cZmP7wYl+uSmTFIS6ZgXOc1ibb7yYxJwpeixPHL1iu5ltvriRiTZ6 +DMbbOjNpPuL7ie3AwgmwXwnpnTL6k/Rj2+ma3B7ImODBMkC4SLtTc0ynCcPAFZKA +Xh78wUAgt1T5Nm4XR555DBO7zPHX9rZzMLil4/j0RMDwn1gitmP2PSNFWsrXJG8p +C46kfpdqoM3Yf6HySlhsith6GW41sMF6imUXwahQQRw240HLW3N876LDe6bjTmgN +eIC7y/4NZk7OmpmP8udAEH+UsNfSGtKA8959AoJDr43XsWkOfccNWstu4sTXA5+w +pCALypmBMdholEsrW9DgsIgbgf2pcOAC9+mAjld+yyQ+UNdKRbmtRDHTztGmcVvw +Szip4YUuTM1tPzReucfm38gVFT7eo1qFQg/FJ4VgeYab7ku5OHuwZQmKyzng/t0U +A1lquVENVYQEIotBiOC7jQ1YTkTasGN4xoFgFTyKLFPyk8bl2/anzr1Fx0ieVGCx +2ipzG2JzIQf/FlHXaYrgkWiF817amty+KZp4/dCJtvDXxzOZKnBTVcjHXpqR1Ik+ +tdV+k+21tXZxP0rkG0yi4//2c5UiWGb0UegpemqutykLuT9tGjsqMuc5DaDH/8zk +wLTVfODT+HqN1/ZLqfq9VoAF5m/ujnPNt3wZcsjsAyBD153rW4Q2yVYMat0sFQN6 +XbNAeNBJZlO/aE1PfKBcSDFkJkPqRxlgdiE5B83/w1MP6Z4qwz7LJ8yTYM22xwRo +LIYpKq52yYMhJm42YeQxbBRTx0MyubCb+ompEVBF28Eh0vE98UAZj7t1szSweg99 +Wq6/4kxR2SQj8rFo2wrZe7ngsDmbIrMk2SinS6WmV4Mj+MBbPlmiuwB6NUV04Id1 +9enBBsJIfWt+PZJXyWkOoG/fOVBUxCY+CMCiab0qQ1EVdhggrdI30BgFqcLjfyD6 +/h5AqIzMGWrhWnap8WDEh1Ah6K9f2oCESSXO751sV5eK8jgl63FJMIVsnjVejxrl +Qa7PCXP3BO6Cnv896NBzAsddPq/AYBLHIC6eX3sTtOxTx52NsmJzoyUSJcAoA/QS +leHU1bLA2z+HGfMrkSzsuvXafmqr3B+PHfWdxrYzTxmVhMBPX/FvEU/gfxXGa6kj +niZYGue/Rk+zXL65ENgPwxiz0mm7QyQ6eMBMRovm6MGyIl/8obkOPygH+lhc+bgR +SNWLmxqjR2YABrKsUgCITQ6GK7VmVR3wOOwbZs+YW/0Yj2yzg7ESjaeqI40/OQFD +Ft2IHaURJPk6jl5vRrcCc0J0GCy7CK0BU14n+Nxfl2+CFRe4efoqZry/CmY2+S4M +p9OqgjUzHGSIbNRAXHf44nIAUjWYvijzzLSj9A7WY3TpYxgtqU8Wbf7SbWmw8RJV +pAYDHGmwHa8fL4Y9xEFF/WqmqWSL3g146i41MKWKY7lchvnWtc6yOgk+0geVFOpe +9BLs4TehFA/SueFC99S0Cxcxc0KMWXOKm0I3bI1CAlLje7wUcdI/pki33iqBLJlL +T2vz8ptPqfgAxDW0ZEvEYY/jfB+jCO0MKT7XK/LZNYSuEke3Y3CeuwZ/5IWkDcwy +7BArmDy7Hpw88le9ODL94mS1fUB8jsBaazeiXniZPNZjBkugt/ZAf4XYuoaGVPAM +DnRd8GW5eiDHFCEB42lpg9n7Ak8cXsSSlODCHeay2VtcQP1DEgwWdI5XdXE879gI +8lLU9bH2MfsxI2mNWCMv5immaioZJDorIVzyMGvIn3OcgqmhTU1owINUJf+Hm8Q7 +JfJq4m6t0J5eoKQH57uSGFkWRZ3dtp5QL3d5bBOMmorXUBzdrLt8wurvNke29bHD +UQdmANjayV8drYWAccZdPWyi9jNC/K31BTDI6RCpZdV3Wr5scOZdXWrl961jirm1 +g/2MGKxriuH2F4MRIh2vp3uS8PLbj4cHJv+5+LtLgs0lpdEMYAvJKDACRg68tDhY +XsF9lhHpcF5+tANOawRtnSvy/rlLn+A3wi7v8tnTZcLkocJ51c+nK5/Ij0YgUrA0 +eLrKNlJM78stswPWkvpBlAJ+G3D4Cw6P3XcJWrLyV3u79jf9PRJZmxMU/COGTmgQ +PJdXp90O3u2Pjdwhp4VdtBK2d/jTpk59j8xbQBavf5flZ+PzoLpd8NSt6GdPVJ5r +uVWvNy14pJXUsn+Tgxj+9Wp3vm5mofWtJAkEgr/Rfp7AVLLShJSd6vsbT7F2+TS/ +OMDv0XH92v1G4tqJ0rbxS1TnxX61+1sfjKlfIQdFR9gxLy71Tb705LQHBAw8vmSx +X6Uv+HbtPaEqRCF+pdvGsLNI2Seo6INA/mXqNpd6VPhfQHtp3bgV+Hxnlcc9lCiI +bCZq6KG4a6sVQHIZ3pZo7PQtoAo22niHvgZFoOVnBv+bu+blmvSV6gxCPoV8rwOe +/WD7YikHE7WVSq1SHtTIcbPv+K+1NKqZIiSCS2qDfJLgI7vH4zjIqibDhzGZTeKV +Km234SSlJ1OL4WQ5FtsxjednjUIAKqVe1auDiTzAKY28dwUkwGN/XXQ+EjrmxQuL +qIAT3WP49EeM+CQCp3D6Vxzm7Picq+RtwtbAXnnSQtvPcaSprODI089a0iR46Pp/ +4DLMUOLS+01HozXF1589YdqYep05No/Fp4eP2RdQxicYxK8d/OcvG7E8F1URVmAa +XdZxVa9caM3xYMWDZaiaOo6IZ+YM5VeZ4KxUblS1L1IlOnGOOZ3AiaLsHOh55ryc +Ei7EaFpheCmlTJyxUg8TdA== +`pragma protect end_protected + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ctl) # ( + parameter SYNC_CLK = 1, + parameter SYNC_STAGE = 2, + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter ASYM_WIDTH_RATIO = 4, + parameter RAM_MUX_RATIO = 1, + parameter PIPELINE_REG = 1, + parameter ALMOST_FLAG = 1, + parameter PROGRAMMABLE_FULL = "NONE", + parameter PROG_FULL_ASSERT = 0, + parameter PROG_FULL_NEGATE = 0, + parameter PROGRAMMABLE_EMPTY = "NONE", + parameter PROG_EMPTY_ASSERT = 0, + parameter PROG_EMPTY_NEGATE = 0, + parameter OUTPUT_REG = 0, + parameter HANDSHAKE_FLAG = 1, + parameter OVERFLOW_PROTECT = 0, + parameter UNDERFLOW_PROTECT = 0 +)( + input wire wr_rst, + input wire rd_rst, + input wire wclk, + input wire rclk, + input wire we, + input wire re, + output wire wr_full, + output reg wr_ack, + output wire wr_almost_full, + output wire rd_empty, + output wire rd_almost_empty, + output wire wr_prog_full, + output wire rd_prog_empty, + output wire wr_en_int, + output wire rd_en_int, + output wire [WADDR_WIDTH-1:0] waddr, + output wire [RADDR_WIDTH-1:0] raddr, + output wire [WADDR_WIDTH:0] wr_datacount, + output wire [RADDR_WIDTH:0] rd_datacount, + output wire rd_vld, + output reg wr_overflow, + output reg rd_underflow +); + +reg [WADDR_WIDTH:0] waddr_cntr; +reg [WADDR_WIDTH:0] waddr_cntr_r; +reg [RADDR_WIDTH:0] raddr_cntr; +reg rd_valid; + +wire [WADDR_WIDTH:0] waddr_int; +wire [RADDR_WIDTH:0] raddr_int; +wire rd_empty_int; +wire [WADDR_WIDTH:0] wr_datacount_int; +wire [RADDR_WIDTH:0] rd_datacount_int; + +assign waddr = waddr_cntr[WADDR_WIDTH-1:0]; +// NIC +wire [RADDR_WIDTH:0] ram_raddr; +assign raddr = (MODE == "FWFT") ? ram_raddr[RADDR_WIDTH-1:0] : raddr_cntr[RADDR_WIDTH-1:0]; +//assign raddr = raddr_cntr[RADDR_WIDTH-1:0]; +//assign wr_en_int = we & ~wr_full; +assign wr_en_int = OVERFLOW_PROTECT ? we & ~wr_full : we; + +assign wr_datacount = wr_datacount_int; +assign rd_datacount = ASYM_WIDTH_RATIO == 4 && SYNC_CLK ? wr_datacount_int : rd_datacount_int; + + +generate + if (MODE == "FWFT") begin + // NIC + //assign rd_en_int = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int); + //assign rd_empty = rd_empty_fwft; + + assign rd_en_int = 1'b1; + //assign rd_empty = rd_empty_int; + + //always @ (posedge rclk or posedge rd_rst) begin + // if (rd_rst) begin + // init_set <= 1'b1; + // end + // else if (~init_set & rd_empty) begin + // init_set <= 1'b1; + // end + // else if (~rd_empty_int) begin + // init_set <= 1'b0; + // end + // else if (rd_empty) begin + // init_set <= 1'b1; + // end + //end + // NIC + //always @ (posedge rclk or posedge rd_rst) begin + // if (rd_rst) begin + // rd_empty_fwft <= 1'b1; + // end + // else if (rd_en_int) begin + // rd_empty_fwft <= 1'b0; + // end + // else if (re) begin + // rd_empty_fwft <= 1'b1; + // end + //end + + //if (FAMILY == "TRION") begin + if (OUTPUT_REG) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid <= 1'b0; + end + else begin + rd_valid <= ~rd_empty; + end + end + assign rd_vld = rd_valid; + end + else begin + assign rd_vld = ~rd_empty; + end + + assign rd_empty = rd_empty_int; + end + else begin + assign rd_en_int = UNDERFLOW_PROTECT ? re & ~rd_empty_int : re; + assign rd_empty = rd_empty_int; + + if (OUTPUT_REG) begin + reg rd_valid_r; + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid_r <= 'h0; + rd_valid <= 'h0; + end + else begin + {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int}; + end + end + assign rd_vld = rd_valid; + end + else begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid <= 'h0; + end + else begin + rd_valid <= rd_en_int; + end + end + assign rd_vld = rd_valid; + end + end + + if (ALMOST_FLAG) begin + assign wr_almost_full = wr_datacount >= WR_DEPTH-1; + assign rd_almost_empty = rd_datacount <= 'd1; + end + else begin + assign wr_almost_full = 1'b0; + assign rd_almost_empty = 1'b0; + end + + if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + // NIC + //wr_ack <= wr_en_int & ~wr_overflow; + wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; + end + end + end + + if (OVERFLOW_PROTECT) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else begin + wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; + end + end + end + + if (UNDERFLOW_PROTECT) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else begin + rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + // NIC + else if (ASYM_WIDTH_RATIO == 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - raddr_int; + assign rd_datacount_int = waddr_int - raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + // NIC + //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_r <= 'h0; + end + else begin + waddr_cntr_r <= waddr_cntr; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + end + // NIC + //else if (rd_en_int) begin + else begin + //raddr_cntr <= raddr_cntr + 1'b1; + //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); + raddr_cntr <= ram_raddr; + end +end +// NIC +assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); + + +generate + if (SYNC_CLK) begin : sync_clk + if (MODE == "FWFT") begin + assign waddr_int = waddr_cntr_r; + assign raddr_int = raddr_cntr; + end + else begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr; + end + end + else begin : async_clk + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx= 2045); + +always @(posedge rx_axis_clk or negedge rx_axis_rstn) +begin + if(rx_axis_rstn == 1'b0) + rx_axis_mac_tready <= 1'b0; + else if(u1_almfull == 1'b1) + rx_axis_mac_tready <= 1'b0; + else + rx_axis_mac_tready <= 1'b1; +end + +/*----------------------- Fifo 1 Region ----------------------------*/ +DC_FIFO #( + .FIFO_MODE ("ShowAhead" ), + .DATA_WIDTH (10 ), + .FIFO_DEPTH (2048 ) +) +u1 +( + //System Signal + .Reset (!rx_axis_rstn ), + //Write Signal + .WrClk (rx_axis_clk ), + .WrEn (u1_wrreq ), + .WrDNum (u1_wrcnt ), + .WrFull ( ), + .WrData (u1_data ), + //Read Signal + .RdClk (tx_axis_clk ), + .RdEn (u1_rdreq ), + .RdDNum ( ), + .RdEmpty (u1_empty ), + .RdData (u1_q ) +); + +assign u1_data = {rx_axis_mac_tuser,rx_axis_mac_tlast,rx_axis_mac_tdata}; +assign u1_wrreq = (rx_axis_mac_tvalid == 1'b1) && (rx_axis_mac_tready == 1'b1); +assign u1_rdreq = (u1_empty == 1'b0) && ((tx_axis_mac_tvalid == 1'b0) || (tx_axis_mac_tready == 1'b1)); + +/*----------------------- Tx Clock Region ----------------------------*/ + +always @(posedge tx_axis_clk or negedge tx_axis_rstn) +begin + if(tx_axis_rstn == 1'b0) + tx_axis_mac_tvalid <= 1'b0; + else if(u1_rdreq == 1'b1) + tx_axis_mac_tvalid <= 1'b1; + else if(tx_axis_mac_tready == 1'b1) + tx_axis_mac_tvalid <= 1'b0; +end + +always @(posedge tx_axis_clk or negedge tx_axis_rstn) +begin + if(tx_axis_rstn == 1'b0) + tx_axis_mac_tdata <= 8'h0; + else if(u1_rdreq == 1'b1) + tx_axis_mac_tdata <= u1_q[7:0]; + else if(tx_axis_mac_tready == 1'b1) + tx_axis_mac_tdata <= 8'h0; +end + +always @(posedge tx_axis_clk or negedge tx_axis_rstn) +begin + if(tx_axis_rstn == 1'b0) + tx_axis_mac_tlast <= 1'b0; + else if(u1_rdreq == 1'b1) + tx_axis_mac_tlast <= u1_q[8]; + else if(tx_axis_mac_tready == 1'b1) + tx_axis_mac_tlast <= 1'b0; +end + +always @(posedge tx_axis_clk or negedge tx_axis_rstn) +begin + if(tx_axis_rstn == 1'b0) + tx_axis_mac_tuser <= 1'b0; + else if((u1_rdreq == 1'b1) && (u1_q[8] == 1'b1)) + tx_axis_mac_tuser <= u1_q[9]; + else if(tx_axis_mac_tready == 1'b1) + tx_axis_mac_tuser <= 1'b0; +end + +endmodule diff --git a/fpga/ip/gTSE/Testbench/modelsim.do b/fpga/ip/gTSE/Testbench/modelsim.do new file mode 100644 index 0000000..ccfb639 --- /dev/null +++ b/fpga/ip/gTSE/Testbench/modelsim.do @@ -0,0 +1,6 @@ +onerror {quit -f} +vlib work +vlog -sv -timescale 1ns/1ps +define+SIM+SIM_MODE+EFX_SIM -sv ./temac_ex.v ./apb3_2_axi4_lite.v ./axi4_st_mux.v ./mac_pat_gen.v ./mac_rx2tx.v ./reg_apb3.v ./udp_pat_gen.v ./tb_header.v ./tb_top.v ./ODDR.v ./glbl.v ./DaulClkFifo.v ./modelsim/gTSE.sv +vsim -t ns work.tb_top -gui -voptargs="+acc" +log -r /* +run -all diff --git a/fpga/ip/gTSE/Testbench/modelsim/gTSE.sv b/fpga/ip/gTSE/Testbench/modelsim/gTSE.sv new file mode 100644 index 0000000..b042cf4 --- /dev/null +++ b/fpga/ip/gTSE/Testbench/modelsim/gTSE.sv @@ -0,0 +1,4617 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.288.2.10 +// IP Version: 7.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _4c19f37180ff465ca20760e199a0613f +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module gTSE +( + input mac_reset, + input proto_reset, + output rx_mac_aclk, + input tx_mac_aclk, + output [2:0] eth_speed, + input rx_axis_clk, + output rx_axis_mac_tuser, + output rx_axis_mac_tlast, + output rx_axis_mac_tvalid, + input rx_axis_mac_tready, + input tx_axis_clk, + input tx_axis_mac_tvalid, + input tx_axis_mac_tlast, + input tx_axis_mac_tuser, + output tx_axis_mac_tready, + output [3:0] rgmii_txd_HI, + output [3:0] rgmii_txd_LO, + output rgmii_tx_ctl_HI, + output rgmii_tx_ctl_LO, + output rgmii_txc_HI, + output rgmii_txc_LO, + input [3:0] rgmii_rxd_HI, + input [3:0] rgmii_rxd_LO, + input rgmii_rx_ctl_HI, + input rgmii_rx_ctl_LO, + input rgmii_rxc, + input s_axi_aclk, + output [7:0] rx_axis_mac_tdata, + input [7:0] tx_axis_mac_tdata, + input [0:0] tx_axis_mac_tstrb, + output [0:0] rx_axis_mac_tstrb, + output MdoEn, + output Mdo, + input Mdi, + output Mdc, + input [9:0] s_axi_araddr, + output s_axi_arready, + input s_axi_arvalid, + input [9:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_awvalid, + input s_axi_bready, + output [1:0] s_axi_bresp, + output s_axi_bvalid, + output [31:0] s_axi_rdata, + input s_axi_rready, + output [1:0] s_axi_rresp, + output s_axi_rvalid, + input [31:0] s_axi_wdata, + output s_axi_wready, + input s_axi_wvalid +); +`IP_MODULE_NAME(efx_mac1gbe) +#( + .VERSION (16), + .TXFIFO_EN (1'b1), + .RXFIFO_EN (1'b1), + .TXFIFO_DTH (4096), + .RXFIFO_DTH (4096), + .PHY_INTF_MODE (0), + .AXIS_DW (8), + .RGMII_RXC_EDGE (1'b1), + .RGMII_TXC_DLY (1'b1), + .INTER_PACKET_GAP (6'd12), + .MTU_FRAME_LENGTH (16'd1518), + .MAC_SOURCE_ADDRESS (48'd0), + .ENABLE_BROADCAST_FILTERING (1'b1), + .LOOPBACK_EN (1'b1), + .APBIF (1'b0), + .FAMILY ("TITANIUM") +) +u_efx_mac1gbe +( + .mac_reset ( mac_reset ), + .proto_reset ( proto_reset ), + .rx_mac_aclk ( rx_mac_aclk ), + .tx_mac_aclk ( tx_mac_aclk ), + .eth_speed ( eth_speed ), + .rx_axis_clk ( rx_axis_clk ), + .rx_axis_mac_tuser ( rx_axis_mac_tuser ), + .rx_axis_mac_tlast ( rx_axis_mac_tlast ), + .rx_axis_mac_tvalid ( rx_axis_mac_tvalid ), + .rx_axis_mac_tready ( rx_axis_mac_tready ), + .tx_axis_clk ( tx_axis_clk ), + .tx_axis_mac_tvalid ( tx_axis_mac_tvalid ), + .tx_axis_mac_tlast ( tx_axis_mac_tlast ), + .tx_axis_mac_tuser ( tx_axis_mac_tuser ), + .tx_axis_mac_tready ( tx_axis_mac_tready ), + .rgmii_txd_HI ( rgmii_txd_HI ), + .rgmii_txd_LO ( rgmii_txd_LO ), + .rgmii_tx_ctl_HI ( rgmii_tx_ctl_HI ), + .rgmii_tx_ctl_LO ( rgmii_tx_ctl_LO ), + .rgmii_txc_HI ( rgmii_txc_HI ), + .rgmii_txc_LO ( rgmii_txc_LO ), + .rgmii_rxd_HI ( rgmii_rxd_HI ), + .rgmii_rxd_LO ( rgmii_rxd_LO ), + .rgmii_rx_ctl_HI ( rgmii_rx_ctl_HI ), + .rgmii_rx_ctl_LO ( rgmii_rx_ctl_LO ), + .rgmii_rxc ( rgmii_rxc ), + .s_axi_aclk ( s_axi_aclk ), + .rx_axis_mac_tdata ( rx_axis_mac_tdata ), + .tx_axis_mac_tdata ( tx_axis_mac_tdata ), + .tx_axis_mac_tstrb ( tx_axis_mac_tstrb ), + .rx_axis_mac_tstrb ( rx_axis_mac_tstrb ), + .MdoEn ( MdoEn ), + .Mdo ( Mdo ), + .Mdi ( Mdi ), + .Mdc ( Mdc ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arready ( s_axi_arready ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awready ( s_axi_awready ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rready ( s_axi_rready ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_wready ( s_axi_wready ), + .s_axi_wvalid ( s_axi_wvalid ) +); +endmodule + +//pragma protect +//pragma protect begin +`protected + + MTI!#e;@xIi7[-HGzLj~uK$ABr$Zn-[=27Ae'i}@{^NE;{e6lAK?nvVnanL_/'ua3cAXKuv?3BaD + V;$uMGZ,%lwJ#*+[[o_n=['CW!Ul$HUl_T{3A=O#}Ev@;7IVvZX$s#;\VpE[%H'vCO]}}q/ovC!l,oQ$?;'vGBX1nmXY~Kj*j{pzRA]n + V!wX^7Z_$2+bff}dCJuu~\uOs;>jln,es?E>K,'BmaC5ICU5x{5;mG\}Rnzs$eJ+BnzV-sAz1?G7iA5KCa'VoPO#OQCi3k^;3u#saCXAeuE + TOu'G-'-UA5#YE'*,+\T,#7>}D=VuWO_$*r'\TkY$}<\wlGbn15[$Q3u~C^$xYn~$VvDNI!URHG{ + JkT{szJ[?~{UB;Y-@[;ZR~{ulXEX[6a[#7QR_+f7m1RNCMOUxTMETI#}I}WkC$U~C>G?VCn#l2#d + FqOwj{HRU<{-X~]3zn']e=1Il~,[}7veO>#r*H[JZe5a=2Vl?sYA]*),gjlBZQp*TIlwG1ruYxoA + HD^GIY;Vzn>3[r[5\O=,3#+{vSm$!*U>erKI\^*?rom1W['Y+Dv+R,VAv?=+mzKj,_kw\X=u5;XY + amx,Z7az#=CU]'*iTU|$'e#mxn=kpBv\m5ir[n~4%N_a,=}2l$us_777oK)_n_!;\vu*~lXROEj~CiU + [$'#q7+WsACCv}$wUX5VX@pe}YeUZ9[R\wDA_u;s?>HD!>#H_'zwVHs$,prY<\dpk~JYAjzZ]e]+ + lGs\Hew'1?<]x>vaG_eA-[pC+K}7x#C>*=]F{H*!JrOVizi'<};U-*O5?GZJ0opwmI[5^Ua\O~}] + KK1![G3sQz{u!]9mz!JKRzJz!uvxIaXEa3pETQV^IYlXE[w.^@~A7m=Ze#-3@epk,Ie@+Gi^|%~+ + ~u&3^ICv#snHwIi\!'YH^I;]CG!7[7RVaK5BlU<)kA-J~CvHvW1=#U-_OpmlP2{o~*,_jzCOm3\n + ;9)A]VDRzA*?7<]O^l}Bs7'wQ{=iXAJ5pj5]luYJns{}!xrkCtR$a>[wG@C!7+G;3UkvYY=ww,w1 + v**J>kvYjYyr'Z*3N{e]\Gr'_}p@~-nTlfXCul:\U7lL2_zpPs71ie>Qp$>,v5jBm9s?T7Vu*>]B + hWAYQyX$E^CQOxsXlujE#;TT<<(rT$Q?aCIO=aU:bOioaDQ+T(U5]^l\=uY!zKoYIBy^I_~sEk1i + GZ$rXA7x<-;k'kxr,5#zCo>BQQR2aA^mrrr#,oX7{nZ:@Q'3=m]esHIk'r1Q",nEu6J6Z{++nz\],u1!.Vr~}eGnwIx@DhOEW7p$2CjQ[^EH@KaEJn*7A23xlO1p!DuQ< + Jo_xuvOs}rH;j,vJ2wO;@D,1H.z5}upz1!@[U5)G?{7.zvJUSK,Ea!>}oKrOs:2[,WU{O}~E-{r1 + WK+$wxQYv~Y[_<3\J-x1{k7jBs1ZEp-AO;a]?7G!BEkjRr"EooEiBC*HQp@~>J_7!\C1OUG$u0I- + P-{+3>o;Xs[=^e3WrAn15+~3,YD$^sn#,!p[QUKe>] + ~E2,l@V1>'*lYIbo-3$[j@}iNo~=Uh\_?xO+=G*zeZ=T;*x!no@9<X\}v[OjQu7Dn,?@l3[YZ'uUz?{7YD*aa^wBvjX'ZXnzwD-E,^!uj^,pF=BI2sDV + ChEpJ+Y_zRI;eIHs~1\]YBUY[*i>{-v3mRR4sk1=Kj^skUK]B;o5JjErW_Y2o31sn$1kE~2njV{K + gO]H1,7^#::&Ym*-#\;E}{C]kQr;R?};$QTKt3-ul7T!kB,7@OpK#7^aCwvkD{},^5rA<=sT];v- + YVeok>CV~;DW;VXBVQ[BeaCaB'7our1rKsZp]lIUxToE%UTHJ + $[A7mHRT=BEu7jYKn\Bk'Q,>_QwYVJBrrwK!j,>2K5oJ0#HHl1uR]l'H+jn--\-a;,KVkT}7Ea1? + l@]HA[iw};CA?0,woQ}D{Ju,nKW<1Wj\p{FJ>CwJX}pD3@{,uY-~EOaI+\k>}$x~5?H!I,GYsI?b + xmJE>T$EKA'L&uQ-HOZX$>nBof*w>Xu}[QtG2XCl@n@W_mI4aT^J9MaK6Aj}ap7YQiw~U# + x1w\1O7js-B1AlK2*7KK][zu]-~iTJVWn,U,Y>Ri{I$DW$,<_RR2=VwT}Jz#{+$%ga>==Q,n}9*z + 7n^;wQDTQU5OTpV5GwE};K_t__p}ue5ZKRp]Oa3[+U*OY~o3o>mR1$$ut3{W'+xlY'DQr]t)_Or, + P6^I-I!rw+ou7"n^7@-]{]UwB[0-o}oEu!-l_CJ,b + D3]]w^~3oi +`endprotected +//pragma protect end + + +//pragma protect +//pragma protect begin +`protected + + MTI!#*=C_eX;er73ZAUn>TT_GeCE'6KYE@T-GiE#+BN"iwAueQz#\xW]Zzp[RZXwuDUlkU27Us5* + J[x?I2TX>YT}aap<+1$'Q,AmOoXA31,['>Kjr7oe-p#]>l~z='mVsX^mE$pKATo*D?7J=?[*rJ@o + [Cdp{EWu}7pD^!=sWO~G!}ANTavv]v1?Cw~KkEQWL@xYipr5wwA3mo-E[luM<5G76-sDA>BsBx77 + pA<3;T6#wo7hHXU[#ar+[Z&1i@R}[{unaUBV2ITE5*#aUTQY^7[V}YaJ'1HuI_'+O1AM[x[}o\Qj + 7#=K1rpw-="l^r2=ynD>[W};3=m@>Kx7#[i}#Qx}j|;1I72T{ZB1+=1i$@>R'y_;B>Y:>Ijwp]?2<,5Kz7_VGGnZ@Wo=sH5^u}Z-WKY"pjG{>jUKIOy}$1ifm^@o{QA~7Qk{so3E + !THu$--s~{BBY6+1$'Q,AmOoXA31,['>Kj[oE2-]C]w<'~^~WRo\Bm1N6#n,BV+Wky>>2=-ov@/F + Xj-A}k$YSk}rU@5klShh.v + jSwRx_=\-C73,Y4!,lQ1AI + >B%>l?BnG;#a'?@VkB{RW{~}vo7?^k^N-QrxF=<{VeHomwTYOu{>Y?T\Ys*@#Q*m\n[$+7,7V$?1 + '$-IOfn1;nWD~2,EY+nsIVE-T{7s[H!z!QpZ;!z@GESe<[oUR}mu1_Q:9i,J1zRmBUDe{;p]^Bim + 257,jRp#ZwEA3W5?DCk^vC*[+lD^K6-EHJ*nW3I+sA$BB=1CE19W\]sIT=7]^G\z9Rkp}=.oIpDmjDUu^aA]nez;[}5lEC_^U[YsrBk + Hpn1{?nnCRtG1e;5CMA51>p#5AwwE!$rmW+w@$l2{uGxW3Q?<{1mHUIW$@KXsXdxezk1*VC9mnQ^ + ^OssWeQx=$nE.t;+{Trm~^oQ7XBB2kxA?BOKrTeCr7\;2Y-*~5};R]_}$Rz-5QBYG1W[\T-,mCA's:U>!njpHv<[2k~pmOqir7l/i*Ep\^ + VVKor@Y~Aa{YUA~wQpe^j;BI?xB5v?ki>nH0,{Vn + v$eGCpU-'womJzlaiHWj/]=Y3y.?5QZnVziw1;r#RZ\7 + <5wOpR5~Rj_mEXK;GxYYp-5LCe?!3Dn2 + ^D#pGar*Jr2[uE##I51r3>m[waA@Bkn]l>v^\1'#01Q1{uR=X{U<=uO?UY9@pz# + [>{I3@jQ]-9s1zm*xG3L'IRlP9NE>RKkl\O2>WKG7[W}Y{G2[}*[sx[{TTAWp~Q]1>,5\>5?Z+luJEouQnu=ZD{,]vpYs,~v\$/Z_]=k}Ou03a2-< + XKJ{a=BeZ^\Qx>snp\5?V^5A*5*=nzlB?ATXo3soK=QB+TpE@Y]$-po8q"2H}Uxjuv^ + @ui1UDGE?BcC=Tu\$Xv$Y>n*u,Yv;}_bx6Ei1n1Wn-=AEYGw'DwwY;sTZCa-7]el,]q@UUYsEl1nnQZ@Kv'n[=,2#+'A?wT;+D\7Jy3C\?'D-_e5z!Tn + 2{oQ_GE>oD2Ea}O]4YSdDjuTwRa2U'w28KR!l,$&^5vxJV$je=V + AiQ'oX+][v05AEqj;QTx+YuL7Uh%zXQoZRIp-{_'X1#uz|x<@OQ< +`endprotected +//pragma protect end + + +//pragma protect +//pragma protect begin +`protected + + MTI!#;,_@!{KEi^ril'A?olZx@EIRar\~Xa]UFl~*7|"BZ,D,,_<+HWr_e+[o32s]e_e$E3UZ'}? + eBp#^2$+>YT}aap<+1$'Q,AmOoXA31,['>Kj^kpsJa52o/}mnpcY5RiFQY]Cn-5Oo_}Y[*nUl>Ri'~*zXj*\jwH + -11WYpZrsNEKYoJVzQY+VBf>DAGOvDv{szn;TQ\YzlY7ka}^_!XZTJ;QJXE^Qm]V~+##n1ROUQG[ + -x79?]v*wI+R,OiwBWEmGG'{Y+*U=YB;l+u7l5$@opVz]e+}p$noJXl3~\e?la^I#h?$IzHw{=[siHieK~Ok~Hlm{AN' + X-HUDTQ[^E3HV2k}kXjI\B!::r3~$Vjl]Y5XxUNIm*UxCAwawo;U<*2f?XwFO;]2W[h^dM + mCEE1*BZ +`endprotected +//pragma protect end + + +//pragma protect +//pragma protect begin +`protected + + MTI!#Crl^]Q3n5XwJ'5x]rIvQHEIRar\~Xa;;Fl~*7|Q~zeIGWO$vjUGZjv\3-LTj@$<,m};Gla+C$Vr*Duxm^;j+~Y@K[-m#r#rJ'veE'7_KeQe'eRr-iTI22];pVG_@T7a3A + 1n7IP\^aT + alBn?Z8q-8In$kJT]{'2e]@U!5Fi5r>k+'k[TpE]u\$$~rA<]Q*DYw!RAIn,eRwwr^_*jJE]!@VT + p$<'B{EC!n$gP[}'e@DJsGaxO%YH$Z~CY'I6%=owE5UOJXEa$v@J!-10=?oDnl7;'+aK5<{25r~$ + JTrJBeX+jYxHs}+;7{mJZ]ZG7='GklakiXaZ'paJo$#3lmj,XD7='v5#g{xZ's2EvVs?~5HEz=w7 + {j<=^**5@5QKRr}jX,$}r5]^$z{}+}x[#[\u]\7KuQ]Vsk!= + 'KQjuzlZ*xD3Tx!aGum+sQIm{O^'#RXk0E}2U-]T[YIrG + so$pH'UaN1l^]m{v,UE>5*<^?D'3+3AC5XeVOlW]\jzi=mJe + RTuciDmkx>AYl^$AR[IO1k33BZIrzOu3Cjpo[pTsEmY]uE+xR=T3CEC7O*ewlB}vIW+-]rzB*aQX + IxxIATD~'I?YJ>z=TB#!QXDsxjzm=o+=l*YY"FB]Z{k{aIz'xAv\^pTzC;zuTKk1jT#w;@l!$mAX + B\a'K~Q;QSjriw,E7o#e-2vZJQrQ_[%,~ensGe=-_*-=D?I_zXJDHoUI>nDmEBOx>^@Dw[,#>'=^ + 7n;uXe@1B\^ElnKx3W=$xJTs>x>'BY}_YkaJ,s?6~{QGP^$$]5*K+~B>J^%ECIZHaTkT$#*u=o@OB{$N[Cx=~Y;}y)n{ + w~law$Hl+n;rVToC+xRW7Rwo1#[nx!Hxn_'><'3j\]J\CT${IO1^WtjV$saR?7^y'sB>DT]?HUd$6n + $puezro]aDC^2^o[JIXB-wU8aHH29>aNI;jJC?DRa + ^s!a2Y-AH*{nu]OmoOpUoH[$rA7-IJ[ws/i1iDoKmsk7v7;E>X;@UB~!;\E*'}VXRT<-wD\3XAH\MlNBWurvB~?Q@-K)''aGs[23G\TXG\1n>D[u*al[OI-A'<+}W + 7T#?AwVk9]?s2[$Vep&sr{+BuoViE@;5iBE%S7l=YG_JVmI;_x3QEWesRlibC!ABs2\Ijw_]Ii=,Z{+[Q~JeQu1uM[WamFEl,u}iV\Vs + aeB25T*XKrzCU#O2+{z\[~Mcz2EmO'vi[vT3=>=jQnVzeAsQi\}QDIAa*}BQ_tIZY[e'>XM@[#{9 + {{5I^2U^9heUCO#T'[{YVC}wr=q'6Q];vPHO\{CXZ!]YZXRn_\Vk8'RRpw*ou$GKYRIG}I35Eo>G + !\ZlW\!'a.QwvupQJv1>l-Oz^GBWvTwBT!7eA*poEaYUCv + W7%?H^WBdH/W$wuxZ]'QGXoN\Wz}zO__7I^Q?w}n[}^@]hs*]ussYT@7]G0z\7x7ZVZ7#XYpBHHCj[+K[{ + AT=eEp=\pYXnwQH\3GWV-Dso;7UoYY[T9Je>Q^-m[U*Wwp?I{kBr,!#lB[F[*aW\VwYUlk_ve + ;#GneT_lrrv!!=i'[a_HXxX+KDs<]]]zA<@eEe-jm$~E-@>^Sa-_s\;[svsBIk,2Yn*Yp9R-{uk< + +#JjuKD;$sTnvmo?\R@p'aZ'a![;Ur7{}!uTB@neT#{Q}iIdm=op_v{ZOa*C\a*#G}KZ9i<{]Z>I + #,Cf[?sI'~Q#iz,2*x!*5c-jp^F"epC}^WYz>NRlKUV?CTw]px2w7{Q72QU,up1{;sU{W2T';YBB + eCBO1{WBk[ZlIY11Wwel$wJOKu3nKsT<[NYs*iYk-,p + 5$k![ +`endprotected +//pragma protect end + + +//pragma protect +//pragma protect begin +`protected + + MTI!##AT7WBH3;8ZX+=WY;?}a7,]wA?7IY-+t&wa1[yN}-[2o1WQ!+E#1^5D|DksiGZD]Mv3Wx5< + j*VTm[rZ,%lwJ#*+[[o_n=['CW!Ul$HUlIC7BA,O#vGi[wp3xag7Jl-1R7IwsGr}?RJ|R*#I~n7@ + (FoC1Dre5U;IKH.t(e2~w7K@zG7n}}lSIQeZI@'2j|VY~O2[{p~V)TnW@$R25|BB\2Pze-j|~Tpp + 7v@2RR1-XY[OEBuZmYJwv!}[oj_#W5R-bq9Z6:JT{[}<\2E+H*JHKJDG=<$$1GD + kw#'+ze1-]kIO{-xzvW,#~n'ijJ~r@$GTQr_=],J\za^;VTu53xo]!r>Dj[[e=C%i{jZCZI.Im>R5uGR#$k+B9eZ}H&):vIi[IiJx'<_QN~wB'r_e{I + R\$jOAX}QUA72!*+r_xD}EDtawl,=sY>!nl,{TKW}iD@72_J*WGAEQp>l-o[SV\+;^lzmBx\V{E' + }?we{yIlKkaGTFI\+E~RJ_Zjr-1_peOZn@p1Q,I~Z}ljlWlY^[#}>IV>$j6s?@ooCkKLvWA,B + UwU}Hj@XYaw#eu{B[X''px3_GWrNC+l17]KI1A@uJT,sblUX,DTnak7WRzJO]8iwrKRr*krHI=V!C]rmp'zE1VFDG[@H + vuI!-E3}msvVUv?uDo^WeVul1iQW'_kWD+Q8]@JG>xeW}\p$h3Y*xCk,o@jIuYs7*X\^J}s=Z[k> + UTBo3O?Tpj2,RziXx\,Aa$X5_o-RY$v7qs;Ewl*UOm'Z=HX2I/'\:|[2+;^z}R:k'Bv + rkY1lUzD$OOW'*k_onoG8-=j5z+u_}@'iQ?Z@U77v~aTopT~'CXpG[j?Xvm*VuDO<#1w[[k+?12J + \\$,u^5U\xpon7o+n,}JZxE7wJ[@Yl{Z@bQoQ>r;Vu5\VK=>rAQ~vZ*-x=dl4"gJ-X]VG+D-G_21cn+_ajWZATsH:ru$J$2OD$QjGCl-CAsuC#jls}2e3H6@,s3kjUnrjZn^[=s9]5o-P]*p<(kYkT%MO[ + ?Ckm{CoWR\,'4~r;5 + zT<'k$_rPlwJ#*+[[o_n=['CW!Ul$HUl1U<@BIM+1a-iIAH-Xzi0[3oK'3e_]W=5AO<'3j&njzGo + U'X\SR3*'s@QeIg}mUoE>~=S1@3Ac"4bA},\=>n2{Uu\r1<$\'sJ3l!*j_XEzaZx]e]U>A + '!r{O@e2z'<>s;eTp,7$YGTwJY}a^ZD2xl[#@zHo~j{9UsT~.-w2X^e}K5TujrvQ-F?{t1qE"}k$_|s>>7L5d?+aV],T2=;*Z+XQCYx*>G1G>wjQ^-U*ZrR#UmoD=u^weZTwX, + Ena~A!<*VAUx>~mrRoxIiEx_^[_^Q1!GY\#QnEW>\sKhkUUID?<'a-l2]T#wDkrTERg#]BOG>$s^O=J=i-*2}s#?x[[WrTr1WKl + RCDn,=Ymf~=\~=u73UD<'x]Do_apje*,DTrV\.$zT1>[~a^!AaBA-U<][K{I'em]KGT]\Z,p2?RC + VmvlW\G+~->AuCqaTeQD3Uz1m$CQwsa1#JzDe5C;},B}\4Tz5{V#3,RC5e+7A[<^KE?zrvr_mwV{ + <~Z56*ko'Y;1e_[2aX's[:3_\nInHK +`endprotected +//pragma protect end + + +//pragma protect +//pragma protect begin +`protected + + MTI!#J[kZ#}{]Y<,WEjNs7z3\yCnJ?[Q#~,[k[6EtEuJI6lXRmnpjT5nn[6}0^!R2;]Q[9^@2Ken + C?pHQzvjk}]irz!w$wIi@DFzx^QI}VCXvopV'[QNP7uZzs@;ABHQ1RXBYQ+ji:eBA{Gn5kp;]#l' + kQ'ZQis+O?r]WT(&F)M"3.M#j=;Gj+XtOa\VsH,ivO'=T[OG=[-oarAsy]Bv{;VQ]=xR{;l{V5[w + 74DA{jxx1D$pr\lDv7rHA_3^7IxeG<1o+k@[\*K>'[3_dTxlHw]>zp@uOnCmQTIxH9TXX+wj5aQ! + _WI,?zJsXIr+,YOBU{!pIs~|v;@+]7QTpj\Jf*X-x/e7DJviDYYqVu_aJC2_WUnB-Dp-_KZ],\3E + ~]X^\9Ip;@2>sz_5?'wxm]bYX$k@<'s/r$nV#n*s\m>z-s5k@e$r}bJOAp;lO5Zl7 + +>Un'<85]piC1RR]V$>J + oTK^_mC@_K{$V{7HG;UtTr[V$i,Yw@>E'=jGBeTl<$v + ^-W^neQ2Y\<'-_,l#_V2YxW,ZX2Xz{KCrUv!5X+Y1eRXB+3R$HuI2IV + 3'[H*,pvrxRGI!Cv[VD}'rZXzuIsejxn[HQxi{jBQwW@0Q'me#}Br3>^DiI?,vGRjVs\U)5J}Af5 + @l}/o+a^u7*uH_TvI#~@[{Bp]*3IuB2kn$IT0Ei+Bi+\[,CX-o[2UVzD*rT1lk]ID[;HaEBI~*** + 5vV+Q=rxpG*QJI'=e~DBiE5[Iaaln3Lnr]jHRQA5aKICiWuj2A'r5pvB=s'wC{aOB~r;^\#7i+RE + 'okpYCEo^HvYeB57~,sWB}^)+>O>q]'TOKo+TdrvmOT-sV#Dks*7VVTsR$lm1<}I5-w1in=a-~r! + ZaV@n7Z1X}*{}u<{uDwto]?aaAw^]2I_GsYUr,'T8E{_psH[T2s*GpJBG.LsD;T=a>I}H+Tt{vG@ + [W2l{^JU2Q;aU*r7lul[1_u+fY2'Be[sx'EzZDrva=mvz}i@zpw;DX5QZvHpKExCU4lXZA;Iv~D@G+'>E1QUCX-Q;$]~{QoKjAHI?OHGvp=ZQW;$oi:,HQVwO,]I*z_Ovsn*1R@I-5Te + jv\q5DAz61>K@IK)DRuJqwjr7Jn[e!;L-[D*F-vZjVj2j#F1ope(V}XJ=3u+?[lGBJux=KO1bRroY:^aUzmR1C=$R{m$]UH1R\}E7$,~5plv,?RTV+jNOCio= + u5W+wlvE?}B7BBT|,Cv+^wJ!|Q?vOouQ!BRXa\\Y@bRo?TqY~e{x#AKBI@A+Q;o^Tj['G_lEAH-E + D?kx;~B4E[5\gnswkJOB7M_YmrR;J,,LnsoYB,<^ + eCK}r*CJ7zp0z{a]%2{[X + +5QmBk+QIA7{'C{DBKW<^p!urVi~RkEQne#,pxB#]=OvIW;BOAZl2;3TTGrsQK*J>Ro1?QO_YEIj + E*[[wlT5&5VVlzi5aiO]n)!X(AHZz#RG};^ + sW3(z1,+8UOi!W}YE3H>E!_{'r$B;R;<'mCjv[;77c1>Tj7I]EjR;KIUQ1:Q~R{pwv-^TJBhrC!C + R\i$CI'-DsZUkO+EtuDI}*'iD2,ua*;7ltAl[mrIua#O7u]XH<1a}2+D'> + ID$Q|:Qi5;I\u@PB{v1AAXsrjmXO^k$iO5,Imwj2~*^exJ + pjUmCDRoRI\Q;zEvy#X\GY!=7EXjn!kCV~++lCDA7_w7[s$9.Rxvx7o~3=}'U[KlirEs}9!^i#Y>H$3C=?v3GjU5ZJK + '=O[aRQkVns\I3' + [?s[DnJq|>jv>DY+Tv{!~?5X]iv2u@_~RlkaRDYBwKeWEwYG}AQ0]e_{@>5!k};zeU{Otsp$3Ep{ + _vJQ*I!*@>r3=/=l#r0nHlROo]WfjI,Q}XmjT}[r[zE]kl>X1s{{#7lYC1^Q,[mRVjvlOnpw2CI1 + z15H7noXp]zx%vUU-CGkW2oY*_!^^-*1r1QW>)XIO{ATK>J';sYu[azGkjJQR-C*XpWGE@71<17CK[ + ?{a^55x{5EBj^XOzV\RKj9CBK^ZT[='\H3DB,ev@vC{O~p>Ozo}W>{*e$TurVv,J}1#G$'~XonV7 + THW-+!l5GvXp~l}?n=\vz~CIvQYH_#[GTl[7_GmGDK^Ew>W$rY<>TXebksY#.(x2E~$zjasll-uw + JR]v!CUjYz,ApDPwYAO'KO*'np,*1Wp\Z;v8?s+@,jJ+IAH,a<'TU^OJ[VW1=!W}gk7-{37*GSr'jo?${pFf=7I;'EzXLDGQH + 3V]J^ZZRuGr^eI@__+QrvwWU7 + z#,k}r0;wX@j#w5{OunZ^G>%FNRj*ox;Ds-sBuZwCj}*npUBTvkGo5-OaW_li + @p(rj-BBXT]l^]Ym-\r!C3j);,7$l!!axk~*~wDQYor!wjj#,inBJeW5RmKu@DYwnw3{,_mU|$*s + J_}2avrl!Bq[^XW)<5<3j{$T3}aZ~z[nkrw=wnCV:$YxK^7Hx]XxO(I}1\V6!+lDrz>3XxE=^GDi + U[13+,so6Oms]m_[!-^'\SkOYI1=]lI31e#r5<-+~E8~ATB$aC@3o@~GJ1KHrKjj7-n7jO'n-{zA$eUeY[],WEuY>F2Y1OrE + XA^BIX~_jn{s[+uGK7Bk_YaDRWw;XY!uz#_4OGw{ + x<~52n77#W}v{ + mHX--[!oQXY'rJ;BmsCa\l"KYJJ-YX,qd>C!z-e+JZ-wzBe]zT9a<_g_pX^*7##$KTuYr7x + xuG~5uZ;G2~EOZR;(<'?BYOxoI}Ol?E=zA^HxqOEX=sIZC,\IXiY>D$A1+XTrw~a]QT5]w^uj\'Y + KUe+^GLw>KCWCpXY\HeTEDK>s1X\kxa@V@JGEroAnoAH_ + G^Qob]oXeBGm*M*w+5k]:3r'lO2J}ouO~'&pzCja<<~=,$3[kHDOxajsI;_D]!EQ5VW:RR3@2Qev + 0BiVYuTR+b_+T7C~}^e1+XbOC]vK\2sJ5GQGJ{m'<{AoHeRZ\A73eITRGA!Z_{W_J+JD_;oHGU?O + Z;7a_=K:]35Jn>7^l3DAe'w>Ox_YpA~5p#Qpfgw'[[om'_|qRI-?r;~$|_2+\kB=DL +`endprotected +//pragma protect end + + +//pragma protect +//pragma protect begin +`protected + + MTI!#VEJ'R$IWv0GBq{sOk-Gn-lArsmD+*+E#$AY}[^@,?t^n=?IjOA}T,?%FPzpe$uUD-CJ_eU$ + jmjum[rZ,%lwJ#*+[[o_n=['CW!Ul$HUls5QxGR_#^xkUUp~T+HU[7K<&]JK*N5[i#IUAA^0Se>Q + GOAKj7!ZV_s!r_^T1,UrXD!;p^-^m7@R';;5XJ?*^zuOz}]*]<#W'aTPpkWk~G@kaEYH)uY]WI1{'eHKUn_ + =-JpAl\>HZ{opARz]Q!l_CCU{v,*~2-YxVolE5$anY4Q2QDOzeA,T=!*@v$s\{ZpBGHPFs{W_lH1 + #]=YG[\pj2Vi#z+-{&f>Ym,[@>p'+w>n=K=BC{-aG=7$Bkl7kARTBk\nDm3vQw#7QXmi51nJ<{ow + EHap>R}lRJ@nr7+:_f~HoUE'2m2>'rT}Dmw\Y}'ul'2$HJH{$^_R?YZ(o?3sjl>;jRWl5KCkP--H + >!-$RgZY]-&7k2?_ZE<&=Z!~3^!-Gp#ui_lTz7W>ox3r_k1;y>}3[[OXmh,_^I!>z]RsY?*@~[mx + !?ri+'OWz$j_e;V@RoVAo{/F-E}-#e1put(o]=i'B*vje=O*1U*QAe$va^A}=Y5'W3vX*_]s1ZT# + <_Rm_mxYH}-UY4C#@K'75r--,]Ua_X~'pkE${AxF|RJ]mX1aQ_\-Bieks+GmRw!kEm{l~j7s[OO'2]HrFNzV_2y*z*7nHr2Y7p#M0#7Der_avba1C,[VUnZ'AT[gWa3>^Gir$nT~> + E=e/HeK]csz@\vrU]CjnTYi2uIKr7BToo\XIZ(@x;7ln+D7[T2+sQ#a7H3Rh}YZ~R-W?AYrDS>6h + s<7ZD[B~Ra'jF-{^o::#+~r3ww!erOz\3'\a>vAWxRE2Q,pevsiH^lAA.Gn^2+Bi~]xW#rEz}vRw + _7e[EI#$xV1v[FDEH-q>G}7$!>mgAjQ1njA>c?7OO"6cIQ+]yTYnU^'+@Bk2D/*H++(aRpkX+z[#$ZW7KIE<3\EE\jHj']ZE?m}#^'vAj#JI?OrTuaQUZxoj;QK + ws1uBa^En<}+DA=~\-@(XswJpGvTR^7^=!p_t_2Y>l3;pK\#<6=9cGx?AB#Q?#n_sjBT-l+T?V=> + xpWW~BWX>\Ooe,2EQ@G_wKo\E+\0$u2'=KX'(Y$BRcf_EH2{Tan'X{s]I@HpTpGf[=J5B#m~Y>n[ + gWCpY]-3OHp\Kux'',{11IHReb{7nC_[uZ!5+RRr7wl@OT|VoRp'5Y#7slz<}T[x$T@IG_C]@*G@ + v_jD?7o[IQjGp\<>'\~'@@\o#G@~msx*E{n;T>r,C$v'vC{2^C@I^ + GZABWs2$O}joe+AvW,;1,?*(v[A2$w;?Un6L*}G#*\^=>O~xgZaD'@_kx]$v,j}v=h,aG~\[\C$s + B\5rkBV+OiEo{s&GZ~sIr}_Z[D!\RmThC[IZ5Ow#OCVu[nHa#o{,3Gs}2r>X7JY7o}E\!xQ*u>3- + BZW~Hj@=VoC~Ue[YYp']Sx\\e>AGB[zkHvEK'Wr'>e7H'aoRs;p=n4(3},piQJ_o=ZVwT_e^\I~D + n}vj\5}l2Bak\p{!_754z[VT:]eA2#Y7eyceV[V{jZ;ao#?IWW[wxC[7@K_q]_,,~tTQ\AP:zi-Q + *_xDYTQ>^weXnnGmDY^1jx(X\3-p1w{ka;$*AY1Okwj3-2]k*~xjz12GGHHHa + +UDD@jW,D*1xoR$QlC;TB{fj[ol{eVGD2Xr2{'m_}W\('R{:~*>@$Enn^1u}'p\i=p#R}?<'EXTe=JlC|~p + o@Dlv#z+j$6xnH_VZxKA=s>*eeWQQkj}2RnEJ*~LQunR}1WR_mm + GC{,2XAT>B_o^Tn}{*$^KV?lOrD=i:!_ETz^ATx7zs.;vVevoiE:j~s3.~pQ,<>a,TwO*TIuwxTV + i#^{_Ol@'p\pu='-@T_3rl=5YP4GIu*R!nk>^I[*C[,nC,#se{D$-5w?^T[tr$K=z_ZZEYQ3KT_DA5m[O7UBlRsQW[Vi\ACXQaaor*U + 1w3^!=D=cJU}BuD=-lmlr|^nu[;'xxAU-Ck{[7Ga{Kio,UdI%ip-7lmo@?a^}AG,la'GKG\!]d[@ + K5HXx'jD;[}F~p#CEsA#ZrvDYV2zu_@*GxZ\lnI?7^xQs3w~YIE-{CR^z3j~lqa>j?;k7?ak%=C,pq)pM*>sQ*p>KIwIpNXIvvv;-Dr*CrIX!?t + er-'WH$u!BBp5/iHY^uECH2tr,_;6e?={krZ1vv!#>oBT5kJ5z"z~xH^~2u}GDKmsHDEC5i@@#Qn-!]\X['x^Ix{C-Hrw--{-lVDpWD'!rT7WAvJ[ARC}+J#} + ={D=5#7RT3',eROVA<2o{}EiQRZT$p$p=+IBgl3$uTn7OB+KT.j*>xCV>B=3Z'aY'jV}EERpIE^e + _^1MS@[sCCmj7Rp,}hua$1.C-K?mEw_Bj2k<}tr}{G&uGu~/B*2TRO=~|MrRkszRZ;fAn*AaDam. + IVX2#o]O[WZ_rXBBO;7_$HC&e^@=c%ma-~s}>jwp*zI,Xw5hA7W,_KX$=M7_Z-~\*$ + ;*VX7D7\$@+s![ns5pWBO',+o{5ZT_#7Aj{A!<~IY{wx*CrIM9Uw*Jl!+Qq}z[jrww{1#^O$;zI] + {V-AC~z*aj,E1w-I5l}?lr^Bz^@>]E"2}UYZO<5B?{\W]~;\\^J)kQ+>Q11{_l^2y?T1E}&zGk= + *BKan*ZkX,4jmXpB>Wv3\1-YR-TV<,>ZQVRC\H-u'aI_ZuoQ[7W1JVZ=i{!+X;UXE5<};\sQKw$n + Bx_<=mocY;TV]a^[vevJ=vipfo{X,u,OV$\Z*V}WD^#~sVW2w]#D>x!U15$E]vsrd'[,sH_o2QHC$'JW + ,U,\$xxz3p2*CRIV?T1u!dBeGQ!B^GX&/kEQ!@RXz;zYe1wjXD\#{ + T?\o,=}sowxVuJCVUxCx#3-D!P=prrTs}3nVRjsY}_J>,m+@lGA5wlerU1U#} + -Ea'kQYwraO~_~$][,DYGw\EQJ$pjV5RZ#f?]x;.=i\H~9kx_uDZwIfUo7ep<2p#s}15\1J';lB+Ek7p-r$rp^J{@x_>,x>JxeB7zK@K3*'?WC*~^WE#1z_Jl+Z+$B.RGRB,+ + }Et8kVKJ3<+I]7#aYepElYi1L!>@u}+,Y@SGA,\EB*1-IO7ZvI5{vBe^?T'w><4;>@jYer'*o$+UA,$R~Tj{xw + }jz-z1C3UZdx]uKQvuH2oe>@]zruY?xR>oB}Y]~;oRn&>WW+ji\C.;'HwQ3rB1s?O}uz_p?Vo#nG'Ri@,]5pa,]># + ?oQpa\>f55 + ^2W_TC@OH3o5xKZX,I?E#'pQ=\1X};7$XlG;VKu>j}pn<>1ap=$C~usK[-zj1DV?vaUH{@[_@,-n + u[r}-zjlAi=#CvGCit1*7r|<6FB>r?Yl_,.=YBo7}aEUz,@_T1V|d,k@e>-T@uw$XtWeWl}R[pC7 + ?~mnxwq7svVX}}~sYHU75}R-e??^kuGS5a[C"\eHurk^Z]cajZ[?E[IMKRT*I$ikwG5]1ao'Ar5X + Ck+\,eO7zV+nT>K;:IG{J\U]As5{Iv3'Vl@YX^zWoXIRuOIAJ}zHLsu2$]wApRG_~'YQi1ivDlH[Kr{$Ul-xun$Gr + BUu}CHT'iI1}%#$5l+[?+6rpT2G=zp.![-wj;QTDGRV=JQnaG{~JIGonj=CRT2C$=^sXu,r3;Q(T{<7~+$}Y3[v{6%*A7kNr{+Z-s@ + 5oaeZse7+ITWs-=zOz3R2$5+rxDj'h_eO_5mvpPlnn}2QJsHe?l*]71G;YUOnET=+}DF$wKAt,jG + zQrv_=XICI~<'oG}B+1G{07jUxtK^j_\spaBk,[gBo,s'jDRErZs=m@zk+;[-ae$N1B>kW'!]BTV + spUCKGi^;5V>j;LRoEx-HjKYZAuzWGY>U$7NRzx'JV}}%DWjvYwajkE#u-jZa2nXxq2j}n2+nEz\ + VzZQ.I3!u#R[1OisV==^BDH]zj]UDSX*GEDiv1=#~eU\snGK12^+}CHnHK]-rn]wQpVW;;?,XY7Y + ,]=a3]_@Wa2o^-W^G-q<}=w=R$-2=[TRmoR + 'Z{A}$1xXaE31okn^TIxp^zl?Bw~+Ua'21IQU-5euvjU|^^,?*1QBC!_ao=uE,$E=;Xu$6<,;Y/Q!zplTR}rB1H:KXZ*IWlstA+r7AaV,2D3$o5u!ID#K\r@51C^D|*piJ4 + u*x3B?'?C@j\'Wr\DG=7v}E+<_!pv'-WiA_{i'=@GoQT+RKGPRupUv+s'#v$n;I$uqAInwo?+1lGImHY3?[@$]W}-jo~@vww'']R1!u^{{owAj}$-5J~T[>zBZQ;];B$JaB\1?j;w>1+_i$TUnzQJ*>KHjk + J\ar_*}s7O,uIw[IaU}s7 + _*T*i131zQToxY$m~|WXYWJs}saAAQEsuCuVZD^n;=C#vsZCBs#]Ispyk=]#-DYZuZ~IlCR\KUWDVz;*\p + ZIsJ.YN1a1Y+1,\VIE;gAz2;^}13F1w,Wb)C_ZxnYl+QsBU*dj2GG!$^#GqH'$Rl#m-RRGrGE^2V + _*o<4OREp:BinCO[=rB_Q525SV3uxria_<]]pKwO'zDuOe + ^Y5v)+8v;Cll5pHmRxk}sKrk7UZC5=-unZ?}#>TT**To]m]I>O-$V2r~EVD*el<{+YUaw{{$HKQd + JQ\TlzBzqvVTYBHZzXCTGVi,[%D*@sw+Z#$TEZGn'[A+E2F=;-3t7#C'?C]ze5~O1\Un)-p+'3DQ + Zn$CDVoY33x>~b+RsZ![1T0,eiEin=;e>E#,CU{T=2l5o}@$H-BE{]krK_^#1b=B+{I-7iX'_@+X3VjI;-[@mI1@ + aXiRZWrQQADKZ*ECirnwHXn]nr~pw2C>7?}32aP_z^H&[55Imzu>TXVOnU$*Ih+a},E@3_cQ@{O~ + DWly8q#^r'lH@Wz+rwGUnm>G,wHA31[Z_?u57;cl7isWopp,mEW?}*>>1BVo + ^j@1=I[}ZJlM:zj!l_W$rfe;GA[GI7%Im~XjH3Bx?n+?QZvIXS2HU;1?JChe*1j#sn~7x}[<9UT!1Y*}#c;TTmZ + YIs#QKVL@-;\8cxWY~'a*E?a^z$xa2*w1~]!5vjKC'>Ol%Ii3];>~D>D'o*kE\f+H$~iG}53\}51o1ZW$mRZI#ARK7ai}Y + 3Q<]A?BB?vzDAonn>UEQa=EI1m>Rkv:rl$xZjJw#R}3@,z> + F)Y]Txe1U++,'impe_^!7YeR}>$V!-ZA2nf*lplDv?_m']+)oi]Ww5awer{G?=;[]~QOd0a1m+Gn + ]V~^^>-}Ra-U]EBzKeKsCK7;DoB.OWA25kDKWaJm{w5G.OlmjRzT;V@zoZ>VioG2OfN'=u{C2=7p3'v + ^w-;1GmI%Cn[]*B5oWn=GGuUl,]>WGiaEXEHw1UXGir;XvRX+zC,^wwW;\1!a]JH2{YX[,3Y,T<- + R!]K@jo?B[@3ICH=50]aQ58~o5_%3r=I*ur,J+3[QoujXQVnuxK{\we+fsQaup;Y}\K-H5WZ_KwG;npXaOCqo!Xm@r]=[WAe}z^\Res<-AK[[Ej@/}vov;]IC-3Hg;'s5=T$OCEE\j7#w(G$k3r7<#k7nGr7^@vuAKivR$=rG*vVYI\aT,2-pU}nGeo!2}*; + p@V^\_1CHXeKJT>Du==m0Qj{x~H>}u]v'Vm+*,7X!-a>]*7ZuopXXsjKRz7Rp}uOH4m\k{ + rKAAS*UWX\BHT@x\'l-ZEW+e2}Y7@2rH[X5J37HT\7Ge]c>X7T_>Tln>ZpeknsiVu1YsiIq?*l[' + m1#Brz@tD=keXp{Ck$ED\+ZD~sXv^,^-s\HoC\@D}TIG,^iw8~,OJ396{zCrVD=$D#CrkBU*@sK# + jU'~'YCm[!r?C[\ksrj~l=2w9ICk'=,2Y*Y-!Ae_l[3eHE}}=n{OY7Oev,-V]yM*W1^!_VsIzXG5 + 1]}rD/IDB^u_@'p[$2|3p}UG7ur2vT@VRJwzsnxl3jna$Gs]iRw-\kW;C1,Go~^ + sUU?2$]^;5HTK[]=F1KZBJCopqwx + 2TD[WRx>@Hc"lXJ>MHCWmzRvVr2DvPJw!nUR_#?n>53^'?QC^{1ZIZBLVGIIzm$Bwx>@wzjjJs2' + Z*a3px?ZRo1n}IVR{v-7jPvw~kT.Yj + 7Y$pZ;[AIU5D-_1!TTw>'U'l@,J->\W+kG;$pfzJuR,Y-$Un5e;-VRYwETpDl1Z<^-'#$79vZV,5$1Wb*eElmj~jE#5Aje^mn+~ssXV + Bp2n*jXR_e6_G\-RtzZ7=u^R5]7W>N#a{W^U$?vXG!nnnuV[*~G_lzRV${v?7llB>'ea-mXO\ + R2$O@l,eRQ{m}wV7*^5V\;pvZ@Wo=sH5sV}Z-WKYk]DB#{^X'mIDGT}T,*yeKJr*171%=JYuC + =}x-TZnp;,+|EfkQ'Be-e]iXa[zx^QI}VCXvo=Iz!'Nm'i>l_$wB2YUjX}BJs7'-(E4$\-3*Jp3O + QQu^zIJNv#@*x^Ix1Hz!$x[@wls~Yxm'um~5_5QtqgVjHo8I?W{2vr^EBkrH[H+&mm#RR[nT{3]'W-s$j{] + 'GBu$OO2+K'oZ!v\vQ?mTvY#z-YQBU*^!l?[KV5z},ai_@=gn{'o5v@@xW21iYr'eGW]T=dQ*kER + 3!Z^'3@=X*RmIwAdrQ@O$vBkj*;{wRu#[BJ2w[i3[a,3pQV2m + Z1-]}?A2Gz'x#n,>VJGU[C{}]OIA+*|#1kG~UG[1^-J;p7v:av}5aXmIlZW_KIG^{X~$aB1s2O^s + %QY$iQ@[X{TX@RNpvI7'#o@_!-@EO?}5OKr%*DTuFcr,o^_Jxr1<7#=axT{IRa*X;!u}DZj_mIPR + r@^K[U7'zz[TtZ]DBw_U'E*QOispxPuCIJ@vnSF7[G~|1u}m(,O~$*)_'QT1E~szp*u\^AHq>=r+ + ^C#+oG<3EQ*E=^oj>-Qo%mUCO}T*O?z}oA{-pflu=vDKo-z%OC1xeDv3_ZweI~D@,O3[|,^] + #Thk_m;QvmU=!'lu^*#Ek\ua$3CDT[UCI7e} + umTEw{WIvnJ>B$[WOR>Xz1kQ@Ge*2T71I+oxku,HHaCk7'a]3}pko''m>$C;@KfZ7}JNY}1+wR<2 + #1K]BkH_?AxDa51$zR+Ul_V}Ip\5;p$VeW2ZN@oXXoTHjK7me~Q!?{ + n$gTxoVp+rJQ5Ce35{=\pp>'mKE{7AU{C,7;U]*{R$Hr$snQwo#a\~rns]lDBZ+5Ew}@nw-6jx?x + l1j}zW3D3zCwG]OPzI]CZZlBeB=G!{cA77\J + [z;JoI5@OXQ-}2Y@sm2xR?+g4OwD7?=;R=>^1r>T,exVpx-*;_w=;}}H}V7u:r73_Xz>D3joiuoEYY~ + Wa.\z;{Hj_Gf[!Z]/I#>Z!+Kar**p*eeRe*'YIUpGs;{2TlGZH7]^#HT2?C5-t'V>n?IRnmTwH+$ + *K}E+nA*a}6oz\Q{D-O3}joE~B$IHl7HOK2-VrEs7i}#-XAKkpa2nD? + AC_;6/"RVX]e\7U1jv2GuMbABAVDWu2wG?[#G3Key04=nTWaT,\:VIm2_QX$}J>PXe]_K>r!I@*_[=Z<,*Yap>sp}k} + EBT\i'aV+pmU1ul[Yj!J-kvv=o1KYI%o7{@rN-'X;Eo1K_k>O,]}{0*ZAQ;l^}xs57My;aCVHW7s#naO,7USNa + -m;QZr#e5oBQ2o[jO!5?GoY'$BY'1j~vKZQLN9nRiWB}Xjv51wfmH\a_Ri>}kW{6Is7eH1W=J57~ + 2sTHKo@_S<]$?YiO{u_1l1HG{J'i1EMFzTTO$71\c~swj}D#UYV]B_IK$s\]aQ\+@'k=TDG$?aK,DJ1]+k=*n~j!GIzR=jz1}=%XA\JC]U5-}JRwGX1V$#X2^Vnz~eG^+op@[Hm;}^BGTVK~EVCC + zVE,>x!{=~,}o^3;|a*~VVli^O$Dim>VK^E}=>[lI|C{+#Kwuz=vKTr;jpU5!\evaVh/]p{nX=+* + \ + R'fE!W^i+7*}O{,2=U7ziJVQ;+]oO+UWYI\7ev*)HBxGN#'\^J}i~R-W{z_v3#rT + ="x-mp7aua#>*UlRz5on~}8wvI~-smuG>VsfBUK}[,]}*KCu([z'pQr{=fCj+Oe~7kZV2B}$T]Hw + x\a>lkIRrCo}a?T1H}pp2V]25Co\eOjj*5]S]+D[hp2r + mUC+x5+s]]uAR)ekZ5@7'~VT{^UvW3WRIT*DJlj;~'^wsw=J^^QZ]Yz$+Qo{vv#Yl#}Y}[H][kOO + R7v3u=D5jxFj+WJ!]OTom{\;Eo;z}}A,m\_=3{;$~WHWo7@~w<*'W1K5}iDEBx@},VD=HTeBr?5r + *vuiTWr\Ov$<[]#as_n7XA5'CzCIR-#AV$;[CIj=KODD@hLVv;TH1#;se^^uj\ouHj~5]QE<7Ae)+}][/eiH[1e@;=3_e!hF6pkpp3Twl]\? + _ppp1a'k}#UG3r;~*TOYEA=iG)F[_;u>x{uKV@\Rsls+pCGO;R*-VE>*+?Q^xaw]zUnv_C3I=7GY+iC]vF@]xU-CW{iXHY_'aUiDrCIko[ + ]_QV[rEO1E?DD$[{en3<,WaQ~A8}2'K}lI^Q,?BYnuwx-*r8 + #'E*xPoZg!aY!>YuBg{pkl5{nLsr,UvVe{?AlJHp + {sJ5iCVsDECIJ?I1V2Njo*i[j5u6{jDm=o>atVVX=aRe{'3,]?Vl}LI3@kD=OYpXW{|;$1\D7#r~ + QGZQ2apiQDs-p-QkEx1O[WrR^~58aoGDU$~T!^$u8#xCkHv+$qa=?B<1UZBzv+Q5_'?1]r1G+r\_ + <{OvOYqYJnW[j]Dw=5;ul?vxIYBvx5W2p@Qv|Bm5' + ?=w'7sl*,CB\Wjv{[WGVCH;C7I;p%~s@V1OZH[?wKVDu7Nu}slwIp#^=W\[!nv3,A@fEH{CL+XR~ + \DOzDE*]QVC~$+xswpg~*G1e$>G'vK;jHls(#1[\v#l{Pfewu<#TW\cvj[o6MPK[5EEa-E}WQzUX + ZoCs!'!o*uO}!,e7Y$U-\C-rl@DeEs.CnmBtxJH3~x5nv7O=$I<+wRAZ0Y5Y_B+Hj%4+{lBqr+X% + v}jC~Oiu[EY}GCpX)c7s+kI7spsTvn7lG,3TyYW^u*m_JIpa-HQ#o3Bsuv_\+_7}T=s-n>Q;U,IG!|E_nOx?*up}v_COTI[@'!mjD!'\uHveI + 57C~uo5-!{nCwTG8AR?@U,pUWUXI$s{7EZ$pK5VEa=Zv_Oz{;zZodVvn[kxuneZWY>e##eT!$wj{ + RvOe1@I7]1~lrKGspZEXQIHlY6z_}mr-@R_TJY14O<-eE{+Hh*1RER;x\;2-Q$I0^}Wr/lYe'8OOn;i-!akBoOw7U$d8'Jp7^>-^P[GY~viJDaYAw + -]*YI3_3_^3Dl*JWf[P3V^}zuu~^uashxwl#Ks]as+aAKT=I^e]>U<@o6_HTw+V}$LGO|_JwUtfl + xwpJ{~o1QI_ZsDxv%#=oWLA<=E3R!U3Y]{xY!$lKavXV!Xlom_@vQDL,75il>VI}5i<7Y\eG]AC7 + 1sWxa_k\*GDA=KjuI\E)<^VE25r3_n;Q_>eZ*'[I@a+On*KKCE>IDa'=xlI~]Eor;+rQU*2=Rl]7 + k$DpB\IUy'IVW3qC_?cWVQOwEi~_v[1ZpVD:w5KG{DZ7-Yi@ + ^U_xpA,{CeR,dTIo[UO<3z>pX(U]}Gz6zrE$ArpBUU;T1k!JBsr,LUG$Ws}7,OxWZ,aJe>'x;#l5 + Yaxx@#[1UG2Q5kC7iapJoG?,lcrv'@wH{-rLZs+1#]z1*U~[eOvIw,YWsVBXaxQmQ3}~}nc|iGeCLTA>e~Tm + ]v?CZC}^k@D77*KI-aGKH[bpk;$5EQpLvVD;w\x{A>V*>Hl5Wl?aO2]weeA,R:-nTQQJ=!YXzE7@ + ;>}X\zGpv2lD73[2*BHU!3.=@OUwE+zXY{#b[Z\3ruoC7*X]^*\uC]\W7-nlG=@1zJjs*kzn-a2E + VC*r,s[7Hs3vx>'$PZU}JxxG#R<,jF^x+7;Im}AsAZ5\3Zo$1DJrH@>=kre[+?a'}er!{-OwTZjn + C1D#z5)kapj4G!T'mBA!peToKU-ss'$[v_;u^@~ER:hfZ_$opK$sMpI*V1eAl**jKY+Gj"];_AYe + BCr[XQT>7aI2vvx{*<}+!-_o]B@$XlAiRX*)1X1;V;w2v*v*CiX<;BI;-ABz=?V7rC5i}j'+~wA@;l-,;=B + uqGrQ]&$oCn;ka>BQi@'VrI>r72<*~,$:l1\r2VT$TsCV}+Wx + $om#[Q2jYzouKVW3I,#HoG]Tu[p@nvIrf^AzTs5*{Ol#ex\_uxKG]Y[X[rYV/A*Dz#-lXMz^A?7s + Wu@&Y{}s;xoEEp@5WrEkw+Z*}JQ]KY'U{H5C$\zKmw@~x3]mnQl}@_CpsexW6_2rX[AK]irE_U7<~TD3,ix}oa+sielp\IU$uX}WD3Ez*j-KV+TE!LDpC{eZ=-Vz + [U'C${$nB?=$wW*zaTGK7;D[wK@}p;@7IXz^v?Ur'OGXOe{-s}2rRj+lDx[QA7]+m[]wAE{VG--s + 5u,r*v,E^7T7Al_BaDIRp3#1|np1u?,v7f|eri*B<;kTX1rspXRPi(mSs_u*=;**$vu'$_Wu#Q{o + em@=s3G3Q3\,2Eu1Sk+=mK7Uw-Q[EOTeVA[_eW}vAzCV3DU'Q + enDerjmplSH=u@m[Bkb05uj@NHYU,>+Km+1KE1CY{0[=}Ibiv^iQACioz<-{a+T=3,JG3^u]e}oE + p#DZ]zJwwAx[[ls*7HD3]Bn_HQz$rks^j\1TOj!v7xsvZnT1vuurUBpcsB_l@<7AZ^Z{KsO*iGr, + -}{=ej~['m]8o)xv;KLr@B[p{JeirC#[QA}qGv}!oH!e:Ox$IDbjs'pN~^kJ]-W~vsEH^k\EQT!2 + ,aBIV{7?$K_$7^E{}TlziRE=F$xm@T\OrkEQAT5O+$YCK#1Za9H\jz\_2T?w-vY;xuCae3Wj2^?q + "]l}ple?ZAnBBu,n7o~u;w,~a/UIYY;Cl]-vWC]2!mrp5=UsxRnBH7}]?$AHJ-eEk>YCi!wI+nDo + ~15z=w@z?5VUxRXY2kBp;oT'2r}7VJ>YXnWnEl[oDl*2E]WVOrGQ>X35-E?{JJB{*Y,o3D$B=+U$ + WVvo3E)ceEe[p_?QNS3DVocYunz+{H?XE;R_n'mc,O,C}iE9xul7NvC;$Ed}mCs,t^,w}u^ + -Y}B$TB'wZl{vrBRx}T$l-!e}U>TCC$=+$s5[1>*2,Zvv>WwJaRaX@;OT!W_<Z=Gp,u\W'E_AjRs<3]B'=$U=wiAD^"RK + @kUuY-^@XE'e-rE}*cH_'#E**kvKAeH-zeC2<\VB\Jjsa^~l!-fP/-*>sW}xQxnsTTIu,sO<@AC<$\_mkx5+IixX^uCe,5[rR2w*l@DGm + ]W2WiO[m\_wDkvJ$aj{{@1J11-->^$Wo_^#*]~J*_3aGC=3p>r*oaaVpBA~r%B3EmAvl3ZR~TIUXr<'~x!nw=CwKv}Gm;<[QsD]KoxiV^u;wkV~3JxG$=B! + @+*U+@TEI#=lVpCU#CVX>o;[EOe!Hnj!\Droao@ev_xQwBAJluY\,a'jn\A>5KvD{@rK2zeZ;_VZnsjjCe]no*A}- + Te+T.i7V}[ZIxQo[HE>VvO>}XNls-?r-3smOx[?!QUQri=j!TQ'\Xu{ + '!nxlx#_e{}sT*\R#Eb-TCV,WCe#eUmq+'jpDpu>=D-Vj5m-R1TaKXJ1^-5{uVm^Z[x!_2sz!e]? + *k3@+I\wk+Cj'!XlW7r71G-o#T1nXsvr3us,'MUT_poS57o]YZZpo-CY6uxvO*Gn@IJo!3xCrTV#5xuZO, + R[\Q'RHRB$YX[^Gq^\~\>-Djko?C[1jjf1U[QGbUjwJYsO>,}3nn>^*Xo_na-Y~7VI'R=~VBvr#[ + E,!=pA}wZT\HBWv=kIVo^IDkk,KoRHT-aHzp;>~zxo$\vZ;OUO-zQ-5}I2onTI}eB + -^*}$p=&]e$\*2{Qn]m]Wlr_~5BX^Iw*=^eCYrR^{si~h$-Hxo5{~\-C3-DTsx*vBJkA56"3[}kZrjHWwm]^Ze3oI$3QtVaDp]eB;^Z[2[eA<7pa3|VzzDlmo-$K + HmV>QpervnpXGVpo{2V5jHwT>{Oe5>Hj2DU{xsQVeU7jDw^kAJ3>_-wIn=qE2VWI{+;[R$uiRZO> + p}p~VK2l3K^;w]p2CJ-:7b'\asgE@Q!7EAxZr@]R2;}.lBRe=>+,Q~=r$p^jd'G?u[n]'lr5m\2T + -AnAm52aT#Qp!{YVrG3m_AGBW]BK=*wHEXCrrG$_$5menkC=Vr\CTDa@pYB^_7IXrBwXE2oUw@G^ + }5-_>,OTn>'!D\{~YB>u_\ICmxCmroUX;vvv}?Qk0Ho'VH1-p],[7MQk + wrz?$*BD\U7Z1]ojXTXjvBCv@>s}?e3'z{xp!?]VBe:9u=Y^|Cz$@kXA'=TXv;n'-:=2u1QD'n=> + CQaT-I($;33es#G*IO$D;KQRB}DwT>mw=Djz<@}[@-}Cvxp'e{<*5e5,jv3E3-Us>QQ[mr5:7m5a + IK];~NQ\mpT_7IBzzwnxU{gw_B-pn7;B~vm!OUQ + @=!BP{$rGF?'+_Eer_>Xu!=o{^3kI]_nRW<@A,~}v[wW,?[UU[1>d]Tx + 1~_J$_or\G>=$yP}RV2l?'rdAY;{@D2owII}><1p]K*e|$D7k2rHDZR^^9Hpu]G>ROnxpIEjT@D^ + BsB5{ZSoxa1x#=#]$]kmI-?GXT,i+lr3^k}#AoG]CH5~U>o3r{O<-Ja+B_I:vr$raw~#i,uKzU-> + +^[3&lD=x+\7@jfVn7TmaE?#aDUoR\I72v$@sNvJ*]K51Rn[ARE?TR?Y~5 + U}ettrO]YxnQrV1C*c"^le]U=}Q*$=+N^Q_uBYe2bYY>on{o{U1Y>jIv]Gw*C?$neKs]]DG<}ojm + 1]>BDq^#jx=R?;Qi]?&DuXlCBQ5Bv]JE$Q1?vGWv@TeV$}<$$j>$m + rBHUein+R\'=O\=[;j7ElKxBX\vC=JEDzziKa5!lO3Ad1u\\YvA]p<{[!HWZv;pq1D^pp{I7oIXj + z7wDj\w=)tas33F'!z,,V=GxW,R>-=}$;1l5;+ZkUEIRmmUJ*m@0epkmC?lxex{@[eJ*Q~<*{YTm + w'H~4@z!]V1mADmTQ7{[\Q@B*lxCpkUA!5s=ED!m7+vm2+_X,,R}WmV{JJ[JXV{{KBw7^"a7d,j> + 32R$v0~=Y]5nKQIv{!Gn@pn^;2J'<-k}kT7=!Qe@V<' + @$O1mvpOV#~^u]7D}zr+aX+,[*2>YzO}rmNBm;}WCov*2aTQ?m11msw-Ts5V\WKx0OaV[fYu\?\? + ^GK\;Q6=^)kQD~SexTuW{p'rp$Two + ^n5-Tu,om;V'm='!sE<{=oQx=zAA{,m}{'Z-xmIACKuBk!j[uo-O'@rJ\rQpA]T#wRe)9x@o@}^oJlaRK__\^*JOAQ7GHLhGJ1Al1^#n}-Y\mK}s@O + TI6,]$Yo-oD=u${}Xuxjk}rlO-U!']$VX_]ARQ=^e'i(QUTz$m*Z'!^Er + jTT5GT[]6Yw!7$VErYyjeWxRv^Ww{\~]5K1C$>EDarj2$@$Zz{[j< + 3Z'ozu}!UZNs~X]wQ}GMvT+;R*\k2HUG\-;*=sx]lv}],~=~II#-^eB+T. + X[[^^wp-^o2w+jC~3seY9\Qj!Q\o-W=e!p!*xCp;<{XQGP',wTzjTOr'\*QJr-EBiQU=5_BQ$iDu + G-NAC;1/7pGiKnsv'OjG]xD?wrUz--11+TXXx};KrqKIOoO3Du=O-7gizXX=5onm6vj~ + z^#RY_lW{Qv$pzk5\=?A~x'7vHw$_s?X>FsCosMZ]i!B[wQZ7!RIW'OTwl?WjUDIOm+$RpO9^iU@ + TX3u-+WR*+},Ck=sG?\{-wse~q}B1o[>eo^5{Vl@2x>,A<,H]lvz,I_?^w_vC]}Yo}e+Rks41rx@ + OQk=xBim{[<^r#5'@*Y^as11m$2ZHovKhJ=^$Ivrp1ku373<3l]V?JEm'RYJX#5-D~s#AxvpBBZw + *OD@[Fa={!TXB=Qa5*D$CD~ + O}U,H]YCEJTjI{1Q?jYo#CRY[~2x$Hv]xrsmJxQ}o=}a*va3o2vulAW[_5?E]w\^np[v_z> + V_T_~AVJDi1R#,GCC\XE?Z53klvK_kXjVeZ7;$o[vQ*!-L\7pE]CTwY,$'\IWWZEJwOHH>xUj,y& + Bl+H{>Hv@oDVtR#]zZ\xu]zi-H[^RRJ*Hn>Xrp#'pZO#nkQ~Ey]B$$Ob.@*]\J\K{Z,aRi';n]#l + 2gKsXU1F]G3uSZ7YXaUBsW[VV5$~Z=CKYzR[=Q\Z+l>o!r$I]}mj{}WU'1@@k-7W}^i_\n<Yma'^Uv}{Bi*&q?ppBbI+5=-BSqv%6 + +V>'GXJ-lC1_|lHVmZxl^]{u}R;*]]\VKWI7D~C-p4[VQe,,XGIK+xI2_,5rmzXo;T7u>[N=lJ55 + i{rCGQ3*V7;xEr<]H~_D]E[=s;D>{slR~+VQ#n$p+OJ^C$iksV?11a{.TI, + ~W}?CY:O3;@?o$\5va}JjY$n={^[xrQKIzplX*RHT2O71]epC;lXQOoQTue{+T2'HH}Rp$$GBi4\^YB$mxlwCHHxnp + D~al7~O;7OAva2ax5[CC35XO-zAvm!,>mjX'T}}5mJ*lY'5{?a'!pv-Vn8315ui]W~}iz[CwHIJ> + Ip'BIJ|2n_;[$Yp4du-n5'OKrO*R=^<*EjjTJC?>$WxK]xGnY;O]^EI[,B]==G,?wl?O'.e+E1?e + skDGvrerBToaw>nxl;A_Zs=UnOu+_z>\3Xp~'*E7EHmV*j2EIQ,_}$'NWB#^lkE@2=A]BI-5\IQX + OTI?+nY7fDoew&,NI1X-mrAsB|EWB*'$1H,MSZ5XDV_HUi(zRkp.y;HsCIDw=5_"aDA]#eHDm>zV + X]7G3ri7wC^}n$K[{51l!_uEkH3B9C$$}B{BusJ-k[]Yo;n~FeTB>GXG}G5}'1U + x{^JQU1RTraOo>'?=C~]AIe^_1X_{m}Qu{e]]OK$?>1Ho*U7Y]R{>AVa{*R+{-CHVuavp,;+}see + u@XrvpM]2Bz\Om}~T1TT=V@E{K]=p7]}5G\$]p10Q*la]o#o5;zX^,skJpi[r{@lQ\axxi~Rs-w/ + KDI1G}BDKzRm~[u#2.DwK;OD;O:x,mm,2rWw_EjU^Gl9a]v#B@s-aV\I?p2~iRKu~pXYYR*_lk2D + ['wu(>v_TR~RHBUzpv3_G?[}Y5=R>U\@HR5UQv6?HB5?rsTUXz3kwOE<=QnnT{lQGHa+CsB_2_'O + -DI5T^'by1HuHDX\TWHo]k-ei3lQ{TjI#rD=v%xp_2!Q$?Vp3Vpn + 'wG3e'-5]-AR#{TVR\@TAArj1VYETo^ItOOV#i + @{xr+[c",J\RC-j>*J7m7Za;60|'iHEw^u\*HnXrzl!T\$X$pXe>{Xo5 + kAw$JlVx[Dp#I+H+sG@o!Fn\$2l}7AU1;O_3x;~1nCr!aaVzawl{OG@_o + l0BEQv=UUC$;7lYZ;Kk-n2WC+2{5Bk*EnWYu5_=H= + e=;XoC?1?H}mGo_XC2*5Jl?U@\vllQKCD[zB@5I4"5TY*!vVk'JZjwz]Qb + [AG--1!edu.=O1[v^>HD;Xe@^a~U=kB1nVRk]j1uR7&},;$>x1>5u!nzmx;v!1iVZr2IK*CG$]^GOV?1l]CQskI1X{A[#}~[G~tGEoRJC$i$*p=^+XHVX|^a3{;o}BHTUW\w{m + B$}QWnJ+jr31^?j[S#aew,>>owO{#+U>Bhn=xDw\2am]}<(!X[';es'<'n[R[AV\@*7\>5$D]#Ha + sG2*X4IvKY=G7i5}IKwXHuVs@+2z7H1!lDRJ*#-joW?Ez?WjR\D>;^.]2uI!Aw?/'ZKTi}3ule[^ + #E#jIX_;_rA#?n**"5j+siIQ\Vx@x52+@a=3K7XK{QIOW_x>m81{IApI+2$a5!Q_OKQ}D+vs=#:;_*HWTW_m}@Ie\O;\<*]k-,Z#C{?D^u^\O>pKTR=l}XwXRnv*IQZYx>T[{rI>\?Qz++*;qjY=w1rH7_j$'pv[2~{C\wa@'c#'n*$*~v4{_w!osT}IUxUrxImw-T+BD@[u=]$G^'Kq@1-x${{>pOKI~Hn#+<1X[BiW + B3@jxl<}^Ea^K}**};+o0$vr7YaS>5lx_b^*E\?xi}CK'OQA~[D;AQB;!*_}XU[7!}#\kTux]I1E + v~H5Q!WR^_3?pe?oxwnIs@Y=wz + Bl!GYVT>Q2I*_yDC}V-H$An$K31JQ+G2*}A=p+e^;2~r^~lb5}x}3QaWJTmJVj-#?Iol~,#nTvYv + pm^kVWAVBu'1?\+Elk{w5;OrlOvI-w*~-*Ja,5ao]2}>Ra3?Bs*{nEzeNl,jQl\B~Wo@oZ,v + xa,#ZeYApC?vRx?=n5J6Mx{epDsnljW@?x[VwpRr-6=kGsBKARa5VDIS\AVaq\\Gw'j,?c{'v;'v + J{y?r~T2Rx{w=z$O?AO1w}RkYI]]W21s@D5vW{x6=WaH{,>[m<,iQkUl;Q!HO?1CTv@?21T]vY=T + e^Gm2zpCK+3D%[#\^YzVwOxe*Qo$pL,_^*oE5Dn]nmI_uQ=zU>o[@3{ + R#+x\aBZ!^u=#,<{Kl2*$^#*q^H[u$imZ^}CVh1ApB[^*v+ojJ[B + JUh=@=ppIXe;ViY2E,}m>w$[zpmaO3AkOT5rziX#As$/BaG'&[,z@x;BCCQlAgU7j2w(Jokmi{D7 + $kaWvFkRwkz*pzlGDwl7rvjZKvs|sSR=OoXpaA%5U+_/!Q,~'X{ZBG#??sVE'hjVipX{B5G{!OMn + 7+5$?GI7o+26^Uun$3XRIY5Dp=mw[Auo7}k?VCG*]Vj}fj+jOBK_C_Jne\X2TV>wZ*{2Jw\kEL6, + l[]-,m{qr;OUQK-pn\[ig:-,I{e11',o{la'Z_3sEj|6onjI_Ts#Y^@_uKIrx?eaTC + UD?Y~\i~s2$7a[Y'zwp{I>x[e;TAVw7aX*}-,!H1Y-HJY[;jKiRGl^G\[bNXwa#pCzZx1irGrm'~3@[Q2{V\HH*QrrV+xrriI2v#Z?=B^\Qn!lI2UYZG~G,{CoQwHm$1@[VDJB~a~Si-=$Hza7TwR3[rVaG3YI\wX51v*s?jm + mAGJ+e*QQ]WzQ]'uA9X[BJ@7n-Ej,xV3l!eo7s]}kQji\Z1Xsiwx?TjVe;{^+l*s#s/H+3\^Xr,] + U[oE=a<@O<3T_*+C3($1I=q\wmKBI}XGz@,fc!Gz>lH7]_u*[IJsAr+xO1!p-VZo,s~7kP\xA+k\xu5,U1i^_BV~Ya7+CkVi-YI!>xa,+_xw~3F<*2J + xHBx5uR75]$vUO,$z~nzBv#p~wQ5OH}j4.s!Cw.DZ$iQ=DJ3]@\[OC@GQWa]r{} + QXnIoH;ue'#,vTKIjoXjKCI1*n}jIE>RQXE2R[Z5$m@=OHHQI$j727]\Yp2X;oTAQm,}IV!*l}}{Vl>lzZrT]C@R2DYRwWCO|Hzrr,S}n37!UG#eKCp-C\l_,pOW + [C+OY>B=~jL1{}a\nnZ + -{KCrW_=AR!,CX$@{>Wzq],*Q}5]Zl;zeslJY5YB;v;xD^<0>U;B{]pW!x2H1*j{s1{\>\@3!7r' + D[Xls55EgG+X7aH_snr[W5*T{uAmBN=YpUo>2#\_kl3KpSo;'wrpBzwva*+GY*x9q^BDvu$\[G>~Wmar*35WXwx\i} + }^$W_wk@I7Tjz]p,I<_)oaGVzK>A+l5{ua+R{e~oAEe7=DG3K]7E\=_zK7<$nH2*D^z]H]?,moao + WGA1W''$'D=Rv{OE-Qk*#>sK#Rw54C_@r-IEBQUw@TIU;+OHxV]k#sY2z?CA*THm+|#$ + v$.fXYY>]WH^]]Z!}D'>Q[zls!^\[Yv-[RXBv[OQ=IIa<}WV? + v2K*^HYC^E{Zv;mVkOpKD#XDHn2+.3jIBU=Z\]{]~ir2VK[]wv+Re:8-B#]r+\9*Rlj4,_$~'XWXjlwzu*vuXH,vDo\w{THVQJ~H_{KsCC7YLfRHXo,$5vCk,*x}Um\*Q}pU(HziW}\+sRIIzW]s+FHT1x*w^rV*537 + nZG.Xee7jGl3L,0^#,mQV[eO^l]=REk7IIlI*2{hmlmwaB\U-'XaT>2QCvkxCm,AQ7TJApZX;I]O + N$PZTUZk'kp_B7GKCe-lWVsi1v3R!*2;RC+xX*;}^zD${EezLF_3QH=?{~}^oRnOQz'>\m2>2x*1VuaHjv${loC>Z#ctyK1r3}8mDllHI>52z}Y?;[z-'OBRYO!A<1\ + 3^<'_A>apnH7!H}p597Z[14x>\{ppu\6wHp}V}[w]\Ql2VRJ[Dk=\Z@QQmAn'RAm*=z?\}zU/AYO + nG>o7]!1@\H_A*jAT:uvv]pw'-~}=]r5GAYIes,E{~^A=[[#K}{j^Bw\=OYYYpQ;7R"r\AI?+=~'l5J^?_?-^Qv~5}C_G + ]I[5zrE?DAs+Ykk[\'i#'Dsu[QX[8DXZRnD_Io*$3Zorny$-ZoTa^AI' + Q'j*1j*~3OxS?UrO>$7;X^]mG.s#jun$D=QW~?b[}T#IYizH5\{Q*HVsA + 1[?1viOv@>awwx\xXx$JoU5}5'_-1_*oZgWvBJ@IuDZH[@[3R>'Kv~i_B+kxz7lr#m!55TY?aX]z + Umk_p{!a$wDnC@!IuGxklXkvo#oo-Q_rwTlTYaGCT-QD2+-z5]5az\Z,a,{+ZVzl3#*2za\]oa7!r_s}K3VUlu,UW + AjX~j7sxpJ^Oo}xR[+N3[_vmQi5oXo^rp_{s~ReaX\7Crv,7l + {;eHVVwa-a_Z,^-Gol?*pRVI7#D@]'a+p5~57wBlADDK + {]Bu=O!z7TJeFWoRCs>[@L6j\AWEu>wFMHnA-YW!#A}Wn~e$*_K1e,wHw9]Y\ + ;OQ$vhlOB;K12CUYrR$#Hzsv]IP8CHlJ)A{l''$ + VJ]Rkppl,Guhf;jJY<&~ejix'v1.D>uWXO2rZ[z~m7+>rTX~W<5^o?Qus2!OsJIU~vnU]]<>lA5; + >_jJ\A}H'1ir7 + Q1)w^^,S{=;kqx!HW+a@H#Co$ArjV4#AzC}Ye3U*w^^3ZJ7<*@C_uW\rik2+Vx1+w7Qks@-w1u0} + ZB]ueew?+mO*<5o>]'u01Ou\eH>]@=KW2CJ2;\aC[mGI\@D*q2xsZ,5X{ne;mPo{3?]QRjWTJBNx + ]A-7j#j^pr[X^^Ja?s<=lvD#xl+_BDCxYGCoR2\<>8OHVG-wjlo,H~7j+^ + 5EA1JAoRpQpU+lwWYBO@rBrY7uuGBnTdKDz_k.x2DG3UE!W + vvD#]TIY*72+wWEWrr[UsaoMdHwK#BGK=1^{vk5sp:*[~-t7A}+KpXzT}V5En,'T*+2HAjoZ[I\Q + aJ!lXju5>^Z^upHoI#BX^}5$XpROm[vUGU#{K?~BYTx*CUYbrkxjYr@\rF(~T=#]V}T7p$3 + 5zWldVB5k{GmOV?17'n*TkR+klU{DH>w0n1_{{H=]}-O7e\IYoUpH*[i[l~*7|"]I_D,,_<+HWr_e+[o3;s]eUmAY2r$_2* + {[nkl2uX>YT}aap<+1$'Q,AmOoXA31,['>KjG"]ZlWLw7BW=HDj=V#mi7iuf$JZorn}G?n\[$*<@ + lNwavZq31lPlF+Up'i7z~5r}[CA{}c^3wVrowUsGUm7@p!-wl>W'5R=n}QO?CGK1v3EwIZ:oHjV' + p71*B}J|,V'XZzeTHwnk_'--+x-rG'EW1sUoGOr#*jmJB;[B%HXE$IlkJ2l~UUDn]KAA]l^_XREW='7e<+O)L1mp;#5K*GD> + 5{r?l^@2Ol#zr$-BAs$VAJV1p#r]vQDanuV,rs3rs}QEmA$5@al5,7HH[?pG-ok}>EBCs2XjGn>j775+H5*'kouVT\Y~@K-J~Q}-Hosx1H^QvTDiJV$Bp*pD[Cau[r?{zIE1i$#w_5 + iaBopZ^-nmne_-W5-U~i}o7nDp=Q?ZnYjrkc+BXEliu'$eW\BJsT3-1R]dBsoZ1nARKV-Z&OQYvZ + }{{'1C_Y2VWqnll^vf'GQIi$KT{on,zKCw=K2nCpKsZ=?$hh[ZB3}iQ<,WxnnOrpJoAsjU=mr>Q\ + 7oXDg!r+z3H+lB2'7s}EC."LpKmX$+B2v<]}XzXzn][xk++CkHoni+'zW7{EGpkIp*XR3O!l_-]TV7\$p#E>EKepjIplUwKVkwnvWp[mx]Tu + CVCa9}->p7z>XZGrwxsT?~^Z!}jea|)Xs{@\VK'--_\HrJC)1tp3Hp>{YV1KneKp\Tuvjr'D!u\x + {2'BA3-jU}E2xCiX--#,xiw{+>ex++!xA>!Q=xG;_GjC3Im'mYK,72\TrvKKms7GTSGmp7'WoZTsD?$O7v>I~~*3]Qz=j5 + >jeK#G*aYU5HkpR}J=sHmvTnXxOGl}*o[}^vh2VCVr@,~X^<7\_#;ne;jb\a,r(vY5=rWOzD{Q{E + spZT$7r#$W'-Y->vk=I<}i7<*D@%l[C{GCCr[@ + UPhj{{;'XUI2}jx,-{!]l?O~ORlVH!,G\CKrzVjI3EEZw2}TR$7C[m*_-V1_:I|eEwJOO^*TG + w7^v-#i>=OYDd.C~Jpx5TB!*nC!>3mjEwO]eOsX\UkvQ^-e4orZEj_]BQ$WDIl1EQ;1uD{OE>-C[ + ,Q=CX_+~ve;lsx^kx7TvSwnjYfjKC^RZmRr^xW{C\pxVn~5Vs7\Q;HJx^is'$m^A_WdsizGS7/EK + J{${A7E'X[e3!E2[CH|7,*js}%U*ZKlrVI +`endprotected +//pragma protect end + + +//pragma protect +//pragma protect begin +`protected + + MTI!#+\zz)pJZCom3KB}nA,E+*WIJ]7'Wap[6&wa1[yTQ2a%o1WQ!+E#1^_J|dD,H$}>xzG3RU+a + $QQ$k[sZz%lwJ#*+[[o_n=['CW!Ul$HUlIH-BAIz#^^BU7B!$#m|2|yE@}E=&BF;,!H<}?Tr#C'7 + A<@io#ult6/*O7BlW=k72]s]{E[v{G@$:7*-3TCC+wNQ*$Chem2v'>[nH+<=ux@nB[Kn{B@$J#HJnY3pUp@j-Ia^^&'\]\Aa;p]5Kw*5~^VQ1o1_5$Iko\=kaT\ + !S'=1ETs^UkxA,,7AAXG]-]^2Al_-CXv2lZ7'?AQTp~n21-aV+7GU;5+{Hw5oiW$!7*GD<_]ZC'luB&Iaw3(_N[yZ[i2=vHT12eVG'WRTE+~\vG + KKT>n<_A7Wp2+H_;v49o{I{Wv1j1d;7R" + }>AOm}$o}uR>I{lUX}zi=Aoo*K,rsT=?H_]W_X1'es~nu1i + Ywa+pI5IHGW\j<}EUJ>ra?2_KR,[A^I2~pl\s@L'rkw}x]*5raz"2p]ZCka]^HWnQ,\i*{R_GXY= + *rn1K{^!\k__-VWB\}]}{}v^{YX!7Zekl*XOz[R[os@$,!s1l{l3#Or3o}#s;w\\DaUKE]VGWXRZ + 1mY]x3T'}\Jw64owx{#E,,GIl[#j}{/@\O@^1oo\?u^BIiJnY!DZ~7B#(f#>z@r?s\*c+EY^MRA,e-1xu{==GU + 5#7Ur'QVVw{7>-jwp{7#oU7waj]H\DG2I,#I_E*[Y7i*-VnE$Ip|>]T2=R>3m$RYoooQDTXREi^J}B?A'lHRDumO*>,uU35D]\J-G]{x>sjI + ~plQ+r@aLG>XXEs]ipz$>C+BosX*Ax++{sT\5&p3;awGW<1532aU\X\G]C]?pU>s#KX[D + ~GaGv$7?jkH_mpI\JHnenOQRka\o?]7QXQIr[~p=YZKlNJNC>#aAlT{ppIW27N^ueO<=rnuDD} + 3$-[J^]s\al\TxrTJz$;]$}c+.r!+=\zIX?pjl_!vpdsQ7@ + !5X'Z'Ozx]+osDx5r<'rI$C#i^jvuRuC"3HCR>>U_0''oY^:rA~>=1XGpov{Bm$VA,v0{Ue+og5UJ-JD'<1>Q!IX1i6m|x_z?E#X>dR~CK + AS4xYZnB>OV +`endprotected +//pragma protect end + + +//pragma protect +//pragma protect begin +`protected + + MTI!#kRR!xmEuACR?ao\X_Ikz;Qs-^2;?Df^$#!wa1["*wUw>$5sr\2YT}aap<+1$'Q,AmOoXA31,['>Kjrl1D_$x]T7TAj'_s1+G?a{}uf^M'C~a!U+7BYX1R + ZW$RmlVG=*QnxV'kE_XpOE<9aE<+Y~A~7R+$Vv^j?'ZRD\*3O_iXO=vW=x],szQVVpZjzTRxRW@Q + [{Bl"~'R~EH*uuUY^<[Oa1.@+[?ZI?VWn[pEC#]2l=lA'U1}5!Z$sp'S[TVkBWO\I]}se~KAC + Y*U(oWpCH2'BlKD/l_\!6jII@l;AK7;Q7at!D7D-SEA{WjTT1N.1x-Ze>HEi_l + T=re_@aCs+CoTV_npjmS'lXE2r2v51P5[GwE?wJ=$k}zYBoV#vK'm$n?]?3roZlk=B7!UB=Kv}2yEF?'O?WTIew'QG+}-lG}S_VTp\gp_n?'-zu#n#X^!vk7O*Y}GBeZC^$mXz+lE\e'mRJVQT/eV2^lGxm3+\=\JIDO'Ar[5%$;>p!X^pYC2zL.?]o + \s^n~5[}iT'An3l-YH${^"2xK@#<;1\k-kdN3{;,5[X?&{[EwpH@E5\z'BsOs-5Xwv]2uKEv~3>1 + Cnn7ss\?}\ep],J{D$rx}eBQ]Qn2?}7ZHjUW0a}EaxK{_YZOm^HQ*{aUHjxZlI@IKl!XuR~+ + w3BsvaoWk$[#A2'QvUrYZur{HiH;'VVJD_OR3sAQ7rz3+;lmehWaZUx1w{\<*a9bU90#RoR,WuC~ + {Jrxow_j]JGiUoo+'ieX,IDQA7wBw*vzU1+$D~}!oT[~sK!-+[>oj-$L-zU}V[Axu\Olv'j}yJR# + *LkG-;,I+aTXKV][Jr?'!vO~Eir*1pJJHu'rsx=X?@]*;/4JzBB7QY#Aw3nYwDKJrW5EDU_B-zUXa*dC7VsWCKXzC5kE>Oekzaj1,@$2IoHQM@YvC[}pUzoF3nAGO1Vw + E?1!?T]UOWz]X,TkG+1pB\[7v5QzoUX=,2DUu_-{Hv]kc~>KG&GU7D^G!CxVXY]eHYIAUrQvXlxj + s3zDQ=pT,pHG* + xs?Rrm~I!W=x~OQ7eA}A\#pzs=s#1'~irz-YY^iBzU=&;7Xpp@zIKaR$37jHTT5#@[EzY\oGW$<#7 + ZxKC3K@2e-vXa-RQWBrEuYH'Tl!BCJK$^V[s[nTLk$;lP#]*Ov;D>7sv!]GH7PpW]u(KpDw7Ej,N + 3wlR^MC[2;[Ov!BQppjYE?j3W7k}inQ-VCO{mRX']+7~1'2r0y^O + Vmw>uvbx@+!AO_+)-=<{7f>nU5!{CpQzB_Na}7152B*>eA,*D'H#YwWMmA{7M{]>s3oG[<,5\n>z + Gn_}RGUo!e5VZj$u$yfm|x\!Gp,n@k[OIv@7#E7B7!UJmT-uu=C,YCDlv;qR{7?,_#VlkW}]pDiv + IQpm7iUZG1rsE]ulpvU+=- + pe'XwAavZje-,?Gxp$_RpzvXR!a5{}oC@Tn]1xr + m_K;m}n'+YUnmQ0yQ~}D\GVu],7*\KZXB?W^%*vZ@'3jH+RARR^YDV + DE?XXIj#*X>%y!+HBl-r]7U;=2DW*Uv#@U_nvaY,e6a,mEz/IXr7ao+BaGkQH=rl^\EVao{5\j@-$;R2@&A<7r[+1 + Bg+Gom~n^ZDo[O@xQeqr$-'!Y;jv+1JX&[s$wJE]z_W^AnHD@KD}Gv?YJ$sx-jR7dieEGuB[2vuB + ;?D;OVDg25Xu{.[_e_-[YmE@5IJJRCkT77MsWDJp,.']*1 + =C^CCemT@OsJ9Eisx^*Es:N|WCeKrzW>.C\Jnp2>7~5'}E~UJIGA'X7[E2}_-JDk\E<,aHpQve!_oAQX=]rB5\;zG-emjZ,QA1>^CUQi$k@u-vZ1unneJJIT[7B-= + ,Dx-GYzTRa=EAv!vEn+'kDA}~C3DAuK + }>!GH{Cl@O!U\as$|5.&>=i7ja{E,O?QC3]^roE5{<1D8l]RwO$wK]uApx]^H}5@'UL~{Z#EQX<' + ~UlHBY]>E,z$+nEI7]wll3Tk{BAITOW;v_[]3O'JS}Ewo)!_CoI7ZvI{u'WI[1RYR--1*i=~osTv?$ikMe,m+o=QjjVV + ?WlQj?,+7\J11wx_Q;1V!WBo{#*=oW[R$b7unjQ{~e={m;bG^TWvU,kOpI7o2C]t+z~JUo5E4'GD + xABCr:5lTH^7X'ITo\meDlgH^Uv0QC!s]Cv^1XE513J!S[>+WoXDnIQ~Qmr]1e]u3w[_5&]1}~oX + @!=QViZ]2EYi'X5slxp[wr|oZ1nXzDXZw*eMl+uE4I^k2ur[OO@=Ru5x]uU-ms1kYk<~QwaO_nXK + e#>rHr;InvHn\Kvuaz\oTio-1!+U!r^@<--|JRru;*o#{xT\JDjj\EAE3*a7j5ClH>CRp*VT72ap + VV1#DzGJ3EAK2U+,$D++]*T>[J*XC=zAIzMm,B'vlpECpRDk]?*is7{]5]uCGYRX5YJGo@*Q#I]> + ]XQ_a!;=s?YLBhk,nDrY;WVAz=5[n5O^{YC[RCH*!Q(Kn+$CoQevoI,owC=WA[J3Y]!OU<>^xo>u + v?oE_~:-^ + $_NoWCg7TrQT]sUWvRnx>Cm+'5231WD^7'7!s3wEBHv>Xe*~lelD_V^!zv3m[A$1pT;Wo}7/QVI# + }!E@w13v@Bk$p!$OYAv5^rBiH+KW*I[x"^{51RHZ>A+znR\>l=e*Em1U}s;]lYTJZr + K*]s,DOJDz}I^wWj2!m'vC?ok'/J1rx~j_J2[=SRu2eJp!>uj@Wk>m!)[27$%oZ}$%eXVR1ssJCm;J[I'K$]kr'5rxD + U*#GM3Vr_Zl$K/sAG~'eY^H\-s8iOiE\w>;]Z'C{,s;C~]sADBj|QE]j+GOJ!o2IQ^wKVaXGl7O! + WX_EBr*jV+r@'2l$<\Wx+DeXEo+w#BW~n_KA]U<1s,^o\GupRs=zA,GXe0M5CTuW1Z^@}k~e#,E$ + KZ\,Yk_IJ_Vr_v+;{~7r5Cj5*u2\>jik=x1e*!UI,a}Z}{m8I5lke\DCZ+[ + [r}<@\Q*3:'i{,P\V[VBWl]{ej!UG+emAU#m>ZafEDkow + <5WN}rC,K5oxU! + s@a1[iI1=|\VAC6(O2\#PD!aC,;OCIL+}z{}z_;IY[[9t5RKH+zsVnw{oXDI}5{D[6QB3El3\T^0 + 5,o-q=v5'x3,Cvz~=pmrVEolZ5w[@,jr-GGViLp\WOBEGU}^7s1*7@zHQ_is_I#]~2coU\Te]p!C + *T]J=+[rqk1!pe]Ho$sDz\jQsKv}OGj+ec(_a7Z=G>o{-WG^l>I_X_Cse#aoZ]xat*Jv?J'TY;_H + Q}n^<,~m37k~DB,$n.#vp*FnUTRH-C#_~]wo+1B'#1~z,X>RKnx1CvQ + hL;$=*|2<3ED?z~7Uw]B#ew$_~$>Q#W9ERTE{z;3_KX_jQ'e.[={!]+]=k{>sJ$Oog\p?urWI<'3 + Q\$Y<^7_[lCD7wBQTz^<>uu>=#*YEwXI$?p[x;DiIZx#*EWlo;_}nU(jNqqmRH*>pHTa[lUciX,, + R!XWKRB$ZTXpJ77eoKo'#U2!JH*&sJ5V5_Uws@ + W*bjO1-&eXQ7=+jkIk>IUwK2Gv5J=O>z#?[+@opD@V3j]_FkQauJ^+l-$O3$X1#_1w + $]@Emv3RT$YI'e*?7}JU#m$JJ_pmkI;oO-\?3^mA;>TW2<'XOkY+eG)p~X7\11,};;H^E!Q$'Ei$ + GDkCx\7iU=C}Q-;#IA~uaVEHCr7xi{ZJAI@Ha[$iDZ}un;_v@Yv5!Wn@\,vmAEYrD}=::wV1@z-Q + +1$<@Ew<7@U$$zC;j-=Er{Y=R3O>*;QR\5p?Ek}T$JVvI#'RRoRkoRue3\AR@'-oZ&rEpvwzjuY> + AQm^seBrG7B_H>o1~Ew^x3--'ZWUeZoKx+s}+_KYR\_Qwv7GwCaE*wcV#;A{>>k<{JR.3>+rC@A, + 4yEC+TY'[Q|-E[#8lw]*hF3AnB/ura]*'}+eK\u@l}pGK=-*m^xr]k]]DuAT-]OwG+u^_k=QDr+l + z7@_s@=n_$DKY+[%'aVY}j$]V'L];Ip1H,Tw]'Q%%'}j=i5$UzOEpV?zuD*a@|@o+UmH[$~5DDh=oU@~1*n,AGDOZ2C]]kGlkD{*Gu! + -aa2V0$HmVa\~,K=oU31]n#s+v]*$'[Dx\#lo>3N[7kDU]oOp2G;.s?}eKTGl#_C2@'=sCE{GZVz + ;/\z[VBkZ7L'a^!W\'@jp_s[wBrBAauI[O2\@]v2'@wkEA5$Q;5!TL~n!kt\ipXS)\S\jp=&O#]1]+OOIu + j'1j?=~-WU)-njn?CCon5B-}^Rjr~7z}EIv]QV_*sXjExEHWA7A;YQO7!Y#j\O#aVr]MTAnsdi^\ + Qj$lOv7WO~\^lw-CuR7*JIpjOaU{azGl,jRQ{)#sl5G;m];[n!R3>$B~wQmVDiU+}Kae!+Fl+}E> + 'T}p=7B^j-!}~~ItTOm!.iE@xupG]z$k15TsmW$mpYO~#6ww=VTC}l^lE\I,WGi^oH%13^{Z#ER^x3D3k\1XGVTGW-^oe?[AzUonO!z#5UC}~GEvzYl + J2K(zqmzXpG2UBvWT2?}^xIk=ojDe7IHEWp3[KKvV?B^2~\ZrrJu-xZ_OHYEi'W*CIQ,iaXvjv[KV&CG@}*z?}x^#KG$Vv + ;roVy+Iw?5uJrjv\xz'[#3D1;Px~A]K^mrtHnrs!H!DbZn,!LRr'rj{Hw9v9E}\_(ODCjXR_@2R' + [4>ozW2=!z[V{wsu!n1}w~wI@RQ@RYVIUEq1auG9k>pY}3_>'pV*UBuJ={BO@9C?,*4hus+JjzEr + w=^o0[Bl{?[vl^GkGpH{^Kw{>zze!x_Plzk?HjCOa,'pm-T3Q]I2UGu\{rx + Uj$H@^rlDj]aJIwe_O'X!#YC!#V}#UaC@!A@o)*{Yk}kUCE7ZI@DGuKpk}l=oum_oB=vie*C\7EVWn;vAT,3p-]z#nWVUuxlzZ]$,Cr=p;Rxz5!^OlY3l + }Jn6M-]AIlKw-D2r*UA*Eu,^j~xT\J[TaXpC_!$B{esCJ=WVXYKla\#mDa;R'e~2$D#VA!ZqrTxr:owQ3]![xrD^enmVr~uxgHE@+Rwv'YVnEx($;G2r]{IT>vJ=A~Bp + )@+]Yp_n>@p@{^-=Gv}u]>\25KVxBKRoa![Qp_Xl!;s + }pu_m-}-G_uBmyoI[ex<}wIaA]LrB^=T\,r/jY!'=AGlHx~]Jwm^8RPu+!AlKW/z^$1pT\{r>\5R + u-WH^K!R$DAsDpvSr4V<~D#w\a#x;,RR$*x4G{ti_,'J,H1Ur}=O!]JOBAHx<+>zGEV"XYsi1#H> + ,7'_C!!r^Y~;@T5[E>Kjk('#TuDzE!3xEDzBnX_EJ,zv{TvwQ$OQ+T@^TwQ5I~V^5l\"$elXWNzE$Q=Qp,A[=V$2YW-oZv=r + >R5}Z2>7xJX+'>;ji,_B;BR7,sT-_pI~QpRuuu{\\nRinnomxpz*TY:+1-u-HTD#l_+-\OmnxlrI + n}ixTT?]Ymu1AAJlJR+rB-WOV<*52K{=lC_xr,*\>YI7BaDJs~uO[3r^O7VaEn\eW_;3*7n,SE<> + 3|GY1H'[s+_}Y>Rm@*e;rl#'z_oTEpsV3+>CICeIoi*]X@ZXD[>'!UrT_mk],l@[7Y=m5-RUU*I$ + zosse_O-JoAo?leJmWNw-\eRi\k,EC^mQ'Yv3+sJv3nj + C5CKIUmIBK^I'wRUNR+jkQKp#Rlp5&c(HBmWG}j+-VY*C}A^o}$W={HgxWg;QwEJR><2l+5 + ^O+og:V{=j7m\r@UVi1?>X*AlpznAQo>XkwIOjC@;+e57\D+nH]*pepCX^ZG~!ZvWR2]C$Ye]]$p + ]3r;-@pw~1RuRC5V~zv>VXZ}OZAn>$3[sY5IY@7D^nUz,WCRCZvk[azl1{3xexJC,1oEI=Wx]\1= + v'"paaTH5;uzbjK1EGwpEm7 +`endprotected +//pragma protect end + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_top) # ( + parameter FAMILY = "TRION", // New Param + parameter SYNC_CLK = 0, + parameter BYPASS_RESET_SYNC = 0, // New Param + parameter SYNC_STAGE = 2, // New Param + parameter MODE = "STANDARD", + parameter DEPTH = 512, // Reverted (Equivalent to WDATA_DEPTH) + parameter DATA_WIDTH = 32, // Reverted (Equivalent to WDATA_WIDTH) + parameter PIPELINE_REG = 1, // Reverted (By default is ON) + parameter OPTIONAL_FLAGS = 1, // Reverted + parameter OUTPUT_REG = 0, + parameter PROGRAMMABLE_FULL = "STATIC_DUAL", // Set to "NONE" if not require this feature + parameter PROG_FULL_ASSERT = 27, + parameter PROG_FULL_NEGATE = 23, + parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature + parameter PROG_EMPTY_ASSERT = 5, + parameter PROG_EMPTY_NEGATE = 7, + parameter ALMOST_FLAG = OPTIONAL_FLAGS, + parameter HANDSHAKE_FLAG = OPTIONAL_FLAGS, + parameter ASYM_WIDTH_RATIO = 4, + parameter WADDR_WIDTH = depth2width(DEPTH), + parameter RDATA_WIDTH = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH), + parameter RD_DEPTH = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH), + parameter RADDR_WIDTH = depth2width(RD_DEPTH), + parameter ENDIANESS = 0, + parameter OVERFLOW_PROTECT = 1, + parameter UNDERFLOW_PROTECT = 1, + parameter RAM_STYLE = "block_ram" + +)( + input wire a_rst_i, + input wire a_wr_rst_i, + input wire a_rd_rst_i, + input wire clk_i, + input wire wr_clk_i, + input wire rd_clk_i, + input wire wr_en_i, + input wire rd_en_i, + input wire [DATA_WIDTH-1:0] wdata, + output wire almost_full_o, + output wire prog_full_o, + output wire full_o, + output wire overflow_o, + output wire wr_ack_o, + output wire [WADDR_WIDTH :0] datacount_o, + output wire [WADDR_WIDTH :0] wr_datacount_o, + output wire empty_o, + output wire almost_empty_o, + output wire prog_empty_o, + output wire underflow_o, + output wire rd_valid_o, + output wire [RDATA_WIDTH-1:0] rdata, + output wire [RADDR_WIDTH :0] rd_datacount_o, + output wire rst_busy +); + +localparam WR_DEPTH = DEPTH; +localparam WDATA_WIDTH = DATA_WIDTH; +localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH) ? 1 : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH*8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32; + +wire wr_rst_int; +wire rd_rst_int; +wire wr_en_int; +wire rd_en_int; +wire [WADDR_WIDTH-1:0] waddr; +wire [RADDR_WIDTH-1:0] raddr; +wire wr_clk_int; +wire rd_clk_int; +wire [WADDR_WIDTH :0] wr_datacount_int; +wire [RADDR_WIDTH :0] rd_datacount_int; + +generate + if (ASYM_WIDTH_RATIO == 4) begin + if (SYNC_CLK) begin + assign wr_clk_int = clk_i; + assign rd_clk_int = clk_i; + assign datacount_o = wr_datacount_int; + assign wr_datacount_o = {(WADDR_WIDTH+1){1'b0}}; + assign rd_datacount_o = {(RADDR_WIDTH+1){1'b0}}; + end + else begin + assign wr_clk_int = wr_clk_i; + assign rd_clk_int = rd_clk_i; + assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; + assign wr_datacount_o = wr_datacount_int; + assign rd_datacount_o = rd_datacount_int; + end + end + else begin + assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; + assign wr_datacount_o = wr_datacount_int; + assign rd_datacount_o = rd_datacount_int; + if (SYNC_CLK) begin + assign wr_clk_int = clk_i; + assign rd_clk_int = clk_i; + end + else begin + assign wr_clk_int = wr_clk_i; + assign rd_clk_int = rd_clk_i; + end + end + + if (!SYNC_CLK) begin + //(* async_reg = "true" *) reg [1:0] wr_rst; + //(* async_reg = "true" *) reg [1:0] rd_rst; + // + //always @ (posedge wr_clk_int or posedge a_rst_i) begin + // if (a_rst_i) + // wr_rst <= 2'b11; + // else + // wr_rst <= {wr_rst[0],1'b0}; + //end + // + //always @ (posedge rd_clk_int or posedge a_rst_i) begin + // if (a_rst_i) + // rd_rst <= 2'b11; + // else + // rd_rst <= {rd_rst[0],1'b0}; + //end + + + if (BYPASS_RESET_SYNC) begin + assign wr_rst_int = a_wr_rst_i; + assign rd_rst_int = a_rd_rst_i; + assign rst_busy = 1'b0; + end + else begin + `IP_MODULE_NAME(efx_resetsync) #( + .ACTIVE_LOW (0) + ) efx_resetsync_wr_rst ( + .clk (wr_clk_int), + .reset (a_rst_i), + .d_o (wr_rst_int) + ); + + `IP_MODULE_NAME(efx_resetsync) #( + .ACTIVE_LOW (0) + ) efx_resetsync_rd_rst ( + .clk (rd_clk_int), + .reset (a_rst_i), + .d_o (rd_rst_int) + ); + assign rst_busy = wr_rst_int | rd_rst_int; + end + + end + else begin + //(* async_reg = "true" *) reg [1:0] a_rst; + // + //always @ (posedge clk_i or posedge a_rst_i) begin + // if (a_rst_i) + // a_rst <= 2'b11; + // else + // a_rst <= {a_rst[0],1'b0}; + //end + wire a_rst; + + `IP_MODULE_NAME(efx_resetsync) #( + .ACTIVE_LOW (0) + ) efx_resetsync_a_rst ( + .clk (clk_i), + .reset (a_rst_i), + .d_o (a_rst) + ); + + if (BYPASS_RESET_SYNC) begin + assign wr_rst_int = a_rst_i; + assign rd_rst_int = a_rst_i; + assign rst_busy = 1'b0; + end + else begin + assign wr_rst_int = a_rst; + assign rd_rst_int = a_rst; + assign rst_busy = wr_rst_int | rd_rst_int; + end + end +endgenerate + +`IP_MODULE_NAME(efx_fifo_ram) # ( + .FAMILY (FAMILY), + .WR_DEPTH (WR_DEPTH), + .RD_DEPTH (RD_DEPTH), + .WDATA_WIDTH (WDATA_WIDTH), + .RDATA_WIDTH (RDATA_WIDTH), + .WADDR_WIDTH (WADDR_WIDTH), + .RADDR_WIDTH (RADDR_WIDTH), + .OUTPUT_REG (OUTPUT_REG), + .RAM_MUX_RATIO (RAM_MUX_RATIO), + .ENDIANESS (ENDIANESS), + .RAM_STYLE (RAM_STYLE) +) xefx_fifo_ram ( + .wdata (wdata), + .waddr (waddr), + .raddr (raddr), + .we (wr_en_int), + .re (rd_en_int), + .wclk (wr_clk_int), + .rclk (rd_clk_int), + .rdata (rdata) +); + +`IP_MODULE_NAME(efx_fifo_ctl) # ( + .SYNC_CLK (SYNC_CLK), + .SYNC_STAGE (SYNC_STAGE), + .MODE (MODE), + .WR_DEPTH (WR_DEPTH), + .WADDR_WIDTH (WADDR_WIDTH), + .RADDR_WIDTH (RADDR_WIDTH), + .ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), + .RAM_MUX_RATIO (RAM_MUX_RATIO), + .PIPELINE_REG (PIPELINE_REG), + .ALMOST_FLAG (ALMOST_FLAG), + .PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), + .PROG_FULL_ASSERT (PROG_FULL_ASSERT), + .PROG_FULL_NEGATE (PROG_FULL_NEGATE), + .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), + .PROG_EMPTY_ASSERT (PROG_EMPTY_ASSERT), + .PROG_EMPTY_NEGATE (PROG_EMPTY_NEGATE), + .OUTPUT_REG (OUTPUT_REG), + .HANDSHAKE_FLAG (HANDSHAKE_FLAG), + .OVERFLOW_PROTECT (OVERFLOW_PROTECT), + .UNDERFLOW_PROTECT (UNDERFLOW_PROTECT) +) xefx_fifo_ctl ( + .wr_rst (wr_rst_int), + .rd_rst (rd_rst_int), + .wclk (wr_clk_int), + .rclk (rd_clk_int), + .we (wr_en_i), + .re (rd_en_i), + .wr_full (full_o), + .wr_ack (wr_ack_o), + .rd_empty (empty_o), + .wr_almost_full (almost_full_o), + .rd_almost_empty (almost_empty_o), + .wr_prog_full (prog_full_o), + .rd_prog_empty (prog_empty_o), + .wr_en_int (wr_en_int), + .rd_en_int (rd_en_int), + .waddr (waddr), + .raddr (raddr), + .wr_datacount (wr_datacount_int), + .rd_datacount (rd_datacount_int), + .rd_vld (rd_valid_o), + .wr_overflow (overflow_o), + .rd_underflow (underflow_o) +); + +function integer depth2width; +input [31:0] depth; +begin : fnDepth2Width + if (depth > 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian + parameter RAM_STYLE = "block_ram" +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + always @ (posedge wclk) begin + for (i=0; i 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_resetsync) #( + parameter ASYNC_STAGE = 2, + parameter ACTIVE_LOW = 1 +) ( + input wire clk, + input wire reset, + output wire d_o +); + + +generate + if (ACTIVE_LOW == 1) begin: active_low + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (1), + .RST_VALUE (0) + ) efx_resetsync_active_low ( + .clk (clk), + .reset_n (reset), + .d_i (1'b1), + .d_o (d_o) + ); + end + else begin: active_high + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (0), + .RST_VALUE (1) + ) efx_resetsync_active_high ( + .clk (clk), + .reset_n (reset), + .d_i (1'b0), + .d_o (d_o) + ); + end +endgenerate + +endmodule + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_asyncreg) #( + parameter ASYNC_STAGE = 2, + parameter WIDTH = 4, + parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset + parameter RST_VALUE = 0, + parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance +) ( + input wire clk, + input wire reset_n, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + + + + + + + + + + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect author = "author-a" , author_info = "author-a-details" +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V +o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE +El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY +kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc +/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 +uYJaS5tuGEuFInBHa7oO8g== +`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 +fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa +rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq +PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL +DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w +K3OoKmk3zFeArSsql8B4/Q== +`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 ) +`pragma protect key_block +RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M +GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l +6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI= +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf +RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk +1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw +Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz +eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0 +2HflB1HYKxojQCcZU7qUgQ== +`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx +Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB +rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr +XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD +e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod +B2Zpo2FQ//YDRSAaEa9ksQ== +`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze +vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 +ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 +06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP +fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN +ZoPzFCMjGk5ZmMyIlytNCw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 ) +`pragma protect data_block +0d33xo/2RnBYy8BD6jq1J42m9u/75PA0owNvxlnr0TDOq7sF8XT6xouctVD1XQW2 +Ylwj0urY+dCJZku0aGRpcvb3H/nTlKVdEZOEl4QqB1gNGz/3mz75A3eudu5zgHEr +MaagjyQfDnoIqLWi1r5uTZrlS298IvNcGAJ+xXzpmkFmfG4Tk/5Jf2GPAPVtjREI +01kt8Go4CL1WNxBKcwm0xCiCchxvZ2oEtpERiC+7LUalgTJapIVoLFpvFv98229k +egvgF1KHNj0rAKedSG2Xo58TyA4iZXJJDdtgCxiKgu3Rimjno7l+ekApwmvx8n+p +yHkRGqetWfRhyE4A5q03RzOeSdA6NbCqijB3NPw/p58brAbA35rrjYpGIZXtZ4mU +De3As8VtD64nS2PRuf4/a2lIcDbwMjNTfMpN7iJfVBJ0/48tLHdetx592TLXenkF +GvAZ2yxoyBYzKctj4Keo+19Xp1UjVd3fr2MR3A7nmxLRKDA+upDxQ7ql8+pR7Moh +0b53/4Ri3Mkl+7EC1KXJNt2VbkZmcT7OAFIoPpibmcXS2R6DNVrhSKzfc2+TRM9r +mwRrJy9/R5RR+WGfw1S57Ho3wBPf4belj+Tfd7yhnwOVRXkTMq5M1BiigrGeeQ3q +z/hc1Kg8b/R+g7lnU0pqASnExPQW/DIMfH1RX75U68CAgaBAH22Vcbkoibp8sxyO +g18LefEh48UffnbpCKyv7SQ3LAdj+YO+KvvXHj1eW+CH7GA2lC5vt2be5Ah2/13H +bCeZ+srG6r7wmafy9MNNh8AgjUfZWwMnuJdCIcHTOfAncCd2B0T1Oza4VIkvnSl5 +60V34JXkfrGsNuHxwCF/sRSBbZUSpqig4ZGYHjOHldx2OANZQeUvLES3fwScYY5D +7SpR4ofVxIB/ev/+RXzvC3MNk1N0GT4F1XwokeeQIr/ilRETe/pFvEKttvviZ7uJ +uEVblS2v61DMXEgDavkbA0WdhMChPulwDvZtisWT4hCKRxfuBvNBtz0wH/WgRoX3 +aipWvPJG3G0xvO0u0EQVNdcxE+LZ7vyGF5HWEwKdQYDyhH+yVDeG+M/b08dU2aq4 +sG7dyygyVnzVbk2Lf0nCkGqKkUZUr05Zim0Wcflkhkqy348SOZ3xmEGuYAkzelLV +feQ+0ScsscFL5Cq4ETfFrN8GO8M5kkBN2ELs1MQecPRsgMCh0hcvd8IQrJTybQPW +aqwp9mgnFvS8AJ1ct+XgrAt8zgVnhaZGS9TKa6OWbr0U+SD5m+/pXjNsZA2dni6b +85/PmQeWeAarE/+EaJn/hlP6y3x3R3ItU8Itf6SB50LZ17LAhIRSIYsa7LBBNWOk +ngFHcGBCJnqTJv3hdVqa9cYipZ98XCa8dqrtAM5Rkxwd6H8KxXA+B+PWEz/cQWlb +szi9u5ufmyaJp6PWhklroQkPJEorUtF96X763itgtlAMHfkZglkElUD/gPlkXLtl +yquUmHqPK5D2pJDq0Q0jromE2yrr9fl3OI+eBehd2YBUivGKeaDFkPx7HbzWp9ok +9bT55H8VKYyF1awcjNND+WcXzm2WfvZHBDUJkRm7dnOQRvcX2RxlPRZSzAA3irVn +GFbHXD0RYn/dUR7Vy4kU68P5S5q4bUxD5vmUCN9vDoCivY7WCnlQCHQs3+iFblzP +A636C3dNQMSw0pjDisiZB63VczY8bivFh3cO82inNw5r2IZjvMB9XPhc4FHuIpfR +F7ptW0TUnO1MSDcZvCnjUfVSnHN22l2FM/P5oI1SbG3W+8YmxBvto8jwpES4ohOQ +YSECrvWkLklq68FVTzB7Tvg3JLdSy3TEKBuZE/ot0w/SXusFovOwd4aeiNDAmzwl +fQuCYHuJ0UKLaVNVAO4mw91PJODKCk2NYTr0ghOLovOXiMhUYtXZ+wFchXVkQKDI +B8BXjM7P+blhoOFA6AhRuCX4gZn0dP6m99qnyBJoxf1/FyfJXuklnPll93amUYUx +MzxNNTf7F08tnKQ8pTOk2mfFZnhA2MFn4XQ9FaGvtUrlJI8bvJTWiZFMF0eOJdIw +kzYOXEzKBjIdWW4rtTZmQJb7AOrznUpYdgTAPip/DQx6cg1+tZAVwhZPCjCsb5wa +em5hMtISQKDc92QrlU5O74OXe7641fzFRcKqy9AzwhZl+tmHk1uvpDkpsYiMa7Rk +YrbIjsKQV36PTqYPvxq1EiwYF8PMRf9FG8JZk85EZdM6QEGuehDHqFcZ+SlUb7/e +ji6GgjKxcZwaRREGKSOslcscHS6QNuGCF3iInqNCT4V2l7nboWOefMT2f1kmQOdE +szTFg563SQ8pu7ok3T3XNqUDi5ulvF+XGHDhcQ2hTkZ+xQ8dHFAWZdgzEGMXF2Lw +jU+ZRA2JULfjxOMIU2j9f+aGWmFx2PELMA5K5uOWYUQG2Fn04p1D6u8MEe7fIPeI +k7KH8j/Tumj+kG4t/lCrme6VM9u6A2NGddX1yH1NCejfophy3UWJg9wL/dNxzf6t +vXdm3rGPdZPWFgSIuGlmT03QZmWGPbs8qvkkUVAL37kMJP2r4L+PI00ZxbX8V5jp +GgYN1Rh+NSOwAcUEFCViRhFYC+Gi5eZ6AF6XDSU6qfjGsUKqJ9yrNx0Km6+SjpAK +7Zxblp7vweFVkJ7IESoFeB+vP8JNeoidbBPGEWo+2V08PgfGgjPEAA6pjj8uc0jC +SDFZ0sVrzvc66PZ5FxbI4g+VuXPJgyJsnQ/eHhPVTVTP3/oGMRVktNiJrkJYxAW7 +Sa/EJMjfXX+rMIWG5ssWLT6WfrojlHduEqJ9hJr24RZy514HHF8SMPRBLD6l1wd5 +07U/ChjFdy5qHn5Ce+lanjxnoxgvCsF3lMqoZ7e2bfzXakj7CxahwqRt6yeU0Q+/ +a8tvIJgHfdtOPw/r6HnSrzpdWzTx2e6/MEryHZqpMN63Lhakpjw1L7u3FD/rW40b +LGajigQ7Ql+cZmP7wYl+uSmTFIS6ZgXOc1ibb7yYxJwpeixPHL1iu5ltvriRiTZ6 +DMbbOjNpPuL7ie3AwgmwXwnpnTL6k/Rj2+ma3B7ImODBMkC4SLtTc0ynCcPAFZKA +Xh78wUAgt1T5Nm4XR555DBO7zPHX9rZzMLil4/j0RMDwn1gitmP2PSNFWsrXJG8p +C46kfpdqoM3Yf6HySlhsith6GW41sMF6imUXwahQQRw240HLW3N876LDe6bjTmgN +eIC7y/4NZk7OmpmP8udAEH+UsNfSGtKA8959AoJDr43XsWkOfccNWstu4sTXA5+w +pCALypmBMdholEsrW9DgsIgbgf2pcOAC9+mAjld+yyQ+UNdKRbmtRDHTztGmcVvw +Szip4YUuTM1tPzReucfm38gVFT7eo1qFQg/FJ4VgeYab7ku5OHuwZQmKyzng/t0U +A1lquVENVYQEIotBiOC7jQ1YTkTasGN4xoFgFTyKLFPyk8bl2/anzr1Fx0ieVGCx +2ipzG2JzIQf/FlHXaYrgkWiF817amty+KZp4/dCJtvDXxzOZKnBTVcjHXpqR1Ik+ +tdV+k+21tXZxP0rkG0yi4//2c5UiWGb0UegpemqutykLuT9tGjsqMuc5DaDH/8zk +wLTVfODT+HqN1/ZLqfq9VoAF5m/ujnPNt3wZcsjsAyBD153rW4Q2yVYMat0sFQN6 +XbNAeNBJZlO/aE1PfKBcSDFkJkPqRxlgdiE5B83/w1MP6Z4qwz7LJ8yTYM22xwRo +LIYpKq52yYMhJm42YeQxbBRTx0MyubCb+ompEVBF28Eh0vE98UAZj7t1szSweg99 +Wq6/4kxR2SQj8rFo2wrZe7ngsDmbIrMk2SinS6WmV4Mj+MBbPlmiuwB6NUV04Id1 +9enBBsJIfWt+PZJXyWkOoG/fOVBUxCY+CMCiab0qQ1EVdhggrdI30BgFqcLjfyD6 +/h5AqIzMGWrhWnap8WDEh1Ah6K9f2oCESSXO751sV5eK8jgl63FJMIVsnjVejxrl +Qa7PCXP3BO6Cnv896NBzAsddPq/AYBLHIC6eX3sTtOxTx52NsmJzoyUSJcAoA/QS +leHU1bLA2z+HGfMrkSzsuvXafmqr3B+PHfWdxrYzTxmVhMBPX/FvEU/gfxXGa6kj +niZYGue/Rk+zXL65ENgPwxiz0mm7QyQ6eMBMRovm6MGyIl/8obkOPygH+lhc+bgR +SNWLmxqjR2YABrKsUgCITQ6GK7VmVR3wOOwbZs+YW/0Yj2yzg7ESjaeqI40/OQFD +Ft2IHaURJPk6jl5vRrcCc0J0GCy7CK0BU14n+Nxfl2+CFRe4efoqZry/CmY2+S4M +p9OqgjUzHGSIbNRAXHf44nIAUjWYvijzzLSj9A7WY3TpYxgtqU8Wbf7SbWmw8RJV +pAYDHGmwHa8fL4Y9xEFF/WqmqWSL3g146i41MKWKY7lchvnWtc6yOgk+0geVFOpe +9BLs4TehFA/SueFC99S0Cxcxc0KMWXOKm0I3bI1CAlLje7wUcdI/pki33iqBLJlL +T2vz8ptPqfgAxDW0ZEvEYY/jfB+jCO0MKT7XK/LZNYSuEke3Y3CeuwZ/5IWkDcwy +7BArmDy7Hpw88le9ODL94mS1fUB8jsBaazeiXniZPNZjBkugt/ZAf4XYuoaGVPAM +DnRd8GW5eiDHFCEB42lpg9n7Ak8cXsSSlODCHeay2VtcQP1DEgwWdI5XdXE879gI +8lLU9bH2MfsxI2mNWCMv5immaioZJDorIVzyMGvIn3OcgqmhTU1owINUJf+Hm8Q7 +JfJq4m6t0J5eoKQH57uSGFkWRZ3dtp5QL3d5bBOMmorXUBzdrLt8wurvNke29bHD +UQdmANjayV8drYWAccZdPWyi9jNC/K31BTDI6RCpZdV3Wr5scOZdXWrl961jirm1 +g/2MGKxriuH2F4MRIh2vp3uS8PLbj4cHJv+5+LtLgs0lpdEMYAvJKDACRg68tDhY +XsF9lhHpcF5+tANOawRtnSvy/rlLn+A3wi7v8tnTZcLkocJ51c+nK5/Ij0YgUrA0 +eLrKNlJM78stswPWkvpBlAJ+G3D4Cw6P3XcJWrLyV3u79jf9PRJZmxMU/COGTmgQ +PJdXp90O3u2Pjdwhp4VdtBK2d/jTpk59j8xbQBavf5flZ+PzoLpd8NSt6GdPVJ5r +uVWvNy14pJXUsn+Tgxj+9Wp3vm5mofWtJAkEgr/Rfp7AVLLShJSd6vsbT7F2+TS/ +OMDv0XH92v1G4tqJ0rbxS1TnxX61+1sfjKlfIQdFR9gxLy71Tb705LQHBAw8vmSx +X6Uv+HbtPaEqRCF+pdvGsLNI2Seo6INA/mXqNpd6VPhfQHtp3bgV+Hxnlcc9lCiI +bCZq6KG4a6sVQHIZ3pZo7PQtoAo22niHvgZFoOVnBv+bu+blmvSV6gxCPoV8rwOe +/WD7YikHE7WVSq1SHtTIcbPv+K+1NKqZIiSCS2qDfJLgI7vH4zjIqibDhzGZTeKV +Km234SSlJ1OL4WQ5FtsxjednjUIAKqVe1auDiTzAKY28dwUkwGN/XXQ+EjrmxQuL +qIAT3WP49EeM+CQCp3D6Vxzm7Picq+RtwtbAXnnSQtvPcaSprODI089a0iR46Pp/ +4DLMUOLS+01HozXF1589YdqYep05No/Fp4eP2RdQxicYxK8d/OcvG7E8F1URVmAa +XdZxVa9caM3xYMWDZaiaOo6IZ+YM5VeZ4KxUblS1L1IlOnGOOZ3AiaLsHOh55ryc +Ei7EaFpheCmlTJyxUg8TdA== +`pragma protect end_protected + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ctl) # ( + parameter SYNC_CLK = 1, + parameter SYNC_STAGE = 2, + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter ASYM_WIDTH_RATIO = 4, + parameter RAM_MUX_RATIO = 1, + parameter PIPELINE_REG = 1, + parameter ALMOST_FLAG = 1, + parameter PROGRAMMABLE_FULL = "NONE", + parameter PROG_FULL_ASSERT = 0, + parameter PROG_FULL_NEGATE = 0, + parameter PROGRAMMABLE_EMPTY = "NONE", + parameter PROG_EMPTY_ASSERT = 0, + parameter PROG_EMPTY_NEGATE = 0, + parameter OUTPUT_REG = 0, + parameter HANDSHAKE_FLAG = 1, + parameter OVERFLOW_PROTECT = 0, + parameter UNDERFLOW_PROTECT = 0 +)( + input wire wr_rst, + input wire rd_rst, + input wire wclk, + input wire rclk, + input wire we, + input wire re, + output wire wr_full, + output reg wr_ack, + output wire wr_almost_full, + output wire rd_empty, + output wire rd_almost_empty, + output wire wr_prog_full, + output wire rd_prog_empty, + output wire wr_en_int, + output wire rd_en_int, + output wire [WADDR_WIDTH-1:0] waddr, + output wire [RADDR_WIDTH-1:0] raddr, + output wire [WADDR_WIDTH:0] wr_datacount, + output wire [RADDR_WIDTH:0] rd_datacount, + output wire rd_vld, + output reg wr_overflow, + output reg rd_underflow +); + +reg [WADDR_WIDTH:0] waddr_cntr; +reg [WADDR_WIDTH:0] waddr_cntr_r; +reg [RADDR_WIDTH:0] raddr_cntr; +reg rd_valid; + +wire [WADDR_WIDTH:0] waddr_int; +wire [RADDR_WIDTH:0] raddr_int; +wire rd_empty_int; +wire [WADDR_WIDTH:0] wr_datacount_int; +wire [RADDR_WIDTH:0] rd_datacount_int; + +assign waddr = waddr_cntr[WADDR_WIDTH-1:0]; +// NIC +wire [RADDR_WIDTH:0] ram_raddr; +assign raddr = (MODE == "FWFT") ? ram_raddr[RADDR_WIDTH-1:0] : raddr_cntr[RADDR_WIDTH-1:0]; +//assign raddr = raddr_cntr[RADDR_WIDTH-1:0]; +//assign wr_en_int = we & ~wr_full; +assign wr_en_int = OVERFLOW_PROTECT ? we & ~wr_full : we; + +assign wr_datacount = wr_datacount_int; +assign rd_datacount = ASYM_WIDTH_RATIO == 4 && SYNC_CLK ? wr_datacount_int : rd_datacount_int; + + +generate + if (MODE == "FWFT") begin + // NIC + //assign rd_en_int = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int); + //assign rd_empty = rd_empty_fwft; + + assign rd_en_int = 1'b1; + //assign rd_empty = rd_empty_int; + + //always @ (posedge rclk or posedge rd_rst) begin + // if (rd_rst) begin + // init_set <= 1'b1; + // end + // else if (~init_set & rd_empty) begin + // init_set <= 1'b1; + // end + // else if (~rd_empty_int) begin + // init_set <= 1'b0; + // end + // else if (rd_empty) begin + // init_set <= 1'b1; + // end + //end + // NIC + //always @ (posedge rclk or posedge rd_rst) begin + // if (rd_rst) begin + // rd_empty_fwft <= 1'b1; + // end + // else if (rd_en_int) begin + // rd_empty_fwft <= 1'b0; + // end + // else if (re) begin + // rd_empty_fwft <= 1'b1; + // end + //end + + //if (FAMILY == "TRION") begin + if (OUTPUT_REG) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid <= 1'b0; + end + else begin + rd_valid <= ~rd_empty; + end + end + assign rd_vld = rd_valid; + end + else begin + assign rd_vld = ~rd_empty; + end + + assign rd_empty = rd_empty_int; + end + else begin + assign rd_en_int = UNDERFLOW_PROTECT ? re & ~rd_empty_int : re; + assign rd_empty = rd_empty_int; + + if (OUTPUT_REG) begin + reg rd_valid_r; + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid_r <= 'h0; + rd_valid <= 'h0; + end + else begin + {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int}; + end + end + assign rd_vld = rd_valid; + end + else begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid <= 'h0; + end + else begin + rd_valid <= rd_en_int; + end + end + assign rd_vld = rd_valid; + end + end + + if (ALMOST_FLAG) begin + assign wr_almost_full = wr_datacount >= WR_DEPTH-1; + assign rd_almost_empty = rd_datacount <= 'd1; + end + else begin + assign wr_almost_full = 1'b0; + assign rd_almost_empty = 1'b0; + end + + if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + // NIC + //wr_ack <= wr_en_int & ~wr_overflow; + wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; + end + end + end + + if (OVERFLOW_PROTECT) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else begin + wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; + end + end + end + + if (UNDERFLOW_PROTECT) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else begin + rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + // NIC + else if (ASYM_WIDTH_RATIO == 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - raddr_int; + assign rd_datacount_int = waddr_int - raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + // NIC + //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_r <= 'h0; + end + else begin + waddr_cntr_r <= waddr_cntr; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + end + // NIC + //else if (rd_en_int) begin + else begin + //raddr_cntr <= raddr_cntr + 1'b1; + //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); + raddr_cntr <= ram_raddr; + end +end +// NIC +assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); + + +generate + if (SYNC_CLK) begin : sync_clk + if (MODE == "FWFT") begin + assign waddr_int = waddr_cntr_r; + assign raddr_int = raddr_cntr; + end + else begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr; + end + end + else begin : async_clk + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idxUU*[oU1[5}Vus#!'AOTp_DVG;x=a + aIEzoCUHJG,X!B{}'Q>UjIGoQ7pp\vi1V3BR{djoH@BIC_~wK2}?H_&OZ+Y72BVoG!WU5*?G@_#XK=TGr\$iujV{mZ]_Zw+>A'Jo;oR!ao==Y>s?{AW]J$a$E]B#~7V + DZ2BBy5,\'lnr=ETQp[Qw=zEVaHCnJ@aDV*{_HSa*aowEA3B{nH|XDwWVi+ky*aXCYRsHKx+K/B{ + W@GO1][gE]Kuk}V_j^AzNuXn5!OA_IX+pTDs2'DHv5(6N>O_reTuJAOR + uG[!u1mVetiIY#@]YCm&*uWE]o+{]7kwy;7TQn+sii=}iQOn<1r3>-I?}rOVDZZ5* + Q,"[el+<'I_wR{{Z5?Qm>Tj!GKI4CYK=\1Hx_R^DQ_lT1GTOIXJuZCO!p_~[r3KIYR7oBwoUKs^R + D}<=1[r2x#D}-+pK_+1G7HxnJp^m-H1~2+e#OTgG-v#B?loId-7Re&'m_KY@}!<]3nBvW;~ti$A] + l?=\5<]al?js;eEVpp_EM?};uVqK5Z1.@5j_b$k_ps;M3Q]-qRzl_vo;C^i$\\?n+<{eks$2m_z< + UY}RTa]e=]K>,+Ej_Dsvxe=G]a>5EgX]#5XruH;T{U-d] + CmnDBBQoAu[!e[-BfQ!K + VG@G>#}a{iTpo[um21{;^b,IW1p}l5"\,{]V=<*W>Dkx?o'ZzXu;\;D~EV}[J_K!ClR*pKv|i$Sr + ^Aj1kwnYHjT$O-?_'BC,pp2Z5jlID#@s2l\2};UCz#@#zXx+>U;'o'7k,T#^5n!GuI22r{IkRkZ$ + =1W1Z>?x?l[eA^Wa[>~73Uuu[je-AKW\;\_ZzBAC_}R2'oY'};^YcQuHkHsx_58^#!Hx7NB7J_{} + {\vRwoR'GiYm\ouTlB'5w_\Q?uMrwAkc/!}n'~e{KRUR'?eHu**E=t=pWz$~-G_;HzpY<]|ajx{! + n~;QH5n?r3HBxV$kE-'8ul_7*#WRzn_A$G~w>A*jV[3EV;lOHH}Ax>K=[ToEH$*Jw''3BD5ClWI{ + >Er<{D]e]szvJapEM,1$u]k+OXQO!Bj~n1XV_eKs!K_rwX=xUB72ki*eUuVTOk1uEKnWI737-^mV + >rI2lXQG];xR+k{x3?r\5=m=n5p]i^[=AGoa7a=JwX_]AoJjRkOq&>p^XK'iT2{aun]?@_RG+B;m\vz}]$zUaB>Q-U^!xzlABY + \?sBY[\m@'['uU\pnoz~Os=7Vu1k\*~URG#+aVBx2\^l<'z>zj2 + OwCH$Ozpp-a6j,;@N5uran5=Z7'J^5Kr@Lb;Oi2QX[B@w}TEBT;rm;axU*!T{|JjJ}2TX}ozm@U]e}Tv5G;I}W1e9*! + YI?{IV>_~_/sw5It,XX@$l1{X_{{Bp1]P:>-GxZSGViTp?$~BB1+=7>CDv>o0WnD^X\{@o$>]oQ} + [Ymv^vo;~[;pV~Y7WCrPh1WV^PQD[>VH^mE>}l{sR3!zXJmI>jmr}QrDjB_s?pTnEX'~@VS + Q;JYmHX}zmWu''{WY{u7=-OUuxs{K5uW^'lCT{oIDYR'rBkRf<_rX+U$B7k7HBPnB-G\Bs;?<1$: + *ze3\OR,rs]]'vIW=O3!$u@C6ipQRl^mls#V$DO_'wT,#i1QDCoQHG=/pY?,kw+A[ + s7vr~>kU1}sbIIr\v1[?zlrU\KrApXAUUT~uEw,^$8yGwOI{j + BsCrs2-OURjeH,ejQDl5^@UO_?!H_}:l]WGDHe<[3*V!\*wnopl2V]K3D${o+z\e5Uze'=$Gzz~\ + aU5KU{QV2v^We{s]*e3K]Ak\K-;^,=$\T_,fEXe!]\un~O@3Vlp!1Ea#,HmUODs[#'zJ[$}UUzx- + GkXG]0kOiRTe2KTCe}Q_sEmje;\~}jQTAvKoiBclu\Yeevs+r{Xlm}QOre]q$lGk[^p/37{G7jI\ + ,'VV_xOHfI,@{sz2Y*K_w@Yw_+7B<^3}UY@=sv+rJVATl[xp*lRRHe<*Et1U7]K\~#9T7EB'\OTv + OAG3752T}TQpToQ[RT;BVXjQR1JWaY?-7{ZQpI,}wI>ybG1-{Vp-+HU*V=aACs'^o/]R;s[OIkk+ + DBY57OB;*sr^swlzpH_B*Xz#J?ZBIjZ<;Ep6knpB~<5Ul,eT_WHDa\7Q!x~]7O{lL}}wAf5}1lji + \]/FQJ1H|>=-R1@$vsJX-CAwUQwn_o@[B3Xw^DB[k]C$2*;Aji!n+[m+KsoB;HIX+E\{B$7ZO^LrCJvMY3vWC]{Y^TV{#{*E*# + ~T7iTHC5<'3}Q!ss-p[rul^?oGEKXs{p[kojjjm}jArHH/N-s3Xm}TZ,UXpH,x}CGJo + M1_AlEez}lC*vHRC#M{RJz~R1r!Xna^_=iCiQuiOWroG^lVma1R[s>+zm#prD@I*?vAVxQQ~s[lJ + 5l=Ee's@J2^_>uX1>!K\<[D5ToXrw<:K$s\3v[ZAGA^B}w{(xk5ZO5JWRz5<1sn}Ae*?K\mY[j<+GU>V5zxpBQ2nTl?p_+zB>HKn*x[x#'A,JTv~>CVE[r;C#]$V@oEA>xT~snr5<2<^^*@s=Qa~R=!1YE{EBxT\C'Yv + XZ\[73E=*2G@\gPR*X1~]k$z4p^'o^;\jT[Hrxb}Rpa6^km^s$;v!@v~x^!V! + T,|DC5Js_HBp{ZkejO-#}j1j7iT$-2zZe!?qNMEe=^NJTw~ei]*~eoV>{l+m[_^l[O^C!TW=m![; + El<{U[GvYe}AvDT}'A5<7<~r[1Qb^aa-EBwr^Br1$?WzOEVUxJT'=Eve_7K{m1VCizw}j]$uOj_> + sVjR\5>Cs11RA=mk#l!'<-YOw-7@9-\#J@R!7T\\5#C,We{a=*!aKr=+CInQo+#S2 + >^3EO~mM]@3HWQ=elz;uoZVBym>-+npB;g@GHK\B?O3>WC|O3Ei~5][JjRTRPd$nl\4a=T?]U+IIJGzR<*_vmGu{1~\hT*{kEIV?@$hvm[{?napI'=w$K3nW[WOC$ + ]pQ1{@}!on7i~s>+11@>j$YuXa.v!nGOwDr]5Cv]ZU*!$,3uA$*oB\kYH1*7]^xIQY]f{R}W'{,C + _BkWZp#]ev=~iU]+Bjxe=VRv_5;?*{_n!GxJ0uvGu]X+x^B;rBaz]Z'o]{rWu2U!Ke?[=ZHO'*pG + 15B[GQzo{xy>7VUvwo@{l2D71>E#$]Tkpn,*vQ$G27ez}$ns;W=^QwG+B,=m,}xwGB>V@o'WQaIV + iU?ml=wJa;3-B#3\Y3[5}pBiHJ-}2{!]3JksTHanw>Xvck.kwne$>Rppaa?^+5_D_iW7_E~V!O\$ + >OD[aRQF#sQJK=-CMnUj#iHUDKC,O!,UJ[m~xRTz#A\,olHQnIH!aGvHWVs=I4QH]+mUU=R{x'H> + AU++uj];>{xRU~O\^$+QjDIsXoa1#^e^>-VY8zG_C?G^VV}U=|C_=~DEunRrX{ + u]7UBvj_Ii7IuA@!3pYX6C7ekB$^U{Iur*eA}xsXkm5+>o$Ip>V5D3GT^*?Br^[>{n+}av>vJs;X + nMz2by~zn$?Xl<>n_r$*'XwvU{I@T*JYQu?1~5bl>\Jj$EW+,}21#D!l+EOVmwGpVZVAp_mf<1To + CkaW^Dw~]U$\HDo@B@Ym$<]7}i<-1AnX}]ieE+lr+p'pCu[rk*r-!]-*#xvRGYK;uxeXX-=na=XC + p~e[-jsrP^Z!Uu5JTe7,3Z}XCop@@BEn{l,l1H{'!MV{^}H<2a-oi$*k=Esria +`endprotected +//pragma protect end + + +//pragma protect +//pragma protect begin +`protected + + MTI!#/YeXKrl_sI!}5{Gea*amOjelTKYE@nTCiE#+BN"uE\ueQz#\xW]Zzp[RZnwuD_-3TM,~A?v + *Hu:j-ns~{BBY6+1$'Q,AmOoXA31,['>Kj}jEZ5awZ]?p_vil_2uJk5X5=lopk7lp$@DxxvQjvZeJlYa,1a&Xnx+]W]jGRB'B= + 1@,R72=sswnB#r,GU#smBx;R,3F]*+zrUT{;x+j_kX+l+yY+ZDJ',,ZwD1GXm[ + peJVrKERs[GqW]Zz*{3{aC;uBjQiYXAU^=;~U'C{k-;Jy7CZ#jJ^uj + v\v>]?\^m5wR@~[g\Y?#RTjuFV1wA[BkUpiZZX[{X*C]On=xiwbT*8,I\;wY#]1Zu{SSO\iQH$?vsEJEVC~^V*s\UUGrQ,BvE$;{yQjToBAB?|~l3 + @[=nYfl!7YBCTeNVnCGa5j$GIU5@jxrh}*xY^Gmn!_,>^+T}7I={xTDm{5*H\zz5OnYU1UbKl!Ye + Bau|wV{o"+IW!eybCID + UpGB@eWz2{Jl,,e#OE-P7Ikr}3m~{>GKZ_wx\_;axr2C|nVlr=2o5+5_,u>n}eK[{1V!2gYjXWVJ + lKm$uz}7}n{1V=ur3xAY]KRCk{Tr;\{rC>DO5Xr{>l^B[->Uo$}p3{^>]s]5V''sJ]QAHO|5!5Up + Sf-1]W^@\sKpZCeGv2\oJR2eD>T7xrB{]kG=}Yuj]~m7Y@s[H-bJ7W;iGJXX>pCm>Kv=or}*^Rv< + [=?P:[-$IXaT{VOV=HjGTsz1m',lRva^uUr-IR6lmOo^CR3Q''k>T + B;w$}Gn}@Vs]ZYlAlT1allZe+#JQ!]_C]RlcU^A>?nw$fXo;'[x{D~Rs*Q$UK0'}TxI#5z@[JODAIJ^u^2 + pa7wjnrUj!Dp!XCkKTk^zJBsEV<}#nf'Tj[kO-YTR<~.,TD\OQOx},> + aTEjV2zV^bj7JH$X;wNG!27Q?DTf-1-O'lDEC]=XpE,CwQU5H1azL + v$}ienuD';]\qR''$lT@VDjQ^Ee?~sO3sIAo@h-HVYmsoI}]CYW{uXE=1$jU*r\Q>o!15uo[-;>j + <Kj}[J,_Zx]_7p~=r{z=ZGm}{}uI?B7i+,B<5Dn{EXK;j + v[7'=Yu}V=sEmUGzei7+R,w[+Zdir#veq5>3=[#YkTYi*q*}onQ[O@av?n-5enI:D[I>I1k+J+ux + DRACtYGVZJ>J;jKGXJ,RnsIX]VVemL*[Z!lxG;*Bm5'ZEO_@}-}673W\]\Ork1Qs(7G_W^?]_.zVjJm[3Tq7o!s=IRKI,GR2[$Bj9m+m>'VwD;l;Y\uT#!Xr3!sujRK3Gu_W + u7omrAra3DrJ15{RQ{$1?^;,{s}>7mE@CRTBXN_i_DI*IOm=Y<1v^AA$'l]w-XzT*CUn5pNUE{'p + Wexg)jW>E_D^$^A*T2ez}r5aTBXDw=5~pOnQI=,@5s@Y>NBnX{OKDVoxaYIAY3_^D}~AKIjo}}7m + T\a}Q[3xD,{IuxCozwp},kU]Y!'CUnGj}iLQ#u!GZ_<#5BHQ{X!A{B[-=TJ}mI_[WK{Up_ju<5JI + __jC1IYxVh.J^i*v$k'Lme+o_Zn,Z{K;e7JpyDKYvNjl^G#vjD?D*e5z>]p@W';7]u}K1wn-_Kir + {?p?K_/d_wB^FrGT2WluaE^>kWDBT\Z2[pji#l2[C;Aj#[,=[M6#w5pq^[@#VKp~|Fa7*BxE\-;L + z-{O7Um_e3}U7X*snl<_osa'uGkCiZ]je>SfX}Zl_po{Op\^'EpkQBjH+,^]eJ5< + meETtwUQa!lC-;v?pR3Ces'ClE5OYjojw3X*vHeeO$OXKITAOD+G\~{U7$H1{#r;'21-G;5*{E+A + RYa^z=BaZ{r+ox~V>~'++Exs3z3H{IZzQVw-a/[A{#ut\1EGz2TDl*JDE5ex(,^3VvXa#HLrz}Yh + |RUrsExX!'*7JQiGp,T3-=B~s1,';T-{C?*r?e#W,AC$T%7vWX,[mmJlB-TaVHOWYRd^+K\\k>'j + \]nm{O5E{DAa{'u#[VO@,!k:U>E}E,\x>DZRpCO-ED!Y*zH+Rv=p+{3GRTAoApjed*Vp>u7\\m,k + EpaTQ,>AC2o-el5^5+TEUQ-eJ<=)@_IiCj7(wQ5VW*u!lT[27[[Z12,j@,K\zCBjR}*a,ZEOH^[G + \v2al>eEGm=YSDaZ1D\p2sl][xB7lsA]^oA}7pmm@AT^~{\=at%fVuB{=YjJUe}ZHQDCO!Y?U]*p + #r=EWoTHa$A,#l1#5e5j#=]@[!K7-j>rTp73E'6KYE@n-fE#+BNY0rr#+[;w?#QIr'eAkUBiwHeZpvzKK=vOp + PQl#>#Ull!r#~$!RVN^,]Eemp[KwJUz^;}W7;Jz'-XS~U\=P)mNI|Gx}$=3Yz}jiGJ=Q3$<~mreY + VOiR+KHjp_5_-7*7mo-jul@>KTaRV[mj$]liHD_j!';QR[I?T5R@\+,J1B!X5?s\[\~!;J$E,3+$ + nGwEYUBV}JN*U;#Q]{ZO,eir,-z-wwzT$mH\[Z]R*XY][w-SQBz>CxAnh-aX,s=H]s~]Gl21sl]H + aIUD1xz\{H-^GlwECrE+K5Y?=p1xvU-nE1\]Cn=a};~~CTQWUu5XR2WeT-$@wE{O?Q>NJV!XlOkQm|mjmA-aZ@5+OYT5Y? + d!}<{Dv{\BmZ\?rZ3}\27_[IG]#JH7cuDjjpI>~]\ZG-Dr\=z}{\7GGa{DuzO~VR\o=}\=JKl}Y@ + QpQrIr<7$7Uj\z[v+zi;eDBB,2zei<;l]E{fl;Xu~iX;@riZxV}}R + M8QZ*w7T>#f$WJ@a}[Du5EEuX!o;AJE@+~I4$jxI2Y]VvZmsk7H_]?s,8Vl#RGW-;]GrCQJIlXa[ + IXsV'ge3{C#U$#KsI$ApjEWal[lUK,Vkap>rkuxAlRjoC]HD*]mBp'RoJOp2^kwD!v[!*+^5p$K] + \JeX+[Vn\??VGjJ5EK*J~kTYX5G}>D3UHBE[$onEH?Ien,IaU@$aDGJ+mI{a--5Z5uG]_G=!++lBA=\A+]VB_#'{Qp\sRN,5QO72_?m^_p + iVHDBR~a6QsI7sjjX3a$1mRTQ}wo*DasVH,$#K-Eu},[[ww]XOe{u/k'l'I]x,Xe!G*~lie~W~Aa + 3~$5*+1_<>eYTpG,E5_EI)nA<3eUeUCaCkEe<3j<<<#x]!@{x*WU~2mjV>'VJ!Y_Jj+sonflX@]a + U2JuUp}G_2J6UT}]x_2@1'}}kj[W&^V~\FDr}?\;O*"B-'[urU=*.uYTBDOD-+5;[2\\YiQQBOxO + T2]_J>E3lArw=vR+TW +`endprotected +//pragma protect end + + +//pragma protect +//pragma protect begin +`protected + + MTI!#j)2zBXW_,'#]nWr'21.G@[V$u3?/q=[k[xmViRiz;_bQI'TnH-H$_#T=K[Ge1*1G0Y@[r1p + @}qC|z3C[EfkQ'Be-e]iXa[zx^QI}VCX$sD72B*NmzaUQevW?rkUP[DYk'H^[D@VKurj=OQ<3\Ij + iPiB#zCJ*![@WW$v'pi^HBf^Q5[QH,ul,[OdQm[l[b5#+3+jD2Ouop_!VpJs?vQepRVQx}Y*a#l? + IZ=3ukZs_'uv3jO<1R3'BmD3yR5jawOm!)~wY5vW~lR@11f4l7]lIi+mP+Gu_@]UWB3rplI3ug3CRUwVCK[* + 2v$?JK*+e[YV>$jQ>@O]%;x={}3YK./1In=G;;Jh-1TJ'@C-$N~oHxmUuOyZ'XwIARpOC'2k{r=] + {2mDE{k*CE!_5,YEI_UVzDo}2vOz)AGDw__BEb@l>onaIQH+<#ZY]ieQ<DvTun[Ee#C#_5[;-j}*#ZH-Gpl3WA7$_wZe + 'Az+]kppx['I[KBs#1IpC^e}u>=KX__'[kE!YunvmD;Ev[XUxv[1i'/E*[,!AD]#-I;LK}i]OQs@VsZ}=I_ZkvH}eWvDV_$1}CmWwrCVVY-2%fPe3[J + x*H~jonX?evnWxew~jnk[-}7_T]2@UI=xJjQp5Tu;jE}O3'\?Ci^B&CkK}DT_+_izOJIpW4D[Ho' + }Ov61i=]h-eHTKr~vw#MY!\UER+G1;H@VmZ?KT2rj[<\-$nI]jlB\^IkRYJwsOWE5p_HDxiZRl[UA:fvI$}7ODIj?eJEe@z=fTwex,Z;+$1jUE + V\XGirExsB5lImIx3<'+$CA}{I~@ssB2<=W!UW5"|(U&f]p]{>X'e[Y_T]5[+GZQ>[j'5G~5ejks\iCjD'DplwwTYUn!,>C/!xj1D-x!I~\uLe/!Ao7#'_AXH{]NSrY~Jz*J15?eXj + pHrd$3DV~TYm$@\}z+eZUOn-u]aEQ>Q>r\1T1eEQ[3EW+O7,*rR7Xu^2HC~-xC$TkslDiK[O=vvC}k+Gze;}X# + z!}x-+A;Xv;<5B;#D?G-UW*,@4Zw + -C[kuplDY*]_{EJv3_E+HWiaZB[e-UrDXBK_}p#^$G{T!s]*{<3pGpQ_X-nX+IUwaxaDQrQrOj?U + C5m5;\4uT=2^Vs{Exa'mrY\TV4Njl$!7r-u1*Wr<^xa|vVj?suB@b + ~{wzRan,er$Qt?{I=^2AwJ-h-j-77}\C#Tv'U7QB~=m$z7'OOux5[SQD2@1n;Z57\!M$?KZVo!o]}QTAo{C'jV@]GDRY,^H!'}Ya!zzl>,TRO}_R!k<'xm+_* + $UvA:%jxpp@zrk$B]3J*!}Q;OI1k>Dz'*ea,;;jomb.P1{_^DGf7?+U!pBV={ap#%pm*\+pI$E@T_,]$_O*=GW + 5~mW}+>s#I^'e@WrTUr7Xse]CkzGj!*-5BQ]j7zu5~xHl7u_%QiK^,~7AKh6"Y5H{B6snorH$xlF + _3V*h~{VGfrCasu1CC7Y@7oW__6^5'[s>p]C3}5H[UU-RKB.!^B,:7>$JUz]xkI~U=[lp~w[}~Xz + Bie3IXeO + u1xe^C,n5OJvr=i-}uDHo@I5>#JDwzBmUAAo + ,~i_ir(w[[/B72ZK&U]n}Z>v~[_aX$v'#^n)U]VY>=OQ'p>KsJRsoGp[CCT1]\\5~=kX0Im~5W]r + =WEA@'p*K+rQ$\^,pQV1eE]Gm@Wk-s!>ouziGzZ;XxvZ[-pPyrj_@{Hx]D + BiAl?IWxlOaXxOEBuX'#_]x$e71-QvGsQ5i'u'ZK, + }5}E-QU~^Y5iI*vZ_=rV1@9}YC*EAT](cB3+2,noogfp-{,F=_5Uf&\~\irQZrE3-VQ[**\~s!nE~H7X$?)K7o{V!'k1?ApDE2H'R{>FHG3lk + DX-'ZIk@TR2^}DDOU-p{'1}+=!W<5Y]'H!>i[{[VXD{s;7r^}\-'Ozuw7HvWaWXR}xnV3$r}Vr^= + D;]BJl-zuz!5A+p2v#$~l!,v?T^{Bx7i=[75uZ>]1T7,1ZExWI's\;=jk7{RwDw}'5sFl^e'GuJo + @x\{P>-3O7}Qk~BA1-,]VC|BZxXnRXOIO^'z;vX1tCEInpj#V\\Dn]z3aY$$*B.EW(i*CQoHo{;1 + YOZY-XZs!~%'eD*V+m[L{IC4U=Yn&GYk2,i+@o7n#<{}rO@$\-{pJ^!+}rvajQ>EpH$#eA'2,EQw + ~uUwxpjKZms>Ds@;QQY>we#Rjj{m}s]j~l?!Y7eB2-v'~c}k]!$^7]{nQ,~R;xj-^,z\zAu#wI<-F;{7;l$mHmT!1I@Ge))Hw=H}3AwoD#rHCX[DQ]#axO@$l~!\Cp7G*2>^+'\]K2Q + 1Zo[i]r#lQ^+="+C@C]Cj5vaXTO?!W.}k!OD8pow[@jsoMk^T@'@=uh{E7T + .=-5V=ZoEopW3sv6eZ\2@RKY?]kX3wQojpU^3n*BO-~7ouV@@>4[Ip=s2u=OilV + =Tpv7?*?0hmVsuqB#Ue=@Gm?1?z]rA[Ge1'aDKG?'XZXIWW];B@oA{;G>nT+<]p}*nW_5YC]yv1e + {Ik\,K=#l]m7$wDn;;o1[$awk_]n3Ws$T|'IjXma~sE{Xow-}!mX${!TK*O7Hu7E-]C7I~O>\1JY*YWl-{kOwKu6l]O7,A;*BTEja5;g!s-IP+B![BGjAHaWChYKK,<+3vuoAX,^ + >X5G!}{s3BK'sZw#E*l_ZwxYH~{v?}6*tpa1p7moQD1+syl,1wT[ei1#eJ5'G;XOwox25m71'm7u,n$.KQx$R\ + }~X^xZK+!C*?~\,a-$C;!o,D#T\^7Uown-/H^Qezr$RIOZxzxoG@='lvA*;+RJ3[B?sb>^KYCKee + 'Kmn7vJUHlZ[.^1sKe[) +`endprotected +//pragma protect end + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/fpga/ip/gTSE/Testbench/ncsim/gTSE.sv b/fpga/ip/gTSE/Testbench/ncsim/gTSE.sv new file mode 100644 index 0000000..a4ca54d --- /dev/null +++ b/fpga/ip/gTSE/Testbench/ncsim/gTSE.sv @@ -0,0 +1,9954 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.288.2.10 +// IP Version: 7.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _4c19f37180ff465ca20760e199a0613f +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module gTSE +( + input mac_reset, + input proto_reset, + output rx_mac_aclk, + input tx_mac_aclk, + output [2:0] eth_speed, + input rx_axis_clk, + output rx_axis_mac_tuser, + output rx_axis_mac_tlast, + output rx_axis_mac_tvalid, + input rx_axis_mac_tready, + input tx_axis_clk, + input tx_axis_mac_tvalid, + input tx_axis_mac_tlast, + input tx_axis_mac_tuser, + output tx_axis_mac_tready, + output [3:0] rgmii_txd_HI, + output [3:0] rgmii_txd_LO, + output rgmii_tx_ctl_HI, + output rgmii_tx_ctl_LO, + output rgmii_txc_HI, + output rgmii_txc_LO, + input [3:0] rgmii_rxd_HI, + input [3:0] rgmii_rxd_LO, + input rgmii_rx_ctl_HI, + input rgmii_rx_ctl_LO, + input rgmii_rxc, + input s_axi_aclk, + output [7:0] rx_axis_mac_tdata, + input [7:0] tx_axis_mac_tdata, + input [0:0] tx_axis_mac_tstrb, + output [0:0] rx_axis_mac_tstrb, + output MdoEn, + output Mdo, + input Mdi, + output Mdc, + input [9:0] s_axi_araddr, + output s_axi_arready, + input s_axi_arvalid, + input [9:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_awvalid, + input s_axi_bready, + output [1:0] s_axi_bresp, + output s_axi_bvalid, + output [31:0] s_axi_rdata, + input s_axi_rready, + output [1:0] s_axi_rresp, + output s_axi_rvalid, + input [31:0] s_axi_wdata, + output s_axi_wready, + input s_axi_wvalid +); +`IP_MODULE_NAME(efx_mac1gbe) +#( + .VERSION (16), + .TXFIFO_EN (1'b1), + .RXFIFO_EN (1'b1), + .TXFIFO_DTH (4096), + .RXFIFO_DTH (4096), + .PHY_INTF_MODE (0), + .AXIS_DW (8), + .RGMII_RXC_EDGE (1'b1), + .RGMII_TXC_DLY (1'b1), + .INTER_PACKET_GAP (6'd12), + .MTU_FRAME_LENGTH (16'd1518), + .MAC_SOURCE_ADDRESS (48'd0), + .ENABLE_BROADCAST_FILTERING (1'b1), + .LOOPBACK_EN (1'b1), + .APBIF (1'b0), + .FAMILY ("TITANIUM") +) +u_efx_mac1gbe +( + .mac_reset ( mac_reset ), + .proto_reset ( proto_reset ), + .rx_mac_aclk ( rx_mac_aclk ), + .tx_mac_aclk ( tx_mac_aclk ), + .eth_speed ( eth_speed ), + .rx_axis_clk ( rx_axis_clk ), + .rx_axis_mac_tuser ( rx_axis_mac_tuser ), + .rx_axis_mac_tlast ( rx_axis_mac_tlast ), + .rx_axis_mac_tvalid ( rx_axis_mac_tvalid ), + .rx_axis_mac_tready ( rx_axis_mac_tready ), + .tx_axis_clk ( tx_axis_clk ), + .tx_axis_mac_tvalid ( tx_axis_mac_tvalid ), + .tx_axis_mac_tlast ( tx_axis_mac_tlast ), + .tx_axis_mac_tuser ( tx_axis_mac_tuser ), + .tx_axis_mac_tready ( tx_axis_mac_tready ), + .rgmii_txd_HI ( rgmii_txd_HI ), + .rgmii_txd_LO ( rgmii_txd_LO ), + .rgmii_tx_ctl_HI ( rgmii_tx_ctl_HI ), + .rgmii_tx_ctl_LO ( rgmii_tx_ctl_LO ), + .rgmii_txc_HI ( rgmii_txc_HI ), + .rgmii_txc_LO ( rgmii_txc_LO ), + .rgmii_rxd_HI ( rgmii_rxd_HI ), + .rgmii_rxd_LO ( rgmii_rxd_LO ), + .rgmii_rx_ctl_HI ( rgmii_rx_ctl_HI ), + .rgmii_rx_ctl_LO ( rgmii_rx_ctl_LO ), + .rgmii_rxc ( rgmii_rxc ), + .s_axi_aclk ( s_axi_aclk ), + .rx_axis_mac_tdata ( rx_axis_mac_tdata ), + .tx_axis_mac_tdata ( tx_axis_mac_tdata ), + .tx_axis_mac_tstrb ( tx_axis_mac_tstrb ), + .rx_axis_mac_tstrb ( rx_axis_mac_tstrb ), + .MdoEn ( MdoEn ), + .Mdo ( Mdo ), + .Mdi ( Mdi ), + .Mdc ( Mdc ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arready ( s_axi_arready ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awready ( s_axi_awready ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rready ( s_axi_rready ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_wready ( s_axi_wready ), + .s_axi_wvalid ( s_axi_wvalid ) +); +endmodule + +//pragma protect begin_protected +//pragma protect encrypt_agent="NCPROTECT" +//pragma protect encrypt_agent_info="Encrypted using API" +//pragma protect key_keyowner=Cadence Design Systems. +//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) +//pragma protect key_method=RSA +//pragma protect key_block +AnxLCEXIwWGNUbKODuvDDj9z3+IsvyasQalysUi/itDT2wwInQ3bBdLVigviyZBs +KfNqHVcHh1PkyYw6Tc63TbVvrM0JlKHeRk9d4Ni755Frdl+e0Yeh82+Cu7JAI77V +toSbtXAPtD6vOVPzzed5ozvhLM0NSdRFehAG9pksl3iYjKFZP6TayMWce09NBstN +j+KnL6lB7cNlu0ejMJXS7VgJ8dx8NGBDtFHQEZ5XfZo3IKXu2RTPmQkW3pU8QhlH +F8qGcX2EikZvcV+7xxJnVc8CjsdqEa+f2tIVEtB7gpGdCQYhsfE4ScprrVpuFhH+ +2Rn6AkA5iTdD385b26iafw== +//pragma protect end_key_block +//pragma protect digest_block +45gGFciNrCTJZXxwMOIqQD36VKE= +//pragma protect end_digest_block +//pragma protect data_block +/fAtlRv3M2ytzKM0VXXGACIycHPm8M1coZKa23W5ckG5VSaPQWRKFrb6mgu8TO0l +bsYYbh10DRf4e0UeK3eUMlW2Nv7PK5r0WlNsZ9MnO0NK/lbgmAILp5iX5xNmPGF7 +gjcW59pKt2Qrn7vnwhWQ63Z39ta8HP6ePI71JfesQqoYcpBSA8AmFzMf1qI1uHz2 +7ErMZ/087JXzS1/EfWz+HieVw9qNIkgQ+VC0HOg62kSOuyGGx0OlFaSSRqrkQBa2 +l5wr1Q5Xfy1pQTbh/5tHAygoyKtL/Xnlgi1THjm3FM9dv+TuX+phlOCiGL4to09Z +Qo7SWTIezt44KA9UucO1/gadJ70aQGrwfgvSO+G8xE5x+lcGeo+7NzoXvFsi0s+j +9eTGqKPEnw71QadHcPTSkKxTN0NE7Xwx076L8bPZ9m8ANfnfKX3m3i8tMSfSW+6F +PSqPF5XddstKumMgnP1oWtr8G7Zn+VyShR7G3E9tmtfgVzQsrLUHluUZogE/ESfw +AeYeJjEoRkzLwRFCKzy0R6BEzeZvZfZ0xv+s38XgmKvEpE/bVplAqDpmFaWpNcWF +Ru8sYhk8Cdyodw8M7YzSE+sqGI4OKHHoZdV75dQof86i87NiQiesruNAVRwbXW7x +fMohhn/h/mhmuE8nKssOyKahZuFxL1ich1gkQPdFZHvvwynRBdS/e5i/6AaaBIBP +bR8p9b8hk3ni1xPjf3lHM+s8LvIwWOC9hoOSzaeJh0K6n39T0LnH9uegg/eGrSg9 +hYUOhRon3mkfbIm3pswVQL/fxjjfwRy1u5yT+1Sxg7JfShqilW/BxEVRr9Vxd+rO +5Cflt4nrXlSTPZrTQSnGiwNKHhSFBEe0RzV+8w1yfbi2NXVWG0US1iKg4p+Op354 +0kJQhKlWcJRODiobUArS4ggIcIR5w/GB1xjpY/MmP7Ow6X8ZkybvsDzXK3bP5UME +hPRFCZKfj2muvkYTY4dNgUhNzvPf3WsIbbgif6UKDDNPoTTUK/GXMfbPqAwF6Zwo +mAkIN054CU5DC8H6Emh5/7fLohI0Z6HQGUV2LETHFcO72lREtIo8QySjIPWGXQt3 +tifo6++SzquMqk7Rekps+tUpor8nVcp1ZDq73IthGNtLY3WhuvNoaC80cno0mcjn +hPN/CggFKQcW3OCS7YPxjd8pbeBpt/4IZVjpp44BYGw572Gc3lBCzVzjxTcwJoN3 +yl7CEMJ7qmzE1Y62eCnaYbONOmj/GmLCqMnFJWkTkW52jSQabu+UpxYsEXwJPgHN +4YNh8yrL4uqbp4rgv7Z72mscn1cV+XGk7m6Y+F/q1CHpa3NmdHNQVTsYyBm6IWcN +JGjSPR7S8PyhXmr9t0iq1x1BfHjG/2tu8iR/IxrRt3tJ815qyEdYb2J8p8ZhoGQr +eQkAgvSof434aqpMwqb81heSFO9IsIbT9jgrL3Yi+2LsEfduq1Zrx/ZsYw5SEacz +4TTn6SozH5LbYhmVgYQt9kYLpdWjjts3ylHeURt2q96DYLGLWp7zGIZSmEQP8Dho +ba8OjSUimWF9Og/bYq9FshT8cTseVjasFp0LPkYDVhEkbEYF7clJiDhrQZwcN16g +6CmBo8LN3x8uCgjakt8P/diYXN+QhQz589WD8F69m6kT3hG48GzwR014Ai/G1t3S +wzA8mZd+LbOuq3vYbkBbTVWS63sBoc3uXm9mxOkJjG2qTMP6lttmpWwOF2lbSWjP +ulAW7E/D0d2Iw7xamSgA/pUpBxtVIYooiOm6WciPAkKoqyF123aXoSEk8VvqdXfu +cYPvXKyHnZHoq+FjpG6TvVlMyF6yZcEQ+H7Exagshqn5VAs1fCCjqbFD4XMhPgv4 +j6pssEFgC86SBZkBKF00klGlhgJAR8w4oB5PUh8CtM55Hb8TUDNWWyN/pnUoHISJ +mA9KIorI7W051wsUrOz7sDJpskMEEuFIKrHmXICjMJpLINKKXeolmpzvyz3lI1kX +A5s4Fgu8/LASJn9ZZQ6CQm7243yPfjSyszsmfx2GFY4JyqzsbSOfPTmAsfJNfpFx +11AH+00eb6QfpQViTYMvrcBS7IR6xYqHChNoN1zxTQNyoNDoCh/Wa8DAsU7WzG6V +1F1cRajRbllWYYaPZYmYzxACdFW+/Ernzm2qYPMlsq+Mkl1isEX/05ma0Dk8aR// +LbcP+pt0w7E2z4+gDAxVc1lsnsuWY0+J43tIJFbvfp+kAnvdChAfJzeKk8ty3QRC +lN64Z/2lt6mjkcIVyYf2pyuzv/ELaxCr4Jfi1COfpB5oDroo34CpxzKYDIIXLQrV +WqQMwfDGl7tFErqtO7UfyymNuYSOoMF3tMNfmO+C7ojGRUbmZZUORBJf3jvfhiKC +lY0mMVSPHznDh9X8iLsJV0641TxiZxQEtXo1Une75LlecLfejLKPAiGjXVdawxZ/ +DmWABfm/8h7XTJrubwm7QiVQF+COMAtwME44d1HjlaNKU14Y/8VlXdprK/52Gs66 +Xs39Dhnkz7THGh5kFnNnGzCve69DTSN1MGNTFyNl+ZE04QHT9KySRjqT+nbwjKW3 +4sHbSPUG4c9qnpbuUIvjjjaS1VH8Fy5PicmsLerEh1Y3kRXpbHh6tTM+/UACLMdW +OwlDRSdNDy5PqCLwaN+TDdsBrOdtw904roL5eSDG55U+Ykdf8fwUXvuiT8mYCdDe +AZAOjVam0ua+0nk1kNsik9PA0umuxbi/tpyM+0RziN4xM+YDZozyYUM9P4ai5xwy +QzwEf9m2n9kMn1Td+gAjRRHqJ07wVLo3gXw7qCfCKF3J1bhlHjTUHRB9ReDBqAt1 +RXhZfW6ZHW+NCl4OMoIY3BOEIbZUZo4pkmadd3ZOms4GcM5bv6tKsjFyuVURTV4r +Qmh3NdlT6QAtuewZT8ZaPG6foPh89BBLL1Xv6CRJJjLu7nwpR3FxqTfqaSPORayJ +V4nYl+EOyGBU5C5PaI3pkXHnv6A8BBe0J8DcLu543qijRctXtlj6z5UHDsgFrOFo +mRfE0H1xUJhst0PgZFxQmjAmxsk/YWS4+KIK0rJ59WmztsliL7RmY35cOPQK/xVz +cbwIS/s1iC4TGa6pqKExhvz5nR08NeUbVkaAo3UvIwprvS9Ym3OQZQrs7vI8B57h +sGGsWk52mqQow3DI86yAZGgBE0j7Lhi6E4OUgpqhvy/24WusuuUg+gjm067PG7G2 +aVFEHmMwzkqmHx2OYt4VDAiZw1iXH+WJ+flo6gtSL4wbDpC4b5UeNK58Avew0qMZ +9kSTjqole6eBPh7BGa4h4egXivvjQ5dSG1ot//rrGvwwTbmyw66C3h1IEpm4J2P+ +RjuzCq2HiGc/7rlORVNpqd72ozUWO+LgaVypF1Muxjrp82Z7VTLYjuXAP8p9IOPM +K+YVfhuqB6HzqPiTQkyJNMSx1b61L1IMRZKSpgW0p65Pv7yHF5Cet+i165uofGfN +ajoDrd6yYjInCka++f50oCHmfowD6XPVgp0JEYYQefsOW5fF+Nju8kc0vyVPr8Bd +VHOtO9ZzsUOkYgTvrLyRrO00xH2slZRmSWLLxOHiNlsBNs2oooyNKMXKa+iXR0IL +NIiDEwZ3091Eb4iD8C36Mz0CR6mlSpIGuY2reZNRB98yZHzb7MlMEGlLwkr6R8lS +JX41WEIOWUPHEjcUZqJc+pClTcIDJZcqNW9Kyqa2jGmL5xOhjHjEnmpx0SieqdHw +uaHyGRlmgFIEPR6MYMvW5iY/IudFZZmb5+PScM09z1p+P23pIj1z3scrt5Xknln3 +lzGg8EBwRKPHTnRybPKjjzKd6wUZykc3bh0pg/B+Bt1/8+M5XyY3KnVf0BbIfBqe +RzOUIzvjsMyF1ugxxVYrF7vQ6++98kN1UBIxO887tVQP0SuF+amfpJqTZ7vkEJtF +ddbVDLslbvTrqznPUj5KfPULSpUSsCxj7M/6sdEg44cwxx9TJ7eEw27XLD4tFBZ3 +BjbObPKmG1KY4XYgFNz0QWay+zwv/MrzcP89WzOiLZxc3IXUAS3ww0v0g/g21kP0 +uiv4NENZtZNFI6fXJ4iKFh1WWOlPAfoNSaSw87kp8wqhHja7uR2vA8Z23P+TJem0 +xNuW1/W62/Mq5SYn/DymTzZlGN/vENUZsSQTfiD+crv8GdqAwHIp3GtRh/LiUNME +JI2LiJ70eMZe6mbZR+a7WQi9eFk7T3uwumpMdDj43MQIC1PBR4ZmaaHnN42KmJ+J +/ondvoylC6xTAvEBkpg5EFJ8yVpMsj9BEa7dEUIst5s+yyieCoMPr5DvxpED+W6c +4ArzX3JazzwyQ2VvUrDajdbTYzkS/GVs3GcQY0eF4ZYXxDAcjdTuNcU2Wh+OYZWQ +8B8kPHROZnCyE9ydiYqFCTnYNWyDKVWErLVK5CaED2Sn9e44HgUaQBT7/ANXXB0T +s1GqfPZgsl2qIPIrXUOotm28v/cwN53Ib88QSBGHVhIks7SiLUV8gGZIUqs1mzjw +2++c4VY8+3HysaCoB7PH8aX/XT1uOX8081PUG84zMNuUeVGV3zhH/xQI8Fcc/aOU +qklMUhywHyTTdw2ZLGUuKYCcNETX4JyyPGLGDagSHFovJ7ejhU3RoxunkNkhApmP +CCa4gGvrknkxoeyjx8/HQwLJ0Xh6UoC83DlXAUkBmJYqOYL2xDdFYh9mGf96bzOE +pfPugu+bSj0COuRpwU7ocwIYbh8q2/Zz9hHBBTnc+p7yAsnEVqQ+AprwsgxCPtU7 +FGOz3WeZKjuOfltD0LXxYfPob5Eqjw/jTCGyAKzA3ZyN4ZIKdwyEswXY/lXrHZV0 +Tg+bcXdZDtq2auOSELpj0yq25M5/lFpy+Gpu5rr8IEBM+mgTzIoJRepNK3RyCyzv +MBx1I4x0EP+0pxKpMR3iq1K7n8Y2LoFQJXIeQDSlaB7K/JoI3O0u8lDx11vyOpX9 +PfoVLKm83xRbiqujxE3N9yYOKNFtLT+nHaDWL29V+BYRanqRqnZX7GNqfdi22MST +WzOPQarJxivrT5bKI0M4MGrsmhI2iweDG2Q1YTlytDYtr8IlK3X2O1kxvw2Sqcbf +03oWPNvPtw5IfIuZ2JeULbHvMZAJTin0MtEsMgfEB6vIyEECgGRLTPx2jLeOsu+K +hvGKzmfgeiuQvc5Z6Ir6ffRcmDou1u+JeSZPXDh/3WjR1qgXNZQwqWLD/m4cM6Kc +lk8//4ZLB0/EKKtsrknblZC8ZiAT2yxtKcQhjy1nYpKxdjxGwOU4jVRYtb6HT4Nk +3ITL68Dnjb0PXMNoShHVBxM4zhLz3E/7VANnDbF5EmsfiHUFdOKNwkRnRytQns1C +oHgEGxi3aebR15befist9yBTO9I7iZUG7gdqfpgG9gYF2jC4MRPLNS8tzEby+ELN +S/Fx/3tH9fTEnemyq/YMM4rIPyMnO4NItfJDGH/JhilV6SXmDZjPBX/nDtH0fgNL +3/5Np3icRiVaI4TC5hn+I8dc8xiTVawHXiZOL3uefi0wOB7aZlSgMx8VKUTnfd87 +wkjLMw7NqLGTFEbBrwAwIxLegXl5wl0RrgNI3a1jvrxOkGCw8RuNmtiytP8xWMu7 +IGTxSg86nPawu1qpaRWYeq8iVRARQxfRo9IKQwbFGgGwQpNrivZmStNOrz5nJSoy +tLQ+ryWtHB6hWHSXjlS41J2ktl8evTGXuFBoZxLMkSeQwYNrfWtE624U/vfQGNDH +1ilCI55htRDIo5hnpWwgYSh7COWwX6lg5Si3KyWpwRsVw6WsaO9SSpHmBWisqcj+ +rPF7UxN/YJW0gHNRXEZDVG5p4GKHqQN6AX4NMzkEBmW+U9+l953Ytt6vpIzF1S98 +ZdBhCsZFU/06kyfJ2Oi6X3hcuOuP789cgev9d62NlbH9yeIZyZFRP7/B4LxtcaJw +8QPzDrIo9nhWbg0YFQ6SAuIcABPGP7crLJJ7TMPZ3CYOYMbGXQnZTnhFxBMMJJbE +FVlkEGvi7DkCBW9i4xQedh19Bcn2LeJVcH5tfBhYm4m3FhikbiKDxbBxuMduMu3y +Ja0Vos3aES2CwsrRkflqwwu5q9MonfuLKViEN1OYrVszHkV8A1ClJd4LojK6rpVr +BZLvyMjAue2naY7RmsCT6Rjw/Ox8Hzoel2WbC4Jv8NZVsqs+NhkYT6wYp+ONZ82L +9K+gnXPGFqEhTYpYyOcNiW7//ge2IFLJVCkQ13W7uYfFooiNJIqUgZqfxKVF8Mmq +qSdnrvzMJwWXP+IaYuQcPC6daMirz3iyntYm86xFqH6L/e2ZEDFSZ8wNRwJV6miO +yD81YV1QpVZYO/qTCLAFeCeE0MB0L++J9uK7M5K86Z91f1CzRXPbWiLxpYp0AqgF +bm8QSKAmWo5FXxHMFDvUIh5QzNq5Mc1X9Rv7E0NrxI6hVcZKWSHQ97isL6XvYU90 ++cWDT1XP8wKrILLuaERzUif6uHCs4Tzchp/QJFTs+4N8H6Qji3COqd7Uduk8C2em +HnFnpB6TYhTGBH9hS2BhJQJtXCV4/8lupZIvj/kY8hGeLX/p9sXZxafGtYCQ1w10 +5+pTKAeRo8U3Ls3m+0+W41jNdsLbPIRLQOB6tP0JbHfBRUb96h524+TPgkdt8L1O +/tR4ZyhqNxN+ttlekhmcx54u51pjw0q46rAGKLsQhhIH/dMSX7aro2TAjik9qG84 +1kq8bdz+0yRYukq776vwLI+PpEMZiZsKy0k9DmeUbsbsXik5o5AaVXoVOL+wOChh +s3fxzkLIXDuAVLf9z5CoWHayUPrngf8BGdejF33lM1EJQ3Y/j7Sp6TEyT+vMxN5E +txCKnySvTtGADNDGwez7bh/pBKW0BxvuubFMLn5oyH7c+BiflJa/T5amTOaGbSdR +Oorl0y0MjxLKm9Q/dVna9PtoOcLFCETA0memiCgcmXW/YK+xXqGPlZJLVoYzwZm7 +M36m7Nu+VPKAo6zkq2DzrKdweGun6Bqvd+D8VqHVsp7e8HsmJ7v8zqfuTQkxHCq9 +h6Oub985CCp6yFRDeja5f1jLW1qE780WmjxHoNeAO9uOEpXdS65HvLoOrfMYQ2Qg +nR79kSegpGDfp6b4yL9Ny7OUxNFwF0HmCk+xv+LLWK/CxsJy+ljQq0M0nKPxxtqa +arLVHYXg3oMwVMCWPJiKYKiTjPLL8Fcl51rPrBCcPnsSArnTGif03OwTEpnHfqQk +TUog/UovK5C4XRvE+ASbFf8wKN9x3ZiKcbw07bSq+qchfYS3kJlzCUvSooJpqEht +NvC+t415hwog6JBIBf0ogpa8slXbj0SZO5vu4giL/OBJQYEnQJ209wekVcdyLqLu +YSpn8p7tiBdTtxL7p91yhU6n12pR86W+MjeL1yFHV2j1n5shGcyRlg9bZ7OFP4S0 +fdQ3gYSNOGqsLenK1aUDQuxyfelyovmZ/uy2dAN6o3lKy4Y6SeWGqOEjE2QZW8Av +wdGAHDT1qEfFY78edqZdks6hLkhwWZ7GHjTjs5CayZZ8sMFpNfsQBn8gDc7jE580 +DGsyK4Nsl0m/Tqoi9z3Y6Gr+k6ilRBUWGTtxDwqsYIG8l+O/z+KPCDxZMZedQr19 ++F5FqLoovU2UrHwe6KHos0I0a/jiY5l2sJB5qmVRjrNEUDv8J4JaFJYzL9M8vZXH +chxcBjD99BrV0aH4XVVIYXkHsj5rYjsqCZ2AOUDTSDJNZD+kPA3NWTPtF1O4yZfk +wZME0qR7cBZyJgTCiTPGM+9J5vC7ybSaGI8FLslfaMeov8G+FN3+qlXDbJxH0qhA +E/kb/OFySopjX/wZi5wLR2msaw63MfKWalJ0YUMUoQHVnd+j6lDHZsf5OWWNYrAn +CucogG7WeTKgbzlAdj/6bxZRhl1Gcob5qQJ7n/oj25+M2IVI1A8LAsc9a0szr6oK +Y3/hZfshTawBsOWfJwXbGt3eOFfYjwKfai46Tc3EGhk/PElsJ23naxQBdtbQixJw +jVdMDSybGkr2rP3j6Gk6VGSEtokwQ1uf5pNFIflxut6565YxexQrV03s4UKgRquB +7boCQiEwBfh7MJ3Els9+EclH7P/kZ0NLngS/iSwWppnLl7nLhXhBy8s9S+1zjmoY +EPvxDoOKrP0CXeqtUBEC8jMaV6uAi8AAYQD3evXGx9I6MSpdrSwm6Eq73Rsiragx +irGKQKAnEukFFJ/R0eePi/NBEjD5iTzDY5Q/doelHC75lKNO1zjnrg7ybPCC3VGa +tnq593ncg8HHJihCtPqHVBGI+BBj/3eah+o+yLZNqItw+Xu96Yms4bI4fkEL8Izb +7zLM8b59njnxSAnW5gqaob/3KJqJOfB7eqhl7NcO6fmKobuVrC6jafpyfjyZUQmp +WUVDpeUyu8Ad4CuT2c8B/WJaRyf+2/R+jE05XcHp08Pt+TcTe/ZfEq8PjqQplXEo +16CJVUBKW3K/kjUUjfHrBqc2FQhKyn1wAC+aLRsgCuwyyJ4U1ViMY59V8xu4Abzy +JwdXMV7eUwOtTOZ4NL84S7TrOVQRWtRYhozIcykLpredCcmz16Z9wKUDEagWEtjr +LPbLrzlWiHKW0I6HstYQPLS9WhK46vaMq+a/lOrEC9AsyzXNhvUPta9JLayScAOW +j8j5o9qLABUohkFZ03SBVW0C2m1xA35AaodXAuaKWGQkcc9qrUhkhAFJmV50myFC +GocJH9R4iGf3sCSj6/wYKEcupiIndxvH8Rwu0NWI+r7yXBZ++De8qSrGLH4O+Auv +/iQ67XJEFJGGroq+jiSeAZ/52Ln8J/xvpOm6+yOd8N/j4N+vv0NtWVbGLCruZGKq +7o/6hI1AcrQ7zmHcbfXB0gGbd3sey3DQPSscOBcAsuh7FMa7+hxjqFbxN9HlIQV2 +7diWn7sJJU7VJA76CLDI8zNToGiER/qun9fMIPjBs+ozF4hvhZDyQXFZYyb52v9O +5H+7FKQjrqJjkB5yMDSOMFtNKcCJvMx5nXtT8w425HVAxShpkXHR9usVrTHtYwKP +mlr8fA6aubjF5Yu8s1pmkk2S+Ast5NB7R6L5IXNsDnkQDWZT3TNO9wRsARf00D/Z +BUsi1s4AsxV50zyV681KqvtEMBfQyIB3aGk+wwM/UlDsfVZd/ztopt6AbaIxPgl7 +S0UZO42M6Y2psHhxs8AIOAIMUfP+vV4e1rWaucKQxHYH13W0Esl5bCckh9WP7z0A +49fehWOJzWaLxPNlrYKyObAKsBYwK5ezeRvqYxJTzn1bf6br8qYF8KcqFTzrw8Qy +b1d5geRrWjRGi67MCjCjFWeOzi1NwV+lhvfE04L/a32dOqFpzS7EIhs8WpFz/j6Z +P6sIuxVrFjquNF0oEYmqNFxrlCYaW12gE5PsTsXbaVxBf+EGZ8uPyVzJA6LGQa9M +6DbM4XuihFZjcrqQmgvsXvDYmRFEBCvvmbjlNPSxc/lVPYjtvLZqcxKIdvogUgrp +JlzNUx94jQV9U7Se+OFWewdHTb+gq+5xr+Sssz3TEpXMNWsE98T1sWgT4uqaWSLT +pK6QKZhbUvQjLxeaz4zdcY+zvyVeXJV6t1zpIwXNqunq9qCZ9MIhZ30xMDoy17Ot +oHfj7SJkewj5AtSVeCdj+47FkUE4d6VyEEbKvHEsdcOKcYkmq6DVt978vbT0sk6j +3cUbtt+wDXRMRUsiqcL9IFCRYpjf0aKS2cOGW3UI1L8S8otVVf9Hs4xWiSr0IvRR +zO6COTIfYdnY29M8EzK8FShiKlhbi9c3r8/si/S2Sw/SnSi7P5+XntCAYV/d5nr2 +CdMFT51S2CENv/QBDM94lx8BbF3lDGURSykV0BuWIfuVgEsafiyf3H98doG4/JJW +WiUiYECopwOrfbhuMFBVUeMDNMll815XcRvun/GjCkouILZ4cnR55mPjkMzjiVcM +D2NuNsffJ/ia8ftmEItZuBP9TR46HcecR05rv9cdk4EP83Z8QqKWwI8t7pArklKQ +fr1RW4ldMFdlWaUHmPceD4LxYR2Pv1VurtZiDF/2ACovIdp28PiNezvQRRlOEiaK +j+DrO368PVFP49nmCmM/SCQVUXPA4mp8zeQSmIkSwVx3JtjbPPX5yiCNq8FnOAQb +EAPKfEDpjwBO9MjVSRk+DhvmiyMOAKuN1Sd2MoPXJIZBqeCD+nbdnJOQVQxVvwnI +LYaA8Q/CGl6Ty97FZFk8XWWVrVb5Fne2cgx52Z2j7R2PPqXL1Y3cUFY6Zf8OnEBX +h7O0Pgm17k0JaSZYsY3CGdcuMemqiVzzs6fmug5YGY8HIJY4mt0WDEqHO0soBIBc +nfMVNsMwsoi216wKNO3aaWGL0qx6mspKBKGOBishSvWra2gfX9YDtbZNVG+ZLONu +wcskTyX3li/mNrVBCUHHIyxeSr5YSZk/CLkLi9w3kWk/bcFJT0CvV2nyfYKatgP0 +7k0tCX+nvmc02R2Of+5SpRXuMaxttvoMS6Hzy/JiJWNrMgu0ac7oPkU4QstXMvSF +Vg6roi4BaGiOqeTLJtxg3AlojGngHK3HaysMFWw6v5urhfrbnHMQQyWIPgQEsmkf +HNqzQiJemMkcBiuy43DKGvXhEQyri6ISJAhcqftkk0RH2UTn/3xWC2u6eGizLlbt +ZyzJy3cv++lTfNfC5E3QsU/wC91mY2nefdBQK1nl9UEZCT7tOgPAFUlon+UFQ9LG +6w1pN7tfuu7NTXNabKi8hHuS9dNcNDYOkfO0XXKzPSHU8Zc6jCQCg2jA1De2BLF4 +VzCzsRuGrSzLPoC/DyCzlEqN0pFubmrKsdTrFhg3V+uSH3Omr/arjdXrTqSH8pNF +c3M1PLew3rC/bVpGBBfAv7Gw9GKn11s7Iw+FttMOM/uR/DSmKeiAUn8/zaY303HB +nF2FSINNiU/6/FS6zCIH0v+hoy9d1AB3XIwwgY3P4OHnkUdHpB3mdzxgozIXGlda +wmXZYMj+pEGVgoR5yjrXtl6FjRr487jboyyfFxxYO2J94OTi3+cwHMsOvUGjkuor +o0J7MHgK8h+0Y/pkl0KfNFDwKTrZU9D5XC2rFzjdwfc9HqHDLFLHya3s6+7TcoR5 +JwHicZDp8PtJTjF7O3Ie14lHhRPqqiZcC2sd64kS9onaefzof5chbbiLDTPMKqGZ +DALjKoOHrHMkP0mpJcLy9ydTQ1cWBPJ0CwBsPs9e0cHM2wUXZTD9uGhT+dY+7qUE +d0D1PRzqoqDLvJH8JKDN5rvMcrnNbyLZCASV8w5DHe+61TRWLxNhBxWjJVehWeVx +Y4jd3PSJkPySmLpnTAPu+Kmz87ehjIMgCLLaHgWEKVJTI4vtuEGhOupntP6VfURN +4SyzTUhi2t7IC9PARiURrPAEsBN/+6pUYiO5W0UDxBx2iRj2PKHPhZ6iS3xtSAYh +pGthUWCurdt7IBvB1PT8UpqvwnAU9apLwpYzxK2i1AMS7n9DByGdniJd2yWRv5Jz +9/q4zeGEtiYDg79Xt8KIOCki9JJL/d5RGaHl9xH5NI+7G1ZKXLIUnzOhCWw2G2pl +QXGeG4FL76PT5TDXGLRyKq9yxo434KJKt/pBV3ZEAJlt/56bnyvfk+pY6aFRCrQs +8zaqEcIZ3DCOfIRfrMBil3eiO2iNBIRu2Q7f8D1rmQ1+WxHL5jOr7AMKoieJ1Tjs +rPPiLBd3ZiHnw6Qyeo5Zc7fDNTurR/fmhtGrpl/OO5rUhwu65gFU8UNrpzE64Zdt +I5hVddBt8RUMWBRATJTdjvLkNor+OHelrlOXiDs+RtGkexSIwPVmB+9D5dNSrCjd +//pragma protect end_data_block +//pragma protect digest_block +ccHJ1CIvmCRS+nbWgLQWKS78CiY= +//pragma protect end_digest_block +//pragma protect end_protected + + +//pragma protect begin_protected +//pragma protect encrypt_agent="NCPROTECT" +//pragma protect encrypt_agent_info="Encrypted using API" +//pragma protect key_keyowner=Cadence Design Systems. +//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) +//pragma protect key_method=RSA +//pragma protect key_block +ARIzM20qvQsOhlemikp1MkhOGVvOqdCptklMFViFENgrk/BZmZ/vFkAL+ZtNt+Rt +gKaoV3CumDZiaq6j1xjRczEEuHtJJdWTPTpDnzJNsuHqOJA15YIcT7YAiS+pDPrH +ba6+VIqZO/0yjRlkoCPVqy9LkQ/xrWMKVbYMlmy0Id69u06KGbU1p5j4cb76uOMu +4bWZZrwVWlKStkTuJxrQaxY4reE/4p1IFspfvCOMNbfhGS5T9NLNuz4Ar+fLhiG4 +h0eIDLgy4gRmRu5lYBBfFDJkzEwoXKCyIu4bc2aTEbIes/iyxQmnggy0jAde8A39 +TdTlABcW1iLl/z9STeHQ+Q== +//pragma protect end_key_block +//pragma protect digest_block +n10L4UZBiziO4pZGJcyPwOagmTY= +//pragma protect end_digest_block +//pragma protect data_block +ks92l8Pg0utWHydDDfUWK9bco9hKy99Ce8wQI89GnW51fDBoSkKipLRroDYR4L4Q +KMxBd6gEhA6tCEBZ5pXXPbMQVWfaTgWvgmvmgJM+Q87n4H2sIERbqjFxtVA4jsAQ +GKjqpvPoUxomiwwwnkEhSBcn4Ln/INnrnN5uwLCndauYhelZ6qq5wwVTsXZ18oiF +muvBDozzgaFd6dsWb6tMSgKGByOe2tbPQ3Ze64+pl6wB+UsLu8Nqrx1MybBEYqhd +XpM9Z2OoRtbv3goP0Q9FMC0F63Q0/M9t4ZMaR788I5ZOhgXiPyeovcj0cB6JgEV5 +fufSyfhl3czHHTjcBqoqKlwcS23nyyugFwexhqMTa9oF7U2q8qancROWTSHDIBzL +IAy4xMe/+jC6iDSpG6X3Av7yKHUlT0gErKDciaW5NxJl6yoTx3Y8wF00QiOHTSjT +7IULO5VkuSn1wXa5uSOzKaRV+7uLVS70BtKW8IqacaGerzIohmYqxrtCa5A8tKSP +epAJld5IzBrNY430eue5o45udqkxEu9fcm+AYLm/w7lErz4Q5JDtoyDFBlRVJMXb +8PyqE3cavcbcj52fiqDfpO2upZkj5HXjknZV5vWg3ed8CC4ftVuMQjYJnDrkMtVL +a31AaGyx1vjrolR18SJn4AL46lDUF57Vfx5qPmX6/yczhMV0n5CvtwonTEtHdsRL +ceUWg+UakzBg9U+v9SOxF5G4q1dK08XqqeIWp3n/B8uy86/eAcsSZfMqGoiQ9t3k +qZF5bmYZU4a/brz5QmvqEPpEO9H1c6H4D0Y01gxeVhIT7kMyaUsLXoLx8Ou4Fcsz +YZ+jQGqXlXkMwjKdh/NTbPjZzkrwJF0JsBGFY12Sked5opcpjQca3MjF4WB4lGSB +PokbR4TTMd8r/YYSFm5C77f4HqTUUzvcUQIRUblxO4P6GD65frrIcK922fuEYvaz +//pragma protect end_data_block +//pragma protect digest_block +6Z3kBITlGBQ1queo/RSCimERKpE= +//pragma protect end_digest_block +//pragma protect end_protected + + +//pragma protect begin_protected +//pragma protect encrypt_agent="NCPROTECT" +//pragma protect encrypt_agent_info="Encrypted using API" +//pragma protect key_keyowner=Cadence Design Systems. +//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) +//pragma protect key_method=RSA +//pragma protect key_block +Atz8tucueABxi6tE+6GDTFGVUzFguCPXX4a1GvHwgkopw6puuI6B/bguieeIeHkL +tgEqfHMU6A0PrYo8SKDzwI5DlGQY/DNWJhbkmWmo/igpJ24aMcFurAskETQkgSIw +IvhTjwwxL0DMnTN0Nn82TOAVMnrBgcDSPDk3+xiL00APePbf79ybpd7wV8gc5FE2 +VkXmLpxK6HxOdbeNRXpD0EwIwh0rz9cRbRNhKklPnAhKLokzOFTALpd6HxvLxg+u +PXAhC0TBY0AfXEfxX9EkGMTXSRFuL4e/Z4hvMY2GFC92HLrzm+zpmFYIIXpSdqmm +mJ1+NJbHvwYN0VTqmYim+w== +//pragma protect end_key_block +//pragma protect digest_block +Hr63lrg3B3IJZh8a3CEdfiqq8kk= +//pragma protect end_digest_block +//pragma protect data_block +9qfofxU8gWlHm8zNLCS+VqBoZEIOR5k63yp7QPGH/vDHxQwY3utVDj0WWvYVxXsb +apzYXBOoIkJ1b5kSMf3n8GB0qqwrHuozP8xAyOAqOUQHDBSxXonyBPNC1hdd948x +g/wYLzsI/bPCJKLrMFzJRVGJh9wRtwfR6BQJvR3z1PqfqEDeBa1datzmoNoI2Kjo +XFSOh167i4WdW8/i90vpxoy3MM1+blEWNW8NJTvOsVMCaK/ZFuiHfYb28uzzXiRF +vI1fW4d5SGJB1cL7oGe+0RDzOM1jqOPnQelxD2fO4mAB8d8+R/yLZkrp8BljLw6A +TbLTI6l8DC45G6LfUTEkpC5x8Cio0jJXRvG8i6FGlZ/zIh6kh0eBm/JMoDqXCEf5 +F2SWDK/ZBl0FX2d8VOCKDx9x60oPjmi7E4rmijTXF8N1kJaDY4jtDxoFaVBaNsEO +6IkXHJqrzO5LDa30WxStDljF1y+CYlHCyPJJdDoMooounxcWFZDgO6HMmMwg3KMM +YN/UggiY+eqqQ0Dc+rDkYrKFjvWWyqCIP65/IPee8tM0WLaOiY7njKWhwlU7duY4 +yu29Twsqtw+9f1ZA9N8TARtkKOIN1kcoGA27eeGTH5wIu9U8YjdpxBtTCowMj5e+ +iRAolrHCF7RAoXtpe/qe45sJ0NegAWwmq0CH5uxvo9HDkpOU+XACgSBKkH8yPlbr +t9GnQtsncgQNJX9rVE0YDqtyIY+dqC+sVlBQ2QlAckiP5xtIgyvMMpaEaDEQvq/I +TmkCuNy8ZMLbwyK+wU8YErCSWjAqpW4DBlZun6B7MzqCUufawlj+vINZrmxIRsVC +ExUEGENIZ1EIGqUJ7keGU1iKLr4pgGGgL3DS66YTaWbQ7/mdddPsj9NKVNM86sGn +DRt71wH8JBVc8WkcfGl+zxvSPaFnmbDUwArG/rzDjqWCsHwThmhA7A5kd53y/gtO +pBIWf+FghpzCZylZE9flPeIucuA96JyW7gzoGjRYA2wBNlDc9RFyPC6ttWsNQ1OI +U8LFcU9BNOR5VYsff1nxQmsSIXANIsiXN817XK/ZKXP+RXN6a4LPfcM4m9QDehsm +F6Fmrsev1bzkyPWLHD3X8e4rt/KybPN660YNtgQNwP6BJEw4zDgoO3o5R9rdDlF+ +nqmEWoEuf8TnKO0/LtzxtG4NWPrzeUw0rq/zC3lfxobuirUXc+c851nqaE4f7I7Z +N44lhZ5sm83hYT01X4jj5P3mHT/Hnf6YyDtLqwoNLOs+zldRJjURKyGYfVEuNQ84 +O71crQOhiMeYnQPehkTIgo9R462BhUst6Alga2CEAqrOuy0o7JWv1e8AGoHdx0/y +d2R7VdMYJb3oBdeQRFdDpJ0LSh7uh454J5vsmosuv691Xh2w2RvyvgfO328qPWM2 +UHcRH40W++a8D+BA3Oc6gJaPoaRn4k3PqNDzWozpW3+RU7sW3CYp9dWbzVuSOzqr +za3rr/fwlF4rJMQsDcsTObQCEMoWe1msqA+qo7M2MwXnetPXC8xSdMXyMPVyQKHX +E1fztXqcsqMaGfFOsa/rauZz8BUilQ1+ZpUjYRHixJgK5y5jdBH/fuiQ0u0ultsR +ILPiS/FBdEssnJzoLJVN2JbQSI9B87tTNDLK6MI6BkHwZ/e+su2mzyjOtTadhvQw +xsLpV8qxFe7ZsG+E2zyQ5lJckwEi3JF0Xp3dG+Y/rMNds827rHLWobzc5B7U93Yr +Ca9Xq7bXU4qmh9GP8ZQlBhNXNckt94QUtnUz7TGRUCNvviCZ9965NMg3gl+sX4er +iQ4Wqa3teBJ7vHdCiVrE0YnTWnYgsFVT6MXpV1nxrzyuob+gtZ0YMwJHnsiCB/pt +FxYg9gizyTfB7GdfmzKFGKRKhQp+tt9IImBQcLT1dqpCxXlyh74B2Np1fvRZJzRh +cH/GyostK9dD2HW1w6q713sU4nIBQK1Zwq36/fDbDZrurRmJem2rQuLEQ6lev0bN +0Hn8L6zhH5aKSq+1+2zfzaR2OoMNrRZiW7LfAE+MHHaaxeHkNl6/V/WNj+QhEunp +NYEjhd/c1OXsiWsnvrT7AdYyVJr2jHpBYOzTuYxeqJKlmh4Lgwzgbd2JOUWsvRlr +JsbluNsI4WOxhe19Kh0lKIrI0BxbrWZ/Lx+Z/+Ow8eU78Yn4c07N0R6RrS1oTJRj +6kLrlUw9Gg+3LPkI5rxK3dK9zoosjekHy6D3eVBD4mVVMS9nNJuUb6YNL92f32VP +UVPgt0mDUrpbf1Yc2M27NhayqQciOId6T+r3obNEhBWwd9oASqpsGZzOFz130aIe +pknvhy0J+L5JhTq5S5hobrtJJLPMzxufsSY7YRxCrDmUtByEZ90OPTPsG6QyUX+z +YKpOue4veRHQwdhgvuX8fZA01f5aCt7rIwuROBEu2uZluwEPsQOc73oalutVsPrv +v/TTcSGX35H3bSQXWlfFJz+kUfSbGjP7/kDDpnhDD1NcjTgF2haB01jBNGEElel/ +cTpfXjAEd5METVt8wxhUPbIgevcDlriFEkZMbNO3HdVpGfNzGf8lmhaU/yPWCqMV +oeHceWYVqRKej3EmJbRe1r+zPl1frV6guxEMTejhE7m94aF96uCmXS1mIyx2FjbR ++9k+0TECRb+7ts1OgYNO9hGfp7Uz89mAIOMev2Xs72fPFhBHl5Ra9cEv5rTTOrdJ +cG82bLpuDtCIg/W+31JHGe5E1XIlx9u5NxxPjQ7Qi1W3yaiiGjiMdpXCa4Ta67LU +CXuQKxuqeRp9s2qBHPprHUxrF7syRKqSftgTydv4kELYMeUV3ksYvqhGKQuODshp +B1rKt3hkBlL/VDN9NZT3hBou/oy0adNp76cUgpnGe/HUeJBTsiSFqKjae+OMGqcR +Lg1KfMqR3ktm4w1VfizUadSceLinhgOQU6Lt5wk9cIr/OAE5Ca2g6lxNZoFF4yox +aEuLhYHbjnGbSKYkFW5JqNLtN3T65lyvnJu4wY6jD29ZicoAItIf5TqnPjK6mGWM +r4Z2ZjWzwZykCfDmsRscU/LRkL7OmbouhKyuE+A5ZnN8cqRAkL6r1PJY71iwC8Py ++kpw76iQAdPTWqZDM38ZjjPK+qxPfVuPahRA0PKTRH3ohHsMfxEz/vpR0P6EXMvO +iDchQ/1+XqdX82XY2KbOhzBR/BF94ZxeaA5E8tR7StbplMPSPLc62yzjNd2O8CSN +LaxO/vW+EsJQog6pLp3B0lLrMspbKknC15eRV4Czb5IQoE674cx/dx5aenmD66i9 +L5IdHW8Xwv4zBHc7IMmGFHW1EfjmOTUC7r4oz0y8RK7f8RZgke5PjIgRoUDrp7gy +Yll/DIY/GEyTFzGB1JHz7lw4FJCmR7Xuv4u4FaoXGtXNcCzcAIBnWwWbdJwa5SF4 +2TVGLI7NpjjM/S3K3SmBB140KKQoZ/bmIh7jKpcszmROcTnCeitwE6Iiin33N5Yj +qEA4VbhygEDIvMVOK8VVUoCscenf8Hj37dZMYpoQUy4FPUFH+SoE7wiJLrJVAk6F +Ot4XyeQeUphOmSLEbjC2eJRb/cLpafUi3oFj986gl13QxIbcn7EeLd+YSfC5UVMi +Nawqsehcp6vqhUwHnC9SGgDVt3LjhazdCi52k7S+sEMAF73hSfSWi8A9L4A8D+ci +/Ug8QgIVweVRWCobsnRKiipSXmoI47SztsjQP5RoMOrfXyZZkC2X6aXYyOzc9G3n +Zh172SNB2tZug15+1omT/rFpcJn5yCzKCoSVkz8Ufcdv/0gVX9TVFKvaRVJSiyeU +vtrvSeFZgbUpUG6uG9ZWbSPp4s9zbpq2FeN6RlNYS6IEXrPE2V/Z29VND1cLtyQA +w6NsBRGLSZj6lKqIAM/dWfEPe2m/7n1zsl/HXSjokZvcwKihyxa0n5r14X9heEkj +W9MSmaAU88n35JJvhKI10oSZ2R5PaAbBjcALi4eYehR7IUcJBaADhA8aalxL54Ll +wik7hsYHAUz3vFqrX3Txfn9lpdI1oruvDrB5EkLPcDmqAVVo672+H6Gzmh2ZlXkn ++fBL+v8Ic2I/UqPc0yUER8maK4CvRtJF3aEI31jdd0LhBPjIHXQ2vjxVk3LmMQxE +tXLWic4OSRcBq7k8Te9aPezv3Pu8c5aOaUCRJ1zzZyzs2Snf2CIkEDlorppe4+V3 +H2u3LfTofiLu8wiQNekoOs5Yw7QWCQAhucIOE0vU7HBZg0GwpwYQrhnYp7Pgvliv +KVXPBcLNlFK5r2peJGIP5PmmRWqptSxuCKw3En/NNFugn8rp2eWhWSlZcbO7uRCf +BI+DmA+5TJiprEiWnCJnZJOX4wBGINnHYoEesCRZWatKSKI1kg4NPvZ9X7QKA9CV +W4OSheWBNvZJhmley/Cq8WeY5J0dkOsv1iEq9jb1sHzikoIKaFrtioi1Hx7zbXg6 +I/fIsrM2noSrmjTCXbPS0iD0QZHQhMEUmuxoxdBXKWUmxHk4d2FJXGK0BVJ+SyGP +2QL2ug71/qJNwDZYlrjxVA0bZ8RlMFXAGnbjk9vU78rUJO9bv1HzBnc2E4sMaSAW +HWyFSGrh5Bz4kSlYsl8rRd9E7WeGKe/xVQiS6IQnBqlLkVgJmmoKAq3q851alnYm +u+alBEhZIKYqfxXA0bay3ZKNacCOJRW5I2bIRpzhlxeZ1n2Zmwi9fGQa/vRj/rLW +R131GUE78CZKXMHUvmUPO/Io+0mU4/QUS42FSfG6Iu6UE5FCCB+Sky0Ms5KjysxJ +/xEF9m3fDJhNhUQNiOcHBNulm7+SI4BC7TfLTrlm52ZvQ5jQDRmZ4gdWagH106LB +3ExOLK94V3U6UsGgexKOJwwqwZR16uaYbKOtm09YyXP18PO8PSp0916PJqlZUpxL +7jvCKB0in/+oGB5H6yAVzqDgTGS2DeIeN+Va78R1kAjN/zZI6pszATFVLUt3dfaT +d+lUTdcJwjZpa1b5WW6CjKokMJCXXYyPQSnZt8dLgP9JmzNJ0GiJ4Fe6/s+ECvRW +EaBJihMgzuKHwDs/Jc9sdP/vqOCxeDv/b6E5ZgfhcCurRj9OHsryTTuvXcW/y97/ +Lv7wl10gdbHmsQZcaR4Oqw5XDz27dLx67imxdqN0CN3zqRoMO/AZH2URMX+XZKVA +ewNKCm6K4UrA8fwaGsg275Xcu2hXLixQ5FvbhA4o+6VcBCKY77z8ktD7xIQtausZ +O99Bt90H8MLoALRB0HDb9vEgiG8xHn+1hvkXSypVJFL+PefCva5k2BfoYinFx673 +c/9839iatXe3jYjD0eXAvCP2dpDcsegSEPhLKN8+hHD3mfWVZaRN5LVweKAhlMeB +aY7PfkkQ1X8hSQvrofzwHNpfWu0Di7p6GKbusuV5VqOj4JgGvoZp/uG/I1p2T82O +eeXCfNsERoLHh037zhauRG7h3yLZIRfs7pJ8O6FvMcBTgudY1AyrreuBhtg/seee +4wQfjhUsWHXw1yZyNjXmmS52qcRvMBDMjZAX2faeVIpMOCc9j3zQ3gAcxBZ+Mivv +K8l6xD3DGmZ4lp+YrMDztmbQpcFblXnwofxauvsg2t0clhrjzUt3ww1hZ44EkzSy +AwurqYGId5D3ezHM1iKqW5FT4W+Dj5M4SU7hB9TbWDb/iCvaPehTaS9uYNkabQ+B +cuglOkzcQGBiKv//TFVKLFt2UyEpw3h5b09DWdJoYOGxL7xszWe63ZSz5goSCf9j +tIDZe2ttQrI0pWNyqbjlga5MpVSVV063wg/4Dkp71TQSxmdY5CEYn9A+z7UIN0YF +twTE/zV0yLRfXB1mXdvlAZ/vjZBWP4IdZ2XzpVQ1bOcb6WFVGJ9DI8PyUltBOzBo +BVFFvr1+kP8pexkgG53MVen6+IsPV1+FHJHJNWxMJa5BVYX7WUYWYJOTEF2S+p9s +mQDybeg/Y9PVFRw3KE1VF1d7MAPXToYKFEKbiN1JspzaGnPps0aFzFSCMzTVRzHD +pRDYxmE0Uy6DIltb1MyMZp93uyasUgQFpf0XaE6m/0hoS7OJqvf7s8zOIXFRyia5 +PX1OG9s3WAOdkF98a7H0IhBDnx/22VAN0uLid0zb9smsA1pSwhoYe4jEuBHKFgXA +AOGz66cdIir4fnRo8O045l89Zf4Xrg/u0XwiEVzoKwrFyuxyWPhXliwV0FTbs7nM ++rAHOixMa7cLvHhd2xhMTAtKo05CVxhGYSgeThwNVSKz+07pIc2Z45ynacVBGkh6 +/Hwr8Vjl1gdK+AeV0uxq7u6qLKsZNwcgljs5GISe99JNFCOgJcsWgmawTaslHm5w +L4/Ucjwy+RDBOhFyO9bGhnIwBj7up2Z+RPldJbjlsiQ4rmiDduVNrpJx6ma7ofyQ +DVhxiWEbXEIPZuMxkK6dvA3qzHWlolPOcn5qiCWwD7MvGEHhQi+hS37VzjliA7UO +KCNE+zfcnoC6KmtC0KQqIx+j1vYwoMuFa5gBNilvRtfET+TbX7ddnJDRhSybqT2N +Ske95zC9DpyKZ8zf7u2Ntsy0af5l/faT772ibMxCqsNpACKYc6U/2Obn4PrNfHJz +tIyG8xldeKfGU5lEZ9sFgZBvhmI4eRRPT3pZUiJ4xT9cdHY5FxIUctv59kh4XanD +5rqqvRsODUf9wchMFptKT68CzsJrqec5K3KT0IoMJHR7fVeD8caNh6EESN44l11N +h+casOGvf+ynbVezJ26vXp0Z28c7FUxXVPsT+O5uyPNbkKPO0qN0mR7PtJs5KfJ2 +Jg50L8hq8TERElkU49A3/sDalCAZSEbgntzr7lK1fPWA8ExCh8AKB0atTHJnek2P +AZXDpQIrGrd1lJVgRYiHgrp3yIujBPRD61Gd9DW/L+225nxizLFVaL8sMBIHCSLo +/x0uIXxcemcqa/2H1HtKU6I6RKVGR6I0Ea2lA34DUZpwTv2tD7LGnvAsBC66achv +XHD4Um3v/SupNKbBIpIntamqCmhKqHE24tLBic/Bg342v6k1O7sJfcKcu0aA5d/9 +l0tMYFNWxITDk3P61f3Axq6RKoScTOGOpCrdMCNa9c6hLJCP1QSgmMGtoOXQzRCh +MtuaURsuVfwLDPIE17B7WY8kJ1lxcimJHY7w3B9P3zZjAB4uonCHzCfZCazQMIEE +C2/VLA7A4iYrHbcI8/YLKH0H99MI1sF5/kiGK0zs/TOTTKeLJJ9QwuY4I7h8P8KG +FN+kzKUNlIKknMNfrgGAI0ra2duOW+WMN4xSguCSYUI7qia1aE2ZlUnFU58qfoO4 +vwHRk198UmhUFCfspAws9eNn8qCpbkVOPRvKDiNovdRBhWRPw6U+LSEhh42s8wAl +eeCJoDY92MrXPorD7Ae6mXZGXOFjmMIeU76NppWpQu9WZtMfgprk25U11v3fvJbD +y+ohavLx1+lqVPTFEmK0zjo9eUfiUwuxtnbS+2FAgph/EgPGMYT5Lvn0CWsbTF6T +vBzn89iZaUDBVgZ0rhxRCc02t/PSbNgVd5Wv91l5nWU5rl98r3bh/MBKyVwq6bOq +foVjDI2z6/E8qR0KNuGyflvVabFjeGmHYxUHLm3GH8P3sHjD6AC7kFDjdmbzbWJU +hO2OQQIXSfjeJ5w1/fb357eKOmlOGorkjhAwbxbZauF/5ZFyfB0rfi61umUR2IMd +03C5K7JVYrUFOwdlx2QIpz1ROPpzcFdW73gRiZy/7Xa6yM42LBrKx3K2krYPinQW +SzHVSQENpIp9p4NF8IdpJyi+Ak4+B/w8bceQJ79sdtomZWjrtiotAdk9l5geyIBS +aiARZZhAOGeb1tlBuisE0D9WSf+hfbx9m4Va8XmMa2awQ8c4aysAwipfFcDSokqe +0J0+yjz8IhGvC0k1MlsS3nF1xSckBFtEQBqQ85d9zWBdDMBsQkUuvDXQ/PKSMecR +yKLLBNWEVLe4S/iTzc79SEax3Ik6HKFozawETA+OZqcVtGAhM8YoxFctxPYg+uXD +bWUzV/Ja54HXPNEv71aGMXmtC9Jzg50ObzU7njHdy8Q5cl+4h96sX3iC/8fgKxcV +GxAsVqirR7VXVxne0efzFNtQFcIOh9vPs9qHN5BCoYu4bXvSdijjCQqjD+8P/Wl6 +K+Qu9l6ESXl4mb5i6xb4F4fjZk+C7uKt8rM/bK1fOaxx2QMzf2f4GAZjfK2NoLKm +vDKNU5ihfZai9xIJqQ5FVUHoQzSQboee/ojE3neMGeVPRQgsBnf9v9E2c6TdK+Yd +fuQWTePp4XW9/zE9qWsKaYHLxj7oxKyPitOMktjgTaFDoXeX6DZxe4Od2r4fHKmV +rrtXLjB6FIwaByaXWefvP3McRSxMZARdgIc4NePBrPWDr3iKJtsHuVaXNYHsPcsn +xyyq2KT6isALcOYG1eAgyPtGBhaR+UCpAi7VZtjJD9tRZF2vwkjaDi5ryJ8L+oCn +b/7J52bKD7OwKJQ9m6Y7q8+KVhpkSUPcSDnvBOKosIX+lEN9SnKm1Zjw1xYPPDZT +b469Q5d11Q6yIYhLat+5d5x1MXe0CnM6qDTqj7odIgN82HfiWakPiijx4FVOpwhE +nU0HPm8huYJ6tKVHXcr0w27BViaPS4liZIWKe/zyOUI0sOXIQ8ycX55jXS1X9JQK +EcH41tzIcqRMZZrUqZMgihUivPdTtXZRaKnaRozuPyo= +//pragma protect end_data_block +//pragma protect digest_block +NoNN/+HOL/6XnNdLy3d9uw2O3HQ= +//pragma protect end_digest_block +//pragma protect end_protected + + +//pragma protect begin_protected +//pragma protect encrypt_agent="NCPROTECT" +//pragma protect encrypt_agent_info="Encrypted using API" +//pragma protect key_keyowner=Cadence Design Systems. +//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) +//pragma protect key_method=RSA +//pragma protect key_block +AbCzhd0qNN1a3YD2COxnxD9tA4+Q8AthzDbzjUhGr06Te3TXX9nYsgo3lUXkiQvh +TCqgcIyaHSmj7N4taHx2OHQM65fqZ9Kxlkmcs4uwd5L5keLAE/xHBK+oOX+mAu0n +wi9qZnDk2POmSmxaLIinPJJLXmbOu1tKcNUqryv6jGSZqxHFGYNuIrCWEPHGhH8z +ScFwZj1MH7MLTBso3FGbgqoMfAGglrHtPPIRqQToZJ5UyrJ5OnliZvjjHUct4lAt +oxuezsQeVftgh7ARe0q/34Uw5IB+tFu0T648sWtQrbOuK2lirrsT70RyQVaFNJOB +afEEkSjZUwZJ8Gim6nx7fA== +//pragma protect end_key_block +//pragma protect digest_block +ANmuh8+Z/fi0NpDa8f8OOgJt3vE= +//pragma protect end_digest_block +//pragma protect data_block +W6sMrQihbaMdI2RPKLIUTNwA3Gc4uUMkomlzSKCIsSnwjupA8mz6SVNbXWxoov96 +Wq6a1C1N/Dm3topALugkZTReuwtDwAKkfPoY/lqmvwI/ZbudZA8SPZ7O5w7UAHMe +sOgMxf79xE5rvAq4xKQnAM0VLBqegLEUtz66mw4srVKttRDNIhNDpaJ47ApsJxY0 +SQs98wsAI8U9feEarxvg8T1zgq5eiO9dPIa8j8lwI9bOmA1ZkuwQZ9L1UPTfDf1A +c15Aqge5ZRwClqgCuP4LrrtlPbdba15wIXIM4SrZmkT8Ymb3H6prJJvzW+LFOfTt +7JuJ4TTuwrO0F81xm25CnwSiYvzR4UeaGwMfhjU0wBKcBOD0B4XYxUVOVpqw8CnX +w7Pf4LLrSwmUMgRCHfTe2wSRUlT8/W5lGXCCKzTIeFc7e66Tv5F0dVQoTezOretn +IdrxIs+FluvZltCHWNK7wTsCYe5ZF+E1BYE6+PPZrnsEJXa9SeeWq0cssknmR14T +miF2IVo5HoRSlCrEwRGMa+oK8DVIE0ohMX/7YORCTp3m8Hco5S8vFq26NBv/w2m/ +asV+1/y7N6Suk/PnG2VEwnjlliJf0CZTkY1Cgovfm6yzc1diAXGMxKdb0HTlPcKH +U+4yv2lrROslwGbgT99x7R0pecjwY5Z8v8jUn2xowXnuH5mtNAUIsWsT63+/l2wY +hzujAJnunUhPzEpiSPMlgxcCnQnZy33MXUf1ZtkooAtEfZt98i26L7QcAjDZx0/F +hQW3sMRyKlPh04dpEHWKW+lsYwXVPVIou0TbEVwnQ1rdhJH3aq9pHXc2TVBpLjjy +zZQg6ett6jU87uoffZXg0TRVVGGMH1KprdoGZR3XRg/L30ED5H5nBQ7l4Yuf/7eS +bXYec6xDUGxLDKG87iSacHYFC4hsTd2HRDggVPwAwItZCP2hsO5nrYWIgod/3ZnY +OY0gaLqbF4/fZNKr6KQUVDTP1VP1iaiFVYLNDHZ3Jw1taicnfUkIgpuOcieXHL19 +1FQi7ljYZDHDLBdg/UpR50JWsGPSXrFFCyBAZdqu+Gl+doYXRD2QWqCbrHr4YFce +v0DtSjB9EUvQXQaUfj0zBpFBnmQ3alpUu3TttlGuRRwfNtnf71DclD1tqwPVF6Ii +Y+ovFZTAl6984V5t6Q9ioZWc/Ru9tB2K+Cl5/pkSCq54UMVJnYVM+aa6P3Ssb7dx +45lGpqjNKrfQ89TN9eqo63jDAKCwGFiuPQoUxDunlJpXonbZVy/UhbdtMqIW5ESI +33D0BeXiqgHE+KCNft8aBJFM3tQ8/ZoN4MzD6ZCHOuurrxsGUz0aS1SongSJFfQX +0GBsRwhzaoEgkVqAhNEkLJHG45LSLUlklYLeD5c4KWZKSYtggqLk5g+TlK72akQV +eZe/gvQQJsNIVq0A5fQoOWXoRXmKYtBSfd9VlXxbImc+Mm6OAHDk2LsYG0qNJ6hp +hPM/c2+wML7iK0uLJX6T28Gyw4dvKYEJT2pJn/RlVlggOV4vcO4VDaRLu2VPO6DY +1ne5XtWtqEEmQo6qcjo+hNHKPaLmZeuiHLLfSi0p9BKd1E5PwRejhCDp2Tl/ohut +pGAxleOWkKh3F1p5lB5/oRievr0g3KiIskFHL2CxJvG2olL3OBmeL4x/QxELGj8N +m+1cKH3PsPsIbCPjDFFVLC6dEYQQ4bnY24/o5IBwxJDUm+gaiMRVX+JaSE54DqM4 +VkEMQ8d+RTEcVlORJOYYRs7bNdH6s4bIz3rtH9cZHHRIBQAQzhe5nTtWWMr01dXw +neNWPmRn4tTkXzQYmqazhY0JBUBQyyIUNoR09Wg/kkXaKaNPCxzzpoa4c5swx3Ct +WbWpkOf8uqehUOTyZ5jnccJItbhFwhV2SnbVK5RMEn0= +//pragma protect end_data_block +//pragma protect digest_block +d1Onj9prOJmn4JcwcCCC8cvvcYw= +//pragma protect end_digest_block +//pragma protect end_protected + + +//pragma protect begin_protected +//pragma protect encrypt_agent="NCPROTECT" +//pragma protect encrypt_agent_info="Encrypted using API" +//pragma protect key_keyowner=Cadence Design Systems. +//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) +//pragma protect key_method=RSA +//pragma protect key_block +AsnvdlQQG2G/k9b5qztkkW7Dv+FAZiPWR6QAUQ+DxyO86/iCpkBlRR6oSVI7Og+p +9CtGpeXkbt4RrFe90nWZGjqvKgB7RxmhXppMUa7bi5yTGg6r1eOI3gAVzAd0YjMy +25rpc2ixPCo14GQPh++XOQ9s40V4LBII16ArZidT3TUwXSob65RLazB/eIV/sUNy +5eBEKR7/xyx/F+evqlp6SnUvcfFe0SuOopPUCAACMa/w2N6o2t6qUgzpnKjvfpyy +aL6wquWnMYxt1ZWghTs3ESImUnkDXkLHeOrJnpqOt4oal8yNil8aDRGPYogUCq9v +nwUaPfDpVSeVWP85S9g4tg== +//pragma protect end_key_block +//pragma protect digest_block +I+eFsI6owEDO8y+cCD4HefhLDZ4= +//pragma protect end_digest_block +//pragma protect data_block +YBr4Lz06/z/y6NMgOg+/Z4NSGk3d2hW5fBB2iuvreGqU+603ueDP6H/nW0GnOhQI +Xj/eGmbuXNLoAWPJ9TZFRHWxyqmOcc7QA1t7hn1cZc5pYVhlSK1YHkPzrzHjyBzw +4Qs3YLoyQf9hdSiKrEunzJrGyuX29UNzxDbEPrmSqs5p3HAkH4T+wKGx7HG89fUZ +RWK7+EVNWOdrjJB8czqOHNBUNWBPHfBC/PvM7GNNXQtV881N4wWJp4sxBdn++mgj +Iq4nQrC1ruOlYmYCAUgLyQrnyfwkcKXJ/UuX4Kf1y4xoq9dVINO/wU0cikRwvFrM +Mo7eNVLcm69LHFs4o580/Jcqdq43eNROGXm0exZGg4cq2sl3yf7ZVQ6i7x7v4Qfc +lzUZ8lRPr82Y/lXgLqBl9RGT4ClceSJ1b8NWmASpE+/erXTdU0kQYy8QDLCqa7OQ +cgnFXLpZfYu/vbOEbtOA6EYmhJim7zj6jxBVjDL++ci43I0oJys696sf4VIReENQ +g4xIg3yXN/+a8uoAqLi7EvjqzC373Jea2zOwBfmxzbQ8QsXD2uymeTcaNWTvkQiv +vmeof/DqISbjoj9RqraMVt/7Nn800xgtQlfS847/ToSA6IFE5dwAWUNTpG4lXjz8 +FneCJduvQRHYTpyDgltyDQ7YFShoCt7u2p9AAPAzJTvfn24FThPFJLaNMp9bxJMx +/Dj6ZzxyBEKDWIR5iLTdVLvSyyqVeZxqeHL9Zcwc+Qpw9rCRyavlHBwKPsXeiq/n +Mqz9zyuR1kHvRA+WdESlZF+P4nQUaVPmR4r/Odu8NJXiD6eAWbcbqKXHca/1hyIK +T4oRI3G0iUZBKG5gMkjhLAuArxSYxOcwYTzeob9IArQrWtgqYmdZltSttLO87Mhf +6B118ZnS9ybnoUELJwhufoYKWmNwA7SfVBL74y86t4+tEDKRJDRURM3yfzlhwGVt +N6RKsIMAvX0MHrIGez3Ob/e6LS5RDxXvxMOOyXk7zVhzOQLqOBKjcoKsUWqV+si7 +fiyZq2GyzAKSvfhEbiHxHgZaDOJTN7a6xhXzy/ZFcN+tjkE5GtVOKuU1avyqvj1+ +Ijb5FeAhLJujDtBTCjqrE4plAtSjND/5tyAibv/SNclMHAxVlyVzsn+UDhTn6CO5 +V6a+cJSiJarGUf8dOexjId8GB6LJNWg9JHD+ltpPqggwtEgxYXizJcOuNr2LIPy/ +DdSYDCMJHGceEXX45h4XI0Lx9v1M/DplJA9WcIitE8WRuSg7e0Z8J2peCaJV+05R +nrN52K8FSbHlCq25kYzKzkibydmKO7qmiqI31SB+42lr6NlqoWwUmLf21CHtpQkb +dzYuy8XSNQG+tFSxX9f+jwS2jZRUa1yUY1BL5Pg/ICVoGSpAaqm/s9mfD4fHEGT+ +/cFgINXsA5Nb6J3LhhVayqpJ5Mjwfkr47LgfAiUg7g9BR+zna78J8YwPlN/OwCZZ +IKyK2McobzcGu7J7Q4cXb+TH0thqCUAsiJFQZJjiVDoHQEuSen/RGO36py9lcK+r +A0QCdwIj1WMzO3LO+kN3vqOrApy2Q1IUoDijEEumzd4ezQJCD9nmEoCcBsnwyS0p +Hv81m6Urhm+Jk7JJcWV74NUewvHW01hdOwpW5WJJRj/hFE5yv6Q8AGCTgDRaGb/s +OtH2EbvcvRfKcr5y6hkjJj9l2IY7NvNzSIyF6EHlnJu+V/CknueAT617pjH1+JsG +SeOmBSr/ZNAVaMU2Pdtx+cySuNUCPt+5pr4s7BQA2x8TOr1DZJeJ2gKYdPE9Wzcu +c1iqoSlvM48KJEaFdstAoOfcugw+U1Eson4PjGxNF/VzPbW853lFshVJKiebJ1nD +E0OncHiSrARFRIPJOUbdaT7tUYwfT1n9a80AvfGcyVEYGE9vDHp8nlBzfWxdRfv9 +GSTyVhPhzdacqYl/eoubnD0WuZDVqxApff2HL8E5KIOA1CBfP1fiM+7dadYibVDr ++sHvSYcBzC3+WezA/GWW0FqASmzIEJ1v3T3HqFwTnJpd5r242Xu5jzxt4gk0g99c +Lg54HYsJx1qYtGP58CsB6tAoe7X4ExZ3Y0Gz7/z3cxpkrLqZ28aRG25SczVLn7Ec +qOLMDtELRpsDBbSkTiqoPLIDj59vXN5U+UmhpJLwqwg2OWZ8BOaOa5V8oj+lNvhL +rk4VkHUH3+ahEewd+rnp5lXNbNfEPpyoQ+duYnEKhwvxvxxFvN+plPFYiXX/lMnB ++ZORLI7AtbBVxkA2/F8tPQa69ml17rLWFZkcnBUrg4aKqk3iRVOAxpfbLCAr4zwF +pVG+l6zcR21YNmKXzTQL/3sWRsrIJTew/nxawsk5DTQ76ytJFcQ72ESCwFa5B8ZT +oD8F1d8c2xyqRVd+KFWPXlADBemmdpkFgDfdGQNW/nN/Hyg4+u1oKIKu2DXl3cSU +k5Y8j0NSLCEaGxMoXk4WWtfKo5kE8oY/A4hy1fzPQhFhDRl5jh27ll4yFkORSvC7 +UQRWWwGrQe2OlBv3B+rDtAWxWR5UGowTxP8vLy4q9f5Ipq5yw7l/yATwhlMD9xiA +y1Nfv6De7BCZ0OcfGSBVW+glsdmowsRu5Dk3dvKHv7IMgXY/OIXao7xvmK8KW9uF +HWbckBz/+x1oflsZED+xbe9GG8TXzLRKxQTygB3L0m2TZd7P7mGhnHPv7fDN4DGv +s38bK7n2MAR8SMh/bIH0VPZ0y6z/JhoBdNDCS+D2XjZXo5RZttjVsLnfnQPvCsdn +lLKtEeo0McvTLMCzm6y4FIZOctd2i1RMzrOB/RncLtWvkemRy+6csMO8r0/wrXX4 +JlUFlC+813RooH9FmOEIKl0M8Ft6DRpb6W9Yr97bbAYQ063JTW2gqKgzk3l0QfhI +C7tHrLMGgAbvI21ejR+wOnI2qGPjm0HufgFAK7DMmNQuDqJ8cTb+EVzC49dWrXjt +IHkZvK+cjPwgKKbAvqkUoG2LKfo5A0RFkZO2JSN6KHPBnvl/+Hd/8leFDbIHYSQu +x24J47S46tFqyxoA2NqkndUkkljRdb7S9fn00OICbVsO9dcke/u2UXKMBFxd20GH +LCYyQV4kxkhXfSss5EtMQHm/p31k86Pls/kWWgZjGTeRwj7oE1W0uTYElkJ8dy+i +OFkwk4WO643nmvoWSxq3RHbZJnGkCOIVvse87G+QtB3v5I99gB//M8LbKvqrUm5N +9//8xMLdoFB/LRP0XKKldNjbTs0qADD/WFYxYb2yiItvXldjyuVAkt2CCDAwR0CE +1L3CaL59rGFSx9pSSrQXWVy83eq6X3LJ/sojv+C8Fjes2Kcw2DAtNj2066y0d0Km +NFdlnSTgfdfjTALWVAaLR2No0gvFYXd9jg8GVnlkfpVOfMD/NKK0iltGKO2FDeWL +TTabimNnu8GD4qyji2pofuc1gVqC6TK82qJbS0T4nZoVGPO4dAIlhhV7Wkf5fPSg +khJb7BEV3cnhW8gf8KOKx1M26sQT0uf9CywdkbdAg2ih0GnN+ezI5IHVwwUoue3P +Z/TWxxwmVbyUj44rD3XmgnVD9T9eIMBwrWC5+U0w8V19dZNvO9S3bsaEqOY6pAvU +uFzUNIUAe0l5GcUWFHH1HOvYSUQkzDmI4EQabubaWf35WD56xo0UE/XLtQYfSZcP +rB1TxQ52j1bEMWTP+2sBRnzvjqHVJAja7oQNnNls77eB61axJPkp+IUw0ItE3Fxd +xSI4lzfnCLYpu+aKYfybr+H60OjW732UGTjShJ7hrZq3KEO7dZTc7MYg8vWkUdSo +CQsExTFcPUg683DM0PhXPn39Dhv4sX+I9FcijP/fAmOszOKsaWIGInl5o5W43Fk4 +7KDOotYzSpnI+blI/EoaO/BUSC5iUK5zW/pGYg9s3moLfuIYgkI7roV4TR4Rgj91 +EIvZVQLrdgHty0dB99Upfya4DQqKeWf3f5Zs4Cioj1RqGw+W78XbWj/0wpNXVB+6 +MVs+IZCcKjRQ+pxO/JI+pwwqXLc5ve8R9RXE0etHft1436PGnadlhhTW+kt+4w85 +lezy5o+b9Gcio9P2XV62UmHoiiYOSwQGNlAMVKihWvdVsQj6toAxpCIBnBAF+5PH +K7+/VuozdosRFKgsuZIWEsach/s2I+dzWqbf3n7ndtwaA2/RyD4zm/e70xzt4dnB +qxKPQcs2XuVpOaFA7Hcnv4yWDnOptvschh+2uKlBviWKMEGAtTOVrHkqOlPxPNZ2 +RMfsb+GcTebXyeK0JYSPRv5NL6KdoTNJK1hsQxU94zgGu4OrK0ysSwalNwuCOHGn +7UVA9+JJ+izkj6hesLbAhB5z/HFIPBNKkM+3Objul1ZU548yrNT1BBdtdltsQDQa +CKN9CKKSph1mZuPhpQ/SNdYFblm8PzzWOi9mh4opVLErlXyjHt3BPT1WDwp4AfD5 +IPZ9mHa/VhIjpL+8NgWuSSWqryC43Kgzv69njNt8qVEWou5nGj/0iXC0tHXv3D9W +m10EhU7wI3hXuCpji6NCE3goEiMJwNkm0to0d1auxO/MdTxzZRfxX1HCiVB+zZNI +aqrFRI7eRvzd6FnKxd6UxJ7F3uyi+IOdv3mbXke2Dt3s3sxeisABHC+H9qjVM5/V +HGG8er/xRlOk420LtE3IpO7zvbxy4HHgqIE8huO49sbenDNQAtHOKkuFNWsDVv83 +AZEm4neKPhaLRT6GIWVl3Rix63aVpeJm/av5YYN15DaYNHmxRWRTxUgJdOSw4uiM +A/WrxXh7OFx1cOx4GT8WdTqUPYWMPfpPRF7wN04SmofuO83Ix7pdBoip+yVEROEn +7LHgkPd00uvM4v3pwxe2EZH6DH2DH4OHchnen/aZGKs3F6kgMs6Gh6Lk8/SBDGo1 +SoO6B1ekYkaW/pEY4eHbg22Uuw5aGhLyjC1r3xA1R0+SN4X3nrju7+zOIKZ+vKiZ +9mFvR8dy201q1v4+EnXT901tqnEtc/D935DDHnqIoVJr1jBlfZim7SHiRQLPem5C +JYGrt83L5cXqc8XwHZXBVSuXyZE+mdggzObYkNg8tmz7pI6Q4p61Hiwb//rbYRuk +NjRfkJCtbRUu1S84oUDscTmdMdOBcGZcGvJJHs5OrmCmB/pmLgt9oW6RKa+p5XET +AV9a6WcyXSIBH9i4vIXOycxvXXbAr/oXccielCtBymdbLbsQePLe6y/uxEgi5JDQ +hoI+C1Xtb4Qj7QnMizeS09IJJp7M4kO4qFLtgwCQSwJkEyksvJtrv4HAZsYURvrz +V7dLQB2XDp8BlUMIlEXgSlO2/RJ0ovfYQLsABXMlM+eO1gu/NL/tdmunyTqp9WTx +7qkepX38TILxa/sBAxfoTqqf87twaIt2I7hbpNZWPYKFRCf7Jlpdhen6Rzd+KoaU +9/BwqD1wopGdhW6L6rVB6PeP0W08xJaKiuRUpj22+w7L/vD8xWsn90Mh3Q7pWukN +oMdKc7xoy/qbhZvekzE0JtFmt1VwzPcYqm3V+adP5FP0IKEz30K/TKE/H7FiiM2d +2K9eP3hxwm0qFeM274v+Hh90V6ZnfRiY8Kr21uLn673ni3zxHdwlteVL1cGku/Sa +laQUkoA8Y1sTCZXYgs792r/Jdvr2QMa6KW6zXInnFZhfWk8gkHbrEQ0D+5THLTxt +lYok3L/zW1AZ/Ntkenu1iBTXKHUhTsvo9+8uN9u52GntaWett3l4vZcUB72ONHGJ +kFThRe6drEb3o08cp1sc6oBQE77slHXQqIgPTnO4+ri3YPMc4vb4eWr8nmtgRJHX +2J2fe+EPeiXlZ8bdnt1iaNAXfd36TT9aLA25EPIZB4LShTojmU23xf6xkOIEbEFp +CfawIryZoOG+5r2ZVAnWKv2OJe0NSu5nXOHX17glFzTLK6PPRTTJTBB2+g0/Wbys +gbJk+9o0TDBDr0VpRKpCAb3REpG7KPBUf2QKmBsdig6haaBOJvjUHuConX0H6knN +maGVX+6jvDL0rjz1I+c0gmBkm/p87Mdq2wC0F6HbgPXKsVT4NSFotC3mR/10TpIt +yGLqcG78/ZZgy235I+WgYKX3PSVrGcEFbw+9ucNKDAH9KbCxRU7R8uFNSRw3yTcA +xunfn8IGKFvgLPM4iAjlJGIhG6fjtHyd1L6PzahCNoPShAad6KkpdjuMZUVkV/Ya +8BULXgwF7r1GVNd6YlNxMoMHSCuu/xA2G5+UyPxHoZSM3+8fi4q8w5ETIDXrRn1f +jN3bIk6K+OtALPGwcOC3aax9YNSNKxjadgd20zu/ysiXuvMaGzk0/d6smWvgEe3K +3Kb4go8NkG4Da7W/J8Bg3A6fwm8esdQTCZ8GMz+vibi9k3ofCIcJFZ1oP0NiYtW6 +8E448CI0OVKlDnm9dqBxbdWZcsW6kDnQvGE7P2tnS8MmQcXH4L/pV1tWv3ydaAQS +l2RbiojJEj499ql7ttYNZuNJ0I+rHin32Eg+Ihxm5fSeoFoI2ihSKsbgLPiqGF2V +1ou/0pDHRt+ju6GKts9Igpcrnq0slE71lw0ceRRCNl/FfwjKAlUuR6eQ0EI4oeQi +/+xEj2rSCybFbScrz3pNWTUrruR38oy9S6YNj8XNQRJcLMxwOJ3Ni09YdKLPMXnb +wWuYvCy9CVfJAs5MgZ8xSoBaXFbPFCmj9Pm42iIHpGPbf6rHihx4zBa3W4CrYXO9 +vg+5Ahu2xIvgv7drAiax6rpwFKC0UNo+UpoizLjRhaMrTh5mBUlGHkXKbejovZbe +ny6qbj7uoKUD6++fga1p13DHR35JivS4I7ddi08QRsvxuk8L42wEvIUVjyeIsUlT ++1PVqRBDZZzD1haK5eAF8uHhehupK8D/7ypPbV4Ly7IR/qDo9VvExS8iokCiJRak +uiV8uwJmhUxM+TOPXpZF+hrvWgq5LddGv6C54bCZuUYXfzqybJo6Szku1nH6KbVW +fanloeD39yh2bptNX3zJ+vtYsowuHCSxml6AHdYRaxRnrFKjW3sjtR8yADM7dkml +irPDsraNtaPl1Unm6uuLJawMX/crv7Fv2LGUpfyrSfC8MlPAh6auQSGFiZR66u5w +kUrN73r2RN/F2VlVvB4dyIwOve5qhF/T9ExNZGTZEZ2kl2OsatN1NyxcR2yZmpaP +DphFMDXg+Vk0mt6VxEdO83oqXsXqCYwObyxEw4F4tgtQiLfJ23SDWnUO4uibmKFX +lGJlckrx8FDWrrN1X2yiJTXqKPT3iovuPD8hLs2E9idjQR1IqhxMG1sEwKdT/u9Q +0kS9AghVVPmXE/xnO2kaTeZbElpG8a2DuZaxlDqVwmvYdjtYRGiuP5f+lzfkX70M +/BoAdW8QtSaUCdlnWnTDaNZXU3/eXAJssrvPylIbHJ04Bel9cz8NZrS7QryiojrC +8oawcxUwWT/htBDt4LPR4IpEkFTxxgaNjmQI0za984wpwW5s+qtP9Q25+3spueKf +WgiAS4fNvRU6tsHXDzJMcQVYyC4tUo0s9J+76DGwyVM4Qb6EqOWgGXgPCSaUo+24 +UuMkQ8S2BLQdehw5Fov2+rED4O9xf8kmEfh6HwIDjYjM6gJobGJ0l9BxUZY6vSEd +tG/gf/obT7MpyDpnd+wCGALy43uJQ0CBD/3CTHf1d8cONnZxNJ3ItAzJF8UQMQEw +OlyI088UPmLrhspk1G2YsC0HgiqJuf2HH3mWc/nGCaEbmhkNW1C2+N2wlOGUI56Y +Qo2scaeMN2F1Aa5V1yEXlt7YjN+DbbXswbqnQX4qrboQzxhB1J6839jgnXhgHxby +ev/HAqMBiquncTaU8zQBD1PHexiyWUQq+DuAGKL270gRjgFxBsxXgqTuexn2r89k +wMQZWZVN+j1Ago8AThZ+Ce0E922Gxjhqa5uRla2/8rk8ytD9yw4yqxkX8cBk6f1z +Y1anReflgcrLKjmT+FO0PNORDoQTJQ8EuNf+viKuDj5g56XwRFOj1O3EHEsOPrZH +dyoSWNG7t7a8Ef194Aa1IFlHDC5ULhUzDzeyx58KvqPWFTBCWLHcZ9qU63WHnstP +l0uKqVLLRHV5X7FROk0g5ACbgSXYR5otV+S12cN7Cd1GX5kS8FPH3Mu/ZviJiOn1 +S/N6o9Z+MXMaN/IFNX4WP8r3/c7ls9envRCNeLidGzRcfhxmMorsjfrZpz1/i+WI +Wwu+2rxc1M6u5J0ZD0c7S68vRo7+BkGTTjiV/axcYwqlXLZzFu/b8jORKJlwDZv0 +A9TV/gnMweKrtLJRLZi691x8vgHQcSlks4c7e0s4ZYJdUb8FxCh6qInip9F7nyY+ +sIbZWb64Vaz/8IPJ9My3oinvuf9KZg8YLY5UsQ06rzm8zNsaWZ25KyT1B/+rIwjH +6GbCZZxelwW9c0o+zzXBDKpJ3mMNjUydYQjJuaHY1ICn+mYxgTOPoBPHi6IvsxSR +FgJYle9er/oX6eRKwx8jBdi1dAaCnIhEOqUBXGJ922SiyXRdidXll+rimeOZ1YkS +Oc6qsbvp8NMiBAvapmBiDCPeySUW56mXswhNE0bpbKWnLkv4coyOzsstpb3ySOxN +IrPMAT4/KB/JNEFMBGWEbP4QVyXWtme/Qp6Cb+yeISwY/8yAI6zjYLSUCiCxStaT +6IVbUqCPpfSsAnH84L1mqUVuSdCYCTyws/Lp7SWtx5zbpjp8YzMWP/K/8S5NZOZs +iUAfsI5VmibCcMT0uRqIHALLYoc+tGNiu9j9kgor5wNcSt3jnpLWRoO32YcZbwPH +n7FzMLSoexqXxS/HnMErelFksHHIFQhzC/MSk5bK82K2qP3z/d5sBy6Rx5umRhkp +w9UHRmUv2mPNVKK0x1C+JnqXnFUfGryjFS+rpxX7hwgHqaYFlmniFGChZg41IU7C +fh/GHRhL/M9m4o2/gRkmHrq/DbXP2t7cfU8nbiFdKYcZZPSlkKhhHfrpWMcJ/juW +q9R8bk9N/B98XZIyZfxM1XwFqq6qCARRzBDCtLKST1uilc/i/TzWDB7jMGIB562h +W0v2ROKXNWnPmbbFYAfjr4skV/hCHcrWYeUhQsiFe3GsaQ/tNuLOEbh4UZk9awRQ +RNCoR+5VEmN080WR4lcWGEC0U1GXpGczQy+ZqTamy8NwN6ePFt3J/F+HoEZ1nNCS +cVPWqIo9WaXfG6ai6KDKDP3PLljN8HMjMXqY7k281lmIEVIhiHiJCnFSTJ/Z6yS1 +7NTFuFPCrHPHHROMOzS3JHdzAs5VuJu6UrdysbbLzwuUzRYLFxN5PMhbwsIhjc++ +Dcnp0pUdRyli/u0zsN5p0+sEDigXkKLMW1tpoKEPntH3JfRYwrnf8Fz9q+Bm+0ur +X4DIHmxYRGV5Efd6tBMptve8p2qFEoCW8u6xYB4/3oJRfNSRTZv7fCgzMMKHnCQQ +iQ7801c74gR0nlOuVtwkJE6tj+Bsg5YHWnBJpd41PGF5eldaNVBn1A+YkQiUjDtR +5m0Hz5i9FRh9iihnxrkoTgb+IfNXpGaf6GLGmfKPxTX/Z92lBXfb/UGkv8N5JjKa +RW5HnJazEONukUAXGKdl1dsyXplQNKjg30yLmczMIfxxF0EH1+5SThX9hVSZRldU +/oCYSou5Br42LVbm2hcyrsexLILG7qZwKyetCt18ZhayLan9wzl3msWCKC2slvWL +ntb2DypQjUf2RKegxFlBIYjQ2Bz02rRW7ccG2YJDs3IBaDh/lCLDjwclNuUmTtLW +E4hSL/px8oOm2V/7bItE8N8iHayhnUV4xFBGRQBLsjxNX66mabmObeTFjQHu2ZwB +lajZIlM1kYJ/0zWhmM/4/6GrSUCBc8lDT7w3BBvchNuCR2iwrhuUhPRLW8mBuPCx +o/FC5HC+haFcFJIWRG2QU+l8QaBpX/cxptfA8C9gy90c4fvZvfxuoEs25G8OQ1cB +txLWka7OcyirRIm9iW5SzAFDdp8hz4PEQLvdPy1QFBGJBTpo00FIhtTNY0Qr5oAW +87E8+EUdLeR82Hv9GqDazzCyRXixvy11ffGqX/bFreJEK48haNhlU41QB8iPmDnA +KRnUXBMjsqgs+M5rkmLK9/4W4rOyVG0Nv1rzvMoEVnRW3n4PR2vM7qc/KK9ihxXx +Ts5H/FYm8C4rWlq03UWAyfzA60lFT6ASaljKWQAbzNbbu/u4PjVRmWCdeMUW7okh +b1wQEYenKEhPmEILZn0rN1nRM8/DJoqbhS9Aep/ZEL0k7erQnf1nKvP0WG8l40ZP +4rXgoDSd8Ozd8jlW9GrhXLHoYA+3Ie9XkTtkYyyh0pUyH5AQ0XtoB0H1HNqoUo+M +eqciVzfGVnllz80i4I+DE8QDZZmNNtqjRet2tPKEKM2VN9HL4cNmbTrYQ2ZVo1iC +8lI6xxc7tafDB4JFtPF1bvYkOom2Dahuuy99B8veV7jJ2eoyAqd9UWJSZoy8L90U +5erZVHrBPDejNKmKMX1AAcRhXaruf3GAn3y0bciRyf2SlAgqjEgmfp0qCD60p/b3 +O/dBOAdtHkgAxM3iWBlZ27g6jggyGpph5SUK4zGgx4XnWV0ogwbKWVXi+ZvWxeXl +CNDiiRzFIqb0TDU+3NTmmbbsukHhqwz4+eLXFladY7b+WkAirrwP9C+9Im4w4j/r +07mY83sEn8MJQ2MLPA51TqtF8Qa2WAW85uU9TzEb27BcHBqVmy0IIagRYFvaYALZ +OUS32h7eNSdz/JL4YcfJHnZLFPey/gmE4FZxp/rp5m7cH6EomSSMlCDsa9jScPNu +lBNpniQJEPVCI5Hn0Jd+/VtWI/hmvLWT666cn2qcbrQFVBQM+/GadWrcuWS5t01F +yJkoi4ca90KnhiB0t7aYxgEP+oa9HLvBI/EDhDuuG9/IuQwepv1Dv/JR5B14fQkx +adMkZa+ZyaHu7nnfmntOInxAbhAjJVph+vrIAL4jUjwh2bSHv9TRasmQmf7aGmzM +XUs4qRgQEmiqdfqZKn1vfsN17SbMKj3OWyS91LGY5o3P/MKI0NvriJUjC8iSjf68 +Uq5vfQIin8TvpIvRlF1pqPNvsTm+fCwZdUdLNbGOJNekcI8hTuRVzObHhqL+exYJ +XODGB/KZNdfnuDynK8WBJZdjj5g+DEBK8R2Lek1WhMiTT761Huz/UY7DZrd8CJ8e +7kqagJ7fHHGZA7m3+uGKCKxN1TM7hFxduZGwfmZikT6GaXdB3zbiLyG3dqpSEEbz +Ru8JPMPEBfAFft/sJFb1956DCpwbuMprRu3Puw69b7sRqOBIwYsCz4OQYVbVdzzX +J6kZYd+yoGQ/7Avxfc28dymd9PC25v7l5+oQHJMTvv8cjncI4mYBXuD6yPn4u0AL +Jln3muh6n766T6bMjhuhm7QBJeFlziBT4B8zvPSS7ms= +//pragma protect end_data_block +//pragma protect digest_block +D7e/03/mF2BL9YuHkWwHU2Ux1m4= +//pragma protect end_digest_block +//pragma protect end_protected + + +//pragma protect begin_protected +//pragma protect encrypt_agent="NCPROTECT" +//pragma protect encrypt_agent_info="Encrypted using API" +//pragma protect key_keyowner=Cadence Design Systems. +//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) +//pragma protect key_method=RSA +//pragma protect key_block +Abb/aU6vd4NK5iXNnimYoWO7UYIoJonmB0a4Z6SFd+HXx2lY6uqbs9SGpllvwPAM +Wb5IV0DhyUtyh2WTfgW93UdYA6et2F4f4KFsV1HrIgx6YyTvefxkddDkXJ2Hdt0i +DVY7dOwl8pi5G0G/iVLsg++KpwuRAqFdKMIQM5kdDn7yvb9J4fwdXXBHtykep1+4 +RrEaIf+oTgqDzfalR4V1G1WlQz+6HOac8ohOpYDiASBMMrbEZBkNnw4F58YLsweu +ZFwlILhLIQ0p8ZXVNlvdC4j03Ir8B5UguySAxZby07M2EMi0wFLqi4PD493fVPKz +iiVHouTBWJlaPEyX51xzQA== +//pragma protect end_key_block +//pragma protect digest_block +pWD285A16E48GpWKY9w7PswvVQg= +//pragma protect end_digest_block +//pragma protect data_block +tbC5phADw5ibrgILsA6yzkwnDfSWH7zOwDaZ6EJLfQPfvj6SJKAsCZsnB8f+/eYy +BwY6m/LYrNnACYKG6hTiObSY7+2IbqvbKrMZEv/NTlurYmDf6wV4btaadDLl2Wku +DjsdRKs81nn+P+CBiZVD4F8xIQkNUrTc2xI1d5L4zU9Cnu7I+rjGFEpouCpYtGmX +jJ0uopKZuO0ExRMmp2vxEcIGZVNNyMaImeQLr2JnwndvCBc0kdw9ypFJJYm0aYRw +Y3z7cuiWTggHwEWRujz0SXODHjOKLkczh2lqilWtfhOGyrlFOHU18uwQmvRL8ahn +8RaOiaPf5AJcvUHsJGt95vw7srGMaALs2qDqHGIZA6Cehv5J1pLFZQXAjt9E5yCC +xipoPwtYKbHTxaw7zbLW6HIisW2pA36/TFQ4L0H7Br5dUtOryXWYAE0dzzBANUKe +r/RzjWLmwWAkWuZVt14lDDPAMROxEP0aRpBK/LXQX1VnoEkXqHe4jswYkN3ncgOP +51pYAY71krd12pCBs2aDChpu431mMgzGUjot3JuJ97sBXuOFl+OidSBb6iEqRvmq +xY73FBBZh4WWkm+nbmTmLuIjVpcQbUYHq5FOD108SZz/YLNSCDHPdoRIqp0ZQxJh +pJFOotWNf6alEPIRX3bJxEnjALGM3NtDQBVCiy39JQe4GPdYkxSB45ekPx8+VhFa +7uB3qovPPyhvkqsDBHCzRwtbir3KmH+ph1su951iTPRaos7Ge4zkEtoX030q1a30 +FEiX/MwWjeUxzmNPmsArzKTA/doH5NXOLigVq1odhmSjCiDbitQTAikvGJ5PLXjj +LtSzeZVF9mtAGP3Epny8gEShJuQUruPLOtDqzW9B5EElhu4ltE2cG9SsZ5gc0XTV +8H/46JhLYNxJXluUPa995tvqstk3BHCQiPkro4zbJZJPIEB/pioEBL7IR+hnVkFa +Wf0zI7LYVMK8n66wM54iLK9ve0MGLx5LUat2xkM4WfnsO+vxrL0o8Xy5H8jsDmuu +Ev/D3mFU1pjpnBNEMRu4FUXhHmCh5dXykeBG48H2n8V8hD5hGdPNKANVZqgL7Nm2 +lWgEekSBB4bDfkycUge9xBvyHeI6OK45jYKf552/wdMIZuCiYS8+laUi+IrCgfVp +gLoY6Jq8BInh0sQaPFHASxdXuR6vwBdrQ793lTBGHIsP5d75zTOYvoVmUjowoTX4 +pX9+5A+vcIIHAmq7Y0sKjZGs9f+YhI4xxID7iH+tect9C32aY3rsOuiPIsIF9cwq +/hcRBENALP6VK0QRLI/L13yLiFfYP5GzwW0w5m0BX4/pBReCyfW0B8BtU8H+ki3h +AXxANnbC2F5eJbRFWe3QF0uqn3Y8HfD+3/OUy0XVARPn2QlCNQBQnLT2dHeMoHe3 +zfs+X0YJhaefWi0UXSXmzjdhn5uvQR2t4tpDviDgOMaFVIX7lFkij/p9JBuswcf7 +JJPHyDSOmRAci+FPHX3rw0liWnJic3SFyx27saxlTMlDjxuXz6RUsxgmykgwXS2q +XFj4Y2qmKi1HjNu+sr23zKFzu9C7qPcxpt3EdjI6BnG2Ks2guYXv0Gwqr+mpQ5E1 +RgU45UCjhWK/9Zo3CeoXJjHyG0/5SufH155/hmltrpf/eInxz0oQ1ghwwgrvjTqZ +5as7CqOk+T6BTdOiBn3NzcQQHF/TuhOXs1b9OdVUritY6nA56Dh5UuG90Nc65Gef +/B4vwieJ4p0Uor8JrUVt8TBeILazBlM5NzzQDIXV1Mmuiz8Wbhg24RM+P7hlxqNx +irbPIimPdX1PuX9dirAkq6SRbdNScE6mDvzvIQWIfxaPvwH2f2nhI4YuFsNROpoY +PBZAbdyAyBVwthKpmLDcY4OkiehCDWrxPlH7vq8PdqAYcmLUtgijiGvssqDog5db +gIsMuzTnV93QKwuGrFXn+zV9EOc11MMBEIcm57sqylRCYxY7ytpjP7p0hp9FVXdD +zGWiihTEdQQVKICmGUezqF0zVzAxNYqdaGkO0hXYGAt1Fx4EilEI233Tk9XUG/PL +Id3vdrlXCfiq4SGMYR6er30QbQANt/VMjMcz+QO4rf8K1P0lCVe7PGun8/z4o7YP +m+oSy5M+46ZGvsILKRXhQXsFkZtTB33r0MoGjXsj9BWG9YrTDyEy45XqS+iSfie3 +KQmvIe+/XPLLyXAhxhxQxluCM8wr9hi/tWQF2N59lRkx/C15Ys3acNvcYHfrgTQB +WdKVG6Bn+o07TQaYEInbJ3MEonMG7mbn1MAVLdsaYuLrwtjc7gFqIGsto2CqXZkG +qmlooCBVplz3ZwCY6gTzGRNKu07UtAClI6P7Dm6Ctdk9G4AfJP05aAx4va1C2jVv +ua+Klymxl/Mws++p7tsE5wNBLg8/9hKw+SVprSFgwHLR5wKwjVVm3A+QyfsOEwDr +q92mjPKmbNTHIeqlsV28oZtZClh0uexmXprF0vOw8euL4FSjxd6nTpBSxJmK7C7t +bNiFNYTd5YMPQxYRgQ4uoaTmr7JMSgnbfqLAYF7Sl9OmW9pB5ieexe0HWyWI+c50 +QLvSKkbMbxPjq5/TDNvSAAfrxnSMwcQTyX7MJeJvRUQ= +//pragma protect end_data_block +//pragma protect digest_block +q8FQ8IPkH9SC749Sk1McZpJf12E= +//pragma protect end_digest_block +//pragma protect end_protected + + +//pragma protect begin_protected +//pragma protect encrypt_agent="NCPROTECT" +//pragma protect encrypt_agent_info="Encrypted using API" +//pragma protect key_keyowner=Cadence Design Systems. +//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) +//pragma protect key_method=RSA +//pragma protect key_block +AuMoHPX8Pd3mqbQO1GA1lDwNRW4jVDSCCnolu3a6qpNdY5kHzBOGmD+lMc+C6ham +DMiMRT9V4xdB/+OwhRUdvnDdS8ZdNEzgQ16Gp2C+bb8C8fxGtMhNxkoUVWf587Kn +BgG/gBlTbJeO63zuzFdgGYvAyJ2VnKYt5wWMlOEkPu9ltYfcrLIG3R13kjyTD1Ci +XIHkBgGaddrqRpVONdrM+FKVtXZ57ZAqBgLbG6DP1TCMKkiChSMPG8h480WRmgKc +dQ0b22rh00a8vsr/qVARmzjRyOJSx4rgZOEhGRcQ8evgL7SOZxu3JXy3m0oErgqT +QVYOONJeCKkvOy9Jgs+EaQ== +//pragma protect end_key_block +//pragma protect digest_block +8qSCHJneLBb6XVLZi9bJi6+NcUw= +//pragma protect end_digest_block +//pragma protect data_block +mjUZOoJM2MxBaXTtENbAKMWZ9cufVZblhfcbSkDa7OaUetrwGVOBa+POnkO7nBlb +t4K/wQkA+RF7Rhk2fuAx5SfklhKO9JKLYqP6gq+X8LkxlcTF7uuL0jeQWJF0OCyp +Zjh+SCwSUz33Y9NeU8tYfOVaNE6eJIWcV2gdFIkISSQzLem3h+G3LL/IXZZ85/HS +dBsLSIqz3Xj5h4+aAzn60yoeeTXLFw5cpcYHXeOjazyGPRwBFvMXntIwwgyZtUf2 +TgtGZUKJicZOcgx+INVrAWh7UykCu8GgEhP3gHz2FFWDaykgozYa+BdWlHYVZRnd +u4HttmarkcM1hDmIrDkN0xeI0R3B3cOYK93O+SfFZRjgPgWSgfe0Dniw4rFvSb/6 +xfLwV2p8Tb6WjH43i5+zp5RLfqwh4GhPqUKiWdj/NRP+2jZI6DfnXdKpUtPqCD4Y +ie+t/1dmyPeAnHThwKsqhOjxXY3ektJOkC8tEfQQ+xQGqS6V2Yw98zDIGCBqR5tm +ykkfpn2EOiqZAF21pDpQNWKAbKFV4COTE244UTVwVRP8PvLm7MigAvstvPfogjle +pgwyeO54yhhf/t+I+dh7Ol2PbPIIKq6queTfDFK7iFP94L12lgHAdUAl+HE5fzlP +wFK0iM7gVC5Rpg4rP+y0e9vCX5DU3W7w5J0QRMnwnWPg+KQ8YczK3/W/spBaHZOB +kN4ZVGB0LvCTPyaJzGr5LoFnA+cYlUsazBidM8Xy3/br/sI2BprOeT0Bbq0pgZ+7 +ZozDzNd7LZtVNGBHU0z30YjaArVNIbrxjGvrM1rMBiXMKMkBKnAK6OPDz/Cv81Bu +sr4T3WjutY+QUyn6JJb4WBh0C52rGPWkmApEmDrViAoBfIikmr6NOZWjoX7lTUBX +ktMH4cCtEGL7kpJrtSal2lBI75l7dQugTNXInwxuckce7Xe+OEzvP2MmloJy0O6M +BdQew09sZNR7qH+pATwkTgOxzR8WD2uFJ4xRG2JXMCeQmOJ8GqVLNtWCRBTZu/w7 +Ei4QQiFUDii1+M0vuTqWGWd0nI1+TjsqB02FbH4wfCUh3GJEtaAnXJsLa0bsSqPG +F91Q0P7JKG94GRUCaZzWaY4l5rmgTOHdsKIDkMrO8ZomgqxIW8/PyrdVufecyuhS +tagF7wdMRFl4N0wj9U7nvS1ap9/Y0druycAD0giFMZqvPMj2TdOcei4WJsgBt97T +qGgspa5rTqVlzARrLSgFLTUyF633pj+0Bb12EWQPX7oDj5k5kS/SzW0ZKNpLV8ty +Hox7DDoQu006ZqZZdY26fxlSh7aRj2b2bF1aToC7GjcA1lbdsOtyQqz1zTn8Idvk +Y423RWAAXMfO+FUTbExd30pDrp2EVJL0xSS/Od0v4F0yjNS3nd9e8JMxF6bZyrwp +lPmapxq0TNxCxs5DcQje6xpbdGTE9tGTevyk7YhE2jmVBQoBNS8ollR1cChJnMX2 +A3wgJSwc1/R7mArGuO4d6V4WyrVjy1ay3Dn587sRxBoIEyYfQtbvw4Hp57EGMTmB +z3Wedc32RaQ/gYdi8W5ALb7e3ZugnCImvKAO9Zys41rR80jfZgDibRRE7R7eWBpx +Dca/tfPT/nm0kmLMrr+QLFj6NG+W46M/9s+RUPVjXmRQWYWn3DoL/urWcc4dA5ED +ZSW7QYb19DJ6uG9QHoeMzbPTheO3qpk3upfbp54jnvKXkTiEN8i2NN6WpJcByXVT +eYWrCmNsPKij4RylgCrk9+TnrF+SmUV1Qdg4qRveSj3oRXo9hVjlyJWbHhwdDhWh +aEdl+0aCT2cjFTiR8yeqW+vuoKioYN9qh8TLLuAdGLgmZtq9WxsyGkPKOtspDUMq +EWydQ0p+4RzUAulPvbwIKb0sGggpPGngkt6TyLp83Cs516Y40mH6DSaTl71MfUPN +6hVNGmJHFYj3tTvj0TQ5Yn6LDKZIFMYthZGHop+ROh+IEXUubzHm7a3cDCtqkTyE +b03LsJC6CbMnKI4XGecMXYfQw9IYR+L/5ks46VSRiptymUrTtRogrHb4JM3vMykV +eiowloo3C+iXYPHohrH0mtLiiPc6R58vOFVfL8nYoib2JO6D8+6Xy2g7xxq3mJAV +yqdbRTu0VObw/j4oDm3QhDtedNtGn5zFi6EsNsnD8Mo610kERxQ5JWUQ9pFn+Q8C +z25QzeOUO0xcG5p73pWvx/iYAmLe1udtKsweXltd/jqfrnxSd82xNUv+VYdzwn84 +OelM0vLrTklkXPc4+OoI/t0vlN9HTKz71v9vN46rliiLEjWEK4q1O2f4rlqbyB5j +y2+8e26HbD3xg3kmwDYHKnBdp6BHGoal9KnDxzTz/eu9LNHlwf5zjck8iA3+97jz +HHwOnEGLRkzAUM3vr5Rh9YHCl4LPYSLVC1p3wLPAjbS6kIN2SxaHQmW2+qkCyeBK +ayJOmojJZvd2ytxxil979lOGyGnqssMnSOVD5y/xarNrTxcWneOD5zLaidEWVIeN +hcQwoNqbl9ou6rUMlFYsbbC1Sodw7eSpKhoIcISyqvzudaCOPOvydwvaKECE2AO8 +kcNmqRNarkBd6EztjGGGjpo/VKwuSjjKmTTVG6UosMIu98rT8GMpN0XPDQLZcGUM +SZhPY7MvdYR+5IytmxaxPpwNtw2pXjPzyu+txd6Hc3qgeJJi+7qWWOwTGPbxgu2j +5gKuah3rKsqgRqDyspNjnaf4Jur338xZJSy4ei+FfF4Bzn4NEO1x/+SarhFS+Qi8 +8oci+qlUaAtPSUXwZ4W5uUVK6B4XAOf3Q8jfxQHQXZS3FBSTUCAe9TzAE1mv+gdq +DBDftqQtX/oHWfAmeZhmRBuj7LdF4fVNcnOSlb9RYYo= +//pragma protect end_data_block +//pragma protect digest_block +fISjrQLVTMznoejKTXLxneEH1rM= +//pragma protect end_digest_block +//pragma protect end_protected + + +//pragma protect begin_protected +//pragma protect encrypt_agent="NCPROTECT" +//pragma protect encrypt_agent_info="Encrypted using API" +//pragma protect key_keyowner=Cadence Design Systems. +//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) +//pragma protect key_method=RSA +//pragma protect key_block +Alh+zpnsJ6NtMNwzGSTrfbMl+vFsUFiQe7E8ZGxfpOO4gXH+R8hi3eZ5VwT90lvV +JhwMoeTUKOhlOXbWgCgWxu2KaM6oRZagJxI/qLkZbLXOlM24Altu2z3sJT7Ymbi7 +SifwsoPrd55gSeSnwTmdwAU/3m/+fyVWBK9zo5tri2VJTLDpm2DCcT+5aerLXXPg +ScpwP3go0xQ69IrJdZ9wx9Z2Qb+mbafejlACthfrI/qHqz0+KfF7JU3xnktro9EK +H7agWTVWTyfwEes3oAnLjcgrxQtygl2JcZ384L7W2ohbVxq0M6xNdZ4dc5E1Jd/8 +wWwZ5PjU8hN3vfbePgjZkA== +//pragma protect end_key_block +//pragma protect digest_block +TtmbDmxdMg1zJG/PERb8Ra+Pms8= +//pragma protect end_digest_block +//pragma protect data_block +k+n69WuR4H8EJmfWtnuPsWo8FraZu4DfWYL2PY5YqjsXpkNVPDjqEZdDsG3SqNTN +2S1NZ870LhHCGvBBARLdJA1VLkqWryMAuNBirOylR5IF0321LM6vzQn3Wi9TWmfc +bFEeI3OJeikRfzPkLvH1aLGNjqWEAnQ0M4hS1oMTed7NQFZDLfd7E2MjGMUZPShr +UBv40r3fj+D8GVgPsHkbOLPmp/3nKpGql0CUOocKPoyICPDj7IGwrwNd7oeuDA7v +zQCcZm5LS0THPD2SIa2ass1gWjm7tCNlrh2k4IYRm32YFovPvXQFRgfOvgTxg6JQ +77hKZwhD2x19eRMm0+HXZxjrBXEMKB8rFJNVPC9dWtETwHUJab3lzrXCr4Fgwzgk +jFcwTSIvH0RVVw3fj/cJvUCBX6hCjRqrch6UmteqvuJ6IFGi7aekfL+T8v3Ws2iu +aCQwxfCXMtw30H3obauMB9I/w4hjSFGSCD4u5FH2F1Mqpn0uC6Kk+iRMRPCWbiTm +dxJoJvLlTTUkT1iZj/gOhjRowBboxZlGAEh2is5t9ed8icK6cJuniTKdCndoSnri +9MBhURyF1lipG+3/530Hc5udwnTKXQFlaVzeuPme6+yy3PFkD5Sx2Xjf9qjF8kDx +pwz7GB8IUaRwNK0rkoIk6Jtcx2/xrtxmzsRVkFIsd044rIKyMHdc2YV+1qAzjaVK +miG89UzKseUjt/58f6GBRjHUTbNzeMYrJvqbI++ridb1nwEPo+Yh/0GLq7ykgk5o +x3NpQqxg2FOEIT2wQKDCyJrS9SyYNcDqLSnzTxewDbm77l2WlUE+X7xKaa5RMs06 +dcXJR8GLKF1fDzMdBOj/mUmJBOEtkUSWWhBL7yuGja4BgSdDzMxXvQf9UW+j6ERe +JIPco270nVyQCHrhCkINoj0OPa3rbtmMZxjN3UnloY0wXt6F+vxKcaveXUKsu20R +xzJ9Fk7NiL4xws9qG9B1dJShV9stkYdqRjRM1q4Mjx6zO4dE3IXEovLi3EZTGfH9 +m/PQwWGTXz/14BXn78imWB7C5/rjP3eG3Az4YF8CkB/oYO1bmoG7JOYGT44nuhG0 +hHDN0ZLDnY9cXqdENEuqvfe1SJn1yNIa2QBiIfPwWZ/mpjlMinq04ZS/QWv+F4YP +GADlxVl3fEa/D7UV9PZ733h2MGvM813eA+6dP+7nQ6izER+aqnxXVSR6108m9Fhh +Qlw5p2O5H2uzgB5FMAIflWj7J8eZKu2W28EllU+YNwvoN3mlYNmxBToH2cj1XgQp +btS2r6Xj/F0UXqGwkjO23ySxQ05FwmWPmPRe17S0vfb/tX/q7BagnZH70jjtvKtC +sfF7mVTEWER3JP0QX5QNBej4MsNBRjBd7mkxhuvV28p00rLc/I8rs84VgVPtRRRN +nLJqPgqXxWdZqA1cGh5PjX1oqI2/mfHaePtCCQ/wAXOmnkUCOu0APDCIpVtHvZkI +b9TzbKp2iL3FyLl+enDkH8LoIIBxlF3M8IiKNj2HvTjMGZFYqenhTYoSv36LdtvF +ltyEQMfmJDDgb/QEn0tc+FY2rl04em2Nq/cCjuFc0lgO0zCObt6PnIAPas7Pgfn/ +2+Sk3ypPrp6C8vesKbDAUydYzSN/6veQ43B2srBEX0KyPDHX+1Zh7xxHiY1XdXQv +luUl3pbLoq8CDzpIqLs/KnLFWDqpN732dEXe0gnrx3ZPgalnL4o0y+8kUpj0XRMp +tVxHQqGwuU0K+aqMcZHWORJwolnNtwyjmmFi6HGcbq7WlMaryZxJgSVGqG2dfn/W +CRazQU8VPjZao0tcu3PWMKwVZo9lkCvv3gXksbWFoR2Ql1GTv+ZPTmw/xypk6dhG +kOeDd6N04JrlfkPnM4yh3INLmxUDLAeJepsZdYLCskwLqW0VUtpenQ6kObflHJSH +8zJZNOkiiYrYhxOATiRMxxYJR/tjenOebx7jvKJ3SZ0VwRobUsXbaB5JtVeSLR7A +GOXHVR+DRtrcevCsezaYMmA8lajykBiIvbyU5Oqw+MsmaUxGfacjBcYVtM8P5502 +HWRl1s6zySX0awWWKtAG0cJ/vw/8fJyqOrTXAxPLqG0gKhjjLiAzewbmehoygDXE +mfMm24jUzVvRPm3QpQXRdhUaZdNvwYaLhX+Wm+Onbo3Aq7okNDq8zfBIsuCMN4Mw +1ZshNtS9QWHvWdJoUUEbOPo5YyU0drWX/mS8vkq8uTYfyu/fIWw+rnEfT48iv7p3 +imY1H+2cuaqwEHqslEkhKv2Z3dLI1hO1YJtJFGLYpP8ddFU7CPRu5U9t0MHD1WAf +Gq22GHJFJXt1YXWxgAnZiTLKNgIB1NEtzR1JC6YOMi8Z3rQuasl5FtVGxQ7mjpWi +ZqniCdVTIFgRAU4U2C8YLbW3q1UtBXgzPDsaAYl2lfVpy0DkxyUt2MKuQXcIOsL8 +BWUIHVG8ElfLBQWKzx7sly9V+O3ud0WcgnmXbt2AihDescA3xeGYtFiLLLRMv3j0 +2ya3EGX2R0hDeN9THnTLBGoBvc66vCnwM/PEFJsEsUDYLHBBFRP+KWfJxVtk6nSk +GWa0XA85vqK/MohEtiDg9c6G3uHVWwk5EtN8XBnQJt7l3Wn01FPeonDnz+v4jB4A +sPAL/UUV5RC3g1v3kvjYNEB6vMoTy1/ngzvRpeO0KxeoUshPExPLcp7m8hakQP/2 +ZaMZ2EfnqXVTw9RVTa0VYvY501PDLvJX9HGF/IeDpo3zgloNBBlYazbKsBPdGY+t +iumUOdyMEEWizwEslLqNp2K9GKkZpR2sukxCRUdAQwG/y3SebZVwDU0CBwnJSOmx +DXle5Z+JwkuORjN8rlC+SOowLJM3SWAb6/UlQbj77DMdbv/uCN7QnipP7khrcTKk +fa7CiQIaz60uq27MECrP8AhwO6tfecCloHvmz4L5ys5W+Y5RDQVYOd74J/Jm9pTH +97fEhrJS8s/thV8H95E26kcNUTq0mdRrpG8XN3yIzkWgmD3Nhl8LsqRCvxf2xqYM +pcam8WaqfVSaDZh4uRdj0q6no7WnGAz3J64NcGAqKJKlIA1RK03GBLH4wnS7Msy/ +Xw9eQUc3V5cqL/qv4naKd80+m8GLxlvzh+NUJYzNETs6f99BaWGsoIaWX5fJzG2k +igEdeEMCOivBYJei6tsn39IvHGzU3u9me6I2/Qxnk8cwiIUrdLVnrcKSgagUSfRc +hFOgMejL1W4G2vfgvQ3E6jJ1Gw7/GpUM9BTQwgOS+xgLicT5e9qZjwyDmBtARtDu +YXy9CBo1iVhlcW4U9C67bbBLJkY87ruw4vtIpDCnnVguGP8hfD7CQIMzY/x/3BiT +noB5VtC5pCS3sc9Kw+KjrhOKirM5rgqra8zQG2uXJOpqLWJb928CrkMBmSqvpAmP +HXwztnlmJ1j24kGYS4eMQqq7H8Y2mTB9UInwMwkLgUUvJNeEFIiQoIh7DGnm0WUf +yehkk1ElESPD7idNa0WYSM14QEBhnsSIlYRDx7WLkPJdhiXR0/pPftNS1d8M8sm+ +sk7FazVQEW2aJovwsGYvxEvifNXdLZOPIwTWeMMVRoewTnOmfFGup2RRdifqo3BF +B1My3eFaaTpYg8j54SPjUrbhwQH7SWpKHPUSBb7t8zUplKEKXDOBCuC4mXCC+5Qv +GwJl8wljjwbCdNHrAvQTerZYmjlLuDND3uaU8xqbqKBT0zkWlx7zMApJYisgL9a5 +gvr3wqZj7IbSdZL49oLWQtawz6y9+vPchronN9xhEhgf6oo4N9CXE00eylTzdqFW +hZ4UsVFT9Qbm1/aUmSsHuRHq7NQCP8O44kdDGvCoXO4HhX0qMcRBJ1RdSdfL2GDV +DQR66hnhj5sr3fniKtsFFcXsW/wQ0McEfMPzmbaayvk869DgAGM/HhqN1lCpUdkz +//pragma protect end_data_block +//pragma protect digest_block +Dp33pnOzrjzNeFbe/SSVyHl2kAc= +//pragma protect end_digest_block +//pragma protect end_protected + + +//pragma protect begin_protected +//pragma protect encrypt_agent="NCPROTECT" +//pragma protect encrypt_agent_info="Encrypted using API" +//pragma protect key_keyowner=Cadence Design Systems. +//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) +//pragma protect key_method=RSA +//pragma protect key_block +ADDkpHBcv1QLYI/vnbFUVBLH/vblpSm2j60Iblf8+01HHOD98Yh22bALNGILAwKs +9gQVwKC2DPK94E95kFvX/0oIAboT2fXoRjUne3mjg9Bgg6srz/UjPaq9my7Gxlp3 +mZIJKplYwCFZQ/vV7OFM4LSihaRrcdzBCKY0fkk37axv3XVjuxXw08yClc1SWhob +1iNAzAl1o5YyjeSrMGjox8D3NalxWvLqTkgGJuZ/oRxlAi+t/rk9+Nec8ZCp8IrH +6lbK/r2RCMcJ0tI9SuPpOoahoEYRf7IdN6CLyP7Hoi4pDgDXpmj98vs8cRlUhfr4 +46L2gqFzbwedeQRHmEcDRA== +//pragma protect end_key_block +//pragma protect digest_block +XyTDHV4JZRt+wfV76/WwR7YhVcs= +//pragma protect end_digest_block +//pragma protect data_block +DIQpi5vonwJyBJ2D80G4WZHECvG9vVq/YknlVDO8yLOu/v7EJwCXVnV4CEJbRkoB +G7S7Y436+diYcvbpp5NUVgk59k5vS6NOImBWwi4fMek6uCj6JTlUKCGDP5RNNHNS +qPONRBmo+Bx2tputtqQfkO7Q5xca7SMR3I5WlRRonRrViYfnSG2r7rniJNV/aBdg +N2GulZPlIvJBQt1lXjb5WZzqfiZrnc4yIUGXAGaguf02UjuDF7/TV/RRnJA5fm0+ +3HYsjIuBo7Uv8pTHyFUu6+8LHxlfAR3k9o1dYX3XTEydMb0oz6zOvRbMdcn7NvOJ +TyLV6VXSi+GcjGsJXUUXJ8Io/Y6h0AXGV+t/6ozhr7c5PVsZzsvt/w0HF5pBZZOj +k88mhEgsyspl5UmgMl00+KUbOVIC5kZdilv9zYH/9iQmMv5mN5qR8WTWSlEtm7AZ +pNCYtsV1VVVuzqMAZ+eF8WwoW/dI+6F5Drs/8Lnl1Ap6LLmyWPQ5HO637iZvUjKb +oKpdb8RW+BjQx7mnzacRZhFKMCIoLaTTslxBgOfIX6GT62uidjK4vxxPKwryagFJ +OoWabemNWjoZw7UPheLqy1s5505fXN8ELI0n0jYzi4CfgKFlu5UtdAQrY6X0YgAQ +khyA3SeGhS64IfJw3f+nPzOihEaD9ho8VlYOTS8WjdB9esCQonaeaoGOnKt6ICUG +UMX70VlZVDpgunO64cnXSqiiYkCIwnUsBc9btS8cUfoBr+YvVvzHgXz6FEqll+bW +31SzQ1Cdh9WOkQpnSNy/N8yw/s1obp+NcrTzhVm12aqIWPCrBSpR8Wxh8H8FXSEa +yIlYGziTTrfJnhqXQ4YNQzvKHFny86swxUONRWzRrYweU8NOdIZANgYsM7dpoepA +MhV9Y7DiwAgl1CpUOYdtHfTYPMCiwoIXkpWPDoNF+DREKxnnd0Rm2K1JR4S70z80 +mGQJdZMeXz2GIUzlKuqlWQSwYMAN7ONM+R6/7BlxP47NScyDixqzivQ/+vSJevWL +/r4860aUrhzuX2GWqR8/FuPT24B/GshIEDAyg4FGRrJ0GXoe4uG00zvspJkUyeWy +U6e8nI8iBiKKXQnaBkPUYlRN6MDGQynAHDiKJgJ5/3/KjhWFuXus+om76XxMNBxL +PSIoLtZWtED5ID/TgpMytsL9Ry8a5E1wQ2J/GDcUlC5raiK29pfyIQKc8kUQAvqj +ROz+4xOJiUcQW2CYBSat/dv09S7TZd0eqxEU0CaJ0T7DL2lGOdi+YCi5BfmQuQmj +hFuH7InOfEDXuuxoEMvOmkpOmpaf0sHRkh1LSgfLNG0Vj80Z8fjKoRXp7FBUvjeM +NgvgkNj9PHFSSiq7mdmdvoUjL6gFnLCiCQApj1a+jCU+NPgDsnwj8O5ZAd7+/W54 +vmwM5MpUNVitjM7zqnj+dJtSe8+rK2XYc1ZXZ2263C+ZCj7N7bz7Gd7VdO4jK2zJ +m5S95wFIS+utX2gXg/+gNiivqmm2eyw1Dl27Ho0fZxV2MssnELDVKhIn5YfkhhQT +0YiI20ECjpDcxWTXEknWGHiQl/1+3SbLagjJIvUFnOaVKJ0FwQYSTB++4oGe7sNy +AAJX/Y5TPQZH4jBvU+FaEtCeqq7HjTqLDkyWvWnCIwJQUtnINmv4joaJz8Xv2RvD +srwjuX5kFBEudB/UakugDgGnH2ytO5uHk9wBMVc9Flfae0NlGgwGCI0fU6X42bZB +fGvgicAI5tmzmKKg8yYAeFAB732+KNN7seerVksH55JVXSZr0iumRCktdyavoX1o +WJjiGcGwIuS/8e3gdhsET0mDuHSHOfLHATu6p7ZtOofIp0wPQf3t3KFoABD/f1Cf +hzsz5nyRUXQCEeyptNpnqjmqoLlvjBhLjxxxUIkDj0l8ACwY+rG7BTw6JyOQ3d0B +aAs0iERvaOMLvW8jFGQtiELGcpzZ4hz/7soQ/gVJkN5DjrNaDLN2ofv7q3bDJOvX +nvlDqA1Q5JV6QGYtNf4k/9kWzXfpXsClqhiIbkn1bhOu6sGyL6a7e/LUlpUNBYz2 +QEC0n1cfuJEQ9nvqLJ+niTKAyFuciwScQKxzN4DsQq8zhElXCSL0T0rp/MYWDNOy +Ui8SFwXUAMqidS67LSRU5n8onASYtv4HMPNkbUB0SMj+yz4RruryFmhbBMzmbxch +hUgU0ppfeNOX9V6rxJFiXoBoBs5+BM9vmMc1UM9ncDmjtyUlc4ZxJsXQBqcWTO5q +QBP7jp7WHQjAGDHOr+JwaFxLOOdx5DAKwwE09Kjhh3DsqclPZiriIQTbxiL7nIzF +WjZkkRNuVRdiG+oakTLYliXDP+t7DhhWeOIcJbJdDMxTCzeFB+7RYFNdR4MLee0d +l2mIPbEX2cFtvVjcJjES2eepMa8+RIuwMbyw5PZXmF+A0AFsc+Fyf2YyzZJNn1Gc +HHAFz0uKgH2j83HbKDd2ePLbh6zLzCdv3lVb5t7pUPZsrvKln89vF7kMAhsfGWck +eWCthlAkj+yZFnpM/AGLFhqrRWlB1hjUHL2X0DdNwsEo6HVB5QCW8k+CobSi5WmG +GNyFO2iCAynfYtpVoPCijPXvgegy8v4GcN8PPhi1h/ksAiiUFAQcxvpVjpNXOPWa +VYp37pTPCx6Wg+2h5SCW/KuGQfbhYsjcDob1L3G0Du4ymqwOOzcvori7f4dSPoZp +K6fBRZyhuWZgX6z+88i29UDoH002pitOmMv44gY9203A7bu0YXLOwMCiWkpUTrd8 +tgbXmyUtScr+W9rMFi0qFoQNVcIZzLI67HcSJ2L+XjUO0gePxgNnVF8OCrugyzwR +kL1DANlpIJEcGs6MQ0YSvBOKE3MLljq3L2MEaydSPubTurdSjuCWnr2yo5xdb2Pv +x+0VzyEMaUsdoMw0oiJNT+R8MJwPezGj4eaL7O7AKRHG9KtQJyNRiRk+AO1Cqtln +iJ4dfSBmLMumiNsGTIBTTwzXaELHNQqb1Q6J3RtIsUUEFw6Tk2mlR5NoL4BO9k3N +kVBh9+lO5bFqBJ0K8532irMufbu3vGczovcesJ2o3Mj6BecRzn9kR4dpxmQgQ+1n +nWl9WME5YJIG2gl+9PonjuAVLeg3RoY+eSu30Bkb4xZc+khIudC9gudIaIdz1bsM +CeMosDKYGKoOkaWWrBJp9Cvnhr5LD4py9dBfS7PWCeQY3fp5KSd+XDBONcewKjOh +6j5PY/zskRn6hs+3KvLIYrdkYaNz+wnAz32SQx0Xb6UAw9AHq64t/7NsBjlhv1vl +7yaCVV7C1ewTDXtgz8YXiu6QwufXzkPl8JY+4PXH4JZ+BEUZeGMD2db5ys99fjSQ +rXTt/A26jheXsjq7KY+YRMFhUIVICjrLIsUrY8Z9i5lk0T2Kv+WFKDr3pLNJo/HN +S3WgRKbNeEleeqzRbJ4CQfjDiHsYm74uABXOP7xFXI9cBi43NVufdyZ0paANVlKD +MuShcGb1iXNG0O5P0gLGb9FyrjuCBDlgga/MEHSiIWZJtHMfw4APtSpZUcCTOMpJ +wu4MzO+NAdYrWb58C/8kTzAEPcDMSJcIkJ5TXFnhINq80MFmZr/6OS8lnJAINgr4 +3gdQOYvdntudFxnX0jjWEVeg4ryJ5lA/g8VSFyKlYbEqzHacm1kqtw4wVOUnYhVf +QyVDKBZmY0uVMOUdKWtG9kJ0R5HpbLgfxcUDKHq2EniPG+bGZM0cEVNslH0G8TGb +XrCJdGjRXmNM+GVp3EcwxhPXBYg4shjheKcFoI8kJNyO1JpY4HJEARV8rdnRmsa3 +XZ8x0gGgwuQz+jCvWTeYa8yeWzM8Vuz5DMLTjXV3ERSD30AsxG7+ppOdcT0pGmdB +gdXP//YsE/vpCkI5zhGWqYQR9rd1CA/jDRQJXAJIj2caVGWEzy0kzSJ5hBpsZucy +Erox+0YNbRJIPPs5mrDU1CdCxWw1XPkUSVpOmdV8eyM4HDRvii+ko4/r/TzTw15I +7q3gj2NaNAbikgBj0n2hql4suwRhNclMbD5MYO109ui/urx5pvvURAKtnecs8TqN +k4SK7aKkA+S7zUG7jnc+QMIcD/vDAaE9LIwshHRxpKgVtbJhi+rkOCejN4D4Tr1S +D6f6VTktkvBn+ihF3K5K87GGdjNGL1tU6QXDvL8Os+2mcDTuBM7etIDMMx16rcaJ +VRuMr3n770MqqYJTkAJYlGFF7WcC7ex60puTjPmENlzwohBjEg2MpVFZbTQtcj4n +RbmUtsxMRNkQsYIpTMD0XpQk3zHhn6SwReDA1oT7ODGZJNfcINpUsOa8V5+uGgLE +YqumHtlWM+vfIQpG+I81O4q0WSUa2sZls7EoHdbmu6eMW0OBa3YMN55UP/Z8VneF +qaCKhcD7J0jpAiG5rceKWIBzcnKsCn2pwAWqOq0271rolUU9IbQWSd+PrMC8wpQ9 +r5Hw2EoZ/CoUOp6/i+d1j0E0jXUwXE6DpS4zP8xx3xSKiveXuFfFMmMQB8IpRR6J +msujIiHaXD38H7T20jxNHzJQWrFAx9haOwB/iy/dimoDa0sxJ4w9f5eMmiIVmmbd +s+y1qgEEG+ukBG6XNZKUio10/KGLu99nGEOQjOsxHe1NiUg+rZK6xeWuP2SonFE+ +azyZCZXD0IUzk3OqjOfZRaafG3Psmw5YLHRvqEXMjgRLGb7CmuxPyXA/6q0KMLiV +Gu9yT8aqQ6rtsG3yGjmayQjrpllKZ+uRYFI1rDGqIbnz3vBbIT5ReWmZ2/yDhSUV +ZkkeQ6NqiLahAQDZcZHzCR90flTMarbfYMYmd9BZpwu+X1xzGrG961sjHpbP8wmx +u6kWaU8NQcHvs0WaTVd6iTZe1KY5UkR3P+7xp3FyrTrjp5izLIKkrH5gkDdQbG56 +Z9p+cRrJaQaNro9pxgeAusiiGIpxIwcO0i1DHeZk2ArnP0ETXYI60dJ05uaQpcs7 +oRwmbUI9LbAZLcnbJWK8+2RY+OtFsulI4zZ6ppb+MB6OYXHIfq567pEc/ucEG2Wo +hYN7jJJUsx406PfZVo/WWn+DJj4vvR90CXHK/vYqsW0BLL2zKZzPNlrkl2Tm7mRx +M38YSw3+4Sy3cbp3A+S2fnHLrVQYXgGCKaS2+Ikfbzdn+Auwcab77TuoHysLwGYK +wfpAF0Irmc25ZuyskXpJeziqi3uvY/jcbOXkFcxS04/t5w+TMCH5SUrZLSfUmTJs +JlBMK6gnEO1M3hcFu0grkEHZBBrq0OkG1Oba4M6ePPV+gGylyha3VtUNl10dgCSv +7U7Z7tf/mytyxzE5PWIo8Mnb4QBdkkepQYT76kFGiHC3mjPIVFwvVTieYr5we2wm +QbBMkJN24xe2unJcPqwvXbuTd5pCM8YOll36e94buA/MOGQZ+loFNLP+7qJN4Zs6 +3EdaqxP+otsBf0omlScSBLcH85FaqBtuXzPPeJr8ZW8O18MAkW+lZVb+4794E1/g +rCwgsU9Nxz4UCq5zkuFAfb9tZvkf6+8M3kdbfRkicsM+GCO2rzge3QQmZyoTIX8T +WDwuSH9phfKt50Uemqrgu7eLlfRBIK859A/x9GFJw6rF9Ifms5QYKvy9RVVJTbSI +mwm3t8ppSuLydVDNHEjqjFCDmKwFrnmP7yOEmCVs4WSDu6eNN2H3OF9gVTVlevn0 +fHIWiZsA3ww1SAusO0KdUELzm5Zus62fXPawP0wRvkRTHtsjHB8qmYOAYeMm0n+N +kscJ5TKWw2peccDF8fhZdsao8aFRtgEhh6dQw0ScPK8DMEsncEaHrHqwTKHafD6A +kbCAmKh3K5Q6apnzuTTUBceaNWUxy9ThLzXzWUpVMsX8XaOIcDWLZwahtzuABwzb +4UqMgEBeMFNQdkEJpSnZCweEc0Ruo1aXqYzCX7kw8UmfI/EvU2cRpYzl5Tvhza62 +JEMslWyvrsLcEpIhbOHYuiekGQL3dwiEtjPjGHVp0YWFu/f2Lfiarrqhuo7dccp1 +PpprC9KdfKlly3zCjbDPZm7Y+wmdmv/t+Hv6o/bSEC0KsS3KYwIcNxdwugkh/jkA +2QnFp2dCDwSYAdWwrYL/KEGldH53ePU1GFX3O8bAASxhOaEYv16GyjO69e20iyK/ +pEsuTre+jkXy+Xy+517WgswhIOmjPlzzVQDrsHZyhiZCytgBTmSpad5Jl4Mj409B +07avFBl1hcuepjl/ZPWDGHf/G6toOZNyg2uTN+FefIMNFcpuOhA6ifpsAAWFya1r +Ebt9ZPSgS83Y8f0DOcPXRiTmYeSNSjQ/8YhAJJLhNBj32Ju1VBfR4xqH+RVjCgD8 +By37fot1Jjutnuidm6fh6BWRE3mhdqayAH4EHm4UDsFsePwwdXeOT5NANa12qF29 +aOigD27ZlarZDyG6/MdqcTsDUszLDPrheFQn9884AyJXlwNB/5I8/pmHM67hdGdj ++7aNhISLyYqgtqWgZ6JgEs79gm7iv04cqw9xlcXnHuPon5AoY4kd/V6KuBlNE4ON +jkF/OaIIjN5ZE4TFxit0IJi7QPWxtGDba7i0nm9tIIRTe/MUc5uOBNeMCXzcrp5d +iWGLluwlzXMSb7Ke2wei6JsmRDZXEQi+Lu3s+Ez7xd5NHzTyxA9KPLO0HsO8FCko +FPREribznDzRvqSLuWA8NCglTDcZ6wOgjAZSJgAh13EmGFI+02Dm4gDByzp9de4L +lf99E3cwaC9WmcQNy3yksOGDKoR8VY6qmKC8lLEzk0hFpE+fwKfWS9eQ7lMEsftA +E8NpVmxtxLyZYW+Cod18KanD1S8Z2dALkl+yaOAJroOcT+tkPusyzaS3JEmwj9fP +snLcvc6IG11AcqkRTLQ9cOPYOPKtYi48IisVI1kejJQrHYqyXtZ4xM5RVgzECGV2 +WA59XAOmbGn6LtCb/A13SkrsXYpH2xI78eizLNL6vdc/z/3WYE2ydQGWXXm5W0TF +//5TXKxyvozJru3s2HKQi06FCIlAXvnecHbKS6g9dEbSG5B6imvj0U/JEfQKj9BA +zimenNnE0EpbgGuR9vf3Oh8ueQ62UFIKEbnbVlf+JmvIHAcCU9SJyc8+ol3+eyHq +x9eZ4VUx4bL0Oov3Pi63gM9uEh2V2K3MTjK1yShyKKcp1Eb6r/gKtKTQfsIUn7Be +13nJmEBvsO/AjUh5zUdoYNzE7dAjmxtrZUpRjlPQUriFxA9wPhhpDbOcwtOzLate +vc6uqka+L4Hiz7YoLNvPn9vAlABJPJuodUETznG+ttic6khBMp/ZkckYVxDdfPna +WJKjEmhwK7ddKXl+IQdsdCOcCOEFPKsGKo6qM9bPptSq3NTdNBaTY0JqG2uRG/Us +zmDNRpez2ZgdrhpPCm8rQ2XhBXYTbqVNvimkOTf08Cz5A7bMi3Dil1WaNF2OPGSx +EGRjBY00hWnickALOodvVoCt69GYo5ZIftaerU34rXJwJIxCXPpAjG6Bibgau8nP +fmucL4DjHciH2LCzNQ1lt/U2Pd5vLAeUDwRS5/Qp8+OCNVRjst5OcLR/gXkUWuga +44RwwDHZ5e7CQ3a17qx/h+rYBcKJNU0nyXEP+q5mv7tTmkiO+uKQY8n4tqXaDFEA +6fqHwXtOs/OhbydAhbaMiNrxLa6jMMkgP1+d6o7Yhctsy+Av4VtfKZV9gkj9KeSG +6nXsvj+19yToG+8f0CD7qcboF6DminyDBucYhZFQ/2i6ypH+oJrgI4BjH69af22r +xpE+8PdGenmJQOiNincqVC/BN3QSQDPwiCOUcUGO4POCvWnySyC93bFQxODhku2f +VbNsWeRCbF58C70xR65YUm7ZsGYF5jRz7kjcJnwv+Y1Tf3thAyyEbpjULuZJdChH +F8IX2hbpszWhOuD0UKYAOGaizcxqeipzQHmL4nRsDux9LGhzoJDap2CWPz5KqcBM +K+osVH/7HNEiDPaaWQt4Kka9onavrRVXd7buMAaIr+e6+5qVlJXHQ/uvyEDTizk2 +Lk4q7EQhBMelWIX9eWo4GZuQyS1bcvvwR5KsWQgu5MFK5WnKMoXCkoRdfyAT8HSy +gu1LiVVUPYOI7xXqVTW5qSlfl4d092zREXZUEecA90SyQoQfG8+pcknM9r9LN2Uu +eBXdrLxUxwt5q4OyKfAIARDYSRYX6koJ7LXdVUAtRR3xmaBE8bFwK8CBBcLJJ/Sc +zm1n6HF+Sx+NLDrBCm/YOPfsMCWzbsJK8jP6STchHm4l9JD6S+xLHRw2DHTvVMF4 +q2sHHTN1V0G3ZKcETFj1PkiZEZzxugFdbAtBtkyi/PhV3vM6FHzZZmgsY2Pu/drF +R6BKgMMFt3pmS49F36MerHWXm7CTOstYh1vzCSSsD4cQ43PtA0ELv0xlGqR6iOWH +a3CL4u5tdwrD9CeuxsKz1gY/wyKJqImTALiIihtA4yPhVvFk+E2+45XpSvtKpdPx +2VuCiPa/WVC/ef7AzKPmgRGJQsmF3+tyl2ocOQlJa+r32CfvXyPzqzvIuhPowQcZ +SgFxDM59CrVgNlIsxd3PyUQ4SJMdvZ31FY8c2qj1QdRC3YeBhcauvO43kq5qK+rO +GCIRUE05DlmF4PB5M1gwX8rbgbaVlTqkdpwfE+1/GeJxxLqmcnWTEDBXqA2Yrbbb +zEPWKNrgSer3R+MD4av0NKT3V1iVMJk9O+TX3zGCExre9kNj+TfJPZ5CiPe7yEXf +cPj3RQX7XK9aM/4hvDfu53qCZ2FKZYpDEVUnu72T33cEW5nZJu27JQvU7TvaM+e6 +llHLH6Morfw1GCxPki5ALiB4nOXefifUdG5zuVqw+YhpSY1QJ1LdEp9E1gBKmGTo +Jkaueb1fat+9A5MJKCkKhpoyj0pKlJMATyAmAu8kQlgLr+dJZQzFHwjz0qC8P9Ij +66o7ullDxX/oVR6nLYB8twCdSnuquGvk7aaqI4HvUETmXufqFGX5/jdOntIiyvrD +GISpPLWN70+XuZYHpT3v+hgLW46bgHcsSTxnYlgjDXpasIitRSSfIqs/Qn6usYag +kkvxwvJMoh3hgdvzDdRxGCF1HAv45y/YlDmMaEc3/IKcWn2bllMqGu8SHgzIjwmC +pcDkAMS52Hl4I1sCmVxTJ654sMz56Ehpe/4zkdNu7khaAAkau9noHjNn+/a9jsQD +43+VGgISCiX67psL+GarQRyP9b5nrdeFSXzepggnMv0rW4myKMv+s5MroogMtj2+ +kcWyXpTUWNgm8s9xAd+n6wOBekOk5Xcbs6nswsComjBFLMMs8N3u+b1AY+gaGxtD +LIR5Pms8VJ6dfzAJ5UvIePk3BziybbwnyU1sD+FUoDPIDJSRi+jl/RtJRoGbwtXi +xbcUhnbZtlYkiUAFmzyD2p4feKHL7ZA5somgY38wAjTSNaZWzuPao84HJposlxTc +rd14pki3eAcf0Mrnplq0UwtELyQjUv1TO1k5l25F5kwjC2VcyLe2wS2+vDN/cM9b +oOH1H/AUAwWePk2aaZ3SU+QaqffCJl5EVIEpCNEbuJKk3bpm6AERCOvrM51KQIJU +0tBtybkNcxtIdKe2Fczxynr3dYw1xKbHXW+z1SD2VWQ8pZlkHKmFZPUyxwtAzldF +7G/kTpR6MXX4ng+PPK+nVjlAU3EBTqD9ENr3tj3byyi6UIVAl47o+jUikreyRU8Z +mJr9rwWZyXlEVccdIl70bsGCs27lqPKEcOuaW1A+CPk4udC8pr4ZcRvqH0N8LsSp +VmEh4EFthd61vCTWW+lpRlAQgJTtr5YPzuCtRpHqVBnUe0jvtXCBfFMtfdvZZMxJ +vAcnOVaZnqsHM6G9nrdoGlJO07mvk1av9l5ItfHLdm6pppgCicia1KSL2An0ToDV +NpENjZk5SEx4/YfrHicXgKDHpSOERD7oM9M0UhGkq0blE1lD8n6ZNwRMgzNxrjXK +y+z8F37x7TcgMMGQH1KbQRQnRDarUCAQJ4amfET8bwxJvXdaOqdXNopjVQggWV5V +N0rvcNXP8r8dx0zPmmjfkdlKedarcpwOZGM4b59x9Jv/iJFwz4Ixw86oF9bqyk7N +rYX+6Hj8Zds30hb3AYC7+ZVHo/olMHcdQ/tKoyvOvOswX7jNxD8HUXnzWIXd8mu9 +UD8+cpSSb5bZpco241Ycv/Yn3lUwHjNEqkIICt7HiXW7CSi8blyQelfhNftXxEyH +TTkVntyd+evH8B57y2sgfbALcvOV3yR9qkuKC6VGybWoqut58CywaAybWnvvMlEq +EslDLP3P7gbHgsL2qXjmTdxxAitVy+3TwY4rNLhpMHxtG9qO2CoxU+x6OtaDvJGe +pc2acL6ao3yxRayyxQjA7FoW9nUBjBRA5Z21u3Uhv/TpWoTZBw5qEnbhrCFOd5eX +IrJVY221AMiVIbAVVwfexoW2svoT2Wem+XMjJFnFp8+xD66Fm3+1Lyg0HsbUhd++ +JtpQ9E7+iNIqquRrnh+LpK8mgNwWp23TmTHMYm/3okyjG/PTNWZESG+6AEtwTlN4 +pipbu1rrqfakuWYPmx201i8ypkU9mJk2/3KRPlcdFsgBnYJw1qJLqoozv1MnmcgB +6tzl3rqXTiHHAceWWzexQW3JXK6D9i7GJIKQkIdq/8ZrRC26GXTFcZoXtSsKhWQf +A02Mma8bqOSBfyEs+RJI4PY57m61S5EDUr2fBNNuw8kQzs86eT2EvhQg/hVdnJEO +1rjKiuvNZLtt8AKpKMTNA9jhFlygtynCoXCh2ubUFhiEuLqe5dRsS8jqtf93AATX +D0I1BPuUjw/EibylDV+pyT2Pddc7NAxQsi+ZeRNiKztfclfSKgB9fdY+320tfMcy +x8reX1bfJTYZeZPChxGew+3SojMJ2hIoydXJ0AxoySDc/abjYgsaa9SVLMa88t7c +ctm3hZqhWLw9AYHr0J7EzB5HcOAFlTH87Afe14ownfg+5fKsiodLdGzx4g8cNuVx +pz2F1uo6pL4IvzVmtgLh0tRHa/dD0x2hEKq/YSs0Fq8wEngw215D5EU6esrqLfUZ +FT+UjEyb9KTcsVC0vcFlh8juMAlZ8QG8lhqcSBNbupEprRMzRWxFrPOkVSI/7aC/ +EixJ82EcZ885CO4FdXEQZwOp9dk6YejrWCqk7IOQ4Zr0gnhvsAb+ymxuapxpRg+T +NeI0ekMczDY6aYuG7hBwpa0c9qFSA3K5m6BerPSOsz5E6f0sculzjCxkO/RPsdie +ahrlWDYyb7HfDOCj/EWC5XSceMbU4p260U67NutntDEb5lys9x60ZOoW5amkzpYH +0G7ttX7nQ1H3wZwkjz5hjQgCk7PI8s7/ubIyj0FmACt95p7cXTHHK/6Y9R8MobzC +oZM27RZ9ahh0qyEQVSFFqas69Z2Sx3Q+OyRz81tlZ7YeHBXikjwjN92bVNiXUfWT +m0F4qgtsN0cMNmxzKJNsCkzVC+0GUpysMGNtCO+eV4bRQC8Fe6e962A579xMSYD6 +NDZeCrxUp+rQQQm3/+fghk+C+V49eqtXAjTlrSEe/rQoDgHF8kkDxli/sJohfDiW +ujZwQeQ4+a9PNH0dzoTZL9KPa6lgUBZJ+ei6QPOy2XUSr8y9zbVM5aZeBNRjXDtv +vnyZCP2wu2E3Du+yplzyiVZnsAikwwmph2sBzdAs7QkJquIP5wDoobr3C4HYQIcD +gbCmAYWpaYGdqDYP+7OHg/eGzKlhQvLi8oASPJ1r+LSOKBSq6CboeCLtUkcCxKs7 +FnMh0NuxChkx8zKddpfeDCvFB0o5yDd6JupmgcyK4zb+ahKQepScWLKTCIQwMCKQ +m1UwECA/w18x7X8wrwh6WajU/7HJfDuvz9fkT9k3GbtwBHvNhw/DVDaf3rmvY81G +XEB//OnyQQ6LqusJoKmUmKvoYU3IOPTh1B6MbBwqVlCc5efKD65i52aXJfVcBerY +pnBEDYTePiwaMeV1TIJIp2wbqxh05GBUpCQcGYsfh/MciiNArSbXW9MOWZ7+kmRe +Cx4mlTi6uGNrMH9agSsRUyHJuFFiqMOdEk7WDZSZKIhEyqzNcOspaF11FsRE3RuT +Wck5/TA7qU71KOuwpBgRLW1PNaVBwm7bgqMmzIsplnyn9WOHTNHR/B6t20d5oWGt +Tjfsb1Qc+e4vL6LF98FBTSTj+zqTA//4xL29xR718yBnEbj7pvoxaE1QFXKhCrP2 +UmQeetG02q7BSP5XjGWAQ08WMTS5MSlBELReQ3Ap2cv58m5Ca2FklkAxHG54E+yj +cdQQJu7VBqreDu5PEeFFVNFtLbK92PDze6+iFLFZbPYqV+c7Jou3KSk70aBthGu8 +Goa47wPt7JJexZ0zSGKiuCdMPFp7edrfEWHlKpxzGz6p9TSaBRXEKUVaIiyR7cYq +wVbISiwDb+KxsDfOTcdtNnqpBmZM/pdKvS9vNHQUUvrTJ2cFsmjmjezDSPjMlhHx +YyY50U+ErCsbU8oIpGEZvLK/GxLY4+XBpCY2XKWztMmU1+pnfTjYvREJTMDxDpLy +lBVyYoD9SigM6ivjwNtkU3a2svExjJ5LT16ZTKxFe5vOKGKhJrj63NB0ScB/xyp9 +di7IX/Rhe3cpMnzbcX6PSMKaY7i4Xl8r+A2HBBmFfNMTKRAxKFfzsHSYowGh8UII +UaaXQu1xNG2YnEPdiKSo0XUYkj3ivNOB2QWHog13r2FAOUmWwkZbIrJWZY65Ipe/ +uWljl/TQYRL4mQuTThfOqdtE+NDXnwCUT7pk2U0cbmwoe8LQWUsQU4h/VX31kvE2 +UQt/PhNsatSnzyPnSTW5Nse1fpePOXvsry777l/XpetzelokB3rp4bKdXYn4UYw7 +PTHZPqhXFGD85Ooovm+zjAr/RFOD+SXthfIJAz/OXm7+Ac1nFvS27BoD7Lhx1wWP +zZtIMn7YdHFu13B84qzFksROJlPconl6bqUi1sdwCufYh9P2wzJCJbDf4E2hacj4 +f1ydSSYyblBnB7FHyQyvJVXHsOKahpl6TulTiXJjZWpP3XEqHxKVkxw3tSnEwsPB +ctD/1ib2BKUVFcbluKwBHOMEeHPPc8YOxSsqWsTwpIBMKBv+F7Dv6+zKdU+fCDQF +nVDUMSH5VeVC6be/ik2BD9ouLfDkrKkCTpVOB++bdcm0FpEX5E7SoZSsNzIjs6to +M90RUahzRCmlqsgpn865NLCndE4DOFp67oNXw1V646Rmj6j1VpMGuNoy3cyeWaLq +ag2E+IfU9/LQ0eBWda1K5KJE7GxFiRbL91gySw6wavElPnxRjbyE4NtIy4kZ3bJ+ +QjfCWJtxO+eWkVaJ/wi6RrYp/gmQBF7abjZWbsN9jm06pHaYXxoC0XsdRBGnJRDY +TS8TfVFF+ca2qoWQBMI+TdmrfFRp57JWekZS8Hmk0T2BuQxrD1tNjm+Rc30BgKoc +Awke6PlUmZui/Kq92wPQgXR+uLQRKKt0hIft2nW8zDCzJ9YA2+bywOT8X9iNRiGS +MriweweKrM/nZUTs6kMoYrj35j4TI4pgN6CLZXrBfCOP6LBGEDHRObgr7pntrahL +gqcRcYv+orddbafiC2PjkSZIVxe67nJhx2OiG1SO4/fDQzMmNpNHMuzlztGe4i8Z +aRWNBAifzHgrlJrN0k58OLShajCvYFAZmT6KboBgOMR/zRIMatvB9T+QkrIJ0K88 +WV5ii2pMOC+cnQsN3WcmbMMzM6qsX7oDZoaRq2xGmhfkP7lVmdpSnJnmyZFRK7rr +hRTz28j4280C28IeMlS++acKuos4/C8kGlboThB2urFy15hSdGfu1akVtePAtcCj +UfOKzpkGflBH6KNGUKS3jF9rlV2Hj6FlZnuhgpuB3OVJHKlNty375W0UjLxNnlbK +vQtj+i4GbGupw2/WbhWuPkyljVdsWOL/lzRYCGMj32WLFG4ddQvfXtz2TjfEXAmy +uiWUTlydonwObUEtkALPrxzlmG2HaFj920GX+4wIKnoCqYeyDNlLrcPATv5sPiWv +lpcZOa021Hygb42gvKzojeg3Kedyn7C3IKnqG+cEPajCHQDiiv0eIUHn34ppys/8 +oPOqgq+w8TOiqOHtgthIfoaLuDRV3NUSUgfD1zt+zZ9LwiwXS/t68KvKYWgdidtY +PXhXOPN/BxcvrIIJasmbjuk9DWKteX6CUSwfFBWcdHk3gCOod8dE5SkFuaOoJkF4 +rfXD/dAX7WqQBzLo+xxnRLU07wS7SXYuoayt62JSVYkzV2UnTainpwwichtGAN7v +0SIXWU4Z5esU95NJCk1EOCJtR174IRDObCMRfqsFlD+r0Q+sOVuxfJ6esoBuZuGC +2m4dqV7pJ6kCGih52gkfx1STZWxgkNaCx6+WWw/8n6doObLhjL4FrR+s1/g2AFoC +3cnW1VV+G5k6vu7A5ow1QfFSxubajfk74v9BzmNENuV731Wxqz//Z3rgeECSYi9m +NJMhN0bdVF7IxpnBmmyWbknLSsBaZNOeJi6xpxO3NtfU34SvgGuciH7SzDL/zYtj +aybZo7rnUMJGoU2fkqGqE+glydPwN5vosnW2fuYPmvNKLDoqznCYyu24DH6YwOhj +3aQ+jc4GAPpIKjtUP+aYqrA+sLHirAZr5CrIjh7lx4BMRNK+1Io6aEq2mYnpVd4a +1Q2RqAQyNJQVmyxkVet9WvZEVvs7/A/G0kcgKVlQ5xgGO063Emw4MnkMx8jChXIJ +imUP1wXSeWTghDIRwjv+Yn8zxt/EAbA6zZMF7ZIcYCV2j8Mt87D5P0IJswVFOiNC +IcoyyvVTUR+lZurTAUJfAeddTie8xeGH7xN40OwcqMVhU+w1VNgVtrN9GjLFSN5l +WQR+QfvWSyB2y3L5ThNFuncfdD448eBFkKn1OcGR0RTEZbHBfB1sj5HzSGE+H0ay +MtMum9Eb6KhY+H4Xn4wbQQnDYXBIR1ssaeW8a0zVO+jIaJ6nW3HyF/gF7wawEJXb +mxWDef4dv2spX7RLQC/4ToMlhJEXo1bNvC8TYzOpzRLLyzqXsh7llAXpHLC7xmpF +DX0WsIarO4RciN2I8SFaqqnKpe161tEar0PQeGooG+dYjfQqYNWbudKHWbLwT6iX +7ZE2IVpq2+KOHqV1xQz6tgPn0MK32v87RIkLKpM/lNPVVtFiXWDqsAnF1b3YBj3/ +qREXHi2i5pNzksQ6eTe77fUkE7ftJlt1OVW4PHdHSya3kW4qfv97bG1sXSqRGbHE +SO4CpnZ8DKNsPy3Cc/YGrHvCi1SJKk9zOqIf9HWjF/67zctCmBnM0oHcBdB5ejXW +TnRDGHISB/Yw/tBu9MCHCfhCWBTEXkTipHbr4yZa6R87/nRzkawTiwvV9CMj+1ha +wo9HjMk5jOlxWxAd7eFzz2YhsoPA9vrekjZiOFhtvmd/GBLHeDFRc80G1d5BQMuY +/Y5jEeujrGsfyfcSWbOr6WLF2LTVRWgJ8cmzVvBTG17Tjfym/cQ/PskXSXmuDPrA +vR5ofeWqxVqOrBI5zszPXT99Y3djEWPRWbcfGvFdk99OXrl7Ty+OGTUTU///ldmE +jWd4LnAaBguRKzei5vNwWz807ybsDC7t78al6aTvkl1jhZwKF5ZTZwO1hCZ4xO3z +YVS8EvM02TUKtzRJeATxWSyUJU7vVkLWgfIOw88X9LkOnOhFPiNBB+TpOCsD9L3B +h6DmRCfqcRBIOT24HRTTLAW6DTXS3+uwwqut+djZfQk2iG8wKctgJp4yupJdkKvZ +rUQ2FDcs6Y336mvmWwbW4b0FD0gO5UPWzBVyepdfuxDfXPz2Vfuy96oqF93dANHs +vt3lnM3ZouQXj64vOcjN6GmLzxmHRHSZ05Tt99BqgokGB2g52qb/nQSJbs72icJ4 +KXsK0VKR/BHk6omTeIM+0CExfsv7yp/al+DCmzYMaCiPGqSlmZQmaWxxgxgg1C0f +puRdKSo9nyuc5ZLrzyVNYOkpzFozxFULMkQLS5dNFFXITWJ29GjsPljVHkC06DSS +b8oGSE0N5f1lX+kCBe6R84p8XbwhE+fZdGsvbZI2vxmXFLe8Ye4ZrK4wl8Y6ykxF +qvl0K11uUr3pSwhvf6ZDRjb85+GlPagYqi28P6nLzTnfn0MMzCdHJNQ0ZZzp0mpt +QFHX+BvOhM8d5AcJmSWgJ1p1TntL2WbQhSy9/yybEk+aXI/dQ8NZQWuzFT4M83ix +VSEE8hxnchIxAxgqsvqECBKVdXGx1f7Oj1FyMEfuMaf2zaaoA0dB2RKbI4pqZJFC +2SH2Ih7ERLLnqxuCQNnYu1XpiMQciGyY6fKSFRqE3b8DRiX4jDYn3Gq3XUTWuLnS +Kq8m5Qy8/xwY/0MzNmdhoJBed9ojnku4gvdk0GDMGYmH7TXlcpNOTWiTHZIbKq4A +KHC9hHkO0xsJGyTLkq4XOmAG4SmpI2w770Fqzjq65UP4NiTxGlG2+TmdLaoFeJGO +I6tLmeAdMQN4q2A23JsaSVvrKyPABdypSYwFbUsWs/FvIhb2jC6SQ8uFDnEKjFle +/jKclQSat3H5kUNps4tXG+nf0txey5N7Q+GOtrcCK4d1sGs2kYbd7Ujl3BatH2qj +7jEakTsLTchFE1B13hrT5ML1xU1DsiCvx04mKpYxx4O2ixVBjHmxyXsjrEGxL907 +IrC4LylziJvHwdAUokeam3eJH1SCOyddoFV3+nrNp5aBsVLMQHUb/2u3zlNoPDa2 +n14TB1Jj3Q+9X8RuyqGegqx2tIDhZE5A5FfyLBi/z8pO4+qIxjJUZ/n5y5IdDpjb +AAKc//rIQ9FLqXww+jagAWEkfq9smMdyXYZS567Z+M8o+BeYCzJzawnBAUcc9i9k +jpzPWUcJGXroirg1RW6+KMEjt5d0Nvr8zN7FeCF/zGiPzGC3AqZ1KDGj1ZjTuEES +9EoqmNV3VJbbCfKCASg+2sAaLXDyby8wsOiXeBPKXWMd76/Y5ZG/rm/Jibr89itN +7E6L/geN27XnZQs8wgcsCg6J+NoTfA78a50Md4N3SGptNPZzlU72O7JPALRPx/kw +vjsQr4PWG183Wm26Ggl1tAOxmV4cL7ik9mMOB3HK60ItAcfXidpnp2FAFJz5Nklu +wNLT7s0yc0+g77x0mhksP13gkA+nhxWq4bGyUvt98HLALSw73vOgoH+Dl/s7DjiE +oysIyp/yGj+AygX5r4hWYaaHyZ4oXeFpf1lsnbTN2af/p2ISaN5VvegApXUtrEXZ +eUyjYwIeBmxlvy2d6PW3lxhmQxgePmf4Mzy0pqnGNEOIpWfNUAgpdTULcMBGsXd5 +9MaB9U/8rvDkYfIIhcHhz9gSVE3bQYKUfKsq2YqcO/mSxhnraCE8eB8R0K/Wz1l6 +CjflOIMmz2PCi+9caeQmmsKWJ2oESB88qknwPJo9oofrvGRDsLZ3qyXS0lmZu0vw +zI8b4dLh5j611F99HlKUKYSLSMHR9dlEL4MLoEfoIn1+4HNYARhRxl1a9CFJy5D2 +LV1tNnbZ5EJ7mGDAdm8MWNHNFD6xku0foKVAWOURoNIV9pqxxJFZnmL9Z9VhO2GV +EaUzucAZPRUOoxFyutmxuC+xPn0M+zgx0qxeHtj3Ayq+WZIu1GeCs5RXq8KNmtIb +6lOGGP4qqBzP3TfnsOgxJEGwtafBFB/vGML4W13ZSMbCqrHSo46ZC2rDx8P5gKvp +wbqjzIlHDYhZ/fvOj9vhdy8gRgy7tWPRWCxvVeHD5PRXOpAHqWHDm+QsVZpOp4kU +wF0uzoLHXl9at/DRwCRL7SzlByGADD03m7izfwVnKvPfXHjFAjVGucSpJpw57J3D +VpAK2gU2wA9oO84aXD/r2cVqY9bmnPCmSuZt+h/HD5J6V9zDGO7hMOmbFStYH45l +mssJfPo/OlVddvX/Q4gkp6antMhxEC1GeHLmL+3czD1hZh7UDR6SZRTilb7kZUWk +hENEisBQtv6ysQUiMk7mIVIdOyIqDPTaBpGr4+kTeAPD/W0f7z8qcV9P6IWtPaqT +kEgA7cmGOIEsy8wKkl/Fie2Fv04sFoX2mHo41cK09RceIFVKUHXt1QSOQH0uUzo3 +3lJQXHTnMdlOPep7aIZirlj2XuEqnHvcSumAi0WF+hf7xgAgCLghNxiqIejy6sP4 +tbiYEAK/FjUR9O1wBUyorfJAwvudI9cETA5KtDoNdzsuTt34eXeKf5ZykxmQxVwf +SSWiRD7A22axzRZ6hK7LMvo654XlYaec+oYZw6Br4DceHlfDmjR4UkjlIZDFQl+P +6yJKAsZ1EHdiosDw9JENxiqmcaF0OZElP3Nd0nY6In2stD0GUtuqSCJJLKjzrPVD +CWZEWx/8yAH/WJJCiLECmfgKVO/C4TJKaDsjaiEkHYuUupf/1cmfihLxXj816nQR +y4aqLXVrfpA2PoeEWzxYbvINc7eBxGRTBcjhW2J2q6vEmrUOixKAZrjEWib84s4Y +r+F4DKs0WRVfJ0QPH3S3Ut0ksx+FYnQUXEnD9uDo18m+sEhK8oga3jmJ7k/OAC3W +TE3C0dN9AmuxXvae44O2W9m4wgihocxCcu9E7z/vFJbkM63ZjbO41f8+tQHrBDnE +QkklXZhTMI9VL8a95j6+Q4/t86MJLU1iUxg/Iv7kiK6iMBuO7uXU0ycaZUyGhian +90rJEF6RTH5AWI3SHaFtg6O02XqrLvXp7K/7YPJZsc2O/Ah+j32QcLKqjtMSMtCE +w4sjVnyTMiLI1KhQB5DZS0WmMsAL6QkbLkFhIwdeiLVGtBcr1H9Ow4TMzkcXz2f7 +qEdlE8ZSwE1LOaDP80bu5JmwXc4tf/bVCRb+2nvFAkHPRpq8qn6A3xBV1VKpSW93 +uZLJO8ZCDBMUece/K9oahtluWi3mRJhPuf/IdjfUnkoGnOc9g4YhE/TzeEsICEZU +VqyMwy/YFB1nRmuJTy9YNBd+hNGacWcFTvzQmY7+7zMelSdBgYaUVXkFUZ0t/ADx +k7WBzLqLqHBSz9cyf3uo1CttaawUWcSgwrYndYvMBaYL0dMrTitOOOqrFHlilpcI +wnPSYwHCDe+YrGVJvnx3HsBd81fdnCzAY1rB10IZ6pcn8C3o/6irWOeGWRQFTVwO +fOX2ny67bTRJ3Arqd8b4SwBdkVkgIgiQS+FbvUBOT2HTqevZV2bIS01aGQo+U4wl ++pJ1AdOBO43PiiHojlDXyTjN2sPIhR9NYpVRN+Cnhr7fLwNBZ4ubhgOoU8EoY3lT +FhzNcxKrRjkJqcibJGDFw4CLNZxaHQjdyLm0G6zVsujNC2oVlxEd0Xg2V1YT5Mf4 +IHHzoiQB+XuPau3GPXu+9k+H0NZ5IeeMEwFErnm4otg+QXYnmEYVWMiPEOQVhF0B +vWa7IfHoyJWCPC/wfWFqxk5uNHJgp0aZR9sE8DiPEsNSE3feU/XNn+UCe1QlM11Y +ydg16WsLWPOIYXpUA5HCBmun2AkyfcEey5X8NhssSWfLJ0TTECKjWxSmeN2wxx1y +qFaZ1y+3En/jindJN66U4tSUpVJqglCz1Q74lo2MlEUdLOwIqFSzJDNLuhuQBI+J +5b30cOrLrnsGDyOlWWzGBSX7grmHC6lqhXKSOl63DnkgssBQocMu5vPMRXIg+6pb +h/R7eI69fzJcs1sxpK//5bNFqoJZ0y9n+5qdvCbgWhSHkZ2/aE1xQmdmrbdX9wZF +LlMPewaLggJRFm4SAxhqQ8VbI4LbwqpRutgQL04GdXIHD+uel7cyUi+Vhk7xLK4B +FctU/CleBXHhM1Ya+7YbjPXDlGjMF/DuVDhymEAj3yroIKbTP2vjNetY8acF0Ca7 +V78b8n3MBww/QxVvSBqEtuW4pOizbOb8fH2+0h2EhVh2J6o1/02zNPJMA6KYWkgS +Yelr9FucvSKCaLX1OWXsfBrU7TGYpYJKSm8hvXVmypNKQu7jJ2n63F2TcOfbDJ9J +a7j3B/5bAef7jv9d0BPwBcK2ZcMU1fwMhCOdmIC/vxDxKPTPzSdVcsFHaq3yzy94 +8HrkqznMrYX2DRt/6J0sS2eIjJI+lx1BuK3s4jkeWGuyRKNJHh0MHgtATgydzu8y +0dNtMi/cKLeZ6v0CvmWOIz42GabsPJ+sxTu9sjtULsixJTPOx8sMk8vYtTrtxkjn +nwt9U2EYcDsBo2/R425/H6LvtOS7bMXXdHsZ5Jql2GRInFMT6urcefnej6ClUhtU +Tjt0EZN5zXOoOm3DMHcQIE/fRl5M4eGEGPA4sVlDZBGd90sghuAv4krj9fN3UXh9 +nQ4G7MT1Sbp0i3/uqj/Z3uZAP5GW4zNZ8wonN4RS3nBMw+C28ypUwLl4KHFDhe+i +XluAxLuqAC2NjKb09yy8LSStysCwmQJYVklWk+SftyaBXz3bQ4TIpG774koSScu8 +vnDZaA7STZ8ytGa/W00tPHbgkO4CC3K3/j72DGD8lbiR9YGRDckS6bg+WFqEXVhW +vbogDozak0wglfy1vaLHirujlAfibcEgO8yke82Z05qbNeFJe8oj6kmVhhPIAAyv +4wQUvDkW8oo8xew1VZavqUQbEshtiyDUMYYoXbcT2tTNm5jrb9bB3eDUipSPziPK +nvkAMzfqFZsW4PMOC6U53qUkKXyucO38Oks2vpkdwny63vRNC8yE+OWZBSKe1q4z +Q1yci/BKOVX0n/O11teeBFI+5js4HOYe5+12LBE6htnfttqF+zIMCp/3lI4izS75 +6h5OvJ8uxB/scNXmGdoArHaelffx06RY+DPJBe4muMdQcHj6dZJBN/iEcFGCBUkS +hxIO2rkuyDXWOkm8g0qo0T3pppn0mvUsWgdRcl98eiVa1DYA3BZ6PHKHsgCgnxr5 +v9Uis+sCePr3Wdkzk4K2Tj0PaxnHToqMyYJzJWkVWa5eE5kuQ8djnV1Hrrre58fa +iD5WsCs5J/M/sHG17BurGbwiRjpjfquGQL4LvSxd2+cZH7riEV8xc69AVHx3E4Gz +uG0Pmc5YQYuueXQk9QVajddHmiHjPJf8bUc77fwDuxLyeGbEwHRlgn5VrU74WONt +k0kIpDFRZm89Uz9vZl3QERfukdOdbRZr5yK+aakKkx9QgWTL0dV/qJr2b7OyyZEL +fLxf8+jdX/ShTf0zBKrhAN08mlKq5FZm/p/PGKnkmeBqd+qNRr2BAr2hqN/6AzmR +CI6xFDeAcrpUWLIsxm1+6z91AhRvNy7EEvq5w7rHXQBo8Sx07bCJy6xmXjRZ8rDG +NPKvQFdUUbxnfVjRCJrt7MxoBWb6BTomADl124UpVt754bmpJYKMGYilXB4GUGuC +AaP4vfElJerGYdFuQlhWw2igKvdg26YbMG/kbgHs3J6033loCRwYIo2R02gpsXVk +pPo5W2TLpdn8ZDl5JQO9z1zFlgfh5VzwL5CPu755eE13pt3ZydgazgYgCgD916Sq +J650jgJ0Xwy39MAXfefZAIpkMmad3XzOv6Pq7Vk9nTxlXa9FhwkPV6AXvz9jtJuF +su487mMZbh2xLO5DaWgDSe9Y7G8YbA1zonm50+ZCaBaTHxP99gN6TnSgHz6yBupV +MpQwfsYepnJOgDPUG1DyVAcsAgdpzQBqGjB+lRS1L/HR6du39aKoCQKYgBETthmp +yglbKHSY5P5H4iSk8d0VhmxInnROLlwHEy3/FNUnQDQd8a6jFimtuhVX2Cx5Sk7M +bfLjm4Q3l3S+0Jad+hxbSa1w4H/eNJSY/llox6RCi+69t2DtKkY77mvyElpAFO0c +feIKjKG/ZJ9VpKwf8xLL6WnIo4kCFmRlhJgM1IKUptdcN+Wox48aS9E3kB5LBtkg +UNyOz4Q/PLPsofURk+Qvmbko840pESYhvgXszCjNd5zsGlXKzMYhVQYFztexF1ss +SET0AkUParO41zovAMlmB2CGt0mDBZMDiVun1BdMR+W0QdMJY0dn2eU7QUIU00Mw +A3n1yR2quLoMbE9J5QUvmRLlxL7z3hdsS823rFnK/GnagO3yYov46Nx3RcIFP+L6 +265khquw5PxnsJOvjk0swLnWrGDFTqj9ingSxMW4J07Z5vKrFQVlCvzsUCWDb4GR +i8ma6QLYP7xhS6iUy729H2NI6z9ZefTnFidwOMS8DqkTcod5gyvSB4hjDwlRH42f +v/FZbRlr8Ul73KSSJoP2Gh6KNtH1hSGUVb6R1qRHoZwPFshAwVBE0cYC1TgG0z1v +8tx8NFvY0RwRYMkcYnLXUf96lJnOzTuju5A4BgTEPhnKiQ4Sim7B5kPzyaH4qkWJ +ajBMIzpeHAsKCqSo8X+HnrAexSIWuKrS5nZyT5s0Bw+UylI/DY7cVrkZ6j3lt3rC +tqyia01L5oh5xIculT2/yJxN8/YCl6cFpJWI4KrsjwXW0KJ02qcx473KM9vwI137 +GqD4lQfMVPYyd/X4HW8NEVZ8OTbFGerRmvoPI63erPqDJyWwttrc1RnsMV0JkZEh +KMOrH5FeRCChwuFo06ZS/hIzRMPE7bZS6ZUtbqqeO7xMT2CywY/a1cWXcAzBk8Sf +/9Wm9be7V3QNCtu33IjXZy5+ICxRIezSx0pKlkhjbi5krHcvCgSwwahDvVosNavl +i7ZKK4UFASlHrl82GQfg7lbnPmaUOrXrqpqUEbrhn7WYl5yHnPtGZ33w7ojFg6JH +QDtVTxSpf0pPbjemUfWi5T/msZlwJVT9Mx+kjgFajyG1ztS3GEoLPdQqo5vMLNjF +6yL22MItzoRUxPRucNbImPJAl2p9NKnSP3y7iNe9nDO+i4+wKD1KlM8LcwYuJ9lP +bOo6QvArwAMunxkgWO64uM2mqoL5+2qqWIoX/kOIKSyhESp+emu738SYtaszE9av +//pragma protect end_data_block +//pragma protect digest_block +nWrq3EPDMtEXfKvYGGpSQArDy4k= +//pragma protect end_digest_block +//pragma protect end_protected + + +//pragma protect begin_protected +//pragma protect encrypt_agent="NCPROTECT" +//pragma protect encrypt_agent_info="Encrypted using API" +//pragma protect key_keyowner=Cadence Design Systems. +//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) +//pragma protect key_method=RSA +//pragma protect key_block +AXMNUgx+35APeT+Uh1zoekyaEw7FKPAaxxyAa6Q8Epve4926p5t6aOUqjm31poWm +YkzJXrFJDf+MY5a65f9vjXEYavFbWfqstM5gzpnVEYrCosK5VL4V5haz6/0zm4W8 +3KFU071+dSKb0Ufe4/PRgxBz5L6UD2Q6qbk8pFHXdHqOsuoYxm4jLa0FBY4eoMeF +B3X4RqxbqpDnTDp4VR0rxrbeVE6WR8yH7k/V/F98ngoo+vTi+QAfgYdJqZxlP6nx +g/VBlSVclqWtZDmfhCtSKb81AWK8TVGSJG8BSZvZv/QruxskN8UKeHq3mNnFNA0i +BAQDMmBq+wwHTXv4864ICQ== +//pragma protect end_key_block +//pragma protect digest_block +9CbqG9Bv4IqyciYIBinQCrA58GE= +//pragma protect end_digest_block +//pragma protect data_block +jMNRn7V6p4rxBBcaAuk1P5on3n24ZTx1/18Uj6igM3M5tLkLoIyKq7XHUJNGOizi +iubFGmnNBmakGUz8N7R0wpvs3pIsYr06k67USGsFpaGYcpq8sqBszq0cE3QERicr +kr2hdRTC1oUhhI7uHs7alSO253OkYBfEGn2MaE214SBqNZO8RQQw3sK4wNAOHAd2 +qNSie987mT+rSz/pdMvrATqiD0u/sz7AzOGA65viXK7hAK6le0nh2vkBJadyd4gb +JDcLXjUDVw4C+fOfQrqZC5qctZpLzCgM4dzUhn3o+35n8mJ/VNUTCXjlVh7bX975 +sN23TuEQjAWiHIcCrZab5iTUfHxxLMqRY9njIdRuaYn8pgJlbuBL3tkipB3OSPLo +ztDTxninSSS4/+M8uedRQOk1MtqUhIJClnKf5/jrRphzARSsqvR0z6qtEM9X1mg8 +gyEfKdFy0PAMs8gRy4PP5KhNBipn5TaGIjvurBVCrttdi8hFCXLN4/7vGvXxExWr +A53nxU2X9SM8oreVlZKGkxvPgZgqtTQDO0ACFweu3YD4vbkYDcnUxC/AMARSV1oD +2YlBJVTEd5CFOdJzlqZ3X9fio7UOlabhFGzSfzpUBHLPhw19UmE4g0gZPJwN/nh+ +2ntSnxUVGNnCODuqVGkrPbnl+afOSkFXdjCoOeYiJzo069GqO4cxxB+P+aYpYckT +IDItN/pDj1EgTmAssMMENa67tPZXNoxVVtFpfEQABDmF0COfHfSHM8oyQwSHL3D9 +rY0CjkT/0B82WCjvCwS8cHNmbBK0WyXFjHCcA0MtJ+49qx7p0LA+c50SCAs/Y2X/ +2xGPSp8UaCWfKwdMu3fI2vBtyt0jDQA1ziCvp+2lgS7jGQmw29FoGzT4E/PxNzh9 +shPUHDN1flZAu1kTNQlCettxcWj/N63I8iHAY6NsVBeVDfersE6VsIgkx8xxm8Jn +T/2lYRcxkfUptbIhvwzWtEvXm/QrNE/OAHfhFxWTdt7PVSyygSMuV9R+lxiNqLNj +AivN+gJs5s9JSKqUfZx3am87tb2KvLV8dIUAlu/9VHMs3UA+yEBLLZqkPf0Xad4T +uQQTRIhy1HtFHH3LtNppgzGva+XCfcRdlFFOe806EET7wBNv7QnWCQUyoMD6FZb4 +BI3q3v24VDbus+/MCXLkz3+UKadXzhBmO6uAERFKyDFlGsDaYdEnEnYi5aH270sy +jXf4dVScwjwgacPDVbmOmqAnlriL4BT3IMShvkaG6tH6KqucvMPDRql81TV4SBEc +MwRFUcWH2x0HsdSBHFA6wL8AUr1AVxQFMX5J+kceoXrMxExoWa9u/hhSZ2CC+7YM +/VRFH59iWSrAwb1c6nyoHUR48zexyEqlXjjRRnba83frXaF+8xiHQ8+i39vO1WEd +rpfr+ZhYbc22jY4Pt0HoRp7AEBDTc3UkliSTZkhoxF4m8X81/hBWtS3wwJ0LJ0uI +NKzg+8G1JxV9NavCt+61jREnQihETuYbiGlHs4tfDES00UEAk6eu7Zf1x5EKNXy8 +cA2zpjAW3zyo+s8+8yG5cKWl9y3qSFr46L9Kxiks/zY1lDGEZJZw/T/MPzSpVRHy +yCIBr60yqNawJYissYU6BFXGNbUGomm4zLzNUQHj+JSZCr5sLhGEn/bJFm0nGa3h +Ss2ZMv9ruMa/vwnFpxsvzMgwAGPnUGrbiSpUAEVJLwyL9jEHhE9ft2NochDreWrK +lYdmSoYY16EjfmN/9mBnz0gvFp4G29Mn6huy2gjdd/0kxv6fb3JVEbxWk9B7kNTb +4vxVZUD4rHafB8lsyXCGItJY8vaflgaW6hQTwtuhKPhqFR1UqSqq7maibpZDaR2Q +2lCmHV3xyOIu/TeFySJmWUJWaiYUalkKeJsIAlC8qfwmBEBnuhWondxLF3k86/AK +WcnhX8nG4dRxFPvtn+k8vqz9HdXAzzolG1MEk+l3SbnvQwwtH+kUTEhDn2Yhi/c2 +EqDFT72JrvJFfOt8gluxqI1owS8IxV9DBGK67TC+XtyJS/4YDACd1XlsM3Run1kj +DLJ/KVZk/oXFPNAIWxygf0HgBBfB9lI29i8DCC0paLR+ZYq6dII/5XtCfG94a0T1 +iHz6hsX/lvO9HYGtR+AzFhEO4vdvCgZ8KA+7LaepnJg0af3ndT/elXn8PWwYHIof +D03ScHPq2Z730v6dnhV7CmmPlXCXwnHJC/gawmXmP1pmQ9HD4YesTpdezXRefDzb +H6HtJVecZ+TO1yAxj07FBCG1nFynUd62ZrE0/Oj3OHOdYVZ2eTUozLxJB34+byRA +Q6Hgxi50KrF3ICoK25U3MeuuBsZszFYibFJDTdhL/D32KAaKfYu6d4IN8My+nX1L +jg23UxKgKqbcvOeFR0ZdsV6ksEp6GzVhIb2jhxb4fdmbD/qLnnDSwY47T3rOCWbR +4qg9jQO7GDtsLKpcVkVyiNT/pSthIAtxe1uYR21VOILk2UTRtRXO/i0n5Y6BYwwC +LYdr2zbvK7lvUPFXCVxvrfEMzVBtuJbDcDHumF37BtUwhv0PISv8bvAtjk5KJS7X +b6U5YkMDkCk9iWJC7X8XmK5kQh8LUv1mCUnoCHl8aOp9s8DVCMkMuA9Tp5e/JR9g +KF+q32vuLPJ/YR4PPatNwifRtDIKBKxRIuitbIOb7Wwac7ou+nrk//Rdu8PyJYcO +7VLweVZXKuR/cNi79W4Xys3CVUTlm1pVLzhkmy10NNwsrauepJqyx0SwPhibbG66 +JdGEhQRAOCYvaafxj9K6ojqCy3wuSuly/i030eUcLRAModu6/iywdxl1QY+FlP+i +Pw9+g+NEF/ayntb2lgMj5kITl5vLujiVMZpeKoShIBfF9GNRW4mzeLIh+1pecTrU +Qjvd5g/Utv6OBwHBFhpB1iH6FRo83JlsrjzZiFaOPDas9Kk2pcO3MQ8zkXOUQE9u +AVm7rNYkdo0/MPSASYKaLZ26DVqiEHGBj7GyiW0XAlwbyPLdu/v6HH36Qx0AaFcb +uuhcj2/o/0Wqmnpau8zXT+anvWpTdgkbyXYvzLi06Dr3Fo4nvnxuDVmCaj6EtG+b +ecsh0Jw2/bpVrKXG2fe1N1vf/OF72YvrYXpzEqlkXHoDlDoidpbc+tQL2gjd3Yd2 +GsFuE4P0v28PK6HQqX8UO6HBkX8MXES4xnO1493H0FCXYNVfrvsf2OIXKZMPxllw +JxowGvYYQ2LWxvqM02qrkJbfci6IY+cbT9sfm3LM9JzRELxBgWPxxQy3BCoCFs7V +0wkPjT1DzaX3eWPcOU085wa2vDzu6ahowiCR3YyiU+c1IpRK22qexMov2OVTTRWj +XSNxlPRgfRrRTf8z9eK3JbtZzMVBLPrJwN8zfNBHfp5vkG0FKGnKkpmTjIWckfre +BVC8kmB2K+C3m5r+vFdnCrfN8kCGQ1xN+NZtXB20N8AFpeDk+IHg82qcESPIlve5 +G6OwdjqD4ZiIBZlot0kPW3DGyjfEbKRukxA22HG6TtLTGYFBUnBTuOklw+L5Nobv +yI59xMHSOJkK+GKo4iu/Oj3mvuml/vDzzd5G/2iJgpctL7rqi5XGekIoM2yASPQl +sqaSUBPEzJgPyUKAHbCII3SJDrbf5a+qdIgD3lOrxMV2TvTSwhVl29uUR3eHKfYF +x/QOlR69adcBbbQVkq86CCpqREnhjXzvVpmi97hzDUEKDUrnhk7JF8SIDlRNdTAY +iOrt1vnd0jQlLH5rVqgFeBgkDlnq9eksVhhDK3n8vLll9R8Vm6ipd5kThFZ1MsIP +xRjKu+bdwATXlxNSCDMKwA3uCZWugSnDvBCtkPf0J4AXf4GLZVAG+dRr6TimpHnL +BhvC4V93HuLmYULHRi0FsD1BMatm/3v7ARzzzl3LzgUwlXaiq5PH/D3gLa6bclBa +RRSftYiL2JJGrICyZZDGiqCzRMTvhBtCjJsyZfdrey4NQS9DSVws9BB0Zm5XfoFT +YmzO55TouhBmNFCGqRrZr3qkW99iRKgAXeeVpdX2dxaMkr3DwblcN3LBn2ZKR+iq +mPdyS+pIvjvrFFzYB5aiJUtKUnmNQNbBWnx+Vw8MeWL2kgt6EsBY7bMGDnieouZM +4duqi9rVvIBg9MYQ1laluU06R36rnK31owb2aqRFtAoWSvYdI33jhVwuFchTqQ6b +aw1K6f01AoLdcpjaateoQxEK9AHmsQEJE/Efqq5kV7La/6fUNkMfp04ZkkTL3jqf +XZqktOcueYTWqBRw7775S4l+qThnOIgcy/IQ0suHBAran0lMx40TCejV/mVuoca5 +c4fM3glEBelPuFXwUQ1TphYXqc9Fior/remo8+ovmiseb6KVVbHF+1KD+rkBSE4a +eSoI085ZoKmHuUr8YN0HTYG2oHI2olG2EOQC2rXpAMLYJ12NpbUux9rCoDRviaOG +al6TmS8Ai5AnyMWK0NumTWGLCcVVllijhqOa1b1moHUQ/HfH+4lfsRRsBBw3OHa/ +0XylB0BqMJtVYbOVwpStam7ncCFvsNpTsrYn0oTAUaiwLyVdLsX77rbGso6nOToi +N2mCovIanaMGZTKT8oL6SIIJRwDB7x292koDq4rlWP+wvl2/YJjC4twCkxTGNR27 +MXCkYHdgw+gmFx5k/0DHIESlP4TaIx3eMoLi/D7kg83qcWJgWaVt8W35FeVHs3Dt +RTAwM02hTrNP9TzRchcCcq6qI/uxxWwvvCilW+f7aTqbiT/ZLyRlQp7o5/wU+s3c +V87YAe3sCwopuscvoII550EA/rj6sMLb2i9WG3n1gdaBx/ErSzlGUclKHLXSOpZH +0D8c7tzUCRatu3M5zrkM9N5NimzeJb7n4u1Lno/id6aQWFEZMjmgI4Wyz3QMNyM2 +K5QOYtmKe97QgGJmGy5t/Ij7cyvE3Fk3qlMhLBU3DcT7tAoJ6TCWrWoi9MQgdtZH +dx4Sm4+mHAxgUtiO9mRvO5UBHcjxPSpZVy53u83PKTaFi+W79yhAllZpxWJ0q4gK +jMmFJVvv/bbSdE/Br3BnCpsX7Bbtgwa1c6kkq7Tq/IPwyZtv49gD0fG1sONra1De +ftUobfAvT9pZOYlwH5a2bvjBliIWGaiAIiebJe9SNmASkuzgkVSk1itN+w+2bGY8 +uitfemDxY4InYp6JU1pV9Rza2EC1hQ8ymky1hI521wancoPNQdUxAdaGWHOyxAul +DPjpCVd9Y53g7cerxTHbR7fKye5B1TJp9iEX8V9l99AxsASxjHIcqDvHQ7R2GTim +s/OyKmTKPzqsFLN2VAtS/0KA3JCsJOFB3uj37Emq5ZzrAMDwqjSVaxewQDRS9FBR +ke+kzmnm2vjJDqrROPpZKWwQdXfX1cdXf/ENu93GpkHvgmeVZLJaiflc3gCpQdNc +sJ72sez9Df5eyQkO+9zAsEJN5fqWaamYVxS/R+UfzhJ6zlmF434oT/NGgmLB6vMf +vCAeAQf/EB6mW6g+qrCmoBjR/iAM7saYZNDyRtTxKHLHne6Yhn7dSjuwFT5Sp9ga +q9f0+372SwHSeMiH9hpCHQ++EWGL1kMK8rXgFCYOmJsXGJ5O26E8Kjb/h7sXRWaZ +wjyj5MzuNk2DRerz5boS15j+xKpFgTq1J3s9oH/WyYC6+inEkjbz/fwhSc6ZVNoX +MxuQUBrlJyDxk5Q8F0L15cTCixl3J4M3207+CytiYAmBskB7rSRNWFT2rtB9qmjn +uRKMSaES+cO21kvrKcLPi4SzpaKBLkR7wfGa18y2x793ypQWqLUrNZ1lCzcvETyU +GccXHzXKzRLhj4Auymqt+ayIw2XItJivHIimsLP/+Yqw5llfsuX4QsUo2WLp69HZ +jIgBYRpWmXWdORL2EM3WTe4u8rHfXN+8/ORK8RBqWIo4NgnGaH79AvW4UFGzwBst +hNEUvDSr1gF3FLA1I/cPI8aenbSR+4TKVwvyyJKdALRNbPaTcy2K7UXEJ65twUkO +d489Guq3nhlzfBGy7JQVPIDvLJ4Pmek21WtdTbg5+7UfFDCd3CPzDiwtKjKoWfjp +p1IcZ07zYbCdPdFGx5UtS6nVgtu8tRMyVZhEtFUNz8b30SjOrOiqk/pKhLcAB/IJ +qstso9jpY+QBITO2hQnKdkVMS6so8lk7YCcsSwkCJpc+wS2W4W/MPIM4Po825GQg +/UXlf+R2fy804KZs+DzI78cSETEIyxhhQ3AamlN1U/ipcBN2ouvRM+iTGzIFNJdC +wjj0lyeuBT1MEnoTxb+zTA6eoX1De31MuJs1ba9wrRlkHYlBZ54LLcr6Lh9AUunc +UIVYaS+cZ5lKoZjZxl6A/xXO37/0NwF98VKUyVyDg5X2uTppav0GmDBX2amXXEi+ +PkOg2WxoUmLzOVdnCeMOXxXb0viGNGUp6ZR0XtumVjDNXEqSE1opcPtPadPzT6ge +nyvldWS1Wl/rWgPXxlw8uHXH7q3Gu+FcgRL484gweZUE6SjDB/xHIUeUC0Y1OsOf +MU5dhGgNF/dqOjoqoCY+gcFh7uyTIcV7tfsGl1qmhZolp949ehpWy+sARAd1dr/J +8/lnPKGhxDPMkhLfr8sOYXDjfvDHm7UQCbScEqnyahOtUxAVdwmuwxTvoENwOZRl +89kZiQ+DW3i9m0PYD0jDq2z0j6/orFFFSBeU4PYUEi9fyVHkaype3fuLDIb2jxdd +2rxG5RYnxC+47THSBaZPsvBZoSGklhJsYERiq9hksr+IV3YkgpsNu95Kgx9UBgUm +204t0Dloh/3VlYTPU5J84d8ypoj9yJt1HWHUb8XWcvNt/uzKDq8EycpjZRHw8Zz4 +7f/wQMHMn1ono6raUBsn/7aLPojawHeo3Rfm09kwf81vTX4aEa/fgZ4DvwjxQMLg +8fRJ6fduqgBtSfFTASeqn4nljn3MDL8LJZvTGUDwkEQZ8CggUdRwdnsrk+JBTn6I +sr1W3n+nPyxqsoyNlR/SjMmQ72qtRzeYf5xKnstp37VnO66CUDcPbBBx1Dg9Jcvh +dFPaVLUjydtoxYGiA+Y31u7/9BvDpoCPBzrHEMozUk4B34/TIz4+otLTmbfz+kv7 +8KR5BWmyFi2gN6gi1U/O9YPRaUFK/ut1+g43ldrRXEQCBn8FxwCu8FrgwdSwVt6b +hF4wLoNAIM3jSDA8j7x7D90w2CElQW5eoRUmHkY/fsTiLZZbSvDd4uxcnLeTh+4E +I5gYlzoadIS9GEDdq5oCXy10uxnm84bCqBRjbkcLs7g8Pfrk6TFrQKUpHWaVqinu +RBBsd9F/l+WlwCaDm4KbRm791EiOio90YhpH4oszbM3Wqj04tHfSHJhpAOUFprq0 +eDeY0WYEF3Xa4I9aMigP6stR2SdBNgePXHHhqMxjxxBS0fSj1gGxz+sij7LzizWc +7O2G4K7ZFy0hu6SuURLQru/WLVmXS8mU0NMSDLDPxw3TRUInivMuJr1fhun+qpAI +mLaCrKqGBMRmJZUNL9j6Km/nEZP28qLg62W+qCILzQiuoTtUqTm9DwKWkYGbLYpG +TfN1IaspQtdSOUYejTVF17vq3G/c9jmapJNx5stJ8XmW+e665DFGANRRSbfPkRZP +kEzfnnKHqsV3P/KNmYbGfYgPMHnEOCF5qoodQNHjshfxFM9My6g8fuTcA6rTAeDy +tehxAJluPsH9y/EbBy09R50sXYRfdGX5rKp1EQboee9fAJRBI0T4BZ3sEUmhm8ob +3vjiEhAbjrIdqp0AHF2VzGnfmvuRsPQyJU8rHQcxmRQqkD7myFF56dYUl5/OMI2W +8kjqWcTb2eO+MLXwXuU/WuwatjrklP9GA4UTLslruGyJ+Nq208E7B4kHcDc9NQcv +ETLl9WcRR10TPerVX32noKDCdmUQPzRXfiPr94L533jZCBkNHThapHeQCzNaEQHy +wPmMK3+/5Lmg2emQOLeF3YI0H1XA2W0GfYCl2LD+4JXJtewA/nkCgHDdMxURFqBQ +bUs5Lljc1xu5DTC6wuyfF2f87CVk6APY4ogU+EWzBB9HD/37Wy1GBSIIKRuKhQf/ +waF9H6xFUjkHUlc+5pKYVWd4Cabl2GQ0d9xq8d5vOsS7lmOjCdp0Sx7JyfJnRBtB +H+EUzYxeBCxgStrNqz9wBd5phqOOkiYtsfKU5RxvN+J5EExm0t91WVjiKOVd3Bx/ +nqBuq50NI2ivGX6T4xZy25tK9hDXs1fZjyi7E5C8PHobILBSMZsl6UiUqq6rPchb ++1yuAL2hQ2bDo12RN1rj8HGc63E+BTdE9qMgcALO7Uq2LtLRvDA+WITBm5NSGP1G +FJmbPjznL4vHVg9Nfh86E7nzi4Gz3hR1O6AP5PjMHalbFpuvK4y1eTokU+5JOxDl +siGR/B01nobBsJ9NjB62Y5ZZJZJdJrIM7xprUq8ktk8zAdVuQKJxozkicNfhhw4T +AAwlaVtnYEI6exHYESnEDAsuqWer6HE5/k6FShCuPtbvSZSRUCYUgo1UiosYV5Nj +bHsV6JjXjJ8Kwx153MogIvL66iHGDiq8LEiXhowIw+uBTh87Fh5dTFDejs3XdA+5 +HRKCqko1PEZ15YZ2jXBcHsC9XCy7McPVa41p4l+GdgedcgjlwUWoqH3MBRuc55KK +Tk9ELAT/K+2uBeBiCPwTSrLVh//DruSYM/7qqfmmoCGEXjwgTdpztfH0yCfm6X/+ +HK10T0mA1v3Kbcx5dFimEahTzoX6DM/xVmz1vsA9kbDOxr5IcE9RKB+GLM2mm3F0 +Lg1m/7hvEtSnlZBGrp3VClyL3+UNtIXokXUWzdYuimswTsoY46ez/83chIxWQoaO +LQ+mPRedm4El1NAPEnCRmt97THZTrt+/yv+3egCfC5pG9jxaovmUjSycZfQhfYKK +KbdodSC0Us9pDFFU1cA3RPlAh+n3bXlwNFg8FsR2tUBotxt7sHdIU6mJ8/wL9YNk +AvqA7cVvnhNwc0+DXXC0hnRHZUgt6/1pXUqBe0Xpz/lifyN4OZGUm5nahkU3KBZo +57PH0L/4ZIDJhW5mSqrRFOB1Ap7Dnv3q/awO+3F1lXjJtMnLFgnLpJSr8mZbOTkL +2A3YkSDBD43pQcgDUNa9EyL/fx35Ph19z+96kUCpAdgAUOPQRdyb0g//+mWx2RMY +nulTjxJisCuLRYJJLDel+uTQIr9fDzBThcEKf5jCIEdH4BGbnnL2b3QFKMIZ4Te0 +kH+/z8OhDMNkvOWfTLXsHc8+/CurbIfUyBWL27Rdgo5NWA2XFzlyPo144TbN+vzI +xe9VtGciv0zcuTJqnLJhpCcQOfvRZ/JjKjmWcIqlV2mzbAAtGgGMIrNhxf7T64rS +TFycVxifKd9NCHfThMhIWcQ5PvhEfBj4vWlFsmMpqHIs3VtzijwVbjVtheWC7+6L +0mMSMI+0mrsYSqidRWpaKtGs2jeQrf25ojMA58pli+2kSYt6dyh0B4eMguEV9c9v +PPHopcNwZWrQJAl2k2OVqzZ1YZZNLKC32RTURIQ/hhOk3ujSTK+In+LKmKeGuaSP +SrnyNYnoxpjhBrRuAhXONIz1BaWobdeTOMWfUgAZeZlvEEfF1OHXHMmNSFTlcxoq +epnjlOEPCGKEokUZKqjH5wshYYT9SWIBI7632mbPlbhGwxhjIQkDe2AC4u+ujBY3 +LWjraQv1Kc0feQlfavuXSyPkf3Qx8qWVt/Nk1GQHS/+UTPFdQS8ABUGoh+Xe9Wv2 +cObTo6Dz93zJMAjbGD5+czy5CRy5b3ISOs4I+N3V933hhbmd8voxbljjXtiHxScs +kLcF2yExb1z6RfA3Baf1oofO8FuwmpcublTLgO5LUoAZqB4M57mXMBoe73ph7aMN +C679abxO15jBA3uTHfmlzSp78aM1EjftIwdCIQHNlFJ1eOJFtLgrXP9PzIOhAsJB +FqWgk6WD3yfCzTgUF1YiQTMHdAvwtNfKTTa6+BvIbcQQbmfZhYubSOh2o1gbmccp +8Nn4KhPQTGVBZHhX7IMoQ/atTqdrvS20ua28VZ1oiOPuMGZj/pbBGdiHWmbH0W4i +tzpEyRkxc5iesZoYH5EekLs2iwltg8HZDIsHaA7kWZQF5+T/Gh4TT5cmTPAIwd0f +XFBmWqm/0M0Hg7qT66iUjdXjIZxWSqFvqAShhs2Na1btR+Xptf0IULbP4eCmz/I0 +HenqOcJ2rC94y8J5lCORfGpf/B+LWVedGp3JD0WkePT4F83kREoH1Oj1zz4RXkO7 +irF9amY/uMsJDs9s60mWnsHVArgNWjqtiG0du21TmZ8obXAedaL/Iv0CyvU6SJMo +ZOMsx8ELb8Qu5Cn0bfPdDTsj8AjjAKBZU5PLVoIFVNCQzvP5ZrR5uOuJniwiGl2/ +RCEFM+7mY7dMe/hOj7HY/fHMPzXLa4FTspZytXovQi/fUqvu6AgUHtwVCHxCLOIf +9CXZePHJaASHrMgoKoUYwblFKopB0bU8Qxzsoq4dnEAFdEpeiUlP0r2/STrAgI/d +5dqt2F+OSdXOGoRlcW5jAIi0rhLDN141Yskbnanodmroruu66yrgdVMuQzn7A69b +n4SNk7aNpEY6wGWimEMJxoG/Q+8T84DrS2VFS4sSVcC27nvmejSHsH6WkBtWKIjK +whGQ3WEuz/6vHCImMUfpQnnlAAfdYaR5QQIu8Uhx2S3K6ltqiLzxQLqEhkYvuJJ6 +fKnzX2Lv5C0BudJkRsel7u8HgOZ8UYRS6J14sJ1T90OinUlo4lnoTiCdC7r1+apf +tCM18q3Oy0qUb35IUjq9NCubbMbJQzt8R44g6+LKSirX0IYq4rhBT3vHC6hKdKAw +7EH8JAJGbbXE6ch+8epogBci7Z9KhHyqNGPntPNmdiOUsvxckwCCspTYWjEBXoTj +ZtUnFsLUEj7y/LTlsyI8p1e0/XaYxWOMYLs9IPzJ6dWZSjTi8KcVodkydujSxdQm +XtBMb2SNFsDkp1/FyWF4o14uLMf/F5ry9ubzH66vowwwU3UybWZ/PXs9sBoXOv+8 +7Ue5exCA7lTkxOLmhcmlEkSI4QvpqLwIDCs26GpWCH3PnAN8ktnTSwmL2+KVaqr6 +kwlkkSHb+YT/F53Iggm52UMD2AkOmmtf+8/SFORihR1zgDf1hOdU3Mtx8OSFB3ga +Bbs7JbHTXLIyrZwjA7o6sksAG8jb90JVt7qywR+fBiBCGwFntfEgQx+gGj1kJuKF +eIn2g+/CtrV0CDMlrYpkit62ois25o9Xm3EoAc8kXUBc/DUprfOUx3zeos/gjrr7 +LGkJnhFPGiqgcsIG5C/qpeLzVDAhYXnyCLdRgmyiTpfDGOxhBN3BxmHhRsNNAMGJ +NmbFWUlkse7lvHrIqoIEIR5eIlXRjF76YnImMSXXOSHjkRLzTQPOgSUq0BVkHUmI +PjjvtLAv67zHJvYEj39Ph13RjECmPmAEPIytLaGTpeA9i7ie65yvA8in0GmKIBrt +nQfP9K6pii7lkmVbdD0iLAQ9iDgewpVJIErXRD0gYqc9bz3VBkxIC2c9R+Q9xYaD +kEsH7lpRwWYcAthHhyereakG/T53927cxpwEas6lqKLarczpK+5wSUM6PBs0S47S +QZbaxp+T6Yjji0Iwf2DYmzcdglQBqW2B2U4lzFgw6xZ2OJHHgpKLKEi96vnD8G+P +LsRfyFpkkDEyjrhS0POQHqHMMItGwW+F/QiL0NbGnjhpAPViNj9FlzRjeQKzbTsF +nuNOcl95E7EBiCag9bTncaOosM9bvyHBSHh91WNNPkHkJ9VgyyCOlmEYDvKR/fKx +UOsLiY6nKDa83fAgBpvIzKuyWxFyIPZEHCEjuwhV3kkRKKw4seVcZQ2roDPd3CmH +bEBzE+4UrnxdERdyMp4yg15tMaEr8IW1Z2Rprbivlt9vAFFc5mlX9WQfxiStkzgK +/vLO8MhAvshZLobV3a40S6MKNu7KSbI9jaH8ZeNY/QwBFXFhezn5JL+hDoBsuNfj +3M43wM8rDzYSSWOxhDyBXUja7u2jR7fIw0Wx8yeu81aIHToxFnuMZT79FAu9PIdb +3o53fVhp+voxPUTqpUcSwURomc3Uc2dj5GIK5Rvib6JVb+fctRfQmu9l7GMTrUIB +PGkM0/8eCAv+smUyekbYSrtVuGZCILiJRlIvM/snw20wYNr2OVUrMRkR2w3IX6RF +R7CgsCeZGfO+ZHLApVKclgTTKukMdCK8bb7ka+mk4wcy7xYUHvL+Z8mqtWm1DcBi +Xtf9Au4qgXaHbRXq7bhZrWNVBg57DPER7YTZ9bFsyFMs7iiq6cNPb/h6omOB49Q8 +gqa9Oy8K9rHz5x7ZN1C340ui6+++gxMHaq4QRywObFvCKUPD6wFVKDFDLXOILEU1 +kqStr6h523aOY2iS2P5Eoat50E+Ots5wymmZu2ThDOWzmqWq0WfN3jpJYPPhOMRU +M4CGxqodEXpC+HMTA+xnaEQYJLdfQZbp0JFKCzF08BFnq25hV9zgsAbBH7myimaD +U74zx+/E6B/FjxERcv/1+FXKb+Iupj4lN4vJorH7lsx9ix6zQOcw5FoKPXnc5CUy +WvF0pNvJca+APE78bockpD1jlNlvw75aeZM6576p+XiG2LGktnTaUGfpPowSE8C0 +lxRQiFrlTYayxJIoPLALnodwV3YiGFzWSJXMIcnBznqqzALzVfcLquLzVmIq7r5S +CYn2jeEHD5mJ0GwYImaGBS2uvAKiW50h/Q6w9OMjTqHnGKfBcUUnN9Rm9lBCEMWs +nbasIIzuzvX3gW9kaLAefv42xk5sVmh8JmWFVMoyvPGClx8uLRKBfIpxwIy3f672 +XYSDmYlXrtxqzVgQLHOhBzIV0+H4EQr8MO+rL5XVdegR+eF5+yOeleugXPWuwq01 +61qlSRaJACjQQwCO3hUvb9MeSF9OOqmSyqeS8KARXuoyO+lgiyVwwVSkaTm7B2GG +dnFrJ8Q0P1V3QUuUz0djbRBkTkoOz7hT83jAtDJRjlohaFPXHIyQO1jJdqOu5G9x +uDjwap8M6HV1j0bqzL7vrur8OnKBj2oQflitS3zrgL+IsmwOdakkQnWEa2iZ8xK0 +oapGrKA23+xhDh/aaa0uV93WZz3K5bS72GyIQCRBBowplK/f4prs+CMaT8rm5yY1 +hqvoI2xbZkOp6VDtv3VVwM1RLUTSYWgoYCsbnr3NH+0ymSU1VGipxpbmWGubtKqH +e+5ZxYaiWf12BYwQu+AVysEBpmkj6+e3fqbOYkfJArzaEsVO4sDWivHWlAiYehv8 +7NV+pbm5lZcKeMzRWf5l+HuuqW/x2DIicZjNBC4KU+Ud5OFxbxwV+87r0F/400vj +E61wnBxm85xYzCq/hf37Sbbo0qzYdBgxwbGmDW0ExzQfJAqyUe+EUYE7vkKrlvQQ +zTv6/ycvZhbm9C/cUOr0MlVAgvLbMYUTKYJBzLMg8ZqZLETKoXVUw69p8/ClEDDZ +aPoVlIWPzRSn/h70TU3NFjXTS0bkwV0jxIIIZSg8k6LRKjLd6V/V921PMTPhKCPM +G5P8Vw6vPNh5mjTPVb8KIzs9zW6eQw4991lZr1tTMI/QXF1/SLbHdDThwHOIEcB4 +3qXwXBmzzOlDOBT69KDiHmq6Yshqh2kA0QOQUE2HTLR5AqULZRmvSBksmgRn5jJl +Cr1GI7h95etfQFtButhcheLg2mUCcAcBwODZw371uZ/THQtHc/y32XRInnTWHiN8 +P1DmEwNUyjBuS2Jni5RfAJx18l+ZSWaFIHeS1Wsau44Kito/9rtaI4r4HYbLWakr +cQSNmvUqcNYbIAOYHI0wKh1BuosyaQYAncnNVzA/rcokG8jG3STqaKwY7qCNLZE/ +L+inYgSwN2NLq84xqe1KFi3hItLsvW+IVViREUgPuK4OuuLIlfScvGFyb3Srjz2b +vc8jl9M7Gq+gmavhAG140fbOaQYuRCDYWfYdZIt17QAqVm7gwkKCv+jEwkuamJG7 +9IVH6sxat/7HMI8FCHWTWEO5jLo5Ey1mqzTMSZ3FLnH8WFbWcX1cbnH7b3p41oIs +MiCRdOXKjN4+oRmlAairDVxwNlwCh0cu3cuKNcz2Q5Ncc7096vSrKgSgpim2torO +u/DBW9KGCRtOjDOYbml/7r7NfMJyZPM1dNRN4fJgUFlfPHYozmlkzEgX6yuHArPu +8IwdNuRtmaoUAsgHUoBn6n+auya7w1M8TE2386JD6vDV5Migd4L2tPCScIEQCyQ5 +jd3OdlSbFqZV07Sr65oelan+kneryquyhRt4DlSHPYY4uedaSAAZ9F0RN0KAk0Fk +ju5hzvn3VOjMZQ/MAe2A8/spt10N0E0gFesJ3jd5XwFhGzvJFIU4FAO/XiTZUq/V +aDzjjV7iWV+mxsWsmGTF7jIwdvu4518T7DfycA4YSbNDpPD7DvmPy+db/z8lNrzN +LRI+2RT5zMcIRcGVPY8PT5Sr7skSO81zLnStcSOfz7q8stafCjbUTu0ns2GWh9YU +kdLQ4TvlwTG+r6sL16RgY5jDVLGMQud0zh7dLAV7fH739ZDGo5dq32IlEtGzzSrR +KVG37rbDuwvOrtV/6nF48bTDiW0gHcl7jmLMfZ9VCPn4qD+11gGglMLz6y2zlcpB +wzxUQKZ9vkL8Bwva9i3N0fPEImxVAi7Bb1uvfCDaFQ/H/aIdkca9Vu7FHomRRTvJ +XE2Ule6RxnzTBe6cJ12FFHWGIux6sOoPHzmyWHCqirujoVGMZO+FxpIBfVVo/5Yr +Csv+Rwl+uRgvjM1FKXTKEPOJW9JPk0BP8HWKZPmZC2HsqspjZKg2DxeugMBPBxNH +LSeHgE21L+d9irJ7Z+jX39yNO5tMQyNPNWA7GVEKsEeX1Lk7QDThcBZRXcQBOs9D +uVeGF26xHmN+WtrIaCIWWnzZLXyb0ne2tmJ4/DoyhWStWjWBQ0cLo0YZxBiBg3Vx +86FYhNrcZ9G9ICKyzHkiFjb3VkVvA+USdLS7TqfjA2lwH1izq8+xZRX0O5HA7TTu +I1RXQGtVnUb03f1hz5+DXr6mo5wZXA2a2Kzn9JGfyyBuUFErjCJUxpZkdfcg17z4 +zOsCzA4jm9kGxv7YhdTIBXUQkRJ+D++s5k3d1kcJBmGqm0+WzUGhmJapg0N2DOMI +3xoU67a2ZkLkJUfnK6KK94Sw3xqWktqll3RURtnLzPcwwf3OEYo2SzXWcfXQN19n +YwgWA5wvPbxNCuDzOgquCMt2YFFmJ3LJYLtWbkklN27ugvVMMbzBaxdb6Z1tJkhs +gdrdTuLMWdwHjTk9xyXi7YCl8kSaeb17vJr7s6Gr9Ocawn9lOVNV129AY09WjwU8 +iX1W/YwjB8gIJQDveIXl+p+gHyTpug2FprqPaEwxQFTeHb5SaM62ibvMxQu39NMk +lrvacIJhnxQsBg8+dL2F1zkqtvpW6wNREGcr83Dxw/YWi/xepaaBUqFCgBEv6B6n +Uuw5x7Cw44q55uPV4FUNrwqPa1+jJRGLQfZgOa39zwbNyrLbXnYBndhQwxNw2ZnX +ndgsUzrJy6sz3yYG0Q+TxaD2KJRlMX1whtQJWlYQfJKvlCY2PoTrDBVbauj/SLsc +zLovR85NUz8QDoJIbyGiaawFNPUXPyD5dYkxMwlgWj7gjJnXhMRrf3vtkEMdWdCy +nkWi9U+EqOUqFT7fXY3yZDJMwOHrJiuwV4S7ImTbFfY95UQBgC86U0BWBRVrXGc2 +WpKI9TOgYfW9xRWpdP8yB4SN7Nowr7jiOoFahehkBhOqKTAfCOIwL6wh+o1cnL16 +qW3v5esomCfxQJjkqRwiycZbjpzPPs5Xy1JrvCgldDMunQs7opR60lTUOq/5xQ+y +oQ5cQIIyWN11qpmWnN4aZafCcjSN+JDFl412ZrVJ2/aQAdIB8LN/Ol6jvta6lLvC +PKotpHsRPzzXcTSO6WobW5TV4ofa09st5jm554DeAP5AO4MN89QAKqSjAbGQhmX3 +0CErNivshFVmC3pAnBwsXYxMmT68kATucIUszhobf94CtGbfwMViARvEURg59Hzz +Um4pcOXI+BhLeWQRocvJ80AuyIBKaMnVVfaBZ4/Ge7KzS/wf9bOvCyH3AlS8pwfL +BodZ0mHd8xZEFsf/oed8EEfV0Vafdl6F2Vct7tVq09f7EaUm8Ge1ph6yNT3QD/xf +aSNyL2Z/iESifCedZLbgj3ehB2dmK+yQHbqplc92sJg0QW7tON1tEtPgFWjJD6WF +Xip/gxK4pNwx/a1HqKsIXnbgG+/2r2daJP8B2TnDnhRt2zhJBxS3R5BgrrMzCmd2 +wN/YrelBrVQAGt4b9voBdNq6j5xVGc2lTb3RaDB0ihiYCjYbWvGIY/I8T5R87qSD +lp1sMIIqkS6iIWKrZPJTdJjASBGIfsYzcB8TuBZSbpJdmMEmhsbd9aJVhBcJgzNc +claKEskjwdrGZaZeyupOqnjQv6C690jH2Hdx7mW8EV8BgwZl79FQYW65taTzkc2X +sGweSZHsPyfL29DKyW6dwpJPYBbHCJXYXzXHlOR1/XWLR7aAR0K34r+WtQOorrRs +f6HKgGU5wCzxFr6ESsAxOMmrWRymzW5Z0xfycV+sG32MGQcXd6+UqkzZbEy5BZkn +3uiPZd9NUjxUSyH1XKlDdqBYG5mUznKWSD+4foQCCuQTahfBOEr1zJmZb/5iqs6G +1+QO0X2zSWbY58PWA0/QIhjUOH5Qr7/hW5rP1iwRS9tfnbgWB2YoS4V9XLeXmdqw +1job7M9u33w4Bp14OJTFsM23E3dkdm+W0uHJlmgIFgK6M/cKBTWVQkkRa/WL46+i +fnJI8xhMkueJLrKIHj9CTEru2+xVAMlj5DPq5fi/fOOsn4qbdEmgz0w3zffm2wol +XAzoDEllPuk+yP8lzzJDNrY8zGDdmGXHv7V0jFd8J302+f4hVUEVOOqI8DrtQwKo +oZ4Im6RETTTt5pWBzXOO9f1s2ZaXfggoURuYEaz2xgDYBANYn+rl27Qv8T2g3hrI +0TI7s6wclW07RPONULMvib3d/WgQ3gTTIYpJ4F7aruMDqV3V0/Lcltsz/WmHfsJd +3MLtHx9kiJB+G4Uj5d9jBPoyOAf55DBRnfpwYIyOYfeTyjcShiZ66alafzH8iu7O +T634Mo7rfwGAsEvaX392pG4aFDCm43TNhqj00uGnhj93wg7wE4Do1P1aE5rY6X2h +H84KlNRrnQcQX3kn/ECN64eMO41t/AY4HQcXmZjAeDMLutX/ZaTZV2zTl3zjxfU8 +9Gn1Qjbq4NUi2KgG0MFSUYK1NpJwvJ/8muekdTdf+j3WtuMqmP4wtruiXaLGvy62 +gCRW2AXcuiHNLrM9wVU3T/0SJZ7MsLln+7QuBux6KlsSbRUz+FChPADUZJY0jWrI +0yKW6cXqlxli0kwutgwraIJDc7Rtm9xsNpZ3QfbSm/a0il7USM06r8Pw1AUbTWEh +3MPrYZeW+zUQ9SRJ5TspYUP6Mp3iqjioHeRud72bDjMn1YkdazlMTVm8Yxxyk/4M +GdAzv5v3h4oUSHmgOCAFT46uh/DHOKnrWQh6N4ZDU1TcCR2nbv9F+lbOrk0FT7vf +pl1byI765t8lF8ogfERtsUpuzodxpeHSs7XwhHEXXbzdlU7zwuWQKBOYtUe0kWht +sD8q+KYkfve7HwIXfJRXu8MA5aYjopWG962ANlxSFb0U2U/wjjouPeJUwkSgrmkw +NKyPo/IEt4j8wUOiX4wNi/+LVU/XH24Z+kj5x4MxY6h1AxVl/DKGO6eE2qAMo1Z3 +OYjVPfSAUSa95yt+PhCAlZVEY0CR0vtVZnTCYkBk69t2UhzVMctIeHZVHB4yxp9T +pkzNhALCUEn8qmYDCgC785XIyqGtOTNyFmVmTaJcsWl5IKau9xnKki4kf6O8ilF5 +em3uf4wOm+oYvzYk6L8lekptenv+YxzG/Z1TgHTTvwSjUtMunoj4C/TqSpRjooS5 +rCMEBmJkwViw4UFSC2nTGM4obCYE9xNkz45UYd30ZsdKU5//62YdD0fAYSA8X3Wh +tfqoZ117Aajx/v2pS32HNp4il7r3QrQHrUwgwvh1Kch1ooNwcxKl4dhOCxJye4O8 +U0Z2pKD+RsAuT2grDJX9aZzUMMjeCycdwuAK9UYkxozwpzmKTA8ceHj00BlVAseq +VIf/zj6bFxb2dTtaZbAYGwCuqlfRrMOTGBxTKhZIa1slriLGpl05v0DWBskFH5hF +ZsZ8H64wNP9g+2bmf4FYXLIPDRoNkeb9ISG0KD/E/RVffOexP6InZd1VrfrsVjhY +Kl26VSumseyWwSDzylosi9s7jRGjP/dfllQ61zMtCXjalXHmxErQeAwzTQTgY+Nd +Xr9YYUUmA4uFcJtQ1uYQt5Bmm/8GhFVIs85ZnrZZQ5ZpLDgHa9KbW5Mbij/nkS+q +ZFSb6jQxtwEd+tCfgPbQ2WnIgeE4FrKdAz+By/N1VU5465eQYVccszTy6FcDsuWd +UYb8hyzJsAq0F5NUPzPPHgrjON7wOG+5pQlTyP/T++s8y1fZn2nqGKuvNJ+k7Jf1 +ioVWpcXIjfjjFLg7T/EQUWNo+8LHKASZGkbLZo0z0/cpzsj5QXba87RKhbDUNPq0 +3h6O/reCiEXNHtfSWDR7pAwfo0mh1pt0sWL3vMJBZYDYKPioIcTlHjqB1VOiCgjo +rPHWJXiGTSEO8l/cUZxAfOaJTbj9uvkjgbEZb1kjNp5f2B2frhWPvoMYes/4YLT4 +2hRZUm9GJnZrWTfKm5ncMYFD09dNC8H2Jx84soEYVUBCkGhY0C5Us6nLkvtdtUWz +6TIQkMlPHZW9AAHHLBz4IPlASZy8hCBgcpylkWDnKogjORPOZOGBDTOLB3oUk+mm +l86FmelGnPyr8yA6/7N5WbqBmWfzMc5NpgaviffxJkvbasDoEXODOwBVmKZEnXqc +uEzf6ESSgv+Y625jJbZTs3s1dSjLd8DoElpzCv2vuNyP081vRxfA4/saKT4xhWwM +nXa4mpnF6GV5ZaYLsxTZfhNWiNylF6nkrYFQ12cH5BjI0olQ+IzepFtAwpsFmi30 +eqOCjD0KGMDPwoV30hCsJNkY4eKx7fpJatAXo1NmorZuSRIg2Ny5pnCPvBWiHUra +F4iJREuo9ikN01ivdVomnazpCDzCSVvJIMUJV7DX8FKUkAPgU3gQHaHIg7TfR2Yw +N+MFdIN5fetr//gzZEBU6Ir0qJWTW1HSSbrTXlH1BEF/7m2Jgvwxb/Mlid6/Fep/ +xVto6z7h1wiLY7JHpwh1xyUmjhVK7LuaR9rJDG4LTgHFaiPGZXkma1/HzHEeKOfz +dVgW8S+O6N/Wyg4vdMXOCCMNvCZf6TuGb0J6CydP00Cmm8MJuexgAgZCKqcQiYfr +b7dwb/0dnGl5idB89p6cAoqzo21xaBAbIPNQBuZClox6bStLYmUpF6yqbGe2NvoP +drPMDzC3OsI5BrT3hOq+7z/YluqFTKRusYd2vz0pOO+i02tfXRXI38sCSTdrn3yc +DvNwtR6MCo1xMnmjwGYqA2GjpqiKxjU2vAf55w3lzGwWsqNigp6se+8Z+xUVUmpO +3ko+dKMlQ9ZtNh/Sc3vqN3kRwBz9/uOl+XAL38GojvAxeAsEoc9ZPxre0pXd2TFO +1AQvrKzKnekyknrSCpvDkcjxIZqLuGHISBWaYCQDzFQWHeaAFr5bm0XCaZMVnduI +2TKccBNfJ6SBEbsX3ignrRdlUSTMnR37tsXBnU1RKt9ysgsIDar2k/R0/OPaXZ0L +v23N3Kss+OK6Woh7TE4AMqDiRDAXINp/xyCCLLDvg9V4yAn5lJ7z4M5Q46GxmBo3 +u8miWkbbN2k36ZhMsv1lYXAN3jKOVVhP49sktCpeFP9SxwoI64zIY1DZ66gD+Gm8 +IT/5MorP1r/vygSD7h6C0C6vbzm4lIyFzTurilvDxtDXMCOURZKHFGqDsa/Pdw1O +46bqz+72F/4Mv4OjJawrxY+RfU9Ti0rlsCk73XGF5SrYzOUOC36ZXIX7KTnHXPSP +LPBx3oo1j3FG+Z4GMXGt1DZTzoE/JTE5/z93pmhhimoghHSIOibjSjIyyTWvjhwZ +BhHG28PEtP298FGs91zdGwTNeWqZeDh7YZXX0LKjXJNOzI6D7WEUflbUbNb2Xg7x +R24fLoH99ZyQeO6vXhjGK584ZzRg8jzKSeCPTaRt3NMttVlPM0XDUrswij6PkGyj +YdnOugjiKsQQQyx9qOEOGXJAlU4M1RU2VEkNQuwKqRqsWhaWRtZ9kMYwYrzwg7U/ +9sVVkztc5mtmMIKuhv7OYbbs4OtiG7C9iJx4r7MwuleQS+VE+Fe1kViVYJDwDz/5 +yY/S9JbSu/J/xYmnJOn8s3sxgeIBNA50aUD/0wzkKVkwxKpvo326MhD2DJm2399b +goDUwvJCpKvLb0YVSFt2sK997fHLo19MT/nu55KuldXEB/ppAilrMfJ0tZGIDEby +EPC+tcqV56wkKlrFjqqZeILpAzQAMrBXpspauhB+fuPqPPmivrzAU7KF3tRoCmBw +TCqg1RiSr61IQI2pqd3Y0g+aVRDUpUkfOZnkMN9bt9aQ8J8+trkrBAmC0q9BfGiK +iiFzRITbgmDZRXTcrCqBH/8GVVDDGo0n61JrxFUUE7YBGtloUJctIEQ2GmTKv7f5 +eGkGrFAZngmqEaa1CgGeeVxJGM34XAOfwm9uFGWyguUtzzTQWaOSqrRKcGVrnZYD +aY52mJGZ83/NLTyn9PgI/9wiqfsW3bMcCpjDMzuCjdlBfncF3onpiIoFLskOG2Yx +HkEcwPr1zElqp+Q5B4h1sBWV5lf6kHMC908IbNlQYsSI56Lfq8GGrLz+GUinDE1e +nW7T3lUyTRDmQVJfDOCdGyj3ppfi9YVfkx4LcU1ewNRb3Zh7GbG2eUhmR4R22Flq +OiDmu3LNa8I6jTCc7pqiRSOPETKzV1PSo49P8qrc70dNh6yNg4wkQOwIsYXL6Yss +OGpJF2oJzJhOpUfBE5RtmawtyFTpshNoWGCSVHQxJO8RI9q1hr8EdDN4ldiQaJRZ +in209IUsO2OUqav/FLw2zj8l+qIJVnv18PGSbeW8TGEdLA4qXpFQ0t5fsthy31xl +ZPiGe9dvcJt584Dx8f35f/DThYhGOX/N9dZKrcHlM3exMdWGzakF+1+Ti7vDKp2s +Onyh9o3aDv+YUOKIQMxfY+9sQaJYtUdPbPqt0dRIZtAnCcCwyzbyFXy79NQkYBXZ ++XsIlEERAslkoiDVi8+aAkODHGvraJGvLNlfKtfpPKxAu+m+OoAsx4oGsZAJ3sr7 +FPKXf0altG1RXf2zI5b9gui5fiUB8mdPGvSyjnHEfn8WefuhkOss62m6YY/I8B40 +yBwZlueJQbDiJgXsogoq19HW2c7Kn/aH24Ba/El03bQR7ciocELE/5CHro0KQblC +/AynWGtY+7gIeMCU3xjiwphiwR1vWxBeMzg73Yjt2evt8DM795UWoeyTQ9KCMRm8 +Qle+kz037m7IFfFQDtr/cpENJib29WXExB4ee6Xi3y4/2p7wra3xv27J0f7qTC8D +7AX05g7OPGH2r5zNNXsMWPnAo64luUCsdrWV4BjWWLiUqZmoMHJS2VuhIrXcUYQv +TBk02I0xf9evqbVO/TVS4sssNPav5MBGBwb/q4CkOKsJqY2YbCmu/yeVGDvJABYF +M7Z8buoUzSNar/48Kt06MOuFEJX6Vqb/8RHC3KcrhvLhALC0wtykuAn9xXcw+bSk +dR0h37ef0TffKyergTq+Eie3IAZ355I11kTG/0XxxVYo6rbYTmRKUt7XtioJQFzZ +PR2BePIlOAJofjb1kpkOGOBdHH8qxNEnBqcKAtcJtG+MwLk671s8owuhbga4oh1S +eq7EwgUTx3sz0vRtGNHx0bK2t7Et+sPt8WNgUD98S553oQXQYS0pSfEX9bjAQxTZ +6lZ2aHLU4kHCCbxZRzcCaUskRhaMjOn5lLewp/e4CEP1C+GYrS4NePoF0Yhis8ld +mW4uGsAQpZjzmCUugiq1o3qzkcMHxsivZ6+BQX41D+QE/D3SGykzO5esRiyBt0dj +fLHbPePbDzkMqjpBlAgIub2oKXkTT+F7AUbidItS1yDaTQ+ju6lXDpDPw0KIOm8G +qAKm6pLJqVTn/j9jeM3p6+WUWXgPS9PXUgihdolnNlZ/CxJFBfOK/czSCHg7E/V8 +5P+NnO6Z8Idlev7vfIbiKWtTWjGPEUpNGUq/zU04vkoI4pZNIin5rS6xX4S+vcPT +1Djo60vIoc6EeGD81H2oJbJLgoo3BZ7sklChINoUUhbySf44pCKDLJKSz2MKNqhY +9pBq8MQNG6NMv8rd5b+tUneQhZ9NSJ7eJ5ZUP2d8Lu1mZceTT6ptNO8XMX9+3yDp +J9+GSIeKtcgNmoh030uUJkPIGNRgvbrpc3BxMPTZ1aFUzzv1mqm6k2HbIt8DGpJB +oYqxyKTONgiPyEH7pIaIR0tU6sSC3V0wLrMrBDMF/SjAwqW1LFHhj2d0OcASe/xA +Ks3mxGdC007JX78hJzhODaS7YtXzcnJvPe40JcO6PskaGnlZNk9sTrj6CPk2VIG6 +go4UwNeFf6WuVtJaSCblRvCm0hFBLWtySC98SgQ7BH2Bg0xxfgePeVVzEAazqjvW +IR/0NNGH+5v0xS7k4Nogm1qlGlIJjcF6Rf280XJXyhvqSIE9RL+doWJnql6CvjUx +58aXyMbdKax+/gtHSjqdoQtQqb6SsJ0ehH3IrG8gtByJCNejXppyyMihIxx4HRoy +5+wO8tTDhMkNjxBCjBuRbR4JsNwDS8Lv/KjKEKc7T/95YbE1Qm6u90IZtzwTIQ6v +3ozJLqD7ZmKz0kity+2ZXT/hrZYv1Q9AvuJMVTF7+XlCOnnPh3dXK3WkQdh5dhYZ +kOaM6w5H0MDbBepLzqzyGG6TCA0YWxH2wGA+ZQL5XbRVePQQ5UuIA3nsUWf9X37o +8xURgPiERwp+Hh5m9fNkVQZWXwXiZsF+qBwxh81oUmI9+ngBmysJg7b/XXWn2F+3 +bkTLvZMsLWVBUXYWFsXyRhwo9ou9oujkuHa81ULshzF/wQAiVNG017iGQQz/DYeb +2CBvqBWFr23m3uJRIrzGySeL79KxXuhpWQKq8/nGWv3up8jMA9pgBamaMckvkryw +ndDnfZgL4lmorT3vmIVr9LGirnyigJ8J68eC4hqHlt6fv47estxcJQdmgaVk6DWz +dCiafGHstFxJ03TAb3Ja+VVW8hQhpEZInO+umHltOxPKZp0iO69PrJ5gYcdzQJOs +TamnTqhE6jdVbpZNf8ojKTsZsttRhSdy6nalZIEznCDJNIACUj+yAsBY3BrVHIBQ +JCMVe7PyoHrIdH/2AiwAgkjPHTWFDgOwQJErifKUQhJL+vJw+/FBihAmkEd6r2EE +ukLLDnp0lL9JW8gAoS8mvtVgngZRTZcftkMd3nW8eiAf9Gkb9kaYT0mdarK2bgRC +1+lVdwu9bOofbS/eir45baGDljiGzozWVOdIBRqZQCrlp0fOV/tGtRhwy2mykzD0 +3QM6OYi6v4qOgOE11923EMuops716SQiDu7JN3thDHeKIdDTD9bGb+/i7ogRNojy +hAFxwqJsGljKgBYOHIuwlOAjyki1nCHkpbnCCDGIbJg5NWauBbqPKKEzW2Ez+i63 +IsZAQLS60qB5CHavT7Fc1X6pz6G2lZOMEZlNE0mIjlpeLNeI4eLSIe7PQnBcsOR/ +m4aLa9AMX6G5h+ngmPUvIfA/8MJClFffmCZHbStXYrAtGBHfSVCtoftRWef/20Rr +TS2fnxehwvhSi0MXyd36Umd15gTmvJsAkjEYrb5TcIjXAMT6DC7RrzHu1jZeMsjS +QyoUyGzY9DXrAbmDsATuj0UnF+JoVgN6BKw0SpvGjmjaAUohE2WQ/ClYRFyzWUKW +SfqkVdVTYVBeiyPPOm/nN4iFs+ym7eDmZs1YVfqcO7RypITz4c7ftSAqR08mY62B +orUqgrtRz6ytMHK70kWa3wOhqAYe8Vi07IntguUj+bElZCIqhzztgGD6nI4+OhVY +19sikQvY5Z2vOzpxRbMfBIE0zxBLq6d+SjW5ebfD0HGCmExGTrjFeo0OB0PTLFwS +ESuWAKn21gC5jtLk0n11jzM0Ap7IkXNy2s5VgvbpKxODL/9Ez8FMRxcPaHayEhIv +fMcE9LLF5O49wZS7AOCsAYls5JEE8YsN6tHqJ19QZX8QEzCyuxr6bmM8Sycwj2bW +hOFDUDNuwZCcDKoS2a0yd0gYxrMWJHwN8m+QtR/JdNrh1KO698ywuiUXvjVlxbEa +C4Lp2eGnhQ2wfmS3LndpboNWRLFQ6WuDO0HYwP9DKiwfxe+PFSYxcm1WoptQ4QK3 +gamJKSAjBO3+rgtYe5suS3zNbTnj/5hAu7SOkZJ+VRlR9o1HfYEIcHhSvuzv0t2X +2vJwM7c0M4Z4q2ysvbeQzvj6Tl2ObZCMnbeearLZJU35rZiV8lFxeGVs4T4FsEFQ +blLRMW9/ZX58huQ/yLvpuTuM1ygG09yrmmvZAiKsR5ug16JOnkZ4z/74FUM8zJtq +tHwZbHyF7SC39Qbwo+0oP8egWhcIceu5017ChZkQjKnPQM6bJKCQy6iT9O2wFBjj +1arkHb6gxeiDmaS/WzZAxnKnG55+RT50NuetANOsqFr1KhhPk4RsCAAcwyChpl7s +kLk7BAwhy5v9WOGZ0VizZ3H4o+DicAEOD9Fyu53pUoHplU/f4xJPAGQgkgpJqeYl +lTERCSiyCXNUoSx4rQtAY29R6d9oUNDVmz6pLR5/fuid/ZZDUEZeThDItHtR8b8i +6Qb78DapxqOnBiyee8IdUiXu75UCoHv1VA8UWeLE8XpKud8A0BnxCvEzNN9OR5SL +DkI6OIB4wLtGR9WkCKTLuiS/GkMh/DAyPb3qmReWIREDXfVLBEdfagHlRTv+JMUg +Ky/X1Kvzay2GckEyNAt6+HHcStlUy+nbgiOkTS4U64gpW84vGovRmvuvNAbbKclu +Qka+daUPQVSltDxDoBb66C9QWYYhibW+H/CbuYPOPfX0/DWBAT8Db8xWGosGYAoo +mWCHZaV44NTrS1n+hhTgh3ctqe7T7VlqtjixXHXOS/9s0ok+Mk9AhtSga2DyDUkn +Qyy7Z2pCM5IbWzrIWxQ83ss7RmQlutGYWTy+K42Bojt1+pGL7J2CyY2mSbiQOdYb +BaQfKs6UM6XkZ3nHCuxToO5jfKy922OglLCrkmVnb4dE20oKwCn46lJwpStCLHSC +4Skt0+43e7SKyKJhszpgoNeDcVhBTZpJzAK3K1YOxfhJzdfdoELhCEr/u/uPGJrm +jJusPpfXT6yVtsAFpQ0VhmcLlaDmw1in+ooUsmlsjbKZXs8TWwljY1dbiKxySsYn +6SrN7vcZggtIFepsmRrAVECFcy80UewjTFvDjbbxF8syu4GJwhbDxtXie8HwCUTR +HUwpcPljEejr7edJbeamG/998vPJmnM6TgChNdz2cfsty1WILfT47T0uzzAaq0XO +gqevW/EVRD1lJhI3hQSsTwoxkiBsZ5FuezcX0xRkHx2OXtFtfeVWatTpu4y8yM+T +j+R0HASbTGEvi6n0MGDrY2PH3xu4dXwqpu+8NtrE7EJbc7qKS2SbeIMx2hQGnshQ +E0NpGrmjiELLFuxOqai7s/WQcUpTL24tz026zKaZCB654jz2wQl0UIG7kVq76HgQ +LBvoCH+Eo4DrSAZwRCocPY5+0Lt9eUzcZZC+MGEggGGRU/7TE8jigl7PgX/S/Tpo +StqxBlsZ6IEdEaXvlxpopVsJu6rvPoVIFFkmEDZUPGsqKYhv1FSawKXKnZkEWVPv +pk3UdkKNbsLzov4AEjKvUv6kwv4vMI6tKjPTyra0CWpgvoUSN4vooGVanBS+GXuF +//pragma protect end_data_block +//pragma protect digest_block +U9YB8/0V+ciChAhgBpR+Mjh1AqA= +//pragma protect end_digest_block +//pragma protect end_protected + + +//pragma protect begin_protected +//pragma protect encrypt_agent="NCPROTECT" +//pragma protect encrypt_agent_info="Encrypted using API" +//pragma protect key_keyowner=Cadence Design Systems. +//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) +//pragma protect key_method=RSA +//pragma protect key_block +AdFY3ddNMI5ObsRGTGZotARFS3CJ+vRLMss+z4M2RCmeWnJYSwbOVqDZT//3v1XS +eZCzvuRSef58imif0HkcVPAPNYx88rZ5R5Wx/QsXAvOU+xzC7nw4m79rzsNreJKW +TECIEiIMrfMnM8TuBS4RJ8ixg2QUxCNyypIpEwob+xA9sLT53CWnVC7PL+RGHtbm +dMfCpH7nsJAzmsF5GPYyCnYnSLmABwHoG3M+7cd1fRbjm1u0yGMCX/Vsir61hSWL +MRns9UFy1BN9D0IV7AmqeDx1lY2NfQm/6bM2X90oIAQ4R15r3rNgs/KRoFmNhAfo +l9LZHRSmPOz3WQkMiwp+vA== +//pragma protect end_key_block +//pragma protect digest_block +LMsSFqJZAXHDtTSKQpoQfkCpEXM= +//pragma protect end_digest_block +//pragma protect data_block +7ffQoyizsb0QzXTZB9aeQhlsi162E8F+lDclxV6tQubQVmIF5M6Atpj0EXivf+Rr +uN1sD1vbrdZ31AE4o2o/eNtFyecQnbWEzvmSwipUU6wbpQAWMtosJyZy1FzIiiJs +peAko7meqrTDG3dKFNVp1R4pyk/zxoz9j7UntuaKB6hneenjRexfZWPdzHpjL5lq +Q6Gq/56DOI8x/Vsya5VFd8sx/F9yPeTHwaCrJcF2UNxtNjs+rAgR8J7UWpIvagtI +R1EHdTo694RVmscvNWjhHG+BWUkJ1AD0fjvDkLh3zfY1v8F8aY8ciQmwOsTNP+v4 +LDTUL9KLXvLJzCD8f7ql4Rdd7KEyvZ9jl52HQipJg2kLi3GeEBUuoPae9ZQ8QexG +kAGJTA9wdjTATzO+XeT7INolWKv8rGl77X0csofJnaZ7FwbZ3PRLP8dNiuV/4nKj +hvjCh76+ufm4QoWzFUFkE8hUUa8Ny09X9SeEypMzVYD/4OsmW1Tlw7pACQKlZKwT +TNv/snOfwT8AizSjfXektkq0rRetCAYTD4fN3+VG6TOK7vhyaHcnZxfuleUi42uA +APv/4OnBCIrQptda1yWzAfH9WGTnySl2cAz7oCqA89FaQ+WRMoZYcl23greBDMRQ +YRG1CKII0heGRGRmBFAIVAvhiWwS8lJ/c5woTWIQNRe4MFyglIAwle2Ry6JDQ2Kr +/p1BXvbMYhvIHJEAwlyxiGSpzIjEShmPXTMcVAd2jgqWjRhoY33qoAe9iR3L9+2w +lZnipSUZA/a3SdYXjW/Khpg0dM9g1xfZYI8+UZcEcp5MwCirr0vs+Sn+bbhwUyMD +hPV3pSlU87rxFdHBEKQN3fHLGqy+kWjQi8TlWTOcONJyBZpLszik7GU0OFuW2yxq +7QCI952189hnUKWglpzfcq1nPEPPErZkaER9U07Cx8of5VUW83C0qMI7pqhODwD9 +tWIrx0167yitkoilJ8IXMJNuB78ad0gDok0rYaprZmyKWTJFKs6sR76ATOY6v3hR +OGIGQ9e3/1yS46ZUmcYXANN2v4myrgtzmHFoNf7tQ0t2Q+nEkerCx7jMfwdorQWo +Gnob9eyneIYp8BJyJdoVoJHu54FTBhuP24xIernGP9QKepBCGVbtapvA4PotTcon +OkHBXHcbwZOdVzodwlrE+Z+E6nQLMf7ULJbNgjg/aL4rciCc2UJMcT60fpeXn/5j +w+aH/Yw2PEclqFqUOUZkT5aqB+8CwP/H8XPB17tlJq6nfVYr/uybp67MXIMHwdk8 +WI7iJNSYgbox7Z7kHrzYNQ+YlT52pb8e/mZ1OCknaZAiTr4Dkyvo92nygkAmMz1c +If+ihIXjoDu1KLHVsP9gdAfsnzihTP7tD2I8gYjb+HYo8BxEQJyOtA1j73lkMq3p +3TEiKDn5O4CXDRV5A1Suat0iR5eMsUxXv2tZh2D065Px53KlpyfbSSu0lsX00Nqq +3kuHzt14MCOtsjZIVMnIvqkmbACv+JDbGrQSCCiwNt+GN/VgQSZfXPzYNsF+ozWM +8Emszbz1aa/yUFxyfn3I6EPYA1C/DiLdZEidNzzn2ND+ShJ96iFlqXY2ZM0CAVUu +xIWofUJxIHXi5hL6Zq8w5/HBuz/GUZESTLYfZ9PEZPq/rTuVVC+oDjc9WmwPUd9m +a3uz9hKanHRon83NXXtG5DgmCHhvqbf+SGrw+WsNkWRNFfKRtet32ZAiLJHrcwjJ ++e4Rtd7/2ndU6w94pDJXFsPS22fn3NNpcNNUANnPIR3MHSntwZp6dbdLfRvCX8C2 +8oZ4Jrm0kmpIILGwEHYh5spCLvr92A8wSlB9E+9D/knPDyydRlLdK7LepNJBvtwm +euwrX4RVuzjF4H4zmzTsJbWTrYHTzCP10HGvrGgxme/IWLyqk6HHPFbjePEw1dQS +MDeGM59Vt5mXucQ6n1oWEb5sV/zLfosXxHEBp0owPli8JRbjBVLjQDb9V2QH4lUv +UK9fas97m/KJu4vS4XY4HWAaTn/t7CsZ/BmuY6/dAWZbXMFSQ8K9VYsfPFNDStH8 +ZoGBk5voAL1ToPpTbg3mQefPwvjJpIWNHz3eXFXYHrP7Gle2vWfm0+mvxp+0gUgy +HjcpuJfMJN5TCN8T/gyYV7a1eeEVfYKuzF49jpgKxaAw9IC3LRyKWvC2vhjknAjr +FfsmWYMic/Lxsaw0S6n0Yww0TqXv7IA2OGp5+ZHqxpu249ecdnR0CC0Y73pehHPS +LgPb6ypeg98a2W6SyZFE9X5fRTJa86XXCob6f3kSN7qs1F2A9LdqkhxLLdy0Xueh +oFm32tRP0cYNYTBILCNprIqVBf0g4K0bcbrLkcbT25M8KNNQmCIo23nM0DgxDFSr +T0rMshoo9+mqhrN2JhJYr4Nbf2VjsVNeIRyyD05XJeeheF+yqWYUgbSpWcyEpXlE +6TpCQxciKZa+sdGu3t2U18LfgUzk16Vcbz+UtKLyfhAg/ajB0wfi1tjIjiTwDIiZ +feSn7bxkV0+tDfXBKhOAOc+4thtWjITMZ7UrJBa50phqCbHnA8cD3OLzoS4s6DzG +r0Xbrw3p/OhCyl1mq1McIpmc0/fN6I6ympip/imQtVC4LKAfTjnExsD9JToi/Lxq +Nup44fKeXM78LKg9GK9Z1ZlmtCyDBRlaO/nq8kl6XjZ/F2A5yiu5IxsLgyR/5G6o +No2lV/3tGskzDWFQfQ6kLjY0x6PiU4Jo2/7MSX59BWn6cEnHX8tMuS23zpg8Ximd +oZnW4NuJ3ZWWy+MMIjFklV1vOUYugqOa0cXp2q5yh3T1DsFD+5W+XdZevZTcasCr +WWg8a/J6qqPzvgAShHniZEqeNQpTEIoRyiQg3JQWRGe6gDR1ckJcjPKdpu4fU7bG +bf8g+UR4aZq37yftOxiPme76Jr90ZJ18x0QNyVxxEy17dPGvipnDSgsVg97ehvcl +o+og37CnNHcG2yHH7MnsJ8cDvbjAAVR2cIEhPVcm+/+joPHQlq9Rsfd/Zt9vzobi +eXtvKuLtvqeGjWvPx8TusofyLLeQnZioUUTAlA8rCRjayYTq/8YjFTjaD/uM+Ufx +A8vUtaI+8mnXmaGv0rUZBGKvXithmcAR4qIv8wN05xrEJYD61JzjQSCROtL0vCnl +kM95H2PwfZgHB1jTqoRud34Yreg6/ogw/b13rrc6g+VAxmwry/bTAFrYvySpqQvm +DVv96I8tY7hIQkG2oGZx3lu3b/pO59r+XBrVdVl5L/HkLeSHThSWur1ujtZMWMj6 +d9s5DXZl3cl8zRZuuq21JVvka/Kxl2ulsJd3aw3A6U7wfm94vtEmcmi0L8RKpzEt +qtz1sivMnvXLbcmCEpTXhcRP0WFT9RZWhm/Tr437Fedz/qXCIEcBzxv9c6HjBW2b +bx2DARd6B+A6GtPHl2BYRjjccieoisKMgpjBQ6TSkmr7LvcP80EyBgIr8bc1RKM6 +KkYKaPYKeJJT4p/oxrevIlBkMBysdFrptJY8MM/ig+vHYmQGeaMsAnmdIECLambM +lZhA4jFksonnWzRJBMdBNzhFEbvYGG46KRzVMMNOz1Nc0khzrC4Ueq7q6Ptb26Tf +OHoOvKjtP1x2b0xPkp6mbrjIN6L5GzgAQASisiNcY6+SF9Uck0seYN5pNY0XNg3Q +guZdEs1olnUkliJEVxC66gfUWK6Ud1EYmSzpxU7oJFfg1oq1T1vCCLxRmEKdbQfN +ILUNwhrZ3w2GJvgtcmSPztmQkA9yT46UFAgKUHk6ME4XzreiJeINlg3P0NaaSS7Q +GxhHovLOFjQmPC19a3O5TzouUMuqCuU2O2KewOCTMUou2OifEorpIy/1hvK4C9v3 +5rSXdxpCncZySuImnIEvbq3zgq3704yGDMmhsNZ79gG5zWE56nHuCPvRGh3xigGm +U33SC2gRIUGMFXgIdTImSJqz2EZhOXGsQcampm3twJvNtvoEvyXCRKPx9RkTM0LP +jVdvDvEc10H5LQCDZuMLZ+3nbIG01js2C88AoD0OrQ+ChGu6d0U1bq7n/B2r75lZ +Rtd9fgRArSumnJNB0r6ZyiGDYCDS2FNytLQjM33hsxL/BA3bhIlG86KWM6Damm4e +QK6k+AaaeGGoE3U+7gXQk0a4g3L7gsjBlCh3PbPYQw5ixravJjjfCqhk0mL2kytg +MM4uw4gu0rJXvzcCPmo84BEk/cL8Lm7zOfJzISi0zUTt1oZiuh6JI1sXiJugBmM0 ++Qe1oThANpP25SMnWN+1CwRUSq2rEDd1yQqpuTW78L+qPDnmUNy0rpvCdkcFNSo5 +nibAAjbWuokt7R9t4rZP5CGNd0CyOj1Arq+RfxeuQ7daBSOZL20Dpn+DT8ubSNmy +0FCo0sakIZ2h7SC3lb27cjy+D8vJZ8ARVM7KN2R2HvQ95ZyQjpRTYFh6bX59WKh+ +Qz+oLXAWvhFzrgRqblRL9XrkX3kr631mW14se8zL8A+GGtc9GzqCVivHiURnCnwa +hk2bBdgHJcdUIBazavXv+EmEd1V7wvk9M//QtUPsdojB9pi6Xswk/80Ua9gOCwbT +oZ1Ply6RPRbAx1p3L12cy8mDsBpe27Fodnb2P4iJkNLDBe+REhyKibm3rtM71N1j +1+ZOd+psjcO/C5A9BZkPTk/UhL3beJrn6RBDI97g7wemnERc1H1gghuyth/n+jlb +GuqJcpF52eYzF3HHXvvtpbL4GGnOB6D3xpZ5f2sB2fLEOqjTW0AvDab68XeH5zLd +yYeyLVvERLQaA0gkmFccDy21fPYfbiDmsizOVD3WI+wWfqBqQe1v16TXgId0uOLM +n79RYSItbsuhAmJyMYCk9uyqVjC0EFBdvoCvRVH3aiaj6kP8f4cV4DOJINFgtCq6 +8QDD/pUyS0XfrWBYrZonfAPoY75LQqF0THZyrcIcsiOkcTJ4v9jnNN3nhnJHqoG6 +KGvXifJi0/lQmV3lTGB3MdWg+91W4o+po8fZbqBVZ+1QmAw4F5Q3nP1y99N1Wdi5 +t0ZiqOs84/172xJT50xGfm4yTuvDqSsL9G+gy2fMKzEsDHD/lzxEz5Tpiun5WRDI +SzQcw7ImZ39jjF7V4+s2/91xVMGV8n4awlfMCOUbKNxeP1Rt5C2DVJNzzVO/VoY5 +No7+C4e+qtKnTYVMTYdUmphL1WylS7Jbh3WFk5Z8cmP2pHEm7MVMJbqzF2MBkYm3 +NT+fPyHDhkQ0bcE81p0cKngzR8b7o6NytDQxv6ifigbPmXxo+wa728PCjMeYyodJ +hhnNQgtVO7dLU+YIEPAlQ7XzBknpDjXLpfF4mOUADlJX/R2VhuO8A5B2/Zd0nnZ9 ++/5CdawxNWLCr72xLjwYOw4vDEX0kaoHNnYfGBt93EQX0fOrX2yjZplMsjN6gt9I +Kyi0n5v9/+Xp5b2ItxYYTrnYB4W6o1y8CQTQa3t+IPAdZTIgwQtlLUYouAjaL2rY +jMPMlPtvKM2/N88xFTqxyNA4qNiKKi+2OKZMzEPlStDC8yIBjpxuuvmYh86XO4fl +dtiY3nJ2tXEPwbe9MX0vj/eFOvxv+vNZ9IQYQsfSVUCrdeuEY3Hf1FbWT9PYZlDY +U8B+W9KZUw/x053Sl2yxcsDmgDPPjJeM4rZAYfxrAxHl9SFnidR6iXGhryCs6j18 +GL9WdunamB0jP3i64O9pSj4YPLDAauAAOCMVo9t53eyO0lw7pr12VM1WWShc6yB7 +IWiapJZxyfv80/Jj+yXeSuG8v26S85rep3W6/qu0cnVfh4CK3HfcRicWfZUZ9EQg +nHU2JP7iSWYKILW8CF6/hGPICqi1i1JDJP3Q9PwT7GeYr2gSZvfXVQDMGJVBKz/T +tXqCYonq1s1vzuuWaESQZz3JsQ5O+PomAJs1RWlYAtycxR6aTmi+Io5N7axHQvd1 +3WW4GMOp/JZdkVmb8Pon9+CR8gKmLvbTubCvqnjynESuMzhZq1x6fI3U1+t5fCU6 +3xLMwCn0ypvX8K0M8gjA7FeahbCnx4BrBdX1cc0C2DFvHPGJMfr6/jfGxKBBs9nE +z5c7oCHT6C8tyintrL0CUOIwzcMFk74vmGm0DfoXDcgtfaeTuuWokPiFqQztheuM +FF0PcdR2ZpEFC4NhVO8A3uJzdA1xLBzKBpH5kfSF1h9fiXJ5AX+Orjt9z5NPwEpG +QrD6SgnmuMDaQ0LU+nm0RV610qmKXBRXbi0k+AbL0nCQen4OAAaaGIv7rupgdLp+ +HqdUZyt0JY7bvN/nU1JNbq/UlwmRG3xhFpgQEUKIIbJ7p3vZWeQYghAKG/rL4IHF +2Im9jUZ9uijitKDriuuJrJ1iVhSJxHTMGEv1AEhpWehqorkNSAUUvOnROwsCW8nX +cDURige+eWdxi1NfaWc9qOaEzodCtiHZNt7XUoRIGmM2XHHGP/iA9dB2anCF+KEi +hIoGHnXeSxpoabVeyDZFXTcWT8YvKDMUOjYvVZKjt/iuy5IoxpVoML6HanI+C6kY +WivcMpquBFRhIkMu+QpIz+jQWvbIafRP4OnTwlk3fMF8c64gVTIMj3uNcUPVO2pV +wmGr4AC1+lhINgoO/K1eyFxmd5LMwQKKGb5OQU835HP2NJuzLLAhTgSHXLnVQjjf +V6Tcqnv9phk86JHSMToQj3CweXtJcprF3crf+RhYuP3nxZM5jYHEfhVV9D7c+A/A +xPaUeCSASPVoWHTYNRHU1mc5uvbw1pG4UboGEGfVXmZfMLuWr5SOBEzsyU0VBhoV +v1jNoleB1/lo/WPW7r942Mg9DEQbRvK+5fGShjmJeJW1Zdagd/hUi2qYqdlO2Yet +E1RXhVUwU7PcJiJKgN2gKSa06fP2IZxHuAzVcOI7cgIRFmov9xveoYSyuWjL53yP +n8z4RCVNloQbClWqrse0Bb46xQx0aor9oPVrwzn9uyVAzkT6Vrh0ffceTf92ltpt +wLbQV0T01Uj3r1nwYeuKnSlNqictjqIjri9qbKAipbcsnf1d5zaz/ISICKhapbgm +UNYogoQifh/ZOpWPw/WAjhcKv5LSTX/psz0eOYttVfg63zE4kxup8N0re9hBNfOD +JaHRH1Us+lbpmjzr2qbxn7PkZNVsGrQKleCRuHp7vvexdY2HcylR/NyG5yeAFafS +5DCledhFmAo63kkyQaqmWZGoMaDR1wYbV2UEgFMjfqNK28DbR7NATttcOAoJglgJ +6GONk48w+/GGZ25qMIjjC6by0ERkJfshNlDfYDl2DIFKMtqOb2QK9RVMaXmnOBjG +l/gUm426NLc2rzYTLt0sftau8bVBvAcwp5lL3oqZvTwkttQqgsk4i31wrCVN4kZN +rBgSUoMW5tuhjb30QTIRzAH6VsUzC4MvClsZfwj7pmgzfuT8t64yEoGCLFOjgIwr +vnKqlnPpMcOfY9b8vX4NzRoatTwTuMDgN+D4YfLSj8Gs6Ou0K3h17oF2RW/mIvoh +nnNBLVCz5ExXbr15BeuAhrrP0YebcW6IevvUiRHU7MObq20N2s4/MiuHCbVFYM6E +bLOvtAcd2Njyo2DIlN4lRELc+Fw5Wgs8caW33CRSiePJwTD8Pca2Ngi1VPqg4ZsF +iSN3+OUNFWcBZNzyfzB8bNoD353fe2H1q5r2t7ypWxiZ95vpCYe+s2tuAHohgEIN +Lb4q2Rj6pmQy1vmBprgDMaP/XBNyBFg082wEhnkZKm3Xt5lHdn9VJ2xZQ7qrmUhJ +m1JMOSENyDOj026LGKFBEytyiq+BfDfQ+v9EO12SDMTGkjX54dUO4x0GD1s9IItz +qhWtOC0tbpTwpIoegI4SYFfcx2sadaCXWVpPXN6GrHwtzyoQccATl9ui7Ri/9HMH +FWnwatNdUQTZvLlKvZYKdnme8Gt7US06a+hIn7uU9W4MFqeC5H4kz6IuCnI5oQF+ +CvKihKDcIyRlJWL7P3XYd3nvTLHfYr6LhNLAoV0fauCZemmxnZf1+6dU+gpKsudI +/HvHzI4qPLQTC+jpKR2pfy9MdRR8SFx/X+OGJNtoytyW4bCI6IdCu3x+lWcopxRZ +/SgPODRt5mKa3SmETJk12A3WwYgKNrRaJaYnyQT2cZueoe20cHVEXlP9uXa76ljm +T89U1lXT04jnGmxI6Yt6ne91tzBl/YychYtMTdmUjfgJ6XRr+sNNVwbXHS4lAfaL +A8UILYmjWxJnLnC14mYkUifRB/wqvZivUFY1DvFd2oF/0ikmz2YumMoEbRkf+xFc +homZANeipLGYe+RucQviJx2FMvopzoZLtL3GzQebJPObgVbOQERcaGUcOCnsUlcy +oR2X2pePYFsLppBYgW3tzLukyQZqErFLjLUvFzsomq423L4XoYmAnkP/ToADLzPW +quHiNVSrPpx0OmecVnfT3IuCSkVtpvT+0Gf73k9+OXXgrJNlvFS74kMsQ9Kr2yOQ +cOMvL+9y0/5p496GJe0Bb/oTKPnVeauW63K16ZFHw+LTNecyIO9cCnXjuzqQm4/c +L6VnuBVVKTcb7NU9SCmkEFDO2AJSaKjEC83qdGcLRKjdPAYE3Db5DE0nfH7cJODA +L4iHqngz5v9j2uv+iI8hbO64oq66A0mPGbdEtZey9IM/xt9QdEryNZY0YFBdc68m +b/+fADSSfA0Nmvy1MZFKrPobujf/IHJGLBfrrTdg1ju+NIZ+EJvAawVIebbkXgh2 +DrCLA/5ByYJAnC5gdEgVEP0iZ/8rDFxPt2q2KiYxhHur5k+ZCnBCb9gkPZwgv+UO +kF2Nubv+ohnnn4X+r//xg8HcD1O/0sdGB3htyD6hLsZzut5aIM6wo6xPJvE+TydW +tzalPRKIXZjaJOwW0yDON8qjGXTNG8kJiYNc5bKhyIjG2n1A8Evm5tL5gO+rZIOJ +NGJmuonXHF1UZZCju2l0nyEPwEZDJ7HYRjGEkxkAdo+iSYqy0dJ8iKA7dHeI4AI0 +lKzwFQuEuhwEuZBRQ9mNsPlFqju4cHmFUtZTJVyJlj/aE9pbP2uwNx6B15sD718F +ulJs8iFnr3AvzNaN/fCmKZ4KDCDrY+4EXaGQzQxVvxkHA/5nsMRTOUGt+dT4cuV/ +bGRJ5opE3u6ptn7x7MAtw1Rlohqjr39gs8aH17yPyl2eSgVOPqGWFcPRa9GqSR8m +f3bMCOEA8qrO1iNyD20SPfED0atuwovWYgiCzlf16GlD0ao83LUa/zs3SlHZOMPT +U0SZtp4mU4/uSFFblKXRlp9QcuQL3C0RN+vvP6dexTwpnTu5Z6xgea8OBNdxB5ko +//Z655oCd/HpPVUR0AKbAgoKf7cpp0WjuM3zoncgPYgYunTso/o00hNwpkOf/6/I +AvFZLWDjFNeCAqYqTLGEtGIslIA/knZC98Xat012UqOFsKON0d4HSW0QqSafLhwO +u63szXlx4DfZ0IzTUIM4CVgCBQ9RXCOqf8I1fV6CiLkGGnd+pMYPVCooMN2XDSgI +UPHbhfXNGShA5lywi4M28BYvf/kuld+VQ91maf0ujt5VexGQoycqxccFXykmA21F +z8jhuKrhgNV1LtKVndjqYMIRpsfGwabGA0wAcb0YFVNPEgvzKse/QbdpvkMkygXC +I5KVy8uqMgCWG0WuMa/gIiS6l5GZgolDzUnCi3TLNVNaQp85ORel5pt48yHb5Ip1 +UBGBOdLwKUuImJKR30sYhjxOJ/I4BanetmQ4s7gKEMstoX5vdlTwWM2v8GYag3nq +f6mx4qUj5dSkOcWjwis6h70ZAaPZsGE8xKh2LtDajaFowxtAc/rvw+FehQpDNf0J +cMnJtPtepA8XPGwmMRWu2takrgLs52V4TNtqRlLQgfXbkvA2Ojjy/wDvZmP+lP6p +8UKMK38J6wHuc11SRGm9svDYh54qHNuOnwtFUDXjVZ/5m127vm9KM428jKv6G4JM +Jh8tj7Yk3nFljpAZSgRfEPc4mr4O+ucFqwXpidYxZQfOw3Yq8PFtNo7xzbu3l1fr +ttmHp3Nm4fsEiI8nHXbsxUi4wHkC442lJdrRenddGVsToon61tD0CkO5LQ4Hned5 +rHL0IZ38yFK1uJcHtNa+HbPLBgbA1jLu7nwEubNZTERlIcwjUcqoSM5Wnjk8MvZ4 +DrHqPfq3bevQEtATjjuZXM9jNcgHR155i++X3pWJElt6otvaXLSnRDIVoZpuTwtN +7gDENJeMzYF4hF/TH+q/EEsKf1OkqREPHjTZqn0XV1carslIwCMryCqZLo3p6hCY +d2I4ekbFCN4egs6WFCdUbfc+ak97f5HzpwObvZPNWWJ2AECIHOuF8E/Uv9j642rR +4foVVedYDY3OGUk7jfvOtyumgZv9N84YuPfv+QBPEUFL80zThUVWECMTh6rjNwbv +hHO1pLUjMWyYuctqzzlIMHvY7recAyOSC+a0e8K9wWZwbDnTC3mhLLB66YisJZev +TF55Gq0IhRRdPvve0AgycYj+Jr/iqgM0b5qiU0PqDvw/o7hwMkEDLwgv4fqk9URw +ZoYvGsUuVSGhrn2PZL+vvDAIlymbVvcEQLwN7/YtQc82iv2gvpVp4HZo3TDskDzE +i5aJkGAgZIia2V6oFJdTmxOV643ilQeLLU/khvwwl9xSGz4B7lrQxYq1CvYQYvB1 +I3wIwKo22aCbh4oS0O0a6p4TU0/LWzrWXtI3A0SVrBLqJcbbNi07r1C+3aBvd40W +Uv6bISTXaTukuNWfzP9zDSv45VIck8aSgTVXm7ZUewq+Ns3noGgrr+xg9nOwIuzT +E4blzdZF02WRTgnLbFOhB/EoXFpXvIGueQyzwu5GcVh6rPykirD+3MraGI46mEKp +GAvbkpAA1EiXj5vKGfzhOni6+/CUGV50LvMDu9/6F5I5mGtWTz7GHzONQmqfxVXk +zxT4Xvl7Wje/WZ44fdk4EFwj6naHGmZm/lnuZrDUQFF0sT7KDkjkjuvGPRgULYZV +m2c4M+uVb6GURjSIW2UM0G8zQkMALS5pVLxRbCBfejYii0jDN257uXFrv6o5CAKB +zMDVE7UIURftHjqnRko76WEpp8tDh6QxM/HtCnkToh2kLe3aZdW/ZGVEPtrLQmGa +NENtXRjWn3tqYlwRC+UoVEs3aIQ1rHOYBTFjClkC8X/mx3JUuPpl23ptrZJpkvyt +AzfmgcHJDCQGt2WEWp6ICz5abL0jbFwnIggkGeg/SygdjmZK++1kTIl+v5m+qvgr +PW8doU/K19qaYG/Wx0ftwQ/6taLiG1HvBs1UA3Sn3M/zn3Jrf02YIEe2IdBwdDWI +nJFsVj/6hQ8ot+BDRlY85iQE9VpqDdJbzy2z5+X6lV/UbIqssNL7z8y2TNhe8Lo2 +dtCEwxcOUklIXZ92+sqr9wANCARZGc/QoIZfgT0DFxUtT1kKOqb4jOSJYvq5BZ0T +3SRVxtH4iToPTi25EgZV9cE3WyrWjn1Jdnrh0keMey9GNAAOOl4Zx6VTnt2pGK88 +UyNdqDgdwudgyyWKpZFF6falDZlDLZ8YNiG97fbE2xoZhqNcUy4Wsgv/dZxp1z47 +eloOdgWrKd4ICLPuDseyw8zTwDsDPIurGdoZPccS2Bf30HaHFrvGQZ3kTITAgkEx +pQAFQBOQ5YkQ7pIApvHqlsBtB29PBXPT9tksUGwV+W38Tb+l5kYHhHQP2MSb6ez2 +R3EjTfzCZZCN+rJ61q7p4CBalx27R+0gbwnSvjZVMHgETddlIecLmN0d6Zj1bm8K +GZ2Av0CbHd82JldqIbL1kjh5jdy7QhE3T7MIY7HL+x1hTd/fTz51yfSzFnGhepcP +oLdq/4ic5WN8NbKx6vY4j2HmUAdFczW8EoPUmzOUw+aMmJqolEORIBj2nWbyRwPv +C+DgyxAyTrwayuke25m+NLWdWDnqOImkcuj/RiQL7KS6YF9Bxm6eaHTHqtTK8QYp +svxH6DNzs2AytX7WYTBpiV+nppvKFdszCOdupzEJuM95hbTyB9YxY3ZpWPuBqIzr +nlUSpQhUtrvIS2gUKTN9gJhEiAn6k6pa0oSmQ4VwBEy5ahcgHz7kH6KU5dYmpKc0 +gK9xS59bn827QG6VHMXrwvjVNoBC8aaLIzuemWX4NPXlmYvl51k1nCT9eHu8kXJi +KqDX8nq8KLLFxyIZsSVSzt6a2WNwNoA95Toh2XPlCOjUHh7YqpAehliD2ts/vVDN +OgiyfoScmqmi58x6OKgmi2nzdVBtRX25RaMG47AwGK9x6A0xX7LPNN2tzywWl6Aw +4Zl/bg+gs6OzRH1BJcrWiik9wZCWDUZfFnxs2duHZcT0bBTR2FvcI0Lp5bwzcGZ/ +jTT8XKUsViwPoGkoHkoD/dFrAhwaCMhi83AlY2djIbQSoI476oVqnJcVsKYU8riD +JVAt/LoIuGnLGtKKzXDREWInm5iIEQ/tPHr7QX0R1OM7ZAJcC/vbppJzSyvbeGc+ +8wTjnk2XlNAGn2KRA41WiIuj7nNFaTnMeVoOFG+WnQsiq369TDy6TuoFjpfs8Wjf +OZLaxttpbfW7mPSRGHQOnDeEImmSP34h2ImhiJX6pAO38jH+ey8NdnledTFpfAAL +dUX1DXRmOEFlxW0/oPA1P55k6e/nLYt+tRcPbTmJi3hooM8A7FkKFmFdJKVPyjEz +AT7NiuXPfUuBGLwofqVTbUyncDEo29zDmHlxPW0l/ygrcH9Pxpd/22/Adphg+h10 +L4WwhIoMeM4OyKyKRAdLxFlmt12CwR1CRgeXFdIbIs2kYoUKgm/rszhI1usmayrW +7vEu/U2XaEYOr0ytSGcSAh2wYX16/LSQHgdDkCxjrF8QJPsoKBKJ9NziXjlc1xsz +/7hfnizRT+Va7f7zFXQ1vw2mBtw6A05Th70nrkPLbumMLMCoKBFyxQJ9Y11bu3tY +TfeE68p4O1sRboTKLcD/3rWceaB6tguV+MQcHzeAGrlfPTupv8WJHeNo50+3rO6d +JgKtIyAAk3mBo/IkZbFjmwRO07ruiDpVqBiQoyNmq1cCBsIV6rNYGTz/0w6axbLz +cdqgQBOG7kZVgZt2/54FE106il4P0DVJb9RKSFCUVM4abmLLK5S6WwJo3xcNF5xY +M77fn1gSiGYpa60H4L75/ehB/yJ66XnNwzEIioi2z8BK6RSX7JuHhSjGxmYshQp0 +7reKuQ/cY7KbelFGE6CipM2uVCgIPwrHZZCN392V2RIVrpVREZclrMFg6XachH+k +lU4p+eeLCy2wPR+yXgfgic4sOmkTPH1iNG1mpMK2rb/okmu08tJZhRchYimuGINk +uylnfyhsHWoHpXqtZyvsZNlnD6Aupiix9ppMaNN8tl8CTNNppOql6F41Q4NVITWG +Uc40175v/Au3LMMKPyhnrHq1Karc2TJJa4jhkQHXX3y+al2+1DLAlXCnTynPMi7M +Ss0+GxlRepTvAta5rQ4DHz4R03QpG/j4+cBGdpxaQrNLCXLEaGSGzbN1b9p60q4m +ZJy2pGHHAv+A39yDAVrUjwRl32/311UA+ihHzON43ImMULN/lPn0l5b05s5SYrVg +9b1Hl4skibM7XJFFxrK/9FPlEUbGykV4oAgozwC6u8Y0INoYDvhjM38Dh1F+BWQ/ +5pEleEDLcMQTB+xT7sv7DndV+rqJuli1rIdjVNTeUtJfAbtvCzyU9duMWAsF3C0/ +fsVpa7qTXUyCjjN/G1G72hv4E9pRpafBZNYsA0XJXwrScY1DLXsZMhWmw3UwpDrk +CTxUYKHJy4QO3gXPk3VmTsKrlnVtgzF0fveNn4yz1tXXJhA2HxDh0liDv/qWcU/j +b3774hjmiaJ6Cjr/YPl6p0Uyoi+Dev+qD/h9+A2sfpyQzdK02k1kp2Z0/TURK1tq +wKA6mBI8F3HBWZHu1LA6phLPnOPLWSzafX6Cy7ql7zbzdUvrG82692GHtc5g5I6o +84+m/BvaSR0k1NSFrDJAKVhZugYuYFnfoYv7vD8orjS4bbkZRHS4kkjKCiE6CPKe +UQkdWRCfr2gqr54JpKv5dVW6gB8oIjG6nQeTG95QJXi5EunP8UyDv5B2ysmt4jxn ++Ftw7hD5t7zU518RVg/HTQE28cdfEBB8b/a2WYlb0Zi/Mg7Ygo/75xBuoY6Om6cD +jStMe8lKcH20rmJtX8hKJO3oaC9bO8dBbg1UfuCtoazflYZoDxbQ39ArA65V4gqI +Mx4VLzRjpQH8wOZTlFoMu1edZuk8zz2uzGSUXyGx6jybKece5vN/FUsT4o63IAYl +bewSdDLA2lOvF3pess5m8RKa1Y79S/DlyJ801kalWK1auPQlDBY3rqF9QOO5tIqe +bDAAx7gXiW5lDy9Li1L5oOg6/JerEOKW7wdRuOaBINDSdYvmtZVW6iAd4Fd0wWnS +/Kp9WqgjV9Hdt33h3AeI/U2RmEiDZuS1eK1rkBM3iNzlmNvGIiWKG7G7zLe2VzVu +ahYSinq4BvwSrLLqjbeDi3wgIIfOO+KGCzZGYZkSkHF7SIoVVEdVzJSPgTfiYgm5 +QiZVTcS6pvLYKBaHwZQyaQrEPSmaTmZ1kylp1yIYZzmABwIm1RoO9/E9n2D+hEo2 +RJm4Czop/Y1tsh/SgASIg9Xn0Aj8v42XwbOe9TxqQH9BvX65hh/WQtJ6bFS8QmnS +W/GfmpYNpLi3+cktWF/hTbdD4jq7RIgiowsTNAx4zUKx6gSzr9JJyj/+n7kl9ziV +ni6ePFz0nf0b6RnjgiYDTWfiIeDKbr8KBQ4FrY+kEkgiWlSwHsiUc2gFJAOq9Rif +w1+mOZOgXBTyGDyAEzmHNmOiHzLEfNyB0wkcvf13MFrZCavp/9tJ8dnCKZG7T3s9 +T4Zqr6HTv1jaZ1j/RY+V+YBZzu9SAyrq0u5BwHMNSi84OdqYWKPB7CX0qC4DCKx0 +bw2cwJUG5IMUC1qTEObebPhL5zWdgrqUshRYU3M++aa9G6GMpS8eeePImF+Rkcmd +dIsXbPRfANS3AbXXOj9ag268hI2M62ns1b4O7yQ7Jy2ojROtCNUOVdv7BFE/wdRK +qwZrteY8NhVVhu58UoBb96DhK5TUqHm8J2JVzTYgJTGhSheGMETbXyqUGlaAQiFA +DBqTppU8oeTjGjrxL8gd1D0GriFCdX0oQ2RC2tjyrgL2dEB6nDOlV4SLcZ1N5Ua3 +XTTOKZpCK897PRV0/iUI4m52eEiJ3sqrquGhL4Tdql7UKz9HENJ8OnDfcOKVeRkX +UTyJWyja5tZmB/cb736Nd8hVRpEVnJcOLOLUB/g+f+lCqLhkXvNjYuH0KrR9eJXo +bJk4DHv/iAR06lPrNM9BIKwFwPZTm/BZIRKYU3tjddUIsG5T9XMpm/WAU/vKLYMn ++yICXUQ7bQFwBFkZZpprppn0a3gKV9Jd4UTvjswYZcTTZ7IqJSUDhw7V39K0Br58 +vwpSntfJJCvW14TaVZvcncRUa6ZfYrnPUoBdr98q/HvNalY7b8aPFDOTd5tVsU1F +Ammak2+cek/EwlBhoE3bsCutiGFUoU/rJDOJBs6cSPZiSoKw1Xh4BJ2ARH7ml+Mg +XtTLzCrTtTcWkPmss7/3On0wMa8KxqsMBURfqGIv3sLHBzQHGvWLdrryxhtKn7cT +iTrpqYo/u+m1apwlk5a2CCIJ9S3gVMOpaSG6Ek9+2+YXPMhJgAAfU2Ddd6761Oqa +DC2HLYHaQwgArgkA5+A4AgYTFiyLJpUpO8Ez9zHGk/SMqHO0gwjyxKxQXsSkyNEW +Y6zj2QxHj87qqp/yL85R9aeQMVPHBT8+0DC8mh2U6FjqmfGsBl6/3i+aL6UEBOC0 +B4dcXcZMxnDK4V/uC2PoEm5Rv/XHS5y6bRqHBaQpvJYriKLHXagcUtVbkn6njRg+ +gYA/FAKra2mM/B+P3oyrnoPaPWTlRY4eKIYyt5glis6RIuDXN/jwiahIMBu8SCm4 +MtkNuKmpvgyvZICahSQ+8i9F0/+N1qRX9bt//p+FecMNvFTSUMzq4/50R2XI8zAD +ocf+eCWYsrSjbWnsrP553CLpVsCyGx1XAFFoQE3KtKPqMEiZ4BBe62/TATRIbG+N +bFdVD/MVGMQQ6ZmJmjVvBPqbVimHPmY/duJSLepQaw5ukI6kGBHbK+NPTrdCxDP9 +xcWpVBNS93KiR9CJ28uLQjb6Fdd/FR2fUt1L/kRmIRwaZsBoKZ6us4ScjufMSEAn +qLkOb93B+dEHGVmZye5VQkKE4TzCJhd14U1DCrCnUyGab63jy2lp3RigK7emjW8E +OWiqLV9jIiqhc6X5z8frKoQlnWyT3akvep7WZUqM/UZjsIQv4BjZbcmfBeREAG89 +v1A+dCRU6BnXIZBcbTa8A0p/lJQQXeyxA+UGma4UXthrlMm4DbCVppkkUULEDcbe +gTZmDCsNg5GaK4VrmoIM2pnQ1wGsYxIIzlxCHeNP55d63C2/Zqf3m1IP0M5wadKW +UlU8wtQZ6eftzLOjKjoAP5Ony3reOSacrHVB2UMR8vKiCerm0RmAOcR5Cvvtvcoy +2uFiMYTvOVpIL0Yg5RpvxzHkFUfEtYOHGhdv0sO3SBmy4z26Wj+tFSTE30Fr/aCz +qArimvElDG/1iwjosAo6t0uuUwzawDte4xIbnkZlzI6AkA7WnmcPWVanSvN+drgb +luO50aYH4qm/RJ/Ycy/VOHcqrhA1hv2BrbmCh+nfYEGHkiak4zO5H7uYee0PcOv0 +ReKkm7W+4gaykE44kVhYHMfbtAjOxlJ6WrYDp0vugocD35SOabcsr/gVQ7WKMoY8 +zJlxzJuya2bFAQ5zkMrbXZMOwEauQtsrtf29Be3RxQr4Y5DGRR0vXUZricU6Kzst +Sr/lpU5mpTExpCFZm7IMHmiMSKoqiHcH8v9MYnVdSvvlVCKAX38ysnNFig/UUj7i +1sE1dVxk/xdAjF0Qc9DJhERejWFDxPAf0g17d+M4OtNkyrMG0wrthT81hUU9AkBB +n3pCvv11W1SRa3A7QaAOeJ3iazN2w5B1bde/DM/w4JHOv8lZHaHRemMQJmHrDDla +u1gN1bwp5nonFPfu6bYs2xJoGubjXBRt/VkTcQ3EJ9YGr04DX9G1hZZ0g/fNHogB +a7FphiT5UJuX++1CPDbdpeqhaHIFGLjAqQ9KjX4sAjbOCsFp8Rnu+zyM1mE1O8Rl +wHCaeVUmDQzBakyd776PeTFUoSx+HcpmMjlW05i7LUQgdH7x/a/Nwn2NwK64HvDn +wNostB+021mkaAkLsAWhVkXTTLtAn8NGIIJ5Nw0tW9jM+mXJhXRLROadmULq4ojd +rrbEDz4Ss93XSHFSxQpsceRJC5I2CUAi/3qM6vuNWlBFezDC3Z7GXHukFtg5HyvH +H23DzGli0LxCuBU1FZ2no6JvyrORCaZsLRir9TkbYo0Ish/kUP5y0Q23TLzqlN9H +XknOnb1tLEU7j472qxSUwzpfWxcYeXVC4iRu8sohXqNptrAjm0Lm2CYsNShMLfw9 +ggGgf3VYk7xjLYm9pWOItwAqblNWCnHhLkpLrzKE9WUV9jOFpRqCJgiLI3dc8aiB +GK0xpp+L3MOa9Lmumol31evyPvHIySsSDp7vx56Y68t0Kxuw0OAj4WTSPzyw10qv +Yz7M04d3/sOyWeFv8+n3AECQbwUPikgZi5POjMy3PaH8BMA9PtdMJ2fLgVslUJdJ +xNCvetWLhhNuElX1sfptp5qT39Jq2l6CAkE1onMqcqzll6u4TrK8fRwN4x9o4szL +c2zvbe0GPHmyMp1T51KYJHCTQ6dCWJnkiZdSdhOCpVL/4sQ7EmB1jHdIn+UDnq9R +kbe9f00Kfop6VP/+NPKUHfWG7ifviWVSv7/ATw/Pn4CCqEtgmNlqiaCn/aZjy7xX +bbCqhUXSih5VOfHNot12G+fxf02lMzD7KhijTYWgAdTKVK8VUkq8FxAIALl7n0Xa +wfks0TpdKj9OxWSIWVgQgOuiULsAWurTfQiI754GeaINCpicQwx7FH/GDe57jbZ+ +gIu4YxrFy0TO8EPdcL1ELHNq+cgCxK0H48J02xnNGYssZKZEpOmawyqJ9mW2DGDl +ZDKkLJKgc/tVUPxAe9oTRi6XjiZnOIE6LdbMl/DHXFUmXkQ6WPU3wCzq03nkAjvE +/jDPpITI2pPoXWU7E2emgJelhquoI3tmkW9A2Y7ywdSTGOMvLJTanb+6v2sM4oLA +6rat6rd2hGvEoyGFePR426mi5QzdFxjNYAdGC6QWkqDi6Iv9Wq3SnzDiEkYm8h6c +RHi9VfoF+9YdvjKPT3y0xZF4uhwDhqqP3Q+qUW4NbYWPQxXWCbGF+YdGGIzASHBZ +yycg1/qjoYTBQ/QRtMgXc9cANlNS9CJQmZySC2NR2mdWgZnFwg4/CZC5g0AUrxmS +wHNNaTBDYt0CXue5WjmITGinxz5RVG0R4CMu4kFb25aZNrgdqH0I4QeUvNt3mmKy +tfk1XGpmcsyHByvxaC03VwpPrHWAJJXEGDY5vuj/PDIlHTgN8/xwshMPEgL81yZF +PKt2cdHVYDbDleBHVoUgiIyeaz8/DT2ByKfNI6w3tT1sQBJmUvbC9F4a6wpqFIAG +cPKxb4xjVz9VNYviWfOgTwdqKP17v3c2QEvNkwo2dw5GwRBtqZImFxkt9lCm9Xf9 +8SCaThszX+1R9IuHzIopXGMC/p4lNUBptrvt8VC1vS9r/7yhJR4tnVlGKVr97Zt5 +KNKJiEky1nG6PSaJjFTwScEgdcNOIHx+IP0xd3YMmjqLpsS1Zpe4YTUhfkbeMrgv +aNLgi7x0sORuHLgr1wMb33gomTn/THZlLQA9sf8Y0ip/7Z5oh7NN3v+dnxUCHlFp +DbXb9EnRXZgV081IhBA3R61lj8GHPX7boZ6x/yhl17WJoqf9AVQTICXAOFz66bcr +5MAQSxyr089eSH5UP8hCsNAM6jYoD2Y/oOXvsTu8gM94MCMQP+llkoTUazGaXs6A +DGD4jlQjJtD3p9QHG8Dl1MpJ9a3uFeq6agoiS5NBO3kN2BZNNaoPDdJFl5wd95PQ +7UfI1jbINaGscoquncPRsXWycnmH4TW0TOuJnbmpqnxZnW05BcJ8UZxi5vBXfiev +UATeY5pg3UFk6b8Rp7/2CRNt9frCAUCoTbqdkJySwVi/3zRMg5dpoaVFk7Bv6VcQ +R3qe0zdjtPWHqbmV2yTNWJQkQPTqt28p/A+uH82DGXC4hGjIfG22X0g3K3R5LsYz +TtigxPL20SN7J3PjmoKw294rZ94Ny9HjdNfvuh1me8BhwTXjqGBCeFxSuxuum/Ud +BDM1MK/HRwrC3Xd8Z/nzB9r6j54yXFDZV5Ie2YVG0vYKR+mN0MlSsJZOL6ljoJeJ +lOC3Enf/OvoOF1Em0bTjnlNe2qc1b8X9rzVZsxDeJscAC0wTG/rlXdplsiMp0Nxb +g/EdRqUlc0n4rHk2Z2WMTV4T6aO9N1BkNFQCWXN6m2OvbWyjaD6EpmIlrc4tyZVn +B0P8/6RzES84q8n5uZlUw49/Y7FNCtlAmnY5If6e6UFzjBVP2bM2APIAGrVibsc2 +6jG1g5MuAeTQ3qHFaIwJONcBNP4E9QDgv5bAjMEhekiiY3w9V14fzR0ouijIyfEJ +OxeR+wuoGwrLwXS73Xl7EXK4hrl+U+KXOcSmIeUgftl07qJpFSt6q/q5zxrX0bdT +ANxeAz87OCPPckG7RM+5ub8bw1yx6RDcC+1dMiczA/8zR524t1J/LuEB1viI/61E +DSvDDNKa8A1ATvXy5eA+lUA2Wk9bPcXyr5d9EQOwASAA64hZHxVIETnGM+fTv26P +3vLDNlIkO6q3bfbZeFep47kCzaxENR0HX3ZsiMae5ljhn3QIWMaWA31/m8NwjWb4 +I2ZC1o62Udaim0R3I85qO8sE0xTVbU5oeOPSciBpAONck1oReM3C+OY8qeiKzvD8 +1It8wSBM8vNTsIc1ajjGXFpSVu88THQQOkYE0HRAwi/BcuNc8pRmNxyjHDFAjPKc +vH8r8q7f3eJTQVEUedl8HIUVG/QKBm6iOhpDSxEY84OzyRTWWitWUT31bptaaSCk +6J7ALvfOzSoUJW0mepZ2KDZCF/BPn0Or03dZAFULOixAl06/41Y3tU1GYrhImTGL +EFf5fP+3Tf5uBIhs/tRPMB1Qrcoz32EtLDjjX8C0npnqrSgxjLjil+JvJvPAPVSc +1hpokWb708/RiY6t7d24uTc+M723Nw0+Axive5miVhfhyRwMfdY/VqBfaBXxiwdB +/x8r7Q/oj1P9ds+0I6Q8S6PfSad5swHaO89abBaE5ky/E8AzDoxCp01a36Z8VDpC +wW4X6UK2ptzFPeOVHxZJH3gJfnCoY3MOwvdJCh2dMYDHMh5j6Pc5V2M2ZjLOIO9u +n2+VrBwovNGnY/9kIprFHBaWKrRT72hZ35LugXh+TPo2UGrqPYuS3GwfHHMAPSMw +eVwnhXWmf2Cfr39QW8KhCUTIPE+9ilrvr89zLhkFuKWwfmJVZ9zL294sQl6oyagp +I8o68M64LEfacRV80OrozG9Khvrnv+1ykV+kCO4x1dDT3grROiGM7lO4qlW1UVE5 +RA66X/lWIL/dXeuDQrXqxGwKlGgRYQT1JgR6e4TGTxSkneRvD/KZfb+E6NUa3Abq +30FcqOF61bJ9WKpHth6Plu3v5zZs0gPnsCeKliQiE4UixbD+p2k0oHoLTo8hVzNC +j1ik9zHr/+VBpIcK7c+AVCTN92ZDbZowxmbTWym95Kr41ncBgUw6afz+nKUnqW7w +fwu6pVBrYD8DU/Z/N4VvFmQlMlTWtptQkQBdsTPQL5r3nike7wt3Fysd9XIGE3c+ +AHFjSDkY4D8iTAd2zFnoc7JY+3ron2HGE2x4Pdfg9kbDxW02EaIG50lFOq3xb51e +oTrqq2ZOaHt6NbN613lyvd8MSvg9tRNxH2Wh5oOoLFPY0CDFU1hIE8o/+DDhnoYV +Skz7nn//lQaYl4Y/yiuC9/P+nTYrKwIiHILLnHA6e4EqUZDHT7vP8Uwm8d0WBdnu +RFr9wECEBt6ltDKSZkBeBPV95PEEkIcdKh5wl4rNKpH+dG5Z3A2d6f2L+n506bgZ +t6znQ//4g2057hVNmB3i70Y1rejtNgvdkffcQ2YDHVOPvaDUKWQ7D6oAxRGHeQjE +N1TfYyCpTOm2+4ueUWfuaEtg0dRuh+mwzhoEHeJS1Geos3Zk1oMyoyO0vSwaqCZf +/98iPFKeTnCGtWNILeBdk6XhQ86DXh2wjd6fMIaEsZ61L114u0cH+gzZrsRspr3Y +OYHVVzibDi55oRXnkXmiRTmZ+sE3bSKqZeo8qxqLTtKpADdeelWSlUzKYi65t21v +WB01ru0sPXWD6JSQOA6U9wGwwLOnBqas8XoyaZwdhwpPTP+AGIHKmXazKX62zW5X +0ZS4H4ugJX8FqdLAX8EHYMLnokz0XhPUOBob+hhesxp371KfwsuymSTrY/HSzfZi +Y7v9IxkqyViFHe/VeX7F+95JYmk1oOAtkOChGUn9XYrwO8j+NCQzgnGFlYQDMoBb +86HXKdvjuLTXhHzGfnkTIJtqjKR5fcjY7mVgtqvPSTs6EUFKZwcNHXs2AxpVYQ8u +M8KVtEM+doZQo1MUnC9ouS5EIA3/jPGzORXHPmFmjTx3XZDHnt6nRp6iZ1qOhTHX +6xRU1vqLfLsDGLgjTShVEkh+8+FJk9nSFnSAPcN4/Ah4uJhDsyR7JteWzG+e2m2D +yb1vRHza5HGwkaVfBCMUslYD9CObX5EEeS61MXBZCV9/FpvvwR8zmgSWj9UorUNL +PLHoNkdj6lnspvF00nRRSRyO5jrLoFwJup9bLBnQI/1lsJcsRI4ZwaMot/MaLq1U +OLygvk/LKSTW73qzJBuY9x4DGvpQ+SXA96Dl2nPacAyBwJSSqfEHqms2EOg+a+W1 +8F9SLOeSiM83TVDSt5bD2XNlyra4r3XuglnnBo6X2y6Z01h4G7R1PluG6hzqjr/v +b1p7tKJdINTnM3ZTjgqaRKHPtq1IE6sI4NB+aqStaNS46wlL8QnOl/L1/BDH5HY1 +/E6tyDYwzo88tRp53AnRCx/ZoeIQnfl9WArhYKMO0tgPP+1uGAbS/HeBJmIO2BHb +M1FxxRWpUbX+hDgfl0UoGJ51OcTaKoQCna7ndp21dL/rDsEN2Hjmx2Wle3fjTn4g +x8EyHGrkvf3iDKtxPu1pZ9eTCoh0yM2xQjUVVOugZ/x7JFjxbdz1f51XkrTC6QQB +w/hIExnRBMwKQClnyKv+TiGTAKPlyMs6XCrWexKoCmVJjWjZZo6u+duUIGpFLnBM +uAM91u+X5w1BMGyhYz5pTx7w6i1ojJdWLFzCfLKxIjGjZDS+AL4wbiRB0wODQzSS +h8tDRw1L3aFAM+1g2i2DiPUWhNhSMrG2L3v9AtKv3WcuUPxa1J1++wiZI74iWwoL +3QMGJ1t9n9auUZD6JqYBeyDk+oc7fpv+tjI/hBxLNlw7Yn+LpQHjCnqNK14BNMLW +s166aiI2OF6tbsdH+B3qdMkRxcKZE0V6n93YdpLk3m4hJ93MhoHGViP38LkgaJgx +fEpPDo/8Bsj6bN3PEiMFO+agZ8YTyO53qPZI4hGmyczLzEO7D6QcgeZjamLBi7OA +WSkyTdf9vGGBPGOu5JSpLyFz9NEKNPAhX5Qj/Zlqd/r85w947x4lytfI5ToSYLux +vAijCM4Ub1lKsKoGSvHl5jbVKR32umoica7OVk5K7TIEQHlQgRKtFNIa6NFGTiT+ +BC/Y6ts5pLZ+aV8dOi0GBY+ODeb44niFMeIgIE6r2fhYMk0hGq+UM7N50bRNhxRm +DXRyJa9GQgMOASxvfz1U7oeZdufTZJxjo8lPyqUzdP+YsTwQNQHDKeJCubS8poJG +2qlYGGEN6Hs+FcTnP+gvp03S5yTh9IwBK4JnyBFf5sizOikMnRB9Pyhy3j+oyWV7 +kFmH+zNIuK6+3CC/bBlhdYn450enC+QWLCiKITPNQ6Fq4mfzo4uvQBFhet850nfC +KFC/v7J85TY11Rd3A9d2pnIA6KsZH1cP8FKYQPTG+7aVVk3PvI9qUStl310SLo5i +AgftC9ZYnhhGKfGz8W63rHNrWCs7doFBWmSPlCFj7MLvuY3qeEh6OM2xA3r7cv5R +2ebP3Qt+jzqNwoIUzbs3kI33ReZvSE5buPGbN2d+hVEtTA41IqrrgQEtJmLmvz91 +kQdh7M0UcAFZIpVQ2B3c4UqiDCw67TcIF9fTZGB92LTb8qm+RjBio4Or3T97wW+A +0FN/pBZ7QjO0UKnn5msoeNo2isBzMHNNvxV7vkrTYe4venQpCDclxfOIek5Ym7eO +65ZcT2H9urc8Pdh9JH/1RF3hud5no5oSNNjXGYcKNJGM3uSs/cGBaI65/ZcwRuSB +oSgiEwOCgijF4Lje7LFaEtPYOT7aWY1jMFmH3bEyHCpsqyAfjDw0BwHtE8HmI49S +KlPlMnlv1bPf+3YXTG3NXhoMVzuiox/D5nOB1gBx2ZwsuD3bxMQKbVm/p2cxEvph +GpVB4QZDYHRyKp1o4Lft25YfMPAT10vocBYdsIFN7g0BRgd2NyWtAaPFqOwyHLtn +6ZjNNc5exBOQV66yLcA1rcKoW58UfyQx9QPh/OHFcQSLeVvIoJbsb070Am2PueSq +2T0GkGrd2LMOt2yeM6CauKhyRC0K5SMF03V2rzmmSRDmrKFaLgpQf+xR1YPR/q/d +BEMmxUKutWLiDosg2HQPDiZ9t6akddcpsohi7JTul1K6iz3uGuvd9HxFSzJLGhGh +w4xlZd1mpSWa85TmeNFB38IBxLRkZlNGpbeqSI2RJ+wNMqHrwaRoKFyCAaYtqAcS +X3I5VweYaZEFtMrAlrvcTn5STyBjmVrIBIya91P7hLfQXVilfw9aykwV+YVjA1+8 +UAHiWR8tWAVUUGvdc/oVtJCj8OjQjcAsHOFao8SMM6kuFS+SvDpR09Afrfo5yAjb +5tUVPQCQPbFxvP4FfVUjh+gPnWhLCu0pZKAtyKc0Nd2fn3t41hz2bfkg4m9nwGDB +HIL09xmXsf7jE6pQXYqoSEqhFAlboGC8vHEDTpc6Ph8IQdAp6tV3zw5cCizv8jn6 +NWFeYgzePupsuE0JWaiM8SCE8pm3ZNNajXdqQOq43ZtbfrhCnVmA5KjouZ49HouQ +ScYxQVhFmDSnVbPmkyBGFsfwMiy+g9Fu4GhkAGUOkwA+Dg6+RZvx8I8kKDOt2hjP +9GTSmCAXtFbX77DL07A1gaYq0dGxvdV9FAytRtQg4eTpbUQ8cKCx9AHzQlGdabZd +uznmlkTK4l+VMcx14udusSanqWG792t9OS7nonoHRTeUG1Y6Cx8JII+Mn+WF1ECD +OdvG+Tsl3m5+QN9lTIGMH1o7LcqUwjjVMqPvsRauRcOLk+E3OezSgk5UpMw5aoy0 +od4opXiC0QPM2qQt4f0c/z11EvFEIB/sTUnnSNK8faxFVliPHdxJwO1jtGOoaai0 +qwPQPlnaCguafh9iWxT4tIdwaJz3pbB3kEkp8bYYrWBegveVG2aFFOGBMiiIkbph +0/0w1aerClm2wmnHSeG37GM7e9ILiGXQEtW2wWYvkBqni5kxTp0mfZzB9VrZOxCu +Bi6I22VJYs6WkPIkymU05UTPAQ9MMtbXfJfN3Zv+pWwXS0ryXLr2bGhpofw+OF+B +vlNKRJmXJgR9eZaEgpdfwSVPKUdwj4Q8QmpEMIfUCb281VvbQFROkBu7k/grdPLo +Ig7ZtU6fnUFCjkEWTUSXpC2muAIJp0KpebTUBjuZTDQnSKPyRQ1zmXdGurymdUqp +yVtVdaNx6Q4OSVXYo1OktGxMeMh8SnG2NCeaWnXYjqVaF6RvKMNTVySIck3IMAxT +e1IPBj7uwJvUaxN6jx2XOPDySKBug4dHoLa+QFVV15VYCs67Uos4oA04VtJ5dWSR +m+ZOEx3Y7RaxdIfsgSBgkWLxvcLwIJqZNLUOV+pnyyQIV71rY1p0xlTCMARkyCRz +nfMfT4n3JNSj6L/+BkOJ3MfYPfcZ8m4w1YS+T6g8RSEeHFAmnfvkUCDfCOSc5wKq +F3MQd7dckvYmhE7PRRngIozPDe0xhM062ZJXnRgkvPAM/W6iP8kc0JR7EitsKuw7 +xqxGh380C93ywOLO6rtzmbXbbkBnHbhs1uggniZa+9iXYODX0W5OG6CIcoJcLQeU +m8dPV7FnvUivvugsDAxtc4cwDeF9DO0thzA1k2wJxZOQK53tb31hZaICGE/Y1mYY +ATdVDnYIgXHIqqydKd4RkKNtg+jlG3quY7LPJIPY1yPXW7lYarFbx0B/cjQDSeoy +S20eQzUt324MKtAKsPAWIMUfevOlRQI58K6zMJJSxbeskRKtsLfWNpa5DJ5hvhgH +uv3ONPZx3XlHVOZ+pzj1rlgh2PCFvfrZuySl7YSzENeeCv5oUVtRMrsrGkoIP2Ju +G6n1dUpzhPiwW/FsKS+XoZ3xqSoElIzQF0cIUlMYv87tLl4yluL/Ude13SiaRKmA +o5zORVpBm0CLPl5zbr2xMIk/ZIvpgQMNNzvUJiANuh20LqJfZ2BSllLy1XaZe9AH +Tz85VTlnOCC28gl1hGeBPSTN2VBMGNzVo6XP06IO+vcmzwYJP7Oqo9HvRru/cD5T +uWSux8M5QurqCp3SWASKklNWuyiZfCN+5YF+koXZtpZGybNMAsyOEa1BXBeI0k+p +NoT8C1at2WiqdzBrRKYumvdhZ4vbplhkZizlCknGeY3azN7Xkm+wssRQCIwBeE1r +xfUnsafuwWKStSLwFpQHFkRFLyEq0Me9dWodHrjo51HFOcFHNG8UecAHtctaHEGV +aNvSklDGudVbcKstbrcgyu1k5ZGHCgjVnllhcFwuD0MPwJELpyk21Wtp1ulFpUsu +4zWNJ4B+1y0BUpsinEIIvF9hcKMcRBsIShue0Ti2TbbSNAOfpEGRAPqFLN4iK1Vl +IB8dabb/Pc6OFm2tjj8n2btWBXqXaJF7keZ1JcjhsKWwt1Oh5UgHN8elDsuLqFKV +qvuRRYDEQsV3i2LjQ0XbNZbkHOk0+IfQBVaF/prtubCt/O8v+8chXqPzdWCMtNKg +WJLxejVFGN4fxlzarRB51ntz8dtsuzE/lWQejKbjs1K6EbYSIIxRVKGXTtMosDCZ +51nCWaQOrzM19KtP0Du1dWVM7gHqFNvmSJHbzeQc4i6mL7Xorsrf2k4WHr5P9QVG +ze9XiLr78PF5abywGD4W0uSu4u11vE8Hyf6aSvKa7S57dXxevsmgYZ6ACIqgbub9 +HMkY7EW2AsxQmDgPvkQs11gwBH1dAmZXPrUN8u6k4Ct78jhDhiVhJRR8Sm1diyJa +HA9O7Tgk7nqY1KflhwOoABiNMOJktoDIwCZSez9RwubN+CYygzKefYwy+aRhBd1U +wK6eF82zAoaltXztsVWdRwEf39Ra4Y7YdCCVb7m93pAOXDahFenWYUTLO2SlHpsw +YFx0zKBhC8Z/7lQiVd95n7erpe+uOO1KjF9jfOjzNONi56HispJhGXQrs54LU3rz +Q6HLSJYdisQ1By/xWVeU8HzkSXZ7fw+T+zPsWqHBOZ97FodnUZyz721ZG4t3t/LN +CvrL5dQ1/rMkQYS1LvVs74PEsnlRzfUU9ErQBDVszUdjc26QHW4G+UUw6lL7N8OJ +q5VV3bJLrmkT0SiutvPXR2sSTK16mgo+lgfkEFrDEXF2SNSqUyoAwQt+GWofFJ4n +Symo9moUkjeCGyaLz9duf6OXf5BDpPXn85hSLi5OJlvO/4Jql9M1pXIxjQX0z0JC +fiK9Jwe1ebaL5oNwwIFJPNOws0ljysyW2oWL8p/AwNhT6wbmppt13dOpAdw0JhoJ +nSbou31SlYV1RaBCBUpcZZYukNI2qP8a+xuXFDmUCKXcO5aRl/ZaQDY0q5VNQ1G5 +xp1xxheZFvp3W0BaniPRm5no5blJxvv8y18VJ+FZHinGIntskk9gka5xYcLPDqYe +zqVOuw+XsP73zFEG3dVpAsYBdO6IuWmxTW5Z+4MtAGAvzWo+bi0ypYxFVGe0W7YM +MOIdVjB/yvkv2U+9obXg1nw5RRfnz5CGRhBQk/m68Dqaeig+/vYrilJHCAofB+ob +Z7wfewqi7vSajXQR2DKf/iJ+h00kum2KDW4vHgatp65r5qmYzPop74OowrQ38REN +MnD/BTNUax//yDj47KhUl7SfQ6xu3ov+KZmYCyC8t42Fz5HbmN6/bDW6RdC2DIwV +f2oEp66JD5iVZBxPe/oTs3qveWkdCHwHJV9HPMNiUekmDUCb/8AwvwR3McLjXXeN +PHxwD1ZebnPWzz6mTF+DwnbaANZksp2ncmRtRIzvOmcjKrEdq7yiGqgycmbzgYSv +D/k5J+q8bba7HiOddlz+i99Yk2MeGXvoWrqzBOVJQ+rLhEHXDVNyDpyRt9TOQZRe +WxISkJW0QNLo/fxDjhITcy2UM5Tisshjq1bRLlqiKEjhc2pZEWXXaSaTJnwoRB2i +7KyNHf12ZXcEpXtbykQqCAqUZn5qLWVfI4TdKjUgR9qEiHhzxIlOzvjnRrYpTqzM +kbzhO1deT4S0UhKMWvVzJrh+qJAu8Oh39x1d/RGooYQW1P0EOh/ixxCaAznTK0Xr +Pd62Z7NKr1VKidtNhzGoVgaNQcupmP9e2yUqd6YNf1eom1nV3gTfUm127GQ1YJIy +W7jhaClVuTX7MCS9Fz7jvSZFn0ENsvG7Q74saqy+jZpf3LShD+7w/alkhhNmqviE +tE66XaYG143Ocrq2Phzq7YrP9EAjEMToB6P9VhNw5WhYSrzuBNtt/qkBrCW8u2LX +qT1N57c7p1IsZDwWclBKGS3dF1lUjADzTKjC5BQzUYC/gsSgmIMMv61afpIlpXD+ +GS0B9De1ZmY9Wq83PVYgcgey04LrG0J6dw2ueTgSo3rlICTuqt3yoL63XwSQBZDk +6MeJkxE0+Mg014IiukTlrwhR6qaqqwDzFnfXfUyVSRoBUYfQ33YSQXHd4l92NX00 +8LX4A9ban3Vyn8Lg/h864TzOYz4mvg2fWeyQc7I/PHPosfGEInbRoqN1BQGl9Fvc +K3F68VvwQ4g9eQ5+/7N+0XCgKLzMilsBmVjusNOCMgryeZz8I+hjjXCTrhblBEl5 +WekDEPOKJhqsBz3LcQxW6mqG89ZnHMq5Z7opkRVH4dUFTFvTOfUWnVPt4o3ji+9D +8Vhs9GtTS5weoEt9usnG6qdXVGJsvYiswtk4RoPNTyBujMWD2eiR1eNcuG0TfF4t +fqE+fU8AfL2niMOU+D1fcVxrCuLiNycPXDl/TsDpU9CG2sRYAPf0vMJgdToU47oA +h5Br7PhkQO5qWgVhsUzDq2BVAGptGKObCQHZQGNeptcCXxCOBirtC/60pdBVj3qH +QYYshl2QryoChENH+Ajc2Ke8orR4i07y1d7SZ5YQZYEvp/BqX0bjlG5lSFhFDdYY +uqtKqUkZanLd0JVmREcP8NtsPWhqO5mHcdUgsf1AZqSkFSeji05c+x9G4a38hnej +HqSvBS1TIg1C6ZIhI5YPmu0XyK+XheyhCdJ/K7NuSUQRA0UXZ31wQxgmbCk2HOsp +Fd+wybhgiIDNzmgDiE94ZleK2fcJ/vMjLZCysKJAuAnBc+OTFCp5YbYEt5vamK2O +yL/z4S7PznAkWSUNLXYm9okbS4C5CKJCpj2vEXlbmqa2Af1fMwlYOuDXYVC3/DPP +WBfaKQdSHqgYudoQ8HzmMg8GXpBCEPl7Z/+TYNqnEzCB89T433n6PSetlqMgeeFi +PaUC78bGrsKw/drbEvODOPGbt9BbQxiVS1ip6R5okOyKO3uAOfMtQdr4CpuanGmx +KobvS/375fYSzUirGEm5Oq9AqQ2k6kEiO6YIyvcTfH2vKemfii/G4+t0z9SxlY8C +1OrpWksf+rLVAAwxjVflIb1xsPJW0AzIK9hAn2v3qMzJc0hs2hRPWQ58g4GEKTDi +BCQqZuTXDw4wB8eThnSKiu4hzNfnPs03RDSOJo7Y1F6GjnFzlxbG4qEQre8vf6s4 +eilvYv5QqLy0oI1TvjoegneHwaWxzixxHQzbTliVa4bLdw7hrrWsspsytboOjqbz +m4kGx3Y6BQ3K6lyL+cuC+MpN3rPQ7umLnUitR2kgHkqwaHQjkq2Wms6s63+WHEMo +MuxAQ9Kq7B0ApAQhNnI+mjJx4oIp46F7n7i1RxEnJW9Mn4IwDZWxgfiArVh6q7Wg +TAnzDIklj2UE7/TkSJq6/fWbcgdJ2X/FXyhaSCMJwUzOrc1hYhiFbiw7vNLMks17 +SZAmeuTz/FCMztSiAsYtzzbWBaLe48Kg4BeWpJ+1Vavuz3+GntcHMqA7I/kNaGOH +ELjQGkh0Ij0I3IeF9MoOz13SjL5l0zAQEdc7E+ljVldejqBoKdbwakUBqcz1y6gj ++DrwhmAN33ZEA3OoF0Cl6VyH+fusewz62ZMSfFBWxmhQ69GbipQbWEvDeL/k24iR +qha1pVYxtjRYAyK981+CRRziA+wNeXYEt/8lEL9Iquf4TGgw8w813qYGE2uFAGcF +jt8oJ2m1Vd3nWVKm17vRKEaqeigCJeOerJ7Mbl61k/KSWwXE/hr80qm+qa32f/UD +2tRTLyXJKeEOp5U67dLH+VW33ZqAc21aB9rOOSJo9ryddkpP4rt62YCTK1/EtWhd +r4tMeJIf+RIuGqZAmT7wFYS8k0t7oAGYeg3TyIkJKDEFqUgdke9atbGcxJRJUxfe +8ZlEQRrUfQZ6uqfKTCTxQ4CZfjAV1C3YNQgEVxQPgJSj0v97I44McT12rMkUoWWJ +FM9wSL5sXRsemkWoR7g3is9hrnRcvVupwY2HRou2jLEFtORMHvTePdbjM0m1ejYS +IbP6T1Y9E/NtkJSvcA7FBnl7Gv/aT/Y0KWMo3IfLlTr8qdPsJaHVRBeeH9BkxuTx +YSWzkrhRZm0JwAfsFEnFjiGZHB3L8XAWlUR0XGJjClvMbTJThBvABg07srXqbKL3 +YOLy3YH3EdAfLxGrFQLGSwkCUi4CVXUMGq/Z8Ck5Ji6Gc1W20i1qOeJzR/RW9xVO +9MKSCkMccXreb7xOjNOy7BjtvcLi8D+RVJBQxVmwzH2+ko9GrpoxyuGHWktd+hMU +NQlCaelZLbb8DalF7/Lc1YpHZaxTt4Rqw+6ITrzbLgzW/80VsEENjPXKtfjbcqO5 +be2VAdM6/+YZ17iKc5iSJg91nfSF92dLrWxx9o6xc2C11zX8TJgQ4kYqrOEYk0RK +twuDYXMiELLReUUI3YxQoc1nKLAFdzqoZMzGKOCGIbcneeh0FntCvsB2CGdY3N9H +384VMVWfUfEvVpTWrKaMwGKEYtRXRoA6hg83l+WJ02D0h0OT9biBIYXYoSvbm+NV +xy56zFDN9DXNi7S638vtHoBElrM/jQjGTLljl88cVgbjhojvB4v0cxzQM1mg/xYb ++0hTMxwNgcjpSTFzVrW9yK0lv/NhUzgQVzDriJktrtNtYTzz12TsPnndSy37NIHP +MsQMmgTkxtvULED+p2jWhNTWECzwGgDkqwjEwrcDjuk5bllHonfyPI9eCV31eSJ1 +gOdzk6st1q3vZxoxFfWuaJkjB6ojFmBCDMM4wioKi3fH3K6H3aZbJ5/K5tNEEEHb +smNhIyKsIQ8h+4uLvxXuwgaKg83wUHf6krHXj7/a2mJAmhRoy5KKi0MhHduL01xl +5Yei10UJ/3Q7l9v/RWG+U3eQCrWr9HdQS2dgCl7ZYzCMaxJjeAv2AsT5/sa0+E0V +8CNRmPrq8NBXOv+g9rRYDodXesiWiQLVW3eZhpLLMbSv8gpYSwFXrjnHpHsIOyuE +wnyek9XXLhSnHngdzzF3oOFM+bHoCmAI4Q/TMZQaN2lPSELpIKOVZE1Hksnp5Hi0 +BMiLAohmZiIM9RctXEwoj1OtTHZDyDhJmrM6HlTAnTR00L/XEGJTyqOQ5v6NiEUn +YHq2T6jADZUfPpfUAPCB5ixVJQRb+meHyLaabR7wcDzUTfJ+RHGq9X2cByno1zos +NoFPil9XXcvggVQXYXgh4eS8wcxRFq1UDkeX6G5KK8AZvx5L7HCtiauvflYOSu+D +vzBVqLBuq6vCfT9wCY6afXBV8oOKOBNiUq5oKK2mi7/7ANr0Ct0kxRKGK6edaJJp +0WvaJLAAdFyNODpOuPVncA+NvNFgBbwWtNfbjgu7lY09Z3ZhcaDsTISZnyYB8Rro +vVURr9HToyeKNWiuSytAb4Yu5WQb4YzEg/v9rrdVvZIsybSo8/uoqVxPzs9RuQ+w +KYKCsHD5dOJhY1PzlFKc3ba2iTNP6xNw2DSYkkJAJdzguEfvaEFohv2wrmdbbJFl +g34NUNwW/OvOG3noJzjOa72z2nlO6ZagGRhsPq/katgCkITnv2mo0sLi9AWKRJMp +LJPl0tTLw1xM8+fui5VRusrt0fY/dC+rcD8MG3OYi3xq7D6lLsai+dkSsea7qjbY +qBq7lr0ml0zKPMgGGaGUPuICK/itBom2nYo8KTBTJoIXQo7dwwLMabNtsLYSYJ+L +vg3vF31MyuDTg2NYLQyftsK83qQgzNRWj0WHk4y/0Y24kZtWVXyo5FgFFUwYbZXB +x0iG1wU/+qbQlpaHLTC2NS+XybbnmPWBGeeVqmw0Z5jYF1k4jE+O90nqv5cf2Dff +0WoB+swTfqkIVUgSJtvkasT04Nu/YIrjXLFz0Li7JGL3GyWgo6RgDcy4u7QAiI6h +P6LHjHVuA0kGiQNnOpff7B3fzuHIod22+5NHFWZSH5crUonBquGiPPy+wPe+Xc5p +viJnDctx5REWgvBdSIz1xDi57jQor8Vfab91g5YvClaSIui4kPWvRhniGTkTaadV +PS0jskZWYoaEr3/2qVg57uB+4LyN7BXCgzVHHwOpjg4OLx0FfZTLa6Hey99kl268 +7KF9CvQWffUofqlCfJNVCKpYyl96nPLki5ew0WuPj3lDhPVMsMFHMkddFVTrDnXo +iSFv50Bd7joYFI3qiUajXiIhqd33ol1oBuXao9D/Hswb5LwYwd9qXht02NNIRaXk +DxmOa8I3lj3i9xdEwOj6TMHw8E55D6OekK4pn+GrjMKiy/90Cz5dBxpJbFmHDavw +uC51ljs7KZ3+8LVtmE3wOhmY4os2zudjzsBvXy4aiZqMm3sIVk0kwCKTFMrFxQXg +sB3Syl9Lpn75pojnGbYIqVDwKd4QN3Eyt5wpbKm0XX1WfNh9vA2x9TUdfY+hpGpb +RQQzF7ej0NCs4OeXeGh7KIDT88JwFHBmzs2Wu0d5iMXMN8CP3U8CPRRVkKU7t8Hr +FkiSlIJzX9mFFCryJDRJnJHnajaV9U9K78ye6x+wEww2P+5ozbSrETrmT4hz4Snw +lsdpk1+izRu0j8TpuIAho402mM1yA18FGXI6nZ449IcadKo+tCLk6xE+jZ+mJbdN +bye/PLb9IcPIJghX6LQc/zM+qhuJBnCmanKrc7WYPF4sg1Tzl+dly6h3GJ7hktcB +1jmrku5R5xt6oOoDGVJqjO0mXEnMJ6MV+bIgcO6jBFEPzbcOqOI+STO1xVuC8hja +NOlqc/dloLSEOIQY/SvUwTQ9q98jahKcSPdLUjG70YZauiu2dZV+WzX48tiuTrhy +vOneJurgpFJqYu62lIE01NJ0fVZsYNkpUyXpv+GDFD+4C3VUGSqIZ3nPO48EKrSm +t9azCaJOdbgqmGOM6cTRdaoe6SgACFOymVXygatdLLXBpFs7zHMKpsp8lrZdVz3s +mfj6tjwOq2sAi+8WMG6lGWP4SK5lBKdUfZSsTm0tSulvH1dJbIeXs33yIqW9aUFo +y85An/0eAYtRSxS+RkiYkum23b2v0yntmXfGANuDy9bTv4PAdxauDyqe6TcVTmgB +rwGai9M58WBnXu7Tm9LjrFbKR3bej9zr224eZJPN+wIXPWGIUBPvJkSngHyezSAB +NUZoUh9zoCa7HZGmmPLYlWsUzUDl6vJ1026zxGdOzJb631kO9vFsVOoqKoyEBq6K +trI4SMl287XIHC4btCClPXa0DW60P3nwghkL7LqiUWfCsaw7I1P2wr9Sb7AzeT2y +LtvuTbNTuIXGV5NjVOMWHvSNvEMNriPq6/OM1NWG/swQwq768bbWzyOIXxvEnByE +2Es/Zl8IwyO2IBD3tBqiiSvEmgv1oO3PHXTL+1MyHmZU4579H+BzX0dwVeDCkpT9 +vA5JCfc9m8GjIAsvrKiDXmz9ZhAHQqgKUunJjjmN1qWXzUvFgJ3GyKQvJoJ8DBr7 +zezNjtB5ouZVM9DiV654koNHrp8X+WU8KEGczXaTNkIOPCX0RrJxWkbXMf59u9mi +A465U1tiD/7kKCd2oyvh+y6oSLmkeT8wO1Ywzs3UKUX4iZn787pJiUvkUnA42AsW +LRE0ds4/8rsJcoILuxaT7ixA+bsTkgos/mNA08eSWhwNzolJpQZMT2ys2EIwJuY8 +V0du0tdK+h1fRNNxsiFA3C1X9PEE50bykyPTUZf67M7mxc1Lcbk2f3U2AJps1ugA +hRzowOZHy6q5C+V+SjYn0Yx6gtQs7+y/JQOPLb2b9UsG4csg+kXMfc+7OxA3YIFN +Tt70x2mSRAMdxHrn6vuASpKv1MpG2BzFClYAo9cxm0CpPW4Kk/lJgjTWCYV8RFJP +PgYLj8pB6qpqHZmuHOh8C7QukWw4OO3usg2jRGeKDruxrynghqlH9KhuYskdX1tk +0orPr/rvesir5dCM01B/4LC0ZEtBKB/cfnK8w3fIipy5B+/xlW/W8msAAYuTQzZu +ciCbpRV0bY//T86V5UdriTdQsiMrYxI+PSmoXTmd6udW5o8RTejl0E7wC11YBT4H +weaMTFGj34pl7Emtg6C3nKPfuUaEMpB2WdZrVZ6ZmR4RMi+kDjpvTyKABRD7QgMA +NW3/xDvF8tF2oZUD3wZ7Zb+bar0VAj0AO88GlwpKGn2EXAn0dCdtvv86vGv4ymZT +LoOtFbOr/BQbgil0Fu3SndEF/iXbtHdAcej/FQHlVTbGUoGONJX6GUviDJbmINw4 +n4sK5erT92xPMjXo9Z+c/2Rq83fqCqvfZieeS+l6MMnye+JL79g/LVTSVO1KmyCa +xxE2RCsiw467yZY81ALWouKQaf691KcNyFqy6ixLRbXrYsmADXqf1zRAlOnqcBgR +jadJZUyvxHWX1jtHp6xQ65zoyUyHZ3hSRzOcdi6Iku+OT2ckDpITdAO/RCloD0bu +xBWXUPqSrwWyd8sDWhzxnFvvwt7HXxi9zf3ZR/wk0EP8TQ0S2PNIrkR15xrclNI6 +nUCaI30FGEbGc5G1SjEatQSMlP5VVOnrn3xteo7PoVGL/hNsFVrXb5Nd01ewGuHt +HU4pgDrCBSvRMb9IkeUADhD56l4Ge52dYhSyL8GAkR+zJERXDY/x2NyIIJRyJQMn +1NB2n31yVRVZbm+N/jhMgSiiKkJo2REy8Lu7HC/iBaHQLVE3781vaKzaZaAeZEAn +mZotriCQwJdd/F2oEqiaRTnXMb13T64CdeP4N+OwmtSkiCZnppEkB3Vg967O5RzB +HsTdZvDhMeofhXUZ7W1gZNSAT6SV7pMCC+KCha7Gk7B6PFaFn3aAvOCQ84JfxN5V +FiQ7zUxe6P8zXpiIeXE1d4tpZDzFXMoMilG02KkMJB8SICpP5xM92Zs++rGJoeI5 +/7hfZqIWb44RusRQUEOad8ktzMobIhW4KdhLD/Iuy+vQoB0GllH+0jJqm6i1UFxM +m/che4kngq/mzvBjaAYu0zpEs4VRKZmyep/d+ZH4Lnullc3hVDtD6F2ghD76xFSs +MOvUX77M99sYbZck2CSYZg1oxHMVOWJS7tBUjCSTunRcpnl+r48yfmfy+Owdmpt1 +AEyAy31RJh/7dsGjPfYWeIA3NscoiGPNcWVWjaWie1Ymg/NA3T1iLjdY6reqTh5p ++Dck5EX9jsBsd2LUVBbfjLG/rZu6gRf2EO55E87xQ7T97lmkpn0gJYDXqsRFGqVF +ZbnuzdVyvuSDs//CWTxyeOLFbcX8ZUgmVZa01Oqqg9RN5yh1ur7ISKGzTqOwJRaT +0JneYY27Xfz7XXLtWHw6LWS/F/PpUYRCkiNnMbEIg526rgCHs/SozTmr/BMSyyWd +mN+EtBBcDrfOJXQtBn7ddnlnlCy+rnZDr+JkfecXg/+AxJQLxXH0ndmI4wLPkCIS +jwIN+xmIW0IGML06eEgOqwB8NGPvTBmF8Gs0969iRgwlv3FQHyOXmlllrEQ/tU3u +x8tAtALXCwocCMxn+rxwT7V1sCETbIlraJfGZwxXvK0/SwOgyniAyGc62TFknKDl +f+Bo+imVfPsagxEOS9Em/3kM9GS8A3/KV7dp2POAUZsH+OL3zx+kIq1P3coPFd2z +qkAJz91ncBCoe/r1tPKOUVaLGDqVgbMyDGt+wKU11TC1hR3POSe39BqIEBols2/r +gXGGEW1OO+42Ja5yGRsKqbQWCXuuUP4fYy0ljj5vq4nQ7lzdp49vLplkK4wk/yMU +IB5rKit72rEMwPVKHgynsqCsFFvr2PRZc5hp+zPtXkvOgMx3LKG8BkDejqMokUYb +d8DwHSd/Vs/ITd7zRgS8THRGdygPVlJgyrzInCvwmmmSc7cGDQCZdv5rmoRnMSAH +P2cpGzNOqES3xAYYceFgxYH4ocGdBAYvEhCux6MSr7AfP+rea+eC8QwSYbAk0Nn1 +d7nUw6llAnX1+CNWo5mgDgwUxCbM8C/CK1X9Te9RammTM22nX3B0zFUKNqpDx4nb +jp8We5PXaTwO6WUi9GXt2shoyxyNWJi1q6MqhsO32h/oD+Wy8YOqzzKklB1boBbd +F0yrJqyu5ygxwpoCytH/JHE1r/AlXubw0K0L+ZmhDxWfJkKRvc2Lw25I9nt5wFTT +n4NXzQX8MmaUXkJfrCB1LziM6KNh6Rqo8TmMnDEWX2WIz+jkj1orR1oav7sNhZfc +8Pi3A3bbih1vUSeiyNs+2TE5zExPV7mO/V4lqCemDlcfpKYnhQTEk1ArB1c/SqE3 +CEs5k8bz/C/d3VMGFw1hXNGkYu1iVsNpdn6EynXtwt0E2swyWk7wCceDNzPkGD2b +oGcxg79VjYX4aMeE86IyZr64yVzt8HV2aKGZGvkPTYNSoMjdvmiSIgRcO+ji67qz +2ZEFHEdHpAbe047FHX9pUck3dCIuRL+J1d/dkqWx2DIEP0rAH5WujlZ0yxYD47sX +esHrxsGoUCbE3U+/Up9gLGUFCzzaFI45m0lvUz+RWI3LmzRIqXhWWZ8N44B7w+L5 +5tzfqnFjaOdrI3IudSq2crOUJLvBKORC/X22y8ku+VViiYAj9Xks0/4Gi3hqaud+ +W7cpfbGjih8tdvtkfkQa+B5+fStgdp23XEPr5RpzpZAhUtxWdy4pc2rjR4jTV8r0 +NT3UV1umTB/EADyVMnDhnI6+tKsKvF/oIX5AHLOYYRPHzxZH2Dr96TFQcLiLLtZp +qFJ/TSWAabEfw4ZZhkAPtFEij+1D/jik1tTzJC5Jki7yR0lHUm1aKS3Hd4zgMIAW +7T33U8nIq82EyabByL33D5eVOBmPOu0btiUkIDS3S6ikTnyrLEC/Dn7E7Af3YBkT +KfGdWca1RUWKSzTajcCm7fz4i+9/XzoZfeo4lxu8Ku9Tr0LtVq2uevzvpdce5hv4 +/jYv2I9kzlR4QqDlFtvGNfWH4wUnPwQ8lYZeqdiabDBLr3jkaifvxS3bjAAXdffQ +aAxS3FagfLLXmvaJoAh0fMtgY/heqTiNMxvD1SESK3m1sMhNFjZqXXC4rAWNydvz +xYpZpfPS8pd53T6733d8r1IKea4CjVN1upLx0IWNc5bH1gSq+BDTRuiftBviwlPn +OBd/i9L+Ig9IwTYj2o7WCj2eVNEuxZ+Dsww61D3J5Uznqbm86d+mr9wmU3oXsLp8 +KQ7ej0vFIBK2pdEvLlBHp2y6fJt2d2WIFco3EzZmQ3mitrTeTbcRAfojdvhtkf6e +3Qz4W3U7SGwRTOghdwxXHyT6iLZN7nxTo9bFnIHYTggYvqXYR+wgZg0+cbptnhsG +3tmBFQQHPj8EVTEN08jXPs4DngJ0e5PSDzNWCwxXV/z622f5NVIEWoGKO8Gl00jB +HKDwJc2cgflKiquQYBP7dT0ri9iECu+J2ydE9A6IvnH1dyYUjAEUkdW1Mg/eDanZ +r7EbUZiqPSqfyfTnG0xwscOzgilIwzfCne9QH5OefXH7zE5Sg9cItuQPWkaKBmBU +KQtiSMEIw2ijP0aIv62eZLPVI5U+gO+zHOGomynWyYZmRx9/6R3IKeRUdtMtf2WW +tI0KDWOLS1qlWKGQsfpzF7mBz13DQdBkt1n/MAXaqYlCbgJEWV1jcnOth00owFwM +RRxR+0aTXPQtbnfm7A6lhTF6u29n0fNAGTYCho2mnYIVbfHLPyrtvW5LHeepK7KX +Syhm2PeXjKino7QhUucyPoHSh5aexTH/4tJJL04VOg9Tsvb5MklgF2E3WH/PBTVU +qKDNRuANam09JO0wr5/1O2vWqwuZSigfeVLPtpAln4zknzVWtdNUtb6rfUD2tSJI +GdNABt0S/wAu4BN/qGxMgLSGu3n6Q50XZOpjVOzaKGfjU0NwkaqvTtp8MV5N2QNt +wPbifUwuvJZhl5QOLrn8fLzxOVGSfvmOTLLmVTgKpz5iDDpQlN99v+onhVRJbz1A +QVMDLsjJBkh6zK13fyWd4M/+6vMSY2gVhlms/oBPnzsKomTVoXussfpKy/I+OHtX +r16JAqwx7tsbwkaI1c1F4a+FLR41OUtzpOu/8MUtDMwosFg2tIpdNsNzzBCFg2qx +k9aaLnExuBweF4jxTkcVi1E84dohF8IypKnPdsQykTQoyN2Xw5MA9HjpS9TvSaCV ++fJksypyVU8bw498KziFCQsON1EjArTyYxcTa0xpWz5pMpTrR1Dv9nNlTbt6QvmY +KnlAhoQfkqzfw1AUY3U9r7uQGAVOzHCm38VFqoBEA6MIn5Hr+FkAO51nGXd7xL50 +NhEZBzcWhUlcYE0WLCxnoyFARMOtdbC/AkfLfkDdsp3YZxEalhUCeUUZvDFLVQQj +kXsYhKdGNLyuoKsI46B7mLgbB9SGtxbcpS/9m0Tfb3JfsL7tBP2W7gybTDmZJ0Jt +e9MqNc1cVUriEmGkylsqHmxHAy7bhLC7CQByUzruVoR8Ct8kPFgWFhVGgsVbqE8H +nwQKCuzgeVS8yxKM1ofbVE2ktt6Xj/ww09qaKG3mfUVGxPzoiSa+aZsgVz2iZzOG +SK60px+8F1IcdWEoU/RzKWEUPqG7q21VKNW8r3Gkw5WXmDMz0EHe3sS03TU29p4u +ErylgKGVwLFURgsK3m3LQCQN9SXw+L9zHjtzzV5UF9y81CSiiav42hOl2ckdk+BI +vbDrCNsZr8U9i/DTAA5ox9pTRnKt8+St/7Z4ML8K29Elm0lE8hRdXNGRGoNs0qV/ +dvJcvrRCTjNXT3rrS587aEtK+0bnACDb/Xhbe7YDcGexBxjnP+pnLzsD7KMcXsin +jGnLkR/kh+EEuiIwS3YsvtEkIwCH8y2+bIQKRLf+PoZWwvXzTPx5Q4HsfGa9eIMr +zJIYHDDmagnLgxYOOmZcLYrhDiAUB6MDtspAuJ1ffLmY8CNuYR3dgx4FRggkksWd +3mz/3hxdZxDIYaKM22iO0snNQHFhzfPYUdN2IB+W/w1Ny1JxVIAlkwSIrPwhgVzr +nza2zhmrIrhqFOZbjW4io4DZ1Tsc/Cx4n3iq9R2elIzdsoveVPXEtJTAAuIxRSQK +7OARo0YkNn+y1/0NWFtAJVjFQg9WuCcutwe0RrfcMdaLruHw77bFfnok5qNqyPFi +I9Z3EUadJ3ETv9VyJ7oca2ptEdApDoLqayFZMMEBN+OnnoGKcX4Aaeb7GVcjIeA+ +f+cWv3omPX5HOQDGYp6DOBgBqdy2omM3pWnNCsqCh+MraWBivRxzMNxLp0bVIKdV +Owj1UQUttZgJbdFg5YB2y8/ST6uPpX4AkBUa2p9Sn/vDMF0Dw1IDHZejJzDC4FfQ +SH62UFaelCb2T/LRbU6LYj/3DINSZ2DFx3fON4Oubk2YIS514igCV6PLBQ0sQgcz +GmryWwGxKKbAM4cw1ZblHvYVLisZ055W32oQHJCKGZSe4+bsjgAIUMvgmZ7kZ0za +ZHfIVXC9pozwscRTtw4AocU3h+vjpcXIarZXEgIwT1+fDo8sAWe+1//9wohud9CH +nO4JsTzbX8fnqdbkDDAfz6sAEo58gDokwrTbLDUumpOD90WHxIZ2Dgbfnx+lk7Lh +sBcmKKcAqTcjG7A01JUqZ4Yk7aTGqpqmY32B1QIzfoSH55j1teOjny8uY8/ZAHBV +xR/x4we5cIfusltAZrWqEHeUbGzqXKNQhoUmIeE6QAHV2gBI/FWGyjh6rCa2n62b +Z6rrOoJd5wZeQoRHtoXYfJ17Yvb/kNLA1TeWNZsqeETKqP0taHm0TAIPvgXK6UVi +IJU9HOhwU6vgC2aSZ2Po3rn58ZFHI6B10Doeii7t9qQdeP4F/b+7HeDgtEs+RWSo +1/IrRIv4pQxV4l6dgAd7PVCB2ANx4mEWYn/bKw2DKwTr4zL0luUODurilB7Kuhkj +VN0Szq6/iMQ++LjZRgOHAkZ1kTFvOckPO6kLljZgiCw4ytSIUFYvUIMKK6os+zXz +aCZ59VrOVTmyIZnq9BVnrNqUyhBI8vKtFV3uZmugnXEyRULZzEb9S9FdeIbIWCb9 +QvIKWoUtgpuS34XoH9RTyrd+TB0IKAsygwriNDKKHiwG/+BIqkGTWH/tlY5u9p71 +8oYcla+kG++Rf2LddylrDjV9CWEmpurHq2krFVPHgeBaqqEmhzLgXuMCut1K515y +3gv/TFHIaEul/oKkPzUYdS+U2O4mkxCf44F9cyP5N5eOHAtnqr2Hc7viwNs4ODEV +My7Dc28mKcEVfSWwMN/wdOju1JkSeW9tNDfDlQj1bJXL5q2DKrfpXLa+5/NB+Wjr +OMPyIzpNzxFfa1Eq5hIBztqRNsFYccsIIdFYZSRhwVWnnPqYqa83lG1kqTyFc0WC +holInZO4yf/MSci3YEd6vSP2DSF1zhSoVbCrtaEoEJBq3cX465Ow6r0v2k4PXSEd +TGd2FbcELJNm16FlFZ45b3lHy9XIyfht3zowgjcQSPV6kL/S1xctXL5nZM16Iol4 +uLNe+h07khEHptQuGFGHznmMiuJJF+6+oYE5xE7xZLu39dA9oG2x/LF4iSJfngrQ +pLFWLt+Rj0SyutjACswiuv9fRbna1Sz5A4K27DrSW2aLOgGhgmd2eQTIqqfnY7uI +wwn5lce/Q2Dh+YkGnxGq6oc0zJMjm4R4hxroi/9S3KHdeyltz3aAnNwOe5GAwfXt +sE1SOSWfclduPxOlmci5/0YK89jsKvBDtqWyA3neoSDD3YdSAg8D3qnSwjbVwmkd +4mjx7Qh1AbvVevz1RggB8U6jclRiwUILAv0YCz3eOgvmIMetgUoJp6LB8jehT5Gc +er+RKYl/HCDbtPAAzXvzfonJFe3BaKqxLTHIpncoSCpWZ7BIE4S6cts3zxx2vY0i +vuwM2t3v+8r5lQTG1f019sty8mbAru63V4bnKVfyspLAGPwjYgvguOqm1QVP4OTT +BYWX0JPjairZ6/cQA3xNySrSqgT6gkuy0QCBrTGwZjhp8gik70/Lx4Oy5OPnI6kx +S5L9FHagcku7xgJJKDuS3fAiekUGtz/BgMstJQy8WXODOPE0zp8t+GcSlkP6CCX9 +b4nhQydgOWBzSzBaBmGgYoM0zgNl/q4JcI2syX2AO8nJKMSu6bZ0EwUlD41zF8ay +8NWFp4MLQfClmCl8+Z311rWbV4wFDqvXAem6G7WaWCLmRuVIqG6FuWfojaAV6g39 +KHuxOFDSI/zbdNP32jQcMyhZLvYFESMzRVd1qpC+cSr2+T/E9h4L5+VjVkAnwqiE +T0Lkamq0LBnYYh3zxG1Sa5cUKZP8X9LEgZu2sfi7VqgpQJWShcMrcniqSIS2O7wm +fl/v25ovQBVivs/pYhDDlKtoFGoao3QmAt4BymAQDBTt5auQDVSBe7ah3VYN2ttg +vna2ThtNBoB4fa+46G9ZWWDsns/YijzhS84LEl5TwGOkTWdlDGRNNSSmML+2+yN2 +UXfO1m4TsY+xvNtKSgkhR1JvZq7tOvqJqugDMS2vSjpTky5aYeJmUrJtTD5oPCnc +NrOgC1Ji9rnwxObxlcgbDNHJrj5dBa3Y9tA0Djt6CO+3MHyhjmKpGSlSw86BJ85l +QquN33Z/oCNnlmVnvVexwe1dyp6FVnVqXPS/N10uQa/2n9jJaNU4DVnX398CwfDa +pTYXiR8TW+Ep0lH2RawnYWxcJY5lbvkqk+ILqIeSaOTZEhPcBwpK7TZeqFMkG5IB +hDt9+R3LMQUwk2qdE4CcLtW1NdXtiw1HIuHPo/ZqBxcUnJZvTBdV/KUp2DcxRdXk +kn+mZgwQKFq6ZUFbN0I/DR+dmJC+8r1oGo1Tv20sFvY1zcY1522m74KseYgV+NCU +z4vLbYjksvUkICatipgHEFVAeLgLjBJXf9YkXUrTuVkJ7SmzAAb6o++bViNKg/fl +vq1SgZl2zRCw8sb+f8fLGUhgI4WqI/BlF6esGzhaYO9XjHwwjb69Rfdt1E6d6A/W +Hhqlic8D4kzgjUavAAQH4wXCipgNUuj39EnThn6BHraN7aQELI4S+lyBYH4Aat18 +RSmN5vT8TdZdE9N5Xxfz9i0n/Gnhwy79nmlealA1BURR/fkhG5lNTZA5Otnne1iP +GTwGE9icxx14+CbYmqfyPJxfcMquj6FbUn2mdeNg2O2U5Llg60ASBKqxCFfNWOjF +0h/cumAXGbQUPnwxjvKIaGitmcZe1yhBNDvXDqMqGUseKWKWllDi5Q/LO8QldxJo +AY0xiNwm5QpDKLHxdWfaXPrQ2soEHBY3bquG5+zO5tBLzyy10jBKAZRBfw7hGSro +cezoz7axzyhOtamSEiBUrZz6Rxi3WNxb2IeUllqZwM+nCuYQnj42eLhw1Nzyub+B +A9ZYRcCWNgMTYy9Skh1NvtIx80VHEzkVE7TX9ZjXBFLk/VPgpdXjHv8wpnPlGtOO +iM2+4ZgQJwcrJz/dWMdDx6Q4JYA89XbbPtfywyZuU4BA7LTBByTGdkhm5ASNrvGC +1OabUcEbzOtdAYqrJCoW6OrSQM/S3zVz3xF/j9Ujr2TaNEPXwGajVVIkoZGCzUtF +V9noNs5vRPZ0zAnnbWovDxHkD/rk6TbDgU77nxZkfzVtweOIdRwJSxaLStM2Aeo4 +p6Sx8X91Knkdu8fLtHt3PnEqCgNZw2NFppwfZbdiMBcD2CkCY2kJitO1iouP5Hy3 +M1HMmvHeVO4ioGQh1tDa+Dj7pgXmb1rN4VdbSAmCJMHhc7+H35HyhwQzN9sDHHdN +Fdm/pVdjYA3hBWM369oXHHNEeYdr+i1Yi85VbimL4gBtiqS6XQuoGWUkK9de31/n +IN4RPSAKyvyTVzmZ/y5sr6hIAEnjQ/eZwCe93lAV0XH0t2KVvguYgqbqbFbT+Rlm +VreEG+Vxhw0yMb7adQ8J7QCEzQQkqgT2Yla2rF2bV1E5wN3HQTgsJAPCjygebgof +xo9IWLuBt76mSCxoFzjOfSEl26Fhdc7kchpgojifz6IT+zJ8rzblZOMGQ/X5dJwt +ZSxI7wlHtZxBGrIs8Zm50gpwGlTwyN5/wIt/HOFlwOVDry87Ro8/crQ7dWKiLTDb +daK3I1ThCliPcKbFV7ZUcV78tfPAVrouDK7n6+q6Jv+aM7SlIaWyjjRBxhjGd+/h +XXOfG6S2aLlJt34e8NKth6VvSVW4jygAwu6NCDXCwqEQNJsO1zIL90KvSHXZgu09 +APQ8/kjtJQwr4EiBHMhxO5i9i4K16CedTp4BLNdVxFKjCxywbWjwHKNK28bXyNf8 +K98O7p1cQA0OfqAbq+aNa4D+ETy1cM5I0IzBYU15wQOItuRyrFvPq1svIcnnYEtS +GvQXCYWrENm1LJsCCJJU5vm/xzD8k4h7nVUIUCmItat7S5ubzgHsFfgfzsPDPSv1 +k4ZS8gkgwpNctSuP0+0rz1rxdxVivBawwVV12mkkemfgrQ/BK3WNylC05KawWIku +a4RKGwlb+ceiVINSTY35wAn/zpj/F/NcwAoEzXEuHtNGeh5mVAIXUYqLPeVYjfoH +iM/+spxLjFHpO/gLXOiOX7tWblo+dXLSJqzqvu7vKbH/OFUXJQABGXf8HAdLlYIM +vE+Ffm52g1QcV+rsivdIqHiXRtsfmwqXaLiBabNQdMb3ZXxVIzI8evKiaQ+rXUC/ +CIFf6OCLFAhdJ4GKh4g7feL48Bdf5EW6cnzzSC90VhhnqnP2veZOmqu64q9btP+t +ncA+30n8ukNbii0XgXOYwf+AC+ly9zkqMO949WiIrzWVZEaY2e1PgPZfR72ZNgkQ +d+tGr6ESXgucvwXxIVU9eU8H/j+Z0/Ig8AieHl3GnXQS1hrEjT+Sa6reCvoZp88U +M6U2PfhhpuZfizQt+/mxGRdokYAluezzp/oyTWSZopt6eId+CM6emTXN6Yi4T6RI +3C2DG3YLLne1oIY0cVgS/D7Yqg1dlxdEC7Exj6Jsp6ZteKE/kswJHwly8T7vOd4w +8VdxDTbFezW9gPRaMyLP03R7Bo518ED/NjZkz4A49d8HT9MXIRSy18+EvuEQFoyG +qcsaidO+pD4o2PecDx7ksvxQFhH8p+DbQOBWYRQgt6c+Gh545XhskWtHFqaY0FW2 +RAj5oE6+rL5wQpp5CYb7EUvkYL9rJ9cAoxO5lkcf7NBWlLLCwWjmrnLHac0sNlKn +bFLX5wwvHY0EI8IFdf70ZySR3r4Y61EJMj4kGn48C3JQaC8TlSQGCE+RKZ4YOBJ2 +Iz+XNnRu0myYgNWlbmrQrD0tOPgo+wh8oRk17aycR+DLPNGQ2N8plokWdCDLMG1q +A8gck2vR4RR0PNgwRSgvq4rKFKNiRDQxQKNoDUIUbVyD/PsunJ0rdDpc8LgnE1DV +8+9mOwfVq8YpEaMnHzVpZfqgFXqvekQ7+KOuDXawdqYSLoVwo/KyBJDmsTyqZOao +Z1TpRlDPP8i/zmp7YaR+YruEUH4kj5j7dd7Das4A9jYb77Dg7cVNtmeijKIYkd7P +j33FyoaIcb4kDwVMyLw2+YS9pxBJmLsXdIRk51bnl2vnwOXnwzi+0rIQgYhry2La +rqX36iFY5xqxd3xNvCd0pF2+X47e0XALAf4EwJBxyzxylImZNn0rFLVPSUhgBig2 +xQGqk917eYeZS50NgSXDuHK+X1DXIrZU5PN2fKx6loJv/E0fHdpVgA5L+FvWKwpN +OrwX3W0sk0equ+njwwb4UJ3rhqvDwCVFovnlyC97xKVzhfhZWpQRterDqOWtDG49 +TUHig0wMNfSL0WMHnhkmMsGo5Ufqs8lHR5EZWYOw/A1A5v/+N1a6QxK12be76HGr +utimYcoUBWXS9qf/taei7BPYwMlkJGfTaP6g6ebotRsKZpG43AwnkFeCKxl/EnuX +vPNeubJXLcl/qwrzycopS9fdl1EfUFfOL5tgqa8xRtgmnJ4SlGC9XCgTsFU1F1Kh +Nowy0NLUhH57q3JAfHSLbZ9HjUil9I4Wl5D6MEhqo8wm83Qnr3fCpJ9Sso8AJslB +CHaXoh03zxZ2iSVdq469aSsDfTjor3A0/CLAJxSfSqoaKxxL3CEOfB2C9/YRqaAg +rkfotJEmoGIsDybIEUA9GltGCO0RNBuVXZcuiPpuT0EzY1aLJe5WWUV5nn3FggEv +9DkdX0klA5PVdGQzPPD6/2K4dI584mFJKjnvyEiopEYKOcAr279w1NkJ280HqJpu +otZJrt6MXTamz1cTVLUKR7Zzgy9Zgbzl+l1Rj5StvNlqJAgGTRej2liNL5l118WD +gr0/Ca0QNWtDhIzC+v2YB3CdsCkAjErgMTFU+RuLZ340T5R6UbxHj+0bY+3Twae1 +qItkChq0N/Vk1NJ7/dNJ2c0KtAFDAoI0fIWBexa1WxvIx7NIuJx68vWT86i5RYsS ++oawA03X0rjjFcfqIAuQtkyDQBcTBgz+PrS9+4vBMXqOjHtJ9CtAkyhZ1jIobj9U +NUzW/pN0GABqG3mNwJlYCvqsqU8yhz634bLOSrvc2YTWv5TuECX01yNSXgVEBN1e +cpE8oiH1OzDR7ga9aZhfhDw+cLmMPPkDltBinqngckDaoQc4f1gjX82Z1hF3vnkd +5t5aiA6XQx+9DNy803IAr33b80sDo2/MM/MakiZ9fgUM7xg+MK03uSjOXYz4Y9QG +hcaVKiYXSd6yY2TbyqUDkLokUVjv461ZcVTxm+NQoe1/rmXjwT3Fxh3H288u1cku +xHm41Ixz2SmnordRqb9NMiucwex8XNomPcuSXm2D9ZziSuiSOYCbHm4FtNQDH9gL +fJCahHj+j4+YgzJzou24wRV3l+Vbc8BejlxQikGgtO94P+wj5FMWXvpdfVx4y4Pl +lH+BJX/Bd/YFuOg5d01Gnql0DYuJjqO9pmckjl7xnjP8mmZ3MzVThwaxm63VbKlW +XMGfUrIaT+4PWXSBvFKtcuHe44R2wz7QX51Oo5ipR6XwOSsQeWV1l863O4Mx7DxL +LZAN61Lgh/MqM8gnz/xGMiBd2DbxTkMq99VrvQqOwJpKY9fAfO6QYvJXpceSYstH +b7ggqBJES7S542i6En8qUm3KJz7z24kPMJPTvt5TfzK79AK47Ov/zzslJfHxciAV +sCFpcWdoshajW/FFk+bQ+6P3EOxujt32xW3l8vtUUe6XzNM7wanFHDxR1o0HFTBS +RWPir9qOieAROORQdJzCGBamm6uQV02sWHh/COYTG3c4IVL0UkbK6jEVPJCkvax+ +CbcXwkYCqAoqe0LX3UzwBCSPrlSR3N2hXdwrGeGnO10fSlEE5iJ02KfaU1H335Qi +HVYsgW9xfwaRhcoOFpNwQtQ3KSZGO25m8QuUBje7zkkahUZNM62FIDgzzJzg3zsq +DkzYaj6B17ay6SzS7K5MYjdf+kaBw82TvtlNtjbZ54aMlFbQ5HvXksbPFja3xCR/ +UGJInz9b9NhW7yq1wo07bYNgOybLQjh97plWIXPvpDNILB+woOKjR1a2fGjlieEM +P7FTpC4nzbgE4R9FVVkb2HsppUPgNQQ+W/gd1DQb5ySJLFUdFMVgV97RH7zpEmB3 +c1Mc+R+nrWYH904WpmHbLKoY/GPp1pQCuZPgq4zg2nDMjRmjmLY7idlZFYe9NNpR +PBwrmvqrqEgsyUtxl5kF56htKc0EdBWhc/rOpSST39YHc7+6YHxvvdtw6FE9tFdE +EzLXp4iExJf05XSG12xRfN/0RVrBHNe+kUO+wKaqVHddSD8XDd5GHI3b+b4coqtO +zEM21UwX5wX5Pd45w3IXoDXkZKYospxbCydCbacgJK6eBnIJdReFulqqAPnVuDco +S69DIoJVVYPhzVU+uGq4xXYKULCbY5cgH0HrDxu/DEFf0n8g8oOSf3sgpUTmIpoG +Yr1/gefcStdOw5zCySQVThCphcsGXPyusLvyxDCaemkgIEf+MxhW6anj4yGLK8Np +wFIykEItR7JeWo7M/8ScEIudhVo3pvpoV5fNsdSlGyXmMH7mHDJYxOKmWptBeKOh +4R/n4+5mKE23bYFl2otjoJovrpcMib5Q/P0QOx7YUpuNnmAXZknly/btrSqtzk7y +jGcAyrxe0PUN8gVk/dtcOqxlWWXQpHDVitzdbjJdujQNbNZKd2tEL3nulHcWVhwY +VoEmAH/IDYafLs4J2ZxdVt2ya/knxb8K44MrDgHqL9JyjxV7r+xc6Bjypq5+I7P6 +NxgloMktqoLIUXudwDxDfR/dpCmVG/20RB7+z0Kc8KRndHcJSvq1YgTaVn0a0FR2 +3333Sw0bvSpXen5/LTBxozgmR04iR6cS2eW/yVY3XeNafX0opQdxzvfTEtw4NkB+ +kK3jB1LcJl/UR9ueiVj/rtOiltalCFWScLyKaxs3pIEL9vTMpTw3m3+WN7WyqNIy +60whe6cyTHFgRCHfqtHbtfaHRCcnO/0ZVkPcNLOBJdTkvOOwzYg2RRfAF8j3SMZp +Lnev420lonDlhEocMJuy28Oqkvm+4J/YgR8N1ifGBFP2Qy/oK4q7z0XAUk/L5BoZ +FXMUoYFJHzjTFu3Te6+REPV5rvMZ9bRAF1Egc/oddUgpKPEqohyF5ARbhVuipRPn +figw5wntzRF/wv7+Gf11qNHINSnFincIVgdy3QHQHQrRtXqSg+nyGzZGUVhxBYuV +4e4RVT1dGJ+QhKqPoCQBzhg78JdCrZZGB2e3Xf6qhor48sDalvtfTLmqWL4+HWKD +4BnrMCLQxVm7aoK2kTkciSgFZvazGCny00NnqTmS6kCUhVLzr9f9CrX5w7Vsj0RP +xKJNVliqC+8wln092B3v5Yxnx76WGUr7DDtd4jvcFHkW1kYc3Qg6cWZ/5tXRo/6I +D6hx2RSmlNbnddkfgocQYTjjw7wrL7UtDK/3LT5LvVAekrMR+CQP9kbYtGn+AAS6 +FAFK59KI0d8nMsCTA1GauvOXhQIJ63wvTDFYJ3gbwSTBZW2Z2uDZuDv1+wrQvGsX +ugpc3em0/HLH+Ttv0TalPxnN+LNO4aH7Qygke/v/nTBov6xctQX+4s2k/+UBP3D1 +HFOlkYwokMWGHkI8kdJLEm+mGc9AerB7xW/S/MpQj0ktucRlRIf6pyLWVmq8C3dy +n/FAqV2igrgTf3N5xVQTlz0wgpsbcoJ98nkulQ9XjKN1/KGxpwJ+UqAREmLd8Jjx +SlBLR/ZswwzYibu3C6DFy/JnAKlfyljlBuLn7g6j+qcMZ47PSV8phBDBBRCVh3jR +NW6pl8WjE9drTcPJn8jCnJEKOZ7lDXn34dteJb2Ksk7tP4VtUiXgxOdg5Yit46kJ +p63CGhQYZhsWtlcSO8Al9we6AyuW+806UhsPI+9geiNtEqtzSnylV4ReOoE+rTYG +sRC0adOBE/5N3QN3Om6XyRoknZMxbtBfttHRVd9vGLnySBkT3EU2kWG6hQs7ASeF +qvGJJjXdIT4+4udZjXCCwCDXl+ZDOBs4kvw3Jutc9TjjIhYP4Xt0OkL18nH60oQj +3bGvU94SqCAjl63E5lG69oi4zga0maBVicGRypwdZXGGXcqOR77PKe1eUQNRj9zK +zCYifTgtGSKI6pteUe3MZqDCByvT31rf8njqlkItT0bqCkJrRmfMrOHs/pImB80p +dUUd/9FG6Se9kglC+3M8MEuNSetzrS9PIf6SfqMT8TEXQGmIRphuyILR5Q8xlW+9 +kVq4euZ4S1U8piSM0q1o/lFFlWEgtVbVxM/rk4YSOWiNRs0GIyatyikMxGIz/6HF +0yFJ/Rld88M6ed9+IwEFcOAtl6kd8IolX348sQCtQuGnhtPibnJsgx530esslzhH +Bfdx23V6yqp5ScixjP7OlZGX2WNG8DuoDPNP1ss+T6i0cz1jFLZ73+GvIKNQNkBW +kYtjjmukkJQYQAGSEzyDGZ9zuAIfbjYot4M9PU4tvOJLksFYAdw7K+VuorbmqSzL +VmqmhjsglYeB43eWXpX17sPuOZfcbmxV8Mzp+Hm+NCKeELs/QqJ/3giIimBGsnUT +zB4e9UA9W7OWRPzuC8xiVjPAXjekNKP45teAqr0cQFm1gAtV2h7N+rbcB1wemaEr +klg4R8ARIvLkLD0R1iX9KxR0rwaPFaqDXMfnTLRULSHigxZMGjEfw+tPGixveOPj +OyJAM7w7DStaKj50jjqxQI2NF7n1TR1r2lyK9AbJYV5EI05Q+2Gu1zhMOOyut1fi +mC6d397BhJPwDJ+3uA6kuOUcemVkrRragK2Kz5/gssbau0PZbTeQtbTasZAgb0EF +zwHGv4iL11hoKjPKfFWU8VDzmLOH7D7uBzexMTb+aAAJccW4OYEFJdDn5wlgAqmk +J26VxUi79zG3oBcw8bbM8ZfkFQxCmi9t6CR+lp3HRRniQrL/Ny1lPg3QXhqNSmji +K57kWq1R4DY6LoeBMSHbKUuEucqtJQwFKO5niNr44oYdKIPk2aje6Y5ziBDJ0oPq +CIvT9FDYMujmRAVYhWDOhBwgMRbiIjQul7e7UK8iWT3+ncEuzTNaMmVl500Q5c2Q +C3DQS7LWVwtAbO5spBCyONAwyY5kAFoFq/1MTOXgo5q32PAVtsycii+BcHW81VlB +QlVOyLz3qNshjbld8wsPsg== +//pragma protect end_data_block +//pragma protect digest_block +Yac1UeXsmBvviCciB/hrnaEqr10= +//pragma protect end_digest_block +//pragma protect end_protected + + +//pragma protect begin_protected +//pragma protect encrypt_agent="NCPROTECT" +//pragma protect encrypt_agent_info="Encrypted using API" +//pragma protect key_keyowner=Cadence Design Systems. +//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) +//pragma protect key_method=RSA +//pragma protect key_block +AbhYTtNJq/FK+w1fFKm+6xLsSwJOb+mq9T3w8qXIOEgIUR34Njn53155UJnoKrVk +evQKf3BDVcJFLDEZFnCWmDCVW7pjhfevjP3nsAWwNYyEp75//Bba7WgJNlMzpJfT +SrvHXafsyhaZR0ZyxMM7Z2XXjvjBnjZK8vYLfi0J1br/pcztvahh/83ZQLzzfd5S +lqNwBQNiIIxS758t26qAl9x+srdZXs1gKnQgWogadySoK5ww7L7eG2yYNBXrIgnR +A6b5wT61eo+qS+69D8BjfXZ//UskIbXEXsm3bFs9DBhUZt+f8aJgupsuOVODnQly +2epty4jyyW9j/bg7csrOfA== +//pragma protect end_key_block +//pragma protect digest_block +Y5+OOUWvj9rO8MVfeQiy9t9WFcg= +//pragma protect end_digest_block +//pragma protect data_block +2G61gybV7fSpHBr3hzTiPLSbO3KrVGJtbzmoXKfK9jVu3st33/m5gOIe6E/0LrCQ +bm7OCxVugbx7jJn5krynLBO04tm5Me4s3fxNlE10lc7Qr/EVM0RLwQPCEfuI7wGu +lTkGCgHYp5B2Y06T4+IpoGjBYHPcf2t9wYtHuES6JBwIdjh05tLLVxMT7bimNfp/ +ulZkwcrrntxzcQXyEvL6Bdd/IiCGSwcbVeIYpqeAu7KOAw0+A7j0HT5Jh7j+QNcS +Wl6fc6+OSpg3YmF5lEoAPn+0MbIJKUBUhc689Hs2KKQn8DB6XVqLy3w4SZIsr0g/ ++iN1279RLXdGyYk9GrmFSQ/Ar2Eg4o5A4KrSMzVBaBxp8ISZCvoWtCPTfZ3EJtfE +nTGsjN18yeeT7W9V/4Uy4kj8ZuZ05u4pqe6+uFowqAJlL+Z5Dno/mcpbWdwB2+p3 +MlBVcOky7vXyum0t3Px9ABN4GIcg7RlVEZRybAD9Vmrcry42PaNToX+3SQTixFGL +vMkFPj1BH2UxCWNdkxwxwQFypfwirkvT3OHnDV7KhA0D36X+yAX6MgE/aSUPToRH +rpqTITZfhdrKkrz1hn2tmqyVT+R0AaUOEIqByuVKnzTFMcYm6FXsg0tEl1BxbzWd +HtIZri7ORq6b7WTSorShseI8n3OXbc1E2vh6Wf5MMS7wkqAxczrTvEWi1vO2onQZ +N5QRkuhDCYtXfm0b4tGSAm9FOFL7oyP+MK+jvtnNKETKZxbXg3izS3GjDAEkaOQk +stKu8cctflT9ssGsmOm8rI/zuXgXAahOfoBjS7ShY67W/ooPY1+/W4xWbn+LdtqG +eh0ZFPoAy7NYEbO6ApunSHvq5RET1FFlJQkwbpGOP1Utp43fg/3yXS4RLcBX3v0c +wjaOdov6x69s7o8L5GCu7zbCZRwm6jdQ/D5URCbTm3+hcVpgbUu0f1cTO54lPuCX +pRBW8pWDrbVbgirX4/s4+AGCnnkg6k1qaLJXYPdsp07rhYO4wD92pfkJCpvz69hl +PMc9RR33QZx7pg+a/gJxFeM5ez1DYVgRU7L1liirDHG2pw2yJxQTZrN237sV5Mrv +YTLBGD+KsaOunazfRf26l389HDkkJjwcyJKir7YVlSetdr/tzpmY4BCrjebiSXjm +MB7vLXci3i5240tFvQsb165JUM5fqagbi8KJPBCeo3G9p8ncdmTlEFESRIX/X0+9 +F4QvOsto7rBPfS6zJjOlXqQ3USDgsGhkBt2ElAtjymOrjIjX/qgiSt79fB92Yna+ +akulcxYR2W/xDJEojmVRACNVoSPyWZVvP0hAWwiqcGQ6LBuYdFvan+Dp1nT6qVwL +OhdOHri0AdwxII+v3dvrvJfKHcxqx8G5aNBi3LAPDGH2j3CpV1QTgVggDbsAP18o +US1z/vRMqWEJN6U6xTNSj1ILpPPxIrR9Rh3kddSPyNHUnIE6fbQ6MznfN3we/alK +plKs4F3kz0MtHTygKX3HijxvqAM2M210nqr/Q9ZGfFOxxe6ZJNfj4kvTDSVjg/I2 +dlnrzjfoGhh3zeraWWrK5n08YgeVL79HWqiqYoYbdvEU7On1q90DVbyeX9JsbCPL +Bpzppepp4O7I914eN8gEWFYzKEoP81Qbv7pMGT4sBduMkUPSqSA28z8DZOzzz1iF +fpIGmXdfeV1pAX9miKOZTD4vopvba2uhmSYFYBmd8kuA3P9GOhBmVDyMgN/shwnX +0dd0hV2hUfkxNwWaEHz1z/c5MX7HPM8vyOWrP8DXo8kF1Rrsg8dYlHmZrNz1sVhu +JN2hJa7Vsg1rljL+Ul2YJH4ebbi5/e6iN+9yzW6HMqrJnZK0/P4XMb4nvRyVJiGt +Wye+WyGm+5XwzlG2wRmhlpV3qnoA5f2d9J2A7F2KCTBTrdzUQCxpf8+slUMc4RHR +P/iJG+wtSBZPqOuCSK9duqBX3Qs0d0XfPO9sNgMAiZpRHylauETTZfKb5+xwiFm1 +xXUedPjaWMdhjgGyrWSDpRO7ADdEkTjYNCMzylks9UfVRHqahrfQv5Igs+yyHK8Q +JYBY8PW1kq1DzHzkbywW/yrcmxeDILw8JCYxTSAc9jBQ72Y2q5YlWgiHslCsPi3E +Td7uNcBO3eXY9a3LNd/8o4QHUBq+mz259lys98w1iL/GK+/XpTuvESIMhqiNNoB7 +gLCDGX4g2CFN2BIt/FAyALFy+/Hzl180xo5f8Ya33DIz5gQKzB5zxnAAiq9N62y5 +O4SH5X1sRkrxED4guFvwcNBqkpNfDKuooVA2OhlNiaUBQmS8rnWwoDPM6Eqpoara +EIJCllI6Z0WSXR+mM90wqy+BZCuQdsWZZB6Ko0oywpiPQpR6acmvSzIRtNjbDX7H +0X+DN7AVaFO0iGVBhnDzooAwQilD8eREvGptgH1eMTGOipcHwU1O6KvyXrYHtYl6 +LN6R+a6kiGQQ/jYtyBHmdFRqLKzZI1Z6wk2LO7u5PLkfpO74ttjTNO7q0GG1pX1E +wNsyX+nGzo2JgRMhLgEf77BzCJughRXhCMQknXB8yDJR7XPT36z9THmoHz7im0PW +kLvAHo6A2vRq/CuwCxYnWrnieV/cLGaydGp0B9GuMpvUSiLLPW4zaoiQb84RJWIG +wb9lj0uKlP+2c+4LNduRUlwzxLBFYegD8zbVb5kvcYnC53zPWICeb8Rfq633VnRE +IKq5xqymDIWQDZ+PO2e+nr5FQJ3RalXkWvu0LQBWszif2iueS43wcyMZj2zieegl +ZHBjwbazmS4dBbJuw6OWOD1GO9dEonikzym4u9P2LcRWQSDj5rw8zowBV9+mCaXc +gFocIYheW6mMeOpKUA+XjH3u5EfzV2jH47NnkjUBNmKmASS82QjGZhsX5P8JS4Nc +xBKoGnGAbRHz2OKiVJ1+WQtlSJ1hdgbIz1WONLPFwALP5sJUntjsBNhkRc2rVKwy +q7ZPAR4IISmv5P0R3jbGSzPhcJeV4kKLsUC4enXEvlemdXOGgeg3CD/kXhI1LZau +5leatKpR4xCcFVi6O0HLBlhyx1Zp7IExwxiFYs5H8tqtNy+Vb7hlZ0jdAoyF7UmR +N9Bb+qtKjxDV5L32s5pVv1tsGAByKHAWSNYTnlY+vN69JTN+N2QRa++qIeY2YhAn +RJ+51C0eCG0VycwMfURq0C0pVdfKT7EIRu9ga6DRqAYS4GIoHmTt4U9CrKvmw7pn +B9mSvBGINv34bh9aB+GQ5UuCN9/twdxxhyha+yvYS70Al7zS9QA+oJOxn6jVrlf7 +oJCtkkAw510nsagTtQfaiUWx1XVLgIJGlEF0f5L+IT9pGwc0jKvtFD3/8lBa88TZ +jnq2PLl75d3raWrZvLwm8WohvaTAWytEaYZ6094F3kMeAXL1u72Nw1qjPWTE5nM+ +aQ+u7VhxIiD/E7V8xK9m9kpU4M/0O5r2S2/3QpbTDgJkbtxPSg6Vm5nVNJV+e/Xr +87ZuaxvEUTqK83gKjCa4NdyhNweAqYka7n5knL6kkx/ZkGGw//yVmLVQKFMwQu4K +Mpws1barkjlTetkzirYiqVUAjLIH5JqX2fWEvw0e3mMFvusYgcHLcn+dlo7JQ1Js +Qqyr/NpoQAz+LU7cLubtEdgZBY9sPF/M+3XX+FzE+9i3HIsRvx8yrSJRNXXvCYFX +omvM6jq+bsyn70B2kLjYicYzUVNRLYfp4glrqvTZa1Qopz7pGZt7kxfDFnVA9EDH +yulQp/GcpbCYt2bNjkZ53Svnlkklb1prwueNaWWI3SZGB+ESHD7+BGG1xS1JImWp +enMuzIMrRnv0k6ACgayZ6hm5oB2270sgfOZUeB3bEbClmK9P+nJCc93hYkCkZlFa +bLofW5MrO0XAFkK8Trc0WzJXCdkJohWI6t+kcId7Y8DOX6NhA5PrPRFyn5OwMS7O +hgGbKE+0a1iHlQhSBbGMirmL+DhU1cp8nJ9Q7/rDkgM1UJSuZQgsFUiipj18t6L+ +keALXRyj5nsnejHjZ3DRDxOMmttFv5Rt0gC1LfjXVPrms30i2quYakVgjhN6vcnP +wGnwf/vbrtBoyefv7byMRSnaQp9tKdXNmqfUFdVTPm6LJnFmXlmgzhDCO7XWqihu +kZ8rg97IxyO3PSnk+Ovtp7alTsr508/iIiMBBJsTiWH9V0w+z13XuuVQKj0qtb7p +vVT8fnVekz/eCm2ol/9C13BEXP+8iQnqm4aXtdTK86OzbnaDC4zeW1FrkI/CEHua +2t78KhONj8odfXL//33wnNRckmVBlJsHg4+s9I95oBMvG7KZAEvE+MZnDoYMZ4Tm +oXNS336EyJHAbdaKC6t4mFx2GZtItkfDE/YjGR4wOFXbU3424ZXcoIxjA+9xvWgS +xIn3teqiHgirA7JElLzWjb7T0lxoF5ZwwHmcKHpyroUAJ6Cx+SCD8IUaBuWVq3V+ +d8gDOovVxLCklY01FwYrGcUG3RUR+3wzQgVb53GbYuIEHk7z2zVZfWULiXfLm5yP +hsekqIL0mzz/62xsL5DpZ+5fVvXXgSgZW7BLfxTQ9FlRBydXv8vwymgs1y7w99T4 +PMtPxEAzccE5PvCNeso93wEc0Y4GZILlU7+oMeaweSHfP9yZaDdj+MwU+Z4Q3/oF +vXjlKI2hd/QAPVnNN5Q9x4neXY6fEu70rgTj+94M/hNHEA9Zmxs0Maki82EPTZDd +8lnPs+8wYEBM4YZM8cWy3y7y8rpCq5umdJliuQkWmyLOKyhZ1xa7aI62szhx5tXy +vx1C7KT8R0WXoLJettmOUmWQA8bEeq1e4TqofIZuKp4QmDRFd0Wva/3n5nkJoYa+ +of77sjaRz2QbCBQE94bMDSz7JPUcQpPzsCe6ywol3f0oHHkBinxg2lateH7zChL+ +2K0TmsMXTfset6Byw2Z115ru41IjnDGDMYluLKpSD/d9+YwrAlxWXpEnjavU+VXx ++NpK03g/F8aYAmHoyaQxhhQYchIPuxic9x1Fy3TjOfW75u4nFsNwSYqm9/lhA7kK +VSbZSuxPVbwETW33ollN54cp+vCv0nZOwZEXm6gl/REcgPTxzKY6VlJv55Be8I29 +cLf3A3Xkvc5Tj7C6Xxutshb1j4VdUDgB3pMxie4oYOTq2rXBv9ei6nyrCfT51DiN +0fbkDrJ7BJTNu9Gzpnb/S/dAEyZsE0s18Su6aDZgESq7Rh76q2YbCL30CtChgqM3 +d/6LV/Xs7XGD36CiBGOT3alAI6hWNJfw5kB5HuP9xD1CJbtxMKD4FXLl5hc2gYZO +XO+dkpIawb5JTB6NBDPqotCibcfpHR+TTus+yHMntSUKZdVLa3OEWI5Sxgs1mAl5 +jMyIuNHfOjC88dpk9uA2qI/NuEJzI/k3BpG9sXE9398nAFuiTvIV0mCt84Hh4qqr +xSHfpo9/KcseuqiseOufGO1uGZyUSV6Fl3em//xvZsQo0ME1pLJUZOHP6hSpA3qX +s9mRyIO/r7QAw/zG8b53M+1BR6VEM6vNSKSnvxp4HUhnBki1hcfQwXGJKFpqo3ZH +ZMhCqp3lk+MQi9zFhhx3V2dM6+EfJXnEJ+8coSOdJajMJy9fVBfSXSqAh/uBfGIH +N4azT9Wlu5Y9Jo8GHSj+EZoLbiraXiKI6tNJN2uR6e7YzWPp3VbiOSrr2n8kaXEI +VlKCNY/JaTGAZKIHj/jESI22rwm+sqsxLrPXGQ5OQKqOX1LjTe7YiFxsR1YN9lPp +tVO/0yR6QyY6ZLvg66h79hczpY9E+odp8nSWw+wdU4Bpriu6aGNeuyIGKCLwQ/6O +EPoL870so9tQ2ZLZjdSGVxo9xxlb1YPWQ+RVb2+ChCr48OHUV5sfYe5p/34zN+mm +sVy7GRHBs3Q+VMbDtqeMgFmDwWJ12koBsD1juKSlwDyL9db/ffIDwl7aUeZmRa6B +pEX4B6d4uytFx9MfbI6TwSeVdGFuLsprteI2J52t99gKO85Cah0TRB4uoItzd8Tb +zpWFPaGeUtdf531Lf2sNhh/gHWIp7HTzC4ayv1UKD+gnTsGHqtv5Oe0eYJ/GyXPn +o5hGYRA0l1TRhkhOHKvX/O8cMw4JWLyW+IULv5bc0Og6zIn6NuiP37DvGwMH96L3 +l1DUPPCzlF8GJgE/Azk6zdLkgrHkSxmoBWP+J4WEIlQ1ixz2q0RivG6rsUn9qVgI +D0TZ0FlupnBhQtZSHdmIQvZT3IpYZJWvWPY2SE5iJECDhX7zS5L/kdp5dmjsS3wX +2/VGQBY8kZvxXD/pBZCSA5NERt559FHgjC10RBfV6QipfMf7XzEb17dlGHspULck +QOhzLK5OOyKsNgNie8M0VbtlA+3cy7tuIuJRWC5I+iAkn99roC8pBWsHgTtn4Ewt +eY5VBq0eK31poea17uPAAB5VEre4zoJmH79csnKIxDWoiQX9O6i+0IEv/qJ6Lk18 +Nkhj8iLQ/Wdxi6v72DquY9mXMtd1CzHA1+rr9hPAi7c3jais8vQYl6A4mOv5IbOa +xnUK59bywrVsMxYr12JiNbuWzqoyhPEnsQol/udXlJvBkIHJvQOOSxjWYVM1mxD7 +8Xhhaxr5ZoMjOEhMjzuDrk8pRHk/HEi+A0z4ItOqlzdz9FKRMpemAbV6QPpRZxYC +BOvLWuW+OnTFDwkW7OY17/EiNHfSTQ8u7Uq4vE2aT3+06p/PefdJYo0SsU/eVD5V +kk7li9Plezs14Ft8AhE3HZbzJYp81zavdcC3TayRL5ROtCtar5K7AJZPS8SEdnA1 +9OUT+g2ZH1uBmTCbww/VtSAbyb95u44CxhThWPRlnKbb6Zhd9eztzRC8TqaSFko8 +RXA0qO1++hjxx+wa9azrsdyMadgjDNoyoS8AMsqp+ulYEriJdvqt656c/c9syXT1 ++bF1NZ69q04f9e3eliByxzNpJmfGr+UgMHq38BYoHOBR9el9tlLNtaWub8a/3Jbx +4zQRB5Iz9ak7j+gsEBm7sDGa3Ov6/nA8UL3mase2SxaXvVLmWyev6c4T1OPAgLy1 +XBpcK/fU2FRiRvO/haHwffuxSptkRYQNtNETanSjPFViSXRgutJXAMJMQN1EezFW +i+B6y4DOAyOBWuZEWz57KNRAeA9fvTU4QtenDmYLup78u0vtXBX8VG7AmgJActhA +8cFMc8oxaMfc/lWGPRAYAmNQ9TpFwuZ2zR010LA9pgi589xxtQ4RESxiQBzGO0bP +rtG/M05qrxaHbEEo3oiFV6JIvVZCaZIaoFFBtkSFc28Qja9HLE7oyMAn0Sxn6CxD +FDXghiez7m/QMaZ5xGbUesO5Kaqso3BoqLCiuyucJALgKedNzH2Mw6YWBry1Ry+2 +1czV/igf9fubXdVcBNbnMGRnoNtD7MhzrNzPLHbS63Ql0wAlMNkseXLnaBw7i2QL +rg+cQDl7dI6mWfBMbqRjVk8G0n7vHzX1YN30t/vJhkgRLARo/OBG837hOo1vsbpm +rx4vt5YIUxeSW+PuQssqqTqpaKij/4urttGNlr/qFUrKE+CbK9TF7AVBL1rXIMqZ +9ljcjpI17JO+HZcayfGoAj9k2V7nHp3fGMnWE43BT/7FU5h2M2KgOF8DekgN24F3 +ASPMQfpbmWgYrEulSO18Q8vWWyNjt/vWWkkrKBqkWPtNlI+tZCI/G/QtcPDLoQ+F +3RfKFHhdbUMxt8zXoSLszy7+GzbkGUqq42hYDVckA2M6ChvhG/d89oX5lyK43WOS +LEpGwLFCxpT7bPNaBiKfVehSaZoM1JqSPsbh9h+B8PWgH4CSqI8hQg+alBk8ZTt1 +ZulteF8TPK9HMTAAuP6GvfqQEGFgXC8d3/hUQ2ujD6r8st2nF1T0IZYanSweLamc +sLJVdZifnUbCVq3Wt1Ov6dpybpbAygaZ5Z6K37OcCrnjpztSTskK8oScZkNBfkyL +iTm5DzWTjlLHuDa1SlIpQivUXqwYUqpRb4arIZf75L9gOESAzELQfTSk+i+8gQfW +1NVMMSvD/kHm/xthV+8eOiJx/Qf6R6G+wZqZD22Gb1qxLK4DEASt3bZitMC5j2+x +w+XFr31d55eDWLZ6fL0L9haGjZzqt6zh53YFzZv6FqqBtVGpuqdOuiLhpgJw4tl/ +IwSRfOmGBChUaLtEQ5o09LUdKqD9DjnCHZ34CjY3MXavZ12KH0fiMeqVVizWWoji +2xYF1klJrgea7ZQXykCvaQyTb1GGQZngZ+NM/HpDVYqYsxfNlEfEf8zYyTTUN4MH +MQbeQzHfkC1k3aLrH0OCpA6vXFRbjc/ixZgpzRMvqdhuQavqEw06XG0RiBc187TP +gUdApmgq6cnZeyN4wYfMTNr9cG1iHtt4dbTf5Xc34T2UDPmc8KygE4J6A3/BOzXN +uK1DA8dx0UA1GWVi93/po3lxnWP/t3B+gBzdHK0PWO6Wm818Cd00HkQTzGy6r7Db +ejie+Z2krm5BJf37oyZzKVZupG0851MQ33SP1ZB7vT2xDTKraW40OpDYHi/aJXdB +je74G147+EUpbaqyJtN9Khh3Bm1JLm9PKQRnTQY6KOdBOWRjZ/n6IueswGtII1GE +1+H4QjqP2Yh/8Ao8RaakcXBetdZ7ijZ+XdzUiUx5Qmc7pIZkuuU1IpUd+Af8aMbz +KHqBcVAg+mbEI++iTtsS4rH68KU3WMp7cGNM+ZAcEVuL84amHwJW0XowW8/VlpoF +0szNkuVrPYcCMeU1YP4LTngfg7XrhEwit1xNIqSRcOPjR+Prdh8CV/aqhHiZxLBf +A+Do4Tc5XiBFE1byyP+aXItbFtVmja/eSIdFPgD3netgV2Ufys4ySvAjaomfpZ3e +JYckMrAVbRc06s437kYbJh59GYnCE/MVL7LbdgoinrVAnM8y2xSqqhi2ViXxcami +t03WpONtKtJYMzjLqd0NE0YnxCnO18Att2WiHZc9pfDjwcAPERG1AWiYkAaxdBcE +pDm/jhHtpf0tflOjCnRbm3JWO3q0g3kSB8If4UKevqtgYVjqarWtumh3xSLaaQki +ZkU9VXfxb97TsJZBygr2h4ACs+7uFjzozqkn4Hy2726A667VrqRnjvMAjeF3TCPJ +l6uwYrysGtT6HTsF5zY4FBn/zHin2GocmvCnK7hv2wdCH7yodzaIyhn0Z+/0TO4X +0f4S6RMehtoihNHaY07fHwnhAe0FVgygDcDYtF1cbVgk5lB2rDOKubc9uqlg49Xm +BNZIVmTf/82HJPPDM+t8wKwagc/hLocq3ZC1hlUb7T4KjsKi8w6lz5nCSft6/ItE +53zsaRZRAJkbZELWS/b3WcL51wINach2iVTtqXMHkD2/v3F8qfawL8Q9eL3BfHfa +Nf8KIYUXcQGO1+hwmdhAq2LUGxfnstFk/5QraGzydDlhef8+V24qopHSsOQq2SS2 +SQbd86EfZRWmhY1Zk/ROUfeKlC5s/gcKT6dxqIHmeZ8QSKV13Aw6l3y7tIMD5z24 +oaT7bD11fVOPd4OaeLZvYI5gDJWmR03zH4QLklWP2tvtIFwWoeW8p8Q7wBmpddq7 +//pragma protect end_data_block +//pragma protect digest_block +B3TkFI+3N0Wc2L+4rgj86RNP7kM= +//pragma protect end_digest_block +//pragma protect end_protected + + +//pragma protect begin_protected +//pragma protect encrypt_agent="NCPROTECT" +//pragma protect encrypt_agent_info="Encrypted using API" +//pragma protect key_keyowner=Cadence Design Systems. +//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) +//pragma protect key_method=RSA +//pragma protect key_block +ANaeKJ7tSaIxxZfCymrxd1tPx/DBPXQg9P7ADT/kL709RAii9I85IereWkupiW6X +fY7mD+I0mTNaDYB55jD6uk/Tb/bYwk98jdHLh13Oiftml/rqOBjYa5s8RCFlCzqi +zH9uP6y6Poj227jCJTzfWZJaJIsGUpHvR3s+DzzFkDJQfleeW+f4VtylG3SgJckZ +b2s8xuNsNfcm1Drn1nYh8yX3AdzGbZ2UWhHYzDdqdLGLa1v8P0CGufu5lLcq1K2G +hjyMxuyqZ+cExm67cN7Y7GUi8gv/mX2r3ESjEZrKTWk9q9qQv1DcL+WaNoBn3I3T +nxFVy3bqck4R+XXscCf5qQ== +//pragma protect end_key_block +//pragma protect digest_block +qtP42qWnCaGHeHrx5eafulg95k4= +//pragma protect end_digest_block +//pragma protect data_block +loQKr+1WLUX7sLtHLOl2Sjgs3mXgrTbgd9xeSqHYlaBd1KrdhlYujcVXtr6WJdxY +o3zPy+a1ST8IZUbL/QYPlv8/SjwE7xXtcch29IaQ82xkVRK24NKTuXfafCFuMRrx +uRaAZirRXN4UEPtZs1aG/BSAvk/Ico+Vs7O0cdomS2SA+4mcMLdLap7vgFLVW1Jc +ZMVA7UZqNbm3tpIiW0SpSQx4fyIJ96yQJ/Fgby/g7tjGKqAhidkuS409iasvjzUR +cViQtPsnUed/UFbJJug5jcvd05U71Rf7xPlxq1oPAasVs5u8iFrwJ0t/xZ1FP7GX +Ql6GjLzue5RoyRzuArd+H0kbNjJkz9W69sI/2IkJAUVcwAfBSm+z6L6x0/xmP+jJ +3OXM7+X9+jWWOuqvwePuHqrtuVm8W7q4ZGm+rlaypiirpgMuD1bNQetdVo/BK17q +NedzcGNeCKqMPaE6e5RzfUhkqREnsilsEz+uqtjPvLf3AHNybjyntgDpNOxersZA +RKh9dpGDFaiGtAF7vxQHdNifzbjYa8EsUrB9WJs1gyF2ycpCHpSiGheUsJiyTi7V +fnZPKTwIxennbEXnTORQGcyagB3xyPTTRGPTiyHaCXZ/8lTNHcaGE4iLrYF3Mntw +xrHcvhGC1O5S6qCgRUiwbvOdrIVT5ImVz0nPoJfRol+C1u+sghO4Rns2r1o5QjLL +i0DNpDhP9W4OQhNu2ztYaCBVdRVl12WE24diSVgM6WSohAzZJMH8foxxNRKMLD33 +UE6QjTju1Hp9o8v7/pO5eahPQqyn0h/a6NcX0W8fDwL/gkNViCKa3KAQTPE5W5hP +EbVf/yEDMLihmICiWq2waqUwHCC408VB2E/QXrWLljtRKo984kN0zJwpHJdyUdPq +UaYfxVccbiDCAktoq1znf7ky6NWR5JXodW7l82x5sLjPoD8A/Wu/gRfeyRdqO7Kf +778gOAqzQDFrORy2R1XWfp3lY5MQkwHbH1pYHHifKvi5Sneh6gz6FXbJtQQtV2xO +yo0Xpbfo0JdRfFGQu9GYE78b42AeefL6vyLiChHr8/tsZBr8PFjmVBZoOeWxDrW/ +Igwt2nAvKma8SEtbeV0GFzsOvzPvlNy3tXUZg1//z0s7aaZKu1pOs9JrdalCyq7Z +EUeb9TEIep+br22PvI92EcYrFSpyz130wm74FLht21G760Qu3MqGrtw/NitItUeg +m16erFbwtjMQSalQ7da6eB6tmNCdCkF0ZagC/qo9kGD1Kr26Z/VVSsXztq+Cf/HJ +cNJbCjFiDDg9l/JwROk6LzZWHPi9x6sUkPPKEhrrLMhEO4zlvT5960bcd1ictT8l +esf+21BoPCS7Fb2GKFH4bCBNBrOThj3AoaGfw6frJCdz4ZeIBg2zHxvaGxz47Xb2 +u5vDpYmPBFdTreJrCWpqVfgi8RnXshTEaYxdZdHHXGiqr3N3Lx57FP+4kvHBn0X+ +oXtndv51PZLYt1J/3KTEoXrxfAaupr9gk7ycxjeiEk6zBH8hArn532OrTUMEOWf7 +zTh1cRH0kyLsWm6Vnpf0t+zZihNqOiauFET/Bti8pG9rkDqLoi6ioJMjyrRYQ8OJ +aS/dNi8J61OGWtsWjP0Z0DGP+v+sTahLXehwJT22Uq6Suw/JGNno2L5Kbgs9o1JN +e8sZ1HA8xw9jroT3jHMCNjU1YcKD09Ai+6eoH6cuqSgYdxIkyJ/4bczAHVsBgKL2 +0YxrNICXgzmYPa0N0l0l44cN706W2695Y1AFcD2sY+3W9tSvjnGsI7Z2/pBjlByi +1H3AFwPQeMs+AhN2Q8sz+ImGLF1rHyB0rIlD39isXpS1MVH9j2ZmxXRFVO+f+Dtu +IFYfqhE7T2IdvzctpXpYuk1Ub6QKpgGQje9/iceYWLhFIdYLVyld5LbjEmZh7jO8 +0uQBoRodBXcXd58dtFI1ffJGzUgMFNIOdv84Uk79si4C0onBAXJMBlYqvGPFP7wy +Kqkh+OTCTe52nk/b1f+ZCvhfzOL/6L62XR/MF8czO2xZOyXr0yJwPPhPuO5YOdyb +MRSzYHnxpwb1UPtIzimfKXOMD/RLk+MNcIWaTsGlsCz7zQn47nNTTkr6iBJsLWWz +YZLDK04BL6YOIY3N6GuTW+zHNzHr4vCSa2SP9H+gMnuAbvHjCIs0JlwnBGT616jh +hU4RbyDpJXvyxUQBKaPUVh6oGDaCutFTJc/iq/gnVwZOLQKG95dLsa349RjJZ9+r +dzYb7Z6y77+dRJ6ZoJJ9Jf3c/fEp5yg6xUvvAJiqFm2Ico9WKjUi5Z10U5bY+/O8 +qwEYx1d9wEBbliWBADQrKOZTltRsReRfPgdLAvnebb1Wip0aLSXAT3IrA8ugAA1N +TZ7h1VC/kNRm1FlNATFX/yYEjC6eFH1HCuDolm4huH7QCF+dNXt0kPkQGr7ZpZ2R +UMUMwYxlCD2cSSSu/+WbdSLcSlpSTBOizj4D0mpd7xwF58X8nYT6vG53Yxg2Mjy6 +H3AitX1LstUzigQRjGPabr89/C8hrg+aRjJH6nrGbDf3CeaFpRwkkMBFwQtHrgU7 +c+EoIxYJ1IU05dYtXSEte8K0yMOaiMB/rYqi3ZvuEg3FNEfV1Zms8SNELeFEdVDX +jSLA5viYkNgIDsLZJWdgPOEzLxC8wek4XSujYzStgn/19Mgce6tDjYz9FrhKNYCL +Xopy6qYzn4c2BlyNLXqokApSI9iqEIaR31N0gov/a74cCzpp6uFP3e4RuIOnnxKc +4599eBtoJnpXA2AHSAhKamdz5Q4nRet8l/YvGGBLV2kR9hfvy6Bc57IQsYztz+Ut +8vl5rthXt2i7iD2Z1RsWs+qCoR0XPTCKnAwsH6Q1RnCHgPr/VDRmGAw1lH+a2j6Z +73nLSz91AWf49WqXF0m5N3C8uzQK4slp8+oIFW+xEjiY9psGmhQIRX4+/720cV+r +xfMfrTiRP3j9A2C5QbRtqJCpsnRA0FP7e1l/YZuRP1hyBfj3M2dOnheepNFs8izn +VGwwt2eSBMhepatnZyW7pcMGTJD0pqy6DMxDXGSrovMqA0oF/GsBt6mjC2tWClgC +s0BHXBARFwCj69z46UYGDVTUrpsf/YU19UIYy8YrPS2mr1z7iNvoZhtHPiysBs9m +jLBH4A732nqRvP8zgccCw3WnSP5yvNOaGg4PF251HFbLJKJxz4Sbyii+gc1Kqt4/ +gp9IPdgSZTaNLv7QgbS3GaGFys/NksxjKpyM8Q04SCzq10SV9pP2lp5YuE5btwP3 +WL019rHOscNsgmm2/Mh1oKRw4pcJk0uIV6MOyIfCSFtR6CMvq8CMF8IjyhU6cod0 +g4r0nGT03I2jxjDIjUyGvAyI51LWqnNQtYuWVitfwB0LGpBiH5wNUrU4qFJOEFsH +qQanutCM1sAAie3+NQ8Y427bYik63VZmBag4/6NM13Pc7gxvwQJKXuTIr9ZuW0lX +l7JXzuWkgsy84JvU4OZlmv/NhCyTZgd80kz/Cj/RV+sGWq0L2QQZmaFitSs1a9hC +FYdVVkL2HyvXU5h9eZpD2PfMgpnQmNTHyCtMMrQyezNafDHZTI+ZcKsMmirFCpeQ +G5ejqUcuErSt4O5wVoCloyUinRLs8reyDVqldo3lxFphUFzlj3Ha1YEvq4vtCc09 +YvXJieWwNtqvfz0CANVP9DfqVFLfOizjmO98UF9JuAwIwFc24uw57Ksm/J1Z0NoN +iMnAk9CzB9a+u+bknFXJl2jGfgGZ/ESvlNvd0RRtiDF2LKo/VWW4DXbVUOzZ8KUM +TE15ONiMdonq/t0Mgv0S2+Y4gK9FAdhl7G+7tI5a/JHXovcOe+XXFTqy9ANxFl8H +l3J+PMlxQIGZkx1w/AKzQR+W33U5CAKPJ51C0MUitcZVK0kcN5rdA9LKBVBLcGNb +3g3FmBBkQfwmQr2x8uQmhxP2O3dJV/tpZWEehh6RfPfHgjHuBkvcm7azcykur6DO +6ZdZC99FWNwVVmW1t3bNSPQjV0CYIK/Ilf/W1HH1JT61KqqsVfkEpQW24KGFZcTV +y5Fl1QRom8euOZKFobTeTEDplcfiO8e0cx4Da+Q+/61VS6oftla+ZnzEagV3EPbE +iO6Tr51vhBseiGE/ihquVdV/eHLRfv8ByI0t6EhkQpGUZPf/cY0lf5Td5XAENeg0 +pTBs8YSbtaelDjAXdL/beP6rd8P+BPWaCme7CKUs/Ciie02jOJM4hHtdbombnWFj +2WUawxCdB5fjLfNWgqdSmnHTudv5S6EW4c0QkOUR+xQX55oNDZoLudncaUbfFS3d +hlhK6CaDhBOapDwV5bebIRyvop64Rjp2JeloGCCZYf580lp1IiJqBhTWY1+mW0RV +CKtvDw95LOQE9PMfIcwsfhtORt5kaKL9MVzaDf+W8/HhOB8RvvMH7RkJLozkpZHi +5kY0E3/dmoim3pkr8Rimr/FQgsnYwaL/TIHaidaDM79p1fiVjJjJCgQqSZm9ncQD +irL1waHJ+l6m1/oEB0In+6e/3nsESCC/z8UC3P6N7YR+d8jlpidY9DR96uOFsbZC +XZG5Y5IQE8wB4Uw7wTPp5pv/jFmxB6NRy+5nAjtqrVfnp41fnMMu+DR/052NZz9P +Ugy4lbsmL0pdpFiukeMSLK1FLMWjcsFdi2p8w9YQ2pjzbHW0CtZhAqdhOGXRjdIZ +O3jCU62r78mos9r8REgxTLZysDljLpeyhybzUG8MsSvxd1NJt9E/f531gectx0G0 +xIKNgclv8YYVkx7TnIB8LykvQ5y1XXolyDWLGa7HRqvZd5c0AiKnsEoxMAuhyN++ +m31azd31CpJgtLryVPckl1for2TGHR2oTl1nmWfNRgUG7oy1W78ehVyc583AC+bI +LV8cQIkVjfKzGCtUn8zCtHBXlFvjhkW4wbUJlCvdsczXTW9DNwgvsLnbWBZVRCm5 +cPIL7+Utgpd/sLZuvkCggB5hx5uo0UVQRQSFXdZgz9D9I+7jGVzk4EnPoRMLNqSE +4aWaIZlDT5HQnYnwetCRc0gvqMjy673vHPotKJuRD/wZ78xkMSnBiyYRPlhvStbz +Mt81oME4O0fTIKtRywHVYYCHsMq7qopEZpsx2A/zGqn+xNh+qA1g67WUGhe8cUFt +J/aBvMud8uE6ACiNWQ0Tz1QF1PWXDpjVsfSmsZKi4GfHyWvUNU0/U60vY7fZD8hC +Ozedll/lMhl81myOQHx1L+JFgLPZPuhGOgwxUrt+mBxe5+xVbkGquAS7rbEfrK4C +mai6kB3wfkHAgUUjemYL0xShVJHi2wXoEvGWp0nhdkaG3LgIw8A/VUSeAK2X/Xkm +nDIsCMCSYflHz5zS9IJviEl7SXy6xnZ4Ae3c4f8JDk9/ucggcPf+wXqLjrpfXe0Z +KlaVvVpXs77qKCfM91YXHp8JA4edoREHH2zd4PwmkNb972ZvMkGPZzNkfddGRNlb +poD/xY3S0j367pqluyKzeded18jLMeflL3ZXhoUwntjGnQ4sYHl89vlzSufJgpd2 +YmCOxpQ/k1DGN3PkwJ4xiHAsgEwjgJ/dQ05DxciBvth8yJdOWSYRvbMv6KGrD/EV +DAV3Ji9xRAjufDEptXBAPt+NPKM/WEqPVQ/VgqnyCskn3MbLhciUW4kiF7zD10yx +fvJXRFhV7S+jJxPeYP1/e909HacxzMtwAUlVyFd0SjLV+q0YfAxnzfxiaI+guodm +qnc0Yl5UHoD/xvxRpAw4uuOn2qBwwN0xeMugsOgt0ZJOI5Se6I1xJwRlHqiRxxdJ +IEb5t8GfNVnQu1dqanQKhltfJItgiHDSOh169/wGIYofSbIyWXCK5rnaBHyMPxU2 +Y39uy3j4hVb2Q4Qwc1VBdVdFLGdshvs2E8OD7ZWlwQoBRdcUj04oSGRHoYZxClWH +dIaRNRj7GW6M6RiiV1TvHqsON34HPcfmpAzRGuuVVBETzy9Az2b5LaaoRTceXRGv +wjPtUGltIekw5rnYfMqGywKs/gtP7NQR2BPw8WBgkDtTp8Ey+VdPW7EcK+jbVHtY +qpMecKv49EvhuKKXJutcybOiMDjJCdkwY2ZUZ7hKAzGeK3vNMyM+q7gbBhAXyJa7 +el7kQvV8EcQlarnN+QJHeOQ7wL0f7IVrrUMskDd3yePypAQMxSX2nkUsaCdK6PdL +Z0wXrsyvCnC+wrbqg7NR5h5X6tR9TGT6fx73Q36F60X8YjpupO1ye/Ikba3XxkrX +k6Fl3bS/P8jVxhORV986WzxFbWmMqhkdOKnboJ65lL58r8YkbUKfV/VSalsaSTL5 +/vSkWzxzrqq4O61mOXI0xnTa5wsUo2UtyfRABO3twUPYQt1LBTVEy5CSidR0CgHH +9jiPiWobNbglamRrHGcDgPgVcNObiTrrY2TkUCdTRvgi2Wfu5Ox3W/4hq3lHFnAc +Pg7g1bxtePd5WoYC2PxJXwBCulGVE0PBEJAcyRmUO6YmZx3X58+eikEMuBD0pEaG +1doUuSV84JLpuvNT0PbjWktSyyGpj/HDnJfZEnBvuwZK8ucp/82Fpegjw0Co3OdA +ms9OTopdfQF+4alYUfzEW6jFlwZathjW8KWD4WI7V13aQOvyHGgpJeGCOjtgga2F +tev9fs6eJqiAdhdb4jtlGYAxEkcD4/9nI80kJxZ5KzZJWcN6XB2mhEBgs6NZD6E/ +UZQwYZG+g+Qa3/dY6k6C5qkFw3W+dBOEHUDqENDHMx0VeOInuuufaw9ngD6RHbBd +BXsj9dL3klrKYk+5/2n13/9zr/tgO3e5tQE4OoUVu0LEJtNShrAx0GuPEyXqt2UA +ufJckKFf3dX7tfxF6BmaZcw2OaL/cth2VO+llfNenEiR+xOYT+h1j6eCJr30trEO +Y+mP1to64CBVzTMT0hwLIONLn3V2N6Dk4HT9szozmKzLg3h4YtIZz9fdPDgTqRQx +AYQc4Fa6Vr5bJbfZtYv3/eVuUj9pvQo5IW/5SDoH8ab4L2RLpzkjtDWd6lKjhHTz +RuxYkNnygBWS2PIk+olXRPzeiWOI6jK0rjhrfR7Z16tkj7gSI0RSbz423ojicJ5r +DAmwv8OtqDhCS2yHWycDs7i6B08gPZCZHFdfpqFqsHa7UyiTElV/8EyFDkne3+69 +PopeZ1bhnY7JU+SzzCM+jWgZvtX/87R1Ui6KbQ7PrtzZlazERzlmLWBxQLlm1aTn +r7UUIHdemWKep7XrAc0pe1BgRg7LFT7a34+p6HsddBo2KvapvbG2n6z8zE//8A+a +Ic6wuZ1KjeqNpUUp5fkTdmM5LDCGGbp4X1AUw3RPe0fweJb6V3s3ekNvL505Bq0W +KnDg5J+hPpth+zitROfWHMGEeC27Qm3kVTKOB3H5Dl8tXcn9a9H3kqNqy6ONzJ16 +vNP8SpW3ZnhQWqGKST80UMbwXpw4Bds97EavuPLsVSdncOICUbXLh3tPQt8NaJiR +qxusSKm9I2Zc5q7rG77sVyVxnXVx022GTuAFetUHHbrt+rO7NVSEtKIhBDvl2ydj +oIIUQglYuVntAbhg1jYvLqBIAezNc7wWiQ/C2IBHbXLGS72lZ8jG7HaLgRVFZYkd +2Qxf8Sgw+boM+enus/QHOfqkrY7aDLGdmzNHdsyvbQP8dySESRfIhHuHmqzubhvO +yuGkcYlCLsjWkPui2x1XLnBn6IDUzMGEqX/pFmVUdfp2Otn7DRdNz/IWCTT4J7f8 +rYMV0crzIW2eH5y2pjkhPoXcg+7nBzvIS/JTTDtZFCxs+c/liW6Pl4oupZN4dCLk +sqdtNT02OdcSEa5jET547pA4cgV5oqg2+Z6KubJVTOAwJv+khCiCDmwDHrD/Qbb8 +GyHDSj6JJWnSCX10iWGPQCmCNawfaKTJpFRNhVGg3TJKN8vP9+ITraYre1b6hpk8 +8Ol1ypEbLsOMehOH5GwpIK1RsrJ0s3gjF0Uk2Gbm9/X2z2LS1/Y70bQyTZlZHt7a +doXf3yZ6NIbhN+BvtPfp/vdJi4R1vFgdYXm6WBoiD3wrL72pTahAbAOMWiHG1vGX +filAQtTSri4Yfi9E8SiV3DccfEZHwalDNTiP+gw/i0T/QhrXDRFC2qC7YcmXLMtF +aWd4sOcxdCdFcEuxmsQ2w6A76KtIKso6bba4EVd/REdDZYTSLuJt0HVOT3yJCMIo +11WImwpUDNkIffsYfrA6Oc2ue4QVPu3zQw04m7+M00OyjUKBlbFaG/7/UHCR765W +JhnqiK4S771YwkQ86D3Oxc5e7Th4DpfiyStY30+mIBP3GoNMNAuUHCB2ZkkQ4E1v +Z9aW5viMeTLbXrBYkA+XlIis6VNdAY4bSWrTULIIV48O0lAV8E2LygBYNZcYcIaA +zn0BAGaYkzAIikEUR2pwd+UiKIBfavX0+AXBHgTzDL7vVYAVXLBx3JlZTeDWojah +QjQP0J6kR7z05F08WxPlgHMPtMXYGXBQ2iy9iOlXTKhjghQxkQoHALULy6dl/IlM +M4M1ML9zwVUKsAOhyy8du7Q3K+ye1QkMudxmKN9bzpoAGuzz06CVZRpGJ9jcGmzs +c8MTOrSHwx+q6t3jixxghVvVOwWHV0vcysEy4c4hz+zrjo1Q+Na7sq+sfCqnnP1Z +RPnJLZTDLAu7lh4XnTnT2XCN7n3W3Ft3dF2JKyaj6gME/26W9sT/2o6jkZhDliPG +3AL08E8xhO4FbCp/LJosVFtD/+6FZI26GWPlHTfXl2ACK88F2V7/TjqV8HHeh0pc +h+O69nfVRBw6q/xOQ33SooaCdD0J51EFcWgy0yaJi7U5epohP7PlW5iUpwU28OUp +POlTY1oShJBfJ+oz8JCichGRs2ebe+3+y6uqhQMv5oQimNmGrjA78lRJKhp4sx5b +AmyAsQ/erl2ucAN4ul27dKK1/JI6s8WLozZczqyjmp4ZpBegqVn7LTp6xNUzLm8A +BtS48X39x6np6UD2Aa7mgNugv4pL9AWWcLk4ZeS55CzMi6O7oRIkGy863j4sPeI/ +3PGFqzxWrSXk2GK2cLfqpsy9dOWKlPnvDnAuX5vxs2vx3/BCC2uDadUKh5Vx/sbl +/MHC1F45a0SPZVg5mDYjo8rRq/kVpXhl9s/WSf7RHEvgyUjkdzuGeMXeOsq3BWsP +5SAzWxIk8e9vcuXfRLGC5Ug89hP1ep7/FJFDHkIqtzMztIwPZDgn6lA6+rZDRrd4 +FyfdX1x2BMKwYr6jY6qN5SxjKACKSV7nIaDrtMMANBoiYe85qef6bSCHGmV36Cts +R/Om7RR8bUgk7IIO2Q3bGpo3W6I4YJFj3W/1lmlLPJEAxsXdTuLdi+lDd5ENohRH +IuqZl4jG/bwvNHng1qqqZxuJKgk6iNa/l3GaPZiarkGShi8/4Ld2fSGQFbb5FFX3 +dai0Av2VHeUQjckD3onxV+NZ1cwmymqbWvbfZoqpY9HDo4oQNLfpjqJJO1MFlgv+ +q9C7gJGWdXyo4GBbtYNGkMBimTjET5LR6Tx0kM8/8ywZ/89rXE1wZYGlYygnfOz5 +NdG0s6usGA+8FtMPVO/6H1+NwsEWfRlOXG9iIn3QBWkdLjMMuOub4KUwjY/E1Pjp +1trx6LfjecXWmwqGLgv5dGHvWyGM8K2yEgBQHJQgviswxkPdFffqH5DqWN1/7ndd +XJ5RxnjAb9nppZ6/kWrOoxcFi8thb5QmYSOFtdf9LLfv/Hd1T8Q1j/0jA5ak644O +LER+ua0U+rB+PDX1+6I3drar+ox+qVm5Y9qT0FRnyvcU+OsfQteb2B1zcxmqpSZK +RCTok7Ny5r1+ngb/ZGsvoDRh0cBpi2sV4bE+XFUYREWKC4tYryVcIrUqvO27z4I2 +lto5daLj0SuqaCJEwUBuefstCYxZpAwhhZkVta35q7XqP1vUL0HduAvkHguWrOZy +H+8jJpS3IUmskgKs7BrjOsglQIAmMn/6+rCcBF82KXKLRRKSkOkJAHzSruvB3X+i +E6DCktrPiqJpzuOZv+tHUsPhHwcuT8wQherJcusU51+wZoPEzFcRjVOn2C4J524e +HdZ2ukcCDxaGC3wW69/I7fL0IicKcvdFBFjpQkuqh4W3VhTQqmNQEueIC2Iiw5jv +JkZTeBotVUQEXxZXxpheKmym6rczMZ0+6zDVjkGEHNOFzCSwBCWC2sB9vQIjJCZW +/5UFn0VgViecflWG3R0wm4N8YFtzR//6UObkM6bAdXV1QEdO8YBRaeY7vg5RRq7m +oAt7E7T4RDDKk1cNDZsjYn0KbLHyNe6PXayHbkRxDd6HS+ix1lr3+IISJdPWfERm +OZVQtYxe1VSdPee2xJbXE6OOpOo9OrI1XiPeF2pAhtPX/F+VDXxD9pvm0Ngz2Xhh +m5gSpT9eIOqTpGHeX9Li+qwO9zBEZRciM//hzEZjhuxyekhUTlr8YEbS95HFgpcJ +oHLtCEtEEbwH4Cc+WAkdfA+oDrswSteYos4kxr9AgTsHcPXqa3fL5FwxCp0wpsSH +hPSUIhCd+XheHnTJwzUX496bKwF2zpIGn9U3zEjv8SubbbCn2PXGdXaBL5jAE2fZ +xPE98weR4fYnK0flD902oEsrwj2YNUKGFouDDkJcBU+nWcxpyfSomNrHeU9768mY +Bmy0zKI9IASL3D9fVHOJOkbQfnzxZUoVrV1y/4IxLsS436aIgHqZNTf6hm33Q/+D +0ohHGxbwQ2xfdh2FAj9GXaWfIT1Z+3dtVdudX349nq16zIcf6lStnQVLMiFt7SB3 +Qzx94ihgQkip3Y4p4mlSyWexcETFzN7BFXelpP56r1E+64JOGfIZrvu0HSXegyUt +BHWvDMxHp8LUU3QpNnpYdUoUrhH7BIdicRBuazWDcecr3rtdCkhdiHsgHdUhw24T +QE223ZbBPvU2+6PgJQ5suvo7ikamO2RYEPZbmbsF09Z8xarirtKKsfCQG4leI/ct +P5MU7/FAv43GlbdKb53NafJCiVhbWTIJ4DT9ExpAoENNQnYCkUgXGeu1pXzRmuAk +iB/pgJ9O9yQ3YYF8D9TyxJC/hr/nuXi7L4AFFaGvUaBfwrxEjtlJ4b/w4cjbBUTI +iqhQhh7z2xsRhrPgauqgFwQv7UM3/zM2310OgrA4/0G5zdWZDiz+U2j5kN0yh0t6 +JP3q2j1D37e4LalpBQEDULv6+zQ0dmkwDdb4aepDmuMeW37fRoBIp+vBRjg5RJIE +EdlQLHs6kPVOosHpCyPbdDcBWngXA6tgF3nrmtsqJHKx0sUDQjwEFrqhf7KFdnwd +wE6pxud4EujosTYPpkTbz9FI86/qEAQhPTK/3bIyMr+V0rINX1sXGTYn/N7gLnJy +qmxLqW+ZjhZsjB91G5QHyRsqOOs1pQt/A6l1ziWleDE4xtIEbPVYNxsWm2OMZBS/ +S2obZdwg3sNnW8/n51vDKihl/UJptSRng+x12vexYX+76g8b5pO2PMh8KwrF8flY +PCs2H3NGuJHoZZ+4ak8QJYXGmHCqPl1Ix7GXwDjvIPyL9amJV+6tLgNS3LXnQJt1 +ufMtVENfHz1viP3N4VzbcwPuiNFLnFIxpgN42kZmbfOGsok2w8+84YByXFtc2cRn +i/OeP2QDJS4irs0a69CINDwlRf/3IdRqQiaEivaOTelwobMlsdpSYPHYjHum+L4y +OyM0XPPG3l/P+K6sbnrRbPhyFa2PCE5Zicfr7KYa34mjszWPRVcrfY7CJbYNjmjs +vXKU5jLqQxhIIUe4gQlcm+xc/yKS47Hg/kvTcXK+Z5RqrJ0ZUehl/5MLGMXDsjrX +8GvHcIN30sCD3c2ywgIdLQa/dnhCR1ocBgXSweRToef4ZnZ0c0dstefPxJbZPOwE +E4trCYP2OIc+P0GulwaYq+CX1DrLsJPWxX6ygZ7fjS5C2HVcJozo0LZXym3iq78o +LTFSiU7kalWkZ8NU1fSfhPvsgimJOQ6dYVFMTHQx45XpWRiwn+OCMrUhSUFPQ4WT +p2bobED1CxWr6WjawFoz3AqOfmIJbgz7AAdODYbFWLkaneOwz8BUtrMwEL/69Jij +zhGO2GwUtSDazYVAx1rcois1jnmY8dMFKi6wvh/CCCRhAzOZq/4kcR4o0jYDj9k3 +Rb/OU+onuP8hWIW7pLKkhF6Hql6wCQbxaue213fhxpQbU9OM63fFyvlLjjVvqO/7 +LnZuzQMpYbgqZngqaCd5SfBSg9BoQwRr4Oeg8ZeNgAWmFsi5UUWOXh/Cq5jqiDzr +DlH8TCIOu2YtxnofJpkXTjetHKNBtKqgmTMfhtPDIP6UrUJhP5ef6IK9OuIM6JEU +I70CXNBR+cPN30hpvVCGUSGJuR3Xthtq3Z9jZHBOlE//vVwW1jh4BrN6w3C8ABMn +MoZXYcI4qpa0N/Pj+/fv61kXQw12qFwnxDwaRcZKUD7Ovqt1w5E4kVCamNJXa1Bn +P1gznI9BWrvUkw6akjmyvYeDunyE1WEATh09+msP2RNfK6nYQfYFkPqjk9L6yWbA +hIu108o/WYRDzNRASF5bf8+oqFGZSRikZf0HdHhAVYqorZ8y4c76q8PHVsntY9se +U28/SdrpZtiIACfo3y8I4w+ljzh2F0KLhhi/6la8Ky7j0a91n9FHJwc5A0xp6yF9 +Fo1ufbhfj/wTZPJ/GGFy2vEFm7FzIxkNqV6GoZCT4Di5z8pkLCQS0tRJALuNl4Xj +OOq1KUHBarrY6WPR/7Rvs/iHuSnwmRvMl3tlsh0NrPTIpz4ZcLHEMk8irE7XVGK1 +CUWpR6OmHgnkzYXtgxonS7PCResdeNV8NaX4BqQ+susiCklw8ETrzGIySL6GBGJN +c5/hpLu9Qtq/MTlY4p/xMUkbrCBAhF9uIgK2On1pkUBZsC7BYLpztRoBw5F5N4rX +pUcH16sx1/5w6JUKPCHf2cV0iM+cd8bOfH5MabKOtoriZq3imxolGQqriPx1OKrl +YYlu2IQMRT6I75/JY3M8DvQI+K11mB98C+pz3qsPPRnKJnMSykEkwEkI36LVpr69 +ozZCL0x4KR7Pwx1dRLvZWrCbvTTlDXuSOMu46/LfLAdB9IvICi7o07nj4tBTXAfJ +uGFjk0n3Ob3yheE7euT5YgfItXvUnPPcswszgL2Gu5lSDoor0ksAIJSIl1s6KbBz +QmP8sDcx7g/4nPHyUGXoHy5xrj9bdYqf+3bWRqNZfJxTYlU8PtCM/U35dBVJTHB0 +yWpEmcUSabk2ucC6AzsmJj0eZI8t4aXeQzmhe2PBKTB+y+yMH9iewCkFZS+G7kn8 +n4YkoZBOgC/VBYFw3RxnZGiOnqixHhCEUTAu2YeiVJTEioiG5Zft9/jbEQa5lTmp +PadiyhFWDBQ9Li6DxZrx06BpNG0Edn3MALmu1rDIqih8YWVoLwkuQnitL0klTRrC +Ru4ok2Ocz22sj27NCq8T+PVJbxv48nkc+tVG2FYzz/WtW1TTV3wclKoHAz+tOGGm +IweR+GFnC73RtEGcV7tTou9vOnLnYrexWiuEloqiL0B2REuM893h7siLsoTRLHiE +4r5XXL+n8b7q6wjQxYi19qwgsoMDQrtwZstjnzJnmpdI7T+hJeCSCsZHVFOuST0q +l250aixYgE1tTyrwbH8QV5XwBBOQPvwNDs4ek8QzMjWDboKe3aSuetSxk/okURxQ +OKG77VmKIYhL/zbyUgRsiVSkxlUiuCP6rdkE2Re/RkX+X9X2ISrnLGBnFUki13xv +rG4daacN4tPIKefII9qe9NxAdlrUIEsFL9S3p3NO0LaZGMzUc0EhTf5QX5xgtXJS +l6+S4Yj7LlULzfIxJHPzjqhNxiA7SxUyYfnRCmF6YH1QV9rvu5GwxRqVn3kHoLU0 +NY3kDVQOTIxJP4GX2vA8Cfu2LDLGlxqYVmeHuGnE3/lRPo14ZhN+tHAdKkGItKcN +FDg2+itFkrHO9dllJKlRfFwjvBwr8nOmUh4v2k273s1O3fJGAu5DEX+VQ79k+oTI +CKF+4nh0aNMiM39MqQNxmfCmwPetcwiDvqIHAtKhkjpSt/hDBKyagfnsAJmxFIxL +vUvbAW9xnZa2+GE8FV1dmFhBKTsMIhwHBW39XAuNpXp/1r1iWi5sxuQCSY85S0ap +d8fUsClp0ZztPVgtiJvkLMyhhDeKLTpbnabyDV8p5slJ7ZMUtceZsuRXfD6+1iVy +WTsmu6Q7J+Ntp2OUKFyMwhboehF3bMJio0VpgXaIFsc9yKeKqkTEShDN75wggKDP +g0ynrYUL8Y9WPNxUwNywyDDi0crVJi3Ofeh+AdE2kkt4BrjUv1zA933ePUd369O0 +yOWL89X0R75Pm+e+NZJlEjUgNs+peb0GqMkhJEEO1NsVHwMlixOQPEMnzJyJwuq6 +2W5HnyQ9BLlxMRcVPNEBxSkxqy50mCbuwGvFaa+b4g9KYd28lnYA51JzxslmI7z9 +/t3dTSnrx+0R2ESVoTzt3aMpPMwJAxMjO7NThG2BlvRTrGgLu9s5tIizdKcPHPnG +QplavdKPvjjKQsZG2NW4n1aQ857I+3/NKcPi0JAj0n7YZQYkvqGiaD0me49wTHa6 +XBEJFWHp04xE1/Vs4appJZN2pP3BOj6/UXR3HCeM+2DF1Tq645K9Ut6Ypj04VANO +wkRHKTVDil/ALqJt5jYVjwqMlbVEtER7fL/8jXYtergY06L/nWSLW0gVsT29oceh +Z9NeECNh89qwin7yUApuYT50Mz3yiZAY22cFq7AkQLip6fIfiUWxBRLMLN9nJshB +bFdLO7TIV2e/QP74UaBDoiVuhNOjJvx/UEtm9aFF6Sfig8GKNikdy5JoHhegb4rK +OgQCtDqMflQdhSY6KeEMbRoWIgBzdDx5XWwrAcpYmXjibqczCmlk+HyhdqI/GTeX ++A7Mm4jKipiuja29WBmkj8wbo+eIUKQvDdaXXTto7xiFB7q7HK5+hkukrZwvP/uT +oQXtjTl5lCYw5PhG/d6duXGGyuaYYFZimbXQMrRyFFJCe0jgcR4UCI/oosajxkmO +GJjkUe8X5kQjBqyXBY8tXkQjSt6r7LjjBem6BySsthfaP6j28x+Qh1MnZC0Q5yet +ZSkh8KCdjbtteiyMsi5T8in3VJyHax9iMV+s788dAF60vQ3HHxOcH6NOfvKGFv7z +/VB7/M2azLK/GsMYmPUEDyJvE1BOw/S4VuTRDlm99Um19o2mFAmBppREgvgBd24w +UFTU8QmhS2DzkzGuyjjrDCEO/GpLPyyUrI0xWem0XQPrlAThxFRdrw5wBqVu6bh7 +XZpQRimgMz5V1Bz75FVvrvbErE9kJlK9y/KBJ66nN6XfY4P5OEBgw/s0aDs+ZLvS +d9UwjkjVBIBJNPQv8P+SL5v8A5PqH04qR0YxeB7AhpLEc2G+telQSgo9mQkAGQlM +qaOZAP9LkdLxD5CeFYDUwmusfkZTZ6PKphAeMsEAcvinW8tl6JzAOGbEZYs5CBnb +PHSvTkhuFFiFlXmFWw8p3zKTXIVr+wVXivYdgua1DCE4v5IJyflE5+AezE93vg+z +BA9eie221LzIrLxLAR9UQXXBp1aIBdCQTtwksMVmC8BKXgIz2NA6axb0dEWKrP2p +ALhIY4sNt4l/fD/JcJW/XeMBVliSETo55gpEIR/9BNb5H/tVNnWJ3a2Btl98oinv +BxqZvtRoGKXSmah+T2CYkvM5Yl1eR61e2AeNEmMWzcXe1Kju9K6l1pjcWsbQhJbr +K/JSdF7ncY+7I09qZ5kaoO9Yq7WXj6wo3rYmqVSIntx/GxvABV4jYdFt+2AB5HRO +1utkSjE6/YRotvzE9KvoHsGXsi3tTgruv8T92rqG7/P0N2yvkWU3Uimck4jiJFoS +hVs1wlYN4E3Ju5vlQh6aMJLvgHfuYw2WNUIlAa1aQIZPbYdeOs6NIGR8GzDprIsh +qcwITYsUMuuAwc0+dfmzgi2KoXguQdDxE/kIFhOVAHpnVWj4Sx4kKAgS2f/Loy12 +6pZ3nW4GvgOQty4LAZLs80yyuvpzUqwd/L7494PbFvLYCy8eOp+ycOglaWWMWVSK +fyNgfX2oKiNVZmFW7PesxwW0x5eckgRGwPPhjudji8iT3jIGEhyf/zRps+WOQqBX +DHZeEMaVX9nBUuqrs9pIDrmGjZkIrfuwob7PDRboIbn580ZbRvBbw8JR7mGyzZUQ +ykIGCVqJhmOfVKHUrVx31rR31aOXjBhwr2Wojq4pPPImfOSDjHND6Wyu8Quz8F1x +BmhXKzQAfRkeyq5PiQlEagwQ9n7HigRyPvEW+BpTIa0IWRztlT1mxIyEfvOY58tt +8W3nidghjVJTmsGn9QZwQeqhOXONKMsqMGOBB+NSz0At1rXVwWpYp9ThWsaAqs+J +UyGDVqyEdxzHgUWjLgm2wtiGyYZ/JAWmudtT7fgTLlD4Ixlhb/SUNKl2mNkW7cwY +K5aMklqhqMLkar2W1THco7t93DmLhhyyi/NdRMw452T+IL1kGolfnywshimCZNRk ++lrtTnbAIQPlDq6fOBGS84YOcQ1HHgvyAY1ZMllUn5eVFicTSfuaK4cQ9BQJCEcL ++PRCf3rh96NzQ5XBgQse8u6ceU8W5bXSGERvAultsNuVgNQlwf8x1wjQKcu7aHei +TK60bSQdD791Hyb50ntu/BhFGY/MIvZxPHgOmRQmcPzscVbu6ZMOqJvQRjfr5eAN +1ZlJsL7eGyRI8YTg+E3pAjELcrHlf1alHIo+DlgUjFyL1T8zUGEG8VQLr8FrC0dH +h03ULb9C7GDj5VEFBZYdyPwXuoR5BINm08aqtMR2TREADPQ2gQQ6g644IShwaw+w +JSGZJ63qm1tiu71KZzj+2xrTuju/kzRc+53PSPfAE8xUcF99oFpMJckZItf9xnoW +2W04+Cw5alBOSJyQ5SYrlh6ubKyVIrbD2B0tR1NSmtXzyw+BfokZhSrohDkYMrDR +ex7vtiG+sSGLOH1um+w5eaWXAi6GSf4f2ax3PurdlDOeI4XARcB1P1J/rK/7XkTQ +Krb8ooiFnuKJ22bZl9g1MmQf181qWnCd84i2g4a6e48I6cukxu8xn4jjZ4SUhN3B +gMHxO9pra/Sd3hz64oKZ0285gO5tYy4OuVWhifurfKgQmqPN5RRVvclcRF0PU0oh +Wi02jCoSijUGrokCb8IrPVoLOnQSYtMyBrTYKk8Rp3BfQeBSioFsumJFPaC8JMHh +66msZ78EAUBXLOjROYl9A1z9UK7o1sSBl+Wscc75jcjK1Au7fNLdCGWSB+eZlero +gylqCwqVkYMe6qBjc/9T/6gM+0IAms4+xuWhEeVDLA2BkFSWq6RrS1gHHWdM3Cuj +2H24UaAHC1h+DBv+He8qnvcmGweEg8pORkITwi6NaSuLYas1ndzlKv6BpstljysK +iU03jQAxUO9eNRzQpkyLEyOOg2JEvfp+PequhYMHR/x+I/dZokhnL/DolUuROnRr +bnO/jf/GQ04h0YNHC1MUOzkmHj8S2OpeGzkoNWkt45duIf1DfEyKLAUO8XE25Qwb +9ZtePo5RhCvVhC+sRknDdZbIm/LPka9Cep4egMTiMmpYPK9VOQxKMGMWPIDdyD1p +2rr2K84uUljhxlJhf+eqVPMTh8nT2CWfx4u/jW0Xa2WUhK4+egbW2JtuvimdtWTW +celEPASduaMCutqmjsOEPzIfMVI8VY8xEMFUXry8PblHO0SmfvWbyIrNqnml9EKB ++tF44wnJbOltNj6zF+D43fy5w5kSZo2z8tCZ8NzbiJIMxnVoaBdJWiFK9fWPDqYW +5X1go1gvWk1zv7FzUYPHbZF7bqcKYcEmw6BPt7q0PVu4A1xpEKVgZk2w1dF4JfRv +f/HB5J2ojVOyRh9rTrwXrzmCpvTaN8mQ4dbYRhPM9oUK4sKxb6t0vBRUYcy0AXna +nh11eEG4aQfFrhfgfIMCSfUMRnLPxl0gCIe8w2/dpboiW0ZO6Uc7N2L/nIViI++W +U6csJPD5bUbHQnw2NLkfwNMW7kHiTRuVO0f9JjO5B0Q4n6IfC29N4rcW72+2wSkM +3RBC3M0/NHrHe8jroA4qSytNRAVXu79on+MXmhKy6kSx/29S/s8Yr34y8jmVu6Bw +eoBhVpXi9AR9f4c1q77Gw0v0vN/g5eQeEc2xugXJHg/dVIRhTif5RHpVDOYcXSbl +WQ0aSRiJ8mBP9p2K1ojQiQOMLODhDtYzZMQULtSfp6Qtzu/6sLba3E2Fz4kO0P+1 +8+26lHKTWCJvIhy6CRgEtoZj96EmKD9w7B+8utY3CW52aJ1S/o48eqDrKZF9nRLH +M7fufkyxCjb9wyLpr49nvdx/qIFz0JPdZcA3xPIUdvwsoR/zpCgrNwnCcKu+KM/8 +IFMorDyT7gGaIAJchODf/OC7F2j+9E9WfrjQ4z4i3qLZP0dGGnwKi/Aww0Akx924 +fvJ1NQEMR9+2IS1yLlKNQHRnxMPXE3x6RyMFuIZjEWSL37/8rIV9mqKNFwzv39Se +YS4Fh+h0JvFD7Q3dfn/EC4EhPSIpNkBtB98OISRsQxQ0e3dZZUTMb98WUsMO8g9C +Vj8oVXjl6ZC/ZjkmevaQ2oZHXmKahddGzydt/4Spklo9s+iwZjkfFYtGT8R1p13K +XQXtQNTewYrd2VScFug2kyNEtEAipH8wPSjmNg+r2QuvR16Y+elEdsQfacdGmeI4 +kTsKPDGxCgLGCVW8Ov2bjZWDPILu3eMnZrj+ZEcl26qbHxQtag/zO1cTVLBXsIKz +bWAmKwnQIB/j1tJHTE1qdJX+UEbtSRdHnNlWtgjI1Nwn3bm+Pnl1Ji84RFSTnUXy +Habd+/brHkJIUxe46PojC01kaF7aJhwgg89QGcLuB10l0MJvMVW8Iaz/tDTBMVtL +P1lk7frRBH90gnN+fpDpJoGe3w2Kf2XJW6F9iy8wYnhlP9JJ3XKxVwaOBkJnO9NL +Gg61Y0PDoqaj15mqX1pZ57LzLx6ZzUsgsnj8MiYiyO1uyzRwKDCUlF8pwY8W32yh +vYjhXNXKzIVPcwgpdpf4xlNmwRuEyddo3poVidjwkpnRYYe5CrRkIXBEzlnq6BpB +COoCc6hS9vgPR+mFA2hWqiBWi9wGs1QdKr5sVWOHvOFwryzdcVJaS8HalQDNvdOL +0sVnE8rzMLBW5OCDSeVeneqZvmTVeh20RLyYXrO14TUpECkjjUkUJPyor85LDwdo +3sGmBXtD5ESqru8B/nCtahiEdWBev9p4xpfMwHLUBH/zrxdhhWGeLnRDs44CC9KW +xBhe01KuX6S9+BrvGSZdHoJTUgaSsiAucbo59sfoOPTyyTUB5FaRmsqCEH0K5FSI +LUSFHGCcF87X8vx4AyD+f9rekUQVG0B6RgmuSaWjd/yY6wAC6IxQf2KwbXwkMsKr +j6ybAsrzIfICjM54xwOIHIR7eiuotMVjlFwGAvZHyvMsEeA06jBlGpACrRyQ8HtX +H+n71RJOB9WZJwl2zDy0F4/OFaG+XPNPZT8Dgr6ot7qKxGPeqqy6bb0VchBY8BrH +UZjSjVRWeQg2TFSsUf9KivLvZ5lkFurTfojkxKqYLCVKaxsT7/+ZFeATpuic3l3L +LyDGRBRcTyj0jparyRea44DOr6Odz4pefusjRxWYRUE8VpVw7dYKpA3NgGMiF+rX +b6hmbUO46kSiYp/0Ei47nyeSby85PJSnuRv2bnSot/j+uAqhMtNp0hlDpLlqjq6u +2xtu1+nyilMCkl7Yeq294WvHKCpYBz2roy+mU6zX4WqaYNqlxThgZvG03+ncrB1m +sdymzzGmIND7WD//gSjVvWN3CXpV1/6e1iveKkltZVAWQtlbj51fY1gan4unnHrg +3oEN14cy/G/J1gh2bxw3MEeOvNxtju8INx213+XPrqs3+foaXSLM35sGKqUV9hzq +B0JfCg2m23wPmyUjdyQzP8XXwYHYdgJJ90fEWXigDu1GNsRvfqbH+O0paZ/55wLq +aGsXngtbthBSyOCl0Kq/BG7ev4Us5z4p2aS3HkyuH5PiKC2i3vBVBRqqnbuRhTlj +eBObR+JvEy/ebjuVMt+pDTJCZH7OYRMiTiT5w3Ik/5GQBw8LV1uoOVkp1FHOh4r4 +DPq3e5qLVC2R+kqc+mdi3YKGaQAfba96rbTmihNd9nVv1nKquSJ59L6z7INMCQ4t +oM6zkanp75I1XGj6vUJ+rMGyqbDy10Fhkrd0PBo1CUsXjXgj1HN1I/vHHaxm1Odl +l9ZsJyXnuzXsqf1u1fswkMgEEFgIyodljHiwhOsCIdvkD2rKwIzgqMjXG0YJH3Qt +pnmf1ofCPmg+MTmOoOQQyu/4H/zlGaFaZWbfmK/q2ppU4MNb50ryIA4pXG572Vh1 +4gXBIsaH6QrQtjS+r+agwBDCdexQBKAeS7xLPaKl26omIRtOr375Gh9WQYTET/oE +IHGW9eR59jx+Ts4dtn9dX2RcVIYcZwUh7w4dkY+HLvu8BZgiVoXxfzOUkrAeNojz +DY7vqAs2GDAz9I+/wyOy0moxhkC3/Q94vvQUyaLLTrHQduB3scmLWbrxoIA5OAEw +LmrrIC/eqsnSoBnA0b4wXQ+9+AqY8KwkYgo82gz+DX13eXX1Cx1I99pnYU5vcwWS +JVOk0sLG3Q1K74MRJeplCO1jZxX4GjQ+m47QZ+y4MkkLaHuq2Uu1m4Uh/DrHkgHY +0afHWB9anLPnUfG/iGdCjnRlEE9sSBI7c/hovjfAaPsjAgeAPUAtFsT9vC+MD1cZ +dCqJYAOc5Xr95LVGVQd1es5BiMvUHanKRqHWkm13guqq6AMOPShwakZl9XcGEMuS +98X3ir5aOFmwSQ4zl60VGxPuhFuSVtBUkImfjOLBGgkt1KvBB/nlEPKx85Do/GQC +pI6aG2b8nq7C7zmO/OGD0QqifQL43beCc7l4z35JATvy4R6Vc0J+n8+wqaJe85y6 +Ri68w5T7LwENam20EYbAxbNfiHbvXl9uQt4Y6qwCd59NARfJHQ8Rwweu2eOhVxKQ +OiVhzCmYJT/yevidCJDk3GiwVucSyFZzi0lct1J8QKgIhcqx8pTPp5voOx8mxDbW +7ItH7GwEPEacUfv9wPwpDF7iWM4sib2Opq0QaMnp1hJ62BMVQG1uS//chYBUyOAw +aH0kSief56Un7m4JusjYaEGJeOhijMZyGr5dOGVRYcBU+gCmzy/n6PkuO8yThyfV +srkZ4LsitJwlGzqFLJA8lIsE0vPsQZEj9Z6bYgQU0YuNw6fT+eR7NfXFeiXr6+aT +wiw7uxJagTPdYfdu9L572LaG/25xDe8N2NNx4ICz1dA3xphiV64iXTY9JjqXA5wT +vphLbmy298h2ao1PaDu51Jh6oxoKW5FBEqpL5LN7CpnM64Ztz1SHoksfjLUNjppz +zgefh5tRFxIKzs/vferAMEb3y+OEJbxWildlMPlAmXm/NdPoRKi+1iHojNRJS3dR +UobyARpUgjJthsGn/U0oy3BcX6gznYDOFr3m6DiF+G2KgC58osEwU6hzRkr5yFxO +boOHeIYJibzvGug4J37GFWoc9sZYEDr1K5jq/M5fA1nYyCHSUIOuE3rWCYV77ppa +zWCySZ59JmuIy0eBRCcz3JGK+dYdO5wSu3ooyGb5BamjITjz7eAj7hNVAE2W+4V8 +nIcgf0LP6bxHHA1cqBqO3xn3byrv8U1bDzptbh7htvwA1qzOAIDVrg7OV+wzDJlA +wGcpaRppigBFNrtb9Mio/JS1tKnhpjOjUY/Qs6qD4HKN37t0RnZxMdTqJa8SYXmE +quCSWgne8SlkvgZa3rrs6lekGQC9XgYfPCxH1U4vwgvepgst+OgAOmK0v1ngJ0tC +FhCPNXFEbvJ0EY5wUDcD48IOoet7T/QDerlfN+sqXjTMXTkXcWMEu6xMItZQFFij +A/vC/GMbaMJAn4pmpPBeAiVu1LERSo2AGVW+ddEbmlrQxtPbOGATKbjoS2AXo69T +oFkunskIvlvmdL+gdbGTaxVWuvaAImKjZC6M4+Enri/XPJQfZLZ8ONvmDj3NdH4N +kzr+cKg/hCwI00Fqfn3sFJ1KK6KsL5sY1kiHjp4NO9FkNT0qj8NafLDw3vTbAVwV +mdaY4HyNMXdsRRB/5H9EYzl87gvya5rfM5jmHXUQWxc6bnXyriHtdEeBbZKgQ2FX +K+b3hX5hyvN+HNPK4r0hQ/WTLjx1CHgXGPWY1jEGrboxFHekOe+BXX/cdY8vk5Fn +9QQ2GfHHuxkrdgpJ27Cy34a95vmCdJsZi8x+zayKTKxmBtuu3KkglH1A/6zy4ZRG +Qn98YGph9ShZergku2OaGfJTybn1s+bBeYCGWIBGtknG8pc/Y1+9RZzBxD/E24sw +VqpF7SAJ7Kl7iodSsci0rJzy2ezaLCyyC1/9ZtrcT+2/TIRyBAXtd4rVw4SvLAsR +m5Xo77FB0CIP6WaZyXif8AsoYPsClhqaaaeBcnbbhKl4nVZ26N/QJbTAtNmbk4MZ +5zwOutDLjrjEe3VWrKIOKtkjb1dW+ggf8v5/6LDmpFYFKBvePfEkrFUMDPh1t4CA +G1i5p71HOxbnf7kew+IK78BcsNtNyWyUa6ADRaykrWC9Irb8s8oV54TokSVuWFnO +2gKAhXuUsxe5ueQrKFzX5kLwfkqzB2ZsEPcmTwbacREx72yb6tKg8WKPf0r4vKK2 +7TLhLTk7zxCDocg03Yn4ANeIFM0i08iEJiWW8qod2YJ0HbY6Yv89EzufF2OP1yc4 +N2KFERFanozdDnCZDeLpkIEIpWBbAHM2o1lZ7K00oDqc2hvizxwBh6BiS12S+zHe +52esLkuhDowz2kIyxAaMDn0+pRwobBoPwrIvfndHZb1Nk3lgX1iFb0VVfGm7iUyr +V4ONwbfN19SJ1NKAiD3s5XVA7lU51PsHOhQJOakj2bMNiSm98bl/BSQSC8E+ji/C +KIJETf0koJcZJfMwowvYptG1i05Ok98IHiWvJrUYP9LRTHRwGYHuzW8mKl94W4Jn +BGQ0HYk/FGiQMc8OHm8kYmd/T+eXJSNLAEpkQcL7ivDhNQOYiUaH1LoSc76t0+fc +zg9rXhQ5PEk28y0jjC72vPQD0e5wkDJ2+FIVwOFcMlufGKC+UT73Mh8zVRXKbbUH +d3vvRU+FXWpT+8nTJKWsabS3kbPub322usF7IsqUHDKzqKKDQcCamtw4HlMk4e/U +mSqx/FeN4YEndxsFCOPMS8u13XmSWVMXhxXj4mNoDRPTLREWZGcQrxMl1RD1Ej1D +nuxle8K7/JN4NliRDS2qVHSVw+ZS5gxrNxm33C9gWbr5ddYDoYnYeQ4pIMnQW50a +Ayi6ZptpnRO/pApuoHlkyHS8JKhXiJqSfQxLuH+L0aUrnaJbYjytQMZob7skb99R +V5NB8J304bf6n4hEwGqVsCnHAR8RwFmhYw+/UuBCJp82n9Y5ltWeuhLQivVYXWWV +KIiuHVax6yJx+7XjxE4qxHBsZAij+v/HoeTUm0lhH597bUcpAEUjsgpCk0vrY+HK +fgfLkHskKE2BzFFDyaIAJvsvFYwviRmt+iqhStc+nyolvWNjGEAGsWa8X+sXR5WT +mdPWNVxeLVsbT3EXEBkOwKjfSy2i/zy+0A82TM4OFCIIGQ9VanksuImf2qU+4s4k +F+K9seKzvEJqwn3ogGAKTPqiFSz2la5yOaRaIPS7mn4UAo6Fw7s7GHzWsj5vbsyP +p/jJ4dRaS/jBKztU7G3lTNPlKWh3C/uaWdfJL/0z4AOX2tP6dd3p3/fE0hkqwuGy +on/as3NIzhEXmzVNIDMdrs0y1gi6pzpP+X30d766vA9h2//9V3xaLchdTc3X06QE +m9xsijUYjbj0MQQQfVz9MxERXhW/+lvqNvGYJAWKoYjfHNFUR9h12wC3oW6E5kmI +sHscehQYsgxWN6EJ/K6lukVl+gnqYYX8+KScFpHDbKfkCYpS+a14hgzKaLu84D3x +UTjL96EYRYjc75LTEjDfIY8jUJqNQttP8M3Kcn0oF8aJ8/Wa6cfRcYjphYVzAIO/ +QOGIMdhbXX63aefE65spce8SyoqSSM+jocEuJs+S9hnUKmurUHdoSCQVdEidyPmY +nbYY0dPgYCj2WB8gw0zkC5qOBv8QaoT/g1VlOXpY+VMvWbn5jrp4VJhb/uYPPuAb +TT4hAMHJ6LLia637sAH9IHaDMW9j0MfLkTcNeTAivRkAkYS+D54XRDGJpqONSfUS +HbaNN/N8pXV7lNif+HOp8wLVbNazxR98XavetkHbOyzCLkoIGtkmvFXN3Fb2lTCb +vRa3KiWbUzh0XDQ+UyFFNLxxY7TLOQSa5QpfnmbF4qVcoc/inTZVrQ2wJr0NuAZ3 +bGggDOAsS9WZqY+O6oD8+ejVeh7vmp2wUoZl4aDr82Ccf4asiPVTzMG+X7lAAx/U +a9icHuvL/3aZQ6UaPsPe/iSvORd3S6Mhs/uYi/qVWODqF6jxMWDRjnWLu0OQSgBv +Aq90R3mCL3aof5rISYOsf37dtd0eYnsobGTz4bkMpdk/Cx/D9FW1DXRm7myATj6s +4JcgnxZYRdqtWUMahU8jlVb/bRcGga0aGsaricVTgUAL7zmTX+lo+t8DWBJ66tBP +/fR4q2KkpmBGlbg0BfMM0LmkkVdXesYOAlUhIweEunwJt25gJuwJSf0LggVGuDxm +A2PYfwFoWS5VE1JHYQ713/2IXrtaaCf2THJKMgjeZRkHeXKADAEeroNeda6XlgjE +MeapERurXPBgGWNR2+EHoVJkQ5CtpBPCPBBv4NKlqOpNjzwMG8+5CRUeXZ2XqZIY +fYnhHVr/i00kHkq3VkamnZDAeQ9LQpRa8vopUX3vQLEl8hMrj94A2nIkkeFC6rPy +b6otzBYwQ95RanCmDG724EdHGvfXIYu29yv9mqs0GB8gc6rr8cvkGrxjbCXI+STL +arb827seqkrGkV63YgnaUHt5KmJR+QhNx6jWo7CqvmT9t4VBrI/D3BmBKo3xBM24 +VreX0wxQlhJDV5dk8IQcGM4x2N69oDOjQVYdIMMAqbibsOyIXNTg1mB6Elox7a9f +UA3YBEGoqCVtq97BTOrZKDGlsVdfW7Gji4IfWVKOR14qFT+PxqzTNVxWGgxnwB8e +4nhp2r1K5qYtRapQnBQdJ8gkWe+et7o6uHKAEX9G3SoAqRR44DpqbdxqKPO7o5EN +KQdB7eQ1XnLQX/APacItwO6FClglZWQ46DqEYDiulSwhTTsUktakk2s99LAgQ9g9 +Hehnz8N0QTHgXs9+NXgtmq5GAkmG8PaJqoHDbKvZJw3qXGye3G/VhzUZgDcAbCZA +SDz/Ey8fWg7LCyAUcbRIIKv2WfWABbRJRBbpw+AqTOBUQDl5AlugpPvWtoaCipXo +de5mPESGGwU57voMovz8pOSqAYH79K9M5Ugczhp/MPq12FO/Jq04tXqn3v0fEwew +f5HdKiJQZusw8E2KZzLjt+QbUiQqX82I6Xlgw0BqgcSoFx8kbEACshWywJ1vWW43 +I3fhXeO5rJmaNmXu5dSGhxQju1HfgsM1Ts9yX27s+pX7TrnrFYzs6n68J8xZ3uYO +db2njPhNMMy3g/f1gw/ni74Tx3/X3ivUAg+QP2MqxIFq3P9PvOE4oS9vnUQJFrwO +PSrzRDb9gS4vbyRov/IsUNIrZsrt9iq8L8FYBx5e2ikw8M9BJHodJQrWEMbBzv0O +M4uQIX1G373wxo050oQu0s8/R9p8u4m7C7hmUnuUBTWfMlv1T5DpqX2cdk9dhRE6 +wPEKYMcUM7T+IQenFOA5lSRI0SY2JLhMoMmxCUxya5/GIRA4dhMl+UixinmHIpHS +4Zia3e/vxq20lk8YsM3dNYrz1MThO2QDASsRLMHn8eFGFaS8KnRcwz76JdgGKN5a +FhL/nx9jnb5QGKfbopnV0PbWqwdIJ7HX9ryX7nNJmiNOELwljIsCTLGjfsiLrsN6 +MeCXYMLAibs/zNz4d+msVZNHiPF+8jsP0UtwsfZ9ioNUMAxIH35OqzUuZWrY41XQ +2UP2xLktg2IH/k5qIVupfyoMAJ+Z6HdwWz4UR17viXTCv4PrAA1hgQ8GF6CBvCSB +ffitbP/U3gOY/XBr5L6jadFnyTnlVtePNgOTKDJDW7I6fdsJduVgvDYO8iUKMu2+ +bPKHgiMGI7zQfgRYLQQP501ldelwVjeDC1mmH4wX5m8MIMIFg9kNTB96yx+WgANE +L+OCnRwMb4f4WRivRWmeWYvJA0VGi32jk20Xrqgi8A78Dl20VJfTT24EQxnfuL1u +udcog3GUVJAi4odlBMMmg0DDiAbmZWFD5Ls65Yeo6meX6y/3dGd7AnmXj3vnG13x +MlcZwqUf+NIiV1uFFBRTMRp0z4OsWtzgI9ZwT1ZQgmsY4grlazexbn9YiuW0D3Q5 +gb02EuPnaab2a5uCnQxPlFfTiegBW70WbtRY8CAa9zDc8UBOLDU9JOIRRctSy8wR +pc+0JcbvvCtikcEwd06zk0rEpNqmb5YCuUT7F783HvYh5zgR9l2V6i31FCSdW1aC +ojtfbYumF4f/XtXv7dZrDZ4tm1S/HyckdI0b5WSFM0fZhCoAc1UrKkum6O3Iivyx +L6P2ZerCTmiWs3OuZGiFsFYkce6N27t408skkRw9xAHDIUhRO7RVGZbGaaPgk1Fc +ejms8xxRsSDTBPSsBKOf0qpA7Hjdrs8qo9ZEPn38k4pT2XKkzixeV+WJpZS+nuiO +A+wwozJzvxJp9n2CEFd0S4S8ol2f6q0kFZbsO4+ese1HeeGyg+Wc9sI7jkpCpmJu +pZyEBvMmNon9c+yzyTTC30hNK33hLxDs8EYoZIUU42uDMeQxpE9+zd8rXrVxLAzj +qChxhVwS4DiwFs+2Z0koXMbFQIbFB9WMhUWm5XmWroig5q/rXe5kgEnRf/qwkZ9Y +MzUiSpSPoT6VeH/W573RllNieISx0orOWei/HMPmjUtPdSaW97UfQ/fIgBvH/BJV +UpnI4ajAt3EUetUqWYQlXVYmNtS3egRxy0jmnneFnKa5IrZS6tmC3qJZa3LfJTC2 +B5d8NWrC8CD6NEnYoVBIa3izBprcMKCJqb4cZlzBvDwdL2KuXgyC6vu6l8NiK6XJ +L42dt2PcvylG+WmmY8Ea9EmjIjjLKkLSRIaKyVG2bkFbu3z2ZV0sLMxwESUZB5tC +h2XH4NUeI9tSSkPTHsjA8JbCBLZgibEPQbWQoZ5En9dtkUJHj/fRmBMfiD5KLB/y +7kaYyZo6xkil4MRfenHhiT3ZX/R9jESb7k2ZKwlga69loeJk8Y9GtpNc5jMDRTSP +Eo9rk8dddhr8XhuZXVwp27NZCSmcZBqbyf7/2V4BhaoJTjevS2Iqw9JIQ4fqt6Mm +jsTaz+P4Xngv0CLDQ9neUTReOjXXGNNnOC+cCdy6l0mP4ENa0rqYagsvLZcw61k7 +eEKrYPvZSpybMgp09CMvTXKKIj9yX2IfrcUYt5fmbXKL7uSGN8fReJ2L22IdBHGM +c6sNjw90A6Oc0pM1Pd0PZHD/4pWDGA2d/40KFyN6hJBSpIdhmJYW5kuTNZ7A+JiH +0QQR5UYFmt7NLK+Mh6JcH4A1Q71gcUsFJAWfG1muGZJLAQ1vQr0e59MjGzoOeS4G +sePiJ/tXooyvEvEF31AQwVerOnH7r945GYcqJa6RcuCCzDh4xTeVdNuemBb3AiJ1 +Phg+KRW0e5Gogr0VInbmr0dRMW6WT0VIzNry0ILOGGN6t81ake9Y3MTH9dB7XiyX +x7CzvImGyG6j9wwUq387w/9O1MVPUcHRJWG6RKhuJvU4M0srOKsmtyFXIbpP2w4r +XOFxQkK7yKxifRzY3YC77A2j/9h4Oc+bqLTqlYg0DptuMw8nQnjb9l4gKeSL/mpD +POMelqQZovmnQr3eGiSXwXwgdfEBH08iN9bgLNw/zcrfj2G+Ipgh7bnP6ewIcNog +DBCMAJzttP2ee9MCwpY85nQUEVE9N2o6ocFvKw5ra/doejZdqDL+0+cbIxcQyDz7 +qM5ptmRmDH9pxiYk57AjC6w9iERidnMhJD7uqVvBP0/QsreQFKU67rqF7G7QfqOD +vVS4gdlNRBwQA2uOnl6O4meS2YqklJQoNhyiZ2iEATAw+Wq3dXioaOBvZIIAe9dI +9YB0AYrTlvQ3+FTrKeroY7DbaM7Gg0yEAe6I0CHLgn0+94spoAZ2WBDHckj/hLEe +WDUlP5xyvHyYmOEuFW3hXARFB8jN9PQ5YytnNLhPtgewBw+g5R+HCH1GAIc/Q1J3 +TQZq+QWSsArhZflaM1TnaNTu6yvcQ2PDPoZT6z7aC+/0ssem1FLmt69bo+VQsJJ7 +4VstX8VQbkEI/EyQmhBYHITZpYRWyqyAqDtUwG2K+ORSTmhpqdjblFYMvvB+GdEZ +jHk/XWN6uaoq7MdxWEjl3O6NCMbeU3a98nzDC9Q2C7QU5OBxKeBRi4ogNnDfBM+A +GbjCNy4egoXsDJvQIUJQS+y3fzepClv5KcBBpvUBhW9h619r7U6QaIEF4FEKDs3u +0LrZM0euiM/LYMQ2YxxkzlmitbqED2Tn5a6JGVfOYcvJgrXxOMNQ8r6ZxNmlE52J +IcTOECdwDcO2VBKFW/lGtFZFaG8CdQEpp0GIsCFf66R5h3tXs0oK9EPjAFd9wlZ4 +KzBxmv+X00BOdAef3TkHx5np9iT4oOAbzfaStd9aJSWJO62aT1hXv4hR0ISTc8Xx +pX7QMpHT7DFBcT+WLKM07q3e+vZUTuJAKzPd5OX/DUOXS9DGDvKLPu9MiUf653EQ +mSm90v+C77XkU+hQ0GhPG5O2DcVsIYO1GVoEbcKzs374GbhJgctnMvVg2Ur0lDlU +1HV1miHZH0/sKOrgm/sLfAOepCqSlT3+S5PsidnSkPCeaFZxVgAuR8TdsugIU7TM +nArnYe4uSU0I3AMmqeCAAjfmYVe/6KETli+2bLYwXTcqlJahi39aU1QBZd5ibgGt +ORBZi3zIAQ5lf+0npXYHDfgBt3DX54djyLNKQh8lwmtFDdURSjegOXpYbiDAjMo2 +2UNK721LxpOPSUFnwcCghikHm7t9d+qB6fWo1fdE1rBXSpGMZyk1z47Pv8DMQ/ln +CFXqJibY17AfkTLrHeWbXztrFrj5viNDGxblOt4DmT5eZt/xqZdR1VmPoQ0rwnB2 +zoNEi70LeVodVaGqt/QCpxSvutO+zoDUeMUigzmm7hwxjmY+6nPrSv+S6Lq3x4ED +E8Asfov/XqBMKmEUe2jBUrkfEFP38WWimKTRVw0S6mfl6M1T9wqDgrHJE5n75TIp +G49SeMYeF0uEERaUp6uTC/zjdvR9wUSnnHG3idmP4pbOWrKHron6xi7yVlbhUtDX +Tgfwle7ndA1fbUW+qO6v5pKepHDbkuQMesNc8mkuXrg9XRbrNtl3QriYFUXL64TD +8LHaSRhk328KUut+tkWC05+URPhXpIZ7JTFHdd6wx3rhqRz9SwoAUXYGUKJlw+bD +YVdg5sq2Fhrilm72EcFpAIYGncHQhwDbcDfXP3KsxN3xZckyM0N74TiTLZhWyrmq +TxPRArVmkLjlfAXzKtsyKXB7l9BcArzmMrQI9+Ej6tXdcU5Qe4E5q87rGJ//cw4/ +otLvfl+f8aCcqmofshW7YvCgeZCsh/ro0hOpusjGzOVkpYCNo4/U/409KSshoPo3 +Z1R+UqRFucmEyvcOLsvDx3HZRY01zs+jKwDYvMIc8bLooPjremzbGj7/X6auhGFC +KaFXdhqfyrW+jMyEPFqWI5BSjnwOkZERVfcH6jxR+oYEAet2Z4NXIkvGjE7CrRxP +f6mM5+LqBxgBPEpj5nW+giEAZihFNVfI69cZXMwilWBBW/a2f7gUmpNgeHG/4D1Y +OTWDKaZBPR4ti/1UrK8FP86sBW0s+X1fk/OED7WEh1onQA0tL8tz/ykhMlh869Pb +41/NyxkiCv/bOLof64Y/S4sxHL8hHmlYE5ypmVpOfesnv8AZc+4OgSkhZvSzAwVt +2qnAtQ0UP7nN18HtKySp1rn4URhzW4VCtyJTPOMsjo7wLbuoc3djTmhAl5Cqg8/L +XznBI3Yviqy+kqfP6NO+8wwiSGLKvjrGIzf+uLG/ULupZU/+GkeZ8nYMscp6x1oI +RlP6Am7UzLzCfs3ioFvmQaY3HUW/+7wzdtiOMl+8KSx8C9o3aJ3wWpwDgj4eHqZO +16w3tRLZZtVVqS0ArvOj/e6wmislqDVVziyrPeaDkj1UO3v/6aBRbpilsSBbLbub +lcX3Kg3VPXibeK4W6CqLYtAsMYEOW3o7gPms9b9uxMDLA3y4PGcjMBDa4nlMDXx5 +ZunsHCw+ZlCKl9MrqQ3tbNHUuwMt0jOcgA0WvIsr7BS/0RnOBgPUcv484GrurCNC +YBHVvdpg8nv5U06ohwLgZqrGl7LSxGnOYaaaxVPWOkCMpGM3YsacjmqWu0WQCFZ+ +fyhesykMecIGwdn1mA5mOVz7HdnnV3rrIXBX7+P7r7CoMydhMVj8GLxHtIcnSlYA +Fq7JUJptCdHT5zRDvdr/ORjE695X2J2pZLlJ7x10Fje9oR/K6m9aBaEed/4IqkH2 +Lowk3VS8PxA2DcJmuCxrYqDJSxW1PH87pq3fUXUMqTVn1kmn/zBYDQEQrGJ6FYgr +MtgODx7wqeFGiGPTScHN7EA2gmJUsMtTakEicaZqyylJSRqLjtWVBHNJLU82XSLk +lWLEz72UAcQ65toz4DN+uOk3G7hy9C8nRkT7S/9ciaMDQUjJ3gUO27qR9Yc3A6oR +u/ZpZyC0OZSj1WbjIPUEKaM9rJTJmzpJnjknrRtpGyRoeaC3sFGnMp9kqj6EYwS2 +/X0cDj340W9UNG7NBvmpiIyhIFSbCMWgwv8hRQ2+Ea9+Vpy2o1/xKfgS5XDXOS3v +k/v3IrFcMntqw8v/fk2c0lagnAFZvmeNe75Qk88ddqTvdDRRiXgrLV2VTvAiKRIK +UYymwQOBaBiGlxGj4ydboR7e9RqmhDCScZAHiJSZwb2a9/bLHlTcpC7A266OQjLE +KcI49ThTkEXnapkIy4hWcXBR+v+Y07nYnLaCLV8YuMka/A2dPEGd1vQ8iLDBAjFi +KBvhjsppA+HWLtjS/fsItvd79cVT3Bbkz7WXg9Hy+NzdtPOXqubCV6Nf3YhsnS8j +bqcdzV0XT6wykyFy5/AZu+X4NLwmUggFAnXc97TGdfqtGdrpnciSfO3RLW/7HMAj +ls1bK3wW2iwYHeRMfGODHu8fcMd/YdABhA4Gc2aWLAw1wPNPJ5B/A7IX3/2KP+dz +ARAmFQPacZ/RMtNQiGD8iTy1PnS2P46qNDxiOOahWwNkcl3r4pd2IV5b6qUWf7o5 +ixz7C2ARnpFG6tOhYHTY8Y1Gq+p0zwCvRSMORd6JmJQ2BSX38ga5cAGcGP00FmSb +ZYiTF1oWDG+2JV1l+4MVUX4Y6ZjbFk1ASV/DG+nLjAA3mANIP41pV40hyJk2p8Oz ++ODVWp459ocFso9xvnQIMmk1qY6KZ2N4Cy+eZpiwBefWznL7DJJ8g8GuXqRrNtMR +XMvOpVghoO7ePgt18883kEwlMnYQ8jtQL384h8U1IbxSNs6+X4mq8BKR5J9z66LP +hFRS1dHqwaJmBMHqU7QMIRnaJDnb4UyXsLpMFmnRawjkXJxo14dj4k1FiFhW1CjC ++AHTum0pUWakZZX6d3a6VNbd8Nt5FLP3GpiazZmPCx+ETd1KatN3YL5l1Tu5w1+c +KyV85EfZtxVTc6GgkvvXSHnXOk+qpuWVKsMyApI80RZopPhtXNdmgSR8/4Hed/wS +69imLbpTF3GFxb8gwQnik+8+Cfs9gAFICMKn/I8DXEV/VBx7dSCqANyU2JGifaYX +cx5JLq2paLcCA4lmOaJJF2m6LLQ5YY76IRpj3dKXevO+DL8KaSO4N8AnG2qU+647 +l6cXs7NMhqtOzSJrNcMhVDa/oo1ebgqEXjJ1EgFEHOr3vKX97omZU+tYsgzCCERA +tMBxbluzptpNMQCv09mHlbTBbNLGKqJmmpuqobJWtgyEA62ArIRY6krt+p34Q/gj +aRYBdR90lvkg73az38I/s5+q9q+i83FJukJm++r+om0qTKPrf8ZwbWLtfAHLWjVN +jtYQF78yMRgxcJIb3tZDH1freLDqgD5wDn8+t81Ev/XAqFWY84l0Rd5AaHOVzMBv +CJ8WmFg2UPHZUBbeBcppk+cZ1ROiBEq4CPPPhCU0GLNY98eQcu09SD64dmF8+tY1 +Bf3Sx03GWfRrU5xupmIHmskpb/3T3bxMIcrABPsQ/rbQ3vb51FHf14NEVDgAkzYH +U3EkOKDHvfGiYdA9As8BwZlGtPMY2qnus/3kHF12cej3oTYb8v+MBFD2WsuDmxZY +RORyqIB1qProPYMQIVVp33h3eKOB6fmi7enaoXsD1kZX0DF26LYvyqQXmmsCBRte +OcRSD5ydeWc0Dsp4D90iGr/KM2poHeYeX5t5x0MihhtH+4S6b9TP+n+DQpdOrzy4 +DmEV35/w042OeXUrqFWUPAV7kI9nrGGXv5y0SYU/pilwTErAKb0BYFh2vfMFy+WC +a8GH7QbBMVTs1rhsQC0koo0pJwPMnweYUQyzF9Kyo5z+HRXsGiNQIqqgG2gq0nsU +aqVDeUlvXbk/vmcq/UXeXOrWDZg6u1i7cJzjg2VDwWkFKGy+UhjgeeEDk82NS7km +OBAr5bwLkDVREgVH0+wAARkMG/nasfK61eG0GXcNCTRbhqAWVeQE8W8jp/hy2q6x +nfyr/jHtcLL4ydzgxrwm+U3RKkbfpWhx/D/253UWJB5tJnFaTAy41FKd+C78L4j4 +3yEeynqKOWI3YqN8JZBUT4A4fXMZ3g7CFTZABqw5Htr+Hkg2Tj5XChhnEPFRtn4P +T4/Qy4FbdhXu92+1kdwVcMew0faXFLXZz7rXWtfXHib95YKjrivLipF2nAW7rhkD +K5k/WrxpnB7xls1Ke3CAAbanB0hbmyM0opPItyS5pP/HhlT3PfcQP+JAQhoP4oEX +Efas6UBjtnAK629C5JuDc87BiszANGtqZcq1Omjs3nUl7eX8FcX8pjXPwVuM7Ba7 +fEVKhDY5fclPFm5i5iZnq8iRSkhQMX4xYd2KAnFfMoCc9O3Kwuv7RK9IqWVv49Go +3mt0U27O4/ysV8/9Fkn2bQXUuf01UHYqAwrAfheohGYJf7KautC7/Ym63fcOg4H7 +VPfehQk/SZXjiVkEoThUzvJ8NqPQDT/6OtEAINZGyWSPubqgZNt6nmCmcDkpa3zI +7fRF8xPNCG6hdP8c81jCesrypcIKN+zyK+OhfTgKMgg3tNl2IC+haEJhquIkVhws +5rP78kAayf4MuE1/QFJUs6poAr2T8c/MsJpuiEFTp+tjemYligGm1QfSFO7b5Fd9 ++C6IYXTc/CXVwbsOwN7L7+cAHpU7j14RfSL5UeAGwoPjteWtjk9+CUq3F98bXVb5 +HiZIvUEFagXuBm2VT0Oo24p9dbR6Rghcx0yzAuz+u25Qo87Bj21TQ3FCfCEI5BcW +QWG4aFadMDv1bGO6mVmviaiUU2tn5uxJENkyDBV7YI48i4Nk/KpzScYvNh5CWXC6 +fcb9vo5Ifsq4WFkVMD3S30ROY+f3b71gmwOWjO2of0QEimqw9L6ikd0ftzXA0fRn +A8kXM2pX3KW6ZaC97fRnis1PvJToX75zREtN6wDepil24lorL7oNfuzw6UrQTzMx +L6SUgzlrmq6bRkDXVa39hnlEYuNGgZb2glt8+dWLWYuR5/yxdB/zPXCT0QFfhd+K +Khiu4nZBSTQjbSginF+rB0EtXONemzjj4CsdgGt++x6a2K4Sqnr/N3rkBR9TPOJx +4XpsslFO/xid6Ld9MGttW/rMQJlQUr2YamAGLVWHK9IFYGw3+bPXMKvr42Iw3frl +5NjHVDUOFtugS9/m6OBoQpAQr0mLtabMoK/cd/rZ7NZ/vRXx4Tl/6sCajMXhcVxx +BduVZcaONgt/wgY71H6xHe6mcb4d+M9P0wdu3+Ig+a81MWtu+SxDLJGn1FIk44E5 +eBklsUvdcqFfp40w86y2Em5LXaZ1BYaIrJ3tVwPQfPQnGHF0hsr+i8vIrARpFPjx +c6XgvOe3Zq61wtxifeC+2KuDUEHsh+wkFPrrLNbpda9tF3VnHVaCqUC7dhRxQeiF +uVRpZbcK1bZhQ1JW4YvGP4/+TD+vZvmLXjZaunlJkRappZV+SxyhWqxSLqq10wFt +OCR5CDC8YxB3iFdUIDSr6YYM8GoeCnkMrA9aDODNKj5GVpdng/kL+FsxQjEotZCL +7YDvqSH7Z2xkhdqOVw4fmlf78SXRL2B5AmVdVEdmsvGsHSfsRtQdFvzbfrRdAjOc +2Y6K5jNbUjbzbGpgBg7p7G9j32Z/fXf/rHCAaYBttvHvmbgvNrs5JCJrOA+JGE1q +IrtMk7EMWPoLtOxc1i1c3oaOWUeZIYaX+Ygj/j8psHmfvyvDKLtUmEJYvKWyPxco +LccsfrXXaFA6e5j921Zv670sscRrRMMUL/aauc2PqFts9VbDVvMgImZ9dmmq5Jx8 +cD/c0Gvroj5pAQovKlRwczuVGj0txQcJC5u6R6CkYCgap+n1FeLGMzDQkNS66ygL +ThDJBcoRJxEZ3JYMeNHyGvRQ62LZXHgMhugdcHJ6BxtWMqhIllydQ8+YS9AHrvub +mXQnkOvMV7CK3fntMBV09oT6wdt0fy/YnPoXnzhjSJIoI42Dm0Qct7aDo3BWT935 +51K3q/Q2bD1flZmZtz5bDdN5FSH6AzMRDwi4UvkJ01qVf50L+3cbtMl+Wi7de46I +OcX2x4BHzsJXDfCX+crq9/LwEF8hMCu8FghbfyVi6DKeDeUWsL5sSqQfiRwldmAX +yV/0/iyVoQ29Xy3yIJajsz7h3EAmURxBVFRDQpbn2s5WZwKRA0TXDQJN+aTXxOTN +8xX2laFf531D2K+e6qZO5LO+wcymZaozzHHd54mrj2W8hDhfvuBlTkBR0cjvfEFS +yMIFNtQ14HMh0U1cwp74fAkXr6HTn8b3PlczHKjiqHHnTOGP4h5dgAszpnWE6eIq +J1NxGHqQ0hC1TynjOp5Zhi4AU6YXYelIxnvLvdqyBHAIZQ3ukIcpToDEY8f8MpKQ +CRaoIRDSrsCDW18JzoQByQWoAFVztCJPU5w6ipo50wXmXnPJleWjbZ2GHBR9KZPn +32WS0HQ942f9WrlV1wCy+9MivwWb+EKGqZipYb9Oqr1ybvt84tRHoQvpmT6khFtl +AaIrBykVX4adjM6NXoUG/X1Hu2gWBer7cqQhDv8vnmAYhHZy+AhzKpBSkdvCFC2/ +CNGicnGZssuGEn+HEzIoK6GwnzExcQNKphDetGGOFVkTmmdsw49UVGFY+YU7rzJe +Y+vNRG7mO8MO09zrt+TXKF2AtErd7grcPR+fF8ajFjaaYow9yc7Q1doBKANKpwHx +Apv85BIA2AfTwAD3hswpz+IfdcWGbK89tEwUZCK1QFMEuGuTDYLogfYzjFKDoM/s +SsqA+VU5vRmbAahm9Mie60Z5RGsfiSqpeu7xfi1FpENc8TOvOFBOdcF2kAkOY1Cm +52Z4JhEJCfUHKjUHdL+VwcJfmRWUDWmP4n9xIMgkuH82SKMqaenEBNH/Y36Hh+Xc +zoE3Kiam7YdCTFcGlJn93a8XBQGaxT5CIhX3F6VHa2rVVR3qj1XGBuX5nmciuWR6 +SOGBMGmTO4r7z3Ickv+ZCgPaCa4R7RpJii+JfdKG2lg1icC0T/gdiV+sc/ElaXQs +dxzXcdwKun3R892Eu57dKZUv+47EayU4ETNFk7z42udd4xHgrzWykh6a+52chWO8 +Ne+WEd+nxpU+L3wSS0VXqG72Yx0A0As+4z/0zVNwnRr4bslzXuB9mzNaGxGhYbVb +u7znz96t03CCsdgKUrmyTK5+G6FWZ7io+AJDrcfGdkl/69FK8E+6HDi3HV85UeSg +yiymPcmvxIUgwVsBUDT5Bk6HpTehniw27aK75KdBu0Zk+bqbdGtM1/sIXo5MtjUH +HsqCzIAhqunoAuv9lCvwYrmf4A6m0gGOyxAnxVtbt5GxKYX0rcc059dQzqWnOIhM ++DtlRnM2lolTFcBKeGWSwpySrnlwqbBDGgPTWSIa+4hDWxkYNuYLxLcqhb60eaWM +tSooAk2fNr7PTLnC1nseGNf86PHMr1VbzejH8uKdbwe+tBoaC1QMSbiEYql+FSHZ +Egao7WwuCn32oPZLqrklV/FPgy1QIdRnl6aD59+Zu6CpG3UU+lF1yUKv8sUSaJEd +bct1zgHrQtPS9NniLWjstPpFn7+53/NvOf3vzUHK+rUpjxmQzEEGpEfPaWyV2TQ/ +QrQ4CL8CHIDtRnYs6gtEtD5Wvq9+QuZqg5HjrYh/fJJfr/irR6k01nziKdOBFl5l ++NrmqNys/j2P1Qqne0NysoygUUy/ayk4rkZCknCfCvSAav4MsVJKlWtFO7wSrxA4 +ntQGRMcuEYix0qDj5Djkj5K8fVfyGceskYotQnaSG3kALcB/g49YsDGfQIK96Q60 +mr5XM+EGqB5BNSYxVzH2VIYK+IRENJbnRBfOdP3FnOPsQwW/CGQYvIbjFdxzXFBt +1LkvBVI7DIhp1J4jU8UVxPBum8yyNUjNJDFJ6kclDO/Y0vAHFsgJVMGuuhM5D0rf +MYR2iUK55TihlapjYjrojjGX2Yxd7ER7KWvKKXPne86ddYeWJNMXjjHT7Ab/YzJC +fNXKm3SwfM3rdkyQvoG9/WIHoZK3MOceTzufs1H7VdyRKUvOdvnMD609rF/bmxz7 +aoue9I3xIjrWXkmI3oR436GuhEpis0yd2WLG6CWH58eAYxIBbBwFviqmr+OGHfiH +xhI+y1/Q83LGD9WxHBLiMn4GmYAGI5LCtwMXxdEA8OnclJKtitvsePWFFn50CZ5w +aI0C+MSdYIc3vk2TNtwVrgiTW/tPWSCN01m0k4/EVaPbZ0+Ou+I3gIPFg+A7Ljt2 +io3JoIlC8QUNUrgo8PIT0nPM3nJj0ux6g5WD8dhkxv4PrZTrAs7pVVviD/koNT50 +Hj1ysIH34gsos5ptYodF1scbBKtD9qW0IqpwzJuvZ600vdgVLV1Q+eH6N98YerfG +P2g+r+VCf0hFbbCaxAgCzr3j/w7p9+ReoOuhAy8D3+pz5UaG1TtFSaSltiE86D/O +MBV90uQUh/O44QgU7yxRwrvUXex4nQgPIq/oP3vBO9FeV0eUcRaHKu2cfN9mSkrf +nPsV9p8w1AOdVvxir6RletoCtCNV8HrdPfqJJRCsLRzTdvcmGDRbZ/zTKyfQpRzw +xLRE0GZJaoIqBZMJMpQPXzRIdZ9VxCbPOn8Y6YBSeG0C+UnDJhL7iFfX/0Fui/pW +dPuAzdAybWPI6u/M/CjRgZwp1Qp/9s7mCtvNgxX1HxiINfbA9yMzhTAkm4mfXotR +DSm0ZcQzWf3WIEL3JDU21iIu1nF0/pvi1hdbS72VBlQKlZSJ9eVoq2PCDF0efp6n +MN5oR9Lar6LQbY6XZTw5rY8d7LQ2YPbrd3xbGRQdcgFwlG7CCmRRLOuo7t3FTUXO +qzyudYlkQPICeGybFZWk5v7zmu5WFFPJM/PLczza6TUrejHVGmLVYOfysBnL8O4i +Mn21TNUkm2VKpoqOVSjED6JNXqNoBzVgblkDPicQKqUHR3f6RrTg8aN8Pm5c26wB +ExIyGtWiES7TPx938kZuMpNdVyfVJEZ9393RAgVzhTQwoqciZiaG2uylU2CI5hGC +6wuhO+hhArvR2LF1Aa4Lht3b7KmaAGNkMPIkLGLhXrg5s1DXAgeCwYzI04R0oAUp +75kkgGyKjGfa4gIDfWdOzGn/SdXdoPrUc9O12Z1YtNhCazhNaZ3tQlAhjtc4WLmn +0ZqKS2Jwshk5k1QervFSulCNHXDkfjE1RdwI/Crek+C8T9hWLsR82eD2sBC52Uhy +b4kf4jL9IpsKZnefTEHKRcYFJsJWkn1kD8zAAnogwUNoW4KHRUBBNXm+Qe8T2JeY +ONgCeDiwdg53nz46SDC2uXojVG2GlpPKeMKxLrqqYekQeJPsx1cNnFi0EvzhiMqL +Ei+XDL9ZYyTZuqgRYd35IN3py6OaIgeZBGBCZbVFrLH6yLbZdqKDCd+ISmhSzIiR +e9VDg+STQlntBkkXjqvirwOFy5AwryrPKF1vbMhTGZHt/h3tyPxsI7HzgRkw/gep +JIxRlNVWholMzjudWiWCTnpoRc936KSNHmLb/aPG2CnTjIjwn2X9ERWljT6ewq9K +z6DdA87gUG49RqMNA/nf1+S/CfbBNT+SGJ1W92piZyOa20aEpzho/HVWL7124Tz5 +jnDi48f+gZjd7X/19FK7q9t70uhORNX0v2cFL6+E6i6UCoal1j2KYR0DXALlOWWj +q+kPUbhjjsZlmnnz6YPILaJHtqA/hR91CW/zraRfPajqNIFq4cpxjS3xjvOAKwIq +yDj/YijMpcfWjsasvEn6WkNprm3BhDr2TBxMlNoYR8h8nsQj6bEgiav3YzLX5je1 +3tt5CK/jv3G9A1L7JMgB5NuPrYGGoTVWIWKSeGxtuRgEegMA47lVnh6d71KkVCsf +Y/EaIfBxfMyHoC3oHfrAPbawM2Jzzh0HxPrtKhwSAtHBVq7qBEQWZ9co0LXOzc2p +eknj9VneM28zHAEJoD0fm4JdSWarw1aRQILKaXD57BZCc9haxs/g0z+5etvsxpOW +XjEY33tHoCU9pdILJrXKdJAbDmCalGPQD0xTqO8cBYmi7TeEa+PuJy2g5kX8hAOx +Tqe+VqBAR5hIH8JpOG65ZuVDnt+3HTVfVlkVcYhUiCw611F/lO0HbLeSKeOjTWRC +yA/EMv1olx0UYQuTE0Few+HG2UOtSbwwsfm+8ewVkKGg2iI5sS2w7SQBlHCtVQpY +7WRTsZXd6gwEyw+RPJZ/eDgadOHnp5LLkWpLKxSR5kMfeRY/5MlS4xrrdx9JU2pA +i/AKw65m1sr/Cme1fHhpoz6t5DnkKqQQj4i1QR2aATRN6ZHghqAus2puuc1K/hWK +MDocLAn9s7KrAtgG9+7a26GTKB9SDNVPjhRpA3bnuGrfL1HKW+L6j4FhuK/Yu7KE +VAVQahkd+bdyidoij+na6Jn8WtjgFv+GbqGHmfb2I7AGaDA4uIyL9jYCr4mKgOvl +4v+anNDhw57wLaDU9woHFCXfLf8+EGB4XMlwIX8xANqsWyh8dlRB8tMJgE4cK/Vb +/WFER/Vnxrcqr9p/+VmT7z2jcpjnXcjg/dH5nK91TwAym1Fr1e0fw2Lqkp++3gVA +xj9mvTvcaFtTSUsZR5zbuGP3s9HXeQ1+esYFYIHwE+ZqtA2Vo759OVQW1fyCah80 +vmPuuw3Ur66sceqNP+UV6pGOaSHLgdnHTvWOyfLtBHOIUbYQQBTZXds5iFZXAKtZ +suAzn1QaZrkDOSMezZBibMabUNgsR8QOapj0zP6imVNgmn95FjXwRgKQqkYMI8yz +wDTbwjs4ukD0EGs6zne4eZMCQf9j4gRF1l11l+ZwDT7ohOgtPSVmGFL3YktAecWY ++PSCo4qldnVTbxGHrLI6YKGjYXI1xPbdJtBFF/n1/0appMhbkt1Sbz4BMICEqe87 +mdoVdPQVurVjKw19WWpeQs6srhNFYshDKUU+dvj4EPZa16NkViAlXlvgmcagcReV +K1yhL+Hytr5L+iRT78Qsk6KI8ANZ5ATNXlcbPjBy0/Dy6asoKguo87t1rbQjf62P +L89YjKvXOY5vGemIKrzTEa2cU3YtOqo/TE6z+xZnx5ysjNHWs2KrnGlytHWJ/Lq1 +94KmJbJ5vT5gr4RN1HSRJKwm/UT6qxarxdE0oM1kQxb+xAEwjmHBdDgC8lLZTSyZ +oxm98yxvgZ5Vd/qFQ/1J0rbREDvJIq8MinSwqsg41kmsqdDzQbNCv+zHAynQTiKB +tPUgfv8OIsIRC8sWoipnzYjjKNWN9JM/j/dBk+f9zYyqrgbfK9b8rB0NMvaNAIwa +gSNpBwxHcmewi0rPfHCND9B48B1SRR+J3Xzee/e+cviLWIaMrCMCLQ6chFQyLiS7 +iDAhfSqUhTMduXPnRcEE+CZ4ntnKOo7aYbg9f6keNMtLTaAbFE9zaSHkWNc0Lcd5 +d0ju2A7B5xRMx7XXE3gwLtwz0G/aD8eRGN/SJKhBIEUxvInZ0hUxyCVWmwLsZ1TQ +HukBZFdBMCDMVk+h7cxd13X0STunpFIUmXEqbM/O/8juzaMDLWNwz6ztzycSNyje +SS2RiWnNQapdAtH8I2gvUtG/GLeIBWM0In2PsPl9JesTg9esja8oVaOU9zb8XBal +5TW/oiscaTJLeZreJ3lRJTlgcjt42V66L4986AtoUdKYzbCccEqram/pC3GlGSFA +0hmtuw9Gy+ujruqWjQck4EbIIUm8n8kwW8HsBMqeJwkWImaSMmJLZPDhmZIELo+l +X+yG25XCZBT3cl2WmSa+Mm0eyIGVZrccAucunnwGl0PsIbsIfb0ZD7lDpMDPOaKU +//pragma protect end_data_block +//pragma protect digest_block +6N9u26hVMpcbyyfmRwuCf6Az/lU= +//pragma protect end_digest_block +//pragma protect end_protected + + +//pragma protect begin_protected +//pragma protect encrypt_agent="NCPROTECT" +//pragma protect encrypt_agent_info="Encrypted using API" +//pragma protect key_keyowner=Cadence Design Systems. +//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) +//pragma protect key_method=RSA +//pragma protect key_block +AT1EB0I/npWqScdRvpJcRO4gQZmZ32n55aokvX66dpBReWYyfJe+e8xu3FsuL0hj +xFTYzPqCsokjEbxWJcQ7AqcTcNtY92dNwmIFk+9mtQL11nDQuEcAz+9qG+DzKQE0 +wEFxB1EFOwxq3BFrmHDuIOBCt4mqLXAlzSTZW5xJI34SVmPvvsg9ljtOu5ovC1fo +qrj4xbbiOv9JlswWSL87kY3/EAlJB93cTi8uIzDi7mLeylEdcn2Jw5H8S/Vwyafw +pM9YxN44/wv1Sm/j6jj5BDCKjFZ+0zxNMHtlB96vfvM2pNIgnswgk6ZCMT8kyGMR +eLKSDiJKdiLlAm3AiIYAxg== +//pragma protect end_key_block +//pragma protect digest_block +IjTle94Bs2ph1I75fY7zPvZwn7c= +//pragma protect end_digest_block +//pragma protect data_block +jEwb8aPdGcJbG/78ZebWTFTU/Ib2DeT61bEMW5W56vJUleaukGL7KoJzTTwLEw1b +OEtglXQIcCsUJz6B8MlcA9fLKPpPgtYkHxcWnNSSxxW22BTpVXM6iIhckb3QMaKh +rFK39UnLYiuZpCKu2NFFlVECv84Q2hV/W9wxA/bfyL2H+n425Wf7e0A8YN9Mji+8 +eYZjcLX+ey1yvjENqI79uEUREvBee+aZJMgYudNyXTXB9MpRXNXcFnOIku2t9OKb +Id/DdAaMM5O1rixCR2QyOJLd2NVVmoXEYBEGPnjk9y6Yg9XxJfSRwv3YMgHMq8db +eN2QfvW+l5vrTTRc41ub7AYB2r2nhVpY9KHMMIt7VJkZ4Bosn4b4ebLNq9C8cefm +hP3TK4N5O+sSaRi91PXj9LRKCjNwrVrkvW3RgDzxUe4Fir+q5IOc8czPoTjUxhcU +y7NVBi1dprTq6vbg11irFbW9sykx8NJH7AWFPKEbpVk25y1Hre9UX396KY7RmSLx +Lp7i9sY5k4rs8QIEzydEmtlyfP8bX61HccrJaAokH9bcroIxhF3L0TDxGxllH/mK +hOtHROnvelqID3Ac3+h8puXvs6vb98TydQKCrlXhwKl7UiVZVGeeRDSX2DULVzwt +EGQGUW4qiUuE2+vVoZeHCHmg3oByct9xMid6+7e1YbpNSnuTisFbGdECbEKtz/Xj +jYDe7qL34CsW3zgcmb1rFhUr+4TWEjWrlUWG7jPYRs3ArkDtF9i3ifVL+juwukNR +AshO83H9aIjiDsg9A7uGaCFzkKb/9dqHdSuhFPws0jvXKscy7pxDnZx2TU5D+rKK +UAagyGQQRG56hb6/PC07tMyEKoNnRLIBsfpwT5I2ByZHI7Ds7EnnNIRCpH+J2GCm +bMVb6XA1QBOBktarAlMZr0/YTrPRybjSa2U+/fEaTFbJ8YQcrBIXkV6IPhI5jr5r +8QnP7lFI49DugoES+KGdXS+0BZp6avOxzk7C6Q45V9HPU9MmgRoOn63ymfCcdwY/ +Ut6r0b9GlzGL6poiwoEjveEQk4587zPMka/nu2/s+Iq5y2yRIRjVFY07GQKQXCkL +/2tqvlLdbwflxGQDV6J5k5yuIBlKt6p5Lof2sopDnlchFVkZvE8jaqGeO/M/9tYg +L7SSrhSBpFp4h6LrTqLciGOOz4g4QV6d26XzanlKg8Mpab5EJHt7VzS5VMlV7mUd +Jlf1mPbDqq+dMOc1/Q1fZ0npKjtdLpgDvWDe9HDqCM9pOE6DMYwtE5pTIovWxDq0 +VE/sWvCxfJ/yyFYvDf2fSC82BAbPKJgntr2Y2VTEIvWUntWsTfkKl+G+XXgsev5x +Tf+qGjc2HQ4T8Kohf7rkzSj71QSlVOsLNQmhXIMSLQMMLfwd74HnBpReZrgYyHid +bG+rIOjM9EQ1NRQWiddYR2soJdm6oGxrMZUBYcqcG77HAG0EcZEHK57u2RoO/7mx +9KnlHnAvpZAKqieEgD2rcq5cDBeqOVE0NOikb9JMFHUBnFBOtNSwi/aEc3RM5p2p +Nkj1dyeD8bDFbN5MeXKVvlmgTvy67hkK6B/VzKjKoe4RsxW/526xR3d+kM7ePYL0 +qfzwdinGX1leF5ldO+iwDEU4KXqQIMzYqJsUFcjz9QmhjOg+75REzijeyZTUH/ON +IKElcmNkg1YNQVqsBUmQS97+DcRmsHi72hk8bB7C7RPjNIXf4R7WUuxlCcJ+vrDj +ikd5di+hFQd8nz5JjyH8j7iZzUUKa2X3eG7mWt58kCVKVa7yPgjYqeh/Sn9OQQps +qvJR3O16u0mpuyefdifyeMJP8xVlqZYs6skf1qoNT0zSaKwrCacFvwHbuWaUkoDR +yqBb+ejNQ+0sASEbJqJRO77clppojoHF8T45EVuL5cStQV2yEF9CZbp9v2P1upbb +jMp8X3KlG5RwaR1LY1EPIAjiRHT5IHzi11qG4NQLrfK2eK8Fx23PRoMFbknGwJuk +hzunSzyncDetpEfNs7gFPVV2XoEc7bZaubq+kpe5BkkpZ4BzfGRk38SJJdVi1Kcj +3qE78MNsU5Q54nCMzdduOZawiLGmpmtM9tV5b7rjldgRWyKojzTDDw9t5aQQrPDO +rSH4ACmvrs4KPfx8BcQFoaSmMuvQvh7Msj5Apzv7zk5jAJ7ixxXjh1uz3ScVDADf +Z+IsPhltiCuJG/pWbPlAvIoHAU9DMcqxsJuJfVzZzQMCA/ySGBUerc1f40YbcaXN +fP6TWgM8ddPkR3xtNIomMC1z6xQNAXVxpuHtH2NqysfvhxNNCh++nz5pslow/6t4 +23JHm/U4QEYCr9lUI7ioXzM159ygF4CYNGVz3vZSbhfhBodwu6sKXx+HQzPHFrNi +/s5fhdytS6/YWfb8b2ce5KGTDq3i0dmIyvqqKhR+JKZrYGTRg1n1cz4gnLL8B50a +5p/jCCo5Jc8+kw4FgXKHVFfKmfE/lquAhigG77DvMxymAHwt3zoac4vX9+d/3lgY +sMFt3rKxVtg59Lw4jiz5qLJnPRIeX7v86tzqI7tXIb4tJCanzhToNYmvnZvglRzn +ao5IpxdVdQMiM6+1viVRm7FhtheOemRn5vyEI8miARr7SozW8eAUc2loaEi5t2RS +YcFhiAuCwS1AUpya4oHRglW5KKBV51hrWWbu/p6jLpCHfCvzscyTcGGes99A3lD4 +LXmeu+HofjQsVpf+opg3CHhpOMbT/PAqoFXYKKQniSDfqWrH+AQ1scRfFrbCs+ph +eTHWvnMDlqK5SxQAEG8W1obDiq6bwAfmhDo+aqriO5sdk3K5pL94TVbhrX4N0acy +1zd5TDPo00KCTQQlyA5FSblwcCchtqW+atNVJFYqfSntd1xhmzQyu9Ngc6lV1l5n +2oJtM5+jeEJrgAnpIp7FjQA/CfCdbqlX93vHAu7uiYV8G3C2CSEotkfvzBwW7X57 +EDRVej+VJL2f5nu2HxCJevv3tQxGrv4ahe1YlIXBOmlColhrQ84YUvuVEXSwktZV +mxQqH0niUtvejNulserIiQUP3zWv9bpEmfsYevRp2X3SKhB1K7IbLwJrE38hOygP +Qhpmp0Xg2NVckrULVxss8SMLu+GaPb1lbas8ksNvL3oT4CNTUsZVlU927xazedGq +mIBtFENM6de4Z4ksslh2iJ3BGYGeX5dwcA7CQq9j0hVq1WaeftvRXhQi0Gk5sfGn +ZcW1XlMP+V0ulokHWNt7PsA+tj/FJUiaOz/dn6+FwRjH3jsmSAfywigb71S8fJdY +DJFcobD7f5wrzgJrb2Ahq1miZ3FhFVT8nXrv5kuyspbJ2XsXQ3CMMbzki1grLp0q +t8rStf3ulp5Yqw56N1+s3efyH74+r6Tq/7BD1uQmWpLby9Z/POCe+yHSd+6U7Pb5 +y0xJ8vGzE2vVVEafL/4hTbZrj3sThZ3n3kRArCv75KlHjWfJJcfKUlsq6nl4UXEM +nzOPM3aM3Pazc/DeXhpgr1r/SGjnYOa9HywqBi5xRqLxuoACWWLAaiSpuSb3Suyy +QeASPwMvQ701CvgDQOiyL2hwsfPydA9xmY8mc/eIFe44BmN3UypfkqYJDEZuuxaE ++eEVZ8RD0Xt5X/fXwN4Ke/QJiHBUc+yhw2Y19CX9/8tlR7V3YhhuXSGsvcm6Z6oj +eEO+eEDXgUeaiiwAsgf9lpLU6sg7tHDuOvUlQbnhYtHBH69GFPrNQVDym7wvxojj +M5NZHI2pv/GYOlzeoLcAYr5731+kSg6l2qrZjft5LqL7YDOFt/njnj1gToUpoaOP +jogHOhbJziTCw1tV3dYJbQPszPnsxl6fwmquDcklDY1up4eAC7u94l/rXYxCSyBI +BF28POggy+HWc52HhORSy+UonJM1sLARMgr4Y+1NR6uhkLP1KsF8z9KDxqGpFFDD +rTuhCytEBR/NNJLVXXEzsQJrSofimLdN9PwRocPV0/LX61+ZiQnQV3+PGKpjlxah +TbTBPjm62aENIdzoqtoSV7SPO2fj1CjXDxcZn2vgg4bCxDvOlf8e+9bfyy5jF5J0 +FiV6am4a2YZzgZaTin/+cseqaoK5X3a9iqzU+gl31XwFPR8vkHfbGi6xprWqKi61 +UtyCn3eeNt9n5+LGUvcjWlED5KUW74Mrh5KdfCyen0sSaqDOZMclo4QPfPZXS9gl +Fo7uy8ECzJf1el6mn+cYR4H9NBkA3Q7LT1pSh/u+PznphgAsyVoL9dJ/mppPpcBd +ShqWxhu3/eUKZmY+h6F+sA/3928bwKwz4QrzacyV396dPGXn7biSDGJ6/gsZEkPe +Mf5T54HcsRmOEV/Ox8rijiBs3LN87fAlesAAxMPil7La5t+2sSXyjcMhRE9aoirs +38gV1v6p4zqWcXOCCiVS9xHdFLk5JiFy0OLrB89jlhBCoQwqdw4IwebxBgSclJaJ +aEwKyKQlxKQv7pfKWxQQm6zIiH1YhkYnMiqDDtM9ooVDYxc+ASkEkDLV365wi6h6 +U55YUdUrsSNH9TttiXNx3o+jjbAY8f3+r1aNdOz01SONBWCFSJGfgvo82cqOE4Gy +cNKtaVtbzLl5HinPjbJp0Hx5Gl3P+BECvcoii7SCmDxL9GuTrC0r7oPyWJ0kIpQK +7UnPdsp/H2Jp/gfXztP4jKR6FwScQgPkbbfGPY9XSrzP4w0fH+ckXQOUlBhXwYDQ +sKXGkBNBkebjjpP93GYGv/PLHRrgrFn8vK+r+G7MMCgSH55plzDwqEXS4mQW0J4w +K9LhxhiRFWt4gI6eynxP3gB+IXRuUNutGIfVSLQV0UIqytOuXi4CPhlU2qPInfG8 +iHqD2bF9+tYnKYF8LpHST0x/izkl/UbLeLWYxp8bQ7/XY/U5c7DROIagBZc1tYBs +sEBLqVaUjYAy9bQfEGi6qPwbYoh+UQdexROxZ0wPCknBOgDrtxJLabbE9hxnGVjV +qO7C3he/QGEcCzrj5h2LHI5ZuD3KlCtGzXhQNCepuxoJAWUYFHppqE5gUXfB8O3w +LFhk6Q2gwV21SGfRA7GumvDtR2buwRywLbyrQJZYZ4XXC1Pr8Mczu3EWyczizTfc +mwi+ix+coDWaIyQKpbhcDlADo69YwPPiT+i79XLhZ0L5SE0Cd5jG65oJjMT6ytkg +K2bMPTgxu47PYW8YRfJaUS42WP4wSEBV2H0mD63cg1JHdCpvTqhxDw9s/v1NlOrQ +vUoMhpv7TljR/7aMLRGgpD1CNG8ZOx2rMTOt9cFkiabN5xmdllmaO1p7yvXq8aty +OshknOXPXbPus+RPrnUTujA50Azv50OIih7Q8GMmZ7m24fLVgrY82O3OLHK9+qJe +wM6kPyE9+dTX0DCnw5viSa5AOL5eTFsBfLC3cjVKg+SvBKuWOj/fbrn9x/HHXLiW +Llbsie6EpLqReMWD3IumZq/CXPoHAlJ+oFgoS0MbZqfIyWFpNSQiFEacdeVsqe6f +e+1bCnekexXxQ/eVaXLyEWOgufteCNHqr2zjoOa83iYpe9Bq3SuuekN8g5HGeCkH +xj/KKx214bl7WocoITWSEMREBfmIiADqe1zkv7Y7xWtYSwXNZ7nsoE1ziXYPiVLT +acfkQIH6plCIU4nl+AtOD+UyPtyka9QVmKaiHL745PLZMpbROGd7yWH/Jz1QDIIl +vvAko/yqyRfMawWnNXukAsr4UsoanaLR7amx1RemN8ONf8YMHFzUQrn6QGYN7eiQ +XxkIyw+fNBsquLp8ud1AA7WJie//pgcFHc/icDHVNc/EKF+m9m/0SjDUxq6ncXzg +9IeFJnmXeVbx1iFy2BuOkzSCpsdsJyJqXq39Wjlm8ggBudNNkwfdrhntaaUu7Zhl +cI/DMgCICTcT8Tl7XAO0Mczocz6Siq7As04N3Yks6gIGLQFwkFe9HzvKW/z1m2IL +Q1N22IX1/uCYG9eUqImTsgPwdeFSjFxrmxsU+mBcF0tNt0Lf7xlIsPnbCUFM+VwJ +AdOgAYwpfdxfS7k+l8KjAgNanoR7sO3g03lzpktC0cH6hCDq++Sf34PBMTEGq4dw +pBQinLgltT9hFhou/sjDMGeQFcIR8auKGUY+P+n3Ceg8RLADIukdzFlnpyJzKnm2 +1hUbdFHAQsKpAJxl56KbfQ1JfeADzvfKdSXraacBG3eoWoshPhC0beXaDibDZtKe +//kTJoe2qMrYNGGYReiAxQbK3IuMC+uyNq0Cl3r9NaXo3VlCULNgJ+8iE0gvpno9 +WPYVrENQ38YjcZE1qQGWvmwZqHuVoxlTCXx1/bnNyIZ9kKHbgD/2j9SLBjbqoc73 +WDBRspX5sFhKP3eLt30v0Wq5j+NCWIjDCvOrKypMf9KCQnnx8JREiQuTepleSayr +YATxJK0Da2W/BQ4w0UeFs4cyKMHSu9bO/8mY2riLjP5uFWxopt8VQbiuwVvxu5c6 +JMRW+llNoT3OdDOueT6a5zEdl1/NOk2MoY9Pors7vrIrc+3SoNtu8lsqRMqJk943 +BlRV75Z2k+CLsvqsLWuHfuQO9pXrbrNAl0KULAZcpuxk1hrIe1Xcd4mJs3MDvhvl +FQkPYeWbBGPPg3F0saFpF41O5jDlx5HphwubEtxcHK//h2LAp7o9j4OuMjOFrBS9 +8o9ja5cd+O9fcWtJpMiXiY9bxhR3yrvG/GiN56GQjZW0eBP9vJJdiSD4VV44B0Me +5+mcluKunRQUXz3EibAobICX9au1nfMlsxP6pteCucDwetm94hajt5O9KeNoKKMB +O7AyvITSaY3ij7fomkKXibd298JYyp8LwYWf6gmsk+gMuaCHD4k4+gCi7vOMRSnt +Lr6CUOpCFVlE4RMnNSW9S7BEtz4pHwju8M12Ft9tcympjMeW6yo6x0I21cr2LDcz +rcrcAd5O1z2BYwFdXKS/Hw59hclRvXFIXcMbSsZ2gQ5ZUL8QXej+v+V5dlslEsEJ +Xn6w0WeBZ0WDypMKLRyDSVLMRdsB8m5xGr4sGAc7JyTeYRFva9wvc/ra/4PjnT93 +EZtvRkWXCj1slPKsVJ+ZQDSwJm4ejNb3a3UMfXv7YGdapxdZYn5Bk51mHDEZH7PK +5raEVlTUySHqzZZUY8B0hFPx7crIn1bdH5Ke7OvgCJUT8X5mbAhu9heGkK6+rwOw +P/iHEncY2Q2tvm57rptUS9cyNTatR2VNjNVT8KxXJhUwfSSAy1A7Y3EWlUtVxOje +DaiCOXDNwz8hCfKkAFXmNwKrdY4JJcY7c7Zj8o3pRaPTL+NyavHFYiTc6tq/Hyqf +dVBJbyZz29pCpMJ3ZQsE8axV2nQDGg+HtIvRHYYe7PKedUjPvJ4mXlN11v3aIqeM +Jw/ZVTAX2Z4LK3e2MI/48L+qr5ciVTC+Hpompoz/JC/6oh8JQ+MFwshCvtBB0pgs +dS+NbBvUtZBxp2Eyl+tdmPghTEC8gG/Jrea+ozNwLf0qmuOlZRSeR7VXpa0sIMUZ +qE5Mogw4co2trx7b1KHwqIGoVbwQtk1Ym4s0vLRD1i7ma5XUsHVlG58xeaaR5tnp +nbZ6LRn2f9ZgfPCCeLL6phVDo/8eyJBMfnSAEnO7IN5L5pIfeTpw2KozH5RwKlTP +EB724/aKKAtAQNc0QFrf72Rg0FYmgxjzRr2Xg4PqnyH27JI85qwdROlZ6sEKCk/E +afE+ctB4XyAY9c7gvMvBNleqN3z89D7cD7g5W21UrrBd69h/DyY17GuUyetThvlk +bYNbfjyagZjSGTitDW/lsTObtZlZ4x4QGmLkwFQ+9EIX1iTUG1J2waeKbJ2Q8h2K +tynno/UU4633NpxjR+FU8Pvn5k/DTkpZTw7REwr5e5tW9ZlcJy1ccdemATdbKfUn +Zjqh4IqUnEbHtq0cnhQbOrCMCLk+nFXnrwpwf/WTK0SCMyYhHHdS8f3qeexn04ta +pjKceQNbwbErN5+Buz2vA8VBnATLVRoPzmEktQeFmEQBFokmNcpUR3dCWAAvH3uh +Ryk75AWdbGMbFwgqLJ0RWAwqSBhlLS9OUI6AhZ3aYN0Mkiaz1YSZkNzNibnK5ycG +tc0mz7Tr/4wmVRxiEYvv6Ki99xKGognP0CEPdhc5Q81lr6fg16ThIgDC4YbS7Zrt +8ofVx8pw2N/S8aru7J65UlBxaJao3cdm5m0tA8lPqCw4aNee0NiUMy0Z5o28t0/o +EF6A8QPqYUZ4twXTWJ7QDKaMILJG0EoO/O69De1Eu0r6OzEXhi1x6/jev/oPJHwo +LUM5BQcWIPP2PHD+kH8sP+Zp0m5CvrN9dnYjOPp48oP52VKGjKBM9oysBw0qVhxB +0dL1quRXL38AuDYjQz+ra2ymPu1AzX0+L8q+s6q2BtOJsTER/ENupjsBXPXroePo +ld5x1mJTMcbhftxpC3TZ0WZQsCmtTkPXZ3ZnXXbbzL43FVT7Ja3zxiFi3YvFSOqt +RPedTFBfyT3AknSSLFIXNkSwV2hAyZfBEt3W3lzRdzLjbov/SG4KsqYMZp5OOHjl +3rrKnccI4WqBch27fys3/JA5AL4AM/1QXNWYR0iWsH0ds3ClUa+JS6vXVeBtisOL +VigSIOgoTuVhEZsffTSSYytWoTdtENReuEUa0/DakYgX3AokEpcyD6/mBvhi8Oxi +0TdF3PKulY4AytwSFD4wAKWXdLAqmAnrsUCaBYlKNmyGfZEi8ivtXiv8F5IXiEtv +k+d2IuYeyMekp94VtKjzoA6qXGLoyYfoZo5rfRYg9JbU0HoXbIiqOPCOs/qmkp3H +jjAXchaJk8sZfRFwd9GoTSsSzsniTZwB331QiZav11Q7SpSACKRilCR+AkTgO7h6 +qtiaql+m2pJOlIxiDEeJUu0n3+kMFOjQsxqgAnHj1VHzEuimNMFHMb5qAPhZqB/q +lm1keKwyt99y/6HpL7CP3YCDg7fULKCvoWyI5wnz3omwNdot6ivTO25UleNccWvK +RBC0BvPmADXkJlZHiyhIjJvCMnZirV4maXZAX5LVWuQNF1b4Th7oheZr7EdCyWVF +3WdF2v3DZaEpcJRaH4pajrLiRDwLK2lG/eJiV6iarOIg5aD/ry/WoerQ5i6BvsWK +wY5z8PSotFz27IPrrPKnXKBcnyvg1sGf0IP0h96HxhG5jLCO/bZls6cRg7V1UhoW +eXNYC35FjacouV3HR0SSB2uhRnnnmhJmgauObP7lZGNHAGZj7THC/NtlKZMtgnSJ +WSn8/7I+pxIkbIP6BgL7GwNjxZENF5e5AvILwVeWvDnOw0DqitpHlpoh1czTWG+C +wSndSPco4OXzHYBFqjS9ILoxpdcJlkeioLfY1rB2AZOmb5w6+kVRmxBunf0hb2ax +p84WJKCVfA9x/oCZCXP7lSnncoE3G6RYWwcoSYFrS7jVEbf0D8dTN/cN0V4j0cqM +SX2yekw3bPIS3nUlLiCyfAi42kXprfdNubRTrV1YG+7ZZcTHE72M/1AUWI7jwg4H +zMz2WS8bvAWDDjhvPTzdUegVmFN3E1ZzMrd3BT2yFMdabjomwqz7nhmeRCvPuKWS +3GzZYm1eCm4spVMR4KCifpF/peh1AmEbxip4IKeNzwP8bpgZMvGHzzwZN+CY1eCm +eJuy8mteMRmANMsusrfJSNIEoMWtm7pXkPz7FqtjAqEuyTnBfAXSL31U/D8SxTtO +yNm5BWXgeDWjQAigfzWUAoxRRqnIg0mzimFeMLvW583BQ0ySAEtSiVZsqRNBqZDT +neKt87VXKa41abnQjRuXgFJejhwMjteVJY8Seyh91hTgBuBtbuTecheCQre1Hdgj +X42qAz9f3mDdhB6GDfc9iefXqgt9wmkwc3dyGgrG74AJbqVCVizJj46ZpOcBFzHM +6Lszrv85nR7ui/W+lSlev+j3fKqYtyZscI2wwIaj8rWpLpGMVUXyXe11MgTKoOb0 +6HW72+gJ4DlouEdUOJOnW4Dj+ADFuBZEFz81rLtPuT1N8HrbnhpgKuFS/yQFlyYm +GFw8KYUApg793tlt2ru41ovcUOAmnZYzXpYY9l8mmpdXYYJyk64clR9flozcMNwY +aq6IZaowfvjdRXD7Glcr9ocHYm+wxrzXmMJAm6tc85JIVhhFp68Xvw7wrmQhl1XO +V0hODw6I8Ni+f0gVbzH7pP/Oehpb5E7y0ILLx5Rbrs7hNBiKErV+fu4TDr1hgTGD +h/XbjUImtsFUunMxD3KKRLcIFs1THCnKYzFVS6QVJ8ENYG3VCD+MraucqEB0g7dV +gRQGHiMfOQRIiGSlxM5VZUSjCSMFFUzFfNgsxM+NP2hNA+Y1QJgOtAv+jnIFHbHb +tMQZbMCY5vCwM1gOu5v/Et/Gi2Lw5oH8iLEcWkhNg5mappUCSO/Tw+AVPkZ1YdN+ +3vEw5Fm5Ym/dxFwbB0yDrwCCb7GoOmhVddVxLYhJIIkrHfG9WKAb7jVDvSLfPuD1 +OX0aQyqTDCixwZPi4OXL86VvSQ7jC2G9evME8T18DxkP25TC3dgRA0AmiBHIhvTM +Zy+MwZewju1yH9NzY0mCegA5lyAXPb32MmO4YcQHmWBZCVD6sOZxIyVDmajCKdz4 +HqUEaN1qsTdBVh+Btfw09IJQ3ufImnthvGANQ/RhgoZF3N1jfvXtNofc8z3SZSSv +EKe6/aghjzNQ19l8EGn7ijhANB03YuWB4NMakt/53HLwrECfR7Dvha18Y7SUQ2T2 +t2YnaxIGgOt8Uo5BuqSne7ZGlg0OVvG552yAjWcNHRU9WuGL4Hzeg3K7IeuUhU00 +lqviQj7nPDyRFk9iJRVkeI39yYE7RS8n1AWZkZVFNvyUnfomeorHSGJiOOI1gE4e +M8NZQ36hRaCTUyfm64jDMTydPNXII+09R9buFUKnZALt3d5p8z9D1IKTTPpdJVlr +SW9lTLvE41nKtnrE8MGGJde0OZYSS/UAfnATzHT8A2+ctArDs7+u8OWVOV2wcvEb +l7FC4JBVX+Tm28FJtkajjbVKUv6AllfKzEMuh6/uxH+55QWtize053mHPD65CjsU +Bj5Rhv3yvEYYAmx1iDQnO6PXpIit88x7BdqfWxEhLPQGykvY2eQNaLFBZB+aka6e +26rHJyLBq9duiDgCECwHOXl9VuXsblpzbf7TC/JWr2Nz0y2pRatTGAiUvMHDRlpj +YziU/BdSw99KTXzYl1rQRJeE07iNha1DmjS2VpvXsCa917oWGoyu6EAY/LtxbPeI +q5ryNIDKDvACGpXEcVBFNYKs3P+yY5TorTNWmN3xW58fN2SZWnNcKzQFng+i5kLz +DavXwfWi7rpdB4id83dvLD4kD9XrT5C3McS5+W4URiJutCQJ71Y1cETHOGq/PpY9 +YlswG6X3+CZ3zGs7pOOw8KA7kprIvcqOzPw7ZDJl2jPy2R/dBDx4Y7Gr616JWcTz +A6DQKF9fvFgJeYP9Di1K8KTdK+h/9LoyHiKzk7PmCy5N46OTu7pSvb7fA/Q31W90 +HWZBcRF9sF3HksprBSM9YLbGSHsOKmGAl6FOtBdE2+U4VypMbq3b0r6OpkwW8Gkj +6uws2cRk5SUQRvrWbeJ5oE7vGBrp99cNbEHzkpApFWsxkWGEy349132sY4CptIr4 +RZORO8R5X8Kwq7N5N9NOPQVVMXHRa3XXo454IqsZnRFXpLA5Z5i024vQ2md1kw2M +nta4cjUVuNXSEWHBWLB6U58ZohYDEKc2tWwnKeiz6/QTG16ds9Jw0794L1NzTbyN +iw80px9qTH58Ng0nY0VKVxmWNxRaIONkDlwrhldpVrsoA+4IHUa8veY0C/8TW5o0 +k4WFBsiUAsxasU9lOS55an9My3rqygpfcrSQIKGefToy967m1Pl3nMcOVK/Ms/4l +COTheMrf7U9Bdt2j8aiay41GsJgLkRpsV9WaHGHiBImMjikLxmOwqH9C5Lm3K3mM +UE28CW8UoMi30kkAJy9DoJ9npxu5A4GP8nwaS9yNMddaQuUEbWXjB8Mz1W7BpHHI +yuUoYvKNfUJ1de2h5xB+PBG9sTyUX42PO5FE5nXb6pBAOTfLQ4Gw1+g+67rNhrV3 +sx5qea6T79rPpH4wk1eQQOkVCcIwJxeDCb8KI+Fditja7kPJG83hpCeOf0OTk5Wc +IS5HIZc/cB/7h29Y8kPlT/8VWUKfnS44oESj9XONHlwXl/2f3FqDRGdtxfAN43fn +qQMla6UyShWrOU8i6nHuiVk5B0V5ObZhhKjmbeamAKiaczAsrtanYIYxeNCLarBD +8qfikdW7kbDiHNF1CtjlDk9Es3SKO9XcvwH8ffgr9J+uLlVBzYAC81Ag/HAQfRoV +fyNY+HXlwOvJBpCPQNtiUfJkpwppaSu6SqyLSsPlvKB8/hXqOjHP+RGUVyND+CJw +W1c1R4HICn5jYrqQkSdiJlvfAOarL2d8mzRKCcf098W+zHMzpMqA1CLAVB7UHgLF +Yl+gjjJhVHjItSxMnhRCKy9LNA4sajVmmTRgj+tkrmtYis639bZKhWuhJHxYVBFB +pprpVwwvi5VH5EOEkqWHPaihVdusvXLTXO20sqF2gGZ8FLdoe5iX0F3G0XnJIS4J +Xc9ApGNh4dS5hj5tITIRwOGAsYj/8369wBr3VrtSjYkSwg/n5L7NKkLRxmLv/d6I +zUVetXHHYKc8nC0X3QChemOkXhlvg2L5LQRnnGQduYZ2J29giE7yMsjSGFWwEXxX +nagj0d8odtWLIln2z4StOyqxl9Y165Hw/OzZinbuWO0AFiXPigqFoxLUct39GCLL +J66nIBYilMS/9S0stKUb82CnZ8+DKueHSo5XhYxnWXk5n91ZnufSmwC0gMFtanDD +RlNnFMV/ak/EcLgnVgNuNfWg7KbLAmBTHUNm+Nkhx4Zac/wm530SjCz+wdaEhE4o +qTxhR/1XhV4ZfhPnwky3DAFohnkFGMsO6NhRGH8L3Q1i5Swz/Lo0P0aOesM6TW4d +tfhQTUvWk3MLTGy+tJvbY7KaI8LEAHjGhlQoVYRC8FbAJTDETG6DAHmlwK6OfY0b +2QlpkaqtRrW5S9qxxXOjGBqdRuYTd8HXM31BmvF86bAKiYST4Y4OdX36Stlf2bwl +Rq4oXDNFYUGOAmOV3tudTnbH8BBbsHSH9OYf9Dw8cxClvNA7lkcFVMpJOcXYUwAJ +anuzLk3U30TBtd52Crc3oE+cR/lAnNsgJPc56NAlsmkApD+zMri6I4K44cwPQLSf +Wyha2Y0o1Aqkw5QG1BPTTgVUa5sGIeVujDS0d86odqFP8Oqu45ek+oU8cGqPRBeK +aaS4xiD2ZHyiexPp+LGApzogq7KLiRsNy88kXcDkJyO84/r3vF4zMj/GC0FSTaws +6Pz9yPt27slcSEwkD/CWMQvBz0YpUJJJUPnoMwV7IuhowfvYK770AMeKhEkUgOK7 +EAlIPHXU/hyxK3bfA+Z5jrQZWWeGHYZYErbbcX2/dZUA2ZePS17n+Pvz2gthJwPR +99bhPIFnrohb+DzA4pGXEvQvL6cyOCNeacq6Tc+k4wU7C8rt89UVbdtlxKY4APqj +qckIQWesqwrMHz+Sy4jZkHRQiLFVzDDiqjYNnDIouVz0oCjclUHXaIyA7Hb+8MR5 +iTikDD80wEIhsKPooqM6lPEa77qKRnKg0Z5RqkmFxGrXkroKmyoCGFQHNjmxHQdM +RazDBT4RlByAcyHXkG8qcEEPOP3uSw3Prx9M9y02dqqKyBaF72zevg1f2z+5CJ+6 +o77oPE9DUJggTc4vjKIL0ZEGT69isbu0hjrLsoURoWiS7YEyJChyCEDcyZiSUxBW +3z2mQO2dF2hDeFrB+JctH7WpFUPZDpbQobCnSA0A0XKZeDuJU/Wnb2cT/8ZTr21g +ivYf1yUgXsvN0mlgPBnUKmQRfHQaUj6OZgYnv6swEqbFyRK7S5vuvf1pq2gMQUv8 +arXLcf7ireNXSwiFGbgBzQTe4B/McrM+32WKcMXIo2XuaJebOmw/2d5QqUDqU+JA +XedPP92vG4BhGbGh01oItw6nYmAqgcnPB2JnF/lDyvHuypji9YgQiAmOX7kBB201 +QchNZ87nKL6Ii831vX7kWz8p3jL6fqO0Jf2M/QRNK1hi+XNDFo6Ckl9dr6mXrJ7C +46VxWE8G4dQgt8Hg9pPWt2KtcUHuIL4yv7+eBGan9nm0WEh5h1fvTAajWXzjAaHL +No7nmSqYKE2BE/oj6GN5gAgCarLsSsE6SYrRP+NAHzsnAWH1FNv0gkD4RsZLXABm +DmppIeIrq+RiapI9LaPfmEfIA7uIwGY0S+H4iBDsOmXtzvlrHrtMct5p+FzM4XuT +S19LOM3OJJs++AOeBkvRYpqVRcCMc/SAf2yqGRG1cZrKNIbfWas9q45Wz/S23QDs +lLH6guDQ3tcl0MOkv8ZxUtQByBwvHInJy2i92kop4JxHjpf5wsHs5TWYVGGwuwII +8VYnUChR1/znYr41BtkS9DA9fR7MqKYhxZd0fJmiL6MJqtmnejniTkO8A65+bUXK +rIVPC7ZnBghz0OYg6vye3jUqhsP1wIWkMFsP85z+W6cYU93Jw0PB6pc8GBxlNLtJ +9K6pDpKQBMhbfdxauI25dmoMf3oc68vzVmSQiYmbzk7IQQrRJUUmO1h73LShf9mD +GckMHN7AZ0r1RgZrwIYEmCykgchHEmZliJ+Iua3063VZIeMa+NYAcN8GvWVhV+MN +75C/o1bXcT+KLUeLYU+KVnifzsGVDGdHB0hsbOVzDsi4v702hRfgof2IzhWUfTFO +8xkVTpLEiggLOwHw4qnN2+YgPd0FnDh7rm+ATXFclErpLnEHuZ/+jTNAANzqvw6I +grA6YEvZSHx0zFiBnSWmdL/CgXZvD4+DNvoZDPjBt4n8wUcr7EmYNCWRoLCNsv+s +yMAoQrcaLDxjekagyLqDsu7OlyGcPuNYQcokyXVWpboojjshMsEXkge2kfvmeeh1 +zCP2V+CygEE9+undax1ClLzdFZRk8R6opsHJUh6Haol4xEefSIP1iQkeYBllObpA +1E56ri7UzGCv4wzSZ6TrAg+jCVQ5eovlMDqp4vLq0TxHwRQ9PRHwF/39V+LE9Je7 +7qwiK0RoKmHwfd5Qo7hAygKN02isT3vBYFv+N1mBkKoQ6fw5nrX/hMbI0hCqtxLY +RwYwYvHFztAqeWnYEZqeH/zIWhtVbCNW8NgvwSqs0YjutmShdM1+E9zE7+DHGWx1 +JUpQFDZ0r7/rx8IopZwNM3L/502GzYHvemKcdccfG0ZiIWFRVtGtlKrZWgKpv2OO +cJ/Q/W4pGt38GGYacT1fqF62g4J0Eyt4wI2WnmXQCpVKQWYYLUCsGIMbaFZIZp0a +bHsccnurAJ9LNKz3xVAvHouFdP2WMGOx0gO3d+MXs8drrnEvFuOVPW3WI1kMYFto +YB8W2AhtVbd4g7opOebjr3DL2mRXokms42dMXSOtRO6RtWXzIJW10KEM+D+KJqLR +lBkZNVnGYKSu196X/4Mpr+DOfotdnIHE507qkaxzLmzQAM21Nv2tqzAjsSuvp1V2 +MM0n9uMw4nOV1vaXovbXjJ6Emu+NmEg8Xj9ikIi59G9fT/Akosy1w2SqB3qV2c45 +1b2W0JYuYv8YVIOmfhQw1sVR9jGSCv0WbrLptMfPRAiUqvvCh0m96F/wehxnbnWs +i22O/OQxDMHsyFq0RUTMnVjRf6FKv5l/JwNb0qprXMgnUoj1W4JvlFvNbbwHPHFw +srtzcJMMJx6YL7TGPudK+drfJ6kY0NGHK0J9I1t5mzTkzyPFQWzRTli7nQQYJnWX +g5HEn9jRNBr1jMBjhXoqJIksSavidFg7tZuioczl57t0i0d9IrbVgmKOJU5g5X3S +EdwIgaJxDQuLmK8jCIsNuZmRFp/KJUIR25Ep3+58j7BVqm89vET4MvKs1RcM1v0O +qaAsaw9MMWVHboNIAauQ75cfykZuWZ2A4MkhL1KC9oxx6ZD8xigjenvyqebnnw0t +0ilL8Akw3NIAixCOnYcBF24pPMLVfoVTfy14O4YZtFMVGmfAYC94wBQ1BTN4tpmr +9x0AP8nSUQiDcxoxEHyVFA7jvND/YBOlx620KoNvoQGzlKF8PZqG8dCJIqGlRtHY +N+S5lKh7xnzFUla6AIv3bz/r3r+vgiJmLvwh5CkkG23EQQuDKoYAeHbvjg07NoAu +ja84TbDTFgLCxNcWFm/NMC5gM8xKhBlKSlRFCT2uAh2M+GFlCIusCcZXqdGNPl2E +F65WGWS4JKwGAGqOMDZuOgL/qmV1GcO33tJaVbiyv1T05fMyfmtIfErIvtNXl7KK +iufozOh/jPvUcIY/nbGdnlMiqQktelgHdi5v/XMejrepdvpRoYogTi3JPGSMwqE8 +WUkEG/P8KIIWy4pTGkdjfJqnLUbaeyvm0sDnQC98HoHiB5aHJXCNe/LDBUKnuvuw +aG7xAgmUlWAXTlv4HWqo3gnFQFgCSrhwAFeT0xtCavP+wcYnf43stGgKtsR9ycGi +SN01ic6o3OhKO1aGRlL5UHvAaCDAlheHn4/tN6kAb2JAUye2y44ROWIydMAzfhyX +NZunm0tVoZCrSr+/+QVOiWGcP+UD1u78hR5691OB5Oh+tjOSVoa2TAB7D87zNNb3 +T6El9bpidObm9P9MXmQ861E1j7lxSJ4YhhlgSUijFA/QFE+CKDzrZlqMZL+Cy4Ms +/5TrUmSsYmQ4P1eAPmleqMuo2akRD9VabKN4E+vFke4/iwkidLxOdtEF7cNTxBCp +XkMbmLHks7GQtxLpYw7OoXzrbJqPpXhBSKyLa54VLX3nQ7R11JeJIrFidcVhw+vi +cQkAeeiksFjvUKngcmdyavkYnpwqwyeUYF3dV6QGuLQCcXqdCgQ5Pfq0h9tq1qN0 +N3qSBEuSCTqRk7agvLGUoTM3uTRGCf87KJxR3e4PLonfnbfm9RPwiB9ivBSrN2PD +OZjUrSwYfYi3J34D/GvJfdEJwkvb1VQl4qSx4aKMnOQ7XQ8ZiPI8uL0MRELmyjpO +phl/nY5IYlQuTjAW2RzQ7vSh6Y/K5/9EzgwHekMmp2+/x8CPxnVOeEHJ71Tc9UEy +1Bq+6++2Qtnnu+/L3rwHYb6Vo36+PEPCh8iLkqrf8XCAEXCrijmMbMythJBb50DL +tpFmuf4P8i0O89ykJEx/g0D/wRFfLY8dC95LyIAYnkUeduS+lZY665mG4uUBCRFk +5werNfNT91El/0/PO29wOWiBjrbZeB0VJNd/irCdULIS5VD5CkjjrQhbqf76mM5B +fjdeXIosWPDVCAbHpuYIIsLHUAvj7B25G/9JCwo+Kn9LmlnPGMszqXphrngiHlrv +rtQvnMSOspx+3ePlW6meHERzV1Yfe806d6lujp0NQc628hVuLCv/XQ0SHdZtvc1M +dl8fN4m7s1PPaizWm9S43Iahjc1mLKdKsnAHP0XEcKeUQlsPRXFmGkSE0qFPz5XB +NrBf5brLA5nAXSCRZHgTq8Vh35zJYEm/HNnlXaF/psPVH43IGpPOZrG2WtdfQrAz +Lkb+sG8lgUpN9b8BNM7GPBJpJCojt68xZBdYsOGi4LB87jYUy6IT986B1Gj5BS9i +kXtIX/bRSfQh4vv8C3p8fWInh+S+J7u46YDwbHUICav8WnbqmeafD87o+1DW6KMW +JxDbRXdYTGxFBR6Luyazr40sAFRd228JDnuPdcRmCjAY5j9I4CqU8kgcq2862Xqw +hHo1r7CnT+mUJOztLiyGW3JEujVfl90Dt/i0dQJcFIEhAkWoL+wk9ixWnvbopdZz +v9x+KsKdTYnNEEIjCcHZ+nTnvH6arB/POj74VDR5Y5m87xEpERl72AaTT/cSjqOX +hLjbeKPX8y+ghTREDPgnk2+kF8I5McRPUm5yKjNLx2IPSNh7ivnuDHRDbVuhSlGB +Qt80/Q0CKEnopKw2QohLxtGEdoQV9f5LebCr2jtrUbW8S9XamY8A+OaJ/mo4Cl0i +TtcTtvNPAtxvK65Dsq7VpWH+auKowLiKQ69WJEAY6frKUSqlLojE5SC7nJDSSQhk +LicP3qIAaJC9yv4Ji328dFoyVX3wh8ZOFC6q+fU3KqyOSYV7adfmeNq9lmi3dhrv +iYyBRWdox3fy8yHTrgKgA7LPYigiMUhFrPK5l3ftE/N6DmdylwZBvaTCRRnSTTzL +hdzkvqmhwhj0CDCY1Q8COR0krYt8PtgIwYYGIcvHIxTnhUt+QMmu32ozTlMrb9hH +zb4A1t6j1i0Bl8BZmvwnD4awj7yqvveRKQalmowHP0UuTEndoyHp1Iva6lfd7GNu +Sy88jl50b7f8x5Z66REpOm3/AASDb2rqaOVDM9m3XOrS9k5Qfj76l5kHCxpwXmmX +bUgm0DEgsWPpbGiQE2UnhxQ9S9fXSMQd5H7nuN0YZva9tbDd/RB9Qbdp3gYPNAT/ +YVz6NXK+Mq5p+ebbKWwrH6Qp47ZfYKYhIaX8+xZNXqWf+Lny2ZK3SzheuUtmN82H +GbhSddCco9bjqBFCLuL2+Vw5kmpAVm0LiwSX9X6QQ/dd0AUblC/Gc+jR4aAYX8UH +n73CfZY1TsAkTJIaf5MyAYbwyl58lvMkr9GnBhlW3FjMiEwzmLXUUnTs9Y0tcS0/ +9tDUe7xTKqk9h+GUNgLbfDwCZE+wwKWWrCfOjwUoxZbGIwT0YrdisNMWEFJxCnNC +LAKShwSC3LbcMay5pYHSrDsxS+jfqTu8JbT2oJKrQk4ecYEG4z0dbv3JxFYB+L8R +la1S6YF0vROE9HtdIf+IYHv61vMLOAHFiiPsa+p1J13EgI4sFWGv7VRtKqSFCOr8 +K5zLW9ANlHRnr8y+ya+KEqB2f71KoEivpSj8Bc2L7PLc74HO3/gM6XhfaUP9pbKV +MsL7jcJcZ54oNwqCwUrif/w3SDrHtmfvYyjRaHp9zZ2O1QUdGsXv3FQl5KZYQk8p +rAM6xOZiv05XfSEdDtvYBUuSTNGRoh6Gub66NRJ9wDupH7vNscRAWwHdjycXGBsu +lZHjDCfCDIXUbbmXI5POYVHufa1FhDjFscVMG1GxWfnNtLIrkXEim7ADBaF8OaXA +dPlaAND712zFcTFnWU49yCKOpyvrUmAUGanIsxofU0feFTa0HCbKr67sayR3deSv +DkIBb8vZ5vCZPhIWT4mO9P1GU91iE7/itH6rYJ9jHrs/g5M+tzL828aOalCj+MMh +WSs5M8yPw0tTNrdzJrGLfTVUjie8LfmGVFqXPANfeJv6UTEnraUdB/AWK9ySFZ6Z +qK+NXucUuIZFnS3pOkFjJBs/Kyv6V4fBynae7LL+Inth1IsBG32voxqh61FXlKY3 +EQpbtdoczqHlAhog1gNTS8Zh47HCWrf9xAeieQ8Hp2Dk1EJL+9rG1ipDX2Kz9629 +slNZXTcNDpB7nykBrZcE1n5MsOjd0HqS1PsDSYa0l8KYn5fBiX7ytakQ6HMMQM3G +dnES4BvExGbJSoyO18WtZET9DmzEzHxV9XgW6pP1g/6H++u4Z4g0TJkVmUf1Llqe +ubVFexSH+d9mzXcX3ftn0Eg8d7SLeChfP3T4v9EfutOgqFSb6MguxWXqA2cqcbIr +F2ZqFBtLl8sSIamBhNzhTJIEnDrauqeTWs8zJgas4Y4+NNIH/P2jis9GrxeTUhyU +sQNjUD6aq2/tinKAv2SlFN22e0vB2y6rErUlSegjIDBLEAEKjl83Lmc5UiG2bkPg +SGeaNMGqz5eTknrSt8+8V/vpkw1tkI0I/qwzU3gx7qbrmMYeell1jSLuDGZuC9WZ +v5Sv9dpemtnpBOOvWelMMmdN7uvSOaHzSNW1hHfbtrxrNPv6GOj13Rdehe0N6824 +Knsf8DxyLovYdOQtsSziE5LkcElJrggOiS+C/pgJLFI728L9JqFA4wfvnIUqOtvv +Nt0cm+WskXo5KxQlzWgFzjvdK0ZP1nvgNxLtotKCOgifeki9GPBDNpqLeadxol7t +tBih4i0ULeULM74k69dqbZDf6TjDi7ApxqcWRHJ37C/g8yS5+B0B1L+kEENrBRbD +trDEwNxB1ykpeFOm6HnyaNRuuY5OMNJKMLnteBS49fkeDiu0jKqqcKnVyjYnkS2+ +hu4oX8cJmlHEs0wcAZqB3vjwnphl7d0ylZMPn6ttDiGQsLbqCg0mhdRj3KrVADS7 +KBWf0k3ioesVBKNU3A7Y/CX6qMAYkmfars+ipPEdVE3FIAFWxCY/O9FwhehWqqG7 +tOUlOjKohrT+VrZcP8HrMr6X/fFT1/ucRAFETBhb4I7wSKiZb6ZOVDw2wCHhrC9o +FvhfrGGgvczWghDSNiaPAd+UlYw6W5l8yzAn0EKlEqNlLCU+eby/6pBW9K7grgHd +WOAG2p4Zj6veaMC5ql6kzcg56yb8sMQoSD6jjsKnAUmLSGc9WrZKIeULyKDtemV0 +iE47UUjaUbZMrY8sIHi+OnOTBVAzw5XzUC11V/bW1qHRZf9nUuCeVoGDgxwpM1IK +1e9RnupqadwjdwnBCE3qGNMNU/QhEyNNfH0ApggYTOCD7NS29ji5lAWetvOM76ve +U5FCfWOWwja+isxkoxTmUbSobujwuERYXXTgqNTK2NSUiD0A8q0b6/EEtIK/qwsT +dMIqAfHpLNeHUnhwhOn0ng2KbNF0Vlt32Alp+xDuzvIGPDLvY2bXA5EOuXv0rNZS +/h7mhDEhtOL06UqEHemUl/WJlfEqlMatAp1tZxgEPFsd1bW0N+sCCOZtXitdbJvf +3Yt1JREyGjkrEiPrUHTTzAsEnvhszBlMc1BCvd/fimsUV8WuH2ubmyVYtxqLfTrr +PiWz0FUb8bAA/KCeHorunppWY4CC2t0qBAup59kdVH/ncsXFKU4WSymIbRpF1S1n +zvXU7isDuEcEfV74m8Xt71XFbRul+NHxsiVjimRm0JBqcyteEQFIBtN72ZK4D2Mf +Oh0wySHbjUOO54VUAgZ0Jrgq9v0wQWOKeUuTV2iefSbcawaXaQU7B1aeL3cEDuM/ +yFcdm9ggjmE6A2laa7+5M2pEGTr/yiIaMpgCnBWNwipQzS8flYW7Xy11qGl+/uA2 +5FyPHHq25Yqa1mW9fPIqHvYjqWvgxh9MDERH/TjQLFaT31gPJVM6TTAyRbd8OZfo +aiod5JXcpECuTLxb2xPm1KqTXinm1a6o6UdSHmvofdisUwnU9Go0tPuPvftpgc07 +myRVK1T+GHaiSgb0ziaDm9btvioiiERgQoHXqcBZBdNCGm8JKSrAIMgpK03rKXs1 +/0f/0vUj0lOg4ak0LSiLXE1ck5zeZK2FDQXjGY2RNmFA2RG7Afazwzu4o3HCZuom +mH0hUzvLoKeEd/EmVkO1xbqEU2UaBDYKHegnWKL4DPYLUI3x7LTqivC42J6v2tQK +e0n64xzFcnkmCP9AwomWoRdR7Wj3+Ko5JfjWLGLsTFQuWWnexmoAgbzUp8jp/ddj +n8+uEwUu9ls3tKzGSjD5eluFYV7gW//60OYSuKqq7DFn2Gvdcu7nS2RW0KVkpaki +lTjN16/4IjjPE1xlBwS6BITVMCGmMqURo5iOYnHUjfIDuePEs73VkkfCELWUJqVv +6UC93bkVJOPXdOC4yhwXA2HyNPzeRE+X0ySk2aOSRAboBiuq8JmnhmIdWHMs0Fwa +3dqZiECrqNmr9K+dTrgyMeLLL5H8+ksgF3g7BB6+hhPd/Pi7uC9cIEXqbFyQaYRy +GhNiT5mkltOiqQvnCJ4MREAn2ZvjeAf86EJXltW6D5pgIelb1zvH0XF5eD3f8xY+ +44kH9fILRAaHb0k/aHwY1puwaOsoa7ZDN6gx/2ahqtllLWsoP+veCJvrW3OcYBTb +mdFi6s597R/nuNMnKBqyXac8WP+YPj6vmHWeUxNZM6LrewJzM3e7fb+bNb3b0A6F +RWXoTMAJh0Gk4wtVZHqPIH5nBXc3ltzpT0cX1vGOAnl/UQjLHSblobZVEyHiZuUD +ii4JwXZmSU3MLVxBgD8vILW2SYQakkvVTyxzBLixB3rkbjMzanf+FF8qFJCcFjI0 +QlHFipNcA7EKtxC/UOwNdsRl/2nuwtteZTdV8/Ahvc2/0Ks4gpSgeD8HhU+2yP1k +ijxBc/+hkjpaEa+S5cHnz1CjngTnu06qNBOR4k6c9YmCUMONe7RhQhdAcUt7JECm +RqX9Olhor2NXwT9MzQZ170BTTjW9LLc0vL+U/MFqzqaSxZ3PYGwGwPrZGQ+9QYzz +r9z7fHC/oZl0f2JFG2pAGcW21UOTvyZLCuRh/5Kkjy74I8qcCRH1+mJwTjsacFhP +zMSeVCzXKaUNB4vAnViFm89h2GEABYN2vCWDsRUY479ZY59MAjXAgBmi3joR0vwe +FsmOoYXRB37t4slmCC+8lLJxFeQOjrKUipXMYeMamLxddaEkPKyPQcP6rkLLHm/s +R0259/CXU48Aq5aav9cBTZbSRysN0BRb+BsFxo0DceISTPGYtKK8MF4fkac0MYaT +ZOVouWbxfZd4iz6DnzqHgMaTSHGFEDXC6jh+PhmUBsfrqiwDkAvBzsSQmV+CsVae +oVHDUStpt5iCjchPa5aPKeGCLxe/juMCOrdY4cpUVHfexeKqa7o7gMSo68YFpYzr +G5C8cBAYTqXKMSCPOQHddZsAg9TFVzKGjl2H0Kr1JDHbwP8ogw8o2zQriafbAVLn +jWvs4t0W3q60Q9rYR1WvH5zb/YNoH2Sw82+pg36cr5kKH12GFxFe+OS+pDF0nLGb +Tao3fZfmLFLM1zHE6dk4X/T+HAnSjJcXZAPBisdUq3Zzh/ate/G2VlSWOi5cs/wJ +4pz4ViBFoy6H8GMZ//vlkoXnxIcnKWtdHBBsqOCz3/lYi1JcG8Iuw1ev5YGfSGQ6 +x7jFwCTiTmHfp2UxCqqdXUfFUiigyHnqVcwdKcUesWQq5uzYNxYQyqRunBqaOm7B +QfiPa6SE4Aq+nkcpoymq5nyVDZpyFXksItI/Ma7TGZoWYTfPx4aqwE3BRxDjAHzC +w2sKEfLmpvx/bxgACXkI8ECrV/TusrDd8799G55RZn2XKAEgSW76LBZYCCyA9nLS +2sjN4xx3+ohWYJiUMK3F/psJZM+LiIhWncgQVsoOovUPazJ5bBc7KrtS2+bfvCxt +Cc9VgiOSZuC73v9c4zVGl8MAWgWNbLd5cwWzpxOwfbe5lMfdnBGLNi+VL0PkHoKp +55x77XlNc76eQSp3Lahdp25uwuvi4Z9z2VAwA7CyCUUpPApG9TcZ+ZH0tkw8XVEf +hPA6mD0SMB3JeVIBY1cpJkkYqsUM2aNm5pl1s331ihk6FgJlv33zPf66GzhGkid3 +JjId+mHlZixxiEddIVGxMj9heJhNQvLAbUsV3iniU3m450h2QHrQES+0AVsjnnjs +n80nXDItc5ssOA2ISVzOPxoz7Sxl16dXY/mm3ksPAJbKz1D9H7j6IN9jJsHATX4o +QHz6px/aMyXxCYCe7IYwFbtcS/RC7jk0avy0cLuzBTV5XCQu0iHQsSxhdAVNN88E +i5+0EUo0ezmu9ucfGscknakFp/ybATF+Nk2E5K/L7HGnEo5+y/TMaiqiG7jTUbgk +bQmmyRrx3BIppvldZFFkq5jHm1B5Wx2YR64QJ8lkJFBjCcpFMMFQNaMw3rL5X2Zj +rX0hzwgrNHn9yNRj3hSbb9BZTNRzEaa1uPfftMQ9bfXP8QCY4wKWAVPV4215Kj/Z +mVgFn1uyeyoxgsMh7a8/OiFdIS/9F51Mj8402F08lB3EQ2mZ6wlb3KOd0YEtmXtb +EIgfERW/jlwijoAlBqYboNd5Y1JCG3Q4860zv6SnIQlG53o6gKAmYyGDlSMUuO15 +u2vayQSP8UsA53QfzntWF9FcNfxX6cQ5bcEWS0cnogODcH9ZkZezx+AsX2suERZv +N2pA3aNiLs+/w+kjf9zFswcrCGabenP39SPbUuWPGzRNVK9rOtOELK0Yl8wqwKUX +hkb02FMKdnmKk5j0apUjFoRrmhuqnaAV1pC8VFxWUn636/1cY8oBCZFZCr+snisS ++mYRc/rwrPpzkapler+/RfUyzJK2IXhFzf5CtWAlGpgOJjIQBJdwiDu2TkEB626V +Ck8VNg/PyJFTCxcdrbWu8Y5RHxo/HHJQ3lqbTSeZgAqqetbJxDD2YHBW4WTa8rga +FkzIy26EnNYvwljOzy85M5ZnBO9h03sT/kaRD6MSZNY9ErYUX94umXZ/4/uHyiG/ +OwBy9VwN02JNBwxU8K5qKYTTCcpJ/z1upqyM+ew/2j1C4QMvkgqoqWFnjtpyc2CS +85RDXNVkl/K6hgAxxq69ylb1HuX1W98Td6NwKdAPfooDgRod5uUbzK4Ncp5KZlNd +8T2x7HpXJXfQBRrilQU1HIhGIf3t1rHezU5o8i5EEGUHM4Bb7m1aLw0cevdG9If4 +u/lUT4shHdS3KsqnBCb8iH0OdBk+Sq3qxOu7pvbgb10JiXrflh3mVaJ35UoWX0Vp +2J7bYhaLkHfk2QFmSekb5SgC5N+HG49IS2NdUqz6P5Ob9MvPQKMAM/k7Im6fTtMQ +yyR2DBDjCZI6TbnCYQE2UE6rnok3SSA16v6SOkfYLq+y3MNRJMTRGJpTR5Mjwf7o +AMb7mOEkBqJH//Zj1BOZwunTc2/B2DkOhxcfneBHsT6TwIV5bMcmyBP4kJlyLd0x +JExQAhmA9C1H221F9CCiz9Qd9M8sAM9hnaL1OKnLDrWH3BnLs5u4/fv35wazeynl +ZtCKdala54+iWQ6DNNf5M9Oi+gxw+g9uK+9JioAtYTMfu3vVZtlHd0sFnhFa+BBD +DxbI0a30u1hbEWzO9cZ1Ya4u9ZomaAIjUoWCJUqQDcsgf/Dem7b+vV+OjsBdUQ7z +S8M+gbT1+pohf8koqXc+Jj/Tfnl9VN6H6NsDCTC175pvoU9518U1jZBC1fBQ6b9L +W56YVscU7GLXha51oYRpgTYUToa3n2x0aStXwkAmfzmCuqY3XK41Zef/vnVeAIPX +/5qc+fzi63HZCAc7WBmnWMN+5GNJh1OaW5vgj9ZoU5fQPMpo7NTaoZultqY9tOxh +Cd7LjcqvmvYQfER2A6s8Tq9vvwPf4bg8X+4BywQfs/tBfSA7f7ChItELH2VCY9h0 +ZNeIoAx75w9zyCQ6ace3yJpa3fDAooh7BvdSbhymhz0pFK4/j/ic3W9V8GHqc6Po +tjWOgmXqtiexior1/q3QEH2U+bblIOpIRmpIl8trBNAkGd1Roezf7zpQ3Pd4DR4y +PMsJGf9FIT53/aMMiNcN5I4CMBP4cTb0I44vYCW+mugT9Jmr5hXO+BOKgsRzy3o1 +w2YTcn0e6abI6fWkMEiiCSBrUjpl5JS1gy11ZMLmjItC3PwEFiwTUTLm0gFlS9id +TdHDt1yPHv2cSBdH2xzuFbuXTW6SdydZ0POAdO+pJqxWXpkzGFhL7LOOqZPOhmIG +b3SPl+9CaxPl2HQQfYU186Dluwn/CdD6ASh1lkq5lgcuLXxytZFdrlFxiUOn5D+c +3kVGlqhHKD57nhryI83w3V/T37IYC4ICEwhbfWYxm3+QISlHZm37wQmEVsvS8Tte +z8RFR8vhbrzD9Fo18S1ESbrPCVg8vtiz8+u3l/aaU/5v63pqS2l9Km0VbZ1kr+UC +2Plh/bcu5INFqXprh11jsSrJ6cyI9qVZ2ZyBEuu4KNWHsEvewYymENQIIvric1GA +p0OT/0nBSFzZ7ZB6flpbMfB283etY/lzH2DtatE45yPCyFTjMuJTMH46G907uNp4 +KXw3xq9XUKFCfVw5v11Wtjqa+oyGcSxcZmaQJfSiCLJm05L9C5l8fFbogc7JhpXj +Lp6bv2Z6H5X0t8frCt2V8tMWeCn/K/vrvGa0RGqMDotAcRUbjw2xkakxA9o620uC +Lf8ZceinuXTvz6BayZt9OxzZwTn1XKQwSWlS6nJzMOkCA1tB0MKYOyKPsxVHrX9u +rMecxrAKRYRwn1EwspSd8wN9mvtLIQ66ytQ/NiVOUB3OlMduTKNKBeZd2+t4teVd +hgGgynXdjARnKPPoQuTbMUtCoInDihCwzzPzp5btVrLv1ycrTrfTpeXOJAv95L0f +5+tyVpRnOMAg6rVDCleHxi3lnXHbZAKzX78C3JXn7zjwN8svQp9SLstMr1fafj3X +Lvoy0kycUlaWw7sRtC4sjrQqwMr5QI9IQRXKCCrHH/m8kqsqWIrhuRza6u/xzjS5 +T03vf7hyOD/SgvYSYfJNoQ7FGCRTPARZnUQP3It/pgLwpQhX7bAJwcNmX3TPxs3A +iqmEbVUV3At4Q6SuiDfUbJKNwmWTdVdbItjyPY/el889i8i6tHh/SRKEVvpjxA5s +cTwQmJOcFTfz9VlhhYc5AeAghgAEIzE+gAV10Y3FF+CcljOYqwh/AOc7ls7SWIJc +UCHDBe1u4P+Ob4s51AEzv1fkcXBtyvUulZGFV7IEb5IKeuuVGT5nFTqyftfpO9pb +l4ZlZ8C4ct2Y6hKLDzhbPcaWmAV4gZpdHFXlYf3TJGFgjoQr13m4FHB+BzqA1z6d +HYm6ZYuWyfHPDth7Mp6F6r6ot7e4nysvznbHwoy7mLP3RrYuC08voHZovYkK0Dl3 +wCKGDi1jodG5gQtoaCDk4zAYFqHx2VJwR+Zz541LX+arlNJZXrjMJVztZCEcfkbS +JmgkVmTxAsOpi4tRhYcjNViN3jLFLJhgaA6enXaFxuh5GZFXL9FfjttqeM0D7I6S +EBAfGNs3l0mqDjvLAnKqPwcIeuLdEyrHGugoTH536ywoyUsaUCdxeNmZS22gxPp6 +dj9zBZplln5LVpY83vHOGHbF4QRGsFwHL5YJqXGm8ITOYAkhcjzCi+WBiCfJP7fG +gCEo1m0Avr6kmAwEzOANMKhY0rIH9EeFq0ZzuSa1BVfcME6HgGYUkWXTw/aT5qfK +yytZKDSF/jE67EluE/NSs/ufgF8ySHvtI1H2UwOSDgxI6VeugynoqvT9hWngn2Br +bV2Qb6XdHL8BFRHIn7NdLd2nX89QsshzAbulaqXM+OZ6jZDijsbECNbKXVFtTR3p +Y1KcRdumMujEU5flIwm4ahWfus18kgGAOqBW4kfvX6NyomOLDzb2KnWHkyx3zMRt +K1mlPB5HedsPY3qffIpRtPPJtnuJKWc/gU1ylqN8/njaYVt4XsPbOPmWJFiboIiJ +LDzGMQ7sqbe7I+bIrWfb7kt2JZK7U0zsRd12VdKItWCJaq362n/n7QtKtdhe75aR +7NLny+O5ZxsWuuAlflR48ij/ysonqjbHLJCJXgxBbaW0TRuz5kMM36Ji8FbZaYr4 +vrCim5P+aWTp5noHfMXsftoVHj2UWJ/1e45rPM3myhXHZ5JSyjB85/ViEdgq3WQR +fAPYVxdhtzkWt6YxIi84OSJr0Pv1wMiTNFQXkPl9xAsGjnJN3wS8BRpWy8aqDvnK +Ex/c749vTJh+uDuFu5vBT0fQ9pRV6/lRsGd5vC6+hbiTYQb2WHnkCeURsO3KXRiU +qLPrPWEbwj9i89BztXyMy1s0AMEk68HZum9AD66dNAmCT3XH04Mn/6l+UiyEnhA1 +RLjc+SXu5CWVthHoAZcJVw5VODbLTbRTSQSTgGrC8HTmC9KKziE7isSYrY0jhXA5 +SYGzk9BCGRvJIoKRiHZGtRDkniCrrKQlFu+XQGNX//k8OAMgczquP0p6O1LTCcMa +HEQwE16La/TKFJ4oWYc+nFToYozhueTIRVspPa8IoX6Epj7wj6C+SEeDztRbtggb +hHeBtUQO4LkK7sq0Hb+Q9l69wrWESJgH19oNQdjIBXHnxzVMHZ2nNJgYufUtNZSS +cWJzwfpROT06vl0ymGpqogE4b8z+eUJmAMW1CHSewH+NCMiEOKXFbn9rsWG52VdH +A8tAgoly6uHFWs8HQhjGxGqz6712opmn6kwb8E1F1os73e9UuSWu4kj79/puvHCP +AlUAQ2SFnaztm3h6cu3NTRJbaT42pMeS6bFfJPcZPeGOZ/mlndhs8yFSW/hY44u0 +xUEGj+yGxA6F7LUq6AHLDX1ZjURPLa+r9956zpMiCweVKC1lQtfqevIA3JNetWWu +en14ahlcqbd3imYWP7DxHddDVrCjoc+0w7k/s1OVPbYFv+r2W5GPKISSwZsJmwU8 +U1x1A3XYuK7ukemgnkgqTSG2gNysGNN9e/NQ2Ld5nLxaTwsrsNTq3bDGbhji5cNj +gq9Gz5lkT0QKsDE74a/8qySMdAys3kFFQrQa0H0iUPXhaj90o30mo9Pd7ee0eFsb +5G8qmoS5bJITBsALaqPz1VjK6ZckbdsQndailmCT4A7PwQ5Lc1JBnBEVHE359sTg +g65p42FOR3k60DUKAGsHB6wl1UsqMG9Ln4fq789RE0wcL+C7Q1ijEObQtkX9x6Gg +zyJXgfnR31V+A4A23kDRax5+aBT5w+BE9QNdO57HZ18hLV6NEiF5SLt33tde4H4A +k56/HGxwi+MbalCXph+3pYCAV0X+kabJOMbC8/yGw/Y4rP2otnACaeibcUF+tvQY +X2lHMFHJiKj/QBZm/nqdtMkMX/6CWtXTPpx4r9dsY6B7klK5LLicLnxsXMCjpllc +44WxhiNlabs/ScpV5F6UpRu8+idwZxmVUxqi38nlsvXv+DblOZQ8WgXewUoiLhRM +DHN7qV3nlK+/gRw3afm49oDQs7Ee+/N7eW9A22W+FSON8zuLlKXApV5bnOJPXCBK +CXcFzDkUnmO70AImpnJiWv2QtTXrUcaQkwT3wXbojOYgfvApywRmxubPpmFqM9wR +VfuKX9rjzVzyj0i1sll+8VtG1t+aAyVLQsNkvyp4X2wMf5sh4JyQulqwLZDIhiAc ++4O1hnRp1cCqkLeRINNGs5pTY32KRZqzQafTajZv2MqbQtctq2/juukkme6F4VvZ +bV7qhwARy+gPkxW/fZMBuokwQ+B7HatawX3+0amFfF/gecg3Ms6DF0GgMLBFijIc +r0Jp1aIUDY/GFoVkbuT+Ibqay3KN/CthvCb/xS/+y9XvAHbGDYA5QWB0cv5HlJx/ +A4/51hodyWPP76so/SNjOvNQqPl8Vut98NtAAtnlDL9MKWz6zc/ys5TH0tJfJz47 +dYW3KbjVfJp/gEEMeWuBvueEVOIb1XgJcHQRlWUzuqfp2xYFqPjMVrIDM/kT3ZF2 +3yzZPCsj3VMf8NQH8KUK42f32OzbhqKSYjL2hcbPpDOjjp1hudG/nW/JfvlCsmdZ +I4LI2Qbrz1ZWLOJ+SPTgwN3d6o7f2MKWJukheWdx+1D6ymx5JhjXbOk0JOqDlFMV +rH/ygXP9rabwlR9cBgfodSIGwbBk4DUsaBVnDTsbRbWouLqjwqRkjDDHzE5i5wQw +QQJcsukMvpbplfXWxGY4wxuwCJuXI6TMn8Zom6cnzpYEYEvspnJovL/gd8893EEa +LFp/qmO5zfqN4udDrtvpNzyrWM/htRWOAIA4NNdNI89Eb66qz3fSW1AH6OH/MNzb +kyQUVpCh6pU1axPpCPjG9vFPrnXwfZW5N+TcboE/WWTjbZPjqSbQldeWnePpPmUj +dAfyRpgSvQ1PRXSZUw6arN5J2pmgWIWRCJyPSZuHj5pG1l/W5549sXDYJxISveho +mrg6BuW+DjlknFZLZvmsfOV4yYefmeaWJhlzsfT4BOtQY9TQG7U+GO4hSulbaxFb +B/FV2Zo04D25HBK1ga6/e7vQYxD8KIcvnOmKDKyiJgEL29aIxn4dxUpY49thnMQ2 +NdNF20jPkrKlrmaCD54+Ks77rwlzIa5t+a0xYSt/FobKtt6CfGaAMDjntPYAaanX ++7Ss9PVArTqxxVpgjYzusK4l+WFaz0nt6VFfBsHK+rDR729sPhn8RvEnAgrpbnJ7 +3fuPPqV9EniuZtymI36HS9dc5FzcgPfbDX8fVerDHuhHGRy4FBW1Sy1ccLF7yPly +Z6heJZ4GkbJ0WzZVi5fAY1bGnuYVfRccqQhTwQOO7l1KJf6uvB1WTHPC+y4r6G7m +BkB7aqlW/+kIjTOfJpHoC5cGIovz5VifVgv5sDBUCLSe1uUDTSCkGJlB964b3pr4 +BOewdNGTojTtIxq4mZ0kWOZfbGRUU7DCghtdEDBCuNtPMJV0HCyMQO+ftEmbopzX +F1UUT4tzFLyvu+SAZVKab6ihpXhW5pZlexBtw9GcgW9kvh7pNpetNxUMU9ygzPtr +o/yE3pMmrmANbT29n0Sj+NWhJT+gtda3gipIqm+qLZn1FOqRmBdsR3j9vKuSk2HU +OQx0TNTcBp5TNKtfCBu8dllupUMKyRy4YN6YlA1vfpWTH7ajvPTaCMAsjBayJWb9 +ruo4C6dV51svZaNPVwXxRqMZC9zko9R7xJ9ApMEFhmKnX5FVUTm4oqnSdXTx6nMO +n4vCD+jGgsU3/aO2CmPaR62qFTU/HdJRtot4Lx5eEUFwVQkec4zYop8xE38AyEWm +uq/OQk9vaUFWEJT0MGOdE/oM5TLaMGyvcAIXk19zOEn0CFlPlvD3gYSPegJIccrw +9q9USdZfneV7308MfPsQ1/lhopFss6iovdlGz4m7uxHJkYXH9cK2Gn8qxLJF28NH +8kmC6LhrK0cKuZYyUl4zJqAjA8gpkJ42hMLM4PZf/pxXJMyEZd+GLPAOpw/eHS4o +bGtHuINcrETQ0fhwp14L3dxBw3LdX9ej3yCrBwO+dzIdm5iGTfkPArauhbZt82gm +Gh617LC6Vzko0pwiuKj3TcKLwsfWjkV0BopttW+9/I4MWfrgtsmPCekg5BUWTZJ3 +sqpYCPKsH5SyqoBhIOo3Iq5ucK+atZQEp5Yk1Vg7/GP6vChW8XmOTbckWS5gWiMA +QSv7bdJZgzCLLoo7mFSrVNslA/3ia0A5X8RBKLQQWZBLm2lwKyU4KE8yL2LS8A4Z +SvIYRhGoRKaqIw+ehTNDlo63YaUTyUPEBT2pcR+kdv66z+1xSIQiyAwthZIOIslL +Rciggdpdiof0j2jzTL9F3K2eSQH8EFVSbBBnpEgGusPQkhKAJZ08tjF/kKBesHzt +mQs2HTnUR6IOfKispR7sYK+vOzdLVjzMOMvcW20W69s9ydIAZlgmn3vuetXxzYp7 +rJnZV9jZG29wmh0rmDzpa01KpKagD72yVJoje29ihNa6VzTGLIMwxiTyvNsYKN+e +zl+RMs3s0RTKxl0wXLveXRZRrQ4ImA2R5itBeKa1u+//4SVNL8W11BTRNgLOjJIC +SYdu80yxK+c6B+2ID3YHAvfxP/b+Uziv+AWSbouWOluzogCr3b+nWk7uTcDUf3Pd +aBfJvMuQ2YXS9zebYncfzBhrwDYoPUQc4tXx20Ub1P+Pr00h0XJPIYgCXl8dVwRU +7kpzShEO+sxea0ta+kkebG+UIox3j/RwruNXTepnUsvhXKRZFSLLCpG7WnDZp6GA +EJg6etYLK6E10y8Ss5q1F9izAjqUvnnEXZqzw0Aq1UWR1dStoefabvmwlT1Ihcj7 +4uyHGha5+Mgf/kZZYEW/F5EvLYXoRQn4mTQCw2CrKwOyyu9WoDjs56R0BCJ5VBHG +6Nb7dFXE7ECZAU7TddvWma6KmuQIkA6R5fdloHx/HJ8iKBlUYgJb7OVg5w2NPk31 +/RuZoIeJJkUuilNhT3yBhIuQZsdvfsGek6lu2Q+3Vgt8GwRrh+ubZqWRcKJ2wuem +NNIxzSaa03ljUrF92KZFkf+hbjuXqo+k3YdFmAq3RpGCBdJvAmhLusfFQJZLccRj +PA4cugThUMzt1YJDbj1mOBIzGxDt1/+ykvM+bvwoGbZ/refaO8QYiplrniAWf6h1 +aYQ3FR8JbXkALc8fhFN3KWmBRMOnTl8NcDirVrmPRj/HYbzE1VRh9KQo3HcRRmgc +izq3eDVt9/Jty9NaXza/BRIuZKVK6hIct/A/htz4HqNwyy/ympef+KoyOQ508Ffa +yWs433IRdj/PKG6jviZiy4WpxKjECTkoYnwEbD5aQJRst80yTPA4AU1aGnNMqy3j +PBZUX46LOOvwL4qABhKFcFbbA96tY3B6HZCjmCy19Y0T3KIYJNlhsoN7Bzw0FUnd +xiF2N9U9R+9ybJE4OGsUEKWe8pNsefsEtlKkFMFpIB6XFSDhaB9sywRRNLd/PtKC +d+6QMEKADaTWurunLadHnrUhYTKTud/D9aVHMAq/wN9wQExmUDVBdG/BnxxzAjY9 +JQ+nTr/veENeYkjIJ8Jg1oi6wgBGyCo/izzIu3GT+hsuyZgLmSoA8eLdOI58X88B +A7PM4tm1zyDw5x1YZiO1+Iu09yznTSTArQNXbQx7vSI5b/0URUd2VAVKTse5CPqh +U5RGyTVirhxO3mc6NGolqtc8Z3zAO8eVfTzCeIa4FfcazG3ZAyapLQs36PTtozq9 +tAjanPqh7dgoRFRZUPFfcd4/IUq0dU0nUgsji76Q3duwmNuNg9GYb42weISj9WY2 +P2wLz6iEJpEnNUik3S3fUhnwIzVn7Sfus1GtMWdrV5ow/MOZy0f1iVAA0b8Uo666 +1be0c+SzZIxcm/P5Sw4Jlg6euCO2XYschfepIrKv/WRv+CcAla3ZbQVOqHN61vus +Jo8zkQEZGEcpQj0vmYy7FRcO0TYp5cTkxWPrQ+zUmQAbw8WFtnPKdasvAQfT2VKK +MRFNZkV2L2CWCHssna8kzmCGYF/pmzzhTy68QvUZtNoJ95ynKjP9+zgQ1KwVaGon +c5rsxf0ze0m/7KPQ7lv3jJnuMdWujOxihIsB71nMnKpVxn1GHeFXz+jcMOUy9LZz +VJlRFTkxG5V0F3qzu54gr/ROte5wTb2Kb1DetgaUL3tiWrd6zaA4+Zvg/C9SyCDW +ZluRuFnOaB5gE1+b+hDB9f5hFdDxTe+XgGu8AJKzA7As9jgYaEc5j0Q9tBh146sg +ras9UqY7oXS2tyBV5Zk7Alw/zMMZ8JBRzfZu8CTD/sGJeytViG0wT0Byw9GgWcna +LHfZpI5jflNW8Sqpd+IzSsl0JHMGMK1JDPe4C4NRiZcWF78DlQPh42hJGVwe/sKb +bN/lPJCGAO8+az2mHjbCNiu3IYCXiqlj0kGlMiZJVg6Eq5gSDuvEcSZbbiN6xPxk +AQ3cpEKLrzhXzc1F8/y9d/tSxIEQPG+lwN/iJm86jhfcpLKfBAE+tFJIpLiizpJC ++43fKIjifjeIGdy1sifv7rtMuD4xwg4GuVYdXXNrIAiQxsSGiRfwYq5bWRG5atsq +3n5rsskpekQA+EHglrHBTLEJrP3NnIIQGJlU544ZpyIvei0fFmDzzVbJqdH3GzOV +ASSJzcIvFjEMw2H7SOXjtre2ZmhHndM7ZmkMiEjlb+1tCtGQnKh6PUrJW6yx1L7m +3tusqkPfseWcfcuxW4o4oOpkAwOeV0DxbGZGEsILwGsZykvH+jlC0atM/1EwdGH6 +5JDmBEStC3H3+s4G1thRV6SUGJT2XiyPCQgbaM7mbvO0bZEysBTyaiULaFZffzn3 +lYKNznunskmGGQXvybrrjylgtvaEtk0rEPZB3ivSllqqXKz3AVPe7ygzJZRxqwU0 +dfFAagy4uxU5P2qR5zwzSfvYgNFsYHq+iWyruBRQyR5/gpC3j4Gp8WzOINflcgIZ +i//rPJ6+ouHXAjmjdrqA3VyR5lmJVhP4YGbax8r76G5A6wHZkwnjXceScpGXrCz8 +UGkcAlVI4jLyldCHDOHshxKcyFbE5ZUGqWgo7vi8dmbRotxAoxXIwv9oJWeNEwm0 +vv6Udrec4nJxQJl/bEkBjqlgKvOPwE9/Dpt2rLGOURruWFjDcE2sJ3CjL8Og9RzS +v5zA3sV2nSJzOyltui7PnNXQNUVOfxIjCD/cj8NH9W/437EAIc+TNiJyfnf9Dpkv ++ft8uSM+JmBCj4fHgn/TEZSj6neUxS8c1F7al4fTFWPXsc7bGFlpgOeMJv4MLPkq +wp7eYqbno9nCh30WSsxrVL3WI5J3cYRkzwQuXakFIePxDcgGSsLYtUcyTcfcoUyz +9sYmuh0VL9dLKe4nc0z5Bs4rM23Um7caIw8p3mTfxspXUWqWFCxzV2FapNl6Vfoi +IlM+Xr8kp/DCbkAHU8YCvh5o3k0ze2EhCedVf1JztW7td3l2ftcgRwof2CA9N4DY +Q3JMcvCbMG2b6VELdBul+W1lr4BnzYlY7V+TaNz4pNscTZsET3sNlSaVEw4sXTMh +xlHw6ErBskCHKVMtgYTGp/+4bYS2nfIT8OT9T1vWofO6mJQlUYwXYSowmpAuEYdT +lxz0LqiujCZWe6YzOLLriXjvFXGNnrVO1VtwHJbqLYKXINa0qq8SrCURFBPngL89 +tZEtHPsl2EjLJOp716EJYjOutFm8FhNKPUGwYTwtYwij5ZwS1YfGZM+MNPw3J+5A +yx33sl5q5PbUuClwJdtPYmpkhYYbIsqY5KYOFkASnVGeIXJ07Sq3b0V0P8vQcuF8 +qJD4egiA4cBmVAkhl8cRBRgNApOa0aNgRlln0/w+mSZTU3W30Cb7buHiwuYkr4n3 ++uzJwPs1/jMaPvRdZSTLCZEH2fwGUz79bmPBysln1q7zl5cPQDWvSPZdBCm3ONUF +VGtCWbVLJUHUCGGyopsRvqsaoWBU5ZvlGRrFrmtf/vjQe4UxQ5VGVUZMhfulO7cY +NkwajszDbcD3a6uD27bihpeja74qqVMd7TRue3RImRUOL+SbLR+nLDkfVVZsuEm8 +XmHONgt8Edsm9+I8rtfZjYhUJtJWHtBNV1mLlr0k8zbGDm8JeP6HUSaQUEWdU6b8 +sZMh9WXBfWEhO+xDtHE7SYiuBmlBSHNE7jfQNc+CC3KQrYESjiaUtyGEs9dRI3dS +no4ctGO2RNHjcPeXuhc3zoqvs3KOv8dI11TTTtzod2hBHvqMconGnx4oMnLZUJVc +0XhGLNm/dnfv6M2WomfbtsDr4Yn12dnU8aq1qS4T1Pswk7IhTj/aAZ5/6coZtBQW +BRn181If/WBujd/v/0UZV3LBu3+KDGgaDwgBrGlIEo7zyZK1oeLNi1bZUmPQJz6h +PSrQR0U2+qY8ui9v+SKEoe1rp3/IzxuR2NHCMcfEIE6ZTmBWvawFhGG1VEaHDUB1 +LCAetCyQ0HLSaDgDCTBrhblAb2noar9MgltOdA5tszaZpIHPSljP62wGDrT6k+4E +KBmAFywhw9sl4AaD/o+1xlbZzGAwubmCNArK49QWrLJIkRnu1jW6qud3ywD51ATS +vzQXXtthb57sPmGBeTMfQrGL1X/N3IAhyzLwHUBivygjtUWLHtK9c8Du0Gr1nkb2 +MCXt2GB693+t84fm6gJ2VXjMkiMiW4t5RSXTL/tHVINWOEZvAqY9jqLRGRsZwJpL +S6MLJp/G8Fs5yhBZprYziayEcl+SFnuEJy/QJDThiEhJNcaP1ZGJ5ptO8d8B70+f +1XCv4WDKwBp4hEokfxouyecQ5+MA3na3pQZ4Dx3gY+dICNJPSJ3LhiaX1Gf65DqS +czlJJJtbmKMOMXyxmSV4gfr73XoSPspBB0HJlXIyIDdeUiPaExlPrQlsBiBo1TjW +/8C72ZJHNJyVgFZx7RYjf4rfzxy1pcLfwv+HqCp4gCN9RFuzCK1lTlCe3dnS5Hbt ++0ULVP4xAF3+HEC+CW/J01Ee6o7ZiNgM2ITMPFlUFGDaH9XbD4RYAc19mjS3g3Bq +nXk5LTQYkcMPzB9mcwWKO8BxSJirRBsYMBgC7Cg4OZvfSHBj/Xq+HZMkD5hsSbH+ +5EmRsTsqHHKRyWd1R4YJ6IZ/WaROFApMQuorH4EBr62PShzFHwWje6LcoZiA/Mxj +e1qBDQbGXxH6IUWfpnYk5VIvs3BwuS+kypeo9H29dHIMX66WikuLLVY7I+MAc06C +xoxI+xVANYp8t+k7LeYx2g+Y2dy/Gqj19z9Cibw/9TFFpkzat5lxWLQNXpajH3ZX +MHEZ44C8HbSK3+xIdu1zVbaoE9CXOaHX/Rh9nnH+cFZ8wy9YGROC8EHXItMyaAw0 +8wTe6jkaSx1eSmduclES85y6z0ZytLlUH1caHmt/hkRJGDaobUutZaQYiYY3Z4l+ +2k6ra0zk9Zfkp3HVjIIIfpIPmylB6t0M69aDevv+7B3FNW5w97MCNWj0a0erWt0N +zoIztjfdja7QZhjIEP1sWqjK0vAJlk69UDGwmFNn8UKAxtRzQW7KSe+ZeJJsabeW +2LROdXfIO5A93GzjVDMymFDO61l800uC+94cSELWSQpkjjDpasmn5TWMh4vngeuj +p0yHtFP6pMDEJofhu03AQFJqxDn4Pqpsy1j5LaZ+m1m2Xsf/kxfNFqwDAyFYA9+p +KH2m4t1UNqKqYgYWwC9/igYd3SJIwmcpzHGBzlDZ48akkxeBqqM1jW572Z5lLzf4 +9fNGCRjY45ligT/EymsIj+FYXnoTpBwR0qoSHg5kFQF1HImqi1u/sABPYgfD3FyI +CE7+sgoardaX9iTuX2UspQc4BgW6/fBM60dgmGZPOE2l7fT1sl9xe/j7+jrbLoCv +migHUvOFfJw4bWR9w5xD/tjbi7ZykYvSWmQARJujemwX5+pXeWH3hJyJDAORA4ti +0SkfKsPX/o4ippM7PijBzJbUpMezkzwKRseYf1HofkPBulFBRKqnWxD2Z6G2zjzr +4epIKHdjyUER7uhrfUFhpESwwCkKlMJ4Injdo8bUJ8/9jNmK8aGtTOChrVIUvsoK +ARgroOIg5s2C0nprcrIntEH5Nzvwb6epNvWFciO1RWUKPcf+qqJxwJIYiRqAuog/ +0mLiGVHMhPVCTGOCz3l+26m7nytdDRz0JuQ1db1ER/VihSucITYTA83auJrK0dS2 +VvedSNHCNNjKxq4x/94JdLFamjE1kJyHaMmujuUTbR70yICypbfxfjGTZmu3AFOb +I7OqlcuDYpwlLLDSZbT/JA8VvZxGfrZmzOry84s8DHIP1l0M+JOZgEaFSSTqa41M +Ik3R+twBHNnfHQf4DGkfh1iPi00V8pxfR52YcFI39EQzMy89yF6NaeM78dFtn3Er +p06PDBsszRD0BU+HRR0YGJrSzBbFoIxpeJQMzYuEYW6rJR9TIxOrFIbz6D5XKB3P +lzaHj+XXCPOr/fA2Hv2o9MikqubNaHNCLS64VcojTykk+4nq8AGCgob1CtoR13gd +AB894TjgEvlXtQWUr+SJWq1y/fSsP5hG/IlBxB03uOiSEDmBmqDsvDg8zAqHNJH8 +bQaT6Jc4Esvjf3LwLRUA5Ey84zhNdOS2X1naAn13nwbmMruX/RAFd//CkkMJyH0Y +uv4YtRcY+RaTfNw7gCg4TNB/9sCt92VAUzpEEMcet310wzq8WeQmtHVJ43E5ggAc +WvwB3MVJ+R5kgqkCO26suAHsl+AvJXK4AWjKp4J5B/d3vxgk8h2yqsHHmEdTJfSF +FSO+9ZfGPfj4sTp1rEEMfO/pZzLnRQjgchwj54SB+iqfGleuY8s8ZLE1yNOCv80f +PMJxogg2/crRP39+5lW8OmFgKLvfXRipAm7nWyWtsjOr/p8leh9WSvR+N4huO20G +ytNisY0nKBQ+i0BZ+WJAcjIiMuRBaGWz8SXmM+lzFXAqAMw8W/5tmgiv6UwJJFhQ +7HJZalW6z5BErk3JBhyJbRZIzKTP41OqXTb3+38+lc1nBejxKAeiljGTuONJZJkz +lNzpRZs0sNUoenysOh7/PW3ia4PCHPXWLYkwOnIh9zzmF/HWP4sUWETGB0BlGkjz +bL4F9ZyI1oIqIJN0C1Ub0cqN2QCNC4TDWp7nmDEfnf4GZZrbcY2kous7TWxhJKpM +3cZ30WDtmLBsu9vzV6cWtTPvETnE0/Yx3ce6zPge8h1P5EIdMUdRDRXq0Aj8+HnE ++3u70A6xqIyrXDvvvajGJB69clAWa29SqowyiFkM/T9Sn816UQKc4BpIA9D3bHBR +8gn2Vh8nWj+PL7oA7C6muOSP9vjNTy7PNs5WzU9+pAdxp2l7YL0UMwgmz8nTeQeA +gfwGAL2dkfLRbm/THj7BzxkUOSYYKD+0dnuEUzpK/i5hSUjjOUqv1SnuxzhXWopJ +vMZ6qoC6ZATcfBVjrEG/rkGj7n1MLO5Un0y60jKreekco5exSsnEik5k9YWFSqpZ +Hlsk4oXe8XE+YaL5t9RPQyu4X+7kjYcym2IFtnERQrTRfVj89Qh6bOO5MEue8qra +SiHFqyIZPDMCTB5hOxLxaIdW2lB+ma9Mmo9mBDFdj8vrT9TsIqQmmLL2e1vFCYhq +X8uC5Ptp1WaKJHkAm4wNp9rjGwmWj9rdGn1MTIJUZIqxcJUqEUvX+RoookVIgAZr +4OlKIasu9T4jkHA5PKq5EUIqVHzcEYXFqgT8e4dyV9XGIrmZB/nXr6qfRZdlD7Nt ++1slxlCk00KyJzcyQUQzesBpDuISz7gejc568WyOsRARBv+HmAr3EW8cEo0gFIne +qKtHvrA3uVh8gNYjTJfKyTJ6HQXlILb9/mJl58jWExopjuuC44gVS68nRBBbNKj5 +cL8sZVAiXuJdoSGdY252ZP085bjsWgHe02SolimZ2853tqpvSIUt6YmvQuXDuis3 +S6t2voHkuAxGAWezLcPhi1VWoX1HRHan2c9EwD6tIiQIgEWwrauJXSau3i6e+qrd +8dYFhTZuA8qbTvd1w3Y4w2xVUliMCAkzHrltWMRQcd5XRrM2JzaxNA0D/rFh3vQf +9jmlNGgsbi9p1LT4mMYB1foKLJ+DhMUeWwbHCEuAcjJ4nrmNAgJ5lFSmLpsJ3QkM +qJoLwrp2bXMYAKIQZlny1B5fQw/tj5NMQ2YYMQClQxcBYBnOBoHynlw0FK37KJwW +LifMXOUZkDHQ2hHq49mMztAhTi4zlgpEK5FmKg4XIF6glerTnS2W/5LW6wDhKsVg +sNs5F/bYB5yqstcXkNmIiq7UI4MRHoQ0zqMN/zwqTzQw5ijyWaoiPVeEosoYCxhT +83L0yKnNhYJ70ZyXmo3g5TiMtN5J6NYNRI7zfTN4aU7GpYgJeptPiocnE8d3LiAY +WWorh0YBE17OXWNMSCAe570+m/AXGTtElNMtR6OcCQsZZw3Ux91PjSFIc2WrWz1/ +vIauH4M6cE0gHI22sLspu+F2xSidJTfMQbZfP6xpvqaWeVbEsWsB1PgOCtlKK/52 +d8Rzo+/JDMy1zKNDHfBjKBHJfZjaA8iDnYzLnH2Bg/KzRfyOVnY3UNnyj+sB7EDx +FasWUpt+SFZcE8Kesa9tziIbGex5RRPd4ceQOEOV1JTZ3lmWuaJTxz7ekp5PYh+t +J0nhdOugtUf46zKNqFQG3oVIGgN+Reop0oAzwT7vuIfjiLYn1MuC7D5ikJHZGqF9 +KueLHgrFWtuw54U1u3yYONZDRLt7BNI0WJNKyNxM29o0iKlg7carznQ3zxhxTZne +WTNfEFt4vy25yJaEAT9W6KKIFtZXF+rZgYcZlLdxwGc3GIVMOyFmuaJLEt/W/vtF +5zel72Ns6w/8qZmQhkjiwTcoVkpPSGfJXD0y5j7x/KCtNhBd7+crADFURl0mQlsG +7QHYVA+qjGMX5ujuDkKVkEBMGEkmo7sXFyZ/cmQpCDAZtPzAUpqwEPFj+G9P3sWh +QxZNW58Mxolo2vnZm94Ia3hn6py6Z0tLThNOGAlU2ytIESefr82BJKru0Sy3NVjz +41fOM8ZlZs1kpDoo4kEimZAsOneu5LZbpavyUs8d1zIIb0mE8qXCnX25Q5pu9XZ/ +e+xO6epnNeh5aHUC9//vO31vE7kiZhZkNuQ6t/Q8i6uxTb6cpbBaGg7KcEtf5io4 +2Q9ZdL5B8t7ThQaZpC7w03/9hJrciYoEUxdlarteeCeRyH7FV4IU1WsQNh/Tzef8 +uLhq48lgRz1nxJ9KDxvOFnFhcoD+EGnzib6u6UvtlbS5FjJPRaIiF7M5uzI78XeP +sH5wqddDweqTr7m7ozBYbgC9HV6bfdhL6a03MzrtMqWCsJM3nTCgN3yzuz6LObFe +Vzx9KNhdJsZwOJIoysv36FQ5BiZpQZhhgNoczowZy9AiYos16HKq70gNR5yCiBTx +IL/m07sW3kQg5buzHFceiEuYOVAYdFQeoLla7fTrl2mwPC9H0kBPsynWCclXu+dT +GhkO748fvRp6NQGmKq3H+wQ07OKgmi1+PqMjUvwAR4cM6n1ri5HMq8Y/xHNdKhTi +007FMXg+EyZxIDaRhIB30+dZILqKGnfRJCHp2hsJos3njnajdjqBGUa/C5UlYh9+ +WF8XjJDXd5G2qwLpdTLmbHvtf37BCdxst+8TsIWRTJb2W/d5wdxBS8oXYvEuoUpA +/R/zOG9tdUJW2TK0x8PEALODcM6QxxB3XW4ryFTFKfO04GtJfPJLY4wt7//DAgWh +zisWm0SSG2mvEoATVELCZWTPZ37SZjfHtYbTp81SKVDnTsv5AxU6Zd2Giy19iB4r +SGfiCeQZq2pgOf/NmvwsRs6ZfvYe+39SUg6KVn6yXcYym+acKXIWM0yUHDibFoxX +8w0zNfY+mJqMM3/XIxU6TdGDE0pFSCH7nNaWO6YkSA0rub71G2CLIc6oP69TJJSR +1KAudDaZtqncGrRsrC/nWcak3/1iAa7SeSIz1q/dKEXMzkPA3MiLVyXjKCxOtU4r +/6FU4p6yl6cHdCRkkiy+A7oUqetE5e0CjBxGRG/dCe+JSLDUyCN7gaj2FQNOKCtJ +djyB63uaUkcDLxJqKk9ds9sU8S9V3LgQlQ/oBuoxDIMeAO4Al3LRjkDPdOIiRLso +fsPou8DnopI6jMFSNoMYN8W5nLR47A4syLuMN5845LwTviHrNJAUBvlypGaxq655 +Nle5gGsmB5x+4xsUH+UCSwOjxT3e+KVpiDlnsaBmbCWghcQdtNCn6vAVGrRNlSlA +ogcMzLrdwjUxjzlDBUy4hUHAHxnuCbyy9Wt+QS7J7v34gd83WjEwiZX6gmy2LTn1 +6ZIu3WHZfFc5fpDT2BHNHMBKSsoSsyVhBtlW2NX76JU/07EKyVm093wrpd1S8uMy +n8OTCoDqru0yWEZNzXuNtZTKcgA8joBi1o2wBMr2o+PN5fRqVdxkM8Zgg5RnN9AK +f2E6xY+YGMJzxBKPCnz5TU7JMi+iHcB1uUbF/GK7F7jBLd2VFidN0tyL+FjDX3xZ +wQoTzrd9oOKSPexUjHBWYq071Ey2Sc3D6XVR+ij5hIj0EG2LYSSErjRQ+AqE5quv +a9tBrDH4HXm1vSyD/GYErTudD9QEVRvC9MBu8SmkIMBRgtmFZgq+c+hYiZmaUhLl +SiSqzaLo8ljHNI2gPO6seKJ6GSt1ZvBBsc1w8xfnXsFlOKnOFk+Ly+qYwoFGKj7K +YgKjqj+cdmD11CujHfLhjJ1ipMavDagvEz9TAXilD4IpUfbHHchsp0uNOo1LNZJD +kkqVrYA4KrhcZImdFwmZ0W84Ra0Vhg96ZMxrgdY9l9bzVj2QNyEUFmzFRu9gqrQy +nMZkg0F1w6xNZOjunpNwHB51nv4rns7ey8jP4B8iEOZckJDQC0W9Sbg34Xw+Gwo7 +4t0RifkPsOdXSRRnhexQM1kM7sMvditkXk51HAUH2/Vdpeh4EnsxmEb64FTvjyul +1qw5jo6izKO0v/pI5bQUsQZ7qdrbLU8zAh6iI7ZNZXlGCtABcsDDs02WE/wtbADI +j6++KNd+ABK4lfxhe+xBOVpKjlPeU2h3KXbCkLDvX5br948Kc21Hlw1UbYdqT48U +e2WGB43hhOvIoZvn4ODj3R/aD02o4AyWCq/W25M4IG2PXiHeNGLKvYGMPindE+Ib +Wjq/P13jgRtA4SU4kOwsudSghfrjm3vp0oSwArzVfe78oQXBk+twIJr8dl15GoSN +6vyvTsrUeohIwQmGBKYMQfndQ4Pn27btaKu5hEvSL4R/h6g9+cSV7o6xNCNgbPFU +AEoOhJ7FRYdxNyH0yKHHzS+7clvOny6+NAmIOelQ0xnt5oajB8+t8aVPhCxFmU0g +s0EEWxh6MDfrsviBVZaVGkH+FJMXldnnRDpbSYsayTx+TOuW8gkSTFqeSso4knA9 +JoR0c/7/C/Sy0ZwC7uzIcYcvJ8ngNpppWKeiIYpiyjejAhQnbpPj5k3S8ZFaC5YR +lo0RXREE+/Jny7LZrjsSpeQNR546eSJXX7+gju1o+ydX/Bpa0RIGQsmTBQld41KN +WPzGlseFP3PXh8Wmif+2pUdSSPyWxF91JMsIBuwRDsu3ZCRSO0rqOYImLzh2Wx92 +B6S56HUNJ9mjaulC8GslaIeha7coFr8sPtZw1x1ticGfCWoSom2mr61eDeyTxfcp +bmIkBVZ5I2VEf+GkeXXFVwF0jrHWyE1Bz5pH8ru6PiWK9pUdBH6g0apRdNEYl0PP +Wi/VAxe/2sBh8/NK7tjsbqcCPYLbUOvSetxxTwQainkNL/K3pBbXHFnALi3lYXxw +VyzBB2MCVQRd3VyA8c9li9LNcRjjLaBl2n+kCvgY8lXAaYdwOUWUwx3NdVpitbP+ +M93jwbNN7nZDCNYOejGOCNa9nEDDhkTqnRznZlFNUSODKKDgZvWS4R+S8l9Xt/6w +ZcbTtmRXhkad67km1XPrkZK+lIy4DRinXoXu7ZTMBYyQacfojq0xsMvSfNI0FCQA +gfBF5W0XkOGywAFxzwIyBqbXY9sM4KQbXmQazb95PWYkLMsubtJEB8DkIbgG+W+D +sTTtJKbUKhJ2FK7pcsLK09xvaagJ9TovLe8lTx6COlVJDvEtOqdtOG85xZJzsFH1 +4k71+8oiKhN3M7RGNHjOzcwXCjp2K57QRLsMOYjXDKB1oWMqjpmdq8usBdMCMRau +sbiKnAjvzSEjAKxd08OvhqEGVeVp26KHbfxCzmeajc5PvV3ll/g9u9D08Oy4Mbbq +ICMCPcPl7TTOaGVfiZqi2GWOyGjqSCHjM7yHXgQdiTPi5YzPQBFW8EXEoxcb4fG2 +ACb/rNzBUzih5wW+YC1CCvYwS5sE1fGKlfs4vW1xK9yP32nBYAUi/cXecewNWnHm +xUkod5Zvb7gj7CzwHY/BQiG9pyep2f3Hl/1tXIBis6g2HtOs9Vk8b2kjFh1DKkaf +NZphFfpa6t16WmnFO7fdCz2wTsuKO+y6U96LLtQ8PCKB9ucOuPgGYfqugp0S/qr+ +nUyNqsIueViD01cQANaVDsfGIjorwdNTG/+PbsLKwF8H1zU5vScdWNqhS7RpiamO +bVt+DsbxGFj+2+GzPtL9ymtIbVD22PHoAMwHvmtdIOvdImL4vFg9qRkyPAxbpcRN +VeKQHNEBbpTMR3FTgNp6yoViTd/FisvMRsyESY8bOyogaHsc41Zneevjloke8Qsx +M3+N2uuhJcnr/zlfqDzUeFuyyyE1LD7dw5qepXt4M5xJwVzQ10A40ov0WpjeQVfC +9FFaiF1LEbooU7d2rFEm5jdu2Qp66y2rHXfwUpHB+91yNIguQqYoi/I6z9G/it0n +oE9806Q9g6pSdTCQxOQhWej4TXrYGfuJiYS1Vj+GP50uX+HRkjcxi+YEBU80MLMM +sgiBPhiJeBw0WZjIESM92c8ILovEyTy1uSpWz1yWhDUblkJT70e4XVECse6KcDFk +yVIZVWTSvRppXn9TvkWmVpcFlhkHRQ9P/MGLuhrm2MAEmWzCLl+1ZjIaRFU6hRnj +NQ5yEVeL85/8jYnFpbyop8iD/WJooNB8ZMFFZaCFbW36jYb3CIvYZE+Rtcvu9Stj +MdTPgbv52U4qcX2OGD+/c8Uk3+/lm10cwWjZdQXZ+ZKyACMEWHjNksgC1pKZKBJ5 +tPSlYyXFPlROivUlKPL4WpgIOXj4zo7rQZXAxucofqjaknMfOnP1qkq6EokciEA9 +a/bC+V+rQos4c0ls3e04V9W69pygmcu3xbkjZizHYi+JEVBwYSHaeKTF6z+sMULz +bNEFIpShY12rPlFbD53rk2cGoUQkRyBspAqwXY1rdWa+g82ApeMNnyfKLopxfrur +VCaaMcmVcYZpGYfzuL+zFNfROMjHWHgVxaZcIgHX71ed7mmPcpT9pXElWkUoelPB +ELqPiO+QO7Z/ezqaUk89+gqlEZVGPIV9i90FJWfEZeulPKYQgUnDdvJi9QU1wsxi +xiE1M80gw0lmH0bFQQaFoXOZo1UcFds7Hc4lmZ8LCEV8JAsgJW1JC3nk3qEOYu5S +YhxvCKYFA48LwdxHWI4HzKPJx0tl2yaOJ4p6Rl0VQQqBtz+kxs1L2QS8JAGKbgmh +BesVzySmztCzh3X0s7ihxxn9bNDaMH73KZIydSN2QssIl3gwUxYy7AW1vqFsJQky +w/Kk4GWrnfTeru6pfYDV1DRZzN5WfDPIUxSVLP7+XV5S2s0DP+GkQqF7Jyk/zjWK +Eg+pTEmEs6jjbwUNfbKzWmDwZoic0hkrZMRtlDhmmnjDTEY0zRnt6aAWIbR2dCNp +l9VQIAzGSU9rQTWQZwLXOd42NHZessgRavF0maQ+JbtbpHQGhPD58H/RGTXHlUtd +0VvIiowTWZFKB1lUDYAtFKS58ifiOKAqVdH4nHa83SoqC+D2GSwXSw+UwhGUYOnp +00ZsyrWRkQpdc6r4FeoskIVLqt8BbUNafjRhOc5s1rXTwN/BQV+YAXOwOxuO+0hK +0gvyrnc95lKWrrrYIkgJ+EzcWxbdv32VZwRpXiRjVC81gI9ceY7OC549cSBegh04 +s30dU28Od8uCzn4e5j7SFyd+K0cbZ4InIXOyVX0cTXFFy9GVTEeSSD3iDFsjPpkw +IwmhRAvpNfhOd2u1I3Q9B3g2n9svYIEK+7eWglVofV9k0E/zFPOTspNT1m0LTe+E +sUBZb8Qqjk6X4LXzj8wvJrzqcSqhxocsETQ2GXilxwkO2go5tN2PFO+rsNCU8UxO +dnsXZq5Gui/Y7YHftMHRmps5ZXRMRGXLm7p0jMJTvX6/LNAy+0qYsnSifINZyqxo +UGmviT6mclaeFcz7V/AhO4cwLwXx2GsOk/SbFKeRF6JbCnYDkE6lRuAUvLNtt2ze +WP6Ng04RkSIoTl5wS2YKTYX1qeMbGTK9wkhN6N9sMBV9kf4qhqwL+gUxo1Lb2flg +iXh4bpFgr6Z9QSjT4sokLNBhiqXYWosHejLgL4QKb48EguIeCGZyaf6f/i10fsfW +5dYrfFJh6nw2DweWgRDNbscAhef9Di/FiwybaE0xo/qvM/QLROjTCdVYPMzzimg3 +5d1HKdWrJYhFZyeFe7BAUd51vhbN7xa0KTz2KehaUJO3DSWy8wz+e85zk7wz2bSv +fT+Sc33fxzys5LVwIYgxAfH6HFd7rxAGsjbbtX8h2m6KxryBioa0TpV7MIlnD0vg +S1E2ZrUWQeP3GP1yFwl8DIeHGtpDcW6fHeOZTqUT4tIGgG5wzWs+gPrWF32tuVs7 +I0fTLhdahfxnVtJIVW1RqffJ3sqtrd+UQhXsnhm/tUx20utwtyU2PQkfw/gdzyDu +1KKr+XcihA4bCUIkVCs72aZbrPloKMA2iWUSR+duT3qbnfkxc9TjWtcbpzTnDSUv +/o8GDc6yTmXrotjtJNeS+lLlChE8Nk0n6ylAsvgn5LJTkPUpE5uKDwtZH74BUSHe +XcDf2WjrRYurzSGrnj/ATmTi6mjSLRoKTTUd2D/X8Np3b4DurBqCICi/xv5gh4sC +nidkPSkm6qCXoQe68ahlAThBmQAlog2XEaJ6RRkOqo+AWhJ6JQ0g0S/+4HrFBLJ9 +utp5HtRTzDZ1OZkXDDUgTKcqBbddEaZE26mM7mo3KP6mGgy7yxykK3nZouW+NDWP +o1v8oWDOMlyUU09MEVWgqDPuU5p7WdJbdvJZ0mrjHN/72g5BP66Av4ZEaqTkYnoV +RnA9BNhlYbyzGWAnXIBW7SwWncWuwnFzmOac7GMX87vBYfBAup9IwtOgthils5g6 +Cd69W0RILzsfRPh0rpblc0YMMZY/TkM+6MKysV7qCDmI0mF+ecrviRsIVuiyQFaK +E7IvSkpvgiwc6zigvTGa3PMSHGU0pW8obURqnHM9NRiOpn8ZuAmdjjrqldAGvKwB +QPsh758Gza5Ncy6VMhIzliLi/FuXQ89S5n/T7bnfwfgprVpbA/sCArJ/0wHyDlKr +zzPsDUKrjvfj4L7vibvzl3WWXyQ5fTkMX8ASY9BSuGw79m7a5NB1slQ/X57Xvdqd +HddB/sTlHPrSbMED1s+HYHacPCjbIIXXdGQ+5wSvWkOu2kuENX/nIQxp/9R1Y2Nt +BwxFeSfkRq7dzQWN6ZGJl6SWL8Q49tWEXvJfi7MDu2l/EV9djprjlfo5U8HnJOGO +botwo5L+zTTw0Z2+tTVGZNSZ8LKc/bSgULnBaUY+0rIXdIXAYhepffFvV9f5CTii +rHU2o+WAu5b3uTziqB6086dsK6DBnxsnbyeeS3xXwe5sIe3UsQ6dEBVSijSgrSN6 +UqkfwX/Pb8UqNZCfK86TytH6jPaopIZeInno97byuKlNM46c49/GL1a79BsOfQkd +ARfHXWFf/Ko98OYjji0Npgmt12P/bzFnC1hzw+Hnyjmlbxvv4SnXyiX+YZR/ns8V +qDVWhBOCoLk+Aqa/oZC75A06+RGZsoPWVtJs3GWRLQApXpete11ey9dEBFJWHFZR +W8zwjPkN3neFsGzq/Yud+hMCXBHREbY4Fl6NXe1Al7zs4nR3EPeqDyVhh0Mk9Hxb +j/TYr0eEH5EU7n4UDmoU2mZJYnoQhmp3eW07RYcqsckf4s5pZLRljex0Q3UgbHha +28wnjFEZIbmJFQmfliOMB1zbWe8vSPC/B5sAXp0VOtGeQrELKRTHgWpRrctJTToJ +5ajip0a5odwUsoo0vl5gJCElSZIAJMPRW18sYx0mEEPOU+Ol38g3APRncM00ShW0 ++D8osICjxzsd//lmOg7grfNtsbHORq7yvfxwSqFlB3pZSu2sYz3gR0gWoEg/NcDe +mrh6/8n47YL3lIrRBGRTScVfQx1jYgSdTt+CPNtFgcdsF3EELYTLNJwb5pkyJy5Y +7UTylWmytxU3G1QZKv7Qs5uXwHJc4+0qFKm0GHZecLBfNyEaxwhix7T70meLoFY4 +O2Fo3N8i4Y5XIM5Lgyg9bdAR6LuBG7MCY0bo52XAUj5HSWqiouo6OQsGBk9heCGF +xTvhxAVHMZAmgt7HtrCM+nkYpOG0ozpCVGiZFH0Mn+eVy4yYHkaMg+m/qLQ7eRhB +B3xTXuhYwXvwZzl/P0cHJb3uRKOWY0JZyL+4BisYilcUR+8BczVpZg8UG+7yOpVU +XAPF9VGGQTzi/suKt5d3WpIcxTGAG8L+0WXeJV76EUIj+vwszkuTP/Q2r27UtQhD +XZjpKtUWdVtobtyb9/4u4OvObsBmZgpDVj0YNXLgrKinlyJHSgTaO5g16gU8Mh9c +TOJOPgGHVY/XLU4AyNhG9mMhKZt2YhSeFTgdae/0b93DGeQho38uxGgF4cwYq8sJ +vZ3r2td5w+vRxkX+V0REAusYZEO8+K3Gy0KoJO8O4nKvN/WWDqKWZCvSmWfNYVHV +cJcH1bdytW1SGEQfhji5aLHZpu4ICHHZ6hNlUHugWMP63M9qOyDqS7TF9ntNdv+0 +Ge72I+2gvlbJQyu/Vhmx7QjTCGbO/xI5UKWHB/uYVBkudGgFkY7XWnaQ6Qi+Crqr +wDOdZvlQ10UkofswXWkpEPSOHN4DEz3ZKA/FRaCeV3yFdvod3X/IEXuGP0NlMPcG +zgs6ZBVJg7VtaUZmIomh0KdjMazCtlx2azwP04pnhWzoK40SOsxtUcNvOfX0aboB +4M6WG89iHiPBZx/O6MLO1IwrNK+KU8+E5M8kM5y8n8YWsluZTslYgGphAKCm3jua +wsUdhNOKM05rFK8X2sx7aC5ui0RJdHzie+nENWU0CqKfHmkZ7JR9AIo/3kkycbeW +A218Mt9CmnOT8w/iEZFe+uxQPQMEs9fkbTShciz3R2j9cOeXYxEUkEEWTYChVcin +cARU4IAvYZJu9mhtmsTMNvBmuXQgQChZYgPfMo1A4SXFY3qoiVlf+jj8OcXEbLFh +6KLEpOIiPKUe43UfC0HaNyoOxkaMnvH58In7Tu2Hb3Vi/MdUHjOxii2NtpvXnU/c +lAOfEyYdybkAy919uHB6sceC7S7bJAsZTHE3RPsDG4FNbPLYSIx3VOTVZUrpD7gs +fpYGY6mKdkXMZu6Y8kVGJsXm5BxvOCI+If/ILtruMBe960OwX2JHYseAn9B8Co+I +TRjEl09lKHbDNbq8QudfvdNsd7VlK/ONe/y0X23F+ITq868oZzM2txoxlTZIdXcY +akbeeoam5C7zYOSB8Jxpin3OhOyBcJ/UM0gOt+SQ4BymSA6r7qK3DevKnZH9oLkD +9crBSh9AsnhcYLuXYTS66t6Y8YJa7uI/AXlDR5MrME/CXXTbncQfidkTUNRx293h +041JYVe7ebnoot7ShKSiIh/QBSUyqDe6wIMBYUA2lMRTU6Io3NyS+gkWBzGscv6h +i8O2WpyLAmWKHI0YrvfcMyhkUsgx0pnC6gUeukRkgTdqmJy9ydpa67Aenjqjd+M2 +BKend41ZlpTaqIfzq3y7/NsYE/BPfqazKPqm5yQeOJGaDthMa+X116K8TjzxnzL5 +cvspMjOFTEs0/0/rm8hoVVumox0s4crGdeB5JJeWUNwFcgu0H8OtpcpIEsdi6KnA +DUnhgwnkGKJupvDgPL+WVrJ6r96gryFJTbXLOC+fnyY1iDpeVWu58cvKWIl7yKVJ +4MYmIlV8z0kO8AQ/+nS4WPqYzlgEe2LQeJJXHRzbUEd+4fA5/k1Tw7P6jMNOUIOh +qsajb0XM5cvHwHiQwnA40i7YL+ZiRQSC7IpPMBpN9HsEdU6aqMgPKly9Z8jVatxR +7L2EiN0P+yQVRMRdaP4j0AFOO8ZTrNFCEJQ+I618pSDq/sZi6qtLyb/SSN10QXO9 +vLsuDdbqEqyHcnl0L3peoL7OgFx58wXZVo9AyVaVFX5PFYLeMYjgP35BexvlGJhg +U19npeWcnGT1oeRLZZcKWVbHTHsR4c4PNECd/HkzjfFVbsGh5ImVttW+Hp76/HRk +FrY4ziLldaitqZUQsYz4B55Bt+5gfENy3TmN2XcQ8IqTypTo5iCzB+QO6Yv1pWEx +4fL21Vp86TQGvC5uRhB9Aw40mhjo56ZthgLtyT0jgJLmi7NsmVXrP3I63m2kTA1q +enLzxXU5+XB4SYuPIC9RI4N2SxlOpo+Y8YQoOZWmRnfFbu7CdC9EDtXpAJG+a6CB +GOLqNWg99h4jnG9ctUwn1ZZ5/SUcT0AaiA1pHfMo1zqihR02lXY2hA7/waPM+l+N +WCAujKIS7jQrtNlaLhJM3DpPBbLXOFzrt0d3RCe9mz3t0TNrxmx/kz6S70FWlL6l +v8+AZsLp/lOy2qMac6JNj+mCoPgnY22lsOS7b4ikl1LKk9rJFObq7KFUX8hluqW1 +C8nqBQIQLpwBDo8cgnLDGJomdj/JZbXsfqBszi0op2nRtHy08dCc6hcKcH5mnxxc +OGD0JnUW/Oi1O+CankzhKZuSqL/Lkev//TecMlfb+ng0clihM6tKIZcC6Naijyo7 +yEhS1xaRS9NAIk3PyO84ZJykHRfe4Tmt+Hy4IowbR99WL3ZZ4qybT3xyg+iTZ3xm +Ofd7N0Vt5bxBY9NP1tmcJQIAW0ODQrba3g8cDUKLxFzP/IjN+85ePCMGa65jnb5/ +Q+NkvAlPiPXO9lDkk7qu1A4J1Wzb36/tjDqHsaRLgJQ6B8boUbFeyxSrABLn2DH/ +ZUySp8aI2rAQsKRFFIs4gmQSZf8lDFZuef9HLsyImH7IazqmF3eDiQGbI3iXYIdB +dLjprY/P3PHbzp84aVRh9kMdkW7tcyO2KHX1DPbwSa689+xDWV9YQAwh/vk2+u9a +x7UqXoyuGaeyPErOdJ2T0gFRrAyamWrMGFc5SNwTxr1ucrovPTg71V/+zWh7NSoc +hNcvftYs9HOdtVVHuxM0IfiHwGY5DqU17nz5H+DCPIe3qVKaJmZVxlVMl6fXiCRB +oTRMhZU5bEE3ZWGBgKpIIPZo0oJVewW7dcsWUcPa0/TzvnV/a2JbXYOcx9DGXusq +72ESmOe1aY6mym8sArqUTrCIxDJYFFOj1itTnxmVY1Zvids3IZ7EnfXuZPTLDELX +sJUVOJXiMpUmY7jKaiPDX6K8dYaiBFKFTrQXYBY3kpyRoBcykSLvBoL6Cfp3Cbo8 +OsLkdql03DKIcA5C8dfLCCyNSepQKm+uVynxxTzRsOj/8A4J65W7dVXn+RBmfCQu +bBcpNg75/3tRYAsCz53pp8Tq8vlg0bVt4wY1dUe7g9TWGMFT7k/v5aTntVKI3rx6 +O/CaBMbQpBJGKdLCh0EVmNbdb7UrW+heZZLd98IM04+JHBJGnxv7PAJPZdUjtR9a +3kHR6G9GIh+vJzkyv7amYTKvUZMOmtvbN4ci0KZO8kDMbLjjTh7tSRK7a16OBFdz +FNwveScydFNsK9h/cVQdbEaWbZRk4qcMhVtMEjVBILtpSWmrY8JpAM5mpk5EIYDN +8FSG/ePjqbGOVXrcicjCAsYewdElCjjGoO59CYgerqVwW1y0UFpPknn61oW8FFRp +DXSXQHxMdsD7DPRqi/dGSskhIBck+DRismJLYSD7LwCIOBs66Ce7lSxudpGoCfaP +uFgBcOqMB4WwmQViXV7Rgpsxo5Ei+XXOB9iq+pj4T/tjWBwWineiBqbsW9XY3ZPs +nCL/6O1J/z0zugvS0kYkUs/2Qiy7nfwk/+D8vlHKhRWxn3lkqKOr97W9UloPYZkM +8dij6EZ7/Cr7AMyJwFBFXavTvPDrPb7chot17QdsJMJMdXW+HV5mzLjlTMhsBKEb ++5uZcTnWARGD9Vxb4M7bJLVEgATo2fQi+LSYKVWK2ATB11+V08tJIl8kJhc2zCi/ +XqQgtbN54qYrmUkfGbnnJlm7AhWHfHim7cLrRKPmUf31KO5kYfPOOxPDPwZ9r4Pa +AQMweNYmg7cywN49LqP5SwWbRmMVdQNLwrs9VOowH2rhsKLZX4gGfULizq5FuwNP +C01pox5t/YvjL8g/Si5UXA59oeKaV1wTIQ2XNwBA5/pllNVLmwPK0qzA2PByEUqo +FXylEqf+FDSUFmB+JeRoEHqqRBRz2F5+GIiyCKooLYklAkfcRgfSw+1nYlYVyfHd +CxMb77pvAzYsDTgqwvdTRBdKTenGRyzftAfgSDHsIk7/8JhU9zAenFPSFGmDqtyQ +oYjR9PDM5TqABbPYfp/gKdFNaP7HJxyp522knF9ucJoGtLBN88a3vGfoY4NO1m+Z +JsWa1t9YGgHdH01oGca2L6zC3xfif6SkJMcQZvhJLhnelEBJSHqv/Q0/ijkewAM1 +lexdqJsXQl8doxf9lmLzs3IlPFu3mMh53WFf+crNcUgnSAEeFkEp8CXQmGgHHXU7 +c1XnbcuqmQ7NKFCkVqQWdSg5WuXOFwXgmWhHRSk5jY2p+ihLLFn7Bb4/CFdT8R21 +VVn4HdBtIt2W2g1nWAeXGqeKdcan+zQ8KpTJwXkXYDP6RIvO8zS/O834ysCICdOT +T5ZNuXaBn3HzygYlUpx0fUvYzcax5zv32afEc/RWNcSCwOabJu5Wwi6kvVvKHHOT +BOFPewHWKZtncpNfrZc0R1ldIDSMYNLZ+QyEYej9O4kVKkLTARDgnyE9EhO9kiDK +SsGbloIJWY8ZwukRvmiGUciMXGLuRfO/+Y2eQEvSz9EZrPPj0/ooQyw2LKznLPwV +CJoSBGwkpRHOyuvmyV2IOzI723tdoT66z4bfxRpXswDJ1uO0DanPZI4ihTI9Byug +4F9bHmO3dYP3G+Z9QgQRk3sPVpEYUUAEoAJOBFfS0rKOgei0tNabGmpyelbsUGcc +xrpFcNggtQifLqHUCe4ozTzSs1D1DPHUJFDZIOUX7Kmn+I4f7wTFdQ/neP0v94bP +YMYAbJ4dH8bB1/hQJFXWSdO5/P5xqz2j4Fux6Fm7O/T+J1v0VWb52HtyEnS5FSQ7 +N4p6P5w44I9a/9VuhMmJUJNY4uqUVTT0JjgiZDvP4s0zkEIE0AnwTpwJHVdNKBJj +QpL8XfYm79gIhbvkCsxYU5Ux5jgeIi3M8fKBuR5QeKaLJbhwksn3bZ/swqoMAxV7 +XP+77TPWBPlrlfyOHcDlF2orWDXkvVKP+7iL0zCg8OXpDkGMqddyfmz9CLfxFQu+ +PRg/yif/AGu++i2fogXkRNTS18jmqFivURC5Puy0oDjczjkoxE7swntjhAbBWTq+ +S6hR5JHj5zS76+CaXJpt8FcZHnHdzgo8CycpL9KFmXGelj6WGIywGRMKdvWBWxIH +V7L9qGwKN3snXRWGcjAf2bpgsGAlTS4+SRobGNtzpQ1XRttZuiKdmTVv+MI3S1ms +E1m286Wl1hpKIIBzlx23vvL4jEPk2yLfPjV2MIImJ+qgT46zxByEKgNe0XME3KTs +Vi09IZhOuVPy0TX65LVefgBJaeZdDfF1WyQ3VCdFMKq1nxcs2rGYQP4Zq9k1NQ/1 +3Pw2YOB8btStiwan03n84nTtVCQbLMoBOWWcaZWW+0Br6lDqIEO9Cwf16f4YE5Y+ +yjtt9nm2tbtOrwDsTzhMzUDZvF/VjZdHxtyNfSmIXihuD6mRzQ9HkfBhsUjG/uq3 +xqU7pElJ3j6n/MnwMcgN5nsTAP6SKUQGuLGqVoVMfiNubiOZUb5lgGHazLE7XPtU +VyEyj0TnPB7DWLa6Yh6cgMKrpWOFOE/+fepsQqmyPW+WSCtcwD+XqONPV6l2e9T9 +XZJicu2LaK3C7FCmGQxQOqnZDtLLtsTpO2RNOWCvbQQe2FuFb7bFwqsGCfsvuvjW +n/DgD5ypoWtpF6MrjHsqgLB3zncj5uAtLlWddfGI7PDyNBALtm0JBHGsBCNFVUIX +Z4AB1ThFRiIxtHzIjveFU15PxMnyURX3qFBjlOhNBFbPGGWWeTlm/PSI4InMcB6Y +2wqrkfY0S4/+TnIdz4Yab1LmRruAX5O3q1hEYAVUvPtcD1v9JAp+HuGgeQKa9xIp +FRAEeVRbMcuLB4cXXdSSA6qVC/vkpcZP8UVpZPShj9jzyCxPV5LmbkEwrRRo1vAd +55m0zXtJ+G4FO79DYpnj/c+VnJC4e1o55Hbicg9OYFCu2nzjTt5Mra38oKa+8ieW +koXv9lzZ8b55gbAB1mTFvFcB5VS7qlQTAcuIIsAdcMz75ijh6I3OphtAOuOh8yDh +yt/4cAO/71+4nfI5k9OwWh0ka+95Uiud0hdWSxrDgAL2+tIcKSym1WvOhGjg9ymh +hfKfmklhTA59J3S+p66Up035G1nOi6cdAHNYf4pwon3yLsqf2KJQNY8l2SA8h6gt +gXm2S/FASKbkl5WlCNWEzX9Bwo8Jkm8O9evwO7RKef4xCWTK331wHmCnjFUfmnfy +AYnJVT/yT+aRlN5fTzJzuOIq3KRYfpPOa23HirfDLzT2NFc7BU9m0/DraZIBbGgq +3Fo49p7s3Bc8W754lyl9JdiC9GVQBV0n1DHf6wAbAMQQ7DnX1aL9MhuuwffRMpGO +k8/RYnLy2OaD8oBmcFbMKAZNj8gudEFXLIRxIsewkBoRq2cerAqBkyk2LHpXshVq +jg9kCWKJPClrhJpvvO84p8D6sQV/Ru7KweOH0XnBNcxt+4acPnabulekwtkvZ8Sg +1H+YaOm66TUplnQ1lctrsD/4ow8ri8KkUdFTKKtLoUSMi3/ET52ipxsAvt19zfVT +Y+tWk4JjWYJmPiD7QVaMejANuGFEVQdDCxmA1PeOBGRVpk4/ONnuggxMpZCHpE6/ +8tjPkZ68FU9+2/tPjFusqd+5Qpzkir3ZSr6yzaxLPKF7QD7fMxfwIFTDGvQtNLks +PsjDWsjWB9UtWhzzAAydLo6A4t2HzmaeT+chNyOKRwhcawCcwQEk99NBk0qhn7E1 +C13itBftdg/43yQlshePzBWKPSarV4slZbuwB45o/YQ2nf3uIPYZFd+TpbtufJHk +tAnFOx2aTy2CKNfTCgzp8stlCIjjFwrQoMlrah4EljXFrnpOm4NShTOk9fsVvHpm +hnyACjDZDT4jpz8STNG3HTMHUAJwoWOphI+Vp76HnielN2LGQwgPUHIMaXFxb7Ap +75vIWNAkqMC6YHtfrSj1edSM229Q/Cel3awhoJekpgeedeT0wiLVKEWWfb5OFpnj +VT6UHvUiofT0QkWt1jLPNvcC9ol6NRVL0vrEGi+M2WWo/3TycOqVMWJ3CDet7MYZ +SIR3uGqaFtKtQgXcNxJ0lEHkysUn89649PLYcQz1x1XqjFLAoWxQHIEnjQt5MXuS +g3AYsmBPQgplON2yNk743tunahieTknSdMRwUftzh5EU91MjFtgpijaqSBnC9/r2 +o7AtTXs7VMcKRyUZv7/u63mHrhpU2tdyhbm+eSgm395Rr1Jrb5WEmJNHDAl5y/nW +Hl0vGd3XuRFouhmeRPSAc0EDkXwf3cwTWzmkMR8PNmrQPASLrH0ZPW/51E1oE+ya +K6/Ph9zv3z0+/1nGrHZDFCLBRKXfDaxp4pBSk1Qq8E755NKrEfrA9iq+BW0PwI4D +QNIr5I6Epfjsic2f4sYPpSrZz26zDTg5j10E081RJkCWziZjXR6aH+ytpbreEi8O +SVyPO0UqSeg3Q5qjMJf7oq3PSbtvJqIC5y4OmVyg5hUKOxvj0+XT33kePx7Jzm7a +pCII7dFrBKrzXKzd3O49EzeQgNIt2NwNqzczAjAwhKT8jMUCac0HcwU5KaeirKOK +iRy1Vj+1amAN18V37x2HjuG16kdEzrtUJJqeuNPaFHVFksCOadlxPq81HUUVGH3K +a/Ktlqb8Hc6HZ/Lalt1JONtZAOrkWMhAsjtePmP6MKc04MJEDpXk5ph+IS89pOVw +jYmykAlLEH1qTIj+BWfn0SEZZ4It9rJ8Iobdu1Tuvt6Sdf6QDQx3yp/+smvBPpn0 +kfLSznIgNPjBSbgHsWc53GFfjsDW9xo1iqWZLqeDVhPwvS6R+WomQbcmHU8AxqSE +nKT6PP6pyQRJjml0KbfGtoIsaXon1luRVgiaM3nszWmZ9NHuf2TNMCG2nYBKep1C +nVa+0Sa5oPyAz9a6zf17cOYC4bY0KVCpDPzMfplt9YGcLghbfqY4OsjHMxwohuYU +MnQjWwyDzPeeP2C1B8ooZNLHvFAoHOPoKCVN0ZUiNMNiqtRpQZzqVr4mz3VWfQfv +9rTcPvhWUuQvPmV48bIDHDsaP0El0AYU6H32sMmbwQob+hSacNgumQe94sEtVVGj +6GpSt18h47AcAptpzF0Fk9etzPydWpYnY+Dcdxnhs1O/M/HcUzmGQnEHjfExYKLY +FWGSVieO5BHZC5XLnERczMLLPiMsWqdeWEdkX301GWUq8pmsxPH6Ny4bcGiLxzGv +EHgLBBGrcnnk2CzmXGJzuiCXgLExedeF5ozfclpfPdQ5Pob11LrXHNlu0+KGE3Sy +cGDVgkuEgS8IKvd8C1sJjoU/EstVmU/U90pPSOhayrK5V3Odw2g5/LJyY1cdp/u7 +RW1IAOb4/dT7I0rVp5PO9cpi1Jbuv0Yc5QhMckPx0BKLi1TrbW6uIdw2lirehvbx +RdiFIfqapbjzX/QDjKFqOcF+uXGJaYD7aC/rq0Xe/x8W36hbN1x3kbpt/b97apFQ +cSgyKVTDtGkGBddYMQ4LWF6QOfW+NF3k3tyrnc9xtjqNfEbWjxGccQH/6MjGf9SW +maqm640c5qs1JPFDKNzdYSFOs24ckHQ1hipdgxp+3GfCTkz/lVK7wVYGYpNgvLXr +VBCgkGnayviOai7y35Dl/qj3NXmC2/T2jK8xjvYGCvSbHQkiGrPeeP7bAGvORAHl +Q5C6I948X8LdLktLEzUVSOFMB4SFEYuW+aDgjprODWDmq0YaxCmV0pITbGX8+O02 +zE9t5SGDX5m9zAcUezF7fpOm3WlhWUoUhqR4ueL55rzobLVgVp/vVznOJ0avt89V +9rFR4Pu7JmAiG6rNdpdpux8HiX53PO+r8z509HIclT6+ZAhpRZzfON+d2kAFvZ8E +7V+xQ7H9FWqWR8h+Wt8A9v6wNfvDgmWc+02mRKs3ITljBoxat0aLa0QQ3cWf5Inv +AwuXgH2bp0cJkpw4IJmexEo3HtjjcMge7eOWlGhF44pJ3314VZ5t/mG7D49vdj6I +k+HpXPBhDx4vXlE0yGEJYpsvTW/f7Q3voq5ikfkkHNWBjPRNqsjt2ZnVLLa3qLux +HvofgAFNKJ5zrXEB3gSGfCTWgXLoNGFLryp9lp8Q5WE0a0O/JuLNz68rM9CozJxT +nz95sVm2x0xA7fEYm77EaaIULG5Y7IBwPVHLJzN5xSpNqL0TjN9SHNhU6VZTJqeh +1hLAT+gm9tCwUGUOx/bCN3nFSs2fJiEdfmqAJLMyhNHLC8OWjugVE76vaSV9HHpV +TGtIg74IScWoq8ZoM23Xy5e7ihFUz/45BwcECft3YtruD8Fb5dA6WW37Ih6pzJRd +mrGGDeM40nkRTNac6MPdVDw5fW6tplCW0R4PGnR424c3Gujbpn9/OdzOnE3p9h5z +oK0VFrIa64K65ogvLYPg62vi6XwUxEHlHujysjQ5VsBjkzKqZCNaRpZgx7RH/ocO +OwV/mItewwGwfjRFthYFgoWzcwaiWkambFaQspoiqkmA/Qrxej++Z0tmpxm/WsFb +vwLZ/m410KxZA+hBsLigf3ZDRc6gfhVIN8+kQZ4Nrhzmv3mNsjLkecxKYsL/yyPZ +Nj76Y61hl2XhBvYXbs4gbr/NOoBZJFi0/IpKqPfph1lUbIEyxkKrXZrQKW70eFJa +nad7eIB9aMAJyvBlR1Og/bu4+Q1VS2L7wNrA9aI93PaiNnskC3HhGFszrGN88JnF +mm6jN8Q5O1Apn+nhuL9KzLpsK9BdpA9o8T9YobOriV/yGhSHL74Met4MLt3zuSAf +HykNvNyoAny/iJZezGL/NgtluZx7wfslrJR69y0dy/IhHMo505vNZKmPRcF3fLVa +6kqV4xQGbc899B0moc0DlMYNBv0dIlJGMym3HeUVNi5gXq/5gyzMQ/rAHoxLsSUC +u3rxSpebUApmhxlKMnY0wbNvl8Ufim83bq6t+S57fRO6VruE1yh/uEZXGiPlm2kU +en/UK5PnTgyvkqewn1kRbATmDBbsIixBc3+0k7DALeVMPFkKEeyZHbOB8xaeCsYf +RYUeAk8Je35l6mbc1+4a4qptTSMc20w03q7PM+Gt/PsPMSpxCxKnZEgGRUQg//4E +MWBx3b+yGcCK7++PhRR4TvlxPVxRjrS1vWSiQ6Hj0LzSyT71HZUDFs92oTNLvoGM +HFRTMgVbUm7KMKHIWcADVAiAk94bw/BpYRn6c7PmqLb8SCZ63kPS1j2LwMAHOH4x +FfE0qys41IsyZ/+2frSoldKqo4/wwox8zEVGLBeXqcsp46BJIqgIsTNlxYFnAnxi +827mSRucWZ7gm3xVpNrANeXXDa8t6tWSpukekX8Tdhe2XPrOlyCNNsGOtDTSXpez +zJ3PWP1AH6jLqAMP8gxMQpYWaVTkS+T4DQ9F+iUqiQC7mMa5Nw+2n4epQQRyYr3s +HYljGrKdvd4N0X7th7+D1fIhelYnbC5SRgp9JokJ66rAYEpkH3kcqjEnlx4xZoAa +qhzqFXdXyibnx2HNaExdJjCBCzPIHFbR2QevIjltUJQmxVvwqor7Z86zZZhdq8Xo +lcHI9QQY+6JnTaOccuBpzPpnWJPbrlCerk1re6X1dQTL34QtS8xlPcypG9DktdXz +12xu6PB/tOnAWicVqcCEOS08nnZMeK3y+OtDd6vvNVP7k5u6z4Q4dP/0MeszWlr+ +pfHXG5KXIUloE36F+YDJiarB8U2i8mTnsABn3CbxymXFvg4jnvozTxYQVguaEpig +0Q01/vNRS3Z6zaVknUbfoCmdIr82tdkHvfQWkbXmC6RKVqIqaTcH2noje/0WPOOa +GAiyuqzLBYIAeRAzJOqPSKr4zcLp8dNWnuTL5Pl+s/oZAD117bybuqyR3kfASUZS +SEakXKZ08gKJ4D8lRfwHzp91s4YuBnYD5HnWhCQzl4xhPv0NxIAFSw4G4oe+XBG4 +KxPuL28JI6s7aV3phHTN6E9NMK73FJOR9CQ7fT8pRGAxEieynE3yccGBe9D4dIx7 +FCEk4W+BDP3ogQX7r6aj6mmhs0BlZyBy78wplacYskocYNPAIOX+YO+mnPbYVlQi +cc0dJbcKD1vYzDIXAaD1D/o/+uY1zKQBrGQAqGu71hmKs8aIDO3bi7J7riB7Cf1c +dm9GC58Vd4cX6Fy19BJ5hPE/+ukJ6rZ9mmY2eE3pT+HmlvXYeHirUK/7ZyM9UyZ0 +tpvYFy7usDvvzcSnm0UCW0cbliZo3bfDf9zOYP/drJW/jF3rS7b0vTtxIN4jOrBz +V+bhA2FpdDs9puTOEeb06WwEiPxn15/B5IB6hgscaePalwWL/8urX0gPEdFNy27e +tiCkuSuOwVPrPb8PrcMQR5B85pWO+TtgLrSj+AQL3ZE/25HLQuYDW6BofYAzKM2o +Z6ZHGe6m019BeVNdrhECf9UErTLydAQ2Q/e38v9GrtRhacPZA3QcXfUV4Q+zLNqa +d7x95ju1szHlNhnLHtOkKU2K1MtfhLeKBQuTNEU0RMmsF7HDp/LJ38R3Oxm4iYrw +dxyIzWGXe0tDSA4i0diDft3MvqfxWWF/eNpp1+KmhgSG5uEn3PesbO2zmHxP30Io +ZRcB/Zc77UjBYHu6URazosznSyyPqnGV9zcbnowRhilFVXgUF/N/cEV2RQs9C2CB +K8i3ef/rk83XTVMNT6JBNRrz55fwV/JX+i8+J/9FbEpsH9nlZfnocdR3Q2yzu0RB +IG/3ykpiw6ZGIiKuTQsDthahfVnKkru27f9o3KRv9ChLMhMMFW78Zs3eE9YQI7SM +Ww5tBQeWXEM99yBh4rc7z/qtGjecsPZG9leXsPDm+ER/+WbVryTPS2jSkQQbrbmp +BKyDWhWh+q9s9QxMZ9cT3SvX+Bz6ba/tICWMkydiOIDTbyOpRxPs8S92Lk0XlGZF +BZ1lCt0FMdM5KrIm/GoxvCEhlbD0wD+4XHxkUjm3q5o7lXlMWAmfBB8H5k1wPE/P +fC0pAdB4BmS6vonbOn3vQS+9zQUnX024rH1rrh2mvgal8QDuRqUReU1yYZ6EXXYP +wsOu/vcjuV5RuUSwIItVGTN0fY7aGNJJAK2WFCrvq56NfpHe+XNQBhA9/IygPymw +ZYsP/y89UFafKJm9ssk3h7hiagXtGu2HmZQqZElAvkEM1Msx+jx5PnMDvUbEvb0W +FAqU0c/mbNfRKiYiFKWtTMFJT7wu81CHNElMs2un++6XfmtyqIxtGfWar29jrxA3 ++g/STafRPxSnPoLihK3uTHzRWJ9jNr3DoNQtL+5SQzLOlWHYBZM7BerlPF1UqlOP +49cqoU5JQvHwDKs+iVSKIr8cUW7ORh3lb7/G9hu9HibQSVtTeKcBONJMTlKSnZDN +SQ9pwTYbLLi40oOn3OjFQlIhhifN6Yd45bNlXbdQm4v44dRr/ia/q5p5CgecQKVY +ipeE+ksxHuUuptP8Dzaqm3nte7Ehuv/AQtG2L5dvsjWcLqvVw0WLGXRwQYby64Q+ +uaA8+aO4Jv+TgFbiAS7MMJ/GIY+sFXs9fiR+XuMZr/LrWiSYshET4IclRN8udP6J +lZ/RzRg3NvfHF7NKaJ96Ii6DAG6X9rywpD0qKQsPdRUfLEu9nljQ+NilMq+qPnNz +W8jFG2mqmpEc/e88OGdxD+tHLIlOWukNooNzTxJ3VBwyg1Vf8qy1DfxaiSQkAnxB +siYLiTNW+rOPBc39cT0tqrLVv20L6Fl0KoWrSrcmWQP7y8gKGUsVZaOfRxoRryWm +3g/PqnLZOmSxRaYJOwZGWGcqdTP+Bgi6PDKfCpyzK64DuVhgl2lg7/nb3Moq56eL +CAroJ3aZ/UjBI2H1e8vgjeq3QyTMyuPe1sWqzAkNqaRi4PjemcGbDO0ukBg/TVod +fTti5TTUIo3SnxUINsmqWRJWkmhXNIUywP8LGXQmYQdXs4pQeHx7Kes6GLV0BXHz +4TfU/ohqv+bJFrKXJy1qa1RnnHuvfxL+xcEibt+xXdUfZTUD3MeU9QpUbsqthiO3 +sU84nyqUK3SjZ/LL1McJm0L1BJh9EjJWyCeGUGyvjf9tvI/vfgRdvuXrT1oUBqCk +GD7Wur2sbAxmsOffkB5GlYapaJLKJW3EWsE5JYG8Zx2VpZVoGdgs+tnxnY9Mk0sp +WBPbs/DVMY7t+SssSIJ3U+PYMjy1sgxM0HhRPB1T0kCDNgx3T8MF215QKSoIZWee +nBUC2Eg0TqTAOnCUQgedvtCS8SvXh0n8ftlpnTBT0eLY9XjPAaMPgx6ZecwqApYu +MsVF7/alWaNQ/VCIqI7hOfgCELreRwKqeVxkoCCnweER29KPuv2MA5d5WGDsBOA0 +YSi53SK7VSYPUgrh4TseSqkE2FuTuhAotQ6vduBUBkDkIuj86W4RN2xxGTbGmRR2 +A8hr7UEVfUP638iQ3BmUTCnfxecJ+9ujOV7E65jPQRPZqFsbX2TuKFk56iEZDGv4 +NjDHrlLaQIyLn0jb2Divnkrrh+MER0sYtITL9gIWor1K9Sd9bujj40dL6wCthXB7 +ljcnlUNRE5o2dKpBXRttBRLLyZBIpSYeBsUjMQNFfGgOh4S2/Y4HXEYmVvHoHWuS +oAEkth/ECCO27O6svyegSl1gj3SGk5ZtsCSLrZyuxpT6SWUZPXvQfTUoz835ybyc +3gyCJNAA8SX9LXzDBHIXhgm0TIrzKyRweHwEiDhMNRh6CvgFDnJ8UMkJy73z7GQz +jE00JCWdq6egp3sW+z3+WOAxbNqO8B7Dee9Sr/ILjmk8/dKSju8anQW5pc6VJR3n +CCI2hPV4L6Qvn9sBTALwkbhxKOGCH3q9SqE4PxmwEgjcIWrLeKgAQTg71m3PowKF +irAl6Ljzf0qhGhqAO6M+Jl2qlN+oACt1VHUt+Jx4ILNRVBlQd7PbbSbkytxciEfs +00n49wNTNOlFY4kRO8sAlLmvEo2Q6aDcg4XpdG/EsIf/90nmCuz88o/kPrJZnCBR +PnYfzF3Q6YF4r+aBbJDc3vJlxr7iufNgEzXswDtJ8o0EGfiea+/e99dqfs+Q71FL +5TmJ1C3MLkAf88x5+mmMPMCE4L7T1TFDgUMq/Y/lpott/gvo48jJVbSe3/IjFoe/ +3QFc5NMqwCNlVLyGiTseQTDJ4XENmUUykdthX70eICj3miAQ9jy5H1u/ogs37B9D +Av2Yoyirt+W0vb4O1tJo86NzJHvPMUTNR6Gd9caYLpgTYAQKHMKg27hjIwH300m+ +FVRM/g92LuaW0VuIkb+747Pqsl3yevA1zQ5goFDwwDzVvbuDtXUJSj87vShBvuKk +ab/ywdkkeRmUcwlzUAU/Zag9YaJPkL18fRrXlpJBGFIMbkUrzD/vOVqB9lcgRmGO +oP7qIJAcbvCVXTBBv0Ru2x09UHdKwOzXh5XG1eDuAm8KFOypQk8qgVmDrbNTjUw9 +fF7qLbX/extGK+pbjyFAfgCWVsXdK1Q3Sc1hWcCDjhAwPhcIJmxP3BFuKcGk7h7E +oWPUB3GBDGzCjCD0De6ZFrUZErSxRg/GUZJ9DYKTWtZc7SlE2Mjb+ESaaD3Ncu7m +S5bhRGmkp45opkx85HuVji6Bvwq74yhNLR1mzlb+yrYaJ7X6vd/QA8yT+CZkG/V3 +EHTF707FDjXTZSQAJtatzGSaYnlnPwLllolJlxp4/LMHC2xnX5uGnAUg30xgdOyC +QZba+QMJLWC62INFNLZGxCVEs50SCKNp/dvpNiCEVboVZreF/KB31CK4GkkvDGw6 +b2cB50szV1qzIJ4kvhrD9JyOB1Xvc7LeDu7TRPScMLLysByPHWYzEopf0rojhmwu +NsL/TYfeb86oUB55znf9eDljrO30mzY9aq+nHib03pgmXaPHVDU8f2EeAknzNnoU +roZqmujBoFJZ+XkqcenltRbYaofyGin1e+ACEy93h64LhgHq2WVN7D5h2tfbQlxn +pc65fqHYrkiMXjyhRLN8VELCTHwoYzpgEu04gNZDYHY1JnhbdjoN8JMgDf4FyxJc +jQR/ysdfqXBrDW6UYKv93GRxD0jHgoAUsNLjgRqi+a3FLz4Ymroc6zuycvBH1+Dp +aA7R3C0IjV8D0y9u5D/uWTmnAQ/tVvTugNM1hmzgrVhtZSljSxOLSo4ecp3rOx9o +braPBBmfR8kWshIbSEHigbTsnLsbV8me8CiuK8vxhH9QG30GFCojIvZqWEJ5NN0r +IcQ7tW6T7Vy4Kkd9V/+PG+R9eL9gXh8d9yCMLUX7tUy4DbHIfysL2YFdr4Icinu0 +bogN2owaGsZA2mNcvLS1Yq7mp7c/2rzkiKfp5XdIN+60BJBG+b6oIi9nQ4VSMmiz +C0TQT+zJjxS2Ll3PcYsdASZlKdBmRR2CdqlR05AI3D62/hpV7LStrvlnp7zkudhq +fdUfeDtyrBU0DFtKLwnR2m9KeVdyM2JC+lxCwWGzlX/urRBAvnytU5ohcnz8gRul +YBaGr8X/39/MNOsK6/xdVwBPAz9YMJjpqekuDpxfgyhlwvIwBbbdWUnhfWHSjRrZ +ZeKyvDo/51KVLC9ui4SsoVZYYa4ScXXzJkDOKZC8I96RK1Y8ukr86vh+0we4z43v +XjoOHz762aXuV1kLGt5I4tCTI/RFlUB25e8WSWeTvkBybwB1VsxRqj7Ahui6QHeJ +NHAfN5QO4qIZirkIlQhl4xYe/Rot5NkqgK2kJ8QCeUoawMEl5JuF+UvxGdc8bjNu +YHQDq1chkoG1PBZ2AT1WyYXHKF7+BuMZaaYDO/nK//S/bdtnt0p2Le4W3t2zxhk+ ++ZWxAz5apLALrM65XHQnLR0bawQYi8FOJZaJcREEir0bQFnjvaui5Pgpj9QKxTMq +aCc0zgLLC14crDmAjKqg0auSZUPGM7i9FBBmdWP22vw6yTttnGjzI3wtl0FAPVBS +Isl0XCFWQfjsk8AZ9smFP9cjyuez72Dr/vG9ln+nACxQw83mE8nL0I2xWo0IJeQS +Mj6oXbxxlOk8BxCPlTZf4OxVC22ywJCYOnaxqVPGIYJCRMV2X6NAL2hw5YgKIcHA +/64be9EM1QgJo33aMVQ6tokp3oS/R8RM5s5dC9SihBljQvN36CM79s/8Mmww2fXO +G4K1lB5Ty2bFLTBJ2lWVOE5uErS4ChfHEfo+Mr1BWGCAHdprclZg2bMo9f0lOwgv +6Z5bOLc86eMAYgJV00RtJyHQ8DOdEefXWbOwq7DewGikJjR2q7xCCJOR6bMFhMTH +4qm1V5HA4nNxbT6q8pBpuse8huAukNXxdvYmwj/XKO6XWSLEMXr0Ee4XyFnQzLm4 +EDg06z2etWeEwptHKZSU/Tth2QP/Fs29KyZNmQy6oT+N2LlrvSalYCuSYjSsd0Z+ +BLSefU8WxmNNxC/ALaSv+k2PBGpe56B171UbDIpivKjksb5taJ0ABVBW8caLfsaV +542vvKhZuVl+tvgsXhhHs7K+ZRDmDu0JPNHoye1eNKNTYHFkts9LfKctuXUeR3ub +ZkYJReJE39onZjtepjSeZjRHFwAJ4bR++tDQKO8W9MI/gfCQgbJZ3MFdumrkNy0w +SfzK2aS/x8bMPgliGYUu/9SGl5Ta/NhKeA9ZJVeMIXGz/pC3vMIvmTBCvX0N2RAh +ya5mxNDgedIdVt5oa7jicm6s0TNa8smHktoqfaMx56PmF1S34wX43N5R2HJu0o2L +lsNGDSE8W/+xvvwQG4aicuwJ3HmKq92sPGMZ57qKDvYhIPix/1vVvITcDCHOLS/9 +RWphxpiOVWdYZgeKi/2xj6t/PLOYeRg+lVSQa4UdfDw82aboOcQ+jZhJ7fUEqqME +vgWq/jLvExwPfeTvHQZodyM3EsTh24vk0qtQbmiC0OAxFaD5ZjY0Lj7CSpAbDn/C +oTI+PxYPtUqHgCbyn9yXtnmdBi04aJHaWDyEhQis2uM7hTMGB8/t2h1mZaRlhCij +13pxthqoNzPW69p875EfP6YzkMrLYQLz5us5ajL5fr6/ZQkieotcDWr8UcMETruB +0TIBPx5YCecpDCRsDOggfVuwo2dkHgbq152U9mEFzW5oGQZGHX5NrvyakmftfzhV +kbXyx8gYnCaUqQXon0haFDMEAfSFpPDAzsjOSoyEwV3Dd7DCbO8k3+bZlmGOPBkV +KRDUeqmFEWoWIB2vMOtOTxWupM4Q26IzqaGQZmZPQLA2MRJDj9jCsEvOYbrC/44D +5BuyukeYXlFnC90neR+MF2Lbt3BHeEgWIUdZ3JE23vFdi3LUKd06XYBYco+seS+B +F4WGl3HLhJRKQdwS073GHImb0vkGW2ggd/t4HxbCYPglIHEZ1cut6x7Sqzn16gTn +fFnUDTyHEI3+NuGAoM+ZK2Srrr36ZqAEH8GTsx1gLVSkwksevcf9o7f2ue2kty5x +NtQazVjez6qCZOQhfkVH3VORYSa52Nf3Mxm5S5o0CzNqsGvtv/FfHkm804HpmsAd +sbAa9CHVGL6HmktexxQ6pmgGRgFsG8nH6e0ShrPF4ObA2FXb/Si7Pg+comInfkHd +9pT4P/8He8eC6ZrNvmn6HafgqX9I3IrExRgo40iwIzREY71x6dygDuJtfI4MPVvn +AEtBxELtq63d/mMIDBHwrqSez59S7kv6O5J79hYl79IoDnkwyD8tPFBGOJEqB0hU +DkBnb5Kkl7D43ma05FNwBjbtNSIQZTycAE5iaKQap3Aah5fcE3iYHibGyxmPMkB7 +5DrPs9l+9+SkHmlvzyXFlFLb3yk7Ydk6UFVMz84uEGFASyayUstP3Br5KuRV+fDI +vSp0DER7wWuuyykUScwqThPMQgUGTCcazm8HJpNH6GCa+gyHGJUu0TfHfDgDF0VB +V2bt2gWgs3JPRsNfMsOw5zCrtOPX0/fQpMEdVOngdIt3zwtZpA4Nb+/1o16zOXxT +ZOtmyWdJbEhqD8d0E/0P5t9KEeXKJKUV+dtoHUUHZkuuHKHj7b11BzlQkNXJrEKz +jlLxPbu+7qfUOaVoVUvki7fAAw1LjRXzUB8UpUyVotow4AWYAKhiD+MuNHwJgA9V +/0+46Rzxqxjsiw0os5kui7VY7VrqtoPo6db9p9iD+CJFkq4cU6vSiRUNMjgauL28 +Gtqj867CqfEHXQ8ev0j4MekFavAHkjz0kzEi2PXt4QPKnzHOO2Knj+D/luGyu901 +M5X3wSC2RZh/9U8iKc/cxMys6o1dLcgmnoKUwQNMkwrvfU3aYd57ChguCpANKw5K +mI/F5gtnjxmxcRnWqiO3QODTY3dGMTsR4KNwFYF7qRgX5eJH5epT3eGrk1x3umpC +7V87TFTpnNgy1Nx+eFwzb8fzrCzMO8NYrk9QXDJoSxLP/zsiXPcGaVjpMDIgD0f3 +Hkkm4DRHv5ueupVrPAk7/Xh61x4KPrEpBObVNM525ogi528O1vroJ5Kbm5A3kV/n +Q2tf4421dPTQBg0jMPJ0609G2tv7iNM4x5Gkl4JEkUkM+SkNQqQyXfEY9UW1Vqiq +0Mfb5Evkg3k0uDpPZTLQihjCOng76wHbO7NoNcGRiM6exKb9IjejfR1898N9cSxC +stHe8K63TXu+SLkWobEn29WKpa1KFINgXEUArhnc9xjq4JQNqpagb0LtSYoEtZkG +Kn0MlTTA+KD4IggJtaBPGR3RtUC+JLnlL+9rJXc3fYNK+J2pauMa+TNrlJpGuZAg +gg1gvzG0xsH97cko9j/yhITDF23odYjO+kB5j3OmHgp3bfJpEQh/raC9jzSSVYFA +ggBLHw+5zhgWRYnzuhDbg3Z66vZIBBf5bC71w0Vd9PlavU+pSOhpQM3x5uPeeKO/ +bF0gpYX12SaGz8Z5CSTbmOo8SKSYDrB67IWaV0ZblpMZs1hBjT2mtj16uM+WSt2y +z9a49p8+Bl7n19q5hKsa9dXPzVSS+JkPkYjM2f5lwStVZENNUxOYryNwH4JPjkDZ +dcHolWiW7q2DWsqsM7yw0TgGZ1dS4UqP+fcCni+wwqhDgFwEs5e8BXA09jSMuTK0 +5vVwnedgwsm0uDIv5UCEYzEVEtAm7jsyoWVzauDb3uL8TOrveJt2DbPFr5sFU+dL +8ewM/tgYptBGzLTqz8VUi0YJJPr74ugiP/722zt2Ywy6IEBoRmQV5rPjPqoRDTL4 +0diZ0fRn/rt1BaMG3oHvYVQShBGmL43DpKztikmVHA0v1OtE49HvXGlHwveDiDmY +nYMXmcbDo9f+MEX08jRIFJVhZcGSupNPL7+ZB6mGfEQAr/+crOySRwZvvlIleOJK +Zs6098drFtml1cR80BnWwLVKNvdnd5wYJ7E4LepTTq4omq/K7QBxMhvD4hwUdfMj +vPHR+AD+JI0bpb56o83r2iguMHA7W3mjH3Hvxhk8LbevygA3S/+U0AoPr7Ka3uGS +9jR3QB+bU54bT5su/tbb0DZkAsBCmOVQiGU/vvkG3taqelUdGz7RKHepZLWRu2Eo +OivG0uwQ8ZNgVKEeFY58Oy7Xhbj9Iw3fYTZmClyec/s+CpbHxHXDCj5jJIzfMohP +c/jLFCyxYl9vmZwF73mQoxoMfgMplZVfCESDjr/VK24Yd5zufp/1fZYg0DgeoB7R +LEH3B5/TLtdehy/sEWosZGlkIopbxUxhpOSc5SFtjmg1l17puGodlYYdHRp4euYs +F5RtH1eCvNXDxwJXDT2QK6bBYQa2+t3jyyo96zOB4V0DMxmuPGYznYmKC+Wd0lkf +y3mDijwHXfatjc1YzUIBlwyRj4dXKqO4mlaK/IQnfkjdEFZ3EhZyn07XFXm8wLA4 +MgnyFusEZIy9mveXx2MCkfnC8E9mNqH9m560bVaANaRXFmPjmDSjSTze3XJShSQt +r54ZQG8Xbls0PrzZ6y+tQ/fmUnYMgmaWWC9Pxlffj8K2HaWb0LTvIYOt2RG/U5yu +lrgq83JH+8GNqwUbASb1V9suFTRFXu0Dq7fI/sddtoEl1HXQUEULPu09Hol7Cai+ +zk7kP3dgo9ylPB0yebci0k0rJlD4B2zmNiM4BebGupYiJYFTAd6WYhanoERRn3GO +P1heTf2dilVAWfRgnjBdi6/7QXdclRglxM4Do/Tl7N90cuDGrUqxVAviBCIbqF7q +7P9PWKYvn97yDxvQz96WTRJ/ASw8iwexUoBRetmVwXhMK4AIs6vXxPdWvBVO9BjR +WyJR97CtLKl33Pr2LOQfQkeySb8ObmwToSnRg5AyJJgmaFrkCVf5XB4pKgKi/8em +EsRq2TDD8Vqx9btVfGsJZP1KgTaSmHw7ubrkZzc++u8k/Wny7G5bvycLBW7KGRtB +IkUM9adHTbxFflbkSctkL4KsqjndNg1OjGDchMYrxF7MFmR47TcnJvxOkgFBa8hA +KBEzxfse3zj+Q0WwRzZzPWg7nMmBGSAaa5+8w+GosH4p2acXgEQzzEmSVOHp8fmA +Uk0eaxc5ppJMdQdqxCgd5od/D9TZjZ25b4IqTtEVavo2rGWZvl927v1q6FvloqkA +MSYZjFmJX/vUq+1ohL9v5LxdoDYy1EXLk7KJ/DMXBe/aetwf2pGL8AEpnPcVxk8g +GIWKZwohsrZ6M4AruTeRyNAqE/11DOyGR+mXHRsXFNvfrITUGA8kCOFgKA5mpw7/ +dlwCejg2oayitROSurMw5sPLmzTcPoUPnYSffSRXbsnwXBVgG2gar/Ph+4pal0W9 +qvcoTup5B6FuDGnEV0Q4GYKX3Usx0QzvhXDxOxRX5a36CyobXZBFhirg/de4zSpk +2PLB9fy0KcSTmevSunSBNguijiND07+0JJxiDxtRhVYqmC/0ZASjPohs+9RIM3qa ++TShF3j9qT2hZyuecOpepDm/PV8H2ZFjvAAQJaXkXZfRFJfhbvSaLfgBiWoE0D9G +Ia2Q3QTFTuextDGwucjC4K4EbHTpVKqZ42HYjbU3Vu+JzFDw4mVodrC+CNc8fgCy +9AH0wJDj7orYnd7LZh/d3S5CQOH1e4uYO+EheyrRisCDuA+wMvULGZYiFSf6FWKD +knQYNzLuo/0bvSCkEVcmFb8ZOGNyNhMNm5QrNt1OEBA= +//pragma protect end_data_block +//pragma protect digest_block +oVKojFyDpw5GaFjaBy/xgPtTTkw= +//pragma protect end_digest_block +//pragma protect end_protected + + +//pragma protect begin_protected +//pragma protect encrypt_agent="NCPROTECT" +//pragma protect encrypt_agent_info="Encrypted using API" +//pragma protect key_keyowner=Cadence Design Systems. +//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) +//pragma protect key_method=RSA +//pragma protect key_block +ALEP0YMKgY2hG6kMs04J3ytNSCr7F/iMNJKtSVcQNf2nURIh8tgmUuQpfKedON+G +spusQvansFOzVgoi8JYjVQQzMHgqtriLVUNC6Goo7dbuaEy3NYy5IyBYJ5iwOYdL +X7cIbkKxnAFeMusuwsWRkdfDLft/pCqr0wo+76mQW9Jwx+DD5JzOtHwRCqoHT21n +nrg9qzdGO7eKZEqtQ/fvFHYJr01/zn85jGx+JlaDX6ZILJP68eAUjBLbaCxb8rVM +Yi0+qmto+QZkkuAI0Lul2JJkTYGpQ6a3MMsia70DpLOnt4TBdRCMwsdmtCG4sLmS +MXuDTBs8Hpzg7J0glGHLRA== +//pragma protect end_key_block +//pragma protect digest_block +H0bopUu32ivTFDA3K9T8J8SS43U= +//pragma protect end_digest_block +//pragma protect data_block +xSiDBU3P55Z9nPhPcRJoLNdiEV18n/eqw4MStefAh2Ht+DRhQl+v927uY8KQbqfw +nwpIZW5JcvK+vwBSoCmQ3izGMoCW/UruHGprihkMr0VreOxFWJlrPD1u0UqjiDTH +k/yjgH7S3JvGOQdJvynT4m3j/vywf95vdesePZaReQhCVdx5dOXLC87yka398Ugg +vWrVRpJeU4kTi9BbdHEYPKNLMI3dF25nm+8Y+YsUsuJqujkdHUAhJSgOIK0ci5ox +n5boIolqTuoHq85xf+o+PPMwHeykh6Uz5Q/Gq2KjT0PKn9avSRilfMPNnC6fIATM +1foGRuuz2UiwAn4QKEU/vjNeY1mlfLY0e7cwV+Z2udW2GH0igdPzn2nvHeRtN8lq +zuft3kHvWFmSH5Sg8w1dlL18v+XbJnNtqCvuBPQ9pjouZV40kehzawEzsawKmODE +IQy9NEnFZ5DoUGm59rb0mzcoRUBuf6u46K546Tvs/NrBXPW3EBWjWwksK4fG4QHN +j/tGpttczSqXZLFMsniYk49MoPvaeS2Vw4DBl88reyTiyjq770U6nKX54tTGG326 +149y4ZamqD6r2bknCwDJF0rHoM7++MfrL87UwB7NW1cVuLTdhN23yAVrVazVvsu1 +suwepSGaJ30eYtCQmpJ8AYxmU7e00Nf8fqwh93DIZjYs3Vv4gvhuZczGBMKPn8mQ +7c0PuNNcs8lCn/v2f66Au0pIXdsNmtf5Igb6TFHycqrhPTZz+owjdb/s7rsZ3lXT +9TwgljYVP84wDZqvmUMlp3//aNZhTqHf0YY/ft8uhGrq3UCQRLVBgbXmtal6gdbU +sta/TkTZ9YmWj34P1zyUlgHFDk0mrxiLqhCcCr/D9c/8P+agWBxjJDs5sbATiXim +WjqKCbdr+VIgVV+BSiBmR3mXB47L9yyrF09Vw688wT2nxepsGW5mCqa+ecNhTc7I +VxekweOkBEQNDm5XluDn8OXr500TWc2cq/MGEMPezzCBlnmmdpGkSgtZHpGaVrt6 +ztuGb/1OS1t/+RDHmu5S272YtACfD1qyI5sJiEddr6qMarG8lCAU/xGROqMbpfc5 +wb17QtLRE01AGyh7q6KdskeuEbFbDSHgcbxibivQ9FL1z2FfG8Sm9vnGzPPGfO7N +Y0KKULp0/zqBJ8RVhzsmZo/BQkxKvNTm15dvoyIaGO+L3v9F0xU+tpKVwAwrYE47 +tJXoFchyEIW0QEZUU5A4vXu/0dyQsiaHWe0ZVTAYvI3AoilUzXs/CR3BfI2t3gGd +g6ft2mqweO3xtTYyvWQ16xtDqax58L2bUdXCHtOQWOuHql5BXWe1m0O3VfFhlgW2 +V/Tpq/ee1DH57rovVwAHHYm4yh+HPvZuzW+Xqvtb4vjWKQ55rMUnrLPkIs1AWZW4 +qtiSPInZiE+UlKWTFPwmEpzOMeyEEHPDzq/+gtBtNKDrnN/RkjqZlVbmhUGusgpN +MTW1mGkLhldfm2PhgRF4yl7K/ZReVI8GuktRmK3H5fy36eyD0yP7oTQCqZ2q5+Wn +K97i33FUKT0z/3lRMj+nOz0iL9CNqFMn6JpmrktS+UJl9wcZqBDGU5NWivx4ZN64 +r5dYBqUOkb6gtCrQQguKW1LB6lM/bH53OQ9OoeVQzXwOZkvdiBWmJGqoA3PoO+Jt +sxD5dMcKEU1qfOvWq764QS2WJsYDaBcKUrsZRtQWOnhAJLOibmS0zH1CFi9p+phs +w7lQRD6L5oe1q+iX/k65VDEmh3tgnpsPYDFVoz2QTwwdcxceq2TscQmD+vPcg2tB ++Xu6YyVHPHWqOopDe07uUqvHGNyK4FqSccjAIHzLoLJBhqn7sW2wzB8+7gv0QW/Y +Q4DRP/aU89/SzUbUmXMy2M2k3jsU12+yMY426APDgjTnI3eXIXkM3Q2uF9JT9yt9 +r7C1GnK6DbVh7E47BW8Ogt4C7es8orlN7vh6EIwV1oPK7RUroJ2XDt9iVJJqW5dY +B6rarGbxqspOyTbvClRHgXg5Pcb3RfUIoptIe2lm4B8tKJuG6XV8A/s5KNLm7IZV +ZFYsxMLywDnByltIyYE3lqVMjlmK85Q048KeU+uuSOSRLPdgEQYxTFn98vnKUx1l +k8mVZ1QWD9ZI9tSMGvptftHnmgKbapeu79JFerNvbfqfyNkTURvRfvMMdzWFbsVK +bNcP/SEcIS+aqmLY6lDiKYs7q4Y6ELDFSsueVGyG93fs5BmqKm2Dd5uBdRdnV9VH +tqGfNkhfqfV3EGZg5IbmNqkRZgjMwrWJWPYPMOXN/74ZUN/o101XqIyqo0PuAE8x +8SpssK/IrbIcB5WnQgFMk8nHseDgunesmPjMErskxxXAjIDdHP1uWR5mAk8oabMn +S1F9y2L+K3YpYk6U9WDvqtQ2lMxKmX7D53qNK464280g9kte7PsgKXW46+Vo3FuI +Dh5yIs60Gq66x95KENnYM9hrPmaYoFojPI1XeI1vQ4bIz2LfonAbWYzJpbppBpjA +L89n63glPedbdK5ORaFogR9Wx+M/7TbJ8A/fr7h4zJGZgzl3Px7zH384w+kvsKdd +FUvI+EQrst3no+ODS+Av9akSkdlfgSEIveS/q6zMdJ7TTABxvyimhvYO08LQOuc8 +IgiBL3Bi/AlmkKMOVKwKigngMFk5NEbHbAQpGk/j9H3BNpB/I1nG4M2/TnHjJEL6 +5h89QNj1AGjeZ2ipOcJO7HKhwIUJk1nHfXr/jVlFv5y1cTQcT64Z8aF/LvNiwT/b +swBhWw+mBjgwI5cl36ZEt5llEZ17RZu04zW4G7WpacqomP3TRdQHToKmCaX22q18 +VMHuJRbIdFKSw2nypM6Kn8vkzhspLM5pwwmx3/WVqt14LM70o4hZdwjRj6CYLFZI +58yEcFNpbDWR5Lyth9346k+lTqATZ9Ed9wFzkMtizT5R/ulm/pB6fXyoH5ufMUz/ ++kkqxjkCC27gksQYX4PU73l40jzXwKPKDe5Imk7p5zapC879G36ErxI2PfDZNgR/ +ekz+YQo21IgpqisNB/v6rJATLhM7ywb15JQ3qu/w8OGZOvqLfWjETHkhhhID2Cp3 +2v4BUeIuSWZ7HiknHICshfDeL1ymuK+P9ETDDFe3+ry/6ipUCaAZo6x7rNUyYBfv +gxTNeegmbxElQ+7RPD2bjLsJXXDzuQJBSDD5AoiH6EEI5VJ3n8k8apifeLtot0pC +fI+6fLZtFwZr8R0H/2Qc6oLUW0XStUkQvlrTiIITCzcPcOO6oxZXABITO9oUbE3j +4+TKcT3ndOAbi8VUz0ZPrqA3mOyjhUNbA9YRuc5sWGUnjtW0V6wfiHQpfnj8GA1D +xHfjM8VLW8GWBJICuq7kZJQkaLv3g5VLvzsHEZw0Hy90sLR2txPRVaGb8lBPSD6S +T713wecx0hW7F6rXpQscZ9tukk2oT4H/G5x1TBqFk3OIJaEB/S+xrmmiA21ZtLZg +bwxTs+XUkofxRHjkMTs0XnRdvlFAA4dvPesP7Xcvjoz5Q7A/o+jpTcsMPrFKPy1m +PZnJj9sJLeT5IqbbKwSQioJzFhpOwApUYqGjwrYcTABAyoo0LmxPLOMSiF3zjkSh +8fkE7rBUj4g8B6cjKxMajcB2scmwYg/lvHT2+7xHD3BYvBtlLl/XABCxSNVgis0G +TOlf6Jao3sEZxl3MRY7ybg699a+AXndPuGPH+omD7w4NNEBk68zEyih63nJT4Rjv +ChU97nOiGTaY/QxWT5dlWPM+CdJkYV2zc1Q5zmrGeOtoDMbpxCu4d0/trtgu8fI3 +Eqq8ekiSvmiZFinzFR5Xurs/E9N3JpUI0jsGn87/G5L9Sv5XlZGz79R3KVeP9Nly +ZJzlB/2tDidVK5xGC8ChtdsoFQAie4GFfhHvQFyuMBT+ZhOJRvPyMO8oq2VxgFxK +dffQH+ZzbDuFgbRe9L4GS/pzDNUybsVYML1Wv2ann3Ux2o4Kdq7WgqJ40xTnJKDJ +EJjlyif6HK91PovJd9u/RJ1Wx32EZNIEimtuc9QMKl2DgWutpU5GqmhDW8ghpLnX ++obbOY/vliJBqaKB5ZBOl9a8woJA0HN9WfwZZGhFPzAavpwnxvo1ZXWkL8EY+Ed2 +gbjCBkFgmYZ2nQbH83TINl4QJcQuqVWRZxuO9L0eZFIeni7Xi4lWt2aNPIK159QA +uQN0tX8jJkGTw85rdBS7MWv181aPQ/1wBvd24PfMsOPK8zD5PvkT/Mbc7SMiHtEx +fg4IeYz8Xf3c+SBQBAx2pavDPRnhGb8nop3/QlNw4Dy6wsV843aZnD9vUJhune8a +yZPE+qL+W+CwNWq4DRfInjzQncqiIzoN6OYHczXH8FVDX9/hATazPVTB7PuWm62G +1J2UcFWxcow6b0c1GztvYAKjfe9AIzFmi2ABjMvpwztSlEIvqdwU3wCyaR/PCOdC +OgEA90/UfEXtTaO7hhGQ/CaZZYdIg+15nrXqYJydgYfcZb9K0Vbt+MmMvEiFTQXq +aqLFtR6Qg58q7sPjkkMKpQUZ0ZTgtg5Bn4WW76L9xGjkhGRqHtqLdLxtB3oTIgsp +lGrC+HD0ynFYTh8gxh/Y4S0jMl2JBLJHEYlRcGefIbJWg1lmW3FhiEumjnvARGhh +LTAaTaf4XUVgh5hfHcbDEVqexhxwzVPndmkfY/4HHJ3UFMEbZb7BttdXZXcgTnkf +nkE3LxELdIiiPN4BLsc8+pU4i1jQSQyZWjrUfKdGYEUswkxBqqS/S6oJ3Bwh7qI+ +ASBbNeQNaq+S7najqTvvw/ybnVv1vMOkAAajU4ooFarcmhX30l6dOojaoC6k/q4Z +xSoYnZboqAZ46xV/rbtHIqIhSmALbsIu/KNNhWzAWqS++/0Mmt1u3TCWS3mRY2il +CnfRSr+sY9smcSXcqMO5+rCR7NGHlzGyZmmzg1mpqcMK46e/RXTwr7Kp5TCTytDX +4onS3i4SkWOTPuwkk+ZZ+8jYtf96QCo8Jjh6NxhpkhI0UjgFqNTfpEXkxBANNOlB +5BFU5sXzDNPpepPTvuFkIylk89n9lcNODhcT9nC0AeC18OAQZyRk2aAo2f+W8ax0 +ipcedQgQUMTdSYBV5lIM1D9bZ8X2ypjr4NvE215pb6WmoI2rA2YmVBFDTSZ8OO0z +uPhBpY02cenYl5ChIp4KO4BK9T2CALs9v5ZOui5g1fSK8NzrQH0x1FYHAxP2VFPX +PsATv+SFMVI5ira5n0uA6hlWl2BxXltf8+zucpZzFJ3Hy71mUgQwetYSdwV2d3nE +EG8eW3zGvBBdXzEQyz5T2COcLAmHaG85Kk5f1Dyey/YMEuJTXY/FPBAHJW4qFbG5 +B/VYZx1kxwdYGd+dNjtjL2cz9Cdv16WZGmdHMHbAq7XzMsffM8BVrlBN0EVoUyUw +DBJuD9ERh5bqSs732BBoIwI+IfQMfkQ/PTmp0rjSCJSjmOeHpzFOvFubi7VcYuUu +GEp0d/T2vvyq4qRAYhYklOQi70+msgXjFp4G+DcFYI+mO/Sal0QeCf3MyDV9HSUM +YGbBrsN+XXcOq5KRxP3myGUZPIEGv/SzvJ3QXP31ruBwtDSxV1S/cZJzCplVX6Xk +MCwCMLogDoWTHWsDEhWR0ib8ryMtOnZwa0Yqdl1RAzvXlBzqajpojliJyr069Y9i +Rme2JIlQNriCxNyhwSYYOEvzehn/eV2DyhZ6Z0OTjHNp1Kaqy72Th3qG8NELJkmh +2M/Iaok2KmIiY96qEj6Xwwp1iPQcfPNwRuwoBtN1PJuQFVKpEYWla1oQM1rwXUxB +3A93+vgJWCs5Q0EjijGhdJLWz3jLeC714arYYf6rSgXvdoPnJIUfXOG6Z4Zwtqq/ +JtiE6Be/LYMWbmWtZiRlvDfYJtHU+oJJIpK8im3ZLP63sUr8I2vR2Lkuky991UJg +bJdQZAEn7bl0HT+B2eQpVjVJeHb8XU6u1jv0Fw1oBa0E/YVpEOzNZciUEYnn9pJr +nYLxJHfEQSn9j0wu1Xc1LMiZPyT5+zddc7keoBk998QeouwuXKDl5Fu1h41EMOu5 +dsrGu5kuaPQQx9JI+wqt7dnJHujs3SNx9d/yOwx69BE8tUdz5ftKmGrL6dR4Wz3v +X0HqpxqnP7VU+/fNNXu4OIZMAkFWQ+L9F6JG5yFgtWOSIKJ6xN8BQHskUTa0UfH3 +AvTmJEqs1b0fbCqFeRYXhd8amSzhwyF/BfJ898IQum9g9VdNuwoIYmEC++sJDRV7 +nq2oFsw61+MnW0f8eh/jSRgbpmMCt+cXxUR3K0lZiU9CUh3F/+wYxGtrOhINd7ji +BuTCaxBO7sla00f6VoZOdRN+295B3GW7oQsqrPaylbntpx5pMTC/WGsJt9RMrHeh +ANkhnVKchQhAmSPF4gaz/Up1RcClzPslGOxWn/PH/FLPALns/aY9tLBB0c8RpaqN +0KLkJn4R6nwXAgVxxuukldB60MK5ZU+OiKYcAboTaaW0KvgMXx+E9brnehdkQPBG +GtF0YvGNM5o9SkUPQe3dsazkM9epBweFjYgmrIRH2kQLX3ujWlFnVUTeBzVzfIYw +j9HRrR9hpfInKLa1bQvWswWaqm9glHMreXmfPbsWITgi2A3mfzoOXPCKCVTse0Ax +3egy5UnVr8lVbXDOUugt85aaRzQSyIwOVFGLJYjox/IL9Sszy+v6dDSEoZ+HcBJA +4Q5BLLsdKPeongJwe+/JSknVLsawUvo1JM/w18jeHllduTq19e2p+UdjLGBHunSN +XYjDcgUDIiLjO8Dqho6v0rkhGxtkPrUS9u1Spp5S0PqAE5LMuMjwU51RhiCTBu7E +abmHwp0PJgOHErP0Ai1NhuXOlUELPhgLXHEt+c73ifIjqZByVdOEYPFzWJTOP0En +WYolXUFdhhy0PcmAK+qmqv+kIvicUIlCjBzHDYXt1KG9hriTLpJYzdlLQ+rrmxnb +9a+mSvsW1aWLxZlIFXS+gn8y4iyDCOL8cawQcIuBgl3MRtYit4YrWzP9di0XVWNz +pW0NCAOOhqTFzoP2CTjRJmnQseJFBIJEF/K2TqAO++L26LGmm1LxlRmYHXOSiZ5B +0jy9R23pZ1ObZUpLpjp1jbQXi5SfAxKBK/w53UpvJDgX3A4BAuXgls2+FI3srTdE +mWeiKaLpTPGDMCLExxB59sIZN8ESJwvTleBjAXJg2Lk= +//pragma protect end_data_block +//pragma protect digest_block +1Okcq3Bx+b3XH43kFoKz4zxqo5g= +//pragma protect end_digest_block +//pragma protect end_protected + + +//pragma protect begin_protected +//pragma protect encrypt_agent="NCPROTECT" +//pragma protect encrypt_agent_info="Encrypted using API" +//pragma protect key_keyowner=Cadence Design Systems. +//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) +//pragma protect key_method=RSA +//pragma protect key_block +AQeRdzVOqJ4iwDoe99zvboXiU5lXFKDvlhNtq/WoiJqz4LI8dneGqViS0qW8E5cW +dFrNY74BxRuU1zUyWX2q7ND72HLZ7b43cP7d8Tx0UViZ4YnpFDbDdItwoawze53j +e7dyCusjEq4t/mD6olfwd9QnMg1orJWxZ8cPJ5j5xikDWP7ePgP4c277SWzoxnac +zaPxeAhOFGBJeIchq5UPEmXGUYcv58Xb5AlMc9yeTKOd+qgNHT2a7+6pvw0nC/Xu +X53tQILJGS8ZfJDFjSphdOcpjwpyF/M3/LJvhukvC3FT+TWVdtiq9wFcgfuQvGgP +b2syN15Zt9silhfUS78i/Q== +//pragma protect end_key_block +//pragma protect digest_block +ITI7TKpnea8mGeIScDpwDiMkohE= +//pragma protect end_digest_block +//pragma protect data_block +tN84ozPtJgItVKSJa+JX3LCw5hsWc3/koaW74ODjnIcLsx0UhMpwntPtDiCxsC3w +zfCJ03MvTDAjpYybyzHUV06rZnOGF08tZzDnRhRlBHJqvuKGfXzOkR/jJLCojJ6e +qO2NZ0ZT0I1aQAN6RL/NsKYmA52bRdOP9F+kPbq/1pVTsK68pbO8WXEZqjcO2sCt +HTrkxMnP9pGuYivwzG7IcUGpdktkCPa3VDhQw9RYaDVCyVZX9x+OJKHU7i7xp96i +WtSdlWNRE+lO4BBRvXWOLaGTnCuvNJTeYcGsbj629X04Lpg4YxmOB7u49VNxFSI3 +xydQZMGQ0MrlmCGNiHYlocJLKoXc0JCFMbUPJQREK7FJslx378FNifLH8XQq4Oqe +WDD1bVzDYJRILpCNRnvbXGSdJOk11tGY4c1R/IdJca2a0qgG5xPOOPI9jxltbtlz +lBlpV88yL6EjJBF6SPXu3t04Hhz0nAh/5Y2U09q9nVybwdG+qxuiv6gtF+D5MnCF +14u9y6KaDa2+CszIkaRDudrhzE1PJj2P1zHrqqI3JWFZ1Z+t1hKxogOIhhZVl17S +l7j9mgjVTnZn6PTGpheW+rDfm98F9XAQ4UBROzhNZ7IHDJH3dsZ+Rz9+1mmAWll6 +DBYVxO3t6ctWale79Nmvharu5zN7A+wF5OLWvOXlcVtvHdq2WAbQSJFpIxX6avXM +9zBCsTjLYXepGS5klnvN7LAFIzkrEt5NcUpZYvMDCYHjDGsffS2SkkQDriJpqbiC +mLRs7mQbEveM+aFm7ENerH+pm+GeY8OhLupoxl67hJP3qyLI1iqIF8fJeaLiwoJW +wYQZ7g02ROZtVMNseFvxkyapzyoTfi9vdZLiglRZPvdpBmMAmhwSYfsT1kIrIo9t +KlQr+N58nrYhiPrv+5Ty65MQfoDTYkoODlH9MEN/AzNsR9Wx9BeEU2M9krv62Jsq +gf1vXputWAH6UQHCZyO3irucoGmGz6cDzjpM1io0pM3LRyE8qWjc6SMAOuAsII2P +/LTCsd1RVUtRAhOub11pSYYR2PCeJgZ0IvHlVr8C/KkKooIKE/0LtkTu6/yQBdsZ +vNAdQV0b+F617CfbwYODymEj4W4TWDZ8pp0Y1zgeJDeMWIPgGlF6A4Ln1/BRbvWZ +EU1heC8rCKGDCDAanXv+K+Xdl+ooaYmDY1NxDzwkOkWMMBnUX4lHd+P+uxaBypaa +LVWayzvBrjum/uB8yFAkMSCk8qx0ebLFl3ioQnZR5bdIbe6ht1UXZRRXJQt+tY0N +Exr5Mr7NNMkl3NoLrdKV5NkP+TtHmiEDJpErVF8Le3UC77H0rs9dLtRKLOLkdR4G +eijzsSdksvDqxixbgkMaRjEOjyBnxWKqE/hKWqDbSaQW1Kcpn5zd90y2rHCOJEAL +P67iCOigD49dJaMAdMIXa7eUE1zXqstWzj66Ya5TUjBddXooVljnncFnFwcSqoKH +OK6l0MRjAfjg5lyrVkAzn6dFQBAbobwRCfj7mvcVcVp6gkHbCzujnImd+eHngS4e +uayNLDNdUjvRfntRTcTYgkc2ai6CMPGfFpwbjLDNa8Zi+SymrjANhRNfIr7lDLwT +G8VD3KdEWOKAvxKxtK5Q9xmohB7Cnb4hrayjbXYHGm/7rm9pBGDcjxUx73Ay+3ae +P831Dqt5rpRz4WbL+qdfPL9Qp0ViA9ie7xnT781uhAtKjkqa+3OhqC9aYIHZ0uLf +yAb/ZlcXi50veF0fXiarFQ0t3CgqZQ/cP5TLpAgCaRcoMFTncuQSQvU/hChJbvUQ +dtx3O555HRlE0WX8BpEybcCG+XcBZspiP05bzxcvZVXzpxdaAurLsm4BE/KWlHL+ +GlZxNqISSYibjSGntcWMtLg66vmwy3FUNd2VcaSV0z4qfU5a22RoT/YmsYuOGskq +pIskZGdhIWAFZcDqZFcD1mu8S99r1lnBrhMzESD7ByhBmfn7fAAZUlYwyeENBhFd +XzT/C4iWLofsYA2+ra/VZX74BQQnBC+Pwn+o81cDJ7DWPQU4flYqY7zSZcbM5jlX +8y3rMGVQKUPTmuhOyNWR63eYsCDpjT3zPGJyHxSYW+JVIVWMru51jmlz0/Bh19ji +j7lQhrSK7GqaaFDpwTq7hb14/7dqG4jZdkMI9jFNLZiV90LV0CXKngkSwiNYf+K7 +dJRQzZADgoE6zBkN7dRyORQAsRDBlQ4DUnkEDQI6/XfTOBhM6cmxNVaNRSwvo2J5 +9lQejjW2UKrEmjl81BiAy8IQYrPMCAjWNTcFE4SiaB11CUvKM1U7XmYNbMizdfP+ +qfpn43CIHhVWsMsyWik3dvWru36yuWDI8jcSB2n4G6ql8P8mdOLirjYoTraM72ar +wz97VkNK0m2BohfELy8Lfe1bJwEi2QHFfM8rI2N0JRTBdke/tg5Wo7RnRkoiEX6h +VKF8HSGyG2uu2cOdqrlMVWq71fC/BPfvJrP0nZDecnjunjAyDhUYvo6y1/01R/+w +8veH7jSXJZ92krkoXCpMJhVvmZx+3Yy13aVZisNHxnEhGZvrsl7pORsk/YisYtwk +XqGWc3rnQVZKoPm8r3nGF4K6xlt3nnFygzAqterc7z9NWXwaCWdZfrOssRDBsYNf +xLqkiHwSwZDFTgQpXjlfljEE4nERDfupA1j827idwWpHPz5djzHxMJzhVH3f9zDD +2546baXSG/3uoIVujcnhI17RCakoA1hS893lLHH0OI+HuM2dyCaRBcbdgPvLVQRm +D8xmsU/rc57TEwSuP8AoT2iGe9zwFRdSqjopeK3TkIkVo1MDY6RYg6QI1AG8j2Si +cZw5UyNT912WbpZalgD5j0asxyqXK2BLATT9Btp9oTB1mMe6jRIAZ+etuTbSL7aL +HPjLGft6RYftCxMXBorz2V8T37n5xUVdN+NNxZesiA9X1VEUlml4iPKRFy8yqv4M +0HAupVEZAUPZFUkAKXsQ4WU8+Sfivssu1C2C247kFiahPsmRxyJWTxm6uRVl9Qpq +BVfvQRJpKGJtDoXN7I9Mp7Utwllj6+HgQGE5GeouXk967oqNi93wSMhNPpZF60ze +MDCacoLHmf5T8rRuZIGExdnXhNuSxTgclFyE15M248OGFoo7s+8TEca7e9Mj7nHh +5OfcCMjx4l6yAP9pnMqeM4hqjKUH5N3XPRwerK8GZgaTYZ+LLXq4jU2NIEGi9WXa +H+5PMUwCHzfJLa5BycXAomMcFjG8WhDEOP1urgmTBdJsfVS8kcvqZFa4wbnA7lOb +z/hx5ZnwAhqVE9GTIGq871GjPteV8sCMyuoy7Z8Kn5NAjKu8exz+axBuBORgrYTL +eGSH7cl/jB3uvcZWPs5ybDXTcp4ByRohAUD61MnRAyVrbdsf3pPNlFeDcA7Yn9lF +o1xGM2/O/kGLYx6dCb/HV5iHsC2txmIEzLOzDvYgmHCieRsp+72gs2SQhQilAj+4 +fWytbk19P6xrh8Fu5K83gPRUWhDv5bnx9fwVIvIFERgeqA1TycNAlVOp04n1qS76 +dZ0lzYSGmCZpAY7YT0tFBfyKC4fwrCjgEaVCb6OOejoS1qWjRIt7kKDGFRKrpmSb +pETU7TDnApeh7OxWRmKDgcnqrEU7IhOJYbxfF+IEq5PTZmhNAVAx+NZ0CVdrybjo +I4fOTRy0rrHJ1lvVBk6ac3/0FO5SszTlNb4GLycZQwpvgPlirK6+EWrAksPDUzFV +Q1pfz1jePUPYx9lwH9743tyhXD6VA+1kla7BnYpvvKwBoYIyY/jmV0q/Msj6e6xX +sszWffzRAhtzBw73tnjScxZyaksYwFUFV73Tua2aRwAFVRLwqhYN7yn6h2vT9bE3 +IP7eQkFyCdP6EkPcnBgWgtG9O6i2uDrUt0gIKGLThrpLs6bTDaj1kTBkUql87wk/ +06ivDdgVU3oQKi+pMeK7FizbB8SfbfIF5AF1+wXZmsUfhmA4KYtrz9flgF0i/ezp +EVEgYdB6KWPpeGpcy5Ow4nwnpeb/fLc0YgexiAyeMstHauYBPrhcFklhOan1ECb7 +Hgo2/YBzkDUmWWqAmopt1M8Mpb/mPdUTkj/zmGoWzTGEzDIrWd1ubOZbkK9al6sZ +ar6z/CQJpJjWBEG5zMZPtKryRM2xJ4wC7LYQL3mafDT0BHooE45zb1f7wqpnYrre +ys+gUrQARzNZLHDnxBoquidaDWWXY6ma1gKmGM9tt4tA2eypk6SYxJPNXzRnChiy +zccf1Gdk0fUKt2aG4qZjHKJcrbZz1z1VSuyqg16Cm354uff48ixAHrpv8uZAJ4XB +eHzIk5DP/l860CXzi1EawHTId5PsnUcuhReoapDIpMrJ9R2Ac/edcY1K9nYm29MO +rWn3zC9MAQaO06t78EpyTxe8jKCj5UwpnJ8FTuK8/0M8joT8OkNMlkbkJXTdiyTs +oQutYpSnOWwG+ZfnRnfC8exQGPPr/3Bmi+iBeXvLQftBglAUjnGlnCrXLXPxpo+w +oivQAxXCYhYDk8VfKdD1A5K2jF+D9k5CXG6ZPEzFBPpHgra/T+ZO4RBpFXL923zr +T5J+4jOp24NJGaE2P6WcV72lDScShF+eqALYQYlMtuowWL3wIugRa9KGHatl6/Li +SIrdlQ28iIUGBcLneKmN3zHf20EdwPN+M5OYtGHeCbId+sZldYy4REPAftSwi+TM +WX/FzmTBV1U16gnYyJW4Q8GexC1tEDQC+GZQXfX301ZUYR8mGkWuMuxz72od3fFd +10CR3+bjVwZ9wzOqpLbSwpm5yhH5373WfqwpLTKUhNAtPxfjlPQkbWAm1uNzGStB +BIpYg8OgYvjGx1htxaVRNPcon9O7ojndd6dbcXd4MxDReCiyAU0HwJKhF4Sq1LgZ +aTd5/B5GRWng5gPvEkMuOQmVlsNgFuvdjSPpKmM0vXVmhA6111gplfHG+bPOpAr3 +hRRkI49WjnY6OzdvrChO6qcmvP26u2djvaHYu3bj1Pr8lT/YijV/FPa7/2zsL2Y5 +TacIPImOZ1Fkl2s998oRTosT4w+HKx+AItENqI+9vml/nFxzSTSCVlCOy+8+HNv7 +p6I6k37m3Wy2l6PtqRapX/k7VZ8DfInTOsVlGHC8uzD8CPTjJK9hcaRNchVCR2nH ++VDXEF0Dt+FEFesByvjN7yhfHF0DiVUKPMuZ6gCEGiEcBU3aZdjDXCfErbcCv6f5 +iijrGAu0S3iyh+ktMSL1jjSIajlaECXRE8ys7pr7fx7MYi6vQvPR0FYUy/eFZm6H +BCNdykGGtopIAn3xioGuUnD5immhylwyi3s83Fzq8bZPnpHDrSTEpCGvD31GLM2H +3UFIBTjFQo6NX6iPPnKLH5BP6z/3xXOIIAM2aAOHFxOCVp3jd3Juni5zpmh+vxhO +EY9V3brZUzZjbq83/Rbrjp3hNwDtD5bpE2F+x50l+AtwQZtMrIzCUVmffh1Smv6y +j4wVZyxPfbgbxjXNrD+7B63pewhLKjI+z0bSxzGNGz4T9TUqqFilSQOXNr3Vq2xS +XucfI0wWXM5gZtwbbrKrpImEILJgKdqH+YB1jS3ZOLtwO2pCX27TTmpF2LVrbZcq +ocOuKPeioqmaA/iCnPnPhYmhIJyxRtoZp63uUHLorce2LIxGg15yKJ5k9hRW0JdY +30RWPI/Y4PWbDVhjBY+6GwXVspyFTj6zSTEHjuh9XxZI8/U5zLtViYFFy1Qpt112 +NcggD7mWv9jHJ9/dy0g2g0bdSNV4L0YQwmunsiPZdpX9nBjM04etGVLPi/eNNrQN +UW3y1t31iGBoR8/KkTrjaHykl9T6ubW8bSPTXHjT9TrWDpb0t4j2I/bERe6Mx/jf +FVVzeFvuAMjc5no6WuaUdSJebLcQ8JRygdVh7IPiRTIAWte6i5JHfNa3gMrm3uCq +MHpEnH9RgzAgSnuc2oCJrApNB7N93b6zuj+eYy7G2wmMLWQik1uluJgXdA/2kK6N +L6ncjAHyYLoh3V/OnfD6EQ5QCQSX5Mf1I9bRlfv7CIgw50QKAdPcyhazbT4OxmEm +o8raZ9CgnKUxc2dK7OuOZOkX5xxh46TjxEBVV2YpDG19q5PO+BwLw4egsAUf5zSA +N/iVJaca1ZVEKvNz/ISVKOYLXpfdrv9/wLy2RDvVCXG4Ftjah3orTycn5FsroVnc +dMyDD8WcunSJI/AGhtPfRgR3+CkcID5cEtcLtpOgllKDS1cyDncZxXa/va30on6M +qBzpmhpYYNUNApndAGF8Svu6O9DuRuN3B9uiXWPxA0PlJ0EbHAVzBa6CWaGoLnPH +tMFm2HQ678DBSyUzwz2fS9GwvwqOxlhpvqbJ9yjlVAu6A2DgWF3a9m9tDwL2Yqzs +okwu+Dxw3l33rweCtsXCy9R7l9M1YZ0I3CY33RP3lXaGjMmJ8a+JTFmlNqrdyS8W +VoYH+hEV6GA14pUP4fnPwvFpBHuGJqJUJqy+mJ5PLwv9493UP+qxHJkollXQkVVS +irdsePkx2wQyjaxOjKzhyqMKU0aDVmzsyHtLrPPLrcg3BRxz0QSJPRPGkh078xrK +gfv2F1AmPszqlzd/bA5d8WzBM2nNcapQytH/1sjmv1BtFdL/9jeKdKCDJHXpyzPG +EQZrUkGIctdFcb8mYCHgAky6UFnb6DSjcybAdtIrCSL4nXVZWrRaZEqEj2oAYhaw +9hDvyvItzluj1U7tzFoYYmLwuQ6rfcr5oBp3Fk1p3gManBmInkIKda1H9CUru8Yd +nL76vUDAWfU14zrkuKYS2iTNHxPfqM84R+ca8Ma8BWTsI38lqTg1sQ4opnWucpHb +HNIuyZyTzhBu3AArKfn46GjNRbdzA3VPp1hTTbcaob4DIbZKF06PYblahzILL3uv +4igVoxzjgxgVljBDLZYJRRBxWlUqoP2Yf1Xui+ngM+XXU5um3N9qMs+YSDWtMFal +/718ybd7xL98JHb9Rgt3HlrXep12Tj+MZjLh+vZDuP8N/xr76odkCJuBU3Wc7XJf +8W43sCFD7LPmh8821iwLhsqT/2sldj3qhlpMrWRaWlyFgSsMQkUNfll/aGOaLk5b +hXdH9iyPJgqMtgjmpiCyHxeNgZ+rs/zXF+Sj6iGEmskTVJMcWYUpmeRHuJZBu4jT +2w7KoiVLY4wO1rMyxLS0kas0ZbQc2hwhGiCm1RmSdGcwvyjqnj0RKA6Sm8jSg8Fm +5ZeQ2zG2Kh3zhYbRn64GFMTbg7tPHP/wF2L2yah02tsFix7Q+4N2Y8w/0nSIxWvn +98LEtHkP9ra3tKYg8XWnUkczx3g4ffkWayqLu+6RuE7LDLWGWHsIDjKLSXykCaYG +TH4hMMf5l9t5r6JKK8mRDVy0U9JFjme6yR6RSZ94P6nWk4YOmFaERZID7dG7PoZV +z/kKN2gouyVkiFcPsuvti5s4N7zSlx4/XA9GPNXAjSr7mzTcA8HHcZw2xOTaj2XF +Pd+6XQkMh8/gudBQ92C3CT5W3PEqtrhipsERxoNCNoDbGFylslMqzVRlt3diuf48 +MwUvJo9s3QodnX18DNOMPQeV82KXViLROm+dFTvXBepDxsi+4IMPGVREM1e9ln4f +W/3NIA1sGIfX6AfWUloSfp2UMpAAN0PNEqCVL5BOvMyVTd/nm6C0tfKRf2kMMoKi +wMj3J3GhQDCTEvNb9ZHVD8truQYrB+1lltgjusIAYBH1s+JivG1ubxyY8e7+rJ4T +HReXAJ6TvOpjY/4JcWkL8yQLJSNomagv8LxgLPSshTvyycR5UHYc4lSWrG19t0u3 +RK9uRf3mWr1mnzUjviQKIW7I+vo+llvg6bp1h6m3ZQQPquQV3uftcoZM/LKHNZv4 +CD477OOO6dSiFAv0NhsOOCE7ONXRjzJ7X7golNuO+wzRnDvGKHCCF3k/MdZlrUvW +6+D4xx5eqORujSoYZgilZLFVpzvhJuBi1clrTv8gs85SRJJkhtAQBe6OhoIhbfOm +//pragma protect end_data_block +//pragma protect digest_block +GB4TclGiedNPwOlCGOg+lt+8X2M= +//pragma protect end_digest_block +//pragma protect end_protected + + +//pragma protect begin_protected +//pragma protect encrypt_agent="NCPROTECT" +//pragma protect encrypt_agent_info="Encrypted using API" +//pragma protect key_keyowner=Cadence Design Systems. +//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) +//pragma protect key_method=RSA +//pragma protect key_block +Ansv9YAwGh1QaXL1XvJIO4maHH0snzDgp0De9+9uCOGT7CK9+Roc9kV8pfYNuPlx +wSpH0ULhTI6FHPRKT6sQFmLuiJ6xFw7VzoVhPmHhpZSF57Tnwzae65R/Q1wuBFsS +VF8eDk0UtJJQ46qXepGqz24I13aL9v3MvqCcL5GprH5TkwDCgArozzr2Iwg5KsYG +fwuEPi78tJuSZd8J+iQ1mJhN1xRT4EEGZq7Q0SEJk74s8r5DQYoVZLfrqtInkP9i +gBebjMdYOLNlwGBFQJxa7r6QuNiRihf9E/lxc9CsNGzgLcfF4KFl36kNJJcMORRP +yKmksiA1VTS/ApNZ0EH+uw== +//pragma protect end_key_block +//pragma protect digest_block +0tRm4qYvLsm4+VVCglvfy7MBywQ= +//pragma protect end_digest_block +//pragma protect data_block +9NWSUs3T6JqlmsubqWEDqL68Gzk6byUddFxu60jMO58UwMsEKSx+xGNyVH6GtgIT +gvk3MxLAUvKyLPY9Hlor/Ux3oaY3XYay89Gs/r9JTdz+eYvoSRmmTKfFq61MSOxv +lI4GTgYJrRk8tpjkAFiWNghVyjR+68GB4ITTxWnrKEq3dBKKNlwzJILw1mH/odyF +LCvpXu4+bvViiJjz/h6av9ECRe/MJEUQ74SFna5k1ahPmRcJT5bo6ebKz5UdpwkS +ZLsVYGTuDceOTKYkqs3hM/DRalfrb0DZshkFK6iDUV2J9URjFO5KZLQNijCjVCNs +kEHoKLOysIvn0KHNuvJ00ke7FU6V31TR7UyurCQBlU52+JnPdxlAZHLSaHiHuTsy +SFZDrTJk1IY3UuXhCnvUQA1GMwSyIoDB41cGOLquARJqXxGZ5wNoy5jsTIyZCZpk +ZMLip6nBXttmXSIJpDuxC1honfbdFXPrDTYC7lF+CW81FmbPRjv2d+VKjYeEVsev +nkTGSnbXdhKk4Q4gFVISK0W64QuYgzi2cTEAo0088TkX2MI0ndlyccbVXKp9Nm28 +/ZhLfE7ssUzDSi7rsuMPSLt/jy4smvTd7QXI2LizKBXrBLGxvbcnII7/zoG0KqIW +oFvWE/tXcgpwnyga4eu4i7/tGxaZW4UanfVqlgTKP1EX8OszabWe0N+Kjdo+KslT +jSadkgAE2Npm0ZxJsHQhaBjNAkFQM0uH6FS6SPPbbumsjJedssMp0Q4qhDwLXl2I +grUwgaW0FMP+oDDaTx+gp0H0Y2slAjROk5a7N2Kgok4PBa7XG52chWoqbLDGwiDA +Cw8jvpKVVeTyVpsWVMGURcOdkIaJk1aPwUqocMDYQY/G1HAm3MU3HbCm9iUZAo63 +rVBpl1h8o7oCSTI5UxjWEoooZlwl1pxCC3JzT3qCceaGSFKtymxP8oKz8ALdX6sQ +w55eDoJLE5BInO4j3lppUgXfsmYirbl4bgZOE4X9o4gdDVQ5baQrAvcBUpUeleBB +zsXr5vVaV9te7bsHW9eQFxBBfzINNeadH/0CRfPj20HvwYnIaeY6tKhiuzUuGHzs +VqTPFnAI1hItn3X5DX2/IuiYKOX36A+7WrMAVtflljOf/eg6wL9ahzYw4BdKdwqX +K1trXc5yJeUEQn64C20zSAWQj8etl0DKQwjvHFfJKI6BkmONs2ppEK+ptqglpy+t +QMkuRAdgn5U4XaXwWdgIwIJqhE8ER48kydWNbicjJJgcaVBu9NwfCXi/LopVHLqp +xTdnl2us6nOOxgVtvBF7m/6THG+1F/msxs5Vg45oLceCM8FaOascPbYfVPQLPPjK +n1VxrseqfNprPnbRxFoLb2T8an8649QjqVsLZzJpMVbi31KDKs3XGMi0F+qYCED5 +5XUjIZAkD5SNUGwIDG29JOfwehVB5w26qGRXx/QJ/5gJpJU17MDowZf3FdDpGiJh +KojC77GGjCjIDkDCYuiRgLda4Oa/vRoF+XO0Vw1dHJioerJTSX7p19NGryfIDCAs +X37RVc94+NctN3ySw1HyA6wzFjD+T7GN0ghkk2qv85BEnDTm7d0gIzXDTdLknelm +/zuGongbnEBA3HnLhvMkdnNMS4DoltPDgA4ucdLbV2y9/v4z5OCXattvTpVvgUGL +MhvJeOB+0qqIwAFmsIvh0FSZ4WzvmIKeoOEjRMMP0zPBIUzAMhpHwlbcyfa5o8xP +DwAPWKPUgJM8QU8mx8/1tP5pClV/WeDGHDV72/1wlk3cbalwVW05N6PseS7xxgT/ +LMHD2q+tgHA1WSx4M9dUSC54l6ZH23kflsFZ4ltTCxS2z5kWdCeh/TjqMSCpnbL/ +k6oY0vaYRBkssaHZfzHoa14jmno9SRsms8lkCoSYbQA0zfbZTYOOzN1ie4tdcYMO +UHbIUPGU5y9wj8mLdwHu8U0A9RnwzUl/3H8s/pYWigMWUDbDeu9TOB8QVFU2fM+j +ShquQc4E5CdtvOOGkBM4mOdRIrcfBbS/dfb6uyC/s8uMtIhk6cz1Vs9JM77bCxpN +YQN4Y2K79msgrxH9kLtg9TtFOZkDzacXzlKWKL4EJyCPC6dSOgz3M6egFHsdMk5K +xPQmA74i06KrxetqszF36ZRzUb2PaXr9saHZbJQSUrDtZT0C3lhiRL60hZPpzO+M +ShiDak4gAcqzhmr67JT2kqTiQBZsBcIHj4IP5Dgpa6U+id2w6P+CT9AyPL3OU1UH +iDHF0PWsd0mXvRdi267k5nA4lDACaqyiIui0FBEZQuWyRIJ58xqsT3YRAlpk1Bn4 +5TlqZgciCXKTfCekp6iDr02Wwk+CZZ6timjx2S2pjRk1ifjoDLlyAxJKczwAE4Vz +h3vzPoiRpQW1kB52NH16kacZCn75ujjLBzoXAAAwjgHpDIPsp+/50Z1xNpWVEMTZ +2bXXMJkRARMHq6O0EFARL0HlyIQwY+kFd5DdLQA3E9DTdlLFnDJmnTTzUujZq4ke +1b0St+TR9wyZkbqFw6rRssc0DcPJugIFuaNBTLNQ8nFinnQu8okJIsyfF5+EmXfE +07IE8l3DQgAor2x0n9bc+KxShsexg1o6DWcyxNhZ6dIAiyLUsCHA2mCsXwPo3+KM +LXpaL7ZJvkTy2T2TevmvBUirBpzCXJEDNPDZ2S/1aXm6hFdNDXnjNzTKQ+wq3oAE +LSvRMfHsb+3Wf5S8VdE8nxWJf21H02DpbNWv+jjDVsxlH9I8H8w81iQcoKXecc+/ +s7H2cVj6pBvd+3pj2t5duH32W5BZTH7htf+lXJ40VPEzDDojTstktTq9fO4b3Tqp +t2iaToU5qwZ0X2bTEsJL0rOTx/IvWe/zpRsneQ9vUkDMxjbsZbfhQ6hx2LSsvB9z ++vpUAQcXHEmM4D9SIuKbFzoAiRY0ZztIA8DcFKwJOSBBEOOGRI3nandbSyiXrnG8 +f3AQvX3vVkoyVR2/KdcS7PH0zHTi9dWDo//PmZ5EROdx4oNfM0uHs9HBLo44MMzy +irMbyYaSHLUEuUWPMjy94MRdqSs7HsqwZPQbXfkgccnKllSzLlqiwVk+EN2Q0rmM +ZycFWw2Y1ZwEmlFkbBaZqmS7Y2Tm87XJvuJDbKOUAGg2ppOCBwL74iVEx0E1Tj+Z +LmgaR0xZcsoPhjy+2+TShEN0Qhcuod4wrFScCMnR6QjulLPZaw1ogC50rj3yXuSc +ZDRih4bQ0U9BdIptJ2g3v/Ks5/+Yl5CHoVYhSmqz7toBPZmjS4Q6so6vnVp7D8uu +KTJg0DH2iY8cV6n0JzO0c857HY+f7MtnyCMh/2lPDq7U3Nvvxb2B2MgVxPK4tYb9 +upAtk6R6BQvYRwogWvso+0lMU7gVAlk+hAmHdMHErcmbzjHW4Y5QkHPI9mxg6WiG +sWhd78YZ9+REZZaO8aI1A2p0YL5rrdQzWuj0wVHdnWLvyK9XcEi6suv41BO1S6J3 +R2cMYqmOEYYwibxRbEURGYEJdBccLpCyk/rQ/0tIgvOnzOx51pfcoBvBjdiv0JpZ +nsJ+iaOceJRsHtcrDZXyA2qDnoPGTWFlygMWMKSL+fLXu4f6TpQrlM316w4vRhEv +OPWnxAFuuX7AfeYM/qBWSb05G2o9aXWqdPAgbrxs3/1+gAyWN51/Oe1yK8a47V0q +LYWJqZmYzSnFMvtSRWXHmmzxn3B6egMOZl+SFqtJnlPqn3keF6iXc3Epg2q7se3U +MmNJ1oRuONsG4MmGLM51CpI2Y64zWpeXA3IQj7lHTZbSEX2D0hYACdzLchHpTYEO +F/N2KN9wBeWKLrLsyqF6ZVCD3dHBQaNYRfVBFkJzUk4TsEYz1u3EqJJ9sqkOwgp2 +GeHKJy802wE9cI/zdyaIkRK0Ir1msGoea7WvUfh5QR6NpBPQWizn6krkRlCxACTm +EJCTNu71e9tJCMGAj04y7yBdob02T+n85suG79i4E6rRZC1t53FHLFtVf4FZvTZw +TUknMzLJO8Z76Y5bZu9YrdmgTRzJvDyeIxPEWa3lnEcPP59lXffnpDXxwWo09T76 +IY6obnH+X3Ft8ny8mq2AOOYJpu/5/dDH6Mp4bmcFO3XUC6fvkgTMx+Oygtxjke5U +1qcTFyhncwUUkkedfPGpqKspMSrfwXT8TQEgzXXC6mVmxCSx0s82q09TLXlCvlUZ +2uavraV1L1vOyi8t/kznmBSAcvxSLtgfa8RuxPue0gjQatRoUvTRkL2PFyBAJgew +KumA3hH++av5OgvHvmk4EG+WcS5xKgsKWmPyhVKlVUFpAv7bNu7WBM62Asl3Prv3 +08mVo8lMkK+Smnx2N2Ya2M+QsA1b7wPlEO2w3MHYaNsI1uGPJg1ldxECGpukIWyn +aJ2A+gvC2hAydh/SOJWcRVHC/U9pxoAPjPnSKC+6liwQlR7AnZBHX31N7VR7/u/R +5MYdkgwHY1VlZwHBGlpfQR9gy7ALb7ndfIxxM2JzvQ6+MZT8xmte+QbLTAwZt2R2 +/0nbpB1AxLGnHD6uqVov8pgpCUQ2bKbUuJbOyGU73ecfYLj3onC8Igl5ksG/VgRC +8c5TqtBElkN5LVsCuoGhhBk1gstYxz8AlMEvknpr5qMp7qcNj0rJkFDUJKkJjWSa +rOPbrUo8tZ/aixj3E0nqS09dwEMbS2ZiOv04jwUad4ZdhpCN0EcIe6kQIORP8rhh +K4Dad19SXkN1dq+5C5CaQjuOs+CfQ5jIN6TimLA1LGgcwWfxS+EbGT5RY1xFRBVu +Ekv0qCyghdCY4GZen0568tDshlGO8+k2sSsEU3yQo2lPWeSFUc3Nhe0p8KWUa5K2 +KYk0yQJOYaWY1ttkyiZ5AWEE8FnpW5kLJWDDb61ZO9GYCU/6eVeWCmrzJhO+TsCL +0C8WEFKNIPHa423WWDaghNG3KomR0CtF7uKCUTf+mK9eAfxxrSn1q0/fIrcc1XMj +iffaAM1McTLkkUWjmgJHdKYMK5jRl05+15KG0N4mCYv3itsFyJCsHs8OF3Hh2aSU +P2AOvclZP5+DvLIqnfK8wOtD8kvDQOzj+nEvuWR4rgY= +//pragma protect end_data_block +//pragma protect digest_block +QmYdJtuhCo0aZM4+JP1v/m9eIME= +//pragma protect end_digest_block +//pragma protect end_protected + + +//pragma protect begin_protected +//pragma protect encrypt_agent="NCPROTECT" +//pragma protect encrypt_agent_info="Encrypted using API" +//pragma protect key_keyowner=Cadence Design Systems. +//pragma protect key_keyname=prv(CDS_RSA_KEY_VER_2) +//pragma protect key_method=RSA +//pragma protect key_block +Amajp3mby2UDUQLdpbYiAw9tFvXWC0k0x3RvEBRx1c7yL98M0GQX9AuQAM7ZWGKJ +cFuoIgVye3DoC/kXHvDRAzLJVaNEIXzaL9LtEBb0LITuFKpVhVAiUouMtvCcp0gm +C3y/rHeZEZelkSb4CpYPOF3H6YmH1phTaLaahAXTntOJAvxxNABVVs68XwhFaOe+ +KEuopJkLi3hkRYWeaEyhj9kqC9IBrmXHUJYQ4qcIGIAl4tgHZPBv+0C35Cyg1Kqc +iW4Iczy8v7iNdsFAB/MxgW9Q/RNowBYIpnf61pXBeMFbwIsKxe8bTS1xu6R3+/19 +3kwGS0I922iDeQiFN3Ir/w== +//pragma protect end_key_block +//pragma protect digest_block +6EuaYA9k9pp62W1ll3O8D6cdfeE= +//pragma protect end_digest_block +//pragma protect data_block +2P1SP5SmTOE7mtxtJo7zszroKRkk1HUMcgSUCN9R9oRHJ1cWYMYtBi7Xj+IeI+j+ +rm41BpMtdSTMHzOQg7el4FoK32q1TPwHrqUyWfnbsozT+29fKWwaL7u+Xul0ks7C +AurHssgNXOb8BXqEVSPTL8By2mFKK07pTIf1tA+2hWYJR62nCP84hT0wueFva4U8 +4Sgx4FmDf4GeDiKz/V2GfaP3rhKeB3TZWrOe7TYiAYtORG4O6Bgt79RzKGQDL91i +D74TLgVlBK8tUFtFkkGxqC2oJJM7WyUrYiZyF8NLXFsriSzCXSFFFQPHXPLDL1FD +RKR3o/6/bJBlAXtSK3zocvxL5gVknEkUSuRQ2QPKdybe75qA5pj1DlgURyXGhQCh +jP8odgxgBFLi0agq+BZfa9h3PZxM6tyobMhVkJKVZ/61Lq9wpHRuwVjlifMErrPq +5fvNWo4R1OHZyCKhf1BRXl9B8mR0KnRCJ+LNNE3CzLvjNzAZoKmpjr8hcQUHjTrm +xfFkufVtjwRUJrstnfmmzieL6QW7b6DGYsezEeEQcm7jFPxLNTn7sRPFb8dyS+MB +imyuWHrydo02j/gTWXYFv95/G8YZ6DnWwgMg2pIMvEnI3JP+8kzNQPH8YF6JIMgi +XS+XG8+0dGIA/FKC8XFwYCZIcS/p3PgYWH8S798Vdl2Ty9bo1Qx8SquB0d35+Q/c +Z8cH6ZGk5tJJ3tE1UqvqZ5CurtjQpDbfU6sMocP+q2PjEpUI7xEvK3wVp2dgDcyC +AriquFPjvXjBuVYbc3C/acE7JFt8Sfw9YaLPfm3O4XVlJFwNRch7GQhEs+P05/Jb +c8VVZlTxV1iPBvbKWn25Yurr1oLwf/O0BITPFkwTzC3oUxXKxY27ae6KYt/0ezuP +RCnpGnE5oDMRIpqyWfNgOm5FzsTgk0mW9PNtiBM7dylh+aI+3MTRhi7yOF7DVrA3 +2+i2ySBjmhLxZUa4YdPOkAsuYMS66+nWeX7eCSvaiwzUX55kcf13jkmLaWL8J7Xo +qj3NqMxvHtipE7y+tw0Eqomxc511UBNg8r2oDNsG2Vd0axh812IPqBih30Go7obJ +jE4cLE/lMTta3jKhZmDLG7qMpqOYs8TyYw3Dro2ijonvGRjPU8YeDcyvDV0dO4QB +5qNV/IJh3aUvug0vwfpnPCACmfPsS4lW+Wnal4HEHzA9vevbRfwAdCiDFdm5X4mf +SJplQQJTIy0/hb58G7wDbKnTIbKJq+09n5KFMzKucUr1NDk4wqJXpyAcBQxlIO7+ +ZFMVearQMMvadzYTt4b652shufiRgFIWUfmj3qBr95Yw/mNktU6mbOlFJseIwy0j +Sf/43za5cgXFf0ZqurDl4s1+eaSkQWkmDtd7l3uoblEqPdrj2Rms6xi0E3W8IRTd +7x+7w/D148akJN3tILwi8w3vj1cU7qBR6xEflQvpOJqCjep73X8hO3t3g3KzwRCw +XWEA4EUS7AF0DDfB0LUfNyfw2+13fwwZ3PUiniFd/Yfm/wv49O6ndLDa0p5H0pVQ +FJodBvYjgyF24nI2RE117sYjulpO7h6J83aoc8xpPm2AjK+uChwfqFCenmCFdzb7 +6OyvZKNeE6L7KLFDDdIMUR1e9WQc3HHeiVHuTcrPVejDfDVM//jaIKCdv3zIKI5P +ud1xLhoL4Wwqg4e2eUa6sQ4NO9h9Nsun3P8PdisAxXWvzj7lYpipfwTFlzp0QRbn +CCyQFRCU6iBgbavtYiqh72V0MwMX3K0aHzzZfZOqgAJV7uzVQrHM8SE5asja/Og5 +l+ABgZkKbuBWWhEHKW9HnpN2quEIpEzJrUZgXj2HpJFpGz1B7PXh8JjP9WwxYFFR +bNF2sWXolbXB1Gi1x1C91D1r+d6+BWq5j05NkojEqx5ZLpr9S0BzpTfo2uX+QsJu +TJwSJttfJg6GFOTqhEV35c5Tx1jCEY1wVKV1EpqXgdQuFi/f2HiQsQ9E3F8Z/vab +YvIaNq+DQilQ5aVbZscpwC4GMBUFbj88Z6TllBkygJ1rLHISNmpXsgRch8F1QuGs +tYFYn92x8LoGowkyFPqNJZno9z/90H95cBsQtWm4M58RVCwCttMN7j2p/5VM2ybU +5rTiFRAX/FMc+VJ5h8IB7FBJ8ljuFeK0WhwtcN0zVB/nghXITRDnWLosOkTCsSxr +x+pq0SBv0WPxoZk6Nuq/EtVDUweHnDz+XGRGyKk0/s5j9yiEDSYZ2/Cjw6RR5uRo +20H2tOSATxmRGXzEF+Md4RA6U2mpuwtXasZA491hK439jVCaga/qhaJl/Fa1nLJ3 +yRU7CCRpvT9XAOaDrJiwV/4CRQMkM3gtDDVdr3kqVM96SxL7Pi9Wv0WIf8Je7qD1 +OhTW0FBfDpi+GPzEMCA6KMwkPIfBpg/lctuTtKa5y4JuSo78cSx34eWYkLN0tBtU +paygCDHzXOG1pan7WdZHSmcHF68oMbsX7DxZcdtS8DU25TRlG35UHCv2fym7x8lA +5PtI9pHYLJL1JOZHVcoAtKkHd1ZcIGhuaIFquEM/kY31dXMMWKW25sNEeDF0WY3I +wTeiLBDS+xcPyZzF5WTbccoVSau21IuYCQ6tYRTsG6rIFHUdxABPk3CtHyYEhFSp +UUi2vRxFvD9JIWmOvsn8joRHz1QNIwaH5ATY8M9++EJF2t4sIpv4MWrCJfF8Ao87 +rQL26AXu14Jy2UhcgoLu71llPikX6rQri54EmvtQhzS8Pd8n86TpwCtKYlEhcAVT +aXfLhl520mBnoVFn9OaXdczxDqt4GBRjuFtGefb1fzrxiZhYiQs0g1CaZJxQv8ra +uakN19vAlTR2yDmkjgUJ+ijkLJw46HRJbTD68TyXhyjWDXhfshPYBP6b2X6n1Yg7 +BwY+u0p1G7c2Rd/xAwf1/37NoBjZ90SFpuIODwKMUlP/bd3aun0KaN3j2AaypRS6 +nHoqmgZsZEpzJTc+L1L4ny34DB7ubrFwd5B2E7TA78GsYCGmRflai/h8m0pAuRqK +XldhZAH4WX32r7454/mI9pCO6W+iv1S2OVX840ZrLiHpdyngfS2bcxV7A8cLVjG7 +NQEAskZDxxT2JxHm1giYERV0BcyrqwzUNazY5cAgT+kSfkN31sI0oQDOtLB1yJN8 +Zqs4UT+FASLzgpvcGkRiqLX3L4I8MWOm2OR7zFXmc/ZozHmEdCF7c/a1qh3cTmTu +MhbKetYXsbNkXAPLhRY6Hahn0V39o0GJj2sQipUeKlM2OfuXnFlERt34ETmxn3ic +cTmvKE26Y7nEaLp0KxPrp8k5Y+VUJDuUAOq/c3F+AldmybQxBet1PENMunz44i8V +nfH6a/fsQlVToG+yvksWHI7U1Mc9YMW0eDKWzXIQB4i+qzOqzscKjc/ahR5wW9IC +xAbMpsPhbh2pWFi/OkK+9XohVvErLDGuYTmEHAhcarZquamxVdr7CCoLKbBGYZf1 +4X/adjVJMZsj0c3tu6krLNUy83NCHcTVejMkrgsPEeafgnOQi+7BrtXbkzijKIyz +BMXa3+t07yANihqk2b7Kkq3aN3qcdUtWnF+lj5tZWXBXqha+DmOlWimSW1B0Ps6N +T0uTTxl9pKWiJjKLhRG4Ixn+toC31fKdlbkLagPm78cT/6yDXB9C0oTaWYij/zQh +aVv/XDDpbhFW5xsOzIn5DemvG9jror22aJDkwRcxLv/XVXU99EeMwEGJ5AtTisT3 +TKj76hHXyB5kTQqQH81iF5aTunvuQSyTyeuNYxolDJMM7yDGtMwzc+eoe1zf6fHG +XsZmIYbjI0+Mw9elkudWEZT46QhAU4evFlwvs4wlI5pvf5d2MwEDxBAlFZz9zPgN +bx7HyxoBL5bSfNrhgDTxJM2pIKiHtS6u4raRH6/Njf2AWWkZV0/FDGixBH8vLwoK +/FkVLrTuay0z9h8/j1yTdDeHiQzFd7YzyxefRZ0RLZcJ0r22eAB0EYH+/tuv0Kju +/DhkbnXGq+py+VvJI3nqQDXEFc5cUPmpw1WEX7C4VkXVOm4QLwLuex2BQprlMJDS +XAeOHIhoNRiEG1BtSxYzP7CPYQtN/SAJ4h8Qb9Ah1ur9G0w6gLGqIAwfj20F5jjv +VPOvdx17iiFPPoSfIYQlGDM4Gac1UjH5Uc1hZwqsAqHze+X47DU9+8NbTza64HxZ +QphLBiTMPR5uIp39eRbRd2k3QHMKPFWONfdG5Cwi0Z7CmYMFtl4cKoTZzs2ahLrr +wW7n6Iw6UIPQRZ1d6ymynbWa+3/ip68PKd2wAYuDz5835dLjRw3AHw3CJR7MHYrY +8b4Q5U+3SuD8dMqGPIqfKZx6t2lXCUjV/br1O+evnZJCfg64Y3RNHlzaA38YNnKG +67ueHCisslw0h6ZF11oRtPywqm5RFuZdyTrBHECZNVLU7F4qyFz5H/e7b4hq5xDv +nVCk0FMPT54NoXtWdxOuTD7sscICBM6Q+nHxIgmKGdCKjEXeUOz6FmfWOIuJxqQd +ucoGMKzLX5uEPOEyGYAmuUKp6LFCCX7Muxgkha+K4UT0sDk8/RyV845MSHRt5qP0 +LSi632AbpcVOavbcnaKh1WFdOtoWcRJX8jLVYBrq/EJ2Qzj9PeTQx8vKOSaTHPnq +aECNk2/wC4OxfSqz5T9sx1uu4Eg0W3blHjDjO6iYT6wCcT/7PEqpLqFKBoLGpntD +XELxIpHI03tm4uHgX1cTT2+jkr7UibWEmInP/qnzcaA2GYwkGmCgLZam3T/demZC +6qChI/Id5G9pUdeuTZLddybqjpw/8QO+acSfXuDRP5G+v4CNrXRU1WZgabbBpYfS +LWaUeUaAlAtdqf9ObKCLTc0V1aIoFjP//jKFdf1M0hzce4q7Tsc6kxuNX28pwQRD +2KqoYB9V50G0HhzeEATqGBTfSzjsBj3x1VmY9YkcqibgFpJndMq0MoBppUjnc3Qt +kBUuPWbFih01R1b6Ht+3EcSAZv6WIi/e83IMNirgw+zuYbRSn5GapmLhV8Dq8oQo +vLhUjNpUhVLP00VddE9/Y4nojU9KjS/59T/9+8ioBVnjguipZ6kKvcFU1HPmppA+ +k2RcwnOBnRs+SWRgR9rGJ5hpA5hy8EyjbFwzfxEAKAzd/pVhlErdHzYIPPnNmwob +ckCU3QSxaLLCJ7oOcdEprMFFBbYTm4/G88fzRktH6rq7o0rCMLQKvr0Kziv4X3LZ +9tVcTXkDcBY/zJNivtC8e1A4VO7keTyV1MkLbZLeC1rQDjq96xAJx5s4p19QOJ59 +wjwMM3PHrz/Dg2ImChWJJZ94o6u6teA1XpgO5Bg+y/u26WRQqhb0qZWdqF3FqaAC +Qj5GNVF3yCmFK6eVvZEOhHQenPfhuGZvdR0knwwFukXgrYb3DKAY2WparKQtpQh+ +MvcTXHW5HjMIO88P2kDSjvBL/ktRKPFbe1xhTLzhLYE/Tm0HMIrzRGIi9obYTaMm +UYqQYysMHLRLuzZJMOcUYHldHkOA4gwgkBwVhMGb3Vl71drTcYDqUsOMvWLWPJW+ +gpUEE9MiGn4hT97unKLHXIyBW2kg7c9gQkEQ23WWJ+GAojmDlC4NEUKTXGDyX/Xh +f1W5+F01+w+o3bZECblKWEuc07RlR5DJt84jkII9LmbNUM7vMjuQJKvJil6v/182 +iz9bN2DNCMiVZtDgQSla41z5OgYCg52ofjiZaOOTvkg+Xl6V+k8UuZ29CdR26jRZ +ZtcwPsEDUts1OwrvD6KxeMqgjyZtu553n/kT6Rb+pq2MMiZfoWq72xnWdBEp2nyT +hLz5nmgiOSALf9MSvk0nL5VaGTZZCoDGQX3boyKINBC/wNNfEpaYAc9GN1HiLYzB +nZPFkmY8Xi121pH0gwqgSe/1Dk4vsiRfV2nvAVX3GqOfrp0cqXGCT08Xtc9/ibcf +XYVEHbNugWWShNeLF4OSfpdSjcAXms30pB6FZSqkCXsA94TD6ePziDt0pn2WKQNs +GiIPHyWb3g7YbgX2H1IgBYeyYzw6PCMJy2B5jOOa+cA8Q/CTAAzsqJMPQlRCM58r +EdPr1IxHHJUruGGe64G3MAvrC6jHIb2tzbWJ4qAHcev6ZfPKWWJtX/WS9ae3b9xU +usHDDMpnhu/n3APClE/ucjBHkpM9R3PKu0p1UYeAVKpw6ltGZkcasJ90aI/x+HK3 +NcU+tGmdYkEQoSlWiVbnoMLsOBAutTiAP+O8KUFUEZDGCjBjHZ5/kMsg7wrIKrD2 +bA+uvDy+NQtlrrTToPvnTPjIWpHAhuAOl7oS9ltxjUFCWYQyR9Kok7dZJAwAyG7v +QJDhtVVzIUlAJimX+T36sgJcNFEp8MrDqUj+nKxSWQHo2pFl1bGUhE65skulIwjU +1EpqX4TQYgNuscbVSfXzCnzYZoiAwxm030CzAXVY3TKC+F7l6+Bth9+2tV2wMsWm +uV0h0Vg7PxW4VX+shxkn35JREpt4rQvhtPXpnMpS1rki9jn+/3iyTn8ybfxcPPZt +fQEe2KsYLN17nskTtsoGpMoOAjLGLPTBxZIjzHfijEThbTyQ10sh4wWvfTw4P1R1 +/5bqlcg+nNlgQ1Y+Bd9L2IYWjz0hLEnQZaWkH+4f7GTNEU2IfiSAimzfL45N4air +w7U9snKD88lqXtYpXD6FxVKKX18j6aeT2TAkd0OWoIjB5QT+72ou+ukrVLo6Lgrq +vgdSqVrlbNtORfWNQ0zt+8G5BuieoCFGwF1r+yGN4uKIaSpIZ6+hyrh2OyYOorPW +U5jQldBl1VeGEWUmAZSIpfncvjccEH2xbIvQytGSxz5EgtP4VnZ8tcof301XeWR+ +4pzRN3idRjpawLnCE4T0R5WYKc0yiE26eb1fAwqgdaYEoYz7sAwpuiJe47RKT5Rl +BEm7SKcxHyGT8pxW27ZjwldG0eZxe2lWjLTuGR3wb3yqV4iJFcfyhFz+oENCfZDU +PluzgcuGqqSZIZoJ/cExKofh//EU8VplDSiTPvomUo+u1YHZVtqzD25ewG16zizG +g5bJ+WQ9BKD/p8/25t/XwIBn4VRLCblpFCKjycpWFpTfmZzLh5InX+j3LqkB3d8d +5vfH3NDE3aToPIUF5W/r09liQaPwvSgROqOkQslQULu+8bQX3XJ4Nd5u2QIdULEq +Cqqdrz8q2042AwatUqAJDcKpiMmA6Qb9reiAU3SDaNtOEcnRLxHVvr7sx1mtoYEq +cQw3gGLqgV5trhBDB/bZ5AmOkFBYYx/O1Z/axt4qjmqMH+/WKAC7v+46yAP5H1h3 +9tr/YfDzanJHWo0PnYfpIqjJmprZXRiZ9hAYOUIi6wY2mko6f/dTkTP/+jFYmyLb +5QGBJtJ6no2rpQqDTcuZKHcsC7uv9kkC2U6a5Yz7YQrx5yyGKSJ5mGZmxJuVZi8u +0sPviuY4AW0ItKnAuZfdvXPtlQbL8Z912gA75gfOH8GbyP8TuoxfqeU9Md/gc3ic +G3TxqwOGyh0vQxO9+TfVPV/mXA4CX1ZsSWEEHadyyRDG+L1aZNKrYC1dGoK1BjaE +UrE6OQC+pwjBtJgRu7nxf1P75SCQktA+QL5BGXL+M/Fg3NWF+iAVWhcLc27FEjrO +057HmjlCrNgc8XtGRphp0PQ75Sv2q43nq5BYGCiwUQbwhpvpdR55/rZsZjfS5CME +v+/o0nHWKw9HTj0+kmUzNOORk06RMoeCRc0pG2YuF3kHusQSKq0lCri8huRFT9TU +XJ8itMLHX+mx/9t+qBMR5u2puH6NjsjsItuI7lEp4OVerTS0LEaWk0samAtceTnD +V7WeY6mkiPj1qcTsDj3NBz9t6GdI4rjwZlphBJWoP1WpABwdLHLvLTXacX8dF2oc ++Tw6ZPZF99NFF7kQJFsVKW5Qrd1FKR1N15QVGUkkGAkieD9BOYO78eVnEI7GmHLw +qVanXaIfmovukCKXtz2/0rQKacCMnHcxdZNPq6sEDnK61JWV2VhTF2RTSFD17JC2 +pctrIgYEpjtC5FoXBAl2WFIu4L1jwODk6kzL4a9XPSRvKH/R7Ae/fMcXyrjeDm30 +GfiXdI7iqN72h5oa66qTzlORtSvLyH5IErUK4rad8EV4vidMkyVfuTQwR50LgkGH +fo/LfOkxr5gKtPVaZqOV8pJUTG/GRnpq+3qAM1jW2XLsp3d0SgEVhHWpo8y80DPj +5YUGMZogMY/nDHP+OGfNcGSNbgoGGsiiI2DiSQRLj4tYIIdS9vDgLBkI2mPzTF8p +a6k2/T6dLrZehYXqyGNpik44k8NMvq9/6OrPFG39+/fI/TacyCiejq6N4RAj1fjR +Cv/YBNU0+IN2kttC1DQGXpOEzdAgM35TrLslmVW1cnfPuYmzMe5QlE9WcWDz661x +OLYxqCJQ4WsCyduRNDib8X6Xh3wyKShYY109tLUbK1lKARBye07JD9jtW6ZHSMT4 +k/fPkTSIvhCE8N/txRmUhMx/OiZgRXsu37uT3UjN1SFjP+6AJMuj7Cx1fHFhk/hD +KdZdYfAurEWIDUnSeWA51/FjHYrJPMElhS9YKjMyHIs0WqmbqVsQIlyR9sOsy7KL +vgScuUV0qSfsjPXvNZsSY/oe1j3FpD8rAm4pmnP4EB46mBXL2lpSN3cQD9JKfQZ4 +fTFKBpaWHzQpk9yaRpcVgmPcSniccnw4AYR+mDt9VDoQ2KGR/Gd8q+ZYn4DhKFi8 +bqY9RkvIG27gW/74dmtuPyqTkabfOt4xrgOy+yFSK49ReVkb7der66+6GreXgvTp +f0Ms6AXOhr2FaymrvkTK5YNdeuTOOqmm/afuq7D2+5305LMC9i8uhhHayczvbmk5 +FP1bLRKuWGN+RLfu4vfDY9ZXxyInQge3QKDTlVScD90oc+CS/h5rMfHT8PpC0NnH +7CbcT2Ik5XqLLyakfiGDU9WQr3JGZ2klFA3XPGi5UxqV4dO99U/MQ5+P8K1P3HiY +3Kj5uf5gq6UR6+Pb/IOYJ/bk2x1MCj/CdCQK2KUnVjgeFS6NpQMS4QXguQV7iTR5 +w0XRP5EBHbrQh7GAwu0rCn7qyABQqIGVymfSFx9zJ6tlN2r3m8M4sYGv6mRA9/JL +KGeTFA+TVUXPulXlw4MApI4FVydFVJIk7/ND5WY2xlx3sbQGJUKTJnQN9WmN7Gul +stU7PQM/PyKs3X+MywnDY77twCll6n0PdhMQirVUDCdH50Z4LibIwp6J3nq+tG1T +SpcJxJdK1EuKmeBempNwUO9hZQOR6ZJTXtQUe/x1/RaIkduIhLxjhYmeswRgGTsL +8qFWabaXzyDmsqVTOnX5jb9teRnNX7gdPIOzFk7hZbV6kvRXVkw6IJifrnxaD9wO +K0BlJXIa1UuH4UGayUXYbGOsFGdY8nu8TtuWPpf+LG6XntXK09ZDBORbcuNYE3M1 +/BHpZk5R268E0DPcDeGAxPM8hfZZqoJV5C+AbmngR8BlZ8ceropJR+rrco6qyEoH +U4DyeA7GKRNLbY9KZGqeBvYCvS8ymHA/zlKl+e1tG+BRC1actgCpeWBbKWNcLLGW +wXD/Ftkpjb9yGamLlHzy5Ng5XFkv9pe4fz6VuuP1YeHy2tQPXYcku7Eh2ZImNkTG +CXfaJ/7ttz654CNXTvL302w/Q7hSaKY+PofwQqc4Z7vabH5tov56W/XCUTNdTy0R +GI4EmjTw0JtfDMMWa0c8Sch0PIfgFap0FJSG9E1CAapPQXYmL96iEmtWFxtYOeBJ +bqgXLl54zMrIeFyXm84DVLe+RrVwI/ECinmEyukVJfGzYmllwfk2cWL5g7e1AWNZ +whK9g29uQwOOsEjvV0ooc6GSboHT9GIqU1wdOMWA2VBRpg/zhknTKpIGB08xZX3R +TS5NikBOi/VRiuG3EXidXIKr7NB4NPYKbzk6m5RKkprNvsOpy2jdgndMkY4haYSc +IyCT0bwa+UeOW2jb36awyOKD0TkYfBFoomOiLP6Ra3rrAqqNYkVDZx6S43gcg+Tl +xqGvSH2aq/uR0yi+XeFYibvz0iAmbOILZCiEvjhF8E23GGmaU0jR2wz3ECAV+HUy +FfMI8NgqmTiTIgDRlSG/jWtI/MLBvnDU3TS0AHL9DiFJ43N9oK3dUTUWW4vUAWRa +RaRLfTxdS1wCF4GgmsVXWtEZP52lxzI51viOt8r3O9akGPEo9DqfGwifDIRVxxmY +1KarqSQQ+KaHzqGj8ORFGMlNFzkMfuqb5dYdy1p/POOE/lTL60zbN/RbeWAAUJsx +cLjweXJcsK7qc0xFHa+SDuVyv6ZN+PnN019yZTlgc/bvjZiK8Gm8kJ9gDQs5J4rX +bF9FRo19DcIq3O/SQcGBePepssEHeC21UjgQ+EocC1SfOs/X0Rgq24tgUJZqTWfs +k0Zd2gg8ll9b7b0fAZPYRRksnwjqg501jloioeG7ykHA1od7UzR+N7OLzg3/B6pA +3URIwSBf3I5Zr2op7mi0aUAQtQlB/Jg9so4GFsPef3vHUzYhDjLabTSCLu7f+3SL +2xgHRruLhuExQ5dHDQ8j/8ChY73BMzVfe/eB8leRKdbSVkVFI6mPhUCJzoMsH4TH +KFEDOPIYC4wg9TyhjHIzhDRIbYowMny+UI57LlGpXc0nIplgAXls9pXjm9jy+602 +h2MCZ3PNDYxVEgdxrhRuC/38VN/NVpoUFcPAfdfPnZl+/38TzMXbziguZGuAstdU +8XqY5CB+KfDlM1wtpnhdzWT+o5KUHiKwZ7N+ZDkghqKaNA2F2OwsrtiR5+X/R+Nq +H/MOWlKxfGJ9cO480oAHNhnYwLxafAOhmGJXkTzTginORxx32vkv3isXJT5P+tcI +WDQdbTCMwVYs9/GLMHCd+SEJsP2SXmBBG7tqs72i4wVQ7ftL1EBHbsSSOBIfOQho +3ZhDl3VmCEzu2bB/d6CfiNiRj557w9sXaJ98UOZsNbb0S0HA4RbfejbH5+ufjZn5 +N/6c2nhqKZFK60+Tw/NtiE8RZdGCo2ZV/Qpvc64ZpmRs9G1FzgWVXbTRb4HOolu+ +XMedPYsz57B8qPt5QnKbzu7/mUC4QP2pmBjp6aShO+BTCuRioBnB4Ez8pgRqMrMJ +tohSgq2Z4QM5KigoepEPIkEVI8BVMjrb34+QgeSqq4gTOi3HZzT/6vAeFLhkAYZg +CQ4ErUC+rygYIhYgRHJjDm8mreV97YDLqTctZESgtYCJpd/qb0+NQapjsvXqoEia +wosBgHixhrI0A5+xt8a3gK2RDVshgSNjdZRCa1BCPImDpfqvXmPQMDqAXUQ0TIIw +r9wIqKEjvJhlkQJYcalTHu0REV4eRmPT5ToIXd+6GQowHfAAJ8m16iyIfBXd3BZ+ +0VOdyxYHk2UeD0IS8WRsOBQ7iDItBJLKayV7fALvi2C3LvsWdPrNwCzPYbYLXdXC +1DnQzjZekzMWdW309CaYCH5M0Y3ermRXB2lxrvhzspViqLoTwOfPe2k/u2lnYZaa +OeKiGOOqNLu7whES7U7WJyoiXQunS5/Qj/EZSinTYjRAlj1+HVPXIA4gb1/8VOww +9f8DgnVNKzOcO087WFhfV844Kjy/ZE3A4Tdy3Eta8EP3P1qdLXW6KyukcmvZtvpy +BlJgFcVfSc8tbP+cR3XSwPAIqAvmwx5KdFT/29UusdL7lW++uIkepCO2rrqFlqWF +QPnS1wec4Ziujkk/0vJZn8z4r8EctmcRoC+Us1Jq63ohvu57LBoZG41voFtIjnln +8pjdzaldAmc6b7RHxA48N+F1TP9yHA8s2us6Xcy44xskgvMOASvnbxsQIvCiKrtS +5F0h+STIse2BZT94a4OptADfEXWrPrjkUXJaV8I86AKyQMzOwRq65vnMS1eJ+Bkg +/edlZ/0VN06d4RZJUoipfZcljQLuwjKDSP8JxeLDDsc5ZjRHuh35rk8vOIJqYftf +Xj9gHDQ2lN8FEXV+1h76wW4ZUVAJHvcefA54loC/tISsps6bduzqazJqkLFjolVR +b4nOCtpJYMyo05OvrzdN5RYpsClClUZ+450CqBEyAOJzOe4HNHmta2k4jsi2tP8A +NnoDtOBzzcyk36C4OeQKvQP1FQ0WcZOYEzPQ8+5rfJ2hjKdebTFxHgrMCy3Xmd1C +wSiucuMdEVu4QVine8Q1Cu6p4nw/tpxFTWbj9xyT8pzcjK+glkDP+2++dhfJxRpO +7kWt2MgeJ/zTkAE+nBcTnsLchjzNi4jXETqr66AUnddb0lsl6MwNUiXdpM7qcFos +ntWBVDuBFmguRDwVgKtvNyfi/SY++6MyxGaBRrUm+DDLZbnvLoWpSJU/RoOkynFs +1DZkFT/tgsGRgeAdF2gZMZ/H9x7VLyR6EnAj+FuxU+crHz/m6lncqQskRItinUyz +MelRTQuSotPmpYEKUKTHAb+XlwEgtEQU7YrZjZnq1bUDSNf7NV0GrhHJ8wmSoE5a +DUGWaJwsJwKU51eu+CjF36emtTR7V0vax82uOfIbvdFgplCJziP/hiH0/Pfy1wI5 +6WSHKam43UZfGfbEWzstai/fmD9mlecVfLOkO8I/OKO2LfTvA0bH9yIST/yjKDwu +YKXLOCGjFt1cWznqXEY+dg0ek0xtpXELvWJvoFKKAlK2dhM6TL/ciwpmswD/4mmf +1SoEyRlWDQ0poT54K2/7448jESgKEs6qN0YvIkxrkylRpUIl0tcqpxLGio94ZI9j +1BYT0ImG9cpxgREhyfZL4Jcg/YwbnKSm8OL62P5MuS5BCssSjJ2U5kj/s3XAWcPy +0mgAujs0liNA5eeWmRQHmfgTNFuTPWSKb0hjQ9Odq9sPd9QA9whafuDEIadcz5XO +/wD8SVe4Li/vnKo3np/fFunzqAtlrVwLOLEyYrWUMLYsYO0hlT1qMAq5bVBoj5yc +yI4ksxrWdXTfv36NOpgB1p7F2uxO9joHeIDBmyNyoqirw4hjGV0a2g6oPJUyK6yA +y+zwKIZTQL2TvKqXFEaNlqL8ZHynGZSLc4qhFsgR9Z1+qMrjprm1C8h1iYfPfAQ7 +jynC4wF16G8EuR93pBN9Dsw869skD2Z12gP1YZuEG8jdpd+X//XTTA3ypPeyzuyD +1M0AvhUDPY6ItR0wrb4TpfNHzcnRCfbLXExnHujgl4a21L55LaWqjYWRVWq+MTgU +9/CGCsCMJMBABRoL6ZQw2Wen5NdufXHD1YSOPTgac+UsGXJlPwBIv1E6EnodwpQg +NXK6pBlOt22zE0UHHvHS+8TTrvZKgE50obL0jXgpAA5IqjaoRGCN27xsCuQfRSU3 +FkliJn683ppQfUm3Gip26HSgzsEgzaaU7fTaZwPJt9ppgSK4Yet1azDbH2VBY1bk +X0E7O0XyHSaIjCA7KgMGcIMuAE09bBiQXz6ZELKt+P7/awrmPOCbXyCGwaUzbauZ +rsFn37U4rc8WNU1zNU7d97Z5uWH5cgE/QKiMIeVFP9QHryCPfq9CMHQoCy7SsrLz +VFuaQQxOdMow7+NEI9IxSqLofV47CCHZJL9SFP9WROnjA3JbKk2lrfAg8mCdIlUP +iP8/KS938hzZ4u1RLrRIFeGhcUXO7fEUqP6Kjz8rcpJIqg60wK24X+xWmrGgAg42 +n8ywSzlVgqTD5FbpcOCzG5V2H5ovuHZ8SLLh1z8TBqiIj6U7KTtkPJRvmOD0tQKg +nGaDQY+BIG8EBEOW3y7B8LsAwmVDjchIGs1jIl6E++DugM8b8VMTZC+njj91fncr +gqcjnhGDVryJCdxENUWuDsF04OgTILM91/6bhF0UP42gqu2fZ2iBUZp5k7dDoTtI +N3+ecb+5Munvc07YaYse3rcgfalwwcqq8o6yt9Om+pFFsH3P84tjjrKTupXbzeEv +4AfhHCZH1e0JCAe98ADAh3OMo1b+QD1/N9/Gsdw6Z4sNJSO0zeWLLvnMIbN9TFoz +VaJirzp1kHJyeimwVmvjsGwPSoF1Wrh1IXX07fPx0wjDMIF4Qj8PtatV9u4aJXEH +Xqt+9qhYbLgscuR9V/9s4OPrLhaaj7OaFqYb1nJtD7mWSRf6CBM2eZmREdiKaR8V +1Vtf9FOCVx8itBjxyrE7+FLbez/xbwDVythWNvqkm32kmT5y0vfTCaL/oJaos1fi +T+aIAm3PcHF+mz9Yob7bRHYKVvDLjn0XRZb9foS2wbnbnUWHAAym5V1a5UlCmkQu +8CcAPzL/jlyyGrF5QzEDoUmLIVvYKHH0/ZzYP7HPlmzh+6NCWsllwMtbrA9W0re0 +VnMOrLDi0JRjxgopCJR9zxG9KLze2w2rPdVFPRX2wibFbBapGW0U9TmL53HzsczB +70WKN3I15lQ6fv8TuC5r3gWErstWzbl8L5GYrKm/8gol1XV/KPJWG5Ykqwqv+CgT +qTPdjdDhiYFYaQs7IN+MlIqWwWj12oziOdLmhHJB3C8JZpnq3hIpehSFAdbq8nDe +YUOfv7M1N7VXEDktlXY9O8l4Hvfc8yxu4z+QLRAdgu04dmYmgpNx2P0su+bArARb +Pf4fJWLCJYM8T3xpZthDm/rSltu+aJr6W1K6ZWuQXeHO001cPpjQ61EpGS8OdDUA +TEUNwyUVhKF6BERFANZEY0DuEY3HUure5ZfVotWm9hAFfZBQRrROFMdtC2lbem4N +17dg+yUY4k/HJsZtVaicLYdCkrt/lamdhYfRVE0mE7tigsUwERNe1YmB0dH0R7rP +H08fIogVjq0pKY/AE2VYIs68Qu9+HrpxGVcuTauHyjiIuuEbyRfgtqvCTte9uvnC +8kro0wzKL/BF4ZZlU0BaV07GD04BbxhmDP7tOWTkUumzlalUNPSjXVHgAGgDF+bQ +PpELyVv3XHBDhrayiJkgIsweGdk+y87ddepGUW2znTVN0ZjQ5KPhk3lK687d9UwE +2QQxP63UTvwphTYmi0nx9UgU0R/UrNgwvdANNnjXyjnEBNk8dl6oUtcM+CANTI+q +sKeSuj6fy/kyWooA6OEW8l9FLeceNUVLjuMPfuralwCA4e/zCqQ0HJD8awcY+JTE +Ke0X+vtHitnucVthoNz/J2bnBWPYjofhIpAanr/lqkXIUboB9lHZCdYKxVFC/e9x +OYKyE4HMMw+O9YyGadbisbHglbZDe6sN/x95qDRHoZumJPf34GptaG1rWNDh2x2x +8h25M33tgNSJJk/L6372tPh82kESENx+4tt65xblw+74K2FSbQp1aQ9eXzW/iI0C +vmiCTMCO9xwEsPMOPvXfqDd2gbE6q5Pxb01X6/FWtvNWJMEZ5S6qbu1UL1mEbeEp +NzNxjLSY+EJ0B0VBVygh4HotfeYkxz8mgjJAW7pods/Bm57HYRIWSIH8axAYNTqX +J0LGkI4uTpGwp+gPpuyomVevHOmJX7gP86z8Xm5F2mD8Xku8xtKD6l1nfnnfyR6B +Cmmd9aNkzN9AJEB0m+9p/valxv4qz/6eniVvfYUBXEl+lXyq06avBJkSWYUDwjUG +0W6bd501O/5R1s6CEHeIDiKsb76poKMMg2ghbL1Y0aF0qADsalATH9XWP0BoHEqt +pW6cOxqG10C8uKqShiNDpoP8LrR/SF0+ucxlk2WR+Wz+8KbBuWBrJb+X1zCoZg8E +w/fcjCTJX42TYB+bJttTKf51gq/m3quKBFONbk/mhsZtL3Dj4iU+K9nJOWtCCJbr +0krpB/opv/HZo9uz4tUXRbhAXDGy+29tKS31UibuIJzNkrZtRGJKjYZCFrjB7LUN +yMsB5l8pyk0fjLMTyl9eVTqUpeT87Q7NcMkdQdq8foUOxui8u5DLfEvhl/X4Aaa1 +jbNtK0xW3VZzYBGajWBTvRaLfnDywTE1JZD+PnZraks5Kh0wWu5zQLvHB2VUuIP8 +f4XrpbCQd+Lkqz7XCzBVnxIwB9hEeguxiNLpYzjdVTRPImFSsaj+V8AjfrcoIYV7 +/xU0p9FPSxakBkWgQW3hkSRd39/sllU/KD0TSA+4Zs3gwHgw1Hq5N3a6Qg/9IKpW +qmLqUFzCjehN9zynmI9ylI+PGh5gKS1Su2ALipYJmpVBQGPXXeq3nCUYHdctC0be +uSmH3adcaqGUDtcOMBePOqn0Nv+MecB5NkVWhiphpS4iIQCV4rF8dGnUJcnyteGq +UzFpyOaU8LZP5SgStlfzYx0PvbapWM2Fa4Kss9kHh9fmkFwCs2fBJLWGLzSoIiR0 +JDifzLNJCSVb0+xoedm9duHZPZISS69dcV1SpUXDy8XXfGHBxoVcjqBhivQ0cJwW +VSPjv21gR3Mh/H4q5WaOw/csCQp6rd+sCpkjmAYZ9RUxDtZxwIaYdAgq1OzfkMOm +/kIXiePZY7naeTklunin/uO7ayAie1VehDL3RQNXGVoyk88sopp/w7lMGPUkft/d +6ZyHl0HXQe315mH0xkc2+RV7Ii0PIk7+CsHOchEpG644IorR8Lwq/w4D1q/4FtKo +Q97L3bU/tVc15gYDgwbRKQhBflH5eCdZxQiAw/OokJmPgo9rpazqHK9L8EFZVB4m +13Zwfe3q/6dVXAS9XPtWxpcSfmyctEJjh5kAitRrWIoxjP0mM/OpGJ7mcYvf0s7t +bIaKl2uqgDTetRphQUbWcQIbjxfyElFypZo9LGEySH8Px/BYGLtypdRucb8cwKna +nR67cLxu0qoaaDh3YhPs5pkz8s7gx6FG0xxItOMRZKBW8hxYRp+qDmEfGROna0v/ +ZHfJRbETObowZqJse8eL9l25rNBo4aXJIgcwmuOouMGnMKn77aAcVVhJrw3eM1tN +9q8juAX/2gT8CTquTxe4Ulm+Q52n0EepSJnF1+8usHdZjNs61n7PpqGqh7IX7nwP +o4ymp5uDDbsIx0VQ/BRp075vu3LQ7jNix9SHSjqReU6XG+nhSHW4v4jY936ZcqGN +JN9SP/91whCmI1pj81k51KngnN0ur9KV9hwWOOHeUWv0sgBH9i8fDT1mqqCbFeC/ +xVn+qcLk+MUI8uaVIu9d87+vn7DjbH/JIlnvwxG5tXwW9SYH26EGYEl/+pwEcRaE +pCvhRO91vTxq+dD5FwA9z7vp8TyBzKPVZ18H2VICHh2E3fMazE9g+EP+rM408ZVo +6kocbLuM9IexyMeuk8Pq4hR3HfhRGeMcZfA0EAZawUu/OE8yrNdBPlG3MrH1O1w/ +jFvySf+p3K+1xcAVB+NTJYAFZqO6Bjc5ldZkjAf25m02hCHG0HuiSkth7k3tGlzL +P0gCow4IGvowXTilv1SFzMuiSJYIANo+8HW+1zMhtCWKS3alfzMKLeUZc+75iXkU +/w/bXa/iuFEMGnmnKLG4ewi8li2MX1pK2QZrNcD09oYQlwZKVkPlHBcxBM/5naPN +yohXIYKWEP1mnIa9k5Tgq2ePNrbSibrakbrdwrKOFilTNLZdYv1txf4azML1SVbo +6siDXw6XFF0MZdeIA+Fe1QB/4D1Ppr7lcoVEkNeBUFLEk7GjLW75vmdjOXf8Qh82 +8utaznJQmkHMIyS/hCUGXMSUebB9F6dm2H9juPvTCVdAVnOn7EV0wNDgNPJlz6jA +2uxBCxXVduGlQCqeVHqi7SktoMOW/hChbZrXKtMRL8ej0aN9g/XtzZbRRUtPUfMG +3FDaxkbAkkxltk2tryW+tLMRO6HUKLNkBWJX2rC89+H6lItXTICfSBrz5R+UIygl +QK4GXF9Jd2+x8wQIhqHUlxiTumVRWjvgwJKNfQLBzRxD539HKRb48nfDozlvFBA2 +HesU0RdzsGlKitOiXfbWQs2fAOHvW80YptHGBd7jii2LZeS2S3J4eYaEK1pgCBNm +s+jtFT5W/DVmX4B8ihspTb+gnS2cdAbRh5uzd6vICiw8kUYlTVMAsFsPVi4pq15n +6eKrgz4WxDET1jB2pObHUVUDjKUhHMf4jSX5NwqyELzodMkKCStXxTa7Nyuo2g3a +iTJxcn4sTU0VGPH1kgsS/Nf74re3DwXhQLb5S+Ecw8W9a/dlUpEc3IpuKmRKNIK3 +0xPoLG8kEfiFuTYtQNIDGrjAzaxHP4Ie+JQqs707pjgsejqKJehwRD2K+AsDqPFR +F+60F5dMb0diRv4zowGRcTJbfMCYeLYfgetNBd7BSCeu2jv11yP+CozR+vZztpnJ +/IAO0TvDUdGZMY4neBKT5cbYsQy6FQF9w9TrbrYHwc74+y/YdFJD0CwbYs1nPuon +IfEZFxR4KiNL0ZOu0t3Mtz9gMbrR15RxrRsROyYArN1zWgcZFcuyIGsT9fvHCON8 +nAQsN3rkYTks++LF9BJGJTmASrK5amwTT4f5TK+qlm8KDdRs5EtW5AbDyjya2Akm +GxM5A94lVtxIydPrRD4/NWbFVCT+lT1JpCAUT+XNeQ3WBeYCB1yDR3ym3YbmM+E3 +zJphn7yKz4CpnM3ihtvEPP7c5ww4jHsoaF9QqiKtv//qjnGGh5hNNDxVocCIVCIK +yEkasHtaQKqt7SQzicy/xBRP0bTdbApzszJndiXibimcNxcoz2dYmjMoJ936ZqVk +q+m1MO/1aD4ExkOTBfj6o1W9XRFfusyWApk5CVUQymyNe9mDPR15yBkWXWtw1Bhf +ehthbMrGjhy7ExxCqlHob4nbQsrQVUeW8Wj4nyCWK9Q7KqaVltLJOpngoZjY8KNc +HP+jOEnLe3vgjpxWjLc/483AQM0Q0xBrJ3kewfMuphqr9auQYvPzBKgvyIbfQoq4 +8uYCJjmFWGkVjgkCpawz4N3qCtwZkNkD+Go1A8JeBRI6xdx1vPDyBGrzHpOFAaIV +PPHJJ0yeVWL5jX2MeKjzWsdXQ9bmGsFfo2RcW2LYdyt0GRVcbxjOBzqMCNW1SPNY +HUOUJohOZndpdI80yLWb+oQI/iFz/W904eIfq67QwmP9sAPXFxHAVos8YEw85icT +1u00IqgkOKXu86w/ECUrUq6gWs1kshuIw+qmtPVjnX2tSveeSSRKVJXoJE+UpQki +Z+lQekk97iIxFprmOjauZrCBNv6EckjBaqFtXnw143ddstPkfGNf5dX6zkT0t86y +N2q2M7qB7T1vfaypGtTuBMS6Wi95L55NPSeVIP4PYBg0nBL1cYZNYfG0uEIB36Jh +WiicbTK2e1WvYo0ScwfsbOj9uDj4r1JqNBsK4HtfEO4ILnYu9OYkHg9vjKp/KQlI +1ICm16LUxvGPbhU9xFTKJO5Y3vlnMeK28o26ZatUdmYm5KtIkYrXbc9/3RXHCqya +K5aodfDSJIZN/8Ptwvvt0FGeAy97MZvKHgixYCXZ/+l3szVbSbu9DrKTdl3fUQtR +ATcLIUgPydpa61xGAnq0mk8gbnEV3RKgwnl/HjUEDUNKQm80KHk18lG9ah9fNRoW +lK33SfhQE8pxAfudx4JSkbpX1h0rED6NR2jNjitU4o9pmBNt4pe0B6B5BE3eR7b6 +0X4gfY+OLbsOBLWNIrtDznJuGlT3GZp3/3P5bS3s5B/pGJ9ki+9dyLfhBKW8HL/o +HHb4ZLTSHEc5dko5VYIj+JJxFzrsQz1VNK5sHqna5OYGiz9eyhzQey0r3HFX1fgM +OygcGxsJn2Zq96EukHD0RFGA0Ng/BI+Wnb6TvBKX9GzpmVDq1wsDe4AAtKypcU4z +1LzLJt7oDoxFWK4Eg3APYhbj8D1PgZzdlGvcZO4sOzzOjd/itfjr+IbTvk4xlKvk +9s88pEzjfe7ckYhiuT6qKRRqzb3CGG6Rlx2T49XvojcJOWgSHglo2boSMpVQWyUc +iM8E/ZAHCdJVqlaiP5dsigXXQkyCPFwH7FMcWKFl+R50bOVCYWFg+NlDBDLAG8Xg +F5fJfFPSp3XcDkMpg/7+bpO6kXVusqPcq/vffIIT63+73M/hFsTICTr1fHFcfS/2 +OscQevoL3Bg9dwmMFnRkerVyX/voFbw9nykKJ/XZvY12hhBH8WBV11hp6ve6Tx+m +at0PQ66JHNkuFGPZIJJfrzoyA9fiid0SleA35wlbB+ZJDIQJWmFUH7e3+FgVl/y4 +hCpRQhJ6feZkZQIgUynKLjSLdya/lI6rpxA/Szvit6Gl6WP81Y4bE4DRxwrh1iH0 +Bc32ge8Nunp1GKTgeIh25pQi8Yr31/d0Wx7TdY6LnMv9wF2AM/FVgesURFiYN07r +NiP2b9vz3oPRB1laj7IUDb3rjDVtur43pl9uIGKpjC9wYCVz90SBwLyRcLcdDWiH +gM4llSQLCQOgo11MAxNhVpQWMTIDGHCUBTSsNZAL3QWmnRhZzfgMpom1qQ5rc1a/ +Y5t3w9gfTI6hs/CHugZknU3qCVItY8fLmEpXkcnQx7junbvAowhUkucR9dRMMvGF +832HjYVbYOV8c2WRfZ1SkWabno7lG3OOtrnB6razALgtlqvc4d9NvRn5K3LtHg33 +FceWBCmqS40M4YF+EWBM0DSvhI+d9J+Bhid2d2aGMhFBKbV2dequF0mtSJNp5ZOW +Cn/m3zGZ7xyysP+212EIjcGth5ALPIez8L0d4MIhWk6htCNJy4zJs/aGekBgKpaK +FFoVVAAxmHN7qnHdbxF8XvCiUYlLlA/wG4iPk4n+/y7elIcGKVmg4kbsmfq48jK3 +5s+IxW6BMGkruBXHXNbz1qOhjw2y4PaML3WxR6kKDx4z3nAdG4xvPCrHYGhKqJDl +AD66YhzdwG4WV4WidtacbYxVhK4TN1wWFibBhgAG+TneI8hhZ01CgYkTnitwHUA7 +0uHO3DbvvluFGHvvrG9AKpp7JbNVt4ZJEShJEHrlioB7im18bZ97Mx8yQJfWsZje +1qbm1Kl3CbyhAdMQij/N+jOScQ/1Fqm+TslItbptrARoXNBMwo9pheVEU9rTpCG4 +B129lg3sxWGPs+OwuLKjyDmj1bpEZAUeXxqlxFvz6nPwPN1rfvWK/iCs/wJAw0jy +to6Qsig5Nj0q7TYa+wWqloe4NrIgQsT6RMOn1yfTXc7CWX/G2jAkmcTaK1Kfxpmm +dBybm6gwfzaPzqBful8kYd9u2XQm90nMtWIH2pcKFpwNeVs8Ai+SSbB1oOXldiJA +lpl9PQAnV94T1cECg3FhrstTtx/AyAi0uMa6PZv6MgagQfMFV8mg1RR0v6eCBR4e +Di32C7ZYIFaRFXcBpZNhqIAvC3nvfhuCMNwFyptE/QXAm3vNFjVQZcRPj14XaFiK +wzFxp1Rmcg+HjCSiVq4JWMQZVMba6UqTzaofinu2kRk29uw0d23rkkF8YBeSahOb +KYQnGi78J5fe78ihJVSRuXBIGLiXRMJ1DUjIoiX97YYUcS/kBkmVdKpgIpjEsrVE +M3htmIm4T5keAMCXnk5UDSArvMJjhXuLmkcCyGWhsDxhQG6Swxz577NSRoKT0PAr +FcSrrjnu9CTKZdtaC/7FCmyxGb1V8P9HKb2sKsNElPBi7RHOok2FD6qKcsj+eAFD +gg+tFLsmzua1YS1AGa9Gyxk+4x0FMhsHAvNi4zNAsQUf/z+ZQ0Q0Oc3Af8xUa3lk +CU5ULW4905AuIK0HVXWLcogYxe0jIIXmJ2npEou8KamlmkyCQDKu2iRdAFuWSwUl +uMOAxBYTbN6E/7l3IXInWqFeBQi4CAXEn7Xts20wXpJbiSEYnFz2etdhcf4tPrSU +7dsbWLKkYGMgPbCSzgRf2BFqsyypVOMzMEv96bNy6/iTdF3IRN2qCLLMTBvATU5u +WZV2NJAHPmD1vUtM83dPMXJJy3vljbkVwgXk4iA5Q1Nblf/cAEkQ77TUD1ZZEUbY +cf5F23HicHqERr5rtCHVhfHhXGSqr2WvpJCHw9iJ+3vtpdoybC35gERXe1L0bJYf +JI5bgtv+FAgaoOq7V6lfy67gw7gKcAR8oD4MXWFd279KarbA22b0LuKgu6zPwwGJ +7137RKLXSCYVqBHbqlvLg4oFaDbM3hy/TF4r0wZfniavw1fHEm5YpnSCzE/WVMDg +ilbthvc5WhVvQLdh4z19iBt2U4RtFLVtxYrnczoYzKDqqXhaRrSbNL2BjCObtg7s +JKDztgrjiDafLWk5cX3JxO4q1v1CZtfh7qylMhnugoRsQvtLs+bnuEfjSQs70kpB +NLNfstijHwKKIbRbPXl0uYqvzbXGZWgPulgW0PtO+Nd5YxlfGhmbAdycENMl65bq +lJtYcziW3wcliGBszWRcAVfctnFMKsnoxPV6MQLG3cj6ysbMpO0jpPjtBMvxmC1L +3/FUAuN8x9KDPCsG2r8v4xlgSKtmUzEk78HkTvRGRG6fl/xjTgEWI+dgupntqFKP +1oC+brwPc8/Zm1qZSFRVN9d4JyA3a7pVP5B/Yc7cqQJG5ERLjzucT/aO1FFTzchH +zMUCa94N/z7cS7fPZuFrIhUejerSXG3Fy/BMcoQzykDxpJyhODrsRj+XVmjzc9sh +TQn7gCGNsltyLJqMe2z38HWx6dPb7A1SMH0JRb8vUmN+IGEp7fxPHLtUQXRmzvaI +Sx6zKw7cs/+Sd9mM/bRs2pCwmwBPDCRsVpYshV+8rGf/EbtFw8suTrA+Bz2yMnmw +2OAs0+yA49Ekn/UzGv89rA6J8FzUctCK2S3L33Xg49KJE3PBtJCfYr7F0HMSq5nH +G3hjItqHyGIOijDIcBbUn3vaCqbgUKLLS7BUr4UGTZRMzik5EVXYfgZv3FTkMKzR +xRhQ36DXmLgQC+s1S+SDAJu2BrCKV5F+WLsJin+8rk14Ly2wUu97FSqTIsI+oC6l +XHASiXqCldWacuAL7hJJpDF4fpo4BJ0VBjMn8jJfca5NDgbk9VyDe/Bu9P5OSFtk +aDfHAYjcTff5HZ1/PxgG0lZgFBPLdL3vX6bRGIqFQf321u8SjAHRlSKcHXU1ROia +koNgEoJdWVOssOEe0moT4s8tU3Au+EslVVujOc6Nu8eczx1MPQglT+TAaH8Qji8+ +FBVJ5rNMk2j5fCtIfcc4XYWKukVvIjuRQvH05nLECvsldwseFap8pxo3RrAJsJtd +nkfWt1aFJeCzckg3XJyI1eQy7zO2WQ0LtIkcilKCv8g2AeDN3U65Sl8OdSl//J5q +tPqUxjjZQ53XXkcn4eCTfdMamnyTj0t8KZtCObt1CCxrFjpE6RxMzE2d2opeoZxx +mBFeWkIDwRW6JmZiZCWFqcvzQjpSO3oJbZtfPLoNENXOk+2a9hDpQC9vkGH2oaXN +CZPytbEPd2RDv2Qr+zuAJqA7I4l0gpsajo6D/qsty/vHGDbF4KyxTAxaLcMLeASD +2sd1NdjOHHpyDrKMuh/zpVjuvHlY6uCwKcBmoBAvxu5EwVCtdUebdL4RMWI5FttM +9ePQMQGCD9ohC0c6SrBVjq35PvxLqr5P8xKqWZF2cLBsbQ0ppOvmVFDqJUmRmAUJ +BjN90H+E3TUt0wj0uZNdhoa1Elj/sbjAeDHiI9jv6LiYKRhW3lKGfMN3uW/7hSyr +JBJ1U6oK7i8e3Pf4Pff/IqncpVTcT68SW5k78y+r2qPcA7DNdPTrFaRSsKyNjKfx +OKq18iAJ4l7+QwlleZ9Zz2i7JCxZAxySWEd0JNmAhcoXatFsBzi8GvmfDg41A93V +0d5AoLFfhuYLaX0pw6oKmm7ouEivb1dcrk+kvHu3MlH0dcXkTUCU6jMhKxy4F7qu +ox+Xf+gnXsxi5T4/tTbqUdN+itHVZjP+2Dw+Hl/4Gtoa/i6ywRmHMtTxsZGnx1aN +6yPMy1LFaEySADrbb9zkC86JBuDZIR4QlTN6bVXX9xSvbCmBaN2uA2iK2hL5OSXD +Lavl5iGj+Ux/xF7OtJ+kMJX1HpCS8hq3P8YN6l5NpnTFg1ztGa++k4A8VyFdDJOe +jEnCzH57FKkpl+H0l6mvbrj2S0pANOEp4VN/CRCFM24Aa7Vbh3NynWntthHfA16X +7XweTg2ZA+RHg3eCFuV/TfqVt3Zpxtk+wL9+lL9caDAUZ8zz1T5+DPl4gMyRy74F +PJ6kNLLYMggZkx1ae+9irxieC/3ZBjqHGvOHVYhA0fERmIWR/zQEG8OcPpO2/c7R +DpggCnhw56FPqPikzU/KLVngw6dX3qHfgAYUVrWC3S6m8JULhAGCqSceB+TYLuI7 +lFnKN/puyiNJoNmPjtaVH3NGUubgHoxfZyuDwgXdVrdVz+ML7ziffLXoIm+ngQtF +AIMyCPWyYcaxNwUsWX9Q1Jj1wzVGcSTSZ1xEP2SNrDJnYIIy8FIOqpHYnEdRw0T2 +1JjkXOjyar4B76aFmURQupjUFEe19smkMYP/KLoxtHY5f2PL1yWEFqrhXDVhO4Ay +rxw0GRFvRi46W6hdAs1sZadK7eWXIwyeiWdBThTBxpyA0aLV9+RR19z4hRBT6iiJ +AtNibf5K22mYxW4gw6uh3MVET2lY+ZLgN4RYM0xg6RuD4SaL0v8BQ4c1A+z56RnB +xjrU2dF2/Lzk4X23jIhzx+X5erivIJz2Ks8rl3Ine+397KuiOQpmzsvAtoIPjXkU +w6ACqmOgLudHDsWDAO+8+ImUJZXu+yIElLvXMB+YRatsq9VcxttfHs3S/ANklGPz +WU5jOQuMKjn3kVR/vUVmpuK7OfRWqzDnm6xbx9fGxCZ6RpUWI9wKDYttLQytvEpw +wQC+O6oc0E5aRnVHNKSTGNjYVJ1hF8sxrzaakv0ALrawqLU74PQRN1Ntohz7DLig +LhNRknNp9b/hUupXFEovdnZRTWVKMYxKrgE2p3+wnoWqvlLRVYaFKu8UJ9tuB9sw +wgyP5XHAggvHZXu6iCOlh/ZT1WU3JnyD/Sv4FM9DDM9xxhTNNBm/ncY0s5PFPA6H +XXvKXav2Sh+AwoB9cbqw0wSbxAPTop1NjmQDiwC5TMVy/PdZHVVHqQ/04QWuxKAz +b5CzVvnmfHT9kpy1YS6wjEc9yQR6uPR24n+s0wVBf/Vz0pbag5UV7kA/AergZjA6 +W48mh/FKt/l1p1k94V8hqIdjn1bc+3dCHioQuYcZMgGfaIUuKCR4yypA7DsErXe7 +t305LfmFXR8FzsbqCgtaurXaiO6soBiPOIjldUYLewGl8AsSND5tAgB0TuCTFZ7h +dtpsbcDQXdzYMuY2VESh4PucV2fTHA5QnEqBdQUP65xiS7JYYbPgw2v6kx7Akc+z +KCCDAmSKwfftjN6Oqv6v6S5znN39a0Hx+TNOAuh4LMRU8br7eefEwjjhPCnrhH6N +fMk0gmpoB0pSeNnHfecDRuTksHOlbMQ53kSglD5FEHcEEvHqREmbSGqhw/557uQ5 +RTl2uSbpFy8MuM1WIyBU1HrKRKtstF3w9EnHxDG2OJF1wPW8TK2VL6YKTsIR67Nc +tcWaKtXExT8kaz0/hI8Spb64jvTTzBoD6HXSlfYRosjHQHVrhgB61cckjcxnSoHY +JveE1Yfo0xBBvptzGKoA2HMFl7g9gvPcD6QFCGF5wzZhtnFmcWFN/Xx1SOhMIBmi +zt9qEeDLhkIxr7HkITd79aRxJK97idV1LCNrmjWE9peU3mo2k1qH80RTUGkLO5Sr +RdEF1Ch+oeI+rTr5w5JcxHcb8Qv1b2renPS8TrZHO0LBz7O1zHSp+3rLOWbxfNso +PoEbz0ZBcB1kQnK7P+fe1YvODvK+huCg/wMDcmUSuBfPRj0WIoTIXA5lNnbRLlHG +A5LRPhckM/gQejBS6CrxJQ1aI5AMMMs717DsnyaKuaZr1CVzQfd+6OdjyLDb6+UO +MO7ftGdu6WNvCr4zeIO+WzOevQZ/+zGjidvSb10xS0018reAGRz2ksAIUq5gSoBH +oIkMtjnZbFqqvL9qKUFG8qNU7uv+nMVxHrlMpnUVg614iY1lvRg8K12gm+wfj+iA +I/9kulPCj+vkE/4krY2iYrETu0NykzZjMG6sMD+MmMygOl04tbeUpY2j0CEs8fNE +/kBkaqg9JDP6Mz/31KkZA2wGSb85bs57X5P/c71XsGNwBqn4ugeJxG2jPOGx2GFF +XAjbeQm+b7uruDCI9lJ2WIS9xNPne9KJvCGKaQvrT+SliNgVin3Spiof85giOrlX +xCzKUMFOJMLY337SWarGZb/ACqukfTkOLOC5RpSisq9o1JRj9Tp+mpT+I2NydqrX +UZxWyC53psKOXZNlKiJ17HQqGGWuJbDUQN6cscpUOo/IGXdvg4qdIoeZgxaRTedj +6t00udSF5BTh+H4LdU7lND/fSrP/jmF+7XPQFm6pHH5T+QOTzl6aQLFJ3t8+nGb5 +hfeNi06p1EVbirxL8qVprGUPEI122TcnDIa3pKpSYoLsisF6EYjXGxA7N1A+V23A +2wFTzHSakTTkyDmILmc0PKWi9NG+lOXdQ5i9g+NXYqwelOUqICf4BbaLq2IaNxXU +x2gbQC85uPXB8zfxLp8RunSObR35/R5BnC249zVlyXwJZBszlhmJkHagadgbzqht +NOfINca41KgnoTDzjeAtkovIlaxwedijPdTj0yEzDQ+cucVXm86yfV+/esXpoMHn +PvEtumivic5ZFsp01wC/4ap2w5/8WIhfaHhsednsexzHMjeSSVgyPAA7mSBtHN0j +iGFWBBoHAIEFzszT1NOoBheKmv7179Xb7usTiUUhJiDrNzlWxLyJdx5AtxwzZzsw +hY6a6UHpmhsEy0eCWx0LzgZHMNHFuf8Uh3SNBQZWcwDrk78KPQyNTMLmUmvArUu0 +GzRisAGxNnDAgQ5N/8iWQwiYF0uA5TBuPABq6gZNBkwWGqYoE+Z8lQUZlKA1a5xZ +emaKzlna7bzDU5iD+jup9ZIT45mIyrqVrHTLnEx2el7NC//VA/kt/3GMWU/SA/ks +NjCAJQvmLtn052CB+//ROS2zRX9q7HF6nToAQbsOvbprsvp8onpia9djY+GYdSSQ ++ohdd8KAduEeYy3PLBlrHptEsmP+kZO1AWhX6JeikCsXiGL6QqH9AlkhuRJEg0Xp +IArCBu8K6NpAT/fM9c5FzRZ9cMmju4nraK3ikcMnW/cm4xgQxS9eLMJMRmHeNNoh +8cx6/lyDOci2BuXeERdxSsl3LZUXf9JomXFVOWkJKbQ8pTpFnpuQwF/7hlYeIBtf +HceZ8dKKnmBNQupuWONrawuwXf956Y5VoPd1tjz2iklvEUiwbZvCaBzdD5DINp/P +5XC/+dUqWNTBL4iS4k2qMThlCbXUJ/qposR+imbYZhj4MrrBsJUIvZEDVOxQ2KVN +nYkflY82/mGe/bezLs6UIV6vYqkWpiZGdjdmBTAwpfSoPQMLITV35s3IOZnkXVjV +YeySBjS2ypLaJqWNHAeN7QXac2RAaz+VoNh7wywxxQ0O2ybfRI3AmMLTEv9qRM9b +oJMCVFZi/kEW7FGqO9VdF3aARWuljWec+/Lqcw95aqZXN5dgz7iMXu2ASOWgSjkW +UkiUbso2L7f4W6h9w//D6f1q8hPlTlFcUtpMfwrK55xq78v5XiBe1jvjyystEzO+ +EegJwSpMVd/Ag/nf5eWJaHdcxf8GMaEpkF5IOIpyhkrjPG1bjTZEEwL0tUPWqLuS +setC2m0yZzctqpNjvWkVoghi3+iPY34ZISxQcVR9sAFuYTpBEuPodelO2tyhIQXw +Z5kgSFr5V3yu6yzteVRAJ3xhRKGQvHs93PXCMIWQW8NfED8vi2EiVgMofk3+i7X1 +tc60ksuWA83ZNZnAKLVWOxokXGsHB4SNMmbAxMzI4fhBMje3IM/41DuOJZiR0VCF +Fkig7ysL53szipgiOXruWVVkHd0zioBcVgAfM3OOmwqOyWiJ/3NxXbtTWAEUebbv ++Ef6vGaFT5xfbTRVTEvuEccgfdx4C0JWlqAteOqTh4TDpdengP++VHUf91jEez7n +Keve6BcEDKjzlSPVg2VSSTrVRJJTwSESTd0ZhPvApz+2huAeUxMnnrBiGvu+IOtR ++tqwNBIlILRaX9sNxe4YfGRn+f0sIBT+N6vcyFBieaglTLDCAXGajiVtmBKuNfTM +//eWSvyx4mn0/Bkmppn1N/a+4RwuuzKCecCOQYBqLDTCpvHsn49fMsfTsA9DI93E +HkwH9OJIneD4nl8Fc3Nl6IfD8ng7/uNC2+URfJnezcTdgwxxrg1nMKNKlVf7DUgm +OjJG3WejIwZJGUIqmAdrTr13TMNwgP/7XLiuCzzTVmtsY+NWwfsh80H71ctOfP3T +L6dJTOrQ0nLeiHsAp1w0wE8n+ZVIO8Dr08NKoEGzkXe4XSA312T7fOoc24Vkpy+Q +ZCq6dDJaHQnurjuYEOw9QX7h4KrLdkvLqCtY7MYaEhd2tT+5liotLEFc76Khlbk9 +l/B5hbSb2AuUPhhYolpfH6mHCtlxD9PRA8yr5PL0/wAeiaNxcS3O51Zuj+6zQak0 +FnI8R9QFYe5bZ7rHkbotep6tQgmsHQ0O5saVWfxyQ97IyYTl9l+8Nj++MmGFRJ+s +rmZ/VUtkX1WrQr1fipWNoqpJrNEbwDYBbLuvjlLEhavNAIUFC+GMQeJKOE5Ri5y+ +JJtETDnOJAV+K+I8ewrb54TaROZ0QBqZDbY2tlHKoQYHwBvQghJ0Psf2nXOcsw7U +6IzWdnLJE89p11LtT2iseG1mjT4YK2al+gKIVi3s4jncZwVQ9F3UqzEAqwdQ4CNm +51NVLqYJWW6c69rJnxmZH5HLrnq1S4jVZL3Dz3SUj6IM2r0i5p53ZygMsoLtk3FK +mACkBT/4od9l9lMnM9egp4ztLZirbxlcRzHXr2+j/l3KcEGBpZq1SpXvuqMT0mC5 +v6JnUa5wnZu03y7qcNmsklTRVGXprAn29EDZeap6dmhEc2Z0bk6kvd+Nd/ReUa8v +VvqhgYSFHnqmgD/PZbWd8sbn9pZ6C2hpxptFF1Aok0ix6e59EosX5DQ+7olH6g4G +mT2/kuvd3Pi6aVVqYUVPw3ietQajLW/zb3prdhkr6r0qjXcDzgBmZamASbX1qUcQ +gKCUUfXYIcr4Rj7uErUv/zyjm7eDZHX5HyUVegW1u6oi0SRKUiazUk5uLXxZ7CF2 +/nLkd5vpapOfrUsXLx4MBdh2EwXezBltGx9EbkR8AYM92vkVR8kO2ZYJfEVic/wB +biV3R0TNAR/0mwMxWf1ozSnbYsMhrmArUXRw0HYxsEJRcjMyCe5IZiwgEeKUw6Xx +rEg3h3iVz0PBvfCZs/Smmq8R+56BC2jjkMNmeuS7ObWqYzUEc9c8vyMjgKZKJG8M +zVsmcTeCbE9IX36bBpW3sA/lM3nZ3ezqQulULzRLFWAvy6sOx2KFiel9GLTYDQDB +zUp8jJlQz2loYK1xE2L7HOUunEEUOmRLHYk7ZZzVR8PNjMjlZQflCkdbNrGteVPL +Ahizq0jDM1qqw57WDvs8ENqJ8BWrrZvV3sAgJATPXFmzE/vI0zeuk+KW8zPs1pTJ +wsT1fJOPa2sqRoqmpD9Ex2IF0kkZ0NFe7aWouj1JcKXi9ZtgfdD0PhCdPnCaDnHN +l9LUcvWMD9o8zue4XVm1W+l4ZEn7Ki5jZwmK7n23QuJpdR1LgSh+YnN23FK3eBEN +j+JSTzNNCNXm+beqtmV4lC6y/xU7pu9CtxGW7+xVYOjPKEewEQrLt3H0dZnAARV5 +IhJ7t0E5qrlpJfJXuxLAHoff8bNSd87nMRKOWymbNymitifq7avAsXLJwiRCIyiT +lmaFehmuPplmlDVZGkIa/o0+x1iH6kbBrCYtOjiiMrmf+JXCUh8xMuDbixMvZSM7 +vJkY6HlXzK2pizB4xPC3cMGkFGYBXRnZB31HhZJJfLhzI/NkUlltafuBfbzrJLwc +2o6gADhTiUjevQ1tijRWJX9EE8ki/DxZrjdo05XmJyA7wVs8Ga+UmCwb4qYh68wY +gJZjP0PW802UBP83iYTW9T3Ro5Mh6Zv7u7D1HWyF88Z1MMiqkMGEwsXmQLJitWpp +4uLBIqcb8vsGN8afHTFm7E3mmwi8qOIWWAtuY2Enq0dc1NhTxRA2Zy8vIettEj3w +TdkJWiT8sjmXOFWF8u3V/hLuKQ75vYDpiD0pDGzXmS0cByYVhObTHi8lKNCo3MYi +5/5DDm/OPQbmg6c7SeDnSFhrl+szk0f0aBXsH7yKOPO06Wg90iyoaKrTcEbrKgUG +X1HRl/coDg20ugeU4MERpuw0jMQlJFpTNfJ/LxpcVLgMXyIMwMboWX3b1BcgvvCU +5sth/oz0RKiZD5QJhFEHCtkPk0QweXA+zXGYQ4P/mta6m4wHoCB26NT+oXfCPsqK +oZpbUOgW3XFLcqPjl+2sbWTc7sPrzSu8t5J/GWhFh1VoTlbVQ4QpcggJ5yCWC4E4 +8knB75CQ/NK8fOap6Knybyyt/EFhC/Ynt69aTlN3MhnmcvNsUKga2+pd/m6BN/2G +YFrh/s1cZIf3JBYGwdwsmRPYE9t/xHlxmBfDyWk7qFtZCuoloTS0wj6CPff5qza2 +MBhKbpveRZy+8pOK1CfM6tteYAcbW8ILfTO/dz+c2C8Jt5ksOpgUyPfBD6N+TMrC +iBJiHRIbKPn12n0SBFx63KRQZpZmN1yEYv0PmyUSyJhP1i5eDgpZtYYlKYFosEhB +Wr2hc6yRWVCKyaTATV2lDLTbl+eZFp+p+/4fLIajmlOJ1yaPvrN47SEGqTkWJOSY +rib53AUaWywqUWBt240ygy/HKIbOl+PreR+v2tfR9DsJTnSCBaA1EUzXitPhk/Mx +WYARFTa5pBU5vRwABP1Zey4DvWypwhjee19ArUYNUt/6dLFdr/WNc70VMVoFrdVB +Gz9ykdyAlJ48tnyQ8kq3sQhghrpZ7eJsAOtcNJHQI0WJ1Ukhwldn7ZH/A6JqGWcn +RInAU0B82EjaEDvBXRkcHhatOQRZcKO10hsR7E6ldgFwjrL7bD4u0f66Zwcr5LcN +arSKZsKRC63XfZEp4MFocxqJzx6FLBJn18C0lIPGW3c8B6nfjNbfJ4aiPmzUGZ9A +kIe8SY8GIgIqj7N6it0fEl0pmBINaUx2q75F55D7ztBeXZzPkHvsK9ZuL6iCfRyl +5KFHR3vlIN+JslecTdzlaDw0n+7Q5rUqeP+mymyFcDyLr3pGBGLh8SNKSY8t6EhB +ry1+/TCZXc8Lc+lORpePGzDthjndhG3JQrykvThFnznMMkoN8pBeHs377Y0e0L4y +kCxPusIBj0pKEPkz+sggMwB1kB6qepLvzW2Vx5BmaEbZQtX/+gwRaQb70ZZJa3fs +NPxSgP9Tx7nDsb2O3SrfOtvLwEFV0pM8UC5UNvFcJJcOhB2vqaa4Ar+PGuI0KwrT +1wKIZs0wY4U7IKZ1RUwe3xvEz3z2cn4YM95VllYgdiZ1PE9M2QltV8VuQljPvShX +BU96YJLQ5SS9HPjZHJx/mMiJeQaWzF6opwwDVodS8aMkGMPPSiVgdiI3+fOfxaQP +enJYWj5nRfNlC296YjkmaO7DZ9FySaK/EmyhLS5qcfYzjy5nclZQQ4bx/SRsJ4Sb ++SqJCf4zOE2O4DOyuWp/iOGyH+sKCtk9FAVP02Vphc+qRhzmBdS0w4sW4dbh/C8T +ZmrouLehSJHvNBu9N9qVDoNulzgYeb73L94+J/PB97ETGsVxnXOsOTqfLywLiRfl +WVT31QT+QXsxrr/29ggKn9fI4Ay6iWAdf1USOd60SRtRBLJvOp50o661wxu51uzH +IjLbdSQ+NlSQ3sKEUpXEYxRh/9CzZP6/3WPDizT+i772jwuLK2zCcyCajeo+p/HH +vAhm1kkPOuwb66oCVXsB5KSfDEg6LLsLk3YhbLzT18xZ4C8AMQberDbN0Qk2uSho +S4Gd4Robx/P8pN3feDsNH1Dref5XSx/SrmGjcowUm4b4IP8WpxB3Dmgy9BEqdQeM +8LhZiys1nwhmLqvxUby+MykcOHxfRP5FGRSJfFCAyA27ofryaAvMQECA65Gcj3n+ +zUjie1UK6GtaNpyDM0p1KT8u96XQD5UfO6TFSqFPi1mTvNMWw+tpEH78500Asc0B +j7Gsc49qJnu4tA5ggoe+cNqtvolxQWaS3zeSeUOMBVTjOd/4hjdIM1Mt0DnljMGT +UxcHb8ojCqpafbq+PErJNxJrmtKbd0QiqiGVn9RsHj1nUnpfgm6w7DKZXoCiv8hM +XYpG8mSbfJfJiJWVNthV7aoE4pbA/GgXjmfUIyQDfIaPUaivmCZn7yuVFhrZBeyO +uy3sZVsF1DhH6NudG4CCWYIw6FEOQbKNR2drfiyYeQwaq7SQIIGJDqa7hgm0Qq4j +B6AbpMX9cIqqYWv9/+pYevqf0sgNP7QJ+uhfl47VhfSBspRWkWcNV3HWvGy6WHw4 +tOpAe1vFrTTr/zEls4oCgl7TtGJ95kvc20g876h4I6OTZJgGb91Fo0W2thMNWy7I +einHd/exMiDsqi3VLA1xvr1JT+YQFtzVa5QMRpa2+A8JGsaGHAGr37/EoNoDJFvo +mkfT9EZu2lpXRW2280T2KrXxCO2aMc5V74dGM7dMw8ZRQrcN/WTh4ChoI85OL5yP +3xVuIABC8KUFItUyLqqGldRia0x2T3ue831x8G5n2mSWdtEHqf6i5fX30W95+xk8 +AK8i2P4D8s4NjF/OxlDKOk0z7o50I3Bk/GVx89Ef/Ga9i+1Lit+uWUSSYOWdkcG3 +QkFLLadqm4XYfsZZMixjiCjvrdJN0RRgOQ2se3mzbwVcd6MllsKmK/AnwZjx7btt +m4Kg5tQ9/9Fpcra0B56R/i/Yqi95R9TRNC7+mU6XWlpZKM+GGRyQLKj1qIIzGzyh +xjDFkoe1RpWEHcv0UCD18z9GIQ42MyzsfJIC18RKAIxhKd7v7VziEkzhuWcRntrx +bblms23U78v22JUHATCyFXs8CruCMjrqTR2cqDyfe4KsEoRmgLJOgnnUZkv+6OFN +dkobhBXPhf/fN0kxyV05eLvcVafRNPdkn02OVfzSjfhwTM1ksbGnYoJg4JAk6qI1 +ZzuKe9QNzoFalCMS6Vnsy+ZAs3Qjy9oNjJbiL6QB19vcm+hjKrNvMkrMijBkZ2oW +GBwkHN4gQz1ovJCoXjTMNWUikPBr7NFv+1Ygm7xACwF8i0szHEt7Fq42Tq3fZG6I +Kqbgsgm56ABN7mRJVjAGL6Bx5nOsHlxPMHIMS0I/92WuG52fqyaE4EFrFyQt7Axn +TDh5YNM7DuvE+ls09xgUJhdDz99WtyR80wluAljn4g8SQ8UuNnRg+vRt5wjtP0Fi +hFZBa5ba7x/aRTElxwtEI7cV7tkzMUajTFQ1OdWL4KvNR5EEDl5vPa8sdZuRHATC +ak8xTWIhyeleCBO1TRBpO+39LVVdGTn4Q+v6B/kRH43hKLZy/GZUUWk7ep6nTRE4 +h7GWht7yOc3pyIY6NtHuCRugnlnBeDu7E3TkgwWEpscLs309SJZtOGkHDh7o/7Qx +V8XMo4nqK3d9WcfKNoduVkm3PKaBr31RZGU1Y/fzc6S5PG4W6KFklqBw/U9/mfkA +1wO+TYsnlRcZ7QxyV8etxiQBzT/IjkXldWKhBQMtphk5qR1L7h+vk6iniRvY2uUF +6pvoZs85/EQoMrq8YLLp5kPMaX9J8GNEAXjOVPo+IaVNH/a+Ouws7YTGTdT4fBlo +BFwz5zzZE+S9S2hDiFmvaQ0hWujP2fGoVLD7yFKnFZOztXKKFtrvhieeSpyysceE +gWVxhTL49UuPRtKW8F8pfi+IW9+DiuBJ3+9QBtYqiIGogZ74jHXjy8Ta8nzd1foW +EeJsA7qtW7lP5HNKDjfXJdZj4z5nCsuxyg8b5g5pjYMVwsjowUOm7zn0v2TohpvG +bfphPd7P6ppTImX4c3A6odHTmzS6iWCZLDEqMAYj597/3ZKCtlmAR4+5VElG2Ybx +tM+X3krCYws0/HeB42iJ5+aKVOTboqz3n02/pVx3+7P7I1OgeniH5JmDyuxsT0xR +XrOLHjdnKVLAYjQ1auo2usLnw3vJLHQxNOMrcHOuOzwexj4soCrQTN13NXjsMH+g +U1tv+Xint/h94m07gOpBefqSijvKHyZGC9zuQYW6n1E3CryZPPal1c3DLeEp0lMN +1euK/kVMMyj8rOLEck0oAhutLTO1R1j8WRHI5L3yBFxzx5Hkmxu4lUdAkVnGxdi2 +pgX7w9kkykuhCkMkJM7JC6MOWwOIz9+XuHxlFkCtu3DrY4phK38PYcK1sZRmvaX1 +tkXtlsPXsmlTtOOwx8nk3+Stmtpp90gvZeqN7/M6zGSOg2qASRsATe1ndUFdfYbj +r5Dpg6bLtK6FE9UnPmLBaZ4AMd6QOPpyKljO5wStNauZvVbVgZY3rsqxrt8AnNx8 +nt+H6zs0u62fFyf8IgeJ/4zYLeaaPPl37uQkr7Rhx/ZFLfED0fJGUJzP+7HzZb+8 +TXwfYYJpMMYqTd6QHTw1GVBFemWqL2d2UPQRDtZ/Ogt4FHvII3IifnA6XQZ/TN6q +QA29yLX7nO6xMn2E4+fqW/OqWQzl+RsDsj41+1FXZY4aCgCTHBTaS3keVRaeYxiS +q1xIuwtu1k45w2fWxEH8zhc/z4bjgH+PO+Mk1DSOBw51d58ujxEDW0Bb/Jcb+cZ1 +fyBO7P/aSU7sgsytzgGpuXM4UcSOv7+VXSLGCnkJC400Ufjp5BjpC/d17PYMQaHV +AWPxyhRH5SGOtbmx8IHSDdlWDrFTu4t81doupuJq8I95H9TJk5NcU+1KxuZrVfZT +r0dW0wRmeePRX1YMY3TROXIRBSncW5sqn3+AzROryQ70GpdfrYTuhio+ER0uRQy1 +8/yIVvbTHztFe2JfHC5JL8B6YxSwUTeX+u9ZOV+4ECjuYDLNbL+r4KX7r9E61HQu +g4OCw9l6L2MPUAZtBS7CSeNXorNLYyzr3jcO70c3l2Xd5iQVA0Ki2FeYowB1bqt+ +hhXDaKrt+WIVTgWhilo63uqgbZYXZgnUa3Ol8NIwbRkQQSrEWh+Tl8g/678Wa7wP +8qcqb3ZGfpCiAyt4/zMa8+hfHxV+ofczsv0sB4MriheW8jFN9cCOLhMNZrbc3ExP +J47UhG/Nh9LOTjhC6y+rxsdD8PmiWdZOh/tuK4n184pfy+7hfESyxfxpSFyP2UZG +5aTOMKt7BRnB6Cc5OV0si3/RtLmsbsktM7eXE0ueRs03tnRTftyzZgk38BVINwDg ++MBiNAka61VdZgRXnG46VSUf2ny1qyL/ISAThQYduwOiOvXzaCssOnulyCqnBsqp ++ZmJQ7BiZQ3HwZkYkTQn4BOFtohBfCjOjv/8i2mTmNeaSUwsMzXVMsBaBjJwwQkb +7VDDPAWnF/hz+a/BTqb7LXeIvtq6VrCoM8YPDSz9phO5GzhCyCuk1odngPsX0bEZ +WZS7SzUwvPGGwGse1drbYrvY/QTjb0O7BNcipq65jh8FbaEfvI64j9Av/UwnRhod +jOzbN3PmpYn2RlpfqHshSqBFsQY0q6I8Sju73xqEK/QwSdlpWVbEvdw8Z20/Ysd6 +ZeNBloHw/enSxbHZx1vqgPHuCWHCTZ0OFEkaM1lyyrv+H0bCmvHwkCwKP7oE14Fb +PY0zly8cXHVCUB6byJK8ZmRvJ6YI8y6CCLz1nzcRWGHnLnHEnTxuBboX1bZvD9mi +18gvtGXpZ5LVUMuSS3qOuCFF664DEvGiQVoyAORDiQSJ/cZJ1hN6dYBzXKhq69lF +ix9rUHZdokWhsIAr7K+ys2/AEoqaU2vz8Sov9EzWAHtXhAGT7Ef1uQctuphtvu1e +p7bw/i6mALii8Ib96YHjmFhnnycQe8t9j2QjY9CsgLsp0Izp8OpGBWJyWUZo/zh0 +3bQLywu0OQYZEOknCLjCteyd48WMcWg36F/GO0amAhF50UUERWZSEd9V1Vskt9hU +D4wld/pNxMfnLo2y7jy/4+nE3BmjTGBeAuOQCwmWwTE9Mxci4yDOsMKUTtC0BMvB +V1IrXR3lThexkwJVwtFBWK9FJ7gqoZwsNAVZmLM8TjGG+ZUach9lF86IetMp9UUb ++PJ9BR1aEVw5z1fBi6s2oKSci/8m+gIPLYIQ8ehhaa1O1UANgP3u6WMDVyRejIIg +MeApUGeUWSuhdv90S3w/fpe1AwzgAUZkQRvpcMBqI3hLPJh84zukcYMTa9u62rUO +1EDx2uLvxpBAmMgHgvLVSoVmRprtMSxGMkcSwaz2cAwJ8oGt1sUYcGImmp2u9sif +JKbY65MiTLssLxBA1i2bh9/WbRgKz3249QotJJYSRklztPi5IGgOWP7HbC0GmUxy +bNdn/iOm/wJrC/B+ORFsxvROzTm8EZZFMEbrLhoJjaHA2hFn6nYrHOx6hbHVo7oj +RleVGaCj9aL79lSjqssQZdq5vKIe/nc1hW6v+80VbAzc/Ekbys8+516vytl3o5r4 +KW+CT8JZNwupYHFg57O4tBpFY23DEGwwUAgXSmM2dAp6U8UBeFz1uG5mZCiWDY2R +UNIwEXTBAYgLSvYkb7FCg20Zh0CzR4uCbuAmcJyOWVzlC9H5mooGpVy8tZq+qydb +NQgflpxzkeENDTzC6wFwxOEhupVNh7DbmqnIc9SIXDj/ORurlQ5k9+uHAo2rKtzt +BM+pVw6/lpB0jCH5PARDWwLpSg9YSkTxPgsZSuu3DMFAfvUCPQAQCRy20Tqzqjme +WcHl6x/rJ4RvppbBuHJlpGn2uEwFF5jzAt5c0T3ygaJYpAGF/lkdJpdnhRcbV/2q +B8vkUgglCIt5QOldsNBDtQOGa46eRxtT/Y3Jc6OlKQ4G6yeTfdLPOJdRj5qLScIF +b3OtOMwPglf7hXcsS3ucCgox/1J0mHQsloy+uBX+qBdzkQa9fHCs3InEhgf6l1r0 +rfeXmdW+RJDL9SnI2iLXNmOzO+kAeFJT5tBnTUZw0J1YGHUpe7ZuHFldgx6szjVt +n7a2ZSn4xsUVodv4uVkQpDF2jPzWrIMgi00sdaqFNe5/hIHzFhoKCwu2Xhnb1crT +QR9nZkzcK9hzc73DaRusJdC2sBc/wPOVdtimPznfQY18B9Q2cqMC4rTsWpi2pehk +BKMi6Kd2v/2CC6Cb0ug2V7OCM9idNFaib3LFZmbySbTe2WRDVCBUvZv68Isr3UPN +WuTi8hCCUOBqTVkYdvrb8ZaTuUhjuo+6lB4i4lH73HJwlwqhmMP2SZiduah3daF0 +ynlmHW7dFdSln3xHP6Kp7mpGZ26eucZ2hBnoGuZdY+PlvoVNIw8UyzqKRGI3E7g/ +xIfXgMEGojYIceD9725J9PJw9iIRMF5CzEyvaYNTnTWdnuxM3WIYszOYnR0P8Ohu +YIA+FTTYehepgnXYkI4n7ePzoC5ar4P7hBwD6+D8Mk4gZTK/EABRYiSvBGfMNCg9 +tCm5iKdklJnP4wz9aCFDJU2s/5Zy9hNr5JVCITVGYM0e1EsHEa6e+JHs3A2WNEde +Aq6CcEDuEdZuHJbiInhI5PZntwM863biF/eVhGTGLWq06MW/7EHDLaPCSu3FYUeU +8t2HBmKoH8vFrOilQMYebwxlTTv6wqvh18NOATa4fo9FQuayMa+CDW+JZNjRko3d +Fz7qwsKKYrFhK364K2r7l0rxXCNAWyXH6Fq41Ne72RiAHPla3ULqwAernPULFPsC +prvimmP0E5m46eVJBD2LWvxdl8zGCxMm7kN30uT4C/qo+s3cceosRXZ94gmlAUJg +EWu3lXI5joXNvZPEqOfFs3O29fn/MyEmFENVO3XwSyhpjOcvA+iSW+NLPZiCDiWQ +4HLKmClo8sOMCnDwpFJL7zo1s1zVQdwhkTyXb/SysE7KETJF1zp9xVAnm5+V0wBz +YEyi+6g2xL6Pi6m6UmpAsLT9ZjBn82Igx9dJ+llb8bq+i0kmlxV6mZThNPdZmjGh +Qd8zy43lEcKKn2qQSQTnLwiYY9+ZAYL24RXDGWDvxT/zGR4rd24jGJW3SLTt6Suc +fO3+PV6sYhT1nluaFUdEecMTZ8JKC5gKenoEagw9PysQgydP113uQL/Jc5Fmp+HU +HTg5g5ewleM38+IXqOUtPL2FCdr5zCM4QinbrlcfEAQ69BOuYuD4m7MrRpFeG6g1 +ECuE1T/0xeo/gQyS25iuUqi1PJKhe+HfljmLKX7AxNTBeQnzqmp1KDoLDWxN9WFU +ZpvFVWlA6vfqpFWX3Ofm+GuTN92V4H4nhudb3d8nyR3GSpncsHm8M1vHGXsgVxEA +r4e+YFRQ/akXQBuwXlsQYLVIuvLAS3jiR4HM9IHo11klpY5ZaVnNq/71mSops0h7 +iaYxuSUfeXJdslSpujWd7uZjxeFMbBABi7jrd1pu7mthdmJIhmdvnbxdLylKCGn3 +1xSzO1A3Rw00Wg7aa+9k4+0WFIZckX4NEQRAcpDmjl7cNXbxwIibQ5VhGDGc4rbl +7abtBEWrIq4Wm2NulgZraBqiJ4XzivzmGxV68eso3hqYPo5UHD6PailbwPfCUp6B +FeAm7aMsD6OPejPtACDRlPfnO16WvQXjTLz99Prm8pKLKD54jWJtp2g8IggjEl6N +7nHZJLRtQbyDIzBUxcMFyjhq/1STZR8hpookHBFBE0ukd70TVICLOmfzxLk+QqZp +D5d4hkHTneBufLhLJlJ2B+k2KLckRdVfoXz0tKH6YN+SelxwizZUQoxyZojMMCFB +YX8549iCeGR+GfCH8hk5AN/BL4t5OLcu29H1TIxQAw/KONG6zwKnc0S4k6lSkL1O +6QQI2RPMkfLsAaBBro+R8i0c7rxLHyZLshTIDqnkjeijFs02zZQ1WRVZ2t0ElJ/b +FsjzfJgGTM/QhsIP1/f5Ey67oMoCiBlu4aqHS62rUgtwB5wpQKGY4j5B+hu7/Mgu +etC9iINgYRjedbYEa/YUZfaLpS6LzXU6VPw8jua3KcVzYc7L0Yf4QvgfdYH6hOhs +PfHijk6AyiI+FBpogW03kKM1Z1+/tS1i7w31zEHCtrdyb4yKg/yfl5hWi0Aa5o/5 +ug1P5TTE3wf5v+fNogH0sithHeLh5b5Uh1HOhefDF286t5Ml51kkPbCPYGw1ZD9k +pJ+nbn82l+7DvdHa2dqRi6g1GUp3/XlE57PNUYN+ckDQMSzdDqvEY1+vQzE8eMPG +Y8FJaAXNL5xVJeHk7Vv4ndiv3EJQ1HW+Iiq+nkcN2cDVIS30xM9IKWpmn5t3hUzm +EbQCAmXnwmEEBKdGWhvc+DmiCqGZcc8GMd8z4JuUlKwZdqldtD8mpmEKhm80YbyJ +K9SNppDsRp62rUqj8zG8xz1/tQCfd6gyUsm+VbJzajES/bD7dvarJgTnGHzfeIyJ +89mOhPVPfOIQN3mHyJEwrdZNYg43t02j/zrLI+nMxHmvwBd5x940yAAWIn0aSMP2 +TfXpasZHSiRQvcLS0TRitbP6HmwNugHhDbnHeg8LfIILi/CTV0gnSn+sXBM5cOXh +SPPdl6UkLcJr0ug+zjIjGIkzGX9D9MTh0T8Pk0XRbMEF50tRraRsj69pKMvt414O +lB21gvWoLTNmek0hefkreOHsHFNRxgEotq08Xv0WSmM4CT1sI3DJcyMqE7vdBQ7I +o+SLlXYAOlxXDBlr2zJl9d4PDq581oMkxqHfDGj3CSSorlCNIki+MAlfyd8Swl63 +M1+blHrXh04b/y9Hnxf7p8Mzsd/pOXBow9YY4hu24H2sjhpmHxb7yNMo3HrycYpw +AhIIYWn6fsphRKV+SRagZ1XgDt0jPeMPVdJwDiVKnLsvsMHID6EkwGck17umCCas +8xKx89JBC9RJoQb8DMnu6RZC4bnNRWZ4aNZY30l3CXASc0V2qoQgUDsCOKsL+Ons +PAXmeaZ5ieakT5mLBV1EuIF+vK8OXCEt3OJ0CD67CHGsJk75EAu4VxhGotHv2QGI +vfBmsJTs4pyLpNwaF6yCsjERSB9SM9XjRtNMPbYzy9atiB1ViKnVGIADKOSR/S8D +0e0GPYEw/Xh8CU3DBnalJYFHnQBdLppBsxN21W6ZsT6MYf7BoQEo0doPNj2OKksI +BNUNunBPc6avToS08SC39n/yBfo+nXgm2e/xZThNieihy/ijb5k7wrmulTUTIk4L +K2Mih0lwOWPi0SqKaBK+6aV75rcGVBgUejgzWco35/8jLa3LYUzjkEuXUpYiHB+c +pJw9WyzyIdAhgsZmEcqrMTXSK+tEkW9gyki8XA3deDArRz2Nlmoh0vFhR8oFaEJw +O0ctH3e2v/3pM0iYiF7zwi3WF9lEA4N1UfIR4UajVS8SNZsVtENPzgbQJ8C4o0xV +FEM2tWcJZ0h6umGkzDnBl0TV+NYbiNlAVcl7O6w8VDbV//2EQO/WqkK8RpzoK+Gm +VXZucMz0GNkBGzVuKR2eNGyG45J4tVXH9sOhiH+y6SAacxWlMEOB6f0rwLbwish1 +Fwu85mVobd818jRgEe/z2yy6Bk9LArJ7Q06yXUhlZcNmXXiUJmyXw4Ehzk+TtpTv +TUqwIvpFPubwhs22T+zXCMBHoFufWqil9nbbVLH4muVrxkJAoRa5qvI7wM+i7ign +OeKBHE1rg2Xckohgyuowxw7iC9zl0MVyeWTk7TvlKIzDEux9TSBdxru5J8tzJjx0 +1IUPs6O6nVIGd6dFjAXGTczCcxBekW5fdtVC3dQQgftAEsAv/iTlUNNlIuURAPYC +BN1cu1BqB43iCmZhM/9Wyq7szTyGqtLHzXt9WvotcKN+3+wsdVBviw22l4bPUvd4 +LlHNMgZI36AuiEZsjw9pY/XEZi0Fc8IPGIrnqk9WjEI6jzPFxG+FjktwSPUUwodt +jXyxiE1CSuViB2GS0j9uVxEfCFpUDHaNnGF/vOjfUD8ICc4KM84vqkgFkUYFflHn +QPt3+xeYstdKVGNPrqqrji9OI1t510fNMbK1vrngDlJ41BYlpCanedE/x3UX9P5w +pMGu8bHyZ8qAylR7TUEmM/eRJuApIGvpdxKmdClfi1eucZbkOkLx3LUApowCnjwo +WZd008A4V7LWhAixMqLAlgqKDMurg11DGhk7ngmhAtvjdzcbxyvWt55OJH0HV/Yd +gi98Hx5El0A59yaAC621nRCDeMh/M4XtP+oReA2R6BBvXQvl8lgXOR2jJ/B/wIqR +j3Wk57ilOIusoC7R67ZUYp9eXElI/TBG2h0FwU/JCzTmpylIwKTA64xbu2I+fpbf +N3IeVn5riLGaB/r2wBdQKPDqy2DbsO7iWMjHJbJTBL+verqLRRARJ3ahio1DS0CX +2iAI4Tvml+6Dmg8ZPCfDEKN53QQ4kXxD0vKx9qsGCmqQfzhUrXV1NA6EbNovMOp8 +ydGgVi6KS35HuXvMmzouv3sxJ0bxbcTI7LBvoBz5InjcX5gGUeegp2v9/kWKbmNF +4J2Y2Pp6I8VTOfxGbDTBt9+kuoWJLp800pr/GyHd990smDOzALRV/fwYQvT/i65k +ma/lGIuJAA8RO6q6RemyQfkGnMZvbfX38i35KLl2zMgFRX5HNSPAvBE4ga5lP1Xa +dtDSrmm322ikfJ/ylkXdSvqU8ESC8+iEqUB/9Qoic2Gj9veGe0MUQVjV7961BQ9V +uNXoJFECWqZb6qybR8POTrAqMqVVIkGC0Buw+qpunyXKgnFLxxfHc4qmffUJMWfa +g9IW5Lg3uVwdGoXwm8hq6CNU2WJ0Lusrn7/dY2LYKs8i1646t6Lh44hCvt3nyBls +cDOjkzAv9Z96TFEH78hn4pWyyPS8VgqDu6jrBnB3LhhMT1NM3dJp5aLy7mJVQbsL +rN9u2AoPamQiHQsEo5EMo76jSvO6vNG2D9dXgd6SG+n/eRS0ddC1Y8wZtNiV/ltx +q0xvsEmsp5GRl45jm/bP3n9I01y98qKssNK/PhzvlygOwi8Hu509VwK9Suc4Fmhs +1idwCto198SDQdtdMPLF7Lj01Qg+0nM8e4MSWwUeb/9e4BPtri0z5XIxVXHIwoGG +Vi4LZS2fG+U6k8YSkMRBE+++WeAwDk9x9C2dBRVFms5+kyFIB8VU0WRxka3YU3rS +tKQmIWe8/pRdZATkjcmREgr8P/lfcR/QEuP6VmhXcUjr185hXnIGDkoLtVsD+F8i +G20o/UswV7QeIpUremFuxEshdW6w9cRENX0RPgRlSmPpgfRiTEXh5iv3eloNC1Of +XalIJDU7w8XRQCBljNp+q0Ln/08OLda89S9OMn4olxnlOK7qYs7t+/FmFUh2jBVP +8OulTTkIL+u1j7sBhZtk6Tdp/ui1A3EzdmWMuN5YXZBdHXFA0gVeKXsiv3iWfzRK +iyCLCiQnUwm4nzeqaM6vU0y5/+ywRDp4CHKiszULLMUGONUlHJEt/QdPXe8Q9QL1 +NpgRTNh2DlLyIqHUDXiHQcedXRO/2s2DQOSFeKx6Z/XQ7C33yFWMcDOPEJ3NZGxn +hDQ1vXqtd69JjMERPkpHiKSapkHl/a1irLNqwMofDjMvmZGRScDdDilgAjb4sV7v +K2ZbQe94qH5wFOaTcjZC7RSh3fV3RBXjLSuX73iTJCJe15+n4xERlZutvm6lzCC5 +a4u0gAAy0n8byXzyawTXQczEEEAUC2pJexEWMriVfbK8zWLXAfvbN6geFBrD+M1p +Kdg16ejwGkuI1ZTqkg+3/4D7n0kZ8nel6/+qdJUDpKLf3HwTpzSXIFxkjBioT9lO +/y2BO3KrFs5o3hpjXGL0XQeDfske3wlRG4H95bVRTGQUK7b7SHchTJng6nkowfcB +H42up7VB/NEF/AARq7lPGfTwfJTl0tGK0n73Vi8yuu9mB9Cz/YfAUwZHidq72UVJ +zFJb7S7i+mHeujJSXBtj/8ag6GuM58C0ek2Io9dUibg2WWLtj266DRPuyZ+S7LaB +QT1Ogf9iFOB98UxD5sq6rP7x4y2u/eDjEyJBbq7qArEhbXc6/7YGdYdyZ+7HL/Wc +coFzflc5a9HBjJDgKqZOoqzc8POXMLybWxwDivSDbyF0b3NrtIPj5ubLXpzQaUc5 +aS1U4Z0z5BZ+76NGUvdzcbosbybXf+Mrj8HhXP+ob7eCdUam1/0cKAHUvTPjKfJ2 +NpZxeCgyTqAh/KgGJ/LfjxC0jRV+YlJkeQD5Q5NuLHtjswGU2743glGzvKZ9Pc+/ +Ar1eE0I5WI2+ImVsO4MQlBzOidRX7VFQlojSW0Vl19etm3MrjcGwrhP9FcMh9Hd0 +OZLzTsaNPk+oUC7ifRecJvEDDCMc5vFuvcgmdAf6WdxtshgJW5hSVonrpgBPjr1k +//pragma protect end_data_block +//pragma protect digest_block +X+tWUYKDSvSQwlcpHm5Nf2KNUiQ= +//pragma protect end_digest_block +//pragma protect end_protected + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_top) # ( + parameter FAMILY = "TRION", // New Param + parameter SYNC_CLK = 0, + parameter BYPASS_RESET_SYNC = 0, // New Param + parameter SYNC_STAGE = 2, // New Param + parameter MODE = "STANDARD", + parameter DEPTH = 512, // Reverted (Equivalent to WDATA_DEPTH) + parameter DATA_WIDTH = 32, // Reverted (Equivalent to WDATA_WIDTH) + parameter PIPELINE_REG = 1, // Reverted (By default is ON) + parameter OPTIONAL_FLAGS = 1, // Reverted + parameter OUTPUT_REG = 0, + parameter PROGRAMMABLE_FULL = "STATIC_DUAL", // Set to "NONE" if not require this feature + parameter PROG_FULL_ASSERT = 27, + parameter PROG_FULL_NEGATE = 23, + parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature + parameter PROG_EMPTY_ASSERT = 5, + parameter PROG_EMPTY_NEGATE = 7, + parameter ALMOST_FLAG = OPTIONAL_FLAGS, + parameter HANDSHAKE_FLAG = OPTIONAL_FLAGS, + parameter ASYM_WIDTH_RATIO = 4, + parameter WADDR_WIDTH = depth2width(DEPTH), + parameter RDATA_WIDTH = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH), + parameter RD_DEPTH = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH), + parameter RADDR_WIDTH = depth2width(RD_DEPTH), + parameter ENDIANESS = 0, + parameter OVERFLOW_PROTECT = 1, + parameter UNDERFLOW_PROTECT = 1, + parameter RAM_STYLE = "block_ram" + +)( + input wire a_rst_i, + input wire a_wr_rst_i, + input wire a_rd_rst_i, + input wire clk_i, + input wire wr_clk_i, + input wire rd_clk_i, + input wire wr_en_i, + input wire rd_en_i, + input wire [DATA_WIDTH-1:0] wdata, + output wire almost_full_o, + output wire prog_full_o, + output wire full_o, + output wire overflow_o, + output wire wr_ack_o, + output wire [WADDR_WIDTH :0] datacount_o, + output wire [WADDR_WIDTH :0] wr_datacount_o, + output wire empty_o, + output wire almost_empty_o, + output wire prog_empty_o, + output wire underflow_o, + output wire rd_valid_o, + output wire [RDATA_WIDTH-1:0] rdata, + output wire [RADDR_WIDTH :0] rd_datacount_o, + output wire rst_busy +); + +localparam WR_DEPTH = DEPTH; +localparam WDATA_WIDTH = DATA_WIDTH; +localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH) ? 1 : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH*8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32; + +wire wr_rst_int; +wire rd_rst_int; +wire wr_en_int; +wire rd_en_int; +wire [WADDR_WIDTH-1:0] waddr; +wire [RADDR_WIDTH-1:0] raddr; +wire wr_clk_int; +wire rd_clk_int; +wire [WADDR_WIDTH :0] wr_datacount_int; +wire [RADDR_WIDTH :0] rd_datacount_int; + +generate + if (ASYM_WIDTH_RATIO == 4) begin + if (SYNC_CLK) begin + assign wr_clk_int = clk_i; + assign rd_clk_int = clk_i; + assign datacount_o = wr_datacount_int; + assign wr_datacount_o = {(WADDR_WIDTH+1){1'b0}}; + assign rd_datacount_o = {(RADDR_WIDTH+1){1'b0}}; + end + else begin + assign wr_clk_int = wr_clk_i; + assign rd_clk_int = rd_clk_i; + assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; + assign wr_datacount_o = wr_datacount_int; + assign rd_datacount_o = rd_datacount_int; + end + end + else begin + assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; + assign wr_datacount_o = wr_datacount_int; + assign rd_datacount_o = rd_datacount_int; + if (SYNC_CLK) begin + assign wr_clk_int = clk_i; + assign rd_clk_int = clk_i; + end + else begin + assign wr_clk_int = wr_clk_i; + assign rd_clk_int = rd_clk_i; + end + end + + if (!SYNC_CLK) begin + //(* async_reg = "true" *) reg [1:0] wr_rst; + //(* async_reg = "true" *) reg [1:0] rd_rst; + // + //always @ (posedge wr_clk_int or posedge a_rst_i) begin + // if (a_rst_i) + // wr_rst <= 2'b11; + // else + // wr_rst <= {wr_rst[0],1'b0}; + //end + // + //always @ (posedge rd_clk_int or posedge a_rst_i) begin + // if (a_rst_i) + // rd_rst <= 2'b11; + // else + // rd_rst <= {rd_rst[0],1'b0}; + //end + + + if (BYPASS_RESET_SYNC) begin + assign wr_rst_int = a_wr_rst_i; + assign rd_rst_int = a_rd_rst_i; + assign rst_busy = 1'b0; + end + else begin + `IP_MODULE_NAME(efx_resetsync) #( + .ACTIVE_LOW (0) + ) efx_resetsync_wr_rst ( + .clk (wr_clk_int), + .reset (a_rst_i), + .d_o (wr_rst_int) + ); + + `IP_MODULE_NAME(efx_resetsync) #( + .ACTIVE_LOW (0) + ) efx_resetsync_rd_rst ( + .clk (rd_clk_int), + .reset (a_rst_i), + .d_o (rd_rst_int) + ); + assign rst_busy = wr_rst_int | rd_rst_int; + end + + end + else begin + //(* async_reg = "true" *) reg [1:0] a_rst; + // + //always @ (posedge clk_i or posedge a_rst_i) begin + // if (a_rst_i) + // a_rst <= 2'b11; + // else + // a_rst <= {a_rst[0],1'b0}; + //end + wire a_rst; + + `IP_MODULE_NAME(efx_resetsync) #( + .ACTIVE_LOW (0) + ) efx_resetsync_a_rst ( + .clk (clk_i), + .reset (a_rst_i), + .d_o (a_rst) + ); + + if (BYPASS_RESET_SYNC) begin + assign wr_rst_int = a_rst_i; + assign rd_rst_int = a_rst_i; + assign rst_busy = 1'b0; + end + else begin + assign wr_rst_int = a_rst; + assign rd_rst_int = a_rst; + assign rst_busy = wr_rst_int | rd_rst_int; + end + end +endgenerate + +`IP_MODULE_NAME(efx_fifo_ram) # ( + .FAMILY (FAMILY), + .WR_DEPTH (WR_DEPTH), + .RD_DEPTH (RD_DEPTH), + .WDATA_WIDTH (WDATA_WIDTH), + .RDATA_WIDTH (RDATA_WIDTH), + .WADDR_WIDTH (WADDR_WIDTH), + .RADDR_WIDTH (RADDR_WIDTH), + .OUTPUT_REG (OUTPUT_REG), + .RAM_MUX_RATIO (RAM_MUX_RATIO), + .ENDIANESS (ENDIANESS), + .RAM_STYLE (RAM_STYLE) +) xefx_fifo_ram ( + .wdata (wdata), + .waddr (waddr), + .raddr (raddr), + .we (wr_en_int), + .re (rd_en_int), + .wclk (wr_clk_int), + .rclk (rd_clk_int), + .rdata (rdata) +); + +`IP_MODULE_NAME(efx_fifo_ctl) # ( + .SYNC_CLK (SYNC_CLK), + .SYNC_STAGE (SYNC_STAGE), + .MODE (MODE), + .WR_DEPTH (WR_DEPTH), + .WADDR_WIDTH (WADDR_WIDTH), + .RADDR_WIDTH (RADDR_WIDTH), + .ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), + .RAM_MUX_RATIO (RAM_MUX_RATIO), + .PIPELINE_REG (PIPELINE_REG), + .ALMOST_FLAG (ALMOST_FLAG), + .PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), + .PROG_FULL_ASSERT (PROG_FULL_ASSERT), + .PROG_FULL_NEGATE (PROG_FULL_NEGATE), + .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), + .PROG_EMPTY_ASSERT (PROG_EMPTY_ASSERT), + .PROG_EMPTY_NEGATE (PROG_EMPTY_NEGATE), + .OUTPUT_REG (OUTPUT_REG), + .HANDSHAKE_FLAG (HANDSHAKE_FLAG), + .OVERFLOW_PROTECT (OVERFLOW_PROTECT), + .UNDERFLOW_PROTECT (UNDERFLOW_PROTECT) +) xefx_fifo_ctl ( + .wr_rst (wr_rst_int), + .rd_rst (rd_rst_int), + .wclk (wr_clk_int), + .rclk (rd_clk_int), + .we (wr_en_i), + .re (rd_en_i), + .wr_full (full_o), + .wr_ack (wr_ack_o), + .rd_empty (empty_o), + .wr_almost_full (almost_full_o), + .rd_almost_empty (almost_empty_o), + .wr_prog_full (prog_full_o), + .rd_prog_empty (prog_empty_o), + .wr_en_int (wr_en_int), + .rd_en_int (rd_en_int), + .waddr (waddr), + .raddr (raddr), + .wr_datacount (wr_datacount_int), + .rd_datacount (rd_datacount_int), + .rd_vld (rd_valid_o), + .wr_overflow (overflow_o), + .rd_underflow (underflow_o) +); + +function integer depth2width; +input [31:0] depth; +begin : fnDepth2Width + if (depth > 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian + parameter RAM_STYLE = "block_ram" +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + always @ (posedge wclk) begin + for (i=0; i 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_resetsync) #( + parameter ASYNC_STAGE = 2, + parameter ACTIVE_LOW = 1 +) ( + input wire clk, + input wire reset, + output wire d_o +); + + +generate + if (ACTIVE_LOW == 1) begin: active_low + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (1), + .RST_VALUE (0) + ) efx_resetsync_active_low ( + .clk (clk), + .reset_n (reset), + .d_i (1'b1), + .d_o (d_o) + ); + end + else begin: active_high + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (0), + .RST_VALUE (1) + ) efx_resetsync_active_high ( + .clk (clk), + .reset_n (reset), + .d_i (1'b0), + .d_o (d_o) + ); + end +endgenerate + +endmodule + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_asyncreg) #( + parameter ASYNC_STAGE = 2, + parameter WIDTH = 4, + parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset + parameter RST_VALUE = 0, + parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance +) ( + input wire clk, + input wire reset_n, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + + + + + + + + + + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect author = "author-a" , author_info = "author-a-details" +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V +o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE +El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY +kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc +/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 +uYJaS5tuGEuFInBHa7oO8g== +`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 +fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa +rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq +PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL +DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w +K3OoKmk3zFeArSsql8B4/Q== +`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 ) +`pragma protect key_block +RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M +GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l +6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI= +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf +RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk +1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw +Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz +eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0 +2HflB1HYKxojQCcZU7qUgQ== +`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx +Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB +rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr +XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD +e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod +B2Zpo2FQ//YDRSAaEa9ksQ== +`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze +vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 +ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 +06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP +fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN +ZoPzFCMjGk5ZmMyIlytNCw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 ) +`pragma protect data_block +0d33xo/2RnBYy8BD6jq1J42m9u/75PA0owNvxlnr0TDOq7sF8XT6xouctVD1XQW2 +Ylwj0urY+dCJZku0aGRpcvb3H/nTlKVdEZOEl4QqB1gNGz/3mz75A3eudu5zgHEr +MaagjyQfDnoIqLWi1r5uTZrlS298IvNcGAJ+xXzpmkFmfG4Tk/5Jf2GPAPVtjREI +01kt8Go4CL1WNxBKcwm0xCiCchxvZ2oEtpERiC+7LUalgTJapIVoLFpvFv98229k +egvgF1KHNj0rAKedSG2Xo58TyA4iZXJJDdtgCxiKgu3Rimjno7l+ekApwmvx8n+p +yHkRGqetWfRhyE4A5q03RzOeSdA6NbCqijB3NPw/p58brAbA35rrjYpGIZXtZ4mU +De3As8VtD64nS2PRuf4/a2lIcDbwMjNTfMpN7iJfVBJ0/48tLHdetx592TLXenkF +GvAZ2yxoyBYzKctj4Keo+19Xp1UjVd3fr2MR3A7nmxLRKDA+upDxQ7ql8+pR7Moh +0b53/4Ri3Mkl+7EC1KXJNt2VbkZmcT7OAFIoPpibmcXS2R6DNVrhSKzfc2+TRM9r +mwRrJy9/R5RR+WGfw1S57Ho3wBPf4belj+Tfd7yhnwOVRXkTMq5M1BiigrGeeQ3q +z/hc1Kg8b/R+g7lnU0pqASnExPQW/DIMfH1RX75U68CAgaBAH22Vcbkoibp8sxyO +g18LefEh48UffnbpCKyv7SQ3LAdj+YO+KvvXHj1eW+CH7GA2lC5vt2be5Ah2/13H +bCeZ+srG6r7wmafy9MNNh8AgjUfZWwMnuJdCIcHTOfAncCd2B0T1Oza4VIkvnSl5 +60V34JXkfrGsNuHxwCF/sRSBbZUSpqig4ZGYHjOHldx2OANZQeUvLES3fwScYY5D +7SpR4ofVxIB/ev/+RXzvC3MNk1N0GT4F1XwokeeQIr/ilRETe/pFvEKttvviZ7uJ +uEVblS2v61DMXEgDavkbA0WdhMChPulwDvZtisWT4hCKRxfuBvNBtz0wH/WgRoX3 +aipWvPJG3G0xvO0u0EQVNdcxE+LZ7vyGF5HWEwKdQYDyhH+yVDeG+M/b08dU2aq4 +sG7dyygyVnzVbk2Lf0nCkGqKkUZUr05Zim0Wcflkhkqy348SOZ3xmEGuYAkzelLV +feQ+0ScsscFL5Cq4ETfFrN8GO8M5kkBN2ELs1MQecPRsgMCh0hcvd8IQrJTybQPW +aqwp9mgnFvS8AJ1ct+XgrAt8zgVnhaZGS9TKa6OWbr0U+SD5m+/pXjNsZA2dni6b +85/PmQeWeAarE/+EaJn/hlP6y3x3R3ItU8Itf6SB50LZ17LAhIRSIYsa7LBBNWOk +ngFHcGBCJnqTJv3hdVqa9cYipZ98XCa8dqrtAM5Rkxwd6H8KxXA+B+PWEz/cQWlb +szi9u5ufmyaJp6PWhklroQkPJEorUtF96X763itgtlAMHfkZglkElUD/gPlkXLtl +yquUmHqPK5D2pJDq0Q0jromE2yrr9fl3OI+eBehd2YBUivGKeaDFkPx7HbzWp9ok +9bT55H8VKYyF1awcjNND+WcXzm2WfvZHBDUJkRm7dnOQRvcX2RxlPRZSzAA3irVn +GFbHXD0RYn/dUR7Vy4kU68P5S5q4bUxD5vmUCN9vDoCivY7WCnlQCHQs3+iFblzP +A636C3dNQMSw0pjDisiZB63VczY8bivFh3cO82inNw5r2IZjvMB9XPhc4FHuIpfR +F7ptW0TUnO1MSDcZvCnjUfVSnHN22l2FM/P5oI1SbG3W+8YmxBvto8jwpES4ohOQ +YSECrvWkLklq68FVTzB7Tvg3JLdSy3TEKBuZE/ot0w/SXusFovOwd4aeiNDAmzwl +fQuCYHuJ0UKLaVNVAO4mw91PJODKCk2NYTr0ghOLovOXiMhUYtXZ+wFchXVkQKDI +B8BXjM7P+blhoOFA6AhRuCX4gZn0dP6m99qnyBJoxf1/FyfJXuklnPll93amUYUx +MzxNNTf7F08tnKQ8pTOk2mfFZnhA2MFn4XQ9FaGvtUrlJI8bvJTWiZFMF0eOJdIw +kzYOXEzKBjIdWW4rtTZmQJb7AOrznUpYdgTAPip/DQx6cg1+tZAVwhZPCjCsb5wa +em5hMtISQKDc92QrlU5O74OXe7641fzFRcKqy9AzwhZl+tmHk1uvpDkpsYiMa7Rk +YrbIjsKQV36PTqYPvxq1EiwYF8PMRf9FG8JZk85EZdM6QEGuehDHqFcZ+SlUb7/e +ji6GgjKxcZwaRREGKSOslcscHS6QNuGCF3iInqNCT4V2l7nboWOefMT2f1kmQOdE +szTFg563SQ8pu7ok3T3XNqUDi5ulvF+XGHDhcQ2hTkZ+xQ8dHFAWZdgzEGMXF2Lw +jU+ZRA2JULfjxOMIU2j9f+aGWmFx2PELMA5K5uOWYUQG2Fn04p1D6u8MEe7fIPeI +k7KH8j/Tumj+kG4t/lCrme6VM9u6A2NGddX1yH1NCejfophy3UWJg9wL/dNxzf6t +vXdm3rGPdZPWFgSIuGlmT03QZmWGPbs8qvkkUVAL37kMJP2r4L+PI00ZxbX8V5jp +GgYN1Rh+NSOwAcUEFCViRhFYC+Gi5eZ6AF6XDSU6qfjGsUKqJ9yrNx0Km6+SjpAK +7Zxblp7vweFVkJ7IESoFeB+vP8JNeoidbBPGEWo+2V08PgfGgjPEAA6pjj8uc0jC +SDFZ0sVrzvc66PZ5FxbI4g+VuXPJgyJsnQ/eHhPVTVTP3/oGMRVktNiJrkJYxAW7 +Sa/EJMjfXX+rMIWG5ssWLT6WfrojlHduEqJ9hJr24RZy514HHF8SMPRBLD6l1wd5 +07U/ChjFdy5qHn5Ce+lanjxnoxgvCsF3lMqoZ7e2bfzXakj7CxahwqRt6yeU0Q+/ +a8tvIJgHfdtOPw/r6HnSrzpdWzTx2e6/MEryHZqpMN63Lhakpjw1L7u3FD/rW40b +LGajigQ7Ql+cZmP7wYl+uSmTFIS6ZgXOc1ibb7yYxJwpeixPHL1iu5ltvriRiTZ6 +DMbbOjNpPuL7ie3AwgmwXwnpnTL6k/Rj2+ma3B7ImODBMkC4SLtTc0ynCcPAFZKA +Xh78wUAgt1T5Nm4XR555DBO7zPHX9rZzMLil4/j0RMDwn1gitmP2PSNFWsrXJG8p +C46kfpdqoM3Yf6HySlhsith6GW41sMF6imUXwahQQRw240HLW3N876LDe6bjTmgN +eIC7y/4NZk7OmpmP8udAEH+UsNfSGtKA8959AoJDr43XsWkOfccNWstu4sTXA5+w +pCALypmBMdholEsrW9DgsIgbgf2pcOAC9+mAjld+yyQ+UNdKRbmtRDHTztGmcVvw +Szip4YUuTM1tPzReucfm38gVFT7eo1qFQg/FJ4VgeYab7ku5OHuwZQmKyzng/t0U +A1lquVENVYQEIotBiOC7jQ1YTkTasGN4xoFgFTyKLFPyk8bl2/anzr1Fx0ieVGCx +2ipzG2JzIQf/FlHXaYrgkWiF817amty+KZp4/dCJtvDXxzOZKnBTVcjHXpqR1Ik+ +tdV+k+21tXZxP0rkG0yi4//2c5UiWGb0UegpemqutykLuT9tGjsqMuc5DaDH/8zk +wLTVfODT+HqN1/ZLqfq9VoAF5m/ujnPNt3wZcsjsAyBD153rW4Q2yVYMat0sFQN6 +XbNAeNBJZlO/aE1PfKBcSDFkJkPqRxlgdiE5B83/w1MP6Z4qwz7LJ8yTYM22xwRo +LIYpKq52yYMhJm42YeQxbBRTx0MyubCb+ompEVBF28Eh0vE98UAZj7t1szSweg99 +Wq6/4kxR2SQj8rFo2wrZe7ngsDmbIrMk2SinS6WmV4Mj+MBbPlmiuwB6NUV04Id1 +9enBBsJIfWt+PZJXyWkOoG/fOVBUxCY+CMCiab0qQ1EVdhggrdI30BgFqcLjfyD6 +/h5AqIzMGWrhWnap8WDEh1Ah6K9f2oCESSXO751sV5eK8jgl63FJMIVsnjVejxrl +Qa7PCXP3BO6Cnv896NBzAsddPq/AYBLHIC6eX3sTtOxTx52NsmJzoyUSJcAoA/QS +leHU1bLA2z+HGfMrkSzsuvXafmqr3B+PHfWdxrYzTxmVhMBPX/FvEU/gfxXGa6kj +niZYGue/Rk+zXL65ENgPwxiz0mm7QyQ6eMBMRovm6MGyIl/8obkOPygH+lhc+bgR +SNWLmxqjR2YABrKsUgCITQ6GK7VmVR3wOOwbZs+YW/0Yj2yzg7ESjaeqI40/OQFD +Ft2IHaURJPk6jl5vRrcCc0J0GCy7CK0BU14n+Nxfl2+CFRe4efoqZry/CmY2+S4M +p9OqgjUzHGSIbNRAXHf44nIAUjWYvijzzLSj9A7WY3TpYxgtqU8Wbf7SbWmw8RJV +pAYDHGmwHa8fL4Y9xEFF/WqmqWSL3g146i41MKWKY7lchvnWtc6yOgk+0geVFOpe +9BLs4TehFA/SueFC99S0Cxcxc0KMWXOKm0I3bI1CAlLje7wUcdI/pki33iqBLJlL +T2vz8ptPqfgAxDW0ZEvEYY/jfB+jCO0MKT7XK/LZNYSuEke3Y3CeuwZ/5IWkDcwy +7BArmDy7Hpw88le9ODL94mS1fUB8jsBaazeiXniZPNZjBkugt/ZAf4XYuoaGVPAM +DnRd8GW5eiDHFCEB42lpg9n7Ak8cXsSSlODCHeay2VtcQP1DEgwWdI5XdXE879gI +8lLU9bH2MfsxI2mNWCMv5immaioZJDorIVzyMGvIn3OcgqmhTU1owINUJf+Hm8Q7 +JfJq4m6t0J5eoKQH57uSGFkWRZ3dtp5QL3d5bBOMmorXUBzdrLt8wurvNke29bHD +UQdmANjayV8drYWAccZdPWyi9jNC/K31BTDI6RCpZdV3Wr5scOZdXWrl961jirm1 +g/2MGKxriuH2F4MRIh2vp3uS8PLbj4cHJv+5+LtLgs0lpdEMYAvJKDACRg68tDhY +XsF9lhHpcF5+tANOawRtnSvy/rlLn+A3wi7v8tnTZcLkocJ51c+nK5/Ij0YgUrA0 +eLrKNlJM78stswPWkvpBlAJ+G3D4Cw6P3XcJWrLyV3u79jf9PRJZmxMU/COGTmgQ +PJdXp90O3u2Pjdwhp4VdtBK2d/jTpk59j8xbQBavf5flZ+PzoLpd8NSt6GdPVJ5r +uVWvNy14pJXUsn+Tgxj+9Wp3vm5mofWtJAkEgr/Rfp7AVLLShJSd6vsbT7F2+TS/ +OMDv0XH92v1G4tqJ0rbxS1TnxX61+1sfjKlfIQdFR9gxLy71Tb705LQHBAw8vmSx +X6Uv+HbtPaEqRCF+pdvGsLNI2Seo6INA/mXqNpd6VPhfQHtp3bgV+Hxnlcc9lCiI +bCZq6KG4a6sVQHIZ3pZo7PQtoAo22niHvgZFoOVnBv+bu+blmvSV6gxCPoV8rwOe +/WD7YikHE7WVSq1SHtTIcbPv+K+1NKqZIiSCS2qDfJLgI7vH4zjIqibDhzGZTeKV +Km234SSlJ1OL4WQ5FtsxjednjUIAKqVe1auDiTzAKY28dwUkwGN/XXQ+EjrmxQuL +qIAT3WP49EeM+CQCp3D6Vxzm7Picq+RtwtbAXnnSQtvPcaSprODI089a0iR46Pp/ +4DLMUOLS+01HozXF1589YdqYep05No/Fp4eP2RdQxicYxK8d/OcvG7E8F1URVmAa +XdZxVa9caM3xYMWDZaiaOo6IZ+YM5VeZ4KxUblS1L1IlOnGOOZ3AiaLsHOh55ryc +Ei7EaFpheCmlTJyxUg8TdA== +`pragma protect end_protected + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ctl) # ( + parameter SYNC_CLK = 1, + parameter SYNC_STAGE = 2, + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter ASYM_WIDTH_RATIO = 4, + parameter RAM_MUX_RATIO = 1, + parameter PIPELINE_REG = 1, + parameter ALMOST_FLAG = 1, + parameter PROGRAMMABLE_FULL = "NONE", + parameter PROG_FULL_ASSERT = 0, + parameter PROG_FULL_NEGATE = 0, + parameter PROGRAMMABLE_EMPTY = "NONE", + parameter PROG_EMPTY_ASSERT = 0, + parameter PROG_EMPTY_NEGATE = 0, + parameter OUTPUT_REG = 0, + parameter HANDSHAKE_FLAG = 1, + parameter OVERFLOW_PROTECT = 0, + parameter UNDERFLOW_PROTECT = 0 +)( + input wire wr_rst, + input wire rd_rst, + input wire wclk, + input wire rclk, + input wire we, + input wire re, + output wire wr_full, + output reg wr_ack, + output wire wr_almost_full, + output wire rd_empty, + output wire rd_almost_empty, + output wire wr_prog_full, + output wire rd_prog_empty, + output wire wr_en_int, + output wire rd_en_int, + output wire [WADDR_WIDTH-1:0] waddr, + output wire [RADDR_WIDTH-1:0] raddr, + output wire [WADDR_WIDTH:0] wr_datacount, + output wire [RADDR_WIDTH:0] rd_datacount, + output wire rd_vld, + output reg wr_overflow, + output reg rd_underflow +); + +reg [WADDR_WIDTH:0] waddr_cntr; +reg [WADDR_WIDTH:0] waddr_cntr_r; +reg [RADDR_WIDTH:0] raddr_cntr; +reg rd_valid; + +wire [WADDR_WIDTH:0] waddr_int; +wire [RADDR_WIDTH:0] raddr_int; +wire rd_empty_int; +wire [WADDR_WIDTH:0] wr_datacount_int; +wire [RADDR_WIDTH:0] rd_datacount_int; + +assign waddr = waddr_cntr[WADDR_WIDTH-1:0]; +// NIC +wire [RADDR_WIDTH:0] ram_raddr; +assign raddr = (MODE == "FWFT") ? ram_raddr[RADDR_WIDTH-1:0] : raddr_cntr[RADDR_WIDTH-1:0]; +//assign raddr = raddr_cntr[RADDR_WIDTH-1:0]; +//assign wr_en_int = we & ~wr_full; +assign wr_en_int = OVERFLOW_PROTECT ? we & ~wr_full : we; + +assign wr_datacount = wr_datacount_int; +assign rd_datacount = ASYM_WIDTH_RATIO == 4 && SYNC_CLK ? wr_datacount_int : rd_datacount_int; + + +generate + if (MODE == "FWFT") begin + // NIC + //assign rd_en_int = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int); + //assign rd_empty = rd_empty_fwft; + + assign rd_en_int = 1'b1; + //assign rd_empty = rd_empty_int; + + //always @ (posedge rclk or posedge rd_rst) begin + // if (rd_rst) begin + // init_set <= 1'b1; + // end + // else if (~init_set & rd_empty) begin + // init_set <= 1'b1; + // end + // else if (~rd_empty_int) begin + // init_set <= 1'b0; + // end + // else if (rd_empty) begin + // init_set <= 1'b1; + // end + //end + // NIC + //always @ (posedge rclk or posedge rd_rst) begin + // if (rd_rst) begin + // rd_empty_fwft <= 1'b1; + // end + // else if (rd_en_int) begin + // rd_empty_fwft <= 1'b0; + // end + // else if (re) begin + // rd_empty_fwft <= 1'b1; + // end + //end + + //if (FAMILY == "TRION") begin + if (OUTPUT_REG) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid <= 1'b0; + end + else begin + rd_valid <= ~rd_empty; + end + end + assign rd_vld = rd_valid; + end + else begin + assign rd_vld = ~rd_empty; + end + + assign rd_empty = rd_empty_int; + end + else begin + assign rd_en_int = UNDERFLOW_PROTECT ? re & ~rd_empty_int : re; + assign rd_empty = rd_empty_int; + + if (OUTPUT_REG) begin + reg rd_valid_r; + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid_r <= 'h0; + rd_valid <= 'h0; + end + else begin + {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int}; + end + end + assign rd_vld = rd_valid; + end + else begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid <= 'h0; + end + else begin + rd_valid <= rd_en_int; + end + end + assign rd_vld = rd_valid; + end + end + + if (ALMOST_FLAG) begin + assign wr_almost_full = wr_datacount >= WR_DEPTH-1; + assign rd_almost_empty = rd_datacount <= 'd1; + end + else begin + assign wr_almost_full = 1'b0; + assign rd_almost_empty = 1'b0; + end + + if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + // NIC + //wr_ack <= wr_en_int & ~wr_overflow; + wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; + end + end + end + + if (OVERFLOW_PROTECT) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else begin + wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; + end + end + end + + if (UNDERFLOW_PROTECT) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else begin + rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + // NIC + else if (ASYM_WIDTH_RATIO == 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - raddr_int; + assign rd_datacount_int = waddr_int - raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + // NIC + //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_r <= 'h0; + end + else begin + waddr_cntr_r <= waddr_cntr; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + end + // NIC + //else if (rd_en_int) begin + else begin + //raddr_cntr <= raddr_cntr + 1'b1; + //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); + raddr_cntr <= ram_raddr; + end +end +// NIC +assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); + + +generate + if (SYNC_CLK) begin : sync_clk + if (MODE == "FWFT") begin + assign waddr_int = waddr_cntr_r; + assign raddr_int = raddr_cntr; + end + else begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr; + end + end + else begin : async_clk + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian + parameter RAM_STYLE = "block_ram" +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + always @ (posedge wclk) begin + for (i=0; i 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_resetsync) #( + parameter ASYNC_STAGE = 2, + parameter ACTIVE_LOW = 1 +) ( + input wire clk, + input wire reset, + output wire d_o +); + + +generate + if (ACTIVE_LOW == 1) begin: active_low + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (1), + .RST_VALUE (0) + ) efx_resetsync_active_low ( + .clk (clk), + .reset_n (reset), + .d_i (1'b1), + .d_o (d_o) + ); + end + else begin: active_high + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (0), + .RST_VALUE (1) + ) efx_resetsync_active_high ( + .clk (clk), + .reset_n (reset), + .d_i (1'b0), + .d_o (d_o) + ); + end +endgenerate + +endmodule + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_asyncreg) #( + parameter ASYNC_STAGE = 2, + parameter WIDTH = 4, + parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset + parameter RST_VALUE = 0, + parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance +) ( + input wire clk, + input wire reset_n, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + + + + + + + + + + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect author = "author-a" , author_info = "author-a-details" +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V +o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE +El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY +kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc +/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 +uYJaS5tuGEuFInBHa7oO8g== +`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 +fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa +rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq +PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL +DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w +K3OoKmk3zFeArSsql8B4/Q== +`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 ) +`pragma protect key_block +RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M +GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l +6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI= +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf +RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk +1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw +Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz +eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0 +2HflB1HYKxojQCcZU7qUgQ== +`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx +Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB +rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr +XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD +e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod +B2Zpo2FQ//YDRSAaEa9ksQ== +`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze +vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 +ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 +06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP +fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN +ZoPzFCMjGk5ZmMyIlytNCw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 ) +`pragma protect data_block +0d33xo/2RnBYy8BD6jq1J42m9u/75PA0owNvxlnr0TDOq7sF8XT6xouctVD1XQW2 +Ylwj0urY+dCJZku0aGRpcvb3H/nTlKVdEZOEl4QqB1gNGz/3mz75A3eudu5zgHEr +MaagjyQfDnoIqLWi1r5uTZrlS298IvNcGAJ+xXzpmkFmfG4Tk/5Jf2GPAPVtjREI +01kt8Go4CL1WNxBKcwm0xCiCchxvZ2oEtpERiC+7LUalgTJapIVoLFpvFv98229k +egvgF1KHNj0rAKedSG2Xo58TyA4iZXJJDdtgCxiKgu3Rimjno7l+ekApwmvx8n+p +yHkRGqetWfRhyE4A5q03RzOeSdA6NbCqijB3NPw/p58brAbA35rrjYpGIZXtZ4mU +De3As8VtD64nS2PRuf4/a2lIcDbwMjNTfMpN7iJfVBJ0/48tLHdetx592TLXenkF +GvAZ2yxoyBYzKctj4Keo+19Xp1UjVd3fr2MR3A7nmxLRKDA+upDxQ7ql8+pR7Moh +0b53/4Ri3Mkl+7EC1KXJNt2VbkZmcT7OAFIoPpibmcXS2R6DNVrhSKzfc2+TRM9r +mwRrJy9/R5RR+WGfw1S57Ho3wBPf4belj+Tfd7yhnwOVRXkTMq5M1BiigrGeeQ3q +z/hc1Kg8b/R+g7lnU0pqASnExPQW/DIMfH1RX75U68CAgaBAH22Vcbkoibp8sxyO +g18LefEh48UffnbpCKyv7SQ3LAdj+YO+KvvXHj1eW+CH7GA2lC5vt2be5Ah2/13H +bCeZ+srG6r7wmafy9MNNh8AgjUfZWwMnuJdCIcHTOfAncCd2B0T1Oza4VIkvnSl5 +60V34JXkfrGsNuHxwCF/sRSBbZUSpqig4ZGYHjOHldx2OANZQeUvLES3fwScYY5D +7SpR4ofVxIB/ev/+RXzvC3MNk1N0GT4F1XwokeeQIr/ilRETe/pFvEKttvviZ7uJ +uEVblS2v61DMXEgDavkbA0WdhMChPulwDvZtisWT4hCKRxfuBvNBtz0wH/WgRoX3 +aipWvPJG3G0xvO0u0EQVNdcxE+LZ7vyGF5HWEwKdQYDyhH+yVDeG+M/b08dU2aq4 +sG7dyygyVnzVbk2Lf0nCkGqKkUZUr05Zim0Wcflkhkqy348SOZ3xmEGuYAkzelLV +feQ+0ScsscFL5Cq4ETfFrN8GO8M5kkBN2ELs1MQecPRsgMCh0hcvd8IQrJTybQPW +aqwp9mgnFvS8AJ1ct+XgrAt8zgVnhaZGS9TKa6OWbr0U+SD5m+/pXjNsZA2dni6b +85/PmQeWeAarE/+EaJn/hlP6y3x3R3ItU8Itf6SB50LZ17LAhIRSIYsa7LBBNWOk +ngFHcGBCJnqTJv3hdVqa9cYipZ98XCa8dqrtAM5Rkxwd6H8KxXA+B+PWEz/cQWlb +szi9u5ufmyaJp6PWhklroQkPJEorUtF96X763itgtlAMHfkZglkElUD/gPlkXLtl +yquUmHqPK5D2pJDq0Q0jromE2yrr9fl3OI+eBehd2YBUivGKeaDFkPx7HbzWp9ok +9bT55H8VKYyF1awcjNND+WcXzm2WfvZHBDUJkRm7dnOQRvcX2RxlPRZSzAA3irVn +GFbHXD0RYn/dUR7Vy4kU68P5S5q4bUxD5vmUCN9vDoCivY7WCnlQCHQs3+iFblzP +A636C3dNQMSw0pjDisiZB63VczY8bivFh3cO82inNw5r2IZjvMB9XPhc4FHuIpfR +F7ptW0TUnO1MSDcZvCnjUfVSnHN22l2FM/P5oI1SbG3W+8YmxBvto8jwpES4ohOQ +YSECrvWkLklq68FVTzB7Tvg3JLdSy3TEKBuZE/ot0w/SXusFovOwd4aeiNDAmzwl +fQuCYHuJ0UKLaVNVAO4mw91PJODKCk2NYTr0ghOLovOXiMhUYtXZ+wFchXVkQKDI +B8BXjM7P+blhoOFA6AhRuCX4gZn0dP6m99qnyBJoxf1/FyfJXuklnPll93amUYUx +MzxNNTf7F08tnKQ8pTOk2mfFZnhA2MFn4XQ9FaGvtUrlJI8bvJTWiZFMF0eOJdIw +kzYOXEzKBjIdWW4rtTZmQJb7AOrznUpYdgTAPip/DQx6cg1+tZAVwhZPCjCsb5wa +em5hMtISQKDc92QrlU5O74OXe7641fzFRcKqy9AzwhZl+tmHk1uvpDkpsYiMa7Rk +YrbIjsKQV36PTqYPvxq1EiwYF8PMRf9FG8JZk85EZdM6QEGuehDHqFcZ+SlUb7/e +ji6GgjKxcZwaRREGKSOslcscHS6QNuGCF3iInqNCT4V2l7nboWOefMT2f1kmQOdE +szTFg563SQ8pu7ok3T3XNqUDi5ulvF+XGHDhcQ2hTkZ+xQ8dHFAWZdgzEGMXF2Lw +jU+ZRA2JULfjxOMIU2j9f+aGWmFx2PELMA5K5uOWYUQG2Fn04p1D6u8MEe7fIPeI +k7KH8j/Tumj+kG4t/lCrme6VM9u6A2NGddX1yH1NCejfophy3UWJg9wL/dNxzf6t +vXdm3rGPdZPWFgSIuGlmT03QZmWGPbs8qvkkUVAL37kMJP2r4L+PI00ZxbX8V5jp +GgYN1Rh+NSOwAcUEFCViRhFYC+Gi5eZ6AF6XDSU6qfjGsUKqJ9yrNx0Km6+SjpAK +7Zxblp7vweFVkJ7IESoFeB+vP8JNeoidbBPGEWo+2V08PgfGgjPEAA6pjj8uc0jC +SDFZ0sVrzvc66PZ5FxbI4g+VuXPJgyJsnQ/eHhPVTVTP3/oGMRVktNiJrkJYxAW7 +Sa/EJMjfXX+rMIWG5ssWLT6WfrojlHduEqJ9hJr24RZy514HHF8SMPRBLD6l1wd5 +07U/ChjFdy5qHn5Ce+lanjxnoxgvCsF3lMqoZ7e2bfzXakj7CxahwqRt6yeU0Q+/ +a8tvIJgHfdtOPw/r6HnSrzpdWzTx2e6/MEryHZqpMN63Lhakpjw1L7u3FD/rW40b +LGajigQ7Ql+cZmP7wYl+uSmTFIS6ZgXOc1ibb7yYxJwpeixPHL1iu5ltvriRiTZ6 +DMbbOjNpPuL7ie3AwgmwXwnpnTL6k/Rj2+ma3B7ImODBMkC4SLtTc0ynCcPAFZKA +Xh78wUAgt1T5Nm4XR555DBO7zPHX9rZzMLil4/j0RMDwn1gitmP2PSNFWsrXJG8p +C46kfpdqoM3Yf6HySlhsith6GW41sMF6imUXwahQQRw240HLW3N876LDe6bjTmgN +eIC7y/4NZk7OmpmP8udAEH+UsNfSGtKA8959AoJDr43XsWkOfccNWstu4sTXA5+w +pCALypmBMdholEsrW9DgsIgbgf2pcOAC9+mAjld+yyQ+UNdKRbmtRDHTztGmcVvw +Szip4YUuTM1tPzReucfm38gVFT7eo1qFQg/FJ4VgeYab7ku5OHuwZQmKyzng/t0U +A1lquVENVYQEIotBiOC7jQ1YTkTasGN4xoFgFTyKLFPyk8bl2/anzr1Fx0ieVGCx +2ipzG2JzIQf/FlHXaYrgkWiF817amty+KZp4/dCJtvDXxzOZKnBTVcjHXpqR1Ik+ +tdV+k+21tXZxP0rkG0yi4//2c5UiWGb0UegpemqutykLuT9tGjsqMuc5DaDH/8zk +wLTVfODT+HqN1/ZLqfq9VoAF5m/ujnPNt3wZcsjsAyBD153rW4Q2yVYMat0sFQN6 +XbNAeNBJZlO/aE1PfKBcSDFkJkPqRxlgdiE5B83/w1MP6Z4qwz7LJ8yTYM22xwRo +LIYpKq52yYMhJm42YeQxbBRTx0MyubCb+ompEVBF28Eh0vE98UAZj7t1szSweg99 +Wq6/4kxR2SQj8rFo2wrZe7ngsDmbIrMk2SinS6WmV4Mj+MBbPlmiuwB6NUV04Id1 +9enBBsJIfWt+PZJXyWkOoG/fOVBUxCY+CMCiab0qQ1EVdhggrdI30BgFqcLjfyD6 +/h5AqIzMGWrhWnap8WDEh1Ah6K9f2oCESSXO751sV5eK8jgl63FJMIVsnjVejxrl +Qa7PCXP3BO6Cnv896NBzAsddPq/AYBLHIC6eX3sTtOxTx52NsmJzoyUSJcAoA/QS +leHU1bLA2z+HGfMrkSzsuvXafmqr3B+PHfWdxrYzTxmVhMBPX/FvEU/gfxXGa6kj +niZYGue/Rk+zXL65ENgPwxiz0mm7QyQ6eMBMRovm6MGyIl/8obkOPygH+lhc+bgR +SNWLmxqjR2YABrKsUgCITQ6GK7VmVR3wOOwbZs+YW/0Yj2yzg7ESjaeqI40/OQFD +Ft2IHaURJPk6jl5vRrcCc0J0GCy7CK0BU14n+Nxfl2+CFRe4efoqZry/CmY2+S4M +p9OqgjUzHGSIbNRAXHf44nIAUjWYvijzzLSj9A7WY3TpYxgtqU8Wbf7SbWmw8RJV +pAYDHGmwHa8fL4Y9xEFF/WqmqWSL3g146i41MKWKY7lchvnWtc6yOgk+0geVFOpe +9BLs4TehFA/SueFC99S0Cxcxc0KMWXOKm0I3bI1CAlLje7wUcdI/pki33iqBLJlL +T2vz8ptPqfgAxDW0ZEvEYY/jfB+jCO0MKT7XK/LZNYSuEke3Y3CeuwZ/5IWkDcwy +7BArmDy7Hpw88le9ODL94mS1fUB8jsBaazeiXniZPNZjBkugt/ZAf4XYuoaGVPAM +DnRd8GW5eiDHFCEB42lpg9n7Ak8cXsSSlODCHeay2VtcQP1DEgwWdI5XdXE879gI +8lLU9bH2MfsxI2mNWCMv5immaioZJDorIVzyMGvIn3OcgqmhTU1owINUJf+Hm8Q7 +JfJq4m6t0J5eoKQH57uSGFkWRZ3dtp5QL3d5bBOMmorXUBzdrLt8wurvNke29bHD +UQdmANjayV8drYWAccZdPWyi9jNC/K31BTDI6RCpZdV3Wr5scOZdXWrl961jirm1 +g/2MGKxriuH2F4MRIh2vp3uS8PLbj4cHJv+5+LtLgs0lpdEMYAvJKDACRg68tDhY +XsF9lhHpcF5+tANOawRtnSvy/rlLn+A3wi7v8tnTZcLkocJ51c+nK5/Ij0YgUrA0 +eLrKNlJM78stswPWkvpBlAJ+G3D4Cw6P3XcJWrLyV3u79jf9PRJZmxMU/COGTmgQ +PJdXp90O3u2Pjdwhp4VdtBK2d/jTpk59j8xbQBavf5flZ+PzoLpd8NSt6GdPVJ5r +uVWvNy14pJXUsn+Tgxj+9Wp3vm5mofWtJAkEgr/Rfp7AVLLShJSd6vsbT7F2+TS/ +OMDv0XH92v1G4tqJ0rbxS1TnxX61+1sfjKlfIQdFR9gxLy71Tb705LQHBAw8vmSx +X6Uv+HbtPaEqRCF+pdvGsLNI2Seo6INA/mXqNpd6VPhfQHtp3bgV+Hxnlcc9lCiI +bCZq6KG4a6sVQHIZ3pZo7PQtoAo22niHvgZFoOVnBv+bu+blmvSV6gxCPoV8rwOe +/WD7YikHE7WVSq1SHtTIcbPv+K+1NKqZIiSCS2qDfJLgI7vH4zjIqibDhzGZTeKV +Km234SSlJ1OL4WQ5FtsxjednjUIAKqVe1auDiTzAKY28dwUkwGN/XXQ+EjrmxQuL +qIAT3WP49EeM+CQCp3D6Vxzm7Picq+RtwtbAXnnSQtvPcaSprODI089a0iR46Pp/ +4DLMUOLS+01HozXF1589YdqYep05No/Fp4eP2RdQxicYxK8d/OcvG7E8F1URVmAa +XdZxVa9caM3xYMWDZaiaOo6IZ+YM5VeZ4KxUblS1L1IlOnGOOZ3AiaLsHOh55ryc +Ei7EaFpheCmlTJyxUg8TdA== +`pragma protect end_protected + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ctl) # ( + parameter SYNC_CLK = 1, + parameter SYNC_STAGE = 2, + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter ASYM_WIDTH_RATIO = 4, + parameter RAM_MUX_RATIO = 1, + parameter PIPELINE_REG = 1, + parameter ALMOST_FLAG = 1, + parameter PROGRAMMABLE_FULL = "NONE", + parameter PROG_FULL_ASSERT = 0, + parameter PROG_FULL_NEGATE = 0, + parameter PROGRAMMABLE_EMPTY = "NONE", + parameter PROG_EMPTY_ASSERT = 0, + parameter PROG_EMPTY_NEGATE = 0, + parameter OUTPUT_REG = 0, + parameter HANDSHAKE_FLAG = 1, + parameter OVERFLOW_PROTECT = 0, + parameter UNDERFLOW_PROTECT = 0 +)( + input wire wr_rst, + input wire rd_rst, + input wire wclk, + input wire rclk, + input wire we, + input wire re, + output wire wr_full, + output reg wr_ack, + output wire wr_almost_full, + output wire rd_empty, + output wire rd_almost_empty, + output wire wr_prog_full, + output wire rd_prog_empty, + output wire wr_en_int, + output wire rd_en_int, + output wire [WADDR_WIDTH-1:0] waddr, + output wire [RADDR_WIDTH-1:0] raddr, + output wire [WADDR_WIDTH:0] wr_datacount, + output wire [RADDR_WIDTH:0] rd_datacount, + output wire rd_vld, + output reg wr_overflow, + output reg rd_underflow +); + +reg [WADDR_WIDTH:0] waddr_cntr; +reg [WADDR_WIDTH:0] waddr_cntr_r; +reg [RADDR_WIDTH:0] raddr_cntr; +reg rd_valid; + +wire [WADDR_WIDTH:0] waddr_int; +wire [RADDR_WIDTH:0] raddr_int; +wire rd_empty_int; +wire [WADDR_WIDTH:0] wr_datacount_int; +wire [RADDR_WIDTH:0] rd_datacount_int; + +assign waddr = waddr_cntr[WADDR_WIDTH-1:0]; +// NIC +wire [RADDR_WIDTH:0] ram_raddr; +assign raddr = (MODE == "FWFT") ? ram_raddr[RADDR_WIDTH-1:0] : raddr_cntr[RADDR_WIDTH-1:0]; +//assign raddr = raddr_cntr[RADDR_WIDTH-1:0]; +//assign wr_en_int = we & ~wr_full; +assign wr_en_int = OVERFLOW_PROTECT ? we & ~wr_full : we; + +assign wr_datacount = wr_datacount_int; +assign rd_datacount = ASYM_WIDTH_RATIO == 4 && SYNC_CLK ? wr_datacount_int : rd_datacount_int; + + +generate + if (MODE == "FWFT") begin + // NIC + //assign rd_en_int = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int); + //assign rd_empty = rd_empty_fwft; + + assign rd_en_int = 1'b1; + //assign rd_empty = rd_empty_int; + + //always @ (posedge rclk or posedge rd_rst) begin + // if (rd_rst) begin + // init_set <= 1'b1; + // end + // else if (~init_set & rd_empty) begin + // init_set <= 1'b1; + // end + // else if (~rd_empty_int) begin + // init_set <= 1'b0; + // end + // else if (rd_empty) begin + // init_set <= 1'b1; + // end + //end + // NIC + //always @ (posedge rclk or posedge rd_rst) begin + // if (rd_rst) begin + // rd_empty_fwft <= 1'b1; + // end + // else if (rd_en_int) begin + // rd_empty_fwft <= 1'b0; + // end + // else if (re) begin + // rd_empty_fwft <= 1'b1; + // end + //end + + //if (FAMILY == "TRION") begin + if (OUTPUT_REG) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid <= 1'b0; + end + else begin + rd_valid <= ~rd_empty; + end + end + assign rd_vld = rd_valid; + end + else begin + assign rd_vld = ~rd_empty; + end + + assign rd_empty = rd_empty_int; + end + else begin + assign rd_en_int = UNDERFLOW_PROTECT ? re & ~rd_empty_int : re; + assign rd_empty = rd_empty_int; + + if (OUTPUT_REG) begin + reg rd_valid_r; + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid_r <= 'h0; + rd_valid <= 'h0; + end + else begin + {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int}; + end + end + assign rd_vld = rd_valid; + end + else begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid <= 'h0; + end + else begin + rd_valid <= rd_en_int; + end + end + assign rd_vld = rd_valid; + end + end + + if (ALMOST_FLAG) begin + assign wr_almost_full = wr_datacount >= WR_DEPTH-1; + assign rd_almost_empty = rd_datacount <= 'd1; + end + else begin + assign wr_almost_full = 1'b0; + assign rd_almost_empty = 1'b0; + end + + if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + // NIC + //wr_ack <= wr_en_int & ~wr_overflow; + wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; + end + end + end + + if (OVERFLOW_PROTECT) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else begin + wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; + end + end + end + + if (UNDERFLOW_PROTECT) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else begin + rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + // NIC + else if (ASYM_WIDTH_RATIO == 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - raddr_int; + assign rd_datacount_int = waddr_int - raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + // NIC + //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_r <= 'h0; + end + else begin + waddr_cntr_r <= waddr_cntr; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + end + // NIC + //else if (rd_en_int) begin + else begin + //raddr_cntr <= raddr_cntr + 1'b1; + //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); + raddr_cntr <= ram_raddr; + end +end +// NIC +assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); + + +generate + if (SYNC_CLK) begin : sync_clk + if (MODE == "FWFT") begin + assign waddr_int = waddr_cntr_r; + assign raddr_int = raddr_cntr; + end + else begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr; + end + end + else begin : async_clk + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idxP#I5B-:M0GLUND=:[=ba))NYXA03V1Rb +ZO[aCWeS/Eb3_)O27cd-WCe?DS?_FOb_fN?3-[Y^O&/I1.d.4OYe&=+Z53@0W@dG@\\<;59&LV +XWfHKXeDH^db,c(UUL;RFf<+7I=5Z^>-4K)dQ:a]S3YNM/ZRaYA3\Uc@.:g9cF9. +012@V,QDaEE2>HN#ROZ^B(7KeZ&B3A7>14Z&QXG4cg)GKEDa2N1\bK9gQA=gX1SIe6ace84TF>8U +B(TR:9E8cH=CLUc&L_R.7OLDOBAEI@bf/#:3;GBS:R]6ZTX +ME)YS7=)-?)db#7(DOPML4N;?2&_f=N+VZO1OC\L133dGN]ZS77#d[FaI_bUcA6e +fEZ0ZJF;cf5SDF[Ea[,Q?-Tf^(JdJT8[/]J(f/;]A>@9.Qc+a99F\4\4db\4W]E@@O[)-&\P0HLKY+#3>OdGeZ5Q\eDe/@) +5_F?OQEeB(3ILabGc&[EeS(2P[2c#9>NOWV&[a9@DVDBA<-fgSUA#]=eX)6d7<(, +[5E-17#bQ\&?M1a\A;T\HcSXgTF&[B;V7d#1OC_1CE^47g)MN)U04-OgSC9P/B09 +JSaFb-De;fXf:+7?R[P2X4+_WNYOVgQdLT\7@(C?UNWYb&O0]ec^-P=-6N+ZV]5e?1XcNMa6H=[e/fM:&ZR+/a2O3HDaaa5#;4ZCR(>WE=M&I(KE@O863-4Y_6B3^^b4 +V:P#I9,6ROS1@/ +4Q/91.bGSA@BJQ,07HRR&^D^8.M7^E@4HC?JW#JWf?Y#6 +0HOCZ6\WZ/B7K4Rgf+34>O#,QJM-a/Sgb&6VBH,G&,GU-VH[01?9GS^[J_BC4Nbf +^\f;J7Oa=0?B#=FY304L+3d4K?5O45F^-4O@g#UcYH03OHW4C:>H(W,_:01B8d]D +Y1X_Z\+G4LMYE\/]P3Zf0gg+NIA@UJTZTa;g3&;R7 +Y[/Y#PGUE;.0B<&((eDb+CM8LbWN;I-JN+K:4I9W?g_X7,6C8M3_BJfFc-LVPQWA +:HPIP.KUc[WLcO7(VG<2MI?ICcPa#d77a<;PUE^P>L__&?0AIAMTOK9Ze&,e0+;;eK.f:1:]/bK3L6J7#F,,@\:(\UIdDG6>[A]X+>GK&O<-]S/]?4^WaQ[-N@F&,=C(C;\9_4e(IVdb03;fQKEI)DJaCRc74\NGS_#1cTO)?C^eC->B:?AI63(gNb +e<^PAQW:/a>N(#5fE,N>gVI/fZLA\G&aUQR/G_UNVTA?aa,A/AJ8SS1<[Q77a6J\)Y,S^XJ-N@M4ZJ6 +&4Y-Ad6Fg];)Ne-g,[O03>.RL[&fGS@OSTFNFB<6>Jca4Zf#;8M&NQ-CBZMM<&&CKKBT(gPPg\CO_^NOM[FS=4A5/PMAT +CDN(4=4851G;HYA?2? +)ZPF04,5QF35J9JC&\A93,C;fg5O>SV_MT?_ZNeK,,aZZ0VG3We<#22)O,FeM5K3 +U#:&S7Xc<^T]ac7@RgO<-W67]T[TYb)PK6.I^;/(HS.;P+Vd(W0:Db0NJ\VbD]1] +Z0E4/+)&+4F&8=R?>A8H4ICZ3cca>dT0Z##VWI^bg9,e_2ARQ4cESBD:^#X8&4EF +^)(+6O#1BVAT4F1I4Q7S/)1KURg-U]@DU3,+.bC_Y<&RUOVYGa]^QS2-#/[@DA/N +U#Gb=Qg?OaP0Y8[-U.G00VE.ISMfeX;M#/&@F7JE+dZFZK,P^\L= 8'd42) begin + if ((rx_data_cnt - u_temac_ex.rx_axis_mac_tdata) != 8'd42) + rdata_mismatch <= 1'b1; + end +end + +//-----------------------------------------------------------------------------------// +// THE DUT RX +//-----------------------------------------------------------------------------------// +temac_ex u_temac_ex +( +//Globle Signals +//----pll_0 +//output wire pll_0_reset, + .clk (clk_50m ), + .clk_125m (clk_125m ), + .pll_0_locked (!Reset ), + .sw6 (), +//TEMAC PHY RGMII Interface + .rgmii_txd_HI (rgmii_txd_HI ), + .rgmii_txd_LO (rgmii_txd_LO ), + .rgmii_tx_ctl (rgmii_tx_ctl ), + .rgmii_txc_HI (rgmii_txc_HI ), + .rgmii_txc_LO (rgmii_txc_LO ), + .rgmii_rxd_HI (rgmii_rxd_HI ), + .rgmii_rxd_LO (rgmii_rxd_LO ), + .rgmii_rx_ctl (rgmii_rx_ctl ), + .rgmii_rxc (rgmii_rxc ), +//TEMAC PHY MDIO Interface + .phy_mdi (1'b0 ), + .phy_mdo ( ), + .phy_mdo_en ( ), + .phy_mdc ( ) +); + +/*----------------------- ODDR Region ----------------------------*/ +//rgmii_txc +ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE" )// "OPPOSITE_EDGE" or "SAME_EDGE" +) rgmii_txc_ddr ( + .Q (rgmii_txc ),// 1-bit DDR output + .C (clk_125m ),// 1-bit clock input + .CE (1'b1 ),// 1-bit clock enable input + .D1 (rgmii_txc_HI ),// 1-bit data input (positive edge) + .D2 (rgmii_txc_LO ),// 1-bit data input (negative edge) + .R (1'b0 ),// 1-bit reset + .S (1'b0 )// 1-bit set +); + +//-----------------------------------------------------------------------------------// +// THE Base Task +//-----------------------------------------------------------------------------------// + +//apb3 bus wr task +task apb3_wr; + input [9:0] awaddr; + input [31:0] wdata; + + begin + @(posedge clk_50m); + m_apb3_paddr <= awaddr; + m_apb3_pwrite <= 1'b1; + m_apb3_psel <= 1'b1; + m_apb3_pwdata <= wdata; + @(posedge clk_50m); + m_apb3_penable <= 1; + wait(m_apb3_pready); + @(posedge clk_50m); + m_apb3_paddr <= 0; + m_apb3_pwrite <= 0; + m_apb3_psel <= 0; + m_apb3_pwdata <= 1'b0; + m_apb3_penable <= 0; + @(posedge clk_50m); + end +endtask + +//apb3 bus rd task +task apb3_rd; + input [9:0] araddr; + + begin + @(posedge clk_50m); + m_apb3_paddr <= araddr; + m_apb3_pwrite <= 1'b0; + m_apb3_psel <= 1'b1; + @(posedge clk_50m); + m_apb3_penable <= 1; + wait(m_apb3_pready); + @(posedge clk_50m); + m_apb3_paddr <= 0; + m_apb3_pwrite <= 0; + m_apb3_psel <= 0; + m_apb3_penable <= 0; + @(posedge clk_50m); + end +endtask + +//initial task +task init_task; + begin + //initial mac_reg + tx_ena <= 1'h1; + rx_ena <= 1'h1; + xon_gen <= 1'h0; + promis_en <= 1'h0; + pad_en <= 1'h0; + crc_fwd <= 1'h0; + pause_ignore <= 1'h0; + tx_addr_ins <= 1'h0; + sw_reset <= 1'h0; + loop_ena <= 1'h0; + eth_speed[2:0] <= MAC_SPEED; + xoff_gen <= 1'h0; + cnt_reset <= 1'h0; + @(posedge clk_50m); + $display("---- Configure TSE MAC IP register setting ----"); + apb3_wr('h2*4,mac_command_config);//mac_reg command_config + + //initial ex_reg + apb3_wr('h84*4,DST_MAC_L);//ex_reg pat_dst_mac[31:0] + apb3_wr('h85*4,DST_MAC_H);//ex_reg pat_dst_mac[47:32] + apb3_wr('h86*4,SRC_MAC_L);//ex_reg pat_src_mac[31:0] + apb3_wr('h87*4,SRC_MAC_H);//ex_reg pat_src_mac[47:32] + apb3_wr('h89*4,SRC_IP);//ex_reg pat_src_ip + apb3_wr('h8a*4,DST_IP);//ex_reg pat_dst_ip + apb3_wr('h8b*4,{DST_PORT,SRC_PORT});//ex_reg pat_dst_port & pat_src_port + if(PAT_TYPE == 1'b0) + begin + apb3_wr('h81*4,32'h0);//ex_reg pat_mux_select & axi4_st_mux_select + end + else + begin + apb3_wr('h81*4,32'h2);//ex_reg pat_mux_select & axi4_st_mux_select + end + end +endtask + +//pause frame generator task +task pause_gen_task; + input [15:0] pause_quant; + + begin + apb3_wr('h6*4,pause_quant);//mac_reg pause_quant + + xoff_gen <= 1'h1; + @(posedge clk_50m); + apb3_wr('h2*4,mac_command_config);//mac_reg command_config + wait(u_temac_ex.u_tsemac.u_efx_mac1gbe.inst_tsemac.u_tsemac.u_tx_engine.u_tx_ctr.cur_state == 4'd4); + xoff_gen <= 1'h0; + @(posedge clk_50m); + apb3_wr('h2*4,mac_command_config);//mac_reg command_config + end +endtask + +task check_rdata_task; + input integer i; + input [1:0] check_error_bit; + begin + + while (rx_data_rlast == 0) @(posedge clk_125m); + + if (check_error_bit == 2'b01) begin + apb3_rd('h22*4); // read ifInErrors + if (|m_apb3_prdata == 0) begin + $display("%t - Error: Expecting MAC packet ifInErrors to go high, ifInErrors = %h", $time, m_apb3_prdata); + $fatal("FAIL: simulation fail"); + end + else begin + $display("%t - Correct MAC packet %d, received", $time, i); + end + end + else if (check_error_bit == 2'b10) begin + if (rx_data_ruser == 0) begin + $display("%t - Error: Expecting MAC packet rx_data_ruser to go high, rx_data_ruser = %h", $time, rx_data_ruser); + $fatal("FAIL: simulation fail"); + end + else begin + $display("%t - MAC packet %d is filtered", $time, i); + end + end + else begin + apb3_rd('h22*4); // read ifInErrors + if (rdata_mismatch != 0) begin + $display("%t - Error: Received data mismatch", $time); + $fatal("FAIL: simulation fail"); + end + + if (|m_apb3_prdata != 0) begin + $display("%t - Error: There is an Error in the MAC received packet, ifInErrors = %h", $time, m_apb3_prdata); + $fatal("FAIL: simulation fail"); + end + else begin + $display("%t - Correct MAC packet %d, received", $time, i); + end + end + end +endtask + +task check_udp_rdata_task; + input integer i; + input [1:0] check_error_bit; + begin + + while (rx_data_rlast == 0) @(posedge clk_125m); + + if (check_error_bit == 2'b01) begin + apb3_rd('h22*4); // read ifInErrors + if (|m_apb3_prdata == 0) begin + $display("%t - Error: Expecting UDP packet ifInErrors to go high, ifInErrors = %h", $time, m_apb3_prdata); + $fatal("FAIL: simulation fail"); + end + else begin + $display("%t - Correct UDP packet %d, received", $time, i); + end + end + else if (check_error_bit == 2'b10) begin + if (rx_data_ruser == 0) begin + $display("%t - Error: Expecting UDP packet rx_data_ruser to go high, rx_data_ruser = %h", $time, rx_data_ruser); + $fatal("FAIL: simulation fail"); + end + else begin + $display("%t - UDP packet %d is filtered", $time, i); + end + end + else begin + apb3_rd('h22*4); // read ifInErrors + if (rdata_mismatch != 0) begin + $display("%t - Error: Received data mismatch", $time); + $fatal("FAIL: simulation fail"); + end + + if (|m_apb3_prdata != 0) begin + $display("%t - Error: There is an Error in the UDP received packet, ifInErrors = %h", $time, m_apb3_prdata); + $fatal("FAIL: simulation fail"); + end + else begin + $display("%t - Correct UDP packet %d, received", $time, i); + end + end + end +endtask + +//-----------------------------------------------------------------------------------// +// THE Test Case Task +//-----------------------------------------------------------------------------------// +task test_case_1_task; + begin + apb3_wr('h81*4,32'h2);//ex_reg pat_mux_select & axi4_st_mux_select + apb3_wr('h88*4,MAC_DLEN);//ex_reg pat_mac_dlen + apb3_wr('h83*4,{16'h10,16'h3E8});//ex_reg pat_gen_ipg & pat_gen_num + apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + for (i=0; i<16'h3E8; i = i + 1) begin + check_rdata_task(i, 2'b00); + end + end +endtask + +task test_case_2_task; + begin + apb3_wr('h81*4,32'h0);//ex_reg pat_mux_select & axi4_st_mux_select + apb3_wr('h8c*4,UDP_DLEN);//ex_reg pat_udp_dlen + apb3_wr('h83*4,{16'hff,16'h3E8});//ex_reg pat_gen_ipg & pat_gen_num + apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + for (i=0; i<16'h3E8; i = i + 1) begin + check_udp_rdata_task(i, 2'b00); + end + end +endtask + +task test_case_3_task; +begin + begin // to transmit tx packet after rx pause frame finished processed + apb3_wr('h88*4,16'd100);//ex_reg pat_mac_dlen + apb3_wr('h8c*4,16'd100);//ex_reg pat_udp_dlen + apb3_wr('h83*4,{16'hf,16'h2});//ex_reg pat_gen_ipg & pat_gen_num + + //Send 2 mac frames + if(PAT_TYPE == 1'b0) + begin + apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_udp_rdata_task(0, 2'b00); + check_udp_rdata_task(1, 2'b00); + end + else + begin + apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_rdata_task(0, 2'b00); + check_rdata_task(1, 2'b00); + end + + //send 1 pause frames + pause_gen_task(16'd8); + + while (rx_data_rlast == 0) @(posedge clk_125m); + + #1000 // to have some buffer to make sure the core process rx pause frame entirely + + //Send 2 mac frames + if(PAT_TYPE == 1'b0) + begin + apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_udp_rdata_task(2, 2'b00); + check_udp_rdata_task(3, 2'b00); + end + else + begin + apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_rdata_task(2, 2'b00); + check_rdata_task(3, 2'b00); + end + end + + begin + //Send 2 mac frames + if(PAT_TYPE == 1'b0) + begin + apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_udp_rdata_task(4, 2'b00); + check_udp_rdata_task(5, 2'b00); + end + else + begin + apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_rdata_task(4, 2'b00); + check_rdata_task(5, 2'b00); + end + + //send 1 pause frames + pause_gen_task(16'd8); + + //Send 2 mac frames + if(PAT_TYPE == 1'b0) + begin + apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + // check to make sure entire pause frame is received + while (rx_data_rlast == 0) @(posedge clk_125m); + repeat(1) @(posedge clk_125m); + + check_udp_rdata_task(6, 2'b00); + check_udp_rdata_task(7, 2'b00); + end + else + begin + apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + // check to make sure entire pause frame is received + while (rx_data_rlast == 0) @(posedge clk_125m); + repeat(1) @(posedge clk_125m); + + check_rdata_task(8, 2'b00); + check_rdata_task(9, 2'b00); + end + end +end +endtask + +task test_case_4_task; + begin + apb3_wr('h83*4,{16'hf,16'h1});//ex_reg pat_gen_ipg & pat_gen_num + //Send 1 mac frames + if(PAT_TYPE == 1'b0) + begin + apb3_wr('h5*4,16'd9000+46);//mac_reg frm_length + apb3_wr('h8c*4,16'd9000);//ex_reg pat_udp_dlen + apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_udp_rdata_task(0, 2'b00); + end + else + begin + apb3_wr('h5*4,16'd9000+18);//mac_reg frm_length + apb3_wr('h88*4,16'd9000);//ex_reg pat_mac_dlen + apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_rdata_task(0, 2'b00); + end + //Send 1 mac frames + if(PAT_TYPE == 1'b0) + begin + apb3_wr('h8c*4,16'd9001);//ex_reg pat_udp_dlen + apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_udp_rdata_task(1, 2'b01); + end + else + begin + apb3_wr('h88*4,16'd9001);//ex_reg pat_mac_dlen + apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_rdata_task(1, 2'b01); + end + end +endtask + +task test_case_5_task; + begin + apb3_wr('h83*4,{16'hf,16'd20});//ex_reg pat_gen_ipg & pat_gen_num + + for (i=0; i<20; i = i + 1) begin + apb3_wr('h88*4,i);//ex_reg pat_mac_dlen + apb3_wr('h8c*4,i);//ex_reg pat_udp_dlen + + //Send 1 mac frames + if(PAT_TYPE == 1'b0) + begin + apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_udp_rdata_task(i, 2'b00); + end + else + begin + apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_rdata_task(i, 2'b00); + end + end + end +endtask + +task test_case_6_task; + begin + apb3_wr('h88*4,16'd64);//ex_reg pat_mac_dlen + apb3_wr('h8c*4,16'd64);//ex_reg pat_udp_dlen + apb3_wr('h83*4,{16'hf,16'h1});//ex_reg pat_gen_ipg & pat_gen_num + //Send 1 mac frames + if(PAT_TYPE == 1'b0) + begin + apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_udp_rdata_task(0, 2'b00); + end + else + begin + apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_rdata_task(0, 2'b00); + end + //Send 1 mac frames + if(PAT_TYPE == 1'b0) + begin + apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_udp_rdata_task(1, 2'b00); + end + else + begin + apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_rdata_task(1, 2'b00); + end + + //Send 1 mac frames + if(PAT_TYPE == 1'b0) + begin + apb3_wr('h8c*4,16'd200);//ex_reg pat_udp_dlen + apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + $display("%t Wait for rgmii_rx_ctl to go high", $time); + wait(u_temac_ex.u_tsemac.u_efx_mac1gbe.inst_tsemac.rgmii_rx_ctl_HI == 1); + repeat(20) @(posedge rgmii_rxc); + + err_ins <= 1'b1; + $display("%t - insert error", $time); + repeat(4) @(posedge rgmii_rxc); + err_ins <= 1'b0; + $display("%t - deassert error", $time); + + check_udp_rdata_task(2, 2'b01); + end + else + begin + apb3_wr('h88*4,16'd200);//ex_reg pat_mac_dlen + apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + $display("%t Wait for rgmii_rx_ctl to go high", $time); + wait(u_temac_ex.u_tsemac.u_efx_mac1gbe.inst_tsemac.rgmii_rx_ctl_HI == 1); + repeat(20) @(posedge rgmii_rxc); + + err_ins <= 1'b1; + $display("%t - insert error", $time); + repeat(4) @(posedge rgmii_rxc); + err_ins <= 1'b0; + $display("%t - deassert error", $time); + + check_rdata_task(2, 2'b01); + end + end +endtask + +task test_case_7_task; + begin + apb3_wr('h88*4,16'd64);//ex_reg pat_mac_dlen + apb3_wr('h8c*4,16'd64);//ex_reg pat_udp_dlen + apb3_wr('h83*4,{16'hf,16'h1});//ex_reg pat_gen_ipg & pat_gen_num + //Send 1 mac frames + if(PAT_TYPE == 1'b0) + begin + apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_udp_rdata_task(0, 2'b00); + end + else + begin + apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_rdata_task(0, 2'b00); + end + apb3_wr('h51*4,32'hffffffff);//mac_reg mac_addr_mask[31:0] + apb3_wr('h52*4,16'hffff);//mac_reg mac_addr_mask[47:32] + //Send 1 mac frames + if(PAT_TYPE == 1'b0) + begin + apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_udp_rdata_task(1, 2'b10); + end + else + begin + apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_rdata_task(1, 2'b10); + end + apb3_wr('h84*4,32'hffffffff);//ex_reg pat_dst_mac[31:0] + apb3_wr('h85*4,16'hffff);//ex_reg pat_dst_mac[47:32] + //Send 1 mac frames + if(PAT_TYPE == 1'b0) + begin + apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_udp_rdata_task(2, 2'b01); + end + else + begin + apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_rdata_task(2, 2'b01); + end + apb3_wr('h50*4,32'h1);//mac_reg broadcast_filter_en + //Send 1 mac frames + if(PAT_TYPE == 1'b0) + begin + apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_udp_rdata_task(3, 2'b10); + end + else + begin + apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + check_rdata_task(3, 2'b10); + end + end +endtask + +task test_case_8_task; // small packet length & small inter-gap + begin + apb3_wr('h81*4,32'h2);//ex_reg pat_mux_select & axi4_st_mux_select + apb3_wr('h88*4,MAC_DLEN);//ex_reg pat_mac_dlen + apb3_wr('h83*4,{16'd12,16'd100});//ex_reg pat_gen_ipg & pat_gen_num + apb3_wr('h82*4,32'h2);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + for (i=0; i<16'd100; i = i + 1) begin + check_rdata_task(i, 2'b00); + end + end +endtask + +task test_case_9_task; // small packet length & small inter-gap + begin + apb3_wr('h81*4,32'h0);//ex_reg pat_mux_select & axi4_st_mux_select + apb3_wr('h8c*4,UDP_DLEN);//ex_reg pat_udp_dlen + apb3_wr('h83*4,{16'd12,16'd100});//ex_reg pat_gen_ipg & pat_gen_num + apb3_wr('h82*4,32'h1);//ex_reg mac_pat_gen_en & udp_pat_gen_en + apb3_wr('h82*4,32'h0);//ex_reg mac_pat_gen_en & udp_pat_gen_en + + for (i=0; i<16'd100; i = i + 1) begin + check_udp_rdata_task(i, 2'b00); + end + end +endtask + +endmodule diff --git a/fpga/ip/gTSE/Testbench/temac_ex.v b/fpga/ip/gTSE/Testbench/temac_ex.v new file mode 100644 index 0000000..15d4a24 --- /dev/null +++ b/fpga/ip/gTSE/Testbench/temac_ex.v @@ -0,0 +1,563 @@ +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / +// / / .' / +// __/ /.' / +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* +`timescale 1 ns / 1 ns +//`include "header.v" // use JTAG hard block +module temac_ex +( +//Globle Signals +//----pll_0 +input clk, +input clk_125m, +input pll_0_locked, +input sw6, +output wire pll_rstn, + +//TEMAC PHY RGMII Interface +output wire [3:0] rgmii_txd_HI, +output wire [3:0] rgmii_txd_LO, +output wire rgmii_txc_HI, +output wire rgmii_txc_LO, +input [3:0] rgmii_rxd_HI, +input [3:0] rgmii_rxd_LO, +`ifdef TITANIUM + output wire rgmii_tx_ctl_HI, + output wire rgmii_tx_ctl_LO, + input rgmii_rx_ctl_HI, + input rgmii_rx_ctl_LO, + input mux_clk, + output [1:0] mux_clk_sw, +`else + input rgmii_rxc, + output wire rgmii_tx_ctl, + input rgmii_rx_ctl, +`endif +//TEMAC PHY Ctr Interface +output wire phy_rstn, +//hardware Jtag Interface +`ifndef SIM_MODE +`ifndef SOFT_TAP +input jtag_inst1_TCK, +input jtag_inst1_TDI, +output wire jtag_inst1_TDO, +input jtag_inst1_SEL, +input jtag_inst1_CAPTURE, +input jtag_inst1_SHIFT, +input jtag_inst1_UPDATE, +input jtag_inst1_RESET, +`else +//software Jtag Interface +input io_jtag_tms, +input io_jtag_tdi, +output wire io_jtag_tdo, +input io_jtag_tck, +`endif + +//Debug Signals +//output wire [1:0] debug_led +output wire system_uart_0_io_txd, +input system_uart_0_io_rxd, +`endif + +output system_spi_0_io_sclk_write, +output system_spi_0_io_data_0_writeEnable, +input system_spi_0_io_data_0_read, +output system_spi_0_io_data_0_write, +output system_spi_0_io_data_1_writeEnable, +input system_spi_0_io_data_1_read, +output system_spi_0_io_data_1_write, +output system_spi_0_io_ss, + +//TEMAC PHY MDIO Interface +input phy_mdi, +output wire phy_mdo, +output wire phy_mdo_en, +output wire phy_mdc +); +// Parameter Define +`include "gTSE_define.svh" + +// Register Define + +// Wire Define +wire clk_50m; +wire clk_50m_rstn; +wire mac_reset; +wire proto_reset; +wire mac_rstn; +//AXI4-Stream Interface +wire rx_axis_clk; +wire [7:0] rx_axis_mac_tdata; +wire rx_axis_mac_tvalid; +wire rx_axis_mac_tlast; +wire rx_axis_mac_tuser; +wire rx_axis_mac_tready; +wire tx_axis_clk; +wire [7:0] tx_axis_mac_tdata; +wire tx_axis_mac_tvalid; +wire tx_axis_mac_tlast; +wire tx_axis_mac_tuser; +wire tx_axis_mac_tready; +wire [7:0] udp_tx_axis_mac_tdata; +wire udp_tx_axis_mac_tvalid; +wire udp_tx_axis_mac_tlast; +wire udp_tx_axis_mac_tready; +wire [7:0] mac_tx_axis_mac_tdata; +wire mac_tx_axis_mac_tvalid; +wire mac_tx_axis_mac_tlast; +wire mac_tx_axis_mac_tready; +wire [7:0] pat_tx_axis_mac_tdata; +wire pat_tx_axis_mac_tvalid; +wire pat_tx_axis_mac_tlast; +wire pat_tx_axis_mac_tuser; +wire pat_tx_axis_mac_tready; +wire [7:0] loop_tx_axis_mac_tdata; +wire loop_tx_axis_mac_tvalid; +wire loop_tx_axis_mac_tlast; +wire loop_tx_axis_mac_tuser; +wire loop_tx_axis_mac_tready; +//RiscV APB3 Interface +wire [15:0] apb3_paddr; +wire apb3_psel; +wire apb3_penable; +wire apb3_pready; +wire apb3_pwrite; +wire [31:0] apb3_pwdata; +wire [31:0] apb3_prdata; +wire apb3_pslverror; +//Mac APB3 Interface +wire [9:0] mac_apb3_paddr; +wire mac_apb3_psel; +wire mac_apb3_penable; +wire mac_apb3_pready; +wire mac_apb3_pwrite; +wire [31:0] mac_apb3_pwdata; +wire [31:0] mac_apb3_prdata; +wire mac_apb3_pslverror; +//Ex APB3 Interface +wire [9:0] ex_apb3_paddr; +wire ex_apb3_psel; +wire ex_apb3_penable; +wire ex_apb3_pready; +wire ex_apb3_pwrite; +wire [31:0] ex_apb3_pwdata; +wire [31:0] ex_apb3_prdata; +wire ex_apb3_pslverror; +//AXI4-Lite Interface +wire [9:0] axi_awaddr; +wire axi_awvalid; +wire axi_awready; +wire [31:0] axi_wdata; +wire axi_wvalid; +wire axi_wready; +wire [1:0] axi_bresp; +wire axi_bvalid; +wire axi_bready; +wire [9:0] axi_araddr; +wire axi_arvalid; +wire axi_arready; +wire [1:0] axi_rresp; +wire [31:0] axi_rdata; +wire axi_rvalid; +wire axi_rready; +//Cfg Space Registers +wire mac_sw_rst; +wire axi4_st_mux_select; +wire pat_mux_select; +wire udp_pat_gen_en; +wire mac_pat_gen_en; +wire [15:0] pat_gen_num; +wire [15:0] pat_gen_ipg; +wire [47:0] pat_dst_mac; +wire [47:0] pat_src_mac; +wire [15:0] pat_mac_dlen; +wire [31:0] pat_src_ip; +wire [31:0] pat_dst_ip; +wire [15:0] pat_src_port; +wire [15:0] pat_dst_port; +wire [15:0] pat_udp_dlen; + +//TSE DDIO +`ifdef TITANIUM + wire rgmii_rxc; + + assign rgmii_rxc = mux_clk; +`else + wire rgmii_rx_ctl_LO; + wire rgmii_rx_ctl_HI; + wire rgmii_tx_ctl_LO; + wire rgmii_tx_ctl_HI; + + assign rgmii_tx_ctl = rgmii_tx_ctl_HI | rgmii_tx_ctl_LO ; + assign rgmii_rx_ctl_HI = rgmii_rx_ctl ; + assign rgmii_rx_ctl_LO = rgmii_rx_ctl ; +`endif +/*----------------------------------------------------------------------------------*\ + The main code +\*----------------------------------------------------------------------------------*/ +assign pll_rstn = 1; +/*----------------------- Clock Region -----------------------*/ +//In full throughput usecase, rx_axis_clk and tx_axis_clk should be set to 125Mhz or above. +//In this example design, these clocks are set to 50Mhz because the UDP/MAC pattern generator has +//high combi logic and couldn't meet timing at 125Mhz. +assign rx_axis_clk = clk;//clk_125m; +assign tx_axis_clk = clk;//clk_125m; + + +/*----------------------- Reset Region -----------------------*/ +//assign pll_0_reset = 1'b0; +assign clk_50m = clk; +assign phy_rstn = sw6; +assign clk_50m_rstn = pll_0_locked; +assign mac_reset = ~pll_0_locked; +assign proto_reset = mac_sw_rst; +assign mac_rstn = ~(mac_reset || proto_reset); + +/*----------------------- MCU Module ----------------------------*/ +`ifndef SIM_MODE +sapphire u_mcu +( +//user custom ports + //SOC + .io_systemClk (clk_50m ), + .io_asyncReset (1'b0 ), + .system_uart_0_io_txd (system_uart_0_io_txd ), + .system_uart_0_io_rxd (system_uart_0_io_rxd ), + .system_spi_0_io_sclk_write (system_spi_0_io_sclk_write ), + .system_spi_0_io_data_0_writeEnable (system_spi_0_io_data_0_writeEnable ), + .system_spi_0_io_data_0_read (system_spi_0_io_data_0_read ), + .system_spi_0_io_data_0_write (system_spi_0_io_data_0_write ), + .system_spi_0_io_data_1_writeEnable (system_spi_0_io_data_1_writeEnable ), + .system_spi_0_io_data_1_read (system_spi_0_io_data_1_read ), + .system_spi_0_io_data_1_write (system_spi_0_io_data_1_write ), + .system_spi_0_io_ss (system_spi_0_io_ss ), + .jtagCtrl_tck (jtag_inst1_TCK ), + .jtagCtrl_tdi (jtag_inst1_TDI ), + .jtagCtrl_tdo (jtag_inst1_TDO ), + .jtagCtrl_enable (jtag_inst1_SEL ), + .jtagCtrl_capture (jtag_inst1_CAPTURE ), + .jtagCtrl_shift (jtag_inst1_SHIFT ), + .jtagCtrl_update (jtag_inst1_UPDATE ), + .jtagCtrl_reset (jtag_inst1_RESET ), +//APB3 Master Interface + .io_apbSlave_0_PADDR (apb3_paddr ), + .io_apbSlave_0_PSEL (apb3_psel ), + .io_apbSlave_0_PENABLE (apb3_penable ), + .io_apbSlave_0_PREADY (apb3_pready ), + .io_apbSlave_0_PWRITE (apb3_pwrite ), + .io_apbSlave_0_PWDATA (apb3_pwdata ), + .io_apbSlave_0_PRDATA (apb3_prdata ), + .io_apbSlave_0_PSLVERROR (apb3_pslverror ) +); +`endif + +assign apb3_pready = (apb3_paddr[9] == 1'b0) ? mac_apb3_pready : ex_apb3_pready; +assign apb3_prdata = (apb3_paddr[9] == 1'b0) ? mac_apb3_prdata : ex_apb3_prdata; +assign apb3_pslverror = (apb3_paddr[9] == 1'b0) ? mac_apb3_pslverror : ex_apb3_pslverror; + +assign mac_apb3_paddr = apb3_paddr[9:0]; +assign mac_apb3_psel = (apb3_paddr[9] == 1'b0) ? apb3_psel : 1'b0; +assign mac_apb3_penable = apb3_penable; +assign mac_apb3_pwrite = apb3_pwrite; +assign mac_apb3_pwdata = apb3_pwdata; + +assign ex_apb3_paddr = apb3_paddr[9:0]; +assign ex_apb3_psel = (apb3_paddr[9] == 1'b1) ? apb3_psel : 1'b0; +assign ex_apb3_penable = apb3_penable; +assign ex_apb3_pwrite = apb3_pwrite; +assign ex_apb3_pwdata = apb3_pwdata; + +apb3_2_axi4_lite#( + .ADDR_WTH (10 ) +) +u_apb3_2_axi4_lite +( +//Globle Signals + .clk (clk_50m ), + .rstn (clk_50m_rstn ), +//APB3 Slave Interface + .s_apb3_paddr (mac_apb3_paddr ), + .s_apb3_psel (mac_apb3_psel ), + .s_apb3_penable (mac_apb3_penable ), + .s_apb3_pready (mac_apb3_pready ), + .s_apb3_pwrite (mac_apb3_pwrite ), + .s_apb3_pwdata (mac_apb3_pwdata ), + .s_apb3_prdata (mac_apb3_prdata ), + .s_apb3_pslverror (mac_apb3_pslverror ), +//AXI4-Lite Master Interface + .m_axi_awaddr (axi_awaddr ), + .m_axi_awvalid (axi_awvalid ), + .m_axi_awready (axi_awready ), + .m_axi_wdata (axi_wdata ), + .m_axi_wvalid (axi_wvalid ), + .m_axi_wready (axi_wready ), + .m_axi_bresp (axi_bresp ), + .m_axi_bvalid (axi_bvalid ), + .m_axi_bready (axi_bready ), + .m_axi_araddr (axi_araddr ), + .m_axi_arvalid (axi_arvalid ), + .m_axi_arready (axi_arready ), + .m_axi_rresp (axi_rresp ), + .m_axi_rdata (axi_rdata ), + .m_axi_rvalid (axi_rvalid ), + .m_axi_rready (axi_rready ) +); + +reg_apb3#( + .ADDR_WTH (10 ) +) +u_reg_apb3 +( +//Globle Signals +// +//APB3 Slave Interface + .s_apb3_clk (clk_50m ), + .s_apb3_rstn (clk_50m_rstn ), + .s_apb3_paddr (ex_apb3_paddr ), + .s_apb3_psel (ex_apb3_psel ), + .s_apb3_penable (ex_apb3_penable ), + .s_apb3_pready (ex_apb3_pready ), + .s_apb3_pwrite (ex_apb3_pwrite ), + .s_apb3_pwdata (ex_apb3_pwdata ), + .s_apb3_prdata (ex_apb3_prdata ), + .s_apb3_pslverror (ex_apb3_pslverror ), +//Cfg Space Registers +//--Example Registers Field + .mac_sw_rst (mac_sw_rst ), + .axi4_st_mux_select (axi4_st_mux_select ), + .pat_mux_select (pat_mux_select ), + .udp_pat_gen_en (udp_pat_gen_en ), + .mac_pat_gen_en (mac_pat_gen_en ), + .pat_gen_num (pat_gen_num ), + .pat_gen_ipg (pat_gen_ipg ), + .pat_dst_mac (pat_dst_mac ), + .pat_src_mac (pat_src_mac ), + .pat_mac_dlen (pat_mac_dlen ), + .pat_src_ip (pat_src_ip ), + .pat_dst_ip (pat_dst_ip ), + .pat_src_port (pat_src_port ), + .pat_dst_port (pat_dst_port ), + .pat_udp_dlen (pat_udp_dlen ), + .clkmux_sel (mux_clk_sw ) +); + +//generate if (PATTERN_TYPE == 0) begin //UDP +// +//assign mac_tx_axis_mac_tdata = 8'h0; +//assign mac_tx_axis_mac_tvalid = 1'b0; +//assign mac_tx_axis_mac_tlast = 1'b0; + +/*----------------------- The Ethernet Pattern Module -----------------------*/ +udp_pat_gen u_udp_pat_gen +( +//Globle Signals + .clk (tx_axis_clk ), + .rstn (mac_rstn ), +//Control Interface + .pat_gen_en (udp_pat_gen_en ), + .pat_gen_num (pat_gen_num ), + .pat_gen_ipg (pat_gen_ipg ), +//MAC Protocol Signals + .dst_mac (pat_dst_mac ), + .src_mac (pat_src_mac ), +//IP Protocol Signals + .src_ip (pat_src_ip ), + .dst_ip (pat_dst_ip ), +//UDP Protocol Signals + .src_port (pat_src_port ), + .dst_port (pat_dst_port ), + .udp_dlen (pat_udp_dlen ), +//AXI4-Stream Interface + .rclk (rx_axis_clk ), + .rrstn (mac_rstn ), + .rdata (rx_axis_mac_tdata ), + .rvalid (rx_axis_mac_tvalid ), + .rlast (rx_axis_mac_tlast ), + .tdata (udp_tx_axis_mac_tdata ), + .tvalid (udp_tx_axis_mac_tvalid ), + .tlast (udp_tx_axis_mac_tlast ), + .tready (udp_tx_axis_mac_tready ) +); +//end +//else begin //MAC +// +//assign udp_tx_axis_mac_tdata = 8'h0; +//assign udp_tx_axis_mac_tvalid = 1'b0; +//assign udp_tx_axis_mac_tlast = 1'b0; + +mac_pat_gen u_mac_pat_gen +( +//Globle Signals + .clk (tx_axis_clk ), + .rstn (mac_rstn ), +//Control Interface + .pat_gen_en (mac_pat_gen_en ), + .pat_gen_num (pat_gen_num ), + .pat_gen_ipg (pat_gen_ipg ), +//MAC Protocol Signals + .dst_mac (pat_dst_mac ), + .src_mac (pat_src_mac ), + .mac_dlen (pat_mac_dlen ), +//AXI4-Stream Interface + .rclk (rx_axis_clk ), + .rrstn (mac_rstn ), + .rdata (rx_axis_mac_tdata ), + .rvalid (rx_axis_mac_tvalid ), + .rlast (rx_axis_mac_tlast ), + .tdata (mac_tx_axis_mac_tdata ), + .tvalid (mac_tx_axis_mac_tvalid ), + .tlast (mac_tx_axis_mac_tlast ), + .tready (mac_tx_axis_mac_tready ) +); +//end +//endgenerate + +axi4_st_mux u_pat_mux +( +//Globle Signals + .mux_select (pat_mux_select ),//0:udp pat; 1:mac pat; +//Mux In 0 Interface + .tdata0 (udp_tx_axis_mac_tdata ), + .tvalid0 (udp_tx_axis_mac_tvalid ), + .tlast0 (udp_tx_axis_mac_tlast ), + .tuser0 (1'b0 ), + .tready0 (udp_tx_axis_mac_tready ), +//Mux In 1 Interface + .tdata1 (mac_tx_axis_mac_tdata ), + .tvalid1 (mac_tx_axis_mac_tvalid ), + .tlast1 (mac_tx_axis_mac_tlast ), + .tuser1 (1'b0 ), + .tready1 (mac_tx_axis_mac_tready ), +//Mux Out Interface + .tdata (pat_tx_axis_mac_tdata ), + .tvalid (pat_tx_axis_mac_tvalid ), + .tlast (pat_tx_axis_mac_tlast ), + .tuser (pat_tx_axis_mac_tuser ), + .tready (pat_tx_axis_mac_tready ) +); + +/*----------------------- The Tx AXI4 St Mux Module -----------------------*/ +axi4_st_mux u_tx_axi4st_mux +( +//Globle Signals + .mux_select (axi4_st_mux_select ),//0:pat; 1:rx2tx loopback; +//Mux In 0 Interface + .tdata0 (pat_tx_axis_mac_tdata ), + .tvalid0 (pat_tx_axis_mac_tvalid ), + .tlast0 (pat_tx_axis_mac_tlast ), + .tuser0 (pat_tx_axis_mac_tuser ), + .tready0 (pat_tx_axis_mac_tready ), +//Mux In 1 Interface + .tdata1 (loop_tx_axis_mac_tdata ), + .tvalid1 (loop_tx_axis_mac_tvalid ), + .tlast1 (loop_tx_axis_mac_tlast ), + .tuser1 (loop_tx_axis_mac_tuser ), + .tready1 (loop_tx_axis_mac_tready ), +//Mux Out Interface + .tdata (tx_axis_mac_tdata ), + .tvalid (tx_axis_mac_tvalid ), + .tlast (tx_axis_mac_tlast ), + .tuser (tx_axis_mac_tuser ), + .tready (tx_axis_mac_tready ) +); + +/*----------------------- The Tri-mode Ethernet MAC core -----------------------*/ +gTSE u_tsemac +( +//Globle Signals + .mac_reset (mac_reset ), + .proto_reset (proto_reset ), + .tx_mac_aclk (clk_125m ), + .rx_mac_aclk ( ), + .eth_speed ( ), +//Receive AXI4-Stream Interface + .rx_axis_clk (rx_axis_clk ), + .rx_axis_mac_tdata (rx_axis_mac_tdata ), + .rx_axis_mac_tvalid (rx_axis_mac_tvalid ), + .rx_axis_mac_tlast (rx_axis_mac_tlast ), + .rx_axis_mac_tstrb (), + .rx_axis_mac_tuser (rx_axis_mac_tuser ), + .rx_axis_mac_tready (rx_axis_mac_tready ), +//Transmit AXI4-Stream Interface + .tx_axis_clk (tx_axis_clk ), + .tx_axis_mac_tdata (tx_axis_mac_tdata ), + .tx_axis_mac_tvalid (tx_axis_mac_tvalid ), + .tx_axis_mac_tlast (tx_axis_mac_tlast ), + .tx_axis_mac_tstrb (1'b1 ), + .tx_axis_mac_tuser (tx_axis_mac_tuser ), + .tx_axis_mac_tready (tx_axis_mac_tready ), + //--RGMII Interface + .rgmii_txd_HI (rgmii_txd_HI ), + .rgmii_txd_LO (rgmii_txd_LO ), + .rgmii_tx_ctl_HI (rgmii_tx_ctl_HI ), + .rgmii_tx_ctl_LO (rgmii_tx_ctl_LO ), + .rgmii_txc_HI (rgmii_txc_HI ), + .rgmii_txc_LO (rgmii_txc_LO ), + .rgmii_rxd_HI (rgmii_rxd_HI ), + .rgmii_rxd_LO (rgmii_rxd_LO ), + .rgmii_rx_ctl_HI (rgmii_rx_ctl_HI ), + .rgmii_rx_ctl_LO (rgmii_rx_ctl_LO ), + .rgmii_rxc (rgmii_rxc ), + //AXI4-Lite Interface + .s_axi_aclk (clk_50m ), + .s_axi_awaddr (axi_awaddr ), + .s_axi_awvalid (axi_awvalid ), + .s_axi_awready (axi_awready ), + .s_axi_wdata (axi_wdata ), + .s_axi_wvalid (axi_wvalid ), + .s_axi_wready (axi_wready ), + .s_axi_bresp (axi_bresp ), + .s_axi_bvalid (axi_bvalid ), + .s_axi_bready (axi_bready ), + .s_axi_araddr (axi_araddr ), + .s_axi_arvalid (axi_arvalid ), + .s_axi_arready (axi_arready ), + .s_axi_rresp (axi_rresp ), + .s_axi_rdata (axi_rdata ), + .s_axi_rvalid (axi_rvalid ), + .s_axi_rready (axi_rready ), + //MDIO Interface + .Mdo (phy_mdo ), + .MdoEn (phy_mdo_en ), + .Mdi (phy_mdi ), + .Mdc (phy_mdc ) +); + +/*----------------------- User Interface Loopback Module ----------------------------*/ +mac_rx2tx u_mac_rx2tx +( +//Globle Signals +// +//Receive AXI4-Stream Interface + .rx_axis_clk (rx_axis_clk ), + .rx_axis_rstn (mac_rstn ), + .rx_axis_mac_tdata (rx_axis_mac_tdata ), + .rx_axis_mac_tvalid (rx_axis_mac_tvalid ), + .rx_axis_mac_tlast (rx_axis_mac_tlast ), + .rx_axis_mac_tuser (rx_axis_mac_tuser ), + .rx_axis_mac_tready (rx_axis_mac_tready ), +//Transmit AXI4-Stream Interface + .tx_axis_clk (tx_axis_clk ), + .tx_axis_rstn (mac_rstn ), + .tx_axis_mac_tdata (loop_tx_axis_mac_tdata ), + .tx_axis_mac_tvalid (loop_tx_axis_mac_tvalid ), + .tx_axis_mac_tlast (loop_tx_axis_mac_tlast ), + .tx_axis_mac_tuser (loop_tx_axis_mac_tuser ), + .tx_axis_mac_tready (loop_tx_axis_mac_tready ) +); + +endmodule + diff --git a/fpga/ip/gTSE/Testbench/udp_pat_gen.v b/fpga/ip/gTSE/Testbench/udp_pat_gen.v new file mode 100644 index 0000000..e5626c3 --- /dev/null +++ b/fpga/ip/gTSE/Testbench/udp_pat_gen.v @@ -0,0 +1,497 @@ +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / +// / / .' / +// __/ /.' / +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* +`timescale 1 ns / 1 ns +module udp_pat_gen +( +//Globle Signals +input clk, +input rstn, +//Control Interface +input pat_gen_en, +input [15:0] pat_gen_num,//When value is 0, it's infinite mode +input [15:0] pat_gen_ipg, +//MAC Protocol Signals +input [47:0] dst_mac, +input [47:0] src_mac, +//IP Protocol Signals +input [31:0] src_ip, +input [31:0] dst_ip, +//UDP Protocol Signals +input [15:0] udp_dlen, +input [15:0] src_port, +input [15:0] dst_port, +//AXI4-Stream Interface +input rclk, +input rrstn, +input [7:0] rdata, +input rvalid, +input rlast, + +output reg [7:0] tdata, +output reg tvalid, +output reg tlast, +input tready +); + +// Parameter Define +localparam VER = 4'h4;//IPv4 +localparam IHL = 4'h5;//Internet Header Length +localparam TOS = 8'h0;//Type Of Service +localparam FLG = 3'h0;//Flags +localparam TTL = 8'h40;//Time To Live +localparam PTC = 8'h11;//UDP Protocol + +localparam IDLE = 3'h0; +localparam UDP_CHKSUM = 3'h1; +localparam IP_CHKSUM = 3'h2; +localparam PAT_IPG = 3'h3; +localparam PAT_GEN = 3'h4; + +// Register Define +reg [2:0] cur_state; +reg [2:0] next_state; +reg pat_gen_en_dl1; +reg pat_gen_en_dl2; +reg [31:0] src_ip_r; +reg [31:0] dst_ip_r; +reg [15:0] src_port_r; +reg [15:0] dst_port_r; +reg pat_en; +reg infinite_en; +reg [15:0] num_cnt; +reg [15:0] udp_chksum_cnt; +reg [3:0] ip_chksum_cnt; +reg [15:0] ipg_cnt; +reg [15:0] pat_cnt; +reg [15:0] udp_len; +reg [15:0] udp_chksum_num; +reg [7:0] udp_data_h; +reg [7:0] udp_data_l; +reg [16:0] udp_chksum_r; +reg [15:0] udp_chksum; +reg [15:0] ip_len; +reg [15:0] ip_id; +reg [12:0] ip_ofs; +reg [16:0] ip_chksum_r; +reg [15:0] ip_chksum; + +reg [15:0] pat_gen_num_r; +reg [15:0] pat_gen_ipg_r; +reg [47:0] dst_mac_r; +reg [47:0] src_mac_r; +reg [15:0] udp_dlen_r; + +// Wire Define +/*----------------------------------------------------------------------------------*\ + The main code +\*----------------------------------------------------------------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) begin + pat_gen_num_r <= 16'h0; + pat_gen_ipg_r <= 16'h0; + dst_mac_r <= 48'h0; + src_mac_r <= 48'h0; + udp_dlen_r <= 16'h0; + end + else begin + pat_gen_num_r <= pat_gen_num; + pat_gen_ipg_r <= pat_gen_ipg; + dst_mac_r <= dst_mac; + src_mac_r <= src_mac; + udp_dlen_r <= udp_dlen; + end +end + +/*----------------------- FSM Region ----------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + cur_state <= IDLE; + else + cur_state <= next_state; +end + +always @(*) + begin + case(cur_state) + IDLE : + if(pat_en == 1'b1) + next_state = UDP_CHKSUM; + else + next_state = IDLE; + + UDP_CHKSUM : + if(udp_chksum_cnt == udp_chksum_num) + next_state = IP_CHKSUM; + else + next_state = UDP_CHKSUM; + + IP_CHKSUM : + if(ip_chksum_cnt == 4'd9) + next_state = PAT_GEN; + else + next_state = IP_CHKSUM; + + PAT_IPG : + if((pat_en == 1'b1) || ((ipg_cnt == pat_gen_ipg_r) && (infinite_en == 1'b0) && (num_cnt == 16'h0))) + next_state = IDLE; + else if(ipg_cnt == pat_gen_ipg_r) + next_state = IP_CHKSUM; + else + next_state = PAT_IPG; + + PAT_GEN : + if((tlast == 1'b1) && (tready == 1'b1)) + next_state = PAT_IPG; + else + next_state = PAT_GEN; + + default : + next_state = IDLE; + endcase + end + +/*----------------------- Generator Control Region ----------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + begin + pat_gen_en_dl1 <= 1'h0; + pat_gen_en_dl2 <= 1'h0; + end + else + begin + pat_gen_en_dl1 <= pat_gen_en; + pat_gen_en_dl2 <= pat_gen_en_dl1; + end +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + begin + src_ip_r <= 32'h0; + dst_ip_r <= 32'h0; + src_port_r <= 16'h0; + dst_port_r <= 16'h0; + end + else + begin + src_ip_r <= src_ip; + dst_ip_r <= dst_ip; + src_port_r <= src_port; + dst_port_r <= dst_port; + end +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + pat_en <= 1'h0; + else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) + pat_en <= 1'h1; + else if((cur_state == IDLE) && (pat_en == 1'b1)) + pat_en <= 1'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + infinite_en <= 1'h0; + else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1) && (pat_gen_num_r == 16'h0)) + infinite_en <= 1'h1; + else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) + infinite_en <= 1'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + num_cnt <= 16'h0; + else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) + num_cnt <= pat_gen_num_r; + else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1) && (num_cnt != 16'h0)) + num_cnt <= num_cnt - 1'b1; +end + +/*----------------------- UDP Protocol Region ----------------------------*/ + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + udp_len <= 16'h0; + else + udp_len <= udp_dlen_r + 16'd8; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + udp_chksum_num <= 16'h0; + else if(udp_dlen_r[0] == 1'b1) + udp_chksum_num <= udp_dlen_r[15:1] + 16'd10; + else + udp_chksum_num <= udp_dlen_r[15:1] + 16'd9; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + begin + udp_data_h <= 8'h0; + udp_data_l <= 8'h0; + end + else if(cur_state == IDLE) + begin + udp_data_h <= 8'h0; + udp_data_l <= 8'h1; + end + else if((cur_state == UDP_CHKSUM) && (udp_chksum_cnt >= 16'h9)) + begin + udp_data_h <= udp_data_h + 8'h2; + udp_data_l <= udp_data_l + 8'h2; + end +end + +//udp checksum calculate +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + udp_chksum_r <= 17'h0; + else if(cur_state == IDLE) + udp_chksum_r <= 17'h0; + else if(cur_state == UDP_CHKSUM) begin + if (udp_chksum_cnt <= 16'd8) begin + case(udp_chksum_cnt[3:0]) + 4'd0 : udp_chksum_r <= udp_chksum_r[15:0] + src_ip_r[31:16] + udp_chksum_r[16]; + 4'd1 : udp_chksum_r <= udp_chksum_r[15:0] + src_ip_r[15:0] + udp_chksum_r[16]; + 4'd2 : udp_chksum_r <= udp_chksum_r[15:0] + dst_ip_r[31:16] + udp_chksum_r[16]; + 4'd3 : udp_chksum_r <= udp_chksum_r[15:0] + dst_ip_r[15:0] + udp_chksum_r[16]; + 4'd4 : udp_chksum_r <= udp_chksum_r[15:0] + 16'h11 + udp_chksum_r[16]; + 4'd5 : udp_chksum_r <= udp_chksum_r[15:0] + udp_len + udp_chksum_r[16]; + 4'd6 : udp_chksum_r <= udp_chksum_r[15:0] + src_port_r + udp_chksum_r[16]; + 4'd7 : udp_chksum_r <= udp_chksum_r[15:0] + dst_port_r + udp_chksum_r[16]; + 4'd8 : udp_chksum_r <= udp_chksum_r[15:0] + udp_len + udp_chksum_r[16]; + default : udp_chksum_r <= 17'h0; + endcase + end + else begin + if(udp_chksum_cnt == udp_chksum_num) + udp_chksum_r <= udp_chksum_r[15:0] + udp_chksum_r[16]; + else if((udp_chksum_cnt == udp_chksum_num-1) && (udp_dlen_r[0] == 1'b1)) + udp_chksum_r <= udp_chksum_r[15:0] + {udp_data_h,8'h0} + udp_chksum_r[16]; + else + udp_chksum_r <= udp_chksum_r[15:0] + {udp_data_h,udp_data_l} + udp_chksum_r[16]; + end + end +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + udp_chksum <= 16'h0; + else + udp_chksum <= ~udp_chksum_r[15:0]; +end + +/*----------------------- IP Protocol Region ----------------------------*/ +//IP Frame Total Length +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ip_len <= 16'h0; + else + ip_len <= udp_len + 16'd20; +end + +//IP Frame Identification +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ip_id <= 16'h0; + else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1)) + ip_id <= ip_id + 1'b1; +end + +//IP Frame Fragment Offset +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ip_chksum <= 16'h0; + else + ip_chksum <= ~ip_chksum_r[15:0]; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ip_ofs <= 13'h0; +end + +//ip checksum calculate +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ip_chksum_r <= 16'h0; + else if(cur_state == IDLE) + ip_chksum_r <= 16'h0; + else if(cur_state == IP_CHKSUM) begin + case(ip_chksum_cnt) + 4'd0 : ip_chksum_r <= ip_chksum_r[15:0] + {VER,IHL,TOS} + ip_chksum_r[16]; + 4'd1 : ip_chksum_r <= ip_chksum_r[15:0] + ip_len + ip_chksum_r[16]; + 4'd2 : ip_chksum_r <= ip_chksum_r[15:0] + ip_id + ip_chksum_r[16]; + 4'd3 : ip_chksum_r <= ip_chksum_r[15:0] + {FLG,ip_ofs} + ip_chksum_r[16]; + 4'd4 : ip_chksum_r <= ip_chksum_r[15:0] + {TTL,PTC} + ip_chksum_r[16]; + 4'd5 : ip_chksum_r <= ip_chksum_r[15:0] + src_ip_r[31:16] + ip_chksum_r[16]; + 4'd6 : ip_chksum_r <= ip_chksum_r[15:0] + src_ip_r[15:0] + ip_chksum_r[16]; + 4'd7 : ip_chksum_r <= ip_chksum_r[15:0] + dst_ip_r[31:16] + ip_chksum_r[16]; + 4'd8 : ip_chksum_r <= ip_chksum_r[15:0] + dst_ip_r[15:0] + ip_chksum_r[16]; + 4'd9 : ip_chksum_r <= ip_chksum_r[15:0] + ip_chksum_r[16]; + endcase + end + else if(cur_state == PAT_IPG) + ip_chksum_r <= 16'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ip_chksum <= 16'h0; + else + ip_chksum <= ~ip_chksum_r[15:0]; +end + +/*----------------------- Pattern Counter Region ----------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + udp_chksum_cnt <= 16'h0; + else if(cur_state == UDP_CHKSUM) + udp_chksum_cnt <= udp_chksum_cnt + 1'b1; + else + udp_chksum_cnt <= 16'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ip_chksum_cnt <= 4'h0; + else if(cur_state == IP_CHKSUM) + ip_chksum_cnt <= ip_chksum_cnt + 1'b1; + else + ip_chksum_cnt <= 4'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ipg_cnt <= 16'h0; + else if(cur_state == PAT_IPG) + ipg_cnt <= ipg_cnt + 1'b1; + else + ipg_cnt <= 8'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + pat_cnt <= 16'h0; + else if(cur_state != PAT_GEN) + pat_cnt <= 16'h0; + else if(tready == 1'b1) + pat_cnt <= pat_cnt + 1'b1; +end + +/*----------------------- Pattern Generator Region ----------------------------*/ + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + tvalid <= 1'b0; + else if((cur_state == PAT_GEN) && (pat_cnt == 16'h0) && (tready == 1'b1)) + tvalid <= 1'b1; + else if((tready == 1'b1) && (tlast == 1'b1)) + tvalid <= 1'b0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + tdata <= 8'h0; + else if((cur_state == PAT_GEN) && (tready == 1'b1) && (pat_cnt <= 16'd42)) + case(pat_cnt[5:0]) + 6'd0 : tdata <= dst_mac_r[5*8 +: 8]; + 6'd1 : tdata <= dst_mac_r[4*8 +: 8]; + 6'd2 : tdata <= dst_mac_r[3*8 +: 8]; + 6'd3 : tdata <= dst_mac_r[2*8 +: 8]; + 6'd4 : tdata <= dst_mac_r[1*8 +: 8]; + 6'd5 : tdata <= dst_mac_r[0*8 +: 8]; + 6'd6 : tdata <= src_mac_r[5*8 +: 8]; + 6'd7 : tdata <= src_mac_r[4*8 +: 8]; + 6'd8 : tdata <= src_mac_r[3*8 +: 8]; + 6'd9 : tdata <= src_mac_r[2*8 +: 8]; + 6'd10 : tdata <= src_mac_r[1*8 +: 8]; + 6'd11 : tdata <= src_mac_r[0*8 +: 8]; + 6'd12 : tdata <= 8'h08; + 6'd13 : tdata <= 8'h00; + 6'd14 : tdata <= {VER,IHL}; + 6'd15 : tdata <= TOS; + 6'd16 : tdata <= ip_len[15:8]; + 6'd17 : tdata <= ip_len[7:0]; + 6'd18 : tdata <= ip_id[15:8]; + 6'd19 : tdata <= ip_id[7:0]; + 6'd20 : tdata <= {FLG,ip_ofs[12:8]}; + 6'd21 : tdata <= ip_ofs[7:0]; + 6'd22 : tdata <= TTL; + 6'd23 : tdata <= PTC; + 6'd24 : tdata <= ip_chksum[15:8]; + 6'd25 : tdata <= ip_chksum[7:0]; + 6'd26 : tdata <= src_ip_r[3*8 +: 8]; + 6'd27 : tdata <= src_ip_r[2*8 +: 8]; + 6'd28 : tdata <= src_ip_r[1*8 +: 8]; + 6'd29 : tdata <= src_ip_r[0*8 +: 8]; + 6'd30 : tdata <= dst_ip_r[3*8 +: 8]; + 6'd31 : tdata <= dst_ip_r[2*8 +: 8]; + 6'd32 : tdata <= dst_ip_r[1*8 +: 8]; + 6'd33 : tdata <= dst_ip_r[0*8 +: 8]; + 6'd34 : tdata <= src_port_r[15:8]; + 6'd35 : tdata <= src_port_r[7:0]; + 6'd36 : tdata <= dst_port_r[15:8]; + 6'd37 : tdata <= dst_port_r[7:0]; + 6'd38 : tdata <= udp_len[15:8]; + 6'd39 : tdata <= udp_len[7:0]; + 6'd40 : tdata <= udp_chksum[15:8]; + 6'd41 : tdata <= udp_chksum[7:0]; + 6'd42 : tdata <= 8'h0;//UDP First Data + default : tdata <= tdata + 1'b1; + endcase + else if((cur_state == PAT_GEN) && (tready == 1'b1)) + tdata <= tdata + 1'b1; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + tlast <= 1'b0; + else if((tready == 1'b1) && (cur_state == PAT_GEN) && (pat_cnt == ip_len+16'd13)) + tlast <= 1'b1; + else if(tready == 1'b1) + tlast <= 1'b0; +end + +endmodule diff --git a/fpga/ip/gTSE/Ti60F225_devkit/DaulClkFifo.v b/fpga/ip/gTSE/Ti60F225_devkit/DaulClkFifo.v new file mode 100644 index 0000000..7d34961 --- /dev/null +++ b/fpga/ip/gTSE/Ti60F225_devkit/DaulClkFifo.v @@ -0,0 +1,498 @@ + +`timescale 1ns/100ps + +module DC_FIFO +# ( + parameter FIFO_MODE = "Normal" , //"Normal"; //"ShowAhead" + parameter DATA_WIDTH = 8 , + parameter FIFO_DEPTH = 512 , + + parameter AW_C = $clog2(FIFO_DEPTH), + parameter DW_C = DATA_WIDTH , + parameter DD_C = 2**AW_C + ) +( + //System Signal + input Reset , //System Reset + //Write Signal + input WrClk , //(I)Wirte Clock + input WrEn , //(I)Write Enable + output [AW_C-1:0] WrDNum , //(O)Write Data Number In Fifo + output WrFull , //(I)Write Full + input [DW_C -1:0] WrData , //(I)Write Data + //Read Signal + input RdClk , //(I)Read Clock + input RdEn , //(I)Read Enable + output [AW_C-1:0] RdDNum , //(O)Radd Data Number In Fifo + output RdEmpty , //(O)Read FifoEmpty + output [DW_C-1 :0] RdData //(O)Read Data +); + +//Define Parameter +/////////////////////////////////////////////////////////////// + localparam TCo_C = 0 ; + + reg [1:0] WrClkRstGen = 2'h3; + reg [1:0] RdClkRstGen = 2'h3; + + always @( posedge WrClk or posedge Reset) + begin + if (Reset) WrClkRstGen <= # TCo_C 2'h3; + else + begin + WrClkRstGen[0] <= # TCo_C 1'h0; + WrClkRstGen[1] <= # TCo_C (&RdClkRstGen); + end + end + + wire WrClkRst = WrClkRstGen[1]; + + /////////////////////////////////////////////////// + always @( posedge RdClk or posedge Reset) + begin + if (Reset) RdClkRstGen <= # TCo_C 2'h3; + else + begin + RdClkRstGen[0] <= # TCo_C 1'h0; + RdClkRstGen[1] <= # TCo_C (&WrClkRstGen); + end + end + + wire RdClkRst = RdClkRstGen[1]; + + /////////////////////////////////////////////////// + wire FifoWrEn = WrEn; + wire [AW_C :0] WrAddrCnt ; + wire [AW_C :0] FifoWrAddr ; + wire FifoWrFull ; + + FifoAddrCnt # ( .CounterWidth_C (AW_C)) + U1_WrAddrCnt + ( + //System Signal + .Reset ( WrClkRst ) , //System Reset + .SysClk ( WrClk ) , //System Clock + //Counter Signal + .ClkEn ( FifoWrEn ) , //(I)Clock Enable + .FifoFlag ( FifoWrFull ) , //(I)Fifo Flag + .AddrCnt ( WrAddrCnt ) , //(O)Address Counter + .Addess ( FifoWrAddr ) //(O)Address Output + ); + + /////////////////////////////////////////////////// + reg [DW_C-1:0] FifoBuff [DD_C-1:0]; + + always @( posedge WrClk) + begin + if (WrEn & (~WrFull)) + begin + FifoBuff[FifoWrAddr[AW_C-1:0]] <= # TCo_C WrData; + end + end + + /////////////////////////////////////////////////// + + /////////////////////////////////////////////////// + wire FifoEmpty ; + wire FifoRdEn ; + + wire [AW_C :0] RdAddrCnt ; + wire [AW_C :0] FifoRdAddr ; + + FifoAddrCnt #( .CounterWidth_C (AW_C)) + U2_RdAddrCnt + ( + //System Signal + .Reset ( RdClkRst ) , //System Reset + .SysClk ( RdClk ) , //System Clock + //Counter Signal + .ClkEn ( FifoRdEn ) , //(I)Clock Enable + .FifoFlag ( FifoEmpty ) , //(I)Fifo Flag + .AddrCnt ( RdAddrCnt ) , //(O)Address Counter + .Addess ( FifoRdAddr ) //(O)Address Output + ); + + /////////////////////////////////////////////////// + reg [DW_C-1 :0] FifoRdData ; + + always @( posedge RdClk) + begin + if (FifoRdEn) FifoRdData <= # TCo_C FifoBuff[FifoRdAddr[AW_C-1:0]]; + end + + /////////////////////////////////////////////////// + assign RdData = FifoRdData ; //(O)Read Data + + reg [AW_C:0] WrRdAddr = {AW_C+1{1'h0}}; + + always @( posedge WrClk) + begin + if (WrClkRst) WrRdAddr <= # TCo_C {AW_C+1{1'h0}} ; + else WrRdAddr <= # TCo_C FifoRdAddr [AW_C:0] ; + end + + /////////////////////////////////////////////////////////// + wire [AW_C-1:0] WrRdAHex; + wire [AW_C-1:0] WrWrAHex; + + GrayDecode #(AW_C) WRAGray2Hex (WrRdAddr [AW_C-1:0] , WrRdAHex[AW_C-1:0]); + GrayDecode #(AW_C) WWAGray2Hex (FifoWrAddr [AW_C-1:0] , WrWrAHex[AW_C-1:0]); + + /////////////////////////////////////////////////////////// + reg [AW_C-1:0] WrAddrDiff; + + always @( posedge WrClk) + begin + if (WrFull) WrAddrDiff <= # TCo_C {AW_C{1'h1}} ; + else WrAddrDiff <= # TCo_C (WrWrAHex - WrRdAHex) ; + end + + /////////////////////////////////////////////////////////// + assign WrDNum = WrAddrDiff[AW_C-1:0]; //(O)Data Number In Fifo + + reg [AW_C:0] WrRdAddrReg = {AW_C+1{1'h0}}; + + always @( posedge WrClk) + begin + if ( WrClkRst) WrRdAddrReg <= # TCo_C {AW_C+1{1'h0}} ; + else WrRdAddrReg <= # TCo_C WrRdAddr[AW_C : 0] ; + end + + /////////////////////////////////////////////////////////// + reg RdAddrChg = 1'h0; + reg WrFullClr = 1'h0; + + always @( posedge WrClk) + begin + if ( WrClkRst) RdAddrChg <= # TCo_C 1'h0 ; + else RdAddrChg <= # TCo_C (FifoWrFull & (WrRdAddr[AW_C-1:0] != WrRdAddrReg[AW_C-1:0])); + end + + always @( posedge WrClk) + begin + if ( WrClkRst) WrFullClr <= # TCo_C 1'h0 ; + else WrFullClr <= # TCo_C (FifoWrFull & RdAddrChg); + end + + /////////////////////////////////////////////////////////// + reg RdAHighNext = 1'h0; + + wire RdAHighRise = (~WrRdAddrReg[AW_C-1]) & WrRdAddr[AW_C-1]; + + always @( posedge WrClk) + begin + if (WrClkRst ) RdAHighNext <= # TCo_C 1'h0 ; + else if (RdAHighRise) RdAHighNext <= # TCo_C (~WrRdAddr[AW_C]) ; + end + + /////////////////////////////////////////////////// + wire FullCalc = (WrAddrCnt[AW_C-1:0] == WrRdAddr[AW_C-1:0]) + && (WrAddrCnt[AW_C ] != (WrRdAddr[AW_C-1] ? WrRdAddrReg[AW_C] : RdAHighNext) ); + + /////////////////////////////////////////////////// + reg FullFlag = 1'h0; + + always @( posedge WrClk) + begin + if (WrClkRst) FullFlag <= # TCo_C 1'h0; + else if (FullFlag) FullFlag <= # TCo_C (~WrFullClr); + else if (FifoWrEn) FullFlag <= # TCo_C FullCalc; + end + + assign FifoWrFull = FullFlag; + + /////////////////////////////////////////////////// + assign WrFull = FifoWrFull ; //(I)Write Full + + reg [AW_C :0] RdWrAddr = {AW_C+1{1'h0}}; + + always @( posedge RdClk) + begin + if (RdClkRst ) RdWrAddr <= # TCo_C {AW_C+1{1'h0}} ; + else RdWrAddr <= # TCo_C FifoWrAddr [AW_C:0] ; + end + + /////////////////////////////////////////////////////////// + wire [AW_C-1:0] RdWrAHex; + wire [AW_C-1:0] RdRdAHex; + + GrayDecode # (AW_C) RWAGray2Hex (RdWrAddr [AW_C-1:0] , RdWrAHex[AW_C-1:0] ); + GrayDecode # (AW_C) RRAGray2Hex (FifoRdAddr [AW_C-1:0] , RdRdAHex[AW_C-1:0] ); + + /////////////////////////////////////////////////////////// + reg [AW_C-1:0] RdAddrDiff; + + always @( posedge RdClk) + begin + if (RdEmpty ) RdAddrDiff <= # TCo_C {AW_C{1'h0}} ; + else RdAddrDiff <= # TCo_C (RdWrAHex - RdRdAHex) ; + end + + /////////////////////////////////////////////////////////// + assign RdDNum = RdAddrDiff[AW_C-1:0]; //(O)Data Number In Fifo + + reg [AW_C:0] RdWrAddrReg = {AW_C+1{1'h0}}; + + always @( posedge RdClk) + begin + if (RdClkRst) RdWrAddrReg <= # TCo_C {AW_C+1{1'h0}} ; + else RdWrAddrReg <= # TCo_C RdWrAddr [AW_C:0] ; + end + + /////////////////////////////////////////////////////////// + reg WrAddrChg = 1'h0; + reg EmptyClr = 1'h0; + + always @( posedge RdClk) + begin + if (RdClkRst) WrAddrChg <= # TCo_C 1'h0 ; + else WrAddrChg <= # TCo_C FifoEmpty & (RdWrAddr[AW_C-1:0] != RdWrAddrReg[AW_C-1:0]); + end + always @( posedge RdClk) + begin + if (RdClkRst) EmptyClr <= # TCo_C 1'h0; + else EmptyClr <= # TCo_C (FifoEmpty & WrAddrChg); + end + + /////////////////////////////////////////////////////////// + reg WrAHighNext = 1'h0; + + wire WrAHighRise = (~RdWrAddrReg[AW_C-1]) & RdWrAddr[AW_C-1]; + + always @( posedge RdClk) + begin + if (RdClkRst) WrAHighNext <= # TCo_C 1'h0 ; + else if (WrAHighRise) WrAHighNext <= # TCo_C (~RdWrAddr[AW_C]); + end + + /////////////////////////////////////////////////////////// + wire EmptyCalc = (RdAddrCnt[AW_C-1:0] == RdWrAddr[AW_C-1:0]) + && (RdAddrCnt[AW_C ] == (RdWrAddr[AW_C-1] ? RdWrAddrReg[AW_C] : WrAHighNext)); + + /////////////////////////////////////////////////////////// + reg EmptyFlag = 1'h1; + + always @( posedge RdClk) + begin + if (RdClkRst) EmptyFlag <= # TCo_C 1'h1; + else if (EmptyFlag) EmptyFlag <= # TCo_C (~EmptyClr); + else if (FifoRdEn) EmptyFlag <= # TCo_C EmptyCalc; + end + + assign FifoEmpty = EmptyFlag; + + /////////////////////////////////////////////////////////// + reg EmptyReg = 1'h0; + + always @( posedge RdClk ) + begin + if (RdClkRst) EmptyReg <= # TCo_C 1'h1; + else if (FifoRdEn) EmptyReg <= # TCo_C FifoEmpty; + end + + /////////////////////////////////////////////////////////// + assign RdEmpty = (FIFO_MODE == "ShowAhead") ? EmptyReg : FifoEmpty; //(O)Read FifoEmpty + + reg RdFirst = 1'h0; + + always @( posedge RdClk) + begin + if (FIFO_MODE == "ShowAhead") + begin + if (RdClkRst) RdFirst <= # TCo_C 1'h0 ; + else if (RdFirst) RdFirst <= # TCo_C 1'h0 ; + else if (EmptyClr) RdFirst <= # TCo_C RdEmpty ; + end + else RdFirst <= # TCo_C 1'h0 ; + end + + /////////////////////////////////////////////////////////// + assign FifoRdEn = RdEn || RdFirst ; + + /////////////////////////////////////////////////////////// + +//666666666666666666666666666666666666666666666666666666666 + +endmodule + +//////////////// DaulClkFifo ////////////////////////////// + +///////////////// FifoAddrCnt ///////////////////////////// + +module FifoAddrCnt +# ( + parameter CounterWidth_C = 9 , + parameter CW_C = CounterWidth_C + ) +( + //System Signal + input Reset , //System Reset + input SysClk , //System Clock + //Counter Signal + input ClkEn , //(I)Clock Enable + input FifoFlag , //(I)Fifo Flag + output [CW_C:0] AddrCnt , //(O)Address Counter + output [CW_C:0] Addess //(O)Address Output +); + +//Define Parameter +/////////////////////////////////////////////////////////// +localparam TCo_C = 1; + + wire [CW_C-1:0] GrayAddrCnt; + wire CarryOut; + + GrayCnt #(.CounterWidth_C (CW_C)) + U1_AddrCnt + ( + //System Signal + .Reset ( Reset ), //System Reset + .SysClk ( SysClk ), //System Clock + //Counter Signal + .SyncClr ( 1'h0 ), //(I)Sync Clear + .ClkEn ( ClkEn ), //(I)Clock Enable + .CarryIn ( ~FifoFlag ), //(I)Carry input + .CarryOut ( CarryOut ), //(O)Carry output + .Count ( GrayAddrCnt ) //(O)Counter Value Output + ); + +/////////////////////////////////////////////////////////// + reg CntHighBit; + + always @( posedge SysClk ) + begin + if (Reset) CntHighBit <= # TCo_C 1'h0; + else if (ClkEn) CntHighBit <= # TCo_C CntHighBit + CarryOut; + end + +/////////////////////////////////////////////////////////// + reg [CW_C:0] AddrOut; //(O)Address Output + + always @(posedge SysClk) + begin + if (Reset) AddrOut <= # TCo_C {CW_C{1'h0}}; + else if (ClkEn) AddrOut <= # TCo_C FifoFlag ? AddrOut : AddrCnt; + end + +/////////////////////////////////////////////////////////// + assign AddrCnt = {CntHighBit , GrayAddrCnt} ; //(O)Address Counter + assign Addess = AddrOut ; //(O)Address Output + +//111111111111111111111111111111111111111111111111111111111 + +endmodule + +/////////////////// FifoAddrCnt ////////////////////////// + +module GrayCnt +# ( + parameter CounterWidth_C = 9 , + parameter CW_C = CounterWidth_C + ) +( + //System Signal + input Reset , //System Reset + input SysClk , //System Clock + //Counter Signal + input SyncClr , //(I)Sync Clear + input ClkEn , //(I)Clock Enable + input CarryIn , //(I)Carry input + output CarryOut , //(O)Carry output + output [CW_C-1:0] Count //(O)Counter Value Output +); + +//Define Parameter +/////////////////////////////////////////////////////////// +localparam TCo_C = 1; + + wire [CW_C:0 ] CryIn ; + wire [CW_C-1:0] CryOut ; + + reg [CW_C-1:0] GrayCnt; + + assign CryIn[0] = CarryIn; + + genvar i; + generate + for(i=0;i1) ? 1'h0: 1'h1 ; + else if (SyncClr) GrayCnt[i] <= # TCo_C (i>1) ? 1'h0: 1'h1 ; + else if (ClkEn) GrayCnt[i] <= # TCo_C GrayCnt[i] + CryIn[i]; + end + + ////////////// + if (i==0) + begin + assign CryOut[0] = GrayCnt[0] && CarryIn; + assign CryIn [1] = ~GrayCnt[0] && CarryIn; + end + else + begin + assign CryOut[i ] = CryOut[ 0] && (~|GrayCnt[i:1]); + assign CryIn [i+1] = CryOut[i-1] && GrayCnt[i ] ; + end + end + + endgenerate + + wire GrayCarry = CryOut[CW_C-2]; + +/////////////////////////////////////////////////////////// + reg CntHigh = 1'h0; + + always @( posedge SysClk) + begin + if (Reset) CntHigh <= # TCo_C 1'h0; + else if (ClkEn) CntHigh <= # TCo_C (CntHigh + GrayCarry); + end + +/////////////////////////////////////////////////////////// + assign Count = {CntHigh , GrayCnt[CW_C-1:1]} ; //(O)Counter Value Output + assign CarryOut = CntHigh & GrayCarry ; //(O)Carry output + +/////////////////////////////////////////////////////////// + +//111111111111111111111111111111111111111111111111111111111 + +endmodule + +////////////////////// GrayCnt //////////////////////////// + +module GrayDecode +# ( + parameter DataWidht_C = 8 + ) +( + input [DataWidht_C-1:0] GrayIn, + output [DataWidht_C-1:0] HexOut +); + + //Define Parameter + /////////////////////////////////////////////////////////////// + parameter TCo_C = 1; + + localparam DW_C = DataWidht_C; + + /////////////////////////////////////////////////////////////// + reg [DW_C-1:0] Hex; + + integer i; + + always @ (GrayIn) + begin + Hex[DW_C-1]=GrayIn[DW_C-1]; + for(i=DW_C-2;i>=0;i=i-1) Hex[i]=Hex[i+1]^GrayIn[i]; + end + + assign HexOut = Hex; + + /////////////////////////////////////////////////////////////// + +endmodule + + + diff --git a/fpga/ip/gTSE/Ti60F225_devkit/apb3_2_axi4_lite.v b/fpga/ip/gTSE/Ti60F225_devkit/apb3_2_axi4_lite.v new file mode 100644 index 0000000..a167005 --- /dev/null +++ b/fpga/ip/gTSE/Ti60F225_devkit/apb3_2_axi4_lite.v @@ -0,0 +1,215 @@ +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / +// / / .' / +// __/ /.' / +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* +`timescale 1 ns / 1 ns +module apb3_2_axi4_lite#( + parameter ADDR_WTH = 10 +) +( +//Globle Signals +input clk, +input rstn, +//APB3 Slave Interface +input [ADDR_WTH-1:0] s_apb3_paddr, +input s_apb3_psel, +input s_apb3_penable, +output reg s_apb3_pready, +input s_apb3_pwrite,//0:rd; 1:wr; +input [31:0] s_apb3_pwdata, +output reg [31:0] s_apb3_prdata, +output reg s_apb3_pslverror, +//AXI4-Lite Master Interface +output reg [ADDR_WTH-1:0] m_axi_awaddr,//Write Address. byte address. +output reg m_axi_awvalid,//Write address valid. +input m_axi_awready,//Write address ready. +output reg [31:0] m_axi_wdata,//Write data bus. +output reg m_axi_wvalid,//Write valid. +input m_axi_wready,//Write ready. +input [1:0] m_axi_bresp,//Write response. +input m_axi_bvalid,//Write response valid. +output wire m_axi_bready,//Response ready. +output reg [ADDR_WTH-1:0] m_axi_araddr,//Read address. byte address. +output reg m_axi_arvalid,//Read address valid. +input m_axi_arready,//Read address ready. +input [1:0] m_axi_rresp,//Read response. +input [31:0] m_axi_rdata,//Read data. +input m_axi_rvalid,//Read valid. +output wire m_axi_rready//Read ready. +); +// Parameter Define +parameter State_idle = 3'd0; +parameter State_wsetup = 3'd1; +parameter State_rsetup = 3'd2; +parameter State_ready = 3'd3; +parameter State_err = 3'd4; + +// Register Define +reg [2:0] cur_state; +reg [2:0] next_state; +reg [7:0] timeout_cnt; + +// Wire Define + +/*----------------------------------------------------------------------------------*\ + The main code +\*----------------------------------------------------------------------------------*/ + +/*----------------------- FSM Region ----------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + cur_state <= State_idle; + else + cur_state <= next_state; +end + +always @(*) +begin + case(cur_state) + State_idle : + if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) + next_state = State_wsetup; + else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0)) + next_state = State_rsetup; + else + next_state = State_idle; + + State_wsetup : + if((m_axi_awvalid == 1'b0) && (m_axi_wvalid == 1'b0)) + next_state = State_ready; + else if(timeout_cnt[7] == 1'b1) + next_state = State_err; + else + next_state = State_wsetup; + + State_rsetup : + if(m_axi_rvalid == 1'b1) + next_state = State_ready; + else if(timeout_cnt[7] == 1'b1) + next_state = State_err; + else + next_state = State_rsetup; + + State_ready : + next_state = State_idle; + + State_err : + next_state = State_idle; + + default : + next_state = State_idle; + endcase +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + timeout_cnt <= 8'h0; + else if((cur_state == State_wsetup) || (cur_state == State_rsetup)) + timeout_cnt <= timeout_cnt + 1'b1; + else + timeout_cnt <= 8'h0; +end + +/*----------------------- APB3 Region ----------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + s_apb3_pready <= 1'b0; + else if((cur_state == State_ready) || (cur_state == State_err)) + s_apb3_pready <= 1'b1; + else + s_apb3_pready <= 1'b0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + s_apb3_pslverror <= 1'b0; + else if(cur_state == State_err) + s_apb3_pslverror <= 1'b1; + else + s_apb3_pslverror <= 1'b0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + s_apb3_prdata <= 32'h0; + else if(m_axi_rvalid == 1'b1) + s_apb3_prdata <= m_axi_rdata; +end + +/*----------------------- AXI4-Lite Region ----------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + m_axi_awaddr <= {ADDR_WTH{1'b0}}; + else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) + m_axi_awaddr <= s_apb3_paddr; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + m_axi_awvalid <= 1'b0; + else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) + m_axi_awvalid <= 1'b1; + else if((m_axi_awready == 1'b1) || (cur_state == State_idle)) + m_axi_awvalid <= 1'b0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + m_axi_wdata <= 32'h0; + else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) + m_axi_wdata <= s_apb3_pwdata; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + m_axi_wvalid <= 1'b0; + else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) + m_axi_wvalid <= 1'b1; + else if((m_axi_wready == 1'b1) || (cur_state == State_idle)) + m_axi_wvalid <= 1'b0; +end + +assign m_axi_bready = 1'b1; + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + m_axi_araddr <= {ADDR_WTH{1'b0}}; + else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b0)) + m_axi_araddr <= s_apb3_paddr; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + m_axi_arvalid <= 1'b0; + else if((cur_state == State_idle) && (s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b0)) + m_axi_arvalid <= 1'b1; + else if((m_axi_arready == 1'b1) || (cur_state == State_idle)) + m_axi_arvalid <= 1'b0; +end + +assign m_axi_rready = 1'b1; + +endmodule diff --git a/fpga/ip/gTSE/Ti60F225_devkit/axi4_st_mux.v b/fpga/ip/gTSE/Ti60F225_devkit/axi4_st_mux.v new file mode 100644 index 0000000..fc32c17 --- /dev/null +++ b/fpga/ip/gTSE/Ti60F225_devkit/axi4_st_mux.v @@ -0,0 +1,61 @@ +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / +// / / .' / +// __/ /.' / +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* +`timescale 1 ns / 1 ns +module axi4_st_mux +( +//Globle Signals +input mux_select, +//Mux In 0 Interface +input [7:0] tdata0, +input tvalid0, +input tlast0, +input tuser0, +output wire tready0, +//Mux In 1 Interface +input [7:0] tdata1, +input tvalid1, +input tlast1, +input tuser1, +output wire tready1, +//Mux Out Interface +output wire [7:0] tdata, +output wire tvalid, +output wire tlast, +output wire tuser, +input tready +); + +// Parameter Define + +// Register Define + +// Wire Define + +/*----------------------------------------------------------------------------------*\ + The main code +\*----------------------------------------------------------------------------------*/ + +assign tdata = (mux_select) ? tdata1 : tdata0; +assign tvalid = (mux_select) ? tvalid1 : tvalid0; +assign tlast = (mux_select) ? tlast1 : tlast0; +assign tuser = (mux_select) ? tuser1 : tuser0; + +assign tready0 = (mux_select) ? 1'b1 : tready; +assign tready1 = (mux_select) ? tready : 1'b1; + + +endmodule diff --git a/fpga/ip/gTSE/Ti60F225_devkit/gTSE.sv b/fpga/ip/gTSE/Ti60F225_devkit/gTSE.sv new file mode 100644 index 0000000..8095d65 --- /dev/null +++ b/fpga/ip/gTSE/Ti60F225_devkit/gTSE.sv @@ -0,0 +1,9844 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.288.2.10 +// IP Version: 7.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _4c19f37180ff465ca20760e199a0613f +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module gTSE +( + input mac_reset, + input proto_reset, + output rx_mac_aclk, + input tx_mac_aclk, + output [2:0] eth_speed, + input rx_axis_clk, + output rx_axis_mac_tuser, + output rx_axis_mac_tlast, + output rx_axis_mac_tvalid, + input rx_axis_mac_tready, + input tx_axis_clk, + input tx_axis_mac_tvalid, + input tx_axis_mac_tlast, + input tx_axis_mac_tuser, + output tx_axis_mac_tready, + output [3:0] rgmii_txd_HI, + output [3:0] rgmii_txd_LO, + output rgmii_tx_ctl_HI, + output rgmii_tx_ctl_LO, + output rgmii_txc_HI, + output rgmii_txc_LO, + input [3:0] rgmii_rxd_HI, + input [3:0] rgmii_rxd_LO, + input rgmii_rx_ctl_HI, + input rgmii_rx_ctl_LO, + input rgmii_rxc, + input s_axi_aclk, + output [7:0] rx_axis_mac_tdata, + input [7:0] tx_axis_mac_tdata, + input [0:0] tx_axis_mac_tstrb, + output [0:0] rx_axis_mac_tstrb, + output MdoEn, + output Mdo, + input Mdi, + output Mdc, + input [9:0] s_axi_araddr, + output s_axi_arready, + input s_axi_arvalid, + input [9:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_awvalid, + input s_axi_bready, + output [1:0] s_axi_bresp, + output s_axi_bvalid, + output [31:0] s_axi_rdata, + input s_axi_rready, + output [1:0] s_axi_rresp, + output s_axi_rvalid, + input [31:0] s_axi_wdata, + output s_axi_wready, + input s_axi_wvalid +); +`IP_MODULE_NAME(efx_mac1gbe) +#( + .VERSION (16), + .TXFIFO_EN (1'b1), + .RXFIFO_EN (1'b1), + .TXFIFO_DTH (4096), + .RXFIFO_DTH (4096), + .PHY_INTF_MODE (0), + .AXIS_DW (8), + .RGMII_RXC_EDGE (1'b1), + .RGMII_TXC_DLY (1'b1), + .INTER_PACKET_GAP (6'd12), + .MTU_FRAME_LENGTH (16'd1518), + .MAC_SOURCE_ADDRESS (48'd0), + .ENABLE_BROADCAST_FILTERING (1'b1), + .LOOPBACK_EN (1'b1), + .APBIF (1'b0), + .FAMILY ("TITANIUM") +) +u_efx_mac1gbe +( + .mac_reset ( mac_reset ), + .proto_reset ( proto_reset ), + .rx_mac_aclk ( rx_mac_aclk ), + .tx_mac_aclk ( tx_mac_aclk ), + .eth_speed ( eth_speed ), + .rx_axis_clk ( rx_axis_clk ), + .rx_axis_mac_tuser ( rx_axis_mac_tuser ), + .rx_axis_mac_tlast ( rx_axis_mac_tlast ), + .rx_axis_mac_tvalid ( rx_axis_mac_tvalid ), + .rx_axis_mac_tready ( rx_axis_mac_tready ), + .tx_axis_clk ( tx_axis_clk ), + .tx_axis_mac_tvalid ( tx_axis_mac_tvalid ), + .tx_axis_mac_tlast ( tx_axis_mac_tlast ), + .tx_axis_mac_tuser ( tx_axis_mac_tuser ), + .tx_axis_mac_tready ( tx_axis_mac_tready ), + .rgmii_txd_HI ( rgmii_txd_HI ), + .rgmii_txd_LO ( rgmii_txd_LO ), + .rgmii_tx_ctl_HI ( rgmii_tx_ctl_HI ), + .rgmii_tx_ctl_LO ( rgmii_tx_ctl_LO ), + .rgmii_txc_HI ( rgmii_txc_HI ), + .rgmii_txc_LO ( rgmii_txc_LO ), + .rgmii_rxd_HI ( rgmii_rxd_HI ), + .rgmii_rxd_LO ( rgmii_rxd_LO ), + .rgmii_rx_ctl_HI ( rgmii_rx_ctl_HI ), + .rgmii_rx_ctl_LO ( rgmii_rx_ctl_LO ), + .rgmii_rxc ( rgmii_rxc ), + .s_axi_aclk ( s_axi_aclk ), + .rx_axis_mac_tdata ( rx_axis_mac_tdata ), + .tx_axis_mac_tdata ( tx_axis_mac_tdata ), + .tx_axis_mac_tstrb ( tx_axis_mac_tstrb ), + .rx_axis_mac_tstrb ( rx_axis_mac_tstrb ), + .MdoEn ( MdoEn ), + .Mdo ( Mdo ), + .Mdi ( Mdi ), + .Mdc ( Mdc ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arready ( s_axi_arready ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awready ( s_axi_awready ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rready ( s_axi_rready ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_wready ( s_axi_wready ), + .s_axi_wvalid ( s_axi_wvalid ) +); +endmodule + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_top) # ( + parameter FAMILY = "TRION", // New Param + parameter SYNC_CLK = 0, + parameter BYPASS_RESET_SYNC = 0, // New Param + parameter SYNC_STAGE = 2, // New Param + parameter MODE = "STANDARD", + parameter DEPTH = 512, // Reverted (Equivalent to WDATA_DEPTH) + parameter DATA_WIDTH = 32, // Reverted (Equivalent to WDATA_WIDTH) + parameter PIPELINE_REG = 1, // Reverted (By default is ON) + parameter OPTIONAL_FLAGS = 1, // Reverted + parameter OUTPUT_REG = 0, + parameter PROGRAMMABLE_FULL = "STATIC_DUAL", // Set to "NONE" if not require this feature + parameter PROG_FULL_ASSERT = 27, + parameter PROG_FULL_NEGATE = 23, + parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature + parameter PROG_EMPTY_ASSERT = 5, + parameter PROG_EMPTY_NEGATE = 7, + parameter ALMOST_FLAG = OPTIONAL_FLAGS, + parameter HANDSHAKE_FLAG = OPTIONAL_FLAGS, + parameter ASYM_WIDTH_RATIO = 4, + parameter WADDR_WIDTH = depth2width(DEPTH), + parameter RDATA_WIDTH = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH), + parameter RD_DEPTH = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH), + parameter RADDR_WIDTH = depth2width(RD_DEPTH), + parameter ENDIANESS = 0, + parameter OVERFLOW_PROTECT = 1, + parameter UNDERFLOW_PROTECT = 1, + parameter RAM_STYLE = "block_ram" + +)( + input wire a_rst_i, + input wire a_wr_rst_i, + input wire a_rd_rst_i, + input wire clk_i, + input wire wr_clk_i, + input wire rd_clk_i, + input wire wr_en_i, + input wire rd_en_i, + input wire [DATA_WIDTH-1:0] wdata, + output wire almost_full_o, + output wire prog_full_o, + output wire full_o, + output wire overflow_o, + output wire wr_ack_o, + output wire [WADDR_WIDTH :0] datacount_o, + output wire [WADDR_WIDTH :0] wr_datacount_o, + output wire empty_o, + output wire almost_empty_o, + output wire prog_empty_o, + output wire underflow_o, + output wire rd_valid_o, + output wire [RDATA_WIDTH-1:0] rdata, + output wire [RADDR_WIDTH :0] rd_datacount_o, + output wire rst_busy +); + +localparam WR_DEPTH = DEPTH; +localparam WDATA_WIDTH = DATA_WIDTH; +localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH) ? 1 : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH*8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32; + +wire wr_rst_int; +wire rd_rst_int; +wire wr_en_int; +wire rd_en_int; +wire [WADDR_WIDTH-1:0] waddr; +wire [RADDR_WIDTH-1:0] raddr; +wire wr_clk_int; +wire rd_clk_int; +wire [WADDR_WIDTH :0] wr_datacount_int; +wire [RADDR_WIDTH :0] rd_datacount_int; + +generate + if (ASYM_WIDTH_RATIO == 4) begin + if (SYNC_CLK) begin + assign wr_clk_int = clk_i; + assign rd_clk_int = clk_i; + assign datacount_o = wr_datacount_int; + assign wr_datacount_o = {(WADDR_WIDTH+1){1'b0}}; + assign rd_datacount_o = {(RADDR_WIDTH+1){1'b0}}; + end + else begin + assign wr_clk_int = wr_clk_i; + assign rd_clk_int = rd_clk_i; + assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; + assign wr_datacount_o = wr_datacount_int; + assign rd_datacount_o = rd_datacount_int; + end + end + else begin + assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; + assign wr_datacount_o = wr_datacount_int; + assign rd_datacount_o = rd_datacount_int; + if (SYNC_CLK) begin + assign wr_clk_int = clk_i; + assign rd_clk_int = clk_i; + end + else begin + assign wr_clk_int = wr_clk_i; + assign rd_clk_int = rd_clk_i; + end + end + + if (!SYNC_CLK) begin + //(* async_reg = "true" *) reg [1:0] wr_rst; + //(* async_reg = "true" *) reg [1:0] rd_rst; + // + //always @ (posedge wr_clk_int or posedge a_rst_i) begin + // if (a_rst_i) + // wr_rst <= 2'b11; + // else + // wr_rst <= {wr_rst[0],1'b0}; + //end + // + //always @ (posedge rd_clk_int or posedge a_rst_i) begin + // if (a_rst_i) + // rd_rst <= 2'b11; + // else + // rd_rst <= {rd_rst[0],1'b0}; + //end + + + if (BYPASS_RESET_SYNC) begin + assign wr_rst_int = a_wr_rst_i; + assign rd_rst_int = a_rd_rst_i; + assign rst_busy = 1'b0; + end + else begin + `IP_MODULE_NAME(efx_resetsync) #( + .ACTIVE_LOW (0) + ) efx_resetsync_wr_rst ( + .clk (wr_clk_int), + .reset (a_rst_i), + .d_o (wr_rst_int) + ); + + `IP_MODULE_NAME(efx_resetsync) #( + .ACTIVE_LOW (0) + ) efx_resetsync_rd_rst ( + .clk (rd_clk_int), + .reset (a_rst_i), + .d_o (rd_rst_int) + ); + assign rst_busy = wr_rst_int | rd_rst_int; + end + + end + else begin + //(* async_reg = "true" *) reg [1:0] a_rst; + // + //always @ (posedge clk_i or posedge a_rst_i) begin + // if (a_rst_i) + // a_rst <= 2'b11; + // else + // a_rst <= {a_rst[0],1'b0}; + //end + wire a_rst; + + `IP_MODULE_NAME(efx_resetsync) #( + .ACTIVE_LOW (0) + ) efx_resetsync_a_rst ( + .clk (clk_i), + .reset (a_rst_i), + .d_o (a_rst) + ); + + if (BYPASS_RESET_SYNC) begin + assign wr_rst_int = a_rst_i; + assign rd_rst_int = a_rst_i; + assign rst_busy = 1'b0; + end + else begin + assign wr_rst_int = a_rst; + assign rd_rst_int = a_rst; + assign rst_busy = wr_rst_int | rd_rst_int; + end + end +endgenerate + +`IP_MODULE_NAME(efx_fifo_ram) # ( + .FAMILY (FAMILY), + .WR_DEPTH (WR_DEPTH), + .RD_DEPTH (RD_DEPTH), + .WDATA_WIDTH (WDATA_WIDTH), + .RDATA_WIDTH (RDATA_WIDTH), + .WADDR_WIDTH (WADDR_WIDTH), + .RADDR_WIDTH (RADDR_WIDTH), + .OUTPUT_REG (OUTPUT_REG), + .RAM_MUX_RATIO (RAM_MUX_RATIO), + .ENDIANESS (ENDIANESS), + .RAM_STYLE (RAM_STYLE) +) xefx_fifo_ram ( + .wdata (wdata), + .waddr (waddr), + .raddr (raddr), + .we (wr_en_int), + .re (rd_en_int), + .wclk (wr_clk_int), + .rclk (rd_clk_int), + .rdata (rdata) +); + +`IP_MODULE_NAME(efx_fifo_ctl) # ( + .SYNC_CLK (SYNC_CLK), + .SYNC_STAGE (SYNC_STAGE), + .MODE (MODE), + .WR_DEPTH (WR_DEPTH), + .WADDR_WIDTH (WADDR_WIDTH), + .RADDR_WIDTH (RADDR_WIDTH), + .ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), + .RAM_MUX_RATIO (RAM_MUX_RATIO), + .PIPELINE_REG (PIPELINE_REG), + .ALMOST_FLAG (ALMOST_FLAG), + .PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), + .PROG_FULL_ASSERT (PROG_FULL_ASSERT), + .PROG_FULL_NEGATE (PROG_FULL_NEGATE), + .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), + .PROG_EMPTY_ASSERT (PROG_EMPTY_ASSERT), + .PROG_EMPTY_NEGATE (PROG_EMPTY_NEGATE), + .OUTPUT_REG (OUTPUT_REG), + .HANDSHAKE_FLAG (HANDSHAKE_FLAG), + .OVERFLOW_PROTECT (OVERFLOW_PROTECT), + .UNDERFLOW_PROTECT (UNDERFLOW_PROTECT) +) xefx_fifo_ctl ( + .wr_rst (wr_rst_int), + .rd_rst (rd_rst_int), + .wclk (wr_clk_int), + .rclk (rd_clk_int), + .we (wr_en_i), + .re (rd_en_i), + .wr_full (full_o), + .wr_ack (wr_ack_o), + .rd_empty (empty_o), + .wr_almost_full (almost_full_o), + .rd_almost_empty (almost_empty_o), + .wr_prog_full (prog_full_o), + .rd_prog_empty (prog_empty_o), + .wr_en_int (wr_en_int), + .rd_en_int (rd_en_int), + .waddr (waddr), + .raddr (raddr), + .wr_datacount (wr_datacount_int), + .rd_datacount (rd_datacount_int), + .rd_vld (rd_valid_o), + .wr_overflow (overflow_o), + .rd_underflow (underflow_o) +); + +function integer depth2width; +input [31:0] depth; +begin : fnDepth2Width + if (depth > 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian + parameter RAM_STYLE = "block_ram" +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + always @ (posedge wclk) begin + for (i=0; i 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_resetsync) #( + parameter ASYNC_STAGE = 2, + parameter ACTIVE_LOW = 1 +) ( + input wire clk, + input wire reset, + output wire d_o +); + + +generate + if (ACTIVE_LOW == 1) begin: active_low + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (1), + .RST_VALUE (0) + ) efx_resetsync_active_low ( + .clk (clk), + .reset_n (reset), + .d_i (1'b1), + .d_o (d_o) + ); + end + else begin: active_high + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (0), + .RST_VALUE (1) + ) efx_resetsync_active_high ( + .clk (clk), + .reset_n (reset), + .d_i (1'b0), + .d_o (d_o) + ); + end +endgenerate + +endmodule + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_asyncreg) #( + parameter ASYNC_STAGE = 2, + parameter WIDTH = 4, + parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset + parameter RST_VALUE = 0, + parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance +) ( + input wire clk, + input wire reset_n, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + + + + + + + + + + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect author = "author-a" , author_info = "author-a-details" +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V +o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE +El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY +kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc +/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 +uYJaS5tuGEuFInBHa7oO8g== +`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 +fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa +rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq +PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL +DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w +K3OoKmk3zFeArSsql8B4/Q== +`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 ) +`pragma protect key_block +RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M +GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l +6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI= +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf +RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk +1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw +Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz +eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0 +2HflB1HYKxojQCcZU7qUgQ== +`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx +Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB +rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr +XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD +e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod +B2Zpo2FQ//YDRSAaEa9ksQ== +`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze +vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 +ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 +06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP +fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN +ZoPzFCMjGk5ZmMyIlytNCw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 ) +`pragma protect data_block +0d33xo/2RnBYy8BD6jq1J42m9u/75PA0owNvxlnr0TDOq7sF8XT6xouctVD1XQW2 +Ylwj0urY+dCJZku0aGRpcvb3H/nTlKVdEZOEl4QqB1gNGz/3mz75A3eudu5zgHEr +MaagjyQfDnoIqLWi1r5uTZrlS298IvNcGAJ+xXzpmkFmfG4Tk/5Jf2GPAPVtjREI +01kt8Go4CL1WNxBKcwm0xCiCchxvZ2oEtpERiC+7LUalgTJapIVoLFpvFv98229k +egvgF1KHNj0rAKedSG2Xo58TyA4iZXJJDdtgCxiKgu3Rimjno7l+ekApwmvx8n+p +yHkRGqetWfRhyE4A5q03RzOeSdA6NbCqijB3NPw/p58brAbA35rrjYpGIZXtZ4mU +De3As8VtD64nS2PRuf4/a2lIcDbwMjNTfMpN7iJfVBJ0/48tLHdetx592TLXenkF +GvAZ2yxoyBYzKctj4Keo+19Xp1UjVd3fr2MR3A7nmxLRKDA+upDxQ7ql8+pR7Moh +0b53/4Ri3Mkl+7EC1KXJNt2VbkZmcT7OAFIoPpibmcXS2R6DNVrhSKzfc2+TRM9r +mwRrJy9/R5RR+WGfw1S57Ho3wBPf4belj+Tfd7yhnwOVRXkTMq5M1BiigrGeeQ3q +z/hc1Kg8b/R+g7lnU0pqASnExPQW/DIMfH1RX75U68CAgaBAH22Vcbkoibp8sxyO +g18LefEh48UffnbpCKyv7SQ3LAdj+YO+KvvXHj1eW+CH7GA2lC5vt2be5Ah2/13H +bCeZ+srG6r7wmafy9MNNh8AgjUfZWwMnuJdCIcHTOfAncCd2B0T1Oza4VIkvnSl5 +60V34JXkfrGsNuHxwCF/sRSBbZUSpqig4ZGYHjOHldx2OANZQeUvLES3fwScYY5D +7SpR4ofVxIB/ev/+RXzvC3MNk1N0GT4F1XwokeeQIr/ilRETe/pFvEKttvviZ7uJ +uEVblS2v61DMXEgDavkbA0WdhMChPulwDvZtisWT4hCKRxfuBvNBtz0wH/WgRoX3 +aipWvPJG3G0xvO0u0EQVNdcxE+LZ7vyGF5HWEwKdQYDyhH+yVDeG+M/b08dU2aq4 +sG7dyygyVnzVbk2Lf0nCkGqKkUZUr05Zim0Wcflkhkqy348SOZ3xmEGuYAkzelLV +feQ+0ScsscFL5Cq4ETfFrN8GO8M5kkBN2ELs1MQecPRsgMCh0hcvd8IQrJTybQPW +aqwp9mgnFvS8AJ1ct+XgrAt8zgVnhaZGS9TKa6OWbr0U+SD5m+/pXjNsZA2dni6b +85/PmQeWeAarE/+EaJn/hlP6y3x3R3ItU8Itf6SB50LZ17LAhIRSIYsa7LBBNWOk +ngFHcGBCJnqTJv3hdVqa9cYipZ98XCa8dqrtAM5Rkxwd6H8KxXA+B+PWEz/cQWlb +szi9u5ufmyaJp6PWhklroQkPJEorUtF96X763itgtlAMHfkZglkElUD/gPlkXLtl +yquUmHqPK5D2pJDq0Q0jromE2yrr9fl3OI+eBehd2YBUivGKeaDFkPx7HbzWp9ok +9bT55H8VKYyF1awcjNND+WcXzm2WfvZHBDUJkRm7dnOQRvcX2RxlPRZSzAA3irVn +GFbHXD0RYn/dUR7Vy4kU68P5S5q4bUxD5vmUCN9vDoCivY7WCnlQCHQs3+iFblzP +A636C3dNQMSw0pjDisiZB63VczY8bivFh3cO82inNw5r2IZjvMB9XPhc4FHuIpfR +F7ptW0TUnO1MSDcZvCnjUfVSnHN22l2FM/P5oI1SbG3W+8YmxBvto8jwpES4ohOQ +YSECrvWkLklq68FVTzB7Tvg3JLdSy3TEKBuZE/ot0w/SXusFovOwd4aeiNDAmzwl +fQuCYHuJ0UKLaVNVAO4mw91PJODKCk2NYTr0ghOLovOXiMhUYtXZ+wFchXVkQKDI +B8BXjM7P+blhoOFA6AhRuCX4gZn0dP6m99qnyBJoxf1/FyfJXuklnPll93amUYUx +MzxNNTf7F08tnKQ8pTOk2mfFZnhA2MFn4XQ9FaGvtUrlJI8bvJTWiZFMF0eOJdIw +kzYOXEzKBjIdWW4rtTZmQJb7AOrznUpYdgTAPip/DQx6cg1+tZAVwhZPCjCsb5wa +em5hMtISQKDc92QrlU5O74OXe7641fzFRcKqy9AzwhZl+tmHk1uvpDkpsYiMa7Rk +YrbIjsKQV36PTqYPvxq1EiwYF8PMRf9FG8JZk85EZdM6QEGuehDHqFcZ+SlUb7/e +ji6GgjKxcZwaRREGKSOslcscHS6QNuGCF3iInqNCT4V2l7nboWOefMT2f1kmQOdE +szTFg563SQ8pu7ok3T3XNqUDi5ulvF+XGHDhcQ2hTkZ+xQ8dHFAWZdgzEGMXF2Lw +jU+ZRA2JULfjxOMIU2j9f+aGWmFx2PELMA5K5uOWYUQG2Fn04p1D6u8MEe7fIPeI +k7KH8j/Tumj+kG4t/lCrme6VM9u6A2NGddX1yH1NCejfophy3UWJg9wL/dNxzf6t +vXdm3rGPdZPWFgSIuGlmT03QZmWGPbs8qvkkUVAL37kMJP2r4L+PI00ZxbX8V5jp +GgYN1Rh+NSOwAcUEFCViRhFYC+Gi5eZ6AF6XDSU6qfjGsUKqJ9yrNx0Km6+SjpAK +7Zxblp7vweFVkJ7IESoFeB+vP8JNeoidbBPGEWo+2V08PgfGgjPEAA6pjj8uc0jC +SDFZ0sVrzvc66PZ5FxbI4g+VuXPJgyJsnQ/eHhPVTVTP3/oGMRVktNiJrkJYxAW7 +Sa/EJMjfXX+rMIWG5ssWLT6WfrojlHduEqJ9hJr24RZy514HHF8SMPRBLD6l1wd5 +07U/ChjFdy5qHn5Ce+lanjxnoxgvCsF3lMqoZ7e2bfzXakj7CxahwqRt6yeU0Q+/ +a8tvIJgHfdtOPw/r6HnSrzpdWzTx2e6/MEryHZqpMN63Lhakpjw1L7u3FD/rW40b +LGajigQ7Ql+cZmP7wYl+uSmTFIS6ZgXOc1ibb7yYxJwpeixPHL1iu5ltvriRiTZ6 +DMbbOjNpPuL7ie3AwgmwXwnpnTL6k/Rj2+ma3B7ImODBMkC4SLtTc0ynCcPAFZKA +Xh78wUAgt1T5Nm4XR555DBO7zPHX9rZzMLil4/j0RMDwn1gitmP2PSNFWsrXJG8p +C46kfpdqoM3Yf6HySlhsith6GW41sMF6imUXwahQQRw240HLW3N876LDe6bjTmgN +eIC7y/4NZk7OmpmP8udAEH+UsNfSGtKA8959AoJDr43XsWkOfccNWstu4sTXA5+w +pCALypmBMdholEsrW9DgsIgbgf2pcOAC9+mAjld+yyQ+UNdKRbmtRDHTztGmcVvw +Szip4YUuTM1tPzReucfm38gVFT7eo1qFQg/FJ4VgeYab7ku5OHuwZQmKyzng/t0U +A1lquVENVYQEIotBiOC7jQ1YTkTasGN4xoFgFTyKLFPyk8bl2/anzr1Fx0ieVGCx +2ipzG2JzIQf/FlHXaYrgkWiF817amty+KZp4/dCJtvDXxzOZKnBTVcjHXpqR1Ik+ +tdV+k+21tXZxP0rkG0yi4//2c5UiWGb0UegpemqutykLuT9tGjsqMuc5DaDH/8zk +wLTVfODT+HqN1/ZLqfq9VoAF5m/ujnPNt3wZcsjsAyBD153rW4Q2yVYMat0sFQN6 +XbNAeNBJZlO/aE1PfKBcSDFkJkPqRxlgdiE5B83/w1MP6Z4qwz7LJ8yTYM22xwRo +LIYpKq52yYMhJm42YeQxbBRTx0MyubCb+ompEVBF28Eh0vE98UAZj7t1szSweg99 +Wq6/4kxR2SQj8rFo2wrZe7ngsDmbIrMk2SinS6WmV4Mj+MBbPlmiuwB6NUV04Id1 +9enBBsJIfWt+PZJXyWkOoG/fOVBUxCY+CMCiab0qQ1EVdhggrdI30BgFqcLjfyD6 +/h5AqIzMGWrhWnap8WDEh1Ah6K9f2oCESSXO751sV5eK8jgl63FJMIVsnjVejxrl +Qa7PCXP3BO6Cnv896NBzAsddPq/AYBLHIC6eX3sTtOxTx52NsmJzoyUSJcAoA/QS +leHU1bLA2z+HGfMrkSzsuvXafmqr3B+PHfWdxrYzTxmVhMBPX/FvEU/gfxXGa6kj +niZYGue/Rk+zXL65ENgPwxiz0mm7QyQ6eMBMRovm6MGyIl/8obkOPygH+lhc+bgR +SNWLmxqjR2YABrKsUgCITQ6GK7VmVR3wOOwbZs+YW/0Yj2yzg7ESjaeqI40/OQFD +Ft2IHaURJPk6jl5vRrcCc0J0GCy7CK0BU14n+Nxfl2+CFRe4efoqZry/CmY2+S4M +p9OqgjUzHGSIbNRAXHf44nIAUjWYvijzzLSj9A7WY3TpYxgtqU8Wbf7SbWmw8RJV +pAYDHGmwHa8fL4Y9xEFF/WqmqWSL3g146i41MKWKY7lchvnWtc6yOgk+0geVFOpe +9BLs4TehFA/SueFC99S0Cxcxc0KMWXOKm0I3bI1CAlLje7wUcdI/pki33iqBLJlL +T2vz8ptPqfgAxDW0ZEvEYY/jfB+jCO0MKT7XK/LZNYSuEke3Y3CeuwZ/5IWkDcwy +7BArmDy7Hpw88le9ODL94mS1fUB8jsBaazeiXniZPNZjBkugt/ZAf4XYuoaGVPAM +DnRd8GW5eiDHFCEB42lpg9n7Ak8cXsSSlODCHeay2VtcQP1DEgwWdI5XdXE879gI +8lLU9bH2MfsxI2mNWCMv5immaioZJDorIVzyMGvIn3OcgqmhTU1owINUJf+Hm8Q7 +JfJq4m6t0J5eoKQH57uSGFkWRZ3dtp5QL3d5bBOMmorXUBzdrLt8wurvNke29bHD +UQdmANjayV8drYWAccZdPWyi9jNC/K31BTDI6RCpZdV3Wr5scOZdXWrl961jirm1 +g/2MGKxriuH2F4MRIh2vp3uS8PLbj4cHJv+5+LtLgs0lpdEMYAvJKDACRg68tDhY +XsF9lhHpcF5+tANOawRtnSvy/rlLn+A3wi7v8tnTZcLkocJ51c+nK5/Ij0YgUrA0 +eLrKNlJM78stswPWkvpBlAJ+G3D4Cw6P3XcJWrLyV3u79jf9PRJZmxMU/COGTmgQ +PJdXp90O3u2Pjdwhp4VdtBK2d/jTpk59j8xbQBavf5flZ+PzoLpd8NSt6GdPVJ5r +uVWvNy14pJXUsn+Tgxj+9Wp3vm5mofWtJAkEgr/Rfp7AVLLShJSd6vsbT7F2+TS/ +OMDv0XH92v1G4tqJ0rbxS1TnxX61+1sfjKlfIQdFR9gxLy71Tb705LQHBAw8vmSx +X6Uv+HbtPaEqRCF+pdvGsLNI2Seo6INA/mXqNpd6VPhfQHtp3bgV+Hxnlcc9lCiI +bCZq6KG4a6sVQHIZ3pZo7PQtoAo22niHvgZFoOVnBv+bu+blmvSV6gxCPoV8rwOe +/WD7YikHE7WVSq1SHtTIcbPv+K+1NKqZIiSCS2qDfJLgI7vH4zjIqibDhzGZTeKV +Km234SSlJ1OL4WQ5FtsxjednjUIAKqVe1auDiTzAKY28dwUkwGN/XXQ+EjrmxQuL +qIAT3WP49EeM+CQCp3D6Vxzm7Picq+RtwtbAXnnSQtvPcaSprODI089a0iR46Pp/ +4DLMUOLS+01HozXF1589YdqYep05No/Fp4eP2RdQxicYxK8d/OcvG7E8F1URVmAa +XdZxVa9caM3xYMWDZaiaOo6IZ+YM5VeZ4KxUblS1L1IlOnGOOZ3AiaLsHOh55ryc +Ei7EaFpheCmlTJyxUg8TdA== +`pragma protect end_protected + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ctl) # ( + parameter SYNC_CLK = 1, + parameter SYNC_STAGE = 2, + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter ASYM_WIDTH_RATIO = 4, + parameter RAM_MUX_RATIO = 1, + parameter PIPELINE_REG = 1, + parameter ALMOST_FLAG = 1, + parameter PROGRAMMABLE_FULL = "NONE", + parameter PROG_FULL_ASSERT = 0, + parameter PROG_FULL_NEGATE = 0, + parameter PROGRAMMABLE_EMPTY = "NONE", + parameter PROG_EMPTY_ASSERT = 0, + parameter PROG_EMPTY_NEGATE = 0, + parameter OUTPUT_REG = 0, + parameter HANDSHAKE_FLAG = 1, + parameter OVERFLOW_PROTECT = 0, + parameter UNDERFLOW_PROTECT = 0 +)( + input wire wr_rst, + input wire rd_rst, + input wire wclk, + input wire rclk, + input wire we, + input wire re, + output wire wr_full, + output reg wr_ack, + output wire wr_almost_full, + output wire rd_empty, + output wire rd_almost_empty, + output wire wr_prog_full, + output wire rd_prog_empty, + output wire wr_en_int, + output wire rd_en_int, + output wire [WADDR_WIDTH-1:0] waddr, + output wire [RADDR_WIDTH-1:0] raddr, + output wire [WADDR_WIDTH:0] wr_datacount, + output wire [RADDR_WIDTH:0] rd_datacount, + output wire rd_vld, + output reg wr_overflow, + output reg rd_underflow +); + +reg [WADDR_WIDTH:0] waddr_cntr; +reg [WADDR_WIDTH:0] waddr_cntr_r; +reg [RADDR_WIDTH:0] raddr_cntr; +reg rd_valid; + +wire [WADDR_WIDTH:0] waddr_int; +wire [RADDR_WIDTH:0] raddr_int; +wire rd_empty_int; +wire [WADDR_WIDTH:0] wr_datacount_int; +wire [RADDR_WIDTH:0] rd_datacount_int; + +assign waddr = waddr_cntr[WADDR_WIDTH-1:0]; +// NIC +wire [RADDR_WIDTH:0] ram_raddr; +assign raddr = (MODE == "FWFT") ? ram_raddr[RADDR_WIDTH-1:0] : raddr_cntr[RADDR_WIDTH-1:0]; +//assign raddr = raddr_cntr[RADDR_WIDTH-1:0]; +//assign wr_en_int = we & ~wr_full; +assign wr_en_int = OVERFLOW_PROTECT ? we & ~wr_full : we; + +assign wr_datacount = wr_datacount_int; +assign rd_datacount = ASYM_WIDTH_RATIO == 4 && SYNC_CLK ? wr_datacount_int : rd_datacount_int; + + +generate + if (MODE == "FWFT") begin + // NIC + //assign rd_en_int = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int); + //assign rd_empty = rd_empty_fwft; + + assign rd_en_int = 1'b1; + //assign rd_empty = rd_empty_int; + + //always @ (posedge rclk or posedge rd_rst) begin + // if (rd_rst) begin + // init_set <= 1'b1; + // end + // else if (~init_set & rd_empty) begin + // init_set <= 1'b1; + // end + // else if (~rd_empty_int) begin + // init_set <= 1'b0; + // end + // else if (rd_empty) begin + // init_set <= 1'b1; + // end + //end + // NIC + //always @ (posedge rclk or posedge rd_rst) begin + // if (rd_rst) begin + // rd_empty_fwft <= 1'b1; + // end + // else if (rd_en_int) begin + // rd_empty_fwft <= 1'b0; + // end + // else if (re) begin + // rd_empty_fwft <= 1'b1; + // end + //end + + //if (FAMILY == "TRION") begin + if (OUTPUT_REG) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid <= 1'b0; + end + else begin + rd_valid <= ~rd_empty; + end + end + assign rd_vld = rd_valid; + end + else begin + assign rd_vld = ~rd_empty; + end + + assign rd_empty = rd_empty_int; + end + else begin + assign rd_en_int = UNDERFLOW_PROTECT ? re & ~rd_empty_int : re; + assign rd_empty = rd_empty_int; + + if (OUTPUT_REG) begin + reg rd_valid_r; + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid_r <= 'h0; + rd_valid <= 'h0; + end + else begin + {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int}; + end + end + assign rd_vld = rd_valid; + end + else begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid <= 'h0; + end + else begin + rd_valid <= rd_en_int; + end + end + assign rd_vld = rd_valid; + end + end + + if (ALMOST_FLAG) begin + assign wr_almost_full = wr_datacount >= WR_DEPTH-1; + assign rd_almost_empty = rd_datacount <= 'd1; + end + else begin + assign wr_almost_full = 1'b0; + assign rd_almost_empty = 1'b0; + end + + if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + // NIC + //wr_ack <= wr_en_int & ~wr_overflow; + wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; + end + end + end + + if (OVERFLOW_PROTECT) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else begin + wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; + end + end + end + + if (UNDERFLOW_PROTECT) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else begin + rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + // NIC + else if (ASYM_WIDTH_RATIO == 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - raddr_int; + assign rd_datacount_int = waddr_int - raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + // NIC + //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_r <= 'h0; + end + else begin + waddr_cntr_r <= waddr_cntr; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + end + // NIC + //else if (rd_en_int) begin + else begin + //raddr_cntr <= raddr_cntr + 1'b1; + //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); + raddr_cntr <= ram_raddr; + end +end +// NIC +assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); + + +generate + if (SYNC_CLK) begin : sync_clk + if (MODE == "FWFT") begin + assign waddr_int = waddr_cntr_r; + assign raddr_int = raddr_cntr; + end + else begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr; + end + end + else begin : async_clk + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx>> 2); + assign _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask_1 = ({3'd0,_zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask} <<< system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address[1 : 0]); + BufferCC_2_b62b14ffe6bb44e5a817b8d08e286c6b bufferCC_5 ( + .io_dataIn (1'b0 ), //i + .io_dataOut (bufferCC_5_io_dataOut), //o + .io_systemClk (io_systemClk ), //i + .io_asyncReset (io_asyncReset ) //i + ); + BufferCC_3_b62b14ffe6bb44e5a817b8d08e286c6b bufferCC_6 ( + .io_dataIn (1'b0 ), //i + .io_dataOut (bufferCC_6_io_dataOut ), //o + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset) //i + ); + VexRiscv_b62b14ffe6bb44e5a817b8d08e286c6b system_cores_0_logic_cpu ( + .dBus_cmd_valid (system_cores_0_logic_cpu_dBus_cmd_valid ), //o + .dBus_cmd_ready (system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready ), //i + .dBus_cmd_payload_wr (system_cores_0_logic_cpu_dBus_cmd_payload_wr ), //o + .dBus_cmd_payload_uncached (system_cores_0_logic_cpu_dBus_cmd_payload_uncached ), //o + .dBus_cmd_payload_address (system_cores_0_logic_cpu_dBus_cmd_payload_address[31:0] ), //o + .dBus_cmd_payload_data (system_cores_0_logic_cpu_dBus_cmd_payload_data[31:0] ), //o + .dBus_cmd_payload_mask (system_cores_0_logic_cpu_dBus_cmd_payload_mask[3:0] ), //o + .dBus_cmd_payload_size (system_cores_0_logic_cpu_dBus_cmd_payload_size[2:0] ), //o + .dBus_cmd_payload_last (system_cores_0_logic_cpu_dBus_cmd_payload_last ), //o + .dBus_rsp_valid (system_cores_0_logic_cpu_dBus_rsp_valid ), //i + .dBus_rsp_payload_last (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_last ), //i + .dBus_rsp_payload_data (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_data[31:0]), //i + .dBus_rsp_payload_error (system_cores_0_logic_cpu_dBus_rsp_payload_error ), //i + .timerInterrupt (_zz_timerInterrupt ), //i + .externalInterrupt (system_cores_0_externalInterrupt_plic_target_iep_regNext ), //i + .softwareInterrupt (_zz_softwareInterrupt ), //i + .debug_bus_cmd_valid (system_cores_0_debugBmb_cmd_valid ), //i + .debug_bus_cmd_ready (system_cores_0_logic_cpu_debug_bus_cmd_ready ), //o + .debug_bus_cmd_payload_wr (system_cores_0_logic_cpu_debug_bus_cmd_payload_wr ), //i + .debug_bus_cmd_payload_address (system_cores_0_debugBmb_cmd_payload_fragment_address[7:0] ), //i + .debug_bus_cmd_payload_data (system_cores_0_debugBmb_cmd_payload_fragment_data[31:0] ), //i + .debug_bus_rsp_data (system_cores_0_logic_cpu_debug_bus_rsp_data[31:0] ), //o + .debug_resetOut (system_cores_0_logic_cpu_debug_resetOut ), //o + .iBus_cmd_valid (system_cores_0_logic_cpu_iBus_cmd_valid ), //o + .iBus_cmd_ready (system_cores_0_iBus_cmd_ready ), //i + .iBus_cmd_payload_address (system_cores_0_logic_cpu_iBus_cmd_payload_address[31:0] ), //o + .iBus_cmd_payload_size (system_cores_0_logic_cpu_iBus_cmd_payload_size[2:0] ), //o + .iBus_rsp_valid (system_cores_0_iBus_rsp_valid ), //i + .iBus_rsp_payload_data (system_cores_0_iBus_rsp_payload_fragment_data[31:0] ), //i + .iBus_rsp_payload_error (system_cores_0_logic_cpu_iBus_rsp_payload_error ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i + ); + JtagBridgeNoTap_b62b14ffe6bb44e5a817b8d08e286c6b system_hardJtag_debug_logic_jtagBridge ( + .io_ctrl_tdi (jtagCtrl_tdi ), //i + .io_ctrl_enable (jtagCtrl_enable ), //i + .io_ctrl_capture (jtagCtrl_capture ), //i + .io_ctrl_shift (jtagCtrl_shift ), //i + .io_ctrl_update (jtagCtrl_update ), //i + .io_ctrl_reset (jtagCtrl_reset ), //i + .io_ctrl_tdo (system_hardJtag_debug_logic_jtagBridge_io_ctrl_tdo ), //o + .io_remote_cmd_valid (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_valid ), //o + .io_remote_cmd_ready (system_hardJtag_debug_logic_debugger_io_remote_cmd_ready ), //i + .io_remote_cmd_payload_last (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_last ), //o + .io_remote_cmd_payload_fragment (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_fragment), //o + .io_remote_rsp_valid (system_hardJtag_debug_logic_debugger_io_remote_rsp_valid ), //i + .io_remote_rsp_ready (system_hardJtag_debug_logic_jtagBridge_io_remote_rsp_ready ), //o + .io_remote_rsp_payload_error (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_error ), //i + .io_remote_rsp_payload_data (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_data[31:0]), //i + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ), //i + .jtagCtrl_tck (jtagCtrl_tck ) //i + ); + SystemDebugger_b62b14ffe6bb44e5a817b8d08e286c6b system_hardJtag_debug_logic_debugger ( + .io_remote_cmd_valid (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_valid ), //i + .io_remote_cmd_ready (system_hardJtag_debug_logic_debugger_io_remote_cmd_ready ), //o + .io_remote_cmd_payload_last (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_last ), //i + .io_remote_cmd_payload_fragment (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_fragment), //i + .io_remote_rsp_valid (system_hardJtag_debug_logic_debugger_io_remote_rsp_valid ), //o + .io_remote_rsp_ready (system_hardJtag_debug_logic_jtagBridge_io_remote_rsp_ready ), //i + .io_remote_rsp_payload_error (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_error ), //o + .io_remote_rsp_payload_data (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_data[31:0]), //o + .io_mem_cmd_valid (system_hardJtag_debug_logic_debugger_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (system_hardJtag_debug_logic_mmMaster_cmd_ready ), //i + .io_mem_cmd_payload_address (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address[31:0]), //o + .io_mem_cmd_payload_data (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_wr (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_size (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_size[1:0] ), //o + .io_mem_rsp_valid (system_hardJtag_debug_logic_mmMaster_rsp_valid ), //i + .io_mem_rsp_payload (system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_data[31:0] ), //i + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i + ); + BufferCC_4_b62b14ffe6bb44e5a817b8d08e286c6b bufferCC_7 ( + .io_dataIn (1'b0 ), //i + .io_dataOut (bufferCC_7_io_dataOut ), //o + .io_systemClk (io_systemClk ), //i + .system_cores_0_debugReset (system_cores_0_debugReset) //i + ); + BmbDecoder_b62b14ffe6bb44e5a817b8d08e286c6b bmbDecoder_4 ( + .io_input_cmd_valid (system_hardJtag_debug_bmb_connector_decoder_cmd_valid ), //i + .io_input_cmd_ready (bmbDecoder_4_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_length[1:0] ), //i + .io_input_cmd_payload_fragment_data (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_mask[3:0] ), //i + .io_input_rsp_valid (bmbDecoder_4_io_input_rsp_valid ), //o + .io_input_rsp_ready (system_hardJtag_debug_bmb_connector_decoder_rsp_ready ), //i + .io_input_rsp_payload_last (bmbDecoder_4_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (bmbDecoder_4_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (bmbDecoder_4_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_valid (bmbDecoder_4_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i + .io_outputs_0_cmd_payload_last (bmbDecoder_4_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_opcode (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_address[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_length (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_0_cmd_payload_fragment_data (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_mask (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_0_rsp_valid (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i + .io_outputs_0_rsp_ready (bmbDecoder_4_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i + .io_outputs_0_rsp_payload_fragment_opcode (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i + .io_outputs_0_rsp_payload_fragment_data (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0]), //i + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i + ); + BmbExclusiveMonitor_b62b14ffe6bb44e5a817b8d08e286c6b system_fabric_exclusiveMonitor_logic ( + .io_input_cmd_valid (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid ), //i + .io_input_cmd_ready (system_fabric_exclusiveMonitor_logic_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_address[31:0]), //i + .io_input_cmd_payload_fragment_length (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_length[5:0] ), //i + .io_input_cmd_payload_fragment_data (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_context ), //i + .io_input_rsp_valid (system_fabric_exclusiveMonitor_logic_io_input_rsp_valid ), //o + .io_input_rsp_ready (_zz_io_input_rsp_ready ), //i + .io_input_rsp_payload_last (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_context ), //o + .io_output_cmd_valid (system_fabric_exclusiveMonitor_logic_io_output_cmd_valid ), //o + .io_output_cmd_ready (system_fabric_exclusiveMonitor_output_connector_decoder_cmd_ready ), //i + .io_output_cmd_payload_last (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_length[5:0] ), //o + .io_output_cmd_payload_fragment_data (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_data[31:0] ), //o + .io_output_cmd_payload_fragment_mask (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_mask[3:0] ), //o + .io_output_cmd_payload_fragment_context (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_context ), //o + .io_output_rsp_valid (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_valid ), //i + .io_output_rsp_ready (system_fabric_exclusiveMonitor_logic_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_data[31:0] ), //i + .io_output_rsp_payload_fragment_context (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_context ) //i + ); + BmbDecoder_1_b62b14ffe6bb44e5a817b8d08e286c6b system_fabric_iBus_bmb_decoder ( + .io_input_cmd_valid (system_fabric_iBus_bmb_cmd_m2sPipe_valid ), //i + .io_input_cmd_ready (system_fabric_iBus_bmb_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_fabric_iBus_bmb_cmd_m2sPipe_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_length[5:0] ), //i + .io_input_rsp_valid (system_fabric_iBus_bmb_decoder_io_input_rsp_valid ), //o + .io_input_rsp_ready (system_fabric_iBus_bmb_rsp_ready ), //i + .io_input_rsp_payload_last (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_valid (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (system_bridge_bmb_arbiter_io_inputs_1_cmd_ready ), //i + .io_outputs_0_cmd_payload_last (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0]), //o + .io_outputs_0_cmd_payload_fragment_length (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //o + .io_outputs_0_rsp_valid (system_bridge_bmb_arbiter_io_inputs_1_rsp_valid ), //i + .io_outputs_0_rsp_ready (system_fabric_iBus_bmb_decoder_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_last ), //i + .io_outputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //i + .io_outputs_0_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_data[31:0] ) //i + ); + BmbArbiter_b62b14ffe6bb44e5a817b8d08e286c6b system_bridge_bmb_arbiter ( + .io_inputs_0_cmd_valid (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid ), //i + .io_inputs_0_cmd_ready (system_bridge_bmb_arbiter_io_inputs_0_cmd_ready ), //o + .io_inputs_0_cmd_payload_last (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last ), //i + .io_inputs_0_cmd_payload_fragment_opcode (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode ), //i + .io_inputs_0_cmd_payload_fragment_address (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address[31:0]), //i + .io_inputs_0_cmd_payload_fragment_length (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length[5:0] ), //i + .io_inputs_0_cmd_payload_fragment_data (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data[31:0] ), //i + .io_inputs_0_cmd_payload_fragment_mask (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask[3:0] ), //i + .io_inputs_0_cmd_payload_fragment_context (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context ), //i + .io_inputs_0_rsp_valid (system_bridge_bmb_arbiter_io_inputs_0_rsp_valid ), //o + .io_inputs_0_rsp_ready (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready ), //i + .io_inputs_0_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_last ), //o + .io_inputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_opcode ), //o + .io_inputs_0_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_data[31:0] ), //o + .io_inputs_0_rsp_payload_fragment_context (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_context ), //o + .io_inputs_1_cmd_valid (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_valid ), //i + .io_inputs_1_cmd_ready (system_bridge_bmb_arbiter_io_inputs_1_cmd_ready ), //o + .io_inputs_1_cmd_payload_last (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_last ), //i + .io_inputs_1_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //i + .io_inputs_1_cmd_payload_fragment_address (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_1_cmd_payload_fragment_length (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //i + .io_inputs_1_cmd_payload_fragment_data (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ), //i + .io_inputs_1_cmd_payload_fragment_mask (4'bxxxx ), //i + .io_inputs_1_rsp_valid (system_bridge_bmb_arbiter_io_inputs_1_rsp_valid ), //o + .io_inputs_1_rsp_ready (system_fabric_iBus_bmb_decoder_io_outputs_0_rsp_ready ), //i + .io_inputs_1_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_last ), //o + .io_inputs_1_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //o + .io_inputs_1_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_data[31:0] ), //o + .io_output_cmd_valid (system_bridge_bmb_arbiter_io_output_cmd_valid ), //o + .io_output_cmd_ready (system_bridge_bmb_cmd_ready ), //i + .io_output_cmd_payload_last (system_bridge_bmb_arbiter_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_source (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_source ), //o + .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_length[5:0] ), //o + .io_output_cmd_payload_fragment_data (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_data[31:0] ), //o + .io_output_cmd_payload_fragment_mask (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_mask[3:0] ), //o + .io_output_cmd_payload_fragment_context (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_context ), //o + .io_output_rsp_valid (system_bridge_bmb_rsp_valid ), //i + .io_output_rsp_ready (system_bridge_bmb_arbiter_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (system_bridge_bmb_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_source (system_bridge_bmb_rsp_payload_fragment_source ), //i + .io_output_rsp_payload_fragment_opcode (system_bridge_bmb_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (system_bridge_bmb_rsp_payload_fragment_data[31:0] ), //i + .io_output_rsp_payload_fragment_context (system_bridge_bmb_rsp_payload_fragment_context ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbDecoder_2_b62b14ffe6bb44e5a817b8d08e286c6b system_bridge_bmb_decoder ( + .io_input_cmd_valid (system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid ), //i + .io_input_cmd_ready (system_bridge_bmb_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_last ), //i + .io_input_cmd_payload_fragment_source (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_length[5:0] ), //i + .io_input_cmd_payload_fragment_data (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_context ), //i + .io_input_rsp_valid (system_bridge_bmb_decoder_io_input_rsp_valid ), //o + .io_input_rsp_ready (system_bridge_bmb_rsp_ready ), //i + .io_input_rsp_payload_last (system_bridge_bmb_decoder_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_context ), //o + .io_outputs_0_cmd_valid (system_bridge_bmb_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (system_bridge_bmb_unburstify_1_io_input_cmd_ready ), //i + .io_outputs_0_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_source ), //o + .io_outputs_0_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0]), //o + .io_outputs_0_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //o + .io_outputs_0_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_0_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_context ), //o + .io_outputs_0_rsp_valid (system_bridge_bmb_unburstify_1_io_input_rsp_valid ), //i + .io_outputs_0_rsp_ready (system_bridge_bmb_decoder_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (system_bridge_bmb_unburstify_1_io_input_rsp_payload_last ), //i + .io_outputs_0_rsp_payload_fragment_source (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_source ), //i + .io_outputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_opcode ), //i + .io_outputs_0_rsp_payload_fragment_data (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_data[31:0] ), //i + .io_outputs_0_rsp_payload_fragment_context (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_context ), //i + .io_outputs_1_cmd_valid (system_bridge_bmb_decoder_io_outputs_1_cmd_valid ), //o + .io_outputs_1_cmd_ready (system_bridge_bmb_unburstify_io_input_cmd_ready ), //i + .io_outputs_1_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_last ), //o + .io_outputs_1_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_source ), //o + .io_outputs_1_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //o + .io_outputs_1_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[31:0]), //o + .io_outputs_1_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[5:0] ), //o + .io_outputs_1_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_1_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_1_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_context ), //o + .io_outputs_1_rsp_valid (system_bridge_bmb_unburstify_io_input_rsp_valid ), //i + .io_outputs_1_rsp_ready (system_bridge_bmb_decoder_io_outputs_1_rsp_ready ), //o + .io_outputs_1_rsp_payload_last (system_bridge_bmb_unburstify_io_input_rsp_payload_last ), //i + .io_outputs_1_rsp_payload_fragment_source (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_source ), //i + .io_outputs_1_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_opcode ), //i + .io_outputs_1_rsp_payload_fragment_data (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //i + .io_outputs_1_rsp_payload_fragment_context (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_context ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbOnChipRam_b62b14ffe6bb44e5a817b8d08e286c6b system_ramA_logic ( + .io_bus_cmd_valid (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_valid ), //i + .io_bus_cmd_ready (system_ramA_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_address[14:0]), //i + .io_bus_cmd_payload_fragment_length (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_mask (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_mask[3:0] ), //i + .io_bus_cmd_payload_fragment_context (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_context[3:0] ), //i + .io_bus_rsp_valid (system_ramA_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (_zz_io_bus_rsp_ready ), //i + .io_bus_rsp_payload_last (system_ramA_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_ramA_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_ramA_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_ramA_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbUnburstify_b62b14ffe6bb44e5a817b8d08e286c6b system_bridge_bmb_unburstify ( + .io_input_cmd_valid (system_bridge_bmb_decoder_io_outputs_1_cmd_valid ), //i + .io_input_cmd_ready (system_bridge_bmb_unburstify_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[5:0] ), //i + .io_input_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_context ), //i + .io_input_rsp_valid (system_bridge_bmb_unburstify_io_input_rsp_valid ), //o + .io_input_rsp_ready (system_bridge_bmb_decoder_io_outputs_1_rsp_ready ), //i + .io_input_rsp_payload_last (system_bridge_bmb_unburstify_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_context ), //o + .io_output_cmd_valid (system_bridge_bmb_unburstify_io_output_cmd_valid ), //o + .io_output_cmd_ready (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i + .io_output_cmd_payload_last (system_bridge_bmb_unburstify_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_length[1:0] ), //o + .io_output_cmd_payload_fragment_data (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_data[31:0] ), //o + .io_output_cmd_payload_fragment_mask (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_mask[3:0] ), //o + .io_output_cmd_payload_fragment_context (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_context[3:0] ), //o + .io_output_rsp_valid (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i + .io_output_rsp_ready (system_bridge_bmb_unburstify_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0] ), //i + .io_output_rsp_payload_fragment_context (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context[3:0]), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbUnburstify_b62b14ffe6bb44e5a817b8d08e286c6b system_bridge_bmb_unburstify_1 ( + .io_input_cmd_valid (system_bridge_bmb_decoder_io_outputs_0_cmd_valid ), //i + .io_input_cmd_ready (system_bridge_bmb_unburstify_1_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //i + .io_input_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_context ), //i + .io_input_rsp_valid (system_bridge_bmb_unburstify_1_io_input_rsp_valid ), //o + .io_input_rsp_ready (system_bridge_bmb_decoder_io_outputs_0_rsp_ready ), //i + .io_input_rsp_payload_last (system_bridge_bmb_unburstify_1_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_context ), //o + .io_output_cmd_valid (system_bridge_bmb_unburstify_1_io_output_cmd_valid ), //o + .io_output_cmd_ready (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i + .io_output_cmd_payload_last (system_bridge_bmb_unburstify_1_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_length[1:0] ), //o + .io_output_cmd_payload_fragment_data (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_data[31:0] ), //o + .io_output_cmd_payload_fragment_mask (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_mask[3:0] ), //o + .io_output_cmd_payload_fragment_context (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_context[3:0] ), //o + .io_output_rsp_valid (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i + .io_output_rsp_ready (system_bridge_bmb_unburstify_1_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0] ), //i + .io_output_rsp_payload_fragment_context (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context[3:0]), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbDecoder_3_b62b14ffe6bb44e5a817b8d08e286c6b system_bmbPeripheral_bmb_decoder ( + .io_input_cmd_valid (system_bmbPeripheral_bmb_cmd_combStage_valid ), //i + .io_input_cmd_ready (system_bmbPeripheral_bmb_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_bmbPeripheral_bmb_cmd_combStage_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_address[23:0] ), //i + .io_input_cmd_payload_fragment_length (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_length[1:0] ), //i + .io_input_cmd_payload_fragment_data (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_context[3:0] ), //i + .io_input_rsp_valid (system_bmbPeripheral_bmb_decoder_io_input_rsp_valid ), //o + .io_input_rsp_ready (_zz_io_input_rsp_ready_1 ), //i + .io_input_rsp_payload_last (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context[3:0] ), //o + .io_outputs_0_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_4 ), //i + .io_outputs_0_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[23:0]), //o + .io_outputs_0_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_0_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_0_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context[3:0] ), //o + .io_outputs_0_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_4 ), //i + .io_outputs_0_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 ), //i + .io_outputs_0_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 ), //i + .io_outputs_0_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4[31:0] ), //i + .io_outputs_0_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4[3:0] ), //i + .io_outputs_1_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid ), //o + .io_outputs_1_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready ), //i + .io_outputs_1_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last ), //o + .io_outputs_1_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //o + .io_outputs_1_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[23:0]), //o + .io_outputs_1_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_1_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_1_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_1_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context[3:0] ), //o + .io_outputs_1_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid ), //i + .io_outputs_1_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready ), //o + .io_outputs_1_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last ), //i + .io_outputs_1_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode ), //i + .io_outputs_1_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data[31:0] ), //i + .io_outputs_1_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context[3:0] ), //i + .io_outputs_2_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid ), //o + .io_outputs_2_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_1 ), //i + .io_outputs_2_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last ), //o + .io_outputs_2_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode ), //o + .io_outputs_2_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address[23:0]), //o + .io_outputs_2_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_2_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_2_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_2_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context[3:0] ), //o + .io_outputs_2_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_1 ), //i + .io_outputs_2_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready ), //o + .io_outputs_2_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 ), //i + .io_outputs_2_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 ), //i + .io_outputs_2_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1[31:0] ), //i + .io_outputs_2_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1[3:0] ), //i + .io_outputs_3_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid ), //o + .io_outputs_3_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_2 ), //i + .io_outputs_3_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last ), //o + .io_outputs_3_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode ), //o + .io_outputs_3_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address[23:0]), //o + .io_outputs_3_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_3_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_3_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_3_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context[3:0] ), //o + .io_outputs_3_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_2 ), //i + .io_outputs_3_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready ), //o + .io_outputs_3_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 ), //i + .io_outputs_3_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 ), //i + .io_outputs_3_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2[31:0] ), //i + .io_outputs_3_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2[3:0] ), //i + .io_outputs_4_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid ), //o + .io_outputs_4_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_3 ), //i + .io_outputs_4_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last ), //o + .io_outputs_4_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode ), //o + .io_outputs_4_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address[23:0]), //o + .io_outputs_4_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_4_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_4_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_4_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context[3:0] ), //o + .io_outputs_4_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_3 ), //i + .io_outputs_4_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready ), //o + .io_outputs_4_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 ), //i + .io_outputs_4_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 ), //i + .io_outputs_4_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3[31:0] ), //i + .io_outputs_4_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3[3:0] ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbClint_b62b14ffe6bb44e5a817b8d08e286c6b system_clint_logic ( + .io_bus_cmd_valid (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i + .io_bus_cmd_ready (system_clint_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[15:0]), //i + .io_bus_cmd_payload_fragment_length (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_context (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[3:0] ), //i + .io_bus_rsp_valid (system_clint_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_bus_rsp_payload_last (system_clint_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_clint_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_clint_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_clint_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o + .io_timerInterrupt (system_clint_logic_io_timerInterrupt ), //o + .io_softwareInterrupt (system_clint_logic_io_softwareInterrupt ), //o + .io_time (system_clint_logic_io_time[63:0] ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbUartCtrl_b62b14ffe6bb44e5a817b8d08e286c6b system_uart_0_io_logic ( + .io_bus_cmd_valid (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i + .io_bus_cmd_ready (system_uart_0_io_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[5:0]), //i + .io_bus_cmd_payload_fragment_length (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_context (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[3:0]), //i + .io_bus_rsp_valid (system_uart_0_io_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (_zz_io_bus_rsp_ready_1 ), //i + .io_bus_rsp_payload_last (system_uart_0_io_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_uart_0_io_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_uart_0_io_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o + .io_uart_txd (system_uart_0_io_logic_io_uart_txd ), //o + .io_uart_rxd (system_uart_0_io_rxd ), //i + .io_interrupt (system_uart_0_io_logic_io_interrupt ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbSpiXdrMasterCtrl_b62b14ffe6bb44e5a817b8d08e286c6b system_spi_0_io_logic ( + .io_ctrl_cmd_valid (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i + .io_ctrl_cmd_ready (system_spi_0_io_logic_io_ctrl_cmd_ready ), //o + .io_ctrl_cmd_payload_last (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i + .io_ctrl_cmd_payload_fragment_opcode (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i + .io_ctrl_cmd_payload_fragment_address (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[11:0]), //i + .io_ctrl_cmd_payload_fragment_length (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i + .io_ctrl_cmd_payload_fragment_data (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i + .io_ctrl_cmd_payload_fragment_context (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[3:0] ), //i + .io_ctrl_rsp_valid (system_spi_0_io_logic_io_ctrl_rsp_valid ), //o + .io_ctrl_rsp_ready (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_ctrl_rsp_payload_last (system_spi_0_io_logic_io_ctrl_rsp_payload_last ), //o + .io_ctrl_rsp_payload_fragment_opcode (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode ), //o + .io_ctrl_rsp_payload_fragment_data (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data[31:0] ), //o + .io_ctrl_rsp_payload_fragment_context (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context[3:0] ), //o + .io_spi_sclk_write (system_spi_0_io_logic_io_spi_sclk_write ), //o + .io_spi_data_0_writeEnable (system_spi_0_io_logic_io_spi_data_0_writeEnable ), //o + .io_spi_data_0_read (system_spi_0_io_data_0_read ), //i + .io_spi_data_0_write (system_spi_0_io_logic_io_spi_data_0_write ), //o + .io_spi_data_1_writeEnable (system_spi_0_io_logic_io_spi_data_1_writeEnable ), //o + .io_spi_data_1_read (system_spi_0_io_data_1_read ), //i + .io_spi_data_1_write (system_spi_0_io_logic_io_spi_data_1_write ), //o + .io_spi_data_2_writeEnable (system_spi_0_io_logic_io_spi_data_2_writeEnable ), //o + .io_spi_data_2_read (system_spi_0_io_data_2_read ), //i + .io_spi_data_2_write (system_spi_0_io_logic_io_spi_data_2_write ), //o + .io_spi_data_3_writeEnable (system_spi_0_io_logic_io_spi_data_3_writeEnable ), //o + .io_spi_data_3_read (system_spi_0_io_data_3_read ), //i + .io_spi_data_3_write (system_spi_0_io_logic_io_spi_data_3_write ), //o + .io_spi_ss (system_spi_0_io_logic_io_spi_ss ), //o + .io_interrupt (system_spi_0_io_logic_io_interrupt ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbToApb3Bridge_b62b14ffe6bb44e5a817b8d08e286c6b io_apbSlave_0_logic ( + .io_input_cmd_valid (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i + .io_input_cmd_ready (io_apbSlave_0_logic_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[15:0]), //i + .io_input_cmd_payload_fragment_length (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i + .io_input_cmd_payload_fragment_data (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_context (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[3:0] ), //i + .io_input_rsp_valid (io_apbSlave_0_logic_io_input_rsp_valid ), //o + .io_input_rsp_ready (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_input_rsp_payload_last (io_apbSlave_0_logic_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (io_apbSlave_0_logic_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (io_apbSlave_0_logic_io_input_rsp_payload_fragment_context[3:0] ), //o + .io_output_PADDR (io_apbSlave_0_logic_io_output_PADDR[15:0] ), //o + .io_output_PSEL (io_apbSlave_0_logic_io_output_PSEL ), //o + .io_output_PENABLE (io_apbSlave_0_logic_io_output_PENABLE ), //o + .io_output_PREADY (io_apbSlave_0_PREADY ), //i + .io_output_PWRITE (io_apbSlave_0_logic_io_output_PWRITE ), //o + .io_output_PWDATA (io_apbSlave_0_logic_io_output_PWDATA[31:0] ), //o + .io_output_PRDATA (io_apbSlave_0_PRDATA[31:0] ), //i + .io_output_PSLVERROR (io_apbSlave_0_PSLVERROR ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + initial begin + debugCd_logic_holdingLogic_resetCounter = 12'h0; + debugCd_logic_outputReset = 1'b1; + end + + always @(*) begin + debugCd_logic_inputResetTrigger = 1'b0; + if(debugCd_logic_inputResetAdapter_stuff_syncTrigger) begin + debugCd_logic_inputResetTrigger = 1'b1; + end + end + + always @(*) begin + debugCd_logic_outputResetUnbuffered = 1'b0; + if(when_ClockDomainGenerator_l77) begin + debugCd_logic_outputResetUnbuffered = 1'b1; + end + end + + assign when_ClockDomainGenerator_l77 = (debugCd_logic_holdingLogic_resetCounter != 12'hfff); + assign debugCd_logic_inputResetAdapter_stuff_syncTrigger = bufferCC_5_io_dataOut; + always @(*) begin + systemCd_logic_inputResetTrigger = 1'b0; + if(bufferCC_6_io_dataOut) begin + systemCd_logic_inputResetTrigger = 1'b1; + end + if(bufferCC_7_io_dataOut) begin + systemCd_logic_inputResetTrigger = 1'b1; + end + end + + always @(*) begin + systemCd_logic_outputResetUnbuffered = 1'b0; + if(when_ClockDomainGenerator_l77_1) begin + systemCd_logic_outputResetUnbuffered = 1'b1; + end + end + + assign when_ClockDomainGenerator_l77_1 = (systemCd_logic_holdingLogic_resetCounter != 6'h3f); + assign system_cores_0_iBus_cmd_valid = system_cores_0_logic_cpu_iBus_cmd_valid; + assign system_cores_0_iBus_cmd_payload_fragment_opcode = 1'b0; + assign system_cores_0_iBus_cmd_payload_fragment_address = system_cores_0_logic_cpu_iBus_cmd_payload_address; + assign system_cores_0_iBus_cmd_payload_fragment_length = 6'h3f; + assign system_cores_0_iBus_cmd_payload_last = 1'b1; + assign system_cores_0_logic_cpu_iBus_rsp_payload_error = (system_cores_0_iBus_rsp_payload_fragment_opcode == 1'b1); + assign system_cores_0_iBus_rsp_ready = 1'b1; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_valid = system_cores_0_logic_cpu_dBus_cmd_valid; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_last = system_cores_0_logic_cpu_dBus_cmd_payload_last; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_opcode = (system_cores_0_logic_cpu_dBus_cmd_payload_wr ? 1'b1 : 1'b0); + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_address = system_cores_0_logic_cpu_dBus_cmd_payload_address; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_data = system_cores_0_logic_cpu_dBus_cmd_payload_data; + always @(*) begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'bxxxxxx; + case(system_cores_0_logic_cpu_dBus_cmd_payload_size) + 3'b000 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h0; + end + 3'b001 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h01; + end + 3'b010 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h03; + end + 3'b011 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h07; + end + 3'b100 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h0f; + end + 3'b101 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h1f; + end + 3'b110 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h3f; + end + default : begin + end + endcase + end + + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_mask = system_cores_0_logic_cpu_dBus_cmd_payload_mask; + assign system_cores_0_logic_cpu_dBus_Bridge_withoutWriteBuffer_busCmdContext_isWrite = system_cores_0_logic_cpu_dBus_cmd_payload_wr; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_withoutWriteBuffer_busCmdContext_isWrite; + always @(*) begin + system_cores_0_logic_cpu_dBus_rsp_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_valid; + if(when_DataCache_l532) begin + system_cores_0_logic_cpu_dBus_rsp_valid = 1'b0; + end + end + + assign when_DataCache_l532 = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_context[0]; + assign system_cores_0_logic_cpu_dBus_rsp_payload_error = (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_opcode == 1'b1); + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_ready = 1'b1; + assign system_cores_0_iBus_cmd_combStage_valid = system_cores_0_iBus_cmd_valid; + assign system_cores_0_iBus_cmd_ready = system_cores_0_iBus_cmd_combStage_ready; + assign system_cores_0_iBus_cmd_combStage_payload_last = system_cores_0_iBus_cmd_payload_last; + assign system_cores_0_iBus_cmd_combStage_payload_fragment_opcode = system_cores_0_iBus_cmd_payload_fragment_opcode; + assign system_cores_0_iBus_cmd_combStage_payload_fragment_address = system_cores_0_iBus_cmd_payload_fragment_address; + assign system_cores_0_iBus_cmd_combStage_payload_fragment_length = system_cores_0_iBus_cmd_payload_fragment_length; + assign system_cores_0_iBus_cmd_combStage_ready = system_cores_0_iBus_connector_decoder_cmd_ready; + always @(*) begin + _zz_system_cores_0_iBus_connector_decoder_rsp_ready = system_cores_0_iBus_rsp_ready; + if(when_Stream_l368) begin + _zz_system_cores_0_iBus_connector_decoder_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! _zz_system_cores_0_iBus_rsp_valid); + assign _zz_system_cores_0_iBus_rsp_valid = _zz_system_cores_0_iBus_rsp_valid_1; + assign system_cores_0_iBus_rsp_valid = _zz_system_cores_0_iBus_rsp_valid; + assign system_cores_0_iBus_rsp_payload_last = _zz_system_cores_0_iBus_rsp_payload_last; + assign system_cores_0_iBus_rsp_payload_fragment_opcode = _zz_system_cores_0_iBus_rsp_payload_fragment_opcode; + assign system_cores_0_iBus_rsp_payload_fragment_data = _zz_system_cores_0_iBus_rsp_payload_fragment_data; + assign system_cores_0_iBus_connector_decoder_cmd_valid = system_cores_0_iBus_cmd_combStage_valid; + assign system_cores_0_iBus_connector_decoder_rsp_ready = _zz_system_cores_0_iBus_connector_decoder_rsp_ready; + assign system_cores_0_iBus_connector_decoder_cmd_payload_last = system_cores_0_iBus_cmd_combStage_payload_last; + assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_opcode = system_cores_0_iBus_cmd_combStage_payload_fragment_opcode; + assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_address = system_cores_0_iBus_cmd_combStage_payload_fragment_address; + assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_length = system_cores_0_iBus_cmd_combStage_payload_fragment_length; + always @(*) begin + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_ready; + if(when_Stream_l368_1) begin + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready = 1'b1; + end + end + + assign when_Stream_l368_1 = (! system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid); + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_last = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_last; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_opcode = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_opcode; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_address = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_address; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_length = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_length; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_data = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_data; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_mask = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_mask; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_context; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_ready = system_cores_0_dBus_connector_decoder_cmd_ready; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_valid = system_cores_0_dBus_connector_decoder_rsp_valid; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_last = system_cores_0_dBus_connector_decoder_rsp_payload_last; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_opcode = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_opcode; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_data = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_data; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_context = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_context; + assign system_cores_0_dBus_connector_decoder_cmd_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid; + assign system_cores_0_dBus_connector_decoder_rsp_ready = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_ready; + assign system_cores_0_dBus_connector_decoder_cmd_payload_last = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_last; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_opcode = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_opcode; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_address = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_address; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_length = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_length; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_data = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_data; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_mask = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_mask; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_context; + assign system_hardJtag_debug_logic_mmMaster_cmd_valid = system_hardJtag_debug_logic_debugger_io_mem_cmd_valid; + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_last = 1'b1; + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_length = 2'b11; + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_opcode = (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_wr ? 1'b1 : 1'b0); + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address = {_zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address,2'b00}; + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_data = system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_data; + always @(*) begin + case(system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_size) + 2'b00 : begin + _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b0001; + end + 2'b01 : begin + _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b0011; + end + default : begin + _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b1111; + end + endcase + end + + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask_1[3:0]; + assign system_hardJtag_debug_logic_mmMaster_rsp_ready = 1'b1; + assign jtagCtrl_tdo = system_hardJtag_debug_logic_jtagBridge_io_ctrl_tdo; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_valid = system_hardJtag_debug_logic_mmMaster_cmd_valid; + assign system_hardJtag_debug_logic_mmMaster_cmd_ready = system_hardJtag_debug_bmb_connector_decoder_cmd_ready; + assign system_hardJtag_debug_logic_mmMaster_rsp_valid = system_hardJtag_debug_bmb_connector_decoder_rsp_valid; + assign system_hardJtag_debug_bmb_connector_decoder_rsp_ready = system_hardJtag_debug_logic_mmMaster_rsp_ready; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_last = system_hardJtag_debug_logic_mmMaster_cmd_payload_last; + assign system_hardJtag_debug_logic_mmMaster_rsp_payload_last = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_last; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_opcode = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_opcode; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_address = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_length = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_length; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_data = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_data; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_mask = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask; + assign system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_opcode = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_opcode; + assign system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_data = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_data; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_ready = bmbDecoder_4_io_input_cmd_ready; + assign system_hardJtag_debug_bmb_connector_decoder_rsp_valid = bmbDecoder_4_io_input_rsp_valid; + assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_last = bmbDecoder_4_io_input_rsp_payload_last; + assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_opcode = bmbDecoder_4_io_input_rsp_payload_fragment_opcode; + assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_data = bmbDecoder_4_io_input_rsp_payload_fragment_data; + assign system_fabric_iBus_bmb_cmd_valid = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_iBus_bmb_cmd_ready; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_iBus_bmb_rsp_valid; + assign system_fabric_iBus_bmb_rsp_ready = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_fabric_iBus_bmb_cmd_payload_last = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_iBus_bmb_rsp_payload_last; + assign system_fabric_iBus_bmb_cmd_payload_fragment_opcode = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_fabric_iBus_bmb_cmd_payload_fragment_address = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_fabric_iBus_bmb_cmd_payload_fragment_length = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_rsp_payload_fragment_opcode; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_iBus_bmb_rsp_payload_fragment_data; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_cores_0_iBus_connector_decoder_cmd_valid; + assign system_cores_0_iBus_connector_decoder_cmd_ready = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_cores_0_iBus_connector_decoder_rsp_valid = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_cores_0_iBus_connector_decoder_rsp_ready; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_cores_0_iBus_connector_decoder_cmd_payload_last; + assign system_cores_0_iBus_connector_decoder_rsp_payload_last = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_opcode; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_address; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_length; + assign system_cores_0_iBus_connector_decoder_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_cores_0_iBus_connector_decoder_rsp_payload_fragment_data = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_valid = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid || system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_last = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_opcode = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_address = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_length = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_data = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_mask = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_mask : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_context = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context); + always @(*) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l368_2) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l368_2 = (! system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_last = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_last; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_opcode = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_opcode; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_address = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_address; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_length = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_length; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_data = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_data; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_mask = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_mask; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_context = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_context; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_ready = system_fabric_exclusiveMonitor_logic_io_input_cmd_ready; + always @(*) begin + _zz_io_input_rsp_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + if(when_Stream_l368_3) begin + _zz_io_input_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368_3 = (! _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid); + assign _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_cores_0_debugBmb_cmd_valid = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_cores_0_debugBmb_cmd_ready; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_cores_0_debugBmb_rsp_valid; + assign system_cores_0_debugBmb_rsp_ready = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_cores_0_debugBmb_cmd_payload_last = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_cores_0_debugBmb_rsp_payload_last; + assign system_cores_0_debugBmb_cmd_payload_fragment_opcode = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_cores_0_debugBmb_cmd_payload_fragment_address = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_cores_0_debugBmb_cmd_payload_fragment_length = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_cores_0_debugBmb_cmd_payload_fragment_data = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_cores_0_debugBmb_cmd_payload_fragment_mask = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_cores_0_debugBmb_rsp_payload_fragment_opcode; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_cores_0_debugBmb_rsp_payload_fragment_data; + assign system_cores_0_logic_cpu_debug_bus_cmd_payload_wr = (system_cores_0_debugBmb_cmd_payload_fragment_opcode == 1'b1); + assign system_cores_0_logic_cpu_debug_bus_cmd_fire = (system_cores_0_debugBmb_cmd_valid && system_cores_0_logic_cpu_debug_bus_cmd_ready); + assign system_cores_0_debugBmb_cmd_ready = system_cores_0_logic_cpu_debug_bus_cmd_ready; + assign system_cores_0_debugBmb_rsp_valid = system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext; + assign system_cores_0_debugBmb_rsp_payload_last = 1'b1; + assign system_cores_0_debugBmb_rsp_payload_fragment_opcode = 1'b0; + assign system_cores_0_debugBmb_rsp_payload_fragment_data = system_cores_0_logic_cpu_debug_bus_rsp_data; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbDecoder_4_io_outputs_0_cmd_valid; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbDecoder_4_io_outputs_0_rsp_ready; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbDecoder_4_io_outputs_0_cmd_payload_last; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_opcode; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_address[7:0]; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_length; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_data; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_mask; + assign system_fabric_dBusCoherent_bmb_cmd_valid = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_dBusCoherent_bmb_cmd_ready; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_dBusCoherent_bmb_rsp_valid; + assign system_fabric_dBusCoherent_bmb_rsp_ready = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_fabric_dBusCoherent_bmb_cmd_payload_last = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_dBusCoherent_bmb_rsp_payload_last; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_context; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_valid = system_fabric_dBusCoherent_bmb_cmd_valid; + assign system_fabric_dBusCoherent_bmb_cmd_ready = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_ready; + assign system_fabric_dBusCoherent_bmb_rsp_valid = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_valid; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_ready = system_fabric_dBusCoherent_bmb_rsp_ready; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_last = system_fabric_dBusCoherent_bmb_cmd_payload_last; + assign system_fabric_dBusCoherent_bmb_rsp_payload_last = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_last; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_address; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_length; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_mask; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_context; + assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_context; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_valid = system_fabric_exclusiveMonitor_logic_io_output_cmd_valid; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_ready = system_fabric_exclusiveMonitor_logic_io_output_rsp_ready; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_last = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_last; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_opcode = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_opcode; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_address = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_address; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_length = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_length; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_data = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_data; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_mask = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_mask; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_context = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_context; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_cores_0_dBus_connector_decoder_cmd_valid; + assign system_cores_0_dBus_connector_decoder_cmd_ready = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_cores_0_dBus_connector_decoder_rsp_valid = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_cores_0_dBus_connector_decoder_rsp_ready; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_cores_0_dBus_connector_decoder_cmd_payload_last; + assign system_cores_0_dBus_connector_decoder_rsp_payload_last = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_address; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_length; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_mask; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_context; + assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_valid; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_valid = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_ready; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_last; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_last = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_opcode; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_address; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_length; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_data; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_mask; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_context; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_opcode = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_data = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_context = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_fabric_dBus_bmb_cmd_valid = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_dBus_bmb_cmd_ready; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_dBus_bmb_rsp_valid; + assign system_fabric_dBus_bmb_rsp_ready = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_fabric_dBus_bmb_cmd_payload_last = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_dBus_bmb_rsp_payload_last; + assign system_fabric_dBus_bmb_cmd_payload_fragment_opcode = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_fabric_dBus_bmb_cmd_payload_fragment_address = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_fabric_dBus_bmb_cmd_payload_fragment_length = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_fabric_dBus_bmb_cmd_payload_fragment_data = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_fabric_dBus_bmb_cmd_payload_fragment_mask = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign system_fabric_dBus_bmb_cmd_payload_fragment_context = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_dBus_bmb_rsp_payload_fragment_opcode; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_dBus_bmb_rsp_payload_fragment_data; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_fabric_dBus_bmb_rsp_payload_fragment_context; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_valid; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_ready = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_valid = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_fabric_exclusiveMonitor_output_connector_decoder_rsp_ready; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_last; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_last = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_opcode; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_address; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_length; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_data; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_mask; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_context; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_opcode = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_data = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_context = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + always @(*) begin + system_fabric_iBus_bmb_cmd_ready = system_fabric_iBus_bmb_cmd_m2sPipe_ready; + if(when_Stream_l368_4) begin + system_fabric_iBus_bmb_cmd_ready = 1'b1; + end + end + + assign when_Stream_l368_4 = (! system_fabric_iBus_bmb_cmd_m2sPipe_valid); + assign system_fabric_iBus_bmb_cmd_m2sPipe_valid = system_fabric_iBus_bmb_cmd_rValid; + assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_last = system_fabric_iBus_bmb_cmd_rData_last; + assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_opcode = system_fabric_iBus_bmb_cmd_rData_fragment_opcode; + assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_address = system_fabric_iBus_bmb_cmd_rData_fragment_address; + assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_length = system_fabric_iBus_bmb_cmd_rData_fragment_length; + assign system_fabric_iBus_bmb_cmd_m2sPipe_ready = system_fabric_iBus_bmb_decoder_io_input_cmd_ready; + assign system_fabric_iBus_bmb_rsp_valid = system_fabric_iBus_bmb_decoder_io_input_rsp_valid; + assign system_fabric_iBus_bmb_rsp_payload_last = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_last; + assign system_fabric_iBus_bmb_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_opcode; + assign system_fabric_iBus_bmb_rsp_payload_fragment_data = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_data; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid = system_fabric_dBus_bmb_cmd_valid; + assign system_fabric_dBus_bmb_cmd_ready = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready; + assign system_fabric_dBus_bmb_rsp_valid = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready = system_fabric_dBus_bmb_rsp_ready; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last = system_fabric_dBus_bmb_cmd_payload_last; + assign system_fabric_dBus_bmb_rsp_payload_last = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode = system_fabric_dBus_bmb_cmd_payload_fragment_opcode; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address = system_fabric_dBus_bmb_cmd_payload_fragment_address; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length = system_fabric_dBus_bmb_cmd_payload_fragment_length; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data = system_fabric_dBus_bmb_cmd_payload_fragment_data; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask = system_fabric_dBus_bmb_cmd_payload_fragment_mask; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context = system_fabric_dBus_bmb_cmd_payload_fragment_context; + assign system_fabric_dBus_bmb_rsp_payload_fragment_opcode = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode; + assign system_fabric_dBus_bmb_rsp_payload_fragment_data = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data; + assign system_fabric_dBus_bmb_rsp_payload_fragment_context = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context; + assign system_bridge_bmb_cmd_valid = system_bridge_bmb_arbiter_io_output_cmd_valid; + assign system_bridge_bmb_rsp_ready = system_bridge_bmb_arbiter_io_output_rsp_ready; + assign system_bridge_bmb_cmd_payload_last = system_bridge_bmb_arbiter_io_output_cmd_payload_last; + assign system_bridge_bmb_cmd_payload_fragment_source = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_source; + assign system_bridge_bmb_cmd_payload_fragment_opcode = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_opcode; + assign system_bridge_bmb_cmd_payload_fragment_address = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_address; + assign system_bridge_bmb_cmd_payload_fragment_length = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_length; + assign system_bridge_bmb_cmd_payload_fragment_data = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_data; + assign system_bridge_bmb_cmd_payload_fragment_mask = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_mask; + assign system_bridge_bmb_cmd_payload_fragment_context = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_context; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready = system_bridge_bmb_arbiter_io_inputs_0_cmd_ready; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid = system_bridge_bmb_arbiter_io_inputs_0_rsp_valid; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_last; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_opcode; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_data; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_context; + assign system_bridge_bmb_cmd_ready = (! system_bridge_bmb_cmd_rValid); + assign system_bridge_bmb_cmd_s2mPipe_valid = (system_bridge_bmb_cmd_valid || system_bridge_bmb_cmd_rValid); + assign system_bridge_bmb_cmd_s2mPipe_payload_last = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_last : system_bridge_bmb_cmd_payload_last); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_source = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_source : system_bridge_bmb_cmd_payload_fragment_source); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_opcode = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_opcode : system_bridge_bmb_cmd_payload_fragment_opcode); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_address = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_address : system_bridge_bmb_cmd_payload_fragment_address); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_length = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_length : system_bridge_bmb_cmd_payload_fragment_length); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_data = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_data : system_bridge_bmb_cmd_payload_fragment_data); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_mask = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_mask : system_bridge_bmb_cmd_payload_fragment_mask); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_context = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_context : system_bridge_bmb_cmd_payload_fragment_context); + always @(*) begin + system_bridge_bmb_cmd_s2mPipe_ready = system_bridge_bmb_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l368_5) begin + system_bridge_bmb_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l368_5 = (! system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid); + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid = system_bridge_bmb_cmd_s2mPipe_rValid; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_last = system_bridge_bmb_cmd_s2mPipe_rData_last; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_source = system_bridge_bmb_cmd_s2mPipe_rData_fragment_source; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_opcode = system_bridge_bmb_cmd_s2mPipe_rData_fragment_opcode; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_address = system_bridge_bmb_cmd_s2mPipe_rData_fragment_address; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_length = system_bridge_bmb_cmd_s2mPipe_rData_fragment_length; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_data = system_bridge_bmb_cmd_s2mPipe_rData_fragment_data; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_mask = system_bridge_bmb_cmd_s2mPipe_rData_fragment_mask; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_context = system_bridge_bmb_cmd_s2mPipe_rData_fragment_context; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_ready = system_bridge_bmb_decoder_io_input_cmd_ready; + assign system_bridge_bmb_rsp_valid = system_bridge_bmb_decoder_io_input_rsp_valid; + assign system_bridge_bmb_rsp_payload_last = system_bridge_bmb_decoder_io_input_rsp_payload_last; + assign system_bridge_bmb_rsp_payload_fragment_source = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_source; + assign system_bridge_bmb_rsp_payload_fragment_opcode = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_opcode; + assign system_bridge_bmb_rsp_payload_fragment_data = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_data; + assign system_bridge_bmb_rsp_payload_fragment_context = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_cmd_valid = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_bmbPeripheral_bmb_cmd_ready; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_bmbPeripheral_bmb_rsp_valid; + assign system_bmbPeripheral_bmb_rsp_ready = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_bmbPeripheral_bmb_cmd_payload_last = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_bmbPeripheral_bmb_rsp_payload_last; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_address = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_length = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_data = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_mask = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_context = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_bmbPeripheral_bmb_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_bmbPeripheral_bmb_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bridge_bmb_unburstify_io_output_cmd_valid; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bridge_bmb_unburstify_io_output_rsp_ready; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bridge_bmb_unburstify_io_output_cmd_payload_last; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_address[23:0]; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_mask; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_context; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_valid = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_ready; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_last = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_opcode = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_address = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_length = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_data = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_mask = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_context = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_ready = system_ramA_logic_io_bus_cmd_ready; + always @(*) begin + _zz_io_bus_rsp_ready = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + if(when_Stream_l368_6) begin + _zz_io_bus_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368_6 = (! _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid); + assign _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bridge_bmb_unburstify_1_io_output_cmd_valid; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bridge_bmb_unburstify_1_io_output_rsp_ready; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bridge_bmb_unburstify_1_io_output_cmd_payload_last; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_opcode; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_address[14:0]; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_length; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_data; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_mask; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_context; + assign system_bmbPeripheral_bmb_cmd_combStage_valid = system_bmbPeripheral_bmb_cmd_valid; + assign system_bmbPeripheral_bmb_cmd_ready = system_bmbPeripheral_bmb_cmd_combStage_ready; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_last = system_bmbPeripheral_bmb_cmd_payload_last; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_opcode = system_bmbPeripheral_bmb_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_address = system_bmbPeripheral_bmb_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_length = system_bmbPeripheral_bmb_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_data = system_bmbPeripheral_bmb_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_mask = system_bmbPeripheral_bmb_cmd_payload_fragment_mask; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_context = system_bmbPeripheral_bmb_cmd_payload_fragment_context; + assign system_bmbPeripheral_bmb_cmd_combStage_ready = system_bmbPeripheral_bmb_decoder_io_input_cmd_ready; + assign _zz_io_input_rsp_ready_1 = (! _zz_system_bmbPeripheral_bmb_rsp_valid_1); + assign _zz_system_bmbPeripheral_bmb_rsp_valid = _zz_system_bmbPeripheral_bmb_rsp_valid_1; + assign system_bmbPeripheral_bmb_rsp_valid = _zz_system_bmbPeripheral_bmb_rsp_valid; + assign system_bmbPeripheral_bmb_rsp_payload_last = _zz_system_bmbPeripheral_bmb_rsp_payload_last; + assign system_bmbPeripheral_bmb_rsp_payload_fragment_opcode = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_rsp_payload_fragment_data = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_rsp_payload_fragment_context = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_context; + assign system_uart_0_io_txd = system_uart_0_io_logic_io_uart_txd; + assign io_apbSlave_0_PADDR = io_apbSlave_0_logic_io_output_PADDR; + assign io_apbSlave_0_PSEL = io_apbSlave_0_logic_io_output_PSEL; + assign io_apbSlave_0_PENABLE = io_apbSlave_0_logic_io_output_PENABLE; + assign io_apbSlave_0_PWRITE = io_apbSlave_0_logic_io_output_PWRITE; + assign io_apbSlave_0_PWDATA = io_apbSlave_0_logic_io_output_PWDATA; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_clint_logic_io_bus_cmd_ready; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_clint_logic_io_bus_rsp_valid; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_clint_logic_io_bus_rsp_payload_last; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_clint_logic_io_bus_rsp_payload_fragment_opcode; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_clint_logic_io_bus_rsp_payload_fragment_data; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_clint_logic_io_bus_rsp_payload_fragment_context; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_uart_0_io_logic_io_bus_cmd_ready; + assign _zz_io_bus_rsp_ready_1 = (! _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1); + assign _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign when_PlicGateway_l21 = (! system_uart_0_io_interrupt_plic_gateway_waitCompletion); + assign when_PlicGateway_l21_1 = (! system_spi_0_io_interrupt_plic_gateway_waitCompletion); + assign system_spi_0_io_sclk_write = system_spi_0_io_logic_io_spi_sclk_write; + assign system_spi_0_io_data_0_writeEnable = system_spi_0_io_logic_io_spi_data_0_writeEnable; + assign system_spi_0_io_data_0_write = system_spi_0_io_logic_io_spi_data_0_write; + assign system_spi_0_io_data_1_writeEnable = system_spi_0_io_logic_io_spi_data_1_writeEnable; + assign system_spi_0_io_data_1_write = system_spi_0_io_logic_io_spi_data_1_write; + assign system_spi_0_io_data_2_writeEnable = system_spi_0_io_logic_io_spi_data_2_writeEnable; + assign system_spi_0_io_data_2_write = system_spi_0_io_logic_io_spi_data_2_write; + assign system_spi_0_io_data_3_writeEnable = system_spi_0_io_logic_io_spi_data_3_writeEnable; + assign system_spi_0_io_data_3_write = system_spi_0_io_logic_io_spi_data_3_write; + assign system_spi_0_io_ss = system_spi_0_io_logic_io_spi_ss; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_spi_0_io_logic_io_ctrl_cmd_ready; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_spi_0_io_logic_io_ctrl_rsp_valid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_spi_0_io_logic_io_ctrl_rsp_payload_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = io_apbSlave_0_logic_io_input_cmd_ready; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = io_apbSlave_0_logic_io_input_rsp_valid; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = io_apbSlave_0_logic_io_input_rsp_payload_last; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = io_apbSlave_0_logic_io_input_rsp_payload_fragment_data; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = io_apbSlave_0_logic_io_input_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_withoutMask_cmd_valid = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_rsp_ready = system_bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_cmd_ready = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_bmbPeripheral_bmb_withoutMask_rsp_valid = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address[15:0]; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_1; + assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_1; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1[5:0]; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + always @(*) begin + system_plic_logic_bus_readHaltTrigger = 1'b0; + if(when_PlicMapper_l122) begin + system_plic_logic_bus_readHaltTrigger = 1'b1; + end + end + + assign system_plic_logic_bus_writeHaltTrigger = 1'b0; + assign _zz_system_plic_logic_bmb_rsp_valid = (! (system_plic_logic_bus_readHaltTrigger || system_plic_logic_bus_writeHaltTrigger)); + assign system_plic_logic_bus_rsp_ready = (_zz_system_plic_logic_bus_rsp_ready && _zz_system_plic_logic_bmb_rsp_valid); + always @(*) begin + _zz_system_plic_logic_bus_rsp_ready = system_plic_logic_bmb_rsp_ready; + if(when_Stream_l368_7) begin + _zz_system_plic_logic_bus_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368_7 = (! _zz_system_plic_logic_bmb_rsp_valid_1); + assign _zz_system_plic_logic_bmb_rsp_valid_1 = _zz_system_plic_logic_bmb_rsp_valid_2; + assign system_plic_logic_bmb_rsp_valid = _zz_system_plic_logic_bmb_rsp_valid_1; + assign system_plic_logic_bmb_rsp_payload_last = _zz_system_plic_logic_bmb_rsp_payload_last; + assign system_plic_logic_bmb_rsp_payload_fragment_opcode = _zz_system_plic_logic_bmb_rsp_payload_fragment_opcode; + assign system_plic_logic_bmb_rsp_payload_fragment_data = _zz_system_plic_logic_bmb_rsp_payload_fragment_data; + assign system_plic_logic_bmb_rsp_payload_fragment_context = _zz_system_plic_logic_bmb_rsp_payload_fragment_context; + assign system_plic_logic_bus_askWrite = (system_plic_logic_bmb_cmd_valid && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b1)); + assign system_plic_logic_bus_askRead = (system_plic_logic_bmb_cmd_valid && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b0)); + assign system_plic_logic_bmb_cmd_fire = (system_plic_logic_bmb_cmd_valid && system_plic_logic_bmb_cmd_ready); + assign system_plic_logic_bus_doWrite = (system_plic_logic_bmb_cmd_fire && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b1)); + assign system_plic_logic_bmb_cmd_fire_1 = (system_plic_logic_bmb_cmd_valid && system_plic_logic_bmb_cmd_ready); + assign system_plic_logic_bus_doRead = (system_plic_logic_bmb_cmd_fire_1 && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b0)); + assign system_plic_logic_bus_rsp_valid = system_plic_logic_bmb_cmd_valid; + assign system_plic_logic_bmb_cmd_ready = system_plic_logic_bus_rsp_ready; + assign system_plic_logic_bus_rsp_payload_last = 1'b1; + assign system_plic_logic_bus_rsp_payload_fragment_opcode = 1'b0; + always @(*) begin + system_plic_logic_bus_rsp_payload_fragment_data = 32'h0; + case(system_plic_logic_bmb_cmd_payload_fragment_address) + 22'h000004 : begin + system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_uart_0_io_interrupt_plic_gateway_priority; + end + 22'h001000 : begin + system_plic_logic_bus_rsp_payload_fragment_data[1 : 1] = system_uart_0_io_interrupt_plic_gateway_ip; + system_plic_logic_bus_rsp_payload_fragment_data[4 : 4] = system_spi_0_io_interrupt_plic_gateway_ip; + end + 22'h000010 : begin + system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_spi_0_io_interrupt_plic_gateway_priority; + end + 22'h200000 : begin + system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_cores_0_externalInterrupt_plic_target_threshold; + end + 22'h200004 : begin + system_plic_logic_bus_rsp_payload_fragment_data[2 : 0] = system_cores_0_externalInterrupt_plic_target_claim; + end + 22'h002000 : begin + system_plic_logic_bus_rsp_payload_fragment_data[1 : 1] = system_cores_0_externalInterrupt_plic_target_ie_0; + system_plic_logic_bus_rsp_payload_fragment_data[4 : 4] = system_cores_0_externalInterrupt_plic_target_ie_1; + end + default : begin + end + endcase + end + + assign system_plic_logic_bus_rsp_payload_fragment_context = system_plic_logic_bmb_cmd_payload_fragment_context; + assign system_cores_0_externalInterrupt_plic_target_requests_0_priority = 2'b00; + assign system_cores_0_externalInterrupt_plic_target_requests_0_id = 3'b000; + assign system_cores_0_externalInterrupt_plic_target_requests_0_valid = 1'b1; + assign system_cores_0_externalInterrupt_plic_target_requests_1_priority = system_uart_0_io_interrupt_plic_gateway_priority; + assign system_cores_0_externalInterrupt_plic_target_requests_1_id = 3'b001; + assign system_cores_0_externalInterrupt_plic_target_requests_1_valid = (system_uart_0_io_interrupt_plic_gateway_ip && system_cores_0_externalInterrupt_plic_target_ie_0); + assign system_cores_0_externalInterrupt_plic_target_requests_2_priority = system_spi_0_io_interrupt_plic_gateway_priority; + assign system_cores_0_externalInterrupt_plic_target_requests_2_id = 3'b100; + assign system_cores_0_externalInterrupt_plic_target_requests_2_valid = (system_spi_0_io_interrupt_plic_gateway_ip && system_cores_0_externalInterrupt_plic_target_ie_1); + assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority = ((! system_cores_0_externalInterrupt_plic_target_requests_1_valid) || (system_cores_0_externalInterrupt_plic_target_requests_0_valid && (system_cores_0_externalInterrupt_plic_target_requests_1_priority <= system_cores_0_externalInterrupt_plic_target_requests_0_priority))); + assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1 = (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_priority : system_cores_0_externalInterrupt_plic_target_requests_1_priority); + assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 = (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_valid : system_cores_0_externalInterrupt_plic_target_requests_1_valid); + assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 = ((! system_cores_0_externalInterrupt_plic_target_requests_2_valid) || (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 && (system_cores_0_externalInterrupt_plic_target_requests_2_priority <= _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1))); + assign system_cores_0_externalInterrupt_plic_target_iep = (system_cores_0_externalInterrupt_plic_target_threshold < system_cores_0_externalInterrupt_plic_target_bestRequest_priority); + assign system_cores_0_externalInterrupt_plic_target_claim = (system_cores_0_externalInterrupt_plic_target_iep ? system_cores_0_externalInterrupt_plic_target_bestRequest_id : 3'b000); + assign system_uart_0_io_interrupt_plic_gateway_priority = _zz_system_uart_0_io_interrupt_plic_gateway_priority; + assign system_spi_0_io_interrupt_plic_gateway_priority = _zz_system_spi_0_io_interrupt_plic_gateway_priority; + always @(*) begin + system_plic_logic_bridge_claim_valid = 1'b0; + case(system_plic_logic_bmb_cmd_payload_fragment_address) + 22'h200004 : begin + if(system_plic_logic_bus_doRead) begin + system_plic_logic_bridge_claim_valid = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + system_plic_logic_bridge_claim_payload = 3'bxxx; + case(system_plic_logic_bmb_cmd_payload_fragment_address) + 22'h200004 : begin + if(system_plic_logic_bus_doRead) begin + system_plic_logic_bridge_claim_payload = system_cores_0_externalInterrupt_plic_target_claim; + end + end + default : begin + end + endcase + end + + always @(*) begin + system_plic_logic_bridge_completion_valid = 1'b0; + if(system_plic_logic_bridge_targetMapping_0_targetCompletion_valid) begin + system_plic_logic_bridge_completion_valid = 1'b1; + end + end + + always @(*) begin + system_plic_logic_bridge_completion_payload = 3'bxxx; + if(system_plic_logic_bridge_targetMapping_0_targetCompletion_valid) begin + system_plic_logic_bridge_completion_payload = system_plic_logic_bridge_targetMapping_0_targetCompletion_payload; + end + end + + always @(*) begin + system_plic_logic_bridge_coherencyStall_willIncrement = 1'b0; + if(when_PlicMapper_l122) begin + system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; + end + if(when_BmbSlaveFactory_l71) begin + if(system_plic_logic_bus_askWrite) begin + system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; + end + if(system_plic_logic_bus_askRead) begin + system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; + end + end + end + + assign system_plic_logic_bridge_coherencyStall_willClear = 1'b0; + assign system_plic_logic_bridge_coherencyStall_willOverflowIfInc = (system_plic_logic_bridge_coherencyStall_value == 1'b1); + assign system_plic_logic_bridge_coherencyStall_willOverflow = (system_plic_logic_bridge_coherencyStall_willOverflowIfInc && system_plic_logic_bridge_coherencyStall_willIncrement); + always @(*) begin + system_plic_logic_bridge_coherencyStall_valueNext = (system_plic_logic_bridge_coherencyStall_value + system_plic_logic_bridge_coherencyStall_willIncrement); + if(system_plic_logic_bridge_coherencyStall_willClear) begin + system_plic_logic_bridge_coherencyStall_valueNext = 1'b0; + end + end + + assign when_PlicMapper_l122 = (system_plic_logic_bridge_coherencyStall_value != 1'b0); + assign system_cores_0_externalInterrupt_plic_target_threshold = _zz_system_cores_0_externalInterrupt_plic_target_threshold; + always @(*) begin + system_plic_logic_bridge_targetMapping_0_targetCompletion_valid = 1'b0; + case(system_plic_logic_bmb_cmd_payload_fragment_address) + 22'h200004 : begin + if(system_plic_logic_bus_doWrite) begin + system_plic_logic_bridge_targetMapping_0_targetCompletion_valid = 1'b1; + end + end + default : begin + end + endcase + end + + assign system_cores_0_externalInterrupt_plic_target_ie_0 = _zz_system_cores_0_externalInterrupt_plic_target_ie_0; + assign system_cores_0_externalInterrupt_plic_target_ie_1 = _zz_system_cores_0_externalInterrupt_plic_target_ie_1; + assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_2; + assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_2; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_2; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2[11:0]; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_3; + assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_3; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_3; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3[15:0]; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_plic_logic_bmb_cmd_valid = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_plic_logic_bmb_cmd_ready; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_plic_logic_bmb_rsp_valid; + assign system_plic_logic_bmb_rsp_ready = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_plic_logic_bmb_cmd_payload_last = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_plic_logic_bmb_rsp_payload_last; + assign system_plic_logic_bmb_cmd_payload_fragment_opcode = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_plic_logic_bmb_cmd_payload_fragment_address = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_plic_logic_bmb_cmd_payload_fragment_length = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_plic_logic_bmb_cmd_payload_fragment_data = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_plic_logic_bmb_cmd_payload_fragment_context = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_plic_logic_bmb_rsp_payload_fragment_opcode; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_plic_logic_bmb_rsp_payload_fragment_data; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_plic_logic_bmb_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_4; + assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_4; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_4; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4[21:0]; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_plic_logic_bridge_targetMapping_0_targetCompletion_payload = system_plic_logic_bmb_cmd_payload_fragment_data[2 : 0]; + assign when_BmbSlaveFactory_l71 = 1'b1; + always @(posedge io_systemClk) begin + if(when_ClockDomainGenerator_l77) begin + debugCd_logic_holdingLogic_resetCounter <= (debugCd_logic_holdingLogic_resetCounter + 12'h001); + end + if(debugCd_logic_inputResetTrigger) begin + debugCd_logic_holdingLogic_resetCounter <= 12'h0; + end + debugCd_logic_outputReset <= debugCd_logic_outputResetUnbuffered; + end + + always @(posedge io_systemClk) begin + if(when_ClockDomainGenerator_l77_1) begin + systemCd_logic_holdingLogic_resetCounter <= (systemCd_logic_holdingLogic_resetCounter + 6'h01); + end + if(systemCd_logic_inputResetTrigger) begin + systemCd_logic_holdingLogic_resetCounter <= 6'h0; + end + systemCd_logic_outputReset <= systemCd_logic_outputResetUnbuffered; + end + + always @(posedge io_systemClk) begin + io_systemReset <= systemCd_logic_outputReset; + if(_zz_system_cores_0_iBus_connector_decoder_rsp_ready) begin + _zz_system_cores_0_iBus_rsp_payload_last <= system_cores_0_iBus_connector_decoder_rsp_payload_last; + _zz_system_cores_0_iBus_rsp_payload_fragment_opcode <= system_cores_0_iBus_connector_decoder_rsp_payload_fragment_opcode; + _zz_system_cores_0_iBus_rsp_payload_fragment_data <= system_cores_0_iBus_connector_decoder_rsp_payload_fragment_data; + end + if(system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready) begin + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_last <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_last; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_opcode <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_opcode; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_address <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_address; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_length <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_data <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_data; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_mask <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_mask; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_context <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_context; + end + if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_mask <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_last <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_last; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_opcode <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_opcode; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_address <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_address; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_length <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_length; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_data <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_data; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_mask <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_mask; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_context <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_context; + end + if(_zz_io_input_rsp_ready) begin + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_last; + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_opcode; + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_data; + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_context; + end + if(system_fabric_iBus_bmb_cmd_ready) begin + system_fabric_iBus_bmb_cmd_rData_last <= system_fabric_iBus_bmb_cmd_payload_last; + system_fabric_iBus_bmb_cmd_rData_fragment_opcode <= system_fabric_iBus_bmb_cmd_payload_fragment_opcode; + system_fabric_iBus_bmb_cmd_rData_fragment_address <= system_fabric_iBus_bmb_cmd_payload_fragment_address; + system_fabric_iBus_bmb_cmd_rData_fragment_length <= system_fabric_iBus_bmb_cmd_payload_fragment_length; + end + if(system_bridge_bmb_cmd_ready) begin + system_bridge_bmb_cmd_rData_last <= system_bridge_bmb_cmd_payload_last; + system_bridge_bmb_cmd_rData_fragment_source <= system_bridge_bmb_cmd_payload_fragment_source; + system_bridge_bmb_cmd_rData_fragment_opcode <= system_bridge_bmb_cmd_payload_fragment_opcode; + system_bridge_bmb_cmd_rData_fragment_address <= system_bridge_bmb_cmd_payload_fragment_address; + system_bridge_bmb_cmd_rData_fragment_length <= system_bridge_bmb_cmd_payload_fragment_length; + system_bridge_bmb_cmd_rData_fragment_data <= system_bridge_bmb_cmd_payload_fragment_data; + system_bridge_bmb_cmd_rData_fragment_mask <= system_bridge_bmb_cmd_payload_fragment_mask; + system_bridge_bmb_cmd_rData_fragment_context <= system_bridge_bmb_cmd_payload_fragment_context; + end + if(system_bridge_bmb_cmd_s2mPipe_ready) begin + system_bridge_bmb_cmd_s2mPipe_rData_last <= system_bridge_bmb_cmd_s2mPipe_payload_last; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_source <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_source; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_opcode <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_opcode; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_address <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_address; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_length <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_length; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_data <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_data; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_mask <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_mask; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_context <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_context; + end + if(_zz_io_bus_rsp_ready) begin + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_ramA_logic_io_bus_rsp_payload_last; + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_ramA_logic_io_bus_rsp_payload_fragment_opcode; + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_ramA_logic_io_bus_rsp_payload_fragment_data; + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_ramA_logic_io_bus_rsp_payload_fragment_context; + end + if(_zz_io_input_rsp_ready_1) begin + _zz_system_bmbPeripheral_bmb_rsp_payload_last <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_last; + _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_opcode <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode; + _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_data <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data; + _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_context <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context; + end + _zz_timerInterrupt <= system_clint_logic_io_timerInterrupt[0]; + _zz_softwareInterrupt <= system_clint_logic_io_softwareInterrupt[0]; + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + if(_zz_io_bus_rsp_ready_1) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_uart_0_io_logic_io_bus_rsp_payload_last; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_data; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_context; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + if(_zz_system_plic_logic_bus_rsp_ready) begin + _zz_system_plic_logic_bmb_rsp_payload_last <= system_plic_logic_bus_rsp_payload_last; + _zz_system_plic_logic_bmb_rsp_payload_fragment_opcode <= system_plic_logic_bus_rsp_payload_fragment_opcode; + _zz_system_plic_logic_bmb_rsp_payload_fragment_data <= system_plic_logic_bus_rsp_payload_fragment_data; + _zz_system_plic_logic_bmb_rsp_payload_fragment_context <= system_plic_logic_bus_rsp_payload_fragment_context; + end + system_cores_0_externalInterrupt_plic_target_bestRequest_priority <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1 : system_cores_0_externalInterrupt_plic_target_requests_2_priority); + system_cores_0_externalInterrupt_plic_target_bestRequest_id <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_id : system_cores_0_externalInterrupt_plic_target_requests_1_id) : system_cores_0_externalInterrupt_plic_target_requests_2_id); + system_cores_0_externalInterrupt_plic_target_bestRequest_valid <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 : system_cores_0_externalInterrupt_plic_target_requests_2_valid); + system_cores_0_externalInterrupt_plic_target_iep_regNext <= system_cores_0_externalInterrupt_plic_target_iep; + end + + always @(posedge io_systemClk) begin + system_cores_0_debugReset <= system_cores_0_logic_cpu_debug_resetOut; + end + + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + _zz_system_cores_0_iBus_rsp_valid_1 <= 1'b0; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid <= 1'b0; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid <= 1'b0; + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + system_fabric_iBus_bmb_cmd_rValid <= 1'b0; + system_bridge_bmb_cmd_rValid <= 1'b0; + system_bridge_bmb_cmd_s2mPipe_rValid <= 1'b0; + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b0; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + system_uart_0_io_interrupt_plic_gateway_ip <= 1'b0; + system_uart_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; + system_spi_0_io_interrupt_plic_gateway_ip <= 1'b0; + system_spi_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + _zz_system_plic_logic_bmb_rsp_valid_2 <= 1'b0; + _zz_system_uart_0_io_interrupt_plic_gateway_priority <= 2'b00; + _zz_system_spi_0_io_interrupt_plic_gateway_priority <= 2'b00; + system_plic_logic_bridge_coherencyStall_value <= 1'b0; + _zz_system_cores_0_externalInterrupt_plic_target_threshold <= 2'b00; + _zz_system_cores_0_externalInterrupt_plic_target_ie_0 <= 1'b0; + _zz_system_cores_0_externalInterrupt_plic_target_ie_1 <= 1'b0; + end else begin + if(_zz_system_cores_0_iBus_connector_decoder_rsp_ready) begin + _zz_system_cores_0_iBus_rsp_valid_1 <= system_cores_0_iBus_connector_decoder_rsp_valid; + end + if(system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready) begin + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_valid; + end + if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_valid; + end + if(_zz_io_input_rsp_ready) begin + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= system_fabric_exclusiveMonitor_logic_io_input_rsp_valid; + end + if(system_fabric_iBus_bmb_cmd_ready) begin + system_fabric_iBus_bmb_cmd_rValid <= system_fabric_iBus_bmb_cmd_valid; + end + if(system_bridge_bmb_cmd_valid) begin + system_bridge_bmb_cmd_rValid <= 1'b1; + end + if(system_bridge_bmb_cmd_s2mPipe_ready) begin + system_bridge_bmb_cmd_rValid <= 1'b0; + end + if(system_bridge_bmb_cmd_s2mPipe_ready) begin + system_bridge_bmb_cmd_s2mPipe_rValid <= system_bridge_bmb_cmd_s2mPipe_valid; + end + if(_zz_io_bus_rsp_ready) begin + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= system_ramA_logic_io_bus_rsp_valid; + end + if(system_bmbPeripheral_bmb_decoder_io_input_rsp_valid) begin + _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b1; + end + if((_zz_system_bmbPeripheral_bmb_rsp_valid && system_bmbPeripheral_bmb_rsp_ready)) begin + _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b0; + end + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + if(system_uart_0_io_logic_io_bus_rsp_valid) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b1; + end + if((_zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready)) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + end + if(when_PlicGateway_l21) begin + system_uart_0_io_interrupt_plic_gateway_ip <= system_uart_0_io_logic_io_interrupt; + system_uart_0_io_interrupt_plic_gateway_waitCompletion <= system_uart_0_io_logic_io_interrupt; + end + if(when_PlicGateway_l21_1) begin + system_spi_0_io_interrupt_plic_gateway_ip <= system_spi_0_io_logic_io_interrupt; + system_spi_0_io_interrupt_plic_gateway_waitCompletion <= system_spi_0_io_logic_io_interrupt; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + if(_zz_system_plic_logic_bus_rsp_ready) begin + _zz_system_plic_logic_bmb_rsp_valid_2 <= (system_plic_logic_bus_rsp_valid && _zz_system_plic_logic_bmb_rsp_valid); + end + if(system_plic_logic_bridge_claim_valid) begin + case(system_plic_logic_bridge_claim_payload) + 3'b001 : begin + system_uart_0_io_interrupt_plic_gateway_ip <= 1'b0; + end + 3'b100 : begin + system_spi_0_io_interrupt_plic_gateway_ip <= 1'b0; + end + default : begin + end + endcase + end + if(system_plic_logic_bridge_completion_valid) begin + case(system_plic_logic_bridge_completion_payload) + 3'b001 : begin + system_uart_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; + end + 3'b100 : begin + system_spi_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; + end + default : begin + end + endcase + end + system_plic_logic_bridge_coherencyStall_value <= system_plic_logic_bridge_coherencyStall_valueNext; + case(system_plic_logic_bmb_cmd_payload_fragment_address) + 22'h000004 : begin + if(system_plic_logic_bus_doWrite) begin + _zz_system_uart_0_io_interrupt_plic_gateway_priority <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; + end + end + 22'h000010 : begin + if(system_plic_logic_bus_doWrite) begin + _zz_system_spi_0_io_interrupt_plic_gateway_priority <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; + end + end + 22'h200000 : begin + if(system_plic_logic_bus_doWrite) begin + _zz_system_cores_0_externalInterrupt_plic_target_threshold <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; + end + end + 22'h002000 : begin + if(system_plic_logic_bus_doWrite) begin + _zz_system_cores_0_externalInterrupt_plic_target_ie_0 <= system_plic_logic_bmb_cmd_payload_fragment_data[1]; + _zz_system_cores_0_externalInterrupt_plic_target_ie_1 <= system_plic_logic_bmb_cmd_payload_fragment_data[4]; + end + end + default : begin + end + endcase + end + end + + always @(posedge io_systemClk) begin + if(debugCd_logic_outputReset) begin + system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext <= 1'b0; + end else begin + system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext <= system_cores_0_logic_cpu_debug_bus_cmd_fire; + end + end + + +endmodule + +module BmbToApb3Bridge_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [15:0] io_input_cmd_payload_fragment_address, + input [1:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_context, + output io_input_rsp_valid, + input io_input_rsp_ready, + output io_input_rsp_payload_last, + output [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output [3:0] io_input_rsp_payload_fragment_context, + output [15:0] io_output_PADDR, + output [0:0] io_output_PSEL, + output io_output_PENABLE, + input io_output_PREADY, + output io_output_PWRITE, + output [31:0] io_output_PWDATA, + input [31:0] io_output_PRDATA, + input io_output_PSLVERROR, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire bmbBuffer_cmd_valid; + reg bmbBuffer_cmd_ready; + wire bmbBuffer_cmd_payload_last; + wire [0:0] bmbBuffer_cmd_payload_fragment_opcode; + wire [15:0] bmbBuffer_cmd_payload_fragment_address; + wire [1:0] bmbBuffer_cmd_payload_fragment_length; + wire [31:0] bmbBuffer_cmd_payload_fragment_data; + wire [3:0] bmbBuffer_cmd_payload_fragment_context; + reg bmbBuffer_rsp_valid; + reg bmbBuffer_rsp_ready; + wire bmbBuffer_rsp_payload_last; + reg [0:0] bmbBuffer_rsp_payload_fragment_opcode; + wire [31:0] bmbBuffer_rsp_payload_fragment_data; + wire [3:0] bmbBuffer_rsp_payload_fragment_context; + wire io_input_rsp_isStall; + wire _zz_io_input_cmd_ready; + wire bmbBuffer_rsp_m2sPipe_valid; + wire bmbBuffer_rsp_m2sPipe_ready; + wire bmbBuffer_rsp_m2sPipe_payload_last; + wire [0:0] bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; + wire [31:0] bmbBuffer_rsp_m2sPipe_payload_fragment_data; + wire [3:0] bmbBuffer_rsp_m2sPipe_payload_fragment_context; + reg bmbBuffer_rsp_rValid; + reg bmbBuffer_rsp_rData_last; + reg [0:0] bmbBuffer_rsp_rData_fragment_opcode; + reg [31:0] bmbBuffer_rsp_rData_fragment_data; + reg [3:0] bmbBuffer_rsp_rData_fragment_context; + wire when_Stream_l368; + reg state; + wire when_BmbToApb3Bridge_l46; + + assign io_input_rsp_isStall = (io_input_rsp_valid && (! io_input_rsp_ready)); + assign _zz_io_input_cmd_ready = (! io_input_rsp_isStall); + assign io_input_cmd_ready = (bmbBuffer_cmd_ready && _zz_io_input_cmd_ready); + assign bmbBuffer_cmd_valid = (io_input_cmd_valid && _zz_io_input_cmd_ready); + assign bmbBuffer_cmd_payload_last = io_input_cmd_payload_last; + assign bmbBuffer_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign bmbBuffer_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign bmbBuffer_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign bmbBuffer_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign bmbBuffer_cmd_payload_fragment_context = io_input_cmd_payload_fragment_context; + always @(*) begin + bmbBuffer_rsp_ready = bmbBuffer_rsp_m2sPipe_ready; + if(when_Stream_l368) begin + bmbBuffer_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! bmbBuffer_rsp_m2sPipe_valid); + assign bmbBuffer_rsp_m2sPipe_valid = bmbBuffer_rsp_rValid; + assign bmbBuffer_rsp_m2sPipe_payload_last = bmbBuffer_rsp_rData_last; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_opcode = bmbBuffer_rsp_rData_fragment_opcode; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_data = bmbBuffer_rsp_rData_fragment_data; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_context = bmbBuffer_rsp_rData_fragment_context; + assign io_input_rsp_valid = bmbBuffer_rsp_m2sPipe_valid; + assign bmbBuffer_rsp_m2sPipe_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = bmbBuffer_rsp_m2sPipe_payload_last; + assign io_input_rsp_payload_fragment_opcode = bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = bmbBuffer_rsp_m2sPipe_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = bmbBuffer_rsp_m2sPipe_payload_fragment_context; + always @(*) begin + bmbBuffer_cmd_ready = 1'b0; + if(!when_BmbToApb3Bridge_l46) begin + if(io_output_PREADY) begin + bmbBuffer_cmd_ready = 1'b1; + end + end + end + + assign io_output_PSEL[0] = bmbBuffer_cmd_valid; + assign io_output_PENABLE = state; + assign io_output_PWRITE = (bmbBuffer_cmd_payload_fragment_opcode == 1'b1); + assign io_output_PADDR = bmbBuffer_cmd_payload_fragment_address; + assign io_output_PWDATA = bmbBuffer_cmd_payload_fragment_data; + always @(*) begin + bmbBuffer_rsp_valid = 1'b0; + if(!when_BmbToApb3Bridge_l46) begin + if(io_output_PREADY) begin + bmbBuffer_rsp_valid = 1'b1; + end + end + end + + assign bmbBuffer_rsp_payload_fragment_data = io_output_PRDATA; + assign when_BmbToApb3Bridge_l46 = (! state); + assign bmbBuffer_rsp_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign bmbBuffer_rsp_payload_last = 1'b1; + always @(*) begin + bmbBuffer_rsp_payload_fragment_opcode = 1'b0; + if(io_output_PSLVERROR) begin + bmbBuffer_rsp_payload_fragment_opcode = 1'b1; + end + end + + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + bmbBuffer_rsp_rValid <= 1'b0; + state <= 1'b0; + end else begin + if(bmbBuffer_rsp_ready) begin + bmbBuffer_rsp_rValid <= bmbBuffer_rsp_valid; + end + if(when_BmbToApb3Bridge_l46) begin + state <= bmbBuffer_cmd_valid; + end else begin + if(io_output_PREADY) begin + state <= 1'b0; + end + end + end + end + + always @(posedge io_systemClk) begin + if(bmbBuffer_rsp_ready) begin + bmbBuffer_rsp_rData_last <= bmbBuffer_rsp_payload_last; + bmbBuffer_rsp_rData_fragment_opcode <= bmbBuffer_rsp_payload_fragment_opcode; + bmbBuffer_rsp_rData_fragment_data <= bmbBuffer_rsp_payload_fragment_data; + bmbBuffer_rsp_rData_fragment_context <= bmbBuffer_rsp_payload_fragment_context; + end + end + + +endmodule + +module BmbSpiXdrMasterCtrl_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_ctrl_cmd_valid, + output io_ctrl_cmd_ready, + input io_ctrl_cmd_payload_last, + input [0:0] io_ctrl_cmd_payload_fragment_opcode, + input [11:0] io_ctrl_cmd_payload_fragment_address, + input [1:0] io_ctrl_cmd_payload_fragment_length, + input [31:0] io_ctrl_cmd_payload_fragment_data, + input [3:0] io_ctrl_cmd_payload_fragment_context, + output io_ctrl_rsp_valid, + input io_ctrl_rsp_ready, + output io_ctrl_rsp_payload_last, + output [0:0] io_ctrl_rsp_payload_fragment_opcode, + output [31:0] io_ctrl_rsp_payload_fragment_data, + output [3:0] io_ctrl_rsp_payload_fragment_context, + output [0:0] io_spi_sclk_write, + output io_spi_data_0_writeEnable, + input [0:0] io_spi_data_0_read, + output [0:0] io_spi_data_0_write, + output io_spi_data_1_writeEnable, + input [0:0] io_spi_data_1_read, + output [0:0] io_spi_data_1_write, + output io_spi_data_2_writeEnable, + input [0:0] io_spi_data_2_read, + output [0:0] io_spi_data_2_write, + output io_spi_data_3_writeEnable, + input [0:0] io_spi_data_3_read, + output [0:0] io_spi_data_3_write, + output [0:0] io_spi_ss, + output io_interrupt, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready; + wire ctrl_io_rsp_queueWithOccupancy_io_pop_ready; + wire ctrl_io_cmd_ready; + wire ctrl_io_rsp_valid; + wire [7:0] ctrl_io_rsp_payload_data; + wire [0:0] ctrl_io_spi_sclk_write; + wire [0:0] ctrl_io_spi_ss; + wire [0:0] ctrl_io_spi_data_0_write; + wire ctrl_io_spi_data_0_writeEnable; + wire [0:0] ctrl_io_spi_data_1_write; + wire ctrl_io_spi_data_1_writeEnable; + wire [0:0] ctrl_io_spi_data_2_write; + wire ctrl_io_spi_data_2_writeEnable; + wire [0:0] ctrl_io_spi_data_3_write; + wire ctrl_io_spi_data_3_writeEnable; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; + wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy; + wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; + wire ctrl_io_rsp_queueWithOccupancy_io_push_ready; + wire ctrl_io_rsp_queueWithOccupancy_io_pop_valid; + wire [7:0] ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_occupancy; + wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_availability; + wire factory_readHaltTrigger; + wire factory_writeHaltTrigger; + wire factory_rsp_valid; + wire factory_rsp_ready; + wire factory_rsp_payload_last; + wire [0:0] factory_rsp_payload_fragment_opcode; + reg [31:0] factory_rsp_payload_fragment_data; + wire [3:0] factory_rsp_payload_fragment_context; + wire _zz_io_ctrl_rsp_valid; + reg _zz_factory_rsp_ready; + wire _zz_io_ctrl_rsp_valid_1; + reg _zz_io_ctrl_rsp_valid_2; + reg _zz_io_ctrl_rsp_payload_last; + reg [0:0] _zz_io_ctrl_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_ctrl_rsp_payload_fragment_data; + reg [3:0] _zz_io_ctrl_rsp_payload_fragment_context; + wire when_Stream_l368; + wire factory_askWrite; + wire factory_askRead; + wire io_ctrl_cmd_fire; + wire factory_doWrite; + wire io_ctrl_cmd_fire_1; + wire factory_doRead; + wire [31:0] mapping_cmdLogic_writeData; + reg mapping_cmdLogic_doRegular; + reg mapping_cmdLogic_doWriteLarge; + reg mapping_cmdLogic_doReadWriteLarge; + wire mapping_cmdLogic_streamUnbuffered_valid; + wire mapping_cmdLogic_streamUnbuffered_ready; + wire mapping_cmdLogic_streamUnbuffered_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_payload_read; + wire mapping_cmdLogic_streamUnbuffered_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_payload_data; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write; + reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; + reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; + wire when_Stream_l368_1; + wire ctrl_io_rsp_toStream_valid; + wire ctrl_io_rsp_toStream_ready; + wire [7:0] ctrl_io_rsp_toStream_payload_data; + reg _zz_io_pop_ready; + reg _zz_io_pop_ready_1; + reg mapping_interruptCtrl_cmdIntEnable; + reg mapping_interruptCtrl_rspIntEnable; + wire mapping_interruptCtrl_cmdInt; + wire mapping_interruptCtrl_rspInt; + wire mapping_interruptCtrl_interrupt; + reg _zz_io_config_kind_cpol; + reg _zz_io_config_kind_cpha; + reg [1:0] _zz_io_config_mod; + reg [11:0] _zz_io_config_sclkToogle; + reg [11:0] _zz_io_config_ss_setup; + reg [11:0] _zz_io_config_ss_hold; + reg [11:0] _zz_io_config_ss_disable; + reg [0:0] _zz_io_config_ss_activeHigh; + wire [1:0] _zz_io_config_kind_cpol_1; + + TopLevel_b62b14ffe6bb44e5a817b8d08e286c6b ctrl ( + .io_config_kind_cpol (_zz_io_config_kind_cpol ), //i + .io_config_kind_cpha (_zz_io_config_kind_cpha ), //i + .io_config_sclkToogle (_zz_io_config_sclkToogle[11:0] ), //i + .io_config_mod (_zz_io_config_mod[1:0] ), //i + .io_config_ss_activeHigh (_zz_io_config_ss_activeHigh ), //i + .io_config_ss_setup (_zz_io_config_ss_setup[11:0] ), //i + .io_config_ss_hold (_zz_io_config_ss_hold[11:0] ), //i + .io_config_ss_disable (_zz_io_config_ss_disable[11:0] ), //i + .io_cmd_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid ), //i + .io_cmd_ready (ctrl_io_cmd_ready ), //o + .io_cmd_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind ), //i + .io_cmd_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read ), //i + .io_cmd_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write ), //i + .io_cmd_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data[7:0]), //i + .io_rsp_valid (ctrl_io_rsp_valid ), //o + .io_rsp_payload_data (ctrl_io_rsp_payload_data[7:0] ), //o + .io_spi_sclk_write (ctrl_io_spi_sclk_write ), //o + .io_spi_data_0_writeEnable (ctrl_io_spi_data_0_writeEnable ), //o + .io_spi_data_0_read (io_spi_data_0_read ), //i + .io_spi_data_0_write (ctrl_io_spi_data_0_write ), //o + .io_spi_data_1_writeEnable (ctrl_io_spi_data_1_writeEnable ), //o + .io_spi_data_1_read (io_spi_data_1_read ), //i + .io_spi_data_1_write (ctrl_io_spi_data_1_write ), //o + .io_spi_data_2_writeEnable (ctrl_io_spi_data_2_writeEnable ), //o + .io_spi_data_2_read (io_spi_data_2_read ), //i + .io_spi_data_2_write (ctrl_io_spi_data_2_write ), //o + .io_spi_data_3_writeEnable (ctrl_io_spi_data_3_writeEnable ), //o + .io_spi_data_3_read (io_spi_data_3_read ), //i + .io_spi_data_3_write (ctrl_io_spi_data_3_write ), //o + .io_spi_ss (ctrl_io_spi_ss ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + StreamFifo_2_b62b14ffe6bb44e5a817b8d08e286c6b mapping_cmdLogic_streamUnbuffered_queueWithAvailability ( + .io_push_valid (mapping_cmdLogic_streamUnbuffered_valid ), //i + .io_push_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready ), //o + .io_push_payload_kind (mapping_cmdLogic_streamUnbuffered_payload_kind ), //i + .io_push_payload_read (mapping_cmdLogic_streamUnbuffered_payload_read ), //i + .io_push_payload_write (mapping_cmdLogic_streamUnbuffered_payload_write ), //i + .io_push_payload_data (mapping_cmdLogic_streamUnbuffered_payload_data[7:0] ), //i + .io_pop_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid ), //o + .io_pop_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready ), //i + .io_pop_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind ), //o + .io_pop_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read ), //o + .io_pop_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write ), //o + .io_pop_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data[7:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy[8:0] ), //o + .io_availability (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability[8:0] ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + StreamFifo_3_b62b14ffe6bb44e5a817b8d08e286c6b ctrl_io_rsp_queueWithOccupancy ( + .io_push_valid (ctrl_io_rsp_toStream_valid ), //i + .io_push_ready (ctrl_io_rsp_queueWithOccupancy_io_push_ready ), //o + .io_push_payload_data (ctrl_io_rsp_toStream_payload_data[7:0] ), //i + .io_pop_valid (ctrl_io_rsp_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (ctrl_io_rsp_queueWithOccupancy_io_pop_ready ), //i + .io_pop_payload_data (ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data[7:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (ctrl_io_rsp_queueWithOccupancy_io_occupancy[8:0] ), //o + .io_availability (ctrl_io_rsp_queueWithOccupancy_io_availability[8:0] ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + assign factory_readHaltTrigger = 1'b0; + assign factory_writeHaltTrigger = 1'b0; + assign _zz_io_ctrl_rsp_valid = (! (factory_readHaltTrigger || factory_writeHaltTrigger)); + assign factory_rsp_ready = (_zz_factory_rsp_ready && _zz_io_ctrl_rsp_valid); + always @(*) begin + _zz_factory_rsp_ready = io_ctrl_rsp_ready; + if(when_Stream_l368) begin + _zz_factory_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! _zz_io_ctrl_rsp_valid_1); + assign _zz_io_ctrl_rsp_valid_1 = _zz_io_ctrl_rsp_valid_2; + assign io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid_1; + assign io_ctrl_rsp_payload_last = _zz_io_ctrl_rsp_payload_last; + assign io_ctrl_rsp_payload_fragment_opcode = _zz_io_ctrl_rsp_payload_fragment_opcode; + assign io_ctrl_rsp_payload_fragment_data = _zz_io_ctrl_rsp_payload_fragment_data; + assign io_ctrl_rsp_payload_fragment_context = _zz_io_ctrl_rsp_payload_fragment_context; + assign factory_askWrite = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign factory_askRead = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign io_ctrl_cmd_fire = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); + assign factory_doWrite = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign io_ctrl_cmd_fire_1 = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); + assign factory_doRead = (io_ctrl_cmd_fire_1 && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign factory_rsp_valid = io_ctrl_cmd_valid; + assign io_ctrl_cmd_ready = factory_rsp_ready; + assign factory_rsp_payload_last = 1'b1; + assign factory_rsp_payload_fragment_opcode = 1'b0; + always @(*) begin + factory_rsp_payload_fragment_data = 32'h0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + factory_rsp_payload_fragment_data[31 : 31] = (! ctrl_io_rsp_queueWithOccupancy_io_pop_valid); + factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + end + 12'h004 : begin + factory_rsp_payload_fragment_data[8 : 0] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; + factory_rsp_payload_fragment_data[24 : 16] = ctrl_io_rsp_queueWithOccupancy_io_occupancy; + end + 12'h00c : begin + factory_rsp_payload_fragment_data[16 : 16] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; + factory_rsp_payload_fragment_data[0 : 0] = mapping_interruptCtrl_cmdIntEnable; + factory_rsp_payload_fragment_data[1 : 1] = mapping_interruptCtrl_rspIntEnable; + factory_rsp_payload_fragment_data[8 : 8] = mapping_interruptCtrl_cmdInt; + factory_rsp_payload_fragment_data[9 : 9] = mapping_interruptCtrl_rspInt; + end + 12'h058 : begin + factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + end + default : begin + end + endcase + end + + assign factory_rsp_payload_fragment_context = io_ctrl_cmd_payload_fragment_context; + always @(*) begin + mapping_cmdLogic_doRegular = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doRegular = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + mapping_cmdLogic_doWriteLarge = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h050 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doWriteLarge = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + mapping_cmdLogic_doReadWriteLarge = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h054 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doReadWriteLarge = 1'b1; + end + end + default : begin + end + endcase + end + + assign mapping_cmdLogic_streamUnbuffered_valid = ((mapping_cmdLogic_doRegular || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_write = (((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[8]) || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_read = ((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[9]) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_kind = (mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[11]); + assign mapping_cmdLogic_streamUnbuffered_payload_data = mapping_cmdLogic_writeData[7:0]; + assign mapping_cmdLogic_streamUnbuffered_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready = (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid || mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data); + always @(*) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; + if(when_Stream_l368_1) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l368_1 = (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready = ctrl_io_cmd_ready; + assign ctrl_io_rsp_toStream_valid = ctrl_io_rsp_valid; + assign ctrl_io_rsp_toStream_payload_data = ctrl_io_rsp_payload_data; + assign ctrl_io_rsp_toStream_ready = ctrl_io_rsp_queueWithOccupancy_io_push_ready; + always @(*) begin + _zz_io_pop_ready = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + if(factory_doRead) begin + _zz_io_pop_ready = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + _zz_io_pop_ready_1 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h058 : begin + if(factory_doRead) begin + _zz_io_pop_ready_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign ctrl_io_rsp_queueWithOccupancy_io_pop_ready = (_zz_io_pop_ready || _zz_io_pop_ready_1); + assign mapping_interruptCtrl_cmdInt = (mapping_interruptCtrl_cmdIntEnable && (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid)); + assign mapping_interruptCtrl_rspInt = (mapping_interruptCtrl_rspIntEnable && ctrl_io_rsp_queueWithOccupancy_io_pop_valid); + assign mapping_interruptCtrl_interrupt = (mapping_interruptCtrl_rspInt || mapping_interruptCtrl_cmdInt); + assign io_spi_sclk_write = ctrl_io_spi_sclk_write; + assign io_spi_data_0_writeEnable = ctrl_io_spi_data_0_writeEnable; + assign io_spi_data_0_write = ctrl_io_spi_data_0_write; + assign io_spi_data_1_writeEnable = ctrl_io_spi_data_1_writeEnable; + assign io_spi_data_1_write = ctrl_io_spi_data_1_write; + assign io_spi_data_2_writeEnable = ctrl_io_spi_data_2_writeEnable; + assign io_spi_data_2_write = ctrl_io_spi_data_2_write; + assign io_spi_data_3_writeEnable = ctrl_io_spi_data_3_writeEnable; + assign io_spi_data_3_write = ctrl_io_spi_data_3_write; + assign io_spi_ss = ctrl_io_spi_ss; + assign io_interrupt = mapping_interruptCtrl_interrupt; + assign mapping_cmdLogic_writeData = io_ctrl_cmd_payload_fragment_data[31 : 0]; + assign _zz_io_config_kind_cpol_1 = io_ctrl_cmd_payload_fragment_data[1 : 0]; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + _zz_io_ctrl_rsp_valid_2 <= 1'b0; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b0; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= 1'b0; + mapping_interruptCtrl_cmdIntEnable <= 1'b0; + mapping_interruptCtrl_rspIntEnable <= 1'b0; + _zz_io_config_ss_activeHigh <= 1'b0; + end else begin + if(_zz_factory_rsp_ready) begin + _zz_io_ctrl_rsp_valid_2 <= (factory_rsp_valid && _zz_io_ctrl_rsp_valid); + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b1; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b0; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; + end + case(io_ctrl_cmd_payload_fragment_address) + 12'h00c : begin + if(factory_doWrite) begin + mapping_interruptCtrl_cmdIntEnable <= io_ctrl_cmd_payload_fragment_data[0]; + mapping_interruptCtrl_rspIntEnable <= io_ctrl_cmd_payload_fragment_data[1]; + end + end + 12'h030 : begin + if(factory_doWrite) begin + _zz_io_config_ss_activeHigh <= io_ctrl_cmd_payload_fragment_data[0 : 0]; + end + end + default : begin + end + endcase + end + end + + always @(posedge io_systemClk) begin + if(_zz_factory_rsp_ready) begin + _zz_io_ctrl_rsp_payload_last <= factory_rsp_payload_last; + _zz_io_ctrl_rsp_payload_fragment_opcode <= factory_rsp_payload_fragment_opcode; + _zz_io_ctrl_rsp_payload_fragment_data <= factory_rsp_payload_fragment_data; + _zz_io_ctrl_rsp_payload_fragment_context <= factory_rsp_payload_fragment_context; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; + end + case(io_ctrl_cmd_payload_fragment_address) + 12'h008 : begin + if(factory_doWrite) begin + _zz_io_config_kind_cpol <= _zz_io_config_kind_cpol_1[0]; + _zz_io_config_kind_cpha <= _zz_io_config_kind_cpol_1[1]; + _zz_io_config_mod <= io_ctrl_cmd_payload_fragment_data[5 : 4]; + end + end + 12'h020 : begin + if(factory_doWrite) begin + _zz_io_config_sclkToogle <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h024 : begin + if(factory_doWrite) begin + _zz_io_config_ss_setup <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h028 : begin + if(factory_doWrite) begin + _zz_io_config_ss_hold <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h02c : begin + if(factory_doWrite) begin + _zz_io_config_ss_disable <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + default : begin + end + endcase + end + + +endmodule + +module BmbUartCtrl_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_bus_cmd_valid, + output io_bus_cmd_ready, + input io_bus_cmd_payload_last, + input [0:0] io_bus_cmd_payload_fragment_opcode, + input [5:0] io_bus_cmd_payload_fragment_address, + input [1:0] io_bus_cmd_payload_fragment_length, + input [31:0] io_bus_cmd_payload_fragment_data, + input [3:0] io_bus_cmd_payload_fragment_context, + output io_bus_rsp_valid, + input io_bus_rsp_ready, + output io_bus_rsp_payload_last, + output [0:0] io_bus_rsp_payload_fragment_opcode, + output [31:0] io_bus_rsp_payload_fragment_data, + output [3:0] io_bus_rsp_payload_fragment_context, + output io_uart_txd, + input io_uart_rxd, + output io_interrupt, + input io_systemClk, + input systemCd_logic_outputReset +); + localparam UartStopType_ONE = 1'd0; + localparam UartStopType_TWO = 1'd1; + localparam UartParityType_NONE = 2'd0; + localparam UartParityType_EVEN = 2'd1; + localparam UartParityType_ODD = 2'd2; + + reg uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready; + wire uartCtrl_1_io_write_ready; + wire uartCtrl_1_io_read_valid; + wire [7:0] uartCtrl_1_io_read_payload; + wire uartCtrl_1_io_uart_txd; + wire uartCtrl_1_io_readError; + wire uartCtrl_1_io_readBreak; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_availability; + wire uartCtrl_1_io_read_queueWithOccupancy_io_push_ready; + wire uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid; + wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload; + wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_occupancy; + wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_availability; + wire [0:0] _zz_bridge_misc_readError; + wire [0:0] _zz_bridge_misc_readOverflowError; + wire [0:0] _zz_bridge_misc_breakDetected; + wire [0:0] _zz_bridge_misc_doBreak; + wire [0:0] _zz_bridge_misc_doBreak_1; + wire [7:0] _zz_busCtrl_rsp_payload_fragment_data; + wire [19:0] _zz_bridge_uartConfigReg_clockDivider; + wire [19:0] _zz_bridge_uartConfigReg_clockDivider_1; + wire busCtrl_readHaltTrigger; + wire busCtrl_writeHaltTrigger; + wire busCtrl_rsp_valid; + wire busCtrl_rsp_ready; + wire busCtrl_rsp_payload_last; + wire [0:0] busCtrl_rsp_payload_fragment_opcode; + reg [31:0] busCtrl_rsp_payload_fragment_data; + wire [3:0] busCtrl_rsp_payload_fragment_context; + wire _zz_io_bus_rsp_valid; + reg _zz_busCtrl_rsp_ready; + wire _zz_io_bus_rsp_valid_1; + reg _zz_io_bus_rsp_valid_2; + reg _zz_io_bus_rsp_payload_last; + reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_bus_rsp_payload_fragment_data; + reg [3:0] _zz_io_bus_rsp_payload_fragment_context; + wire when_Stream_l368; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire io_bus_cmd_fire; + wire busCtrl_doWrite; + wire io_bus_cmd_fire_1; + wire busCtrl_doRead; + reg [2:0] bridge_uartConfigReg_frame_dataLength; + reg [0:0] bridge_uartConfigReg_frame_stop; + reg [1:0] bridge_uartConfigReg_frame_parity; + reg [19:0] bridge_uartConfigReg_clockDivider; + reg _zz_bridge_write_streamUnbuffered_valid; + wire bridge_write_streamUnbuffered_valid; + wire bridge_write_streamUnbuffered_ready; + wire [7:0] bridge_write_streamUnbuffered_payload; + reg bridge_read_streamBreaked_valid; + reg bridge_read_streamBreaked_ready; + wire [7:0] bridge_read_streamBreaked_payload; + reg bridge_interruptCtrl_writeIntEnable; + reg bridge_interruptCtrl_readIntEnable; + wire bridge_interruptCtrl_readInt; + wire bridge_interruptCtrl_writeInt; + wire bridge_interruptCtrl_interrupt; + reg bridge_misc_readError; + reg when_BusSlaveFactory_l335; + wire when_BusSlaveFactory_l341; + reg bridge_misc_readOverflowError; + reg when_BusSlaveFactory_l335_1; + wire when_BusSlaveFactory_l341_1; + wire uartCtrl_1_io_read_isStall; + reg bridge_misc_breakDetected; + reg uartCtrl_1_io_readBreak_regNext; + wire when_UartCtrl_l155; + reg when_BusSlaveFactory_l335_2; + wire when_BusSlaveFactory_l341_2; + reg bridge_misc_doBreak; + reg when_BusSlaveFactory_l371; + wire when_BusSlaveFactory_l373; + reg when_BusSlaveFactory_l335_3; + wire when_BusSlaveFactory_l341_3; + wire [1:0] _zz_bridge_uartConfigReg_frame_parity; + wire [0:0] _zz_bridge_uartConfigReg_frame_stop; + wire when_BmbSlaveFactory_l71; + `ifndef SYNTHESIS + reg [23:0] bridge_uartConfigReg_frame_stop_string; + reg [31:0] bridge_uartConfigReg_frame_parity_string; + reg [31:0] _zz_bridge_uartConfigReg_frame_parity_string; + reg [23:0] _zz_bridge_uartConfigReg_frame_stop_string; + `endif + + + assign _zz_bridge_misc_readError = 1'b0; + assign _zz_bridge_misc_readOverflowError = 1'b0; + assign _zz_bridge_misc_breakDetected = 1'b0; + assign _zz_bridge_misc_doBreak = 1'b1; + assign _zz_bridge_misc_doBreak_1 = 1'b0; + assign _zz_busCtrl_rsp_payload_fragment_data = (8'h80 - bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy); + assign _zz_bridge_uartConfigReg_clockDivider_1 = io_bus_cmd_payload_fragment_data[19 : 0]; + assign _zz_bridge_uartConfigReg_clockDivider = _zz_bridge_uartConfigReg_clockDivider_1; + UartCtrl_b62b14ffe6bb44e5a817b8d08e286c6b uartCtrl_1 ( + .io_config_frame_dataLength (bridge_uartConfigReg_frame_dataLength[2:0] ), //i + .io_config_frame_stop (bridge_uartConfigReg_frame_stop ), //i + .io_config_frame_parity (bridge_uartConfigReg_frame_parity[1:0] ), //i + .io_config_clockDivider (bridge_uartConfigReg_clockDivider[19:0] ), //i + .io_write_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //i + .io_write_ready (uartCtrl_1_io_write_ready ), //o + .io_write_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0]), //i + .io_read_valid (uartCtrl_1_io_read_valid ), //o + .io_read_ready (uartCtrl_1_io_read_queueWithOccupancy_io_push_ready ), //i + .io_read_payload (uartCtrl_1_io_read_payload[7:0] ), //o + .io_uart_txd (uartCtrl_1_io_uart_txd ), //o + .io_uart_rxd (io_uart_rxd ), //i + .io_readError (uartCtrl_1_io_readError ), //o + .io_writeBreak (bridge_misc_doBreak ), //i + .io_readBreak (uartCtrl_1_io_readBreak ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + StreamFifo_b62b14ffe6bb44e5a817b8d08e286c6b bridge_write_streamUnbuffered_queueWithOccupancy ( + .io_push_valid (bridge_write_streamUnbuffered_valid ), //i + .io_push_ready (bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready ), //o + .io_push_payload (bridge_write_streamUnbuffered_payload[7:0] ), //i + .io_pop_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (uartCtrl_1_io_write_ready ), //i + .io_pop_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy[7:0] ), //o + .io_availability (bridge_write_streamUnbuffered_queueWithOccupancy_io_availability[7:0]), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + StreamFifo_b62b14ffe6bb44e5a817b8d08e286c6b uartCtrl_1_io_read_queueWithOccupancy ( + .io_push_valid (uartCtrl_1_io_read_valid ), //i + .io_push_ready (uartCtrl_1_io_read_queueWithOccupancy_io_push_ready ), //o + .io_push_payload (uartCtrl_1_io_read_payload[7:0] ), //i + .io_pop_valid (uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready ), //i + .io_pop_payload (uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (uartCtrl_1_io_read_queueWithOccupancy_io_occupancy[7:0] ), //o + .io_availability (uartCtrl_1_io_read_queueWithOccupancy_io_availability[7:0]), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(bridge_uartConfigReg_frame_stop) + UartStopType_ONE : bridge_uartConfigReg_frame_stop_string = "ONE"; + UartStopType_TWO : bridge_uartConfigReg_frame_stop_string = "TWO"; + default : bridge_uartConfigReg_frame_stop_string = "???"; + endcase + end + always @(*) begin + case(bridge_uartConfigReg_frame_parity) + UartParityType_NONE : bridge_uartConfigReg_frame_parity_string = "NONE"; + UartParityType_EVEN : bridge_uartConfigReg_frame_parity_string = "EVEN"; + UartParityType_ODD : bridge_uartConfigReg_frame_parity_string = "ODD "; + default : bridge_uartConfigReg_frame_parity_string = "????"; + endcase + end + always @(*) begin + case(_zz_bridge_uartConfigReg_frame_parity) + UartParityType_NONE : _zz_bridge_uartConfigReg_frame_parity_string = "NONE"; + UartParityType_EVEN : _zz_bridge_uartConfigReg_frame_parity_string = "EVEN"; + UartParityType_ODD : _zz_bridge_uartConfigReg_frame_parity_string = "ODD "; + default : _zz_bridge_uartConfigReg_frame_parity_string = "????"; + endcase + end + always @(*) begin + case(_zz_bridge_uartConfigReg_frame_stop) + UartStopType_ONE : _zz_bridge_uartConfigReg_frame_stop_string = "ONE"; + UartStopType_TWO : _zz_bridge_uartConfigReg_frame_stop_string = "TWO"; + default : _zz_bridge_uartConfigReg_frame_stop_string = "???"; + endcase + end + `endif + + assign io_uart_txd = uartCtrl_1_io_uart_txd; + assign busCtrl_readHaltTrigger = 1'b0; + assign busCtrl_writeHaltTrigger = 1'b0; + assign _zz_io_bus_rsp_valid = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); + assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready && _zz_io_bus_rsp_valid); + always @(*) begin + _zz_busCtrl_rsp_ready = io_bus_rsp_ready; + if(when_Stream_l368) begin + _zz_busCtrl_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! _zz_io_bus_rsp_valid_1); + assign _zz_io_bus_rsp_valid_1 = _zz_io_bus_rsp_valid_2; + assign io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; + assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; + assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; + assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; + assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; + assign busCtrl_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign busCtrl_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign io_bus_cmd_fire_1 = (io_bus_cmd_valid && io_bus_cmd_ready); + assign busCtrl_doRead = (io_bus_cmd_fire_1 && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign busCtrl_rsp_valid = io_bus_cmd_valid; + assign io_bus_cmd_ready = busCtrl_rsp_ready; + assign busCtrl_rsp_payload_last = 1'b1; + assign busCtrl_rsp_payload_fragment_opcode = 1'b0; + always @(*) begin + busCtrl_rsp_payload_fragment_data = 32'h0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + busCtrl_rsp_payload_fragment_data[16 : 16] = (bridge_read_streamBreaked_valid ^ 1'b0); + busCtrl_rsp_payload_fragment_data[7 : 0] = bridge_read_streamBreaked_payload; + end + 6'h04 : begin + busCtrl_rsp_payload_fragment_data[23 : 16] = _zz_busCtrl_rsp_payload_fragment_data; + busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; + busCtrl_rsp_payload_fragment_data[31 : 24] = uartCtrl_1_io_read_queueWithOccupancy_io_occupancy; + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_interruptCtrl_writeIntEnable; + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_interruptCtrl_readIntEnable; + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_interruptCtrl_writeInt; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_interruptCtrl_readInt; + end + 6'h10 : begin + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_misc_readError; + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_misc_readOverflowError; + busCtrl_rsp_payload_fragment_data[8 : 8] = uartCtrl_1_io_readBreak; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_misc_breakDetected; + end + default : begin + end + endcase + end + + assign busCtrl_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; + always @(*) begin + _zz_bridge_write_streamUnbuffered_valid = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + if(busCtrl_doWrite) begin + _zz_bridge_write_streamUnbuffered_valid = 1'b1; + end + end + default : begin + end + endcase + end + + assign bridge_write_streamUnbuffered_valid = _zz_bridge_write_streamUnbuffered_valid; + assign bridge_write_streamUnbuffered_payload = io_bus_cmd_payload_fragment_data[7 : 0]; + assign bridge_write_streamUnbuffered_ready = bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + always @(*) begin + bridge_read_streamBreaked_valid = uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid; + if(uartCtrl_1_io_readBreak) begin + bridge_read_streamBreaked_valid = 1'b0; + end + end + + always @(*) begin + uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready = bridge_read_streamBreaked_ready; + if(uartCtrl_1_io_readBreak) begin + uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready = 1'b1; + end + end + + assign bridge_read_streamBreaked_payload = uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload; + always @(*) begin + bridge_read_streamBreaked_ready = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + if(busCtrl_doRead) begin + bridge_read_streamBreaked_ready = 1'b1; + end + end + default : begin + end + endcase + end + + assign bridge_interruptCtrl_readInt = (bridge_interruptCtrl_readIntEnable && bridge_read_streamBreaked_valid); + assign bridge_interruptCtrl_writeInt = (bridge_interruptCtrl_writeIntEnable && (! bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid)); + assign bridge_interruptCtrl_interrupt = (bridge_interruptCtrl_readInt || bridge_interruptCtrl_writeInt); + always @(*) begin + when_BusSlaveFactory_l335 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l335 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l341 = io_bus_cmd_payload_fragment_data[0]; + always @(*) begin + when_BusSlaveFactory_l335_1 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l335_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l341_1 = io_bus_cmd_payload_fragment_data[1]; + assign uartCtrl_1_io_read_isStall = (uartCtrl_1_io_read_valid && (! uartCtrl_1_io_read_queueWithOccupancy_io_push_ready)); + assign when_UartCtrl_l155 = (uartCtrl_1_io_readBreak && (! uartCtrl_1_io_readBreak_regNext)); + always @(*) begin + when_BusSlaveFactory_l335_2 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l335_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l341_2 = io_bus_cmd_payload_fragment_data[9]; + always @(*) begin + when_BusSlaveFactory_l371 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l371 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l373 = io_bus_cmd_payload_fragment_data[10]; + always @(*) begin + when_BusSlaveFactory_l335_3 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l335_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l341_3 = io_bus_cmd_payload_fragment_data[11]; + assign io_interrupt = bridge_interruptCtrl_interrupt; + assign _zz_bridge_uartConfigReg_frame_parity = io_bus_cmd_payload_fragment_data[9 : 8]; + assign _zz_bridge_uartConfigReg_frame_stop = io_bus_cmd_payload_fragment_data[16 : 16]; + assign when_BmbSlaveFactory_l71 = ((io_bus_cmd_payload_fragment_address & (~ 6'h03)) == 6'h08); + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + _zz_io_bus_rsp_valid_2 <= 1'b0; + bridge_uartConfigReg_clockDivider <= 20'h0; + bridge_uartConfigReg_clockDivider <= 20'h00035; + bridge_uartConfigReg_frame_dataLength <= 3'b111; + bridge_uartConfigReg_frame_parity <= UartParityType_NONE; + bridge_uartConfigReg_frame_stop <= UartStopType_ONE; + bridge_interruptCtrl_writeIntEnable <= 1'b0; + bridge_interruptCtrl_readIntEnable <= 1'b0; + bridge_misc_readError <= 1'b0; + bridge_misc_readOverflowError <= 1'b0; + bridge_misc_breakDetected <= 1'b0; + bridge_misc_doBreak <= 1'b0; + end else begin + if(_zz_busCtrl_rsp_ready) begin + _zz_io_bus_rsp_valid_2 <= (busCtrl_rsp_valid && _zz_io_bus_rsp_valid); + end + if(when_BusSlaveFactory_l335) begin + if(when_BusSlaveFactory_l341) begin + bridge_misc_readError <= _zz_bridge_misc_readError[0]; + end + end + if(uartCtrl_1_io_readError) begin + bridge_misc_readError <= 1'b1; + end + if(when_BusSlaveFactory_l335_1) begin + if(when_BusSlaveFactory_l341_1) begin + bridge_misc_readOverflowError <= _zz_bridge_misc_readOverflowError[0]; + end + end + if(uartCtrl_1_io_read_isStall) begin + bridge_misc_readOverflowError <= 1'b1; + end + if(when_UartCtrl_l155) begin + bridge_misc_breakDetected <= 1'b1; + end + if(when_BusSlaveFactory_l335_2) begin + if(when_BusSlaveFactory_l341_2) begin + bridge_misc_breakDetected <= _zz_bridge_misc_breakDetected[0]; + end + end + if(when_BusSlaveFactory_l371) begin + if(when_BusSlaveFactory_l373) begin + bridge_misc_doBreak <= _zz_bridge_misc_doBreak[0]; + end + end + if(when_BusSlaveFactory_l335_3) begin + if(when_BusSlaveFactory_l341_3) begin + bridge_misc_doBreak <= _zz_bridge_misc_doBreak_1[0]; + end + end + case(io_bus_cmd_payload_fragment_address) + 6'h0c : begin + if(busCtrl_doWrite) begin + bridge_uartConfigReg_frame_dataLength <= io_bus_cmd_payload_fragment_data[2 : 0]; + bridge_uartConfigReg_frame_parity <= _zz_bridge_uartConfigReg_frame_parity; + bridge_uartConfigReg_frame_stop <= _zz_bridge_uartConfigReg_frame_stop; + end + end + 6'h04 : begin + if(busCtrl_doWrite) begin + bridge_interruptCtrl_writeIntEnable <= io_bus_cmd_payload_fragment_data[0]; + bridge_interruptCtrl_readIntEnable <= io_bus_cmd_payload_fragment_data[1]; + end + end + default : begin + end + endcase + if(when_BmbSlaveFactory_l71) begin + if(busCtrl_doWrite) begin + bridge_uartConfigReg_clockDivider[19 : 0] <= _zz_bridge_uartConfigReg_clockDivider; + end + end + end + end + + always @(posedge io_systemClk) begin + if(_zz_busCtrl_rsp_ready) begin + _zz_io_bus_rsp_payload_last <= busCtrl_rsp_payload_last; + _zz_io_bus_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; + _zz_io_bus_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; + _zz_io_bus_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; + end + uartCtrl_1_io_readBreak_regNext <= uartCtrl_1_io_readBreak; + end + + +endmodule + +module BmbClint_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_bus_cmd_valid, + output io_bus_cmd_ready, + input io_bus_cmd_payload_last, + input [0:0] io_bus_cmd_payload_fragment_opcode, + input [15:0] io_bus_cmd_payload_fragment_address, + input [1:0] io_bus_cmd_payload_fragment_length, + input [31:0] io_bus_cmd_payload_fragment_data, + input [3:0] io_bus_cmd_payload_fragment_context, + output io_bus_rsp_valid, + input io_bus_rsp_ready, + output io_bus_rsp_payload_last, + output [0:0] io_bus_rsp_payload_fragment_opcode, + output [31:0] io_bus_rsp_payload_fragment_data, + output [3:0] io_bus_rsp_payload_fragment_context, + output [0:0] io_timerInterrupt, + output [0:0] io_softwareInterrupt, + output [63:0] io_time, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire [31:0] _zz_logic_harts_0_cmp; + wire [31:0] _zz_logic_harts_0_cmp_1; + wire [31:0] _zz_logic_harts_0_cmp_2; + wire [31:0] _zz_logic_harts_0_cmp_3; + wire factory_readHaltTrigger; + wire factory_writeHaltTrigger; + wire factory_rsp_valid; + wire factory_rsp_ready; + wire factory_rsp_payload_last; + wire [0:0] factory_rsp_payload_fragment_opcode; + reg [31:0] factory_rsp_payload_fragment_data; + wire [3:0] factory_rsp_payload_fragment_context; + wire _zz_io_bus_rsp_valid; + reg _zz_factory_rsp_ready; + wire _zz_io_bus_rsp_valid_1; + reg _zz_io_bus_rsp_valid_2; + reg _zz_io_bus_rsp_payload_last; + reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_bus_rsp_payload_fragment_data; + reg [3:0] _zz_io_bus_rsp_payload_fragment_context; + wire when_Stream_l368; + wire factory_askWrite; + wire factory_askRead; + wire io_bus_cmd_fire; + wire factory_doWrite; + wire io_bus_cmd_fire_1; + wire factory_doRead; + reg [63:0] logic_time; + reg [63:0] logic_harts_0_cmp; + reg logic_harts_0_timerInterrupt; + reg logic_harts_0_softwareInterrupt; + wire [63:0] _zz_factory_rsp_payload_fragment_data; + wire when_BmbSlaveFactory_l71; + wire when_BmbSlaveFactory_l71_1; + wire when_BmbSlaveFactory_l71_2; + wire when_BmbSlaveFactory_l71_3; + + assign _zz_logic_harts_0_cmp_1 = io_bus_cmd_payload_fragment_data[31 : 0]; + assign _zz_logic_harts_0_cmp = _zz_logic_harts_0_cmp_1; + assign _zz_logic_harts_0_cmp_3 = io_bus_cmd_payload_fragment_data[31 : 0]; + assign _zz_logic_harts_0_cmp_2 = _zz_logic_harts_0_cmp_3; + assign factory_readHaltTrigger = 1'b0; + assign factory_writeHaltTrigger = 1'b0; + assign _zz_io_bus_rsp_valid = (! (factory_readHaltTrigger || factory_writeHaltTrigger)); + assign factory_rsp_ready = (_zz_factory_rsp_ready && _zz_io_bus_rsp_valid); + always @(*) begin + _zz_factory_rsp_ready = io_bus_rsp_ready; + if(when_Stream_l368) begin + _zz_factory_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! _zz_io_bus_rsp_valid_1); + assign _zz_io_bus_rsp_valid_1 = _zz_io_bus_rsp_valid_2; + assign io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; + assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; + assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; + assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; + assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; + assign factory_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign factory_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign factory_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign io_bus_cmd_fire_1 = (io_bus_cmd_valid && io_bus_cmd_ready); + assign factory_doRead = (io_bus_cmd_fire_1 && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign factory_rsp_valid = io_bus_cmd_valid; + assign io_bus_cmd_ready = factory_rsp_ready; + assign factory_rsp_payload_last = 1'b1; + assign factory_rsp_payload_fragment_opcode = 1'b0; + always @(*) begin + factory_rsp_payload_fragment_data = 32'h0; + case(io_bus_cmd_payload_fragment_address) + 16'h0 : begin + factory_rsp_payload_fragment_data[0 : 0] = logic_harts_0_softwareInterrupt; + end + default : begin + end + endcase + if(when_BmbSlaveFactory_l71) begin + factory_rsp_payload_fragment_data[31 : 0] = _zz_factory_rsp_payload_fragment_data[31 : 0]; + end + if(when_BmbSlaveFactory_l71_1) begin + factory_rsp_payload_fragment_data[31 : 0] = _zz_factory_rsp_payload_fragment_data[63 : 32]; + end + end + + assign factory_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; + assign _zz_factory_rsp_payload_fragment_data = logic_time; + assign io_timerInterrupt[0] = logic_harts_0_timerInterrupt; + assign io_softwareInterrupt[0] = logic_harts_0_softwareInterrupt; + assign io_time = logic_time; + assign when_BmbSlaveFactory_l71 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'hbff8); + assign when_BmbSlaveFactory_l71_1 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'hbffc); + assign when_BmbSlaveFactory_l71_2 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'h4000); + assign when_BmbSlaveFactory_l71_3 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'h4004); + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + _zz_io_bus_rsp_valid_2 <= 1'b0; + logic_time <= 64'h0; + logic_harts_0_softwareInterrupt <= 1'b0; + end else begin + if(_zz_factory_rsp_ready) begin + _zz_io_bus_rsp_valid_2 <= (factory_rsp_valid && _zz_io_bus_rsp_valid); + end + logic_time <= (logic_time + 64'h0000000000000001); + case(io_bus_cmd_payload_fragment_address) + 16'h0 : begin + if(factory_doWrite) begin + logic_harts_0_softwareInterrupt <= io_bus_cmd_payload_fragment_data[0]; + end + end + default : begin + end + endcase + end + end + + always @(posedge io_systemClk) begin + if(_zz_factory_rsp_ready) begin + _zz_io_bus_rsp_payload_last <= factory_rsp_payload_last; + _zz_io_bus_rsp_payload_fragment_opcode <= factory_rsp_payload_fragment_opcode; + _zz_io_bus_rsp_payload_fragment_data <= factory_rsp_payload_fragment_data; + _zz_io_bus_rsp_payload_fragment_context <= factory_rsp_payload_fragment_context; + end + logic_harts_0_timerInterrupt <= (logic_harts_0_cmp <= logic_time); + if(when_BmbSlaveFactory_l71_2) begin + if(factory_doWrite) begin + logic_harts_0_cmp[31 : 0] <= _zz_logic_harts_0_cmp; + end + end + if(when_BmbSlaveFactory_l71_3) begin + if(factory_doWrite) begin + logic_harts_0_cmp[63 : 32] <= _zz_logic_harts_0_cmp_2; + end + end + end + + +endmodule + +module BmbDecoder_3_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [23:0] io_input_cmd_payload_fragment_address, + input [1:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_mask, + input [3:0] io_input_cmd_payload_fragment_context, + output reg io_input_rsp_valid, + input io_input_rsp_ready, + output reg io_input_rsp_payload_last, + output reg [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output reg [3:0] io_input_rsp_payload_fragment_context, + output reg io_outputs_0_cmd_valid, + input io_outputs_0_cmd_ready, + output io_outputs_0_cmd_payload_last, + output [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output [23:0] io_outputs_0_cmd_payload_fragment_address, + output [1:0] io_outputs_0_cmd_payload_fragment_length, + output [31:0] io_outputs_0_cmd_payload_fragment_data, + output [3:0] io_outputs_0_cmd_payload_fragment_mask, + output [3:0] io_outputs_0_cmd_payload_fragment_context, + input io_outputs_0_rsp_valid, + output io_outputs_0_rsp_ready, + input io_outputs_0_rsp_payload_last, + input [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input [31:0] io_outputs_0_rsp_payload_fragment_data, + input [3:0] io_outputs_0_rsp_payload_fragment_context, + output reg io_outputs_1_cmd_valid, + input io_outputs_1_cmd_ready, + output io_outputs_1_cmd_payload_last, + output [0:0] io_outputs_1_cmd_payload_fragment_opcode, + output [23:0] io_outputs_1_cmd_payload_fragment_address, + output [1:0] io_outputs_1_cmd_payload_fragment_length, + output [31:0] io_outputs_1_cmd_payload_fragment_data, + output [3:0] io_outputs_1_cmd_payload_fragment_mask, + output [3:0] io_outputs_1_cmd_payload_fragment_context, + input io_outputs_1_rsp_valid, + output io_outputs_1_rsp_ready, + input io_outputs_1_rsp_payload_last, + input [0:0] io_outputs_1_rsp_payload_fragment_opcode, + input [31:0] io_outputs_1_rsp_payload_fragment_data, + input [3:0] io_outputs_1_rsp_payload_fragment_context, + output reg io_outputs_2_cmd_valid, + input io_outputs_2_cmd_ready, + output io_outputs_2_cmd_payload_last, + output [0:0] io_outputs_2_cmd_payload_fragment_opcode, + output [23:0] io_outputs_2_cmd_payload_fragment_address, + output [1:0] io_outputs_2_cmd_payload_fragment_length, + output [31:0] io_outputs_2_cmd_payload_fragment_data, + output [3:0] io_outputs_2_cmd_payload_fragment_mask, + output [3:0] io_outputs_2_cmd_payload_fragment_context, + input io_outputs_2_rsp_valid, + output io_outputs_2_rsp_ready, + input io_outputs_2_rsp_payload_last, + input [0:0] io_outputs_2_rsp_payload_fragment_opcode, + input [31:0] io_outputs_2_rsp_payload_fragment_data, + input [3:0] io_outputs_2_rsp_payload_fragment_context, + output reg io_outputs_3_cmd_valid, + input io_outputs_3_cmd_ready, + output io_outputs_3_cmd_payload_last, + output [0:0] io_outputs_3_cmd_payload_fragment_opcode, + output [23:0] io_outputs_3_cmd_payload_fragment_address, + output [1:0] io_outputs_3_cmd_payload_fragment_length, + output [31:0] io_outputs_3_cmd_payload_fragment_data, + output [3:0] io_outputs_3_cmd_payload_fragment_mask, + output [3:0] io_outputs_3_cmd_payload_fragment_context, + input io_outputs_3_rsp_valid, + output io_outputs_3_rsp_ready, + input io_outputs_3_rsp_payload_last, + input [0:0] io_outputs_3_rsp_payload_fragment_opcode, + input [31:0] io_outputs_3_rsp_payload_fragment_data, + input [3:0] io_outputs_3_rsp_payload_fragment_context, + output reg io_outputs_4_cmd_valid, + input io_outputs_4_cmd_ready, + output io_outputs_4_cmd_payload_last, + output [0:0] io_outputs_4_cmd_payload_fragment_opcode, + output [23:0] io_outputs_4_cmd_payload_fragment_address, + output [1:0] io_outputs_4_cmd_payload_fragment_length, + output [31:0] io_outputs_4_cmd_payload_fragment_data, + output [3:0] io_outputs_4_cmd_payload_fragment_mask, + output [3:0] io_outputs_4_cmd_payload_fragment_context, + input io_outputs_4_rsp_valid, + output io_outputs_4_rsp_ready, + input io_outputs_4_rsp_payload_last, + input [0:0] io_outputs_4_rsp_payload_fragment_opcode, + input [31:0] io_outputs_4_rsp_payload_fragment_data, + input [3:0] io_outputs_4_rsp_payload_fragment_context, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire [3:0] _zz_logic_rspPendingCounter; + wire [3:0] _zz_logic_rspPendingCounter_1; + wire [0:0] _zz_logic_rspPendingCounter_2; + wire [3:0] _zz_logic_rspPendingCounter_3; + wire [0:0] _zz_logic_rspPendingCounter_4; + reg _zz_io_input_rsp_payload_last_3; + reg [0:0] _zz_io_input_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_input_rsp_payload_fragment_data; + reg [3:0] _zz_io_input_rsp_payload_fragment_context; + wire logic_input_valid; + reg logic_input_ready; + wire logic_input_payload_last; + wire [0:0] logic_input_payload_fragment_opcode; + wire [23:0] logic_input_payload_fragment_address; + wire [1:0] logic_input_payload_fragment_length; + wire [31:0] logic_input_payload_fragment_data; + wire [3:0] logic_input_payload_fragment_mask; + wire [3:0] logic_input_payload_fragment_context; + reg io_input_cmd_rValid; + wire logic_input_fire; + reg io_input_cmd_rData_last; + reg [0:0] io_input_cmd_rData_fragment_opcode; + reg [23:0] io_input_cmd_rData_fragment_address; + reg [1:0] io_input_cmd_rData_fragment_length; + reg [31:0] io_input_cmd_rData_fragment_data; + reg [3:0] io_input_cmd_rData_fragment_mask; + reg [3:0] io_input_cmd_rData_fragment_context; + wire logic_hitsS0_0; + wire logic_hitsS0_1; + wire logic_hitsS0_2; + wire logic_hitsS0_3; + wire logic_hitsS0_4; + wire logic_noHitS0; + wire io_input_cmd_fire; + reg logic_hitsS1_0; + reg logic_hitsS1_1; + reg logic_hitsS1_2; + reg logic_hitsS1_3; + reg logic_hitsS1_4; + wire io_input_cmd_fire_1; + reg logic_noHitS1; + wire _zz_io_outputs_0_cmd_payload_last; + wire _zz_io_outputs_1_cmd_payload_last; + wire _zz_io_outputs_2_cmd_payload_last; + wire _zz_io_outputs_3_cmd_payload_last; + wire _zz_io_outputs_4_cmd_payload_last; + reg [3:0] logic_rspPendingCounter; + wire logic_input_fire_1; + wire io_input_rsp_fire; + wire logic_cmdWait; + wire when_BmbDecoder_l56; + reg logic_rspHits_0; + reg logic_rspHits_1; + reg logic_rspHits_2; + reg logic_rspHits_3; + reg logic_rspHits_4; + wire logic_rspPending; + wire logic_rspNoHitValid; + reg logic_rspNoHit_doIt; + wire io_input_rsp_fire_1; + wire when_BmbDecoder_l60; + wire logic_input_fire_2; + wire when_BmbDecoder_l60_1; + wire logic_input_fire_3; + reg logic_rspNoHit_singleBeatRsp; + wire logic_input_fire_4; + wire logic_input_fire_5; + reg [3:0] logic_rspNoHit_context; + wire logic_input_fire_6; + wire _zz_io_input_rsp_payload_last; + wire _zz_io_input_rsp_payload_last_1; + wire [2:0] _zz_io_input_rsp_payload_last_2; + + assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); + assign _zz_logic_rspPendingCounter_2 = (logic_input_fire_1 && logic_input_payload_last); + assign _zz_logic_rspPendingCounter_1 = {3'd0, _zz_logic_rspPendingCounter_2}; + assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign _zz_logic_rspPendingCounter_3 = {3'd0, _zz_logic_rspPendingCounter_4}; + always @(*) begin + case(_zz_io_input_rsp_payload_last_2) + 3'b000 : begin + _zz_io_input_rsp_payload_last_3 = io_outputs_0_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_0_rsp_payload_fragment_context; + end + 3'b001 : begin + _zz_io_input_rsp_payload_last_3 = io_outputs_1_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_1_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_1_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_1_rsp_payload_fragment_context; + end + 3'b010 : begin + _zz_io_input_rsp_payload_last_3 = io_outputs_2_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_2_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_2_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_2_rsp_payload_fragment_context; + end + 3'b011 : begin + _zz_io_input_rsp_payload_last_3 = io_outputs_3_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_3_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_3_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_3_rsp_payload_fragment_context; + end + default : begin + _zz_io_input_rsp_payload_last_3 = io_outputs_4_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_4_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_4_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_4_rsp_payload_fragment_context; + end + endcase + end + + assign logic_input_fire = (logic_input_valid && logic_input_ready); + assign io_input_cmd_ready = (! io_input_cmd_rValid); + assign logic_input_valid = io_input_cmd_rValid; + assign logic_input_payload_last = io_input_cmd_rData_last; + assign logic_input_payload_fragment_opcode = io_input_cmd_rData_fragment_opcode; + assign logic_input_payload_fragment_address = io_input_cmd_rData_fragment_address; + assign logic_input_payload_fragment_length = io_input_cmd_rData_fragment_length; + assign logic_input_payload_fragment_data = io_input_cmd_rData_fragment_data; + assign logic_input_payload_fragment_mask = io_input_cmd_rData_fragment_mask; + assign logic_input_payload_fragment_context = io_input_cmd_rData_fragment_context; + assign logic_noHitS0 = (! ({logic_hitsS0_4,{logic_hitsS0_3,{logic_hitsS0_2,{logic_hitsS0_1,logic_hitsS0_0}}}} != 5'h0)); + assign io_input_cmd_fire = (io_input_cmd_valid && io_input_cmd_ready); + assign io_input_cmd_fire_1 = (io_input_cmd_valid && io_input_cmd_ready); + assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 24'h3fffff)) == 24'hc00000); + always @(*) begin + io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS1_0); + if(logic_cmdWait) begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; + assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; + assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_0_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_1 = ((io_input_cmd_payload_fragment_address & (~ 24'h00ffff)) == 24'hb00000); + always @(*) begin + io_outputs_1_cmd_valid = (logic_input_valid && logic_hitsS1_1); + if(logic_cmdWait) begin + io_outputs_1_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_1_cmd_payload_last = logic_input_payload_last; + assign io_outputs_1_cmd_payload_last = _zz_io_outputs_1_cmd_payload_last; + assign io_outputs_1_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_1_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_1_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_1_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_1_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_1_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_2 = ((io_input_cmd_payload_fragment_address & (~ 24'h00003f)) == 24'h010000); + always @(*) begin + io_outputs_2_cmd_valid = (logic_input_valid && logic_hitsS1_2); + if(logic_cmdWait) begin + io_outputs_2_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_2_cmd_payload_last = logic_input_payload_last; + assign io_outputs_2_cmd_payload_last = _zz_io_outputs_2_cmd_payload_last; + assign io_outputs_2_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_2_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_2_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_2_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_2_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_2_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_3 = ((io_input_cmd_payload_fragment_address & (~ 24'h000fff)) == 24'h014000); + always @(*) begin + io_outputs_3_cmd_valid = (logic_input_valid && logic_hitsS1_3); + if(logic_cmdWait) begin + io_outputs_3_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_3_cmd_payload_last = logic_input_payload_last; + assign io_outputs_3_cmd_payload_last = _zz_io_outputs_3_cmd_payload_last; + assign io_outputs_3_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_3_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_3_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_3_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_3_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_3_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_4 = ((io_input_cmd_payload_fragment_address & (~ 24'h00ffff)) == 24'h100000); + always @(*) begin + io_outputs_4_cmd_valid = (logic_input_valid && logic_hitsS1_4); + if(logic_cmdWait) begin + io_outputs_4_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_4_cmd_payload_last = logic_input_payload_last; + assign io_outputs_4_cmd_payload_last = _zz_io_outputs_4_cmd_payload_last; + assign io_outputs_4_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_4_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_4_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_4_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_4_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_4_cmd_payload_fragment_context = logic_input_payload_fragment_context; + always @(*) begin + logic_input_ready = (({(logic_hitsS1_4 && io_outputs_4_cmd_ready),{(logic_hitsS1_3 && io_outputs_3_cmd_ready),{(logic_hitsS1_2 && io_outputs_2_cmd_ready),{(logic_hitsS1_1 && io_outputs_1_cmd_ready),(logic_hitsS1_0 && io_outputs_0_cmd_ready)}}}} != 5'h0) || logic_noHitS1); + if(logic_cmdWait) begin + logic_input_ready = 1'b0; + end + end + + assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); + assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); + assign logic_rspPending = (logic_rspPendingCounter != 4'b0000); + assign logic_rspNoHitValid = (! ({logic_rspHits_4,{logic_rspHits_3,{logic_rspHits_2,{logic_rspHits_1,logic_rspHits_0}}}} != 5'h0)); + assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); + assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); + assign when_BmbDecoder_l60_1 = ((logic_input_fire_2 && logic_noHitS1) && logic_input_payload_last); + assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_6 = (logic_input_valid && logic_input_ready); + always @(*) begin + io_input_rsp_valid = (({io_outputs_4_rsp_valid,{io_outputs_3_rsp_valid,{io_outputs_2_rsp_valid,{io_outputs_1_rsp_valid,io_outputs_0_rsp_valid}}}} != 5'h0) || (logic_rspPending && logic_rspNoHitValid)); + if(logic_rspNoHit_doIt) begin + io_input_rsp_valid = 1'b1; + end + end + + assign _zz_io_input_rsp_payload_last = (logic_rspHits_1 || logic_rspHits_3); + assign _zz_io_input_rsp_payload_last_1 = (logic_rspHits_2 || logic_rspHits_3); + assign _zz_io_input_rsp_payload_last_2 = {logic_rspHits_4,{_zz_io_input_rsp_payload_last_1,_zz_io_input_rsp_payload_last}}; + always @(*) begin + io_input_rsp_payload_last = _zz_io_input_rsp_payload_last_3; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_last = 1'b1; + end + end + + always @(*) begin + io_input_rsp_payload_fragment_opcode = _zz_io_input_rsp_payload_fragment_opcode; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_opcode = 1'b1; + end + end + + assign io_input_rsp_payload_fragment_data = _zz_io_input_rsp_payload_fragment_data; + always @(*) begin + io_input_rsp_payload_fragment_context = _zz_io_input_rsp_payload_fragment_context; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_context = logic_rspNoHit_context; + end + end + + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign io_outputs_1_rsp_ready = io_input_rsp_ready; + assign io_outputs_2_rsp_ready = io_input_rsp_ready; + assign io_outputs_3_rsp_ready = io_input_rsp_ready; + assign io_outputs_4_rsp_ready = io_input_rsp_ready; + assign logic_cmdWait = ((logic_rspPending && ((((((logic_hitsS1_0 != logic_rspHits_0) || (logic_hitsS1_1 != logic_rspHits_1)) || (logic_hitsS1_2 != logic_rspHits_2)) || (logic_hitsS1_3 != logic_rspHits_3)) || (logic_hitsS1_4 != logic_rspHits_4)) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 4'b1000)); + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + io_input_cmd_rValid <= 1'b0; + logic_rspPendingCounter <= 4'b0000; + logic_rspNoHit_doIt <= 1'b0; + end else begin + if(io_input_cmd_valid) begin + io_input_cmd_rValid <= 1'b1; + end + if(logic_input_fire) begin + io_input_cmd_rValid <= 1'b0; + end + logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); + if(when_BmbDecoder_l60) begin + logic_rspNoHit_doIt <= 1'b0; + end + if(when_BmbDecoder_l60_1) begin + logic_rspNoHit_doIt <= 1'b1; + end + end + end + + always @(posedge io_systemClk) begin + if(io_input_cmd_ready) begin + io_input_cmd_rData_last <= io_input_cmd_payload_last; + io_input_cmd_rData_fragment_opcode <= io_input_cmd_payload_fragment_opcode; + io_input_cmd_rData_fragment_address <= io_input_cmd_payload_fragment_address; + io_input_cmd_rData_fragment_length <= io_input_cmd_payload_fragment_length; + io_input_cmd_rData_fragment_data <= io_input_cmd_payload_fragment_data; + io_input_cmd_rData_fragment_mask <= io_input_cmd_payload_fragment_mask; + io_input_cmd_rData_fragment_context <= io_input_cmd_payload_fragment_context; + end + if(io_input_cmd_fire) begin + logic_hitsS1_0 <= logic_hitsS0_0; + logic_hitsS1_1 <= logic_hitsS0_1; + logic_hitsS1_2 <= logic_hitsS0_2; + logic_hitsS1_3 <= logic_hitsS0_3; + logic_hitsS1_4 <= logic_hitsS0_4; + end + if(io_input_cmd_fire_1) begin + logic_noHitS1 <= logic_noHitS0; + end + if(when_BmbDecoder_l56) begin + logic_rspHits_0 <= logic_hitsS1_0; + logic_rspHits_1 <= logic_hitsS1_1; + logic_rspHits_2 <= logic_hitsS1_2; + logic_rspHits_3 <= logic_hitsS1_3; + logic_rspHits_4 <= logic_hitsS1_4; + end + if(logic_input_fire_3) begin + logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); + end + if(logic_input_fire_5) begin + logic_rspNoHit_context <= logic_input_payload_fragment_context; + end + end + + +endmodule + +//BmbUnburstify_b62b14ffe6bb44e5a817b8d08e286c6b replaced by BmbUnburstify_b62b14ffe6bb44e5a817b8d08e286c6b + +module BmbUnburstify_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_input_cmd_valid, + output reg io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_source, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [31:0] io_input_cmd_payload_fragment_address, + input [5:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_mask, + input [0:0] io_input_cmd_payload_fragment_context, + output io_input_rsp_valid, + input io_input_rsp_ready, + output io_input_rsp_payload_last, + output [0:0] io_input_rsp_payload_fragment_source, + output [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output [0:0] io_input_rsp_payload_fragment_context, + output reg io_output_cmd_valid, + input io_output_cmd_ready, + output io_output_cmd_payload_last, + output reg [0:0] io_output_cmd_payload_fragment_opcode, + output reg [31:0] io_output_cmd_payload_fragment_address, + output reg [1:0] io_output_cmd_payload_fragment_length, + output [31:0] io_output_cmd_payload_fragment_data, + output [3:0] io_output_cmd_payload_fragment_mask, + output [3:0] io_output_cmd_payload_fragment_context, + input io_output_rsp_valid, + output reg io_output_rsp_ready, + input io_output_rsp_payload_last, + input [0:0] io_output_rsp_payload_fragment_opcode, + input [31:0] io_output_rsp_payload_fragment_data, + input [3:0] io_output_rsp_payload_fragment_context, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire [3:0] _zz_buffer_last; + wire [0:0] _zz_buffer_last_1; + wire [11:0] _zz_buffer_addressIncr; + wire [11:0] _zz_buffer_addressIncr_1; + wire [11:0] _zz_buffer_addressIncr_2; + wire doResult; + reg buffer_valid; + reg [0:0] buffer_opcode; + reg [0:0] buffer_source; + reg [31:0] buffer_address; + reg [0:0] buffer_context; + reg [3:0] buffer_beat; + wire buffer_last; + wire [31:0] buffer_addressIncr; + wire buffer_isWrite; + wire io_output_cmd_fire; + wire [3:0] cmdTransferBeatCount; + wire requireBuffer; + reg cmdContext_drop; + reg cmdContext_last; + reg [0:0] cmdContext_source; + reg [0:0] cmdContext_context; + wire io_output_cmd_fire_1; + wire rspContext_drop; + wire rspContext_last; + wire [0:0] rspContext_source; + wire [0:0] rspContext_context; + wire [3:0] _zz_rspContext_drop; + wire when_Stream_l434; + reg io_output_rsp_thrown_valid; + wire io_output_rsp_thrown_ready; + wire io_output_rsp_thrown_payload_last; + wire [0:0] io_output_rsp_thrown_payload_fragment_opcode; + wire [31:0] io_output_rsp_thrown_payload_fragment_data; + wire [3:0] io_output_rsp_thrown_payload_fragment_context; + + assign _zz_buffer_last_1 = 1'b1; + assign _zz_buffer_last = {3'd0, _zz_buffer_last_1}; + assign _zz_buffer_addressIncr = (_zz_buffer_addressIncr_1 + 12'h004); + assign _zz_buffer_addressIncr_2 = buffer_address[11 : 0]; + assign _zz_buffer_addressIncr_1 = _zz_buffer_addressIncr_2; + assign buffer_last = (buffer_beat == _zz_buffer_last); + assign buffer_addressIncr = {buffer_address[31 : 12],(_zz_buffer_addressIncr & (~ 12'h003))}; + assign buffer_isWrite = (buffer_opcode == 1'b1); + assign io_output_cmd_fire = (io_output_cmd_valid && io_output_cmd_ready); + assign cmdTransferBeatCount = io_input_cmd_payload_fragment_length[5 : 2]; + assign requireBuffer = (cmdTransferBeatCount != 4'b0000); + assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign io_output_cmd_payload_last = 1'b1; + assign io_output_cmd_payload_fragment_context = {cmdContext_context,{cmdContext_source,{cmdContext_last,cmdContext_drop}}}; + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_address = buffer_addressIncr; + end else begin + io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + if(requireBuffer) begin + io_output_cmd_payload_fragment_address[1 : 0] = 2'b00; + end + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_opcode = buffer_opcode; + end else begin + io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_length = 2'b11; + end else begin + if(requireBuffer) begin + io_output_cmd_payload_fragment_length = 2'b11; + end else begin + io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length[1:0]; + end + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_context = buffer_context; + end else begin + cmdContext_context = io_input_cmd_payload_fragment_context; + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_source = buffer_source; + end else begin + cmdContext_source = io_input_cmd_payload_fragment_source; + end + end + + always @(*) begin + io_input_cmd_ready = 1'b0; + if(buffer_valid) begin + io_input_cmd_ready = (buffer_isWrite && io_output_cmd_ready); + end else begin + io_input_cmd_ready = io_output_cmd_ready; + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_valid = (! (buffer_isWrite && (! io_input_cmd_valid))); + end else begin + io_output_cmd_valid = io_input_cmd_valid; + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_last = buffer_last; + end else begin + cmdContext_last = (! requireBuffer); + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_drop = buffer_isWrite; + end else begin + cmdContext_drop = (io_input_cmd_payload_fragment_opcode == 1'b1); + end + end + + assign io_output_cmd_fire_1 = (io_output_cmd_valid && io_output_cmd_ready); + assign _zz_rspContext_drop = io_output_rsp_payload_fragment_context; + assign rspContext_drop = _zz_rspContext_drop[0]; + assign rspContext_last = _zz_rspContext_drop[1]; + assign rspContext_source = _zz_rspContext_drop[2 : 2]; + assign rspContext_context = _zz_rspContext_drop[3 : 3]; + assign when_Stream_l434 = (! (rspContext_last || (! rspContext_drop))); + always @(*) begin + io_output_rsp_thrown_valid = io_output_rsp_valid; + if(when_Stream_l434) begin + io_output_rsp_thrown_valid = 1'b0; + end + end + + always @(*) begin + io_output_rsp_ready = io_output_rsp_thrown_ready; + if(when_Stream_l434) begin + io_output_rsp_ready = 1'b1; + end + end + + assign io_output_rsp_thrown_payload_last = io_output_rsp_payload_last; + assign io_output_rsp_thrown_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_output_rsp_thrown_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_output_rsp_thrown_payload_fragment_context = io_output_rsp_payload_fragment_context; + assign io_input_rsp_valid = io_output_rsp_thrown_valid; + assign io_output_rsp_thrown_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = rspContext_last; + assign io_input_rsp_payload_fragment_source = rspContext_source; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = rspContext_context; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + buffer_valid <= 1'b0; + end else begin + if(io_output_cmd_fire) begin + if(buffer_last) begin + buffer_valid <= 1'b0; + end + end + if(!buffer_valid) begin + buffer_valid <= (requireBuffer && io_output_cmd_fire_1); + end + end + end + + always @(posedge io_systemClk) begin + if(io_output_cmd_fire) begin + buffer_beat <= (buffer_beat - 4'b0001); + buffer_address[11 : 0] <= buffer_addressIncr[11 : 0]; + end + if(!buffer_valid) begin + buffer_opcode <= io_input_cmd_payload_fragment_opcode; + buffer_source <= io_input_cmd_payload_fragment_source; + buffer_address <= io_input_cmd_payload_fragment_address; + buffer_context <= io_input_cmd_payload_fragment_context; + buffer_beat <= cmdTransferBeatCount; + end + end + + +endmodule + +module BmbOnChipRam_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_bus_cmd_valid, + output io_bus_cmd_ready, + input io_bus_cmd_payload_last, + input [0:0] io_bus_cmd_payload_fragment_opcode, + input [14:0] io_bus_cmd_payload_fragment_address, + input [1:0] io_bus_cmd_payload_fragment_length, + input [31:0] io_bus_cmd_payload_fragment_data, + input [3:0] io_bus_cmd_payload_fragment_mask, + input [3:0] io_bus_cmd_payload_fragment_context, + output io_bus_rsp_valid, + input io_bus_rsp_ready, + output io_bus_rsp_payload_last, + output [0:0] io_bus_rsp_payload_fragment_opcode, + output [31:0] io_bus_rsp_payload_fragment_data, + output [3:0] io_bus_rsp_payload_fragment_context, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [31:0] _zz_ram_port0; + wire io_bus_rsp_isStall; + reg io_bus_cmd_valid_regNextWhen; + reg [3:0] io_bus_cmd_payload_fragment_context_regNextWhen; + wire [12:0] _zz_io_bus_rsp_payload_fragment_data; + wire io_bus_cmd_fire; + wire _zz_io_bus_rsp_payload_fragment_data_1; + wire [31:0] _zz_io_bus_rsp_payload_fragment_data_2; + reg [7:0] ram_symbol0 [0:8191]; + reg [7:0] ram_symbol1 [0:8191]; + reg [7:0] ram_symbol2 [0:8191]; + reg [7:0] ram_symbol3 [0:8191]; + reg [7:0] _zz_ramsymbol_read; + reg [7:0] _zz_ramsymbol_read_1; + reg [7:0] _zz_ramsymbol_read_2; + reg [7:0] _zz_ramsymbol_read_3; + + initial begin + $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol0.bin",ram_symbol0); + $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol1.bin",ram_symbol1); + $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol2.bin",ram_symbol2); + $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol3.bin",ram_symbol3); + end + always @(*) begin + _zz_ram_port0 = {_zz_ramsymbol_read_3, _zz_ramsymbol_read_2, _zz_ramsymbol_read_1, _zz_ramsymbol_read}; + end + always @(posedge io_systemClk) begin + if(io_bus_cmd_fire) begin + _zz_ramsymbol_read <= ram_symbol0[_zz_io_bus_rsp_payload_fragment_data]; + _zz_ramsymbol_read_1 <= ram_symbol1[_zz_io_bus_rsp_payload_fragment_data]; + _zz_ramsymbol_read_2 <= ram_symbol2[_zz_io_bus_rsp_payload_fragment_data]; + _zz_ramsymbol_read_3 <= ram_symbol3[_zz_io_bus_rsp_payload_fragment_data]; + end + end + + always @(posedge io_systemClk) begin + if(io_bus_cmd_payload_fragment_mask[0] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin + ram_symbol0[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[7 : 0]; + end + if(io_bus_cmd_payload_fragment_mask[1] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin + ram_symbol1[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[15 : 8]; + end + if(io_bus_cmd_payload_fragment_mask[2] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin + ram_symbol2[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[23 : 16]; + end + if(io_bus_cmd_payload_fragment_mask[3] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin + ram_symbol3[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[31 : 24]; + end + end + + assign io_bus_rsp_isStall = (io_bus_rsp_valid && (! io_bus_rsp_ready)); + assign io_bus_cmd_ready = (! io_bus_rsp_isStall); + assign io_bus_rsp_valid = io_bus_cmd_valid_regNextWhen; + assign io_bus_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context_regNextWhen; + assign _zz_io_bus_rsp_payload_fragment_data = (io_bus_cmd_payload_fragment_address >>> 2); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign _zz_io_bus_rsp_payload_fragment_data_1 = (io_bus_cmd_payload_fragment_opcode == 1'b1); + assign _zz_io_bus_rsp_payload_fragment_data_2 = io_bus_cmd_payload_fragment_data; + assign io_bus_rsp_payload_fragment_data = _zz_ram_port0; + assign io_bus_rsp_payload_fragment_opcode = 1'b0; + assign io_bus_rsp_payload_last = 1'b1; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + io_bus_cmd_valid_regNextWhen <= 1'b0; + end else begin + if(io_bus_cmd_ready) begin + io_bus_cmd_valid_regNextWhen <= io_bus_cmd_valid; + end + end + end + + always @(posedge io_systemClk) begin + if(io_bus_cmd_ready) begin + io_bus_cmd_payload_fragment_context_regNextWhen <= io_bus_cmd_payload_fragment_context; + end + end + + +endmodule + +module BmbDecoder_2_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_source, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [31:0] io_input_cmd_payload_fragment_address, + input [5:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_mask, + input [0:0] io_input_cmd_payload_fragment_context, + output reg io_input_rsp_valid, + input io_input_rsp_ready, + output reg io_input_rsp_payload_last, + output reg [0:0] io_input_rsp_payload_fragment_source, + output reg [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output reg [0:0] io_input_rsp_payload_fragment_context, + output reg io_outputs_0_cmd_valid, + input io_outputs_0_cmd_ready, + output io_outputs_0_cmd_payload_last, + output [0:0] io_outputs_0_cmd_payload_fragment_source, + output [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output [31:0] io_outputs_0_cmd_payload_fragment_address, + output [5:0] io_outputs_0_cmd_payload_fragment_length, + output [31:0] io_outputs_0_cmd_payload_fragment_data, + output [3:0] io_outputs_0_cmd_payload_fragment_mask, + output [0:0] io_outputs_0_cmd_payload_fragment_context, + input io_outputs_0_rsp_valid, + output io_outputs_0_rsp_ready, + input io_outputs_0_rsp_payload_last, + input [0:0] io_outputs_0_rsp_payload_fragment_source, + input [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input [31:0] io_outputs_0_rsp_payload_fragment_data, + input [0:0] io_outputs_0_rsp_payload_fragment_context, + output reg io_outputs_1_cmd_valid, + input io_outputs_1_cmd_ready, + output io_outputs_1_cmd_payload_last, + output [0:0] io_outputs_1_cmd_payload_fragment_source, + output [0:0] io_outputs_1_cmd_payload_fragment_opcode, + output [31:0] io_outputs_1_cmd_payload_fragment_address, + output [5:0] io_outputs_1_cmd_payload_fragment_length, + output [31:0] io_outputs_1_cmd_payload_fragment_data, + output [3:0] io_outputs_1_cmd_payload_fragment_mask, + output [0:0] io_outputs_1_cmd_payload_fragment_context, + input io_outputs_1_rsp_valid, + output io_outputs_1_rsp_ready, + input io_outputs_1_rsp_payload_last, + input [0:0] io_outputs_1_rsp_payload_fragment_source, + input [0:0] io_outputs_1_rsp_payload_fragment_opcode, + input [31:0] io_outputs_1_rsp_payload_fragment_data, + input [0:0] io_outputs_1_rsp_payload_fragment_context, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire [6:0] _zz_logic_rspPendingCounter; + wire [6:0] _zz_logic_rspPendingCounter_1; + wire [0:0] _zz_logic_rspPendingCounter_2; + wire [6:0] _zz_logic_rspPendingCounter_3; + wire [0:0] _zz_logic_rspPendingCounter_4; + reg _zz_io_input_rsp_payload_last_1; + reg [0:0] _zz_io_input_rsp_payload_fragment_source; + reg [0:0] _zz_io_input_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_input_rsp_payload_fragment_data; + reg [0:0] _zz_io_input_rsp_payload_fragment_context; + wire logic_input_valid; + reg logic_input_ready; + wire logic_input_payload_last; + wire [0:0] logic_input_payload_fragment_source; + wire [0:0] logic_input_payload_fragment_opcode; + wire [31:0] logic_input_payload_fragment_address; + wire [5:0] logic_input_payload_fragment_length; + wire [31:0] logic_input_payload_fragment_data; + wire [3:0] logic_input_payload_fragment_mask; + wire [0:0] logic_input_payload_fragment_context; + wire logic_hitsS0_0; + wire logic_hitsS0_1; + wire logic_noHitS0; + wire _zz_io_outputs_0_cmd_payload_last; + wire _zz_io_outputs_1_cmd_payload_last; + reg [6:0] logic_rspPendingCounter; + wire logic_input_fire; + wire io_input_rsp_fire; + wire logic_cmdWait; + wire when_BmbDecoder_l56; + reg logic_rspHits_0; + reg logic_rspHits_1; + wire logic_rspPending; + wire logic_rspNoHitValid; + reg logic_rspNoHit_doIt; + wire io_input_rsp_fire_1; + wire when_BmbDecoder_l60; + wire logic_input_fire_1; + wire when_BmbDecoder_l60_1; + wire logic_input_fire_2; + reg logic_rspNoHit_singleBeatRsp; + wire logic_input_fire_3; + reg [0:0] logic_rspNoHit_source; + wire logic_input_fire_4; + reg [0:0] logic_rspNoHit_context; + wire logic_input_fire_5; + reg [3:0] logic_rspNoHit_counter; + wire [0:0] _zz_io_input_rsp_payload_last; + wire when_BmbDecoder_l81; + wire io_input_rsp_fire_2; + + assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); + assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); + assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; + assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; + always @(*) begin + case(_zz_io_input_rsp_payload_last) + 1'b0 : begin + _zz_io_input_rsp_payload_last_1 = io_outputs_0_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_source = io_outputs_0_rsp_payload_fragment_source; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_0_rsp_payload_fragment_context; + end + default : begin + _zz_io_input_rsp_payload_last_1 = io_outputs_1_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_source = io_outputs_1_rsp_payload_fragment_source; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_1_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_1_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_1_rsp_payload_fragment_context; + end + endcase + end + + assign logic_input_valid = io_input_cmd_valid; + assign io_input_cmd_ready = logic_input_ready; + assign logic_input_payload_last = io_input_cmd_payload_last; + assign logic_input_payload_fragment_source = io_input_cmd_payload_fragment_source; + assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign logic_input_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign logic_noHitS0 = (! ({logic_hitsS0_1,logic_hitsS0_0} != 2'b00)); + assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 32'h00007fff)) == 32'hf9000000); + always @(*) begin + io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); + if(logic_cmdWait) begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; + assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; + assign io_outputs_0_cmd_payload_fragment_source = logic_input_payload_fragment_source; + assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_0_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_1 = ((io_input_cmd_payload_fragment_address & (~ 32'h00ffffff)) == 32'hf8000000); + always @(*) begin + io_outputs_1_cmd_valid = (logic_input_valid && logic_hitsS0_1); + if(logic_cmdWait) begin + io_outputs_1_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_1_cmd_payload_last = logic_input_payload_last; + assign io_outputs_1_cmd_payload_last = _zz_io_outputs_1_cmd_payload_last; + assign io_outputs_1_cmd_payload_fragment_source = logic_input_payload_fragment_source; + assign io_outputs_1_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_1_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_1_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_1_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_1_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_1_cmd_payload_fragment_context = logic_input_payload_fragment_context; + always @(*) begin + logic_input_ready = (({(logic_hitsS0_1 && io_outputs_1_cmd_ready),(logic_hitsS0_0 && io_outputs_0_cmd_ready)} != 2'b00) || logic_noHitS0); + if(logic_cmdWait) begin + logic_input_ready = 1'b0; + end + end + + assign logic_input_fire = (logic_input_valid && logic_input_ready); + assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); + assign logic_rspPending = (logic_rspPendingCounter != 7'h0); + assign logic_rspNoHitValid = (! ({logic_rspHits_1,logic_rspHits_0} != 2'b00)); + assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); + assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); + assign when_BmbDecoder_l60_1 = ((logic_input_fire_1 && logic_noHitS0) && logic_input_payload_last); + assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); + always @(*) begin + io_input_rsp_valid = (({io_outputs_1_rsp_valid,io_outputs_0_rsp_valid} != 2'b00) || (logic_rspPending && logic_rspNoHitValid)); + if(logic_rspNoHit_doIt) begin + io_input_rsp_valid = 1'b1; + end + end + + assign _zz_io_input_rsp_payload_last = logic_rspHits_1; + always @(*) begin + io_input_rsp_payload_last = _zz_io_input_rsp_payload_last_1; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_last = 1'b0; + if(when_BmbDecoder_l81) begin + io_input_rsp_payload_last = 1'b1; + end + if(logic_rspNoHit_singleBeatRsp) begin + io_input_rsp_payload_last = 1'b1; + end + end + end + + always @(*) begin + io_input_rsp_payload_fragment_source = _zz_io_input_rsp_payload_fragment_source; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_source = logic_rspNoHit_source; + end + end + + always @(*) begin + io_input_rsp_payload_fragment_opcode = _zz_io_input_rsp_payload_fragment_opcode; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_opcode = 1'b1; + end + end + + assign io_input_rsp_payload_fragment_data = _zz_io_input_rsp_payload_fragment_data; + always @(*) begin + io_input_rsp_payload_fragment_context = _zz_io_input_rsp_payload_fragment_context; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_context = logic_rspNoHit_context; + end + end + + assign when_BmbDecoder_l81 = (logic_rspNoHit_counter == 4'b0000); + assign io_input_rsp_fire_2 = (io_input_rsp_valid && io_input_rsp_ready); + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign io_outputs_1_rsp_ready = io_input_rsp_ready; + assign logic_cmdWait = ((logic_rspPending && (((logic_hitsS0_0 != logic_rspHits_0) || (logic_hitsS0_1 != logic_rspHits_1)) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + logic_rspPendingCounter <= 7'h0; + logic_rspNoHit_doIt <= 1'b0; + end else begin + logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); + if(when_BmbDecoder_l60) begin + logic_rspNoHit_doIt <= 1'b0; + end + if(when_BmbDecoder_l60_1) begin + logic_rspNoHit_doIt <= 1'b1; + end + end + end + + always @(posedge io_systemClk) begin + if(when_BmbDecoder_l56) begin + logic_rspHits_0 <= logic_hitsS0_0; + logic_rspHits_1 <= logic_hitsS0_1; + end + if(logic_input_fire_2) begin + logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); + end + if(logic_input_fire_3) begin + logic_rspNoHit_source <= logic_input_payload_fragment_source; + end + if(logic_input_fire_4) begin + logic_rspNoHit_context <= logic_input_payload_fragment_context; + end + if(logic_input_fire_5) begin + logic_rspNoHit_counter <= logic_input_payload_fragment_length[5 : 2]; + end + if(logic_rspNoHit_doIt) begin + if(io_input_rsp_fire_2) begin + logic_rspNoHit_counter <= (logic_rspNoHit_counter - 4'b0001); + end + end + end + + +endmodule + +module BmbArbiter_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_inputs_0_cmd_valid, + output io_inputs_0_cmd_ready, + input io_inputs_0_cmd_payload_last, + input [0:0] io_inputs_0_cmd_payload_fragment_opcode, + input [31:0] io_inputs_0_cmd_payload_fragment_address, + input [5:0] io_inputs_0_cmd_payload_fragment_length, + input [31:0] io_inputs_0_cmd_payload_fragment_data, + input [3:0] io_inputs_0_cmd_payload_fragment_mask, + input [0:0] io_inputs_0_cmd_payload_fragment_context, + output io_inputs_0_rsp_valid, + input io_inputs_0_rsp_ready, + output io_inputs_0_rsp_payload_last, + output [0:0] io_inputs_0_rsp_payload_fragment_opcode, + output [31:0] io_inputs_0_rsp_payload_fragment_data, + output [0:0] io_inputs_0_rsp_payload_fragment_context, + input io_inputs_1_cmd_valid, + output io_inputs_1_cmd_ready, + input io_inputs_1_cmd_payload_last, + input [0:0] io_inputs_1_cmd_payload_fragment_opcode, + input [31:0] io_inputs_1_cmd_payload_fragment_address, + input [5:0] io_inputs_1_cmd_payload_fragment_length, + input [31:0] io_inputs_1_cmd_payload_fragment_data, + input [3:0] io_inputs_1_cmd_payload_fragment_mask, + output io_inputs_1_rsp_valid, + input io_inputs_1_rsp_ready, + output io_inputs_1_rsp_payload_last, + output [0:0] io_inputs_1_rsp_payload_fragment_opcode, + output [31:0] io_inputs_1_rsp_payload_fragment_data, + output io_output_cmd_valid, + input io_output_cmd_ready, + output io_output_cmd_payload_last, + output [0:0] io_output_cmd_payload_fragment_source, + output [0:0] io_output_cmd_payload_fragment_opcode, + output [31:0] io_output_cmd_payload_fragment_address, + output [5:0] io_output_cmd_payload_fragment_length, + output [31:0] io_output_cmd_payload_fragment_data, + output [3:0] io_output_cmd_payload_fragment_mask, + output [0:0] io_output_cmd_payload_fragment_context, + input io_output_rsp_valid, + output io_output_rsp_ready, + input io_output_rsp_payload_last, + input [0:0] io_output_rsp_payload_fragment_source, + input [0:0] io_output_rsp_payload_fragment_opcode, + input [31:0] io_output_rsp_payload_fragment_data, + input [0:0] io_output_rsp_payload_fragment_context, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire memory_arbiter_io_inputs_0_ready; + wire memory_arbiter_io_inputs_1_ready; + wire memory_arbiter_io_output_valid; + wire memory_arbiter_io_output_payload_last; + wire [0:0] memory_arbiter_io_output_payload_fragment_source; + wire [0:0] memory_arbiter_io_output_payload_fragment_opcode; + wire [31:0] memory_arbiter_io_output_payload_fragment_address; + wire [5:0] memory_arbiter_io_output_payload_fragment_length; + wire [31:0] memory_arbiter_io_output_payload_fragment_data; + wire [3:0] memory_arbiter_io_output_payload_fragment_mask; + wire [0:0] memory_arbiter_io_output_payload_fragment_context; + wire [0:0] memory_arbiter_io_chosen; + wire [1:0] memory_arbiter_io_chosenOH; + wire [1:0] _zz_io_output_cmd_payload_fragment_source; + reg _zz_io_output_rsp_ready; + wire [0:0] memory_rspSel; + + assign _zz_io_output_cmd_payload_fragment_source = {memory_arbiter_io_output_payload_fragment_source,memory_arbiter_io_chosen}; + StreamArbiter_b62b14ffe6bb44e5a817b8d08e286c6b memory_arbiter ( + .io_inputs_0_valid (io_inputs_0_cmd_valid ), //i + .io_inputs_0_ready (memory_arbiter_io_inputs_0_ready ), //o + .io_inputs_0_payload_last (io_inputs_0_cmd_payload_last ), //i + .io_inputs_0_payload_fragment_source (1'b0 ), //i + .io_inputs_0_payload_fragment_opcode (io_inputs_0_cmd_payload_fragment_opcode ), //i + .io_inputs_0_payload_fragment_address (io_inputs_0_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_0_payload_fragment_length (io_inputs_0_cmd_payload_fragment_length[5:0] ), //i + .io_inputs_0_payload_fragment_data (io_inputs_0_cmd_payload_fragment_data[31:0] ), //i + .io_inputs_0_payload_fragment_mask (io_inputs_0_cmd_payload_fragment_mask[3:0] ), //i + .io_inputs_0_payload_fragment_context (io_inputs_0_cmd_payload_fragment_context ), //i + .io_inputs_1_valid (io_inputs_1_cmd_valid ), //i + .io_inputs_1_ready (memory_arbiter_io_inputs_1_ready ), //o + .io_inputs_1_payload_last (io_inputs_1_cmd_payload_last ), //i + .io_inputs_1_payload_fragment_source (1'b0 ), //i + .io_inputs_1_payload_fragment_opcode (io_inputs_1_cmd_payload_fragment_opcode ), //i + .io_inputs_1_payload_fragment_address (io_inputs_1_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_1_payload_fragment_length (io_inputs_1_cmd_payload_fragment_length[5:0] ), //i + .io_inputs_1_payload_fragment_data (io_inputs_1_cmd_payload_fragment_data[31:0] ), //i + .io_inputs_1_payload_fragment_mask (io_inputs_1_cmd_payload_fragment_mask[3:0] ), //i + .io_inputs_1_payload_fragment_context (1'b0 ), //i + .io_output_valid (memory_arbiter_io_output_valid ), //o + .io_output_ready (io_output_cmd_ready ), //i + .io_output_payload_last (memory_arbiter_io_output_payload_last ), //o + .io_output_payload_fragment_source (memory_arbiter_io_output_payload_fragment_source ), //o + .io_output_payload_fragment_opcode (memory_arbiter_io_output_payload_fragment_opcode ), //o + .io_output_payload_fragment_address (memory_arbiter_io_output_payload_fragment_address[31:0]), //o + .io_output_payload_fragment_length (memory_arbiter_io_output_payload_fragment_length[5:0] ), //o + .io_output_payload_fragment_data (memory_arbiter_io_output_payload_fragment_data[31:0] ), //o + .io_output_payload_fragment_mask (memory_arbiter_io_output_payload_fragment_mask[3:0] ), //o + .io_output_payload_fragment_context (memory_arbiter_io_output_payload_fragment_context ), //o + .io_chosen (memory_arbiter_io_chosen ), //o + .io_chosenOH (memory_arbiter_io_chosenOH[1:0] ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + always @(*) begin + case(memory_rspSel) + 1'b0 : _zz_io_output_rsp_ready = io_inputs_0_rsp_ready; + default : _zz_io_output_rsp_ready = io_inputs_1_rsp_ready; + endcase + end + + assign io_inputs_0_cmd_ready = memory_arbiter_io_inputs_0_ready; + assign io_inputs_1_cmd_ready = memory_arbiter_io_inputs_1_ready; + assign io_output_cmd_valid = memory_arbiter_io_output_valid; + assign io_output_cmd_payload_last = memory_arbiter_io_output_payload_last; + assign io_output_cmd_payload_fragment_opcode = memory_arbiter_io_output_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = memory_arbiter_io_output_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = memory_arbiter_io_output_payload_fragment_length; + assign io_output_cmd_payload_fragment_data = memory_arbiter_io_output_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = memory_arbiter_io_output_payload_fragment_mask; + assign io_output_cmd_payload_fragment_context = memory_arbiter_io_output_payload_fragment_context; + assign io_output_cmd_payload_fragment_source = _zz_io_output_cmd_payload_fragment_source[0:0]; + assign memory_rspSel = io_output_rsp_payload_fragment_source[0 : 0]; + assign io_inputs_0_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b0)); + assign io_inputs_0_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_0_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_0_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_inputs_0_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; + assign io_inputs_1_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b1)); + assign io_inputs_1_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_1_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_1_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_output_rsp_ready = _zz_io_output_rsp_ready; + +endmodule + +module BmbDecoder_1_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [31:0] io_input_cmd_payload_fragment_address, + input [5:0] io_input_cmd_payload_fragment_length, + output io_input_rsp_valid, + input io_input_rsp_ready, + output io_input_rsp_payload_last, + output [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output io_outputs_0_cmd_valid, + input io_outputs_0_cmd_ready, + output io_outputs_0_cmd_payload_last, + output [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output [31:0] io_outputs_0_cmd_payload_fragment_address, + output [5:0] io_outputs_0_cmd_payload_fragment_length, + input io_outputs_0_rsp_valid, + output io_outputs_0_rsp_ready, + input io_outputs_0_rsp_payload_last, + input [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input [31:0] io_outputs_0_rsp_payload_fragment_data +); + + + assign io_outputs_0_cmd_valid = io_input_cmd_valid; + assign io_input_cmd_ready = io_outputs_0_cmd_ready; + assign io_input_rsp_valid = io_outputs_0_rsp_valid; + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign io_outputs_0_cmd_payload_last = io_input_cmd_payload_last; + assign io_input_rsp_payload_last = io_outputs_0_rsp_payload_last; + assign io_outputs_0_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + +endmodule + +module BmbExclusiveMonitor_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [31:0] io_input_cmd_payload_fragment_address, + input [5:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_mask, + input [0:0] io_input_cmd_payload_fragment_context, + output io_input_rsp_valid, + input io_input_rsp_ready, + output io_input_rsp_payload_last, + output [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output [0:0] io_input_rsp_payload_fragment_context, + output io_output_cmd_valid, + input io_output_cmd_ready, + output io_output_cmd_payload_last, + output [0:0] io_output_cmd_payload_fragment_opcode, + output [31:0] io_output_cmd_payload_fragment_address, + output [5:0] io_output_cmd_payload_fragment_length, + output [31:0] io_output_cmd_payload_fragment_data, + output [3:0] io_output_cmd_payload_fragment_mask, + output [0:0] io_output_cmd_payload_fragment_context, + input io_output_rsp_valid, + output io_output_rsp_ready, + input io_output_rsp_payload_last, + input [0:0] io_output_rsp_payload_fragment_opcode, + input [31:0] io_output_rsp_payload_fragment_data, + input [0:0] io_output_rsp_payload_fragment_context +); + + + assign io_output_cmd_valid = io_input_cmd_valid; + assign io_input_cmd_ready = io_output_cmd_ready; + assign io_input_rsp_valid = io_output_rsp_valid; + assign io_output_rsp_ready = io_input_rsp_ready; + assign io_output_cmd_payload_last = io_input_cmd_payload_last; + assign io_input_rsp_payload_last = io_output_rsp_payload_last; + assign io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign io_output_cmd_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; + +endmodule + +module BmbDecoder_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [31:0] io_input_cmd_payload_fragment_address, + input [1:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_mask, + output reg io_input_rsp_valid, + input io_input_rsp_ready, + output reg io_input_rsp_payload_last, + output reg [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output reg io_outputs_0_cmd_valid, + input io_outputs_0_cmd_ready, + output io_outputs_0_cmd_payload_last, + output [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output [31:0] io_outputs_0_cmd_payload_fragment_address, + output [1:0] io_outputs_0_cmd_payload_fragment_length, + output [31:0] io_outputs_0_cmd_payload_fragment_data, + output [3:0] io_outputs_0_cmd_payload_fragment_mask, + input io_outputs_0_rsp_valid, + output io_outputs_0_rsp_ready, + input io_outputs_0_rsp_payload_last, + input [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input [31:0] io_outputs_0_rsp_payload_fragment_data, + input io_systemClk, + input debugCd_logic_outputReset +); + + wire [6:0] _zz_logic_rspPendingCounter; + wire [6:0] _zz_logic_rspPendingCounter_1; + wire [0:0] _zz_logic_rspPendingCounter_2; + wire [6:0] _zz_logic_rspPendingCounter_3; + wire [0:0] _zz_logic_rspPendingCounter_4; + wire logic_input_valid; + reg logic_input_ready; + wire logic_input_payload_last; + wire [0:0] logic_input_payload_fragment_opcode; + wire [31:0] logic_input_payload_fragment_address; + wire [1:0] logic_input_payload_fragment_length; + wire [31:0] logic_input_payload_fragment_data; + wire [3:0] logic_input_payload_fragment_mask; + wire logic_hitsS0_0; + wire logic_noHitS0; + wire _zz_io_outputs_0_cmd_payload_last; + reg [6:0] logic_rspPendingCounter; + wire logic_input_fire; + wire io_input_rsp_fire; + wire logic_cmdWait; + wire when_BmbDecoder_l56; + reg logic_rspHits_0; + wire logic_rspPending; + wire logic_rspNoHitValid; + reg logic_rspNoHit_doIt; + wire io_input_rsp_fire_1; + wire when_BmbDecoder_l60; + wire logic_input_fire_1; + wire when_BmbDecoder_l60_1; + wire logic_input_fire_2; + reg logic_rspNoHit_singleBeatRsp; + wire logic_input_fire_3; + wire logic_input_fire_4; + wire logic_input_fire_5; + + assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); + assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); + assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; + assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; + assign logic_input_valid = io_input_cmd_valid; + assign io_input_cmd_ready = logic_input_ready; + assign logic_input_payload_last = io_input_cmd_payload_last; + assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign logic_noHitS0 = (! (logic_hitsS0_0 != 1'b0)); + assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 32'h00000fff)) == 32'h10b80000); + always @(*) begin + io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); + if(logic_cmdWait) begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; + assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; + assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + always @(*) begin + logic_input_ready = (((logic_hitsS0_0 && io_outputs_0_cmd_ready) != 1'b0) || logic_noHitS0); + if(logic_cmdWait) begin + logic_input_ready = 1'b0; + end + end + + assign logic_input_fire = (logic_input_valid && logic_input_ready); + assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); + assign logic_rspPending = (logic_rspPendingCounter != 7'h0); + assign logic_rspNoHitValid = (! (logic_rspHits_0 != 1'b0)); + assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); + assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); + assign when_BmbDecoder_l60_1 = ((logic_input_fire_1 && logic_noHitS0) && logic_input_payload_last); + assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); + always @(*) begin + io_input_rsp_valid = ((io_outputs_0_rsp_valid != 1'b0) || (logic_rspPending && logic_rspNoHitValid)); + if(logic_rspNoHit_doIt) begin + io_input_rsp_valid = 1'b1; + end + end + + always @(*) begin + io_input_rsp_payload_last = io_outputs_0_rsp_payload_last; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_last = 1'b1; + end + end + + always @(*) begin + io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_opcode = 1'b1; + end + end + + assign io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign logic_cmdWait = ((logic_rspPending && ((logic_hitsS0_0 != logic_rspHits_0) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); + always @(posedge io_systemClk) begin + if(debugCd_logic_outputReset) begin + logic_rspPendingCounter <= 7'h0; + logic_rspNoHit_doIt <= 1'b0; + end else begin + logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); + if(when_BmbDecoder_l60) begin + logic_rspNoHit_doIt <= 1'b0; + end + if(when_BmbDecoder_l60_1) begin + logic_rspNoHit_doIt <= 1'b1; + end + end + end + + always @(posedge io_systemClk) begin + if(when_BmbDecoder_l56) begin + logic_rspHits_0 <= logic_hitsS0_0; + end + if(logic_input_fire_2) begin + logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); + end + end + + +endmodule + +module BufferCC_4_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_dataIn, + output io_dataOut, + input io_systemClk, + input system_cores_0_debugReset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge io_systemClk or posedge system_cores_0_debugReset) begin + if(system_cores_0_debugReset) begin + buffers_0 <= 1'b1; + buffers_1 <= 1'b1; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module SystemDebugger_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_remote_cmd_valid, + output io_remote_cmd_ready, + input io_remote_cmd_payload_last, + input [0:0] io_remote_cmd_payload_fragment, + output io_remote_rsp_valid, + input io_remote_rsp_ready, + output io_remote_rsp_payload_error, + output [31:0] io_remote_rsp_payload_data, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output io_mem_cmd_payload_wr, + output [1:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload, + input io_systemClk, + input debugCd_logic_outputReset +); + + reg [66:0] dispatcher_dataShifter; + reg dispatcher_dataLoaded; + reg [7:0] dispatcher_headerShifter; + wire [7:0] dispatcher_header; + reg dispatcher_headerLoaded; + reg [2:0] dispatcher_counter; + wire when_Fragment_l346; + wire when_Fragment_l349; + wire [66:0] _zz_io_mem_cmd_payload_address; + wire io_mem_cmd_isStall; + wire when_Fragment_l372; + + assign dispatcher_header = dispatcher_headerShifter[7 : 0]; + assign when_Fragment_l346 = (dispatcher_headerLoaded == 1'b0); + assign when_Fragment_l349 = (dispatcher_counter == 3'b111); + assign io_remote_cmd_ready = (! dispatcher_dataLoaded); + assign _zz_io_mem_cmd_payload_address = dispatcher_dataShifter[66 : 0]; + assign io_mem_cmd_payload_address = _zz_io_mem_cmd_payload_address[31 : 0]; + assign io_mem_cmd_payload_data = _zz_io_mem_cmd_payload_address[63 : 32]; + assign io_mem_cmd_payload_wr = _zz_io_mem_cmd_payload_address[64]; + assign io_mem_cmd_payload_size = _zz_io_mem_cmd_payload_address[66 : 65]; + assign io_mem_cmd_valid = (dispatcher_dataLoaded && (dispatcher_header == 8'h0)); + assign io_mem_cmd_isStall = (io_mem_cmd_valid && (! io_mem_cmd_ready)); + assign when_Fragment_l372 = ((dispatcher_headerLoaded && dispatcher_dataLoaded) && (! io_mem_cmd_isStall)); + assign io_remote_rsp_valid = io_mem_rsp_valid; + assign io_remote_rsp_payload_error = 1'b0; + assign io_remote_rsp_payload_data = io_mem_rsp_payload; + always @(posedge io_systemClk) begin + if(debugCd_logic_outputReset) begin + dispatcher_dataLoaded <= 1'b0; + dispatcher_headerLoaded <= 1'b0; + dispatcher_counter <= 3'b000; + end else begin + if(io_remote_cmd_valid) begin + if(when_Fragment_l346) begin + dispatcher_counter <= (dispatcher_counter + 3'b001); + if(when_Fragment_l349) begin + dispatcher_headerLoaded <= 1'b1; + end + end + if(io_remote_cmd_payload_last) begin + dispatcher_headerLoaded <= 1'b1; + dispatcher_dataLoaded <= 1'b1; + dispatcher_counter <= 3'b000; + end + end + if(when_Fragment_l372) begin + dispatcher_headerLoaded <= 1'b0; + dispatcher_dataLoaded <= 1'b0; + end + end + end + + always @(posedge io_systemClk) begin + if(io_remote_cmd_valid) begin + if(when_Fragment_l346) begin + dispatcher_headerShifter <= ({io_remote_cmd_payload_fragment,dispatcher_headerShifter} >>> 1); + end else begin + dispatcher_dataShifter <= ({io_remote_cmd_payload_fragment,dispatcher_dataShifter} >>> 1); + end + end + end + + +endmodule + +module JtagBridgeNoTap_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_ctrl_tdi, + input io_ctrl_enable, + input io_ctrl_capture, + input io_ctrl_shift, + input io_ctrl_update, + input io_ctrl_reset, + output io_ctrl_tdo, + output io_remote_cmd_valid, + input io_remote_cmd_ready, + output io_remote_cmd_payload_last, + output [0:0] io_remote_cmd_payload_fragment, + input io_remote_rsp_valid, + output io_remote_rsp_ready, + input io_remote_rsp_payload_error, + input [31:0] io_remote_rsp_payload_data, + input io_systemClk, + input debugCd_logic_outputReset, + input jtagCtrl_tck +); + + wire flowCCByToggle_1_io_output_valid; + wire flowCCByToggle_1_io_output_payload_last; + wire [0:0] flowCCByToggle_1_io_output_payload_fragment; + wire system_cmd_valid; + wire system_cmd_payload_last; + wire [0:0] system_cmd_payload_fragment; + wire system_cmd_toStream_valid; + wire system_cmd_toStream_ready; + wire system_cmd_toStream_payload_last; + wire [0:0] system_cmd_toStream_payload_fragment; + (* async_reg = "true" *) reg system_rsp_valid; + (* async_reg = "true" *) reg system_rsp_payload_error; + (* async_reg = "true" *) reg [31:0] system_rsp_payload_data; + wire io_remote_rsp_fire; + wire jtag_wrapper_ctrl_tdi; + wire jtag_wrapper_ctrl_enable; + wire jtag_wrapper_ctrl_capture; + wire jtag_wrapper_ctrl_shift; + wire jtag_wrapper_ctrl_update; + wire jtag_wrapper_ctrl_reset; + reg jtag_wrapper_ctrl_tdo; + reg [1:0] jtag_wrapper_header; + wire [1:0] jtag_wrapper_headerNext; + reg [0:0] jtag_wrapper_counter; + reg jtag_wrapper_done; + reg jtag_wrapper_sendCapture; + reg jtag_wrapper_sendShift; + reg jtag_wrapper_sendUpdate; + wire when_JtagTapInstructions_l183; + wire when_JtagTapInstructions_l186; + wire jtag_writeArea_ctrl_tdi; + wire jtag_writeArea_ctrl_enable; + wire jtag_writeArea_ctrl_capture; + wire jtag_writeArea_ctrl_shift; + wire jtag_writeArea_ctrl_update; + wire jtag_writeArea_ctrl_reset; + wire jtag_writeArea_ctrl_tdo; + wire jtag_writeArea_source_valid; + wire jtag_writeArea_source_payload_last; + wire [0:0] jtag_writeArea_source_payload_fragment; + reg jtag_writeArea_valid; + reg jtag_writeArea_data; + wire when_JtagTapInstructions_l209; + wire jtag_readArea_ctrl_tdi; + wire jtag_readArea_ctrl_enable; + wire jtag_readArea_ctrl_capture; + wire jtag_readArea_ctrl_shift; + wire jtag_readArea_ctrl_update; + wire jtag_readArea_ctrl_reset; + wire jtag_readArea_ctrl_tdo; + reg [33:0] jtag_readArea_full_shifter; + wire when_JtagTapInstructions_l209_1; + + FlowCCByToggle_b62b14ffe6bb44e5a817b8d08e286c6b flowCCByToggle_1 ( + .io_input_valid (jtag_writeArea_source_valid ), //i + .io_input_payload_last (jtag_writeArea_source_payload_last ), //i + .io_input_payload_fragment (jtag_writeArea_source_payload_fragment ), //i + .io_output_valid (flowCCByToggle_1_io_output_valid ), //o + .io_output_payload_last (flowCCByToggle_1_io_output_payload_last ), //o + .io_output_payload_fragment (flowCCByToggle_1_io_output_payload_fragment), //o + .jtagCtrl_tck (jtagCtrl_tck ), //i + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i + ); + assign system_cmd_toStream_valid = system_cmd_valid; + assign system_cmd_toStream_payload_last = system_cmd_payload_last; + assign system_cmd_toStream_payload_fragment = system_cmd_payload_fragment; + assign io_remote_cmd_valid = system_cmd_toStream_valid; + assign system_cmd_toStream_ready = io_remote_cmd_ready; + assign io_remote_cmd_payload_last = system_cmd_toStream_payload_last; + assign io_remote_cmd_payload_fragment = system_cmd_toStream_payload_fragment; + assign io_remote_rsp_fire = (io_remote_rsp_valid && io_remote_rsp_ready); + assign io_remote_rsp_ready = 1'b1; + assign jtag_wrapper_headerNext = ({jtag_wrapper_ctrl_tdi,jtag_wrapper_header} >>> 1); + always @(*) begin + jtag_wrapper_sendCapture = 1'b0; + if(jtag_wrapper_ctrl_enable) begin + if(jtag_wrapper_ctrl_shift) begin + if(when_JtagTapInstructions_l183) begin + if(when_JtagTapInstructions_l186) begin + jtag_wrapper_sendCapture = 1'b1; + end + end + end + end + end + + always @(*) begin + jtag_wrapper_sendShift = 1'b0; + if(jtag_wrapper_ctrl_enable) begin + if(jtag_wrapper_ctrl_shift) begin + if(!when_JtagTapInstructions_l183) begin + jtag_wrapper_sendShift = 1'b1; + end + end + end + end + + always @(*) begin + jtag_wrapper_sendUpdate = 1'b0; + if(jtag_wrapper_ctrl_enable) begin + if(jtag_wrapper_ctrl_update) begin + jtag_wrapper_sendUpdate = 1'b1; + end + end + end + + assign when_JtagTapInstructions_l183 = (! jtag_wrapper_done); + assign when_JtagTapInstructions_l186 = (jtag_wrapper_counter == 1'b1); + always @(*) begin + jtag_wrapper_ctrl_tdo = 1'b0; + if(when_JtagTapInstructions_l209) begin + jtag_wrapper_ctrl_tdo = jtag_writeArea_ctrl_tdo; + end + if(when_JtagTapInstructions_l209_1) begin + jtag_wrapper_ctrl_tdo = jtag_readArea_ctrl_tdo; + end + end + + assign jtag_wrapper_ctrl_tdi = io_ctrl_tdi; + assign jtag_wrapper_ctrl_enable = io_ctrl_enable; + assign jtag_wrapper_ctrl_capture = io_ctrl_capture; + assign jtag_wrapper_ctrl_shift = io_ctrl_shift; + assign jtag_wrapper_ctrl_update = io_ctrl_update; + assign jtag_wrapper_ctrl_reset = io_ctrl_reset; + assign io_ctrl_tdo = jtag_wrapper_ctrl_tdo; + assign jtag_writeArea_source_valid = jtag_writeArea_valid; + assign jtag_writeArea_source_payload_last = (! (jtag_writeArea_ctrl_enable && jtag_writeArea_ctrl_shift)); + assign jtag_writeArea_source_payload_fragment[0] = jtag_writeArea_data; + assign system_cmd_valid = flowCCByToggle_1_io_output_valid; + assign system_cmd_payload_last = flowCCByToggle_1_io_output_payload_last; + assign system_cmd_payload_fragment = flowCCByToggle_1_io_output_payload_fragment; + assign jtag_writeArea_ctrl_tdo = 1'b0; + assign when_JtagTapInstructions_l209 = (jtag_wrapper_header == 2'b00); + assign jtag_writeArea_ctrl_tdi = jtag_wrapper_ctrl_tdi; + assign jtag_writeArea_ctrl_enable = 1'b1; + assign jtag_writeArea_ctrl_capture = ((jtag_wrapper_headerNext == 2'b00) && jtag_wrapper_sendCapture); + assign jtag_writeArea_ctrl_shift = (when_JtagTapInstructions_l209 && jtag_wrapper_sendShift); + assign jtag_writeArea_ctrl_update = (when_JtagTapInstructions_l209 && jtag_wrapper_sendUpdate); + assign jtag_writeArea_ctrl_reset = jtag_wrapper_ctrl_reset; + assign jtag_readArea_ctrl_tdo = jtag_readArea_full_shifter[0]; + assign when_JtagTapInstructions_l209_1 = (jtag_wrapper_header == 2'b01); + assign jtag_readArea_ctrl_tdi = jtag_wrapper_ctrl_tdi; + assign jtag_readArea_ctrl_enable = 1'b1; + assign jtag_readArea_ctrl_capture = ((jtag_wrapper_headerNext == 2'b01) && jtag_wrapper_sendCapture); + assign jtag_readArea_ctrl_shift = (when_JtagTapInstructions_l209_1 && jtag_wrapper_sendShift); + assign jtag_readArea_ctrl_update = (when_JtagTapInstructions_l209_1 && jtag_wrapper_sendUpdate); + assign jtag_readArea_ctrl_reset = jtag_wrapper_ctrl_reset; + always @(posedge io_systemClk) begin + if(io_remote_cmd_valid) begin + system_rsp_valid <= 1'b0; + end + if(io_remote_rsp_fire) begin + system_rsp_valid <= 1'b1; + system_rsp_payload_error <= io_remote_rsp_payload_error; + system_rsp_payload_data <= io_remote_rsp_payload_data; + end + end + + always @(posedge jtagCtrl_tck) begin + if(jtag_wrapper_ctrl_enable) begin + if(jtag_wrapper_ctrl_capture) begin + jtag_wrapper_done <= 1'b0; + jtag_wrapper_counter <= 1'b0; + end + if(jtag_wrapper_ctrl_shift) begin + if(when_JtagTapInstructions_l183) begin + jtag_wrapper_counter <= (jtag_wrapper_counter + 1'b1); + jtag_wrapper_header <= jtag_wrapper_headerNext; + if(when_JtagTapInstructions_l186) begin + jtag_wrapper_done <= 1'b1; + end + end + end + end + jtag_writeArea_valid <= (jtag_writeArea_ctrl_enable && jtag_writeArea_ctrl_shift); + jtag_writeArea_data <= jtag_writeArea_ctrl_tdi; + if(jtag_readArea_ctrl_enable) begin + if(jtag_readArea_ctrl_capture) begin + jtag_readArea_full_shifter <= {{system_rsp_payload_data,system_rsp_payload_error},system_rsp_valid}; + end + if(jtag_readArea_ctrl_shift) begin + jtag_readArea_full_shifter <= ({jtag_readArea_ctrl_tdi,jtag_readArea_full_shifter} >>> 1); + end + end + end + + +endmodule + +module VexRiscv_b62b14ffe6bb44e5a817b8d08e286c6b ( + output dBus_cmd_valid, + input dBus_cmd_ready, + output dBus_cmd_payload_wr, + output dBus_cmd_payload_uncached, + output [31:0] dBus_cmd_payload_address, + output [31:0] dBus_cmd_payload_data, + output [3:0] dBus_cmd_payload_mask, + output [2:0] dBus_cmd_payload_size, + output dBus_cmd_payload_last, + input dBus_rsp_valid, + input dBus_rsp_payload_last, + input [31:0] dBus_rsp_payload_data, + input dBus_rsp_payload_error, + input timerInterrupt, + input externalInterrupt, + input softwareInterrupt, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output iBus_cmd_valid, + input iBus_cmd_ready, + output reg [31:0] iBus_cmd_payload_address, + output [2:0] iBus_cmd_payload_size, + input iBus_rsp_valid, + input [31:0] iBus_rsp_payload_data, + input iBus_rsp_payload_error, + input io_systemClk, + input systemCd_logic_outputReset, + input debugCd_logic_outputReset +); + localparam ShiftCtrlEnum_DISABLE_1 = 2'd0; + localparam ShiftCtrlEnum_SLL_1 = 2'd1; + localparam ShiftCtrlEnum_SRL_1 = 2'd2; + localparam ShiftCtrlEnum_SRA_1 = 2'd3; + localparam BranchCtrlEnum_INC = 2'd0; + localparam BranchCtrlEnum_B = 2'd1; + localparam BranchCtrlEnum_JAL = 2'd2; + localparam BranchCtrlEnum_JALR = 2'd3; + localparam EnvCtrlEnum_NONE = 2'd0; + localparam EnvCtrlEnum_XRET = 2'd1; + localparam EnvCtrlEnum_ECALL = 2'd2; + localparam EnvCtrlEnum_EBREAK = 2'd3; + localparam AluBitwiseCtrlEnum_XOR_1 = 2'd0; + localparam AluBitwiseCtrlEnum_OR_1 = 2'd1; + localparam AluBitwiseCtrlEnum_AND_1 = 2'd2; + localparam AluCtrlEnum_ADD_SUB = 2'd0; + localparam AluCtrlEnum_SLT_SLTU = 2'd1; + localparam AluCtrlEnum_BITWISE = 2'd2; + localparam Src2CtrlEnum_RS = 2'd0; + localparam Src2CtrlEnum_IMI = 2'd1; + localparam Src2CtrlEnum_IMS = 2'd2; + localparam Src2CtrlEnum_PC = 2'd3; + localparam Src1CtrlEnum_RS = 2'd0; + localparam Src1CtrlEnum_IMU = 2'd1; + localparam Src1CtrlEnum_PC_INCREMENT = 2'd2; + localparam Src1CtrlEnum_URS1 = 2'd3; + + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + wire dataCache_1_io_cpu_execute_isValid; + wire [31:0] dataCache_1_io_cpu_execute_address; + wire dataCache_1_io_cpu_memory_isValid; + reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; + reg dataCache_1_io_cpu_writeBack_isValid; + wire dataCache_1_io_cpu_writeBack_isUser; + wire [31:0] dataCache_1_io_cpu_writeBack_storeData; + wire [31:0] dataCache_1_io_cpu_writeBack_address; + wire dataCache_1_io_cpu_writeBack_fence_SW; + wire dataCache_1_io_cpu_writeBack_fence_SR; + wire dataCache_1_io_cpu_writeBack_fence_SO; + wire dataCache_1_io_cpu_writeBack_fence_SI; + wire dataCache_1_io_cpu_writeBack_fence_PW; + wire dataCache_1_io_cpu_writeBack_fence_PR; + wire dataCache_1_io_cpu_writeBack_fence_PO; + wire dataCache_1_io_cpu_writeBack_fence_PI; + wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; + wire dataCache_1_io_cpu_flush_valid; + wire dataCache_1_io_cpu_flush_payload_singleLine; + wire [5:0] dataCache_1_io_cpu_flush_payload_lineId; + wire dataCache_1_io_mem_cmd_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_writeBack_exclusiveOk; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_size; + wire dataCache_1_io_mem_cmd_payload_last; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [13:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [7:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [1:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [2:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_4; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [25:0] _zz_io_cpu_flush_payload_lineId; + wire [25:0] _zz_io_cpu_flush_payload_lineId_1; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; + wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_1; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_2; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_3; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_4; + wire _zz__zz_decode_BRANCH_CTRL_2_5; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_6; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_7; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_8; + wire _zz__zz_decode_BRANCH_CTRL_2_9; + wire _zz__zz_decode_BRANCH_CTRL_2_10; + wire [26:0] _zz__zz_decode_BRANCH_CTRL_2_11; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_12; + wire _zz__zz_decode_BRANCH_CTRL_2_13; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_14; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_15; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_16; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_17; + wire [22:0] _zz__zz_decode_BRANCH_CTRL_2_18; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_19; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_20; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_21; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_22; + wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_23; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_24; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_25; + wire _zz__zz_decode_BRANCH_CTRL_2_26; + wire _zz__zz_decode_BRANCH_CTRL_2_27; + wire _zz__zz_decode_BRANCH_CTRL_2_28; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_29; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_30; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_31; + wire _zz__zz_decode_BRANCH_CTRL_2_32; + wire [18:0] _zz__zz_decode_BRANCH_CTRL_2_33; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_34; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_35; + wire _zz__zz_decode_BRANCH_CTRL_2_36; + wire _zz__zz_decode_BRANCH_CTRL_2_37; + wire _zz__zz_decode_BRANCH_CTRL_2_38; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_39; + wire _zz__zz_decode_BRANCH_CTRL_2_40; + wire [15:0] _zz__zz_decode_BRANCH_CTRL_2_41; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_42; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_43; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_44; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_45; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_46; + wire _zz__zz_decode_BRANCH_CTRL_2_47; + wire _zz__zz_decode_BRANCH_CTRL_2_48; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_49; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_50; + wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_51; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_52; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_53; + wire _zz__zz_decode_BRANCH_CTRL_2_54; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_55; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_56; + wire _zz__zz_decode_BRANCH_CTRL_2_57; + wire [12:0] _zz__zz_decode_BRANCH_CTRL_2_58; + wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_59; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_60; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_61; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_62; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_63; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_64; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_65; + wire _zz__zz_decode_BRANCH_CTRL_2_66; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_67; + wire _zz__zz_decode_BRANCH_CTRL_2_68; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_69; + wire _zz__zz_decode_BRANCH_CTRL_2_70; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_71; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_72; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_73; + wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_74; + wire _zz__zz_decode_BRANCH_CTRL_2_75; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_76; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_77; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_78; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_79; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_80; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_81; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_82; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_83; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_84; + wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_85; + wire _zz__zz_decode_BRANCH_CTRL_2_86; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_87; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_88; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_89; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_90; + wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_91; + wire _zz__zz_decode_BRANCH_CTRL_2_92; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_93; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_94; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_95; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_96; + wire [9:0] _zz__zz_decode_BRANCH_CTRL_2_97; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_98; + wire _zz__zz_decode_BRANCH_CTRL_2_99; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_100; + wire _zz__zz_decode_BRANCH_CTRL_2_101; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_102; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_103; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_104; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_105; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_106; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_107; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_108; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_109; + wire [6:0] _zz__zz_decode_BRANCH_CTRL_2_110; + wire _zz__zz_decode_BRANCH_CTRL_2_111; + wire _zz__zz_decode_BRANCH_CTRL_2_112; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_113; + wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_114; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_115; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_116; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_117; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_118; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_119; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_120; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_121; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_122; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_123; + wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_124; + wire _zz__zz_decode_BRANCH_CTRL_2_125; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_126; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_127; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_128; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_129; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_130; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_131; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_132; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_133; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_134; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_135; + wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_136; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_137; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_138; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_139; + wire _zz__zz_decode_BRANCH_CTRL_2_140; + wire _zz__zz_decode_BRANCH_CTRL_2_141; + wire _zz__zz_decode_BRANCH_CTRL_2_142; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_143; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_144; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_decode_SRC1_1; + wire [4:0] _zz__zz_decode_SRC1_1_1; + wire [11:0] _zz__zz_decode_SRC2_4; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_decode_RS2_2; + wire [31:0] _zz__zz_decode_RS2_2_1; + wire [5:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext; + wire [0:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_2; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_3; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_4; + wire [0:0] _zz_memory_MulDivIterativePlugin_div_result_5; + wire [32:0] _zz_memory_MulDivIterativePlugin_rs1_2; + wire [0:0] _zz_memory_MulDivIterativePlugin_rs1_3; + wire [31:0] _zz_memory_MulDivIterativePlugin_rs2_1; + wire [0:0] _zz_memory_MulDivIterativePlugin_rs2_2; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire _zz_when; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire [51:0] memory_MUL_LOW; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [31:0] execute_MEMORY_VIRTUAL_ADDRESS; + wire [31:0] memory_MEMORY_STORE_DATA_RF; + wire [31:0] execute_MEMORY_STORE_DATA_RF; + wire decode_DO_EBREAK; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire [31:0] decode_SRC2; + wire [31:0] decode_SRC1; + wire decode_SRC2_FORCE_ZERO; + wire [1:0] decode_BRANCH_CTRL; + wire [1:0] _zz_decode_BRANCH_CTRL; + wire [1:0] _zz_decode_to_execute_BRANCH_CTRL; + wire [1:0] _zz_decode_to_execute_BRANCH_CTRL_1; + wire [1:0] _zz_memory_to_writeBack_ENV_CTRL; + wire [1:0] _zz_memory_to_writeBack_ENV_CTRL_1; + wire [1:0] _zz_execute_to_memory_ENV_CTRL; + wire [1:0] _zz_execute_to_memory_ENV_CTRL_1; + wire [1:0] decode_ENV_CTRL; + wire [1:0] _zz_decode_ENV_CTRL; + wire [1:0] _zz_decode_to_execute_ENV_CTRL; + wire [1:0] _zz_decode_to_execute_ENV_CTRL_1; + wire decode_IS_CSR; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire decode_IS_MUL; + wire [1:0] _zz_execute_to_memory_SHIFT_CTRL; + wire [1:0] _zz_execute_to_memory_SHIFT_CTRL_1; + wire [1:0] decode_SHIFT_CTRL; + wire [1:0] _zz_decode_SHIFT_CTRL; + wire [1:0] _zz_decode_to_execute_SHIFT_CTRL; + wire [1:0] _zz_decode_to_execute_SHIFT_CTRL_1; + wire [1:0] decode_ALU_BITWISE_CTRL; + wire [1:0] _zz_decode_ALU_BITWISE_CTRL; + wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire [1:0] decode_ALU_CTRL; + wire [1:0] _zz_decode_ALU_CTRL; + wire [1:0] _zz_decode_to_execute_ALU_CTRL; + wire [1:0] _zz_decode_to_execute_ALU_CTRL_1; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + wire [1:0] execute_BRANCH_CTRL; + wire [1:0] _zz_execute_BRANCH_CTRL; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire [1:0] memory_ENV_CTRL; + wire [1:0] _zz_memory_ENV_CTRL; + wire [1:0] execute_ENV_CTRL; + wire [1:0] _zz_execute_ENV_CTRL; + wire [1:0] writeBack_ENV_CTRL; + wire [1:0] _zz_writeBack_ENV_CTRL; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + wire execute_IS_MUL; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_decode_RS2; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_decode_RS2_1; + wire [1:0] memory_SHIFT_CTRL; + wire [1:0] _zz_memory_SHIFT_CTRL; + wire [1:0] execute_SHIFT_CTRL; + wire [1:0] _zz_execute_SHIFT_CTRL; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_decode_SRC2; + wire [31:0] _zz_decode_SRC2_1; + wire [1:0] decode_SRC2_CTRL; + wire [1:0] _zz_decode_SRC2_CTRL; + wire [31:0] _zz_decode_SRC1; + wire [1:0] decode_SRC1_CTRL; + wire [1:0] _zz_decode_SRC1_CTRL; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire [1:0] execute_ALU_CTRL; + wire [1:0] _zz_execute_ALU_CTRL; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire [1:0] execute_ALU_BITWISE_CTRL; + wire [1:0] _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire [1:0] _zz_decode_BRANCH_CTRL_1; + wire [1:0] _zz_decode_ENV_CTRL_1; + wire [1:0] _zz_decode_SHIFT_CTRL_1; + wire [1:0] _zz_decode_ALU_BITWISE_CTRL_1; + wire [1:0] _zz_decode_SRC2_CTRL_1; + wire [1:0] _zz_decode_ALU_CTRL_1; + wire [1:0] _zz_decode_SRC1_CTRL_1; + reg [31:0] _zz_decode_RS2_2; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_MEMORY_STORE_DATA_RF; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire memory_MEMORY_ENABLE; + wire [31:0] memory_MEMORY_VIRTUAL_ADDRESS; + wire execute_MEMORY_FORCE_CONSTISTENCY; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_MANAGMENT; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; + wire [31:0] decode_PC; + wire [31:0] decode_INSTRUCTION; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + reg decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + wire IBusCachedPlugin_forceNoDecodeCond; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_isPaging; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_isPaging; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + reg _zz_when_DBusCachedPlugin_l393; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; + wire CsrPlugin_inWfi /* verilator public */ ; + reg CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + reg CsrPlugin_allowEbreakException; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg BranchPlugin_inDebugNoFetchFlag; + reg IBusCachedPlugin_injectionPort_valid; + reg IBusCachedPlugin_injectionPort_ready; + wire [31:0] IBusCachedPlugin_injectionPort_payload; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l134; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l134_1; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l161; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l243; + wire IBusCachedPlugin_injector_decodeInput_valid; + wire IBusCachedPlugin_injector_decodeInput_ready; + wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_pc; + wire IBusCachedPlugin_injector_decodeInput_payload_rsp_error; + wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + wire IBusCachedPlugin_injector_decodeInput_payload_isRvc; + reg _zz_IBusCachedPlugin_injector_decodeInput_valid; + reg [31:0] _zz_IBusCachedPlugin_injector_decodeInput_payload_pc; + reg _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error; + reg [31:0] _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + reg _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc; + wire when_Fetcher_l323; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l332; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l332_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l332_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l332_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire when_Fetcher_l332_4; + reg IBusCachedPlugin_injector_nextPcCalc_valids_5; + wire when_Fetcher_l332_5; + reg [31:0] IBusCachedPlugin_injector_formal_rawInDecode; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + reg dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_rValid; + reg dataCache_1_io_mem_cmd_rData_wr; + reg dataCache_1_io_mem_cmd_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_rData_size; + reg dataCache_1_io_mem_cmd_rData_last; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire when_Stream_l368; + reg dBus_rsp_regNext_valid; + reg dBus_rsp_regNext_payload_last; + reg [31:0] dBus_rsp_regNext_payload_data; + reg dBus_rsp_regNext_payload_error; + reg [31:0] DBusCachedPlugin_rspCounter; + wire when_DBusCachedPlugin_l308; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; + wire dataCache_1_io_cpu_flush_isStall; + wire when_DBusCachedPlugin_l350; + wire when_DBusCachedPlugin_l366; + wire when_DBusCachedPlugin_l393; + wire when_DBusCachedPlugin_l446; + wire when_DBusCachedPlugin_l466; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire [31:0] writeBack_DBusCachedPlugin_rspRf; + wire [1:0] switch_Misc_l210; + wire _zz_writeBack_DBusCachedPlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; + wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire when_DBusCachedPlugin_l492; + wire [32:0] _zz_decode_BRANCH_CTRL_2; + wire _zz_decode_BRANCH_CTRL_3; + wire _zz_decode_BRANCH_CTRL_4; + wire _zz_decode_BRANCH_CTRL_5; + wire _zz_decode_BRANCH_CTRL_6; + wire _zz_decode_BRANCH_CTRL_7; + wire _zz_decode_BRANCH_CTRL_8; + wire [1:0] _zz_decode_SRC1_CTRL_2; + wire [1:0] _zz_decode_ALU_CTRL_2; + wire [1:0] _zz_decode_SRC2_CTRL_2; + wire [1:0] _zz_decode_ALU_BITWISE_CTRL_2; + wire [1:0] _zz_decode_SHIFT_CTRL_2; + wire [1:0] _zz_decode_ENV_CTRL_2; + wire [1:0] _zz_decode_BRANCH_CTRL_9; + wire when_RegFilePlugin_l63; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_2; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_decode_SRC1_1; + wire _zz_decode_SRC2_2; + reg [19:0] _zz_decode_SRC2_3; + wire _zz_decode_SRC2_4; + reg [19:0] _zz_decode_SRC2_5; + reg [31:0] _zz_decode_SRC2_6; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_decode_RS2_3; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + reg [0:0] execute_MulPlugin_delayLogic_counter; + wire when_MulPlugin_l65; + wire when_MulPlugin_l70; + wire [1:0] switch_MulPlugin_l87; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + reg [31:0] execute_MulPlugin_withOuputBuffer_mul_ll; + reg [33:0] execute_MulPlugin_withOuputBuffer_mul_lh; + reg [33:0] execute_MulPlugin_withOuputBuffer_mul_hl; + reg [33:0] execute_MulPlugin_withOuputBuffer_mul_hh; + wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; + reg [32:0] memory_MulDivIterativePlugin_rs1; + reg [31:0] memory_MulDivIterativePlugin_rs2; + reg [64:0] memory_MulDivIterativePlugin_accumulator; + wire memory_MulDivIterativePlugin_frontendOk; + reg memory_MulDivIterativePlugin_div_needRevert; + reg memory_MulDivIterativePlugin_div_counter_willIncrement; + reg memory_MulDivIterativePlugin_div_counter_willClear; + reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext; + reg [5:0] memory_MulDivIterativePlugin_div_counter_value; + wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; + wire memory_MulDivIterativePlugin_div_counter_willOverflow; + reg memory_MulDivIterativePlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; + reg [31:0] memory_MulDivIterativePlugin_div_result; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_MulDivIterativePlugin_rs2; + wire _zz_memory_MulDivIterativePlugin_rs1; + reg [32:0] _zz_memory_MulDivIterativePlugin_rs1_1; + reg [1:0] CsrPlugin_misa_base; + reg [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle; + reg [63:0] CsrPlugin_minstret; + wire _zz_when_CsrPlugin_l965; + wire _zz_when_CsrPlugin_l965_1; + wire _zz_when_CsrPlugin_l965_2; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire when_CsrPlugin_l922; + wire when_CsrPlugin_l922_1; + wire when_CsrPlugin_l922_2; + wire when_CsrPlugin_l922_3; + wire when_CsrPlugin_l935; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l959; + wire when_CsrPlugin_l965; + wire when_CsrPlugin_l965_1; + wire when_CsrPlugin_l965_2; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l993; + wire when_CsrPlugin_l993_1; + wire when_CsrPlugin_l993_2; + wire when_CsrPlugin_l998; + reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l1004; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1032; + wire when_CsrPlugin_l1077; + wire [1:0] switch_CsrPlugin_l1081; + reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1129; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire when_CsrPlugin_l1142; + wire when_CsrPlugin_l1149; + wire when_CsrPlugin_l1150; + wire when_CsrPlugin_l1157; + wire when_CsrPlugin_l1167; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + wire switch_Misc_l210_1; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1189; + wire when_CsrPlugin_l1193; + wire [11:0] execute_CsrPlugin_csrAddress; + wire execute_BranchPlugin_eq; + wire [2:0] switch_Misc_l210_2; + reg _zz_execute_BRANCH_DO; + reg _zz_execute_BRANCH_DO_1; + wire [31:0] execute_BranchPlugin_branch_src1; + wire _zz_execute_BranchPlugin_branch_src2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; + reg [31:0] _zz_execute_BranchPlugin_branch_src2_6; + wire [31:0] execute_BranchPlugin_branch_src2; + wire [31:0] execute_BranchPlugin_branchAdder; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + wire when_DebugPlugin_l225; + reg DebugPlugin_haltedByBreak; + reg DebugPlugin_debugUsed /* verilator public */ ; + reg DebugPlugin_disableEbreak; + wire DebugPlugin_allowEBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_when_DebugPlugin_l244; + wire when_DebugPlugin_l244; + wire [5:0] switch_DebugPlugin_l267; + wire when_DebugPlugin_l271; + wire when_DebugPlugin_l271_1; + wire when_DebugPlugin_l272; + wire when_DebugPlugin_l272_1; + wire when_DebugPlugin_l273; + wire when_DebugPlugin_l274; + wire when_DebugPlugin_l275; + wire when_DebugPlugin_l275_1; + wire when_DebugPlugin_l295; + wire when_DebugPlugin_l298; + wire when_DebugPlugin_l311; + reg DebugPlugin_resetIt_regNext; + wire when_DebugPlugin_l331; + wire when_Pipeline_l124; + reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; + reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; + reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; + reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; + reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; + reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + wire when_Pipeline_l124_10; + reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_11; + reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_12; + reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_13; + reg memory_to_writeBack_MEMORY_ENABLE; + wire when_Pipeline_l124_14; + reg [1:0] decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_15; + reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_16; + reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_17; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_19; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_20; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_21; + reg decode_to_execute_MEMORY_WR; + wire when_Pipeline_l124_22; + reg execute_to_memory_MEMORY_WR; + wire when_Pipeline_l124_23; + reg memory_to_writeBack_MEMORY_WR; + wire when_Pipeline_l124_24; + reg decode_to_execute_MEMORY_MANAGMENT; + wire when_Pipeline_l124_25; + reg decode_to_execute_SRC_LESS_UNSIGNED; + wire when_Pipeline_l124_26; + reg [1:0] decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_27; + reg [1:0] decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_28; + reg [1:0] execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_29; + reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_30; + reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_31; + reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_32; + reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_33; + reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_34; + reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_35; + reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_36; + reg decode_to_execute_IS_CSR; + wire when_Pipeline_l124_37; + reg [1:0] decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_38; + reg [1:0] execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_39; + reg [1:0] memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_40; + reg [1:0] decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_41; + reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_42; + reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_43; + reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_44; + reg [31:0] decode_to_execute_SRC1; + wire when_Pipeline_l124_45; + reg [31:0] decode_to_execute_SRC2; + wire when_Pipeline_l124_46; + reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_47; + reg decode_to_execute_CSR_READ_OPCODE; + wire when_Pipeline_l124_48; + reg decode_to_execute_DO_EBREAK; + wire when_Pipeline_l124_49; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_50; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_51; + (* keep , syn_keep *) reg [31:0] execute_to_memory_MEMORY_VIRTUAL_ADDRESS /* synthesis syn_keep = 1 */ ; + wire when_Pipeline_l124_52; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_53; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_54; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + wire when_Pipeline_l124_55; + reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_56; + reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_57; + reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_58; + reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_59; + reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_60; + reg execute_to_memory_BRANCH_DO; + wire when_Pipeline_l124_61; + reg [31:0] execute_to_memory_BRANCH_CALC; + wire when_Pipeline_l124_62; + reg [51:0] memory_to_writeBack_MUL_LOW; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + reg [2:0] switch_Fetcher_l365; + wire when_Fetcher_l381; + wire when_Fetcher_l401; + wire when_CsrPlugin_l1277; + reg execute_CsrPlugin_csr_3860; + wire when_CsrPlugin_l1277_1; + reg execute_CsrPlugin_csr_769; + wire when_CsrPlugin_l1277_2; + reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1277_3; + reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1277_4; + reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1277_5; + reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1277_6; + reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1277_7; + reg execute_CsrPlugin_csr_832; + wire when_CsrPlugin_l1277_8; + reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1277_9; + reg execute_CsrPlugin_csr_835; + wire [1:0] switch_CsrPlugin_l723; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + wire when_CsrPlugin_l1310; + wire when_CsrPlugin_l1315; + `ifndef SYNTHESIS + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [47:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [47:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [47:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [47:0] _zz_execute_to_memory_ENV_CTRL_1_string; + reg [47:0] decode_ENV_CTRL_string; + reg [47:0] _zz_decode_ENV_CTRL_string; + reg [47:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [47:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; + reg [47:0] memory_ENV_CTRL_string; + reg [47:0] _zz_memory_ENV_CTRL_string; + reg [47:0] execute_ENV_CTRL_string; + reg [47:0] _zz_execute_ENV_CTRL_string; + reg [47:0] writeBack_ENV_CTRL_string; + reg [47:0] _zz_writeBack_ENV_CTRL_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_execute_ALU_CTRL_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [47:0] _zz_decode_ENV_CTRL_1_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [47:0] _zz_decode_ENV_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_9_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [47:0] decode_to_execute_ENV_CTRL_string; + reg [47:0] execute_to_memory_ENV_CTRL_string; + reg [47:0] memory_to_writeBack_ENV_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + `endif + + reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == ShiftCtrlEnum_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 3'b001); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz_io_cpu_flush_payload_lineId = _zz_io_cpu_flush_payload_lineId_1; + assign _zz_io_cpu_flush_payload_lineId_1 = (execute_RS1 >>> 6); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_decode_SRC1_1 = 3'b100; + assign _zz__zz_decode_SRC1_1_1 = decode_INSTRUCTION[19 : 15]; + assign _zz__zz_decode_SRC2_4 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1 = memory_MulDivIterativePlugin_div_counter_willIncrement; + assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext = {5'd0, _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1}; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_MulDivIterativePlugin_rs2}; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator = {_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_MulDivIterativePlugin_div_result_1 = _zz_memory_MulDivIterativePlugin_div_result_2; + assign _zz_memory_MulDivIterativePlugin_div_result_2 = _zz_memory_MulDivIterativePlugin_div_result_3; + assign _zz_memory_MulDivIterativePlugin_div_result_3 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_memory_MulDivIterativePlugin_div_result) : _zz_memory_MulDivIterativePlugin_div_result)} + _zz_memory_MulDivIterativePlugin_div_result_4); + assign _zz_memory_MulDivIterativePlugin_div_result_5 = memory_MulDivIterativePlugin_div_needRevert; + assign _zz_memory_MulDivIterativePlugin_div_result_4 = {32'd0, _zz_memory_MulDivIterativePlugin_div_result_5}; + assign _zz_memory_MulDivIterativePlugin_rs1_3 = _zz_memory_MulDivIterativePlugin_rs1; + assign _zz_memory_MulDivIterativePlugin_rs1_2 = {32'd0, _zz_memory_MulDivIterativePlugin_rs1_3}; + assign _zz_memory_MulDivIterativePlugin_rs2_2 = _zz_memory_MulDivIterativePlugin_rs2; + assign _zz_memory_MulDivIterativePlugin_rs2_1 = {31'd0, _zz_memory_MulDivIterativePlugin_rs2_2}; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz__zz_execute_BranchPlugin_branch_src2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_3,_zz_IBusCachedPlugin_jump_pcLoad_payload_2}; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00001013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hfc00307f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00005033; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; + assign _zz__zz_decode_BRANCH_CTRL_2 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz__zz_decode_BRANCH_CTRL_2_1 = 32'h00000004; + assign _zz__zz_decode_BRANCH_CTRL_2_2 = (decode_INSTRUCTION & 32'h00000058); + assign _zz__zz_decode_BRANCH_CTRL_2_3 = 32'h00000040; + assign _zz__zz_decode_BRANCH_CTRL_2_4 = ((decode_INSTRUCTION & 32'h10003050) == 32'h00000050); + assign _zz__zz_decode_BRANCH_CTRL_2_5 = (|{_zz_decode_BRANCH_CTRL_8,(_zz__zz_decode_BRANCH_CTRL_2_6 == _zz__zz_decode_BRANCH_CTRL_2_7)}); + assign _zz__zz_decode_BRANCH_CTRL_2_8 = (|{_zz__zz_decode_BRANCH_CTRL_2_9,_zz__zz_decode_BRANCH_CTRL_2_10}); + assign _zz__zz_decode_BRANCH_CTRL_2_11 = {(|_zz_decode_BRANCH_CTRL_7),{(|_zz__zz_decode_BRANCH_CTRL_2_12),{_zz__zz_decode_BRANCH_CTRL_2_13,{_zz__zz_decode_BRANCH_CTRL_2_15,_zz__zz_decode_BRANCH_CTRL_2_18}}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_6 = (decode_INSTRUCTION & 32'h10403050); + assign _zz__zz_decode_BRANCH_CTRL_2_7 = 32'h10000050; + assign _zz__zz_decode_BRANCH_CTRL_2_9 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz__zz_decode_BRANCH_CTRL_2_10 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz__zz_decode_BRANCH_CTRL_2_12 = _zz_decode_BRANCH_CTRL_7; + assign _zz__zz_decode_BRANCH_CTRL_2_13 = (|((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_14) == 32'h02004020)); + assign _zz__zz_decode_BRANCH_CTRL_2_15 = (|(_zz__zz_decode_BRANCH_CTRL_2_16 == _zz__zz_decode_BRANCH_CTRL_2_17)); + assign _zz__zz_decode_BRANCH_CTRL_2_18 = {(|{_zz__zz_decode_BRANCH_CTRL_2_19,_zz__zz_decode_BRANCH_CTRL_2_21}),{(|_zz__zz_decode_BRANCH_CTRL_2_23),{_zz__zz_decode_BRANCH_CTRL_2_28,{_zz__zz_decode_BRANCH_CTRL_2_31,_zz__zz_decode_BRANCH_CTRL_2_33}}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_14 = 32'h02004064; + assign _zz__zz_decode_BRANCH_CTRL_2_16 = (decode_INSTRUCTION & 32'h02004074); + assign _zz__zz_decode_BRANCH_CTRL_2_17 = 32'h02000030; + assign _zz__zz_decode_BRANCH_CTRL_2_19 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_20) == 32'h00005010); + assign _zz__zz_decode_BRANCH_CTRL_2_21 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_22) == 32'h00005020); + assign _zz__zz_decode_BRANCH_CTRL_2_23 = {(_zz__zz_decode_BRANCH_CTRL_2_24 == _zz__zz_decode_BRANCH_CTRL_2_25),{_zz__zz_decode_BRANCH_CTRL_2_26,_zz__zz_decode_BRANCH_CTRL_2_27}}; + assign _zz__zz_decode_BRANCH_CTRL_2_28 = (|(_zz__zz_decode_BRANCH_CTRL_2_29 == _zz__zz_decode_BRANCH_CTRL_2_30)); + assign _zz__zz_decode_BRANCH_CTRL_2_31 = (|_zz__zz_decode_BRANCH_CTRL_2_32); + assign _zz__zz_decode_BRANCH_CTRL_2_33 = {(|_zz__zz_decode_BRANCH_CTRL_2_34),{_zz__zz_decode_BRANCH_CTRL_2_36,{_zz__zz_decode_BRANCH_CTRL_2_39,_zz__zz_decode_BRANCH_CTRL_2_41}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_20 = 32'h00007034; + assign _zz__zz_decode_BRANCH_CTRL_2_22 = 32'h02007064; + assign _zz__zz_decode_BRANCH_CTRL_2_24 = (decode_INSTRUCTION & 32'h40003054); + assign _zz__zz_decode_BRANCH_CTRL_2_25 = 32'h40001010; + assign _zz__zz_decode_BRANCH_CTRL_2_26 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); + assign _zz__zz_decode_BRANCH_CTRL_2_27 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); + assign _zz__zz_decode_BRANCH_CTRL_2_29 = (decode_INSTRUCTION & 32'h00000064); + assign _zz__zz_decode_BRANCH_CTRL_2_30 = 32'h00000024; + assign _zz__zz_decode_BRANCH_CTRL_2_32 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz__zz_decode_BRANCH_CTRL_2_34 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_35) == 32'h00002000); + assign _zz__zz_decode_BRANCH_CTRL_2_36 = (|{_zz__zz_decode_BRANCH_CTRL_2_37,_zz__zz_decode_BRANCH_CTRL_2_38}); + assign _zz__zz_decode_BRANCH_CTRL_2_39 = (|_zz__zz_decode_BRANCH_CTRL_2_40); + assign _zz__zz_decode_BRANCH_CTRL_2_41 = {(|_zz__zz_decode_BRANCH_CTRL_2_42),{_zz__zz_decode_BRANCH_CTRL_2_47,{_zz__zz_decode_BRANCH_CTRL_2_56,_zz__zz_decode_BRANCH_CTRL_2_58}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_35 = 32'h00003000; + assign _zz__zz_decode_BRANCH_CTRL_2_37 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz__zz_decode_BRANCH_CTRL_2_38 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz__zz_decode_BRANCH_CTRL_2_40 = ((decode_INSTRUCTION & 32'h00004048) == 32'h00004008); + assign _zz__zz_decode_BRANCH_CTRL_2_42 = {(_zz__zz_decode_BRANCH_CTRL_2_43 == _zz__zz_decode_BRANCH_CTRL_2_44),(_zz__zz_decode_BRANCH_CTRL_2_45 == _zz__zz_decode_BRANCH_CTRL_2_46)}; + assign _zz__zz_decode_BRANCH_CTRL_2_47 = (|{_zz__zz_decode_BRANCH_CTRL_2_48,{_zz__zz_decode_BRANCH_CTRL_2_49,_zz__zz_decode_BRANCH_CTRL_2_51}}); + assign _zz__zz_decode_BRANCH_CTRL_2_56 = (|_zz__zz_decode_BRANCH_CTRL_2_57); + assign _zz__zz_decode_BRANCH_CTRL_2_58 = {(|_zz__zz_decode_BRANCH_CTRL_2_59),{_zz__zz_decode_BRANCH_CTRL_2_70,{_zz__zz_decode_BRANCH_CTRL_2_83,_zz__zz_decode_BRANCH_CTRL_2_97}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_43 = (decode_INSTRUCTION & 32'h00000034); + assign _zz__zz_decode_BRANCH_CTRL_2_44 = 32'h00000020; + assign _zz__zz_decode_BRANCH_CTRL_2_45 = (decode_INSTRUCTION & 32'h00000064); + assign _zz__zz_decode_BRANCH_CTRL_2_46 = 32'h00000020; + assign _zz__zz_decode_BRANCH_CTRL_2_48 = ((decode_INSTRUCTION & 32'h00002040) == 32'h00002040); + assign _zz__zz_decode_BRANCH_CTRL_2_49 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_50) == 32'h00001040); + assign _zz__zz_decode_BRANCH_CTRL_2_51 = {(_zz__zz_decode_BRANCH_CTRL_2_52 == _zz__zz_decode_BRANCH_CTRL_2_53),{_zz__zz_decode_BRANCH_CTRL_2_54,_zz_decode_BRANCH_CTRL_4}}; + assign _zz__zz_decode_BRANCH_CTRL_2_57 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); + assign _zz__zz_decode_BRANCH_CTRL_2_59 = {(_zz__zz_decode_BRANCH_CTRL_2_60 == _zz__zz_decode_BRANCH_CTRL_2_61),{_zz_decode_BRANCH_CTRL_5,{_zz__zz_decode_BRANCH_CTRL_2_62,_zz__zz_decode_BRANCH_CTRL_2_65}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_70 = (|{_zz_decode_BRANCH_CTRL_5,{_zz__zz_decode_BRANCH_CTRL_2_71,_zz__zz_decode_BRANCH_CTRL_2_74}}); + assign _zz__zz_decode_BRANCH_CTRL_2_83 = (|{_zz__zz_decode_BRANCH_CTRL_2_84,_zz__zz_decode_BRANCH_CTRL_2_85}); + assign _zz__zz_decode_BRANCH_CTRL_2_97 = {(|_zz__zz_decode_BRANCH_CTRL_2_98),{_zz__zz_decode_BRANCH_CTRL_2_101,{_zz__zz_decode_BRANCH_CTRL_2_106,_zz__zz_decode_BRANCH_CTRL_2_110}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_50 = 32'h00001040; + assign _zz__zz_decode_BRANCH_CTRL_2_52 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_BRANCH_CTRL_2_53 = 32'h00000040; + assign _zz__zz_decode_BRANCH_CTRL_2_54 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_55) == 32'h00000040); + assign _zz__zz_decode_BRANCH_CTRL_2_60 = (decode_INSTRUCTION & 32'h00000040); + assign _zz__zz_decode_BRANCH_CTRL_2_61 = 32'h00000040; + assign _zz__zz_decode_BRANCH_CTRL_2_62 = (_zz__zz_decode_BRANCH_CTRL_2_63 == _zz__zz_decode_BRANCH_CTRL_2_64); + assign _zz__zz_decode_BRANCH_CTRL_2_65 = {_zz__zz_decode_BRANCH_CTRL_2_66,_zz__zz_decode_BRANCH_CTRL_2_68}; + assign _zz__zz_decode_BRANCH_CTRL_2_71 = (_zz__zz_decode_BRANCH_CTRL_2_72 == _zz__zz_decode_BRANCH_CTRL_2_73); + assign _zz__zz_decode_BRANCH_CTRL_2_74 = {_zz__zz_decode_BRANCH_CTRL_2_75,{_zz__zz_decode_BRANCH_CTRL_2_77,_zz__zz_decode_BRANCH_CTRL_2_80}}; + assign _zz__zz_decode_BRANCH_CTRL_2_84 = _zz_decode_BRANCH_CTRL_6; + assign _zz__zz_decode_BRANCH_CTRL_2_85 = {_zz__zz_decode_BRANCH_CTRL_2_86,{_zz__zz_decode_BRANCH_CTRL_2_88,_zz__zz_decode_BRANCH_CTRL_2_91}}; + assign _zz__zz_decode_BRANCH_CTRL_2_98 = {_zz_decode_BRANCH_CTRL_5,_zz__zz_decode_BRANCH_CTRL_2_99}; + assign _zz__zz_decode_BRANCH_CTRL_2_101 = (|{_zz__zz_decode_BRANCH_CTRL_2_102,_zz__zz_decode_BRANCH_CTRL_2_103}); + assign _zz__zz_decode_BRANCH_CTRL_2_106 = (|_zz__zz_decode_BRANCH_CTRL_2_107); + assign _zz__zz_decode_BRANCH_CTRL_2_110 = {_zz__zz_decode_BRANCH_CTRL_2_111,{_zz__zz_decode_BRANCH_CTRL_2_113,_zz__zz_decode_BRANCH_CTRL_2_124}}; + assign _zz__zz_decode_BRANCH_CTRL_2_55 = 32'h00400040; + assign _zz__zz_decode_BRANCH_CTRL_2_63 = (decode_INSTRUCTION & 32'h00004020); + assign _zz__zz_decode_BRANCH_CTRL_2_64 = 32'h00004020; + assign _zz__zz_decode_BRANCH_CTRL_2_66 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_67) == 32'h00000010); + assign _zz__zz_decode_BRANCH_CTRL_2_68 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_69) == 32'h00000020); + assign _zz__zz_decode_BRANCH_CTRL_2_72 = (decode_INSTRUCTION & 32'h00002030); + assign _zz__zz_decode_BRANCH_CTRL_2_73 = 32'h00002010; + assign _zz__zz_decode_BRANCH_CTRL_2_75 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_76) == 32'h00000010); + assign _zz__zz_decode_BRANCH_CTRL_2_77 = (_zz__zz_decode_BRANCH_CTRL_2_78 == _zz__zz_decode_BRANCH_CTRL_2_79); + assign _zz__zz_decode_BRANCH_CTRL_2_80 = (_zz__zz_decode_BRANCH_CTRL_2_81 == _zz__zz_decode_BRANCH_CTRL_2_82); + assign _zz__zz_decode_BRANCH_CTRL_2_86 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_87) == 32'h00001010); + assign _zz__zz_decode_BRANCH_CTRL_2_88 = (_zz__zz_decode_BRANCH_CTRL_2_89 == _zz__zz_decode_BRANCH_CTRL_2_90); + assign _zz__zz_decode_BRANCH_CTRL_2_91 = {_zz__zz_decode_BRANCH_CTRL_2_92,{_zz__zz_decode_BRANCH_CTRL_2_93,_zz__zz_decode_BRANCH_CTRL_2_95}}; + assign _zz__zz_decode_BRANCH_CTRL_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_100) == 32'h00000020); + assign _zz__zz_decode_BRANCH_CTRL_2_102 = _zz_decode_BRANCH_CTRL_5; + assign _zz__zz_decode_BRANCH_CTRL_2_103 = (_zz__zz_decode_BRANCH_CTRL_2_104 == _zz__zz_decode_BRANCH_CTRL_2_105); + assign _zz__zz_decode_BRANCH_CTRL_2_107 = (_zz__zz_decode_BRANCH_CTRL_2_108 == _zz__zz_decode_BRANCH_CTRL_2_109); + assign _zz__zz_decode_BRANCH_CTRL_2_111 = (|_zz__zz_decode_BRANCH_CTRL_2_112); + assign _zz__zz_decode_BRANCH_CTRL_2_113 = (|_zz__zz_decode_BRANCH_CTRL_2_114); + assign _zz__zz_decode_BRANCH_CTRL_2_124 = {_zz__zz_decode_BRANCH_CTRL_2_125,{_zz__zz_decode_BRANCH_CTRL_2_128,_zz__zz_decode_BRANCH_CTRL_2_136}}; + assign _zz__zz_decode_BRANCH_CTRL_2_67 = 32'h00000030; + assign _zz__zz_decode_BRANCH_CTRL_2_69 = 32'h02000020; + assign _zz__zz_decode_BRANCH_CTRL_2_76 = 32'h00001030; + assign _zz__zz_decode_BRANCH_CTRL_2_78 = (decode_INSTRUCTION & 32'h02002060); + assign _zz__zz_decode_BRANCH_CTRL_2_79 = 32'h00002020; + assign _zz__zz_decode_BRANCH_CTRL_2_81 = (decode_INSTRUCTION & 32'h02003020); + assign _zz__zz_decode_BRANCH_CTRL_2_82 = 32'h00000020; + assign _zz__zz_decode_BRANCH_CTRL_2_87 = 32'h00001010; + assign _zz__zz_decode_BRANCH_CTRL_2_89 = (decode_INSTRUCTION & 32'h00002010); + assign _zz__zz_decode_BRANCH_CTRL_2_90 = 32'h00002010; + assign _zz__zz_decode_BRANCH_CTRL_2_92 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); + assign _zz__zz_decode_BRANCH_CTRL_2_93 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_94) == 32'h00000004); + assign _zz__zz_decode_BRANCH_CTRL_2_95 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_96) == 32'h0); + assign _zz__zz_decode_BRANCH_CTRL_2_100 = 32'h00000070; + assign _zz__zz_decode_BRANCH_CTRL_2_104 = (decode_INSTRUCTION & 32'h00000020); + assign _zz__zz_decode_BRANCH_CTRL_2_105 = 32'h0; + assign _zz__zz_decode_BRANCH_CTRL_2_108 = (decode_INSTRUCTION & 32'h00004014); + assign _zz__zz_decode_BRANCH_CTRL_2_109 = 32'h00004010; + assign _zz__zz_decode_BRANCH_CTRL_2_112 = ((decode_INSTRUCTION & 32'h00006014) == 32'h00002010); + assign _zz__zz_decode_BRANCH_CTRL_2_114 = {(_zz__zz_decode_BRANCH_CTRL_2_115 == _zz__zz_decode_BRANCH_CTRL_2_116),{_zz_decode_BRANCH_CTRL_4,{_zz__zz_decode_BRANCH_CTRL_2_117,_zz__zz_decode_BRANCH_CTRL_2_119}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_125 = (|(_zz__zz_decode_BRANCH_CTRL_2_126 == _zz__zz_decode_BRANCH_CTRL_2_127)); + assign _zz__zz_decode_BRANCH_CTRL_2_128 = (|{_zz__zz_decode_BRANCH_CTRL_2_129,_zz__zz_decode_BRANCH_CTRL_2_131}); + assign _zz__zz_decode_BRANCH_CTRL_2_136 = {(|_zz__zz_decode_BRANCH_CTRL_2_137),{_zz__zz_decode_BRANCH_CTRL_2_140,_zz__zz_decode_BRANCH_CTRL_2_142}}; + assign _zz__zz_decode_BRANCH_CTRL_2_94 = 32'h0000000c; + assign _zz__zz_decode_BRANCH_CTRL_2_96 = 32'h00000028; + assign _zz__zz_decode_BRANCH_CTRL_2_115 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_BRANCH_CTRL_2_116 = 32'h0; + assign _zz__zz_decode_BRANCH_CTRL_2_117 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_118) == 32'h00002000); + assign _zz__zz_decode_BRANCH_CTRL_2_119 = {(_zz__zz_decode_BRANCH_CTRL_2_120 == _zz__zz_decode_BRANCH_CTRL_2_121),(_zz__zz_decode_BRANCH_CTRL_2_122 == _zz__zz_decode_BRANCH_CTRL_2_123)}; + assign _zz__zz_decode_BRANCH_CTRL_2_126 = (decode_INSTRUCTION & 32'h00000058); + assign _zz__zz_decode_BRANCH_CTRL_2_127 = 32'h0; + assign _zz__zz_decode_BRANCH_CTRL_2_129 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_130) == 32'h00000040); + assign _zz__zz_decode_BRANCH_CTRL_2_131 = {(_zz__zz_decode_BRANCH_CTRL_2_132 == _zz__zz_decode_BRANCH_CTRL_2_133),(_zz__zz_decode_BRANCH_CTRL_2_134 == _zz__zz_decode_BRANCH_CTRL_2_135)}; + assign _zz__zz_decode_BRANCH_CTRL_2_137 = {(_zz__zz_decode_BRANCH_CTRL_2_138 == _zz__zz_decode_BRANCH_CTRL_2_139),_zz_decode_BRANCH_CTRL_3}; + assign _zz__zz_decode_BRANCH_CTRL_2_140 = (|{_zz__zz_decode_BRANCH_CTRL_2_141,_zz_decode_BRANCH_CTRL_3}); + assign _zz__zz_decode_BRANCH_CTRL_2_142 = (|(_zz__zz_decode_BRANCH_CTRL_2_143 == _zz__zz_decode_BRANCH_CTRL_2_144)); + assign _zz__zz_decode_BRANCH_CTRL_2_118 = 32'h00006004; + assign _zz__zz_decode_BRANCH_CTRL_2_120 = (decode_INSTRUCTION & 32'h00005004); + assign _zz__zz_decode_BRANCH_CTRL_2_121 = 32'h00001000; + assign _zz__zz_decode_BRANCH_CTRL_2_122 = (decode_INSTRUCTION & 32'h00004050); + assign _zz__zz_decode_BRANCH_CTRL_2_123 = 32'h00004000; + assign _zz__zz_decode_BRANCH_CTRL_2_130 = 32'h00000044; + assign _zz__zz_decode_BRANCH_CTRL_2_132 = (decode_INSTRUCTION & 32'h00002014); + assign _zz__zz_decode_BRANCH_CTRL_2_133 = 32'h00002010; + assign _zz__zz_decode_BRANCH_CTRL_2_134 = (decode_INSTRUCTION & 32'h40000034); + assign _zz__zz_decode_BRANCH_CTRL_2_135 = 32'h40000030; + assign _zz__zz_decode_BRANCH_CTRL_2_138 = (decode_INSTRUCTION & 32'h00000014); + assign _zz__zz_decode_BRANCH_CTRL_2_139 = 32'h00000004; + assign _zz__zz_decode_BRANCH_CTRL_2_141 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz__zz_decode_BRANCH_CTRL_2_143 = (decode_INSTRUCTION & 32'h00005048); + assign _zz__zz_decode_BRANCH_CTRL_2_144 = 32'h00001008; + always @(posedge io_systemClk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_1) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + InstructionCache_b62b14ffe6bb44e5a817b8d08e286c6b IBusCachedPlugin_cache ( + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0]), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0]), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + DataCache_b62b14ffe6bb44e5a817b8d08e286c6b dataCache_1 ( + .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i + .io_cpu_execute_address (dataCache_1_io_cpu_execute_address[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (memory_MEMORY_VIRTUAL_ADDRESS[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0]), //i + .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isFiring (writeBack_arbitration_isFiring ), //i + .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData[31:0] ), //i + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i + .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i + .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i + .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i + .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i + .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i + .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i + .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i + .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM[3:0] ), //i + .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_cpu_flush_payload_singleLine (dataCache_1_io_cpu_flush_payload_singleLine ), //i + .io_cpu_flush_payload_lineId (dataCache_1_io_cpu_flush_payload_lineId[5:0] ), //i + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_regNext_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_regNext_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_regNext_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_regNext_payload_error ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + always @(*) begin + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_5) + 2'b00 : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = DBusCachedPlugin_redoBranch_payload; + 2'b01 : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = CsrPlugin_jumpInterface_payload; + default : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = BranchPlugin_jumpInterface_payload; + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) + 2'b00 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; + 2'b01 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; + 2'b10 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; + default : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) + 1'b0 : _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; + default : _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(decode_BRANCH_CTRL) + BranchCtrlEnum_INC : decode_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : decode_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : decode_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_BRANCH_CTRL) + BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_BRANCH_CTRL) + BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_BRANCH_CTRL_1) + BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_memory_to_writeBack_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_memory_to_writeBack_ENV_CTRL_string = "EBREAK"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_memory_to_writeBack_ENV_CTRL_1) + EnvCtrlEnum_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + EnvCtrlEnum_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_memory_to_writeBack_ENV_CTRL_1_string = "EBREAK"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "??????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_execute_to_memory_ENV_CTRL_string = "EBREAK"; + default : _zz_execute_to_memory_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_ENV_CTRL_1) + EnvCtrlEnum_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + EnvCtrlEnum_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_execute_to_memory_ENV_CTRL_1_string = "EBREAK"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "??????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + EnvCtrlEnum_NONE : decode_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : decode_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : decode_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : decode_ENV_CTRL_string = "EBREAK"; + default : decode_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_decode_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_string = "EBREAK"; + default : _zz_decode_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_decode_to_execute_ENV_CTRL_string = "EBREAK"; + default : _zz_decode_to_execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ENV_CTRL_1) + EnvCtrlEnum_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + EnvCtrlEnum_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_decode_to_execute_ENV_CTRL_1_string = "EBREAK"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "??????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_SHIFT_CTRL_1) + ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_SHIFT_CTRL_1) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + AluCtrlEnum_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_CTRL) + AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_CTRL) + AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_CTRL_1) + AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + BranchCtrlEnum_INC : execute_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : execute_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : execute_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_execute_BRANCH_CTRL) + BranchCtrlEnum_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : _zz_execute_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + EnvCtrlEnum_NONE : memory_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : memory_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : memory_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : memory_ENV_CTRL_string = "EBREAK"; + default : memory_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_memory_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_memory_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_memory_ENV_CTRL_string = "EBREAK"; + default : _zz_memory_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + EnvCtrlEnum_NONE : execute_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : execute_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : execute_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : execute_ENV_CTRL_string = "EBREAK"; + default : execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_execute_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_execute_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_execute_ENV_CTRL_string = "EBREAK"; + default : _zz_execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + EnvCtrlEnum_NONE : writeBack_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : writeBack_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : writeBack_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : writeBack_ENV_CTRL_string = "EBREAK"; + default : writeBack_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_writeBack_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_writeBack_ENV_CTRL_string = "EBREAK"; + default : _zz_writeBack_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_memory_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_execute_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + Src2CtrlEnum_RS : decode_SRC2_CTRL_string = "RS "; + Src2CtrlEnum_IMI : decode_SRC2_CTRL_string = "IMI"; + Src2CtrlEnum_IMS : decode_SRC2_CTRL_string = "IMS"; + Src2CtrlEnum_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_SRC2_CTRL) + Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_string = "RS "; + Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + Src1CtrlEnum_RS : decode_SRC1_CTRL_string = "RS "; + Src1CtrlEnum_IMU : decode_SRC1_CTRL_string = "IMU "; + Src1CtrlEnum_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + Src1CtrlEnum_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC1_CTRL) + Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_string = "RS "; + Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + AluCtrlEnum_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_execute_ALU_CTRL) + AluCtrlEnum_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_BRANCH_CTRL_1) + BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_ENV_CTRL_1) + EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_1_string = "EBREAK"; + default : _zz_decode_ENV_CTRL_1_string = "??????"; + endcase + end + always @(*) begin + case(_zz_decode_SHIFT_CTRL_1) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_BITWISE_CTRL_1) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC2_CTRL_1) + Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_CTRL_1) + AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC1_CTRL_1) + Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC1_CTRL_2) + Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_CTRL_2) + AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC2_CTRL_2) + Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_BITWISE_CTRL_2) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_SHIFT_CTRL_2) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_ENV_CTRL_2) + EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_2_string = "EBREAK"; + default : _zz_decode_ENV_CTRL_2_string = "??????"; + endcase + end + always @(*) begin + case(_zz_decode_BRANCH_CTRL_9) + BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_9_string = "INC "; + BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_9_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_9_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_9_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_9_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + AluCtrlEnum_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + EnvCtrlEnum_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : decode_to_execute_ENV_CTRL_string = "EBREAK"; + default : decode_to_execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + EnvCtrlEnum_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : execute_to_memory_ENV_CTRL_string = "EBREAK"; + default : execute_to_memory_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + EnvCtrlEnum_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : memory_to_writeBack_ENV_CTRL_string = "EBREAK"; + default : memory_to_writeBack_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + BranchCtrlEnum_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : decode_to_execute_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + `endif + + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = _zz_execute_BRANCH_DO_1; + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = execute_MulPlugin_withOuputBuffer_mul_hh; + assign execute_MUL_HL = execute_MulPlugin_withOuputBuffer_mul_hl; + assign execute_MUL_LH = execute_MulPlugin_withOuputBuffer_mul_lh; + assign execute_MUL_LL = execute_MulPlugin_withOuputBuffer_mul_ll; + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign execute_MEMORY_VIRTUAL_ADDRESS = dataCache_1_io_cpu_execute_address; + assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; + assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; + assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_SRC2 = _zz_decode_SRC2_6; + assign decode_SRC1 = _zz_decode_SRC1_1; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_BRANCH_CTRL_2[27]; + assign decode_IS_RS2_SIGNED = _zz_decode_BRANCH_CTRL_2[26]; + assign decode_IS_RS1_SIGNED = _zz_decode_BRANCH_CTRL_2[25]; + assign decode_IS_DIV = _zz_decode_BRANCH_CTRL_2[24]; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign decode_IS_MUL = _zz_decode_BRANCH_CTRL_2[23]; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_BRANCH_CTRL_2[17]; + assign decode_MEMORY_MANAGMENT = _zz_decode_BRANCH_CTRL_2[16]; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_decode_BRANCH_CTRL_2[13]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_BRANCH_CTRL_2[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_BRANCH_CTRL_2[11]; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_decode_BRANCH_CTRL_2[30]; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PC = decode_to_execute_PC; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_RS2_USE = _zz_decode_BRANCH_CTRL_2[15]; + assign decode_RS1_USE = _zz_decode_BRANCH_CTRL_2[5]; + always @(*) begin + _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1189) begin + _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; + end + end + + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @(*) begin + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; + end + end + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; + end + end + end + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2_1; + end + end + end + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2; + end + end + end + end + + always @(*) begin + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; + end + end + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; + end + end + end + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2_1; + end + end + end + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2; + end + end + end + end + + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; + always @(*) begin + _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin + case(memory_SHIFT_CTRL) + ShiftCtrlEnum_SLL_1 : begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; + end + ShiftCtrlEnum_SRL_1, ShiftCtrlEnum_SRA_1 : begin + _zz_decode_RS2_1 = memory_SHIFT_RIGHT; + end + default : begin + end + endcase + end + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2_1 = memory_MulDivIterativePlugin_div_result; + end + end + + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_decode_SRC2 = decode_PC; + assign _zz_decode_SRC2_1 = decode_RS2; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_SRC1 = decode_RS1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_BRANCH_CTRL_2[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_BRANCH_CTRL_2[20]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = decode_to_execute_SRC2; + assign execute_SRC1 = decode_to_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_iBusRsp_output_payload_rsp_inst); + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_BRANCH_CTRL_2[10]; + if(when_RegFilePlugin_l63) begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = (|{((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}}); + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusCachedPlugin_l492) begin + _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; + end + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) + 2'b00 : begin + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; + end + default : begin + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; + end + endcase + end + end + + assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign memory_MEMORY_VIRTUAL_ADDRESS = execute_to_memory_MEMORY_VIRTUAL_ADDRESS; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign decode_MEMORY_ENABLE = _zz_decode_BRANCH_CTRL_2[4]; + assign decode_FLUSH_ALL = _zz_decode_BRANCH_CTRL_2[0]; + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(when_IBusCachedPlugin_l256) begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(when_IBusCachedPlugin_l244) begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(when_IBusCachedPlugin_l239) begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; + end + end + + always @(*) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; + end + end + + assign decode_PC = IBusCachedPlugin_injector_decodeInput_payload_pc; + assign decode_INSTRUCTION = IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @(*) begin + decode_arbitration_haltItself = 1'b0; + if(when_DBusCachedPlugin_l308) begin + decode_arbitration_haltItself = 1'b1; + end + case(switch_Fetcher_l365) + 3'b010 : begin + decode_arbitration_haltItself = 1'b1; + end + default : begin + end + endcase + end + + always @(*) begin + decode_arbitration_haltByOther = 1'b0; + if(when_HazardSimplePlugin_l113) begin + decode_arbitration_haltByOther = 1'b1; + end + if(CsrPlugin_pipelineLiberator_active) begin + decode_arbitration_haltByOther = 1'b1; + end + if(when_CsrPlugin_l1129) begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @(*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_when) begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed) begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + always @(*) begin + decode_arbitration_flushNext = 1'b0; + if(_zz_when) begin + decode_arbitration_flushNext = 1'b1; + end + end + + always @(*) begin + execute_arbitration_haltItself = 1'b0; + if(when_DBusCachedPlugin_l350) begin + execute_arbitration_haltItself = 1'b1; + end + if(when_MulPlugin_l65) begin + execute_arbitration_haltItself = 1'b1; + end + if(when_CsrPlugin_l1193) begin + if(execute_CsrPlugin_blockedBySideEffects) begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + always @(*) begin + execute_arbitration_haltByOther = 1'b0; + if(when_DBusCachedPlugin_l366) begin + execute_arbitration_haltByOther = 1'b1; + end + if(when_DebugPlugin_l295) begin + execute_arbitration_haltByOther = 1'b1; + end + end + + always @(*) begin + execute_arbitration_removeIt = 1'b0; + if(CsrPlugin_selfException_valid) begin + execute_arbitration_removeIt = 1'b1; + end + if(execute_arbitration_isFlushed) begin + execute_arbitration_removeIt = 1'b1; + end + end + + always @(*) begin + execute_arbitration_flushIt = 1'b0; + if(when_DebugPlugin_l295) begin + if(when_DebugPlugin_l298) begin + execute_arbitration_flushIt = 1'b1; + end + end + end + + always @(*) begin + execute_arbitration_flushNext = 1'b0; + if(CsrPlugin_selfException_valid) begin + execute_arbitration_flushNext = 1'b1; + end + if(when_DebugPlugin_l295) begin + if(when_DebugPlugin_l298) begin + execute_arbitration_flushNext = 1'b1; + end + end + end + + always @(*) begin + memory_arbitration_haltItself = 1'b0; + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @(*) begin + memory_arbitration_removeIt = 1'b0; + if(BranchPlugin_branchExceptionPort_valid) begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed) begin + memory_arbitration_removeIt = 1'b1; + end + end + + assign memory_arbitration_flushIt = 1'b0; + always @(*) begin + memory_arbitration_flushNext = 1'b0; + if(BranchPlugin_branchExceptionPort_valid) begin + memory_arbitration_flushNext = 1'b1; + end + if(BranchPlugin_jumpInterface_valid) begin + memory_arbitration_flushNext = 1'b1; + end + end + + always @(*) begin + writeBack_arbitration_haltItself = 1'b0; + if(when_DBusCachedPlugin_l466) begin + writeBack_arbitration_haltItself = 1'b1; + end + end + + assign writeBack_arbitration_haltByOther = 1'b0; + always @(*) begin + writeBack_arbitration_removeIt = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid) begin + writeBack_arbitration_removeIt = 1'b1; + end + if(writeBack_arbitration_isFlushed) begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + always @(*) begin + writeBack_arbitration_flushIt = 1'b0; + if(DBusCachedPlugin_redoBranch_valid) begin + writeBack_arbitration_flushIt = 1'b1; + end + end + + always @(*) begin + writeBack_arbitration_flushNext = 1'b0; + if(DBusCachedPlugin_redoBranch_valid) begin + writeBack_arbitration_flushNext = 1'b1; + end + if(DBusCachedPlugin_exceptionBus_valid) begin + writeBack_arbitration_flushNext = 1'b1; + end + if(when_CsrPlugin_l1032) begin + writeBack_arbitration_flushNext = 1'b1; + end + if(when_CsrPlugin_l1077) begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @(*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(when_CsrPlugin_l935) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(when_CsrPlugin_l1032) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(when_CsrPlugin_l1077) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(when_DebugPlugin_l295) begin + if(when_DebugPlugin_l298) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + if(DebugPlugin_haltIt) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(when_DebugPlugin_l311) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + assign IBusCachedPlugin_forceNoDecodeCond = 1'b0; + always @(*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if(when_Fetcher_l243) begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + if(IBusCachedPlugin_injector_decodeInput_valid) begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @(*) begin + _zz_when_DBusCachedPlugin_l393 = 1'b0; + if(DebugPlugin_godmode) begin + _zz_when_DBusCachedPlugin_l393 = 1'b1; + end + end + + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; + assign CsrPlugin_inWfi = 1'b0; + always @(*) begin + CsrPlugin_thirdPartyWake = 1'b0; + if(DebugPlugin_haltIt) begin + CsrPlugin_thirdPartyWake = 1'b1; + end + end + + always @(*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(when_CsrPlugin_l1032) begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(when_CsrPlugin_l1077) begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1032) begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; + end + if(when_CsrPlugin_l1077) begin + case(switch_CsrPlugin_l1081) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + always @(*) begin + CsrPlugin_forceMachineWire = 1'b0; + if(DebugPlugin_godmode) begin + CsrPlugin_forceMachineWire = 1'b1; + end + end + + always @(*) begin + CsrPlugin_allowInterrupts = 1'b1; + if(when_DebugPlugin_l331) begin + CsrPlugin_allowInterrupts = 1'b0; + end + end + + always @(*) begin + CsrPlugin_allowException = 1'b1; + if(DebugPlugin_godmode) begin + CsrPlugin_allowException = 1'b0; + end + end + + always @(*) begin + CsrPlugin_allowEbreakException = 1'b1; + if(DebugPlugin_allowEBreak) begin + CsrPlugin_allowEbreakException = 1'b0; + end + end + + always @(*) begin + BranchPlugin_inDebugNoFetchFlag = 1'b0; + if(DebugPlugin_godmode) begin + BranchPlugin_inDebugNoFetchFlag = 1'b1; + end + end + + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (((IBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hf8000000) || ((IBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hfa000000)); + assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusCachedPlugin_mmuBus_busy = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (((DBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hf8000000) || ((DBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hfa000000)); + assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusCachedPlugin_mmuBus_busy = 1'b0; + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}} != 3'b000); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[1]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[2]; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_4; + always @(*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid) begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid) begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); + always @(*) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + assign when_Fetcher_l134 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l134_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end + if(IBusCachedPlugin_jump_pcLoad_valid) begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + always @(*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid) begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid) begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + + assign when_Fetcher_l161 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @(*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_mmuBus_busy) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if(when_IBusCachedPlugin_l267) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; + end + end + + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = (IBusCachedPlugin_externalFlush || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if(IBusCachedPlugin_injector_decodeInput_valid) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + if(when_Fetcher_l323) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign when_Fetcher_l243 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign IBusCachedPlugin_iBusRsp_output_ready = ((1'b0 && (! IBusCachedPlugin_injector_decodeInput_valid)) || IBusCachedPlugin_injector_decodeInput_ready); + assign IBusCachedPlugin_injector_decodeInput_valid = _zz_IBusCachedPlugin_injector_decodeInput_valid; + assign IBusCachedPlugin_injector_decodeInput_payload_pc = _zz_IBusCachedPlugin_injector_decodeInput_payload_pc; + assign IBusCachedPlugin_injector_decodeInput_payload_rsp_error = _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error; + assign IBusCachedPlugin_injector_decodeInput_payload_rsp_inst = _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + assign IBusCachedPlugin_injector_decodeInput_payload_isRvc = _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc; + assign when_Fetcher_l323 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l332 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l332_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l332_2 = (! (! IBusCachedPlugin_injector_decodeInput_ready)); + assign when_Fetcher_l332_3 = (! execute_arbitration_isStuck); + assign when_Fetcher_l332_4 = (! memory_arbitration_isStuck); + assign when_Fetcher_l332_5 = (! writeBack_arbitration_isStuck); + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_5; + assign IBusCachedPlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); + always @(*) begin + decode_arbitration_isValid = IBusCachedPlugin_injector_decodeInput_valid; + case(switch_Fetcher_l365) + 3'b010 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b011 : begin + decode_arbitration_isValid = 1'b1; + end + default : begin + end + endcase + if(IBusCachedPlugin_forceNoDecodeCond) begin + decode_arbitration_isValid = 1'b0; + end + end + + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @(*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; + always @(*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(when_IBusCachedPlugin_l239) begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(when_IBusCachedPlugin_l244) begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(when_IBusCachedPlugin_l256) begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + always @(*) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(when_IBusCachedPlugin_l244) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(when_IBusCachedPlugin_l256) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); + always @(*) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l368) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign when_DBusCachedPlugin_l308 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; + assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD; + always @(*) begin + case(execute_DBusCachedPlugin_size) + 2'b00 : begin + _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; + end + endcase + end + + assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign dataCache_1_io_cpu_flush_payload_singleLine = (execute_INSTRUCTION[19 : 15] != 5'h0); + assign dataCache_1_io_cpu_flush_payload_lineId = _zz_io_cpu_flush_payload_lineId[5:0]; + assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); + assign when_DBusCachedPlugin_l350 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); + assign when_DBusCachedPlugin_l366 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); + assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = memory_MEMORY_VIRTUAL_ADDRESS; + assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + always @(*) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if(when_DBusCachedPlugin_l393) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; + end + end + + assign when_DBusCachedPlugin_l393 = (_zz_when_DBusCachedPlugin_l393 && (! dataCache_1_io_cpu_memory_isWrite)); + always @(*) begin + dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_arbitration_haltByOther) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b0; + end + end + + assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); + assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; + assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; + always @(*) begin + DBusCachedPlugin_redoBranch_valid = 1'b0; + if(when_DBusCachedPlugin_l446) begin + if(dataCache_1_io_cpu_redo) begin + DBusCachedPlugin_redoBranch_valid = 1'b1; + end + end + end + + assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; + always @(*) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + if(when_DBusCachedPlugin_l446) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_mmuException) begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_redo) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + end + end + end + + assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; + always @(*) begin + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(when_DBusCachedPlugin_l446) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; + end + if(dataCache_1_io_cpu_writeBack_mmuException) begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; + end + end + end + + assign when_DBusCachedPlugin_l446 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign when_DBusCachedPlugin_l466 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); + assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; + assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; + assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; + assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; + always @(*) begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; + writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; + writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; + end + + assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; + assign switch_Misc_l210 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; + end + + assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; + end + + always @(*) begin + case(switch_Misc_l210) + 2'b00 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; + end + 2'b01 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; + end + default : begin + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; + end + endcase + end + + assign when_DBusCachedPlugin_l492 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_decode_BRANCH_CTRL_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_BRANCH_CTRL_4 = ((decode_INSTRUCTION & 32'h00000018) == 32'h0); + assign _zz_decode_BRANCH_CTRL_5 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_BRANCH_CTRL_6 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_BRANCH_CTRL_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_decode_BRANCH_CTRL_8 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00100050); + assign _zz_decode_BRANCH_CTRL_2 = {(|{_zz_decode_BRANCH_CTRL_6,(_zz__zz_decode_BRANCH_CTRL_2 == _zz__zz_decode_BRANCH_CTRL_2_1)}),{(|(_zz__zz_decode_BRANCH_CTRL_2_2 == _zz__zz_decode_BRANCH_CTRL_2_3)),{(|_zz_decode_BRANCH_CTRL_8),{(|_zz__zz_decode_BRANCH_CTRL_2_4),{_zz__zz_decode_BRANCH_CTRL_2_5,{_zz__zz_decode_BRANCH_CTRL_2_8,_zz__zz_decode_BRANCH_CTRL_2_11}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_BRANCH_CTRL_2[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_BRANCH_CTRL_2[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_BRANCH_CTRL_2[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_BRANCH_CTRL_2[19 : 18]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_BRANCH_CTRL_2[22 : 21]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_BRANCH_CTRL_2[29 : 28]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; + assign _zz_decode_BRANCH_CTRL_9 = _zz_decode_BRANCH_CTRL_2[32 : 31]; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL_9; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_2) begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_2) begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_2) begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + AluBitwiseCtrlEnum_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @(*) begin + case(execute_ALU_CTRL) + AluCtrlEnum_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; + end + AluCtrlEnum_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; + end + default : begin + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; + end + endcase + end + + always @(*) begin + case(decode_SRC1_CTRL) + Src1CtrlEnum_RS : begin + _zz_decode_SRC1_1 = _zz_decode_SRC1; + end + Src1CtrlEnum_PC_INCREMENT : begin + _zz_decode_SRC1_1 = {29'd0, _zz__zz_decode_SRC1_1}; + end + Src1CtrlEnum_IMU : begin + _zz_decode_SRC1_1 = {decode_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_decode_SRC1_1 = {27'd0, _zz__zz_decode_SRC1_1_1}; + end + endcase + end + + assign _zz_decode_SRC2_2 = decode_INSTRUCTION[31]; + always @(*) begin + _zz_decode_SRC2_3[19] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[18] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[17] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[16] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[15] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[14] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[13] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[12] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[11] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[10] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[9] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[8] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[7] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[6] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[5] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[4] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[3] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[2] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[1] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[0] = _zz_decode_SRC2_2; + end + + assign _zz_decode_SRC2_4 = _zz__zz_decode_SRC2_4[11]; + always @(*) begin + _zz_decode_SRC2_5[19] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[18] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[17] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[16] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[15] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[14] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[13] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[12] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[11] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[10] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[9] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[8] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[7] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[6] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[5] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[4] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[3] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[2] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[1] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[0] = _zz_decode_SRC2_4; + end + + always @(*) begin + case(decode_SRC2_CTRL) + Src2CtrlEnum_RS : begin + _zz_decode_SRC2_6 = _zz_decode_SRC2_1; + end + Src2CtrlEnum_IMI : begin + _zz_decode_SRC2_6 = {_zz_decode_SRC2_3,decode_INSTRUCTION[31 : 20]}; + end + Src2CtrlEnum_IMS : begin + _zz_decode_SRC2_6 = {_zz_decode_SRC2_5,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_decode_SRC2_6 = _zz_decode_SRC2; + end + endcase + end + + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == ShiftCtrlEnum_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; + _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; + _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; + _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; + _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; + _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; + _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; + _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; + _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; + _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; + _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; + _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; + _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; + _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; + _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; + _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; + _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; + _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; + _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; + _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; + _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; + _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; + _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; + _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; + _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; + _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; + _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; + _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; + _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; + _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; + _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; + _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; + end + end + + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); + assign when_MulPlugin_l65 = ((execute_arbitration_isValid && execute_IS_MUL) && (execute_MulPlugin_delayLogic_counter != 1'b1)); + assign when_MulPlugin_l70 = ((! execute_arbitration_isStuck) || execute_arbitration_isStuckByOthers); + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) + 2'b01 : begin + execute_MulPlugin_aSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_aSigned = 1'b1; + end + default : begin + execute_MulPlugin_aSigned = 1'b0; + end + endcase + end + + always @(*) begin + case(switch_MulPlugin_l87) + 2'b01 : begin + execute_MulPlugin_bSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_bSigned = 1'b0; + end + default : begin + execute_MulPlugin_bSigned = 1'b0; + end + endcase + end + + assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; + assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; + assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; + assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; + assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; + assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; + assign memory_MulDivIterativePlugin_frontendOk = 1'b1; + always @(*) begin + memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin + memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @(*) begin + memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; + if(when_MulDivIterativePlugin_l162) begin + memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == 6'h21); + assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement); + always @(*) begin + if(memory_MulDivIterativePlugin_div_counter_willOverflow) begin + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; + end else begin + memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_memory_MulDivIterativePlugin_div_counter_valueNext); + end + if(memory_MulDivIterativePlugin_div_counter_willClear) begin + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; + end + end + + assign when_MulDivIterativePlugin_l126 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); + assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted = memory_MulDivIterativePlugin_rs1[31 : 0]; + assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31]}; + assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator); + assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder : _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1); + assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); + assign _zz_memory_MulDivIterativePlugin_div_result = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_MulDivIterativePlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_MulDivIterativePlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_MulDivIterativePlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_MulDivIterativePlugin_rs1_1[31 : 0] = execute_RS1; + end + + always @(*) begin + CsrPlugin_privilege = 2'b11; + if(CsrPlugin_forceMachineWire) begin + CsrPlugin_privilege = 2'b11; + end + end + + assign _zz_when_CsrPlugin_l965 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l965_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l965_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(CsrPlugin_selfException_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(BranchPlugin_branchExceptionPort_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(DBusCachedPlugin_exceptionBus_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + end + if(writeBack_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign when_CsrPlugin_l922 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l922_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l922_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l922_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l935 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l959 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l965 = ((_zz_when_CsrPlugin_l965 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l965_1 = ((_zz_when_CsrPlugin_l965_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l965_2 = ((_zz_when_CsrPlugin_l965_2 && 1'b1) && (! 1'b0)); + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_lastStageWasWfi = 1'b0; + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + assign when_CsrPlugin_l993 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l993_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l993_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l998 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(when_CsrPlugin_l1004) begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException) begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign when_CsrPlugin_l1004 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @(*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException) begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @(*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException) begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @(*) begin + CsrPlugin_xtvec_mode = 2'bxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign when_CsrPlugin_l1032 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1077 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == EnvCtrlEnum_XRET)); + assign switch_CsrPlugin_l1081 = writeBack_INSTRUCTION[29 : 28]; + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1129 = (|{(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == EnvCtrlEnum_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == EnvCtrlEnum_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_XRET))}}); + assign execute_CsrPlugin_blockedBySideEffects = ((|{writeBack_arbitration_isValid,memory_arbitration_isValid}) || 1'b0); + always @(*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_3860) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_769) begin + if(execute_CSR_WRITE_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_768) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_833) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_832) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_835) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1310) begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(when_CsrPlugin_l1315) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @(*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if(when_CsrPlugin_l1149) begin + if(when_CsrPlugin_l1150) begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @(*) begin + CsrPlugin_selfException_valid = 1'b0; + if(when_CsrPlugin_l1142) begin + CsrPlugin_selfException_valid = 1'b1; + end + if(when_CsrPlugin_l1157) begin + CsrPlugin_selfException_valid = 1'b1; + end + if(when_CsrPlugin_l1167) begin + CsrPlugin_selfException_valid = 1'b1; + end + end + + always @(*) begin + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(when_CsrPlugin_l1142) begin + CsrPlugin_selfException_payload_code = 4'b0010; + end + if(when_CsrPlugin_l1157) begin + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = 4'b1000; + end + default : begin + CsrPlugin_selfException_payload_code = 4'b1011; + end + endcase + end + if(when_CsrPlugin_l1167) begin + CsrPlugin_selfException_payload_code = 4'b0011; + end + end + + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + assign when_CsrPlugin_l1142 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign when_CsrPlugin_l1149 = (execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_XRET)); + assign when_CsrPlugin_l1150 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1157 = (execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_ECALL)); + assign when_CsrPlugin_l1167 = ((execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_EBREAK)) && CsrPlugin_allowEbreakException); + always @(*) begin + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(when_CsrPlugin_l1310) begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @(*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(when_CsrPlugin_l1310) begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l210_1 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l210_1) + 1'b0 : begin + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; + end + default : begin + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1189 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1193 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign switch_Misc_l210_2 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l210_2) + 3'b000 : begin + _zz_execute_BRANCH_DO = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_DO = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_DO = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_DO = execute_SRC_LESS; + end + endcase + end + + always @(*) begin + case(execute_BRANCH_CTRL) + BranchCtrlEnum_INC : begin + _zz_execute_BRANCH_DO_1 = 1'b0; + end + BranchCtrlEnum_JAL : begin + _zz_execute_BRANCH_DO_1 = 1'b1; + end + BranchCtrlEnum_JALR : begin + _zz_execute_BRANCH_DO_1 = 1'b1; + end + default : begin + _zz_execute_BRANCH_DO_1 = _zz_execute_BRANCH_DO; + end + endcase + end + + assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == BranchCtrlEnum_JALR) ? execute_RS1 : execute_PC); + assign _zz_execute_BranchPlugin_branch_src2 = _zz__zz_execute_BranchPlugin_branch_src2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + assign _zz_execute_BranchPlugin_branch_src2_2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[19] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[18] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[17] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[16] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[15] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[14] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[13] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[12] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[11] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; + end + + always @(*) begin + case(execute_BRANCH_CTRL) + BranchCtrlEnum_JAL : begin + _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_1,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + end + BranchCtrlEnum_JALR : begin + _zz_execute_BranchPlugin_branch_src2_6 = {_zz_execute_BranchPlugin_branch_src2_3,execute_INSTRUCTION[31 : 20]}; + end + default : begin + _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + end + endcase + end + + assign execute_BranchPlugin_branch_src2 = _zz_execute_BranchPlugin_branch_src2_6; + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; + assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; + assign when_DebugPlugin_l225 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)); + assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak)); + always @(*) begin + debug_bus_cmd_ready = 1'b1; + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l267) + 6'h01 : begin + if(debug_bus_cmd_payload_wr) begin + debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; + end + end + default : begin + end + endcase + end + end + + always @(*) begin + debug_bus_rsp_data = DebugPlugin_busReadDataReg; + if(when_DebugPlugin_l244) begin + debug_bus_rsp_data[0] = DebugPlugin_resetIt; + debug_bus_rsp_data[1] = DebugPlugin_haltIt; + debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; + debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; + debug_bus_rsp_data[4] = DebugPlugin_stepIt; + end + end + + assign when_DebugPlugin_l244 = (! _zz_when_DebugPlugin_l244); + always @(*) begin + IBusCachedPlugin_injectionPort_valid = 1'b0; + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l267) + 6'h01 : begin + if(debug_bus_cmd_payload_wr) begin + IBusCachedPlugin_injectionPort_valid = 1'b1; + end + end + default : begin + end + endcase + end + end + + assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; + assign switch_DebugPlugin_l267 = debug_bus_cmd_payload_address[7 : 2]; + assign when_DebugPlugin_l271 = debug_bus_cmd_payload_data[16]; + assign when_DebugPlugin_l271_1 = debug_bus_cmd_payload_data[24]; + assign when_DebugPlugin_l272 = debug_bus_cmd_payload_data[17]; + assign when_DebugPlugin_l272_1 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l273 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l274 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l275 = debug_bus_cmd_payload_data[18]; + assign when_DebugPlugin_l275_1 = debug_bus_cmd_payload_data[26]; + assign when_DebugPlugin_l295 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign when_DebugPlugin_l298 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign when_DebugPlugin_l311 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign when_DebugPlugin_l331 = (DebugPlugin_haltIt || DebugPlugin_stepIt); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_14 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_16 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_17 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_28 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_31 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_33 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_34 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_35 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_37 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_38 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_39 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; + assign when_Pipeline_l124_40 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_59 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_60 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck); + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + always @(*) begin + IBusCachedPlugin_injectionPort_ready = 1'b0; + case(switch_Fetcher_l365) + 3'b100 : begin + IBusCachedPlugin_injectionPort_ready = 1'b1; + end + default : begin + end + endcase + end + + assign when_Fetcher_l381 = (! decode_arbitration_isStuck); + assign when_Fetcher_l401 = (switch_Fetcher_l365 != 3'b000); + assign when_CsrPlugin_l1277 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_9 = (! execute_arbitration_isStuck); + assign switch_CsrPlugin_l723 = CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_CsrPlugin_csrMapping_readDataInit[12 : 11] = CsrPlugin_mstatus_MPP; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_1 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_1[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_1[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_1[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_2[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_2[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_2[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; + if(execute_CsrPlugin_csr_773) begin + _zz_CsrPlugin_csrMapping_readDataInit_3[31 : 2] = CsrPlugin_mtvec_base; + _zz_CsrPlugin_csrMapping_readDataInit_3[1 : 0] = CsrPlugin_mtvec_mode; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_4[31 : 0] = CsrPlugin_mepc; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; + if(execute_CsrPlugin_csr_832) begin + _zz_CsrPlugin_csrMapping_readDataInit_5[31 : 0] = CsrPlugin_mscratch; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_6[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_7[31 : 0] = CsrPlugin_mtval; + end + end + + assign CsrPlugin_csrMapping_readDataInit = ((((32'h0 | _zz_CsrPlugin_csrMapping_readDataInit) | (_zz_CsrPlugin_csrMapping_readDataInit_1 | _zz_CsrPlugin_csrMapping_readDataInit_2)) | ((_zz_CsrPlugin_csrMapping_readDataInit_3 | _zz_CsrPlugin_csrMapping_readDataInit_4) | (_zz_CsrPlugin_csrMapping_readDataInit_5 | _zz_CsrPlugin_csrMapping_readDataInit_6))) | _zz_CsrPlugin_csrMapping_readDataInit_7); + assign when_CsrPlugin_l1310 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1315 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + IBusCachedPlugin_fetchPc_pcReg <= 32'hf9000000; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; + _zz_IBusCachedPlugin_injector_decodeInput_valid <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + dBus_rsp_regNext_valid <= 1'b0; + DBusCachedPlugin_rspCounter <= 32'h0; + _zz_2 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + memory_MulDivIterativePlugin_div_counter_value <= 6'h0; + CsrPlugin_misa_base <= 2'b01; + CsrPlugin_misa_extensions <= 26'h0041101; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_mcycle <= 64'h0; + CsrPlugin_minstret <= 64'h0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + switch_Fetcher_l365 <= 3'b000; + end else begin + if(IBusCachedPlugin_fetchPc_correction) begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_output_fire) begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if(when_Fetcher_l134) begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_output_fire_1) begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(when_Fetcher_l134_1) begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(when_Fetcher_l161) begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + end + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + end + if(decode_arbitration_removeIt) begin + _zz_IBusCachedPlugin_injector_decodeInput_valid <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_output_ready) begin + _zz_IBusCachedPlugin_injector_decodeInput_valid <= (IBusCachedPlugin_iBusRsp_output_valid && (! IBusCachedPlugin_externalFlush)); + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if(when_Fetcher_l332) begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(when_Fetcher_l332_1) begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(when_Fetcher_l332_2) begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(when_Fetcher_l332_3) begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(when_Fetcher_l332_4) begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; + end + if(when_Fetcher_l332_5) begin + IBusCachedPlugin_injector_nextPcCalc_valids_5 <= IBusCachedPlugin_injector_nextPcCalc_valids_4; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; + end + if(iBus_rsp_valid) begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + end + if(dataCache_1_io_mem_cmd_valid) begin + dataCache_1_io_mem_cmd_rValid <= 1'b1; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_rValid <= 1'b0; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + end + dBus_rsp_regNext_valid <= dBus_rsp_valid; + if(dBus_rsp_valid) begin + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); + end + _zz_2 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring) begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(when_CsrPlugin_l922) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if(when_CsrPlugin_l922_1) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if(when_CsrPlugin_l922_2) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if(when_CsrPlugin_l922_3) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(when_CsrPlugin_l959) begin + if(when_CsrPlugin_l965) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(when_CsrPlugin_l965_1) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(when_CsrPlugin_l965_2) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l993) begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if(when_CsrPlugin_l993_1) begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if(when_CsrPlugin_l993_2) begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(when_CsrPlugin_l998) begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump) begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(when_CsrPlugin_l1032) begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(when_CsrPlugin_l1077) begin + case(switch_CsrPlugin_l1081) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l965_2,{_zz_when_CsrPlugin_l965_1,_zz_when_CsrPlugin_l965}} != 3'b000) || CsrPlugin_thirdPartyWake); + if(when_Pipeline_l151) begin + execute_arbitration_isValid <= 1'b0; + end + if(when_Pipeline_l154) begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(when_Pipeline_l151_1) begin + memory_arbitration_isValid <= 1'b0; + end + if(when_Pipeline_l154_1) begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(when_Pipeline_l151_2) begin + writeBack_arbitration_isValid <= 1'b0; + end + if(when_Pipeline_l154_2) begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(switch_Fetcher_l365) + 3'b000 : begin + if(IBusCachedPlugin_injectionPort_valid) begin + switch_Fetcher_l365 <= 3'b001; + end + end + 3'b001 : begin + switch_Fetcher_l365 <= 3'b010; + end + 3'b010 : begin + switch_Fetcher_l365 <= 3'b011; + end + 3'b011 : begin + if(when_Fetcher_l381) begin + switch_Fetcher_l365 <= 3'b100; + end + end + 3'b100 : begin + switch_Fetcher_l365 <= 3'b000; + end + default : begin + end + endcase + if(execute_CsrPlugin_csr_769) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30]; + CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0]; + end + end + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; + case(switch_CsrPlugin_l723) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b11; + end + default : begin + end + endcase + end + end + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; + end + end + end + end + + always @(posedge io_systemClk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_output_ready) begin + _zz_IBusCachedPlugin_injector_decodeInput_payload_pc <= IBusCachedPlugin_iBusRsp_output_payload_pc; + _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error <= IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst <= IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc <= IBusCachedPlugin_iBusRsp_output_payload_isRvc; + end + if(IBusCachedPlugin_injector_decodeInput_ready) begin + IBusCachedPlugin_injector_formal_rawInDecode <= IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(dataCache_1_io_mem_cmd_ready) begin + dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; + dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + dBus_rsp_regNext_payload_last <= dBus_rsp_payload_last; + dBus_rsp_regNext_payload_data <= dBus_rsp_payload_data; + dBus_rsp_regNext_payload_error <= dBus_rsp_payload_error; + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + execute_MulPlugin_delayLogic_counter <= (execute_MulPlugin_delayLogic_counter + 1'b1); + if(when_MulPlugin_l70) begin + execute_MulPlugin_delayLogic_counter <= 1'b0; + end + execute_MulPlugin_withOuputBuffer_mul_ll <= (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + execute_MulPlugin_withOuputBuffer_mul_lh <= ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + execute_MulPlugin_withOuputBuffer_mul_hl <= ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + execute_MulPlugin_withOuputBuffer_mul_hh <= ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + if(when_MulDivIterativePlugin_l126) begin + memory_MulDivIterativePlugin_div_done <= 1'b1; + end + if(when_MulDivIterativePlugin_l126_1) begin + memory_MulDivIterativePlugin_div_done <= 1'b0; + end + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin + memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; + memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; + if(when_MulDivIterativePlugin_l151) begin + memory_MulDivIterativePlugin_div_result <= _zz_memory_MulDivIterativePlugin_div_result_1[31:0]; + end + end + end + if(when_MulDivIterativePlugin_l162) begin + memory_MulDivIterativePlugin_accumulator <= 65'h0; + memory_MulDivIterativePlugin_rs1 <= ((_zz_memory_MulDivIterativePlugin_rs1 ? (~ _zz_memory_MulDivIterativePlugin_rs1_1) : _zz_memory_MulDivIterativePlugin_rs1_1) + _zz_memory_MulDivIterativePlugin_rs1_2); + memory_MulDivIterativePlugin_rs2 <= ((_zz_memory_MulDivIterativePlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_MulDivIterativePlugin_rs2_1); + memory_MulDivIterativePlugin_div_needRevert <= ((_zz_memory_MulDivIterativePlugin_rs1 ^ (_zz_memory_MulDivIterativePlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(CsrPlugin_selfException_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + end + if(BranchPlugin_branchExceptionPort_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + end + if(DBusCachedPlugin_exceptionBus_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(when_CsrPlugin_l959) begin + if(when_CsrPlugin_l965) begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(when_CsrPlugin_l965_1) begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(when_CsrPlugin_l965_2) begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(when_CsrPlugin_l1032) begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException) begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if(when_Pipeline_l124) begin + decode_to_execute_PC <= _zz_decode_SRC2; + end + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= execute_PC; + end + if(when_Pipeline_l124_2) begin + memory_to_writeBack_PC <= memory_PC; + end + if(when_Pipeline_l124_3) begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if(when_Pipeline_l124_4) begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if(when_Pipeline_l124_5) begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if(when_Pipeline_l124_6) begin + decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; + end + if(when_Pipeline_l124_7) begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if(when_Pipeline_l124_8) begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; + end + if(when_Pipeline_l124_9) begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if(when_Pipeline_l124_10) begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if(when_Pipeline_l124_11) begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if(when_Pipeline_l124_12) begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if(when_Pipeline_l124_13) begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if(when_Pipeline_l124_14) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; + end + if(when_Pipeline_l124_15) begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if(when_Pipeline_l124_16) begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if(when_Pipeline_l124_17) begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if(when_Pipeline_l124_18) begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if(when_Pipeline_l124_19) begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if(when_Pipeline_l124_20) begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if(when_Pipeline_l124_21) begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if(when_Pipeline_l124_22) begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if(when_Pipeline_l124_23) begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if(when_Pipeline_l124_24) begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if(when_Pipeline_l124_25) begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if(when_Pipeline_l124_26) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; + end + if(when_Pipeline_l124_27) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; + end + if(when_Pipeline_l124_28) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; + end + if(when_Pipeline_l124_29) begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if(when_Pipeline_l124_30) begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if(when_Pipeline_l124_31) begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if(when_Pipeline_l124_32) begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if(when_Pipeline_l124_33) begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if(when_Pipeline_l124_34) begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if(when_Pipeline_l124_35) begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if(when_Pipeline_l124_36) begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if(when_Pipeline_l124_37) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; + end + if(when_Pipeline_l124_38) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; + end + if(when_Pipeline_l124_39) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; + end + if(when_Pipeline_l124_40) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; + end + if(when_Pipeline_l124_41) begin + decode_to_execute_RS1 <= _zz_decode_SRC1; + end + if(when_Pipeline_l124_42) begin + decode_to_execute_RS2 <= _zz_decode_SRC2_1; + end + if(when_Pipeline_l124_43) begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if(when_Pipeline_l124_44) begin + decode_to_execute_SRC1 <= decode_SRC1; + end + if(when_Pipeline_l124_45) begin + decode_to_execute_SRC2 <= decode_SRC2; + end + if(when_Pipeline_l124_46) begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if(when_Pipeline_l124_47) begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if(when_Pipeline_l124_48) begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if(when_Pipeline_l124_49) begin + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; + end + if(when_Pipeline_l124_50) begin + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; + end + if(when_Pipeline_l124_51) begin + execute_to_memory_MEMORY_VIRTUAL_ADDRESS <= execute_MEMORY_VIRTUAL_ADDRESS; + end + if(when_Pipeline_l124_52) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; + end + if(when_Pipeline_l124_53) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; + end + if(when_Pipeline_l124_54) begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if(when_Pipeline_l124_55) begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if(when_Pipeline_l124_56) begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if(when_Pipeline_l124_57) begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if(when_Pipeline_l124_58) begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if(when_Pipeline_l124_59) begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if(when_Pipeline_l124_60) begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if(when_Pipeline_l124_61) begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if(when_Pipeline_l124_62) begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if(when_Fetcher_l401) begin + _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst <= IBusCachedPlugin_injectionPort_payload; + end + if(when_CsrPlugin_l1277) begin + execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); + end + if(when_CsrPlugin_l1277_1) begin + execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); + end + if(when_CsrPlugin_l1277_2) begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if(when_CsrPlugin_l1277_3) begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if(when_CsrPlugin_l1277_4) begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if(when_CsrPlugin_l1277_5) begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if(when_CsrPlugin_l1277_6) begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if(when_CsrPlugin_l1277_7) begin + execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); + end + if(when_CsrPlugin_l1277_8) begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if(when_CsrPlugin_l1277_9) begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; + end + end + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; + end + end + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; + end + end + if(execute_CsrPlugin_csr_832) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; + end + end + end + + always @(posedge io_systemClk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready) begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); + if(writeBack_arbitration_isValid) begin + DebugPlugin_busReadDataReg <= _zz_decode_RS2_2; + end + _zz_when_DebugPlugin_l244 <= debug_bus_cmd_payload_address[2]; + if(when_DebugPlugin_l295) begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @(posedge io_systemClk) begin + if(debugCd_logic_outputReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_debugUsed <= 1'b0; + DebugPlugin_disableEbreak <= 1'b0; + end else begin + if(when_DebugPlugin_l225) begin + DebugPlugin_godmode <= 1'b1; + end + if(debug_bus_cmd_valid) begin + DebugPlugin_debugUsed <= 1'b1; + end + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l267) + 6'h0 : begin + if(debug_bus_cmd_payload_wr) begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(when_DebugPlugin_l271) begin + DebugPlugin_resetIt <= 1'b1; + end + if(when_DebugPlugin_l271_1) begin + DebugPlugin_resetIt <= 1'b0; + end + if(when_DebugPlugin_l272) begin + DebugPlugin_haltIt <= 1'b1; + end + if(when_DebugPlugin_l272_1) begin + DebugPlugin_haltIt <= 1'b0; + end + if(when_DebugPlugin_l273) begin + DebugPlugin_haltedByBreak <= 1'b0; + end + if(when_DebugPlugin_l274) begin + DebugPlugin_godmode <= 1'b0; + end + if(when_DebugPlugin_l275) begin + DebugPlugin_disableEbreak <= 1'b1; + end + if(when_DebugPlugin_l275_1) begin + DebugPlugin_disableEbreak <= 1'b0; + end + end + end + default : begin + end + endcase + end + if(when_DebugPlugin_l295) begin + if(when_DebugPlugin_l298) begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; + end + end + if(when_DebugPlugin_l311) begin + if(decode_arbitration_isValid) begin + DebugPlugin_haltIt <= 1'b1; + end + end + end + end + + +endmodule + +module BufferCC_3_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_dataIn, + output io_dataOut, + input io_systemClk, + input debugCd_logic_outputReset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge io_systemClk or posedge debugCd_logic_outputReset) begin + if(debugCd_logic_outputReset) begin + buffers_0 <= 1'b1; + buffers_1 <= 1'b1; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module BufferCC_2_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_dataIn, + output io_dataOut, + input io_systemClk, + input io_asyncReset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge io_systemClk or posedge io_asyncReset) begin + if(io_asyncReset) begin + buffers_0 <= 1'b1; + buffers_1 <= 1'b1; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module StreamFifo_3_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_push_valid, + output io_push_ready, + input [7:0] io_push_payload_data, + output io_pop_valid, + input io_pop_ready, + output [7:0] io_pop_payload_data, + input io_flush, + output [8:0] io_occupancy, + output [8:0] io_availability, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [7:0] _zz_logic_ram_port0; + wire [7:0] _zz_logic_pushPtr_valueNext; + wire [0:0] _zz_logic_pushPtr_valueNext_1; + wire [7:0] _zz_logic_popPtr_valueNext; + wire [0:0] _zz_logic_popPtr_valueNext_1; + wire _zz_logic_ram_port; + wire _zz_io_pop_payload_data; + wire [7:0] _zz_io_availability; + reg _zz_1; + reg logic_pushPtr_willIncrement; + reg logic_pushPtr_willClear; + reg [7:0] logic_pushPtr_valueNext; + reg [7:0] logic_pushPtr_value; + wire logic_pushPtr_willOverflowIfInc; + wire logic_pushPtr_willOverflow; + reg logic_popPtr_willIncrement; + reg logic_popPtr_willClear; + reg [7:0] logic_popPtr_valueNext; + reg [7:0] logic_popPtr_value; + wire logic_popPtr_willOverflowIfInc; + wire logic_popPtr_willOverflow; + wire logic_ptrMatch; + reg logic_risingOccupancy; + wire logic_pushing; + wire logic_popping; + wire logic_empty; + wire logic_full; + reg _zz_io_pop_valid; + wire when_Stream_l1037; + wire [7:0] logic_ptrDif; + reg [7:0] logic_ram [0:255]; + + assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; + assign _zz_logic_pushPtr_valueNext = {7'd0, _zz_logic_pushPtr_valueNext_1}; + assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; + assign _zz_logic_popPtr_valueNext = {7'd0, _zz_logic_popPtr_valueNext_1}; + assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); + assign _zz_io_pop_payload_data = 1'b1; + always @(posedge io_systemClk) begin + if(_zz_io_pop_payload_data) begin + _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_1) begin + logic_ram[logic_pushPtr_value] <= io_push_payload_data; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_pushing) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willIncrement = 1'b0; + if(logic_pushing) begin + logic_pushPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willClear = 1'b0; + if(io_flush) begin + logic_pushPtr_willClear = 1'b1; + end + end + + assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 8'hff); + assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); + always @(*) begin + logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); + if(logic_pushPtr_willClear) begin + logic_pushPtr_valueNext = 8'h0; + end + end + + always @(*) begin + logic_popPtr_willIncrement = 1'b0; + if(logic_popping) begin + logic_popPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_popPtr_willClear = 1'b0; + if(io_flush) begin + logic_popPtr_willClear = 1'b1; + end + end + + assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 8'hff); + assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); + always @(*) begin + logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); + if(logic_popPtr_willClear) begin + logic_popPtr_valueNext = 8'h0; + end + end + + assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); + assign logic_pushing = (io_push_valid && io_push_ready); + assign logic_popping = (io_pop_valid && io_pop_ready); + assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); + assign logic_full = (logic_ptrMatch && logic_risingOccupancy); + assign io_push_ready = (! logic_full); + assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); + assign io_pop_payload_data = _zz_logic_ram_port0[7 : 0]; + assign when_Stream_l1037 = (logic_pushing != logic_popping); + assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); + assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; + assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + logic_pushPtr_value <= 8'h0; + logic_popPtr_value <= 8'h0; + logic_risingOccupancy <= 1'b0; + _zz_io_pop_valid <= 1'b0; + end else begin + logic_pushPtr_value <= logic_pushPtr_valueNext; + logic_popPtr_value <= logic_popPtr_valueNext; + _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); + if(when_Stream_l1037) begin + logic_risingOccupancy <= logic_pushing; + end + if(io_flush) begin + logic_risingOccupancy <= 1'b0; + end + end + end + + +endmodule + +module StreamFifo_2_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_push_valid, + output io_push_ready, + input io_push_payload_kind, + input io_push_payload_read, + input io_push_payload_write, + input [7:0] io_push_payload_data, + output io_pop_valid, + input io_pop_ready, + output io_pop_payload_kind, + output io_pop_payload_read, + output io_pop_payload_write, + output [7:0] io_pop_payload_data, + input io_flush, + output [8:0] io_occupancy, + output [8:0] io_availability, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [10:0] _zz_logic_ram_port0; + wire [7:0] _zz_logic_pushPtr_valueNext; + wire [0:0] _zz_logic_pushPtr_valueNext_1; + wire [7:0] _zz_logic_popPtr_valueNext; + wire [0:0] _zz_logic_popPtr_valueNext_1; + wire _zz_logic_ram_port; + wire _zz__zz_io_pop_payload_kind; + wire [10:0] _zz_logic_ram_port_1; + wire [7:0] _zz_io_availability; + reg _zz_1; + reg logic_pushPtr_willIncrement; + reg logic_pushPtr_willClear; + reg [7:0] logic_pushPtr_valueNext; + reg [7:0] logic_pushPtr_value; + wire logic_pushPtr_willOverflowIfInc; + wire logic_pushPtr_willOverflow; + reg logic_popPtr_willIncrement; + reg logic_popPtr_willClear; + reg [7:0] logic_popPtr_valueNext; + reg [7:0] logic_popPtr_value; + wire logic_popPtr_willOverflowIfInc; + wire logic_popPtr_willOverflow; + wire logic_ptrMatch; + reg logic_risingOccupancy; + wire logic_pushing; + wire logic_popping; + wire logic_empty; + wire logic_full; + reg _zz_io_pop_valid; + wire [10:0] _zz_io_pop_payload_kind; + wire when_Stream_l1037; + wire [7:0] logic_ptrDif; + reg [10:0] logic_ram [0:255]; + + assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; + assign _zz_logic_pushPtr_valueNext = {7'd0, _zz_logic_pushPtr_valueNext_1}; + assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; + assign _zz_logic_popPtr_valueNext = {7'd0, _zz_logic_popPtr_valueNext_1}; + assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); + assign _zz__zz_io_pop_payload_kind = 1'b1; + assign _zz_logic_ram_port_1 = {io_push_payload_data,{io_push_payload_write,{io_push_payload_read,io_push_payload_kind}}}; + always @(posedge io_systemClk) begin + if(_zz__zz_io_pop_payload_kind) begin + _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_1) begin + logic_ram[logic_pushPtr_value] <= _zz_logic_ram_port_1; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_pushing) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willIncrement = 1'b0; + if(logic_pushing) begin + logic_pushPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willClear = 1'b0; + if(io_flush) begin + logic_pushPtr_willClear = 1'b1; + end + end + + assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 8'hff); + assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); + always @(*) begin + logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); + if(logic_pushPtr_willClear) begin + logic_pushPtr_valueNext = 8'h0; + end + end + + always @(*) begin + logic_popPtr_willIncrement = 1'b0; + if(logic_popping) begin + logic_popPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_popPtr_willClear = 1'b0; + if(io_flush) begin + logic_popPtr_willClear = 1'b1; + end + end + + assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 8'hff); + assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); + always @(*) begin + logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); + if(logic_popPtr_willClear) begin + logic_popPtr_valueNext = 8'h0; + end + end + + assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); + assign logic_pushing = (io_push_valid && io_push_ready); + assign logic_popping = (io_pop_valid && io_pop_ready); + assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); + assign logic_full = (logic_ptrMatch && logic_risingOccupancy); + assign io_push_ready = (! logic_full); + assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); + assign _zz_io_pop_payload_kind = _zz_logic_ram_port0; + assign io_pop_payload_kind = _zz_io_pop_payload_kind[0]; + assign io_pop_payload_read = _zz_io_pop_payload_kind[1]; + assign io_pop_payload_write = _zz_io_pop_payload_kind[2]; + assign io_pop_payload_data = _zz_io_pop_payload_kind[10 : 3]; + assign when_Stream_l1037 = (logic_pushing != logic_popping); + assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); + assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; + assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + logic_pushPtr_value <= 8'h0; + logic_popPtr_value <= 8'h0; + logic_risingOccupancy <= 1'b0; + _zz_io_pop_valid <= 1'b0; + end else begin + logic_pushPtr_value <= logic_pushPtr_valueNext; + logic_popPtr_value <= logic_popPtr_valueNext; + _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); + if(when_Stream_l1037) begin + logic_risingOccupancy <= logic_pushing; + end + if(io_flush) begin + logic_risingOccupancy <= 1'b0; + end + end + end + + +endmodule + +module TopLevel_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_config_kind_cpol, + input io_config_kind_cpha, + input [11:0] io_config_sclkToogle, + input [1:0] io_config_mod, + input [0:0] io_config_ss_activeHigh, + input [11:0] io_config_ss_setup, + input [11:0] io_config_ss_hold, + input [11:0] io_config_ss_disable, + input io_cmd_valid, + output reg io_cmd_ready, + input io_cmd_payload_kind, + input io_cmd_payload_read, + input io_cmd_payload_write, + input [7:0] io_cmd_payload_data, + output io_rsp_valid, + output [7:0] io_rsp_payload_data, + output [0:0] io_spi_sclk_write, + output reg io_spi_data_0_writeEnable, + input [0:0] io_spi_data_0_read, + output reg [0:0] io_spi_data_0_write, + output reg io_spi_data_1_writeEnable, + input [0:0] io_spi_data_1_read, + output reg [0:0] io_spi_data_1_write, + output reg io_spi_data_2_writeEnable, + input [0:0] io_spi_data_2_read, + output reg [0:0] io_spi_data_2_write, + output reg io_spi_data_3_writeEnable, + input [0:0] io_spi_data_3_read, + output reg [0:0] io_spi_data_3_write, + output [0:0] io_spi_ss, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [0:0] _zz_outputPhy_dataWrite_3; + wire [2:0] _zz_outputPhy_dataWrite_4; + wire [2:0] _zz_outputPhy_dataWrite_5; + reg [1:0] _zz_outputPhy_dataWrite_6; + wire [1:0] _zz_outputPhy_dataWrite_7; + wire [2:0] _zz_outputPhy_dataWrite_8; + reg [3:0] _zz_outputPhy_dataWrite_9; + wire [0:0] _zz_outputPhy_dataWrite_10; + wire [2:0] _zz_outputPhy_dataWrite_11; + wire [3:0] _zz_inputPhy_dataRead; + wire [3:0] _zz_inputPhy_dataRead_1; + wire [3:0] _zz_inputPhy_dataRead_2; + wire [3:0] _zz_inputPhy_dataRead_3; + wire [3:0] _zz_inputPhy_dataRead_4; + wire [3:0] _zz_inputPhy_dataRead_5; + wire [3:0] _zz_inputPhy_dataRead_6; + wire [8:0] _zz_inputPhy_bufferNext; + wire [10:0] _zz_inputPhy_bufferNext_1; + reg [11:0] timer_counter; + reg timer_reset; + wire timer_ss_setupHit; + wire timer_ss_holdHit; + wire timer_ss_disableHit; + wire timer_sclkToogleHit; + reg fsm_state; + reg [2:0] fsm_counter; + reg [2:0] _zz_fsm_counterPlus; + wire [2:0] fsm_counterPlus; + reg fsm_fastRate; + reg fsm_isDdr; + reg [2:0] fsm_counterMax; + reg fsm_lateSampling; + reg fsm_readFill; + reg fsm_readDone; + reg [0:0] fsm_ss; + wire when_SpiXdrMasterCtrl_l739; + wire when_SpiXdrMasterCtrl_l742; + wire when_SpiXdrMasterCtrl_l749; + wire when_SpiXdrMasterCtrl_l751; + wire when_SpiXdrMasterCtrl_l758; + wire when_SpiXdrMasterCtrl_l764; + wire when_SpiXdrMasterCtrl_l781; + reg [0:0] outputPhy_sclkWrite; + wire [0:0] _zz_io_spi_sclk_write; + wire when_SpiXdrMasterCtrl_l796; + reg [3:0] outputPhy_dataWrite; + reg [2:0] outputPhy_widthSel; + reg [2:0] outputPhy_offset; + wire [7:0] _zz_outputPhy_dataWrite; + wire [7:0] _zz_outputPhy_dataWrite_1; + wire [7:0] _zz_outputPhy_dataWrite_2; + wire when_SpiXdrMasterCtrl_l839; + wire when_SpiXdrMasterCtrl_l839_1; + reg [1:0] io_config_mod_delay_1; + reg [1:0] inputPhy_mod; + reg fsm_readFill_delay_1; + reg inputPhy_readFill; + reg fsm_readDone_delay_1; + reg inputPhy_readDone; + reg [6:0] inputPhy_buffer; + reg [7:0] inputPhy_bufferNext; + reg [2:0] inputPhy_widthSel; + wire [3:0] inputPhy_dataWrite; + reg [3:0] inputPhy_dataRead; + reg fsm_state_delay_1; + reg fsm_state_delay_2; + wire when_SpiXdrMasterCtrl_l861; + reg [3:0] inputPhy_dataReadBuffer; + + assign _zz_outputPhy_dataWrite_4 = (_zz_outputPhy_dataWrite_5 >>> 0); + assign _zz_outputPhy_dataWrite_5 = (outputPhy_offset - fsm_counter); + assign _zz_outputPhy_dataWrite_7 = (_zz_outputPhy_dataWrite_8 >>> 1); + assign _zz_outputPhy_dataWrite_8 = (outputPhy_offset - fsm_counter); + assign _zz_outputPhy_dataWrite_10 = (_zz_outputPhy_dataWrite_11 >>> 2); + assign _zz_outputPhy_dataWrite_11 = (outputPhy_offset - fsm_counter); + assign _zz_inputPhy_dataRead = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_1 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_2 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_3 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_4 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_5 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_6 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[1 : 0]}; + assign _zz_inputPhy_bufferNext_1 = {inputPhy_buffer,inputPhy_dataRead[3 : 0]}; + always @(*) begin + case(_zz_outputPhy_dataWrite_4) + 3'b000 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[0 : 0]; + 3'b001 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[1 : 1]; + 3'b010 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[2 : 2]; + 3'b011 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[3 : 3]; + 3'b100 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[4 : 4]; + 3'b101 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[5 : 5]; + 3'b110 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[6 : 6]; + default : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[7 : 7]; + endcase + end + + always @(*) begin + case(_zz_outputPhy_dataWrite_7) + 2'b00 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[1 : 0]; + 2'b01 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[3 : 2]; + 2'b10 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[5 : 4]; + default : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[7 : 6]; + endcase + end + + always @(*) begin + case(_zz_outputPhy_dataWrite_10) + 1'b0 : _zz_outputPhy_dataWrite_9 = _zz_outputPhy_dataWrite_2[3 : 0]; + default : _zz_outputPhy_dataWrite_9 = _zz_outputPhy_dataWrite_2[7 : 4]; + endcase + end + + always @(*) begin + timer_reset = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l739) begin + timer_reset = timer_sclkToogleHit; + end else begin + if(!when_SpiXdrMasterCtrl_l758) begin + if(when_SpiXdrMasterCtrl_l764) begin + if(timer_ss_holdHit) begin + timer_reset = 1'b1; + end + end + end + end + end + if(when_SpiXdrMasterCtrl_l781) begin + timer_reset = 1'b1; + end + end + + assign timer_ss_setupHit = (timer_counter == io_config_ss_setup); + assign timer_ss_holdHit = (timer_counter == io_config_ss_hold); + assign timer_ss_disableHit = (timer_counter == io_config_ss_disable); + assign timer_sclkToogleHit = (timer_counter == io_config_sclkToogle); + always @(*) begin + _zz_fsm_counterPlus = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + _zz_fsm_counterPlus = 3'b001; + end + 2'b01 : begin + _zz_fsm_counterPlus = 3'b010; + end + 2'b10 : begin + _zz_fsm_counterPlus = 3'b100; + end + default : begin + end + endcase + end + + assign fsm_counterPlus = (fsm_counter + _zz_fsm_counterPlus); + always @(*) begin + fsm_fastRate = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_fastRate = 1'b0; + end + 2'b01 : begin + fsm_fastRate = 1'b0; + end + 2'b10 : begin + fsm_fastRate = 1'b0; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_isDdr = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_isDdr = 1'b0; + end + 2'b01 : begin + fsm_isDdr = 1'b0; + end + 2'b10 : begin + fsm_isDdr = 1'b0; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_counterMax = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + fsm_counterMax = 3'b111; + end + 2'b01 : begin + fsm_counterMax = 3'b110; + end + 2'b10 : begin + fsm_counterMax = 3'b100; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_lateSampling = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_lateSampling = 1'b1; + end + 2'b01 : begin + fsm_lateSampling = 1'b1; + end + 2'b10 : begin + fsm_lateSampling = 1'b1; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_readFill = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l739) begin + if(when_SpiXdrMasterCtrl_l742) begin + fsm_readFill = 1'b1; + end + end + end + end + + always @(*) begin + fsm_readDone = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l739) begin + if(when_SpiXdrMasterCtrl_l742) begin + fsm_readDone = (io_cmd_payload_read && (fsm_counter == fsm_counterMax)); + end + end + end + end + + assign io_spi_ss = (~ (fsm_ss ^ io_config_ss_activeHigh)); + always @(*) begin + io_cmd_ready = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l739) begin + if(when_SpiXdrMasterCtrl_l749) begin + if(when_SpiXdrMasterCtrl_l751) begin + io_cmd_ready = 1'b1; + end + end + end else begin + if(when_SpiXdrMasterCtrl_l758) begin + if(timer_ss_setupHit) begin + io_cmd_ready = 1'b1; + end + end else begin + if(!when_SpiXdrMasterCtrl_l764) begin + if(timer_ss_disableHit) begin + io_cmd_ready = 1'b1; + end + end + end + end + end + end + + assign when_SpiXdrMasterCtrl_l739 = (! io_cmd_payload_kind); + assign when_SpiXdrMasterCtrl_l742 = ((timer_sclkToogleHit && (((! fsm_state) ^ fsm_lateSampling) || fsm_isDdr)) || fsm_fastRate); + assign when_SpiXdrMasterCtrl_l749 = ((timer_sclkToogleHit && (fsm_state || fsm_isDdr)) || fsm_fastRate); + assign when_SpiXdrMasterCtrl_l751 = (fsm_counter == fsm_counterMax); + assign when_SpiXdrMasterCtrl_l758 = io_cmd_payload_data[7]; + assign when_SpiXdrMasterCtrl_l764 = (! fsm_state); + assign when_SpiXdrMasterCtrl_l781 = ((! io_cmd_valid) || io_cmd_ready); + always @(*) begin + outputPhy_sclkWrite = 1'b0; + if(when_SpiXdrMasterCtrl_l796) begin + case(io_config_mod) + 2'b00 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + 2'b01 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + 2'b10 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + default : begin + end + endcase + end + end + + assign _zz_io_spi_sclk_write[0] = io_config_kind_cpol; + assign io_spi_sclk_write = (outputPhy_sclkWrite ^ _zz_io_spi_sclk_write); + assign when_SpiXdrMasterCtrl_l796 = (io_cmd_valid && (! io_cmd_payload_kind)); + always @(*) begin + outputPhy_widthSel = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + outputPhy_widthSel = 3'b000; + end + 2'b01 : begin + outputPhy_widthSel = 3'b001; + end + 2'b10 : begin + outputPhy_widthSel = 3'b010; + end + default : begin + end + endcase + end + + always @(*) begin + outputPhy_offset = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + outputPhy_offset = 3'b111; + end + 2'b01 : begin + outputPhy_offset = 3'b111; + end + 2'b10 : begin + outputPhy_offset = 3'b111; + end + default : begin + end + endcase + end + + always @(*) begin + outputPhy_dataWrite = 4'bxxxx; + case(outputPhy_widthSel) + 3'b000 : begin + outputPhy_dataWrite[0 : 0] = _zz_outputPhy_dataWrite_3; + end + 3'b001 : begin + outputPhy_dataWrite[1 : 0] = _zz_outputPhy_dataWrite_6; + end + 3'b010 : begin + outputPhy_dataWrite[3 : 0] = _zz_outputPhy_dataWrite_9; + end + default : begin + end + endcase + end + + assign _zz_outputPhy_dataWrite = io_cmd_payload_data; + assign _zz_outputPhy_dataWrite_1 = io_cmd_payload_data; + assign _zz_outputPhy_dataWrite_2 = io_cmd_payload_data; + always @(*) begin + io_spi_data_0_writeEnable = 1'b0; + case(io_config_mod) + 2'b00 : begin + io_spi_data_0_writeEnable = 1'b1; + end + 2'b01 : begin + if(when_SpiXdrMasterCtrl_l839) begin + io_spi_data_0_writeEnable = 1'b1; + end + end + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l839_1) begin + io_spi_data_0_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_1_writeEnable = 1'b0; + case(io_config_mod) + 2'b01 : begin + if(when_SpiXdrMasterCtrl_l839) begin + io_spi_data_1_writeEnable = 1'b1; + end + end + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l839_1) begin + io_spi_data_1_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_2_writeEnable = 1'b0; + case(io_config_mod) + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l839_1) begin + io_spi_data_2_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_3_writeEnable = 1'b0; + case(io_config_mod) + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l839_1) begin + io_spi_data_3_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_0_write = 1'bx; + case(io_config_mod) + 2'b00 : begin + io_spi_data_0_write[0] = (outputPhy_dataWrite[0] || (! (io_cmd_valid && io_cmd_payload_write))); + end + 2'b01 : begin + io_spi_data_0_write[0] = outputPhy_dataWrite[0]; + end + 2'b10 : begin + io_spi_data_0_write[0] = outputPhy_dataWrite[0]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_1_write = 1'bx; + case(io_config_mod) + 2'b01 : begin + io_spi_data_1_write[0] = outputPhy_dataWrite[1]; + end + 2'b10 : begin + io_spi_data_1_write[0] = outputPhy_dataWrite[1]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_2_write = 1'bx; + case(io_config_mod) + 2'b10 : begin + io_spi_data_2_write[0] = outputPhy_dataWrite[2]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_3_write = 1'bx; + case(io_config_mod) + 2'b10 : begin + io_spi_data_3_write[0] = outputPhy_dataWrite[3]; + end + default : begin + end + endcase + end + + assign when_SpiXdrMasterCtrl_l839 = (io_cmd_valid && io_cmd_payload_write); + assign when_SpiXdrMasterCtrl_l839_1 = (io_cmd_valid && io_cmd_payload_write); + always @(*) begin + inputPhy_bufferNext = 8'bxxxxxxxx; + case(inputPhy_widthSel) + 3'b000 : begin + inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[0 : 0]}; + end + 3'b001 : begin + inputPhy_bufferNext = _zz_inputPhy_bufferNext[7:0]; + end + 3'b010 : begin + inputPhy_bufferNext = _zz_inputPhy_bufferNext_1[7:0]; + end + default : begin + end + endcase + end + + always @(*) begin + inputPhy_widthSel = 3'bxxx; + case(inputPhy_mod) + 2'b00 : begin + inputPhy_widthSel = 3'b000; + end + 2'b01 : begin + inputPhy_widthSel = 3'b001; + end + 2'b10 : begin + inputPhy_widthSel = 3'b010; + end + default : begin + end + endcase + end + + assign when_SpiXdrMasterCtrl_l861 = (! fsm_state_delay_2); + always @(*) begin + inputPhy_dataRead = 4'bxxxx; + case(inputPhy_mod) + 2'b00 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead[1]; + end + 2'b01 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead_1[0]; + inputPhy_dataRead[1] = _zz_inputPhy_dataRead_2[1]; + end + 2'b10 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead_3[0]; + inputPhy_dataRead[1] = _zz_inputPhy_dataRead_4[1]; + inputPhy_dataRead[2] = _zz_inputPhy_dataRead_5[2]; + inputPhy_dataRead[3] = _zz_inputPhy_dataRead_6[3]; + end + default : begin + end + endcase + end + + assign io_rsp_valid = inputPhy_readDone; + assign io_rsp_payload_data = inputPhy_bufferNext; + always @(posedge io_systemClk) begin + timer_counter <= (timer_counter + 12'h001); + if(timer_reset) begin + timer_counter <= 12'h0; + end + io_config_mod_delay_1 <= io_config_mod; + inputPhy_mod <= io_config_mod_delay_1; + fsm_state_delay_1 <= fsm_state; + fsm_state_delay_2 <= fsm_state_delay_1; + if(when_SpiXdrMasterCtrl_l861) begin + inputPhy_dataReadBuffer <= {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + end + case(inputPhy_widthSel) + 3'b000 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + 3'b001 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + 3'b010 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + default : begin + end + endcase + end + + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + fsm_state <= 1'b0; + fsm_counter <= 3'b000; + fsm_ss <= 1'b0; + fsm_readFill_delay_1 <= 1'b0; + inputPhy_readFill <= 1'b0; + fsm_readDone_delay_1 <= 1'b0; + inputPhy_readDone <= 1'b0; + end else begin + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l739) begin + if(timer_sclkToogleHit) begin + fsm_state <= (! fsm_state); + end + if(when_SpiXdrMasterCtrl_l749) begin + fsm_counter <= fsm_counterPlus; + if(when_SpiXdrMasterCtrl_l751) begin + fsm_state <= 1'b0; + end + end + end else begin + if(when_SpiXdrMasterCtrl_l758) begin + fsm_ss[0] <= 1'b1; + end else begin + if(when_SpiXdrMasterCtrl_l764) begin + if(timer_ss_holdHit) begin + fsm_state <= 1'b1; + end + end else begin + fsm_ss[0] <= 1'b0; + end + end + end + end + if(when_SpiXdrMasterCtrl_l781) begin + fsm_state <= 1'b0; + fsm_counter <= 3'b000; + end + fsm_readFill_delay_1 <= fsm_readFill; + inputPhy_readFill <= fsm_readFill_delay_1; + fsm_readDone_delay_1 <= fsm_readDone; + inputPhy_readDone <= fsm_readDone_delay_1; + end + end + + +endmodule + +//StreamFifo_b62b14ffe6bb44e5a817b8d08e286c6b replaced by StreamFifo_b62b14ffe6bb44e5a817b8d08e286c6b + +module StreamFifo_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_push_valid, + output io_push_ready, + input [7:0] io_push_payload, + output io_pop_valid, + input io_pop_ready, + output [7:0] io_pop_payload, + input io_flush, + output [7:0] io_occupancy, + output [7:0] io_availability, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [7:0] _zz_logic_ram_port0; + wire [6:0] _zz_logic_pushPtr_valueNext; + wire [0:0] _zz_logic_pushPtr_valueNext_1; + wire [6:0] _zz_logic_popPtr_valueNext; + wire [0:0] _zz_logic_popPtr_valueNext_1; + wire _zz_logic_ram_port; + wire _zz_io_pop_payload; + wire [6:0] _zz_io_availability; + reg _zz_1; + reg logic_pushPtr_willIncrement; + reg logic_pushPtr_willClear; + reg [6:0] logic_pushPtr_valueNext; + reg [6:0] logic_pushPtr_value; + wire logic_pushPtr_willOverflowIfInc; + wire logic_pushPtr_willOverflow; + reg logic_popPtr_willIncrement; + reg logic_popPtr_willClear; + reg [6:0] logic_popPtr_valueNext; + reg [6:0] logic_popPtr_value; + wire logic_popPtr_willOverflowIfInc; + wire logic_popPtr_willOverflow; + wire logic_ptrMatch; + reg logic_risingOccupancy; + wire logic_pushing; + wire logic_popping; + wire logic_empty; + wire logic_full; + reg _zz_io_pop_valid; + wire when_Stream_l1037; + wire [6:0] logic_ptrDif; + reg [7:0] logic_ram [0:127]; + + assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; + assign _zz_logic_pushPtr_valueNext = {6'd0, _zz_logic_pushPtr_valueNext_1}; + assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; + assign _zz_logic_popPtr_valueNext = {6'd0, _zz_logic_popPtr_valueNext_1}; + assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); + assign _zz_io_pop_payload = 1'b1; + always @(posedge io_systemClk) begin + if(_zz_io_pop_payload) begin + _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_1) begin + logic_ram[logic_pushPtr_value] <= io_push_payload; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_pushing) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willIncrement = 1'b0; + if(logic_pushing) begin + logic_pushPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willClear = 1'b0; + if(io_flush) begin + logic_pushPtr_willClear = 1'b1; + end + end + + assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 7'h7f); + assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); + always @(*) begin + logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); + if(logic_pushPtr_willClear) begin + logic_pushPtr_valueNext = 7'h0; + end + end + + always @(*) begin + logic_popPtr_willIncrement = 1'b0; + if(logic_popping) begin + logic_popPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_popPtr_willClear = 1'b0; + if(io_flush) begin + logic_popPtr_willClear = 1'b1; + end + end + + assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 7'h7f); + assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); + always @(*) begin + logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); + if(logic_popPtr_willClear) begin + logic_popPtr_valueNext = 7'h0; + end + end + + assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); + assign logic_pushing = (io_push_valid && io_push_ready); + assign logic_popping = (io_pop_valid && io_pop_ready); + assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); + assign logic_full = (logic_ptrMatch && logic_risingOccupancy); + assign io_push_ready = (! logic_full); + assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); + assign io_pop_payload = _zz_logic_ram_port0; + assign when_Stream_l1037 = (logic_pushing != logic_popping); + assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); + assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; + assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + logic_pushPtr_value <= 7'h0; + logic_popPtr_value <= 7'h0; + logic_risingOccupancy <= 1'b0; + _zz_io_pop_valid <= 1'b0; + end else begin + logic_pushPtr_value <= logic_pushPtr_valueNext; + logic_popPtr_value <= logic_popPtr_valueNext; + _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); + if(when_Stream_l1037) begin + logic_risingOccupancy <= logic_pushing; + end + if(io_flush) begin + logic_risingOccupancy <= 1'b0; + end + end + end + + +endmodule + +module UartCtrl_b62b14ffe6bb44e5a817b8d08e286c6b ( + input [2:0] io_config_frame_dataLength, + input [0:0] io_config_frame_stop, + input [1:0] io_config_frame_parity, + input [19:0] io_config_clockDivider, + input io_write_valid, + output reg io_write_ready, + input [7:0] io_write_payload, + output io_read_valid, + input io_read_ready, + output [7:0] io_read_payload, + output io_uart_txd, + input io_uart_rxd, + output io_readError, + input io_writeBreak, + output io_readBreak, + input io_systemClk, + input systemCd_logic_outputReset +); + localparam UartStopType_ONE = 1'd0; + localparam UartStopType_TWO = 1'd1; + localparam UartParityType_NONE = 2'd0; + localparam UartParityType_EVEN = 2'd1; + localparam UartParityType_ODD = 2'd2; + + wire tx_io_write_ready; + wire tx_io_txd; + wire rx_io_read_valid; + wire [7:0] rx_io_read_payload; + wire rx_io_rts; + wire rx_io_error; + wire rx_io_break; + reg [19:0] clockDivider_counter; + wire clockDivider_tick; + reg clockDivider_tickReg; + reg io_write_thrown_valid; + wire io_write_thrown_ready; + wire [7:0] io_write_thrown_payload; + `ifndef SYNTHESIS + reg [23:0] io_config_frame_stop_string; + reg [31:0] io_config_frame_parity_string; + `endif + + + UartCtrlTx_b62b14ffe6bb44e5a817b8d08e286c6b tx ( + .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i + .io_configFrame_stop (io_config_frame_stop ), //i + .io_configFrame_parity (io_config_frame_parity[1:0] ), //i + .io_samplingTick (clockDivider_tickReg ), //i + .io_write_valid (io_write_thrown_valid ), //i + .io_write_ready (tx_io_write_ready ), //o + .io_write_payload (io_write_thrown_payload[7:0] ), //i + .io_cts (1'b0 ), //i + .io_txd (tx_io_txd ), //o + .io_break (io_writeBreak ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + UartCtrlRx_b62b14ffe6bb44e5a817b8d08e286c6b rx ( + .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i + .io_configFrame_stop (io_config_frame_stop ), //i + .io_configFrame_parity (io_config_frame_parity[1:0] ), //i + .io_samplingTick (clockDivider_tickReg ), //i + .io_read_valid (rx_io_read_valid ), //o + .io_read_ready (io_read_ready ), //i + .io_read_payload (rx_io_read_payload[7:0] ), //o + .io_rxd (io_uart_rxd ), //i + .io_rts (rx_io_rts ), //o + .io_error (rx_io_error ), //o + .io_break (rx_io_break ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_config_frame_stop) + UartStopType_ONE : io_config_frame_stop_string = "ONE"; + UartStopType_TWO : io_config_frame_stop_string = "TWO"; + default : io_config_frame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_config_frame_parity) + UartParityType_NONE : io_config_frame_parity_string = "NONE"; + UartParityType_EVEN : io_config_frame_parity_string = "EVEN"; + UartParityType_ODD : io_config_frame_parity_string = "ODD "; + default : io_config_frame_parity_string = "????"; + endcase + end + `endif + + assign clockDivider_tick = (clockDivider_counter == 20'h0); + always @(*) begin + io_write_thrown_valid = io_write_valid; + if(rx_io_break) begin + io_write_thrown_valid = 1'b0; + end + end + + always @(*) begin + io_write_ready = io_write_thrown_ready; + if(rx_io_break) begin + io_write_ready = 1'b1; + end + end + + assign io_write_thrown_payload = io_write_payload; + assign io_write_thrown_ready = tx_io_write_ready; + assign io_read_valid = rx_io_read_valid; + assign io_read_payload = rx_io_read_payload; + assign io_uart_txd = tx_io_txd; + assign io_readError = rx_io_error; + assign io_readBreak = rx_io_break; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + clockDivider_counter <= 20'h0; + clockDivider_tickReg <= 1'b0; + end else begin + clockDivider_tickReg <= clockDivider_tick; + clockDivider_counter <= (clockDivider_counter - 20'h00001); + if(clockDivider_tick) begin + clockDivider_counter <= io_config_clockDivider; + end + end + end + + +endmodule + +module StreamArbiter_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_inputs_0_valid, + output io_inputs_0_ready, + input io_inputs_0_payload_last, + input [0:0] io_inputs_0_payload_fragment_source, + input [0:0] io_inputs_0_payload_fragment_opcode, + input [31:0] io_inputs_0_payload_fragment_address, + input [5:0] io_inputs_0_payload_fragment_length, + input [31:0] io_inputs_0_payload_fragment_data, + input [3:0] io_inputs_0_payload_fragment_mask, + input [0:0] io_inputs_0_payload_fragment_context, + input io_inputs_1_valid, + output io_inputs_1_ready, + input io_inputs_1_payload_last, + input [0:0] io_inputs_1_payload_fragment_source, + input [0:0] io_inputs_1_payload_fragment_opcode, + input [31:0] io_inputs_1_payload_fragment_address, + input [5:0] io_inputs_1_payload_fragment_length, + input [31:0] io_inputs_1_payload_fragment_data, + input [3:0] io_inputs_1_payload_fragment_mask, + input [0:0] io_inputs_1_payload_fragment_context, + output io_output_valid, + input io_output_ready, + output io_output_payload_last, + output [0:0] io_output_payload_fragment_source, + output [0:0] io_output_payload_fragment_opcode, + output [31:0] io_output_payload_fragment_address, + output [5:0] io_output_payload_fragment_length, + output [31:0] io_output_payload_fragment_data, + output [3:0] io_output_payload_fragment_mask, + output [0:0] io_output_payload_fragment_context, + output [0:0] io_chosen, + output [1:0] io_chosenOH, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire [3:0] _zz__zz_maskProposal_0_2; + wire [3:0] _zz__zz_maskProposal_0_2_1; + wire [1:0] _zz__zz_maskProposal_0_2_2; + reg locked; + wire maskProposal_0; + wire maskProposal_1; + reg maskLocked_0; + reg maskLocked_1; + wire maskRouted_0; + wire maskRouted_1; + wire [1:0] _zz_maskProposal_0; + wire [3:0] _zz_maskProposal_0_1; + wire [3:0] _zz_maskProposal_0_2; + wire [1:0] _zz_maskProposal_0_3; + wire io_output_fire; + wire when_Stream_l621; + wire _zz_io_chosen; + + assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); + assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; + assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; + assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); + assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); + assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; + assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; + assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); + assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); + assign maskProposal_0 = _zz_maskProposal_0_3[0]; + assign maskProposal_1 = _zz_maskProposal_0_3[1]; + assign io_output_fire = (io_output_valid && io_output_ready); + assign when_Stream_l621 = (io_output_fire && io_output_payload_last); + assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); + assign io_output_payload_last = (maskRouted_0 ? io_inputs_0_payload_last : io_inputs_1_payload_last); + assign io_output_payload_fragment_source = (maskRouted_0 ? io_inputs_0_payload_fragment_source : io_inputs_1_payload_fragment_source); + assign io_output_payload_fragment_opcode = (maskRouted_0 ? io_inputs_0_payload_fragment_opcode : io_inputs_1_payload_fragment_opcode); + assign io_output_payload_fragment_address = (maskRouted_0 ? io_inputs_0_payload_fragment_address : io_inputs_1_payload_fragment_address); + assign io_output_payload_fragment_length = (maskRouted_0 ? io_inputs_0_payload_fragment_length : io_inputs_1_payload_fragment_length); + assign io_output_payload_fragment_data = (maskRouted_0 ? io_inputs_0_payload_fragment_data : io_inputs_1_payload_fragment_data); + assign io_output_payload_fragment_mask = (maskRouted_0 ? io_inputs_0_payload_fragment_mask : io_inputs_1_payload_fragment_mask); + assign io_output_payload_fragment_context = (maskRouted_0 ? io_inputs_0_payload_fragment_context : io_inputs_1_payload_fragment_context); + assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); + assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); + assign io_chosenOH = {maskRouted_1,maskRouted_0}; + assign _zz_io_chosen = io_chosenOH[1]; + assign io_chosen = _zz_io_chosen; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + locked <= 1'b0; + maskLocked_0 <= 1'b0; + maskLocked_1 <= 1'b1; + end else begin + if(io_output_valid) begin + maskLocked_0 <= maskRouted_0; + maskLocked_1 <= maskRouted_1; + end + if(io_output_valid) begin + locked <= 1'b1; + end + if(when_Stream_l621) begin + locked <= 1'b0; + end + end + end + + +endmodule + +module FlowCCByToggle_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_input_valid, + input io_input_payload_last, + input [0:0] io_input_payload_fragment, + output io_output_valid, + output io_output_payload_last, + output [0:0] io_output_payload_fragment, + input jtagCtrl_tck, + input io_systemClk, + input debugCd_logic_outputReset +); + + wire inputArea_target_buffercc_io_dataOut; + reg inputArea_target; + reg inputArea_data_last; + reg [0:0] inputArea_data_fragment; + wire outputArea_target; + reg outputArea_hit; + wire outputArea_flow_valid; + wire outputArea_flow_payload_last; + wire [0:0] outputArea_flow_payload_fragment; + reg outputArea_flow_m2sPipe_valid; + reg outputArea_flow_m2sPipe_payload_last; + reg [0:0] outputArea_flow_m2sPipe_payload_fragment; + + BufferCC_1_b62b14ffe6bb44e5a817b8d08e286c6b inputArea_target_buffercc ( + .io_dataIn (inputArea_target ), //i + .io_dataOut (inputArea_target_buffercc_io_dataOut), //o + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i + ); + initial begin + `ifndef SYNTHESIS + inputArea_target = $urandom; + outputArea_hit = $urandom; + `endif + end + + assign outputArea_target = inputArea_target_buffercc_io_dataOut; + assign outputArea_flow_valid = (outputArea_target != outputArea_hit); + assign outputArea_flow_payload_last = inputArea_data_last; + assign outputArea_flow_payload_fragment = inputArea_data_fragment; + assign io_output_valid = outputArea_flow_m2sPipe_valid; + assign io_output_payload_last = outputArea_flow_m2sPipe_payload_last; + assign io_output_payload_fragment = outputArea_flow_m2sPipe_payload_fragment; + always @(posedge jtagCtrl_tck) begin + if(io_input_valid) begin + inputArea_target <= (! inputArea_target); + inputArea_data_last <= io_input_payload_last; + inputArea_data_fragment <= io_input_payload_fragment; + end + end + + always @(posedge io_systemClk) begin + outputArea_hit <= outputArea_target; + if(outputArea_flow_valid) begin + outputArea_flow_m2sPipe_payload_last <= outputArea_flow_payload_last; + outputArea_flow_m2sPipe_payload_fragment <= outputArea_flow_payload_fragment; + end + end + + always @(posedge io_systemClk) begin + if(debugCd_logic_outputReset) begin + outputArea_flow_m2sPipe_valid <= 1'b0; + end else begin + outputArea_flow_m2sPipe_valid <= outputArea_flow_valid; + end + end + + +endmodule + +module DataCache_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output reg io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isFiring, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + input [31:0] io_cpu_writeBack_storeData, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output io_cpu_writeBack_exclusiveOk, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output io_cpu_flush_ready, + input io_cpu_flush_payload_singleLine, + input [5:0] io_cpu_flush_payload_lineId, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_size, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [21:0] _zz_ways_0_tags_port0; + reg [31:0] _zz_ways_0_data_port0; + wire [21:0] _zz_ways_0_tags_port; + wire [9:0] _zz_stage0_dataColisions; + wire [9:0] _zz__zz_stageA_dataColisions; + wire [0:0] _zz_when; + wire [3:0] _zz_loader_counter_valueNext; + wire [0:0] _zz_loader_counter_valueNext_1; + wire [1:0] _zz_loader_waysAllocator; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [5:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [5:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [5:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_ways_0_tagsReadRsp_valid_1; + wire _zz_ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire when_DataCache_l642; + wire when_DataCache_l645; + wire when_DataCache_l664; + wire rspSync; + wire rspLast; + reg memCmdSent; + wire io_mem_cmd_fire; + wire when_DataCache_l686; + reg [3:0] _zz_stage0_mask; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + wire stage0_isAmo; + wire when_DataCache_l771; + reg stageA_request_wr; + reg [1:0] stageA_request_size; + reg stageA_request_totalyConsistent; + wire when_DataCache_l771_1; + reg [3:0] stageA_mask; + wire stageA_isAmo; + wire stageA_isLrsc; + wire [0:0] stageA_wayHits; + wire when_DataCache_l771_2; + reg [0:0] stageA_wayInvalidate; + wire when_DataCache_l771_3; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_stageA_dataColisions; + wire [0:0] stageA_dataColisions; + wire when_DataCache_l822; + reg stageB_request_wr; + reg [1:0] stageB_request_size; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + wire when_DataCache_l824; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + wire when_DataCache_l821; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + wire when_DataCache_l821_1; + reg [31:0] stageB_dataReadRsp_0; + wire when_DataCache_l820; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + wire when_DataCache_l820_1; + reg [0:0] stageB_dataColisions; + wire when_DataCache_l820_2; + reg stageB_unaligned; + wire when_DataCache_l820_3; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + wire when_DataCache_l820_4; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_waitDone; + wire stageB_flusher_hold; + reg [6:0] stageB_flusher_counter; + wire when_DataCache_l850; + wire when_DataCache_l856; + reg stageB_flusher_start; + wire stageB_isAmo; + wire stageB_isAmoCached; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + wire [31:0] stageB_requestDataBypass; + reg stageB_cpuWriteToCache; + wire when_DataCache_l926; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + wire when_DataCache_l995; + wire when_DataCache_l1004; + wire when_DataCache_l1009; + wire when_DataCache_l1020; + wire when_DataCache_l1032; + wire when_DataCache_l991; + wire when_DataCache_l1066; + wire when_DataCache_l1075; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [3:0] loader_counter_valueNext; + reg [3:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire when_DataCache_l1090; + wire loader_done; + wire when_DataCache_l1118; + reg loader_valid_regNext; + wire when_DataCache_l1122; + wire when_DataCache_l1125; + reg [21:0] ways_0_tags [0:63]; + reg [7:0] ways_0_data_symbol0 [0:1023]; + reg [7:0] ways_0_data_symbol1 [0:1023]; + reg [7:0] ways_0_data_symbol2 [0:1023]; + reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_ways_0_datasymbol_read; + reg [7:0] _zz_ways_0_datasymbol_read_1; + reg [7:0] _zz_ways_0_datasymbol_read_2; + reg [7:0] _zz_ways_0_datasymbol_read_3; + + assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_when = 1'b1; + assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; + assign _zz_loader_counter_valueNext = {3'd0, _zz_loader_counter_valueNext_1}; + assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @(posedge io_systemClk) begin + if(_zz_ways_0_tagsReadRsp_valid) begin + _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; + end + end + + always @(*) begin + _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; + end + always @(posedge io_systemClk) begin + if(_zz_ways_0_dataReadRspMem) begin + _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @(posedge io_systemClk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(when_DataCache_l645) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + _zz_2 = 1'b0; + if(when_DataCache_l642) begin + _zz_2 = 1'b1; + end + end + + assign haltCpu = 1'b0; + assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; + assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; + assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; + assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2]; + assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + assign when_DataCache_l642 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); + assign when_DataCache_l645 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); + always @(*) begin + tagsReadCmd_valid = 1'b0; + if(when_DataCache_l664) begin + tagsReadCmd_valid = 1'b1; + end + end + + always @(*) begin + tagsReadCmd_payload = 6'bxxxxxx; + if(when_DataCache_l664) begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 6]; + end + end + + always @(*) begin + dataReadCmd_valid = 1'b0; + if(when_DataCache_l664) begin + dataReadCmd_valid = 1'b1; + end + end + + always @(*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(when_DataCache_l664) begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + end + end + + always @(*) begin + tagsWriteCmd_valid = 1'b0; + if(when_DataCache_l850) begin + tagsWriteCmd_valid = 1'b1; + end + if(when_DataCache_l1066) begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_done) begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @(*) begin + tagsWriteCmd_payload_way = 1'bx; + if(when_DataCache_l850) begin + tagsWriteCmd_payload_way = 1'b1; + end + if(loader_done) begin + tagsWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @(*) begin + tagsWriteCmd_payload_address = 6'bxxxxxx; + if(when_DataCache_l850) begin + tagsWriteCmd_payload_address = stageB_flusher_counter[5:0]; + end + if(loader_done) begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 6]; + end + end + + always @(*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(when_DataCache_l850) begin + tagsWriteCmd_payload_data_valid = 1'b0; + end + if(loader_done) begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); + end + end + + always @(*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done) begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); + end + end + + always @(*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done) begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + end + end + + always @(*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache) begin + if(when_DataCache_l926) begin + dataWriteCmd_valid = 1'b1; + end + end + if(when_DataCache_l1066) begin + dataWriteCmd_valid = 1'b0; + end + if(when_DataCache_l1090) begin + dataWriteCmd_valid = 1'b1; + end + end + + always @(*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_way = stageB_waysHits; + end + if(when_DataCache_l1090) begin + dataWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @(*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + end + if(when_DataCache_l1090) begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 6],loader_counter_value}; + end + end + + always @(*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; + end + if(when_DataCache_l1090) begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; + end + end + + always @(*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_when[0]) begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end + end + if(when_DataCache_l1090) begin + dataWriteCmd_payload_mask = 4'b1111; + end + end + + assign when_DataCache_l664 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + always @(*) begin + io_cpu_execute_haltIt = 1'b0; + if(when_DataCache_l850) begin + io_cpu_execute_haltIt = 1'b1; + end + end + + assign rspSync = 1'b1; + assign rspLast = 1'b1; + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign when_DataCache_l686 = (! io_cpu_writeBack_isStuck); + always @(*) begin + _zz_stage0_mask = 4'bxxxx; + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_stage0_mask = 4'b0001; + end + 2'b01 : begin + _zz_stage0_mask = 4'b0011; + end + 2'b10 : begin + _zz_stage0_mask = 4'b1111; + end + default : begin + end + endcase + end + + assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign stage0_isAmo = 1'b0; + assign when_DataCache_l771 = (! io_cpu_memory_isStuck); + assign when_DataCache_l771_1 = (! io_cpu_memory_isStuck); + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_isAmo = 1'b0; + assign stageA_isLrsc = 1'b0; + assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign when_DataCache_l771_2 = (! io_cpu_memory_isStuck); + assign when_DataCache_l771_3 = (! io_cpu_memory_isStuck); + assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); + assign when_DataCache_l822 = (! io_cpu_writeBack_isStuck); + always @(*) begin + stageB_mmuRspFreeze = 1'b0; + if(when_DataCache_l1125) begin + stageB_mmuRspFreeze = 1'b1; + end + end + + assign when_DataCache_l824 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign when_DataCache_l821 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l821_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l820 = (! io_cpu_writeBack_isStuck); + assign stageB_consistancyHazard = 1'b0; + assign when_DataCache_l820_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l820_2 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l820_3 = (! io_cpu_writeBack_isStuck); + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (|stageB_waysHits); + assign stageB_dataMux = stageB_dataReadRsp_0; + assign when_DataCache_l820_4 = (! io_cpu_writeBack_isStuck); + always @(*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(!when_DataCache_l1004) begin + if(io_mem_cmd_ready) begin + stageB_loaderValid = 1'b1; + end + end + end + end + end + if(when_DataCache_l1066) begin + stageB_loaderValid = 1'b0; + end + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @(*) begin + io_cpu_writeBack_haltIt = 1'b1; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l991) begin + if(when_DataCache_l995) begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(when_DataCache_l1004) begin + if(when_DataCache_l1009) begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end + end + if(when_DataCache_l1066) begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + + assign stageB_flusher_hold = 1'b0; + assign when_DataCache_l850 = (! stageB_flusher_counter[6]); + assign when_DataCache_l856 = (! stageB_flusher_hold); + assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[6]); + assign stageB_isAmo = 1'b0; + assign stageB_isAmoCached = 1'b0; + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + assign stageB_requestDataBypass = io_cpu_writeBack_storeData; + always @(*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(when_DataCache_l1004) begin + stageB_cpuWriteToCache = 1'b1; + end + end + end + end + end + + assign when_DataCache_l926 = (stageB_request_wr && stageB_waysHit); + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @(*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(when_DataCache_l1004) begin + if(when_DataCache_l1020) begin + io_cpu_redo = 1'b1; + end + end + end + end + end + if(when_DataCache_l1075) begin + io_cpu_redo = 1'b1; + end + if(when_DataCache_l1122) begin + io_cpu_redo = 1'b1; + end + end + + always @(*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache) begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + end + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @(*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l991) begin + io_mem_cmd_valid = (! memCmdSent); + end else begin + if(when_DataCache_l1004) begin + if(stageB_request_wr) begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if(when_DataCache_l1032) begin + io_mem_cmd_valid = 1'b1; + end + end + end + end + end + if(when_DataCache_l1066) begin + io_mem_cmd_valid = 1'b0; + end + end + + always @(*) begin + io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(!when_DataCache_l1004) begin + io_mem_cmd_payload_address[5 : 0] = 6'h0; + end + end + end + end + end + + assign io_mem_cmd_payload_last = 1'b1; + always @(*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(!when_DataCache_l1004) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end + end + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + always @(*) begin + io_mem_cmd_payload_size = {1'd0, stageB_request_size}; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(!when_DataCache_l1004) begin + io_mem_cmd_payload_size = 3'b110; + end + end + end + end + end + + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + assign when_DataCache_l995 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); + assign when_DataCache_l1004 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign when_DataCache_l1009 = ((! stageB_request_wr) || io_mem_cmd_ready); + assign when_DataCache_l1020 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign when_DataCache_l1032 = (! memCmdSent); + assign when_DataCache_l991 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + always @(*) begin + if(stageB_bypassCache) begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; + end + end + + assign when_DataCache_l1066 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign when_DataCache_l1075 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); + always @(*) begin + loader_counter_willIncrement = 1'b0; + if(when_DataCache_l1090) begin + loader_counter_willIncrement = 1'b1; + end + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 4'b1111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @(*) begin + loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); + if(loader_counter_willClear) begin + loader_counter_valueNext = 4'b0000; + end + end + + assign loader_kill = 1'b0; + assign when_DataCache_l1090 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign loader_done = loader_counter_willOverflow; + assign when_DataCache_l1118 = (! loader_valid); + assign when_DataCache_l1122 = (loader_valid && (! loader_valid_regNext)); + assign io_cpu_execute_refilling = loader_valid; + assign when_DataCache_l1125 = (stageB_loaderValid || loader_valid); + always @(posedge io_systemClk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if(when_DataCache_l771) begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; + end + if(when_DataCache_l771_1) begin + stageA_mask <= stage0_mask; + end + if(when_DataCache_l771_2) begin + stageA_wayInvalidate <= stage0_wayInvalidate; + end + if(when_DataCache_l771_3) begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; + end + if(when_DataCache_l822) begin + stageB_request_wr <= stageA_request_wr; + stageB_request_size <= stageA_request_size; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(when_DataCache_l824) begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; + end + if(when_DataCache_l821) begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; + end + if(when_DataCache_l821_1) begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; + end + if(when_DataCache_l820) begin + stageB_wayInvalidate <= stageA_wayInvalidate; + end + if(when_DataCache_l820_1) begin + stageB_dataColisions <= stageA_dataColisions; + end + if(when_DataCache_l820_2) begin + stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); + end + if(when_DataCache_l820_3) begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; + end + if(when_DataCache_l820_4) begin + stageB_mask <= stageA_mask; + end + loader_valid_regNext <= loader_valid; + end + + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + memCmdSent <= 1'b0; + stageB_flusher_waitDone <= 1'b0; + stageB_flusher_counter <= 7'h0; + stageB_flusher_start <= 1'b1; + loader_valid <= 1'b0; + loader_counter_value <= 4'b0000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_fire) begin + memCmdSent <= 1'b1; + end + if(when_DataCache_l686) begin + memCmdSent <= 1'b0; + end + if(io_cpu_flush_ready) begin + stageB_flusher_waitDone <= 1'b0; + end + if(when_DataCache_l850) begin + if(when_DataCache_l856) begin + stageB_flusher_counter <= (stageB_flusher_counter + 7'h01); + if(io_cpu_flush_payload_singleLine) begin + stageB_flusher_counter[6] <= 1'b1; + end + end + end + stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start) begin + stageB_flusher_waitDone <= 1'b1; + stageB_flusher_counter <= 7'h0; + if(io_cpu_flush_payload_singleLine) begin + stageB_flusher_counter <= {1'b0,io_cpu_flush_payload_lineId}; + end + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); // DataCache_b62b14ffe6bb44e5a817b8d08e286c6b.scala:L1077 + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("ERROR writeBack stuck by another plugin is not allowed"); // DataCache_b62b14ffe6bb44e5a817b8d08e286c6b.scala:L1077 + end + `endif + `endif + if(stageB_loaderValid) begin + loader_valid <= 1'b1; + end + loader_counter_value <= loader_counter_valueNext; + if(loader_kill) begin + loader_killReg <= 1'b1; + end + if(when_DataCache_l1090) begin + loader_error <= (loader_error || io_mem_rsp_payload_error); + end + if(loader_done) begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end + if(when_DataCache_l1118) begin + loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; + end + end + end + + +endmodule + +module InstructionCache_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [31:0] _zz_banks_0_port1; + reg [21:0] _zz_ways_0_tags_port1; + wire [21:0] _zz_ways_0_tags_port; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [6:0] lineLoader_flushCounter; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; + reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l513; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [3:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [5:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire when_InstructionCache_l401; + wire [9:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [5:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; + reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + wire when_InstructionCache_l459_1; + reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; + reg decodeStage_hit_error; + reg [31:0] banks_0 [0:1023]; + reg [21:0] ways_0_tags [0:63]; + + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge io_systemClk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @(posedge io_systemClk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; + end + end + + always @(posedge io_systemClk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid) begin + _zz_2 = 1'b1; + end + end + + always @(*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin + lineLoader_fire = 1'b1; + end + end + end + + always @(*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(when_InstructionCache_l338) begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(when_InstructionCache_l342) begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush) begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[6]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 6],6'h0}; + assign io_mem_cmd_payload_size = 3'b110; + assign when_Utils_l513 = (! lineLoader_valid); + always @(*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if(when_Utils_l513) begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[11 : 6] : lineLoader_flushCounter[5 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 6],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data[31 : 0]; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 4'b1111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[11 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[11 : 6]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[21 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = (|fetchStage_hit_hits_0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 4'b0000; + end else begin + if(lineLoader_fire) begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire) begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid) begin + lineLoader_valid <= 1'b1; + end + if(io_flush) begin + lineLoader_flushPending <= 1'b1; + end + if(when_InstructionCache_l351) begin + lineLoader_flushPending <= 1'b0; + end + if(io_mem_cmd_fire) begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire) begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid) begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 4'b0001); + if(io_mem_rsp_payload_error) begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @(posedge io_systemClk) begin + if(io_cpu_fill_valid) begin + lineLoader_address <= io_cpu_fill_payload; + end + if(when_InstructionCache_l338) begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); + end + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[6]; + if(when_InstructionCache_l351) begin + lineLoader_flushCounter <= 7'h0; + end + if(when_InstructionCache_l435) begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if(when_InstructionCache_l459) begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + end + if(when_InstructionCache_l459_1) begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if(when_InstructionCache_l459_2) begin + decodeStage_hit_error <= fetchStage_hit_error; + end + end + + +endmodule + +module UartCtrlRx_b62b14ffe6bb44e5a817b8d08e286c6b ( + input [2:0] io_configFrame_dataLength, + input [0:0] io_configFrame_stop, + input [1:0] io_configFrame_parity, + input io_samplingTick, + output io_read_valid, + input io_read_ready, + output [7:0] io_read_payload, + input io_rxd, + output io_rts, + output reg io_error, + output io_break, + input io_systemClk, + input systemCd_logic_outputReset +); + localparam UartStopType_ONE = 1'd0; + localparam UartStopType_TWO = 1'd1; + localparam UartParityType_NONE = 2'd0; + localparam UartParityType_EVEN = 2'd1; + localparam UartParityType_ODD = 2'd2; + localparam UartCtrlRxState_IDLE = 3'd0; + localparam UartCtrlRxState_START = 3'd1; + localparam UartCtrlRxState_DATA = 3'd2; + localparam UartCtrlRxState_PARITY = 3'd3; + localparam UartCtrlRxState_STOP = 3'd4; + + wire io_rxd_buffercc_io_dataOut; + wire _zz_sampler_value; + wire _zz_sampler_value_1; + wire _zz_sampler_value_2; + wire _zz_sampler_value_3; + wire _zz_sampler_value_4; + wire _zz_sampler_value_5; + wire _zz_sampler_value_6; + wire [2:0] _zz_when_UartCtrlRx_l139; + wire [0:0] _zz_when_UartCtrlRx_l139_1; + reg _zz_io_rts; + wire sampler_synchroniser; + wire sampler_samples_0; + reg sampler_samples_1; + reg sampler_samples_2; + reg sampler_samples_3; + reg sampler_samples_4; + reg sampler_value; + reg sampler_tick; + reg [2:0] bitTimer_counter; + reg bitTimer_tick; + wire when_UartCtrlRx_l43; + reg [2:0] bitCounter_value; + reg [6:0] break_counter; + wire break_valid; + wire when_UartCtrlRx_l69; + reg [2:0] stateMachine_state; + reg stateMachine_parity; + reg [7:0] stateMachine_shifter; + reg stateMachine_validReg; + wire when_UartCtrlRx_l93; + wire when_UartCtrlRx_l103; + wire when_UartCtrlRx_l111; + wire when_UartCtrlRx_l113; + wire when_UartCtrlRx_l125; + wire when_UartCtrlRx_l136; + wire when_UartCtrlRx_l139; + `ifndef SYNTHESIS + reg [23:0] io_configFrame_stop_string; + reg [31:0] io_configFrame_parity_string; + reg [47:0] stateMachine_state_string; + `endif + + + assign _zz_when_UartCtrlRx_l139_1 = ((io_configFrame_stop == UartStopType_ONE) ? 1'b0 : 1'b1); + assign _zz_when_UartCtrlRx_l139 = {2'd0, _zz_when_UartCtrlRx_l139_1}; + assign _zz_sampler_value = ((((1'b0 || ((_zz_sampler_value_1 && sampler_samples_1) && sampler_samples_2)) || (((_zz_sampler_value_2 && sampler_samples_0) && sampler_samples_1) && sampler_samples_3)) || (((1'b1 && sampler_samples_0) && sampler_samples_2) && sampler_samples_3)) || (((1'b1 && sampler_samples_1) && sampler_samples_2) && sampler_samples_3)); + assign _zz_sampler_value_3 = (((1'b1 && sampler_samples_0) && sampler_samples_1) && sampler_samples_4); + assign _zz_sampler_value_4 = ((1'b1 && sampler_samples_0) && sampler_samples_2); + assign _zz_sampler_value_5 = (1'b1 && sampler_samples_1); + assign _zz_sampler_value_6 = 1'b1; + assign _zz_sampler_value_1 = (1'b1 && sampler_samples_0); + assign _zz_sampler_value_2 = 1'b1; + BufferCC_b62b14ffe6bb44e5a817b8d08e286c6b io_rxd_buffercc ( + .io_dataIn (io_rxd ), //i + .io_dataOut (io_rxd_buffercc_io_dataOut), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_configFrame_stop) + UartStopType_ONE : io_configFrame_stop_string = "ONE"; + UartStopType_TWO : io_configFrame_stop_string = "TWO"; + default : io_configFrame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_configFrame_parity) + UartParityType_NONE : io_configFrame_parity_string = "NONE"; + UartParityType_EVEN : io_configFrame_parity_string = "EVEN"; + UartParityType_ODD : io_configFrame_parity_string = "ODD "; + default : io_configFrame_parity_string = "????"; + endcase + end + always @(*) begin + case(stateMachine_state) + UartCtrlRxState_IDLE : stateMachine_state_string = "IDLE "; + UartCtrlRxState_START : stateMachine_state_string = "START "; + UartCtrlRxState_DATA : stateMachine_state_string = "DATA "; + UartCtrlRxState_PARITY : stateMachine_state_string = "PARITY"; + UartCtrlRxState_STOP : stateMachine_state_string = "STOP "; + default : stateMachine_state_string = "??????"; + endcase + end + `endif + + always @(*) begin + io_error = 1'b0; + case(stateMachine_state) + UartCtrlRxState_IDLE : begin + end + UartCtrlRxState_START : begin + end + UartCtrlRxState_DATA : begin + end + UartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + if(!when_UartCtrlRx_l125) begin + io_error = 1'b1; + end + end + end + default : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l136) begin + io_error = 1'b1; + end + end + end + endcase + end + + assign io_rts = _zz_io_rts; + assign sampler_synchroniser = io_rxd_buffercc_io_dataOut; + assign sampler_samples_0 = sampler_synchroniser; + always @(*) begin + bitTimer_tick = 1'b0; + if(sampler_tick) begin + if(when_UartCtrlRx_l43) begin + bitTimer_tick = 1'b1; + end + end + end + + assign when_UartCtrlRx_l43 = (bitTimer_counter == 3'b000); + assign break_valid = (break_counter == 7'h68); + assign when_UartCtrlRx_l69 = (io_samplingTick && (! break_valid)); + assign io_break = break_valid; + assign io_read_valid = stateMachine_validReg; + assign when_UartCtrlRx_l93 = ((sampler_tick && (! sampler_value)) && (! break_valid)); + assign when_UartCtrlRx_l103 = (sampler_value == 1'b1); + assign when_UartCtrlRx_l111 = (bitCounter_value == io_configFrame_dataLength); + assign when_UartCtrlRx_l113 = (io_configFrame_parity == UartParityType_NONE); + assign when_UartCtrlRx_l125 = (stateMachine_parity == sampler_value); + assign when_UartCtrlRx_l136 = (! sampler_value); + assign when_UartCtrlRx_l139 = (bitCounter_value == _zz_when_UartCtrlRx_l139); + assign io_read_payload = stateMachine_shifter; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + _zz_io_rts <= 1'b0; + sampler_samples_1 <= 1'b1; + sampler_samples_2 <= 1'b1; + sampler_samples_3 <= 1'b1; + sampler_samples_4 <= 1'b1; + sampler_value <= 1'b1; + sampler_tick <= 1'b0; + break_counter <= 7'h0; + stateMachine_state <= UartCtrlRxState_IDLE; + stateMachine_validReg <= 1'b0; + end else begin + _zz_io_rts <= (! io_read_ready); + if(io_samplingTick) begin + sampler_samples_1 <= sampler_samples_0; + end + if(io_samplingTick) begin + sampler_samples_2 <= sampler_samples_1; + end + if(io_samplingTick) begin + sampler_samples_3 <= sampler_samples_2; + end + if(io_samplingTick) begin + sampler_samples_4 <= sampler_samples_3; + end + sampler_value <= ((((((_zz_sampler_value || _zz_sampler_value_3) || (_zz_sampler_value_4 && sampler_samples_4)) || ((_zz_sampler_value_5 && sampler_samples_2) && sampler_samples_4)) || (((_zz_sampler_value_6 && sampler_samples_0) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_1) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_2) && sampler_samples_3) && sampler_samples_4)); + sampler_tick <= io_samplingTick; + if(sampler_value) begin + break_counter <= 7'h0; + end else begin + if(when_UartCtrlRx_l69) begin + break_counter <= (break_counter + 7'h01); + end + end + stateMachine_validReg <= 1'b0; + case(stateMachine_state) + UartCtrlRxState_IDLE : begin + if(when_UartCtrlRx_l93) begin + stateMachine_state <= UartCtrlRxState_START; + end + end + UartCtrlRxState_START : begin + if(bitTimer_tick) begin + stateMachine_state <= UartCtrlRxState_DATA; + if(when_UartCtrlRx_l103) begin + stateMachine_state <= UartCtrlRxState_IDLE; + end + end + end + UartCtrlRxState_DATA : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l111) begin + if(when_UartCtrlRx_l113) begin + stateMachine_state <= UartCtrlRxState_STOP; + stateMachine_validReg <= 1'b1; + end else begin + stateMachine_state <= UartCtrlRxState_PARITY; + end + end + end + end + UartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l125) begin + stateMachine_state <= UartCtrlRxState_STOP; + stateMachine_validReg <= 1'b1; + end else begin + stateMachine_state <= UartCtrlRxState_IDLE; + end + end + end + default : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l136) begin + stateMachine_state <= UartCtrlRxState_IDLE; + end else begin + if(when_UartCtrlRx_l139) begin + stateMachine_state <= UartCtrlRxState_IDLE; + end + end + end + end + endcase + end + end + + always @(posedge io_systemClk) begin + if(sampler_tick) begin + bitTimer_counter <= (bitTimer_counter - 3'b001); + end + if(bitTimer_tick) begin + bitCounter_value <= (bitCounter_value + 3'b001); + end + if(bitTimer_tick) begin + stateMachine_parity <= (stateMachine_parity ^ sampler_value); + end + case(stateMachine_state) + UartCtrlRxState_IDLE : begin + if(when_UartCtrlRx_l93) begin + bitTimer_counter <= 3'b010; + end + end + UartCtrlRxState_START : begin + if(bitTimer_tick) begin + bitCounter_value <= 3'b000; + stateMachine_parity <= (io_configFrame_parity == UartParityType_ODD); + end + end + UartCtrlRxState_DATA : begin + if(bitTimer_tick) begin + stateMachine_shifter[bitCounter_value] <= sampler_value; + if(when_UartCtrlRx_l111) begin + bitCounter_value <= 3'b000; + end + end + end + UartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + bitCounter_value <= 3'b000; + end + end + default : begin + end + endcase + end + + +endmodule + +module UartCtrlTx_b62b14ffe6bb44e5a817b8d08e286c6b ( + input [2:0] io_configFrame_dataLength, + input [0:0] io_configFrame_stop, + input [1:0] io_configFrame_parity, + input io_samplingTick, + input io_write_valid, + output reg io_write_ready, + input [7:0] io_write_payload, + input io_cts, + output io_txd, + input io_break, + input io_systemClk, + input systemCd_logic_outputReset +); + localparam UartStopType_ONE = 1'd0; + localparam UartStopType_TWO = 1'd1; + localparam UartParityType_NONE = 2'd0; + localparam UartParityType_EVEN = 2'd1; + localparam UartParityType_ODD = 2'd2; + localparam UartCtrlTxState_IDLE = 3'd0; + localparam UartCtrlTxState_START = 3'd1; + localparam UartCtrlTxState_DATA = 3'd2; + localparam UartCtrlTxState_PARITY = 3'd3; + localparam UartCtrlTxState_STOP = 3'd4; + + wire [2:0] _zz_clockDivider_counter_valueNext; + wire [0:0] _zz_clockDivider_counter_valueNext_1; + wire [2:0] _zz_when_UartCtrlTx_l93; + wire [0:0] _zz_when_UartCtrlTx_l93_1; + reg clockDivider_counter_willIncrement; + wire clockDivider_counter_willClear; + reg [2:0] clockDivider_counter_valueNext; + reg [2:0] clockDivider_counter_value; + wire clockDivider_counter_willOverflowIfInc; + wire clockDivider_counter_willOverflow; + reg [2:0] tickCounter_value; + reg [2:0] stateMachine_state; + reg stateMachine_parity; + reg stateMachine_txd; + wire when_UartCtrlTx_l58; + wire when_UartCtrlTx_l73; + wire when_UartCtrlTx_l76; + wire when_UartCtrlTx_l93; + reg _zz_io_txd; + `ifndef SYNTHESIS + reg [23:0] io_configFrame_stop_string; + reg [31:0] io_configFrame_parity_string; + reg [47:0] stateMachine_state_string; + `endif + + + assign _zz_clockDivider_counter_valueNext_1 = clockDivider_counter_willIncrement; + assign _zz_clockDivider_counter_valueNext = {2'd0, _zz_clockDivider_counter_valueNext_1}; + assign _zz_when_UartCtrlTx_l93_1 = ((io_configFrame_stop == UartStopType_ONE) ? 1'b0 : 1'b1); + assign _zz_when_UartCtrlTx_l93 = {2'd0, _zz_when_UartCtrlTx_l93_1}; + `ifndef SYNTHESIS + always @(*) begin + case(io_configFrame_stop) + UartStopType_ONE : io_configFrame_stop_string = "ONE"; + UartStopType_TWO : io_configFrame_stop_string = "TWO"; + default : io_configFrame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_configFrame_parity) + UartParityType_NONE : io_configFrame_parity_string = "NONE"; + UartParityType_EVEN : io_configFrame_parity_string = "EVEN"; + UartParityType_ODD : io_configFrame_parity_string = "ODD "; + default : io_configFrame_parity_string = "????"; + endcase + end + always @(*) begin + case(stateMachine_state) + UartCtrlTxState_IDLE : stateMachine_state_string = "IDLE "; + UartCtrlTxState_START : stateMachine_state_string = "START "; + UartCtrlTxState_DATA : stateMachine_state_string = "DATA "; + UartCtrlTxState_PARITY : stateMachine_state_string = "PARITY"; + UartCtrlTxState_STOP : stateMachine_state_string = "STOP "; + default : stateMachine_state_string = "??????"; + endcase + end + `endif + + always @(*) begin + clockDivider_counter_willIncrement = 1'b0; + if(io_samplingTick) begin + clockDivider_counter_willIncrement = 1'b1; + end + end + + assign clockDivider_counter_willClear = 1'b0; + assign clockDivider_counter_willOverflowIfInc = (clockDivider_counter_value == 3'b111); + assign clockDivider_counter_willOverflow = (clockDivider_counter_willOverflowIfInc && clockDivider_counter_willIncrement); + always @(*) begin + clockDivider_counter_valueNext = (clockDivider_counter_value + _zz_clockDivider_counter_valueNext); + if(clockDivider_counter_willClear) begin + clockDivider_counter_valueNext = 3'b000; + end + end + + always @(*) begin + stateMachine_txd = 1'b1; + case(stateMachine_state) + UartCtrlTxState_IDLE : begin + end + UartCtrlTxState_START : begin + stateMachine_txd = 1'b0; + end + UartCtrlTxState_DATA : begin + stateMachine_txd = io_write_payload[tickCounter_value]; + end + UartCtrlTxState_PARITY : begin + stateMachine_txd = stateMachine_parity; + end + default : begin + end + endcase + end + + always @(*) begin + io_write_ready = io_break; + case(stateMachine_state) + UartCtrlTxState_IDLE : begin + end + UartCtrlTxState_START : begin + end + UartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + io_write_ready = 1'b1; + end + end + end + UartCtrlTxState_PARITY : begin + end + default : begin + end + endcase + end + + assign when_UartCtrlTx_l58 = ((io_write_valid && (! io_cts)) && clockDivider_counter_willOverflow); + assign when_UartCtrlTx_l73 = (tickCounter_value == io_configFrame_dataLength); + assign when_UartCtrlTx_l76 = (io_configFrame_parity == UartParityType_NONE); + assign when_UartCtrlTx_l93 = (tickCounter_value == _zz_when_UartCtrlTx_l93); + assign io_txd = _zz_io_txd; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + clockDivider_counter_value <= 3'b000; + stateMachine_state <= UartCtrlTxState_IDLE; + _zz_io_txd <= 1'b1; + end else begin + clockDivider_counter_value <= clockDivider_counter_valueNext; + case(stateMachine_state) + UartCtrlTxState_IDLE : begin + if(when_UartCtrlTx_l58) begin + stateMachine_state <= UartCtrlTxState_START; + end + end + UartCtrlTxState_START : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_state <= UartCtrlTxState_DATA; + end + end + UartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + if(when_UartCtrlTx_l76) begin + stateMachine_state <= UartCtrlTxState_STOP; + end else begin + stateMachine_state <= UartCtrlTxState_PARITY; + end + end + end + end + UartCtrlTxState_PARITY : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_state <= UartCtrlTxState_STOP; + end + end + default : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l93) begin + stateMachine_state <= (io_write_valid ? UartCtrlTxState_START : UartCtrlTxState_IDLE); + end + end + end + endcase + _zz_io_txd <= (stateMachine_txd && (! io_break)); + end + end + + always @(posedge io_systemClk) begin + if(clockDivider_counter_willOverflow) begin + tickCounter_value <= (tickCounter_value + 3'b001); + end + if(clockDivider_counter_willOverflow) begin + stateMachine_parity <= (stateMachine_parity ^ stateMachine_txd); + end + case(stateMachine_state) + UartCtrlTxState_IDLE : begin + end + UartCtrlTxState_START : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_parity <= (io_configFrame_parity == UartParityType_ODD); + tickCounter_value <= 3'b000; + end + end + UartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + tickCounter_value <= 3'b000; + end + end + end + UartCtrlTxState_PARITY : begin + if(clockDivider_counter_willOverflow) begin + tickCounter_value <= 3'b000; + end + end + default : begin + end + endcase + end + + +endmodule + +module BufferCC_1_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_dataIn, + output io_dataOut, + input io_systemClk, + input debugCd_logic_outputReset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + initial begin + `ifndef SYNTHESIS + buffers_0 = $urandom; + buffers_1 = $urandom; + `endif + end + + assign io_dataOut = buffers_1; + always @(posedge io_systemClk) begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + + +endmodule + +module BufferCC_b62b14ffe6bb44e5a817b8d08e286c6b ( + input io_dataIn, + output io_dataOut, + input io_systemClk, + input systemCd_logic_outputReset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + buffers_0 <= 1'b0; + buffers_1 <= 1'b0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/sapphire_define.vh b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/sapphire_define.vh new file mode 100644 index 0000000..c60c9f4 --- /dev/null +++ b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/sapphire_define.vh @@ -0,0 +1,45 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2022.1.196 +// IP Version: 2.2 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + diff --git a/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/sapphire_tmpl.v b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/sapphire_tmpl.v new file mode 100644 index 0000000..4b3fc22 --- /dev/null +++ b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/sapphire_tmpl.v @@ -0,0 +1,76 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +sapphire u_sapphire( +.io_systemClk ( io_systemClk ), +.jtagCtrl_enable ( jtagCtrl_enable ), +.jtagCtrl_tdi ( jtagCtrl_tdi ), +.jtagCtrl_capture ( jtagCtrl_capture ), +.jtagCtrl_shift ( jtagCtrl_shift ), +.jtagCtrl_update ( jtagCtrl_update ), +.jtagCtrl_reset ( jtagCtrl_reset ), +.jtagCtrl_tdo ( jtagCtrl_tdo ), +.jtagCtrl_tck ( jtagCtrl_tck ), +.system_spi_0_io_data_0_read ( system_spi_0_io_data_0_read ), +.system_spi_0_io_data_0_write ( system_spi_0_io_data_0_write ), +.system_spi_0_io_data_0_writeEnable ( system_spi_0_io_data_0_writeEnable ), +.system_spi_0_io_data_1_read ( system_spi_0_io_data_1_read ), +.system_spi_0_io_data_1_write ( system_spi_0_io_data_1_write ), +.system_spi_0_io_data_1_writeEnable ( system_spi_0_io_data_1_writeEnable ), +.system_spi_0_io_data_2_read ( system_spi_0_io_data_2_read ), +.system_spi_0_io_data_2_write ( system_spi_0_io_data_2_write ), +.system_spi_0_io_data_2_writeEnable ( system_spi_0_io_data_2_writeEnable ), +.system_spi_0_io_data_3_read ( system_spi_0_io_data_3_read ), +.system_spi_0_io_data_3_write ( system_spi_0_io_data_3_write ), +.system_spi_0_io_data_3_writeEnable ( system_spi_0_io_data_3_writeEnable ), +.system_spi_0_io_sclk_write ( system_spi_0_io_sclk_write ), +.system_spi_0_io_ss ( system_spi_0_io_ss ), +.io_apbSlave_0_PADDR ( io_apbSlave_0_PADDR ), +.io_apbSlave_0_PENABLE ( io_apbSlave_0_PENABLE ), +.io_apbSlave_0_PRDATA ( io_apbSlave_0_PRDATA ), +.io_apbSlave_0_PREADY ( io_apbSlave_0_PREADY ), +.io_apbSlave_0_PSEL ( io_apbSlave_0_PSEL ), +.io_apbSlave_0_PSLVERROR ( io_apbSlave_0_PSLVERROR ), +.io_apbSlave_0_PWDATA ( io_apbSlave_0_PWDATA ), +.io_apbSlave_0_PWRITE ( io_apbSlave_0_PWRITE ), +.io_asyncReset ( io_asyncReset ), +.io_systemReset ( io_systemReset ), +.system_uart_0_io_txd ( system_uart_0_io_txd ), +.system_uart_0_io_rxd ( system_uart_0_io_rxd ) +); diff --git a/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/sapphire_tmpl.vhd b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/sapphire_tmpl.vhd new file mode 100644 index 0000000..a8c601e --- /dev/null +++ b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/sapphire_tmpl.vhd @@ -0,0 +1,118 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// +------------- Begin Cut here for COMPONENT Declaration ------ +COMPONENT sapphire is +PORT ( +io_systemClk : in std_logic; +jtagCtrl_enable : in std_logic; +jtagCtrl_tdi : in std_logic; +jtagCtrl_capture : in std_logic; +jtagCtrl_shift : in std_logic; +jtagCtrl_update : in std_logic; +jtagCtrl_reset : in std_logic; +jtagCtrl_tdo : out std_logic; +jtagCtrl_tck : in std_logic; +system_spi_0_io_data_0_read : in std_logic; +system_spi_0_io_data_0_write : out std_logic; +system_spi_0_io_data_0_writeEnable : out std_logic; +system_spi_0_io_data_1_read : in std_logic; +system_spi_0_io_data_1_write : out std_logic; +system_spi_0_io_data_1_writeEnable : out std_logic; +system_spi_0_io_data_2_read : in std_logic; +system_spi_0_io_data_2_write : out std_logic; +system_spi_0_io_data_2_writeEnable : out std_logic; +system_spi_0_io_data_3_read : in std_logic; +system_spi_0_io_data_3_write : out std_logic; +system_spi_0_io_data_3_writeEnable : out std_logic; +system_spi_0_io_sclk_write : out std_logic; +system_spi_0_io_ss : out std_logic_vector(0 to 0); +io_apbSlave_0_PADDR : out std_logic_vector(15 downto 0); +io_apbSlave_0_PENABLE : out std_logic; +io_apbSlave_0_PRDATA : in std_logic_vector(31 downto 0); +io_apbSlave_0_PREADY : in std_logic; +io_apbSlave_0_PSEL : out std_logic; +io_apbSlave_0_PSLVERROR : in std_logic; +io_apbSlave_0_PWDATA : out std_logic_vector(31 downto 0); +io_apbSlave_0_PWRITE : out std_logic; +io_asyncReset : in std_logic; +io_systemReset : out std_logic; +system_uart_0_io_txd : out std_logic; +system_uart_0_io_rxd : in std_logic); +END COMPONENT; +---------------------- End COMPONENT Declaration ------------ + +------------- Begin Cut here for INSTANTIATION Template ----- +u_sapphire : sapphire +PORT MAP ( +io_systemClk => io_systemClk, +jtagCtrl_enable => jtagCtrl_enable, +jtagCtrl_tdi => jtagCtrl_tdi, +jtagCtrl_capture => jtagCtrl_capture, +jtagCtrl_shift => jtagCtrl_shift, +jtagCtrl_update => jtagCtrl_update, +jtagCtrl_reset => jtagCtrl_reset, +jtagCtrl_tdo => jtagCtrl_tdo, +jtagCtrl_tck => jtagCtrl_tck, +system_spi_0_io_data_0_read => system_spi_0_io_data_0_read, +system_spi_0_io_data_0_write => system_spi_0_io_data_0_write, +system_spi_0_io_data_0_writeEnable => system_spi_0_io_data_0_writeEnable, +system_spi_0_io_data_1_read => system_spi_0_io_data_1_read, +system_spi_0_io_data_1_write => system_spi_0_io_data_1_write, +system_spi_0_io_data_1_writeEnable => system_spi_0_io_data_1_writeEnable, +system_spi_0_io_data_2_read => system_spi_0_io_data_2_read, +system_spi_0_io_data_2_write => system_spi_0_io_data_2_write, +system_spi_0_io_data_2_writeEnable => system_spi_0_io_data_2_writeEnable, +system_spi_0_io_data_3_read => system_spi_0_io_data_3_read, +system_spi_0_io_data_3_write => system_spi_0_io_data_3_write, +system_spi_0_io_data_3_writeEnable => system_spi_0_io_data_3_writeEnable, +system_spi_0_io_sclk_write => system_spi_0_io_sclk_write, +system_spi_0_io_ss => system_spi_0_io_ss, +io_apbSlave_0_PADDR => io_apbSlave_0_PADDR, +io_apbSlave_0_PENABLE => io_apbSlave_0_PENABLE, +io_apbSlave_0_PRDATA => io_apbSlave_0_PRDATA, +io_apbSlave_0_PREADY => io_apbSlave_0_PREADY, +io_apbSlave_0_PSEL => io_apbSlave_0_PSEL, +io_apbSlave_0_PSLVERROR => io_apbSlave_0_PSLVERROR, +io_apbSlave_0_PWDATA => io_apbSlave_0_PWDATA, +io_apbSlave_0_PWRITE => io_apbSlave_0_PWRITE, +io_asyncReset => io_asyncReset, +io_systemReset => io_systemReset, +system_uart_0_io_txd => system_uart_0_io_txd, +system_uart_0_io_rxd => system_uart_0_io_rxd); +------------------------ End INSTANTIATION Template --------- diff --git a/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/settings.json b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/settings.json new file mode 100644 index 0000000..594e31f --- /dev/null +++ b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/settings.json @@ -0,0 +1,156 @@ +{ + "args": [ + "-o", + "sapphire", + "--base_path", + "/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "soc", + "name": "efx_soc", + "version": "2.2" + } + ], + "conf": { + "HexFile_PathEnable": "0", + "HexFile_Path": "", + "APBSlave0_Size": "65536", + "DEVKIT_CUSTOM": "sapphireBoard_rev0", + "LDSize": "124", + "LDStackSize": "4", + "DEVKIT": "2", + "DEBUG": "1", + "SOFT_TAP": "0", + "TAP_COUNT": "0", + "TAP_SEL": "8", + "Frequency": "50", + "PeriFrequencyEnable": "0", + "PeriFrequency": "50", + "UART2_INT_ID": "3", + "TEST": "0", + "Base_M_AXIS": "3774873600", + "APBSlave0": "1", + "APBSlave2": "0", + "Base_M_IO": "4160749568", + "APBSlave1": "0", + "APBSlave3": "0", + "USER_1_INTR_ID": "17", + "USER_1_INTR": "0", + "USER_0_INTR_ID": "16", + "USER_0_INTR": "0", + "USER_2_INTR": "0", + "USER_2_INTR_ID": "22", + "USER_3_INTR": "0", + "USER_3_INTR_ID": "23", + "USER_4_INTR": "0", + "USER_4_INTR_ID": "24", + "USER_5_INTR": "0", + "USER_5_INTR_ID": "25", + "USER_6_INTR": "0", + "USER_6_INTR_ID": "26", + "USER_7_INTR": "0", + "USER_7_INTR_ID": "27", + "APBSlave4": "0", + "CustomInstruction": "0", + "ATMEXT": "0", + "CMREXT": "0", + "FPEXT": "1", + "FPU": "0", + "LINUX": "0", + "ICACHEWAY": "1", + "DCACHEWAY": "1", + "CpuCount": "1", + "ICacheSize": "4096", + "DCacheSize": "4096", + "Cache": "1", + "DDR": "0", + "DDR_AXI4": "0", + "DDRWidth": "128", + "DDRSize": "3758096384", + "OCRSize": "32768", + "AXISlave": "0", + "AXISlaveSize": "16777216", + "GPIO1_INT_ID1": "15", + "GPIO1_INT_ID0": "14", + "GPIO0_INT_ID1": "13", + "GPIO0_INT_ID0": "12", + "GPIO0": "0", + "GPIO0Width": "4", + "GPIO1Width": "8", + "GPIO1": "0", + "UART0_INT_ID": "1", + "IOSize": "4096", + "UART0_M_Addr": "4096", + "UART1_M_Addr": "8192", + "UART2_M_Addr": "12288", + "SPI0_M_Addr": "24576", + "SPI1_M_Addr": "16384", + "SPI2_M_Addr": "20480", + "I2C0_M_Addr": "40960", + "I2C1_M_Addr": "45056", + "I2C2_M_Addr": "49152", + "GPIO0_M_Addr": "53248", + "GPIO1_M_Addr": "57344", + "APBSlave0_M_Addr": "1048576", + "APBSlave1_M_Addr": "2097152", + "APBSlave2_M_Addr": "3145728", + "APBSlave3_M_Addr": "4194304", + "APBSlave4_M_Addr": "5242880", + "UART0": "1", + "UART2": "0", + "UART1_INT_ID": "2", + "UART1": "0", + "SPI2": "0", + "SPI2DW": "8", + "SPI2SS": "1", + "SPI1_INT_ID": "5", + "SPI1": "0", + "SPI1DW": "8", + "SPI1SS": "1", + "SPI0_INT_ID": "4", + "SPI0": "1", + "SPI0DW": "8", + "SPI0SS": "1", + "I2C2_INT_ID": "10", + "ADDR_Scheme": "0", + "I2C2": "0", + "I2C1": "0", + "SPI2_INT_ID": "6", + "I2C1_INT_ID": "9", + "I2C0_INT_ID": "8", + "I2C0": "0", + "AXIMasterWidth_1": "32", + "AXIMaster_1": "0", + "AXIMasterWidth": "32", + "AXIMaster": "1", + "USER_TIMER0": "0", + "USER_TIMER0_CNT_WIDTH": "12", + "USER_TIMER0_PS_WIDTH": "8", + "USER_TIMER0_INT_ID": "19", + "USER_TIMER0_M_Addr": "61440", + "USER_TIMER1": "0", + "USER_TIMER1_CNT_WIDTH": "12", + "USER_TIMER1_PS_WIDTH": "8", + "USER_TIMER1_INT_ID": "20", + "USER_TIMER1_M_Addr": "65536", + "USER_TIMER2": "0", + "USER_TIMER2_CNT_WIDTH": "12", + "USER_TIMER2_PS_WIDTH": "8", + "USER_TIMER2_INT_ID": "21", + "USER_TIMER2_M_Addr": "69632" + }, + "output": { + "external_generator": [], + "external_source": [ + "/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip/sapphire/sapphire_tmpl.v", + "/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip/sapphire/sapphire.v", + "/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip/sapphire/sapphire_define.vh", + "/projects/SSE/kmlau/install/efinity/2022.1/ipm/bin/gui/None/ip/tse0/T120F324_devkit/ip/sapphire/sapphire_tmpl.vhd" + ], + "external_script": [], + "external_embedded_sw": [] + }, + "sw_version": "2022.1.196", + "generated_date": "2022-08-08T02:57:54.948573" +} \ No newline at end of file diff --git a/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v new file mode 100644 index 0000000..d8f0f2f --- /dev/null +++ b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v @@ -0,0 +1,14093 @@ +// Generator : SpinalHDL v1.7.1-SNAPSHOT git head : 2aaf6e4d1af9719ce8d12a973793990e489d8055 +// Component : EfxSapphireSoc + +`timescale 1ns/1ps + +module EfxSapphireSoc ( + input io_systemClk, + input io_asyncReset, + input jtagCtrl_tck, + output reg io_systemReset, + input jtagCtrl_tdi, + input jtagCtrl_enable, + input jtagCtrl_capture, + input jtagCtrl_shift, + input jtagCtrl_update, + input jtagCtrl_reset, + output jtagCtrl_tdo, + output system_uart_0_io_txd, + input system_uart_0_io_rxd, + output [15:0] io_apbSlave_0_PADDR, + output [0:0] io_apbSlave_0_PSEL, + output io_apbSlave_0_PENABLE, + input io_apbSlave_0_PREADY, + output io_apbSlave_0_PWRITE, + output [31:0] io_apbSlave_0_PWDATA, + input [31:0] io_apbSlave_0_PRDATA, + input io_apbSlave_0_PSLVERROR, + output [0:0] system_spi_0_io_sclk_write, + output system_spi_0_io_data_0_writeEnable, + input [0:0] system_spi_0_io_data_0_read, + output [0:0] system_spi_0_io_data_0_write, + output system_spi_0_io_data_1_writeEnable, + input [0:0] system_spi_0_io_data_1_read, + output [0:0] system_spi_0_io_data_1_write, + output system_spi_0_io_data_2_writeEnable, + input [0:0] system_spi_0_io_data_2_read, + output [0:0] system_spi_0_io_data_2_write, + output system_spi_0_io_data_3_writeEnable, + input [0:0] system_spi_0_io_data_3_read, + output [0:0] system_spi_0_io_data_3_write, + output [0:0] system_spi_0_io_ss +); + + reg system_cores_0_logic_cpu_dBus_rsp_valid; + wire system_cores_0_logic_cpu_dBus_rsp_payload_error; + wire system_cores_0_logic_cpu_debug_bus_cmd_payload_wr; + wire system_cores_0_logic_cpu_iBus_rsp_payload_error; + wire bufferCC_5_io_dataOut; + wire bufferCC_6_io_dataOut; + wire system_cores_0_logic_cpu_dBus_cmd_valid; + wire system_cores_0_logic_cpu_dBus_cmd_payload_wr; + wire system_cores_0_logic_cpu_dBus_cmd_payload_uncached; + wire [31:0] system_cores_0_logic_cpu_dBus_cmd_payload_address; + wire [31:0] system_cores_0_logic_cpu_dBus_cmd_payload_data; + wire [3:0] system_cores_0_logic_cpu_dBus_cmd_payload_mask; + wire [2:0] system_cores_0_logic_cpu_dBus_cmd_payload_size; + wire system_cores_0_logic_cpu_dBus_cmd_payload_last; + wire system_cores_0_logic_cpu_debug_bus_cmd_ready; + wire [31:0] system_cores_0_logic_cpu_debug_bus_rsp_data; + wire system_cores_0_logic_cpu_debug_resetOut; + wire system_cores_0_logic_cpu_iBus_cmd_valid; + wire [31:0] system_cores_0_logic_cpu_iBus_cmd_payload_address; + wire [2:0] system_cores_0_logic_cpu_iBus_cmd_payload_size; + wire system_hardJtag_debug_logic_jtagBridge_io_ctrl_tdo; + wire system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_valid; + wire system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_last; + wire [0:0] system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_fragment; + wire system_hardJtag_debug_logic_jtagBridge_io_remote_rsp_ready; + wire system_hardJtag_debug_logic_debugger_io_remote_cmd_ready; + wire system_hardJtag_debug_logic_debugger_io_remote_rsp_valid; + wire system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_error; + wire [31:0] system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_data; + wire system_hardJtag_debug_logic_debugger_io_mem_cmd_valid; + wire [31:0] system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address; + wire [31:0] system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_data; + wire system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_wr; + wire [1:0] system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_size; + wire bufferCC_7_io_dataOut; + wire bmbDecoder_4_io_input_cmd_ready; + wire bmbDecoder_4_io_input_rsp_valid; + wire bmbDecoder_4_io_input_rsp_payload_last; + wire [0:0] bmbDecoder_4_io_input_rsp_payload_fragment_opcode; + wire [31:0] bmbDecoder_4_io_input_rsp_payload_fragment_data; + wire bmbDecoder_4_io_outputs_0_cmd_valid; + wire bmbDecoder_4_io_outputs_0_cmd_payload_last; + wire [0:0] bmbDecoder_4_io_outputs_0_cmd_payload_fragment_opcode; + wire [31:0] bmbDecoder_4_io_outputs_0_cmd_payload_fragment_address; + wire [1:0] bmbDecoder_4_io_outputs_0_cmd_payload_fragment_length; + wire [31:0] bmbDecoder_4_io_outputs_0_cmd_payload_fragment_data; + wire [3:0] bmbDecoder_4_io_outputs_0_cmd_payload_fragment_mask; + wire bmbDecoder_4_io_outputs_0_rsp_ready; + wire system_fabric_exclusiveMonitor_logic_io_input_cmd_ready; + wire system_fabric_exclusiveMonitor_logic_io_input_rsp_valid; + wire system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_last; + wire [0:0] system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_opcode; + wire [31:0] system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_data; + wire [0:0] system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_context; + wire system_fabric_exclusiveMonitor_logic_io_output_cmd_valid; + wire system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_last; + wire [0:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_opcode; + wire [31:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_address; + wire [5:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_length; + wire [31:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_data; + wire [3:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_mask; + wire [0:0] system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_context; + wire system_fabric_exclusiveMonitor_logic_io_output_rsp_ready; + wire system_fabric_iBus_bmb_decoder_io_input_cmd_ready; + wire system_fabric_iBus_bmb_decoder_io_input_rsp_valid; + wire system_fabric_iBus_bmb_decoder_io_input_rsp_payload_last; + wire [0:0] system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_opcode; + wire [31:0] system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_data; + wire system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_valid; + wire system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_last; + wire [0:0] system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; + wire [31:0] system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; + wire [5:0] system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; + wire system_fabric_iBus_bmb_decoder_io_outputs_0_rsp_ready; + wire system_bridge_bmb_arbiter_io_inputs_0_cmd_ready; + wire system_bridge_bmb_arbiter_io_inputs_0_rsp_valid; + wire system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_last; + wire [0:0] system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_data; + wire [0:0] system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_context; + wire system_bridge_bmb_arbiter_io_inputs_1_cmd_ready; + wire system_bridge_bmb_arbiter_io_inputs_1_rsp_valid; + wire system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_last; + wire [0:0] system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_data; + wire system_bridge_bmb_arbiter_io_output_cmd_valid; + wire system_bridge_bmb_arbiter_io_output_cmd_payload_last; + wire [0:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_source; + wire [0:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_address; + wire [5:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_length; + wire [31:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_data; + wire [3:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_mask; + wire [0:0] system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_context; + wire system_bridge_bmb_arbiter_io_output_rsp_ready; + wire system_bridge_bmb_decoder_io_input_cmd_ready; + wire system_bridge_bmb_decoder_io_input_rsp_valid; + wire system_bridge_bmb_decoder_io_input_rsp_payload_last; + wire [0:0] system_bridge_bmb_decoder_io_input_rsp_payload_fragment_source; + wire [0:0] system_bridge_bmb_decoder_io_input_rsp_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_decoder_io_input_rsp_payload_fragment_data; + wire [0:0] system_bridge_bmb_decoder_io_input_rsp_payload_fragment_context; + wire system_bridge_bmb_decoder_io_outputs_0_cmd_valid; + wire system_bridge_bmb_decoder_io_outputs_0_cmd_payload_last; + wire [0:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_source; + wire [0:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; + wire [5:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; + wire [31:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; + wire [3:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask; + wire [0:0] system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; + wire system_bridge_bmb_decoder_io_outputs_0_rsp_ready; + wire system_bridge_bmb_decoder_io_outputs_1_cmd_valid; + wire system_bridge_bmb_decoder_io_outputs_1_cmd_payload_last; + wire [0:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_source; + wire [0:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; + wire [5:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; + wire [31:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; + wire [3:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask; + wire [0:0] system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; + wire system_bridge_bmb_decoder_io_outputs_1_rsp_ready; + wire system_ramA_logic_io_bus_cmd_ready; + wire system_ramA_logic_io_bus_rsp_valid; + wire system_ramA_logic_io_bus_rsp_payload_last; + wire [0:0] system_ramA_logic_io_bus_rsp_payload_fragment_opcode; + wire [31:0] system_ramA_logic_io_bus_rsp_payload_fragment_data; + wire [3:0] system_ramA_logic_io_bus_rsp_payload_fragment_context; + wire system_bridge_bmb_unburstify_io_input_cmd_ready; + wire system_bridge_bmb_unburstify_io_input_rsp_valid; + wire system_bridge_bmb_unburstify_io_input_rsp_payload_last; + wire [0:0] system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_source; + wire [0:0] system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_data; + wire [0:0] system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_context; + wire system_bridge_bmb_unburstify_io_output_cmd_valid; + wire system_bridge_bmb_unburstify_io_output_cmd_payload_last; + wire [0:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_address; + wire [1:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_length; + wire [31:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_data; + wire [3:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_mask; + wire [3:0] system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_context; + wire system_bridge_bmb_unburstify_io_output_rsp_ready; + wire system_bridge_bmb_unburstify_1_io_input_cmd_ready; + wire system_bridge_bmb_unburstify_1_io_input_rsp_valid; + wire system_bridge_bmb_unburstify_1_io_input_rsp_payload_last; + wire [0:0] system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_source; + wire [0:0] system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_data; + wire [0:0] system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_context; + wire system_bridge_bmb_unburstify_1_io_output_cmd_valid; + wire system_bridge_bmb_unburstify_1_io_output_cmd_payload_last; + wire [0:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_address; + wire [1:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_length; + wire [31:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_data; + wire [3:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_mask; + wire [3:0] system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_context; + wire system_bridge_bmb_unburstify_1_io_output_rsp_ready; + wire system_bmbPeripheral_bmb_decoder_io_input_cmd_ready; + wire system_bmbPeripheral_bmb_decoder_io_input_rsp_valid; + wire system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_last; + wire [0:0] system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode; + wire [31:0] system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context; + wire system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid; + wire system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last; + wire [0:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; + wire [23:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; + wire [1:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; + wire [31:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask; + wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; + wire system_bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready; + wire system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid; + wire system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last; + wire [0:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; + wire [23:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; + wire [1:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; + wire [31:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask; + wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; + wire system_bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready; + wire system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid; + wire system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last; + wire [0:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode; + wire [23:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address; + wire [1:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length; + wire [31:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_mask; + wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context; + wire system_bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready; + wire system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid; + wire system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last; + wire [0:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode; + wire [23:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address; + wire [1:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length; + wire [31:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_mask; + wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context; + wire system_bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready; + wire system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid; + wire system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last; + wire [0:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode; + wire [23:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address; + wire [1:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length; + wire [31:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_mask; + wire [3:0] system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context; + wire system_bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready; + wire system_clint_logic_io_bus_cmd_ready; + wire system_clint_logic_io_bus_rsp_valid; + wire system_clint_logic_io_bus_rsp_payload_last; + wire [0:0] system_clint_logic_io_bus_rsp_payload_fragment_opcode; + wire [31:0] system_clint_logic_io_bus_rsp_payload_fragment_data; + wire [3:0] system_clint_logic_io_bus_rsp_payload_fragment_context; + wire [0:0] system_clint_logic_io_timerInterrupt; + wire [0:0] system_clint_logic_io_softwareInterrupt; + wire [63:0] system_clint_logic_io_time; + wire system_uart_0_io_logic_io_bus_cmd_ready; + wire system_uart_0_io_logic_io_bus_rsp_valid; + wire system_uart_0_io_logic_io_bus_rsp_payload_last; + wire [0:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode; + wire [31:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_data; + wire [3:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_context; + wire system_uart_0_io_logic_io_uart_txd; + wire system_uart_0_io_logic_io_interrupt; + wire system_spi_0_io_logic_io_ctrl_cmd_ready; + wire system_spi_0_io_logic_io_ctrl_rsp_valid; + wire system_spi_0_io_logic_io_ctrl_rsp_payload_last; + wire [0:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; + wire [31:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data; + wire [3:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context; + wire [0:0] system_spi_0_io_logic_io_spi_sclk_write; + wire [0:0] system_spi_0_io_logic_io_spi_ss; + wire [0:0] system_spi_0_io_logic_io_spi_data_0_write; + wire system_spi_0_io_logic_io_spi_data_0_writeEnable; + wire [0:0] system_spi_0_io_logic_io_spi_data_1_write; + wire system_spi_0_io_logic_io_spi_data_1_writeEnable; + wire [0:0] system_spi_0_io_logic_io_spi_data_2_write; + wire system_spi_0_io_logic_io_spi_data_2_writeEnable; + wire [0:0] system_spi_0_io_logic_io_spi_data_3_write; + wire system_spi_0_io_logic_io_spi_data_3_writeEnable; + wire system_spi_0_io_logic_io_interrupt; + wire io_apbSlave_0_logic_io_input_cmd_ready; + wire io_apbSlave_0_logic_io_input_rsp_valid; + wire io_apbSlave_0_logic_io_input_rsp_payload_last; + wire [0:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode; + wire [31:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_data; + wire [3:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_context; + wire [15:0] io_apbSlave_0_logic_io_output_PADDR; + wire [0:0] io_apbSlave_0_logic_io_output_PSEL; + wire io_apbSlave_0_logic_io_output_PENABLE; + wire io_apbSlave_0_logic_io_output_PWRITE; + wire [31:0] io_apbSlave_0_logic_io_output_PWDATA; + wire [29:0] _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address; + wire [6:0] _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask_1; + reg debugCd_logic_inputResetTrigger; + reg debugCd_logic_outputResetUnbuffered; + reg [11:0] debugCd_logic_holdingLogic_resetCounter; + wire when_ClockDomainGenerator_l77; + reg debugCd_logic_outputReset; + wire debugCd_logic_inputResetAdapter_stuff_syncTrigger; + reg systemCd_logic_inputResetTrigger; + reg systemCd_logic_outputResetUnbuffered; + reg [5:0] systemCd_logic_holdingLogic_resetCounter; + wire when_ClockDomainGenerator_l77_1; + reg systemCd_logic_outputReset; + wire system_cores_0_iBus_cmd_valid; + wire system_cores_0_iBus_cmd_ready; + wire system_cores_0_iBus_cmd_payload_last; + wire [0:0] system_cores_0_iBus_cmd_payload_fragment_opcode; + wire [31:0] system_cores_0_iBus_cmd_payload_fragment_address; + wire [5:0] system_cores_0_iBus_cmd_payload_fragment_length; + wire system_cores_0_iBus_rsp_valid; + wire system_cores_0_iBus_rsp_ready; + wire system_cores_0_iBus_rsp_payload_last; + wire [0:0] system_cores_0_iBus_rsp_payload_fragment_opcode; + wire [31:0] system_cores_0_iBus_rsp_payload_fragment_data; + wire system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_valid; + reg system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready; + wire system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_last; + wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_opcode; + wire [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_address; + wire [5:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; + wire [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_data; + wire [3:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_mask; + wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_context; + wire system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_valid; + wire system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_ready; + wire system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_last; + wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_opcode; + wire [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_data; + wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_context; + wire system_cores_0_logic_cpu_dBus_Bridge_withoutWriteBuffer_busCmdContext_isWrite; + reg [5:0] _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; + wire when_DataCache_l532; + reg system_cores_0_debugReset; + wire system_cores_0_iBus_connector_decoder_cmd_valid; + wire system_cores_0_iBus_connector_decoder_cmd_ready; + wire system_cores_0_iBus_connector_decoder_cmd_payload_last; + wire [0:0] system_cores_0_iBus_connector_decoder_cmd_payload_fragment_opcode; + wire [31:0] system_cores_0_iBus_connector_decoder_cmd_payload_fragment_address; + wire [5:0] system_cores_0_iBus_connector_decoder_cmd_payload_fragment_length; + wire system_cores_0_iBus_connector_decoder_rsp_valid; + wire system_cores_0_iBus_connector_decoder_rsp_ready; + wire system_cores_0_iBus_connector_decoder_rsp_payload_last; + wire [0:0] system_cores_0_iBus_connector_decoder_rsp_payload_fragment_opcode; + wire [31:0] system_cores_0_iBus_connector_decoder_rsp_payload_fragment_data; + reg _zz_system_cores_0_iBus_connector_decoder_rsp_ready; + wire system_cores_0_iBus_cmd_combStage_valid; + wire system_cores_0_iBus_cmd_combStage_ready; + wire system_cores_0_iBus_cmd_combStage_payload_last; + wire [0:0] system_cores_0_iBus_cmd_combStage_payload_fragment_opcode; + wire [31:0] system_cores_0_iBus_cmd_combStage_payload_fragment_address; + wire [5:0] system_cores_0_iBus_cmd_combStage_payload_fragment_length; + wire _zz_system_cores_0_iBus_rsp_valid; + reg _zz_system_cores_0_iBus_rsp_valid_1; + reg _zz_system_cores_0_iBus_rsp_payload_last; + reg [0:0] _zz_system_cores_0_iBus_rsp_payload_fragment_opcode; + reg [31:0] _zz_system_cores_0_iBus_rsp_payload_fragment_data; + wire when_Stream_l368; + wire system_cores_0_dBus_connector_decoder_cmd_valid; + wire system_cores_0_dBus_connector_decoder_cmd_ready; + wire system_cores_0_dBus_connector_decoder_cmd_payload_last; + wire [0:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_opcode; + wire [31:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_address; + wire [5:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_length; + wire [31:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_data; + wire [3:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_mask; + wire [0:0] system_cores_0_dBus_connector_decoder_cmd_payload_fragment_context; + wire system_cores_0_dBus_connector_decoder_rsp_valid; + wire system_cores_0_dBus_connector_decoder_rsp_ready; + wire system_cores_0_dBus_connector_decoder_rsp_payload_last; + wire [0:0] system_cores_0_dBus_connector_decoder_rsp_payload_fragment_opcode; + wire [31:0] system_cores_0_dBus_connector_decoder_rsp_payload_fragment_data; + wire [0:0] system_cores_0_dBus_connector_decoder_rsp_payload_fragment_context; + wire system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid; + wire system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_ready; + wire system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_last; + wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_opcode; + wire [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_address; + wire [5:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_length; + wire [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_data; + wire [3:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_mask; + wire [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_context; + reg system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid; + reg system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_last; + reg [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_opcode; + reg [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_address; + reg [5:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_length; + reg [31:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_data; + reg [3:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_mask; + reg [0:0] system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_context; + wire when_Stream_l368_1; + wire system_hardJtag_debug_logic_mmMaster_cmd_valid; + wire system_hardJtag_debug_logic_mmMaster_cmd_ready; + wire system_hardJtag_debug_logic_mmMaster_cmd_payload_last; + wire [0:0] system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_opcode; + wire [31:0] system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address; + wire [1:0] system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_length; + wire [31:0] system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_data; + wire [3:0] system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask; + wire system_hardJtag_debug_logic_mmMaster_rsp_valid; + wire system_hardJtag_debug_logic_mmMaster_rsp_ready; + wire system_hardJtag_debug_logic_mmMaster_rsp_payload_last; + wire [0:0] system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_opcode; + wire [31:0] system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_data; + reg [3:0] _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask; + wire system_hardJtag_debug_bmb_connector_decoder_cmd_valid; + wire system_hardJtag_debug_bmb_connector_decoder_cmd_ready; + wire system_hardJtag_debug_bmb_connector_decoder_cmd_payload_last; + wire [0:0] system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_opcode; + wire [31:0] system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_address; + wire [1:0] system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_length; + wire [31:0] system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_data; + wire [3:0] system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_mask; + wire system_hardJtag_debug_bmb_connector_decoder_rsp_valid; + wire system_hardJtag_debug_bmb_connector_decoder_rsp_ready; + wire system_hardJtag_debug_bmb_connector_decoder_rsp_payload_last; + wire [0:0] system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_opcode; + wire [31:0] system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_data; + wire system_fabric_iBus_bmb_cmd_valid; + reg system_fabric_iBus_bmb_cmd_ready; + wire system_fabric_iBus_bmb_cmd_payload_last; + wire [0:0] system_fabric_iBus_bmb_cmd_payload_fragment_opcode; + wire [31:0] system_fabric_iBus_bmb_cmd_payload_fragment_address; + wire [5:0] system_fabric_iBus_bmb_cmd_payload_fragment_length; + wire system_fabric_iBus_bmb_rsp_valid; + wire system_fabric_iBus_bmb_rsp_ready; + wire system_fabric_iBus_bmb_rsp_payload_last; + wire [0:0] system_fabric_iBus_bmb_rsp_payload_fragment_opcode; + wire [31:0] system_fabric_iBus_bmb_rsp_payload_fragment_data; + wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [31:0] system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [5:0] system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire system_cores_0_debugBmb_cmd_valid; + wire system_cores_0_debugBmb_cmd_ready; + wire system_cores_0_debugBmb_cmd_payload_last; + wire [0:0] system_cores_0_debugBmb_cmd_payload_fragment_opcode; + wire [7:0] system_cores_0_debugBmb_cmd_payload_fragment_address; + wire [1:0] system_cores_0_debugBmb_cmd_payload_fragment_length; + wire [31:0] system_cores_0_debugBmb_cmd_payload_fragment_data; + wire [3:0] system_cores_0_debugBmb_cmd_payload_fragment_mask; + wire system_cores_0_debugBmb_rsp_valid; + wire system_cores_0_debugBmb_rsp_ready; + wire system_cores_0_debugBmb_rsp_payload_last; + wire [0:0] system_cores_0_debugBmb_rsp_payload_fragment_opcode; + wire [31:0] system_cores_0_debugBmb_rsp_payload_fragment_data; + wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [5:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + reg _zz_io_input_rsp_ready; + wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_valid; + reg system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready; + wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_last; + wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_opcode; + wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_address; + wire [5:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_length; + wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_data; + wire [3:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_mask; + wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_context; + reg system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + reg system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + reg [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + reg [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + reg [5:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + reg [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + reg [3:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_mask; + reg [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid; + wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_ready; + wire system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_last; + wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_opcode; + wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_address; + wire [5:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_length; + wire [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_data; + wire [3:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_mask; + wire [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_context; + reg system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid; + reg system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_last; + reg [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_opcode; + reg [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_address; + reg [5:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_length; + reg [31:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_data; + reg [3:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_mask; + reg [0:0] system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_context; + wire when_Stream_l368_2; + wire _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + reg _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + reg _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + reg [0:0] _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + reg [31:0] _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + reg [0:0] _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire when_Stream_l368_3; + wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [7:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire system_cores_0_logic_cpu_debug_bus_cmd_fire; + reg system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext; + wire system_fabric_dBusCoherent_bmb_cmd_valid; + wire system_fabric_dBusCoherent_bmb_cmd_ready; + wire system_fabric_dBusCoherent_bmb_cmd_payload_last; + wire [0:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_opcode; + wire [31:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_address; + wire [5:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_length; + wire [31:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_data; + wire [3:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_mask; + wire [0:0] system_fabric_dBusCoherent_bmb_cmd_payload_fragment_context; + wire system_fabric_dBusCoherent_bmb_rsp_valid; + wire system_fabric_dBusCoherent_bmb_rsp_ready; + wire system_fabric_dBusCoherent_bmb_rsp_payload_last; + wire [0:0] system_fabric_dBusCoherent_bmb_rsp_payload_fragment_opcode; + wire [31:0] system_fabric_dBusCoherent_bmb_rsp_payload_fragment_data; + wire [0:0] system_fabric_dBusCoherent_bmb_rsp_payload_fragment_context; + wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [31:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [5:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + wire [0:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [0:0] system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_fabric_dBusCoherent_bmb_connector_decoder_cmd_valid; + wire system_fabric_dBusCoherent_bmb_connector_decoder_cmd_ready; + wire system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_last; + wire [0:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_opcode; + wire [31:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_address; + wire [5:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_length; + wire [31:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_data; + wire [3:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_mask; + wire [0:0] system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_context; + wire system_fabric_dBusCoherent_bmb_connector_decoder_rsp_valid; + wire system_fabric_dBusCoherent_bmb_connector_decoder_rsp_ready; + wire system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_last; + wire [0:0] system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_opcode; + wire [31:0] system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_data; + wire [0:0] system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_context; + wire system_fabric_exclusiveMonitor_output_connector_decoder_cmd_valid; + wire system_fabric_exclusiveMonitor_output_connector_decoder_cmd_ready; + wire system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_last; + wire [0:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_opcode; + wire [31:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_address; + wire [5:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_length; + wire [31:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_data; + wire [3:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_mask; + wire [0:0] system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_context; + wire system_fabric_exclusiveMonitor_output_connector_decoder_rsp_valid; + wire system_fabric_exclusiveMonitor_output_connector_decoder_rsp_ready; + wire system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_last; + wire [0:0] system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_opcode; + wire [31:0] system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_data; + wire [0:0] system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_context; + wire system_fabric_dBus_bmb_cmd_valid; + wire system_fabric_dBus_bmb_cmd_ready; + wire system_fabric_dBus_bmb_cmd_payload_last; + wire [0:0] system_fabric_dBus_bmb_cmd_payload_fragment_opcode; + wire [31:0] system_fabric_dBus_bmb_cmd_payload_fragment_address; + wire [5:0] system_fabric_dBus_bmb_cmd_payload_fragment_length; + wire [31:0] system_fabric_dBus_bmb_cmd_payload_fragment_data; + wire [3:0] system_fabric_dBus_bmb_cmd_payload_fragment_mask; + wire [0:0] system_fabric_dBus_bmb_cmd_payload_fragment_context; + wire system_fabric_dBus_bmb_rsp_valid; + wire system_fabric_dBus_bmb_rsp_ready; + wire system_fabric_dBus_bmb_rsp_payload_last; + wire [0:0] system_fabric_dBus_bmb_rsp_payload_fragment_opcode; + wire [31:0] system_fabric_dBus_bmb_rsp_payload_fragment_data; + wire [0:0] system_fabric_dBus_bmb_rsp_payload_fragment_context; + wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [31:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [5:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + wire [0:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [0:0] system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_fabric_iBus_bmb_cmd_m2sPipe_valid; + wire system_fabric_iBus_bmb_cmd_m2sPipe_ready; + wire system_fabric_iBus_bmb_cmd_m2sPipe_payload_last; + wire [0:0] system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_opcode; + wire [31:0] system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_address; + wire [5:0] system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_length; + reg system_fabric_iBus_bmb_cmd_rValid; + reg system_fabric_iBus_bmb_cmd_rData_last; + reg [0:0] system_fabric_iBus_bmb_cmd_rData_fragment_opcode; + reg [31:0] system_fabric_iBus_bmb_cmd_rData_fragment_address; + reg [5:0] system_fabric_iBus_bmb_cmd_rData_fragment_length; + wire when_Stream_l368_4; + wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid; + wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready; + wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last; + wire [0:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address; + wire [5:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length; + wire [31:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data; + wire [3:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask; + wire [0:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context; + wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid; + wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready; + wire system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last; + wire [0:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data; + wire [0:0] system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context; + wire system_bridge_bmb_cmd_valid; + wire system_bridge_bmb_cmd_ready; + wire system_bridge_bmb_cmd_payload_last; + wire [0:0] system_bridge_bmb_cmd_payload_fragment_source; + wire [0:0] system_bridge_bmb_cmd_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_cmd_payload_fragment_address; + wire [5:0] system_bridge_bmb_cmd_payload_fragment_length; + wire [31:0] system_bridge_bmb_cmd_payload_fragment_data; + wire [3:0] system_bridge_bmb_cmd_payload_fragment_mask; + wire [0:0] system_bridge_bmb_cmd_payload_fragment_context; + wire system_bridge_bmb_rsp_valid; + wire system_bridge_bmb_rsp_ready; + wire system_bridge_bmb_rsp_payload_last; + wire [0:0] system_bridge_bmb_rsp_payload_fragment_source; + wire [0:0] system_bridge_bmb_rsp_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_rsp_payload_fragment_data; + wire [0:0] system_bridge_bmb_rsp_payload_fragment_context; + wire system_bridge_bmb_cmd_s2mPipe_valid; + reg system_bridge_bmb_cmd_s2mPipe_ready; + wire system_bridge_bmb_cmd_s2mPipe_payload_last; + wire [0:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_source; + wire [0:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_address; + wire [5:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_length; + wire [31:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_data; + wire [3:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_mask; + wire [0:0] system_bridge_bmb_cmd_s2mPipe_payload_fragment_context; + reg system_bridge_bmb_cmd_rValid; + reg system_bridge_bmb_cmd_rData_last; + reg [0:0] system_bridge_bmb_cmd_rData_fragment_source; + reg [0:0] system_bridge_bmb_cmd_rData_fragment_opcode; + reg [31:0] system_bridge_bmb_cmd_rData_fragment_address; + reg [5:0] system_bridge_bmb_cmd_rData_fragment_length; + reg [31:0] system_bridge_bmb_cmd_rData_fragment_data; + reg [3:0] system_bridge_bmb_cmd_rData_fragment_mask; + reg [0:0] system_bridge_bmb_cmd_rData_fragment_context; + wire system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid; + wire system_bridge_bmb_cmd_s2mPipe_m2sPipe_ready; + wire system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_last; + wire [0:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_source; + wire [0:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_opcode; + wire [31:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_address; + wire [5:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_length; + wire [31:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_data; + wire [3:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_mask; + wire [0:0] system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_context; + reg system_bridge_bmb_cmd_s2mPipe_rValid; + reg system_bridge_bmb_cmd_s2mPipe_rData_last; + reg [0:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_source; + reg [0:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_opcode; + reg [31:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_address; + reg [5:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_length; + reg [31:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_data; + reg [3:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_mask; + reg [0:0] system_bridge_bmb_cmd_s2mPipe_rData_fragment_context; + wire when_Stream_l368_5; + wire system_bmbPeripheral_bmb_cmd_valid; + wire system_bmbPeripheral_bmb_cmd_ready; + wire system_bmbPeripheral_bmb_cmd_payload_last; + wire [0:0] system_bmbPeripheral_bmb_cmd_payload_fragment_opcode; + wire [23:0] system_bmbPeripheral_bmb_cmd_payload_fragment_address; + wire [1:0] system_bmbPeripheral_bmb_cmd_payload_fragment_length; + wire [31:0] system_bmbPeripheral_bmb_cmd_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_cmd_payload_fragment_mask; + wire [3:0] system_bmbPeripheral_bmb_cmd_payload_fragment_context; + wire system_bmbPeripheral_bmb_rsp_valid; + wire system_bmbPeripheral_bmb_rsp_ready; + wire system_bmbPeripheral_bmb_rsp_payload_last; + wire [0:0] system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; + wire [31:0] system_bmbPeripheral_bmb_rsp_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_rsp_payload_fragment_context; + wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [23:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + wire [3:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [14:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + wire [3:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [3:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + reg _zz_io_bus_rsp_ready; + wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_valid; + wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_ready; + wire system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_last; + wire [0:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_opcode; + wire [14:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_address; + wire [1:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_length; + wire [31:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_data; + wire [3:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_mask; + wire [3:0] system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_context; + wire _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + reg _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + reg _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + reg [0:0] _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + reg [31:0] _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + reg [3:0] _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire when_Stream_l368_6; + wire _zz_io_input_rsp_ready_1; + wire system_bmbPeripheral_bmb_cmd_combStage_valid; + wire system_bmbPeripheral_bmb_cmd_combStage_ready; + wire system_bmbPeripheral_bmb_cmd_combStage_payload_last; + wire [0:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_opcode; + wire [23:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_address; + wire [1:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_length; + wire [31:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_mask; + wire [3:0] system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_context; + wire _zz_system_bmbPeripheral_bmb_rsp_valid; + reg _zz_system_bmbPeripheral_bmb_rsp_valid_1; + reg _zz_system_bmbPeripheral_bmb_rsp_payload_last; + reg [0:0] _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; + reg [31:0] _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_data; + reg [3:0] _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_context; + wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [15:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [3:0] system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + reg _zz_timerInterrupt; + reg _zz_softwareInterrupt; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [3:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire _zz_io_bus_rsp_ready_1; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last; + wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode; + wire [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address; + wire [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length; + wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data; + wire [3:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context; + reg system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire; + reg system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + reg [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + reg [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + reg [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + reg [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + reg [3:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + wire _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + reg _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + reg _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + reg [0:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + reg [31:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + reg [3:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire [1:0] system_uart_0_io_interrupt_plic_gateway_priority; + reg system_uart_0_io_interrupt_plic_gateway_ip; + reg system_uart_0_io_interrupt_plic_gateway_waitCompletion; + wire when_PlicGateway_l21; + wire [1:0] system_spi_0_io_interrupt_plic_gateway_priority; + reg system_spi_0_io_interrupt_plic_gateway_ip; + reg system_spi_0_io_interrupt_plic_gateway_waitCompletion; + wire when_PlicGateway_l21_1; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [3:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last; + wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode; + wire [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address; + wire [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length; + wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data; + wire [3:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context; + reg system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire; + reg system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + reg [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + reg [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + reg [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + reg [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + reg [3:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [15:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [3:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_bmbPeripheral_bmb_withoutMask_cmd_valid; + wire system_bmbPeripheral_bmb_withoutMask_cmd_ready; + wire system_bmbPeripheral_bmb_withoutMask_cmd_payload_last; + wire [0:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode; + wire [23:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address; + wire [1:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length; + wire [31:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context; + wire system_bmbPeripheral_bmb_withoutMask_rsp_valid; + wire system_bmbPeripheral_bmb_withoutMask_rsp_ready; + wire system_bmbPeripheral_bmb_withoutMask_rsp_payload_last; + wire [0:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode; + wire [31:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data; + wire [3:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context; + wire system_bmbPeripheral_bmb_withoutMask_cmd_valid_1; + wire system_bmbPeripheral_bmb_withoutMask_cmd_ready_1; + wire system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_1; + wire [0:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1; + wire [23:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1; + wire [1:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1; + wire [31:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1; + wire [3:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1; + wire system_bmbPeripheral_bmb_withoutMask_rsp_valid_1; + wire system_bmbPeripheral_bmb_withoutMask_rsp_ready_1; + wire system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_1; + wire [0:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1; + wire [31:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1; + wire [3:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1; + wire system_plic_logic_bmb_cmd_valid; + wire system_plic_logic_bmb_cmd_ready; + wire system_plic_logic_bmb_cmd_payload_last; + wire [0:0] system_plic_logic_bmb_cmd_payload_fragment_opcode; + wire [21:0] system_plic_logic_bmb_cmd_payload_fragment_address; + wire [1:0] system_plic_logic_bmb_cmd_payload_fragment_length; + wire [31:0] system_plic_logic_bmb_cmd_payload_fragment_data; + wire [3:0] system_plic_logic_bmb_cmd_payload_fragment_context; + wire system_plic_logic_bmb_rsp_valid; + wire system_plic_logic_bmb_rsp_ready; + wire system_plic_logic_bmb_rsp_payload_last; + wire [0:0] system_plic_logic_bmb_rsp_payload_fragment_opcode; + wire [31:0] system_plic_logic_bmb_rsp_payload_fragment_data; + wire [3:0] system_plic_logic_bmb_rsp_payload_fragment_context; + reg system_plic_logic_bus_readHaltTrigger; + wire system_plic_logic_bus_writeHaltTrigger; + wire system_plic_logic_bus_rsp_valid; + wire system_plic_logic_bus_rsp_ready; + wire system_plic_logic_bus_rsp_payload_last; + wire [0:0] system_plic_logic_bus_rsp_payload_fragment_opcode; + reg [31:0] system_plic_logic_bus_rsp_payload_fragment_data; + wire [3:0] system_plic_logic_bus_rsp_payload_fragment_context; + wire _zz_system_plic_logic_bmb_rsp_valid; + reg _zz_system_plic_logic_bus_rsp_ready; + wire _zz_system_plic_logic_bmb_rsp_valid_1; + reg _zz_system_plic_logic_bmb_rsp_valid_2; + reg _zz_system_plic_logic_bmb_rsp_payload_last; + reg [0:0] _zz_system_plic_logic_bmb_rsp_payload_fragment_opcode; + reg [31:0] _zz_system_plic_logic_bmb_rsp_payload_fragment_data; + reg [3:0] _zz_system_plic_logic_bmb_rsp_payload_fragment_context; + wire when_Stream_l368_7; + wire system_plic_logic_bus_askWrite; + wire system_plic_logic_bus_askRead; + wire system_plic_logic_bmb_cmd_fire; + wire system_plic_logic_bus_doWrite; + wire system_plic_logic_bmb_cmd_fire_1; + wire system_plic_logic_bus_doRead; + wire system_cores_0_externalInterrupt_plic_target_ie_0; + wire system_cores_0_externalInterrupt_plic_target_ie_1; + wire [1:0] system_cores_0_externalInterrupt_plic_target_threshold; + wire [1:0] system_cores_0_externalInterrupt_plic_target_requests_0_priority; + wire [2:0] system_cores_0_externalInterrupt_plic_target_requests_0_id; + wire system_cores_0_externalInterrupt_plic_target_requests_0_valid; + wire [1:0] system_cores_0_externalInterrupt_plic_target_requests_1_priority; + wire [2:0] system_cores_0_externalInterrupt_plic_target_requests_1_id; + wire system_cores_0_externalInterrupt_plic_target_requests_1_valid; + wire [1:0] system_cores_0_externalInterrupt_plic_target_requests_2_priority; + wire [2:0] system_cores_0_externalInterrupt_plic_target_requests_2_id; + wire system_cores_0_externalInterrupt_plic_target_requests_2_valid; + wire _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority; + wire [1:0] _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1; + wire _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2; + wire _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3; + reg [1:0] system_cores_0_externalInterrupt_plic_target_bestRequest_priority; + reg [2:0] system_cores_0_externalInterrupt_plic_target_bestRequest_id; + reg system_cores_0_externalInterrupt_plic_target_bestRequest_valid; + wire system_cores_0_externalInterrupt_plic_target_iep; + wire [2:0] system_cores_0_externalInterrupt_plic_target_claim; + reg [1:0] _zz_system_uart_0_io_interrupt_plic_gateway_priority; + reg [1:0] _zz_system_spi_0_io_interrupt_plic_gateway_priority; + reg system_plic_logic_bridge_claim_valid; + reg [2:0] system_plic_logic_bridge_claim_payload; + reg system_plic_logic_bridge_completion_valid; + reg [2:0] system_plic_logic_bridge_completion_payload; + reg system_plic_logic_bridge_coherencyStall_willIncrement; + wire system_plic_logic_bridge_coherencyStall_willClear; + reg [0:0] system_plic_logic_bridge_coherencyStall_valueNext; + reg [0:0] system_plic_logic_bridge_coherencyStall_value; + wire system_plic_logic_bridge_coherencyStall_willOverflowIfInc; + wire system_plic_logic_bridge_coherencyStall_willOverflow; + wire when_PlicMapper_l122; + reg [1:0] _zz_system_cores_0_externalInterrupt_plic_target_threshold; + reg system_plic_logic_bridge_targetMapping_0_targetCompletion_valid; + wire [2:0] system_plic_logic_bridge_targetMapping_0_targetCompletion_payload; + reg _zz_system_cores_0_externalInterrupt_plic_target_ie_0; + reg _zz_system_cores_0_externalInterrupt_plic_target_ie_1; + reg system_cores_0_externalInterrupt_plic_target_iep_regNext; + wire system_bmbPeripheral_bmb_withoutMask_cmd_valid_2; + wire system_bmbPeripheral_bmb_withoutMask_cmd_ready_2; + wire system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_2; + wire [0:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2; + wire [23:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2; + wire [1:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2; + wire [31:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2; + wire [3:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2; + wire system_bmbPeripheral_bmb_withoutMask_rsp_valid_2; + wire system_bmbPeripheral_bmb_withoutMask_rsp_ready_2; + wire system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_2; + wire [0:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2; + wire [31:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2; + wire [3:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2; + wire system_bmbPeripheral_bmb_withoutMask_cmd_valid_3; + wire system_bmbPeripheral_bmb_withoutMask_cmd_ready_3; + wire system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_3; + wire [0:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3; + wire [23:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3; + wire [1:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3; + wire [31:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3; + wire [3:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3; + wire system_bmbPeripheral_bmb_withoutMask_rsp_valid_3; + wire system_bmbPeripheral_bmb_withoutMask_rsp_ready_3; + wire system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_3; + wire [0:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3; + wire [31:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3; + wire [3:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3; + wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [21:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [3:0] system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_bmbPeripheral_bmb_withoutMask_cmd_valid_4; + wire system_bmbPeripheral_bmb_withoutMask_cmd_ready_4; + wire system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_4; + wire [0:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4; + wire [23:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4; + wire [1:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4; + wire [31:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4; + wire [3:0] system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4; + wire system_bmbPeripheral_bmb_withoutMask_rsp_valid_4; + wire system_bmbPeripheral_bmb_withoutMask_rsp_ready_4; + wire system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_4; + wire [0:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4; + wire [31:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4; + wire [3:0] system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4; + wire when_BmbSlaveFactory_l71; + + assign _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address = (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address >>> 2); + assign _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask_1 = ({3'd0,_zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask} <<< system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address[1 : 0]); + BufferCC_2 bufferCC_5 ( + .io_dataIn (1'b0 ), //i + .io_dataOut (bufferCC_5_io_dataOut), //o + .io_systemClk (io_systemClk ), //i + .io_asyncReset (io_asyncReset ) //i + ); + BufferCC_3 bufferCC_6 ( + .io_dataIn (1'b0 ), //i + .io_dataOut (bufferCC_6_io_dataOut ), //o + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset) //i + ); + VexRiscv system_cores_0_logic_cpu ( + .dBus_cmd_valid (system_cores_0_logic_cpu_dBus_cmd_valid ), //o + .dBus_cmd_ready (system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready ), //i + .dBus_cmd_payload_wr (system_cores_0_logic_cpu_dBus_cmd_payload_wr ), //o + .dBus_cmd_payload_uncached (system_cores_0_logic_cpu_dBus_cmd_payload_uncached ), //o + .dBus_cmd_payload_address (system_cores_0_logic_cpu_dBus_cmd_payload_address[31:0] ), //o + .dBus_cmd_payload_data (system_cores_0_logic_cpu_dBus_cmd_payload_data[31:0] ), //o + .dBus_cmd_payload_mask (system_cores_0_logic_cpu_dBus_cmd_payload_mask[3:0] ), //o + .dBus_cmd_payload_size (system_cores_0_logic_cpu_dBus_cmd_payload_size[2:0] ), //o + .dBus_cmd_payload_last (system_cores_0_logic_cpu_dBus_cmd_payload_last ), //o + .dBus_rsp_valid (system_cores_0_logic_cpu_dBus_rsp_valid ), //i + .dBus_rsp_payload_last (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_last ), //i + .dBus_rsp_payload_data (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_data[31:0]), //i + .dBus_rsp_payload_error (system_cores_0_logic_cpu_dBus_rsp_payload_error ), //i + .timerInterrupt (_zz_timerInterrupt ), //i + .externalInterrupt (system_cores_0_externalInterrupt_plic_target_iep_regNext ), //i + .softwareInterrupt (_zz_softwareInterrupt ), //i + .debug_bus_cmd_valid (system_cores_0_debugBmb_cmd_valid ), //i + .debug_bus_cmd_ready (system_cores_0_logic_cpu_debug_bus_cmd_ready ), //o + .debug_bus_cmd_payload_wr (system_cores_0_logic_cpu_debug_bus_cmd_payload_wr ), //i + .debug_bus_cmd_payload_address (system_cores_0_debugBmb_cmd_payload_fragment_address[7:0] ), //i + .debug_bus_cmd_payload_data (system_cores_0_debugBmb_cmd_payload_fragment_data[31:0] ), //i + .debug_bus_rsp_data (system_cores_0_logic_cpu_debug_bus_rsp_data[31:0] ), //o + .debug_resetOut (system_cores_0_logic_cpu_debug_resetOut ), //o + .iBus_cmd_valid (system_cores_0_logic_cpu_iBus_cmd_valid ), //o + .iBus_cmd_ready (system_cores_0_iBus_cmd_ready ), //i + .iBus_cmd_payload_address (system_cores_0_logic_cpu_iBus_cmd_payload_address[31:0] ), //o + .iBus_cmd_payload_size (system_cores_0_logic_cpu_iBus_cmd_payload_size[2:0] ), //o + .iBus_rsp_valid (system_cores_0_iBus_rsp_valid ), //i + .iBus_rsp_payload_data (system_cores_0_iBus_rsp_payload_fragment_data[31:0] ), //i + .iBus_rsp_payload_error (system_cores_0_logic_cpu_iBus_rsp_payload_error ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i + ); + JtagBridgeNoTap system_hardJtag_debug_logic_jtagBridge ( + .io_ctrl_tdi (jtagCtrl_tdi ), //i + .io_ctrl_enable (jtagCtrl_enable ), //i + .io_ctrl_capture (jtagCtrl_capture ), //i + .io_ctrl_shift (jtagCtrl_shift ), //i + .io_ctrl_update (jtagCtrl_update ), //i + .io_ctrl_reset (jtagCtrl_reset ), //i + .io_ctrl_tdo (system_hardJtag_debug_logic_jtagBridge_io_ctrl_tdo ), //o + .io_remote_cmd_valid (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_valid ), //o + .io_remote_cmd_ready (system_hardJtag_debug_logic_debugger_io_remote_cmd_ready ), //i + .io_remote_cmd_payload_last (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_last ), //o + .io_remote_cmd_payload_fragment (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_fragment), //o + .io_remote_rsp_valid (system_hardJtag_debug_logic_debugger_io_remote_rsp_valid ), //i + .io_remote_rsp_ready (system_hardJtag_debug_logic_jtagBridge_io_remote_rsp_ready ), //o + .io_remote_rsp_payload_error (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_error ), //i + .io_remote_rsp_payload_data (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_data[31:0]), //i + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ), //i + .jtagCtrl_tck (jtagCtrl_tck ) //i + ); + SystemDebugger system_hardJtag_debug_logic_debugger ( + .io_remote_cmd_valid (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_valid ), //i + .io_remote_cmd_ready (system_hardJtag_debug_logic_debugger_io_remote_cmd_ready ), //o + .io_remote_cmd_payload_last (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_last ), //i + .io_remote_cmd_payload_fragment (system_hardJtag_debug_logic_jtagBridge_io_remote_cmd_payload_fragment), //i + .io_remote_rsp_valid (system_hardJtag_debug_logic_debugger_io_remote_rsp_valid ), //o + .io_remote_rsp_ready (system_hardJtag_debug_logic_jtagBridge_io_remote_rsp_ready ), //i + .io_remote_rsp_payload_error (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_error ), //o + .io_remote_rsp_payload_data (system_hardJtag_debug_logic_debugger_io_remote_rsp_payload_data[31:0]), //o + .io_mem_cmd_valid (system_hardJtag_debug_logic_debugger_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (system_hardJtag_debug_logic_mmMaster_cmd_ready ), //i + .io_mem_cmd_payload_address (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_address[31:0]), //o + .io_mem_cmd_payload_data (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_wr (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_size (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_size[1:0] ), //o + .io_mem_rsp_valid (system_hardJtag_debug_logic_mmMaster_rsp_valid ), //i + .io_mem_rsp_payload (system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_data[31:0] ), //i + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i + ); + BufferCC_4 bufferCC_7 ( + .io_dataIn (1'b0 ), //i + .io_dataOut (bufferCC_7_io_dataOut ), //o + .io_systemClk (io_systemClk ), //i + .system_cores_0_debugReset (system_cores_0_debugReset) //i + ); + BmbDecoder bmbDecoder_4 ( + .io_input_cmd_valid (system_hardJtag_debug_bmb_connector_decoder_cmd_valid ), //i + .io_input_cmd_ready (bmbDecoder_4_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_length[1:0] ), //i + .io_input_cmd_payload_fragment_data (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_mask[3:0] ), //i + .io_input_rsp_valid (bmbDecoder_4_io_input_rsp_valid ), //o + .io_input_rsp_ready (system_hardJtag_debug_bmb_connector_decoder_rsp_ready ), //i + .io_input_rsp_payload_last (bmbDecoder_4_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (bmbDecoder_4_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (bmbDecoder_4_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_valid (bmbDecoder_4_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i + .io_outputs_0_cmd_payload_last (bmbDecoder_4_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_opcode (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_address[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_length (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_0_cmd_payload_fragment_data (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_mask (bmbDecoder_4_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_0_rsp_valid (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i + .io_outputs_0_rsp_ready (bmbDecoder_4_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i + .io_outputs_0_rsp_payload_fragment_opcode (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i + .io_outputs_0_rsp_payload_fragment_data (system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0]), //i + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i + ); + BmbExclusiveMonitor system_fabric_exclusiveMonitor_logic ( + .io_input_cmd_valid (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid ), //i + .io_input_cmd_ready (system_fabric_exclusiveMonitor_logic_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_address[31:0]), //i + .io_input_cmd_payload_fragment_length (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_length[5:0] ), //i + .io_input_cmd_payload_fragment_data (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_context ), //i + .io_input_rsp_valid (system_fabric_exclusiveMonitor_logic_io_input_rsp_valid ), //o + .io_input_rsp_ready (_zz_io_input_rsp_ready ), //i + .io_input_rsp_payload_last (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_context ), //o + .io_output_cmd_valid (system_fabric_exclusiveMonitor_logic_io_output_cmd_valid ), //o + .io_output_cmd_ready (system_fabric_exclusiveMonitor_output_connector_decoder_cmd_ready ), //i + .io_output_cmd_payload_last (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_length[5:0] ), //o + .io_output_cmd_payload_fragment_data (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_data[31:0] ), //o + .io_output_cmd_payload_fragment_mask (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_mask[3:0] ), //o + .io_output_cmd_payload_fragment_context (system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_context ), //o + .io_output_rsp_valid (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_valid ), //i + .io_output_rsp_ready (system_fabric_exclusiveMonitor_logic_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_data[31:0] ), //i + .io_output_rsp_payload_fragment_context (system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_context ) //i + ); + BmbDecoder_1 system_fabric_iBus_bmb_decoder ( + .io_input_cmd_valid (system_fabric_iBus_bmb_cmd_m2sPipe_valid ), //i + .io_input_cmd_ready (system_fabric_iBus_bmb_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_fabric_iBus_bmb_cmd_m2sPipe_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_length[5:0] ), //i + .io_input_rsp_valid (system_fabric_iBus_bmb_decoder_io_input_rsp_valid ), //o + .io_input_rsp_ready (system_fabric_iBus_bmb_rsp_ready ), //i + .io_input_rsp_payload_last (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_valid (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (system_bridge_bmb_arbiter_io_inputs_1_cmd_ready ), //i + .io_outputs_0_cmd_payload_last (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0]), //o + .io_outputs_0_cmd_payload_fragment_length (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //o + .io_outputs_0_rsp_valid (system_bridge_bmb_arbiter_io_inputs_1_rsp_valid ), //i + .io_outputs_0_rsp_ready (system_fabric_iBus_bmb_decoder_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_last ), //i + .io_outputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //i + .io_outputs_0_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_data[31:0] ) //i + ); + BmbArbiter system_bridge_bmb_arbiter ( + .io_inputs_0_cmd_valid (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid ), //i + .io_inputs_0_cmd_ready (system_bridge_bmb_arbiter_io_inputs_0_cmd_ready ), //o + .io_inputs_0_cmd_payload_last (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last ), //i + .io_inputs_0_cmd_payload_fragment_opcode (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode ), //i + .io_inputs_0_cmd_payload_fragment_address (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address[31:0]), //i + .io_inputs_0_cmd_payload_fragment_length (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length[5:0] ), //i + .io_inputs_0_cmd_payload_fragment_data (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data[31:0] ), //i + .io_inputs_0_cmd_payload_fragment_mask (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask[3:0] ), //i + .io_inputs_0_cmd_payload_fragment_context (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context ), //i + .io_inputs_0_rsp_valid (system_bridge_bmb_arbiter_io_inputs_0_rsp_valid ), //o + .io_inputs_0_rsp_ready (system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready ), //i + .io_inputs_0_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_last ), //o + .io_inputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_opcode ), //o + .io_inputs_0_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_data[31:0] ), //o + .io_inputs_0_rsp_payload_fragment_context (system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_context ), //o + .io_inputs_1_cmd_valid (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_valid ), //i + .io_inputs_1_cmd_ready (system_bridge_bmb_arbiter_io_inputs_1_cmd_ready ), //o + .io_inputs_1_cmd_payload_last (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_last ), //i + .io_inputs_1_cmd_payload_fragment_opcode (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //i + .io_inputs_1_cmd_payload_fragment_address (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_1_cmd_payload_fragment_length (system_fabric_iBus_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //i + .io_inputs_1_cmd_payload_fragment_data (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ), //i + .io_inputs_1_cmd_payload_fragment_mask (4'bxxxx ), //i + .io_inputs_1_rsp_valid (system_bridge_bmb_arbiter_io_inputs_1_rsp_valid ), //o + .io_inputs_1_rsp_ready (system_fabric_iBus_bmb_decoder_io_outputs_0_rsp_ready ), //i + .io_inputs_1_rsp_payload_last (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_last ), //o + .io_inputs_1_rsp_payload_fragment_opcode (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //o + .io_inputs_1_rsp_payload_fragment_data (system_bridge_bmb_arbiter_io_inputs_1_rsp_payload_fragment_data[31:0] ), //o + .io_output_cmd_valid (system_bridge_bmb_arbiter_io_output_cmd_valid ), //o + .io_output_cmd_ready (system_bridge_bmb_cmd_ready ), //i + .io_output_cmd_payload_last (system_bridge_bmb_arbiter_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_source (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_source ), //o + .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_length[5:0] ), //o + .io_output_cmd_payload_fragment_data (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_data[31:0] ), //o + .io_output_cmd_payload_fragment_mask (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_mask[3:0] ), //o + .io_output_cmd_payload_fragment_context (system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_context ), //o + .io_output_rsp_valid (system_bridge_bmb_rsp_valid ), //i + .io_output_rsp_ready (system_bridge_bmb_arbiter_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (system_bridge_bmb_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_source (system_bridge_bmb_rsp_payload_fragment_source ), //i + .io_output_rsp_payload_fragment_opcode (system_bridge_bmb_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (system_bridge_bmb_rsp_payload_fragment_data[31:0] ), //i + .io_output_rsp_payload_fragment_context (system_bridge_bmb_rsp_payload_fragment_context ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbDecoder_2 system_bridge_bmb_decoder ( + .io_input_cmd_valid (system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid ), //i + .io_input_cmd_ready (system_bridge_bmb_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_last ), //i + .io_input_cmd_payload_fragment_source (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_length[5:0] ), //i + .io_input_cmd_payload_fragment_data (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_context ), //i + .io_input_rsp_valid (system_bridge_bmb_decoder_io_input_rsp_valid ), //o + .io_input_rsp_ready (system_bridge_bmb_rsp_ready ), //i + .io_input_rsp_payload_last (system_bridge_bmb_decoder_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (system_bridge_bmb_decoder_io_input_rsp_payload_fragment_context ), //o + .io_outputs_0_cmd_valid (system_bridge_bmb_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (system_bridge_bmb_unburstify_1_io_input_cmd_ready ), //i + .io_outputs_0_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_source ), //o + .io_outputs_0_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0]), //o + .io_outputs_0_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //o + .io_outputs_0_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_0_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_context ), //o + .io_outputs_0_rsp_valid (system_bridge_bmb_unburstify_1_io_input_rsp_valid ), //i + .io_outputs_0_rsp_ready (system_bridge_bmb_decoder_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (system_bridge_bmb_unburstify_1_io_input_rsp_payload_last ), //i + .io_outputs_0_rsp_payload_fragment_source (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_source ), //i + .io_outputs_0_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_opcode ), //i + .io_outputs_0_rsp_payload_fragment_data (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_data[31:0] ), //i + .io_outputs_0_rsp_payload_fragment_context (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_context ), //i + .io_outputs_1_cmd_valid (system_bridge_bmb_decoder_io_outputs_1_cmd_valid ), //o + .io_outputs_1_cmd_ready (system_bridge_bmb_unburstify_io_input_cmd_ready ), //i + .io_outputs_1_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_last ), //o + .io_outputs_1_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_source ), //o + .io_outputs_1_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //o + .io_outputs_1_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[31:0]), //o + .io_outputs_1_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[5:0] ), //o + .io_outputs_1_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_1_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_1_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_context ), //o + .io_outputs_1_rsp_valid (system_bridge_bmb_unburstify_io_input_rsp_valid ), //i + .io_outputs_1_rsp_ready (system_bridge_bmb_decoder_io_outputs_1_rsp_ready ), //o + .io_outputs_1_rsp_payload_last (system_bridge_bmb_unburstify_io_input_rsp_payload_last ), //i + .io_outputs_1_rsp_payload_fragment_source (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_source ), //i + .io_outputs_1_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_opcode ), //i + .io_outputs_1_rsp_payload_fragment_data (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //i + .io_outputs_1_rsp_payload_fragment_context (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_context ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbOnChipRam system_ramA_logic ( + .io_bus_cmd_valid (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_valid ), //i + .io_bus_cmd_ready (system_ramA_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_address[14:0]), //i + .io_bus_cmd_payload_fragment_length (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_mask (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_mask[3:0] ), //i + .io_bus_cmd_payload_fragment_context (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_context[3:0] ), //i + .io_bus_rsp_valid (system_ramA_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (_zz_io_bus_rsp_ready ), //i + .io_bus_rsp_payload_last (system_ramA_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_ramA_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_ramA_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_ramA_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbUnburstify system_bridge_bmb_unburstify ( + .io_input_cmd_valid (system_bridge_bmb_decoder_io_outputs_1_cmd_valid ), //i + .io_input_cmd_ready (system_bridge_bmb_unburstify_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[5:0] ), //i + .io_input_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_1_cmd_payload_fragment_context ), //i + .io_input_rsp_valid (system_bridge_bmb_unburstify_io_input_rsp_valid ), //o + .io_input_rsp_ready (system_bridge_bmb_decoder_io_outputs_1_rsp_ready ), //i + .io_input_rsp_payload_last (system_bridge_bmb_unburstify_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (system_bridge_bmb_unburstify_io_input_rsp_payload_fragment_context ), //o + .io_output_cmd_valid (system_bridge_bmb_unburstify_io_output_cmd_valid ), //o + .io_output_cmd_ready (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i + .io_output_cmd_payload_last (system_bridge_bmb_unburstify_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_length[1:0] ), //o + .io_output_cmd_payload_fragment_data (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_data[31:0] ), //o + .io_output_cmd_payload_fragment_mask (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_mask[3:0] ), //o + .io_output_cmd_payload_fragment_context (system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_context[3:0] ), //o + .io_output_rsp_valid (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i + .io_output_rsp_ready (system_bridge_bmb_unburstify_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0] ), //i + .io_output_rsp_payload_fragment_context (system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context[3:0]), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbUnburstify system_bridge_bmb_unburstify_1 ( + .io_input_cmd_valid (system_bridge_bmb_decoder_io_outputs_0_cmd_valid ), //i + .io_input_cmd_ready (system_bridge_bmb_unburstify_1_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[5:0] ), //i + .io_input_cmd_payload_fragment_data (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (system_bridge_bmb_decoder_io_outputs_0_cmd_payload_fragment_context ), //i + .io_input_rsp_valid (system_bridge_bmb_unburstify_1_io_input_rsp_valid ), //o + .io_input_rsp_ready (system_bridge_bmb_decoder_io_outputs_0_rsp_ready ), //i + .io_input_rsp_payload_last (system_bridge_bmb_unburstify_1_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (system_bridge_bmb_unburstify_1_io_input_rsp_payload_fragment_context ), //o + .io_output_cmd_valid (system_bridge_bmb_unburstify_1_io_output_cmd_valid ), //o + .io_output_cmd_ready (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i + .io_output_cmd_payload_last (system_bridge_bmb_unburstify_1_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_length[1:0] ), //o + .io_output_cmd_payload_fragment_data (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_data[31:0] ), //o + .io_output_cmd_payload_fragment_mask (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_mask[3:0] ), //o + .io_output_cmd_payload_fragment_context (system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_context[3:0] ), //o + .io_output_rsp_valid (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i + .io_output_rsp_ready (system_bridge_bmb_unburstify_1_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0] ), //i + .io_output_rsp_payload_fragment_context (system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context[3:0]), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbDecoder_3 system_bmbPeripheral_bmb_decoder ( + .io_input_cmd_valid (system_bmbPeripheral_bmb_cmd_combStage_valid ), //i + .io_input_cmd_ready (system_bmbPeripheral_bmb_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (system_bmbPeripheral_bmb_cmd_combStage_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_address[23:0] ), //i + .io_input_cmd_payload_fragment_length (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_length[1:0] ), //i + .io_input_cmd_payload_fragment_data (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_context[3:0] ), //i + .io_input_rsp_valid (system_bmbPeripheral_bmb_decoder_io_input_rsp_valid ), //o + .io_input_rsp_ready (_zz_io_input_rsp_ready_1 ), //i + .io_input_rsp_payload_last (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context[3:0] ), //o + .io_outputs_0_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_4 ), //i + .io_outputs_0_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[23:0]), //o + .io_outputs_0_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_0_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_0_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context[3:0] ), //o + .io_outputs_0_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_4 ), //i + .io_outputs_0_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 ), //i + .io_outputs_0_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 ), //i + .io_outputs_0_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4[31:0] ), //i + .io_outputs_0_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4[3:0] ), //i + .io_outputs_1_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid ), //o + .io_outputs_1_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready ), //i + .io_outputs_1_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last ), //o + .io_outputs_1_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //o + .io_outputs_1_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[23:0]), //o + .io_outputs_1_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_1_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_1_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_1_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context[3:0] ), //o + .io_outputs_1_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid ), //i + .io_outputs_1_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready ), //o + .io_outputs_1_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last ), //i + .io_outputs_1_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode ), //i + .io_outputs_1_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data[31:0] ), //i + .io_outputs_1_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context[3:0] ), //i + .io_outputs_2_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid ), //o + .io_outputs_2_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_1 ), //i + .io_outputs_2_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last ), //o + .io_outputs_2_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode ), //o + .io_outputs_2_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address[23:0]), //o + .io_outputs_2_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_2_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_2_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_2_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context[3:0] ), //o + .io_outputs_2_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_1 ), //i + .io_outputs_2_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready ), //o + .io_outputs_2_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 ), //i + .io_outputs_2_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 ), //i + .io_outputs_2_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1[31:0] ), //i + .io_outputs_2_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1[3:0] ), //i + .io_outputs_3_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid ), //o + .io_outputs_3_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_2 ), //i + .io_outputs_3_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last ), //o + .io_outputs_3_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode ), //o + .io_outputs_3_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address[23:0]), //o + .io_outputs_3_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_3_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_3_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_3_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context[3:0] ), //o + .io_outputs_3_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_2 ), //i + .io_outputs_3_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready ), //o + .io_outputs_3_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 ), //i + .io_outputs_3_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 ), //i + .io_outputs_3_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2[31:0] ), //i + .io_outputs_3_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2[3:0] ), //i + .io_outputs_4_cmd_valid (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid ), //o + .io_outputs_4_cmd_ready (system_bmbPeripheral_bmb_withoutMask_cmd_ready_3 ), //i + .io_outputs_4_cmd_payload_last (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last ), //o + .io_outputs_4_cmd_payload_fragment_opcode (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode ), //o + .io_outputs_4_cmd_payload_fragment_address (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address[23:0]), //o + .io_outputs_4_cmd_payload_fragment_length (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_4_cmd_payload_fragment_data (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_4_cmd_payload_fragment_mask (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_4_cmd_payload_fragment_context (system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context[3:0] ), //o + .io_outputs_4_rsp_valid (system_bmbPeripheral_bmb_withoutMask_rsp_valid_3 ), //i + .io_outputs_4_rsp_ready (system_bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready ), //o + .io_outputs_4_rsp_payload_last (system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 ), //i + .io_outputs_4_rsp_payload_fragment_opcode (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 ), //i + .io_outputs_4_rsp_payload_fragment_data (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3[31:0] ), //i + .io_outputs_4_rsp_payload_fragment_context (system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3[3:0] ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbClint system_clint_logic ( + .io_bus_cmd_valid (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i + .io_bus_cmd_ready (system_clint_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[15:0]), //i + .io_bus_cmd_payload_fragment_length (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_context (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[3:0] ), //i + .io_bus_rsp_valid (system_clint_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_bus_rsp_payload_last (system_clint_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_clint_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_clint_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_clint_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o + .io_timerInterrupt (system_clint_logic_io_timerInterrupt ), //o + .io_softwareInterrupt (system_clint_logic_io_softwareInterrupt ), //o + .io_time (system_clint_logic_io_time[63:0] ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbUartCtrl system_uart_0_io_logic ( + .io_bus_cmd_valid (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i + .io_bus_cmd_ready (system_uart_0_io_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[5:0]), //i + .io_bus_cmd_payload_fragment_length (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_context (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[3:0]), //i + .io_bus_rsp_valid (system_uart_0_io_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (_zz_io_bus_rsp_ready_1 ), //i + .io_bus_rsp_payload_last (system_uart_0_io_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_uart_0_io_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_uart_0_io_logic_io_bus_rsp_payload_fragment_context[3:0] ), //o + .io_uart_txd (system_uart_0_io_logic_io_uart_txd ), //o + .io_uart_rxd (system_uart_0_io_rxd ), //i + .io_interrupt (system_uart_0_io_logic_io_interrupt ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbSpiXdrMasterCtrl system_spi_0_io_logic ( + .io_ctrl_cmd_valid (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i + .io_ctrl_cmd_ready (system_spi_0_io_logic_io_ctrl_cmd_ready ), //o + .io_ctrl_cmd_payload_last (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i + .io_ctrl_cmd_payload_fragment_opcode (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i + .io_ctrl_cmd_payload_fragment_address (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[11:0]), //i + .io_ctrl_cmd_payload_fragment_length (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i + .io_ctrl_cmd_payload_fragment_data (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i + .io_ctrl_cmd_payload_fragment_context (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[3:0] ), //i + .io_ctrl_rsp_valid (system_spi_0_io_logic_io_ctrl_rsp_valid ), //o + .io_ctrl_rsp_ready (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_ctrl_rsp_payload_last (system_spi_0_io_logic_io_ctrl_rsp_payload_last ), //o + .io_ctrl_rsp_payload_fragment_opcode (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode ), //o + .io_ctrl_rsp_payload_fragment_data (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data[31:0] ), //o + .io_ctrl_rsp_payload_fragment_context (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context[3:0] ), //o + .io_spi_sclk_write (system_spi_0_io_logic_io_spi_sclk_write ), //o + .io_spi_data_0_writeEnable (system_spi_0_io_logic_io_spi_data_0_writeEnable ), //o + .io_spi_data_0_read (system_spi_0_io_data_0_read ), //i + .io_spi_data_0_write (system_spi_0_io_logic_io_spi_data_0_write ), //o + .io_spi_data_1_writeEnable (system_spi_0_io_logic_io_spi_data_1_writeEnable ), //o + .io_spi_data_1_read (system_spi_0_io_data_1_read ), //i + .io_spi_data_1_write (system_spi_0_io_logic_io_spi_data_1_write ), //o + .io_spi_data_2_writeEnable (system_spi_0_io_logic_io_spi_data_2_writeEnable ), //o + .io_spi_data_2_read (system_spi_0_io_data_2_read ), //i + .io_spi_data_2_write (system_spi_0_io_logic_io_spi_data_2_write ), //o + .io_spi_data_3_writeEnable (system_spi_0_io_logic_io_spi_data_3_writeEnable ), //o + .io_spi_data_3_read (system_spi_0_io_data_3_read ), //i + .io_spi_data_3_write (system_spi_0_io_logic_io_spi_data_3_write ), //o + .io_spi_ss (system_spi_0_io_logic_io_spi_ss ), //o + .io_interrupt (system_spi_0_io_logic_io_interrupt ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + BmbToApb3Bridge io_apbSlave_0_logic ( + .io_input_cmd_valid (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i + .io_input_cmd_ready (io_apbSlave_0_logic_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[15:0]), //i + .io_input_cmd_payload_fragment_length (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i + .io_input_cmd_payload_fragment_data (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_context (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[3:0] ), //i + .io_input_rsp_valid (io_apbSlave_0_logic_io_input_rsp_valid ), //o + .io_input_rsp_ready (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_input_rsp_payload_last (io_apbSlave_0_logic_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (io_apbSlave_0_logic_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (io_apbSlave_0_logic_io_input_rsp_payload_fragment_context[3:0] ), //o + .io_output_PADDR (io_apbSlave_0_logic_io_output_PADDR[15:0] ), //o + .io_output_PSEL (io_apbSlave_0_logic_io_output_PSEL ), //o + .io_output_PENABLE (io_apbSlave_0_logic_io_output_PENABLE ), //o + .io_output_PREADY (io_apbSlave_0_PREADY ), //i + .io_output_PWRITE (io_apbSlave_0_logic_io_output_PWRITE ), //o + .io_output_PWDATA (io_apbSlave_0_logic_io_output_PWDATA[31:0] ), //o + .io_output_PRDATA (io_apbSlave_0_PRDATA[31:0] ), //i + .io_output_PSLVERROR (io_apbSlave_0_PSLVERROR ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + initial begin + debugCd_logic_holdingLogic_resetCounter = 12'h0; + debugCd_logic_outputReset = 1'b1; + end + + always @(*) begin + debugCd_logic_inputResetTrigger = 1'b0; + if(debugCd_logic_inputResetAdapter_stuff_syncTrigger) begin + debugCd_logic_inputResetTrigger = 1'b1; + end + end + + always @(*) begin + debugCd_logic_outputResetUnbuffered = 1'b0; + if(when_ClockDomainGenerator_l77) begin + debugCd_logic_outputResetUnbuffered = 1'b1; + end + end + + assign when_ClockDomainGenerator_l77 = (debugCd_logic_holdingLogic_resetCounter != 12'hfff); + assign debugCd_logic_inputResetAdapter_stuff_syncTrigger = bufferCC_5_io_dataOut; + always @(*) begin + systemCd_logic_inputResetTrigger = 1'b0; + if(bufferCC_6_io_dataOut) begin + systemCd_logic_inputResetTrigger = 1'b1; + end + if(bufferCC_7_io_dataOut) begin + systemCd_logic_inputResetTrigger = 1'b1; + end + end + + always @(*) begin + systemCd_logic_outputResetUnbuffered = 1'b0; + if(when_ClockDomainGenerator_l77_1) begin + systemCd_logic_outputResetUnbuffered = 1'b1; + end + end + + assign when_ClockDomainGenerator_l77_1 = (systemCd_logic_holdingLogic_resetCounter != 6'h3f); + assign system_cores_0_iBus_cmd_valid = system_cores_0_logic_cpu_iBus_cmd_valid; + assign system_cores_0_iBus_cmd_payload_fragment_opcode = 1'b0; + assign system_cores_0_iBus_cmd_payload_fragment_address = system_cores_0_logic_cpu_iBus_cmd_payload_address; + assign system_cores_0_iBus_cmd_payload_fragment_length = 6'h3f; + assign system_cores_0_iBus_cmd_payload_last = 1'b1; + assign system_cores_0_logic_cpu_iBus_rsp_payload_error = (system_cores_0_iBus_rsp_payload_fragment_opcode == 1'b1); + assign system_cores_0_iBus_rsp_ready = 1'b1; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_valid = system_cores_0_logic_cpu_dBus_cmd_valid; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_last = system_cores_0_logic_cpu_dBus_cmd_payload_last; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_opcode = (system_cores_0_logic_cpu_dBus_cmd_payload_wr ? 1'b1 : 1'b0); + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_address = system_cores_0_logic_cpu_dBus_cmd_payload_address; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_data = system_cores_0_logic_cpu_dBus_cmd_payload_data; + always @(*) begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'bxxxxxx; + case(system_cores_0_logic_cpu_dBus_cmd_payload_size) + 3'b000 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h0; + end + 3'b001 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h01; + end + 3'b010 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h03; + end + 3'b011 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h07; + end + 3'b100 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h0f; + end + 3'b101 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h1f; + end + 3'b110 : begin + _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = 6'h3f; + end + default : begin + end + endcase + end + + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length = _zz_system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_mask = system_cores_0_logic_cpu_dBus_cmd_payload_mask; + assign system_cores_0_logic_cpu_dBus_Bridge_withoutWriteBuffer_busCmdContext_isWrite = system_cores_0_logic_cpu_dBus_cmd_payload_wr; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_withoutWriteBuffer_busCmdContext_isWrite; + always @(*) begin + system_cores_0_logic_cpu_dBus_rsp_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_valid; + if(when_DataCache_l532) begin + system_cores_0_logic_cpu_dBus_rsp_valid = 1'b0; + end + end + + assign when_DataCache_l532 = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_context[0]; + assign system_cores_0_logic_cpu_dBus_rsp_payload_error = (system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_opcode == 1'b1); + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_ready = 1'b1; + assign system_cores_0_iBus_cmd_combStage_valid = system_cores_0_iBus_cmd_valid; + assign system_cores_0_iBus_cmd_ready = system_cores_0_iBus_cmd_combStage_ready; + assign system_cores_0_iBus_cmd_combStage_payload_last = system_cores_0_iBus_cmd_payload_last; + assign system_cores_0_iBus_cmd_combStage_payload_fragment_opcode = system_cores_0_iBus_cmd_payload_fragment_opcode; + assign system_cores_0_iBus_cmd_combStage_payload_fragment_address = system_cores_0_iBus_cmd_payload_fragment_address; + assign system_cores_0_iBus_cmd_combStage_payload_fragment_length = system_cores_0_iBus_cmd_payload_fragment_length; + assign system_cores_0_iBus_cmd_combStage_ready = system_cores_0_iBus_connector_decoder_cmd_ready; + always @(*) begin + _zz_system_cores_0_iBus_connector_decoder_rsp_ready = system_cores_0_iBus_rsp_ready; + if(when_Stream_l368) begin + _zz_system_cores_0_iBus_connector_decoder_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! _zz_system_cores_0_iBus_rsp_valid); + assign _zz_system_cores_0_iBus_rsp_valid = _zz_system_cores_0_iBus_rsp_valid_1; + assign system_cores_0_iBus_rsp_valid = _zz_system_cores_0_iBus_rsp_valid; + assign system_cores_0_iBus_rsp_payload_last = _zz_system_cores_0_iBus_rsp_payload_last; + assign system_cores_0_iBus_rsp_payload_fragment_opcode = _zz_system_cores_0_iBus_rsp_payload_fragment_opcode; + assign system_cores_0_iBus_rsp_payload_fragment_data = _zz_system_cores_0_iBus_rsp_payload_fragment_data; + assign system_cores_0_iBus_connector_decoder_cmd_valid = system_cores_0_iBus_cmd_combStage_valid; + assign system_cores_0_iBus_connector_decoder_rsp_ready = _zz_system_cores_0_iBus_connector_decoder_rsp_ready; + assign system_cores_0_iBus_connector_decoder_cmd_payload_last = system_cores_0_iBus_cmd_combStage_payload_last; + assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_opcode = system_cores_0_iBus_cmd_combStage_payload_fragment_opcode; + assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_address = system_cores_0_iBus_cmd_combStage_payload_fragment_address; + assign system_cores_0_iBus_connector_decoder_cmd_payload_fragment_length = system_cores_0_iBus_cmd_combStage_payload_fragment_length; + always @(*) begin + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_ready; + if(when_Stream_l368_1) begin + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready = 1'b1; + end + end + + assign when_Stream_l368_1 = (! system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid); + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_last = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_last; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_opcode = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_opcode; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_address = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_address; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_length = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_length; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_data = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_data; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_mask = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_mask; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_context; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_ready = system_cores_0_dBus_connector_decoder_cmd_ready; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_valid = system_cores_0_dBus_connector_decoder_rsp_valid; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_last = system_cores_0_dBus_connector_decoder_rsp_payload_last; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_opcode = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_opcode; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_data = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_data; + assign system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_payload_fragment_context = system_cores_0_dBus_connector_decoder_rsp_payload_fragment_context; + assign system_cores_0_dBus_connector_decoder_cmd_valid = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_valid; + assign system_cores_0_dBus_connector_decoder_rsp_ready = system_cores_0_logic_cpu_dBus_Bridge_bus_rsp_ready; + assign system_cores_0_dBus_connector_decoder_cmd_payload_last = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_last; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_opcode = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_opcode; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_address = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_address; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_length = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_length; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_data = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_data; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_mask = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_mask; + assign system_cores_0_dBus_connector_decoder_cmd_payload_fragment_context = system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_m2sPipe_payload_fragment_context; + assign system_hardJtag_debug_logic_mmMaster_cmd_valid = system_hardJtag_debug_logic_debugger_io_mem_cmd_valid; + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_last = 1'b1; + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_length = 2'b11; + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_opcode = (system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_wr ? 1'b1 : 1'b0); + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address = {_zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address,2'b00}; + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_data = system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_data; + always @(*) begin + case(system_hardJtag_debug_logic_debugger_io_mem_cmd_payload_size) + 2'b00 : begin + _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b0001; + end + 2'b01 : begin + _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b0011; + end + default : begin + _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = 4'b1111; + end + endcase + end + + assign system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask = _zz_system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask_1[3:0]; + assign system_hardJtag_debug_logic_mmMaster_rsp_ready = 1'b1; + assign jtagCtrl_tdo = system_hardJtag_debug_logic_jtagBridge_io_ctrl_tdo; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_valid = system_hardJtag_debug_logic_mmMaster_cmd_valid; + assign system_hardJtag_debug_logic_mmMaster_cmd_ready = system_hardJtag_debug_bmb_connector_decoder_cmd_ready; + assign system_hardJtag_debug_logic_mmMaster_rsp_valid = system_hardJtag_debug_bmb_connector_decoder_rsp_valid; + assign system_hardJtag_debug_bmb_connector_decoder_rsp_ready = system_hardJtag_debug_logic_mmMaster_rsp_ready; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_last = system_hardJtag_debug_logic_mmMaster_cmd_payload_last; + assign system_hardJtag_debug_logic_mmMaster_rsp_payload_last = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_last; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_opcode = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_opcode; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_address = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_address; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_length = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_length; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_data = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_data; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_payload_fragment_mask = system_hardJtag_debug_logic_mmMaster_cmd_payload_fragment_mask; + assign system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_opcode = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_opcode; + assign system_hardJtag_debug_logic_mmMaster_rsp_payload_fragment_data = system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_data; + assign system_hardJtag_debug_bmb_connector_decoder_cmd_ready = bmbDecoder_4_io_input_cmd_ready; + assign system_hardJtag_debug_bmb_connector_decoder_rsp_valid = bmbDecoder_4_io_input_rsp_valid; + assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_last = bmbDecoder_4_io_input_rsp_payload_last; + assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_opcode = bmbDecoder_4_io_input_rsp_payload_fragment_opcode; + assign system_hardJtag_debug_bmb_connector_decoder_rsp_payload_fragment_data = bmbDecoder_4_io_input_rsp_payload_fragment_data; + assign system_fabric_iBus_bmb_cmd_valid = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_iBus_bmb_cmd_ready; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_iBus_bmb_rsp_valid; + assign system_fabric_iBus_bmb_rsp_ready = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_fabric_iBus_bmb_cmd_payload_last = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_iBus_bmb_rsp_payload_last; + assign system_fabric_iBus_bmb_cmd_payload_fragment_opcode = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_fabric_iBus_bmb_cmd_payload_fragment_address = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_fabric_iBus_bmb_cmd_payload_fragment_length = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_rsp_payload_fragment_opcode; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_iBus_bmb_rsp_payload_fragment_data; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_cores_0_iBus_connector_decoder_cmd_valid; + assign system_cores_0_iBus_connector_decoder_cmd_ready = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_cores_0_iBus_connector_decoder_rsp_valid = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_cores_0_iBus_connector_decoder_rsp_ready; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_cores_0_iBus_connector_decoder_cmd_payload_last; + assign system_cores_0_iBus_connector_decoder_rsp_payload_last = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_opcode; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_address; + assign system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_cores_0_iBus_connector_decoder_cmd_payload_fragment_length; + assign system_cores_0_iBus_connector_decoder_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_cores_0_iBus_connector_decoder_rsp_payload_fragment_data = system_fabric_iBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_valid = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid || system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_last = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_opcode = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_address = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_length = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_data = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_mask = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_mask : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_context = (system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid ? system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context : system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context); + always @(*) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l368_2) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l368_2 = (! system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid); + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_valid = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_last = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_last; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_opcode = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_opcode; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_address = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_address; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_length = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_length; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_data = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_data; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_mask = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_mask; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_payload_fragment_context = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_context; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_m2sPipe_ready = system_fabric_exclusiveMonitor_logic_io_input_cmd_ready; + always @(*) begin + _zz_io_input_rsp_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + if(when_Stream_l368_3) begin + _zz_io_input_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368_3 = (! _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid); + assign _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_cores_0_debugBmb_cmd_valid = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_cores_0_debugBmb_cmd_ready; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_cores_0_debugBmb_rsp_valid; + assign system_cores_0_debugBmb_rsp_ready = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_cores_0_debugBmb_cmd_payload_last = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_cores_0_debugBmb_rsp_payload_last; + assign system_cores_0_debugBmb_cmd_payload_fragment_opcode = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_cores_0_debugBmb_cmd_payload_fragment_address = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_cores_0_debugBmb_cmd_payload_fragment_length = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_cores_0_debugBmb_cmd_payload_fragment_data = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_cores_0_debugBmb_cmd_payload_fragment_mask = system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_cores_0_debugBmb_rsp_payload_fragment_opcode; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_cores_0_debugBmb_rsp_payload_fragment_data; + assign system_cores_0_logic_cpu_debug_bus_cmd_payload_wr = (system_cores_0_debugBmb_cmd_payload_fragment_opcode == 1'b1); + assign system_cores_0_logic_cpu_debug_bus_cmd_fire = (system_cores_0_debugBmb_cmd_valid && system_cores_0_logic_cpu_debug_bus_cmd_ready); + assign system_cores_0_debugBmb_cmd_ready = system_cores_0_logic_cpu_debug_bus_cmd_ready; + assign system_cores_0_debugBmb_rsp_valid = system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext; + assign system_cores_0_debugBmb_rsp_payload_last = 1'b1; + assign system_cores_0_debugBmb_rsp_payload_fragment_opcode = 1'b0; + assign system_cores_0_debugBmb_rsp_payload_fragment_data = system_cores_0_logic_cpu_debug_bus_rsp_data; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbDecoder_4_io_outputs_0_cmd_valid; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbDecoder_4_io_outputs_0_rsp_ready; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbDecoder_4_io_outputs_0_cmd_payload_last; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_opcode; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_address[7:0]; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_length; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_data; + assign system_cores_0_debugBmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = bmbDecoder_4_io_outputs_0_cmd_payload_fragment_mask; + assign system_fabric_dBusCoherent_bmb_cmd_valid = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_dBusCoherent_bmb_cmd_ready; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_dBusCoherent_bmb_rsp_valid; + assign system_fabric_dBusCoherent_bmb_rsp_ready = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_fabric_dBusCoherent_bmb_cmd_payload_last = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_dBusCoherent_bmb_rsp_payload_last; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign system_fabric_dBusCoherent_bmb_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_rsp_payload_fragment_context; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_valid = system_fabric_dBusCoherent_bmb_cmd_valid; + assign system_fabric_dBusCoherent_bmb_cmd_ready = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_ready; + assign system_fabric_dBusCoherent_bmb_rsp_valid = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_valid; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_ready = system_fabric_dBusCoherent_bmb_rsp_ready; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_last = system_fabric_dBusCoherent_bmb_cmd_payload_last; + assign system_fabric_dBusCoherent_bmb_rsp_payload_last = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_last; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_address; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_length; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_mask; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_cmd_payload_fragment_context; + assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_context; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_valid = system_fabric_exclusiveMonitor_logic_io_output_cmd_valid; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_ready = system_fabric_exclusiveMonitor_logic_io_output_rsp_ready; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_last = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_last; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_opcode = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_opcode; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_address = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_address; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_length = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_length; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_data = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_data; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_mask = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_mask; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_context = system_fabric_exclusiveMonitor_logic_io_output_cmd_payload_fragment_context; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_cores_0_dBus_connector_decoder_cmd_valid; + assign system_cores_0_dBus_connector_decoder_cmd_ready = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_cores_0_dBus_connector_decoder_rsp_valid = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_cores_0_dBus_connector_decoder_rsp_ready; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_cores_0_dBus_connector_decoder_cmd_payload_last; + assign system_cores_0_dBus_connector_decoder_rsp_payload_last = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_address; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_length; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_mask; + assign system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_cores_0_dBus_connector_decoder_cmd_payload_fragment_context; + assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_data = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_cores_0_dBus_connector_decoder_rsp_payload_fragment_context = system_fabric_dBusCoherent_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_valid; + assign system_fabric_dBusCoherent_bmb_connector_decoder_cmd_ready = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_valid = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_fabric_dBusCoherent_bmb_connector_decoder_rsp_ready; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_last; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_last = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_opcode; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_address; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_length; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_data; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_mask; + assign system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_fabric_dBusCoherent_bmb_connector_decoder_cmd_payload_fragment_context; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_opcode = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_data = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_fabric_dBusCoherent_bmb_connector_decoder_rsp_payload_fragment_context = system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_fabric_dBus_bmb_cmd_valid = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_fabric_dBus_bmb_cmd_ready; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_fabric_dBus_bmb_rsp_valid; + assign system_fabric_dBus_bmb_rsp_ready = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_fabric_dBus_bmb_cmd_payload_last = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_fabric_dBus_bmb_rsp_payload_last; + assign system_fabric_dBus_bmb_cmd_payload_fragment_opcode = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_fabric_dBus_bmb_cmd_payload_fragment_address = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_fabric_dBus_bmb_cmd_payload_fragment_length = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_fabric_dBus_bmb_cmd_payload_fragment_data = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_fabric_dBus_bmb_cmd_payload_fragment_mask = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign system_fabric_dBus_bmb_cmd_payload_fragment_context = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_fabric_dBus_bmb_rsp_payload_fragment_opcode; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_fabric_dBus_bmb_rsp_payload_fragment_data; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_fabric_dBus_bmb_rsp_payload_fragment_context; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_valid; + assign system_fabric_exclusiveMonitor_output_connector_decoder_cmd_ready = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_valid = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_fabric_exclusiveMonitor_output_connector_decoder_rsp_ready; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_last; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_last = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_opcode; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_address; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_length; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_data; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_mask; + assign system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_fabric_exclusiveMonitor_output_connector_decoder_cmd_payload_fragment_context; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_opcode = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_data = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_fabric_exclusiveMonitor_output_connector_decoder_rsp_payload_fragment_context = system_fabric_dBus_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + always @(*) begin + system_fabric_iBus_bmb_cmd_ready = system_fabric_iBus_bmb_cmd_m2sPipe_ready; + if(when_Stream_l368_4) begin + system_fabric_iBus_bmb_cmd_ready = 1'b1; + end + end + + assign when_Stream_l368_4 = (! system_fabric_iBus_bmb_cmd_m2sPipe_valid); + assign system_fabric_iBus_bmb_cmd_m2sPipe_valid = system_fabric_iBus_bmb_cmd_rValid; + assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_last = system_fabric_iBus_bmb_cmd_rData_last; + assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_opcode = system_fabric_iBus_bmb_cmd_rData_fragment_opcode; + assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_address = system_fabric_iBus_bmb_cmd_rData_fragment_address; + assign system_fabric_iBus_bmb_cmd_m2sPipe_payload_fragment_length = system_fabric_iBus_bmb_cmd_rData_fragment_length; + assign system_fabric_iBus_bmb_cmd_m2sPipe_ready = system_fabric_iBus_bmb_decoder_io_input_cmd_ready; + assign system_fabric_iBus_bmb_rsp_valid = system_fabric_iBus_bmb_decoder_io_input_rsp_valid; + assign system_fabric_iBus_bmb_rsp_payload_last = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_last; + assign system_fabric_iBus_bmb_rsp_payload_fragment_opcode = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_opcode; + assign system_fabric_iBus_bmb_rsp_payload_fragment_data = system_fabric_iBus_bmb_decoder_io_input_rsp_payload_fragment_data; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid = system_fabric_dBus_bmb_cmd_valid; + assign system_fabric_dBus_bmb_cmd_ready = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready; + assign system_fabric_dBus_bmb_rsp_valid = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready = system_fabric_dBus_bmb_rsp_ready; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last = system_fabric_dBus_bmb_cmd_payload_last; + assign system_fabric_dBus_bmb_rsp_payload_last = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode = system_fabric_dBus_bmb_cmd_payload_fragment_opcode; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address = system_fabric_dBus_bmb_cmd_payload_fragment_address; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length = system_fabric_dBus_bmb_cmd_payload_fragment_length; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data = system_fabric_dBus_bmb_cmd_payload_fragment_data; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask = system_fabric_dBus_bmb_cmd_payload_fragment_mask; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context = system_fabric_dBus_bmb_cmd_payload_fragment_context; + assign system_fabric_dBus_bmb_rsp_payload_fragment_opcode = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode; + assign system_fabric_dBus_bmb_rsp_payload_fragment_data = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data; + assign system_fabric_dBus_bmb_rsp_payload_fragment_context = system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context; + assign system_bridge_bmb_cmd_valid = system_bridge_bmb_arbiter_io_output_cmd_valid; + assign system_bridge_bmb_rsp_ready = system_bridge_bmb_arbiter_io_output_rsp_ready; + assign system_bridge_bmb_cmd_payload_last = system_bridge_bmb_arbiter_io_output_cmd_payload_last; + assign system_bridge_bmb_cmd_payload_fragment_source = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_source; + assign system_bridge_bmb_cmd_payload_fragment_opcode = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_opcode; + assign system_bridge_bmb_cmd_payload_fragment_address = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_address; + assign system_bridge_bmb_cmd_payload_fragment_length = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_length; + assign system_bridge_bmb_cmd_payload_fragment_data = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_data; + assign system_bridge_bmb_cmd_payload_fragment_mask = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_mask; + assign system_bridge_bmb_cmd_payload_fragment_context = system_bridge_bmb_arbiter_io_output_cmd_payload_fragment_context; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready = system_bridge_bmb_arbiter_io_inputs_0_cmd_ready; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid = system_bridge_bmb_arbiter_io_inputs_0_rsp_valid; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_last; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_opcode; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_data; + assign system_bridge_bmb_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context = system_bridge_bmb_arbiter_io_inputs_0_rsp_payload_fragment_context; + assign system_bridge_bmb_cmd_ready = (! system_bridge_bmb_cmd_rValid); + assign system_bridge_bmb_cmd_s2mPipe_valid = (system_bridge_bmb_cmd_valid || system_bridge_bmb_cmd_rValid); + assign system_bridge_bmb_cmd_s2mPipe_payload_last = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_last : system_bridge_bmb_cmd_payload_last); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_source = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_source : system_bridge_bmb_cmd_payload_fragment_source); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_opcode = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_opcode : system_bridge_bmb_cmd_payload_fragment_opcode); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_address = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_address : system_bridge_bmb_cmd_payload_fragment_address); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_length = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_length : system_bridge_bmb_cmd_payload_fragment_length); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_data = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_data : system_bridge_bmb_cmd_payload_fragment_data); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_mask = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_mask : system_bridge_bmb_cmd_payload_fragment_mask); + assign system_bridge_bmb_cmd_s2mPipe_payload_fragment_context = (system_bridge_bmb_cmd_rValid ? system_bridge_bmb_cmd_rData_fragment_context : system_bridge_bmb_cmd_payload_fragment_context); + always @(*) begin + system_bridge_bmb_cmd_s2mPipe_ready = system_bridge_bmb_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l368_5) begin + system_bridge_bmb_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l368_5 = (! system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid); + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_valid = system_bridge_bmb_cmd_s2mPipe_rValid; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_last = system_bridge_bmb_cmd_s2mPipe_rData_last; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_source = system_bridge_bmb_cmd_s2mPipe_rData_fragment_source; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_opcode = system_bridge_bmb_cmd_s2mPipe_rData_fragment_opcode; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_address = system_bridge_bmb_cmd_s2mPipe_rData_fragment_address; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_length = system_bridge_bmb_cmd_s2mPipe_rData_fragment_length; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_data = system_bridge_bmb_cmd_s2mPipe_rData_fragment_data; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_mask = system_bridge_bmb_cmd_s2mPipe_rData_fragment_mask; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_payload_fragment_context = system_bridge_bmb_cmd_s2mPipe_rData_fragment_context; + assign system_bridge_bmb_cmd_s2mPipe_m2sPipe_ready = system_bridge_bmb_decoder_io_input_cmd_ready; + assign system_bridge_bmb_rsp_valid = system_bridge_bmb_decoder_io_input_rsp_valid; + assign system_bridge_bmb_rsp_payload_last = system_bridge_bmb_decoder_io_input_rsp_payload_last; + assign system_bridge_bmb_rsp_payload_fragment_source = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_source; + assign system_bridge_bmb_rsp_payload_fragment_opcode = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_opcode; + assign system_bridge_bmb_rsp_payload_fragment_data = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_data; + assign system_bridge_bmb_rsp_payload_fragment_context = system_bridge_bmb_decoder_io_input_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_cmd_valid = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_bmbPeripheral_bmb_cmd_ready; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_bmbPeripheral_bmb_rsp_valid; + assign system_bmbPeripheral_bmb_rsp_ready = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_bmbPeripheral_bmb_cmd_payload_last = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_bmbPeripheral_bmb_rsp_payload_last; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_address = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_length = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_data = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_mask = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign system_bmbPeripheral_bmb_cmd_payload_fragment_context = system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_bmbPeripheral_bmb_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_bmbPeripheral_bmb_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bridge_bmb_unburstify_io_output_cmd_valid; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bridge_bmb_unburstify_io_output_rsp_ready; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bridge_bmb_unburstify_io_output_cmd_payload_last; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_address[23:0]; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_mask; + assign system_bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bridge_bmb_unburstify_io_output_cmd_payload_fragment_context; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_valid = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_ready; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_last = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_opcode = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_address = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_length = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_data = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_mask = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_payload_fragment_context = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_combStage_ready = system_ramA_logic_io_bus_cmd_ready; + always @(*) begin + _zz_io_bus_rsp_ready = system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + if(when_Stream_l368_6) begin + _zz_io_bus_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368_6 = (! _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid); + assign _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bridge_bmb_unburstify_1_io_output_cmd_valid; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bridge_bmb_unburstify_1_io_output_rsp_ready; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bridge_bmb_unburstify_1_io_output_cmd_payload_last; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_opcode; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_address[14:0]; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_length; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_data; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_mask; + assign system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bridge_bmb_unburstify_1_io_output_cmd_payload_fragment_context; + assign system_bmbPeripheral_bmb_cmd_combStage_valid = system_bmbPeripheral_bmb_cmd_valid; + assign system_bmbPeripheral_bmb_cmd_ready = system_bmbPeripheral_bmb_cmd_combStage_ready; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_last = system_bmbPeripheral_bmb_cmd_payload_last; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_opcode = system_bmbPeripheral_bmb_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_address = system_bmbPeripheral_bmb_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_length = system_bmbPeripheral_bmb_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_data = system_bmbPeripheral_bmb_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_mask = system_bmbPeripheral_bmb_cmd_payload_fragment_mask; + assign system_bmbPeripheral_bmb_cmd_combStage_payload_fragment_context = system_bmbPeripheral_bmb_cmd_payload_fragment_context; + assign system_bmbPeripheral_bmb_cmd_combStage_ready = system_bmbPeripheral_bmb_decoder_io_input_cmd_ready; + assign _zz_io_input_rsp_ready_1 = (! _zz_system_bmbPeripheral_bmb_rsp_valid_1); + assign _zz_system_bmbPeripheral_bmb_rsp_valid = _zz_system_bmbPeripheral_bmb_rsp_valid_1; + assign system_bmbPeripheral_bmb_rsp_valid = _zz_system_bmbPeripheral_bmb_rsp_valid; + assign system_bmbPeripheral_bmb_rsp_payload_last = _zz_system_bmbPeripheral_bmb_rsp_payload_last; + assign system_bmbPeripheral_bmb_rsp_payload_fragment_opcode = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_rsp_payload_fragment_data = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_rsp_payload_fragment_context = _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_context; + assign system_uart_0_io_txd = system_uart_0_io_logic_io_uart_txd; + assign io_apbSlave_0_PADDR = io_apbSlave_0_logic_io_output_PADDR; + assign io_apbSlave_0_PSEL = io_apbSlave_0_logic_io_output_PSEL; + assign io_apbSlave_0_PENABLE = io_apbSlave_0_logic_io_output_PENABLE; + assign io_apbSlave_0_PWRITE = io_apbSlave_0_logic_io_output_PWRITE; + assign io_apbSlave_0_PWDATA = io_apbSlave_0_logic_io_output_PWDATA; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_clint_logic_io_bus_cmd_ready; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_clint_logic_io_bus_rsp_valid; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_clint_logic_io_bus_rsp_payload_last; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_clint_logic_io_bus_rsp_payload_fragment_opcode; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_clint_logic_io_bus_rsp_payload_fragment_data; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_clint_logic_io_bus_rsp_payload_fragment_context; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_uart_0_io_logic_io_bus_cmd_ready; + assign _zz_io_bus_rsp_ready_1 = (! _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1); + assign _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign when_PlicGateway_l21 = (! system_uart_0_io_interrupt_plic_gateway_waitCompletion); + assign when_PlicGateway_l21_1 = (! system_spi_0_io_interrupt_plic_gateway_waitCompletion); + assign system_spi_0_io_sclk_write = system_spi_0_io_logic_io_spi_sclk_write; + assign system_spi_0_io_data_0_writeEnable = system_spi_0_io_logic_io_spi_data_0_writeEnable; + assign system_spi_0_io_data_0_write = system_spi_0_io_logic_io_spi_data_0_write; + assign system_spi_0_io_data_1_writeEnable = system_spi_0_io_logic_io_spi_data_1_writeEnable; + assign system_spi_0_io_data_1_write = system_spi_0_io_logic_io_spi_data_1_write; + assign system_spi_0_io_data_2_writeEnable = system_spi_0_io_logic_io_spi_data_2_writeEnable; + assign system_spi_0_io_data_2_write = system_spi_0_io_logic_io_spi_data_2_write; + assign system_spi_0_io_data_3_writeEnable = system_spi_0_io_logic_io_spi_data_3_writeEnable; + assign system_spi_0_io_data_3_write = system_spi_0_io_logic_io_spi_data_3_write; + assign system_spi_0_io_ss = system_spi_0_io_logic_io_spi_ss; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_spi_0_io_logic_io_ctrl_cmd_ready; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_spi_0_io_logic_io_ctrl_rsp_valid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_spi_0_io_logic_io_ctrl_rsp_payload_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = io_apbSlave_0_logic_io_input_cmd_ready; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = io_apbSlave_0_logic_io_input_rsp_valid; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = io_apbSlave_0_logic_io_input_rsp_payload_last; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = io_apbSlave_0_logic_io_input_rsp_payload_fragment_data; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = io_apbSlave_0_logic_io_input_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_withoutMask_cmd_valid = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_rsp_ready = system_bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context = system_bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_cmd_ready = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_bmbPeripheral_bmb_withoutMask_rsp_valid = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address[15:0]; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data; + assign system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context = system_clint_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1 = system_bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_1; + assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_1; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1[5:0]; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1 = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + always @(*) begin + system_plic_logic_bus_readHaltTrigger = 1'b0; + if(when_PlicMapper_l122) begin + system_plic_logic_bus_readHaltTrigger = 1'b1; + end + end + + assign system_plic_logic_bus_writeHaltTrigger = 1'b0; + assign _zz_system_plic_logic_bmb_rsp_valid = (! (system_plic_logic_bus_readHaltTrigger || system_plic_logic_bus_writeHaltTrigger)); + assign system_plic_logic_bus_rsp_ready = (_zz_system_plic_logic_bus_rsp_ready && _zz_system_plic_logic_bmb_rsp_valid); + always @(*) begin + _zz_system_plic_logic_bus_rsp_ready = system_plic_logic_bmb_rsp_ready; + if(when_Stream_l368_7) begin + _zz_system_plic_logic_bus_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368_7 = (! _zz_system_plic_logic_bmb_rsp_valid_1); + assign _zz_system_plic_logic_bmb_rsp_valid_1 = _zz_system_plic_logic_bmb_rsp_valid_2; + assign system_plic_logic_bmb_rsp_valid = _zz_system_plic_logic_bmb_rsp_valid_1; + assign system_plic_logic_bmb_rsp_payload_last = _zz_system_plic_logic_bmb_rsp_payload_last; + assign system_plic_logic_bmb_rsp_payload_fragment_opcode = _zz_system_plic_logic_bmb_rsp_payload_fragment_opcode; + assign system_plic_logic_bmb_rsp_payload_fragment_data = _zz_system_plic_logic_bmb_rsp_payload_fragment_data; + assign system_plic_logic_bmb_rsp_payload_fragment_context = _zz_system_plic_logic_bmb_rsp_payload_fragment_context; + assign system_plic_logic_bus_askWrite = (system_plic_logic_bmb_cmd_valid && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b1)); + assign system_plic_logic_bus_askRead = (system_plic_logic_bmb_cmd_valid && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b0)); + assign system_plic_logic_bmb_cmd_fire = (system_plic_logic_bmb_cmd_valid && system_plic_logic_bmb_cmd_ready); + assign system_plic_logic_bus_doWrite = (system_plic_logic_bmb_cmd_fire && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b1)); + assign system_plic_logic_bmb_cmd_fire_1 = (system_plic_logic_bmb_cmd_valid && system_plic_logic_bmb_cmd_ready); + assign system_plic_logic_bus_doRead = (system_plic_logic_bmb_cmd_fire_1 && (system_plic_logic_bmb_cmd_payload_fragment_opcode == 1'b0)); + assign system_plic_logic_bus_rsp_valid = system_plic_logic_bmb_cmd_valid; + assign system_plic_logic_bmb_cmd_ready = system_plic_logic_bus_rsp_ready; + assign system_plic_logic_bus_rsp_payload_last = 1'b1; + assign system_plic_logic_bus_rsp_payload_fragment_opcode = 1'b0; + always @(*) begin + system_plic_logic_bus_rsp_payload_fragment_data = 32'h0; + case(system_plic_logic_bmb_cmd_payload_fragment_address) + 22'h000004 : begin + system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_uart_0_io_interrupt_plic_gateway_priority; + end + 22'h001000 : begin + system_plic_logic_bus_rsp_payload_fragment_data[1 : 1] = system_uart_0_io_interrupt_plic_gateway_ip; + system_plic_logic_bus_rsp_payload_fragment_data[4 : 4] = system_spi_0_io_interrupt_plic_gateway_ip; + end + 22'h000010 : begin + system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_spi_0_io_interrupt_plic_gateway_priority; + end + 22'h200000 : begin + system_plic_logic_bus_rsp_payload_fragment_data[1 : 0] = system_cores_0_externalInterrupt_plic_target_threshold; + end + 22'h200004 : begin + system_plic_logic_bus_rsp_payload_fragment_data[2 : 0] = system_cores_0_externalInterrupt_plic_target_claim; + end + 22'h002000 : begin + system_plic_logic_bus_rsp_payload_fragment_data[1 : 1] = system_cores_0_externalInterrupt_plic_target_ie_0; + system_plic_logic_bus_rsp_payload_fragment_data[4 : 4] = system_cores_0_externalInterrupt_plic_target_ie_1; + end + default : begin + end + endcase + end + + assign system_plic_logic_bus_rsp_payload_fragment_context = system_plic_logic_bmb_cmd_payload_fragment_context; + assign system_cores_0_externalInterrupt_plic_target_requests_0_priority = 2'b00; + assign system_cores_0_externalInterrupt_plic_target_requests_0_id = 3'b000; + assign system_cores_0_externalInterrupt_plic_target_requests_0_valid = 1'b1; + assign system_cores_0_externalInterrupt_plic_target_requests_1_priority = system_uart_0_io_interrupt_plic_gateway_priority; + assign system_cores_0_externalInterrupt_plic_target_requests_1_id = 3'b001; + assign system_cores_0_externalInterrupt_plic_target_requests_1_valid = (system_uart_0_io_interrupt_plic_gateway_ip && system_cores_0_externalInterrupt_plic_target_ie_0); + assign system_cores_0_externalInterrupt_plic_target_requests_2_priority = system_spi_0_io_interrupt_plic_gateway_priority; + assign system_cores_0_externalInterrupt_plic_target_requests_2_id = 3'b100; + assign system_cores_0_externalInterrupt_plic_target_requests_2_valid = (system_spi_0_io_interrupt_plic_gateway_ip && system_cores_0_externalInterrupt_plic_target_ie_1); + assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority = ((! system_cores_0_externalInterrupt_plic_target_requests_1_valid) || (system_cores_0_externalInterrupt_plic_target_requests_0_valid && (system_cores_0_externalInterrupt_plic_target_requests_1_priority <= system_cores_0_externalInterrupt_plic_target_requests_0_priority))); + assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1 = (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_priority : system_cores_0_externalInterrupt_plic_target_requests_1_priority); + assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 = (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_valid : system_cores_0_externalInterrupt_plic_target_requests_1_valid); + assign _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 = ((! system_cores_0_externalInterrupt_plic_target_requests_2_valid) || (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 && (system_cores_0_externalInterrupt_plic_target_requests_2_priority <= _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1))); + assign system_cores_0_externalInterrupt_plic_target_iep = (system_cores_0_externalInterrupt_plic_target_threshold < system_cores_0_externalInterrupt_plic_target_bestRequest_priority); + assign system_cores_0_externalInterrupt_plic_target_claim = (system_cores_0_externalInterrupt_plic_target_iep ? system_cores_0_externalInterrupt_plic_target_bestRequest_id : 3'b000); + assign system_uart_0_io_interrupt_plic_gateway_priority = _zz_system_uart_0_io_interrupt_plic_gateway_priority; + assign system_spi_0_io_interrupt_plic_gateway_priority = _zz_system_spi_0_io_interrupt_plic_gateway_priority; + always @(*) begin + system_plic_logic_bridge_claim_valid = 1'b0; + case(system_plic_logic_bmb_cmd_payload_fragment_address) + 22'h200004 : begin + if(system_plic_logic_bus_doRead) begin + system_plic_logic_bridge_claim_valid = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + system_plic_logic_bridge_claim_payload = 3'bxxx; + case(system_plic_logic_bmb_cmd_payload_fragment_address) + 22'h200004 : begin + if(system_plic_logic_bus_doRead) begin + system_plic_logic_bridge_claim_payload = system_cores_0_externalInterrupt_plic_target_claim; + end + end + default : begin + end + endcase + end + + always @(*) begin + system_plic_logic_bridge_completion_valid = 1'b0; + if(system_plic_logic_bridge_targetMapping_0_targetCompletion_valid) begin + system_plic_logic_bridge_completion_valid = 1'b1; + end + end + + always @(*) begin + system_plic_logic_bridge_completion_payload = 3'bxxx; + if(system_plic_logic_bridge_targetMapping_0_targetCompletion_valid) begin + system_plic_logic_bridge_completion_payload = system_plic_logic_bridge_targetMapping_0_targetCompletion_payload; + end + end + + always @(*) begin + system_plic_logic_bridge_coherencyStall_willIncrement = 1'b0; + if(when_PlicMapper_l122) begin + system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; + end + if(when_BmbSlaveFactory_l71) begin + if(system_plic_logic_bus_askWrite) begin + system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; + end + if(system_plic_logic_bus_askRead) begin + system_plic_logic_bridge_coherencyStall_willIncrement = 1'b1; + end + end + end + + assign system_plic_logic_bridge_coherencyStall_willClear = 1'b0; + assign system_plic_logic_bridge_coherencyStall_willOverflowIfInc = (system_plic_logic_bridge_coherencyStall_value == 1'b1); + assign system_plic_logic_bridge_coherencyStall_willOverflow = (system_plic_logic_bridge_coherencyStall_willOverflowIfInc && system_plic_logic_bridge_coherencyStall_willIncrement); + always @(*) begin + system_plic_logic_bridge_coherencyStall_valueNext = (system_plic_logic_bridge_coherencyStall_value + system_plic_logic_bridge_coherencyStall_willIncrement); + if(system_plic_logic_bridge_coherencyStall_willClear) begin + system_plic_logic_bridge_coherencyStall_valueNext = 1'b0; + end + end + + assign when_PlicMapper_l122 = (system_plic_logic_bridge_coherencyStall_value != 1'b0); + assign system_cores_0_externalInterrupt_plic_target_threshold = _zz_system_cores_0_externalInterrupt_plic_target_threshold; + always @(*) begin + system_plic_logic_bridge_targetMapping_0_targetCompletion_valid = 1'b0; + case(system_plic_logic_bmb_cmd_payload_fragment_address) + 22'h200004 : begin + if(system_plic_logic_bus_doWrite) begin + system_plic_logic_bridge_targetMapping_0_targetCompletion_valid = 1'b1; + end + end + default : begin + end + endcase + end + + assign system_cores_0_externalInterrupt_plic_target_ie_0 = _zz_system_cores_0_externalInterrupt_plic_target_ie_0; + assign system_cores_0_externalInterrupt_plic_target_ie_1 = _zz_system_cores_0_externalInterrupt_plic_target_ie_1; + assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2 = system_bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_2; + assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_2; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_2; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2[11:0]; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3 = system_bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_3; + assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_3; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_3; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3[15:0]; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_plic_logic_bmb_cmd_valid = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_plic_logic_bmb_cmd_ready; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_plic_logic_bmb_rsp_valid; + assign system_plic_logic_bmb_rsp_ready = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign system_plic_logic_bmb_cmd_payload_last = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_plic_logic_bmb_rsp_payload_last; + assign system_plic_logic_bmb_cmd_payload_fragment_opcode = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign system_plic_logic_bmb_cmd_payload_fragment_address = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign system_plic_logic_bmb_cmd_payload_fragment_length = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign system_plic_logic_bmb_cmd_payload_fragment_data = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign system_plic_logic_bmb_cmd_payload_fragment_context = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_plic_logic_bmb_rsp_payload_fragment_opcode; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_plic_logic_bmb_rsp_payload_fragment_data; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_plic_logic_bmb_rsp_payload_fragment_context; + assign system_bmbPeripheral_bmb_withoutMask_cmd_valid_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid; + assign system_bmbPeripheral_bmb_withoutMask_rsp_ready_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4 = system_bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = system_bmbPeripheral_bmb_withoutMask_cmd_valid_4; + assign system_bmbPeripheral_bmb_withoutMask_cmd_ready_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign system_bmbPeripheral_bmb_withoutMask_rsp_valid_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = system_bmbPeripheral_bmb_withoutMask_rsp_ready_4; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = system_bmbPeripheral_bmb_withoutMask_cmd_payload_last_4; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4[21:0]; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4; + assign system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = system_bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4 = system_plic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_plic_logic_bridge_targetMapping_0_targetCompletion_payload = system_plic_logic_bmb_cmd_payload_fragment_data[2 : 0]; + assign when_BmbSlaveFactory_l71 = 1'b1; + always @(posedge io_systemClk) begin + if(when_ClockDomainGenerator_l77) begin + debugCd_logic_holdingLogic_resetCounter <= (debugCd_logic_holdingLogic_resetCounter + 12'h001); + end + if(debugCd_logic_inputResetTrigger) begin + debugCd_logic_holdingLogic_resetCounter <= 12'h0; + end + debugCd_logic_outputReset <= debugCd_logic_outputResetUnbuffered; + end + + always @(posedge io_systemClk) begin + if(when_ClockDomainGenerator_l77_1) begin + systemCd_logic_holdingLogic_resetCounter <= (systemCd_logic_holdingLogic_resetCounter + 6'h01); + end + if(systemCd_logic_inputResetTrigger) begin + systemCd_logic_holdingLogic_resetCounter <= 6'h0; + end + systemCd_logic_outputReset <= systemCd_logic_outputResetUnbuffered; + end + + always @(posedge io_systemClk) begin + io_systemReset <= systemCd_logic_outputReset; + if(_zz_system_cores_0_iBus_connector_decoder_rsp_ready) begin + _zz_system_cores_0_iBus_rsp_payload_last <= system_cores_0_iBus_connector_decoder_rsp_payload_last; + _zz_system_cores_0_iBus_rsp_payload_fragment_opcode <= system_cores_0_iBus_connector_decoder_rsp_payload_fragment_opcode; + _zz_system_cores_0_iBus_rsp_payload_fragment_data <= system_cores_0_iBus_connector_decoder_rsp_payload_fragment_data; + end + if(system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready) begin + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_last <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_last; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_opcode <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_opcode; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_address <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_address; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_length <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_length; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_data <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_data; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_mask <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_mask; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rData_fragment_context <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_payload_fragment_context; + end + if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_mask <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_last <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_last; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_opcode <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_opcode; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_address <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_address; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_length <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_length; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_data <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_data; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_mask <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_mask; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rData_fragment_context <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_payload_fragment_context; + end + if(_zz_io_input_rsp_ready) begin + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_last; + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_opcode; + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_data; + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_fabric_exclusiveMonitor_logic_io_input_rsp_payload_fragment_context; + end + if(system_fabric_iBus_bmb_cmd_ready) begin + system_fabric_iBus_bmb_cmd_rData_last <= system_fabric_iBus_bmb_cmd_payload_last; + system_fabric_iBus_bmb_cmd_rData_fragment_opcode <= system_fabric_iBus_bmb_cmd_payload_fragment_opcode; + system_fabric_iBus_bmb_cmd_rData_fragment_address <= system_fabric_iBus_bmb_cmd_payload_fragment_address; + system_fabric_iBus_bmb_cmd_rData_fragment_length <= system_fabric_iBus_bmb_cmd_payload_fragment_length; + end + if(system_bridge_bmb_cmd_ready) begin + system_bridge_bmb_cmd_rData_last <= system_bridge_bmb_cmd_payload_last; + system_bridge_bmb_cmd_rData_fragment_source <= system_bridge_bmb_cmd_payload_fragment_source; + system_bridge_bmb_cmd_rData_fragment_opcode <= system_bridge_bmb_cmd_payload_fragment_opcode; + system_bridge_bmb_cmd_rData_fragment_address <= system_bridge_bmb_cmd_payload_fragment_address; + system_bridge_bmb_cmd_rData_fragment_length <= system_bridge_bmb_cmd_payload_fragment_length; + system_bridge_bmb_cmd_rData_fragment_data <= system_bridge_bmb_cmd_payload_fragment_data; + system_bridge_bmb_cmd_rData_fragment_mask <= system_bridge_bmb_cmd_payload_fragment_mask; + system_bridge_bmb_cmd_rData_fragment_context <= system_bridge_bmb_cmd_payload_fragment_context; + end + if(system_bridge_bmb_cmd_s2mPipe_ready) begin + system_bridge_bmb_cmd_s2mPipe_rData_last <= system_bridge_bmb_cmd_s2mPipe_payload_last; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_source <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_source; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_opcode <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_opcode; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_address <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_address; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_length <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_length; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_data <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_data; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_mask <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_mask; + system_bridge_bmb_cmd_s2mPipe_rData_fragment_context <= system_bridge_bmb_cmd_s2mPipe_payload_fragment_context; + end + if(_zz_io_bus_rsp_ready) begin + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_ramA_logic_io_bus_rsp_payload_last; + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_ramA_logic_io_bus_rsp_payload_fragment_opcode; + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_ramA_logic_io_bus_rsp_payload_fragment_data; + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_ramA_logic_io_bus_rsp_payload_fragment_context; + end + if(_zz_io_input_rsp_ready_1) begin + _zz_system_bmbPeripheral_bmb_rsp_payload_last <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_last; + _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_opcode <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode; + _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_data <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data; + _zz_system_bmbPeripheral_bmb_rsp_payload_fragment_context <= system_bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context; + end + _zz_timerInterrupt <= system_clint_logic_io_timerInterrupt[0]; + _zz_softwareInterrupt <= system_clint_logic_io_softwareInterrupt[0]; + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + if(_zz_io_bus_rsp_ready_1) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_uart_0_io_logic_io_bus_rsp_payload_last; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_data; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_context; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + if(_zz_system_plic_logic_bus_rsp_ready) begin + _zz_system_plic_logic_bmb_rsp_payload_last <= system_plic_logic_bus_rsp_payload_last; + _zz_system_plic_logic_bmb_rsp_payload_fragment_opcode <= system_plic_logic_bus_rsp_payload_fragment_opcode; + _zz_system_plic_logic_bmb_rsp_payload_fragment_data <= system_plic_logic_bus_rsp_payload_fragment_data; + _zz_system_plic_logic_bmb_rsp_payload_fragment_context <= system_plic_logic_bus_rsp_payload_fragment_context; + end + system_cores_0_externalInterrupt_plic_target_bestRequest_priority <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_1 : system_cores_0_externalInterrupt_plic_target_requests_2_priority); + system_cores_0_externalInterrupt_plic_target_bestRequest_id <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority ? system_cores_0_externalInterrupt_plic_target_requests_0_id : system_cores_0_externalInterrupt_plic_target_requests_1_id) : system_cores_0_externalInterrupt_plic_target_requests_2_id); + system_cores_0_externalInterrupt_plic_target_bestRequest_valid <= (_zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_3 ? _zz_system_cores_0_externalInterrupt_plic_target_bestRequest_priority_2 : system_cores_0_externalInterrupt_plic_target_requests_2_valid); + system_cores_0_externalInterrupt_plic_target_iep_regNext <= system_cores_0_externalInterrupt_plic_target_iep; + end + + always @(posedge io_systemClk) begin + system_cores_0_debugReset <= system_cores_0_logic_cpu_debug_resetOut; + end + + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + _zz_system_cores_0_iBus_rsp_valid_1 <= 1'b0; + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid <= 1'b0; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid <= 1'b0; + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + system_fabric_iBus_bmb_cmd_rValid <= 1'b0; + system_bridge_bmb_cmd_rValid <= 1'b0; + system_bridge_bmb_cmd_s2mPipe_rValid <= 1'b0; + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b0; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + system_uart_0_io_interrupt_plic_gateway_ip <= 1'b0; + system_uart_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; + system_spi_0_io_interrupt_plic_gateway_ip <= 1'b0; + system_spi_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + _zz_system_plic_logic_bmb_rsp_valid_2 <= 1'b0; + _zz_system_uart_0_io_interrupt_plic_gateway_priority <= 2'b00; + _zz_system_spi_0_io_interrupt_plic_gateway_priority <= 2'b00; + system_plic_logic_bridge_coherencyStall_value <= 1'b0; + _zz_system_cores_0_externalInterrupt_plic_target_threshold <= 2'b00; + _zz_system_cores_0_externalInterrupt_plic_target_ie_0 <= 1'b0; + _zz_system_cores_0_externalInterrupt_plic_target_ie_1 <= 1'b0; + end else begin + if(_zz_system_cores_0_iBus_connector_decoder_rsp_ready) begin + _zz_system_cores_0_iBus_rsp_valid_1 <= system_cores_0_iBus_connector_decoder_rsp_valid; + end + if(system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_ready) begin + system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_rValid <= system_cores_0_logic_cpu_dBus_Bridge_bus_cmd_valid; + end + if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + if(system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_ready) begin + system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_rValid <= system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_s2mPipe_valid; + end + if(_zz_io_input_rsp_ready) begin + _zz_system_fabric_exclusiveMonitor_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= system_fabric_exclusiveMonitor_logic_io_input_rsp_valid; + end + if(system_fabric_iBus_bmb_cmd_ready) begin + system_fabric_iBus_bmb_cmd_rValid <= system_fabric_iBus_bmb_cmd_valid; + end + if(system_bridge_bmb_cmd_valid) begin + system_bridge_bmb_cmd_rValid <= 1'b1; + end + if(system_bridge_bmb_cmd_s2mPipe_ready) begin + system_bridge_bmb_cmd_rValid <= 1'b0; + end + if(system_bridge_bmb_cmd_s2mPipe_ready) begin + system_bridge_bmb_cmd_s2mPipe_rValid <= system_bridge_bmb_cmd_s2mPipe_valid; + end + if(_zz_io_bus_rsp_ready) begin + _zz_system_ramA_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= system_ramA_logic_io_bus_rsp_valid; + end + if(system_bmbPeripheral_bmb_decoder_io_input_rsp_valid) begin + _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b1; + end + if((_zz_system_bmbPeripheral_bmb_rsp_valid && system_bmbPeripheral_bmb_rsp_ready)) begin + _zz_system_bmbPeripheral_bmb_rsp_valid_1 <= 1'b0; + end + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + if(system_uart_0_io_logic_io_bus_rsp_valid) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b1; + end + if((_zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready)) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + end + if(when_PlicGateway_l21) begin + system_uart_0_io_interrupt_plic_gateway_ip <= system_uart_0_io_logic_io_interrupt; + system_uart_0_io_interrupt_plic_gateway_waitCompletion <= system_uart_0_io_logic_io_interrupt; + end + if(when_PlicGateway_l21_1) begin + system_spi_0_io_interrupt_plic_gateway_ip <= system_spi_0_io_logic_io_interrupt; + system_spi_0_io_interrupt_plic_gateway_waitCompletion <= system_spi_0_io_logic_io_interrupt; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + if(_zz_system_plic_logic_bus_rsp_ready) begin + _zz_system_plic_logic_bmb_rsp_valid_2 <= (system_plic_logic_bus_rsp_valid && _zz_system_plic_logic_bmb_rsp_valid); + end + if(system_plic_logic_bridge_claim_valid) begin + case(system_plic_logic_bridge_claim_payload) + 3'b001 : begin + system_uart_0_io_interrupt_plic_gateway_ip <= 1'b0; + end + 3'b100 : begin + system_spi_0_io_interrupt_plic_gateway_ip <= 1'b0; + end + default : begin + end + endcase + end + if(system_plic_logic_bridge_completion_valid) begin + case(system_plic_logic_bridge_completion_payload) + 3'b001 : begin + system_uart_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; + end + 3'b100 : begin + system_spi_0_io_interrupt_plic_gateway_waitCompletion <= 1'b0; + end + default : begin + end + endcase + end + system_plic_logic_bridge_coherencyStall_value <= system_plic_logic_bridge_coherencyStall_valueNext; + case(system_plic_logic_bmb_cmd_payload_fragment_address) + 22'h000004 : begin + if(system_plic_logic_bus_doWrite) begin + _zz_system_uart_0_io_interrupt_plic_gateway_priority <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; + end + end + 22'h000010 : begin + if(system_plic_logic_bus_doWrite) begin + _zz_system_spi_0_io_interrupt_plic_gateway_priority <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; + end + end + 22'h200000 : begin + if(system_plic_logic_bus_doWrite) begin + _zz_system_cores_0_externalInterrupt_plic_target_threshold <= system_plic_logic_bmb_cmd_payload_fragment_data[1 : 0]; + end + end + 22'h002000 : begin + if(system_plic_logic_bus_doWrite) begin + _zz_system_cores_0_externalInterrupt_plic_target_ie_0 <= system_plic_logic_bmb_cmd_payload_fragment_data[1]; + _zz_system_cores_0_externalInterrupt_plic_target_ie_1 <= system_plic_logic_bmb_cmd_payload_fragment_data[4]; + end + end + default : begin + end + endcase + end + end + + always @(posedge io_systemClk) begin + if(debugCd_logic_outputReset) begin + system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext <= 1'b0; + end else begin + system_cores_0_logic_cpu_debug_bus_cmd_fire_regNext <= system_cores_0_logic_cpu_debug_bus_cmd_fire; + end + end + + +endmodule + +module BmbToApb3Bridge ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [15:0] io_input_cmd_payload_fragment_address, + input [1:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_context, + output io_input_rsp_valid, + input io_input_rsp_ready, + output io_input_rsp_payload_last, + output [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output [3:0] io_input_rsp_payload_fragment_context, + output [15:0] io_output_PADDR, + output [0:0] io_output_PSEL, + output io_output_PENABLE, + input io_output_PREADY, + output io_output_PWRITE, + output [31:0] io_output_PWDATA, + input [31:0] io_output_PRDATA, + input io_output_PSLVERROR, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire bmbBuffer_cmd_valid; + reg bmbBuffer_cmd_ready; + wire bmbBuffer_cmd_payload_last; + wire [0:0] bmbBuffer_cmd_payload_fragment_opcode; + wire [15:0] bmbBuffer_cmd_payload_fragment_address; + wire [1:0] bmbBuffer_cmd_payload_fragment_length; + wire [31:0] bmbBuffer_cmd_payload_fragment_data; + wire [3:0] bmbBuffer_cmd_payload_fragment_context; + reg bmbBuffer_rsp_valid; + reg bmbBuffer_rsp_ready; + wire bmbBuffer_rsp_payload_last; + reg [0:0] bmbBuffer_rsp_payload_fragment_opcode; + wire [31:0] bmbBuffer_rsp_payload_fragment_data; + wire [3:0] bmbBuffer_rsp_payload_fragment_context; + wire io_input_rsp_isStall; + wire _zz_io_input_cmd_ready; + wire bmbBuffer_rsp_m2sPipe_valid; + wire bmbBuffer_rsp_m2sPipe_ready; + wire bmbBuffer_rsp_m2sPipe_payload_last; + wire [0:0] bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; + wire [31:0] bmbBuffer_rsp_m2sPipe_payload_fragment_data; + wire [3:0] bmbBuffer_rsp_m2sPipe_payload_fragment_context; + reg bmbBuffer_rsp_rValid; + reg bmbBuffer_rsp_rData_last; + reg [0:0] bmbBuffer_rsp_rData_fragment_opcode; + reg [31:0] bmbBuffer_rsp_rData_fragment_data; + reg [3:0] bmbBuffer_rsp_rData_fragment_context; + wire when_Stream_l368; + reg state; + wire when_BmbToApb3Bridge_l46; + + assign io_input_rsp_isStall = (io_input_rsp_valid && (! io_input_rsp_ready)); + assign _zz_io_input_cmd_ready = (! io_input_rsp_isStall); + assign io_input_cmd_ready = (bmbBuffer_cmd_ready && _zz_io_input_cmd_ready); + assign bmbBuffer_cmd_valid = (io_input_cmd_valid && _zz_io_input_cmd_ready); + assign bmbBuffer_cmd_payload_last = io_input_cmd_payload_last; + assign bmbBuffer_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign bmbBuffer_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign bmbBuffer_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign bmbBuffer_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign bmbBuffer_cmd_payload_fragment_context = io_input_cmd_payload_fragment_context; + always @(*) begin + bmbBuffer_rsp_ready = bmbBuffer_rsp_m2sPipe_ready; + if(when_Stream_l368) begin + bmbBuffer_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! bmbBuffer_rsp_m2sPipe_valid); + assign bmbBuffer_rsp_m2sPipe_valid = bmbBuffer_rsp_rValid; + assign bmbBuffer_rsp_m2sPipe_payload_last = bmbBuffer_rsp_rData_last; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_opcode = bmbBuffer_rsp_rData_fragment_opcode; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_data = bmbBuffer_rsp_rData_fragment_data; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_context = bmbBuffer_rsp_rData_fragment_context; + assign io_input_rsp_valid = bmbBuffer_rsp_m2sPipe_valid; + assign bmbBuffer_rsp_m2sPipe_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = bmbBuffer_rsp_m2sPipe_payload_last; + assign io_input_rsp_payload_fragment_opcode = bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = bmbBuffer_rsp_m2sPipe_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = bmbBuffer_rsp_m2sPipe_payload_fragment_context; + always @(*) begin + bmbBuffer_cmd_ready = 1'b0; + if(!when_BmbToApb3Bridge_l46) begin + if(io_output_PREADY) begin + bmbBuffer_cmd_ready = 1'b1; + end + end + end + + assign io_output_PSEL[0] = bmbBuffer_cmd_valid; + assign io_output_PENABLE = state; + assign io_output_PWRITE = (bmbBuffer_cmd_payload_fragment_opcode == 1'b1); + assign io_output_PADDR = bmbBuffer_cmd_payload_fragment_address; + assign io_output_PWDATA = bmbBuffer_cmd_payload_fragment_data; + always @(*) begin + bmbBuffer_rsp_valid = 1'b0; + if(!when_BmbToApb3Bridge_l46) begin + if(io_output_PREADY) begin + bmbBuffer_rsp_valid = 1'b1; + end + end + end + + assign bmbBuffer_rsp_payload_fragment_data = io_output_PRDATA; + assign when_BmbToApb3Bridge_l46 = (! state); + assign bmbBuffer_rsp_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign bmbBuffer_rsp_payload_last = 1'b1; + always @(*) begin + bmbBuffer_rsp_payload_fragment_opcode = 1'b0; + if(io_output_PSLVERROR) begin + bmbBuffer_rsp_payload_fragment_opcode = 1'b1; + end + end + + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + bmbBuffer_rsp_rValid <= 1'b0; + state <= 1'b0; + end else begin + if(bmbBuffer_rsp_ready) begin + bmbBuffer_rsp_rValid <= bmbBuffer_rsp_valid; + end + if(when_BmbToApb3Bridge_l46) begin + state <= bmbBuffer_cmd_valid; + end else begin + if(io_output_PREADY) begin + state <= 1'b0; + end + end + end + end + + always @(posedge io_systemClk) begin + if(bmbBuffer_rsp_ready) begin + bmbBuffer_rsp_rData_last <= bmbBuffer_rsp_payload_last; + bmbBuffer_rsp_rData_fragment_opcode <= bmbBuffer_rsp_payload_fragment_opcode; + bmbBuffer_rsp_rData_fragment_data <= bmbBuffer_rsp_payload_fragment_data; + bmbBuffer_rsp_rData_fragment_context <= bmbBuffer_rsp_payload_fragment_context; + end + end + + +endmodule + +module BmbSpiXdrMasterCtrl ( + input io_ctrl_cmd_valid, + output io_ctrl_cmd_ready, + input io_ctrl_cmd_payload_last, + input [0:0] io_ctrl_cmd_payload_fragment_opcode, + input [11:0] io_ctrl_cmd_payload_fragment_address, + input [1:0] io_ctrl_cmd_payload_fragment_length, + input [31:0] io_ctrl_cmd_payload_fragment_data, + input [3:0] io_ctrl_cmd_payload_fragment_context, + output io_ctrl_rsp_valid, + input io_ctrl_rsp_ready, + output io_ctrl_rsp_payload_last, + output [0:0] io_ctrl_rsp_payload_fragment_opcode, + output [31:0] io_ctrl_rsp_payload_fragment_data, + output [3:0] io_ctrl_rsp_payload_fragment_context, + output [0:0] io_spi_sclk_write, + output io_spi_data_0_writeEnable, + input [0:0] io_spi_data_0_read, + output [0:0] io_spi_data_0_write, + output io_spi_data_1_writeEnable, + input [0:0] io_spi_data_1_read, + output [0:0] io_spi_data_1_write, + output io_spi_data_2_writeEnable, + input [0:0] io_spi_data_2_read, + output [0:0] io_spi_data_2_write, + output io_spi_data_3_writeEnable, + input [0:0] io_spi_data_3_read, + output [0:0] io_spi_data_3_write, + output [0:0] io_spi_ss, + output io_interrupt, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready; + wire ctrl_io_rsp_queueWithOccupancy_io_pop_ready; + wire ctrl_io_cmd_ready; + wire ctrl_io_rsp_valid; + wire [7:0] ctrl_io_rsp_payload_data; + wire [0:0] ctrl_io_spi_sclk_write; + wire [0:0] ctrl_io_spi_ss; + wire [0:0] ctrl_io_spi_data_0_write; + wire ctrl_io_spi_data_0_writeEnable; + wire [0:0] ctrl_io_spi_data_1_write; + wire ctrl_io_spi_data_1_writeEnable; + wire [0:0] ctrl_io_spi_data_2_write; + wire ctrl_io_spi_data_2_writeEnable; + wire [0:0] ctrl_io_spi_data_3_write; + wire ctrl_io_spi_data_3_writeEnable; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; + wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy; + wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; + wire ctrl_io_rsp_queueWithOccupancy_io_push_ready; + wire ctrl_io_rsp_queueWithOccupancy_io_pop_valid; + wire [7:0] ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_occupancy; + wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_availability; + wire factory_readHaltTrigger; + wire factory_writeHaltTrigger; + wire factory_rsp_valid; + wire factory_rsp_ready; + wire factory_rsp_payload_last; + wire [0:0] factory_rsp_payload_fragment_opcode; + reg [31:0] factory_rsp_payload_fragment_data; + wire [3:0] factory_rsp_payload_fragment_context; + wire _zz_io_ctrl_rsp_valid; + reg _zz_factory_rsp_ready; + wire _zz_io_ctrl_rsp_valid_1; + reg _zz_io_ctrl_rsp_valid_2; + reg _zz_io_ctrl_rsp_payload_last; + reg [0:0] _zz_io_ctrl_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_ctrl_rsp_payload_fragment_data; + reg [3:0] _zz_io_ctrl_rsp_payload_fragment_context; + wire when_Stream_l368; + wire factory_askWrite; + wire factory_askRead; + wire io_ctrl_cmd_fire; + wire factory_doWrite; + wire io_ctrl_cmd_fire_1; + wire factory_doRead; + wire [31:0] mapping_cmdLogic_writeData; + reg mapping_cmdLogic_doRegular; + reg mapping_cmdLogic_doWriteLarge; + reg mapping_cmdLogic_doReadWriteLarge; + wire mapping_cmdLogic_streamUnbuffered_valid; + wire mapping_cmdLogic_streamUnbuffered_ready; + wire mapping_cmdLogic_streamUnbuffered_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_payload_read; + wire mapping_cmdLogic_streamUnbuffered_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_payload_data; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write; + reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; + reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; + wire when_Stream_l368_1; + wire ctrl_io_rsp_toStream_valid; + wire ctrl_io_rsp_toStream_ready; + wire [7:0] ctrl_io_rsp_toStream_payload_data; + reg _zz_io_pop_ready; + reg _zz_io_pop_ready_1; + reg mapping_interruptCtrl_cmdIntEnable; + reg mapping_interruptCtrl_rspIntEnable; + wire mapping_interruptCtrl_cmdInt; + wire mapping_interruptCtrl_rspInt; + wire mapping_interruptCtrl_interrupt; + reg _zz_io_config_kind_cpol; + reg _zz_io_config_kind_cpha; + reg [1:0] _zz_io_config_mod; + reg [11:0] _zz_io_config_sclkToogle; + reg [11:0] _zz_io_config_ss_setup; + reg [11:0] _zz_io_config_ss_hold; + reg [11:0] _zz_io_config_ss_disable; + reg [0:0] _zz_io_config_ss_activeHigh; + wire [1:0] _zz_io_config_kind_cpol_1; + + TopLevel ctrl ( + .io_config_kind_cpol (_zz_io_config_kind_cpol ), //i + .io_config_kind_cpha (_zz_io_config_kind_cpha ), //i + .io_config_sclkToogle (_zz_io_config_sclkToogle[11:0] ), //i + .io_config_mod (_zz_io_config_mod[1:0] ), //i + .io_config_ss_activeHigh (_zz_io_config_ss_activeHigh ), //i + .io_config_ss_setup (_zz_io_config_ss_setup[11:0] ), //i + .io_config_ss_hold (_zz_io_config_ss_hold[11:0] ), //i + .io_config_ss_disable (_zz_io_config_ss_disable[11:0] ), //i + .io_cmd_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid ), //i + .io_cmd_ready (ctrl_io_cmd_ready ), //o + .io_cmd_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind ), //i + .io_cmd_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read ), //i + .io_cmd_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write ), //i + .io_cmd_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data[7:0]), //i + .io_rsp_valid (ctrl_io_rsp_valid ), //o + .io_rsp_payload_data (ctrl_io_rsp_payload_data[7:0] ), //o + .io_spi_sclk_write (ctrl_io_spi_sclk_write ), //o + .io_spi_data_0_writeEnable (ctrl_io_spi_data_0_writeEnable ), //o + .io_spi_data_0_read (io_spi_data_0_read ), //i + .io_spi_data_0_write (ctrl_io_spi_data_0_write ), //o + .io_spi_data_1_writeEnable (ctrl_io_spi_data_1_writeEnable ), //o + .io_spi_data_1_read (io_spi_data_1_read ), //i + .io_spi_data_1_write (ctrl_io_spi_data_1_write ), //o + .io_spi_data_2_writeEnable (ctrl_io_spi_data_2_writeEnable ), //o + .io_spi_data_2_read (io_spi_data_2_read ), //i + .io_spi_data_2_write (ctrl_io_spi_data_2_write ), //o + .io_spi_data_3_writeEnable (ctrl_io_spi_data_3_writeEnable ), //o + .io_spi_data_3_read (io_spi_data_3_read ), //i + .io_spi_data_3_write (ctrl_io_spi_data_3_write ), //o + .io_spi_ss (ctrl_io_spi_ss ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + StreamFifo_2 mapping_cmdLogic_streamUnbuffered_queueWithAvailability ( + .io_push_valid (mapping_cmdLogic_streamUnbuffered_valid ), //i + .io_push_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready ), //o + .io_push_payload_kind (mapping_cmdLogic_streamUnbuffered_payload_kind ), //i + .io_push_payload_read (mapping_cmdLogic_streamUnbuffered_payload_read ), //i + .io_push_payload_write (mapping_cmdLogic_streamUnbuffered_payload_write ), //i + .io_push_payload_data (mapping_cmdLogic_streamUnbuffered_payload_data[7:0] ), //i + .io_pop_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid ), //o + .io_pop_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready ), //i + .io_pop_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind ), //o + .io_pop_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read ), //o + .io_pop_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write ), //o + .io_pop_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data[7:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy[8:0] ), //o + .io_availability (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability[8:0] ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + StreamFifo_3 ctrl_io_rsp_queueWithOccupancy ( + .io_push_valid (ctrl_io_rsp_toStream_valid ), //i + .io_push_ready (ctrl_io_rsp_queueWithOccupancy_io_push_ready ), //o + .io_push_payload_data (ctrl_io_rsp_toStream_payload_data[7:0] ), //i + .io_pop_valid (ctrl_io_rsp_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (ctrl_io_rsp_queueWithOccupancy_io_pop_ready ), //i + .io_pop_payload_data (ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data[7:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (ctrl_io_rsp_queueWithOccupancy_io_occupancy[8:0] ), //o + .io_availability (ctrl_io_rsp_queueWithOccupancy_io_availability[8:0] ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + assign factory_readHaltTrigger = 1'b0; + assign factory_writeHaltTrigger = 1'b0; + assign _zz_io_ctrl_rsp_valid = (! (factory_readHaltTrigger || factory_writeHaltTrigger)); + assign factory_rsp_ready = (_zz_factory_rsp_ready && _zz_io_ctrl_rsp_valid); + always @(*) begin + _zz_factory_rsp_ready = io_ctrl_rsp_ready; + if(when_Stream_l368) begin + _zz_factory_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! _zz_io_ctrl_rsp_valid_1); + assign _zz_io_ctrl_rsp_valid_1 = _zz_io_ctrl_rsp_valid_2; + assign io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid_1; + assign io_ctrl_rsp_payload_last = _zz_io_ctrl_rsp_payload_last; + assign io_ctrl_rsp_payload_fragment_opcode = _zz_io_ctrl_rsp_payload_fragment_opcode; + assign io_ctrl_rsp_payload_fragment_data = _zz_io_ctrl_rsp_payload_fragment_data; + assign io_ctrl_rsp_payload_fragment_context = _zz_io_ctrl_rsp_payload_fragment_context; + assign factory_askWrite = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign factory_askRead = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign io_ctrl_cmd_fire = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); + assign factory_doWrite = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign io_ctrl_cmd_fire_1 = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); + assign factory_doRead = (io_ctrl_cmd_fire_1 && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign factory_rsp_valid = io_ctrl_cmd_valid; + assign io_ctrl_cmd_ready = factory_rsp_ready; + assign factory_rsp_payload_last = 1'b1; + assign factory_rsp_payload_fragment_opcode = 1'b0; + always @(*) begin + factory_rsp_payload_fragment_data = 32'h0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + factory_rsp_payload_fragment_data[31 : 31] = (! ctrl_io_rsp_queueWithOccupancy_io_pop_valid); + factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + end + 12'h004 : begin + factory_rsp_payload_fragment_data[8 : 0] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; + factory_rsp_payload_fragment_data[24 : 16] = ctrl_io_rsp_queueWithOccupancy_io_occupancy; + end + 12'h00c : begin + factory_rsp_payload_fragment_data[16 : 16] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; + factory_rsp_payload_fragment_data[0 : 0] = mapping_interruptCtrl_cmdIntEnable; + factory_rsp_payload_fragment_data[1 : 1] = mapping_interruptCtrl_rspIntEnable; + factory_rsp_payload_fragment_data[8 : 8] = mapping_interruptCtrl_cmdInt; + factory_rsp_payload_fragment_data[9 : 9] = mapping_interruptCtrl_rspInt; + end + 12'h058 : begin + factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + end + default : begin + end + endcase + end + + assign factory_rsp_payload_fragment_context = io_ctrl_cmd_payload_fragment_context; + always @(*) begin + mapping_cmdLogic_doRegular = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doRegular = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + mapping_cmdLogic_doWriteLarge = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h050 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doWriteLarge = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + mapping_cmdLogic_doReadWriteLarge = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h054 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doReadWriteLarge = 1'b1; + end + end + default : begin + end + endcase + end + + assign mapping_cmdLogic_streamUnbuffered_valid = ((mapping_cmdLogic_doRegular || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_write = (((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[8]) || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_read = ((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[9]) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_kind = (mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[11]); + assign mapping_cmdLogic_streamUnbuffered_payload_data = mapping_cmdLogic_writeData[7:0]; + assign mapping_cmdLogic_streamUnbuffered_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready = (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid || mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data); + always @(*) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; + if(when_Stream_l368_1) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l368_1 = (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready = ctrl_io_cmd_ready; + assign ctrl_io_rsp_toStream_valid = ctrl_io_rsp_valid; + assign ctrl_io_rsp_toStream_payload_data = ctrl_io_rsp_payload_data; + assign ctrl_io_rsp_toStream_ready = ctrl_io_rsp_queueWithOccupancy_io_push_ready; + always @(*) begin + _zz_io_pop_ready = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + if(factory_doRead) begin + _zz_io_pop_ready = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + _zz_io_pop_ready_1 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h058 : begin + if(factory_doRead) begin + _zz_io_pop_ready_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign ctrl_io_rsp_queueWithOccupancy_io_pop_ready = (_zz_io_pop_ready || _zz_io_pop_ready_1); + assign mapping_interruptCtrl_cmdInt = (mapping_interruptCtrl_cmdIntEnable && (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid)); + assign mapping_interruptCtrl_rspInt = (mapping_interruptCtrl_rspIntEnable && ctrl_io_rsp_queueWithOccupancy_io_pop_valid); + assign mapping_interruptCtrl_interrupt = (mapping_interruptCtrl_rspInt || mapping_interruptCtrl_cmdInt); + assign io_spi_sclk_write = ctrl_io_spi_sclk_write; + assign io_spi_data_0_writeEnable = ctrl_io_spi_data_0_writeEnable; + assign io_spi_data_0_write = ctrl_io_spi_data_0_write; + assign io_spi_data_1_writeEnable = ctrl_io_spi_data_1_writeEnable; + assign io_spi_data_1_write = ctrl_io_spi_data_1_write; + assign io_spi_data_2_writeEnable = ctrl_io_spi_data_2_writeEnable; + assign io_spi_data_2_write = ctrl_io_spi_data_2_write; + assign io_spi_data_3_writeEnable = ctrl_io_spi_data_3_writeEnable; + assign io_spi_data_3_write = ctrl_io_spi_data_3_write; + assign io_spi_ss = ctrl_io_spi_ss; + assign io_interrupt = mapping_interruptCtrl_interrupt; + assign mapping_cmdLogic_writeData = io_ctrl_cmd_payload_fragment_data[31 : 0]; + assign _zz_io_config_kind_cpol_1 = io_ctrl_cmd_payload_fragment_data[1 : 0]; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + _zz_io_ctrl_rsp_valid_2 <= 1'b0; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b0; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= 1'b0; + mapping_interruptCtrl_cmdIntEnable <= 1'b0; + mapping_interruptCtrl_rspIntEnable <= 1'b0; + _zz_io_config_ss_activeHigh <= 1'b0; + end else begin + if(_zz_factory_rsp_ready) begin + _zz_io_ctrl_rsp_valid_2 <= (factory_rsp_valid && _zz_io_ctrl_rsp_valid); + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b1; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValid <= 1'b0; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; + end + case(io_ctrl_cmd_payload_fragment_address) + 12'h00c : begin + if(factory_doWrite) begin + mapping_interruptCtrl_cmdIntEnable <= io_ctrl_cmd_payload_fragment_data[0]; + mapping_interruptCtrl_rspIntEnable <= io_ctrl_cmd_payload_fragment_data[1]; + end + end + 12'h030 : begin + if(factory_doWrite) begin + _zz_io_config_ss_activeHigh <= io_ctrl_cmd_payload_fragment_data[0 : 0]; + end + end + default : begin + end + endcase + end + end + + always @(posedge io_systemClk) begin + if(_zz_factory_rsp_ready) begin + _zz_io_ctrl_rsp_payload_last <= factory_rsp_payload_last; + _zz_io_ctrl_rsp_payload_fragment_opcode <= factory_rsp_payload_fragment_opcode; + _zz_io_ctrl_rsp_payload_fragment_data <= factory_rsp_payload_fragment_data; + _zz_io_ctrl_rsp_payload_fragment_context <= factory_rsp_payload_fragment_context; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; + end + case(io_ctrl_cmd_payload_fragment_address) + 12'h008 : begin + if(factory_doWrite) begin + _zz_io_config_kind_cpol <= _zz_io_config_kind_cpol_1[0]; + _zz_io_config_kind_cpha <= _zz_io_config_kind_cpol_1[1]; + _zz_io_config_mod <= io_ctrl_cmd_payload_fragment_data[5 : 4]; + end + end + 12'h020 : begin + if(factory_doWrite) begin + _zz_io_config_sclkToogle <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h024 : begin + if(factory_doWrite) begin + _zz_io_config_ss_setup <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h028 : begin + if(factory_doWrite) begin + _zz_io_config_ss_hold <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h02c : begin + if(factory_doWrite) begin + _zz_io_config_ss_disable <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + default : begin + end + endcase + end + + +endmodule + +module BmbUartCtrl ( + input io_bus_cmd_valid, + output io_bus_cmd_ready, + input io_bus_cmd_payload_last, + input [0:0] io_bus_cmd_payload_fragment_opcode, + input [5:0] io_bus_cmd_payload_fragment_address, + input [1:0] io_bus_cmd_payload_fragment_length, + input [31:0] io_bus_cmd_payload_fragment_data, + input [3:0] io_bus_cmd_payload_fragment_context, + output io_bus_rsp_valid, + input io_bus_rsp_ready, + output io_bus_rsp_payload_last, + output [0:0] io_bus_rsp_payload_fragment_opcode, + output [31:0] io_bus_rsp_payload_fragment_data, + output [3:0] io_bus_rsp_payload_fragment_context, + output io_uart_txd, + input io_uart_rxd, + output io_interrupt, + input io_systemClk, + input systemCd_logic_outputReset +); + localparam UartStopType_ONE = 1'd0; + localparam UartStopType_TWO = 1'd1; + localparam UartParityType_NONE = 2'd0; + localparam UartParityType_EVEN = 2'd1; + localparam UartParityType_ODD = 2'd2; + + reg uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready; + wire uartCtrl_1_io_write_ready; + wire uartCtrl_1_io_read_valid; + wire [7:0] uartCtrl_1_io_read_payload; + wire uartCtrl_1_io_uart_txd; + wire uartCtrl_1_io_readError; + wire uartCtrl_1_io_readBreak; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_availability; + wire uartCtrl_1_io_read_queueWithOccupancy_io_push_ready; + wire uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid; + wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload; + wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_occupancy; + wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_availability; + wire [0:0] _zz_bridge_misc_readError; + wire [0:0] _zz_bridge_misc_readOverflowError; + wire [0:0] _zz_bridge_misc_breakDetected; + wire [0:0] _zz_bridge_misc_doBreak; + wire [0:0] _zz_bridge_misc_doBreak_1; + wire [7:0] _zz_busCtrl_rsp_payload_fragment_data; + wire [19:0] _zz_bridge_uartConfigReg_clockDivider; + wire [19:0] _zz_bridge_uartConfigReg_clockDivider_1; + wire busCtrl_readHaltTrigger; + wire busCtrl_writeHaltTrigger; + wire busCtrl_rsp_valid; + wire busCtrl_rsp_ready; + wire busCtrl_rsp_payload_last; + wire [0:0] busCtrl_rsp_payload_fragment_opcode; + reg [31:0] busCtrl_rsp_payload_fragment_data; + wire [3:0] busCtrl_rsp_payload_fragment_context; + wire _zz_io_bus_rsp_valid; + reg _zz_busCtrl_rsp_ready; + wire _zz_io_bus_rsp_valid_1; + reg _zz_io_bus_rsp_valid_2; + reg _zz_io_bus_rsp_payload_last; + reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_bus_rsp_payload_fragment_data; + reg [3:0] _zz_io_bus_rsp_payload_fragment_context; + wire when_Stream_l368; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire io_bus_cmd_fire; + wire busCtrl_doWrite; + wire io_bus_cmd_fire_1; + wire busCtrl_doRead; + reg [2:0] bridge_uartConfigReg_frame_dataLength; + reg [0:0] bridge_uartConfigReg_frame_stop; + reg [1:0] bridge_uartConfigReg_frame_parity; + reg [19:0] bridge_uartConfigReg_clockDivider; + reg _zz_bridge_write_streamUnbuffered_valid; + wire bridge_write_streamUnbuffered_valid; + wire bridge_write_streamUnbuffered_ready; + wire [7:0] bridge_write_streamUnbuffered_payload; + reg bridge_read_streamBreaked_valid; + reg bridge_read_streamBreaked_ready; + wire [7:0] bridge_read_streamBreaked_payload; + reg bridge_interruptCtrl_writeIntEnable; + reg bridge_interruptCtrl_readIntEnable; + wire bridge_interruptCtrl_readInt; + wire bridge_interruptCtrl_writeInt; + wire bridge_interruptCtrl_interrupt; + reg bridge_misc_readError; + reg when_BusSlaveFactory_l335; + wire when_BusSlaveFactory_l341; + reg bridge_misc_readOverflowError; + reg when_BusSlaveFactory_l335_1; + wire when_BusSlaveFactory_l341_1; + wire uartCtrl_1_io_read_isStall; + reg bridge_misc_breakDetected; + reg uartCtrl_1_io_readBreak_regNext; + wire when_UartCtrl_l155; + reg when_BusSlaveFactory_l335_2; + wire when_BusSlaveFactory_l341_2; + reg bridge_misc_doBreak; + reg when_BusSlaveFactory_l371; + wire when_BusSlaveFactory_l373; + reg when_BusSlaveFactory_l335_3; + wire when_BusSlaveFactory_l341_3; + wire [1:0] _zz_bridge_uartConfigReg_frame_parity; + wire [0:0] _zz_bridge_uartConfigReg_frame_stop; + wire when_BmbSlaveFactory_l71; + `ifndef SYNTHESIS + reg [23:0] bridge_uartConfigReg_frame_stop_string; + reg [31:0] bridge_uartConfigReg_frame_parity_string; + reg [31:0] _zz_bridge_uartConfigReg_frame_parity_string; + reg [23:0] _zz_bridge_uartConfigReg_frame_stop_string; + `endif + + + assign _zz_bridge_misc_readError = 1'b0; + assign _zz_bridge_misc_readOverflowError = 1'b0; + assign _zz_bridge_misc_breakDetected = 1'b0; + assign _zz_bridge_misc_doBreak = 1'b1; + assign _zz_bridge_misc_doBreak_1 = 1'b0; + assign _zz_busCtrl_rsp_payload_fragment_data = (8'h80 - bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy); + assign _zz_bridge_uartConfigReg_clockDivider_1 = io_bus_cmd_payload_fragment_data[19 : 0]; + assign _zz_bridge_uartConfigReg_clockDivider = _zz_bridge_uartConfigReg_clockDivider_1; + UartCtrl uartCtrl_1 ( + .io_config_frame_dataLength (bridge_uartConfigReg_frame_dataLength[2:0] ), //i + .io_config_frame_stop (bridge_uartConfigReg_frame_stop ), //i + .io_config_frame_parity (bridge_uartConfigReg_frame_parity[1:0] ), //i + .io_config_clockDivider (bridge_uartConfigReg_clockDivider[19:0] ), //i + .io_write_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //i + .io_write_ready (uartCtrl_1_io_write_ready ), //o + .io_write_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0]), //i + .io_read_valid (uartCtrl_1_io_read_valid ), //o + .io_read_ready (uartCtrl_1_io_read_queueWithOccupancy_io_push_ready ), //i + .io_read_payload (uartCtrl_1_io_read_payload[7:0] ), //o + .io_uart_txd (uartCtrl_1_io_uart_txd ), //o + .io_uart_rxd (io_uart_rxd ), //i + .io_readError (uartCtrl_1_io_readError ), //o + .io_writeBreak (bridge_misc_doBreak ), //i + .io_readBreak (uartCtrl_1_io_readBreak ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + StreamFifo bridge_write_streamUnbuffered_queueWithOccupancy ( + .io_push_valid (bridge_write_streamUnbuffered_valid ), //i + .io_push_ready (bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready ), //o + .io_push_payload (bridge_write_streamUnbuffered_payload[7:0] ), //i + .io_pop_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (uartCtrl_1_io_write_ready ), //i + .io_pop_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy[7:0] ), //o + .io_availability (bridge_write_streamUnbuffered_queueWithOccupancy_io_availability[7:0]), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + StreamFifo uartCtrl_1_io_read_queueWithOccupancy ( + .io_push_valid (uartCtrl_1_io_read_valid ), //i + .io_push_ready (uartCtrl_1_io_read_queueWithOccupancy_io_push_ready ), //o + .io_push_payload (uartCtrl_1_io_read_payload[7:0] ), //i + .io_pop_valid (uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready ), //i + .io_pop_payload (uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (uartCtrl_1_io_read_queueWithOccupancy_io_occupancy[7:0] ), //o + .io_availability (uartCtrl_1_io_read_queueWithOccupancy_io_availability[7:0]), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(bridge_uartConfigReg_frame_stop) + UartStopType_ONE : bridge_uartConfigReg_frame_stop_string = "ONE"; + UartStopType_TWO : bridge_uartConfigReg_frame_stop_string = "TWO"; + default : bridge_uartConfigReg_frame_stop_string = "???"; + endcase + end + always @(*) begin + case(bridge_uartConfigReg_frame_parity) + UartParityType_NONE : bridge_uartConfigReg_frame_parity_string = "NONE"; + UartParityType_EVEN : bridge_uartConfigReg_frame_parity_string = "EVEN"; + UartParityType_ODD : bridge_uartConfigReg_frame_parity_string = "ODD "; + default : bridge_uartConfigReg_frame_parity_string = "????"; + endcase + end + always @(*) begin + case(_zz_bridge_uartConfigReg_frame_parity) + UartParityType_NONE : _zz_bridge_uartConfigReg_frame_parity_string = "NONE"; + UartParityType_EVEN : _zz_bridge_uartConfigReg_frame_parity_string = "EVEN"; + UartParityType_ODD : _zz_bridge_uartConfigReg_frame_parity_string = "ODD "; + default : _zz_bridge_uartConfigReg_frame_parity_string = "????"; + endcase + end + always @(*) begin + case(_zz_bridge_uartConfigReg_frame_stop) + UartStopType_ONE : _zz_bridge_uartConfigReg_frame_stop_string = "ONE"; + UartStopType_TWO : _zz_bridge_uartConfigReg_frame_stop_string = "TWO"; + default : _zz_bridge_uartConfigReg_frame_stop_string = "???"; + endcase + end + `endif + + assign io_uart_txd = uartCtrl_1_io_uart_txd; + assign busCtrl_readHaltTrigger = 1'b0; + assign busCtrl_writeHaltTrigger = 1'b0; + assign _zz_io_bus_rsp_valid = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); + assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready && _zz_io_bus_rsp_valid); + always @(*) begin + _zz_busCtrl_rsp_ready = io_bus_rsp_ready; + if(when_Stream_l368) begin + _zz_busCtrl_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! _zz_io_bus_rsp_valid_1); + assign _zz_io_bus_rsp_valid_1 = _zz_io_bus_rsp_valid_2; + assign io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; + assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; + assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; + assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; + assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; + assign busCtrl_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign busCtrl_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign io_bus_cmd_fire_1 = (io_bus_cmd_valid && io_bus_cmd_ready); + assign busCtrl_doRead = (io_bus_cmd_fire_1 && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign busCtrl_rsp_valid = io_bus_cmd_valid; + assign io_bus_cmd_ready = busCtrl_rsp_ready; + assign busCtrl_rsp_payload_last = 1'b1; + assign busCtrl_rsp_payload_fragment_opcode = 1'b0; + always @(*) begin + busCtrl_rsp_payload_fragment_data = 32'h0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + busCtrl_rsp_payload_fragment_data[16 : 16] = (bridge_read_streamBreaked_valid ^ 1'b0); + busCtrl_rsp_payload_fragment_data[7 : 0] = bridge_read_streamBreaked_payload; + end + 6'h04 : begin + busCtrl_rsp_payload_fragment_data[23 : 16] = _zz_busCtrl_rsp_payload_fragment_data; + busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; + busCtrl_rsp_payload_fragment_data[31 : 24] = uartCtrl_1_io_read_queueWithOccupancy_io_occupancy; + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_interruptCtrl_writeIntEnable; + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_interruptCtrl_readIntEnable; + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_interruptCtrl_writeInt; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_interruptCtrl_readInt; + end + 6'h10 : begin + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_misc_readError; + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_misc_readOverflowError; + busCtrl_rsp_payload_fragment_data[8 : 8] = uartCtrl_1_io_readBreak; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_misc_breakDetected; + end + default : begin + end + endcase + end + + assign busCtrl_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; + always @(*) begin + _zz_bridge_write_streamUnbuffered_valid = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + if(busCtrl_doWrite) begin + _zz_bridge_write_streamUnbuffered_valid = 1'b1; + end + end + default : begin + end + endcase + end + + assign bridge_write_streamUnbuffered_valid = _zz_bridge_write_streamUnbuffered_valid; + assign bridge_write_streamUnbuffered_payload = io_bus_cmd_payload_fragment_data[7 : 0]; + assign bridge_write_streamUnbuffered_ready = bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + always @(*) begin + bridge_read_streamBreaked_valid = uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid; + if(uartCtrl_1_io_readBreak) begin + bridge_read_streamBreaked_valid = 1'b0; + end + end + + always @(*) begin + uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready = bridge_read_streamBreaked_ready; + if(uartCtrl_1_io_readBreak) begin + uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready = 1'b1; + end + end + + assign bridge_read_streamBreaked_payload = uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload; + always @(*) begin + bridge_read_streamBreaked_ready = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + if(busCtrl_doRead) begin + bridge_read_streamBreaked_ready = 1'b1; + end + end + default : begin + end + endcase + end + + assign bridge_interruptCtrl_readInt = (bridge_interruptCtrl_readIntEnable && bridge_read_streamBreaked_valid); + assign bridge_interruptCtrl_writeInt = (bridge_interruptCtrl_writeIntEnable && (! bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid)); + assign bridge_interruptCtrl_interrupt = (bridge_interruptCtrl_readInt || bridge_interruptCtrl_writeInt); + always @(*) begin + when_BusSlaveFactory_l335 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l335 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l341 = io_bus_cmd_payload_fragment_data[0]; + always @(*) begin + when_BusSlaveFactory_l335_1 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l335_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l341_1 = io_bus_cmd_payload_fragment_data[1]; + assign uartCtrl_1_io_read_isStall = (uartCtrl_1_io_read_valid && (! uartCtrl_1_io_read_queueWithOccupancy_io_push_ready)); + assign when_UartCtrl_l155 = (uartCtrl_1_io_readBreak && (! uartCtrl_1_io_readBreak_regNext)); + always @(*) begin + when_BusSlaveFactory_l335_2 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l335_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l341_2 = io_bus_cmd_payload_fragment_data[9]; + always @(*) begin + when_BusSlaveFactory_l371 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l371 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l373 = io_bus_cmd_payload_fragment_data[10]; + always @(*) begin + when_BusSlaveFactory_l335_3 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l335_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l341_3 = io_bus_cmd_payload_fragment_data[11]; + assign io_interrupt = bridge_interruptCtrl_interrupt; + assign _zz_bridge_uartConfigReg_frame_parity = io_bus_cmd_payload_fragment_data[9 : 8]; + assign _zz_bridge_uartConfigReg_frame_stop = io_bus_cmd_payload_fragment_data[16 : 16]; + assign when_BmbSlaveFactory_l71 = ((io_bus_cmd_payload_fragment_address & (~ 6'h03)) == 6'h08); + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + _zz_io_bus_rsp_valid_2 <= 1'b0; + bridge_uartConfigReg_clockDivider <= 20'h0; + bridge_uartConfigReg_clockDivider <= 20'h00035; + bridge_uartConfigReg_frame_dataLength <= 3'b111; + bridge_uartConfigReg_frame_parity <= UartParityType_NONE; + bridge_uartConfigReg_frame_stop <= UartStopType_ONE; + bridge_interruptCtrl_writeIntEnable <= 1'b0; + bridge_interruptCtrl_readIntEnable <= 1'b0; + bridge_misc_readError <= 1'b0; + bridge_misc_readOverflowError <= 1'b0; + bridge_misc_breakDetected <= 1'b0; + bridge_misc_doBreak <= 1'b0; + end else begin + if(_zz_busCtrl_rsp_ready) begin + _zz_io_bus_rsp_valid_2 <= (busCtrl_rsp_valid && _zz_io_bus_rsp_valid); + end + if(when_BusSlaveFactory_l335) begin + if(when_BusSlaveFactory_l341) begin + bridge_misc_readError <= _zz_bridge_misc_readError[0]; + end + end + if(uartCtrl_1_io_readError) begin + bridge_misc_readError <= 1'b1; + end + if(when_BusSlaveFactory_l335_1) begin + if(when_BusSlaveFactory_l341_1) begin + bridge_misc_readOverflowError <= _zz_bridge_misc_readOverflowError[0]; + end + end + if(uartCtrl_1_io_read_isStall) begin + bridge_misc_readOverflowError <= 1'b1; + end + if(when_UartCtrl_l155) begin + bridge_misc_breakDetected <= 1'b1; + end + if(when_BusSlaveFactory_l335_2) begin + if(when_BusSlaveFactory_l341_2) begin + bridge_misc_breakDetected <= _zz_bridge_misc_breakDetected[0]; + end + end + if(when_BusSlaveFactory_l371) begin + if(when_BusSlaveFactory_l373) begin + bridge_misc_doBreak <= _zz_bridge_misc_doBreak[0]; + end + end + if(when_BusSlaveFactory_l335_3) begin + if(when_BusSlaveFactory_l341_3) begin + bridge_misc_doBreak <= _zz_bridge_misc_doBreak_1[0]; + end + end + case(io_bus_cmd_payload_fragment_address) + 6'h0c : begin + if(busCtrl_doWrite) begin + bridge_uartConfigReg_frame_dataLength <= io_bus_cmd_payload_fragment_data[2 : 0]; + bridge_uartConfigReg_frame_parity <= _zz_bridge_uartConfigReg_frame_parity; + bridge_uartConfigReg_frame_stop <= _zz_bridge_uartConfigReg_frame_stop; + end + end + 6'h04 : begin + if(busCtrl_doWrite) begin + bridge_interruptCtrl_writeIntEnable <= io_bus_cmd_payload_fragment_data[0]; + bridge_interruptCtrl_readIntEnable <= io_bus_cmd_payload_fragment_data[1]; + end + end + default : begin + end + endcase + if(when_BmbSlaveFactory_l71) begin + if(busCtrl_doWrite) begin + bridge_uartConfigReg_clockDivider[19 : 0] <= _zz_bridge_uartConfigReg_clockDivider; + end + end + end + end + + always @(posedge io_systemClk) begin + if(_zz_busCtrl_rsp_ready) begin + _zz_io_bus_rsp_payload_last <= busCtrl_rsp_payload_last; + _zz_io_bus_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; + _zz_io_bus_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; + _zz_io_bus_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; + end + uartCtrl_1_io_readBreak_regNext <= uartCtrl_1_io_readBreak; + end + + +endmodule + +module BmbClint ( + input io_bus_cmd_valid, + output io_bus_cmd_ready, + input io_bus_cmd_payload_last, + input [0:0] io_bus_cmd_payload_fragment_opcode, + input [15:0] io_bus_cmd_payload_fragment_address, + input [1:0] io_bus_cmd_payload_fragment_length, + input [31:0] io_bus_cmd_payload_fragment_data, + input [3:0] io_bus_cmd_payload_fragment_context, + output io_bus_rsp_valid, + input io_bus_rsp_ready, + output io_bus_rsp_payload_last, + output [0:0] io_bus_rsp_payload_fragment_opcode, + output [31:0] io_bus_rsp_payload_fragment_data, + output [3:0] io_bus_rsp_payload_fragment_context, + output [0:0] io_timerInterrupt, + output [0:0] io_softwareInterrupt, + output [63:0] io_time, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire [31:0] _zz_logic_harts_0_cmp; + wire [31:0] _zz_logic_harts_0_cmp_1; + wire [31:0] _zz_logic_harts_0_cmp_2; + wire [31:0] _zz_logic_harts_0_cmp_3; + wire factory_readHaltTrigger; + wire factory_writeHaltTrigger; + wire factory_rsp_valid; + wire factory_rsp_ready; + wire factory_rsp_payload_last; + wire [0:0] factory_rsp_payload_fragment_opcode; + reg [31:0] factory_rsp_payload_fragment_data; + wire [3:0] factory_rsp_payload_fragment_context; + wire _zz_io_bus_rsp_valid; + reg _zz_factory_rsp_ready; + wire _zz_io_bus_rsp_valid_1; + reg _zz_io_bus_rsp_valid_2; + reg _zz_io_bus_rsp_payload_last; + reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_bus_rsp_payload_fragment_data; + reg [3:0] _zz_io_bus_rsp_payload_fragment_context; + wire when_Stream_l368; + wire factory_askWrite; + wire factory_askRead; + wire io_bus_cmd_fire; + wire factory_doWrite; + wire io_bus_cmd_fire_1; + wire factory_doRead; + reg [63:0] logic_time; + reg [63:0] logic_harts_0_cmp; + reg logic_harts_0_timerInterrupt; + reg logic_harts_0_softwareInterrupt; + wire [63:0] _zz_factory_rsp_payload_fragment_data; + wire when_BmbSlaveFactory_l71; + wire when_BmbSlaveFactory_l71_1; + wire when_BmbSlaveFactory_l71_2; + wire when_BmbSlaveFactory_l71_3; + + assign _zz_logic_harts_0_cmp_1 = io_bus_cmd_payload_fragment_data[31 : 0]; + assign _zz_logic_harts_0_cmp = _zz_logic_harts_0_cmp_1; + assign _zz_logic_harts_0_cmp_3 = io_bus_cmd_payload_fragment_data[31 : 0]; + assign _zz_logic_harts_0_cmp_2 = _zz_logic_harts_0_cmp_3; + assign factory_readHaltTrigger = 1'b0; + assign factory_writeHaltTrigger = 1'b0; + assign _zz_io_bus_rsp_valid = (! (factory_readHaltTrigger || factory_writeHaltTrigger)); + assign factory_rsp_ready = (_zz_factory_rsp_ready && _zz_io_bus_rsp_valid); + always @(*) begin + _zz_factory_rsp_ready = io_bus_rsp_ready; + if(when_Stream_l368) begin + _zz_factory_rsp_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! _zz_io_bus_rsp_valid_1); + assign _zz_io_bus_rsp_valid_1 = _zz_io_bus_rsp_valid_2; + assign io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; + assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; + assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; + assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; + assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; + assign factory_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign factory_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign factory_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign io_bus_cmd_fire_1 = (io_bus_cmd_valid && io_bus_cmd_ready); + assign factory_doRead = (io_bus_cmd_fire_1 && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign factory_rsp_valid = io_bus_cmd_valid; + assign io_bus_cmd_ready = factory_rsp_ready; + assign factory_rsp_payload_last = 1'b1; + assign factory_rsp_payload_fragment_opcode = 1'b0; + always @(*) begin + factory_rsp_payload_fragment_data = 32'h0; + case(io_bus_cmd_payload_fragment_address) + 16'h0 : begin + factory_rsp_payload_fragment_data[0 : 0] = logic_harts_0_softwareInterrupt; + end + default : begin + end + endcase + if(when_BmbSlaveFactory_l71) begin + factory_rsp_payload_fragment_data[31 : 0] = _zz_factory_rsp_payload_fragment_data[31 : 0]; + end + if(when_BmbSlaveFactory_l71_1) begin + factory_rsp_payload_fragment_data[31 : 0] = _zz_factory_rsp_payload_fragment_data[63 : 32]; + end + end + + assign factory_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; + assign _zz_factory_rsp_payload_fragment_data = logic_time; + assign io_timerInterrupt[0] = logic_harts_0_timerInterrupt; + assign io_softwareInterrupt[0] = logic_harts_0_softwareInterrupt; + assign io_time = logic_time; + assign when_BmbSlaveFactory_l71 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'hbff8); + assign when_BmbSlaveFactory_l71_1 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'hbffc); + assign when_BmbSlaveFactory_l71_2 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'h4000); + assign when_BmbSlaveFactory_l71_3 = ((io_bus_cmd_payload_fragment_address & (~ 16'h0003)) == 16'h4004); + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + _zz_io_bus_rsp_valid_2 <= 1'b0; + logic_time <= 64'h0; + logic_harts_0_softwareInterrupt <= 1'b0; + end else begin + if(_zz_factory_rsp_ready) begin + _zz_io_bus_rsp_valid_2 <= (factory_rsp_valid && _zz_io_bus_rsp_valid); + end + logic_time <= (logic_time + 64'h0000000000000001); + case(io_bus_cmd_payload_fragment_address) + 16'h0 : begin + if(factory_doWrite) begin + logic_harts_0_softwareInterrupt <= io_bus_cmd_payload_fragment_data[0]; + end + end + default : begin + end + endcase + end + end + + always @(posedge io_systemClk) begin + if(_zz_factory_rsp_ready) begin + _zz_io_bus_rsp_payload_last <= factory_rsp_payload_last; + _zz_io_bus_rsp_payload_fragment_opcode <= factory_rsp_payload_fragment_opcode; + _zz_io_bus_rsp_payload_fragment_data <= factory_rsp_payload_fragment_data; + _zz_io_bus_rsp_payload_fragment_context <= factory_rsp_payload_fragment_context; + end + logic_harts_0_timerInterrupt <= (logic_harts_0_cmp <= logic_time); + if(when_BmbSlaveFactory_l71_2) begin + if(factory_doWrite) begin + logic_harts_0_cmp[31 : 0] <= _zz_logic_harts_0_cmp; + end + end + if(when_BmbSlaveFactory_l71_3) begin + if(factory_doWrite) begin + logic_harts_0_cmp[63 : 32] <= _zz_logic_harts_0_cmp_2; + end + end + end + + +endmodule + +module BmbDecoder_3 ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [23:0] io_input_cmd_payload_fragment_address, + input [1:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_mask, + input [3:0] io_input_cmd_payload_fragment_context, + output reg io_input_rsp_valid, + input io_input_rsp_ready, + output reg io_input_rsp_payload_last, + output reg [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output reg [3:0] io_input_rsp_payload_fragment_context, + output reg io_outputs_0_cmd_valid, + input io_outputs_0_cmd_ready, + output io_outputs_0_cmd_payload_last, + output [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output [23:0] io_outputs_0_cmd_payload_fragment_address, + output [1:0] io_outputs_0_cmd_payload_fragment_length, + output [31:0] io_outputs_0_cmd_payload_fragment_data, + output [3:0] io_outputs_0_cmd_payload_fragment_mask, + output [3:0] io_outputs_0_cmd_payload_fragment_context, + input io_outputs_0_rsp_valid, + output io_outputs_0_rsp_ready, + input io_outputs_0_rsp_payload_last, + input [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input [31:0] io_outputs_0_rsp_payload_fragment_data, + input [3:0] io_outputs_0_rsp_payload_fragment_context, + output reg io_outputs_1_cmd_valid, + input io_outputs_1_cmd_ready, + output io_outputs_1_cmd_payload_last, + output [0:0] io_outputs_1_cmd_payload_fragment_opcode, + output [23:0] io_outputs_1_cmd_payload_fragment_address, + output [1:0] io_outputs_1_cmd_payload_fragment_length, + output [31:0] io_outputs_1_cmd_payload_fragment_data, + output [3:0] io_outputs_1_cmd_payload_fragment_mask, + output [3:0] io_outputs_1_cmd_payload_fragment_context, + input io_outputs_1_rsp_valid, + output io_outputs_1_rsp_ready, + input io_outputs_1_rsp_payload_last, + input [0:0] io_outputs_1_rsp_payload_fragment_opcode, + input [31:0] io_outputs_1_rsp_payload_fragment_data, + input [3:0] io_outputs_1_rsp_payload_fragment_context, + output reg io_outputs_2_cmd_valid, + input io_outputs_2_cmd_ready, + output io_outputs_2_cmd_payload_last, + output [0:0] io_outputs_2_cmd_payload_fragment_opcode, + output [23:0] io_outputs_2_cmd_payload_fragment_address, + output [1:0] io_outputs_2_cmd_payload_fragment_length, + output [31:0] io_outputs_2_cmd_payload_fragment_data, + output [3:0] io_outputs_2_cmd_payload_fragment_mask, + output [3:0] io_outputs_2_cmd_payload_fragment_context, + input io_outputs_2_rsp_valid, + output io_outputs_2_rsp_ready, + input io_outputs_2_rsp_payload_last, + input [0:0] io_outputs_2_rsp_payload_fragment_opcode, + input [31:0] io_outputs_2_rsp_payload_fragment_data, + input [3:0] io_outputs_2_rsp_payload_fragment_context, + output reg io_outputs_3_cmd_valid, + input io_outputs_3_cmd_ready, + output io_outputs_3_cmd_payload_last, + output [0:0] io_outputs_3_cmd_payload_fragment_opcode, + output [23:0] io_outputs_3_cmd_payload_fragment_address, + output [1:0] io_outputs_3_cmd_payload_fragment_length, + output [31:0] io_outputs_3_cmd_payload_fragment_data, + output [3:0] io_outputs_3_cmd_payload_fragment_mask, + output [3:0] io_outputs_3_cmd_payload_fragment_context, + input io_outputs_3_rsp_valid, + output io_outputs_3_rsp_ready, + input io_outputs_3_rsp_payload_last, + input [0:0] io_outputs_3_rsp_payload_fragment_opcode, + input [31:0] io_outputs_3_rsp_payload_fragment_data, + input [3:0] io_outputs_3_rsp_payload_fragment_context, + output reg io_outputs_4_cmd_valid, + input io_outputs_4_cmd_ready, + output io_outputs_4_cmd_payload_last, + output [0:0] io_outputs_4_cmd_payload_fragment_opcode, + output [23:0] io_outputs_4_cmd_payload_fragment_address, + output [1:0] io_outputs_4_cmd_payload_fragment_length, + output [31:0] io_outputs_4_cmd_payload_fragment_data, + output [3:0] io_outputs_4_cmd_payload_fragment_mask, + output [3:0] io_outputs_4_cmd_payload_fragment_context, + input io_outputs_4_rsp_valid, + output io_outputs_4_rsp_ready, + input io_outputs_4_rsp_payload_last, + input [0:0] io_outputs_4_rsp_payload_fragment_opcode, + input [31:0] io_outputs_4_rsp_payload_fragment_data, + input [3:0] io_outputs_4_rsp_payload_fragment_context, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire [3:0] _zz_logic_rspPendingCounter; + wire [3:0] _zz_logic_rspPendingCounter_1; + wire [0:0] _zz_logic_rspPendingCounter_2; + wire [3:0] _zz_logic_rspPendingCounter_3; + wire [0:0] _zz_logic_rspPendingCounter_4; + reg _zz_io_input_rsp_payload_last_3; + reg [0:0] _zz_io_input_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_input_rsp_payload_fragment_data; + reg [3:0] _zz_io_input_rsp_payload_fragment_context; + wire logic_input_valid; + reg logic_input_ready; + wire logic_input_payload_last; + wire [0:0] logic_input_payload_fragment_opcode; + wire [23:0] logic_input_payload_fragment_address; + wire [1:0] logic_input_payload_fragment_length; + wire [31:0] logic_input_payload_fragment_data; + wire [3:0] logic_input_payload_fragment_mask; + wire [3:0] logic_input_payload_fragment_context; + reg io_input_cmd_rValid; + wire logic_input_fire; + reg io_input_cmd_rData_last; + reg [0:0] io_input_cmd_rData_fragment_opcode; + reg [23:0] io_input_cmd_rData_fragment_address; + reg [1:0] io_input_cmd_rData_fragment_length; + reg [31:0] io_input_cmd_rData_fragment_data; + reg [3:0] io_input_cmd_rData_fragment_mask; + reg [3:0] io_input_cmd_rData_fragment_context; + wire logic_hitsS0_0; + wire logic_hitsS0_1; + wire logic_hitsS0_2; + wire logic_hitsS0_3; + wire logic_hitsS0_4; + wire logic_noHitS0; + wire io_input_cmd_fire; + reg logic_hitsS1_0; + reg logic_hitsS1_1; + reg logic_hitsS1_2; + reg logic_hitsS1_3; + reg logic_hitsS1_4; + wire io_input_cmd_fire_1; + reg logic_noHitS1; + wire _zz_io_outputs_0_cmd_payload_last; + wire _zz_io_outputs_1_cmd_payload_last; + wire _zz_io_outputs_2_cmd_payload_last; + wire _zz_io_outputs_3_cmd_payload_last; + wire _zz_io_outputs_4_cmd_payload_last; + reg [3:0] logic_rspPendingCounter; + wire logic_input_fire_1; + wire io_input_rsp_fire; + wire logic_cmdWait; + wire when_BmbDecoder_l56; + reg logic_rspHits_0; + reg logic_rspHits_1; + reg logic_rspHits_2; + reg logic_rspHits_3; + reg logic_rspHits_4; + wire logic_rspPending; + wire logic_rspNoHitValid; + reg logic_rspNoHit_doIt; + wire io_input_rsp_fire_1; + wire when_BmbDecoder_l60; + wire logic_input_fire_2; + wire when_BmbDecoder_l60_1; + wire logic_input_fire_3; + reg logic_rspNoHit_singleBeatRsp; + wire logic_input_fire_4; + wire logic_input_fire_5; + reg [3:0] logic_rspNoHit_context; + wire logic_input_fire_6; + wire _zz_io_input_rsp_payload_last; + wire _zz_io_input_rsp_payload_last_1; + wire [2:0] _zz_io_input_rsp_payload_last_2; + + assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); + assign _zz_logic_rspPendingCounter_2 = (logic_input_fire_1 && logic_input_payload_last); + assign _zz_logic_rspPendingCounter_1 = {3'd0, _zz_logic_rspPendingCounter_2}; + assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign _zz_logic_rspPendingCounter_3 = {3'd0, _zz_logic_rspPendingCounter_4}; + always @(*) begin + case(_zz_io_input_rsp_payload_last_2) + 3'b000 : begin + _zz_io_input_rsp_payload_last_3 = io_outputs_0_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_0_rsp_payload_fragment_context; + end + 3'b001 : begin + _zz_io_input_rsp_payload_last_3 = io_outputs_1_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_1_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_1_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_1_rsp_payload_fragment_context; + end + 3'b010 : begin + _zz_io_input_rsp_payload_last_3 = io_outputs_2_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_2_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_2_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_2_rsp_payload_fragment_context; + end + 3'b011 : begin + _zz_io_input_rsp_payload_last_3 = io_outputs_3_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_3_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_3_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_3_rsp_payload_fragment_context; + end + default : begin + _zz_io_input_rsp_payload_last_3 = io_outputs_4_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_4_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_4_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_4_rsp_payload_fragment_context; + end + endcase + end + + assign logic_input_fire = (logic_input_valid && logic_input_ready); + assign io_input_cmd_ready = (! io_input_cmd_rValid); + assign logic_input_valid = io_input_cmd_rValid; + assign logic_input_payload_last = io_input_cmd_rData_last; + assign logic_input_payload_fragment_opcode = io_input_cmd_rData_fragment_opcode; + assign logic_input_payload_fragment_address = io_input_cmd_rData_fragment_address; + assign logic_input_payload_fragment_length = io_input_cmd_rData_fragment_length; + assign logic_input_payload_fragment_data = io_input_cmd_rData_fragment_data; + assign logic_input_payload_fragment_mask = io_input_cmd_rData_fragment_mask; + assign logic_input_payload_fragment_context = io_input_cmd_rData_fragment_context; + assign logic_noHitS0 = (! ({logic_hitsS0_4,{logic_hitsS0_3,{logic_hitsS0_2,{logic_hitsS0_1,logic_hitsS0_0}}}} != 5'h0)); + assign io_input_cmd_fire = (io_input_cmd_valid && io_input_cmd_ready); + assign io_input_cmd_fire_1 = (io_input_cmd_valid && io_input_cmd_ready); + assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 24'h3fffff)) == 24'hc00000); + always @(*) begin + io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS1_0); + if(logic_cmdWait) begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; + assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; + assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_0_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_1 = ((io_input_cmd_payload_fragment_address & (~ 24'h00ffff)) == 24'hb00000); + always @(*) begin + io_outputs_1_cmd_valid = (logic_input_valid && logic_hitsS1_1); + if(logic_cmdWait) begin + io_outputs_1_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_1_cmd_payload_last = logic_input_payload_last; + assign io_outputs_1_cmd_payload_last = _zz_io_outputs_1_cmd_payload_last; + assign io_outputs_1_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_1_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_1_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_1_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_1_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_1_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_2 = ((io_input_cmd_payload_fragment_address & (~ 24'h00003f)) == 24'h010000); + always @(*) begin + io_outputs_2_cmd_valid = (logic_input_valid && logic_hitsS1_2); + if(logic_cmdWait) begin + io_outputs_2_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_2_cmd_payload_last = logic_input_payload_last; + assign io_outputs_2_cmd_payload_last = _zz_io_outputs_2_cmd_payload_last; + assign io_outputs_2_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_2_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_2_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_2_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_2_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_2_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_3 = ((io_input_cmd_payload_fragment_address & (~ 24'h000fff)) == 24'h014000); + always @(*) begin + io_outputs_3_cmd_valid = (logic_input_valid && logic_hitsS1_3); + if(logic_cmdWait) begin + io_outputs_3_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_3_cmd_payload_last = logic_input_payload_last; + assign io_outputs_3_cmd_payload_last = _zz_io_outputs_3_cmd_payload_last; + assign io_outputs_3_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_3_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_3_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_3_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_3_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_3_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_4 = ((io_input_cmd_payload_fragment_address & (~ 24'h00ffff)) == 24'h100000); + always @(*) begin + io_outputs_4_cmd_valid = (logic_input_valid && logic_hitsS1_4); + if(logic_cmdWait) begin + io_outputs_4_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_4_cmd_payload_last = logic_input_payload_last; + assign io_outputs_4_cmd_payload_last = _zz_io_outputs_4_cmd_payload_last; + assign io_outputs_4_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_4_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_4_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_4_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_4_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_4_cmd_payload_fragment_context = logic_input_payload_fragment_context; + always @(*) begin + logic_input_ready = (({(logic_hitsS1_4 && io_outputs_4_cmd_ready),{(logic_hitsS1_3 && io_outputs_3_cmd_ready),{(logic_hitsS1_2 && io_outputs_2_cmd_ready),{(logic_hitsS1_1 && io_outputs_1_cmd_ready),(logic_hitsS1_0 && io_outputs_0_cmd_ready)}}}} != 5'h0) || logic_noHitS1); + if(logic_cmdWait) begin + logic_input_ready = 1'b0; + end + end + + assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); + assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); + assign logic_rspPending = (logic_rspPendingCounter != 4'b0000); + assign logic_rspNoHitValid = (! ({logic_rspHits_4,{logic_rspHits_3,{logic_rspHits_2,{logic_rspHits_1,logic_rspHits_0}}}} != 5'h0)); + assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); + assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); + assign when_BmbDecoder_l60_1 = ((logic_input_fire_2 && logic_noHitS1) && logic_input_payload_last); + assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_6 = (logic_input_valid && logic_input_ready); + always @(*) begin + io_input_rsp_valid = (({io_outputs_4_rsp_valid,{io_outputs_3_rsp_valid,{io_outputs_2_rsp_valid,{io_outputs_1_rsp_valid,io_outputs_0_rsp_valid}}}} != 5'h0) || (logic_rspPending && logic_rspNoHitValid)); + if(logic_rspNoHit_doIt) begin + io_input_rsp_valid = 1'b1; + end + end + + assign _zz_io_input_rsp_payload_last = (logic_rspHits_1 || logic_rspHits_3); + assign _zz_io_input_rsp_payload_last_1 = (logic_rspHits_2 || logic_rspHits_3); + assign _zz_io_input_rsp_payload_last_2 = {logic_rspHits_4,{_zz_io_input_rsp_payload_last_1,_zz_io_input_rsp_payload_last}}; + always @(*) begin + io_input_rsp_payload_last = _zz_io_input_rsp_payload_last_3; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_last = 1'b1; + end + end + + always @(*) begin + io_input_rsp_payload_fragment_opcode = _zz_io_input_rsp_payload_fragment_opcode; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_opcode = 1'b1; + end + end + + assign io_input_rsp_payload_fragment_data = _zz_io_input_rsp_payload_fragment_data; + always @(*) begin + io_input_rsp_payload_fragment_context = _zz_io_input_rsp_payload_fragment_context; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_context = logic_rspNoHit_context; + end + end + + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign io_outputs_1_rsp_ready = io_input_rsp_ready; + assign io_outputs_2_rsp_ready = io_input_rsp_ready; + assign io_outputs_3_rsp_ready = io_input_rsp_ready; + assign io_outputs_4_rsp_ready = io_input_rsp_ready; + assign logic_cmdWait = ((logic_rspPending && ((((((logic_hitsS1_0 != logic_rspHits_0) || (logic_hitsS1_1 != logic_rspHits_1)) || (logic_hitsS1_2 != logic_rspHits_2)) || (logic_hitsS1_3 != logic_rspHits_3)) || (logic_hitsS1_4 != logic_rspHits_4)) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 4'b1000)); + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + io_input_cmd_rValid <= 1'b0; + logic_rspPendingCounter <= 4'b0000; + logic_rspNoHit_doIt <= 1'b0; + end else begin + if(io_input_cmd_valid) begin + io_input_cmd_rValid <= 1'b1; + end + if(logic_input_fire) begin + io_input_cmd_rValid <= 1'b0; + end + logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); + if(when_BmbDecoder_l60) begin + logic_rspNoHit_doIt <= 1'b0; + end + if(when_BmbDecoder_l60_1) begin + logic_rspNoHit_doIt <= 1'b1; + end + end + end + + always @(posedge io_systemClk) begin + if(io_input_cmd_ready) begin + io_input_cmd_rData_last <= io_input_cmd_payload_last; + io_input_cmd_rData_fragment_opcode <= io_input_cmd_payload_fragment_opcode; + io_input_cmd_rData_fragment_address <= io_input_cmd_payload_fragment_address; + io_input_cmd_rData_fragment_length <= io_input_cmd_payload_fragment_length; + io_input_cmd_rData_fragment_data <= io_input_cmd_payload_fragment_data; + io_input_cmd_rData_fragment_mask <= io_input_cmd_payload_fragment_mask; + io_input_cmd_rData_fragment_context <= io_input_cmd_payload_fragment_context; + end + if(io_input_cmd_fire) begin + logic_hitsS1_0 <= logic_hitsS0_0; + logic_hitsS1_1 <= logic_hitsS0_1; + logic_hitsS1_2 <= logic_hitsS0_2; + logic_hitsS1_3 <= logic_hitsS0_3; + logic_hitsS1_4 <= logic_hitsS0_4; + end + if(io_input_cmd_fire_1) begin + logic_noHitS1 <= logic_noHitS0; + end + if(when_BmbDecoder_l56) begin + logic_rspHits_0 <= logic_hitsS1_0; + logic_rspHits_1 <= logic_hitsS1_1; + logic_rspHits_2 <= logic_hitsS1_2; + logic_rspHits_3 <= logic_hitsS1_3; + logic_rspHits_4 <= logic_hitsS1_4; + end + if(logic_input_fire_3) begin + logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); + end + if(logic_input_fire_5) begin + logic_rspNoHit_context <= logic_input_payload_fragment_context; + end + end + + +endmodule + +//BmbUnburstify replaced by BmbUnburstify + +module BmbUnburstify ( + input io_input_cmd_valid, + output reg io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_source, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [31:0] io_input_cmd_payload_fragment_address, + input [5:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_mask, + input [0:0] io_input_cmd_payload_fragment_context, + output io_input_rsp_valid, + input io_input_rsp_ready, + output io_input_rsp_payload_last, + output [0:0] io_input_rsp_payload_fragment_source, + output [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output [0:0] io_input_rsp_payload_fragment_context, + output reg io_output_cmd_valid, + input io_output_cmd_ready, + output io_output_cmd_payload_last, + output reg [0:0] io_output_cmd_payload_fragment_opcode, + output reg [31:0] io_output_cmd_payload_fragment_address, + output reg [1:0] io_output_cmd_payload_fragment_length, + output [31:0] io_output_cmd_payload_fragment_data, + output [3:0] io_output_cmd_payload_fragment_mask, + output [3:0] io_output_cmd_payload_fragment_context, + input io_output_rsp_valid, + output reg io_output_rsp_ready, + input io_output_rsp_payload_last, + input [0:0] io_output_rsp_payload_fragment_opcode, + input [31:0] io_output_rsp_payload_fragment_data, + input [3:0] io_output_rsp_payload_fragment_context, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire [3:0] _zz_buffer_last; + wire [0:0] _zz_buffer_last_1; + wire [11:0] _zz_buffer_addressIncr; + wire [11:0] _zz_buffer_addressIncr_1; + wire [11:0] _zz_buffer_addressIncr_2; + wire doResult; + reg buffer_valid; + reg [0:0] buffer_opcode; + reg [0:0] buffer_source; + reg [31:0] buffer_address; + reg [0:0] buffer_context; + reg [3:0] buffer_beat; + wire buffer_last; + wire [31:0] buffer_addressIncr; + wire buffer_isWrite; + wire io_output_cmd_fire; + wire [3:0] cmdTransferBeatCount; + wire requireBuffer; + reg cmdContext_drop; + reg cmdContext_last; + reg [0:0] cmdContext_source; + reg [0:0] cmdContext_context; + wire io_output_cmd_fire_1; + wire rspContext_drop; + wire rspContext_last; + wire [0:0] rspContext_source; + wire [0:0] rspContext_context; + wire [3:0] _zz_rspContext_drop; + wire when_Stream_l434; + reg io_output_rsp_thrown_valid; + wire io_output_rsp_thrown_ready; + wire io_output_rsp_thrown_payload_last; + wire [0:0] io_output_rsp_thrown_payload_fragment_opcode; + wire [31:0] io_output_rsp_thrown_payload_fragment_data; + wire [3:0] io_output_rsp_thrown_payload_fragment_context; + + assign _zz_buffer_last_1 = 1'b1; + assign _zz_buffer_last = {3'd0, _zz_buffer_last_1}; + assign _zz_buffer_addressIncr = (_zz_buffer_addressIncr_1 + 12'h004); + assign _zz_buffer_addressIncr_2 = buffer_address[11 : 0]; + assign _zz_buffer_addressIncr_1 = _zz_buffer_addressIncr_2; + assign buffer_last = (buffer_beat == _zz_buffer_last); + assign buffer_addressIncr = {buffer_address[31 : 12],(_zz_buffer_addressIncr & (~ 12'h003))}; + assign buffer_isWrite = (buffer_opcode == 1'b1); + assign io_output_cmd_fire = (io_output_cmd_valid && io_output_cmd_ready); + assign cmdTransferBeatCount = io_input_cmd_payload_fragment_length[5 : 2]; + assign requireBuffer = (cmdTransferBeatCount != 4'b0000); + assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign io_output_cmd_payload_last = 1'b1; + assign io_output_cmd_payload_fragment_context = {cmdContext_context,{cmdContext_source,{cmdContext_last,cmdContext_drop}}}; + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_address = buffer_addressIncr; + end else begin + io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + if(requireBuffer) begin + io_output_cmd_payload_fragment_address[1 : 0] = 2'b00; + end + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_opcode = buffer_opcode; + end else begin + io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_length = 2'b11; + end else begin + if(requireBuffer) begin + io_output_cmd_payload_fragment_length = 2'b11; + end else begin + io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length[1:0]; + end + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_context = buffer_context; + end else begin + cmdContext_context = io_input_cmd_payload_fragment_context; + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_source = buffer_source; + end else begin + cmdContext_source = io_input_cmd_payload_fragment_source; + end + end + + always @(*) begin + io_input_cmd_ready = 1'b0; + if(buffer_valid) begin + io_input_cmd_ready = (buffer_isWrite && io_output_cmd_ready); + end else begin + io_input_cmd_ready = io_output_cmd_ready; + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_valid = (! (buffer_isWrite && (! io_input_cmd_valid))); + end else begin + io_output_cmd_valid = io_input_cmd_valid; + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_last = buffer_last; + end else begin + cmdContext_last = (! requireBuffer); + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_drop = buffer_isWrite; + end else begin + cmdContext_drop = (io_input_cmd_payload_fragment_opcode == 1'b1); + end + end + + assign io_output_cmd_fire_1 = (io_output_cmd_valid && io_output_cmd_ready); + assign _zz_rspContext_drop = io_output_rsp_payload_fragment_context; + assign rspContext_drop = _zz_rspContext_drop[0]; + assign rspContext_last = _zz_rspContext_drop[1]; + assign rspContext_source = _zz_rspContext_drop[2 : 2]; + assign rspContext_context = _zz_rspContext_drop[3 : 3]; + assign when_Stream_l434 = (! (rspContext_last || (! rspContext_drop))); + always @(*) begin + io_output_rsp_thrown_valid = io_output_rsp_valid; + if(when_Stream_l434) begin + io_output_rsp_thrown_valid = 1'b0; + end + end + + always @(*) begin + io_output_rsp_ready = io_output_rsp_thrown_ready; + if(when_Stream_l434) begin + io_output_rsp_ready = 1'b1; + end + end + + assign io_output_rsp_thrown_payload_last = io_output_rsp_payload_last; + assign io_output_rsp_thrown_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_output_rsp_thrown_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_output_rsp_thrown_payload_fragment_context = io_output_rsp_payload_fragment_context; + assign io_input_rsp_valid = io_output_rsp_thrown_valid; + assign io_output_rsp_thrown_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = rspContext_last; + assign io_input_rsp_payload_fragment_source = rspContext_source; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = rspContext_context; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + buffer_valid <= 1'b0; + end else begin + if(io_output_cmd_fire) begin + if(buffer_last) begin + buffer_valid <= 1'b0; + end + end + if(!buffer_valid) begin + buffer_valid <= (requireBuffer && io_output_cmd_fire_1); + end + end + end + + always @(posedge io_systemClk) begin + if(io_output_cmd_fire) begin + buffer_beat <= (buffer_beat - 4'b0001); + buffer_address[11 : 0] <= buffer_addressIncr[11 : 0]; + end + if(!buffer_valid) begin + buffer_opcode <= io_input_cmd_payload_fragment_opcode; + buffer_source <= io_input_cmd_payload_fragment_source; + buffer_address <= io_input_cmd_payload_fragment_address; + buffer_context <= io_input_cmd_payload_fragment_context; + buffer_beat <= cmdTransferBeatCount; + end + end + + +endmodule + +module BmbOnChipRam ( + input io_bus_cmd_valid, + output io_bus_cmd_ready, + input io_bus_cmd_payload_last, + input [0:0] io_bus_cmd_payload_fragment_opcode, + input [14:0] io_bus_cmd_payload_fragment_address, + input [1:0] io_bus_cmd_payload_fragment_length, + input [31:0] io_bus_cmd_payload_fragment_data, + input [3:0] io_bus_cmd_payload_fragment_mask, + input [3:0] io_bus_cmd_payload_fragment_context, + output io_bus_rsp_valid, + input io_bus_rsp_ready, + output io_bus_rsp_payload_last, + output [0:0] io_bus_rsp_payload_fragment_opcode, + output [31:0] io_bus_rsp_payload_fragment_data, + output [3:0] io_bus_rsp_payload_fragment_context, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [31:0] _zz_ram_port0; + wire io_bus_rsp_isStall; + reg io_bus_cmd_valid_regNextWhen; + reg [3:0] io_bus_cmd_payload_fragment_context_regNextWhen; + wire [12:0] _zz_io_bus_rsp_payload_fragment_data; + wire io_bus_cmd_fire; + wire _zz_io_bus_rsp_payload_fragment_data_1; + wire [31:0] _zz_io_bus_rsp_payload_fragment_data_2; + reg [7:0] ram_symbol0 [0:8191]; + reg [7:0] ram_symbol1 [0:8191]; + reg [7:0] ram_symbol2 [0:8191]; + reg [7:0] ram_symbol3 [0:8191]; + reg [7:0] _zz_ramsymbol_read; + reg [7:0] _zz_ramsymbol_read_1; + reg [7:0] _zz_ramsymbol_read_2; + reg [7:0] _zz_ramsymbol_read_3; + + initial begin + $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol0.bin",ram_symbol0); + $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol1.bin",ram_symbol1); + $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol2.bin",ram_symbol2); + $readmemb("EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol3.bin",ram_symbol3); + end + always @(*) begin + _zz_ram_port0 = {_zz_ramsymbol_read_3, _zz_ramsymbol_read_2, _zz_ramsymbol_read_1, _zz_ramsymbol_read}; + end + always @(posedge io_systemClk) begin + if(io_bus_cmd_fire) begin + _zz_ramsymbol_read <= ram_symbol0[_zz_io_bus_rsp_payload_fragment_data]; + _zz_ramsymbol_read_1 <= ram_symbol1[_zz_io_bus_rsp_payload_fragment_data]; + _zz_ramsymbol_read_2 <= ram_symbol2[_zz_io_bus_rsp_payload_fragment_data]; + _zz_ramsymbol_read_3 <= ram_symbol3[_zz_io_bus_rsp_payload_fragment_data]; + end + end + + always @(posedge io_systemClk) begin + if(io_bus_cmd_payload_fragment_mask[0] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin + ram_symbol0[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[7 : 0]; + end + if(io_bus_cmd_payload_fragment_mask[1] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin + ram_symbol1[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[15 : 8]; + end + if(io_bus_cmd_payload_fragment_mask[2] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin + ram_symbol2[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[23 : 16]; + end + if(io_bus_cmd_payload_fragment_mask[3] && io_bus_cmd_fire && _zz_io_bus_rsp_payload_fragment_data_1 ) begin + ram_symbol3[_zz_io_bus_rsp_payload_fragment_data] <= _zz_io_bus_rsp_payload_fragment_data_2[31 : 24]; + end + end + + assign io_bus_rsp_isStall = (io_bus_rsp_valid && (! io_bus_rsp_ready)); + assign io_bus_cmd_ready = (! io_bus_rsp_isStall); + assign io_bus_rsp_valid = io_bus_cmd_valid_regNextWhen; + assign io_bus_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context_regNextWhen; + assign _zz_io_bus_rsp_payload_fragment_data = (io_bus_cmd_payload_fragment_address >>> 2); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign _zz_io_bus_rsp_payload_fragment_data_1 = (io_bus_cmd_payload_fragment_opcode == 1'b1); + assign _zz_io_bus_rsp_payload_fragment_data_2 = io_bus_cmd_payload_fragment_data; + assign io_bus_rsp_payload_fragment_data = _zz_ram_port0; + assign io_bus_rsp_payload_fragment_opcode = 1'b0; + assign io_bus_rsp_payload_last = 1'b1; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + io_bus_cmd_valid_regNextWhen <= 1'b0; + end else begin + if(io_bus_cmd_ready) begin + io_bus_cmd_valid_regNextWhen <= io_bus_cmd_valid; + end + end + end + + always @(posedge io_systemClk) begin + if(io_bus_cmd_ready) begin + io_bus_cmd_payload_fragment_context_regNextWhen <= io_bus_cmd_payload_fragment_context; + end + end + + +endmodule + +module BmbDecoder_2 ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_source, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [31:0] io_input_cmd_payload_fragment_address, + input [5:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_mask, + input [0:0] io_input_cmd_payload_fragment_context, + output reg io_input_rsp_valid, + input io_input_rsp_ready, + output reg io_input_rsp_payload_last, + output reg [0:0] io_input_rsp_payload_fragment_source, + output reg [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output reg [0:0] io_input_rsp_payload_fragment_context, + output reg io_outputs_0_cmd_valid, + input io_outputs_0_cmd_ready, + output io_outputs_0_cmd_payload_last, + output [0:0] io_outputs_0_cmd_payload_fragment_source, + output [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output [31:0] io_outputs_0_cmd_payload_fragment_address, + output [5:0] io_outputs_0_cmd_payload_fragment_length, + output [31:0] io_outputs_0_cmd_payload_fragment_data, + output [3:0] io_outputs_0_cmd_payload_fragment_mask, + output [0:0] io_outputs_0_cmd_payload_fragment_context, + input io_outputs_0_rsp_valid, + output io_outputs_0_rsp_ready, + input io_outputs_0_rsp_payload_last, + input [0:0] io_outputs_0_rsp_payload_fragment_source, + input [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input [31:0] io_outputs_0_rsp_payload_fragment_data, + input [0:0] io_outputs_0_rsp_payload_fragment_context, + output reg io_outputs_1_cmd_valid, + input io_outputs_1_cmd_ready, + output io_outputs_1_cmd_payload_last, + output [0:0] io_outputs_1_cmd_payload_fragment_source, + output [0:0] io_outputs_1_cmd_payload_fragment_opcode, + output [31:0] io_outputs_1_cmd_payload_fragment_address, + output [5:0] io_outputs_1_cmd_payload_fragment_length, + output [31:0] io_outputs_1_cmd_payload_fragment_data, + output [3:0] io_outputs_1_cmd_payload_fragment_mask, + output [0:0] io_outputs_1_cmd_payload_fragment_context, + input io_outputs_1_rsp_valid, + output io_outputs_1_rsp_ready, + input io_outputs_1_rsp_payload_last, + input [0:0] io_outputs_1_rsp_payload_fragment_source, + input [0:0] io_outputs_1_rsp_payload_fragment_opcode, + input [31:0] io_outputs_1_rsp_payload_fragment_data, + input [0:0] io_outputs_1_rsp_payload_fragment_context, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire [6:0] _zz_logic_rspPendingCounter; + wire [6:0] _zz_logic_rspPendingCounter_1; + wire [0:0] _zz_logic_rspPendingCounter_2; + wire [6:0] _zz_logic_rspPendingCounter_3; + wire [0:0] _zz_logic_rspPendingCounter_4; + reg _zz_io_input_rsp_payload_last_1; + reg [0:0] _zz_io_input_rsp_payload_fragment_source; + reg [0:0] _zz_io_input_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_input_rsp_payload_fragment_data; + reg [0:0] _zz_io_input_rsp_payload_fragment_context; + wire logic_input_valid; + reg logic_input_ready; + wire logic_input_payload_last; + wire [0:0] logic_input_payload_fragment_source; + wire [0:0] logic_input_payload_fragment_opcode; + wire [31:0] logic_input_payload_fragment_address; + wire [5:0] logic_input_payload_fragment_length; + wire [31:0] logic_input_payload_fragment_data; + wire [3:0] logic_input_payload_fragment_mask; + wire [0:0] logic_input_payload_fragment_context; + wire logic_hitsS0_0; + wire logic_hitsS0_1; + wire logic_noHitS0; + wire _zz_io_outputs_0_cmd_payload_last; + wire _zz_io_outputs_1_cmd_payload_last; + reg [6:0] logic_rspPendingCounter; + wire logic_input_fire; + wire io_input_rsp_fire; + wire logic_cmdWait; + wire when_BmbDecoder_l56; + reg logic_rspHits_0; + reg logic_rspHits_1; + wire logic_rspPending; + wire logic_rspNoHitValid; + reg logic_rspNoHit_doIt; + wire io_input_rsp_fire_1; + wire when_BmbDecoder_l60; + wire logic_input_fire_1; + wire when_BmbDecoder_l60_1; + wire logic_input_fire_2; + reg logic_rspNoHit_singleBeatRsp; + wire logic_input_fire_3; + reg [0:0] logic_rspNoHit_source; + wire logic_input_fire_4; + reg [0:0] logic_rspNoHit_context; + wire logic_input_fire_5; + reg [3:0] logic_rspNoHit_counter; + wire [0:0] _zz_io_input_rsp_payload_last; + wire when_BmbDecoder_l81; + wire io_input_rsp_fire_2; + + assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); + assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); + assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; + assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; + always @(*) begin + case(_zz_io_input_rsp_payload_last) + 1'b0 : begin + _zz_io_input_rsp_payload_last_1 = io_outputs_0_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_source = io_outputs_0_rsp_payload_fragment_source; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_0_rsp_payload_fragment_context; + end + default : begin + _zz_io_input_rsp_payload_last_1 = io_outputs_1_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_source = io_outputs_1_rsp_payload_fragment_source; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_1_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_1_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_1_rsp_payload_fragment_context; + end + endcase + end + + assign logic_input_valid = io_input_cmd_valid; + assign io_input_cmd_ready = logic_input_ready; + assign logic_input_payload_last = io_input_cmd_payload_last; + assign logic_input_payload_fragment_source = io_input_cmd_payload_fragment_source; + assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign logic_input_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign logic_noHitS0 = (! ({logic_hitsS0_1,logic_hitsS0_0} != 2'b00)); + assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 32'h00007fff)) == 32'hf9000000); + always @(*) begin + io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); + if(logic_cmdWait) begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; + assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; + assign io_outputs_0_cmd_payload_fragment_source = logic_input_payload_fragment_source; + assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_0_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_1 = ((io_input_cmd_payload_fragment_address & (~ 32'h00ffffff)) == 32'hf8000000); + always @(*) begin + io_outputs_1_cmd_valid = (logic_input_valid && logic_hitsS0_1); + if(logic_cmdWait) begin + io_outputs_1_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_1_cmd_payload_last = logic_input_payload_last; + assign io_outputs_1_cmd_payload_last = _zz_io_outputs_1_cmd_payload_last; + assign io_outputs_1_cmd_payload_fragment_source = logic_input_payload_fragment_source; + assign io_outputs_1_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_1_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_1_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_1_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_1_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_1_cmd_payload_fragment_context = logic_input_payload_fragment_context; + always @(*) begin + logic_input_ready = (({(logic_hitsS0_1 && io_outputs_1_cmd_ready),(logic_hitsS0_0 && io_outputs_0_cmd_ready)} != 2'b00) || logic_noHitS0); + if(logic_cmdWait) begin + logic_input_ready = 1'b0; + end + end + + assign logic_input_fire = (logic_input_valid && logic_input_ready); + assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); + assign logic_rspPending = (logic_rspPendingCounter != 7'h0); + assign logic_rspNoHitValid = (! ({logic_rspHits_1,logic_rspHits_0} != 2'b00)); + assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); + assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); + assign when_BmbDecoder_l60_1 = ((logic_input_fire_1 && logic_noHitS0) && logic_input_payload_last); + assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); + always @(*) begin + io_input_rsp_valid = (({io_outputs_1_rsp_valid,io_outputs_0_rsp_valid} != 2'b00) || (logic_rspPending && logic_rspNoHitValid)); + if(logic_rspNoHit_doIt) begin + io_input_rsp_valid = 1'b1; + end + end + + assign _zz_io_input_rsp_payload_last = logic_rspHits_1; + always @(*) begin + io_input_rsp_payload_last = _zz_io_input_rsp_payload_last_1; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_last = 1'b0; + if(when_BmbDecoder_l81) begin + io_input_rsp_payload_last = 1'b1; + end + if(logic_rspNoHit_singleBeatRsp) begin + io_input_rsp_payload_last = 1'b1; + end + end + end + + always @(*) begin + io_input_rsp_payload_fragment_source = _zz_io_input_rsp_payload_fragment_source; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_source = logic_rspNoHit_source; + end + end + + always @(*) begin + io_input_rsp_payload_fragment_opcode = _zz_io_input_rsp_payload_fragment_opcode; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_opcode = 1'b1; + end + end + + assign io_input_rsp_payload_fragment_data = _zz_io_input_rsp_payload_fragment_data; + always @(*) begin + io_input_rsp_payload_fragment_context = _zz_io_input_rsp_payload_fragment_context; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_context = logic_rspNoHit_context; + end + end + + assign when_BmbDecoder_l81 = (logic_rspNoHit_counter == 4'b0000); + assign io_input_rsp_fire_2 = (io_input_rsp_valid && io_input_rsp_ready); + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign io_outputs_1_rsp_ready = io_input_rsp_ready; + assign logic_cmdWait = ((logic_rspPending && (((logic_hitsS0_0 != logic_rspHits_0) || (logic_hitsS0_1 != logic_rspHits_1)) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + logic_rspPendingCounter <= 7'h0; + logic_rspNoHit_doIt <= 1'b0; + end else begin + logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); + if(when_BmbDecoder_l60) begin + logic_rspNoHit_doIt <= 1'b0; + end + if(when_BmbDecoder_l60_1) begin + logic_rspNoHit_doIt <= 1'b1; + end + end + end + + always @(posedge io_systemClk) begin + if(when_BmbDecoder_l56) begin + logic_rspHits_0 <= logic_hitsS0_0; + logic_rspHits_1 <= logic_hitsS0_1; + end + if(logic_input_fire_2) begin + logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); + end + if(logic_input_fire_3) begin + logic_rspNoHit_source <= logic_input_payload_fragment_source; + end + if(logic_input_fire_4) begin + logic_rspNoHit_context <= logic_input_payload_fragment_context; + end + if(logic_input_fire_5) begin + logic_rspNoHit_counter <= logic_input_payload_fragment_length[5 : 2]; + end + if(logic_rspNoHit_doIt) begin + if(io_input_rsp_fire_2) begin + logic_rspNoHit_counter <= (logic_rspNoHit_counter - 4'b0001); + end + end + end + + +endmodule + +module BmbArbiter ( + input io_inputs_0_cmd_valid, + output io_inputs_0_cmd_ready, + input io_inputs_0_cmd_payload_last, + input [0:0] io_inputs_0_cmd_payload_fragment_opcode, + input [31:0] io_inputs_0_cmd_payload_fragment_address, + input [5:0] io_inputs_0_cmd_payload_fragment_length, + input [31:0] io_inputs_0_cmd_payload_fragment_data, + input [3:0] io_inputs_0_cmd_payload_fragment_mask, + input [0:0] io_inputs_0_cmd_payload_fragment_context, + output io_inputs_0_rsp_valid, + input io_inputs_0_rsp_ready, + output io_inputs_0_rsp_payload_last, + output [0:0] io_inputs_0_rsp_payload_fragment_opcode, + output [31:0] io_inputs_0_rsp_payload_fragment_data, + output [0:0] io_inputs_0_rsp_payload_fragment_context, + input io_inputs_1_cmd_valid, + output io_inputs_1_cmd_ready, + input io_inputs_1_cmd_payload_last, + input [0:0] io_inputs_1_cmd_payload_fragment_opcode, + input [31:0] io_inputs_1_cmd_payload_fragment_address, + input [5:0] io_inputs_1_cmd_payload_fragment_length, + input [31:0] io_inputs_1_cmd_payload_fragment_data, + input [3:0] io_inputs_1_cmd_payload_fragment_mask, + output io_inputs_1_rsp_valid, + input io_inputs_1_rsp_ready, + output io_inputs_1_rsp_payload_last, + output [0:0] io_inputs_1_rsp_payload_fragment_opcode, + output [31:0] io_inputs_1_rsp_payload_fragment_data, + output io_output_cmd_valid, + input io_output_cmd_ready, + output io_output_cmd_payload_last, + output [0:0] io_output_cmd_payload_fragment_source, + output [0:0] io_output_cmd_payload_fragment_opcode, + output [31:0] io_output_cmd_payload_fragment_address, + output [5:0] io_output_cmd_payload_fragment_length, + output [31:0] io_output_cmd_payload_fragment_data, + output [3:0] io_output_cmd_payload_fragment_mask, + output [0:0] io_output_cmd_payload_fragment_context, + input io_output_rsp_valid, + output io_output_rsp_ready, + input io_output_rsp_payload_last, + input [0:0] io_output_rsp_payload_fragment_source, + input [0:0] io_output_rsp_payload_fragment_opcode, + input [31:0] io_output_rsp_payload_fragment_data, + input [0:0] io_output_rsp_payload_fragment_context, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire memory_arbiter_io_inputs_0_ready; + wire memory_arbiter_io_inputs_1_ready; + wire memory_arbiter_io_output_valid; + wire memory_arbiter_io_output_payload_last; + wire [0:0] memory_arbiter_io_output_payload_fragment_source; + wire [0:0] memory_arbiter_io_output_payload_fragment_opcode; + wire [31:0] memory_arbiter_io_output_payload_fragment_address; + wire [5:0] memory_arbiter_io_output_payload_fragment_length; + wire [31:0] memory_arbiter_io_output_payload_fragment_data; + wire [3:0] memory_arbiter_io_output_payload_fragment_mask; + wire [0:0] memory_arbiter_io_output_payload_fragment_context; + wire [0:0] memory_arbiter_io_chosen; + wire [1:0] memory_arbiter_io_chosenOH; + wire [1:0] _zz_io_output_cmd_payload_fragment_source; + reg _zz_io_output_rsp_ready; + wire [0:0] memory_rspSel; + + assign _zz_io_output_cmd_payload_fragment_source = {memory_arbiter_io_output_payload_fragment_source,memory_arbiter_io_chosen}; + StreamArbiter memory_arbiter ( + .io_inputs_0_valid (io_inputs_0_cmd_valid ), //i + .io_inputs_0_ready (memory_arbiter_io_inputs_0_ready ), //o + .io_inputs_0_payload_last (io_inputs_0_cmd_payload_last ), //i + .io_inputs_0_payload_fragment_source (1'b0 ), //i + .io_inputs_0_payload_fragment_opcode (io_inputs_0_cmd_payload_fragment_opcode ), //i + .io_inputs_0_payload_fragment_address (io_inputs_0_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_0_payload_fragment_length (io_inputs_0_cmd_payload_fragment_length[5:0] ), //i + .io_inputs_0_payload_fragment_data (io_inputs_0_cmd_payload_fragment_data[31:0] ), //i + .io_inputs_0_payload_fragment_mask (io_inputs_0_cmd_payload_fragment_mask[3:0] ), //i + .io_inputs_0_payload_fragment_context (io_inputs_0_cmd_payload_fragment_context ), //i + .io_inputs_1_valid (io_inputs_1_cmd_valid ), //i + .io_inputs_1_ready (memory_arbiter_io_inputs_1_ready ), //o + .io_inputs_1_payload_last (io_inputs_1_cmd_payload_last ), //i + .io_inputs_1_payload_fragment_source (1'b0 ), //i + .io_inputs_1_payload_fragment_opcode (io_inputs_1_cmd_payload_fragment_opcode ), //i + .io_inputs_1_payload_fragment_address (io_inputs_1_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_1_payload_fragment_length (io_inputs_1_cmd_payload_fragment_length[5:0] ), //i + .io_inputs_1_payload_fragment_data (io_inputs_1_cmd_payload_fragment_data[31:0] ), //i + .io_inputs_1_payload_fragment_mask (io_inputs_1_cmd_payload_fragment_mask[3:0] ), //i + .io_inputs_1_payload_fragment_context (1'b0 ), //i + .io_output_valid (memory_arbiter_io_output_valid ), //o + .io_output_ready (io_output_cmd_ready ), //i + .io_output_payload_last (memory_arbiter_io_output_payload_last ), //o + .io_output_payload_fragment_source (memory_arbiter_io_output_payload_fragment_source ), //o + .io_output_payload_fragment_opcode (memory_arbiter_io_output_payload_fragment_opcode ), //o + .io_output_payload_fragment_address (memory_arbiter_io_output_payload_fragment_address[31:0]), //o + .io_output_payload_fragment_length (memory_arbiter_io_output_payload_fragment_length[5:0] ), //o + .io_output_payload_fragment_data (memory_arbiter_io_output_payload_fragment_data[31:0] ), //o + .io_output_payload_fragment_mask (memory_arbiter_io_output_payload_fragment_mask[3:0] ), //o + .io_output_payload_fragment_context (memory_arbiter_io_output_payload_fragment_context ), //o + .io_chosen (memory_arbiter_io_chosen ), //o + .io_chosenOH (memory_arbiter_io_chosenOH[1:0] ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + always @(*) begin + case(memory_rspSel) + 1'b0 : _zz_io_output_rsp_ready = io_inputs_0_rsp_ready; + default : _zz_io_output_rsp_ready = io_inputs_1_rsp_ready; + endcase + end + + assign io_inputs_0_cmd_ready = memory_arbiter_io_inputs_0_ready; + assign io_inputs_1_cmd_ready = memory_arbiter_io_inputs_1_ready; + assign io_output_cmd_valid = memory_arbiter_io_output_valid; + assign io_output_cmd_payload_last = memory_arbiter_io_output_payload_last; + assign io_output_cmd_payload_fragment_opcode = memory_arbiter_io_output_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = memory_arbiter_io_output_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = memory_arbiter_io_output_payload_fragment_length; + assign io_output_cmd_payload_fragment_data = memory_arbiter_io_output_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = memory_arbiter_io_output_payload_fragment_mask; + assign io_output_cmd_payload_fragment_context = memory_arbiter_io_output_payload_fragment_context; + assign io_output_cmd_payload_fragment_source = _zz_io_output_cmd_payload_fragment_source[0:0]; + assign memory_rspSel = io_output_rsp_payload_fragment_source[0 : 0]; + assign io_inputs_0_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b0)); + assign io_inputs_0_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_0_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_0_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_inputs_0_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; + assign io_inputs_1_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b1)); + assign io_inputs_1_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_1_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_1_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_output_rsp_ready = _zz_io_output_rsp_ready; + +endmodule + +module BmbDecoder_1 ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [31:0] io_input_cmd_payload_fragment_address, + input [5:0] io_input_cmd_payload_fragment_length, + output io_input_rsp_valid, + input io_input_rsp_ready, + output io_input_rsp_payload_last, + output [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output io_outputs_0_cmd_valid, + input io_outputs_0_cmd_ready, + output io_outputs_0_cmd_payload_last, + output [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output [31:0] io_outputs_0_cmd_payload_fragment_address, + output [5:0] io_outputs_0_cmd_payload_fragment_length, + input io_outputs_0_rsp_valid, + output io_outputs_0_rsp_ready, + input io_outputs_0_rsp_payload_last, + input [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input [31:0] io_outputs_0_rsp_payload_fragment_data +); + + + assign io_outputs_0_cmd_valid = io_input_cmd_valid; + assign io_input_cmd_ready = io_outputs_0_cmd_ready; + assign io_input_rsp_valid = io_outputs_0_rsp_valid; + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign io_outputs_0_cmd_payload_last = io_input_cmd_payload_last; + assign io_input_rsp_payload_last = io_outputs_0_rsp_payload_last; + assign io_outputs_0_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + +endmodule + +module BmbExclusiveMonitor ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [31:0] io_input_cmd_payload_fragment_address, + input [5:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_mask, + input [0:0] io_input_cmd_payload_fragment_context, + output io_input_rsp_valid, + input io_input_rsp_ready, + output io_input_rsp_payload_last, + output [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output [0:0] io_input_rsp_payload_fragment_context, + output io_output_cmd_valid, + input io_output_cmd_ready, + output io_output_cmd_payload_last, + output [0:0] io_output_cmd_payload_fragment_opcode, + output [31:0] io_output_cmd_payload_fragment_address, + output [5:0] io_output_cmd_payload_fragment_length, + output [31:0] io_output_cmd_payload_fragment_data, + output [3:0] io_output_cmd_payload_fragment_mask, + output [0:0] io_output_cmd_payload_fragment_context, + input io_output_rsp_valid, + output io_output_rsp_ready, + input io_output_rsp_payload_last, + input [0:0] io_output_rsp_payload_fragment_opcode, + input [31:0] io_output_rsp_payload_fragment_data, + input [0:0] io_output_rsp_payload_fragment_context +); + + + assign io_output_cmd_valid = io_input_cmd_valid; + assign io_input_cmd_ready = io_output_cmd_ready; + assign io_input_rsp_valid = io_output_rsp_valid; + assign io_output_rsp_ready = io_input_rsp_ready; + assign io_output_cmd_payload_last = io_input_cmd_payload_last; + assign io_input_rsp_payload_last = io_output_rsp_payload_last; + assign io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign io_output_cmd_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; + +endmodule + +module BmbDecoder ( + input io_input_cmd_valid, + output io_input_cmd_ready, + input io_input_cmd_payload_last, + input [0:0] io_input_cmd_payload_fragment_opcode, + input [31:0] io_input_cmd_payload_fragment_address, + input [1:0] io_input_cmd_payload_fragment_length, + input [31:0] io_input_cmd_payload_fragment_data, + input [3:0] io_input_cmd_payload_fragment_mask, + output reg io_input_rsp_valid, + input io_input_rsp_ready, + output reg io_input_rsp_payload_last, + output reg [0:0] io_input_rsp_payload_fragment_opcode, + output [31:0] io_input_rsp_payload_fragment_data, + output reg io_outputs_0_cmd_valid, + input io_outputs_0_cmd_ready, + output io_outputs_0_cmd_payload_last, + output [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output [31:0] io_outputs_0_cmd_payload_fragment_address, + output [1:0] io_outputs_0_cmd_payload_fragment_length, + output [31:0] io_outputs_0_cmd_payload_fragment_data, + output [3:0] io_outputs_0_cmd_payload_fragment_mask, + input io_outputs_0_rsp_valid, + output io_outputs_0_rsp_ready, + input io_outputs_0_rsp_payload_last, + input [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input [31:0] io_outputs_0_rsp_payload_fragment_data, + input io_systemClk, + input debugCd_logic_outputReset +); + + wire [6:0] _zz_logic_rspPendingCounter; + wire [6:0] _zz_logic_rspPendingCounter_1; + wire [0:0] _zz_logic_rspPendingCounter_2; + wire [6:0] _zz_logic_rspPendingCounter_3; + wire [0:0] _zz_logic_rspPendingCounter_4; + wire logic_input_valid; + reg logic_input_ready; + wire logic_input_payload_last; + wire [0:0] logic_input_payload_fragment_opcode; + wire [31:0] logic_input_payload_fragment_address; + wire [1:0] logic_input_payload_fragment_length; + wire [31:0] logic_input_payload_fragment_data; + wire [3:0] logic_input_payload_fragment_mask; + wire logic_hitsS0_0; + wire logic_noHitS0; + wire _zz_io_outputs_0_cmd_payload_last; + reg [6:0] logic_rspPendingCounter; + wire logic_input_fire; + wire io_input_rsp_fire; + wire logic_cmdWait; + wire when_BmbDecoder_l56; + reg logic_rspHits_0; + wire logic_rspPending; + wire logic_rspNoHitValid; + reg logic_rspNoHit_doIt; + wire io_input_rsp_fire_1; + wire when_BmbDecoder_l60; + wire logic_input_fire_1; + wire when_BmbDecoder_l60_1; + wire logic_input_fire_2; + reg logic_rspNoHit_singleBeatRsp; + wire logic_input_fire_3; + wire logic_input_fire_4; + wire logic_input_fire_5; + + assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); + assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); + assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; + assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; + assign logic_input_valid = io_input_cmd_valid; + assign io_input_cmd_ready = logic_input_ready; + assign logic_input_payload_last = io_input_cmd_payload_last; + assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign logic_noHitS0 = (! (logic_hitsS0_0 != 1'b0)); + assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 32'h00000fff)) == 32'h10b80000); + always @(*) begin + io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); + if(logic_cmdWait) begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; + assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; + assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + always @(*) begin + logic_input_ready = (((logic_hitsS0_0 && io_outputs_0_cmd_ready) != 1'b0) || logic_noHitS0); + if(logic_cmdWait) begin + logic_input_ready = 1'b0; + end + end + + assign logic_input_fire = (logic_input_valid && logic_input_ready); + assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); + assign logic_rspPending = (logic_rspPendingCounter != 7'h0); + assign logic_rspNoHitValid = (! (logic_rspHits_0 != 1'b0)); + assign io_input_rsp_fire_1 = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l60 = (io_input_rsp_fire_1 && io_input_rsp_payload_last); + assign logic_input_fire_1 = (logic_input_valid && logic_input_ready); + assign when_BmbDecoder_l60_1 = ((logic_input_fire_1 && logic_noHitS0) && logic_input_payload_last); + assign logic_input_fire_2 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_3 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_4 = (logic_input_valid && logic_input_ready); + assign logic_input_fire_5 = (logic_input_valid && logic_input_ready); + always @(*) begin + io_input_rsp_valid = ((io_outputs_0_rsp_valid != 1'b0) || (logic_rspPending && logic_rspNoHitValid)); + if(logic_rspNoHit_doIt) begin + io_input_rsp_valid = 1'b1; + end + end + + always @(*) begin + io_input_rsp_payload_last = io_outputs_0_rsp_payload_last; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_last = 1'b1; + end + end + + always @(*) begin + io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_opcode = 1'b1; + end + end + + assign io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign logic_cmdWait = ((logic_rspPending && ((logic_hitsS0_0 != logic_rspHits_0) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); + always @(posedge io_systemClk) begin + if(debugCd_logic_outputReset) begin + logic_rspPendingCounter <= 7'h0; + logic_rspNoHit_doIt <= 1'b0; + end else begin + logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); + if(when_BmbDecoder_l60) begin + logic_rspNoHit_doIt <= 1'b0; + end + if(when_BmbDecoder_l60_1) begin + logic_rspNoHit_doIt <= 1'b1; + end + end + end + + always @(posedge io_systemClk) begin + if(when_BmbDecoder_l56) begin + logic_rspHits_0 <= logic_hitsS0_0; + end + if(logic_input_fire_2) begin + logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); + end + end + + +endmodule + +module BufferCC_4 ( + input io_dataIn, + output io_dataOut, + input io_systemClk, + input system_cores_0_debugReset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge io_systemClk or posedge system_cores_0_debugReset) begin + if(system_cores_0_debugReset) begin + buffers_0 <= 1'b1; + buffers_1 <= 1'b1; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module SystemDebugger ( + input io_remote_cmd_valid, + output io_remote_cmd_ready, + input io_remote_cmd_payload_last, + input [0:0] io_remote_cmd_payload_fragment, + output io_remote_rsp_valid, + input io_remote_rsp_ready, + output io_remote_rsp_payload_error, + output [31:0] io_remote_rsp_payload_data, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output io_mem_cmd_payload_wr, + output [1:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload, + input io_systemClk, + input debugCd_logic_outputReset +); + + reg [66:0] dispatcher_dataShifter; + reg dispatcher_dataLoaded; + reg [7:0] dispatcher_headerShifter; + wire [7:0] dispatcher_header; + reg dispatcher_headerLoaded; + reg [2:0] dispatcher_counter; + wire when_Fragment_l346; + wire when_Fragment_l349; + wire [66:0] _zz_io_mem_cmd_payload_address; + wire io_mem_cmd_isStall; + wire when_Fragment_l372; + + assign dispatcher_header = dispatcher_headerShifter[7 : 0]; + assign when_Fragment_l346 = (dispatcher_headerLoaded == 1'b0); + assign when_Fragment_l349 = (dispatcher_counter == 3'b111); + assign io_remote_cmd_ready = (! dispatcher_dataLoaded); + assign _zz_io_mem_cmd_payload_address = dispatcher_dataShifter[66 : 0]; + assign io_mem_cmd_payload_address = _zz_io_mem_cmd_payload_address[31 : 0]; + assign io_mem_cmd_payload_data = _zz_io_mem_cmd_payload_address[63 : 32]; + assign io_mem_cmd_payload_wr = _zz_io_mem_cmd_payload_address[64]; + assign io_mem_cmd_payload_size = _zz_io_mem_cmd_payload_address[66 : 65]; + assign io_mem_cmd_valid = (dispatcher_dataLoaded && (dispatcher_header == 8'h0)); + assign io_mem_cmd_isStall = (io_mem_cmd_valid && (! io_mem_cmd_ready)); + assign when_Fragment_l372 = ((dispatcher_headerLoaded && dispatcher_dataLoaded) && (! io_mem_cmd_isStall)); + assign io_remote_rsp_valid = io_mem_rsp_valid; + assign io_remote_rsp_payload_error = 1'b0; + assign io_remote_rsp_payload_data = io_mem_rsp_payload; + always @(posedge io_systemClk) begin + if(debugCd_logic_outputReset) begin + dispatcher_dataLoaded <= 1'b0; + dispatcher_headerLoaded <= 1'b0; + dispatcher_counter <= 3'b000; + end else begin + if(io_remote_cmd_valid) begin + if(when_Fragment_l346) begin + dispatcher_counter <= (dispatcher_counter + 3'b001); + if(when_Fragment_l349) begin + dispatcher_headerLoaded <= 1'b1; + end + end + if(io_remote_cmd_payload_last) begin + dispatcher_headerLoaded <= 1'b1; + dispatcher_dataLoaded <= 1'b1; + dispatcher_counter <= 3'b000; + end + end + if(when_Fragment_l372) begin + dispatcher_headerLoaded <= 1'b0; + dispatcher_dataLoaded <= 1'b0; + end + end + end + + always @(posedge io_systemClk) begin + if(io_remote_cmd_valid) begin + if(when_Fragment_l346) begin + dispatcher_headerShifter <= ({io_remote_cmd_payload_fragment,dispatcher_headerShifter} >>> 1); + end else begin + dispatcher_dataShifter <= ({io_remote_cmd_payload_fragment,dispatcher_dataShifter} >>> 1); + end + end + end + + +endmodule + +module JtagBridgeNoTap ( + input io_ctrl_tdi, + input io_ctrl_enable, + input io_ctrl_capture, + input io_ctrl_shift, + input io_ctrl_update, + input io_ctrl_reset, + output io_ctrl_tdo, + output io_remote_cmd_valid, + input io_remote_cmd_ready, + output io_remote_cmd_payload_last, + output [0:0] io_remote_cmd_payload_fragment, + input io_remote_rsp_valid, + output io_remote_rsp_ready, + input io_remote_rsp_payload_error, + input [31:0] io_remote_rsp_payload_data, + input io_systemClk, + input debugCd_logic_outputReset, + input jtagCtrl_tck +); + + wire flowCCByToggle_1_io_output_valid; + wire flowCCByToggle_1_io_output_payload_last; + wire [0:0] flowCCByToggle_1_io_output_payload_fragment; + wire system_cmd_valid; + wire system_cmd_payload_last; + wire [0:0] system_cmd_payload_fragment; + wire system_cmd_toStream_valid; + wire system_cmd_toStream_ready; + wire system_cmd_toStream_payload_last; + wire [0:0] system_cmd_toStream_payload_fragment; + (* async_reg = "true" *) reg system_rsp_valid; + (* async_reg = "true" *) reg system_rsp_payload_error; + (* async_reg = "true" *) reg [31:0] system_rsp_payload_data; + wire io_remote_rsp_fire; + wire jtag_wrapper_ctrl_tdi; + wire jtag_wrapper_ctrl_enable; + wire jtag_wrapper_ctrl_capture; + wire jtag_wrapper_ctrl_shift; + wire jtag_wrapper_ctrl_update; + wire jtag_wrapper_ctrl_reset; + reg jtag_wrapper_ctrl_tdo; + reg [1:0] jtag_wrapper_header; + wire [1:0] jtag_wrapper_headerNext; + reg [0:0] jtag_wrapper_counter; + reg jtag_wrapper_done; + reg jtag_wrapper_sendCapture; + reg jtag_wrapper_sendShift; + reg jtag_wrapper_sendUpdate; + wire when_JtagTapInstructions_l183; + wire when_JtagTapInstructions_l186; + wire jtag_writeArea_ctrl_tdi; + wire jtag_writeArea_ctrl_enable; + wire jtag_writeArea_ctrl_capture; + wire jtag_writeArea_ctrl_shift; + wire jtag_writeArea_ctrl_update; + wire jtag_writeArea_ctrl_reset; + wire jtag_writeArea_ctrl_tdo; + wire jtag_writeArea_source_valid; + wire jtag_writeArea_source_payload_last; + wire [0:0] jtag_writeArea_source_payload_fragment; + reg jtag_writeArea_valid; + reg jtag_writeArea_data; + wire when_JtagTapInstructions_l209; + wire jtag_readArea_ctrl_tdi; + wire jtag_readArea_ctrl_enable; + wire jtag_readArea_ctrl_capture; + wire jtag_readArea_ctrl_shift; + wire jtag_readArea_ctrl_update; + wire jtag_readArea_ctrl_reset; + wire jtag_readArea_ctrl_tdo; + reg [33:0] jtag_readArea_full_shifter; + wire when_JtagTapInstructions_l209_1; + + FlowCCByToggle flowCCByToggle_1 ( + .io_input_valid (jtag_writeArea_source_valid ), //i + .io_input_payload_last (jtag_writeArea_source_payload_last ), //i + .io_input_payload_fragment (jtag_writeArea_source_payload_fragment ), //i + .io_output_valid (flowCCByToggle_1_io_output_valid ), //o + .io_output_payload_last (flowCCByToggle_1_io_output_payload_last ), //o + .io_output_payload_fragment (flowCCByToggle_1_io_output_payload_fragment), //o + .jtagCtrl_tck (jtagCtrl_tck ), //i + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i + ); + assign system_cmd_toStream_valid = system_cmd_valid; + assign system_cmd_toStream_payload_last = system_cmd_payload_last; + assign system_cmd_toStream_payload_fragment = system_cmd_payload_fragment; + assign io_remote_cmd_valid = system_cmd_toStream_valid; + assign system_cmd_toStream_ready = io_remote_cmd_ready; + assign io_remote_cmd_payload_last = system_cmd_toStream_payload_last; + assign io_remote_cmd_payload_fragment = system_cmd_toStream_payload_fragment; + assign io_remote_rsp_fire = (io_remote_rsp_valid && io_remote_rsp_ready); + assign io_remote_rsp_ready = 1'b1; + assign jtag_wrapper_headerNext = ({jtag_wrapper_ctrl_tdi,jtag_wrapper_header} >>> 1); + always @(*) begin + jtag_wrapper_sendCapture = 1'b0; + if(jtag_wrapper_ctrl_enable) begin + if(jtag_wrapper_ctrl_shift) begin + if(when_JtagTapInstructions_l183) begin + if(when_JtagTapInstructions_l186) begin + jtag_wrapper_sendCapture = 1'b1; + end + end + end + end + end + + always @(*) begin + jtag_wrapper_sendShift = 1'b0; + if(jtag_wrapper_ctrl_enable) begin + if(jtag_wrapper_ctrl_shift) begin + if(!when_JtagTapInstructions_l183) begin + jtag_wrapper_sendShift = 1'b1; + end + end + end + end + + always @(*) begin + jtag_wrapper_sendUpdate = 1'b0; + if(jtag_wrapper_ctrl_enable) begin + if(jtag_wrapper_ctrl_update) begin + jtag_wrapper_sendUpdate = 1'b1; + end + end + end + + assign when_JtagTapInstructions_l183 = (! jtag_wrapper_done); + assign when_JtagTapInstructions_l186 = (jtag_wrapper_counter == 1'b1); + always @(*) begin + jtag_wrapper_ctrl_tdo = 1'b0; + if(when_JtagTapInstructions_l209) begin + jtag_wrapper_ctrl_tdo = jtag_writeArea_ctrl_tdo; + end + if(when_JtagTapInstructions_l209_1) begin + jtag_wrapper_ctrl_tdo = jtag_readArea_ctrl_tdo; + end + end + + assign jtag_wrapper_ctrl_tdi = io_ctrl_tdi; + assign jtag_wrapper_ctrl_enable = io_ctrl_enable; + assign jtag_wrapper_ctrl_capture = io_ctrl_capture; + assign jtag_wrapper_ctrl_shift = io_ctrl_shift; + assign jtag_wrapper_ctrl_update = io_ctrl_update; + assign jtag_wrapper_ctrl_reset = io_ctrl_reset; + assign io_ctrl_tdo = jtag_wrapper_ctrl_tdo; + assign jtag_writeArea_source_valid = jtag_writeArea_valid; + assign jtag_writeArea_source_payload_last = (! (jtag_writeArea_ctrl_enable && jtag_writeArea_ctrl_shift)); + assign jtag_writeArea_source_payload_fragment[0] = jtag_writeArea_data; + assign system_cmd_valid = flowCCByToggle_1_io_output_valid; + assign system_cmd_payload_last = flowCCByToggle_1_io_output_payload_last; + assign system_cmd_payload_fragment = flowCCByToggle_1_io_output_payload_fragment; + assign jtag_writeArea_ctrl_tdo = 1'b0; + assign when_JtagTapInstructions_l209 = (jtag_wrapper_header == 2'b00); + assign jtag_writeArea_ctrl_tdi = jtag_wrapper_ctrl_tdi; + assign jtag_writeArea_ctrl_enable = 1'b1; + assign jtag_writeArea_ctrl_capture = ((jtag_wrapper_headerNext == 2'b00) && jtag_wrapper_sendCapture); + assign jtag_writeArea_ctrl_shift = (when_JtagTapInstructions_l209 && jtag_wrapper_sendShift); + assign jtag_writeArea_ctrl_update = (when_JtagTapInstructions_l209 && jtag_wrapper_sendUpdate); + assign jtag_writeArea_ctrl_reset = jtag_wrapper_ctrl_reset; + assign jtag_readArea_ctrl_tdo = jtag_readArea_full_shifter[0]; + assign when_JtagTapInstructions_l209_1 = (jtag_wrapper_header == 2'b01); + assign jtag_readArea_ctrl_tdi = jtag_wrapper_ctrl_tdi; + assign jtag_readArea_ctrl_enable = 1'b1; + assign jtag_readArea_ctrl_capture = ((jtag_wrapper_headerNext == 2'b01) && jtag_wrapper_sendCapture); + assign jtag_readArea_ctrl_shift = (when_JtagTapInstructions_l209_1 && jtag_wrapper_sendShift); + assign jtag_readArea_ctrl_update = (when_JtagTapInstructions_l209_1 && jtag_wrapper_sendUpdate); + assign jtag_readArea_ctrl_reset = jtag_wrapper_ctrl_reset; + always @(posedge io_systemClk) begin + if(io_remote_cmd_valid) begin + system_rsp_valid <= 1'b0; + end + if(io_remote_rsp_fire) begin + system_rsp_valid <= 1'b1; + system_rsp_payload_error <= io_remote_rsp_payload_error; + system_rsp_payload_data <= io_remote_rsp_payload_data; + end + end + + always @(posedge jtagCtrl_tck) begin + if(jtag_wrapper_ctrl_enable) begin + if(jtag_wrapper_ctrl_capture) begin + jtag_wrapper_done <= 1'b0; + jtag_wrapper_counter <= 1'b0; + end + if(jtag_wrapper_ctrl_shift) begin + if(when_JtagTapInstructions_l183) begin + jtag_wrapper_counter <= (jtag_wrapper_counter + 1'b1); + jtag_wrapper_header <= jtag_wrapper_headerNext; + if(when_JtagTapInstructions_l186) begin + jtag_wrapper_done <= 1'b1; + end + end + end + end + jtag_writeArea_valid <= (jtag_writeArea_ctrl_enable && jtag_writeArea_ctrl_shift); + jtag_writeArea_data <= jtag_writeArea_ctrl_tdi; + if(jtag_readArea_ctrl_enable) begin + if(jtag_readArea_ctrl_capture) begin + jtag_readArea_full_shifter <= {{system_rsp_payload_data,system_rsp_payload_error},system_rsp_valid}; + end + if(jtag_readArea_ctrl_shift) begin + jtag_readArea_full_shifter <= ({jtag_readArea_ctrl_tdi,jtag_readArea_full_shifter} >>> 1); + end + end + end + + +endmodule + +module VexRiscv ( + output dBus_cmd_valid, + input dBus_cmd_ready, + output dBus_cmd_payload_wr, + output dBus_cmd_payload_uncached, + output [31:0] dBus_cmd_payload_address, + output [31:0] dBus_cmd_payload_data, + output [3:0] dBus_cmd_payload_mask, + output [2:0] dBus_cmd_payload_size, + output dBus_cmd_payload_last, + input dBus_rsp_valid, + input dBus_rsp_payload_last, + input [31:0] dBus_rsp_payload_data, + input dBus_rsp_payload_error, + input timerInterrupt, + input externalInterrupt, + input softwareInterrupt, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output iBus_cmd_valid, + input iBus_cmd_ready, + output reg [31:0] iBus_cmd_payload_address, + output [2:0] iBus_cmd_payload_size, + input iBus_rsp_valid, + input [31:0] iBus_rsp_payload_data, + input iBus_rsp_payload_error, + input io_systemClk, + input systemCd_logic_outputReset, + input debugCd_logic_outputReset +); + localparam ShiftCtrlEnum_DISABLE_1 = 2'd0; + localparam ShiftCtrlEnum_SLL_1 = 2'd1; + localparam ShiftCtrlEnum_SRL_1 = 2'd2; + localparam ShiftCtrlEnum_SRA_1 = 2'd3; + localparam BranchCtrlEnum_INC = 2'd0; + localparam BranchCtrlEnum_B = 2'd1; + localparam BranchCtrlEnum_JAL = 2'd2; + localparam BranchCtrlEnum_JALR = 2'd3; + localparam EnvCtrlEnum_NONE = 2'd0; + localparam EnvCtrlEnum_XRET = 2'd1; + localparam EnvCtrlEnum_ECALL = 2'd2; + localparam EnvCtrlEnum_EBREAK = 2'd3; + localparam AluBitwiseCtrlEnum_XOR_1 = 2'd0; + localparam AluBitwiseCtrlEnum_OR_1 = 2'd1; + localparam AluBitwiseCtrlEnum_AND_1 = 2'd2; + localparam AluCtrlEnum_ADD_SUB = 2'd0; + localparam AluCtrlEnum_SLT_SLTU = 2'd1; + localparam AluCtrlEnum_BITWISE = 2'd2; + localparam Src2CtrlEnum_RS = 2'd0; + localparam Src2CtrlEnum_IMI = 2'd1; + localparam Src2CtrlEnum_IMS = 2'd2; + localparam Src2CtrlEnum_PC = 2'd3; + localparam Src1CtrlEnum_RS = 2'd0; + localparam Src1CtrlEnum_IMU = 2'd1; + localparam Src1CtrlEnum_PC_INCREMENT = 2'd2; + localparam Src1CtrlEnum_URS1 = 2'd3; + + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + wire dataCache_1_io_cpu_execute_isValid; + wire [31:0] dataCache_1_io_cpu_execute_address; + wire dataCache_1_io_cpu_memory_isValid; + reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; + reg dataCache_1_io_cpu_writeBack_isValid; + wire dataCache_1_io_cpu_writeBack_isUser; + wire [31:0] dataCache_1_io_cpu_writeBack_storeData; + wire [31:0] dataCache_1_io_cpu_writeBack_address; + wire dataCache_1_io_cpu_writeBack_fence_SW; + wire dataCache_1_io_cpu_writeBack_fence_SR; + wire dataCache_1_io_cpu_writeBack_fence_SO; + wire dataCache_1_io_cpu_writeBack_fence_SI; + wire dataCache_1_io_cpu_writeBack_fence_PW; + wire dataCache_1_io_cpu_writeBack_fence_PR; + wire dataCache_1_io_cpu_writeBack_fence_PO; + wire dataCache_1_io_cpu_writeBack_fence_PI; + wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; + wire dataCache_1_io_cpu_flush_valid; + wire dataCache_1_io_cpu_flush_payload_singleLine; + wire [5:0] dataCache_1_io_cpu_flush_payload_lineId; + wire dataCache_1_io_mem_cmd_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_writeBack_exclusiveOk; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_size; + wire dataCache_1_io_mem_cmd_payload_last; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [13:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [7:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [1:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [2:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_4; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [25:0] _zz_io_cpu_flush_payload_lineId; + wire [25:0] _zz_io_cpu_flush_payload_lineId_1; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; + wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_1; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_2; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_3; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_4; + wire _zz__zz_decode_BRANCH_CTRL_2_5; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_6; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_7; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_8; + wire _zz__zz_decode_BRANCH_CTRL_2_9; + wire _zz__zz_decode_BRANCH_CTRL_2_10; + wire [26:0] _zz__zz_decode_BRANCH_CTRL_2_11; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_12; + wire _zz__zz_decode_BRANCH_CTRL_2_13; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_14; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_15; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_16; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_17; + wire [22:0] _zz__zz_decode_BRANCH_CTRL_2_18; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_19; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_20; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_21; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_22; + wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_23; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_24; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_25; + wire _zz__zz_decode_BRANCH_CTRL_2_26; + wire _zz__zz_decode_BRANCH_CTRL_2_27; + wire _zz__zz_decode_BRANCH_CTRL_2_28; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_29; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_30; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_31; + wire _zz__zz_decode_BRANCH_CTRL_2_32; + wire [18:0] _zz__zz_decode_BRANCH_CTRL_2_33; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_34; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_35; + wire _zz__zz_decode_BRANCH_CTRL_2_36; + wire _zz__zz_decode_BRANCH_CTRL_2_37; + wire _zz__zz_decode_BRANCH_CTRL_2_38; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_39; + wire _zz__zz_decode_BRANCH_CTRL_2_40; + wire [15:0] _zz__zz_decode_BRANCH_CTRL_2_41; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_42; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_43; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_44; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_45; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_46; + wire _zz__zz_decode_BRANCH_CTRL_2_47; + wire _zz__zz_decode_BRANCH_CTRL_2_48; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_49; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_50; + wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_51; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_52; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_53; + wire _zz__zz_decode_BRANCH_CTRL_2_54; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_55; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_56; + wire _zz__zz_decode_BRANCH_CTRL_2_57; + wire [12:0] _zz__zz_decode_BRANCH_CTRL_2_58; + wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_59; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_60; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_61; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_62; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_63; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_64; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_65; + wire _zz__zz_decode_BRANCH_CTRL_2_66; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_67; + wire _zz__zz_decode_BRANCH_CTRL_2_68; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_69; + wire _zz__zz_decode_BRANCH_CTRL_2_70; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_71; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_72; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_73; + wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_74; + wire _zz__zz_decode_BRANCH_CTRL_2_75; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_76; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_77; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_78; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_79; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_80; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_81; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_82; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_83; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_84; + wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_85; + wire _zz__zz_decode_BRANCH_CTRL_2_86; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_87; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_88; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_89; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_90; + wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_91; + wire _zz__zz_decode_BRANCH_CTRL_2_92; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_93; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_94; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_95; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_96; + wire [9:0] _zz__zz_decode_BRANCH_CTRL_2_97; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_98; + wire _zz__zz_decode_BRANCH_CTRL_2_99; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_100; + wire _zz__zz_decode_BRANCH_CTRL_2_101; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_102; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_103; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_104; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_105; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_106; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_107; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_108; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_109; + wire [6:0] _zz__zz_decode_BRANCH_CTRL_2_110; + wire _zz__zz_decode_BRANCH_CTRL_2_111; + wire _zz__zz_decode_BRANCH_CTRL_2_112; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_113; + wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_114; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_115; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_116; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_117; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_118; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_119; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_120; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_121; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_122; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_123; + wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_124; + wire _zz__zz_decode_BRANCH_CTRL_2_125; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_126; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_127; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_128; + wire [0:0] _zz__zz_decode_BRANCH_CTRL_2_129; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_130; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_131; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_132; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_133; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_134; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_135; + wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_136; + wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_137; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_138; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_139; + wire _zz__zz_decode_BRANCH_CTRL_2_140; + wire _zz__zz_decode_BRANCH_CTRL_2_141; + wire _zz__zz_decode_BRANCH_CTRL_2_142; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_143; + wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_144; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_decode_SRC1_1; + wire [4:0] _zz__zz_decode_SRC1_1_1; + wire [11:0] _zz__zz_decode_SRC2_4; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_decode_RS2_2; + wire [31:0] _zz__zz_decode_RS2_2_1; + wire [5:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext; + wire [0:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_2; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_3; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_4; + wire [0:0] _zz_memory_MulDivIterativePlugin_div_result_5; + wire [32:0] _zz_memory_MulDivIterativePlugin_rs1_2; + wire [0:0] _zz_memory_MulDivIterativePlugin_rs1_3; + wire [31:0] _zz_memory_MulDivIterativePlugin_rs2_1; + wire [0:0] _zz_memory_MulDivIterativePlugin_rs2_2; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire _zz_when; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire [51:0] memory_MUL_LOW; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [31:0] execute_MEMORY_VIRTUAL_ADDRESS; + wire [31:0] memory_MEMORY_STORE_DATA_RF; + wire [31:0] execute_MEMORY_STORE_DATA_RF; + wire decode_DO_EBREAK; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire [31:0] decode_SRC2; + wire [31:0] decode_SRC1; + wire decode_SRC2_FORCE_ZERO; + wire [1:0] decode_BRANCH_CTRL; + wire [1:0] _zz_decode_BRANCH_CTRL; + wire [1:0] _zz_decode_to_execute_BRANCH_CTRL; + wire [1:0] _zz_decode_to_execute_BRANCH_CTRL_1; + wire [1:0] _zz_memory_to_writeBack_ENV_CTRL; + wire [1:0] _zz_memory_to_writeBack_ENV_CTRL_1; + wire [1:0] _zz_execute_to_memory_ENV_CTRL; + wire [1:0] _zz_execute_to_memory_ENV_CTRL_1; + wire [1:0] decode_ENV_CTRL; + wire [1:0] _zz_decode_ENV_CTRL; + wire [1:0] _zz_decode_to_execute_ENV_CTRL; + wire [1:0] _zz_decode_to_execute_ENV_CTRL_1; + wire decode_IS_CSR; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire decode_IS_MUL; + wire [1:0] _zz_execute_to_memory_SHIFT_CTRL; + wire [1:0] _zz_execute_to_memory_SHIFT_CTRL_1; + wire [1:0] decode_SHIFT_CTRL; + wire [1:0] _zz_decode_SHIFT_CTRL; + wire [1:0] _zz_decode_to_execute_SHIFT_CTRL; + wire [1:0] _zz_decode_to_execute_SHIFT_CTRL_1; + wire [1:0] decode_ALU_BITWISE_CTRL; + wire [1:0] _zz_decode_ALU_BITWISE_CTRL; + wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire [1:0] decode_ALU_CTRL; + wire [1:0] _zz_decode_ALU_CTRL; + wire [1:0] _zz_decode_to_execute_ALU_CTRL; + wire [1:0] _zz_decode_to_execute_ALU_CTRL_1; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + wire [1:0] execute_BRANCH_CTRL; + wire [1:0] _zz_execute_BRANCH_CTRL; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire [1:0] memory_ENV_CTRL; + wire [1:0] _zz_memory_ENV_CTRL; + wire [1:0] execute_ENV_CTRL; + wire [1:0] _zz_execute_ENV_CTRL; + wire [1:0] writeBack_ENV_CTRL; + wire [1:0] _zz_writeBack_ENV_CTRL; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + wire execute_IS_MUL; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_decode_RS2; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_decode_RS2_1; + wire [1:0] memory_SHIFT_CTRL; + wire [1:0] _zz_memory_SHIFT_CTRL; + wire [1:0] execute_SHIFT_CTRL; + wire [1:0] _zz_execute_SHIFT_CTRL; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_decode_SRC2; + wire [31:0] _zz_decode_SRC2_1; + wire [1:0] decode_SRC2_CTRL; + wire [1:0] _zz_decode_SRC2_CTRL; + wire [31:0] _zz_decode_SRC1; + wire [1:0] decode_SRC1_CTRL; + wire [1:0] _zz_decode_SRC1_CTRL; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire [1:0] execute_ALU_CTRL; + wire [1:0] _zz_execute_ALU_CTRL; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire [1:0] execute_ALU_BITWISE_CTRL; + wire [1:0] _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire [1:0] _zz_decode_BRANCH_CTRL_1; + wire [1:0] _zz_decode_ENV_CTRL_1; + wire [1:0] _zz_decode_SHIFT_CTRL_1; + wire [1:0] _zz_decode_ALU_BITWISE_CTRL_1; + wire [1:0] _zz_decode_SRC2_CTRL_1; + wire [1:0] _zz_decode_ALU_CTRL_1; + wire [1:0] _zz_decode_SRC1_CTRL_1; + reg [31:0] _zz_decode_RS2_2; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_MEMORY_STORE_DATA_RF; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire memory_MEMORY_ENABLE; + wire [31:0] memory_MEMORY_VIRTUAL_ADDRESS; + wire execute_MEMORY_FORCE_CONSTISTENCY; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_MANAGMENT; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; + wire [31:0] decode_PC; + wire [31:0] decode_INSTRUCTION; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + reg decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + wire IBusCachedPlugin_forceNoDecodeCond; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_isPaging; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_isPaging; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + reg _zz_when_DBusCachedPlugin_l393; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; + wire CsrPlugin_inWfi /* verilator public */ ; + reg CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + reg CsrPlugin_allowEbreakException; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg BranchPlugin_inDebugNoFetchFlag; + reg IBusCachedPlugin_injectionPort_valid; + reg IBusCachedPlugin_injectionPort_ready; + wire [31:0] IBusCachedPlugin_injectionPort_payload; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l134; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l134_1; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l161; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l243; + wire IBusCachedPlugin_injector_decodeInput_valid; + wire IBusCachedPlugin_injector_decodeInput_ready; + wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_pc; + wire IBusCachedPlugin_injector_decodeInput_payload_rsp_error; + wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + wire IBusCachedPlugin_injector_decodeInput_payload_isRvc; + reg _zz_IBusCachedPlugin_injector_decodeInput_valid; + reg [31:0] _zz_IBusCachedPlugin_injector_decodeInput_payload_pc; + reg _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error; + reg [31:0] _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + reg _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc; + wire when_Fetcher_l323; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l332; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l332_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l332_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l332_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire when_Fetcher_l332_4; + reg IBusCachedPlugin_injector_nextPcCalc_valids_5; + wire when_Fetcher_l332_5; + reg [31:0] IBusCachedPlugin_injector_formal_rawInDecode; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + reg dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_rValid; + reg dataCache_1_io_mem_cmd_rData_wr; + reg dataCache_1_io_mem_cmd_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_rData_size; + reg dataCache_1_io_mem_cmd_rData_last; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire when_Stream_l368; + reg dBus_rsp_regNext_valid; + reg dBus_rsp_regNext_payload_last; + reg [31:0] dBus_rsp_regNext_payload_data; + reg dBus_rsp_regNext_payload_error; + reg [31:0] DBusCachedPlugin_rspCounter; + wire when_DBusCachedPlugin_l308; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; + wire dataCache_1_io_cpu_flush_isStall; + wire when_DBusCachedPlugin_l350; + wire when_DBusCachedPlugin_l366; + wire when_DBusCachedPlugin_l393; + wire when_DBusCachedPlugin_l446; + wire when_DBusCachedPlugin_l466; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire [31:0] writeBack_DBusCachedPlugin_rspRf; + wire [1:0] switch_Misc_l210; + wire _zz_writeBack_DBusCachedPlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; + wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire when_DBusCachedPlugin_l492; + wire [32:0] _zz_decode_BRANCH_CTRL_2; + wire _zz_decode_BRANCH_CTRL_3; + wire _zz_decode_BRANCH_CTRL_4; + wire _zz_decode_BRANCH_CTRL_5; + wire _zz_decode_BRANCH_CTRL_6; + wire _zz_decode_BRANCH_CTRL_7; + wire _zz_decode_BRANCH_CTRL_8; + wire [1:0] _zz_decode_SRC1_CTRL_2; + wire [1:0] _zz_decode_ALU_CTRL_2; + wire [1:0] _zz_decode_SRC2_CTRL_2; + wire [1:0] _zz_decode_ALU_BITWISE_CTRL_2; + wire [1:0] _zz_decode_SHIFT_CTRL_2; + wire [1:0] _zz_decode_ENV_CTRL_2; + wire [1:0] _zz_decode_BRANCH_CTRL_9; + wire when_RegFilePlugin_l63; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_2; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_decode_SRC1_1; + wire _zz_decode_SRC2_2; + reg [19:0] _zz_decode_SRC2_3; + wire _zz_decode_SRC2_4; + reg [19:0] _zz_decode_SRC2_5; + reg [31:0] _zz_decode_SRC2_6; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_decode_RS2_3; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + reg [0:0] execute_MulPlugin_delayLogic_counter; + wire when_MulPlugin_l65; + wire when_MulPlugin_l70; + wire [1:0] switch_MulPlugin_l87; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + reg [31:0] execute_MulPlugin_withOuputBuffer_mul_ll; + reg [33:0] execute_MulPlugin_withOuputBuffer_mul_lh; + reg [33:0] execute_MulPlugin_withOuputBuffer_mul_hl; + reg [33:0] execute_MulPlugin_withOuputBuffer_mul_hh; + wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; + reg [32:0] memory_MulDivIterativePlugin_rs1; + reg [31:0] memory_MulDivIterativePlugin_rs2; + reg [64:0] memory_MulDivIterativePlugin_accumulator; + wire memory_MulDivIterativePlugin_frontendOk; + reg memory_MulDivIterativePlugin_div_needRevert; + reg memory_MulDivIterativePlugin_div_counter_willIncrement; + reg memory_MulDivIterativePlugin_div_counter_willClear; + reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext; + reg [5:0] memory_MulDivIterativePlugin_div_counter_value; + wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; + wire memory_MulDivIterativePlugin_div_counter_willOverflow; + reg memory_MulDivIterativePlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; + reg [31:0] memory_MulDivIterativePlugin_div_result; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_MulDivIterativePlugin_rs2; + wire _zz_memory_MulDivIterativePlugin_rs1; + reg [32:0] _zz_memory_MulDivIterativePlugin_rs1_1; + reg [1:0] CsrPlugin_misa_base; + reg [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle; + reg [63:0] CsrPlugin_minstret; + wire _zz_when_CsrPlugin_l965; + wire _zz_when_CsrPlugin_l965_1; + wire _zz_when_CsrPlugin_l965_2; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire when_CsrPlugin_l922; + wire when_CsrPlugin_l922_1; + wire when_CsrPlugin_l922_2; + wire when_CsrPlugin_l922_3; + wire when_CsrPlugin_l935; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l959; + wire when_CsrPlugin_l965; + wire when_CsrPlugin_l965_1; + wire when_CsrPlugin_l965_2; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l993; + wire when_CsrPlugin_l993_1; + wire when_CsrPlugin_l993_2; + wire when_CsrPlugin_l998; + reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l1004; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1032; + wire when_CsrPlugin_l1077; + wire [1:0] switch_CsrPlugin_l1081; + reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1129; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire when_CsrPlugin_l1142; + wire when_CsrPlugin_l1149; + wire when_CsrPlugin_l1150; + wire when_CsrPlugin_l1157; + wire when_CsrPlugin_l1167; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + wire switch_Misc_l210_1; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1189; + wire when_CsrPlugin_l1193; + wire [11:0] execute_CsrPlugin_csrAddress; + wire execute_BranchPlugin_eq; + wire [2:0] switch_Misc_l210_2; + reg _zz_execute_BRANCH_DO; + reg _zz_execute_BRANCH_DO_1; + wire [31:0] execute_BranchPlugin_branch_src1; + wire _zz_execute_BranchPlugin_branch_src2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; + reg [31:0] _zz_execute_BranchPlugin_branch_src2_6; + wire [31:0] execute_BranchPlugin_branch_src2; + wire [31:0] execute_BranchPlugin_branchAdder; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + wire when_DebugPlugin_l225; + reg DebugPlugin_haltedByBreak; + reg DebugPlugin_debugUsed /* verilator public */ ; + reg DebugPlugin_disableEbreak; + wire DebugPlugin_allowEBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_when_DebugPlugin_l244; + wire when_DebugPlugin_l244; + wire [5:0] switch_DebugPlugin_l267; + wire when_DebugPlugin_l271; + wire when_DebugPlugin_l271_1; + wire when_DebugPlugin_l272; + wire when_DebugPlugin_l272_1; + wire when_DebugPlugin_l273; + wire when_DebugPlugin_l274; + wire when_DebugPlugin_l275; + wire when_DebugPlugin_l275_1; + wire when_DebugPlugin_l295; + wire when_DebugPlugin_l298; + wire when_DebugPlugin_l311; + reg DebugPlugin_resetIt_regNext; + wire when_DebugPlugin_l331; + wire when_Pipeline_l124; + reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; + reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; + reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; + reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; + reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; + reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + wire when_Pipeline_l124_10; + reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_11; + reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_12; + reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_13; + reg memory_to_writeBack_MEMORY_ENABLE; + wire when_Pipeline_l124_14; + reg [1:0] decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_15; + reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_16; + reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_17; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_19; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_20; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_21; + reg decode_to_execute_MEMORY_WR; + wire when_Pipeline_l124_22; + reg execute_to_memory_MEMORY_WR; + wire when_Pipeline_l124_23; + reg memory_to_writeBack_MEMORY_WR; + wire when_Pipeline_l124_24; + reg decode_to_execute_MEMORY_MANAGMENT; + wire when_Pipeline_l124_25; + reg decode_to_execute_SRC_LESS_UNSIGNED; + wire when_Pipeline_l124_26; + reg [1:0] decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_27; + reg [1:0] decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_28; + reg [1:0] execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_29; + reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_30; + reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_31; + reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_32; + reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_33; + reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_34; + reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_35; + reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_36; + reg decode_to_execute_IS_CSR; + wire when_Pipeline_l124_37; + reg [1:0] decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_38; + reg [1:0] execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_39; + reg [1:0] memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_40; + reg [1:0] decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_41; + reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_42; + reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_43; + reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_44; + reg [31:0] decode_to_execute_SRC1; + wire when_Pipeline_l124_45; + reg [31:0] decode_to_execute_SRC2; + wire when_Pipeline_l124_46; + reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_47; + reg decode_to_execute_CSR_READ_OPCODE; + wire when_Pipeline_l124_48; + reg decode_to_execute_DO_EBREAK; + wire when_Pipeline_l124_49; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_50; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_51; + (* keep , syn_keep *) reg [31:0] execute_to_memory_MEMORY_VIRTUAL_ADDRESS /* synthesis syn_keep = 1 */ ; + wire when_Pipeline_l124_52; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_53; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_54; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + wire when_Pipeline_l124_55; + reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_56; + reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_57; + reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_58; + reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_59; + reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_60; + reg execute_to_memory_BRANCH_DO; + wire when_Pipeline_l124_61; + reg [31:0] execute_to_memory_BRANCH_CALC; + wire when_Pipeline_l124_62; + reg [51:0] memory_to_writeBack_MUL_LOW; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + reg [2:0] switch_Fetcher_l365; + wire when_Fetcher_l381; + wire when_Fetcher_l401; + wire when_CsrPlugin_l1277; + reg execute_CsrPlugin_csr_3860; + wire when_CsrPlugin_l1277_1; + reg execute_CsrPlugin_csr_769; + wire when_CsrPlugin_l1277_2; + reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1277_3; + reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1277_4; + reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1277_5; + reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1277_6; + reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1277_7; + reg execute_CsrPlugin_csr_832; + wire when_CsrPlugin_l1277_8; + reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1277_9; + reg execute_CsrPlugin_csr_835; + wire [1:0] switch_CsrPlugin_l723; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + wire when_CsrPlugin_l1310; + wire when_CsrPlugin_l1315; + `ifndef SYNTHESIS + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [47:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [47:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [47:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [47:0] _zz_execute_to_memory_ENV_CTRL_1_string; + reg [47:0] decode_ENV_CTRL_string; + reg [47:0] _zz_decode_ENV_CTRL_string; + reg [47:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [47:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; + reg [47:0] memory_ENV_CTRL_string; + reg [47:0] _zz_memory_ENV_CTRL_string; + reg [47:0] execute_ENV_CTRL_string; + reg [47:0] _zz_execute_ENV_CTRL_string; + reg [47:0] writeBack_ENV_CTRL_string; + reg [47:0] _zz_writeBack_ENV_CTRL_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_execute_ALU_CTRL_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [47:0] _zz_decode_ENV_CTRL_1_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [47:0] _zz_decode_ENV_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_9_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [47:0] decode_to_execute_ENV_CTRL_string; + reg [47:0] execute_to_memory_ENV_CTRL_string; + reg [47:0] memory_to_writeBack_ENV_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + `endif + + reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == ShiftCtrlEnum_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 3'b001); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz_io_cpu_flush_payload_lineId = _zz_io_cpu_flush_payload_lineId_1; + assign _zz_io_cpu_flush_payload_lineId_1 = (execute_RS1 >>> 6); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_decode_SRC1_1 = 3'b100; + assign _zz__zz_decode_SRC1_1_1 = decode_INSTRUCTION[19 : 15]; + assign _zz__zz_decode_SRC2_4 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1 = memory_MulDivIterativePlugin_div_counter_willIncrement; + assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext = {5'd0, _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1}; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_MulDivIterativePlugin_rs2}; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator = {_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_MulDivIterativePlugin_div_result_1 = _zz_memory_MulDivIterativePlugin_div_result_2; + assign _zz_memory_MulDivIterativePlugin_div_result_2 = _zz_memory_MulDivIterativePlugin_div_result_3; + assign _zz_memory_MulDivIterativePlugin_div_result_3 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_memory_MulDivIterativePlugin_div_result) : _zz_memory_MulDivIterativePlugin_div_result)} + _zz_memory_MulDivIterativePlugin_div_result_4); + assign _zz_memory_MulDivIterativePlugin_div_result_5 = memory_MulDivIterativePlugin_div_needRevert; + assign _zz_memory_MulDivIterativePlugin_div_result_4 = {32'd0, _zz_memory_MulDivIterativePlugin_div_result_5}; + assign _zz_memory_MulDivIterativePlugin_rs1_3 = _zz_memory_MulDivIterativePlugin_rs1; + assign _zz_memory_MulDivIterativePlugin_rs1_2 = {32'd0, _zz_memory_MulDivIterativePlugin_rs1_3}; + assign _zz_memory_MulDivIterativePlugin_rs2_2 = _zz_memory_MulDivIterativePlugin_rs2; + assign _zz_memory_MulDivIterativePlugin_rs2_1 = {31'd0, _zz_memory_MulDivIterativePlugin_rs2_2}; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz__zz_execute_BranchPlugin_branch_src2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_3,_zz_IBusCachedPlugin_jump_pcLoad_payload_2}; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00001013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hfc00307f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00005033; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; + assign _zz__zz_decode_BRANCH_CTRL_2 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz__zz_decode_BRANCH_CTRL_2_1 = 32'h00000004; + assign _zz__zz_decode_BRANCH_CTRL_2_2 = (decode_INSTRUCTION & 32'h00000058); + assign _zz__zz_decode_BRANCH_CTRL_2_3 = 32'h00000040; + assign _zz__zz_decode_BRANCH_CTRL_2_4 = ((decode_INSTRUCTION & 32'h10003050) == 32'h00000050); + assign _zz__zz_decode_BRANCH_CTRL_2_5 = (|{_zz_decode_BRANCH_CTRL_8,(_zz__zz_decode_BRANCH_CTRL_2_6 == _zz__zz_decode_BRANCH_CTRL_2_7)}); + assign _zz__zz_decode_BRANCH_CTRL_2_8 = (|{_zz__zz_decode_BRANCH_CTRL_2_9,_zz__zz_decode_BRANCH_CTRL_2_10}); + assign _zz__zz_decode_BRANCH_CTRL_2_11 = {(|_zz_decode_BRANCH_CTRL_7),{(|_zz__zz_decode_BRANCH_CTRL_2_12),{_zz__zz_decode_BRANCH_CTRL_2_13,{_zz__zz_decode_BRANCH_CTRL_2_15,_zz__zz_decode_BRANCH_CTRL_2_18}}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_6 = (decode_INSTRUCTION & 32'h10403050); + assign _zz__zz_decode_BRANCH_CTRL_2_7 = 32'h10000050; + assign _zz__zz_decode_BRANCH_CTRL_2_9 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz__zz_decode_BRANCH_CTRL_2_10 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz__zz_decode_BRANCH_CTRL_2_12 = _zz_decode_BRANCH_CTRL_7; + assign _zz__zz_decode_BRANCH_CTRL_2_13 = (|((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_14) == 32'h02004020)); + assign _zz__zz_decode_BRANCH_CTRL_2_15 = (|(_zz__zz_decode_BRANCH_CTRL_2_16 == _zz__zz_decode_BRANCH_CTRL_2_17)); + assign _zz__zz_decode_BRANCH_CTRL_2_18 = {(|{_zz__zz_decode_BRANCH_CTRL_2_19,_zz__zz_decode_BRANCH_CTRL_2_21}),{(|_zz__zz_decode_BRANCH_CTRL_2_23),{_zz__zz_decode_BRANCH_CTRL_2_28,{_zz__zz_decode_BRANCH_CTRL_2_31,_zz__zz_decode_BRANCH_CTRL_2_33}}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_14 = 32'h02004064; + assign _zz__zz_decode_BRANCH_CTRL_2_16 = (decode_INSTRUCTION & 32'h02004074); + assign _zz__zz_decode_BRANCH_CTRL_2_17 = 32'h02000030; + assign _zz__zz_decode_BRANCH_CTRL_2_19 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_20) == 32'h00005010); + assign _zz__zz_decode_BRANCH_CTRL_2_21 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_22) == 32'h00005020); + assign _zz__zz_decode_BRANCH_CTRL_2_23 = {(_zz__zz_decode_BRANCH_CTRL_2_24 == _zz__zz_decode_BRANCH_CTRL_2_25),{_zz__zz_decode_BRANCH_CTRL_2_26,_zz__zz_decode_BRANCH_CTRL_2_27}}; + assign _zz__zz_decode_BRANCH_CTRL_2_28 = (|(_zz__zz_decode_BRANCH_CTRL_2_29 == _zz__zz_decode_BRANCH_CTRL_2_30)); + assign _zz__zz_decode_BRANCH_CTRL_2_31 = (|_zz__zz_decode_BRANCH_CTRL_2_32); + assign _zz__zz_decode_BRANCH_CTRL_2_33 = {(|_zz__zz_decode_BRANCH_CTRL_2_34),{_zz__zz_decode_BRANCH_CTRL_2_36,{_zz__zz_decode_BRANCH_CTRL_2_39,_zz__zz_decode_BRANCH_CTRL_2_41}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_20 = 32'h00007034; + assign _zz__zz_decode_BRANCH_CTRL_2_22 = 32'h02007064; + assign _zz__zz_decode_BRANCH_CTRL_2_24 = (decode_INSTRUCTION & 32'h40003054); + assign _zz__zz_decode_BRANCH_CTRL_2_25 = 32'h40001010; + assign _zz__zz_decode_BRANCH_CTRL_2_26 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); + assign _zz__zz_decode_BRANCH_CTRL_2_27 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); + assign _zz__zz_decode_BRANCH_CTRL_2_29 = (decode_INSTRUCTION & 32'h00000064); + assign _zz__zz_decode_BRANCH_CTRL_2_30 = 32'h00000024; + assign _zz__zz_decode_BRANCH_CTRL_2_32 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz__zz_decode_BRANCH_CTRL_2_34 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_35) == 32'h00002000); + assign _zz__zz_decode_BRANCH_CTRL_2_36 = (|{_zz__zz_decode_BRANCH_CTRL_2_37,_zz__zz_decode_BRANCH_CTRL_2_38}); + assign _zz__zz_decode_BRANCH_CTRL_2_39 = (|_zz__zz_decode_BRANCH_CTRL_2_40); + assign _zz__zz_decode_BRANCH_CTRL_2_41 = {(|_zz__zz_decode_BRANCH_CTRL_2_42),{_zz__zz_decode_BRANCH_CTRL_2_47,{_zz__zz_decode_BRANCH_CTRL_2_56,_zz__zz_decode_BRANCH_CTRL_2_58}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_35 = 32'h00003000; + assign _zz__zz_decode_BRANCH_CTRL_2_37 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz__zz_decode_BRANCH_CTRL_2_38 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz__zz_decode_BRANCH_CTRL_2_40 = ((decode_INSTRUCTION & 32'h00004048) == 32'h00004008); + assign _zz__zz_decode_BRANCH_CTRL_2_42 = {(_zz__zz_decode_BRANCH_CTRL_2_43 == _zz__zz_decode_BRANCH_CTRL_2_44),(_zz__zz_decode_BRANCH_CTRL_2_45 == _zz__zz_decode_BRANCH_CTRL_2_46)}; + assign _zz__zz_decode_BRANCH_CTRL_2_47 = (|{_zz__zz_decode_BRANCH_CTRL_2_48,{_zz__zz_decode_BRANCH_CTRL_2_49,_zz__zz_decode_BRANCH_CTRL_2_51}}); + assign _zz__zz_decode_BRANCH_CTRL_2_56 = (|_zz__zz_decode_BRANCH_CTRL_2_57); + assign _zz__zz_decode_BRANCH_CTRL_2_58 = {(|_zz__zz_decode_BRANCH_CTRL_2_59),{_zz__zz_decode_BRANCH_CTRL_2_70,{_zz__zz_decode_BRANCH_CTRL_2_83,_zz__zz_decode_BRANCH_CTRL_2_97}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_43 = (decode_INSTRUCTION & 32'h00000034); + assign _zz__zz_decode_BRANCH_CTRL_2_44 = 32'h00000020; + assign _zz__zz_decode_BRANCH_CTRL_2_45 = (decode_INSTRUCTION & 32'h00000064); + assign _zz__zz_decode_BRANCH_CTRL_2_46 = 32'h00000020; + assign _zz__zz_decode_BRANCH_CTRL_2_48 = ((decode_INSTRUCTION & 32'h00002040) == 32'h00002040); + assign _zz__zz_decode_BRANCH_CTRL_2_49 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_50) == 32'h00001040); + assign _zz__zz_decode_BRANCH_CTRL_2_51 = {(_zz__zz_decode_BRANCH_CTRL_2_52 == _zz__zz_decode_BRANCH_CTRL_2_53),{_zz__zz_decode_BRANCH_CTRL_2_54,_zz_decode_BRANCH_CTRL_4}}; + assign _zz__zz_decode_BRANCH_CTRL_2_57 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); + assign _zz__zz_decode_BRANCH_CTRL_2_59 = {(_zz__zz_decode_BRANCH_CTRL_2_60 == _zz__zz_decode_BRANCH_CTRL_2_61),{_zz_decode_BRANCH_CTRL_5,{_zz__zz_decode_BRANCH_CTRL_2_62,_zz__zz_decode_BRANCH_CTRL_2_65}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_70 = (|{_zz_decode_BRANCH_CTRL_5,{_zz__zz_decode_BRANCH_CTRL_2_71,_zz__zz_decode_BRANCH_CTRL_2_74}}); + assign _zz__zz_decode_BRANCH_CTRL_2_83 = (|{_zz__zz_decode_BRANCH_CTRL_2_84,_zz__zz_decode_BRANCH_CTRL_2_85}); + assign _zz__zz_decode_BRANCH_CTRL_2_97 = {(|_zz__zz_decode_BRANCH_CTRL_2_98),{_zz__zz_decode_BRANCH_CTRL_2_101,{_zz__zz_decode_BRANCH_CTRL_2_106,_zz__zz_decode_BRANCH_CTRL_2_110}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_50 = 32'h00001040; + assign _zz__zz_decode_BRANCH_CTRL_2_52 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_BRANCH_CTRL_2_53 = 32'h00000040; + assign _zz__zz_decode_BRANCH_CTRL_2_54 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_55) == 32'h00000040); + assign _zz__zz_decode_BRANCH_CTRL_2_60 = (decode_INSTRUCTION & 32'h00000040); + assign _zz__zz_decode_BRANCH_CTRL_2_61 = 32'h00000040; + assign _zz__zz_decode_BRANCH_CTRL_2_62 = (_zz__zz_decode_BRANCH_CTRL_2_63 == _zz__zz_decode_BRANCH_CTRL_2_64); + assign _zz__zz_decode_BRANCH_CTRL_2_65 = {_zz__zz_decode_BRANCH_CTRL_2_66,_zz__zz_decode_BRANCH_CTRL_2_68}; + assign _zz__zz_decode_BRANCH_CTRL_2_71 = (_zz__zz_decode_BRANCH_CTRL_2_72 == _zz__zz_decode_BRANCH_CTRL_2_73); + assign _zz__zz_decode_BRANCH_CTRL_2_74 = {_zz__zz_decode_BRANCH_CTRL_2_75,{_zz__zz_decode_BRANCH_CTRL_2_77,_zz__zz_decode_BRANCH_CTRL_2_80}}; + assign _zz__zz_decode_BRANCH_CTRL_2_84 = _zz_decode_BRANCH_CTRL_6; + assign _zz__zz_decode_BRANCH_CTRL_2_85 = {_zz__zz_decode_BRANCH_CTRL_2_86,{_zz__zz_decode_BRANCH_CTRL_2_88,_zz__zz_decode_BRANCH_CTRL_2_91}}; + assign _zz__zz_decode_BRANCH_CTRL_2_98 = {_zz_decode_BRANCH_CTRL_5,_zz__zz_decode_BRANCH_CTRL_2_99}; + assign _zz__zz_decode_BRANCH_CTRL_2_101 = (|{_zz__zz_decode_BRANCH_CTRL_2_102,_zz__zz_decode_BRANCH_CTRL_2_103}); + assign _zz__zz_decode_BRANCH_CTRL_2_106 = (|_zz__zz_decode_BRANCH_CTRL_2_107); + assign _zz__zz_decode_BRANCH_CTRL_2_110 = {_zz__zz_decode_BRANCH_CTRL_2_111,{_zz__zz_decode_BRANCH_CTRL_2_113,_zz__zz_decode_BRANCH_CTRL_2_124}}; + assign _zz__zz_decode_BRANCH_CTRL_2_55 = 32'h00400040; + assign _zz__zz_decode_BRANCH_CTRL_2_63 = (decode_INSTRUCTION & 32'h00004020); + assign _zz__zz_decode_BRANCH_CTRL_2_64 = 32'h00004020; + assign _zz__zz_decode_BRANCH_CTRL_2_66 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_67) == 32'h00000010); + assign _zz__zz_decode_BRANCH_CTRL_2_68 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_69) == 32'h00000020); + assign _zz__zz_decode_BRANCH_CTRL_2_72 = (decode_INSTRUCTION & 32'h00002030); + assign _zz__zz_decode_BRANCH_CTRL_2_73 = 32'h00002010; + assign _zz__zz_decode_BRANCH_CTRL_2_75 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_76) == 32'h00000010); + assign _zz__zz_decode_BRANCH_CTRL_2_77 = (_zz__zz_decode_BRANCH_CTRL_2_78 == _zz__zz_decode_BRANCH_CTRL_2_79); + assign _zz__zz_decode_BRANCH_CTRL_2_80 = (_zz__zz_decode_BRANCH_CTRL_2_81 == _zz__zz_decode_BRANCH_CTRL_2_82); + assign _zz__zz_decode_BRANCH_CTRL_2_86 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_87) == 32'h00001010); + assign _zz__zz_decode_BRANCH_CTRL_2_88 = (_zz__zz_decode_BRANCH_CTRL_2_89 == _zz__zz_decode_BRANCH_CTRL_2_90); + assign _zz__zz_decode_BRANCH_CTRL_2_91 = {_zz__zz_decode_BRANCH_CTRL_2_92,{_zz__zz_decode_BRANCH_CTRL_2_93,_zz__zz_decode_BRANCH_CTRL_2_95}}; + assign _zz__zz_decode_BRANCH_CTRL_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_100) == 32'h00000020); + assign _zz__zz_decode_BRANCH_CTRL_2_102 = _zz_decode_BRANCH_CTRL_5; + assign _zz__zz_decode_BRANCH_CTRL_2_103 = (_zz__zz_decode_BRANCH_CTRL_2_104 == _zz__zz_decode_BRANCH_CTRL_2_105); + assign _zz__zz_decode_BRANCH_CTRL_2_107 = (_zz__zz_decode_BRANCH_CTRL_2_108 == _zz__zz_decode_BRANCH_CTRL_2_109); + assign _zz__zz_decode_BRANCH_CTRL_2_111 = (|_zz__zz_decode_BRANCH_CTRL_2_112); + assign _zz__zz_decode_BRANCH_CTRL_2_113 = (|_zz__zz_decode_BRANCH_CTRL_2_114); + assign _zz__zz_decode_BRANCH_CTRL_2_124 = {_zz__zz_decode_BRANCH_CTRL_2_125,{_zz__zz_decode_BRANCH_CTRL_2_128,_zz__zz_decode_BRANCH_CTRL_2_136}}; + assign _zz__zz_decode_BRANCH_CTRL_2_67 = 32'h00000030; + assign _zz__zz_decode_BRANCH_CTRL_2_69 = 32'h02000020; + assign _zz__zz_decode_BRANCH_CTRL_2_76 = 32'h00001030; + assign _zz__zz_decode_BRANCH_CTRL_2_78 = (decode_INSTRUCTION & 32'h02002060); + assign _zz__zz_decode_BRANCH_CTRL_2_79 = 32'h00002020; + assign _zz__zz_decode_BRANCH_CTRL_2_81 = (decode_INSTRUCTION & 32'h02003020); + assign _zz__zz_decode_BRANCH_CTRL_2_82 = 32'h00000020; + assign _zz__zz_decode_BRANCH_CTRL_2_87 = 32'h00001010; + assign _zz__zz_decode_BRANCH_CTRL_2_89 = (decode_INSTRUCTION & 32'h00002010); + assign _zz__zz_decode_BRANCH_CTRL_2_90 = 32'h00002010; + assign _zz__zz_decode_BRANCH_CTRL_2_92 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); + assign _zz__zz_decode_BRANCH_CTRL_2_93 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_94) == 32'h00000004); + assign _zz__zz_decode_BRANCH_CTRL_2_95 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_96) == 32'h0); + assign _zz__zz_decode_BRANCH_CTRL_2_100 = 32'h00000070; + assign _zz__zz_decode_BRANCH_CTRL_2_104 = (decode_INSTRUCTION & 32'h00000020); + assign _zz__zz_decode_BRANCH_CTRL_2_105 = 32'h0; + assign _zz__zz_decode_BRANCH_CTRL_2_108 = (decode_INSTRUCTION & 32'h00004014); + assign _zz__zz_decode_BRANCH_CTRL_2_109 = 32'h00004010; + assign _zz__zz_decode_BRANCH_CTRL_2_112 = ((decode_INSTRUCTION & 32'h00006014) == 32'h00002010); + assign _zz__zz_decode_BRANCH_CTRL_2_114 = {(_zz__zz_decode_BRANCH_CTRL_2_115 == _zz__zz_decode_BRANCH_CTRL_2_116),{_zz_decode_BRANCH_CTRL_4,{_zz__zz_decode_BRANCH_CTRL_2_117,_zz__zz_decode_BRANCH_CTRL_2_119}}}; + assign _zz__zz_decode_BRANCH_CTRL_2_125 = (|(_zz__zz_decode_BRANCH_CTRL_2_126 == _zz__zz_decode_BRANCH_CTRL_2_127)); + assign _zz__zz_decode_BRANCH_CTRL_2_128 = (|{_zz__zz_decode_BRANCH_CTRL_2_129,_zz__zz_decode_BRANCH_CTRL_2_131}); + assign _zz__zz_decode_BRANCH_CTRL_2_136 = {(|_zz__zz_decode_BRANCH_CTRL_2_137),{_zz__zz_decode_BRANCH_CTRL_2_140,_zz__zz_decode_BRANCH_CTRL_2_142}}; + assign _zz__zz_decode_BRANCH_CTRL_2_94 = 32'h0000000c; + assign _zz__zz_decode_BRANCH_CTRL_2_96 = 32'h00000028; + assign _zz__zz_decode_BRANCH_CTRL_2_115 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_BRANCH_CTRL_2_116 = 32'h0; + assign _zz__zz_decode_BRANCH_CTRL_2_117 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_118) == 32'h00002000); + assign _zz__zz_decode_BRANCH_CTRL_2_119 = {(_zz__zz_decode_BRANCH_CTRL_2_120 == _zz__zz_decode_BRANCH_CTRL_2_121),(_zz__zz_decode_BRANCH_CTRL_2_122 == _zz__zz_decode_BRANCH_CTRL_2_123)}; + assign _zz__zz_decode_BRANCH_CTRL_2_126 = (decode_INSTRUCTION & 32'h00000058); + assign _zz__zz_decode_BRANCH_CTRL_2_127 = 32'h0; + assign _zz__zz_decode_BRANCH_CTRL_2_129 = ((decode_INSTRUCTION & _zz__zz_decode_BRANCH_CTRL_2_130) == 32'h00000040); + assign _zz__zz_decode_BRANCH_CTRL_2_131 = {(_zz__zz_decode_BRANCH_CTRL_2_132 == _zz__zz_decode_BRANCH_CTRL_2_133),(_zz__zz_decode_BRANCH_CTRL_2_134 == _zz__zz_decode_BRANCH_CTRL_2_135)}; + assign _zz__zz_decode_BRANCH_CTRL_2_137 = {(_zz__zz_decode_BRANCH_CTRL_2_138 == _zz__zz_decode_BRANCH_CTRL_2_139),_zz_decode_BRANCH_CTRL_3}; + assign _zz__zz_decode_BRANCH_CTRL_2_140 = (|{_zz__zz_decode_BRANCH_CTRL_2_141,_zz_decode_BRANCH_CTRL_3}); + assign _zz__zz_decode_BRANCH_CTRL_2_142 = (|(_zz__zz_decode_BRANCH_CTRL_2_143 == _zz__zz_decode_BRANCH_CTRL_2_144)); + assign _zz__zz_decode_BRANCH_CTRL_2_118 = 32'h00006004; + assign _zz__zz_decode_BRANCH_CTRL_2_120 = (decode_INSTRUCTION & 32'h00005004); + assign _zz__zz_decode_BRANCH_CTRL_2_121 = 32'h00001000; + assign _zz__zz_decode_BRANCH_CTRL_2_122 = (decode_INSTRUCTION & 32'h00004050); + assign _zz__zz_decode_BRANCH_CTRL_2_123 = 32'h00004000; + assign _zz__zz_decode_BRANCH_CTRL_2_130 = 32'h00000044; + assign _zz__zz_decode_BRANCH_CTRL_2_132 = (decode_INSTRUCTION & 32'h00002014); + assign _zz__zz_decode_BRANCH_CTRL_2_133 = 32'h00002010; + assign _zz__zz_decode_BRANCH_CTRL_2_134 = (decode_INSTRUCTION & 32'h40000034); + assign _zz__zz_decode_BRANCH_CTRL_2_135 = 32'h40000030; + assign _zz__zz_decode_BRANCH_CTRL_2_138 = (decode_INSTRUCTION & 32'h00000014); + assign _zz__zz_decode_BRANCH_CTRL_2_139 = 32'h00000004; + assign _zz__zz_decode_BRANCH_CTRL_2_141 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz__zz_decode_BRANCH_CTRL_2_143 = (decode_INSTRUCTION & 32'h00005048); + assign _zz__zz_decode_BRANCH_CTRL_2_144 = 32'h00001008; + always @(posedge io_systemClk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_1) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0]), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0]), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i + .io_cpu_execute_address (dataCache_1_io_cpu_execute_address[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (memory_MEMORY_VIRTUAL_ADDRESS[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0]), //i + .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isFiring (writeBack_arbitration_isFiring ), //i + .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData[31:0] ), //i + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i + .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i + .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i + .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i + .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i + .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i + .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i + .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i + .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM[3:0] ), //i + .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_cpu_flush_payload_singleLine (dataCache_1_io_cpu_flush_payload_singleLine ), //i + .io_cpu_flush_payload_lineId (dataCache_1_io_cpu_flush_payload_lineId[5:0] ), //i + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_regNext_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_regNext_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_regNext_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_regNext_payload_error ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + always @(*) begin + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_5) + 2'b00 : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = DBusCachedPlugin_redoBranch_payload; + 2'b01 : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = CsrPlugin_jumpInterface_payload; + default : _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = BranchPlugin_jumpInterface_payload; + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) + 2'b00 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; + 2'b01 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; + 2'b10 : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; + default : _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) + 1'b0 : _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; + default : _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(decode_BRANCH_CTRL) + BranchCtrlEnum_INC : decode_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : decode_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : decode_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_BRANCH_CTRL) + BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_BRANCH_CTRL) + BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_BRANCH_CTRL_1) + BranchCtrlEnum_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + BranchCtrlEnum_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_memory_to_writeBack_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_memory_to_writeBack_ENV_CTRL_string = "EBREAK"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_memory_to_writeBack_ENV_CTRL_1) + EnvCtrlEnum_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + EnvCtrlEnum_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_memory_to_writeBack_ENV_CTRL_1_string = "EBREAK"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "??????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_execute_to_memory_ENV_CTRL_string = "EBREAK"; + default : _zz_execute_to_memory_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_ENV_CTRL_1) + EnvCtrlEnum_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + EnvCtrlEnum_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_execute_to_memory_ENV_CTRL_1_string = "EBREAK"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "??????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + EnvCtrlEnum_NONE : decode_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : decode_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : decode_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : decode_ENV_CTRL_string = "EBREAK"; + default : decode_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_decode_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_string = "EBREAK"; + default : _zz_decode_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_decode_to_execute_ENV_CTRL_string = "EBREAK"; + default : _zz_decode_to_execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ENV_CTRL_1) + EnvCtrlEnum_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + EnvCtrlEnum_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_decode_to_execute_ENV_CTRL_1_string = "EBREAK"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "??????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_SHIFT_CTRL_1) + ShiftCtrlEnum_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_SHIFT_CTRL_1) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + AluCtrlEnum_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_CTRL) + AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_CTRL) + AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_CTRL_1) + AluCtrlEnum_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + BranchCtrlEnum_INC : execute_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : execute_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : execute_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_execute_BRANCH_CTRL) + BranchCtrlEnum_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : _zz_execute_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + EnvCtrlEnum_NONE : memory_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : memory_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : memory_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : memory_ENV_CTRL_string = "EBREAK"; + default : memory_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_memory_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_memory_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_memory_ENV_CTRL_string = "EBREAK"; + default : _zz_memory_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + EnvCtrlEnum_NONE : execute_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : execute_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : execute_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : execute_ENV_CTRL_string = "EBREAK"; + default : execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_execute_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_execute_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_execute_ENV_CTRL_string = "EBREAK"; + default : _zz_execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + EnvCtrlEnum_NONE : writeBack_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : writeBack_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : writeBack_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : writeBack_ENV_CTRL_string = "EBREAK"; + default : writeBack_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_writeBack_ENV_CTRL) + EnvCtrlEnum_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_writeBack_ENV_CTRL_string = "EBREAK"; + default : _zz_writeBack_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_memory_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_execute_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + Src2CtrlEnum_RS : decode_SRC2_CTRL_string = "RS "; + Src2CtrlEnum_IMI : decode_SRC2_CTRL_string = "IMI"; + Src2CtrlEnum_IMS : decode_SRC2_CTRL_string = "IMS"; + Src2CtrlEnum_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_SRC2_CTRL) + Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_string = "RS "; + Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + Src1CtrlEnum_RS : decode_SRC1_CTRL_string = "RS "; + Src1CtrlEnum_IMU : decode_SRC1_CTRL_string = "IMU "; + Src1CtrlEnum_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + Src1CtrlEnum_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC1_CTRL) + Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_string = "RS "; + Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + AluCtrlEnum_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_execute_ALU_CTRL) + AluCtrlEnum_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_BRANCH_CTRL_1) + BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_ENV_CTRL_1) + EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_1_string = "EBREAK"; + default : _zz_decode_ENV_CTRL_1_string = "??????"; + endcase + end + always @(*) begin + case(_zz_decode_SHIFT_CTRL_1) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_BITWISE_CTRL_1) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC2_CTRL_1) + Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_CTRL_1) + AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC1_CTRL_1) + Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC1_CTRL_2) + Src1CtrlEnum_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + Src1CtrlEnum_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + Src1CtrlEnum_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + Src1CtrlEnum_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_CTRL_2) + AluCtrlEnum_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC2_CTRL_2) + Src2CtrlEnum_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + Src2CtrlEnum_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + Src2CtrlEnum_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + Src2CtrlEnum_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_BITWISE_CTRL_2) + AluBitwiseCtrlEnum_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_SHIFT_CTRL_2) + ShiftCtrlEnum_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_ENV_CTRL_2) + EnvCtrlEnum_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + EnvCtrlEnum_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + EnvCtrlEnum_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL "; + EnvCtrlEnum_EBREAK : _zz_decode_ENV_CTRL_2_string = "EBREAK"; + default : _zz_decode_ENV_CTRL_2_string = "??????"; + endcase + end + always @(*) begin + case(_zz_decode_BRANCH_CTRL_9) + BranchCtrlEnum_INC : _zz_decode_BRANCH_CTRL_9_string = "INC "; + BranchCtrlEnum_B : _zz_decode_BRANCH_CTRL_9_string = "B "; + BranchCtrlEnum_JAL : _zz_decode_BRANCH_CTRL_9_string = "JAL "; + BranchCtrlEnum_JALR : _zz_decode_BRANCH_CTRL_9_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_9_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + AluCtrlEnum_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + AluCtrlEnum_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + AluCtrlEnum_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + AluBitwiseCtrlEnum_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + AluBitwiseCtrlEnum_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + ShiftCtrlEnum_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + ShiftCtrlEnum_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + ShiftCtrlEnum_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + ShiftCtrlEnum_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + EnvCtrlEnum_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : decode_to_execute_ENV_CTRL_string = "EBREAK"; + default : decode_to_execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + EnvCtrlEnum_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : execute_to_memory_ENV_CTRL_string = "EBREAK"; + default : execute_to_memory_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + EnvCtrlEnum_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + EnvCtrlEnum_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + EnvCtrlEnum_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL "; + EnvCtrlEnum_EBREAK : memory_to_writeBack_ENV_CTRL_string = "EBREAK"; + default : memory_to_writeBack_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + BranchCtrlEnum_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + BranchCtrlEnum_B : decode_to_execute_BRANCH_CTRL_string = "B "; + BranchCtrlEnum_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + BranchCtrlEnum_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + `endif + + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = _zz_execute_BRANCH_DO_1; + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = execute_MulPlugin_withOuputBuffer_mul_hh; + assign execute_MUL_HL = execute_MulPlugin_withOuputBuffer_mul_hl; + assign execute_MUL_LH = execute_MulPlugin_withOuputBuffer_mul_lh; + assign execute_MUL_LL = execute_MulPlugin_withOuputBuffer_mul_ll; + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign execute_MEMORY_VIRTUAL_ADDRESS = dataCache_1_io_cpu_execute_address; + assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; + assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; + assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_SRC2 = _zz_decode_SRC2_6; + assign decode_SRC1 = _zz_decode_SRC1_1; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_BRANCH_CTRL_2[27]; + assign decode_IS_RS2_SIGNED = _zz_decode_BRANCH_CTRL_2[26]; + assign decode_IS_RS1_SIGNED = _zz_decode_BRANCH_CTRL_2[25]; + assign decode_IS_DIV = _zz_decode_BRANCH_CTRL_2[24]; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign decode_IS_MUL = _zz_decode_BRANCH_CTRL_2[23]; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_BRANCH_CTRL_2[17]; + assign decode_MEMORY_MANAGMENT = _zz_decode_BRANCH_CTRL_2[16]; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_decode_BRANCH_CTRL_2[13]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_BRANCH_CTRL_2[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_BRANCH_CTRL_2[11]; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_decode_BRANCH_CTRL_2[30]; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PC = decode_to_execute_PC; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_RS2_USE = _zz_decode_BRANCH_CTRL_2[15]; + assign decode_RS1_USE = _zz_decode_BRANCH_CTRL_2[5]; + always @(*) begin + _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1189) begin + _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; + end + end + + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @(*) begin + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; + end + end + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; + end + end + end + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2_1; + end + end + end + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2; + end + end + end + end + + always @(*) begin + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; + end + end + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; + end + end + end + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2_1; + end + end + end + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2; + end + end + end + end + + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; + always @(*) begin + _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin + case(memory_SHIFT_CTRL) + ShiftCtrlEnum_SLL_1 : begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; + end + ShiftCtrlEnum_SRL_1, ShiftCtrlEnum_SRA_1 : begin + _zz_decode_RS2_1 = memory_SHIFT_RIGHT; + end + default : begin + end + endcase + end + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2_1 = memory_MulDivIterativePlugin_div_result; + end + end + + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_decode_SRC2 = decode_PC; + assign _zz_decode_SRC2_1 = decode_RS2; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_SRC1 = decode_RS1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_BRANCH_CTRL_2[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_BRANCH_CTRL_2[20]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = decode_to_execute_SRC2; + assign execute_SRC1 = decode_to_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_iBusRsp_output_payload_rsp_inst); + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_BRANCH_CTRL_2[10]; + if(when_RegFilePlugin_l63) begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = (|{((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}}); + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusCachedPlugin_l492) begin + _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; + end + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) + 2'b00 : begin + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; + end + default : begin + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; + end + endcase + end + end + + assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign memory_MEMORY_VIRTUAL_ADDRESS = execute_to_memory_MEMORY_VIRTUAL_ADDRESS; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign decode_MEMORY_ENABLE = _zz_decode_BRANCH_CTRL_2[4]; + assign decode_FLUSH_ALL = _zz_decode_BRANCH_CTRL_2[0]; + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(when_IBusCachedPlugin_l256) begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(when_IBusCachedPlugin_l244) begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(when_IBusCachedPlugin_l239) begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; + end + end + + always @(*) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; + end + end + + assign decode_PC = IBusCachedPlugin_injector_decodeInput_payload_pc; + assign decode_INSTRUCTION = IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @(*) begin + decode_arbitration_haltItself = 1'b0; + if(when_DBusCachedPlugin_l308) begin + decode_arbitration_haltItself = 1'b1; + end + case(switch_Fetcher_l365) + 3'b010 : begin + decode_arbitration_haltItself = 1'b1; + end + default : begin + end + endcase + end + + always @(*) begin + decode_arbitration_haltByOther = 1'b0; + if(when_HazardSimplePlugin_l113) begin + decode_arbitration_haltByOther = 1'b1; + end + if(CsrPlugin_pipelineLiberator_active) begin + decode_arbitration_haltByOther = 1'b1; + end + if(when_CsrPlugin_l1129) begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @(*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_when) begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed) begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + always @(*) begin + decode_arbitration_flushNext = 1'b0; + if(_zz_when) begin + decode_arbitration_flushNext = 1'b1; + end + end + + always @(*) begin + execute_arbitration_haltItself = 1'b0; + if(when_DBusCachedPlugin_l350) begin + execute_arbitration_haltItself = 1'b1; + end + if(when_MulPlugin_l65) begin + execute_arbitration_haltItself = 1'b1; + end + if(when_CsrPlugin_l1193) begin + if(execute_CsrPlugin_blockedBySideEffects) begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + always @(*) begin + execute_arbitration_haltByOther = 1'b0; + if(when_DBusCachedPlugin_l366) begin + execute_arbitration_haltByOther = 1'b1; + end + if(when_DebugPlugin_l295) begin + execute_arbitration_haltByOther = 1'b1; + end + end + + always @(*) begin + execute_arbitration_removeIt = 1'b0; + if(CsrPlugin_selfException_valid) begin + execute_arbitration_removeIt = 1'b1; + end + if(execute_arbitration_isFlushed) begin + execute_arbitration_removeIt = 1'b1; + end + end + + always @(*) begin + execute_arbitration_flushIt = 1'b0; + if(when_DebugPlugin_l295) begin + if(when_DebugPlugin_l298) begin + execute_arbitration_flushIt = 1'b1; + end + end + end + + always @(*) begin + execute_arbitration_flushNext = 1'b0; + if(CsrPlugin_selfException_valid) begin + execute_arbitration_flushNext = 1'b1; + end + if(when_DebugPlugin_l295) begin + if(when_DebugPlugin_l298) begin + execute_arbitration_flushNext = 1'b1; + end + end + end + + always @(*) begin + memory_arbitration_haltItself = 1'b0; + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @(*) begin + memory_arbitration_removeIt = 1'b0; + if(BranchPlugin_branchExceptionPort_valid) begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed) begin + memory_arbitration_removeIt = 1'b1; + end + end + + assign memory_arbitration_flushIt = 1'b0; + always @(*) begin + memory_arbitration_flushNext = 1'b0; + if(BranchPlugin_branchExceptionPort_valid) begin + memory_arbitration_flushNext = 1'b1; + end + if(BranchPlugin_jumpInterface_valid) begin + memory_arbitration_flushNext = 1'b1; + end + end + + always @(*) begin + writeBack_arbitration_haltItself = 1'b0; + if(when_DBusCachedPlugin_l466) begin + writeBack_arbitration_haltItself = 1'b1; + end + end + + assign writeBack_arbitration_haltByOther = 1'b0; + always @(*) begin + writeBack_arbitration_removeIt = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid) begin + writeBack_arbitration_removeIt = 1'b1; + end + if(writeBack_arbitration_isFlushed) begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + always @(*) begin + writeBack_arbitration_flushIt = 1'b0; + if(DBusCachedPlugin_redoBranch_valid) begin + writeBack_arbitration_flushIt = 1'b1; + end + end + + always @(*) begin + writeBack_arbitration_flushNext = 1'b0; + if(DBusCachedPlugin_redoBranch_valid) begin + writeBack_arbitration_flushNext = 1'b1; + end + if(DBusCachedPlugin_exceptionBus_valid) begin + writeBack_arbitration_flushNext = 1'b1; + end + if(when_CsrPlugin_l1032) begin + writeBack_arbitration_flushNext = 1'b1; + end + if(when_CsrPlugin_l1077) begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @(*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(when_CsrPlugin_l935) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(when_CsrPlugin_l1032) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(when_CsrPlugin_l1077) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(when_DebugPlugin_l295) begin + if(when_DebugPlugin_l298) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + if(DebugPlugin_haltIt) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(when_DebugPlugin_l311) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + assign IBusCachedPlugin_forceNoDecodeCond = 1'b0; + always @(*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if(when_Fetcher_l243) begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + if(IBusCachedPlugin_injector_decodeInput_valid) begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @(*) begin + _zz_when_DBusCachedPlugin_l393 = 1'b0; + if(DebugPlugin_godmode) begin + _zz_when_DBusCachedPlugin_l393 = 1'b1; + end + end + + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; + assign CsrPlugin_inWfi = 1'b0; + always @(*) begin + CsrPlugin_thirdPartyWake = 1'b0; + if(DebugPlugin_haltIt) begin + CsrPlugin_thirdPartyWake = 1'b1; + end + end + + always @(*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(when_CsrPlugin_l1032) begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(when_CsrPlugin_l1077) begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1032) begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; + end + if(when_CsrPlugin_l1077) begin + case(switch_CsrPlugin_l1081) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + always @(*) begin + CsrPlugin_forceMachineWire = 1'b0; + if(DebugPlugin_godmode) begin + CsrPlugin_forceMachineWire = 1'b1; + end + end + + always @(*) begin + CsrPlugin_allowInterrupts = 1'b1; + if(when_DebugPlugin_l331) begin + CsrPlugin_allowInterrupts = 1'b0; + end + end + + always @(*) begin + CsrPlugin_allowException = 1'b1; + if(DebugPlugin_godmode) begin + CsrPlugin_allowException = 1'b0; + end + end + + always @(*) begin + CsrPlugin_allowEbreakException = 1'b1; + if(DebugPlugin_allowEBreak) begin + CsrPlugin_allowEbreakException = 1'b0; + end + end + + always @(*) begin + BranchPlugin_inDebugNoFetchFlag = 1'b0; + if(DebugPlugin_godmode) begin + BranchPlugin_inDebugNoFetchFlag = 1'b1; + end + end + + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (((IBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hf8000000) || ((IBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hfa000000)); + assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusCachedPlugin_mmuBus_busy = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (((DBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hf8000000) || ((DBusCachedPlugin_mmuBus_rsp_physicalAddress & (~ 32'h00ffffff)) == 32'hfa000000)); + assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusCachedPlugin_mmuBus_busy = 1'b0; + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}} != 3'b000); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[1]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[2]; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_4; + always @(*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid) begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid) begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); + always @(*) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + assign when_Fetcher_l134 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l134_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end + if(IBusCachedPlugin_jump_pcLoad_valid) begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + always @(*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid) begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid) begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + + assign when_Fetcher_l161 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @(*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_mmuBus_busy) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if(when_IBusCachedPlugin_l267) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; + end + end + + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = (IBusCachedPlugin_externalFlush || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if(IBusCachedPlugin_injector_decodeInput_valid) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + if(when_Fetcher_l323) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign when_Fetcher_l243 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign IBusCachedPlugin_iBusRsp_output_ready = ((1'b0 && (! IBusCachedPlugin_injector_decodeInput_valid)) || IBusCachedPlugin_injector_decodeInput_ready); + assign IBusCachedPlugin_injector_decodeInput_valid = _zz_IBusCachedPlugin_injector_decodeInput_valid; + assign IBusCachedPlugin_injector_decodeInput_payload_pc = _zz_IBusCachedPlugin_injector_decodeInput_payload_pc; + assign IBusCachedPlugin_injector_decodeInput_payload_rsp_error = _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error; + assign IBusCachedPlugin_injector_decodeInput_payload_rsp_inst = _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + assign IBusCachedPlugin_injector_decodeInput_payload_isRvc = _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc; + assign when_Fetcher_l323 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l332 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l332_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l332_2 = (! (! IBusCachedPlugin_injector_decodeInput_ready)); + assign when_Fetcher_l332_3 = (! execute_arbitration_isStuck); + assign when_Fetcher_l332_4 = (! memory_arbitration_isStuck); + assign when_Fetcher_l332_5 = (! writeBack_arbitration_isStuck); + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_5; + assign IBusCachedPlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); + always @(*) begin + decode_arbitration_isValid = IBusCachedPlugin_injector_decodeInput_valid; + case(switch_Fetcher_l365) + 3'b010 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b011 : begin + decode_arbitration_isValid = 1'b1; + end + default : begin + end + endcase + if(IBusCachedPlugin_forceNoDecodeCond) begin + decode_arbitration_isValid = 1'b0; + end + end + + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @(*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; + always @(*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(when_IBusCachedPlugin_l239) begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(when_IBusCachedPlugin_l244) begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(when_IBusCachedPlugin_l256) begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + always @(*) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(when_IBusCachedPlugin_l244) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(when_IBusCachedPlugin_l256) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); + always @(*) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l368) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l368 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign when_DBusCachedPlugin_l308 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; + assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD; + always @(*) begin + case(execute_DBusCachedPlugin_size) + 2'b00 : begin + _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; + end + endcase + end + + assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign dataCache_1_io_cpu_flush_payload_singleLine = (execute_INSTRUCTION[19 : 15] != 5'h0); + assign dataCache_1_io_cpu_flush_payload_lineId = _zz_io_cpu_flush_payload_lineId[5:0]; + assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); + assign when_DBusCachedPlugin_l350 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); + assign when_DBusCachedPlugin_l366 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); + assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = memory_MEMORY_VIRTUAL_ADDRESS; + assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + always @(*) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if(when_DBusCachedPlugin_l393) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; + end + end + + assign when_DBusCachedPlugin_l393 = (_zz_when_DBusCachedPlugin_l393 && (! dataCache_1_io_cpu_memory_isWrite)); + always @(*) begin + dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_arbitration_haltByOther) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b0; + end + end + + assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); + assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; + assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; + always @(*) begin + DBusCachedPlugin_redoBranch_valid = 1'b0; + if(when_DBusCachedPlugin_l446) begin + if(dataCache_1_io_cpu_redo) begin + DBusCachedPlugin_redoBranch_valid = 1'b1; + end + end + end + + assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; + always @(*) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + if(when_DBusCachedPlugin_l446) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_mmuException) begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_redo) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + end + end + end + + assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; + always @(*) begin + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(when_DBusCachedPlugin_l446) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; + end + if(dataCache_1_io_cpu_writeBack_mmuException) begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; + end + end + end + + assign when_DBusCachedPlugin_l446 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign when_DBusCachedPlugin_l466 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); + assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; + assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; + assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; + assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; + always @(*) begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; + writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; + writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; + end + + assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; + assign switch_Misc_l210 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; + end + + assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; + end + + always @(*) begin + case(switch_Misc_l210) + 2'b00 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; + end + 2'b01 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; + end + default : begin + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; + end + endcase + end + + assign when_DBusCachedPlugin_l492 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_decode_BRANCH_CTRL_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_BRANCH_CTRL_4 = ((decode_INSTRUCTION & 32'h00000018) == 32'h0); + assign _zz_decode_BRANCH_CTRL_5 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_BRANCH_CTRL_6 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_BRANCH_CTRL_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_decode_BRANCH_CTRL_8 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00100050); + assign _zz_decode_BRANCH_CTRL_2 = {(|{_zz_decode_BRANCH_CTRL_6,(_zz__zz_decode_BRANCH_CTRL_2 == _zz__zz_decode_BRANCH_CTRL_2_1)}),{(|(_zz__zz_decode_BRANCH_CTRL_2_2 == _zz__zz_decode_BRANCH_CTRL_2_3)),{(|_zz_decode_BRANCH_CTRL_8),{(|_zz__zz_decode_BRANCH_CTRL_2_4),{_zz__zz_decode_BRANCH_CTRL_2_5,{_zz__zz_decode_BRANCH_CTRL_2_8,_zz__zz_decode_BRANCH_CTRL_2_11}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_BRANCH_CTRL_2[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_BRANCH_CTRL_2[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_BRANCH_CTRL_2[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_BRANCH_CTRL_2[19 : 18]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_BRANCH_CTRL_2[22 : 21]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_BRANCH_CTRL_2[29 : 28]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; + assign _zz_decode_BRANCH_CTRL_9 = _zz_decode_BRANCH_CTRL_2[32 : 31]; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL_9; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_2) begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_2) begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_2) begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + AluBitwiseCtrlEnum_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + AluBitwiseCtrlEnum_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @(*) begin + case(execute_ALU_CTRL) + AluCtrlEnum_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; + end + AluCtrlEnum_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; + end + default : begin + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; + end + endcase + end + + always @(*) begin + case(decode_SRC1_CTRL) + Src1CtrlEnum_RS : begin + _zz_decode_SRC1_1 = _zz_decode_SRC1; + end + Src1CtrlEnum_PC_INCREMENT : begin + _zz_decode_SRC1_1 = {29'd0, _zz__zz_decode_SRC1_1}; + end + Src1CtrlEnum_IMU : begin + _zz_decode_SRC1_1 = {decode_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_decode_SRC1_1 = {27'd0, _zz__zz_decode_SRC1_1_1}; + end + endcase + end + + assign _zz_decode_SRC2_2 = decode_INSTRUCTION[31]; + always @(*) begin + _zz_decode_SRC2_3[19] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[18] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[17] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[16] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[15] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[14] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[13] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[12] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[11] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[10] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[9] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[8] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[7] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[6] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[5] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[4] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[3] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[2] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[1] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[0] = _zz_decode_SRC2_2; + end + + assign _zz_decode_SRC2_4 = _zz__zz_decode_SRC2_4[11]; + always @(*) begin + _zz_decode_SRC2_5[19] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[18] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[17] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[16] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[15] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[14] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[13] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[12] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[11] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[10] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[9] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[8] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[7] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[6] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[5] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[4] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[3] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[2] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[1] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[0] = _zz_decode_SRC2_4; + end + + always @(*) begin + case(decode_SRC2_CTRL) + Src2CtrlEnum_RS : begin + _zz_decode_SRC2_6 = _zz_decode_SRC2_1; + end + Src2CtrlEnum_IMI : begin + _zz_decode_SRC2_6 = {_zz_decode_SRC2_3,decode_INSTRUCTION[31 : 20]}; + end + Src2CtrlEnum_IMS : begin + _zz_decode_SRC2_6 = {_zz_decode_SRC2_5,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_decode_SRC2_6 = _zz_decode_SRC2; + end + endcase + end + + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == ShiftCtrlEnum_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; + _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; + _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; + _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; + _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; + _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; + _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; + _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; + _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; + _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; + _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; + _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; + _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; + _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; + _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; + _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; + _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; + _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; + _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; + _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; + _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; + _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; + _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; + _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; + _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; + _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; + _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; + _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; + _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; + _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; + _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; + _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; + end + end + + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); + assign when_MulPlugin_l65 = ((execute_arbitration_isValid && execute_IS_MUL) && (execute_MulPlugin_delayLogic_counter != 1'b1)); + assign when_MulPlugin_l70 = ((! execute_arbitration_isStuck) || execute_arbitration_isStuckByOthers); + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) + 2'b01 : begin + execute_MulPlugin_aSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_aSigned = 1'b1; + end + default : begin + execute_MulPlugin_aSigned = 1'b0; + end + endcase + end + + always @(*) begin + case(switch_MulPlugin_l87) + 2'b01 : begin + execute_MulPlugin_bSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_bSigned = 1'b0; + end + default : begin + execute_MulPlugin_bSigned = 1'b0; + end + endcase + end + + assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; + assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; + assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; + assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; + assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; + assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; + assign memory_MulDivIterativePlugin_frontendOk = 1'b1; + always @(*) begin + memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin + memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @(*) begin + memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; + if(when_MulDivIterativePlugin_l162) begin + memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == 6'h21); + assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement); + always @(*) begin + if(memory_MulDivIterativePlugin_div_counter_willOverflow) begin + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; + end else begin + memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_memory_MulDivIterativePlugin_div_counter_valueNext); + end + if(memory_MulDivIterativePlugin_div_counter_willClear) begin + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; + end + end + + assign when_MulDivIterativePlugin_l126 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); + assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted = memory_MulDivIterativePlugin_rs1[31 : 0]; + assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31]}; + assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator); + assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder : _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1); + assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); + assign _zz_memory_MulDivIterativePlugin_div_result = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_MulDivIterativePlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_MulDivIterativePlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_MulDivIterativePlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_MulDivIterativePlugin_rs1_1[31 : 0] = execute_RS1; + end + + always @(*) begin + CsrPlugin_privilege = 2'b11; + if(CsrPlugin_forceMachineWire) begin + CsrPlugin_privilege = 2'b11; + end + end + + assign _zz_when_CsrPlugin_l965 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l965_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l965_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(CsrPlugin_selfException_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(BranchPlugin_branchExceptionPort_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(DBusCachedPlugin_exceptionBus_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + end + if(writeBack_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign when_CsrPlugin_l922 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l922_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l922_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l922_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l935 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l959 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l965 = ((_zz_when_CsrPlugin_l965 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l965_1 = ((_zz_when_CsrPlugin_l965_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l965_2 = ((_zz_when_CsrPlugin_l965_2 && 1'b1) && (! 1'b0)); + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_lastStageWasWfi = 1'b0; + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + assign when_CsrPlugin_l993 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l993_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l993_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l998 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(when_CsrPlugin_l1004) begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException) begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign when_CsrPlugin_l1004 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @(*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException) begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @(*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException) begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @(*) begin + CsrPlugin_xtvec_mode = 2'bxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign when_CsrPlugin_l1032 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1077 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == EnvCtrlEnum_XRET)); + assign switch_CsrPlugin_l1081 = writeBack_INSTRUCTION[29 : 28]; + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1129 = (|{(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == EnvCtrlEnum_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == EnvCtrlEnum_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_XRET))}}); + assign execute_CsrPlugin_blockedBySideEffects = ((|{writeBack_arbitration_isValid,memory_arbitration_isValid}) || 1'b0); + always @(*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_3860) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_769) begin + if(execute_CSR_WRITE_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_768) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_833) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_832) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_835) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1310) begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(when_CsrPlugin_l1315) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @(*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if(when_CsrPlugin_l1149) begin + if(when_CsrPlugin_l1150) begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @(*) begin + CsrPlugin_selfException_valid = 1'b0; + if(when_CsrPlugin_l1142) begin + CsrPlugin_selfException_valid = 1'b1; + end + if(when_CsrPlugin_l1157) begin + CsrPlugin_selfException_valid = 1'b1; + end + if(when_CsrPlugin_l1167) begin + CsrPlugin_selfException_valid = 1'b1; + end + end + + always @(*) begin + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(when_CsrPlugin_l1142) begin + CsrPlugin_selfException_payload_code = 4'b0010; + end + if(when_CsrPlugin_l1157) begin + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = 4'b1000; + end + default : begin + CsrPlugin_selfException_payload_code = 4'b1011; + end + endcase + end + if(when_CsrPlugin_l1167) begin + CsrPlugin_selfException_payload_code = 4'b0011; + end + end + + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + assign when_CsrPlugin_l1142 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign when_CsrPlugin_l1149 = (execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_XRET)); + assign when_CsrPlugin_l1150 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1157 = (execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_ECALL)); + assign when_CsrPlugin_l1167 = ((execute_arbitration_isValid && (execute_ENV_CTRL == EnvCtrlEnum_EBREAK)) && CsrPlugin_allowEbreakException); + always @(*) begin + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(when_CsrPlugin_l1310) begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @(*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(when_CsrPlugin_l1310) begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l210_1 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l210_1) + 1'b0 : begin + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; + end + default : begin + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1189 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1193 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign switch_Misc_l210_2 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l210_2) + 3'b000 : begin + _zz_execute_BRANCH_DO = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_DO = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_DO = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_DO = execute_SRC_LESS; + end + endcase + end + + always @(*) begin + case(execute_BRANCH_CTRL) + BranchCtrlEnum_INC : begin + _zz_execute_BRANCH_DO_1 = 1'b0; + end + BranchCtrlEnum_JAL : begin + _zz_execute_BRANCH_DO_1 = 1'b1; + end + BranchCtrlEnum_JALR : begin + _zz_execute_BRANCH_DO_1 = 1'b1; + end + default : begin + _zz_execute_BRANCH_DO_1 = _zz_execute_BRANCH_DO; + end + endcase + end + + assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == BranchCtrlEnum_JALR) ? execute_RS1 : execute_PC); + assign _zz_execute_BranchPlugin_branch_src2 = _zz__zz_execute_BranchPlugin_branch_src2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + assign _zz_execute_BranchPlugin_branch_src2_2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[19] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[18] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[17] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[16] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[15] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[14] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[13] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[12] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[11] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; + end + + always @(*) begin + case(execute_BRANCH_CTRL) + BranchCtrlEnum_JAL : begin + _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_1,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + end + BranchCtrlEnum_JALR : begin + _zz_execute_BranchPlugin_branch_src2_6 = {_zz_execute_BranchPlugin_branch_src2_3,execute_INSTRUCTION[31 : 20]}; + end + default : begin + _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + end + endcase + end + + assign execute_BranchPlugin_branch_src2 = _zz_execute_BranchPlugin_branch_src2_6; + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; + assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; + assign when_DebugPlugin_l225 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)); + assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak)); + always @(*) begin + debug_bus_cmd_ready = 1'b1; + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l267) + 6'h01 : begin + if(debug_bus_cmd_payload_wr) begin + debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; + end + end + default : begin + end + endcase + end + end + + always @(*) begin + debug_bus_rsp_data = DebugPlugin_busReadDataReg; + if(when_DebugPlugin_l244) begin + debug_bus_rsp_data[0] = DebugPlugin_resetIt; + debug_bus_rsp_data[1] = DebugPlugin_haltIt; + debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; + debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; + debug_bus_rsp_data[4] = DebugPlugin_stepIt; + end + end + + assign when_DebugPlugin_l244 = (! _zz_when_DebugPlugin_l244); + always @(*) begin + IBusCachedPlugin_injectionPort_valid = 1'b0; + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l267) + 6'h01 : begin + if(debug_bus_cmd_payload_wr) begin + IBusCachedPlugin_injectionPort_valid = 1'b1; + end + end + default : begin + end + endcase + end + end + + assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; + assign switch_DebugPlugin_l267 = debug_bus_cmd_payload_address[7 : 2]; + assign when_DebugPlugin_l271 = debug_bus_cmd_payload_data[16]; + assign when_DebugPlugin_l271_1 = debug_bus_cmd_payload_data[24]; + assign when_DebugPlugin_l272 = debug_bus_cmd_payload_data[17]; + assign when_DebugPlugin_l272_1 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l273 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l274 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l275 = debug_bus_cmd_payload_data[18]; + assign when_DebugPlugin_l275_1 = debug_bus_cmd_payload_data[26]; + assign when_DebugPlugin_l295 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign when_DebugPlugin_l298 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign when_DebugPlugin_l311 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign when_DebugPlugin_l331 = (DebugPlugin_haltIt || DebugPlugin_stepIt); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_14 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_16 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_17 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_28 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_31 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_33 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_34 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_35 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_37 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_38 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_39 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; + assign when_Pipeline_l124_40 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_59 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_60 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck); + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + always @(*) begin + IBusCachedPlugin_injectionPort_ready = 1'b0; + case(switch_Fetcher_l365) + 3'b100 : begin + IBusCachedPlugin_injectionPort_ready = 1'b1; + end + default : begin + end + endcase + end + + assign when_Fetcher_l381 = (! decode_arbitration_isStuck); + assign when_Fetcher_l401 = (switch_Fetcher_l365 != 3'b000); + assign when_CsrPlugin_l1277 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1277_9 = (! execute_arbitration_isStuck); + assign switch_CsrPlugin_l723 = CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_CsrPlugin_csrMapping_readDataInit[12 : 11] = CsrPlugin_mstatus_MPP; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_1 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_1[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_1[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_1[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_2[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_2[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_2[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; + if(execute_CsrPlugin_csr_773) begin + _zz_CsrPlugin_csrMapping_readDataInit_3[31 : 2] = CsrPlugin_mtvec_base; + _zz_CsrPlugin_csrMapping_readDataInit_3[1 : 0] = CsrPlugin_mtvec_mode; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_4[31 : 0] = CsrPlugin_mepc; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; + if(execute_CsrPlugin_csr_832) begin + _zz_CsrPlugin_csrMapping_readDataInit_5[31 : 0] = CsrPlugin_mscratch; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_6[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_7[31 : 0] = CsrPlugin_mtval; + end + end + + assign CsrPlugin_csrMapping_readDataInit = ((((32'h0 | _zz_CsrPlugin_csrMapping_readDataInit) | (_zz_CsrPlugin_csrMapping_readDataInit_1 | _zz_CsrPlugin_csrMapping_readDataInit_2)) | ((_zz_CsrPlugin_csrMapping_readDataInit_3 | _zz_CsrPlugin_csrMapping_readDataInit_4) | (_zz_CsrPlugin_csrMapping_readDataInit_5 | _zz_CsrPlugin_csrMapping_readDataInit_6))) | _zz_CsrPlugin_csrMapping_readDataInit_7); + assign when_CsrPlugin_l1310 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1315 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + IBusCachedPlugin_fetchPc_pcReg <= 32'hf9000000; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; + _zz_IBusCachedPlugin_injector_decodeInput_valid <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + dBus_rsp_regNext_valid <= 1'b0; + DBusCachedPlugin_rspCounter <= 32'h0; + _zz_2 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + memory_MulDivIterativePlugin_div_counter_value <= 6'h0; + CsrPlugin_misa_base <= 2'b01; + CsrPlugin_misa_extensions <= 26'h0041101; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_mcycle <= 64'h0; + CsrPlugin_minstret <= 64'h0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + switch_Fetcher_l365 <= 3'b000; + end else begin + if(IBusCachedPlugin_fetchPc_correction) begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_output_fire) begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if(when_Fetcher_l134) begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_output_fire_1) begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(when_Fetcher_l134_1) begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(when_Fetcher_l161) begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + end + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + end + if(decode_arbitration_removeIt) begin + _zz_IBusCachedPlugin_injector_decodeInput_valid <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_output_ready) begin + _zz_IBusCachedPlugin_injector_decodeInput_valid <= (IBusCachedPlugin_iBusRsp_output_valid && (! IBusCachedPlugin_externalFlush)); + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if(when_Fetcher_l332) begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(when_Fetcher_l332_1) begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(when_Fetcher_l332_2) begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(when_Fetcher_l332_3) begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(when_Fetcher_l332_4) begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; + end + if(when_Fetcher_l332_5) begin + IBusCachedPlugin_injector_nextPcCalc_valids_5 <= IBusCachedPlugin_injector_nextPcCalc_valids_4; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; + end + if(iBus_rsp_valid) begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + end + if(dataCache_1_io_mem_cmd_valid) begin + dataCache_1_io_mem_cmd_rValid <= 1'b1; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_rValid <= 1'b0; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + end + dBus_rsp_regNext_valid <= dBus_rsp_valid; + if(dBus_rsp_valid) begin + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); + end + _zz_2 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring) begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(when_CsrPlugin_l922) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if(when_CsrPlugin_l922_1) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if(when_CsrPlugin_l922_2) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if(when_CsrPlugin_l922_3) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(when_CsrPlugin_l959) begin + if(when_CsrPlugin_l965) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(when_CsrPlugin_l965_1) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(when_CsrPlugin_l965_2) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l993) begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if(when_CsrPlugin_l993_1) begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if(when_CsrPlugin_l993_2) begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(when_CsrPlugin_l998) begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump) begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(when_CsrPlugin_l1032) begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(when_CsrPlugin_l1077) begin + case(switch_CsrPlugin_l1081) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l965_2,{_zz_when_CsrPlugin_l965_1,_zz_when_CsrPlugin_l965}} != 3'b000) || CsrPlugin_thirdPartyWake); + if(when_Pipeline_l151) begin + execute_arbitration_isValid <= 1'b0; + end + if(when_Pipeline_l154) begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(when_Pipeline_l151_1) begin + memory_arbitration_isValid <= 1'b0; + end + if(when_Pipeline_l154_1) begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(when_Pipeline_l151_2) begin + writeBack_arbitration_isValid <= 1'b0; + end + if(when_Pipeline_l154_2) begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(switch_Fetcher_l365) + 3'b000 : begin + if(IBusCachedPlugin_injectionPort_valid) begin + switch_Fetcher_l365 <= 3'b001; + end + end + 3'b001 : begin + switch_Fetcher_l365 <= 3'b010; + end + 3'b010 : begin + switch_Fetcher_l365 <= 3'b011; + end + 3'b011 : begin + if(when_Fetcher_l381) begin + switch_Fetcher_l365 <= 3'b100; + end + end + 3'b100 : begin + switch_Fetcher_l365 <= 3'b000; + end + default : begin + end + endcase + if(execute_CsrPlugin_csr_769) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30]; + CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0]; + end + end + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; + case(switch_CsrPlugin_l723) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b11; + end + default : begin + end + endcase + end + end + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; + end + end + end + end + + always @(posedge io_systemClk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_output_ready) begin + _zz_IBusCachedPlugin_injector_decodeInput_payload_pc <= IBusCachedPlugin_iBusRsp_output_payload_pc; + _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error <= IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst <= IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc <= IBusCachedPlugin_iBusRsp_output_payload_isRvc; + end + if(IBusCachedPlugin_injector_decodeInput_ready) begin + IBusCachedPlugin_injector_formal_rawInDecode <= IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(dataCache_1_io_mem_cmd_ready) begin + dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; + dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + dBus_rsp_regNext_payload_last <= dBus_rsp_payload_last; + dBus_rsp_regNext_payload_data <= dBus_rsp_payload_data; + dBus_rsp_regNext_payload_error <= dBus_rsp_payload_error; + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + execute_MulPlugin_delayLogic_counter <= (execute_MulPlugin_delayLogic_counter + 1'b1); + if(when_MulPlugin_l70) begin + execute_MulPlugin_delayLogic_counter <= 1'b0; + end + execute_MulPlugin_withOuputBuffer_mul_ll <= (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + execute_MulPlugin_withOuputBuffer_mul_lh <= ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + execute_MulPlugin_withOuputBuffer_mul_hl <= ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + execute_MulPlugin_withOuputBuffer_mul_hh <= ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + if(when_MulDivIterativePlugin_l126) begin + memory_MulDivIterativePlugin_div_done <= 1'b1; + end + if(when_MulDivIterativePlugin_l126_1) begin + memory_MulDivIterativePlugin_div_done <= 1'b0; + end + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin + memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; + memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; + if(when_MulDivIterativePlugin_l151) begin + memory_MulDivIterativePlugin_div_result <= _zz_memory_MulDivIterativePlugin_div_result_1[31:0]; + end + end + end + if(when_MulDivIterativePlugin_l162) begin + memory_MulDivIterativePlugin_accumulator <= 65'h0; + memory_MulDivIterativePlugin_rs1 <= ((_zz_memory_MulDivIterativePlugin_rs1 ? (~ _zz_memory_MulDivIterativePlugin_rs1_1) : _zz_memory_MulDivIterativePlugin_rs1_1) + _zz_memory_MulDivIterativePlugin_rs1_2); + memory_MulDivIterativePlugin_rs2 <= ((_zz_memory_MulDivIterativePlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_MulDivIterativePlugin_rs2_1); + memory_MulDivIterativePlugin_div_needRevert <= ((_zz_memory_MulDivIterativePlugin_rs1 ^ (_zz_memory_MulDivIterativePlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(CsrPlugin_selfException_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + end + if(BranchPlugin_branchExceptionPort_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + end + if(DBusCachedPlugin_exceptionBus_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(when_CsrPlugin_l959) begin + if(when_CsrPlugin_l965) begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(when_CsrPlugin_l965_1) begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(when_CsrPlugin_l965_2) begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(when_CsrPlugin_l1032) begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException) begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if(when_Pipeline_l124) begin + decode_to_execute_PC <= _zz_decode_SRC2; + end + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= execute_PC; + end + if(when_Pipeline_l124_2) begin + memory_to_writeBack_PC <= memory_PC; + end + if(when_Pipeline_l124_3) begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if(when_Pipeline_l124_4) begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if(when_Pipeline_l124_5) begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if(when_Pipeline_l124_6) begin + decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; + end + if(when_Pipeline_l124_7) begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if(when_Pipeline_l124_8) begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; + end + if(when_Pipeline_l124_9) begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if(when_Pipeline_l124_10) begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if(when_Pipeline_l124_11) begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if(when_Pipeline_l124_12) begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if(when_Pipeline_l124_13) begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if(when_Pipeline_l124_14) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; + end + if(when_Pipeline_l124_15) begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if(when_Pipeline_l124_16) begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if(when_Pipeline_l124_17) begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if(when_Pipeline_l124_18) begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if(when_Pipeline_l124_19) begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if(when_Pipeline_l124_20) begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if(when_Pipeline_l124_21) begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if(when_Pipeline_l124_22) begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if(when_Pipeline_l124_23) begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if(when_Pipeline_l124_24) begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if(when_Pipeline_l124_25) begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if(when_Pipeline_l124_26) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; + end + if(when_Pipeline_l124_27) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; + end + if(when_Pipeline_l124_28) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; + end + if(when_Pipeline_l124_29) begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if(when_Pipeline_l124_30) begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if(when_Pipeline_l124_31) begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if(when_Pipeline_l124_32) begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if(when_Pipeline_l124_33) begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if(when_Pipeline_l124_34) begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if(when_Pipeline_l124_35) begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if(when_Pipeline_l124_36) begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if(when_Pipeline_l124_37) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; + end + if(when_Pipeline_l124_38) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; + end + if(when_Pipeline_l124_39) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; + end + if(when_Pipeline_l124_40) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; + end + if(when_Pipeline_l124_41) begin + decode_to_execute_RS1 <= _zz_decode_SRC1; + end + if(when_Pipeline_l124_42) begin + decode_to_execute_RS2 <= _zz_decode_SRC2_1; + end + if(when_Pipeline_l124_43) begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if(when_Pipeline_l124_44) begin + decode_to_execute_SRC1 <= decode_SRC1; + end + if(when_Pipeline_l124_45) begin + decode_to_execute_SRC2 <= decode_SRC2; + end + if(when_Pipeline_l124_46) begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if(when_Pipeline_l124_47) begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if(when_Pipeline_l124_48) begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if(when_Pipeline_l124_49) begin + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; + end + if(when_Pipeline_l124_50) begin + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; + end + if(when_Pipeline_l124_51) begin + execute_to_memory_MEMORY_VIRTUAL_ADDRESS <= execute_MEMORY_VIRTUAL_ADDRESS; + end + if(when_Pipeline_l124_52) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; + end + if(when_Pipeline_l124_53) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; + end + if(when_Pipeline_l124_54) begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if(when_Pipeline_l124_55) begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if(when_Pipeline_l124_56) begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if(when_Pipeline_l124_57) begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if(when_Pipeline_l124_58) begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if(when_Pipeline_l124_59) begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if(when_Pipeline_l124_60) begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if(when_Pipeline_l124_61) begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if(when_Pipeline_l124_62) begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if(when_Fetcher_l401) begin + _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst <= IBusCachedPlugin_injectionPort_payload; + end + if(when_CsrPlugin_l1277) begin + execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); + end + if(when_CsrPlugin_l1277_1) begin + execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); + end + if(when_CsrPlugin_l1277_2) begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if(when_CsrPlugin_l1277_3) begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if(when_CsrPlugin_l1277_4) begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if(when_CsrPlugin_l1277_5) begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if(when_CsrPlugin_l1277_6) begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if(when_CsrPlugin_l1277_7) begin + execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); + end + if(when_CsrPlugin_l1277_8) begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if(when_CsrPlugin_l1277_9) begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; + end + end + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; + end + end + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; + end + end + if(execute_CsrPlugin_csr_832) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; + end + end + end + + always @(posedge io_systemClk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready) begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); + if(writeBack_arbitration_isValid) begin + DebugPlugin_busReadDataReg <= _zz_decode_RS2_2; + end + _zz_when_DebugPlugin_l244 <= debug_bus_cmd_payload_address[2]; + if(when_DebugPlugin_l295) begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @(posedge io_systemClk) begin + if(debugCd_logic_outputReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_debugUsed <= 1'b0; + DebugPlugin_disableEbreak <= 1'b0; + end else begin + if(when_DebugPlugin_l225) begin + DebugPlugin_godmode <= 1'b1; + end + if(debug_bus_cmd_valid) begin + DebugPlugin_debugUsed <= 1'b1; + end + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l267) + 6'h0 : begin + if(debug_bus_cmd_payload_wr) begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(when_DebugPlugin_l271) begin + DebugPlugin_resetIt <= 1'b1; + end + if(when_DebugPlugin_l271_1) begin + DebugPlugin_resetIt <= 1'b0; + end + if(when_DebugPlugin_l272) begin + DebugPlugin_haltIt <= 1'b1; + end + if(when_DebugPlugin_l272_1) begin + DebugPlugin_haltIt <= 1'b0; + end + if(when_DebugPlugin_l273) begin + DebugPlugin_haltedByBreak <= 1'b0; + end + if(when_DebugPlugin_l274) begin + DebugPlugin_godmode <= 1'b0; + end + if(when_DebugPlugin_l275) begin + DebugPlugin_disableEbreak <= 1'b1; + end + if(when_DebugPlugin_l275_1) begin + DebugPlugin_disableEbreak <= 1'b0; + end + end + end + default : begin + end + endcase + end + if(when_DebugPlugin_l295) begin + if(when_DebugPlugin_l298) begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; + end + end + if(when_DebugPlugin_l311) begin + if(decode_arbitration_isValid) begin + DebugPlugin_haltIt <= 1'b1; + end + end + end + end + + +endmodule + +module BufferCC_3 ( + input io_dataIn, + output io_dataOut, + input io_systemClk, + input debugCd_logic_outputReset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge io_systemClk or posedge debugCd_logic_outputReset) begin + if(debugCd_logic_outputReset) begin + buffers_0 <= 1'b1; + buffers_1 <= 1'b1; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module BufferCC_2 ( + input io_dataIn, + output io_dataOut, + input io_systemClk, + input io_asyncReset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge io_systemClk or posedge io_asyncReset) begin + if(io_asyncReset) begin + buffers_0 <= 1'b1; + buffers_1 <= 1'b1; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module StreamFifo_3 ( + input io_push_valid, + output io_push_ready, + input [7:0] io_push_payload_data, + output io_pop_valid, + input io_pop_ready, + output [7:0] io_pop_payload_data, + input io_flush, + output [8:0] io_occupancy, + output [8:0] io_availability, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [7:0] _zz_logic_ram_port0; + wire [7:0] _zz_logic_pushPtr_valueNext; + wire [0:0] _zz_logic_pushPtr_valueNext_1; + wire [7:0] _zz_logic_popPtr_valueNext; + wire [0:0] _zz_logic_popPtr_valueNext_1; + wire _zz_logic_ram_port; + wire _zz_io_pop_payload_data; + wire [7:0] _zz_io_availability; + reg _zz_1; + reg logic_pushPtr_willIncrement; + reg logic_pushPtr_willClear; + reg [7:0] logic_pushPtr_valueNext; + reg [7:0] logic_pushPtr_value; + wire logic_pushPtr_willOverflowIfInc; + wire logic_pushPtr_willOverflow; + reg logic_popPtr_willIncrement; + reg logic_popPtr_willClear; + reg [7:0] logic_popPtr_valueNext; + reg [7:0] logic_popPtr_value; + wire logic_popPtr_willOverflowIfInc; + wire logic_popPtr_willOverflow; + wire logic_ptrMatch; + reg logic_risingOccupancy; + wire logic_pushing; + wire logic_popping; + wire logic_empty; + wire logic_full; + reg _zz_io_pop_valid; + wire when_Stream_l1037; + wire [7:0] logic_ptrDif; + reg [7:0] logic_ram [0:255]; + + assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; + assign _zz_logic_pushPtr_valueNext = {7'd0, _zz_logic_pushPtr_valueNext_1}; + assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; + assign _zz_logic_popPtr_valueNext = {7'd0, _zz_logic_popPtr_valueNext_1}; + assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); + assign _zz_io_pop_payload_data = 1'b1; + always @(posedge io_systemClk) begin + if(_zz_io_pop_payload_data) begin + _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_1) begin + logic_ram[logic_pushPtr_value] <= io_push_payload_data; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_pushing) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willIncrement = 1'b0; + if(logic_pushing) begin + logic_pushPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willClear = 1'b0; + if(io_flush) begin + logic_pushPtr_willClear = 1'b1; + end + end + + assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 8'hff); + assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); + always @(*) begin + logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); + if(logic_pushPtr_willClear) begin + logic_pushPtr_valueNext = 8'h0; + end + end + + always @(*) begin + logic_popPtr_willIncrement = 1'b0; + if(logic_popping) begin + logic_popPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_popPtr_willClear = 1'b0; + if(io_flush) begin + logic_popPtr_willClear = 1'b1; + end + end + + assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 8'hff); + assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); + always @(*) begin + logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); + if(logic_popPtr_willClear) begin + logic_popPtr_valueNext = 8'h0; + end + end + + assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); + assign logic_pushing = (io_push_valid && io_push_ready); + assign logic_popping = (io_pop_valid && io_pop_ready); + assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); + assign logic_full = (logic_ptrMatch && logic_risingOccupancy); + assign io_push_ready = (! logic_full); + assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); + assign io_pop_payload_data = _zz_logic_ram_port0[7 : 0]; + assign when_Stream_l1037 = (logic_pushing != logic_popping); + assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); + assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; + assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + logic_pushPtr_value <= 8'h0; + logic_popPtr_value <= 8'h0; + logic_risingOccupancy <= 1'b0; + _zz_io_pop_valid <= 1'b0; + end else begin + logic_pushPtr_value <= logic_pushPtr_valueNext; + logic_popPtr_value <= logic_popPtr_valueNext; + _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); + if(when_Stream_l1037) begin + logic_risingOccupancy <= logic_pushing; + end + if(io_flush) begin + logic_risingOccupancy <= 1'b0; + end + end + end + + +endmodule + +module StreamFifo_2 ( + input io_push_valid, + output io_push_ready, + input io_push_payload_kind, + input io_push_payload_read, + input io_push_payload_write, + input [7:0] io_push_payload_data, + output io_pop_valid, + input io_pop_ready, + output io_pop_payload_kind, + output io_pop_payload_read, + output io_pop_payload_write, + output [7:0] io_pop_payload_data, + input io_flush, + output [8:0] io_occupancy, + output [8:0] io_availability, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [10:0] _zz_logic_ram_port0; + wire [7:0] _zz_logic_pushPtr_valueNext; + wire [0:0] _zz_logic_pushPtr_valueNext_1; + wire [7:0] _zz_logic_popPtr_valueNext; + wire [0:0] _zz_logic_popPtr_valueNext_1; + wire _zz_logic_ram_port; + wire _zz__zz_io_pop_payload_kind; + wire [10:0] _zz_logic_ram_port_1; + wire [7:0] _zz_io_availability; + reg _zz_1; + reg logic_pushPtr_willIncrement; + reg logic_pushPtr_willClear; + reg [7:0] logic_pushPtr_valueNext; + reg [7:0] logic_pushPtr_value; + wire logic_pushPtr_willOverflowIfInc; + wire logic_pushPtr_willOverflow; + reg logic_popPtr_willIncrement; + reg logic_popPtr_willClear; + reg [7:0] logic_popPtr_valueNext; + reg [7:0] logic_popPtr_value; + wire logic_popPtr_willOverflowIfInc; + wire logic_popPtr_willOverflow; + wire logic_ptrMatch; + reg logic_risingOccupancy; + wire logic_pushing; + wire logic_popping; + wire logic_empty; + wire logic_full; + reg _zz_io_pop_valid; + wire [10:0] _zz_io_pop_payload_kind; + wire when_Stream_l1037; + wire [7:0] logic_ptrDif; + reg [10:0] logic_ram [0:255]; + + assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; + assign _zz_logic_pushPtr_valueNext = {7'd0, _zz_logic_pushPtr_valueNext_1}; + assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; + assign _zz_logic_popPtr_valueNext = {7'd0, _zz_logic_popPtr_valueNext_1}; + assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); + assign _zz__zz_io_pop_payload_kind = 1'b1; + assign _zz_logic_ram_port_1 = {io_push_payload_data,{io_push_payload_write,{io_push_payload_read,io_push_payload_kind}}}; + always @(posedge io_systemClk) begin + if(_zz__zz_io_pop_payload_kind) begin + _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_1) begin + logic_ram[logic_pushPtr_value] <= _zz_logic_ram_port_1; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_pushing) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willIncrement = 1'b0; + if(logic_pushing) begin + logic_pushPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willClear = 1'b0; + if(io_flush) begin + logic_pushPtr_willClear = 1'b1; + end + end + + assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 8'hff); + assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); + always @(*) begin + logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); + if(logic_pushPtr_willClear) begin + logic_pushPtr_valueNext = 8'h0; + end + end + + always @(*) begin + logic_popPtr_willIncrement = 1'b0; + if(logic_popping) begin + logic_popPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_popPtr_willClear = 1'b0; + if(io_flush) begin + logic_popPtr_willClear = 1'b1; + end + end + + assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 8'hff); + assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); + always @(*) begin + logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); + if(logic_popPtr_willClear) begin + logic_popPtr_valueNext = 8'h0; + end + end + + assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); + assign logic_pushing = (io_push_valid && io_push_ready); + assign logic_popping = (io_pop_valid && io_pop_ready); + assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); + assign logic_full = (logic_ptrMatch && logic_risingOccupancy); + assign io_push_ready = (! logic_full); + assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); + assign _zz_io_pop_payload_kind = _zz_logic_ram_port0; + assign io_pop_payload_kind = _zz_io_pop_payload_kind[0]; + assign io_pop_payload_read = _zz_io_pop_payload_kind[1]; + assign io_pop_payload_write = _zz_io_pop_payload_kind[2]; + assign io_pop_payload_data = _zz_io_pop_payload_kind[10 : 3]; + assign when_Stream_l1037 = (logic_pushing != logic_popping); + assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); + assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; + assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + logic_pushPtr_value <= 8'h0; + logic_popPtr_value <= 8'h0; + logic_risingOccupancy <= 1'b0; + _zz_io_pop_valid <= 1'b0; + end else begin + logic_pushPtr_value <= logic_pushPtr_valueNext; + logic_popPtr_value <= logic_popPtr_valueNext; + _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); + if(when_Stream_l1037) begin + logic_risingOccupancy <= logic_pushing; + end + if(io_flush) begin + logic_risingOccupancy <= 1'b0; + end + end + end + + +endmodule + +module TopLevel ( + input io_config_kind_cpol, + input io_config_kind_cpha, + input [11:0] io_config_sclkToogle, + input [1:0] io_config_mod, + input [0:0] io_config_ss_activeHigh, + input [11:0] io_config_ss_setup, + input [11:0] io_config_ss_hold, + input [11:0] io_config_ss_disable, + input io_cmd_valid, + output reg io_cmd_ready, + input io_cmd_payload_kind, + input io_cmd_payload_read, + input io_cmd_payload_write, + input [7:0] io_cmd_payload_data, + output io_rsp_valid, + output [7:0] io_rsp_payload_data, + output [0:0] io_spi_sclk_write, + output reg io_spi_data_0_writeEnable, + input [0:0] io_spi_data_0_read, + output reg [0:0] io_spi_data_0_write, + output reg io_spi_data_1_writeEnable, + input [0:0] io_spi_data_1_read, + output reg [0:0] io_spi_data_1_write, + output reg io_spi_data_2_writeEnable, + input [0:0] io_spi_data_2_read, + output reg [0:0] io_spi_data_2_write, + output reg io_spi_data_3_writeEnable, + input [0:0] io_spi_data_3_read, + output reg [0:0] io_spi_data_3_write, + output [0:0] io_spi_ss, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [0:0] _zz_outputPhy_dataWrite_3; + wire [2:0] _zz_outputPhy_dataWrite_4; + wire [2:0] _zz_outputPhy_dataWrite_5; + reg [1:0] _zz_outputPhy_dataWrite_6; + wire [1:0] _zz_outputPhy_dataWrite_7; + wire [2:0] _zz_outputPhy_dataWrite_8; + reg [3:0] _zz_outputPhy_dataWrite_9; + wire [0:0] _zz_outputPhy_dataWrite_10; + wire [2:0] _zz_outputPhy_dataWrite_11; + wire [3:0] _zz_inputPhy_dataRead; + wire [3:0] _zz_inputPhy_dataRead_1; + wire [3:0] _zz_inputPhy_dataRead_2; + wire [3:0] _zz_inputPhy_dataRead_3; + wire [3:0] _zz_inputPhy_dataRead_4; + wire [3:0] _zz_inputPhy_dataRead_5; + wire [3:0] _zz_inputPhy_dataRead_6; + wire [8:0] _zz_inputPhy_bufferNext; + wire [10:0] _zz_inputPhy_bufferNext_1; + reg [11:0] timer_counter; + reg timer_reset; + wire timer_ss_setupHit; + wire timer_ss_holdHit; + wire timer_ss_disableHit; + wire timer_sclkToogleHit; + reg fsm_state; + reg [2:0] fsm_counter; + reg [2:0] _zz_fsm_counterPlus; + wire [2:0] fsm_counterPlus; + reg fsm_fastRate; + reg fsm_isDdr; + reg [2:0] fsm_counterMax; + reg fsm_lateSampling; + reg fsm_readFill; + reg fsm_readDone; + reg [0:0] fsm_ss; + wire when_SpiXdrMasterCtrl_l739; + wire when_SpiXdrMasterCtrl_l742; + wire when_SpiXdrMasterCtrl_l749; + wire when_SpiXdrMasterCtrl_l751; + wire when_SpiXdrMasterCtrl_l758; + wire when_SpiXdrMasterCtrl_l764; + wire when_SpiXdrMasterCtrl_l781; + reg [0:0] outputPhy_sclkWrite; + wire [0:0] _zz_io_spi_sclk_write; + wire when_SpiXdrMasterCtrl_l796; + reg [3:0] outputPhy_dataWrite; + reg [2:0] outputPhy_widthSel; + reg [2:0] outputPhy_offset; + wire [7:0] _zz_outputPhy_dataWrite; + wire [7:0] _zz_outputPhy_dataWrite_1; + wire [7:0] _zz_outputPhy_dataWrite_2; + wire when_SpiXdrMasterCtrl_l839; + wire when_SpiXdrMasterCtrl_l839_1; + reg [1:0] io_config_mod_delay_1; + reg [1:0] inputPhy_mod; + reg fsm_readFill_delay_1; + reg inputPhy_readFill; + reg fsm_readDone_delay_1; + reg inputPhy_readDone; + reg [6:0] inputPhy_buffer; + reg [7:0] inputPhy_bufferNext; + reg [2:0] inputPhy_widthSel; + wire [3:0] inputPhy_dataWrite; + reg [3:0] inputPhy_dataRead; + reg fsm_state_delay_1; + reg fsm_state_delay_2; + wire when_SpiXdrMasterCtrl_l861; + reg [3:0] inputPhy_dataReadBuffer; + + assign _zz_outputPhy_dataWrite_4 = (_zz_outputPhy_dataWrite_5 >>> 0); + assign _zz_outputPhy_dataWrite_5 = (outputPhy_offset - fsm_counter); + assign _zz_outputPhy_dataWrite_7 = (_zz_outputPhy_dataWrite_8 >>> 1); + assign _zz_outputPhy_dataWrite_8 = (outputPhy_offset - fsm_counter); + assign _zz_outputPhy_dataWrite_10 = (_zz_outputPhy_dataWrite_11 >>> 2); + assign _zz_outputPhy_dataWrite_11 = (outputPhy_offset - fsm_counter); + assign _zz_inputPhy_dataRead = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_1 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_2 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_3 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_4 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_5 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_6 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[1 : 0]}; + assign _zz_inputPhy_bufferNext_1 = {inputPhy_buffer,inputPhy_dataRead[3 : 0]}; + always @(*) begin + case(_zz_outputPhy_dataWrite_4) + 3'b000 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[0 : 0]; + 3'b001 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[1 : 1]; + 3'b010 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[2 : 2]; + 3'b011 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[3 : 3]; + 3'b100 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[4 : 4]; + 3'b101 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[5 : 5]; + 3'b110 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[6 : 6]; + default : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[7 : 7]; + endcase + end + + always @(*) begin + case(_zz_outputPhy_dataWrite_7) + 2'b00 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[1 : 0]; + 2'b01 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[3 : 2]; + 2'b10 : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[5 : 4]; + default : _zz_outputPhy_dataWrite_6 = _zz_outputPhy_dataWrite_1[7 : 6]; + endcase + end + + always @(*) begin + case(_zz_outputPhy_dataWrite_10) + 1'b0 : _zz_outputPhy_dataWrite_9 = _zz_outputPhy_dataWrite_2[3 : 0]; + default : _zz_outputPhy_dataWrite_9 = _zz_outputPhy_dataWrite_2[7 : 4]; + endcase + end + + always @(*) begin + timer_reset = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l739) begin + timer_reset = timer_sclkToogleHit; + end else begin + if(!when_SpiXdrMasterCtrl_l758) begin + if(when_SpiXdrMasterCtrl_l764) begin + if(timer_ss_holdHit) begin + timer_reset = 1'b1; + end + end + end + end + end + if(when_SpiXdrMasterCtrl_l781) begin + timer_reset = 1'b1; + end + end + + assign timer_ss_setupHit = (timer_counter == io_config_ss_setup); + assign timer_ss_holdHit = (timer_counter == io_config_ss_hold); + assign timer_ss_disableHit = (timer_counter == io_config_ss_disable); + assign timer_sclkToogleHit = (timer_counter == io_config_sclkToogle); + always @(*) begin + _zz_fsm_counterPlus = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + _zz_fsm_counterPlus = 3'b001; + end + 2'b01 : begin + _zz_fsm_counterPlus = 3'b010; + end + 2'b10 : begin + _zz_fsm_counterPlus = 3'b100; + end + default : begin + end + endcase + end + + assign fsm_counterPlus = (fsm_counter + _zz_fsm_counterPlus); + always @(*) begin + fsm_fastRate = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_fastRate = 1'b0; + end + 2'b01 : begin + fsm_fastRate = 1'b0; + end + 2'b10 : begin + fsm_fastRate = 1'b0; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_isDdr = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_isDdr = 1'b0; + end + 2'b01 : begin + fsm_isDdr = 1'b0; + end + 2'b10 : begin + fsm_isDdr = 1'b0; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_counterMax = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + fsm_counterMax = 3'b111; + end + 2'b01 : begin + fsm_counterMax = 3'b110; + end + 2'b10 : begin + fsm_counterMax = 3'b100; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_lateSampling = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_lateSampling = 1'b1; + end + 2'b01 : begin + fsm_lateSampling = 1'b1; + end + 2'b10 : begin + fsm_lateSampling = 1'b1; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_readFill = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l739) begin + if(when_SpiXdrMasterCtrl_l742) begin + fsm_readFill = 1'b1; + end + end + end + end + + always @(*) begin + fsm_readDone = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l739) begin + if(when_SpiXdrMasterCtrl_l742) begin + fsm_readDone = (io_cmd_payload_read && (fsm_counter == fsm_counterMax)); + end + end + end + end + + assign io_spi_ss = (~ (fsm_ss ^ io_config_ss_activeHigh)); + always @(*) begin + io_cmd_ready = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l739) begin + if(when_SpiXdrMasterCtrl_l749) begin + if(when_SpiXdrMasterCtrl_l751) begin + io_cmd_ready = 1'b1; + end + end + end else begin + if(when_SpiXdrMasterCtrl_l758) begin + if(timer_ss_setupHit) begin + io_cmd_ready = 1'b1; + end + end else begin + if(!when_SpiXdrMasterCtrl_l764) begin + if(timer_ss_disableHit) begin + io_cmd_ready = 1'b1; + end + end + end + end + end + end + + assign when_SpiXdrMasterCtrl_l739 = (! io_cmd_payload_kind); + assign when_SpiXdrMasterCtrl_l742 = ((timer_sclkToogleHit && (((! fsm_state) ^ fsm_lateSampling) || fsm_isDdr)) || fsm_fastRate); + assign when_SpiXdrMasterCtrl_l749 = ((timer_sclkToogleHit && (fsm_state || fsm_isDdr)) || fsm_fastRate); + assign when_SpiXdrMasterCtrl_l751 = (fsm_counter == fsm_counterMax); + assign when_SpiXdrMasterCtrl_l758 = io_cmd_payload_data[7]; + assign when_SpiXdrMasterCtrl_l764 = (! fsm_state); + assign when_SpiXdrMasterCtrl_l781 = ((! io_cmd_valid) || io_cmd_ready); + always @(*) begin + outputPhy_sclkWrite = 1'b0; + if(when_SpiXdrMasterCtrl_l796) begin + case(io_config_mod) + 2'b00 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + 2'b01 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + 2'b10 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + default : begin + end + endcase + end + end + + assign _zz_io_spi_sclk_write[0] = io_config_kind_cpol; + assign io_spi_sclk_write = (outputPhy_sclkWrite ^ _zz_io_spi_sclk_write); + assign when_SpiXdrMasterCtrl_l796 = (io_cmd_valid && (! io_cmd_payload_kind)); + always @(*) begin + outputPhy_widthSel = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + outputPhy_widthSel = 3'b000; + end + 2'b01 : begin + outputPhy_widthSel = 3'b001; + end + 2'b10 : begin + outputPhy_widthSel = 3'b010; + end + default : begin + end + endcase + end + + always @(*) begin + outputPhy_offset = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + outputPhy_offset = 3'b111; + end + 2'b01 : begin + outputPhy_offset = 3'b111; + end + 2'b10 : begin + outputPhy_offset = 3'b111; + end + default : begin + end + endcase + end + + always @(*) begin + outputPhy_dataWrite = 4'bxxxx; + case(outputPhy_widthSel) + 3'b000 : begin + outputPhy_dataWrite[0 : 0] = _zz_outputPhy_dataWrite_3; + end + 3'b001 : begin + outputPhy_dataWrite[1 : 0] = _zz_outputPhy_dataWrite_6; + end + 3'b010 : begin + outputPhy_dataWrite[3 : 0] = _zz_outputPhy_dataWrite_9; + end + default : begin + end + endcase + end + + assign _zz_outputPhy_dataWrite = io_cmd_payload_data; + assign _zz_outputPhy_dataWrite_1 = io_cmd_payload_data; + assign _zz_outputPhy_dataWrite_2 = io_cmd_payload_data; + always @(*) begin + io_spi_data_0_writeEnable = 1'b0; + case(io_config_mod) + 2'b00 : begin + io_spi_data_0_writeEnable = 1'b1; + end + 2'b01 : begin + if(when_SpiXdrMasterCtrl_l839) begin + io_spi_data_0_writeEnable = 1'b1; + end + end + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l839_1) begin + io_spi_data_0_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_1_writeEnable = 1'b0; + case(io_config_mod) + 2'b01 : begin + if(when_SpiXdrMasterCtrl_l839) begin + io_spi_data_1_writeEnable = 1'b1; + end + end + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l839_1) begin + io_spi_data_1_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_2_writeEnable = 1'b0; + case(io_config_mod) + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l839_1) begin + io_spi_data_2_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_3_writeEnable = 1'b0; + case(io_config_mod) + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l839_1) begin + io_spi_data_3_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_0_write = 1'bx; + case(io_config_mod) + 2'b00 : begin + io_spi_data_0_write[0] = (outputPhy_dataWrite[0] || (! (io_cmd_valid && io_cmd_payload_write))); + end + 2'b01 : begin + io_spi_data_0_write[0] = outputPhy_dataWrite[0]; + end + 2'b10 : begin + io_spi_data_0_write[0] = outputPhy_dataWrite[0]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_1_write = 1'bx; + case(io_config_mod) + 2'b01 : begin + io_spi_data_1_write[0] = outputPhy_dataWrite[1]; + end + 2'b10 : begin + io_spi_data_1_write[0] = outputPhy_dataWrite[1]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_2_write = 1'bx; + case(io_config_mod) + 2'b10 : begin + io_spi_data_2_write[0] = outputPhy_dataWrite[2]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_3_write = 1'bx; + case(io_config_mod) + 2'b10 : begin + io_spi_data_3_write[0] = outputPhy_dataWrite[3]; + end + default : begin + end + endcase + end + + assign when_SpiXdrMasterCtrl_l839 = (io_cmd_valid && io_cmd_payload_write); + assign when_SpiXdrMasterCtrl_l839_1 = (io_cmd_valid && io_cmd_payload_write); + always @(*) begin + inputPhy_bufferNext = 8'bxxxxxxxx; + case(inputPhy_widthSel) + 3'b000 : begin + inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[0 : 0]}; + end + 3'b001 : begin + inputPhy_bufferNext = _zz_inputPhy_bufferNext[7:0]; + end + 3'b010 : begin + inputPhy_bufferNext = _zz_inputPhy_bufferNext_1[7:0]; + end + default : begin + end + endcase + end + + always @(*) begin + inputPhy_widthSel = 3'bxxx; + case(inputPhy_mod) + 2'b00 : begin + inputPhy_widthSel = 3'b000; + end + 2'b01 : begin + inputPhy_widthSel = 3'b001; + end + 2'b10 : begin + inputPhy_widthSel = 3'b010; + end + default : begin + end + endcase + end + + assign when_SpiXdrMasterCtrl_l861 = (! fsm_state_delay_2); + always @(*) begin + inputPhy_dataRead = 4'bxxxx; + case(inputPhy_mod) + 2'b00 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead[1]; + end + 2'b01 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead_1[0]; + inputPhy_dataRead[1] = _zz_inputPhy_dataRead_2[1]; + end + 2'b10 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead_3[0]; + inputPhy_dataRead[1] = _zz_inputPhy_dataRead_4[1]; + inputPhy_dataRead[2] = _zz_inputPhy_dataRead_5[2]; + inputPhy_dataRead[3] = _zz_inputPhy_dataRead_6[3]; + end + default : begin + end + endcase + end + + assign io_rsp_valid = inputPhy_readDone; + assign io_rsp_payload_data = inputPhy_bufferNext; + always @(posedge io_systemClk) begin + timer_counter <= (timer_counter + 12'h001); + if(timer_reset) begin + timer_counter <= 12'h0; + end + io_config_mod_delay_1 <= io_config_mod; + inputPhy_mod <= io_config_mod_delay_1; + fsm_state_delay_1 <= fsm_state; + fsm_state_delay_2 <= fsm_state_delay_1; + if(when_SpiXdrMasterCtrl_l861) begin + inputPhy_dataReadBuffer <= {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + end + case(inputPhy_widthSel) + 3'b000 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + 3'b001 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + 3'b010 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + default : begin + end + endcase + end + + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + fsm_state <= 1'b0; + fsm_counter <= 3'b000; + fsm_ss <= 1'b0; + fsm_readFill_delay_1 <= 1'b0; + inputPhy_readFill <= 1'b0; + fsm_readDone_delay_1 <= 1'b0; + inputPhy_readDone <= 1'b0; + end else begin + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l739) begin + if(timer_sclkToogleHit) begin + fsm_state <= (! fsm_state); + end + if(when_SpiXdrMasterCtrl_l749) begin + fsm_counter <= fsm_counterPlus; + if(when_SpiXdrMasterCtrl_l751) begin + fsm_state <= 1'b0; + end + end + end else begin + if(when_SpiXdrMasterCtrl_l758) begin + fsm_ss[0] <= 1'b1; + end else begin + if(when_SpiXdrMasterCtrl_l764) begin + if(timer_ss_holdHit) begin + fsm_state <= 1'b1; + end + end else begin + fsm_ss[0] <= 1'b0; + end + end + end + end + if(when_SpiXdrMasterCtrl_l781) begin + fsm_state <= 1'b0; + fsm_counter <= 3'b000; + end + fsm_readFill_delay_1 <= fsm_readFill; + inputPhy_readFill <= fsm_readFill_delay_1; + fsm_readDone_delay_1 <= fsm_readDone; + inputPhy_readDone <= fsm_readDone_delay_1; + end + end + + +endmodule + +//StreamFifo replaced by StreamFifo + +module StreamFifo ( + input io_push_valid, + output io_push_ready, + input [7:0] io_push_payload, + output io_pop_valid, + input io_pop_ready, + output [7:0] io_pop_payload, + input io_flush, + output [7:0] io_occupancy, + output [7:0] io_availability, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [7:0] _zz_logic_ram_port0; + wire [6:0] _zz_logic_pushPtr_valueNext; + wire [0:0] _zz_logic_pushPtr_valueNext_1; + wire [6:0] _zz_logic_popPtr_valueNext; + wire [0:0] _zz_logic_popPtr_valueNext_1; + wire _zz_logic_ram_port; + wire _zz_io_pop_payload; + wire [6:0] _zz_io_availability; + reg _zz_1; + reg logic_pushPtr_willIncrement; + reg logic_pushPtr_willClear; + reg [6:0] logic_pushPtr_valueNext; + reg [6:0] logic_pushPtr_value; + wire logic_pushPtr_willOverflowIfInc; + wire logic_pushPtr_willOverflow; + reg logic_popPtr_willIncrement; + reg logic_popPtr_willClear; + reg [6:0] logic_popPtr_valueNext; + reg [6:0] logic_popPtr_value; + wire logic_popPtr_willOverflowIfInc; + wire logic_popPtr_willOverflow; + wire logic_ptrMatch; + reg logic_risingOccupancy; + wire logic_pushing; + wire logic_popping; + wire logic_empty; + wire logic_full; + reg _zz_io_pop_valid; + wire when_Stream_l1037; + wire [6:0] logic_ptrDif; + reg [7:0] logic_ram [0:127]; + + assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; + assign _zz_logic_pushPtr_valueNext = {6'd0, _zz_logic_pushPtr_valueNext_1}; + assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; + assign _zz_logic_popPtr_valueNext = {6'd0, _zz_logic_popPtr_valueNext_1}; + assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); + assign _zz_io_pop_payload = 1'b1; + always @(posedge io_systemClk) begin + if(_zz_io_pop_payload) begin + _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_1) begin + logic_ram[logic_pushPtr_value] <= io_push_payload; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_pushing) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willIncrement = 1'b0; + if(logic_pushing) begin + logic_pushPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willClear = 1'b0; + if(io_flush) begin + logic_pushPtr_willClear = 1'b1; + end + end + + assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 7'h7f); + assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); + always @(*) begin + logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); + if(logic_pushPtr_willClear) begin + logic_pushPtr_valueNext = 7'h0; + end + end + + always @(*) begin + logic_popPtr_willIncrement = 1'b0; + if(logic_popping) begin + logic_popPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_popPtr_willClear = 1'b0; + if(io_flush) begin + logic_popPtr_willClear = 1'b1; + end + end + + assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 7'h7f); + assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); + always @(*) begin + logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); + if(logic_popPtr_willClear) begin + logic_popPtr_valueNext = 7'h0; + end + end + + assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); + assign logic_pushing = (io_push_valid && io_push_ready); + assign logic_popping = (io_pop_valid && io_pop_ready); + assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); + assign logic_full = (logic_ptrMatch && logic_risingOccupancy); + assign io_push_ready = (! logic_full); + assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); + assign io_pop_payload = _zz_logic_ram_port0; + assign when_Stream_l1037 = (logic_pushing != logic_popping); + assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); + assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; + assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + logic_pushPtr_value <= 7'h0; + logic_popPtr_value <= 7'h0; + logic_risingOccupancy <= 1'b0; + _zz_io_pop_valid <= 1'b0; + end else begin + logic_pushPtr_value <= logic_pushPtr_valueNext; + logic_popPtr_value <= logic_popPtr_valueNext; + _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); + if(when_Stream_l1037) begin + logic_risingOccupancy <= logic_pushing; + end + if(io_flush) begin + logic_risingOccupancy <= 1'b0; + end + end + end + + +endmodule + +module UartCtrl ( + input [2:0] io_config_frame_dataLength, + input [0:0] io_config_frame_stop, + input [1:0] io_config_frame_parity, + input [19:0] io_config_clockDivider, + input io_write_valid, + output reg io_write_ready, + input [7:0] io_write_payload, + output io_read_valid, + input io_read_ready, + output [7:0] io_read_payload, + output io_uart_txd, + input io_uart_rxd, + output io_readError, + input io_writeBreak, + output io_readBreak, + input io_systemClk, + input systemCd_logic_outputReset +); + localparam UartStopType_ONE = 1'd0; + localparam UartStopType_TWO = 1'd1; + localparam UartParityType_NONE = 2'd0; + localparam UartParityType_EVEN = 2'd1; + localparam UartParityType_ODD = 2'd2; + + wire tx_io_write_ready; + wire tx_io_txd; + wire rx_io_read_valid; + wire [7:0] rx_io_read_payload; + wire rx_io_rts; + wire rx_io_error; + wire rx_io_break; + reg [19:0] clockDivider_counter; + wire clockDivider_tick; + reg clockDivider_tickReg; + reg io_write_thrown_valid; + wire io_write_thrown_ready; + wire [7:0] io_write_thrown_payload; + `ifndef SYNTHESIS + reg [23:0] io_config_frame_stop_string; + reg [31:0] io_config_frame_parity_string; + `endif + + + UartCtrlTx tx ( + .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i + .io_configFrame_stop (io_config_frame_stop ), //i + .io_configFrame_parity (io_config_frame_parity[1:0] ), //i + .io_samplingTick (clockDivider_tickReg ), //i + .io_write_valid (io_write_thrown_valid ), //i + .io_write_ready (tx_io_write_ready ), //o + .io_write_payload (io_write_thrown_payload[7:0] ), //i + .io_cts (1'b0 ), //i + .io_txd (tx_io_txd ), //o + .io_break (io_writeBreak ), //i + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + UartCtrlRx rx ( + .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i + .io_configFrame_stop (io_config_frame_stop ), //i + .io_configFrame_parity (io_config_frame_parity[1:0] ), //i + .io_samplingTick (clockDivider_tickReg ), //i + .io_read_valid (rx_io_read_valid ), //o + .io_read_ready (io_read_ready ), //i + .io_read_payload (rx_io_read_payload[7:0] ), //o + .io_rxd (io_uart_rxd ), //i + .io_rts (rx_io_rts ), //o + .io_error (rx_io_error ), //o + .io_break (rx_io_break ), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_config_frame_stop) + UartStopType_ONE : io_config_frame_stop_string = "ONE"; + UartStopType_TWO : io_config_frame_stop_string = "TWO"; + default : io_config_frame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_config_frame_parity) + UartParityType_NONE : io_config_frame_parity_string = "NONE"; + UartParityType_EVEN : io_config_frame_parity_string = "EVEN"; + UartParityType_ODD : io_config_frame_parity_string = "ODD "; + default : io_config_frame_parity_string = "????"; + endcase + end + `endif + + assign clockDivider_tick = (clockDivider_counter == 20'h0); + always @(*) begin + io_write_thrown_valid = io_write_valid; + if(rx_io_break) begin + io_write_thrown_valid = 1'b0; + end + end + + always @(*) begin + io_write_ready = io_write_thrown_ready; + if(rx_io_break) begin + io_write_ready = 1'b1; + end + end + + assign io_write_thrown_payload = io_write_payload; + assign io_write_thrown_ready = tx_io_write_ready; + assign io_read_valid = rx_io_read_valid; + assign io_read_payload = rx_io_read_payload; + assign io_uart_txd = tx_io_txd; + assign io_readError = rx_io_error; + assign io_readBreak = rx_io_break; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + clockDivider_counter <= 20'h0; + clockDivider_tickReg <= 1'b0; + end else begin + clockDivider_tickReg <= clockDivider_tick; + clockDivider_counter <= (clockDivider_counter - 20'h00001); + if(clockDivider_tick) begin + clockDivider_counter <= io_config_clockDivider; + end + end + end + + +endmodule + +module StreamArbiter ( + input io_inputs_0_valid, + output io_inputs_0_ready, + input io_inputs_0_payload_last, + input [0:0] io_inputs_0_payload_fragment_source, + input [0:0] io_inputs_0_payload_fragment_opcode, + input [31:0] io_inputs_0_payload_fragment_address, + input [5:0] io_inputs_0_payload_fragment_length, + input [31:0] io_inputs_0_payload_fragment_data, + input [3:0] io_inputs_0_payload_fragment_mask, + input [0:0] io_inputs_0_payload_fragment_context, + input io_inputs_1_valid, + output io_inputs_1_ready, + input io_inputs_1_payload_last, + input [0:0] io_inputs_1_payload_fragment_source, + input [0:0] io_inputs_1_payload_fragment_opcode, + input [31:0] io_inputs_1_payload_fragment_address, + input [5:0] io_inputs_1_payload_fragment_length, + input [31:0] io_inputs_1_payload_fragment_data, + input [3:0] io_inputs_1_payload_fragment_mask, + input [0:0] io_inputs_1_payload_fragment_context, + output io_output_valid, + input io_output_ready, + output io_output_payload_last, + output [0:0] io_output_payload_fragment_source, + output [0:0] io_output_payload_fragment_opcode, + output [31:0] io_output_payload_fragment_address, + output [5:0] io_output_payload_fragment_length, + output [31:0] io_output_payload_fragment_data, + output [3:0] io_output_payload_fragment_mask, + output [0:0] io_output_payload_fragment_context, + output [0:0] io_chosen, + output [1:0] io_chosenOH, + input io_systemClk, + input systemCd_logic_outputReset +); + + wire [3:0] _zz__zz_maskProposal_0_2; + wire [3:0] _zz__zz_maskProposal_0_2_1; + wire [1:0] _zz__zz_maskProposal_0_2_2; + reg locked; + wire maskProposal_0; + wire maskProposal_1; + reg maskLocked_0; + reg maskLocked_1; + wire maskRouted_0; + wire maskRouted_1; + wire [1:0] _zz_maskProposal_0; + wire [3:0] _zz_maskProposal_0_1; + wire [3:0] _zz_maskProposal_0_2; + wire [1:0] _zz_maskProposal_0_3; + wire io_output_fire; + wire when_Stream_l621; + wire _zz_io_chosen; + + assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); + assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; + assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; + assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); + assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); + assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; + assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; + assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); + assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); + assign maskProposal_0 = _zz_maskProposal_0_3[0]; + assign maskProposal_1 = _zz_maskProposal_0_3[1]; + assign io_output_fire = (io_output_valid && io_output_ready); + assign when_Stream_l621 = (io_output_fire && io_output_payload_last); + assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); + assign io_output_payload_last = (maskRouted_0 ? io_inputs_0_payload_last : io_inputs_1_payload_last); + assign io_output_payload_fragment_source = (maskRouted_0 ? io_inputs_0_payload_fragment_source : io_inputs_1_payload_fragment_source); + assign io_output_payload_fragment_opcode = (maskRouted_0 ? io_inputs_0_payload_fragment_opcode : io_inputs_1_payload_fragment_opcode); + assign io_output_payload_fragment_address = (maskRouted_0 ? io_inputs_0_payload_fragment_address : io_inputs_1_payload_fragment_address); + assign io_output_payload_fragment_length = (maskRouted_0 ? io_inputs_0_payload_fragment_length : io_inputs_1_payload_fragment_length); + assign io_output_payload_fragment_data = (maskRouted_0 ? io_inputs_0_payload_fragment_data : io_inputs_1_payload_fragment_data); + assign io_output_payload_fragment_mask = (maskRouted_0 ? io_inputs_0_payload_fragment_mask : io_inputs_1_payload_fragment_mask); + assign io_output_payload_fragment_context = (maskRouted_0 ? io_inputs_0_payload_fragment_context : io_inputs_1_payload_fragment_context); + assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); + assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); + assign io_chosenOH = {maskRouted_1,maskRouted_0}; + assign _zz_io_chosen = io_chosenOH[1]; + assign io_chosen = _zz_io_chosen; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + locked <= 1'b0; + maskLocked_0 <= 1'b0; + maskLocked_1 <= 1'b1; + end else begin + if(io_output_valid) begin + maskLocked_0 <= maskRouted_0; + maskLocked_1 <= maskRouted_1; + end + if(io_output_valid) begin + locked <= 1'b1; + end + if(when_Stream_l621) begin + locked <= 1'b0; + end + end + end + + +endmodule + +module FlowCCByToggle ( + input io_input_valid, + input io_input_payload_last, + input [0:0] io_input_payload_fragment, + output io_output_valid, + output io_output_payload_last, + output [0:0] io_output_payload_fragment, + input jtagCtrl_tck, + input io_systemClk, + input debugCd_logic_outputReset +); + + wire inputArea_target_buffercc_io_dataOut; + reg inputArea_target; + reg inputArea_data_last; + reg [0:0] inputArea_data_fragment; + wire outputArea_target; + reg outputArea_hit; + wire outputArea_flow_valid; + wire outputArea_flow_payload_last; + wire [0:0] outputArea_flow_payload_fragment; + reg outputArea_flow_m2sPipe_valid; + reg outputArea_flow_m2sPipe_payload_last; + reg [0:0] outputArea_flow_m2sPipe_payload_fragment; + + BufferCC_1 inputArea_target_buffercc ( + .io_dataIn (inputArea_target ), //i + .io_dataOut (inputArea_target_buffercc_io_dataOut), //o + .io_systemClk (io_systemClk ), //i + .debugCd_logic_outputReset (debugCd_logic_outputReset ) //i + ); + initial begin + `ifndef SYNTHESIS + inputArea_target = $urandom; + outputArea_hit = $urandom; + `endif + end + + assign outputArea_target = inputArea_target_buffercc_io_dataOut; + assign outputArea_flow_valid = (outputArea_target != outputArea_hit); + assign outputArea_flow_payload_last = inputArea_data_last; + assign outputArea_flow_payload_fragment = inputArea_data_fragment; + assign io_output_valid = outputArea_flow_m2sPipe_valid; + assign io_output_payload_last = outputArea_flow_m2sPipe_payload_last; + assign io_output_payload_fragment = outputArea_flow_m2sPipe_payload_fragment; + always @(posedge jtagCtrl_tck) begin + if(io_input_valid) begin + inputArea_target <= (! inputArea_target); + inputArea_data_last <= io_input_payload_last; + inputArea_data_fragment <= io_input_payload_fragment; + end + end + + always @(posedge io_systemClk) begin + outputArea_hit <= outputArea_target; + if(outputArea_flow_valid) begin + outputArea_flow_m2sPipe_payload_last <= outputArea_flow_payload_last; + outputArea_flow_m2sPipe_payload_fragment <= outputArea_flow_payload_fragment; + end + end + + always @(posedge io_systemClk) begin + if(debugCd_logic_outputReset) begin + outputArea_flow_m2sPipe_valid <= 1'b0; + end else begin + outputArea_flow_m2sPipe_valid <= outputArea_flow_valid; + end + end + + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output reg io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isFiring, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + input [31:0] io_cpu_writeBack_storeData, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output io_cpu_writeBack_exclusiveOk, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output io_cpu_flush_ready, + input io_cpu_flush_payload_singleLine, + input [5:0] io_cpu_flush_payload_lineId, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_size, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [21:0] _zz_ways_0_tags_port0; + reg [31:0] _zz_ways_0_data_port0; + wire [21:0] _zz_ways_0_tags_port; + wire [9:0] _zz_stage0_dataColisions; + wire [9:0] _zz__zz_stageA_dataColisions; + wire [0:0] _zz_when; + wire [3:0] _zz_loader_counter_valueNext; + wire [0:0] _zz_loader_counter_valueNext_1; + wire [1:0] _zz_loader_waysAllocator; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [5:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [5:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [5:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_ways_0_tagsReadRsp_valid_1; + wire _zz_ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire when_DataCache_l642; + wire when_DataCache_l645; + wire when_DataCache_l664; + wire rspSync; + wire rspLast; + reg memCmdSent; + wire io_mem_cmd_fire; + wire when_DataCache_l686; + reg [3:0] _zz_stage0_mask; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + wire stage0_isAmo; + wire when_DataCache_l771; + reg stageA_request_wr; + reg [1:0] stageA_request_size; + reg stageA_request_totalyConsistent; + wire when_DataCache_l771_1; + reg [3:0] stageA_mask; + wire stageA_isAmo; + wire stageA_isLrsc; + wire [0:0] stageA_wayHits; + wire when_DataCache_l771_2; + reg [0:0] stageA_wayInvalidate; + wire when_DataCache_l771_3; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_stageA_dataColisions; + wire [0:0] stageA_dataColisions; + wire when_DataCache_l822; + reg stageB_request_wr; + reg [1:0] stageB_request_size; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + wire when_DataCache_l824; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + wire when_DataCache_l821; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + wire when_DataCache_l821_1; + reg [31:0] stageB_dataReadRsp_0; + wire when_DataCache_l820; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + wire when_DataCache_l820_1; + reg [0:0] stageB_dataColisions; + wire when_DataCache_l820_2; + reg stageB_unaligned; + wire when_DataCache_l820_3; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + wire when_DataCache_l820_4; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_waitDone; + wire stageB_flusher_hold; + reg [6:0] stageB_flusher_counter; + wire when_DataCache_l850; + wire when_DataCache_l856; + reg stageB_flusher_start; + wire stageB_isAmo; + wire stageB_isAmoCached; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + wire [31:0] stageB_requestDataBypass; + reg stageB_cpuWriteToCache; + wire when_DataCache_l926; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + wire when_DataCache_l995; + wire when_DataCache_l1004; + wire when_DataCache_l1009; + wire when_DataCache_l1020; + wire when_DataCache_l1032; + wire when_DataCache_l991; + wire when_DataCache_l1066; + wire when_DataCache_l1075; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [3:0] loader_counter_valueNext; + reg [3:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire when_DataCache_l1090; + wire loader_done; + wire when_DataCache_l1118; + reg loader_valid_regNext; + wire when_DataCache_l1122; + wire when_DataCache_l1125; + reg [21:0] ways_0_tags [0:63]; + reg [7:0] ways_0_data_symbol0 [0:1023]; + reg [7:0] ways_0_data_symbol1 [0:1023]; + reg [7:0] ways_0_data_symbol2 [0:1023]; + reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_ways_0_datasymbol_read; + reg [7:0] _zz_ways_0_datasymbol_read_1; + reg [7:0] _zz_ways_0_datasymbol_read_2; + reg [7:0] _zz_ways_0_datasymbol_read_3; + + assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_when = 1'b1; + assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; + assign _zz_loader_counter_valueNext = {3'd0, _zz_loader_counter_valueNext_1}; + assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @(posedge io_systemClk) begin + if(_zz_ways_0_tagsReadRsp_valid) begin + _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; + end + end + + always @(*) begin + _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; + end + always @(posedge io_systemClk) begin + if(_zz_ways_0_dataReadRspMem) begin + _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @(posedge io_systemClk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(when_DataCache_l645) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + _zz_2 = 1'b0; + if(when_DataCache_l642) begin + _zz_2 = 1'b1; + end + end + + assign haltCpu = 1'b0; + assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; + assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; + assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; + assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2]; + assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + assign when_DataCache_l642 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); + assign when_DataCache_l645 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); + always @(*) begin + tagsReadCmd_valid = 1'b0; + if(when_DataCache_l664) begin + tagsReadCmd_valid = 1'b1; + end + end + + always @(*) begin + tagsReadCmd_payload = 6'bxxxxxx; + if(when_DataCache_l664) begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 6]; + end + end + + always @(*) begin + dataReadCmd_valid = 1'b0; + if(when_DataCache_l664) begin + dataReadCmd_valid = 1'b1; + end + end + + always @(*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(when_DataCache_l664) begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + end + end + + always @(*) begin + tagsWriteCmd_valid = 1'b0; + if(when_DataCache_l850) begin + tagsWriteCmd_valid = 1'b1; + end + if(when_DataCache_l1066) begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_done) begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @(*) begin + tagsWriteCmd_payload_way = 1'bx; + if(when_DataCache_l850) begin + tagsWriteCmd_payload_way = 1'b1; + end + if(loader_done) begin + tagsWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @(*) begin + tagsWriteCmd_payload_address = 6'bxxxxxx; + if(when_DataCache_l850) begin + tagsWriteCmd_payload_address = stageB_flusher_counter[5:0]; + end + if(loader_done) begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 6]; + end + end + + always @(*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(when_DataCache_l850) begin + tagsWriteCmd_payload_data_valid = 1'b0; + end + if(loader_done) begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); + end + end + + always @(*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done) begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); + end + end + + always @(*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done) begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + end + end + + always @(*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache) begin + if(when_DataCache_l926) begin + dataWriteCmd_valid = 1'b1; + end + end + if(when_DataCache_l1066) begin + dataWriteCmd_valid = 1'b0; + end + if(when_DataCache_l1090) begin + dataWriteCmd_valid = 1'b1; + end + end + + always @(*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_way = stageB_waysHits; + end + if(when_DataCache_l1090) begin + dataWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @(*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + end + if(when_DataCache_l1090) begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 6],loader_counter_value}; + end + end + + always @(*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; + end + if(when_DataCache_l1090) begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; + end + end + + always @(*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_when[0]) begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end + end + if(when_DataCache_l1090) begin + dataWriteCmd_payload_mask = 4'b1111; + end + end + + assign when_DataCache_l664 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + always @(*) begin + io_cpu_execute_haltIt = 1'b0; + if(when_DataCache_l850) begin + io_cpu_execute_haltIt = 1'b1; + end + end + + assign rspSync = 1'b1; + assign rspLast = 1'b1; + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign when_DataCache_l686 = (! io_cpu_writeBack_isStuck); + always @(*) begin + _zz_stage0_mask = 4'bxxxx; + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_stage0_mask = 4'b0001; + end + 2'b01 : begin + _zz_stage0_mask = 4'b0011; + end + 2'b10 : begin + _zz_stage0_mask = 4'b1111; + end + default : begin + end + endcase + end + + assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign stage0_isAmo = 1'b0; + assign when_DataCache_l771 = (! io_cpu_memory_isStuck); + assign when_DataCache_l771_1 = (! io_cpu_memory_isStuck); + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_isAmo = 1'b0; + assign stageA_isLrsc = 1'b0; + assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign when_DataCache_l771_2 = (! io_cpu_memory_isStuck); + assign when_DataCache_l771_3 = (! io_cpu_memory_isStuck); + assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); + assign when_DataCache_l822 = (! io_cpu_writeBack_isStuck); + always @(*) begin + stageB_mmuRspFreeze = 1'b0; + if(when_DataCache_l1125) begin + stageB_mmuRspFreeze = 1'b1; + end + end + + assign when_DataCache_l824 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign when_DataCache_l821 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l821_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l820 = (! io_cpu_writeBack_isStuck); + assign stageB_consistancyHazard = 1'b0; + assign when_DataCache_l820_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l820_2 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l820_3 = (! io_cpu_writeBack_isStuck); + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (|stageB_waysHits); + assign stageB_dataMux = stageB_dataReadRsp_0; + assign when_DataCache_l820_4 = (! io_cpu_writeBack_isStuck); + always @(*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(!when_DataCache_l1004) begin + if(io_mem_cmd_ready) begin + stageB_loaderValid = 1'b1; + end + end + end + end + end + if(when_DataCache_l1066) begin + stageB_loaderValid = 1'b0; + end + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @(*) begin + io_cpu_writeBack_haltIt = 1'b1; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l991) begin + if(when_DataCache_l995) begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(when_DataCache_l1004) begin + if(when_DataCache_l1009) begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end + end + if(when_DataCache_l1066) begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + + assign stageB_flusher_hold = 1'b0; + assign when_DataCache_l850 = (! stageB_flusher_counter[6]); + assign when_DataCache_l856 = (! stageB_flusher_hold); + assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[6]); + assign stageB_isAmo = 1'b0; + assign stageB_isAmoCached = 1'b0; + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + assign stageB_requestDataBypass = io_cpu_writeBack_storeData; + always @(*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(when_DataCache_l1004) begin + stageB_cpuWriteToCache = 1'b1; + end + end + end + end + end + + assign when_DataCache_l926 = (stageB_request_wr && stageB_waysHit); + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @(*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(when_DataCache_l1004) begin + if(when_DataCache_l1020) begin + io_cpu_redo = 1'b1; + end + end + end + end + end + if(when_DataCache_l1075) begin + io_cpu_redo = 1'b1; + end + if(when_DataCache_l1122) begin + io_cpu_redo = 1'b1; + end + end + + always @(*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache) begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + end + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @(*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l991) begin + io_mem_cmd_valid = (! memCmdSent); + end else begin + if(when_DataCache_l1004) begin + if(stageB_request_wr) begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if(when_DataCache_l1032) begin + io_mem_cmd_valid = 1'b1; + end + end + end + end + end + if(when_DataCache_l1066) begin + io_mem_cmd_valid = 1'b0; + end + end + + always @(*) begin + io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(!when_DataCache_l1004) begin + io_mem_cmd_payload_address[5 : 0] = 6'h0; + end + end + end + end + end + + assign io_mem_cmd_payload_last = 1'b1; + always @(*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(!when_DataCache_l1004) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end + end + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + always @(*) begin + io_mem_cmd_payload_size = {1'd0, stageB_request_size}; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l991) begin + if(!when_DataCache_l1004) begin + io_mem_cmd_payload_size = 3'b110; + end + end + end + end + end + + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + assign when_DataCache_l995 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); + assign when_DataCache_l1004 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign when_DataCache_l1009 = ((! stageB_request_wr) || io_mem_cmd_ready); + assign when_DataCache_l1020 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign when_DataCache_l1032 = (! memCmdSent); + assign when_DataCache_l991 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + always @(*) begin + if(stageB_bypassCache) begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; + end + end + + assign when_DataCache_l1066 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign when_DataCache_l1075 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); + always @(*) begin + loader_counter_willIncrement = 1'b0; + if(when_DataCache_l1090) begin + loader_counter_willIncrement = 1'b1; + end + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 4'b1111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @(*) begin + loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); + if(loader_counter_willClear) begin + loader_counter_valueNext = 4'b0000; + end + end + + assign loader_kill = 1'b0; + assign when_DataCache_l1090 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign loader_done = loader_counter_willOverflow; + assign when_DataCache_l1118 = (! loader_valid); + assign when_DataCache_l1122 = (loader_valid && (! loader_valid_regNext)); + assign io_cpu_execute_refilling = loader_valid; + assign when_DataCache_l1125 = (stageB_loaderValid || loader_valid); + always @(posedge io_systemClk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if(when_DataCache_l771) begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; + end + if(when_DataCache_l771_1) begin + stageA_mask <= stage0_mask; + end + if(when_DataCache_l771_2) begin + stageA_wayInvalidate <= stage0_wayInvalidate; + end + if(when_DataCache_l771_3) begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; + end + if(when_DataCache_l822) begin + stageB_request_wr <= stageA_request_wr; + stageB_request_size <= stageA_request_size; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(when_DataCache_l824) begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; + end + if(when_DataCache_l821) begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; + end + if(when_DataCache_l821_1) begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; + end + if(when_DataCache_l820) begin + stageB_wayInvalidate <= stageA_wayInvalidate; + end + if(when_DataCache_l820_1) begin + stageB_dataColisions <= stageA_dataColisions; + end + if(when_DataCache_l820_2) begin + stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); + end + if(when_DataCache_l820_3) begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; + end + if(when_DataCache_l820_4) begin + stageB_mask <= stageA_mask; + end + loader_valid_regNext <= loader_valid; + end + + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + memCmdSent <= 1'b0; + stageB_flusher_waitDone <= 1'b0; + stageB_flusher_counter <= 7'h0; + stageB_flusher_start <= 1'b1; + loader_valid <= 1'b0; + loader_counter_value <= 4'b0000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_fire) begin + memCmdSent <= 1'b1; + end + if(when_DataCache_l686) begin + memCmdSent <= 1'b0; + end + if(io_cpu_flush_ready) begin + stageB_flusher_waitDone <= 1'b0; + end + if(when_DataCache_l850) begin + if(when_DataCache_l856) begin + stageB_flusher_counter <= (stageB_flusher_counter + 7'h01); + if(io_cpu_flush_payload_singleLine) begin + stageB_flusher_counter[6] <= 1'b1; + end + end + end + stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start) begin + stageB_flusher_waitDone <= 1'b1; + stageB_flusher_counter <= 7'h0; + if(io_cpu_flush_payload_singleLine) begin + stageB_flusher_counter <= {1'b0,io_cpu_flush_payload_lineId}; + end + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); // DataCache.scala:L1077 + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("ERROR writeBack stuck by another plugin is not allowed"); // DataCache.scala:L1077 + end + `endif + `endif + if(stageB_loaderValid) begin + loader_valid <= 1'b1; + end + loader_counter_value <= loader_counter_valueNext; + if(loader_kill) begin + loader_killReg <= 1'b1; + end + if(when_DataCache_l1090) begin + loader_error <= (loader_error || io_mem_rsp_payload_error); + end + if(loader_done) begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end + if(when_DataCache_l1118) begin + loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; + end + end + end + + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input io_systemClk, + input systemCd_logic_outputReset +); + + reg [31:0] _zz_banks_0_port1; + reg [21:0] _zz_ways_0_tags_port1; + wire [21:0] _zz_ways_0_tags_port; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [6:0] lineLoader_flushCounter; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; + reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l513; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [3:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [5:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire when_InstructionCache_l401; + wire [9:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [5:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; + reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + wire when_InstructionCache_l459_1; + reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; + reg decodeStage_hit_error; + reg [31:0] banks_0 [0:1023]; + reg [21:0] ways_0_tags [0:63]; + + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge io_systemClk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @(posedge io_systemClk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; + end + end + + always @(posedge io_systemClk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; + end + end + + always @(posedge io_systemClk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid) begin + _zz_2 = 1'b1; + end + end + + always @(*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin + lineLoader_fire = 1'b1; + end + end + end + + always @(*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(when_InstructionCache_l338) begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(when_InstructionCache_l342) begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush) begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[6]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 6],6'h0}; + assign io_mem_cmd_payload_size = 3'b110; + assign when_Utils_l513 = (! lineLoader_valid); + always @(*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if(when_Utils_l513) begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[11 : 6] : lineLoader_flushCounter[5 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 6],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data[31 : 0]; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 4'b1111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[11 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[11 : 6]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[21 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = (|fetchStage_hit_hits_0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 4'b0000; + end else begin + if(lineLoader_fire) begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire) begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid) begin + lineLoader_valid <= 1'b1; + end + if(io_flush) begin + lineLoader_flushPending <= 1'b1; + end + if(when_InstructionCache_l351) begin + lineLoader_flushPending <= 1'b0; + end + if(io_mem_cmd_fire) begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire) begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid) begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 4'b0001); + if(io_mem_rsp_payload_error) begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @(posedge io_systemClk) begin + if(io_cpu_fill_valid) begin + lineLoader_address <= io_cpu_fill_payload; + end + if(when_InstructionCache_l338) begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); + end + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[6]; + if(when_InstructionCache_l351) begin + lineLoader_flushCounter <= 7'h0; + end + if(when_InstructionCache_l435) begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if(when_InstructionCache_l459) begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + end + if(when_InstructionCache_l459_1) begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if(when_InstructionCache_l459_2) begin + decodeStage_hit_error <= fetchStage_hit_error; + end + end + + +endmodule + +module UartCtrlRx ( + input [2:0] io_configFrame_dataLength, + input [0:0] io_configFrame_stop, + input [1:0] io_configFrame_parity, + input io_samplingTick, + output io_read_valid, + input io_read_ready, + output [7:0] io_read_payload, + input io_rxd, + output io_rts, + output reg io_error, + output io_break, + input io_systemClk, + input systemCd_logic_outputReset +); + localparam UartStopType_ONE = 1'd0; + localparam UartStopType_TWO = 1'd1; + localparam UartParityType_NONE = 2'd0; + localparam UartParityType_EVEN = 2'd1; + localparam UartParityType_ODD = 2'd2; + localparam UartCtrlRxState_IDLE = 3'd0; + localparam UartCtrlRxState_START = 3'd1; + localparam UartCtrlRxState_DATA = 3'd2; + localparam UartCtrlRxState_PARITY = 3'd3; + localparam UartCtrlRxState_STOP = 3'd4; + + wire io_rxd_buffercc_io_dataOut; + wire _zz_sampler_value; + wire _zz_sampler_value_1; + wire _zz_sampler_value_2; + wire _zz_sampler_value_3; + wire _zz_sampler_value_4; + wire _zz_sampler_value_5; + wire _zz_sampler_value_6; + wire [2:0] _zz_when_UartCtrlRx_l139; + wire [0:0] _zz_when_UartCtrlRx_l139_1; + reg _zz_io_rts; + wire sampler_synchroniser; + wire sampler_samples_0; + reg sampler_samples_1; + reg sampler_samples_2; + reg sampler_samples_3; + reg sampler_samples_4; + reg sampler_value; + reg sampler_tick; + reg [2:0] bitTimer_counter; + reg bitTimer_tick; + wire when_UartCtrlRx_l43; + reg [2:0] bitCounter_value; + reg [6:0] break_counter; + wire break_valid; + wire when_UartCtrlRx_l69; + reg [2:0] stateMachine_state; + reg stateMachine_parity; + reg [7:0] stateMachine_shifter; + reg stateMachine_validReg; + wire when_UartCtrlRx_l93; + wire when_UartCtrlRx_l103; + wire when_UartCtrlRx_l111; + wire when_UartCtrlRx_l113; + wire when_UartCtrlRx_l125; + wire when_UartCtrlRx_l136; + wire when_UartCtrlRx_l139; + `ifndef SYNTHESIS + reg [23:0] io_configFrame_stop_string; + reg [31:0] io_configFrame_parity_string; + reg [47:0] stateMachine_state_string; + `endif + + + assign _zz_when_UartCtrlRx_l139_1 = ((io_configFrame_stop == UartStopType_ONE) ? 1'b0 : 1'b1); + assign _zz_when_UartCtrlRx_l139 = {2'd0, _zz_when_UartCtrlRx_l139_1}; + assign _zz_sampler_value = ((((1'b0 || ((_zz_sampler_value_1 && sampler_samples_1) && sampler_samples_2)) || (((_zz_sampler_value_2 && sampler_samples_0) && sampler_samples_1) && sampler_samples_3)) || (((1'b1 && sampler_samples_0) && sampler_samples_2) && sampler_samples_3)) || (((1'b1 && sampler_samples_1) && sampler_samples_2) && sampler_samples_3)); + assign _zz_sampler_value_3 = (((1'b1 && sampler_samples_0) && sampler_samples_1) && sampler_samples_4); + assign _zz_sampler_value_4 = ((1'b1 && sampler_samples_0) && sampler_samples_2); + assign _zz_sampler_value_5 = (1'b1 && sampler_samples_1); + assign _zz_sampler_value_6 = 1'b1; + assign _zz_sampler_value_1 = (1'b1 && sampler_samples_0); + assign _zz_sampler_value_2 = 1'b1; + BufferCC io_rxd_buffercc ( + .io_dataIn (io_rxd ), //i + .io_dataOut (io_rxd_buffercc_io_dataOut), //o + .io_systemClk (io_systemClk ), //i + .systemCd_logic_outputReset (systemCd_logic_outputReset) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_configFrame_stop) + UartStopType_ONE : io_configFrame_stop_string = "ONE"; + UartStopType_TWO : io_configFrame_stop_string = "TWO"; + default : io_configFrame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_configFrame_parity) + UartParityType_NONE : io_configFrame_parity_string = "NONE"; + UartParityType_EVEN : io_configFrame_parity_string = "EVEN"; + UartParityType_ODD : io_configFrame_parity_string = "ODD "; + default : io_configFrame_parity_string = "????"; + endcase + end + always @(*) begin + case(stateMachine_state) + UartCtrlRxState_IDLE : stateMachine_state_string = "IDLE "; + UartCtrlRxState_START : stateMachine_state_string = "START "; + UartCtrlRxState_DATA : stateMachine_state_string = "DATA "; + UartCtrlRxState_PARITY : stateMachine_state_string = "PARITY"; + UartCtrlRxState_STOP : stateMachine_state_string = "STOP "; + default : stateMachine_state_string = "??????"; + endcase + end + `endif + + always @(*) begin + io_error = 1'b0; + case(stateMachine_state) + UartCtrlRxState_IDLE : begin + end + UartCtrlRxState_START : begin + end + UartCtrlRxState_DATA : begin + end + UartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + if(!when_UartCtrlRx_l125) begin + io_error = 1'b1; + end + end + end + default : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l136) begin + io_error = 1'b1; + end + end + end + endcase + end + + assign io_rts = _zz_io_rts; + assign sampler_synchroniser = io_rxd_buffercc_io_dataOut; + assign sampler_samples_0 = sampler_synchroniser; + always @(*) begin + bitTimer_tick = 1'b0; + if(sampler_tick) begin + if(when_UartCtrlRx_l43) begin + bitTimer_tick = 1'b1; + end + end + end + + assign when_UartCtrlRx_l43 = (bitTimer_counter == 3'b000); + assign break_valid = (break_counter == 7'h68); + assign when_UartCtrlRx_l69 = (io_samplingTick && (! break_valid)); + assign io_break = break_valid; + assign io_read_valid = stateMachine_validReg; + assign when_UartCtrlRx_l93 = ((sampler_tick && (! sampler_value)) && (! break_valid)); + assign when_UartCtrlRx_l103 = (sampler_value == 1'b1); + assign when_UartCtrlRx_l111 = (bitCounter_value == io_configFrame_dataLength); + assign when_UartCtrlRx_l113 = (io_configFrame_parity == UartParityType_NONE); + assign when_UartCtrlRx_l125 = (stateMachine_parity == sampler_value); + assign when_UartCtrlRx_l136 = (! sampler_value); + assign when_UartCtrlRx_l139 = (bitCounter_value == _zz_when_UartCtrlRx_l139); + assign io_read_payload = stateMachine_shifter; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + _zz_io_rts <= 1'b0; + sampler_samples_1 <= 1'b1; + sampler_samples_2 <= 1'b1; + sampler_samples_3 <= 1'b1; + sampler_samples_4 <= 1'b1; + sampler_value <= 1'b1; + sampler_tick <= 1'b0; + break_counter <= 7'h0; + stateMachine_state <= UartCtrlRxState_IDLE; + stateMachine_validReg <= 1'b0; + end else begin + _zz_io_rts <= (! io_read_ready); + if(io_samplingTick) begin + sampler_samples_1 <= sampler_samples_0; + end + if(io_samplingTick) begin + sampler_samples_2 <= sampler_samples_1; + end + if(io_samplingTick) begin + sampler_samples_3 <= sampler_samples_2; + end + if(io_samplingTick) begin + sampler_samples_4 <= sampler_samples_3; + end + sampler_value <= ((((((_zz_sampler_value || _zz_sampler_value_3) || (_zz_sampler_value_4 && sampler_samples_4)) || ((_zz_sampler_value_5 && sampler_samples_2) && sampler_samples_4)) || (((_zz_sampler_value_6 && sampler_samples_0) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_1) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_2) && sampler_samples_3) && sampler_samples_4)); + sampler_tick <= io_samplingTick; + if(sampler_value) begin + break_counter <= 7'h0; + end else begin + if(when_UartCtrlRx_l69) begin + break_counter <= (break_counter + 7'h01); + end + end + stateMachine_validReg <= 1'b0; + case(stateMachine_state) + UartCtrlRxState_IDLE : begin + if(when_UartCtrlRx_l93) begin + stateMachine_state <= UartCtrlRxState_START; + end + end + UartCtrlRxState_START : begin + if(bitTimer_tick) begin + stateMachine_state <= UartCtrlRxState_DATA; + if(when_UartCtrlRx_l103) begin + stateMachine_state <= UartCtrlRxState_IDLE; + end + end + end + UartCtrlRxState_DATA : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l111) begin + if(when_UartCtrlRx_l113) begin + stateMachine_state <= UartCtrlRxState_STOP; + stateMachine_validReg <= 1'b1; + end else begin + stateMachine_state <= UartCtrlRxState_PARITY; + end + end + end + end + UartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l125) begin + stateMachine_state <= UartCtrlRxState_STOP; + stateMachine_validReg <= 1'b1; + end else begin + stateMachine_state <= UartCtrlRxState_IDLE; + end + end + end + default : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l136) begin + stateMachine_state <= UartCtrlRxState_IDLE; + end else begin + if(when_UartCtrlRx_l139) begin + stateMachine_state <= UartCtrlRxState_IDLE; + end + end + end + end + endcase + end + end + + always @(posedge io_systemClk) begin + if(sampler_tick) begin + bitTimer_counter <= (bitTimer_counter - 3'b001); + end + if(bitTimer_tick) begin + bitCounter_value <= (bitCounter_value + 3'b001); + end + if(bitTimer_tick) begin + stateMachine_parity <= (stateMachine_parity ^ sampler_value); + end + case(stateMachine_state) + UartCtrlRxState_IDLE : begin + if(when_UartCtrlRx_l93) begin + bitTimer_counter <= 3'b010; + end + end + UartCtrlRxState_START : begin + if(bitTimer_tick) begin + bitCounter_value <= 3'b000; + stateMachine_parity <= (io_configFrame_parity == UartParityType_ODD); + end + end + UartCtrlRxState_DATA : begin + if(bitTimer_tick) begin + stateMachine_shifter[bitCounter_value] <= sampler_value; + if(when_UartCtrlRx_l111) begin + bitCounter_value <= 3'b000; + end + end + end + UartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + bitCounter_value <= 3'b000; + end + end + default : begin + end + endcase + end + + +endmodule + +module UartCtrlTx ( + input [2:0] io_configFrame_dataLength, + input [0:0] io_configFrame_stop, + input [1:0] io_configFrame_parity, + input io_samplingTick, + input io_write_valid, + output reg io_write_ready, + input [7:0] io_write_payload, + input io_cts, + output io_txd, + input io_break, + input io_systemClk, + input systemCd_logic_outputReset +); + localparam UartStopType_ONE = 1'd0; + localparam UartStopType_TWO = 1'd1; + localparam UartParityType_NONE = 2'd0; + localparam UartParityType_EVEN = 2'd1; + localparam UartParityType_ODD = 2'd2; + localparam UartCtrlTxState_IDLE = 3'd0; + localparam UartCtrlTxState_START = 3'd1; + localparam UartCtrlTxState_DATA = 3'd2; + localparam UartCtrlTxState_PARITY = 3'd3; + localparam UartCtrlTxState_STOP = 3'd4; + + wire [2:0] _zz_clockDivider_counter_valueNext; + wire [0:0] _zz_clockDivider_counter_valueNext_1; + wire [2:0] _zz_when_UartCtrlTx_l93; + wire [0:0] _zz_when_UartCtrlTx_l93_1; + reg clockDivider_counter_willIncrement; + wire clockDivider_counter_willClear; + reg [2:0] clockDivider_counter_valueNext; + reg [2:0] clockDivider_counter_value; + wire clockDivider_counter_willOverflowIfInc; + wire clockDivider_counter_willOverflow; + reg [2:0] tickCounter_value; + reg [2:0] stateMachine_state; + reg stateMachine_parity; + reg stateMachine_txd; + wire when_UartCtrlTx_l58; + wire when_UartCtrlTx_l73; + wire when_UartCtrlTx_l76; + wire when_UartCtrlTx_l93; + reg _zz_io_txd; + `ifndef SYNTHESIS + reg [23:0] io_configFrame_stop_string; + reg [31:0] io_configFrame_parity_string; + reg [47:0] stateMachine_state_string; + `endif + + + assign _zz_clockDivider_counter_valueNext_1 = clockDivider_counter_willIncrement; + assign _zz_clockDivider_counter_valueNext = {2'd0, _zz_clockDivider_counter_valueNext_1}; + assign _zz_when_UartCtrlTx_l93_1 = ((io_configFrame_stop == UartStopType_ONE) ? 1'b0 : 1'b1); + assign _zz_when_UartCtrlTx_l93 = {2'd0, _zz_when_UartCtrlTx_l93_1}; + `ifndef SYNTHESIS + always @(*) begin + case(io_configFrame_stop) + UartStopType_ONE : io_configFrame_stop_string = "ONE"; + UartStopType_TWO : io_configFrame_stop_string = "TWO"; + default : io_configFrame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_configFrame_parity) + UartParityType_NONE : io_configFrame_parity_string = "NONE"; + UartParityType_EVEN : io_configFrame_parity_string = "EVEN"; + UartParityType_ODD : io_configFrame_parity_string = "ODD "; + default : io_configFrame_parity_string = "????"; + endcase + end + always @(*) begin + case(stateMachine_state) + UartCtrlTxState_IDLE : stateMachine_state_string = "IDLE "; + UartCtrlTxState_START : stateMachine_state_string = "START "; + UartCtrlTxState_DATA : stateMachine_state_string = "DATA "; + UartCtrlTxState_PARITY : stateMachine_state_string = "PARITY"; + UartCtrlTxState_STOP : stateMachine_state_string = "STOP "; + default : stateMachine_state_string = "??????"; + endcase + end + `endif + + always @(*) begin + clockDivider_counter_willIncrement = 1'b0; + if(io_samplingTick) begin + clockDivider_counter_willIncrement = 1'b1; + end + end + + assign clockDivider_counter_willClear = 1'b0; + assign clockDivider_counter_willOverflowIfInc = (clockDivider_counter_value == 3'b111); + assign clockDivider_counter_willOverflow = (clockDivider_counter_willOverflowIfInc && clockDivider_counter_willIncrement); + always @(*) begin + clockDivider_counter_valueNext = (clockDivider_counter_value + _zz_clockDivider_counter_valueNext); + if(clockDivider_counter_willClear) begin + clockDivider_counter_valueNext = 3'b000; + end + end + + always @(*) begin + stateMachine_txd = 1'b1; + case(stateMachine_state) + UartCtrlTxState_IDLE : begin + end + UartCtrlTxState_START : begin + stateMachine_txd = 1'b0; + end + UartCtrlTxState_DATA : begin + stateMachine_txd = io_write_payload[tickCounter_value]; + end + UartCtrlTxState_PARITY : begin + stateMachine_txd = stateMachine_parity; + end + default : begin + end + endcase + end + + always @(*) begin + io_write_ready = io_break; + case(stateMachine_state) + UartCtrlTxState_IDLE : begin + end + UartCtrlTxState_START : begin + end + UartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + io_write_ready = 1'b1; + end + end + end + UartCtrlTxState_PARITY : begin + end + default : begin + end + endcase + end + + assign when_UartCtrlTx_l58 = ((io_write_valid && (! io_cts)) && clockDivider_counter_willOverflow); + assign when_UartCtrlTx_l73 = (tickCounter_value == io_configFrame_dataLength); + assign when_UartCtrlTx_l76 = (io_configFrame_parity == UartParityType_NONE); + assign when_UartCtrlTx_l93 = (tickCounter_value == _zz_when_UartCtrlTx_l93); + assign io_txd = _zz_io_txd; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + clockDivider_counter_value <= 3'b000; + stateMachine_state <= UartCtrlTxState_IDLE; + _zz_io_txd <= 1'b1; + end else begin + clockDivider_counter_value <= clockDivider_counter_valueNext; + case(stateMachine_state) + UartCtrlTxState_IDLE : begin + if(when_UartCtrlTx_l58) begin + stateMachine_state <= UartCtrlTxState_START; + end + end + UartCtrlTxState_START : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_state <= UartCtrlTxState_DATA; + end + end + UartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + if(when_UartCtrlTx_l76) begin + stateMachine_state <= UartCtrlTxState_STOP; + end else begin + stateMachine_state <= UartCtrlTxState_PARITY; + end + end + end + end + UartCtrlTxState_PARITY : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_state <= UartCtrlTxState_STOP; + end + end + default : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l93) begin + stateMachine_state <= (io_write_valid ? UartCtrlTxState_START : UartCtrlTxState_IDLE); + end + end + end + endcase + _zz_io_txd <= (stateMachine_txd && (! io_break)); + end + end + + always @(posedge io_systemClk) begin + if(clockDivider_counter_willOverflow) begin + tickCounter_value <= (tickCounter_value + 3'b001); + end + if(clockDivider_counter_willOverflow) begin + stateMachine_parity <= (stateMachine_parity ^ stateMachine_txd); + end + case(stateMachine_state) + UartCtrlTxState_IDLE : begin + end + UartCtrlTxState_START : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_parity <= (io_configFrame_parity == UartParityType_ODD); + tickCounter_value <= 3'b000; + end + end + UartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + tickCounter_value <= 3'b000; + end + end + end + UartCtrlTxState_PARITY : begin + if(clockDivider_counter_willOverflow) begin + tickCounter_value <= 3'b000; + end + end + default : begin + end + endcase + end + + +endmodule + +module BufferCC_1 ( + input io_dataIn, + output io_dataOut, + input io_systemClk, + input debugCd_logic_outputReset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + initial begin + `ifndef SYNTHESIS + buffers_0 = $urandom; + buffers_1 = $urandom; + `endif + end + + assign io_dataOut = buffers_1; + always @(posedge io_systemClk) begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + + +endmodule + +module BufferCC ( + input io_dataIn, + output io_dataOut, + input io_systemClk, + input systemCd_logic_outputReset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge io_systemClk) begin + if(systemCd_logic_outputReset) begin + buffers_0 <= 1'b0; + buffers_1 <= 1'b0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule diff --git a/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol0.bin b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol0.bin new file mode 100644 index 0000000..c68d3c6 --- /dev/null +++ b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol0.bin @@ -0,0 +1,8192 @@ +10010111 +10010011 +00010011 +00010011 +10010011 +00010011 +01100011 +10000011 +00100011 +00010011 +10010011 +11100011 +00010011 +10010011 +01100011 +00100011 +00010011 +11100011 +11101111 +11101111 +01101111 +01100111 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +01101111 +00110111 +10110111 +00010011 +10000011 +10110011 +11100011 +00010011 +00100011 +01100111 +00010011 +00100011 +10110111 +00010011 +00100011 +00100011 +00100011 +00100011 +00100011 +00110111 +10110111 +00010011 +10000011 +10110011 +11100011 +10110111 +10010011 +00110111 +00100011 +00010011 +10110111 +10000011 +10110011 +11100011 +10110111 +10010011 +00100011 +00010011 +11101111 +00110111 +10110111 +00010011 +10000011 +10110011 +11100011 +10110111 +10010011 +00100011 +10110111 +00000011 +10110111 +10010011 +00110011 +10110111 +10000011 +10110011 +11100011 +00110111 +10110111 +00010011 +10000011 +10110011 +11100011 +10110111 +10010011 +00100011 +00010011 +11101111 +00010011 +11101111 +00010011 +11101111 +00010011 +11101111 +00010011 +11101111 +00110111 +00110111 +10110111 +10110111 +00010011 +00010011 +00010011 +10000011 +10110011 +11100011 +00100011 +10000011 +10010011 +11100011 +00000011 +10010011 +00100011 +01100011 +00110111 +10110111 +00010011 +10000011 +10110011 +11100011 +10110111 +10010011 +00100011 +00001111 +00010011 +00010011 +00010011 +00010011 +00010011 +00010011 +10000011 +00110111 +00010011 +01100111 +10010011 +01101111 +00010011 +00100011 +00100011 +00010011 +00010011 +00110011 +00100011 +00100011 +00010011 +01100011 +10010011 +10000011 +10010011 +00010011 +11100111 +11100011 +00010011 +00010011 +00110011 +00010011 +01100011 +10010011 +10000011 +10010011 +00010011 +11100111 +11100011 +10000011 +00000011 +10000011 +00000011 +00010011 +01100111 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol1.bin b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol1.bin new file mode 100644 index 0000000..3951424 --- /dev/null +++ b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol1.bin @@ -0,0 +1,8192 @@ +10000001 +10000001 +10000001 +10000101 +10000101 +10000110 +11111100 +00100010 +10100000 +00000101 +10000101 +11101000 +10000101 +10000101 +01111000 +00100000 +00000101 +01101100 +01110000 +01110000 +00000000 +10000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000111 +01000110 +00000111 +10100111 +11110111 +10001100 +01100101 +10100000 +10000000 +00000001 +00100110 +01000111 +00000111 +10100100 +10100000 +10100010 +10100100 +10100110 +00000111 +01000110 +00000111 +10100111 +11110111 +10001100 +00010111 +10000111 +00000111 +10100000 +00000111 +01000110 +10100111 +11110111 +10001100 +00010111 +10000111 +10100000 +00000101 +11110000 +00000111 +01000110 +00000111 +10100111 +11110111 +10001100 +00010111 +10000111 +10100000 +11000111 +10100111 +01010111 +10000111 +00000111 +11000110 +10100111 +00000111 +11011100 +00000111 +01000110 +00000111 +10100111 +11110111 +10001100 +00010111 +10000111 +10100000 +00000101 +11110000 +00000101 +11110000 +00000101 +11110000 +00000101 +11110000 +00000101 +11110000 +00000110 +10000111 +00000110 +01000111 +00000110 +00001000 +00000111 +10100101 +11110101 +10001100 +10100000 +10100101 +11010101 +10001100 +10100101 +10000101 +10000000 +10011010 +00000111 +01000110 +00000111 +10100111 +11110111 +10001100 +00010111 +10000111 +10100000 +00010000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00100000 +00000011 +00000001 +00000000 +10000110 +11110000 +00000001 +00100100 +00100000 +10000100 +10001001 +00001001 +00100110 +00100010 +01011001 +00001110 +00000100 +00100111 +10000100 +00000100 +10000000 +00011000 +10000100 +10001001 +00001001 +01011001 +00001110 +00000100 +00100111 +10000100 +00000100 +10000000 +00011000 +00100000 +00100100 +00100100 +00101001 +00000001 +10000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol2.bin b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol2.bin new file mode 100644 index 0000000..93fa610 --- /dev/null +++ b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol2.bin @@ -0,0 +1,8192 @@ +00000000 +10000001 +01000001 +11000001 +11000001 +01000001 +11000101 +00000101 +01010101 +01000101 +01000101 +11000101 +01000001 +10000001 +10110101 +00000101 +01000101 +10110101 +10010000 +01010000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +10000000 +00000001 +00000001 +11110111 +01000110 +11100111 +00000111 +00000101 +10100110 +00000000 +00000001 +00010001 +00000001 +00100000 +00000111 +11100111 +11100111 +11100111 +11100111 +00000001 +00000001 +11110111 +01000110 +11100111 +00000111 +00000000 +00000111 +00000001 +11110110 +11110111 +00000001 +01000110 +11100111 +00000111 +00000000 +00000111 +11110110 +10110000 +11011111 +00000001 +00000001 +11110111 +01000110 +11100111 +00000111 +00000000 +00000111 +11110110 +10110000 +10000111 +00000000 +00000111 +11110111 +10110000 +10000110 +11110111 +00000111 +00000001 +00000001 +11110111 +01000110 +11100111 +00000111 +00000000 +00000111 +11110110 +10110000 +10011111 +10000000 +00011111 +00000000 +10011111 +00000000 +00011111 +00000000 +10011111 +00000001 +00000000 +00000000 +00000001 +11110110 +00000000 +00000111 +01000111 +11000101 +00000101 +00000111 +01000111 +00000101 +00000101 +00000111 +00010110 +10100110 +11100101 +00000001 +00000001 +11110111 +01000110 +11100111 +00000111 +00000000 +00000111 +11110110 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11000001 +00000000 +00000001 +00000011 +00000101 +00011111 +00000001 +10000001 +00100001 +11000001 +11000001 +10001001 +00010001 +10010001 +00101001 +00001001 +00000000 +00000100 +00010100 +01000100 +00000111 +10011001 +11000001 +11000001 +10001001 +00101001 +00001001 +00000000 +00000100 +00010100 +01000100 +00000111 +10011001 +11000001 +10000001 +01000001 +00000001 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol3.bin b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol3.bin new file mode 100644 index 0000000..5c4a759 --- /dev/null +++ b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/source/hardware/netlist/EfxSapphireSoc.v_toplevel_system_ramA_logic_ram_symbol3.bin @@ -0,0 +1,8192 @@ +00000000 +01100100 +10001001 +10000000 +10000000 +10000001 +00000000 +00000000 +00000000 +00000000 +00000000 +11111110 +10000001 +10000001 +00000000 +00000000 +00000000 +11111110 +01011000 +00111011 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000010 +00000000 +11111000 +11111111 +00000000 +00000000 +11111110 +00010000 +00000000 +00000000 +11111111 +00000000 +11111000 +00000000 +00000000 +00000010 +00000010 +00000010 +00000010 +00000000 +11111000 +11111111 +00000000 +00000000 +11111110 +00000000 +10000000 +00000000 +00000000 +11111111 +11111000 +00000000 +00000000 +11111110 +00000000 +10001000 +00000000 +00001010 +11110110 +00000000 +11111000 +11111111 +00000000 +00000000 +11111110 +00000000 +10000000 +00000000 +11111000 +11111111 +00000000 +11100010 +00000000 +11111000 +11111111 +01000000 +11111110 +00000000 +11111000 +11111111 +00000000 +00000000 +11111110 +00000000 +10001000 +00000000 +00000000 +11101111 +00000011 +11101111 +00000000 +11101110 +00000000 +11101110 +00000000 +11101101 +00000000 +11111001 +11111001 +11111000 +11111111 +00100000 +11000000 +00000000 +00000000 +11111110 +00000001 +00000000 +00000001 +11111110 +00000000 +00000000 +00000000 +00000100 +00000000 +11111000 +11111111 +00000000 +00000000 +11111110 +00000000 +10000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111001 +00000001 +00000000 +00000000 +11111000 +11111111 +00000000 +00000001 +10000000 +10000000 +01000000 +00000000 +00000000 +01000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111110 +10000000 +10000000 +01000000 +01000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +11111110 +00000000 +00000000 +00000000 +00000000 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/source/soc_config b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/source/soc_config new file mode 100644 index 0000000..d77dacb --- /dev/null +++ b/fpga/ip/gTSE/Ti60F225_devkit/ip/sapphire/source/soc_config @@ -0,0 +1,23 @@ +--ramHex "/projects/SSE/kmlau/install/efinity/2022.1/ipm/ip/efx_soc/efx_soc/generator/bootloader/bootloader_32K.hex" +--cpuCount 1 +--spi name=system_spi_0_io,address=0x014000,interruptId=4,width=8,ssCount=1 +--Fpu false +--uart name=system_uart_0_io,address=0x010000,interruptId=1 +--L1I true +--dCacheSize 4096 +--axiAEnable false +--onChipRamSize 0x8000 +--iCacheWays 1 +--apbSlave name=io_apbSlave_0,address=0x100000,size=65536 +--ddrAEnable false +--iCacheSize 4096 +--onChipRamAddress 0xf9000000 +--Atomic false +--PeripheralClock false +--softTap false +--customInstruction false +--apbBridgeAddress 0xf8000000 +--L1D true +--Linux false +--dCacheWays 1 +--systemFrequency 50000000 diff --git a/fpga/ip/gTSE/Ti60F225_devkit/mac_pat_gen.v b/fpga/ip/gTSE/Ti60F225_devkit/mac_pat_gen.v new file mode 100644 index 0000000..64c5fed --- /dev/null +++ b/fpga/ip/gTSE/Ti60F225_devkit/mac_pat_gen.v @@ -0,0 +1,241 @@ +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / +// / / .' / +// __/ /.' / +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* +`timescale 1 ns / 1 ns +module mac_pat_gen +( +//Globle Signals +input clk, +input rstn, +//Control Interface +input pat_gen_en, +input [15:0] pat_gen_num,//When value is 0, it's infinite mode +input [15:0] pat_gen_ipg, +//MAC Protocol Signals +input [47:0] dst_mac, +input [47:0] src_mac, +input [15:0] mac_dlen, +//AXI4-Stream Interface +input rclk, +input rrstn, +input [7:0] rdata, +input rvalid, +input rlast, + +output reg [7:0] tdata, +output reg tvalid, +output reg tlast, +input tready +); + +// Parameter Define +localparam IDLE = 2'h0; +localparam PAT_IPG = 2'h1; +localparam PAT_GEN = 2'h2; + +// Register Define +reg pat_gen_en_dl1; +reg pat_gen_en_dl2; +reg [1:0] cur_state; +reg [1:0] next_state; +reg pat_en; +reg infinite_en; +reg [15:0] num_cnt; +reg [15:0] ipg_cnt; +reg [15:0] pat_cnt; + +reg [15:0] pat_gen_num_r; +reg [15:0] pat_gen_ipg_r; +reg [47:0] dst_mac_r; +reg [47:0] src_mac_r; +reg [15:0] mac_dlen_r; + +// Wire Define + +/*----------------------------------------------------------------------------------*\ + The main code +\*----------------------------------------------------------------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) begin + pat_gen_num_r <= 16'h0; + pat_gen_ipg_r <= 16'h0; + dst_mac_r <= 48'h0; + src_mac_r <= 48'h0; + mac_dlen_r <= 16'h0; + end + else begin + pat_gen_num_r <= pat_gen_num; + pat_gen_ipg_r <= pat_gen_ipg; + dst_mac_r <= dst_mac; + src_mac_r <= src_mac; + mac_dlen_r <= mac_dlen; + end +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + begin + pat_gen_en_dl1 <= 1'h0; + pat_gen_en_dl2 <= 1'h0; + end + else + begin + pat_gen_en_dl1 <= pat_gen_en; + pat_gen_en_dl2 <= pat_gen_en_dl1; + end +end + +/*----------------------- FSM Region ----------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + cur_state <= IDLE; + else + cur_state <= next_state; +end + +always @(*) + begin + case(cur_state) + IDLE : + if(pat_en == 1'b1) + next_state = PAT_GEN; + else + next_state = IDLE; + + PAT_IPG : + if((pat_en == 1'b1) || ((ipg_cnt == pat_gen_ipg_r) && (infinite_en == 1'b0) && (num_cnt == 16'h0))) + next_state = IDLE; + else if(ipg_cnt == pat_gen_ipg_r) + next_state = PAT_GEN; + else + next_state = PAT_IPG; + + PAT_GEN : + if((tlast == 1'b1) && (tready == 1'b1)) + next_state = PAT_IPG; + else + next_state = PAT_GEN; + + default : + next_state = IDLE; + endcase + end + +/*----------------------- Generator Control Region ----------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + pat_en <= 1'h0; + else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) + pat_en <= 1'h1; + else if((cur_state == IDLE) && (pat_en == 1'b1)) + pat_en <= 1'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + infinite_en <= 1'h0; + else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1) && (pat_gen_num_r == 16'h0)) + infinite_en <= 1'h1; + else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) + infinite_en <= 1'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + num_cnt <= 16'h0; + else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) + num_cnt <= pat_gen_num_r; + else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1) && (num_cnt != 16'h0)) + num_cnt <= num_cnt - 1'b1; +end + +/*----------------------- Pattern Counter Region ----------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ipg_cnt <= 16'h0; + else if(cur_state == PAT_IPG) + ipg_cnt <= ipg_cnt + 1'b1; + else + ipg_cnt <= 8'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + pat_cnt <= 16'h0; + else if(cur_state != PAT_GEN) + pat_cnt <= 16'h0; + else if(tready == 1'b1) + pat_cnt <= pat_cnt + 1'b1; +end + +/*----------------------- Pattern Generator Region ----------------------------*/ + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + tvalid <= 1'b0; + else if((cur_state == PAT_GEN) && (pat_cnt == 16'h0) && (tready == 1'b1)) + tvalid <= 1'b1; + else if((tready == 1'b1) && (tlast == 1'b1)) + tvalid <= 1'b0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + tdata <= 8'h0; + else if((cur_state == PAT_GEN) && (tready == 1'b1) && (pat_cnt <= 16'd14)) + case(pat_cnt[3:0]) + 4'd0 : tdata <= dst_mac_r[5*8 +: 8]; + 4'd1 : tdata <= dst_mac_r[4*8 +: 8]; + 4'd2 : tdata <= dst_mac_r[3*8 +: 8]; + 4'd3 : tdata <= dst_mac_r[2*8 +: 8]; + 4'd4 : tdata <= dst_mac_r[1*8 +: 8]; + 4'd5 : tdata <= dst_mac_r[0*8 +: 8]; + 4'd6 : tdata <= src_mac_r[5*8 +: 8]; + 4'd7 : tdata <= src_mac_r[4*8 +: 8]; + 4'd8 : tdata <= src_mac_r[3*8 +: 8]; + 4'd9 : tdata <= src_mac_r[2*8 +: 8]; + 4'd10 : tdata <= src_mac_r[1*8 +: 8]; + 4'd11 : tdata <= src_mac_r[0*8 +: 8]; + 4'd12 : tdata <= mac_dlen_r[15:8]; + 4'd13 : tdata <= mac_dlen_r[7:0]; + 4'd14 : tdata <= 8'h0;//MAC First Data + default : tdata <= tdata + 1'b1; + endcase + else if((cur_state == PAT_GEN) && (tready == 1'b1)) + tdata <= tdata + 1'b1; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + tlast <= 1'b0; + else if((tready == 1'b1) && (cur_state == PAT_GEN) && (pat_cnt == mac_dlen_r+16'd13)) + tlast <= 1'b1; + else if(tready == 1'b1) + tlast <= 1'b0; +end + +endmodule diff --git a/fpga/ip/gTSE/Ti60F225_devkit/mac_rx2tx.v b/fpga/ip/gTSE/Ti60F225_devkit/mac_rx2tx.v new file mode 100644 index 0000000..14508a7 --- /dev/null +++ b/fpga/ip/gTSE/Ti60F225_devkit/mac_rx2tx.v @@ -0,0 +1,139 @@ +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / +// / / .' / +// __/ /.' / +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* +`timescale 1 ns / 1 ns +module mac_rx2tx +( +//Globle Signals +// +//Receive AXI4-Stream Interface +input rx_axis_clk, +input rx_axis_rstn, +input [7:0] rx_axis_mac_tdata, +input rx_axis_mac_tvalid, +input rx_axis_mac_tlast, +input rx_axis_mac_tuser, +output reg rx_axis_mac_tready, +//Transmit AXI4-Stream Interface +input tx_axis_clk, +input tx_axis_rstn, +output reg [7:0] tx_axis_mac_tdata, +output reg tx_axis_mac_tvalid, +output reg tx_axis_mac_tlast, +output reg tx_axis_mac_tuser, +input tx_axis_mac_tready +); +// Parameter Define + +// Register Define + +// Wire Define +wire [9:0] u1_data; +wire u1_wrreq; +wire u1_rdreq; +wire [9:0] u1_q; +wire u1_empty; +wire u1_almfull; +wire [10:0] u1_wrcnt; + +/*----------------------------------------------------------------------------------*\ + The main code +\*----------------------------------------------------------------------------------*/ + +/*----------------------- Rx Clock Region ----------------------------*/ +assign u1_almfull = (u1_wrcnt >= 2045); + +always @(posedge rx_axis_clk or negedge rx_axis_rstn) +begin + if(rx_axis_rstn == 1'b0) + rx_axis_mac_tready <= 1'b0; + else if(u1_almfull == 1'b1) + rx_axis_mac_tready <= 1'b0; + else + rx_axis_mac_tready <= 1'b1; +end + +/*----------------------- Fifo 1 Region ----------------------------*/ +DC_FIFO #( + .FIFO_MODE ("ShowAhead" ), + .DATA_WIDTH (10 ), + .FIFO_DEPTH (2048 ) +) +u1 +( + //System Signal + .Reset (!rx_axis_rstn ), + //Write Signal + .WrClk (rx_axis_clk ), + .WrEn (u1_wrreq ), + .WrDNum (u1_wrcnt ), + .WrFull ( ), + .WrData (u1_data ), + //Read Signal + .RdClk (tx_axis_clk ), + .RdEn (u1_rdreq ), + .RdDNum ( ), + .RdEmpty (u1_empty ), + .RdData (u1_q ) +); + +assign u1_data = {rx_axis_mac_tuser,rx_axis_mac_tlast,rx_axis_mac_tdata}; +assign u1_wrreq = (rx_axis_mac_tvalid == 1'b1) && (rx_axis_mac_tready == 1'b1); +assign u1_rdreq = (u1_empty == 1'b0) && ((tx_axis_mac_tvalid == 1'b0) || (tx_axis_mac_tready == 1'b1)); + +/*----------------------- Tx Clock Region ----------------------------*/ + +always @(posedge tx_axis_clk or negedge tx_axis_rstn) +begin + if(tx_axis_rstn == 1'b0) + tx_axis_mac_tvalid <= 1'b0; + else if(u1_rdreq == 1'b1) + tx_axis_mac_tvalid <= 1'b1; + else if(tx_axis_mac_tready == 1'b1) + tx_axis_mac_tvalid <= 1'b0; +end + +always @(posedge tx_axis_clk or negedge tx_axis_rstn) +begin + if(tx_axis_rstn == 1'b0) + tx_axis_mac_tdata <= 8'h0; + else if(u1_rdreq == 1'b1) + tx_axis_mac_tdata <= u1_q[7:0]; + else if(tx_axis_mac_tready == 1'b1) + tx_axis_mac_tdata <= 8'h0; +end + +always @(posedge tx_axis_clk or negedge tx_axis_rstn) +begin + if(tx_axis_rstn == 1'b0) + tx_axis_mac_tlast <= 1'b0; + else if(u1_rdreq == 1'b1) + tx_axis_mac_tlast <= u1_q[8]; + else if(tx_axis_mac_tready == 1'b1) + tx_axis_mac_tlast <= 1'b0; +end + +always @(posedge tx_axis_clk or negedge tx_axis_rstn) +begin + if(tx_axis_rstn == 1'b0) + tx_axis_mac_tuser <= 1'b0; + else if((u1_rdreq == 1'b1) && (u1_q[8] == 1'b1)) + tx_axis_mac_tuser <= u1_q[9]; + else if(tx_axis_mac_tready == 1'b1) + tx_axis_mac_tuser <= 1'b0; +end + +endmodule diff --git a/fpga/ip/gTSE/Ti60F225_devkit/reg_apb3.v b/fpga/ip/gTSE/Ti60F225_devkit/reg_apb3.v new file mode 100644 index 0000000..3447897 --- /dev/null +++ b/fpga/ip/gTSE/Ti60F225_devkit/reg_apb3.v @@ -0,0 +1,333 @@ +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / +// / / .' / +// __/ /.' / +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* +`timescale 1 ns / 1 ns +module reg_apb3#( + parameter ADDR_WTH = 10 +) +( +//Globle Signals +// +//APB3 Slave Interface +input s_apb3_clk, +input s_apb3_rstn, +input [ADDR_WTH-1:0] s_apb3_paddr, +input s_apb3_psel, +input s_apb3_penable, +output reg s_apb3_pready, +input s_apb3_pwrite,//0:rd; 1:wr; +input [31:0] s_apb3_pwdata, +output reg [31:0] s_apb3_prdata, +output wire s_apb3_pslverror, +//Cfg Space Registers +//--Example Registers Field +output reg mac_sw_rst, +output reg axi4_st_mux_select, +output reg pat_mux_select, +output reg udp_pat_gen_en, +output reg mac_pat_gen_en, +output reg [15:0] pat_gen_num, +output reg [15:0] pat_gen_ipg, +output reg [47:0] pat_dst_mac, +output reg [47:0] pat_src_mac, +output reg [15:0] pat_mac_dlen, +output reg [31:0] pat_src_ip, +output reg [31:0] pat_dst_ip, +output reg [15:0] pat_src_port, +output reg [15:0] pat_dst_port, +output reg [15:0] pat_udp_dlen, +output reg [1:0] clkmux_sel +); +// Parameter Define + +// Register Define +reg [ADDR_WTH-3:0] loc_addr; +reg loc_wr_vld; +reg loc_rd_vld; + +// Wire Define + +/*----------------------------------------------------------------------------------*\ + The main code +\*----------------------------------------------------------------------------------*/ +//apb3 interface +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + loc_addr <= {ADDR_WTH-2{1'b0}}; + else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0)) + loc_addr <= s_apb3_paddr[2+:ADDR_WTH-2]; +end + +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + loc_wr_vld <= 1'b0; + else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b1)) + loc_wr_vld <= 1'b1; + else + loc_wr_vld <= 1'b0; +end + +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + loc_rd_vld <= 1'b0; + else if((s_apb3_psel == 1'b1) && (s_apb3_penable == 1'b0) && (s_apb3_pwrite == 1'b0)) + loc_rd_vld <= 1'b1; + else + loc_rd_vld <= 1'b0; +end + +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + s_apb3_pready <= 1'b0; + else if((loc_wr_vld == 1'b1) || (loc_rd_vld == 1'b1)) + s_apb3_pready <= 1'b1; + else + s_apb3_pready <= 1'b0; +end + +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + s_apb3_prdata <= 32'h0; + else if(loc_rd_vld == 1'b1) + begin + case(loc_addr) + //Example Registers Field + 'h080 : s_apb3_prdata <= {31'h0,mac_sw_rst}; + 'h081 : s_apb3_prdata <= {30'h0,pat_mux_select,axi4_st_mux_select}; + 'h082 : s_apb3_prdata <= {30'h0,mac_pat_gen_en,udp_pat_gen_en}; + 'h083 : s_apb3_prdata <= {pat_gen_ipg,pat_gen_num}; + 'h084 : s_apb3_prdata <= pat_dst_mac[31:0]; + 'h085 : s_apb3_prdata <= {16'h0,pat_dst_mac[47:32]}; + 'h086 : s_apb3_prdata <= pat_src_mac[31:0]; + 'h087 : s_apb3_prdata <= {16'h0,pat_src_mac[47:32]}; + 'h088 : s_apb3_prdata <= {16'h0,pat_mac_dlen}; + 'h089 : s_apb3_prdata <= pat_src_ip; + 'h08a : s_apb3_prdata <= pat_dst_ip; + 'h08b : s_apb3_prdata <= {pat_dst_port,pat_src_port}; + 'h08c : s_apb3_prdata <= {16'h0,pat_udp_dlen}; + 'h08d : s_apb3_prdata <= {30'h0,clkmux_sel}; + endcase + end +end + +assign s_apb3_pslverror = 1'b0; + +/*----------------------------------------------------------------------------------*\ + Register Space -- Example Registers Field +\*----------------------------------------------------------------------------------*/ +//loc_addr = 0x080; axi_addr = 0x200; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + mac_sw_rst <= 1'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h080)) + begin + mac_sw_rst <= s_apb3_pwdata[0]; + end +end + +//loc_addr = 0x081; axi_addr = 0x204; RW; +//[axi4_st_mux_select] 0:pat tx mode; 1:rx2tx loopback mode; +//[pat_mux_select] 0:udp pat; 1:mac pat; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + axi4_st_mux_select <= 1'h0; + pat_mux_select <= 1'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h081)) + begin + axi4_st_mux_select <= s_apb3_pwdata[0]; + pat_mux_select <= s_apb3_pwdata[1]; + end +end + +//loc_addr = 0x082; axi_addr = 0x208; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + udp_pat_gen_en <= 1'h0; + mac_pat_gen_en <= 1'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h082)) + begin + udp_pat_gen_en <= s_apb3_pwdata[0]; + mac_pat_gen_en <= s_apb3_pwdata[1]; + end +end + +//loc_addr = 0x083; axi_addr = 0x20c; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + pat_gen_num <= 16'h0; + pat_gen_ipg <= 16'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h083)) + begin + pat_gen_num <= s_apb3_pwdata[15:0]; + pat_gen_ipg <= s_apb3_pwdata[31:16]; + end +end + +//loc_addr = 0x084; axi_addr = 0x210; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + pat_dst_mac[31:0] <= 32'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h084)) + begin + pat_dst_mac[31:0] <= s_apb3_pwdata[31:0]; + end +end + +//loc_addr = 0x085; axi_addr = 0x214; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + pat_dst_mac[47:32] <= 16'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h085)) + begin + pat_dst_mac[47:32] <= s_apb3_pwdata[15:0]; + end +end + +//loc_addr = 0x086; axi_addr = 0x218; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + pat_src_mac[31:0] <= 32'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h086)) + begin + pat_src_mac[31:0] <= s_apb3_pwdata[31:0]; + end +end + +//loc_addr = 0x087; axi_addr = 0x21c; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + pat_src_mac[47:32] <= 16'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h087)) + begin + pat_src_mac[47:32] <= s_apb3_pwdata[15:0]; + end +end + +//loc_addr = 0x088; axi_addr = 0x220; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + pat_mac_dlen <= 16'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h088)) + begin + pat_mac_dlen <= s_apb3_pwdata[15:0]; + end +end + +//loc_addr = 0x089; axi_addr = 0x224; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + pat_src_ip <= 32'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h089)) + begin + pat_src_ip <= s_apb3_pwdata[31:0]; + end +end + +//loc_addr = 0x08a; axi_addr = 0x228; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + pat_dst_ip <= 32'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08a)) + begin + pat_dst_ip <= s_apb3_pwdata[31:0]; + end +end + +//loc_addr = 0x08b; axi_addr = 0x22c; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + pat_src_port <= 16'h0; + pat_dst_port <= 16'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08b)) + begin + pat_src_port <= s_apb3_pwdata[15:0]; + pat_dst_port <= s_apb3_pwdata[31:16]; + end +end + +//loc_addr = 0x08c; axi_addr = 0x230; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + pat_udp_dlen <= 16'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08c)) + begin + pat_udp_dlen <= s_apb3_pwdata[15:0]; + end +end + +//loc_addr = 0x08d; axi_addr = 0x234; RW; +always @(posedge s_apb3_clk or negedge s_apb3_rstn) +begin + if(s_apb3_rstn == 1'b0) + begin + clkmux_sel <= 2'h0; + end + else if((loc_wr_vld == 1'b1) && (loc_addr == 'h08d)) + begin + clkmux_sel <= s_apb3_pwdata[1:0]; + end +end + + +/*----------------------------------------------------------------------------------*\ + Register Space -- The End +\*----------------------------------------------------------------------------------*/ + +endmodule diff --git a/fpga/ip/gTSE/Ti60F225_devkit/rgmii_2_rmii.v b/fpga/ip/gTSE/Ti60F225_devkit/rgmii_2_rmii.v new file mode 100644 index 0000000..e7a1f19 --- /dev/null +++ b/fpga/ip/gTSE/Ti60F225_devkit/rgmii_2_rmii.v @@ -0,0 +1,206 @@ +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / +// / / .' / +// __/ /.' / +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`timescale 1 ns / 1 ns +module rgmii_2_rmii ( + input clk_50m, //50Mhz refclock + input rst_n, + //conduit + input [2:0] eth_speed, + //rgmii interface + input [3:0] rgmii_txd, + input rgmii_tx_ctl, + output wire [3:0] rgmii_rxd, + output wire rgmii_rx_ctl, + output reg rgmii_rxc, + //rmii interface + output wire rmii_clk, + output reg [1:0] rmii_txd, + output reg rmii_txen, + input [1:0] rmii_rxd, + input rmii_crsdv +); + +wire [3:0] rxd_c; +wire rx_ctl_c; +reg [3:0] rxd_r; +reg rx_ctl_r; +reg rmii_crsdv_r, shift_en; +reg [4:0] txd_cnt, rxd_cnt; +reg [3:0] rxd_shiftreg; +reg [1:0] shift2; +reg [19:0] shift20; +reg [1:0] rx_ctl_p2; +reg [19:0] rx_ctl_p20; + +assign rmii_clk = ~clk_50m; //create 180deg phaseshift + +/*--------------- TX path ---------------------*/ +always @(posedge clk_50m or negedge rst_n) +begin + if (!rst_n) begin + txd_cnt <= 5'd0; + end + else if (rgmii_tx_ctl) begin + if (((eth_speed == 3'h2) && txd_cnt == 5'd1) || + ((eth_speed == 3'h1) && txd_cnt == 5'd19)) begin + txd_cnt <= 5'd0; + end + else begin + txd_cnt <= txd_cnt + 5'd1; + end + end +end + +always @(posedge clk_50m or negedge rst_n) +begin + if (!rst_n) begin + rmii_txen <= 1'b0; + end + else begin + rmii_txen <= rgmii_tx_ctl; + end +end + +always @(posedge clk_50m or negedge rst_n) +begin + if (!rst_n) begin + rmii_txd <= 2'b00; + end + else begin + if ((eth_speed == 3'h2) && txd_cnt == 5'd0) begin + rmii_txd <= rgmii_txd[1:0]; + end + else if ((eth_speed == 3'h2) && txd_cnt == 5'd1) begin + rmii_txd <= rgmii_txd[3:2]; + end + + if ((eth_speed == 3'h1) && txd_cnt == 5'd0) begin + rmii_txd <= rgmii_txd[1:0]; + end + else if ((eth_speed == 3'h1) && txd_cnt == 5'd10) begin + rmii_txd <= rgmii_txd[3:2]; + end + end +end +/*------------------ end of TX path ------------------------*/ + +/*------------ RX path ------------------*/ +always @(posedge clk_50m or negedge rst_n) +begin + if (!rst_n) begin + rxd_cnt <= 5'd0; + end + else if (rmii_crsdv) begin + if (((eth_speed == 3'h2) && rxd_cnt == 5'd1) || ((eth_speed == 3'h1) && rxd_cnt == 5'd19)) begin + rxd_cnt <= 5'd0; + end + else begin + rxd_cnt <= rxd_cnt + 5'd1; + end + end +end + +always @(posedge clk_50m or negedge rst_n) +begin + if (!rst_n) begin + rxd_shiftreg <= 4'd0; + end + else if (rmii_crsdv) begin + if (eth_speed == 3'h2 || ((eth_speed == 3'h1) && (rxd_cnt == 5'd0 || rxd_cnt == 5'd10))) begin + rxd_shiftreg <= {rmii_rxd, rxd_shiftreg[3:2]}; + end + end +end + +always @(posedge clk_50m or negedge rst_n) +begin + if (!rst_n) begin + shift2 <= 2'b1; + shift20 <= 20'b1; + end + else begin + shift2 <= {shift2[0],shift2[1]}; + shift20 <= {shift20[18:0],shift20[19]}; + end +end + +always @(posedge clk_50m or negedge rst_n) +begin + if (!rst_n) begin + rgmii_rxc <= 1'b0; + end + else begin + if ((eth_speed == 3'h2 && shift2[1]) || (eth_speed == 3'h1 && (shift20[10]))) begin + rgmii_rxc <= 1'b1; + end + else if ((eth_speed == 3'h2 && shift2[0]) || (eth_speed == 3'h1 && (shift20[0]))) begin + rgmii_rxc <= 1'b0; + end + end +end + +always @(posedge clk_50m or negedge rst_n) +begin + if (!rst_n) begin + rx_ctl_p2 <= 2'd0; + rx_ctl_p20 <= 20'd0; + end + else begin + rx_ctl_p2 <= {rmii_crsdv , rx_ctl_p2[1]}; + rx_ctl_p20 <= {rmii_crsdv, rx_ctl_p20[19:1]}; + end +end + +/*---- shift rxd & rx_ctl so that they are not edge align with rgmii_rxc ----*/ +assign rxd_c = (rxd_cnt == 5'd0) ? rxd_shiftreg : rxd_r; +assign rx_ctl_c = (eth_speed == 3'h2) ? rx_ctl_p2[0] : rx_ctl_p20[0]; + +always @(posedge clk_50m or negedge rst_n) +begin + if (!rst_n) begin + rxd_r <= 4'd0; + rx_ctl_r <= 1'd0; + rmii_crsdv_r <= 1'd0; + end + else begin + rxd_r <= rxd_c; + rx_ctl_r <= rx_ctl_c; + rmii_crsdv_r <= rmii_crsdv; + end +end + +always @(posedge clk_50m or negedge rst_n) +begin + if (!rst_n) begin + shift_en <= 1'd0; + end // to detect if rmii_crsdv assert at the posedge of rgmii_rxc, delay rgmii_rxd & rgmii_rx_ctl if they are aligned with rgmii_rxc + else if (rmii_crsdv && ~rmii_crsdv_r) begin + if (((eth_speed == 3'h2) && shift2[0]) || ((eth_speed == 3'h1) && shift20[11])) begin + shift_en <= 1'd1; + end + else begin + shift_en <= 1'd0; + end + end +end + +assign rgmii_rxd = shift_en ? rxd_r : rxd_c; +assign rgmii_rx_ctl = shift_en ? rx_ctl_r : rx_ctl_c; +/*--------------------------------------------------------*/ +/*------------------ end of RX path ------------------------*/ +endmodule \ No newline at end of file diff --git a/fpga/ip/gTSE/Ti60F225_devkit/temac_ex.peri.xml b/fpga/ip/gTSE/Ti60F225_devkit/temac_ex.peri.xml new file mode 100644 index 0000000..bb6a41a --- /dev/null +++ b/fpga/ip/gTSE/Ti60F225_devkit/temac_ex.peri.xml @@ -0,0 +1,231 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/ip/gTSE/Ti60F225_devkit/temac_ex.v b/fpga/ip/gTSE/Ti60F225_devkit/temac_ex.v new file mode 100644 index 0000000..15d4a24 --- /dev/null +++ b/fpga/ip/gTSE/Ti60F225_devkit/temac_ex.v @@ -0,0 +1,563 @@ +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / +// / / .' / +// __/ /.' / +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* +`timescale 1 ns / 1 ns +//`include "header.v" // use JTAG hard block +module temac_ex +( +//Globle Signals +//----pll_0 +input clk, +input clk_125m, +input pll_0_locked, +input sw6, +output wire pll_rstn, + +//TEMAC PHY RGMII Interface +output wire [3:0] rgmii_txd_HI, +output wire [3:0] rgmii_txd_LO, +output wire rgmii_txc_HI, +output wire rgmii_txc_LO, +input [3:0] rgmii_rxd_HI, +input [3:0] rgmii_rxd_LO, +`ifdef TITANIUM + output wire rgmii_tx_ctl_HI, + output wire rgmii_tx_ctl_LO, + input rgmii_rx_ctl_HI, + input rgmii_rx_ctl_LO, + input mux_clk, + output [1:0] mux_clk_sw, +`else + input rgmii_rxc, + output wire rgmii_tx_ctl, + input rgmii_rx_ctl, +`endif +//TEMAC PHY Ctr Interface +output wire phy_rstn, +//hardware Jtag Interface +`ifndef SIM_MODE +`ifndef SOFT_TAP +input jtag_inst1_TCK, +input jtag_inst1_TDI, +output wire jtag_inst1_TDO, +input jtag_inst1_SEL, +input jtag_inst1_CAPTURE, +input jtag_inst1_SHIFT, +input jtag_inst1_UPDATE, +input jtag_inst1_RESET, +`else +//software Jtag Interface +input io_jtag_tms, +input io_jtag_tdi, +output wire io_jtag_tdo, +input io_jtag_tck, +`endif + +//Debug Signals +//output wire [1:0] debug_led +output wire system_uart_0_io_txd, +input system_uart_0_io_rxd, +`endif + +output system_spi_0_io_sclk_write, +output system_spi_0_io_data_0_writeEnable, +input system_spi_0_io_data_0_read, +output system_spi_0_io_data_0_write, +output system_spi_0_io_data_1_writeEnable, +input system_spi_0_io_data_1_read, +output system_spi_0_io_data_1_write, +output system_spi_0_io_ss, + +//TEMAC PHY MDIO Interface +input phy_mdi, +output wire phy_mdo, +output wire phy_mdo_en, +output wire phy_mdc +); +// Parameter Define +`include "gTSE_define.svh" + +// Register Define + +// Wire Define +wire clk_50m; +wire clk_50m_rstn; +wire mac_reset; +wire proto_reset; +wire mac_rstn; +//AXI4-Stream Interface +wire rx_axis_clk; +wire [7:0] rx_axis_mac_tdata; +wire rx_axis_mac_tvalid; +wire rx_axis_mac_tlast; +wire rx_axis_mac_tuser; +wire rx_axis_mac_tready; +wire tx_axis_clk; +wire [7:0] tx_axis_mac_tdata; +wire tx_axis_mac_tvalid; +wire tx_axis_mac_tlast; +wire tx_axis_mac_tuser; +wire tx_axis_mac_tready; +wire [7:0] udp_tx_axis_mac_tdata; +wire udp_tx_axis_mac_tvalid; +wire udp_tx_axis_mac_tlast; +wire udp_tx_axis_mac_tready; +wire [7:0] mac_tx_axis_mac_tdata; +wire mac_tx_axis_mac_tvalid; +wire mac_tx_axis_mac_tlast; +wire mac_tx_axis_mac_tready; +wire [7:0] pat_tx_axis_mac_tdata; +wire pat_tx_axis_mac_tvalid; +wire pat_tx_axis_mac_tlast; +wire pat_tx_axis_mac_tuser; +wire pat_tx_axis_mac_tready; +wire [7:0] loop_tx_axis_mac_tdata; +wire loop_tx_axis_mac_tvalid; +wire loop_tx_axis_mac_tlast; +wire loop_tx_axis_mac_tuser; +wire loop_tx_axis_mac_tready; +//RiscV APB3 Interface +wire [15:0] apb3_paddr; +wire apb3_psel; +wire apb3_penable; +wire apb3_pready; +wire apb3_pwrite; +wire [31:0] apb3_pwdata; +wire [31:0] apb3_prdata; +wire apb3_pslverror; +//Mac APB3 Interface +wire [9:0] mac_apb3_paddr; +wire mac_apb3_psel; +wire mac_apb3_penable; +wire mac_apb3_pready; +wire mac_apb3_pwrite; +wire [31:0] mac_apb3_pwdata; +wire [31:0] mac_apb3_prdata; +wire mac_apb3_pslverror; +//Ex APB3 Interface +wire [9:0] ex_apb3_paddr; +wire ex_apb3_psel; +wire ex_apb3_penable; +wire ex_apb3_pready; +wire ex_apb3_pwrite; +wire [31:0] ex_apb3_pwdata; +wire [31:0] ex_apb3_prdata; +wire ex_apb3_pslverror; +//AXI4-Lite Interface +wire [9:0] axi_awaddr; +wire axi_awvalid; +wire axi_awready; +wire [31:0] axi_wdata; +wire axi_wvalid; +wire axi_wready; +wire [1:0] axi_bresp; +wire axi_bvalid; +wire axi_bready; +wire [9:0] axi_araddr; +wire axi_arvalid; +wire axi_arready; +wire [1:0] axi_rresp; +wire [31:0] axi_rdata; +wire axi_rvalid; +wire axi_rready; +//Cfg Space Registers +wire mac_sw_rst; +wire axi4_st_mux_select; +wire pat_mux_select; +wire udp_pat_gen_en; +wire mac_pat_gen_en; +wire [15:0] pat_gen_num; +wire [15:0] pat_gen_ipg; +wire [47:0] pat_dst_mac; +wire [47:0] pat_src_mac; +wire [15:0] pat_mac_dlen; +wire [31:0] pat_src_ip; +wire [31:0] pat_dst_ip; +wire [15:0] pat_src_port; +wire [15:0] pat_dst_port; +wire [15:0] pat_udp_dlen; + +//TSE DDIO +`ifdef TITANIUM + wire rgmii_rxc; + + assign rgmii_rxc = mux_clk; +`else + wire rgmii_rx_ctl_LO; + wire rgmii_rx_ctl_HI; + wire rgmii_tx_ctl_LO; + wire rgmii_tx_ctl_HI; + + assign rgmii_tx_ctl = rgmii_tx_ctl_HI | rgmii_tx_ctl_LO ; + assign rgmii_rx_ctl_HI = rgmii_rx_ctl ; + assign rgmii_rx_ctl_LO = rgmii_rx_ctl ; +`endif +/*----------------------------------------------------------------------------------*\ + The main code +\*----------------------------------------------------------------------------------*/ +assign pll_rstn = 1; +/*----------------------- Clock Region -----------------------*/ +//In full throughput usecase, rx_axis_clk and tx_axis_clk should be set to 125Mhz or above. +//In this example design, these clocks are set to 50Mhz because the UDP/MAC pattern generator has +//high combi logic and couldn't meet timing at 125Mhz. +assign rx_axis_clk = clk;//clk_125m; +assign tx_axis_clk = clk;//clk_125m; + + +/*----------------------- Reset Region -----------------------*/ +//assign pll_0_reset = 1'b0; +assign clk_50m = clk; +assign phy_rstn = sw6; +assign clk_50m_rstn = pll_0_locked; +assign mac_reset = ~pll_0_locked; +assign proto_reset = mac_sw_rst; +assign mac_rstn = ~(mac_reset || proto_reset); + +/*----------------------- MCU Module ----------------------------*/ +`ifndef SIM_MODE +sapphire u_mcu +( +//user custom ports + //SOC + .io_systemClk (clk_50m ), + .io_asyncReset (1'b0 ), + .system_uart_0_io_txd (system_uart_0_io_txd ), + .system_uart_0_io_rxd (system_uart_0_io_rxd ), + .system_spi_0_io_sclk_write (system_spi_0_io_sclk_write ), + .system_spi_0_io_data_0_writeEnable (system_spi_0_io_data_0_writeEnable ), + .system_spi_0_io_data_0_read (system_spi_0_io_data_0_read ), + .system_spi_0_io_data_0_write (system_spi_0_io_data_0_write ), + .system_spi_0_io_data_1_writeEnable (system_spi_0_io_data_1_writeEnable ), + .system_spi_0_io_data_1_read (system_spi_0_io_data_1_read ), + .system_spi_0_io_data_1_write (system_spi_0_io_data_1_write ), + .system_spi_0_io_ss (system_spi_0_io_ss ), + .jtagCtrl_tck (jtag_inst1_TCK ), + .jtagCtrl_tdi (jtag_inst1_TDI ), + .jtagCtrl_tdo (jtag_inst1_TDO ), + .jtagCtrl_enable (jtag_inst1_SEL ), + .jtagCtrl_capture (jtag_inst1_CAPTURE ), + .jtagCtrl_shift (jtag_inst1_SHIFT ), + .jtagCtrl_update (jtag_inst1_UPDATE ), + .jtagCtrl_reset (jtag_inst1_RESET ), +//APB3 Master Interface + .io_apbSlave_0_PADDR (apb3_paddr ), + .io_apbSlave_0_PSEL (apb3_psel ), + .io_apbSlave_0_PENABLE (apb3_penable ), + .io_apbSlave_0_PREADY (apb3_pready ), + .io_apbSlave_0_PWRITE (apb3_pwrite ), + .io_apbSlave_0_PWDATA (apb3_pwdata ), + .io_apbSlave_0_PRDATA (apb3_prdata ), + .io_apbSlave_0_PSLVERROR (apb3_pslverror ) +); +`endif + +assign apb3_pready = (apb3_paddr[9] == 1'b0) ? mac_apb3_pready : ex_apb3_pready; +assign apb3_prdata = (apb3_paddr[9] == 1'b0) ? mac_apb3_prdata : ex_apb3_prdata; +assign apb3_pslverror = (apb3_paddr[9] == 1'b0) ? mac_apb3_pslverror : ex_apb3_pslverror; + +assign mac_apb3_paddr = apb3_paddr[9:0]; +assign mac_apb3_psel = (apb3_paddr[9] == 1'b0) ? apb3_psel : 1'b0; +assign mac_apb3_penable = apb3_penable; +assign mac_apb3_pwrite = apb3_pwrite; +assign mac_apb3_pwdata = apb3_pwdata; + +assign ex_apb3_paddr = apb3_paddr[9:0]; +assign ex_apb3_psel = (apb3_paddr[9] == 1'b1) ? apb3_psel : 1'b0; +assign ex_apb3_penable = apb3_penable; +assign ex_apb3_pwrite = apb3_pwrite; +assign ex_apb3_pwdata = apb3_pwdata; + +apb3_2_axi4_lite#( + .ADDR_WTH (10 ) +) +u_apb3_2_axi4_lite +( +//Globle Signals + .clk (clk_50m ), + .rstn (clk_50m_rstn ), +//APB3 Slave Interface + .s_apb3_paddr (mac_apb3_paddr ), + .s_apb3_psel (mac_apb3_psel ), + .s_apb3_penable (mac_apb3_penable ), + .s_apb3_pready (mac_apb3_pready ), + .s_apb3_pwrite (mac_apb3_pwrite ), + .s_apb3_pwdata (mac_apb3_pwdata ), + .s_apb3_prdata (mac_apb3_prdata ), + .s_apb3_pslverror (mac_apb3_pslverror ), +//AXI4-Lite Master Interface + .m_axi_awaddr (axi_awaddr ), + .m_axi_awvalid (axi_awvalid ), + .m_axi_awready (axi_awready ), + .m_axi_wdata (axi_wdata ), + .m_axi_wvalid (axi_wvalid ), + .m_axi_wready (axi_wready ), + .m_axi_bresp (axi_bresp ), + .m_axi_bvalid (axi_bvalid ), + .m_axi_bready (axi_bready ), + .m_axi_araddr (axi_araddr ), + .m_axi_arvalid (axi_arvalid ), + .m_axi_arready (axi_arready ), + .m_axi_rresp (axi_rresp ), + .m_axi_rdata (axi_rdata ), + .m_axi_rvalid (axi_rvalid ), + .m_axi_rready (axi_rready ) +); + +reg_apb3#( + .ADDR_WTH (10 ) +) +u_reg_apb3 +( +//Globle Signals +// +//APB3 Slave Interface + .s_apb3_clk (clk_50m ), + .s_apb3_rstn (clk_50m_rstn ), + .s_apb3_paddr (ex_apb3_paddr ), + .s_apb3_psel (ex_apb3_psel ), + .s_apb3_penable (ex_apb3_penable ), + .s_apb3_pready (ex_apb3_pready ), + .s_apb3_pwrite (ex_apb3_pwrite ), + .s_apb3_pwdata (ex_apb3_pwdata ), + .s_apb3_prdata (ex_apb3_prdata ), + .s_apb3_pslverror (ex_apb3_pslverror ), +//Cfg Space Registers +//--Example Registers Field + .mac_sw_rst (mac_sw_rst ), + .axi4_st_mux_select (axi4_st_mux_select ), + .pat_mux_select (pat_mux_select ), + .udp_pat_gen_en (udp_pat_gen_en ), + .mac_pat_gen_en (mac_pat_gen_en ), + .pat_gen_num (pat_gen_num ), + .pat_gen_ipg (pat_gen_ipg ), + .pat_dst_mac (pat_dst_mac ), + .pat_src_mac (pat_src_mac ), + .pat_mac_dlen (pat_mac_dlen ), + .pat_src_ip (pat_src_ip ), + .pat_dst_ip (pat_dst_ip ), + .pat_src_port (pat_src_port ), + .pat_dst_port (pat_dst_port ), + .pat_udp_dlen (pat_udp_dlen ), + .clkmux_sel (mux_clk_sw ) +); + +//generate if (PATTERN_TYPE == 0) begin //UDP +// +//assign mac_tx_axis_mac_tdata = 8'h0; +//assign mac_tx_axis_mac_tvalid = 1'b0; +//assign mac_tx_axis_mac_tlast = 1'b0; + +/*----------------------- The Ethernet Pattern Module -----------------------*/ +udp_pat_gen u_udp_pat_gen +( +//Globle Signals + .clk (tx_axis_clk ), + .rstn (mac_rstn ), +//Control Interface + .pat_gen_en (udp_pat_gen_en ), + .pat_gen_num (pat_gen_num ), + .pat_gen_ipg (pat_gen_ipg ), +//MAC Protocol Signals + .dst_mac (pat_dst_mac ), + .src_mac (pat_src_mac ), +//IP Protocol Signals + .src_ip (pat_src_ip ), + .dst_ip (pat_dst_ip ), +//UDP Protocol Signals + .src_port (pat_src_port ), + .dst_port (pat_dst_port ), + .udp_dlen (pat_udp_dlen ), +//AXI4-Stream Interface + .rclk (rx_axis_clk ), + .rrstn (mac_rstn ), + .rdata (rx_axis_mac_tdata ), + .rvalid (rx_axis_mac_tvalid ), + .rlast (rx_axis_mac_tlast ), + .tdata (udp_tx_axis_mac_tdata ), + .tvalid (udp_tx_axis_mac_tvalid ), + .tlast (udp_tx_axis_mac_tlast ), + .tready (udp_tx_axis_mac_tready ) +); +//end +//else begin //MAC +// +//assign udp_tx_axis_mac_tdata = 8'h0; +//assign udp_tx_axis_mac_tvalid = 1'b0; +//assign udp_tx_axis_mac_tlast = 1'b0; + +mac_pat_gen u_mac_pat_gen +( +//Globle Signals + .clk (tx_axis_clk ), + .rstn (mac_rstn ), +//Control Interface + .pat_gen_en (mac_pat_gen_en ), + .pat_gen_num (pat_gen_num ), + .pat_gen_ipg (pat_gen_ipg ), +//MAC Protocol Signals + .dst_mac (pat_dst_mac ), + .src_mac (pat_src_mac ), + .mac_dlen (pat_mac_dlen ), +//AXI4-Stream Interface + .rclk (rx_axis_clk ), + .rrstn (mac_rstn ), + .rdata (rx_axis_mac_tdata ), + .rvalid (rx_axis_mac_tvalid ), + .rlast (rx_axis_mac_tlast ), + .tdata (mac_tx_axis_mac_tdata ), + .tvalid (mac_tx_axis_mac_tvalid ), + .tlast (mac_tx_axis_mac_tlast ), + .tready (mac_tx_axis_mac_tready ) +); +//end +//endgenerate + +axi4_st_mux u_pat_mux +( +//Globle Signals + .mux_select (pat_mux_select ),//0:udp pat; 1:mac pat; +//Mux In 0 Interface + .tdata0 (udp_tx_axis_mac_tdata ), + .tvalid0 (udp_tx_axis_mac_tvalid ), + .tlast0 (udp_tx_axis_mac_tlast ), + .tuser0 (1'b0 ), + .tready0 (udp_tx_axis_mac_tready ), +//Mux In 1 Interface + .tdata1 (mac_tx_axis_mac_tdata ), + .tvalid1 (mac_tx_axis_mac_tvalid ), + .tlast1 (mac_tx_axis_mac_tlast ), + .tuser1 (1'b0 ), + .tready1 (mac_tx_axis_mac_tready ), +//Mux Out Interface + .tdata (pat_tx_axis_mac_tdata ), + .tvalid (pat_tx_axis_mac_tvalid ), + .tlast (pat_tx_axis_mac_tlast ), + .tuser (pat_tx_axis_mac_tuser ), + .tready (pat_tx_axis_mac_tready ) +); + +/*----------------------- The Tx AXI4 St Mux Module -----------------------*/ +axi4_st_mux u_tx_axi4st_mux +( +//Globle Signals + .mux_select (axi4_st_mux_select ),//0:pat; 1:rx2tx loopback; +//Mux In 0 Interface + .tdata0 (pat_tx_axis_mac_tdata ), + .tvalid0 (pat_tx_axis_mac_tvalid ), + .tlast0 (pat_tx_axis_mac_tlast ), + .tuser0 (pat_tx_axis_mac_tuser ), + .tready0 (pat_tx_axis_mac_tready ), +//Mux In 1 Interface + .tdata1 (loop_tx_axis_mac_tdata ), + .tvalid1 (loop_tx_axis_mac_tvalid ), + .tlast1 (loop_tx_axis_mac_tlast ), + .tuser1 (loop_tx_axis_mac_tuser ), + .tready1 (loop_tx_axis_mac_tready ), +//Mux Out Interface + .tdata (tx_axis_mac_tdata ), + .tvalid (tx_axis_mac_tvalid ), + .tlast (tx_axis_mac_tlast ), + .tuser (tx_axis_mac_tuser ), + .tready (tx_axis_mac_tready ) +); + +/*----------------------- The Tri-mode Ethernet MAC core -----------------------*/ +gTSE u_tsemac +( +//Globle Signals + .mac_reset (mac_reset ), + .proto_reset (proto_reset ), + .tx_mac_aclk (clk_125m ), + .rx_mac_aclk ( ), + .eth_speed ( ), +//Receive AXI4-Stream Interface + .rx_axis_clk (rx_axis_clk ), + .rx_axis_mac_tdata (rx_axis_mac_tdata ), + .rx_axis_mac_tvalid (rx_axis_mac_tvalid ), + .rx_axis_mac_tlast (rx_axis_mac_tlast ), + .rx_axis_mac_tstrb (), + .rx_axis_mac_tuser (rx_axis_mac_tuser ), + .rx_axis_mac_tready (rx_axis_mac_tready ), +//Transmit AXI4-Stream Interface + .tx_axis_clk (tx_axis_clk ), + .tx_axis_mac_tdata (tx_axis_mac_tdata ), + .tx_axis_mac_tvalid (tx_axis_mac_tvalid ), + .tx_axis_mac_tlast (tx_axis_mac_tlast ), + .tx_axis_mac_tstrb (1'b1 ), + .tx_axis_mac_tuser (tx_axis_mac_tuser ), + .tx_axis_mac_tready (tx_axis_mac_tready ), + //--RGMII Interface + .rgmii_txd_HI (rgmii_txd_HI ), + .rgmii_txd_LO (rgmii_txd_LO ), + .rgmii_tx_ctl_HI (rgmii_tx_ctl_HI ), + .rgmii_tx_ctl_LO (rgmii_tx_ctl_LO ), + .rgmii_txc_HI (rgmii_txc_HI ), + .rgmii_txc_LO (rgmii_txc_LO ), + .rgmii_rxd_HI (rgmii_rxd_HI ), + .rgmii_rxd_LO (rgmii_rxd_LO ), + .rgmii_rx_ctl_HI (rgmii_rx_ctl_HI ), + .rgmii_rx_ctl_LO (rgmii_rx_ctl_LO ), + .rgmii_rxc (rgmii_rxc ), + //AXI4-Lite Interface + .s_axi_aclk (clk_50m ), + .s_axi_awaddr (axi_awaddr ), + .s_axi_awvalid (axi_awvalid ), + .s_axi_awready (axi_awready ), + .s_axi_wdata (axi_wdata ), + .s_axi_wvalid (axi_wvalid ), + .s_axi_wready (axi_wready ), + .s_axi_bresp (axi_bresp ), + .s_axi_bvalid (axi_bvalid ), + .s_axi_bready (axi_bready ), + .s_axi_araddr (axi_araddr ), + .s_axi_arvalid (axi_arvalid ), + .s_axi_arready (axi_arready ), + .s_axi_rresp (axi_rresp ), + .s_axi_rdata (axi_rdata ), + .s_axi_rvalid (axi_rvalid ), + .s_axi_rready (axi_rready ), + //MDIO Interface + .Mdo (phy_mdo ), + .MdoEn (phy_mdo_en ), + .Mdi (phy_mdi ), + .Mdc (phy_mdc ) +); + +/*----------------------- User Interface Loopback Module ----------------------------*/ +mac_rx2tx u_mac_rx2tx +( +//Globle Signals +// +//Receive AXI4-Stream Interface + .rx_axis_clk (rx_axis_clk ), + .rx_axis_rstn (mac_rstn ), + .rx_axis_mac_tdata (rx_axis_mac_tdata ), + .rx_axis_mac_tvalid (rx_axis_mac_tvalid ), + .rx_axis_mac_tlast (rx_axis_mac_tlast ), + .rx_axis_mac_tuser (rx_axis_mac_tuser ), + .rx_axis_mac_tready (rx_axis_mac_tready ), +//Transmit AXI4-Stream Interface + .tx_axis_clk (tx_axis_clk ), + .tx_axis_rstn (mac_rstn ), + .tx_axis_mac_tdata (loop_tx_axis_mac_tdata ), + .tx_axis_mac_tvalid (loop_tx_axis_mac_tvalid ), + .tx_axis_mac_tlast (loop_tx_axis_mac_tlast ), + .tx_axis_mac_tuser (loop_tx_axis_mac_tuser ), + .tx_axis_mac_tready (loop_tx_axis_mac_tready ) +); + +endmodule + diff --git a/fpga/ip/gTSE/Ti60F225_devkit/temac_ex.xml b/fpga/ip/gTSE/Ti60F225_devkit/temac_ex.xml new file mode 100644 index 0000000..d7a0967 --- /dev/null +++ b/fpga/ip/gTSE/Ti60F225_devkit/temac_ex.xml @@ -0,0 +1,124 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/ip/gTSE/Ti60F225_devkit/timing_Ti60.sdc b/fpga/ip/gTSE/Ti60F225_devkit/timing_Ti60.sdc new file mode 100644 index 0000000..6476988 --- /dev/null +++ b/fpga/ip/gTSE/Ti60F225_devkit/timing_Ti60.sdc @@ -0,0 +1,77 @@ +################################## Clock Constraints ########################## +create_clock -period 20.00 clk +create_clock -period 8.00 clk_125m +create_clock -waveform {2.00 6.00} -period 8.00 clk_125m_90deg +create_clock -period 100.00 [get_ports {jtag_inst1_TCK}] + +# Dynamic Clock Mux Outputs +##################################### +create_clock -period 8.000 -name mux_clk [get_ports {mux_clk}] + + +#################################################################################################################################### +# Timing Mode Constrains +#################################################################################################################################### +set_clock_groups -exclusive -group {clk} -group {clk_125m} -group {clk_125m_90deg} -group {mux_clk} -group {jtag_inst1_TCK} + +# JTAG Constraints +#################### +# create_clock -period [get_ports {jtag_inst1_TCK}] +# create_clock -period [get_ports {jtag_inst1_DRCK}] +set_output_delay -clock jtag_inst1_TCK -max 0.117 [get_ports {jtag_inst1_TDO}] +set_output_delay -clock jtag_inst1_TCK -min -0.075 [get_ports {jtag_inst1_TDO}] +set_input_delay -clock_fall -clock jtag_inst1_TCK -max 0.280 [get_ports {jtag_inst1_CAPTURE}] +set_input_delay -clock_fall -clock jtag_inst1_TCK -min 0.187 [get_ports {jtag_inst1_CAPTURE}] +set_input_delay -clock_fall -clock jtag_inst1_TCK -max 0.243 [get_ports {jtag_inst1_SEL}] +set_input_delay -clock_fall -clock jtag_inst1_TCK -min 0.162 [get_ports {jtag_inst1_SEL}] +set_input_delay -clock_fall -clock jtag_inst1_TCK -max 0.337 [get_ports {jtag_inst1_SHIFT}] +set_input_delay -clock_fall -clock jtag_inst1_TCK -min 0.225 [get_ports {jtag_inst1_SHIFT}] + +# HSIO GPIO Constraints +######################### +set_input_delay -clock mux_clk -reference_pin [get_ports {mux_clk~CLKOUT~218~278}] -max 0.414 [get_ports {rgmii_rx_ctl_LO rgmii_rx_ctl_HI}] +set_input_delay -clock mux_clk -reference_pin [get_ports {mux_clk~CLKOUT~218~278}] -min 0.276 [get_ports {rgmii_rx_ctl_LO rgmii_rx_ctl_HI}] +set_input_delay -clock mux_clk -reference_pin [get_ports {mux_clk~CLKOUT~218~268}] -max 0.414 [get_ports {rgmii_rxd_LO[0] rgmii_rxd_HI[0]}] +set_input_delay -clock mux_clk -reference_pin [get_ports {mux_clk~CLKOUT~218~268}] -min 0.276 [get_ports {rgmii_rxd_LO[0] rgmii_rxd_HI[0]}] +set_input_delay -clock mux_clk -reference_pin [get_ports {mux_clk~CLKOUT~218~267}] -max 0.414 [get_ports {rgmii_rxd_LO[1] rgmii_rxd_HI[1]}] +set_input_delay -clock mux_clk -reference_pin [get_ports {mux_clk~CLKOUT~218~267}] -min 0.276 [get_ports {rgmii_rxd_LO[1] rgmii_rxd_HI[1]}] +set_input_delay -clock mux_clk -reference_pin [get_ports {mux_clk~CLKOUT~218~255}] -max 0.414 [get_ports {rgmii_rxd_LO[2] rgmii_rxd_HI[2]}] +set_input_delay -clock mux_clk -reference_pin [get_ports {mux_clk~CLKOUT~218~255}] -min 0.276 [get_ports {rgmii_rxd_LO[2] rgmii_rxd_HI[2]}] +set_input_delay -clock mux_clk -reference_pin [get_ports {mux_clk~CLKOUT~218~254}] -max 0.414 [get_ports {rgmii_rxd_LO[3] rgmii_rxd_HI[3]}] +set_input_delay -clock mux_clk -reference_pin [get_ports {mux_clk~CLKOUT~218~254}] -min 0.276 [get_ports {rgmii_rxd_LO[3] rgmii_rxd_HI[3]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {sw6}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {sw6}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {phy_mdc}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {phy_mdc}] +set_output_delay -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~210}] -max 0.263 [get_ports {rgmii_tx_ctl_LO rgmii_tx_ctl_HI}] +set_output_delay -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~210}] -min -0.140 [get_ports {rgmii_tx_ctl_LO rgmii_tx_ctl_HI}] +set_output_delay -clock clk_125m_90deg -reference_pin [get_ports {clk_125m_90deg~CLKOUT~218~225}] -max 0.263 [get_ports {rgmii_txc_LO rgmii_txc_HI}] +set_output_delay -clock clk_125m_90deg -reference_pin [get_ports {clk_125m_90deg~CLKOUT~218~225}] -min -0.140 [get_ports {rgmii_txc_LO rgmii_txc_HI}] +set_output_delay -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~171}] -max 0.263 [get_ports {rgmii_txd_LO[0] rgmii_txd_HI[0]}] +set_output_delay -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~171}] -min -0.140 [get_ports {rgmii_txd_LO[0] rgmii_txd_HI[0]}] +set_output_delay -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~170}] -max 0.263 [get_ports {rgmii_txd_LO[1] rgmii_txd_HI[1]}] +set_output_delay -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~170}] -min -0.140 [get_ports {rgmii_txd_LO[1] rgmii_txd_HI[1]}] +set_output_delay -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~196}] -max 0.263 [get_ports {rgmii_txd_LO[2] rgmii_txd_HI[2]}] +set_output_delay -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~196}] -min -0.140 [get_ports {rgmii_txd_LO[2] rgmii_txd_HI[2]}] +set_output_delay -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~195}] -max 0.263 [get_ports {rgmii_txd_LO[3] rgmii_txd_HI[3]}] +set_output_delay -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~195}] -min -0.140 [get_ports {rgmii_txd_LO[3] rgmii_txd_HI[3]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {phy_mdi}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {phy_mdi}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {phy_mdo}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {phy_mdo}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {phy_mdo_en}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {phy_mdo_en}] + +# Clockout Interface +###################### +# rgmii_rx_ctl -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~218~278}] +# rgmii_rxd[0] -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~218~268}] +# rgmii_rxd[1] -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~218~267}] +# rgmii_rxd[2] -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~218~255}] +# rgmii_rxd[3] -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~218~254}] +# rgmii_tx_ctl -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~210}] +# rgmii_txc -clock clk_125m_90deg -reference_pin [get_ports {clk_125m_90deg~CLKOUT~218~225}] +# rgmii_txd[0] -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~171}] +# rgmii_txd[1] -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~170}] +# rgmii_txd[2] -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~196}] +# rgmii_txd[3] -clock clk_125m -reference_pin [get_ports {clk_125m~CLKOUT~218~195}] diff --git a/fpga/ip/gTSE/Ti60F225_devkit/udp_pat_gen.v b/fpga/ip/gTSE/Ti60F225_devkit/udp_pat_gen.v new file mode 100644 index 0000000..e5626c3 --- /dev/null +++ b/fpga/ip/gTSE/Ti60F225_devkit/udp_pat_gen.v @@ -0,0 +1,497 @@ +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / +// / / .' / +// __/ /.' / +// __ \ / +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* +`timescale 1 ns / 1 ns +module udp_pat_gen +( +//Globle Signals +input clk, +input rstn, +//Control Interface +input pat_gen_en, +input [15:0] pat_gen_num,//When value is 0, it's infinite mode +input [15:0] pat_gen_ipg, +//MAC Protocol Signals +input [47:0] dst_mac, +input [47:0] src_mac, +//IP Protocol Signals +input [31:0] src_ip, +input [31:0] dst_ip, +//UDP Protocol Signals +input [15:0] udp_dlen, +input [15:0] src_port, +input [15:0] dst_port, +//AXI4-Stream Interface +input rclk, +input rrstn, +input [7:0] rdata, +input rvalid, +input rlast, + +output reg [7:0] tdata, +output reg tvalid, +output reg tlast, +input tready +); + +// Parameter Define +localparam VER = 4'h4;//IPv4 +localparam IHL = 4'h5;//Internet Header Length +localparam TOS = 8'h0;//Type Of Service +localparam FLG = 3'h0;//Flags +localparam TTL = 8'h40;//Time To Live +localparam PTC = 8'h11;//UDP Protocol + +localparam IDLE = 3'h0; +localparam UDP_CHKSUM = 3'h1; +localparam IP_CHKSUM = 3'h2; +localparam PAT_IPG = 3'h3; +localparam PAT_GEN = 3'h4; + +// Register Define +reg [2:0] cur_state; +reg [2:0] next_state; +reg pat_gen_en_dl1; +reg pat_gen_en_dl2; +reg [31:0] src_ip_r; +reg [31:0] dst_ip_r; +reg [15:0] src_port_r; +reg [15:0] dst_port_r; +reg pat_en; +reg infinite_en; +reg [15:0] num_cnt; +reg [15:0] udp_chksum_cnt; +reg [3:0] ip_chksum_cnt; +reg [15:0] ipg_cnt; +reg [15:0] pat_cnt; +reg [15:0] udp_len; +reg [15:0] udp_chksum_num; +reg [7:0] udp_data_h; +reg [7:0] udp_data_l; +reg [16:0] udp_chksum_r; +reg [15:0] udp_chksum; +reg [15:0] ip_len; +reg [15:0] ip_id; +reg [12:0] ip_ofs; +reg [16:0] ip_chksum_r; +reg [15:0] ip_chksum; + +reg [15:0] pat_gen_num_r; +reg [15:0] pat_gen_ipg_r; +reg [47:0] dst_mac_r; +reg [47:0] src_mac_r; +reg [15:0] udp_dlen_r; + +// Wire Define +/*----------------------------------------------------------------------------------*\ + The main code +\*----------------------------------------------------------------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) begin + pat_gen_num_r <= 16'h0; + pat_gen_ipg_r <= 16'h0; + dst_mac_r <= 48'h0; + src_mac_r <= 48'h0; + udp_dlen_r <= 16'h0; + end + else begin + pat_gen_num_r <= pat_gen_num; + pat_gen_ipg_r <= pat_gen_ipg; + dst_mac_r <= dst_mac; + src_mac_r <= src_mac; + udp_dlen_r <= udp_dlen; + end +end + +/*----------------------- FSM Region ----------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + cur_state <= IDLE; + else + cur_state <= next_state; +end + +always @(*) + begin + case(cur_state) + IDLE : + if(pat_en == 1'b1) + next_state = UDP_CHKSUM; + else + next_state = IDLE; + + UDP_CHKSUM : + if(udp_chksum_cnt == udp_chksum_num) + next_state = IP_CHKSUM; + else + next_state = UDP_CHKSUM; + + IP_CHKSUM : + if(ip_chksum_cnt == 4'd9) + next_state = PAT_GEN; + else + next_state = IP_CHKSUM; + + PAT_IPG : + if((pat_en == 1'b1) || ((ipg_cnt == pat_gen_ipg_r) && (infinite_en == 1'b0) && (num_cnt == 16'h0))) + next_state = IDLE; + else if(ipg_cnt == pat_gen_ipg_r) + next_state = IP_CHKSUM; + else + next_state = PAT_IPG; + + PAT_GEN : + if((tlast == 1'b1) && (tready == 1'b1)) + next_state = PAT_IPG; + else + next_state = PAT_GEN; + + default : + next_state = IDLE; + endcase + end + +/*----------------------- Generator Control Region ----------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + begin + pat_gen_en_dl1 <= 1'h0; + pat_gen_en_dl2 <= 1'h0; + end + else + begin + pat_gen_en_dl1 <= pat_gen_en; + pat_gen_en_dl2 <= pat_gen_en_dl1; + end +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + begin + src_ip_r <= 32'h0; + dst_ip_r <= 32'h0; + src_port_r <= 16'h0; + dst_port_r <= 16'h0; + end + else + begin + src_ip_r <= src_ip; + dst_ip_r <= dst_ip; + src_port_r <= src_port; + dst_port_r <= dst_port; + end +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + pat_en <= 1'h0; + else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) + pat_en <= 1'h1; + else if((cur_state == IDLE) && (pat_en == 1'b1)) + pat_en <= 1'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + infinite_en <= 1'h0; + else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1) && (pat_gen_num_r == 16'h0)) + infinite_en <= 1'h1; + else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) + infinite_en <= 1'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + num_cnt <= 16'h0; + else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1)) + num_cnt <= pat_gen_num_r; + else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1) && (num_cnt != 16'h0)) + num_cnt <= num_cnt - 1'b1; +end + +/*----------------------- UDP Protocol Region ----------------------------*/ + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + udp_len <= 16'h0; + else + udp_len <= udp_dlen_r + 16'd8; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + udp_chksum_num <= 16'h0; + else if(udp_dlen_r[0] == 1'b1) + udp_chksum_num <= udp_dlen_r[15:1] + 16'd10; + else + udp_chksum_num <= udp_dlen_r[15:1] + 16'd9; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + begin + udp_data_h <= 8'h0; + udp_data_l <= 8'h0; + end + else if(cur_state == IDLE) + begin + udp_data_h <= 8'h0; + udp_data_l <= 8'h1; + end + else if((cur_state == UDP_CHKSUM) && (udp_chksum_cnt >= 16'h9)) + begin + udp_data_h <= udp_data_h + 8'h2; + udp_data_l <= udp_data_l + 8'h2; + end +end + +//udp checksum calculate +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + udp_chksum_r <= 17'h0; + else if(cur_state == IDLE) + udp_chksum_r <= 17'h0; + else if(cur_state == UDP_CHKSUM) begin + if (udp_chksum_cnt <= 16'd8) begin + case(udp_chksum_cnt[3:0]) + 4'd0 : udp_chksum_r <= udp_chksum_r[15:0] + src_ip_r[31:16] + udp_chksum_r[16]; + 4'd1 : udp_chksum_r <= udp_chksum_r[15:0] + src_ip_r[15:0] + udp_chksum_r[16]; + 4'd2 : udp_chksum_r <= udp_chksum_r[15:0] + dst_ip_r[31:16] + udp_chksum_r[16]; + 4'd3 : udp_chksum_r <= udp_chksum_r[15:0] + dst_ip_r[15:0] + udp_chksum_r[16]; + 4'd4 : udp_chksum_r <= udp_chksum_r[15:0] + 16'h11 + udp_chksum_r[16]; + 4'd5 : udp_chksum_r <= udp_chksum_r[15:0] + udp_len + udp_chksum_r[16]; + 4'd6 : udp_chksum_r <= udp_chksum_r[15:0] + src_port_r + udp_chksum_r[16]; + 4'd7 : udp_chksum_r <= udp_chksum_r[15:0] + dst_port_r + udp_chksum_r[16]; + 4'd8 : udp_chksum_r <= udp_chksum_r[15:0] + udp_len + udp_chksum_r[16]; + default : udp_chksum_r <= 17'h0; + endcase + end + else begin + if(udp_chksum_cnt == udp_chksum_num) + udp_chksum_r <= udp_chksum_r[15:0] + udp_chksum_r[16]; + else if((udp_chksum_cnt == udp_chksum_num-1) && (udp_dlen_r[0] == 1'b1)) + udp_chksum_r <= udp_chksum_r[15:0] + {udp_data_h,8'h0} + udp_chksum_r[16]; + else + udp_chksum_r <= udp_chksum_r[15:0] + {udp_data_h,udp_data_l} + udp_chksum_r[16]; + end + end +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + udp_chksum <= 16'h0; + else + udp_chksum <= ~udp_chksum_r[15:0]; +end + +/*----------------------- IP Protocol Region ----------------------------*/ +//IP Frame Total Length +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ip_len <= 16'h0; + else + ip_len <= udp_len + 16'd20; +end + +//IP Frame Identification +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ip_id <= 16'h0; + else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1)) + ip_id <= ip_id + 1'b1; +end + +//IP Frame Fragment Offset +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ip_chksum <= 16'h0; + else + ip_chksum <= ~ip_chksum_r[15:0]; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ip_ofs <= 13'h0; +end + +//ip checksum calculate +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ip_chksum_r <= 16'h0; + else if(cur_state == IDLE) + ip_chksum_r <= 16'h0; + else if(cur_state == IP_CHKSUM) begin + case(ip_chksum_cnt) + 4'd0 : ip_chksum_r <= ip_chksum_r[15:0] + {VER,IHL,TOS} + ip_chksum_r[16]; + 4'd1 : ip_chksum_r <= ip_chksum_r[15:0] + ip_len + ip_chksum_r[16]; + 4'd2 : ip_chksum_r <= ip_chksum_r[15:0] + ip_id + ip_chksum_r[16]; + 4'd3 : ip_chksum_r <= ip_chksum_r[15:0] + {FLG,ip_ofs} + ip_chksum_r[16]; + 4'd4 : ip_chksum_r <= ip_chksum_r[15:0] + {TTL,PTC} + ip_chksum_r[16]; + 4'd5 : ip_chksum_r <= ip_chksum_r[15:0] + src_ip_r[31:16] + ip_chksum_r[16]; + 4'd6 : ip_chksum_r <= ip_chksum_r[15:0] + src_ip_r[15:0] + ip_chksum_r[16]; + 4'd7 : ip_chksum_r <= ip_chksum_r[15:0] + dst_ip_r[31:16] + ip_chksum_r[16]; + 4'd8 : ip_chksum_r <= ip_chksum_r[15:0] + dst_ip_r[15:0] + ip_chksum_r[16]; + 4'd9 : ip_chksum_r <= ip_chksum_r[15:0] + ip_chksum_r[16]; + endcase + end + else if(cur_state == PAT_IPG) + ip_chksum_r <= 16'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ip_chksum <= 16'h0; + else + ip_chksum <= ~ip_chksum_r[15:0]; +end + +/*----------------------- Pattern Counter Region ----------------------------*/ +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + udp_chksum_cnt <= 16'h0; + else if(cur_state == UDP_CHKSUM) + udp_chksum_cnt <= udp_chksum_cnt + 1'b1; + else + udp_chksum_cnt <= 16'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ip_chksum_cnt <= 4'h0; + else if(cur_state == IP_CHKSUM) + ip_chksum_cnt <= ip_chksum_cnt + 1'b1; + else + ip_chksum_cnt <= 4'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + ipg_cnt <= 16'h0; + else if(cur_state == PAT_IPG) + ipg_cnt <= ipg_cnt + 1'b1; + else + ipg_cnt <= 8'h0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + pat_cnt <= 16'h0; + else if(cur_state != PAT_GEN) + pat_cnt <= 16'h0; + else if(tready == 1'b1) + pat_cnt <= pat_cnt + 1'b1; +end + +/*----------------------- Pattern Generator Region ----------------------------*/ + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + tvalid <= 1'b0; + else if((cur_state == PAT_GEN) && (pat_cnt == 16'h0) && (tready == 1'b1)) + tvalid <= 1'b1; + else if((tready == 1'b1) && (tlast == 1'b1)) + tvalid <= 1'b0; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + tdata <= 8'h0; + else if((cur_state == PAT_GEN) && (tready == 1'b1) && (pat_cnt <= 16'd42)) + case(pat_cnt[5:0]) + 6'd0 : tdata <= dst_mac_r[5*8 +: 8]; + 6'd1 : tdata <= dst_mac_r[4*8 +: 8]; + 6'd2 : tdata <= dst_mac_r[3*8 +: 8]; + 6'd3 : tdata <= dst_mac_r[2*8 +: 8]; + 6'd4 : tdata <= dst_mac_r[1*8 +: 8]; + 6'd5 : tdata <= dst_mac_r[0*8 +: 8]; + 6'd6 : tdata <= src_mac_r[5*8 +: 8]; + 6'd7 : tdata <= src_mac_r[4*8 +: 8]; + 6'd8 : tdata <= src_mac_r[3*8 +: 8]; + 6'd9 : tdata <= src_mac_r[2*8 +: 8]; + 6'd10 : tdata <= src_mac_r[1*8 +: 8]; + 6'd11 : tdata <= src_mac_r[0*8 +: 8]; + 6'd12 : tdata <= 8'h08; + 6'd13 : tdata <= 8'h00; + 6'd14 : tdata <= {VER,IHL}; + 6'd15 : tdata <= TOS; + 6'd16 : tdata <= ip_len[15:8]; + 6'd17 : tdata <= ip_len[7:0]; + 6'd18 : tdata <= ip_id[15:8]; + 6'd19 : tdata <= ip_id[7:0]; + 6'd20 : tdata <= {FLG,ip_ofs[12:8]}; + 6'd21 : tdata <= ip_ofs[7:0]; + 6'd22 : tdata <= TTL; + 6'd23 : tdata <= PTC; + 6'd24 : tdata <= ip_chksum[15:8]; + 6'd25 : tdata <= ip_chksum[7:0]; + 6'd26 : tdata <= src_ip_r[3*8 +: 8]; + 6'd27 : tdata <= src_ip_r[2*8 +: 8]; + 6'd28 : tdata <= src_ip_r[1*8 +: 8]; + 6'd29 : tdata <= src_ip_r[0*8 +: 8]; + 6'd30 : tdata <= dst_ip_r[3*8 +: 8]; + 6'd31 : tdata <= dst_ip_r[2*8 +: 8]; + 6'd32 : tdata <= dst_ip_r[1*8 +: 8]; + 6'd33 : tdata <= dst_ip_r[0*8 +: 8]; + 6'd34 : tdata <= src_port_r[15:8]; + 6'd35 : tdata <= src_port_r[7:0]; + 6'd36 : tdata <= dst_port_r[15:8]; + 6'd37 : tdata <= dst_port_r[7:0]; + 6'd38 : tdata <= udp_len[15:8]; + 6'd39 : tdata <= udp_len[7:0]; + 6'd40 : tdata <= udp_chksum[15:8]; + 6'd41 : tdata <= udp_chksum[7:0]; + 6'd42 : tdata <= 8'h0;//UDP First Data + default : tdata <= tdata + 1'b1; + endcase + else if((cur_state == PAT_GEN) && (tready == 1'b1)) + tdata <= tdata + 1'b1; +end + +always @(posedge clk or negedge rstn) +begin + if(rstn == 1'b0) + tlast <= 1'b0; + else if((tready == 1'b1) && (cur_state == PAT_GEN) && (pat_cnt == ip_len+16'd13)) + tlast <= 1'b1; + else if(tready == 1'b1) + tlast <= 1'b0; +end + +endmodule diff --git a/fpga/ip/gTSE/gTSE.sv b/fpga/ip/gTSE/gTSE.sv new file mode 100644 index 0000000..8095d65 --- /dev/null +++ b/fpga/ip/gTSE/gTSE.sv @@ -0,0 +1,9844 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.288.2.10 +// IP Version: 7.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _4c19f37180ff465ca20760e199a0613f +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module gTSE +( + input mac_reset, + input proto_reset, + output rx_mac_aclk, + input tx_mac_aclk, + output [2:0] eth_speed, + input rx_axis_clk, + output rx_axis_mac_tuser, + output rx_axis_mac_tlast, + output rx_axis_mac_tvalid, + input rx_axis_mac_tready, + input tx_axis_clk, + input tx_axis_mac_tvalid, + input tx_axis_mac_tlast, + input tx_axis_mac_tuser, + output tx_axis_mac_tready, + output [3:0] rgmii_txd_HI, + output [3:0] rgmii_txd_LO, + output rgmii_tx_ctl_HI, + output rgmii_tx_ctl_LO, + output rgmii_txc_HI, + output rgmii_txc_LO, + input [3:0] rgmii_rxd_HI, + input [3:0] rgmii_rxd_LO, + input rgmii_rx_ctl_HI, + input rgmii_rx_ctl_LO, + input rgmii_rxc, + input s_axi_aclk, + output [7:0] rx_axis_mac_tdata, + input [7:0] tx_axis_mac_tdata, + input [0:0] tx_axis_mac_tstrb, + output [0:0] rx_axis_mac_tstrb, + output MdoEn, + output Mdo, + input Mdi, + output Mdc, + input [9:0] s_axi_araddr, + output s_axi_arready, + input s_axi_arvalid, + input [9:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_awvalid, + input s_axi_bready, + output [1:0] s_axi_bresp, + output s_axi_bvalid, + output [31:0] s_axi_rdata, + input s_axi_rready, + output [1:0] s_axi_rresp, + output s_axi_rvalid, + input [31:0] s_axi_wdata, + output s_axi_wready, + input s_axi_wvalid +); +`IP_MODULE_NAME(efx_mac1gbe) +#( + .VERSION (16), + .TXFIFO_EN (1'b1), + .RXFIFO_EN (1'b1), + .TXFIFO_DTH (4096), + .RXFIFO_DTH (4096), + .PHY_INTF_MODE (0), + .AXIS_DW (8), + .RGMII_RXC_EDGE (1'b1), + .RGMII_TXC_DLY (1'b1), + .INTER_PACKET_GAP (6'd12), + .MTU_FRAME_LENGTH (16'd1518), + .MAC_SOURCE_ADDRESS (48'd0), + .ENABLE_BROADCAST_FILTERING (1'b1), + .LOOPBACK_EN (1'b1), + .APBIF (1'b0), + .FAMILY ("TITANIUM") +) +u_efx_mac1gbe +( + .mac_reset ( mac_reset ), + .proto_reset ( proto_reset ), + .rx_mac_aclk ( rx_mac_aclk ), + .tx_mac_aclk ( tx_mac_aclk ), + .eth_speed ( eth_speed ), + .rx_axis_clk ( rx_axis_clk ), + .rx_axis_mac_tuser ( rx_axis_mac_tuser ), + .rx_axis_mac_tlast ( rx_axis_mac_tlast ), + .rx_axis_mac_tvalid ( rx_axis_mac_tvalid ), + .rx_axis_mac_tready ( rx_axis_mac_tready ), + .tx_axis_clk ( tx_axis_clk ), + .tx_axis_mac_tvalid ( tx_axis_mac_tvalid ), + .tx_axis_mac_tlast ( tx_axis_mac_tlast ), + .tx_axis_mac_tuser ( tx_axis_mac_tuser ), + .tx_axis_mac_tready ( tx_axis_mac_tready ), + .rgmii_txd_HI ( rgmii_txd_HI ), + .rgmii_txd_LO ( rgmii_txd_LO ), + .rgmii_tx_ctl_HI ( rgmii_tx_ctl_HI ), + .rgmii_tx_ctl_LO ( rgmii_tx_ctl_LO ), + .rgmii_txc_HI ( rgmii_txc_HI ), + .rgmii_txc_LO ( rgmii_txc_LO ), + .rgmii_rxd_HI ( rgmii_rxd_HI ), + .rgmii_rxd_LO ( rgmii_rxd_LO ), + .rgmii_rx_ctl_HI ( rgmii_rx_ctl_HI ), + .rgmii_rx_ctl_LO ( rgmii_rx_ctl_LO ), + .rgmii_rxc ( rgmii_rxc ), + .s_axi_aclk ( s_axi_aclk ), + .rx_axis_mac_tdata ( rx_axis_mac_tdata ), + .tx_axis_mac_tdata ( tx_axis_mac_tdata ), + .tx_axis_mac_tstrb ( tx_axis_mac_tstrb ), + .rx_axis_mac_tstrb ( rx_axis_mac_tstrb ), + .MdoEn ( MdoEn ), + .Mdo ( Mdo ), + .Mdi ( Mdi ), + .Mdc ( Mdc ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arready ( s_axi_arready ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awready ( s_axi_awready ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rready ( s_axi_rready ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_wready ( s_axi_wready ), + .s_axi_wvalid ( s_axi_wvalid ) +); +endmodule + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_top) # ( + parameter FAMILY = "TRION", // New Param + parameter SYNC_CLK = 0, + parameter BYPASS_RESET_SYNC = 0, // New Param + parameter SYNC_STAGE = 2, // New Param + parameter MODE = "STANDARD", + parameter DEPTH = 512, // Reverted (Equivalent to WDATA_DEPTH) + parameter DATA_WIDTH = 32, // Reverted (Equivalent to WDATA_WIDTH) + parameter PIPELINE_REG = 1, // Reverted (By default is ON) + parameter OPTIONAL_FLAGS = 1, // Reverted + parameter OUTPUT_REG = 0, + parameter PROGRAMMABLE_FULL = "STATIC_DUAL", // Set to "NONE" if not require this feature + parameter PROG_FULL_ASSERT = 27, + parameter PROG_FULL_NEGATE = 23, + parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature + parameter PROG_EMPTY_ASSERT = 5, + parameter PROG_EMPTY_NEGATE = 7, + parameter ALMOST_FLAG = OPTIONAL_FLAGS, + parameter HANDSHAKE_FLAG = OPTIONAL_FLAGS, + parameter ASYM_WIDTH_RATIO = 4, + parameter WADDR_WIDTH = depth2width(DEPTH), + parameter RDATA_WIDTH = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH), + parameter RD_DEPTH = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH), + parameter RADDR_WIDTH = depth2width(RD_DEPTH), + parameter ENDIANESS = 0, + parameter OVERFLOW_PROTECT = 1, + parameter UNDERFLOW_PROTECT = 1, + parameter RAM_STYLE = "block_ram" + +)( + input wire a_rst_i, + input wire a_wr_rst_i, + input wire a_rd_rst_i, + input wire clk_i, + input wire wr_clk_i, + input wire rd_clk_i, + input wire wr_en_i, + input wire rd_en_i, + input wire [DATA_WIDTH-1:0] wdata, + output wire almost_full_o, + output wire prog_full_o, + output wire full_o, + output wire overflow_o, + output wire wr_ack_o, + output wire [WADDR_WIDTH :0] datacount_o, + output wire [WADDR_WIDTH :0] wr_datacount_o, + output wire empty_o, + output wire almost_empty_o, + output wire prog_empty_o, + output wire underflow_o, + output wire rd_valid_o, + output wire [RDATA_WIDTH-1:0] rdata, + output wire [RADDR_WIDTH :0] rd_datacount_o, + output wire rst_busy +); + +localparam WR_DEPTH = DEPTH; +localparam WDATA_WIDTH = DATA_WIDTH; +localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH) ? 1 : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH*8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32; + +wire wr_rst_int; +wire rd_rst_int; +wire wr_en_int; +wire rd_en_int; +wire [WADDR_WIDTH-1:0] waddr; +wire [RADDR_WIDTH-1:0] raddr; +wire wr_clk_int; +wire rd_clk_int; +wire [WADDR_WIDTH :0] wr_datacount_int; +wire [RADDR_WIDTH :0] rd_datacount_int; + +generate + if (ASYM_WIDTH_RATIO == 4) begin + if (SYNC_CLK) begin + assign wr_clk_int = clk_i; + assign rd_clk_int = clk_i; + assign datacount_o = wr_datacount_int; + assign wr_datacount_o = {(WADDR_WIDTH+1){1'b0}}; + assign rd_datacount_o = {(RADDR_WIDTH+1){1'b0}}; + end + else begin + assign wr_clk_int = wr_clk_i; + assign rd_clk_int = rd_clk_i; + assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; + assign wr_datacount_o = wr_datacount_int; + assign rd_datacount_o = rd_datacount_int; + end + end + else begin + assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; + assign wr_datacount_o = wr_datacount_int; + assign rd_datacount_o = rd_datacount_int; + if (SYNC_CLK) begin + assign wr_clk_int = clk_i; + assign rd_clk_int = clk_i; + end + else begin + assign wr_clk_int = wr_clk_i; + assign rd_clk_int = rd_clk_i; + end + end + + if (!SYNC_CLK) begin + //(* async_reg = "true" *) reg [1:0] wr_rst; + //(* async_reg = "true" *) reg [1:0] rd_rst; + // + //always @ (posedge wr_clk_int or posedge a_rst_i) begin + // if (a_rst_i) + // wr_rst <= 2'b11; + // else + // wr_rst <= {wr_rst[0],1'b0}; + //end + // + //always @ (posedge rd_clk_int or posedge a_rst_i) begin + // if (a_rst_i) + // rd_rst <= 2'b11; + // else + // rd_rst <= {rd_rst[0],1'b0}; + //end + + + if (BYPASS_RESET_SYNC) begin + assign wr_rst_int = a_wr_rst_i; + assign rd_rst_int = a_rd_rst_i; + assign rst_busy = 1'b0; + end + else begin + `IP_MODULE_NAME(efx_resetsync) #( + .ACTIVE_LOW (0) + ) efx_resetsync_wr_rst ( + .clk (wr_clk_int), + .reset (a_rst_i), + .d_o (wr_rst_int) + ); + + `IP_MODULE_NAME(efx_resetsync) #( + .ACTIVE_LOW (0) + ) efx_resetsync_rd_rst ( + .clk (rd_clk_int), + .reset (a_rst_i), + .d_o (rd_rst_int) + ); + assign rst_busy = wr_rst_int | rd_rst_int; + end + + end + else begin + //(* async_reg = "true" *) reg [1:0] a_rst; + // + //always @ (posedge clk_i or posedge a_rst_i) begin + // if (a_rst_i) + // a_rst <= 2'b11; + // else + // a_rst <= {a_rst[0],1'b0}; + //end + wire a_rst; + + `IP_MODULE_NAME(efx_resetsync) #( + .ACTIVE_LOW (0) + ) efx_resetsync_a_rst ( + .clk (clk_i), + .reset (a_rst_i), + .d_o (a_rst) + ); + + if (BYPASS_RESET_SYNC) begin + assign wr_rst_int = a_rst_i; + assign rd_rst_int = a_rst_i; + assign rst_busy = 1'b0; + end + else begin + assign wr_rst_int = a_rst; + assign rd_rst_int = a_rst; + assign rst_busy = wr_rst_int | rd_rst_int; + end + end +endgenerate + +`IP_MODULE_NAME(efx_fifo_ram) # ( + .FAMILY (FAMILY), + .WR_DEPTH (WR_DEPTH), + .RD_DEPTH (RD_DEPTH), + .WDATA_WIDTH (WDATA_WIDTH), + .RDATA_WIDTH (RDATA_WIDTH), + .WADDR_WIDTH (WADDR_WIDTH), + .RADDR_WIDTH (RADDR_WIDTH), + .OUTPUT_REG (OUTPUT_REG), + .RAM_MUX_RATIO (RAM_MUX_RATIO), + .ENDIANESS (ENDIANESS), + .RAM_STYLE (RAM_STYLE) +) xefx_fifo_ram ( + .wdata (wdata), + .waddr (waddr), + .raddr (raddr), + .we (wr_en_int), + .re (rd_en_int), + .wclk (wr_clk_int), + .rclk (rd_clk_int), + .rdata (rdata) +); + +`IP_MODULE_NAME(efx_fifo_ctl) # ( + .SYNC_CLK (SYNC_CLK), + .SYNC_STAGE (SYNC_STAGE), + .MODE (MODE), + .WR_DEPTH (WR_DEPTH), + .WADDR_WIDTH (WADDR_WIDTH), + .RADDR_WIDTH (RADDR_WIDTH), + .ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), + .RAM_MUX_RATIO (RAM_MUX_RATIO), + .PIPELINE_REG (PIPELINE_REG), + .ALMOST_FLAG (ALMOST_FLAG), + .PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), + .PROG_FULL_ASSERT (PROG_FULL_ASSERT), + .PROG_FULL_NEGATE (PROG_FULL_NEGATE), + .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), + .PROG_EMPTY_ASSERT (PROG_EMPTY_ASSERT), + .PROG_EMPTY_NEGATE (PROG_EMPTY_NEGATE), + .OUTPUT_REG (OUTPUT_REG), + .HANDSHAKE_FLAG (HANDSHAKE_FLAG), + .OVERFLOW_PROTECT (OVERFLOW_PROTECT), + .UNDERFLOW_PROTECT (UNDERFLOW_PROTECT) +) xefx_fifo_ctl ( + .wr_rst (wr_rst_int), + .rd_rst (rd_rst_int), + .wclk (wr_clk_int), + .rclk (rd_clk_int), + .we (wr_en_i), + .re (rd_en_i), + .wr_full (full_o), + .wr_ack (wr_ack_o), + .rd_empty (empty_o), + .wr_almost_full (almost_full_o), + .rd_almost_empty (almost_empty_o), + .wr_prog_full (prog_full_o), + .rd_prog_empty (prog_empty_o), + .wr_en_int (wr_en_int), + .rd_en_int (rd_en_int), + .waddr (waddr), + .raddr (raddr), + .wr_datacount (wr_datacount_int), + .rd_datacount (rd_datacount_int), + .rd_vld (rd_valid_o), + .wr_overflow (overflow_o), + .rd_underflow (underflow_o) +); + +function integer depth2width; +input [31:0] depth; +begin : fnDepth2Width + if (depth > 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian + parameter RAM_STYLE = "block_ram" +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + always @ (posedge wclk) begin + for (i=0; i 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_resetsync) #( + parameter ASYNC_STAGE = 2, + parameter ACTIVE_LOW = 1 +) ( + input wire clk, + input wire reset, + output wire d_o +); + + +generate + if (ACTIVE_LOW == 1) begin: active_low + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (1), + .RST_VALUE (0) + ) efx_resetsync_active_low ( + .clk (clk), + .reset_n (reset), + .d_i (1'b1), + .d_o (d_o) + ); + end + else begin: active_high + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (0), + .RST_VALUE (1) + ) efx_resetsync_active_high ( + .clk (clk), + .reset_n (reset), + .d_i (1'b0), + .d_o (d_o) + ); + end +endgenerate + +endmodule + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_asyncreg) #( + parameter ASYNC_STAGE = 2, + parameter WIDTH = 4, + parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset + parameter RST_VALUE = 0, + parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance +) ( + input wire clk, + input wire reset_n, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + + + + + + + + + + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect author = "author-a" , author_info = "author-a-details" +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V +o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE +El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY +kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc +/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 +uYJaS5tuGEuFInBHa7oO8g== +`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 +fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa +rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq +PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL +DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w +K3OoKmk3zFeArSsql8B4/Q== +`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 ) +`pragma protect key_block +RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M +GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l +6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI= +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf +RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk +1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw +Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz +eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0 +2HflB1HYKxojQCcZU7qUgQ== +`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx +Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB +rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr +XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD +e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod +B2Zpo2FQ//YDRSAaEa9ksQ== +`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze +vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 +ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 +06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP +fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN +ZoPzFCMjGk5ZmMyIlytNCw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 ) +`pragma protect data_block +0d33xo/2RnBYy8BD6jq1J42m9u/75PA0owNvxlnr0TDOq7sF8XT6xouctVD1XQW2 +Ylwj0urY+dCJZku0aGRpcvb3H/nTlKVdEZOEl4QqB1gNGz/3mz75A3eudu5zgHEr +MaagjyQfDnoIqLWi1r5uTZrlS298IvNcGAJ+xXzpmkFmfG4Tk/5Jf2GPAPVtjREI +01kt8Go4CL1WNxBKcwm0xCiCchxvZ2oEtpERiC+7LUalgTJapIVoLFpvFv98229k +egvgF1KHNj0rAKedSG2Xo58TyA4iZXJJDdtgCxiKgu3Rimjno7l+ekApwmvx8n+p +yHkRGqetWfRhyE4A5q03RzOeSdA6NbCqijB3NPw/p58brAbA35rrjYpGIZXtZ4mU +De3As8VtD64nS2PRuf4/a2lIcDbwMjNTfMpN7iJfVBJ0/48tLHdetx592TLXenkF +GvAZ2yxoyBYzKctj4Keo+19Xp1UjVd3fr2MR3A7nmxLRKDA+upDxQ7ql8+pR7Moh +0b53/4Ri3Mkl+7EC1KXJNt2VbkZmcT7OAFIoPpibmcXS2R6DNVrhSKzfc2+TRM9r +mwRrJy9/R5RR+WGfw1S57Ho3wBPf4belj+Tfd7yhnwOVRXkTMq5M1BiigrGeeQ3q +z/hc1Kg8b/R+g7lnU0pqASnExPQW/DIMfH1RX75U68CAgaBAH22Vcbkoibp8sxyO +g18LefEh48UffnbpCKyv7SQ3LAdj+YO+KvvXHj1eW+CH7GA2lC5vt2be5Ah2/13H +bCeZ+srG6r7wmafy9MNNh8AgjUfZWwMnuJdCIcHTOfAncCd2B0T1Oza4VIkvnSl5 +60V34JXkfrGsNuHxwCF/sRSBbZUSpqig4ZGYHjOHldx2OANZQeUvLES3fwScYY5D +7SpR4ofVxIB/ev/+RXzvC3MNk1N0GT4F1XwokeeQIr/ilRETe/pFvEKttvviZ7uJ +uEVblS2v61DMXEgDavkbA0WdhMChPulwDvZtisWT4hCKRxfuBvNBtz0wH/WgRoX3 +aipWvPJG3G0xvO0u0EQVNdcxE+LZ7vyGF5HWEwKdQYDyhH+yVDeG+M/b08dU2aq4 +sG7dyygyVnzVbk2Lf0nCkGqKkUZUr05Zim0Wcflkhkqy348SOZ3xmEGuYAkzelLV +feQ+0ScsscFL5Cq4ETfFrN8GO8M5kkBN2ELs1MQecPRsgMCh0hcvd8IQrJTybQPW +aqwp9mgnFvS8AJ1ct+XgrAt8zgVnhaZGS9TKa6OWbr0U+SD5m+/pXjNsZA2dni6b +85/PmQeWeAarE/+EaJn/hlP6y3x3R3ItU8Itf6SB50LZ17LAhIRSIYsa7LBBNWOk +ngFHcGBCJnqTJv3hdVqa9cYipZ98XCa8dqrtAM5Rkxwd6H8KxXA+B+PWEz/cQWlb +szi9u5ufmyaJp6PWhklroQkPJEorUtF96X763itgtlAMHfkZglkElUD/gPlkXLtl +yquUmHqPK5D2pJDq0Q0jromE2yrr9fl3OI+eBehd2YBUivGKeaDFkPx7HbzWp9ok +9bT55H8VKYyF1awcjNND+WcXzm2WfvZHBDUJkRm7dnOQRvcX2RxlPRZSzAA3irVn +GFbHXD0RYn/dUR7Vy4kU68P5S5q4bUxD5vmUCN9vDoCivY7WCnlQCHQs3+iFblzP +A636C3dNQMSw0pjDisiZB63VczY8bivFh3cO82inNw5r2IZjvMB9XPhc4FHuIpfR +F7ptW0TUnO1MSDcZvCnjUfVSnHN22l2FM/P5oI1SbG3W+8YmxBvto8jwpES4ohOQ +YSECrvWkLklq68FVTzB7Tvg3JLdSy3TEKBuZE/ot0w/SXusFovOwd4aeiNDAmzwl +fQuCYHuJ0UKLaVNVAO4mw91PJODKCk2NYTr0ghOLovOXiMhUYtXZ+wFchXVkQKDI +B8BXjM7P+blhoOFA6AhRuCX4gZn0dP6m99qnyBJoxf1/FyfJXuklnPll93amUYUx +MzxNNTf7F08tnKQ8pTOk2mfFZnhA2MFn4XQ9FaGvtUrlJI8bvJTWiZFMF0eOJdIw +kzYOXEzKBjIdWW4rtTZmQJb7AOrznUpYdgTAPip/DQx6cg1+tZAVwhZPCjCsb5wa +em5hMtISQKDc92QrlU5O74OXe7641fzFRcKqy9AzwhZl+tmHk1uvpDkpsYiMa7Rk +YrbIjsKQV36PTqYPvxq1EiwYF8PMRf9FG8JZk85EZdM6QEGuehDHqFcZ+SlUb7/e +ji6GgjKxcZwaRREGKSOslcscHS6QNuGCF3iInqNCT4V2l7nboWOefMT2f1kmQOdE +szTFg563SQ8pu7ok3T3XNqUDi5ulvF+XGHDhcQ2hTkZ+xQ8dHFAWZdgzEGMXF2Lw +jU+ZRA2JULfjxOMIU2j9f+aGWmFx2PELMA5K5uOWYUQG2Fn04p1D6u8MEe7fIPeI +k7KH8j/Tumj+kG4t/lCrme6VM9u6A2NGddX1yH1NCejfophy3UWJg9wL/dNxzf6t +vXdm3rGPdZPWFgSIuGlmT03QZmWGPbs8qvkkUVAL37kMJP2r4L+PI00ZxbX8V5jp +GgYN1Rh+NSOwAcUEFCViRhFYC+Gi5eZ6AF6XDSU6qfjGsUKqJ9yrNx0Km6+SjpAK +7Zxblp7vweFVkJ7IESoFeB+vP8JNeoidbBPGEWo+2V08PgfGgjPEAA6pjj8uc0jC +SDFZ0sVrzvc66PZ5FxbI4g+VuXPJgyJsnQ/eHhPVTVTP3/oGMRVktNiJrkJYxAW7 +Sa/EJMjfXX+rMIWG5ssWLT6WfrojlHduEqJ9hJr24RZy514HHF8SMPRBLD6l1wd5 +07U/ChjFdy5qHn5Ce+lanjxnoxgvCsF3lMqoZ7e2bfzXakj7CxahwqRt6yeU0Q+/ +a8tvIJgHfdtOPw/r6HnSrzpdWzTx2e6/MEryHZqpMN63Lhakpjw1L7u3FD/rW40b +LGajigQ7Ql+cZmP7wYl+uSmTFIS6ZgXOc1ibb7yYxJwpeixPHL1iu5ltvriRiTZ6 +DMbbOjNpPuL7ie3AwgmwXwnpnTL6k/Rj2+ma3B7ImODBMkC4SLtTc0ynCcPAFZKA +Xh78wUAgt1T5Nm4XR555DBO7zPHX9rZzMLil4/j0RMDwn1gitmP2PSNFWsrXJG8p +C46kfpdqoM3Yf6HySlhsith6GW41sMF6imUXwahQQRw240HLW3N876LDe6bjTmgN +eIC7y/4NZk7OmpmP8udAEH+UsNfSGtKA8959AoJDr43XsWkOfccNWstu4sTXA5+w +pCALypmBMdholEsrW9DgsIgbgf2pcOAC9+mAjld+yyQ+UNdKRbmtRDHTztGmcVvw +Szip4YUuTM1tPzReucfm38gVFT7eo1qFQg/FJ4VgeYab7ku5OHuwZQmKyzng/t0U +A1lquVENVYQEIotBiOC7jQ1YTkTasGN4xoFgFTyKLFPyk8bl2/anzr1Fx0ieVGCx +2ipzG2JzIQf/FlHXaYrgkWiF817amty+KZp4/dCJtvDXxzOZKnBTVcjHXpqR1Ik+ +tdV+k+21tXZxP0rkG0yi4//2c5UiWGb0UegpemqutykLuT9tGjsqMuc5DaDH/8zk +wLTVfODT+HqN1/ZLqfq9VoAF5m/ujnPNt3wZcsjsAyBD153rW4Q2yVYMat0sFQN6 +XbNAeNBJZlO/aE1PfKBcSDFkJkPqRxlgdiE5B83/w1MP6Z4qwz7LJ8yTYM22xwRo +LIYpKq52yYMhJm42YeQxbBRTx0MyubCb+ompEVBF28Eh0vE98UAZj7t1szSweg99 +Wq6/4kxR2SQj8rFo2wrZe7ngsDmbIrMk2SinS6WmV4Mj+MBbPlmiuwB6NUV04Id1 +9enBBsJIfWt+PZJXyWkOoG/fOVBUxCY+CMCiab0qQ1EVdhggrdI30BgFqcLjfyD6 +/h5AqIzMGWrhWnap8WDEh1Ah6K9f2oCESSXO751sV5eK8jgl63FJMIVsnjVejxrl +Qa7PCXP3BO6Cnv896NBzAsddPq/AYBLHIC6eX3sTtOxTx52NsmJzoyUSJcAoA/QS +leHU1bLA2z+HGfMrkSzsuvXafmqr3B+PHfWdxrYzTxmVhMBPX/FvEU/gfxXGa6kj +niZYGue/Rk+zXL65ENgPwxiz0mm7QyQ6eMBMRovm6MGyIl/8obkOPygH+lhc+bgR +SNWLmxqjR2YABrKsUgCITQ6GK7VmVR3wOOwbZs+YW/0Yj2yzg7ESjaeqI40/OQFD +Ft2IHaURJPk6jl5vRrcCc0J0GCy7CK0BU14n+Nxfl2+CFRe4efoqZry/CmY2+S4M +p9OqgjUzHGSIbNRAXHf44nIAUjWYvijzzLSj9A7WY3TpYxgtqU8Wbf7SbWmw8RJV +pAYDHGmwHa8fL4Y9xEFF/WqmqWSL3g146i41MKWKY7lchvnWtc6yOgk+0geVFOpe +9BLs4TehFA/SueFC99S0Cxcxc0KMWXOKm0I3bI1CAlLje7wUcdI/pki33iqBLJlL +T2vz8ptPqfgAxDW0ZEvEYY/jfB+jCO0MKT7XK/LZNYSuEke3Y3CeuwZ/5IWkDcwy +7BArmDy7Hpw88le9ODL94mS1fUB8jsBaazeiXniZPNZjBkugt/ZAf4XYuoaGVPAM +DnRd8GW5eiDHFCEB42lpg9n7Ak8cXsSSlODCHeay2VtcQP1DEgwWdI5XdXE879gI +8lLU9bH2MfsxI2mNWCMv5immaioZJDorIVzyMGvIn3OcgqmhTU1owINUJf+Hm8Q7 +JfJq4m6t0J5eoKQH57uSGFkWRZ3dtp5QL3d5bBOMmorXUBzdrLt8wurvNke29bHD +UQdmANjayV8drYWAccZdPWyi9jNC/K31BTDI6RCpZdV3Wr5scOZdXWrl961jirm1 +g/2MGKxriuH2F4MRIh2vp3uS8PLbj4cHJv+5+LtLgs0lpdEMYAvJKDACRg68tDhY +XsF9lhHpcF5+tANOawRtnSvy/rlLn+A3wi7v8tnTZcLkocJ51c+nK5/Ij0YgUrA0 +eLrKNlJM78stswPWkvpBlAJ+G3D4Cw6P3XcJWrLyV3u79jf9PRJZmxMU/COGTmgQ +PJdXp90O3u2Pjdwhp4VdtBK2d/jTpk59j8xbQBavf5flZ+PzoLpd8NSt6GdPVJ5r +uVWvNy14pJXUsn+Tgxj+9Wp3vm5mofWtJAkEgr/Rfp7AVLLShJSd6vsbT7F2+TS/ +OMDv0XH92v1G4tqJ0rbxS1TnxX61+1sfjKlfIQdFR9gxLy71Tb705LQHBAw8vmSx +X6Uv+HbtPaEqRCF+pdvGsLNI2Seo6INA/mXqNpd6VPhfQHtp3bgV+Hxnlcc9lCiI +bCZq6KG4a6sVQHIZ3pZo7PQtoAo22niHvgZFoOVnBv+bu+blmvSV6gxCPoV8rwOe +/WD7YikHE7WVSq1SHtTIcbPv+K+1NKqZIiSCS2qDfJLgI7vH4zjIqibDhzGZTeKV +Km234SSlJ1OL4WQ5FtsxjednjUIAKqVe1auDiTzAKY28dwUkwGN/XXQ+EjrmxQuL +qIAT3WP49EeM+CQCp3D6Vxzm7Picq+RtwtbAXnnSQtvPcaSprODI089a0iR46Pp/ +4DLMUOLS+01HozXF1589YdqYep05No/Fp4eP2RdQxicYxK8d/OcvG7E8F1URVmAa +XdZxVa9caM3xYMWDZaiaOo6IZ+YM5VeZ4KxUblS1L1IlOnGOOZ3AiaLsHOh55ryc +Ei7EaFpheCmlTJyxUg8TdA== +`pragma protect end_protected + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ctl) # ( + parameter SYNC_CLK = 1, + parameter SYNC_STAGE = 2, + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter ASYM_WIDTH_RATIO = 4, + parameter RAM_MUX_RATIO = 1, + parameter PIPELINE_REG = 1, + parameter ALMOST_FLAG = 1, + parameter PROGRAMMABLE_FULL = "NONE", + parameter PROG_FULL_ASSERT = 0, + parameter PROG_FULL_NEGATE = 0, + parameter PROGRAMMABLE_EMPTY = "NONE", + parameter PROG_EMPTY_ASSERT = 0, + parameter PROG_EMPTY_NEGATE = 0, + parameter OUTPUT_REG = 0, + parameter HANDSHAKE_FLAG = 1, + parameter OVERFLOW_PROTECT = 0, + parameter UNDERFLOW_PROTECT = 0 +)( + input wire wr_rst, + input wire rd_rst, + input wire wclk, + input wire rclk, + input wire we, + input wire re, + output wire wr_full, + output reg wr_ack, + output wire wr_almost_full, + output wire rd_empty, + output wire rd_almost_empty, + output wire wr_prog_full, + output wire rd_prog_empty, + output wire wr_en_int, + output wire rd_en_int, + output wire [WADDR_WIDTH-1:0] waddr, + output wire [RADDR_WIDTH-1:0] raddr, + output wire [WADDR_WIDTH:0] wr_datacount, + output wire [RADDR_WIDTH:0] rd_datacount, + output wire rd_vld, + output reg wr_overflow, + output reg rd_underflow +); + +reg [WADDR_WIDTH:0] waddr_cntr; +reg [WADDR_WIDTH:0] waddr_cntr_r; +reg [RADDR_WIDTH:0] raddr_cntr; +reg rd_valid; + +wire [WADDR_WIDTH:0] waddr_int; +wire [RADDR_WIDTH:0] raddr_int; +wire rd_empty_int; +wire [WADDR_WIDTH:0] wr_datacount_int; +wire [RADDR_WIDTH:0] rd_datacount_int; + +assign waddr = waddr_cntr[WADDR_WIDTH-1:0]; +// NIC +wire [RADDR_WIDTH:0] ram_raddr; +assign raddr = (MODE == "FWFT") ? ram_raddr[RADDR_WIDTH-1:0] : raddr_cntr[RADDR_WIDTH-1:0]; +//assign raddr = raddr_cntr[RADDR_WIDTH-1:0]; +//assign wr_en_int = we & ~wr_full; +assign wr_en_int = OVERFLOW_PROTECT ? we & ~wr_full : we; + +assign wr_datacount = wr_datacount_int; +assign rd_datacount = ASYM_WIDTH_RATIO == 4 && SYNC_CLK ? wr_datacount_int : rd_datacount_int; + + +generate + if (MODE == "FWFT") begin + // NIC + //assign rd_en_int = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int); + //assign rd_empty = rd_empty_fwft; + + assign rd_en_int = 1'b1; + //assign rd_empty = rd_empty_int; + + //always @ (posedge rclk or posedge rd_rst) begin + // if (rd_rst) begin + // init_set <= 1'b1; + // end + // else if (~init_set & rd_empty) begin + // init_set <= 1'b1; + // end + // else if (~rd_empty_int) begin + // init_set <= 1'b0; + // end + // else if (rd_empty) begin + // init_set <= 1'b1; + // end + //end + // NIC + //always @ (posedge rclk or posedge rd_rst) begin + // if (rd_rst) begin + // rd_empty_fwft <= 1'b1; + // end + // else if (rd_en_int) begin + // rd_empty_fwft <= 1'b0; + // end + // else if (re) begin + // rd_empty_fwft <= 1'b1; + // end + //end + + //if (FAMILY == "TRION") begin + if (OUTPUT_REG) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid <= 1'b0; + end + else begin + rd_valid <= ~rd_empty; + end + end + assign rd_vld = rd_valid; + end + else begin + assign rd_vld = ~rd_empty; + end + + assign rd_empty = rd_empty_int; + end + else begin + assign rd_en_int = UNDERFLOW_PROTECT ? re & ~rd_empty_int : re; + assign rd_empty = rd_empty_int; + + if (OUTPUT_REG) begin + reg rd_valid_r; + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid_r <= 'h0; + rd_valid <= 'h0; + end + else begin + {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int}; + end + end + assign rd_vld = rd_valid; + end + else begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid <= 'h0; + end + else begin + rd_valid <= rd_en_int; + end + end + assign rd_vld = rd_valid; + end + end + + if (ALMOST_FLAG) begin + assign wr_almost_full = wr_datacount >= WR_DEPTH-1; + assign rd_almost_empty = rd_datacount <= 'd1; + end + else begin + assign wr_almost_full = 1'b0; + assign rd_almost_empty = 1'b0; + end + + if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + // NIC + //wr_ack <= wr_en_int & ~wr_overflow; + wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; + end + end + end + + if (OVERFLOW_PROTECT) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else begin + wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; + end + end + end + + if (UNDERFLOW_PROTECT) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else begin + rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + // NIC + else if (ASYM_WIDTH_RATIO == 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - raddr_int; + assign rd_datacount_int = waddr_int - raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + // NIC + //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_r <= 'h0; + end + else begin + waddr_cntr_r <= waddr_cntr; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + end + // NIC + //else if (rd_en_int) begin + else begin + //raddr_cntr <= raddr_cntr + 1'b1; + //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); + raddr_cntr <= ram_raddr; + end +end +// NIC +assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); + + +generate + if (SYNC_CLK) begin : sync_clk + if (MODE == "FWFT") begin + assign waddr_int = waddr_cntr_r; + assign raddr_int = raddr_cntr; + end + else begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr; + end + end + else begin : async_clk + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx mac_reset, + proto_reset => proto_reset, + rx_mac_aclk => rx_mac_aclk, + tx_mac_aclk => tx_mac_aclk, + eth_speed => eth_speed, + rx_axis_clk => rx_axis_clk, + rx_axis_mac_tuser => rx_axis_mac_tuser, + rx_axis_mac_tlast => rx_axis_mac_tlast, + rx_axis_mac_tvalid => rx_axis_mac_tvalid, + rx_axis_mac_tready => rx_axis_mac_tready, + tx_axis_clk => tx_axis_clk, + tx_axis_mac_tvalid => tx_axis_mac_tvalid, + tx_axis_mac_tlast => tx_axis_mac_tlast, + tx_axis_mac_tuser => tx_axis_mac_tuser, + tx_axis_mac_tready => tx_axis_mac_tready, + rgmii_txd_HI => rgmii_txd_HI, + rgmii_txd_LO => rgmii_txd_LO, + rgmii_tx_ctl_HI => rgmii_tx_ctl_HI, + rgmii_tx_ctl_LO => rgmii_tx_ctl_LO, + rgmii_txc_HI => rgmii_txc_HI, + rgmii_txc_LO => rgmii_txc_LO, + rgmii_rxd_HI => rgmii_rxd_HI, + rgmii_rxd_LO => rgmii_rxd_LO, + rgmii_rx_ctl_HI => rgmii_rx_ctl_HI, + rgmii_rx_ctl_LO => rgmii_rx_ctl_LO, + rgmii_rxc => rgmii_rxc, + s_axi_aclk => s_axi_aclk, + rx_axis_mac_tdata => rx_axis_mac_tdata, + tx_axis_mac_tdata => tx_axis_mac_tdata, + tx_axis_mac_tstrb => tx_axis_mac_tstrb, + rx_axis_mac_tstrb => rx_axis_mac_tstrb, + MdoEn => MdoEn, + Mdo => Mdo, + Mdi => Mdi, + Mdc => Mdc, + s_axi_araddr => s_axi_araddr, + s_axi_arready => s_axi_arready, + s_axi_arvalid => s_axi_arvalid, + s_axi_awaddr => s_axi_awaddr, + s_axi_awready => s_axi_awready, + s_axi_awvalid => s_axi_awvalid, + s_axi_bready => s_axi_bready, + s_axi_bresp => s_axi_bresp, + s_axi_bvalid => s_axi_bvalid, + s_axi_rdata => s_axi_rdata, + s_axi_rready => s_axi_rready, + s_axi_rresp => s_axi_rresp, + s_axi_rvalid => s_axi_rvalid, + s_axi_wdata => s_axi_wdata, + s_axi_wready => s_axi_wready, + s_axi_wvalid => s_axi_wvalid +); + +------------------------ End INSTANTIATION Template --------- diff --git a/fpga/ip/gTSE/ipm/component.pickle b/fpga/ip/gTSE/ipm/component.pickle new file mode 100644 index 0000000..9dd9240 Binary files /dev/null and b/fpga/ip/gTSE/ipm/component.pickle differ diff --git a/fpga/ip/gTSE/ipm/graph.pickle b/fpga/ip/gTSE/ipm/graph.pickle new file mode 100644 index 0000000..5d12c6f Binary files /dev/null and b/fpga/ip/gTSE/ipm/graph.pickle differ diff --git a/fpga/ip/gTSE/settings.json b/fpga/ip/gTSE/settings.json new file mode 100644 index 0000000..1b79acd --- /dev/null +++ b/fpga/ip/gTSE/settings.json @@ -0,0 +1,108 @@ +{ + "args": [ + "-o", + "gTSE", + "--base_path", + "/home/byron/Projects/fpga6502/fpga/ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "ethernet", + "name": "efx_tsemac", + "version": "7.1" + } + ], + "conf": { + "VERSION": "16", + "TXFIFO_EN": "1'b1", + "RXFIFO_EN": "1'b1", + "TXFIFO_DTH": "4096", + "RXFIFO_DTH": "4096", + "PHY_INTF_MODE": "0", + "AXIS_DW": "8", + "RGMII_RXC_EDGE": "1'b1", + "RGMII_TXC_DLY": "1'b1", + "INTER_PACKET_GAP": "6'd12", + "MTU_FRAME_LENGTH": "16'd1518", + "MAC_SOURCE_ADDRESS": "48'd0", + "ENABLE_BROADCAST_FILTERING": "1'b1", + "LOOPBACK_EN": "1'b1", + "APBIF": "1'b0", + "ONCHIP_PHY": "1'b0" + }, + "output": { + "external_testbench_modelsim": [ + "gTSE/Testbench/modelsim/gTSE.sv" + ], + "external_source_source": [ + "gTSE/gTSE_tmpl.sv", + "gTSE/gTSE_define.svh", + "gTSE/gTSE_tmpl.vhd", + "gTSE/gTSE.sv" + ], + "external_testbench_testbench": [ + "gTSE/Testbench/tb_header.v", + "gTSE/Testbench/tb_top.v", + "gTSE/Testbench/ODDR.v", + "gTSE/Testbench/glbl.v", + "gTSE/Testbench/apb3_2_axi4_lite.v", + "gTSE/Testbench/axi4_st_mux.v", + "gTSE/Testbench/mac_pat_gen.v", + "gTSE/Testbench/mac_rx2tx.v", + "gTSE/Testbench/reg_apb3.v", + "gTSE/Testbench/rgmii_2_rmii.v", + "gTSE/Testbench/udp_pat_gen.v", + "gTSE/Testbench/DaulClkFifo.v", + "gTSE/Testbench/temac_ex.v", + "gTSE/Testbench/modelsim.do", + "gTSE/Testbench/gTSE.sv", + "gTSE/Testbench/gTSE_define.svh" + ], + "external_testbench_ncsim": [ + "gTSE/Testbench/ncsim/gTSE.sv" + ], + "external_testbench_synopsys": [ + "gTSE/Testbench/synopsys/gTSE.sv" + ], + "external_testbench_aldec": [ + "gTSE/Testbench/aldec/gTSE.sv" + ], + "external_example_example": [ + "gTSE/T120F324_devkit/temac_ex.peri.xml", + "gTSE/T120F324_devkit/temac_ex.xml", + "gTSE/T120F324_devkit/timing.sdc", + "gTSE/T120F324_devkit/apb3_2_axi4_lite.v", + "gTSE/T120F324_devkit/axi4_st_mux.v", + "gTSE/T120F324_devkit/header.v", + "gTSE/T120F324_devkit/mac_pat_gen.v", + "gTSE/T120F324_devkit/mac_rx2tx.v", + "gTSE/T120F324_devkit/reg_apb3.v", + "gTSE/T120F324_devkit/rgmii_2_rmii.v", + "gTSE/T120F324_devkit/temac_ex.v", + "gTSE/T120F324_devkit/udp_pat_gen.v", + "gTSE/T120F324_devkit/DaulClkFifo.v", + "gTSE/T120F324_devkit/gTSE.sv", + "gTSE/T120F324_devkit/gTSE_define.svh" + ], + "external_example_2": [ + "gTSE/Ti60F225_devkit/temac_ex.peri.xml", + "gTSE/Ti60F225_devkit/temac_ex.xml", + "gTSE/Ti60F225_devkit/timing_Ti60.sdc", + "gTSE/Ti60F225_devkit/apb3_2_axi4_lite.v", + "gTSE/Ti60F225_devkit/axi4_st_mux.v", + "gTSE/Ti60F225_devkit/header.v", + "gTSE/Ti60F225_devkit/mac_pat_gen.v", + "gTSE/Ti60F225_devkit/mac_rx2tx.v", + "gTSE/Ti60F225_devkit/reg_apb3.v", + "gTSE/Ti60F225_devkit/rgmii_2_rmii.v", + "gTSE/Ti60F225_devkit/temac_ex.v", + "gTSE/Ti60F225_devkit/udp_pat_gen.v", + "gTSE/Ti60F225_devkit/DaulClkFifo.v", + "gTSE/Ti60F225_devkit/gTSE.sv", + "gTSE/Ti60F225_devkit/gTSE_define.svh" + ] + }, + "ooc_synthesis": {}, + "sw_version": "2025.2.288.2.10", + "generated_date": "2026-04-11T23:30:05.484149+00:00" +} \ No newline at end of file diff --git a/fpga/ip/gTSE_1to2_switch/axi_interconnect.vh b/fpga/ip/gTSE_1to2_switch/axi_interconnect.vh new file mode 100644 index 0000000..4163a66 --- /dev/null +++ b/fpga/ip/gTSE_1to2_switch/axi_interconnect.vh @@ -0,0 +1,2 @@ +localparam M_BASE_ADDR = {32'h41000000,32'h40000000,32'h30000000,32'h20000000,32'h11100000,32'h11000000,32'h200,32'h0}; +localparam M_ADDR_WIDTH = {32'd20,32'd24,32'd28,32'd28,32'd20,32'd12,32'd8,32'd9}; \ No newline at end of file diff --git a/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch.v b/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch.v new file mode 100644 index 0000000..2046f49 --- /dev/null +++ b/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch.v @@ -0,0 +1,1269 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.1.95 +// IP Version: 5.4 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _c22db128920343a0ae5b4fc5c7fb0e16 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module gTSE_1to2_switch +( + input rst_n, + input clk, + input [0:0] s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [1:0] s_axi_awlock, + output [0:0] s_axi_awready, + input [0:0] s_axi_arvalid, + input [31:0] s_axi_araddr, + input [1:0] s_axi_arlock, + output [0:0] s_axi_arready, + input [0:0] s_axi_wvalid, + input [0:0] s_axi_wlast, + input [7:0] s_axi_wid, + input [0:0] s_axi_bready, + output [1:0] s_axi_bresp, + input [0:0] s_axi_rready, + output [7:0] s_axi_bid, + output [7:0] s_axi_rid, + input [31:0] s_axi_wdata, + output [31:0] s_axi_rdata, + output [1:0] s_axi_rresp, + output [0:0] s_axi_bvalid, + output [0:0] s_axi_rvalid, + output [0:0] s_axi_rlast, + input [3:0] s_axi_wstrb, + output [1:0] m_axi_awvalid, + output [63:0] m_axi_awaddr, + output [3:0] m_axi_awlock, + input [1:0] m_axi_awready, + output [1:0] m_axi_arvalid, + output [63:0] m_axi_araddr, + output [3:0] m_axi_arlock, + input [1:0] m_axi_arready, + output [1:0] m_axi_wvalid, + output [1:0] m_axi_wlast, + output [1:0] m_axi_bready, + input [3:0] m_axi_bresp, + output [1:0] m_axi_rready, + input [15:0] m_axi_bid, + input [15:0] m_axi_rid, + output [63:0] m_axi_wdata, + input [63:0] m_axi_rdata, + input [3:0] m_axi_rresp, + input [1:0] m_axi_bvalid, + input [1:0] m_axi_rvalid, + input [1:0] m_axi_rlast, + output [7:0] m_axi_wstrb, + input [1:0] m_axi_wready, + output [0:0] s_axi_wready +); +`IP_MODULE_NAME(efx_axi_interconnect) +#( + .ARB_MODE ("ROUND_ROBIN_1"), + .S_PORTS (1), + .DATA_WIDTH (32), + .ADDR_WIDTH (32), + .M_PORTS (2), + .ID_WIDTH (8), + .USER_WIDTH (3), + .PROTOCOL ("AXI4_LITE") +) +u_efx_axi_interconnect +( + .rst_n ( rst_n ), + .clk ( clk ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awlock ( s_axi_awlock ), + .s_axi_awready ( s_axi_awready ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arlock ( s_axi_arlock ), + .s_axi_arready ( s_axi_arready ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_wlast ( s_axi_wlast ), + .s_axi_wid ( s_axi_wid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_rready ( s_axi_rready ), + .s_axi_bid ( s_axi_bid ), + .s_axi_rid ( s_axi_rid ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rlast ( s_axi_rlast ), + .s_axi_wstrb ( s_axi_wstrb ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awready ( m_axi_awready ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arready ( m_axi_arready ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_bready ( m_axi_bready ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_rready ( m_axi_rready ), + .m_axi_bid ( m_axi_bid ), + .m_axi_rid ( m_axi_rid ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_rdata ( m_axi_rdata ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_wready ( m_axi_wready ), + .s_axi_wready ( s_axi_wready ) +); +endmodule + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +k0MNGAL+siJuDYrFA58rRJscMTUE6hiuNEylu7uA+mdVk/vCPJpUprjqZIgJ75i6 +csRX146zVh4AUQABC09rbvto0kqPbqsZwZGmdOm1W8NmGZIXLCsG4MZs984TiToI +QMOSc+XFr9GVx1rFODfIQCsRVOla6WZCpHrBZzFjmFwY4t9fXFQCs5fSkNbGyG6v +8YDvdegFPMYp5Qu9ccfxeosyrpdCBompAmWscbYmzMrmyFiInvb8Y5dyqCuve1NW +jirl6fz1954ypdomnZDn+X9k8zTCJAxovyf9Qxk6Q+/Pf6e6yRqEYBxT7dtZhWRG +tEQdKP3bt5KBf+EuwdVLuQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 9552 ) +`pragma protect data_block +CosGYIkH0xBRxN95EJWx839RlT4VAi4LCJZ1mt3NitRA5g2pDgJLsvVh2D1y5BVA +pdFnLxJlKeO8VGxcbjdy9+FeBPs3Bo0hcGMo8L+LaJ0bVkv+6b77n30HN7W4KS8h +FD1Ep9sROiwLtXRFHJO89i05/tAaQLM8i1caOwWOyxnOkkN9uNWnXu8Q0YVHwDSo +6edwH6pDm7sUFDB7MkilS2mpOjdUBdlO7TGkRl9TuEENWQoMfIDEVtwj5ArywPyR +ABP441amQzUHEwhfDKcPN2iMoBL+T+S1wuWnJHqvzHEb6nVPARgwM2LxvxR9dJld +dNlxyS3zC6MHchUMEAThn6/mNnJEIrcrJfsvf1vvLfpUlQ5d+C8Gj2KcQl4cX+1i +y70cPd03g1gHtWhRfChJ+8u0hcEyphEmEnx9SLi2I4xYi+fTWMgPPM9PNN1YXNHq +otMqtc2ceQLlyCdlKJplKqKXkqQdhPcZ9wt1WckUoSV+ZeiA4t7bGUWN3kexbKDy +o/js6xWIxX0ryxN/pbXUzhaj+FMP84LHEs7BoUU3zxlGsUspgAysZAO14S2sGjNI +BGpe6bm0ONuesSHUY7+4NUAWlwtPlG6ulaAEIClApiB8gBOvDsTAQbDKVkunI6rz +9cfhmqP/A1djz1i+Lw6iytrG/0VEU8wOePUdJupVohofGQa/4y+YwGciqdf8bscN +y2H+LIZnDVF8FwQqxUMjnTJGvd0s9fHCJfhYvXMWorLOGLe2wW1l63PmZQoaNVXY +K/JSkYpZKe+1jeyKioBw1ecvAOFXmnHjUXoGGiAbTSgVf2c5qN+UOXty8BIpzXsg +rEi4GkhlmS9JOl4OQehZT8m8XUc6Gk4tOWOFI/Y04qqVeyyHXHoRK2YypFTeGvWZ +QWRGXrwLYJEsSZ4pSXjO2Y1sNzJSAy/LUfHn9ih9RN4pcPd2t5yJBs9i2YKdajDd +mMZ9cfbemdV3IUPvWQsy/p+aey0Cf+JLwgchg/lPfV4xgZIc4ZIqkBiIrOIkYCRT +43pSktGOK0XWBA1vaFIbC3cpTHkDm7LQWLF6LkVws9H+W9Ui7ZphPGJYQ2FZuPFI +x4JdlFgmbh8CKDphsgQ0S9wIPIiTxRywf2P0QWvDuaAPSf1ONlDVSLZTsMpwMhgp +JNkTIkZg82zj0VVndkAznUheBGdHU1LM7Ao8djstDoYkJyBKszFcpg5i+vych5sn +Y+FPaWBO8UY1afO/VO2H3aMYvPs8Ey4fLon6Ot+jqqE2QhWfWOyr6/Y2KpZ29Tn4 +yJFhBLEGx890JscKBgz/Pty/z4uI88ARA6quPcoynMcdIZ7KuZ3//NoLU+MW5Ji7 +VFYtef6sYztFjyVBej5iPcwEB/IFI1d4rEZ5trsKDNcBYtLv8P3uUTrAbkBUrkzI +yAmsEY5jaLeFXJdeT5qZFjyy9LTRuyOEdhKoHr8lsbIvJEP8fKGOyR71wt1P8vDh +baKkrSka1ND+doDAWaIksjVzpZtoOUJMCdyqduEGaSXMoEbOLzjwCwatyUAZnAfl +WwdgTbr+jMNDwm6ZJ1uUwd/AC+w2aunGMR1WHoMDyIK5icyVab5vg4cygOV/vkym +3aFkctiYHlucNCcL8phNpyLUKgGpY7wU7kLNA24HbnKJlqAwUOFuX/TToc7PQlcV +SY9tr2TMOFipbNlOu3jeaB0Vo6yseFq4QJYhA43C14lER0DuVgRveDhb4d+kcEl6 +bNUBGSkHWyh1txe8rFLTipxEBA9OvA4qfpJLdjdZ+y3lkqRQtHFTpuHTBJs691oX +Hut8P6qCvMQWHtqbc3rdk4Y3duWralCzKqrsCmziyZIJpOAC2sAyw8ISN+HX6FV4 +qfLqVX0UeSni7AgSkhblarOhtAnfYULYt5K77BFGy/3v2o9CPNOno8LSdA2CQ6Y4 +8oZYxxqrifzsGvCdSOAPCAmUtCHm/spRjVS3wwZr/JqiazytF1OksyJ3qY9H3Yy9 +cAOg1szShsdHmj4PNrZqE6mwktxWt51Th8QjPkjALxf1zO4f7PHlTl1NxGEZk3je +MQEv/NtiqEzeRmzB3GLiIAPNaq0pD4t6Bn/pUCW3WXfO9SsCw/fk57GZ/MCqIxfz +Wzv24NCpkA9CpffUL4DZ5pcSNGwbDVK8NhmPq3jq9aT9QiYkkv+Mc1G4gDL+NF9D +hbyD1Pr9TxJIKk+kFIFIdVJBMMIcVBOb/wo37185XNJQbJ8TB2axmGnkXjNOge9+ +arrvoVM2SERpIbo8+cbHNMy1fY8ywtiIA/N9+BybUe4qO24RtzrsJHoWJ1Rn1Rg9 +jsFzaIVI27UiFjAhQfsnzYfTKEnHZu4NnbUDGzZrPgFbQQCkbBiENyXRVX360gfC +hsfv5p6XFZfrWjLL55g2EmdV93K2ja+i6klL6yfb9+nyTLI35qz0QFKMIALNis8w +JKwyRM3ThTqe+K8+F25fyT0VqHp7Rk31IMEP2PIM8pkwn7q6CAdeRoPO+rln6Jaq +onLkSko+m25UxbrtdT/oiF5b1eR4oQfUAVJOnMFjMkuBrc/KmkiTotNCeFs47ViV +02JeMX2f8G8daHyES8qCv5R4a6DKb0lrNHoojbtef/gv1HFDUhxGn5xkqlDrApwi +AI2pXanHk96xQ3jzFuEI4oQ6KtHySDBFRby5u5Xrw85f1oSAeDDHvy7/Cw5emFoc +HDu3rpfebgG3sKM3ZrUH06lrR2Im3LbGXusrWI/isuwyYuYXyWMMpsJo8t9n8KpH +DYTSNXwIpbZ/rlm4yLEdyYPxNU1X93LpIY9+XJHBugTXrRpQWNr1NjX7xUD5NdhZ +no7eo1okylN6u2/9VzwwDxzpz6E2/ju3J32x4CYYhQisuP9BfA+GPp3vwp/f8JkF +wqKCtI6nkxCXWkDrPTmplKzKJxCSAN9iwYi0Yn15/oiBTA/l9NWgRb59/zARioB0 +xX3tdsXLlBZFuH57ePS6RcmU/DHKUkyChHupCu+IunhHfEC/EmHtGsjSHKrG5iyA +27M3fpB4Xd/LeuTYo+NaEYTlANaMYUeteH/Eb1PDwDgGF2bGhnriq4JmMd+EFZxL +4FiJpggUJYd/M135cC+ohSWsHT3WK+IIerSKyD72G/xVGexHeNPt0HXhdCrmgyH/ +00tTjTHdZQKdF4CvdjFeCT8+6Q9IQlP3CAaow27SaK9BibNtM6xbsHKlBW17PUbV +JDUZOiRAtSKcePPkEXirrqEFJWBUmBC1pJgAnn0IQE3ZmUSvJeiaxvyAHfP/IvBr +d7dr3MKhikrNMdgNklD4kU01G51cn7ehZQcSt7o1wjJ2bITWQAI4CN17Pa5BSi6x +M130n/O2tghSh4RMRXuM1uOqcMJlSdDaSSrNaXgMAO4ePH9mdquCwRLTFBdGhkej +mYrY6frqP29aFXcwtEaDxnzDmUML+UePGNeksngsXKyLW4NwfSYkwuct2paDGZ2n +l1mutyakT1UgcTYVtTym6xQjxp+fEQt9RWSaYw9my/H2vf7DJ3rgRmlnZ8VGHvsg +Q7vBtFvGEyU5LfD7czZT6ERpJCapbmEhOMibFy74sgIfFf2KYdcAr+ILpb26imPN +kASgszlpTJBiWkHVzM1hcGnYx07ltmPoEpfGnyP6w7idperxlYoUHzJa+QaXCQ4m +IoQUrcLW3olf2qD2dAHy+J7ew5IrXyg/FcEqkeoIvBM43fGKsr9BUlh2s5zm0qZN +PYg0Al3SMA2nVYA2BRPgVjfFL3iyjOFKjboMwEbHGEUMvVWE3YVgj5waDPrjRLIm +kejtSYej3CYAkQIw8DN9lhDSAg44hrdtYkk7EN9O+ASmQi/c9M9ROYv+Qh8S5Jj5 +aU1LWZY40pLJsnu1ihdw5QSHCIC/wsBAe3I+8+rEe8JqJbQ/OVOl2yqdOzJlUF9c +UnTwJIjcPj1/YZ+ouq+J52boVdYPIY03uzXfvh8/h0HS0sSBW+N9N4/qyhjwu498 +if9WWyX5QNldlEzADEOQJm9yvhTGUbOKsQHvLkq0L7ODUqfqh/4I4n3SVQBJLBgc +fJoHsaTB3UL233Itwlddl0RQZeZ44+2UurY6PPi9cs9PQHfBMGM4EEDIGczkfwrb +VXsQDl34cKlIl+ualZ8HO1RTQgonZpI3JpC67Li9mS00jWiYo+61yZ+tDOsKJpWH +rk5RAiDEgeEifE482FrBHyMs3Zi0M1ADm+CzchwS48zNJBS+Np1D9quxmCB1htEG +LpYnY4f5CukA3sRcAdKOBZiPqiZ8epunSri+QBGMzTlsy1jG+BVDiHw7qCnIjETO +uoYWsfqh1J0/Q3Ch1H17d8H75YtBWzWWaK87dTjLrHhu3IbA537Ey8THNaoKfpo6 +Q0aj4nLip/23JZzowTwMFjkdjIxaaUWG3BBwLysR00Ojci4rWhcJ3Kkl7X8mmTN0 +Q124nxpjDKCmoQG926wQYC31yHEVgDNyVILxcyV0zVb9FUIxojPKXlkmqzM6xfnz +fw2rDLAQt0aEZQ04G2P8ogq0Jm/S1PsqY4LoC9LSugckElDBF9jE2pTJbu8zejhN +H4f+b/A8yrlKWsTesVaXNrmTKFvEQErc8vi4UEaHdLvOJtJsA4Z/8zVimjWe+Z7E +RmOV1S53KXGzMg3Bs5Gom3YC9v+Vusuq4BX1Bhq1JkcGbq6TbDMG8rvG29UCt+2P +EplRUHVp9FSQ5aWP6T18iIJ4MSvhHH95hETsFAnkjnavR8q+REgqC+A2U+Gd3ibS +5fvK/B3n83x2SfyU4VcSf42zxVoleOLSYrTlIVVDY7UHQUyGCZhBZ08zXuncYYjF +40x7WtGXgFXhK5uHLyYRKCc67bdq+D7gCUnNhskDr0azpw2O7JrrdNoN0gZ0bSss +wOx+7CzZBb98+Kv8pOBrbU2pMKNFQwd70PBQWmRspVX1ib93hzuOh3uoyFCqHpDo +dkNAQR8AnBTO6wfLI1QLzYkV4XcuIl4YnivmZeWBGg3wCsE6wPJKRJtScC/i9Kq4 +PRalvjf4zDFcUpbLmF6AZ1UtSuExw4OYncihmxUpRcOGYovNufLqtmoC3q1TdExb +w0HGPIyJ/t5KEw1dXq7rd4KgLTIbgjUIDjWkXI5hfshqKBMcs+d51vLXaALHDwNz +VFU/iskzvUp+uE942PEpAH/hFlbSuZeDnKVDv3hfWSE6DnqrN2BvbxOOTSYShGEq +zjn8Xt1ZWmhPYYoBiaOAG/AFlV+tOsRI+g3KQjL+l3+iJ8yh4YwNm/A1t6BxNjgu +Rzr2KZsjDPa0qGRTrMEV4Nb5y2TxS77nDuyf+Efc424O/unlG7XwzpRJxvhYuArS +5yEuhUn+4OFq3XUJjgPeVEJH9fUxHlpKscpjAOMtsxu9lR3u3Krv37aZm9OwyEDG +3tU/l/nrzG4VEXdXExlGFP91lhygme0XJiPvLJAe8DAmTasKYMe5Rg6LNXyZ/4CL +xgjY9uYdSrEiv1J5aMGmdFDuYxfJZb1UxP0zjEGos2eCRUfR2KNwl09dCxRHOvMb +Z4n7HR1Lsqw5V2S9SxmZo/A1ju/rZML1EO1zDLkqe1on8dsPwyu774HfStaMhVGj +OfWr0AVe4DGr0jfajYwc6WE+RUAS85t27GtS9Fyu+Fz0Ifl6FdpzdUaMrJI34hU+ +i9XO8ofzPd68opcswPcO5AOaaL5w74Qfj4Q8xhdPpq+Tu/Ke9ZVLeJ2rFhUug2Ig +8iHhTJofPg8GATOdo7t7efZTS1J6CRk6AVotHvyJ0RCvHKr6i1qT+lCRu9EIuh8b +c5DJ51U1wh6y0k5ffYzFK0QsiujE5huyTFT1LNJrUwApeB8R27kVKSS1mSM6mz/4 +LhNC5nzo3JJ11XmH+ozwXTeXhsQS0NdFKyZJfW30fwgmqcw6UbbzbytJudUsG96L +dRmHzENmUnzRgVsSzB9z0tta/mIJ4aapzp2MPR8rmiiL2oDCOM7uZ7OYrmddzZEG +VsiMxJYOQb3s8MuxKfMIg3YMeKsTXYx016ZTW32L41w6HxqFFEFHIDi5qw2h3H5V +fsS6IIfvKlvfnWt95tO2k5LPmcYfl1Iq2QajQ/k9kgVyiOtAyF6pl6qPWKumZlli +pVcT9mTerAsGA02QLxeAesN8m3ojtpjQ7ZecB8QnN1lZArmeGkrYkGazFArgYJOc +Z9WOl87htK1txyN2ss2dAtgXRZcnDHm9G6NZTckni0CLYzPRXGqPg9Qhzjamx5O8 +RT4JZ9dERJ7nL8hT5uxmMFOgtm4/bfEeYZknj8uWjXP+yPdd96OH+PQ3mRaJSnPp +gmt3/SYLcyLjt2UF+k31JZ3v3y38zo/YhpP415VKsCcLerK7ULokgjgcr1H53Z91 +ss4huvMVNioD7eCutHG7VhRd4W/734DyorcglRWZDFQiGryyXMyhuBqv4z5xU1mW +ItulH01TTC5lPpPqvphq2MPOwMQ+b3QeCdmny98NSvIqy8FDfavqvuwWmIERgoge +QnOe6ytg+5qB7E14cRHWZo3OFGM7jTDvwvlQ/DYMpVMrG9FNr46ij3vTukx0bzDP +iiYU5ltHRny5B6LRyQXJXJi0Xp0UsAfDD7IxTFp7g0JsXxhRotnjqqmsRHID1cUt +9M29af7bU2mdNbhf2ESqjC97RA/1F2AG3ShxJxP/lf94Stc3VHbqi3fB0Nb7Z0rt +FBQk2c+uV1tD0QV8ho4vnUImlUXdPrwbNGamviPOtbGIMPR3Q2Fd3qj502Pi4OLp +Y9GhrZZz4PTDP13vlp7aF9q1vQtZALcOZrLT71PJB+uu3zCkg1e/Jz1UkD3Hpdot +vnX039fSPcJkyJsBzc9tnNlTL/Z8AJTq7NxaQ7NA+bdLBfV9zHhzMpaS7lSiF7lz +YzPwLB0oKTTKi3q4AE6Nm2WliNx4rf8rWW9VJ8IzO8zHgD/03cmdbmGPQBpPW36N +LwROtnLY8u1XRz6d04nrrYBdiG9rU+XzUCfI/QHskulQyMlZRa37gPLYNvcfF1zz +YbUkrCqxnHSn64xnPuQQZGjTk0kQORKuer5/mLjwqy7CYRZyULRinMASnzo47ow0 +Jx5Py6hznQFjAlNlO6NbGbfw7JgaI9kE9tCSZ9qXQtoZ/u5tgswL2R1CWBgHCFlv +tvTuqNwuq/1kG+48jFD+f5O0zWiB+R2tF1dzOaV8GNsynKgvHiLzhy1sMPs4P4U7 +JcQ6I1rV2mD6mKCNsPg5tLWFzi6vgfNkDw1xSaThZVwp5RgGryD6/SO8DSEE/h88 +n8LivWzhC/tLb5d+oXOI20PLwqKgI1qDbEo2/oZdpkHRgurHQ7pLzNPHmnAbjQvx +g0XQbnCPfZEJt5Jgo4fRO9xfXng8lTQbYTMQH1rJg1sGElIsdAZGNPNOP3dZezGq +dJTB6aMp5WUo6wWFvB/Fv5JEHKW1K5SxO+Y5KjnRSbdgpfVKyaoKAutYCcd7q9wJ +7wq8Ft0TT7UMeBPqGvknTXXm8w90V4MA789DdKbGXyx2VhCTLwFjVz2ysT42UJwM +BYbeELCuPhqp7EE0v0ysbT5MD8oPX80U/Dxeq39wdt9PFXAWz7gHae26N3KZdiKL +NCDN751mf3ccCJxy1qZCnQz17ToP6ZL2HWOQzZWBfYTjV+y0md2sNArb/C+GUmri +sISKA+Vp8Dk8/CUrUHV2q02iBFkRJ61QHNEWtqKNgX0pepYM9D6w8Ah9LgHgXgFx +5gJIng2rqOhaDfnUQToP82HdamOmHnCJ/gBNjaqMf+7bn9jVW+hjVY0ZPxCuQPAv +1uc3Sz3q+ZrNKVQmGh29KI7oZtTa9jxhK3VzoSpGNRCAS/anWSq6Hd4Dumm+oSQ+ +lHXUz9881/TiGnzog+eC5nc6O+Kc+wXbT7AmzsX9/5bjf/hrxsk6rEb/ixtHkB+i +GLu/cSBGVfFY01E/YTWetYSM2zUxrItaFaMSEVAkWnKnCLXVUQpB0Kz9qwEco+7U +Py/DFCDDPq/glDrxPTRPT+Bs05xxyx/2XHt+bpq+MsU44Ed3d545oXNyt6nEZKlM +HOAZ5hR7iRN9XTMHcw7N0Hj8w4irvXFIqQRN1R1gA4d57+//KLgVI3r2muMQiZq+ +gB95VPq23ELMxr3mW9TIQ4fq9srfL7AJ6hzLO/MWXkGwkthaudHThv22nioF6LF5 +tCyJUv3pc3xQd+G74SYee+s5YEbqoCzHmTvTz45mQm9qmLgk4ED7FC+8afzZrUWY +DZneOeh1qUIZqQgu7e/ftQc1kB0mY5qLngSaDlkUPHBplUlk0xcNVRqStxNYlyt6 ++egXrZOyty/+FX2wypnXy44ivJDKWIKpNjJKJFXthsSWtzyJBjGY0VttbNviX37j +yuoKGTphHdm7yZ1DRQvtUmr4WGTicaSfUC4oZttTtofEDAr2qipUF+LwUWGuGgWX +0ip/rhABZEM1UuOu6WNMCSf03YDPsXSBqg2ju1rexTk3z53VGM1cbU36G+EzTGim +S00BfgwxVQvdBJ8c0ORYmiZMNYt/IHd+dAFtWEEGaqi5na+rlrZ8qqy1rOufSZ4E +Lhgwp+mPd5p3ZNoMT2KVo/hwXvMhUpucwCT4WW8xKxPeNCTTww2i+yZxZUyLc8Pk +048Kzu9YjSoKUHk7r+hdEa0+CSnuWFARj5CUgscPrIse8Ty1lKKYWGPXQ+OoJC5p +phKW2nKPBeh5CDgRUqlFG/xj0O6dNq9telHYAWwBohz/6adUKI4xNUWlBY8FRTQ6 +hXKVB3iRnqlC+ln6f0fZ1KkT0rvkIBsiJF3tIVbOIGrGsa3pvqiGAP3iWF7BvOPF +5SY33+T7QbZQtrWpft43XUQomKj7RJNdoZpJmmIrVxU/JpesGd4n8Qghy5mRyV7H +aqnTd+JmRocf5aCjFjvYaHR8M67gylAm6h+JZSW9vDwyKv5KVBRPd8oaZpTaqqwz +VkNrrXv7fqDnSTEtoKetTp17kp+aF2tA0wamRKJW6X42SDtFKtinBnd1MFfmq6qR +Wtr+oDpNotRs4Cz5Ml/ETb9V+ctLISmAFpFZsXKMNEBf1l67EaVHhQHshFVo6MmE +gfaISipXVe57j7bJ1c1F2q+UPOTLK11kok5kuoZkZrSRdd0nY1O45diOkMe0f8SQ +s0PjcMXSCOVG5R+NhZHxF0GRm5GOusqh+luad3/HtsmjD2pBaT9TIORoUfo20Edy +hVQkeAWA8z0mjQv/kB/5N+qKVIlRuyz/cOV5MKmX0HFaBurRHbwv/AbS/5Uh5ZPX +F6m0+erd3l9ccqBuAvItaw4ouf/pr1a1kMDjez6R4CxmGRynS7E4al4djdLT7ZE/ +Cf4L5W55tyE3A4zGbYuwXxlvzB5otmjIARCVPaCJsDLQVvQEaS7/OFItoPSCuObn +w0w0h/4Gs7aqO2bsGPGLEr5fMFAjHsRiCiRxmmHUiezrEjiymz6RaZwzb4FFL3B3 +gpGoZRbffCIVaBgKnq1rifvnYtZbOZahg5UbCMALTRqj64lHxRKUaT+c507MBzcT +2A/xQaaMXd1unIp9AQPTmHGneDmpNpipbUwik4wZUVRBaaucrLWrG6LcGp4icVlK +QWwb+t0Ngh3nQgB8q4ywRv39xYJ+Ntu4vGsXz9Mt+hM4bjRSfzCFgdaaNQqqFNPB +c+dC2M7DsriTPTygks9wxwuQtzSECp7sgpkLEWJOGJLy4LVOCFyh4jdmMqdieiHb +BN1iscgTk91VwkG9+kQIgHStsiOsI+n81iz04jxiegCP8peldNSFvX5GYFHWotCO +ht0POQ1shkziTXdydE3F2umaRkAI72qYls5BhDPyfHP+Qf2ZsBACz5UId/nxPeD3 +5aWDupx7LBRLGH6oR2g34oj92Y/o/ph4b+Np1R+XmV+ahBA7RpnUVe6dsvN6UeSR +WglN7R4pTf2UTS+KD72r8aNQlcjwZ0DiDW14GW75OHxf3G5PZ+/KCoucxUfvZRNN +PeWX0pLfgCzN6d61NADCpGqzRaV8N5hfevJ7lWFXsU7hUXFMQd9d2YQsa6Isi2mB +rXHS3ReefPS4PBVhANGSzG2HuNTfc0XTeROebUTT8czFCvv1nRkph+eif5+w9e5Y +wpqZh64iUA5G1Lb68JAL5l96ntIzk+XHzfkF+bA+7E84hPgedhaTw2z4zzESxron +mWxB+8qJnZA1CXsD/PxASxJa3afR2iH0KkUDLyERtSBaZUV+ORUr0t18zpDlHE/0 +agC9ztwh4doxddnpKEXFBftpZaVbKsOypMu1vQFBxVPwwoKSgpcVcAbzUkWYnmJT +ZLX+04cd+Rh5lFe50K/JPYE7rw0EsiqzZFYja0GT/aY0i0sr7ggBv5PGox89DaPR +M+mwNkInkOXxi3MHyRrVITAGp2WcOXHmmzdXO6qpeExaBdhW6lBRDJorwAyOb1cQ +h4SZw5YdoducErUAzTrkd7VelUlhr/w1jZ/31NgyaSkRVOlOmJhTDTmxs83jfWTw +eZSGDO9ZvtDIgHBr4CLE/5SyxgW2lJdgs12MA8AmIFHbwTQRp67rKqD5tqjFON0Y +icTpZRXGj9+IXV/OlkjnMVKeIUjhVP7M9nzyCzQSr32foBsBoW8qEOEIe3Hp8v5N +jka1PWiaeVsORmiFSEJuNQBIbwKLWj8WpOQIU2WBsaSbwLgxZbAq6QeG+fWoHvOf +ZQsrr0aheaJ1sEjp+g7kcRz+OkkxiMLp+zqstbX3HepZcLcjE4sP9r3nffEF+jC0 +Lk6er739jGapdW5xc0mLBK8kUOlRUTOwGvfTMZv91gZkOwonaCOJcYnvoRnSZajJ +ITbUtQ5Ur/sIl/RJ48z0JlENCcZ5t1vwa7H3Iqh1SEDh3QEShy8erQMLb3uhogh1 +2PUTkyH2RVxTZrAjAmn/EZzsLf9st2rU4988fH/F+WN0fQ0pSzOjDOtT7Siie5l1 +LjFScPHYqlnLkl5CpaeHJ0bNu67frdavI9wj3kQzMRtsgTzycZJ0bvA0r2xRq804 +IYtaimeUwIRwg9NoGtcdYBL6k3beA6SMXeE5QJ5GZJcrOhcY40zgTMzcSKrkhSci +cVWK/y9yq20tFKRC95HuZMO1n1sCKpRCez+UluPrmyEhpj9i6SVFAyLhCa5/1T4Z +aIRK2609/+UWwhK/rFMYSAG+AMpFADC/G6hevSzwdq3nPYFNjaJEwuNqdgE08CfW +ZBUzJ7aBGw4QZS88aLrb2T5mdGqHWOCwD1F/0jpMDMwccTpwYqhcuixKy1IGDFsS +SxZrlEdxBAVpAlnWz3j6VGyRiLF2Th76uYHTwEeg5CwmofBk8mtQeHzyU1XelJPd +gT7yvnl9TUpDQ9uNnt5CWKAOy0jgC4lB+HILxpFgtlZ6+JawKnbbBmS5MyU9qsm5 +k+aQ4yQNdP5xyyXRTgyvSa21DiHvgzNv4xwNr2ClPh9xrsILpHGIviphv4ekwk8Q +pTFnZsWkl11LwNCbJZudB/3n+QXsla1k8zBe0oZoHDH/D7ao0GNmpuExKQohUuYm +Bkun4xAB77mhH9DoSaVs+zI5vJcDJK0J0LQNvZfdLek55LLkjLQTxvOKtb8IOHUa +R4PVGheykA4RribJ4gUmTrG4SxWRW6V6c8w/COxUBq6e9X3emTum0BXg2S97ddT/ +ugRqIye92Xu4glEuBKiEiSsYkCRRFRLfy33mg0Qh/wkn2YK6ymErHe3Va/xaHd53 +u4ZQNfZ2zwhyvScbaIIKwvMZglPNQTVKJoYdIRbSsFKAxyxhoiaeAS0e/PnTJrur +mmfNVhSaIcrbUmWrPtqsWn3ytCkkxdFXeDA1Mrr7npc+5MZeGWXYymgb22vn9u66 +VbgBe6JhB4LsFBymmlL78FBkH1Khl759XHwSqWBabZ78Nsma4wBoKqkNERIlTDFg +hM2GSRsibel4dwsBaKSh7XnXS1WialkaMX5jTQ8HgRMGL4Ieh+pBP14IyC8A2PgU +GZsHuiFP6gjnfiXafDlwsG2t85g1g3HW0nfk/lb9mPz9S0DrQpQgWE1hBizL4CN3 +c54o8MNUpj9kGITZ4R1NrkRWVKJGNeLGXMIy6MgmrAN6CjjyfID3jAe4CpIuUinu +F0uKdEsEMvl66AbaK2py4LZPaLpNpA+P6DKvQhVVBJjaOwuoG1zEvKavi+L8J045 +cuo6cLFe+aI+c+Fgl7dJrgLtCXnNojuOT/+/O3YbGWgGMJLq01mnSD2isOXdr1qw +zuL8aJHMRSJgY7p43KcdzyVbc0+0ala94PYpTuLaVVsYJGpyHHMCgHJhZFAgdXtg +Ux3K+QIeLnmphG+CLXWnBqNGzc+Y5h65JJ/Mo58vnrFb0gtG9qNf1y3lPp7iqFHj +j2D2AylIbNJ81RQmFx2cPoX2PKiIvKb0Fy6SD5IQ/2FLqRJqVOjnwg3Uu1AQ1NR+ +OAu6M+ioz+nfZk6rwKkJjrU28weaeNKuNtCQOwbaS39NwTHRNDybrXbAXbso3Izx +hHULq89G/WE7fXIJJ0uNZj/cmIVk3lVF6/9zsx2+nHv/XUIhJZx9EG5LfBBVc6qr +CfMjv+9oxgyUl/uPWDBsm26tkTV3DbbHeU//M/nf4KYRWNdwUirBLfeGqxXgdZFH +9mDPUQ4z6WmHHr3T8a0VqhMnAY9JZPZWtcaMhdhuEyEt5JTTJAmmO/m7cGRh+U9j +Oylxf2Mb1LOHffkW1XhJrQ3bDYFPbrrvddxJb7fYr43RlXkG/NtCA0CR7fzBlhtw +oML9Tv6EfavyLW/lnsOYIqZT3EexL37fh5q/U6iFfb2Fi4yP0ihSU9TcISR8bkn0 +`pragma protect end_protected + +//pragma protect end + + +module `IP_MODULE_NAME(efx_axi_interconnect) #( + parameter PROTOCOL = "AXI4", + parameter ARB_MODE = "PRIORITY", + parameter S_PORTS = 1, + parameter M_PORTS = 8, + parameter ID_WIDTH = 8, + parameter DATA_WIDTH = 32, + parameter USER_WIDTH = 3, + parameter ADDR_WIDTH = 32, + parameter M_REGIONS = 1, + parameter M_CONNECT_READ = {M_PORTS{{S_PORTS{1'b1}}}}, + parameter M_CONNECT_WRITE = {M_PORTS{{S_PORTS{1'b1}}}}, + parameter STRB_WIDTH = DATA_WIDTH/8 +) ( + input wire clk, + input wire rst_n, + input wire [S_PORTS-1:0] s_axi_awvalid, + input wire [S_PORTS*ADDR_WIDTH-1:0] s_axi_awaddr, + input wire [S_PORTS*3-1:0] s_axi_awprot, + input wire [S_PORTS*ID_WIDTH-1:0] s_axi_awid, + input wire [S_PORTS*2-1:0] s_axi_awburst, + input wire [S_PORTS*8-1:0] s_axi_awlen, + input wire [S_PORTS*3-1:0] s_axi_awsize, + input wire [S_PORTS*4-1:0] s_axi_awcache, + input wire [S_PORTS*4-1:0] s_axi_awqos, + input wire [S_PORTS*USER_WIDTH-1:0] s_axi_awuser, + input wire [S_PORTS*2-1:0] s_axi_awlock, + output reg [S_PORTS-1:0] s_axi_awready, + input wire [S_PORTS-1:0] s_axi_wvalid, + input wire [S_PORTS*DATA_WIDTH-1:0] s_axi_wdata, + input wire [S_PORTS*STRB_WIDTH-1:0] s_axi_wstrb, + input wire [S_PORTS-1:0] s_axi_wlast, + input wire [S_PORTS*USER_WIDTH-1:0] s_axi_wuser, + input wire [S_PORTS*ID_WIDTH-1:0] s_axi_wid, + output wire [S_PORTS-1:0] s_axi_wready, + input wire [S_PORTS-1:0] s_axi_bready, + output wire [S_PORTS*2-1:0] s_axi_bresp, + output reg [S_PORTS-1:0] s_axi_bvalid, + output wire [S_PORTS*ID_WIDTH-1:0] s_axi_bid, + output wire [S_PORTS*USER_WIDTH-1:0] s_axi_buser, + input wire [S_PORTS-1:0] s_axi_arvalid, + input wire [S_PORTS*ADDR_WIDTH-1:0] s_axi_araddr, + input wire [S_PORTS*3-1:0] s_axi_arprot, + input wire [S_PORTS*ID_WIDTH-1:0] s_axi_arid, + input wire [S_PORTS*2-1:0] s_axi_arburst, + input wire [S_PORTS*8-1:0] s_axi_arlen, + input wire [S_PORTS*3-1:0] s_axi_arsize, + input wire [S_PORTS*4-1:0] s_axi_arcache, + input wire [S_PORTS*4-1:0] s_axi_arqos, + input wire [S_PORTS*USER_WIDTH-1:0] s_axi_aruser, + input wire [S_PORTS*2-1:0] s_axi_arlock, + output reg [S_PORTS-1:0] s_axi_arready, + input wire [S_PORTS-1:0] s_axi_rready, + output wire [S_PORTS*ID_WIDTH-1:0] s_axi_rid, + output wire [S_PORTS*DATA_WIDTH-1:0] s_axi_rdata, + output wire [S_PORTS*2-1:0] s_axi_rresp, + output wire [S_PORTS-1:0] s_axi_rvalid, + output wire [S_PORTS-1:0] s_axi_rlast, + output wire [S_PORTS*USER_WIDTH-1:0] s_axi_ruser, + output reg [M_PORTS-1:0] m_axi_awvalid, + output wire [M_PORTS*ID_WIDTH-1:0] m_axi_awid, + output wire [M_PORTS*2-1:0] m_axi_awburst, + output wire [M_PORTS*8-1:0] m_axi_awlen, + output wire [M_PORTS*3-1:0] m_axi_awsize, + output wire [M_PORTS*4-1:0] m_axi_awcache, + output wire [M_PORTS*4-1:0] m_axi_awqos, + output wire [M_PORTS*4-1:0] m_axi_awregion, + output wire [M_PORTS*USER_WIDTH-1:0] m_axi_awuser, + output wire [M_PORTS*ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [M_PORTS*3-1:0] m_axi_awprot, + output wire [M_PORTS*2-1:0] m_axi_awlock, + input wire [M_PORTS-1:0] m_axi_awready, + output wire [M_PORTS*DATA_WIDTH-1:0] m_axi_wdata, + output wire [M_PORTS*STRB_WIDTH-1:0] m_axi_wstrb, + output wire [M_PORTS-1:0] m_axi_wvalid, + output wire [M_PORTS-1:0] m_axi_wlast, + output wire [M_PORTS*USER_WIDTH-1:0] m_axi_wuser, + output wire [M_PORTS*ID_WIDTH-1:0] m_axi_wid, + input wire [M_PORTS-1:0] m_axi_wready, + input wire [M_PORTS*2-1:0] m_axi_bresp, + input wire [M_PORTS-1:0] m_axi_bvalid, + input wire [M_PORTS*ID_WIDTH-1:0] m_axi_bid, + input wire [M_PORTS*USER_WIDTH-1:0] m_axi_buser, + output reg [M_PORTS-1:0] m_axi_bready, + output reg [M_PORTS-1:0] m_axi_arvalid, + output wire [M_PORTS*ID_WIDTH-1:0] m_axi_arid, + output wire [M_PORTS*2-1:0] m_axi_arburst, + output wire [M_PORTS*8-1:0] m_axi_arlen, + output wire [M_PORTS*3-1:0] m_axi_arsize, + output wire [M_PORTS*4-1:0] m_axi_arcache, + output wire [M_PORTS*4-1:0] m_axi_arqos, + output wire [M_PORTS*4-1:0] m_axi_arregion, + output wire [M_PORTS*USER_WIDTH-1:0] m_axi_aruser, + output wire [M_PORTS*ADDR_WIDTH-1:0] m_axi_araddr, + output wire [M_PORTS*3-1:0] m_axi_arprot, + output wire [M_PORTS*2-1:0] m_axi_arlock, + input wire [M_PORTS-1:0] m_axi_arready, + input wire [M_PORTS*ID_WIDTH-1:0] m_axi_rid, + input wire [M_PORTS*DATA_WIDTH-1:0] m_axi_rdata, + input wire [M_PORTS*2-1:0] m_axi_rresp, + input wire [M_PORTS-1:0] m_axi_rvalid, + input wire [M_PORTS-1:0] m_axi_rlast, + input wire [M_PORTS*USER_WIDTH-1:0] m_axi_ruser, + output wire [M_PORTS-1:0] m_axi_rready +); +`include "axi_interconnect.vh" +parameter S_PORTS_WIDTH = clog2(S_PORTS); +parameter M_PORTS_WIDTH = clog2(M_PORTS); +parameter M_BASE_ADDR_INT = M_BASE_ADDR ? M_BASE_ADDR : calcBaseAddrs(0); +parameter IDLE = 0, + PORT_GRANT = 1, + ADDR_DECODE = 2, + WR_FORWARD = 3, + WR_RESPONSE = 4, + RD_REQUEST = 5, + RD_RETURN = 6, + DRP_REQUEST = 7, + DRP_WAIT = 8, + END_WAIT = 9; +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +f0DVmU/kdU862C3ryhjQlDsM4c/0bG91GM/Tt0YfOziNIhVBbdZsoYW2RTSSEC81 +yNXUBt7tFmZq4YDopiOye7MWsFmf8WWRQEL3slo6DkYqzPlqCgnjys82AVws5Cco +WGW89TXAcQAYHJy7oG8Ae9oSMdLa3PIQNp7mSA6rz4RhAKHQyvxQU3wr0zXDmYKl +CeyI1ZIu155HAUZL2bXguauGtJWtwaTXIrQO4i5/hXied5l3pm8lCdXsKbM1Enxx +V3E/sk/RBAVETx2fmYxracwCdN363LHRvYHyP4b2qkmUndhj47mK2s4d6wc/G0IJ +HQRhooSUf5bQscVy4yyOxw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 24464 ) +`pragma protect data_block +VTq/qeL5rbYMXcLz0pVnq2QU7OySLW7WR1ySFBochA6uqctGyUZMjS/Pnq7DeDQA +s5ClOKMV4s33FMhzgVOQol94f7qpRytPtHwO4wJfN4F2g5QpANsEk5OSaLDZaL+T +9JNTHQOahODVVMjsEwLu3Hf3nxQqnUpY1Jq2hY3IPT9HQw+jYUbU1mwaaPtk3z/B +wfByi6gTuDXLRhTsDy9zF2v2hyVz2yDuu+x9TSJkxCf5Ivowir1LIvj5/3PTq70h +N6f3RfvSBCkVywuTW3T7/OhSi8wnLfdctcCOumE1svbUYFgxg4J2eKZs7MjC0kx9 +BSZcpQPmbuAEPr0X4s1LPhIA3vVVwZzzfsgimy/Xg5Jay4omrboBZMNf9zoz/upT +CWeKBGZMPg7uyDy+H3GpdRNVVeOleOFSVrU/4KbsSuM7/fgKqbwL1vbL3FoZihPh +ldxqCnYv2m//sJpbeK3FtM5xLVdzq8u7WgS2RNd0wbzqdcIbA5ahg4/wV5r22Zo3 +pDP2uVlZvB4LOCQM7VnNmxqVSUNOdZrdkfxscccugLwsZ/LRvxbuw3GVqzFEQGGl +FBnm83T00BwwWMh3yKaRmz9mYY8xXcUOaZ9cgJpRVvfKPq/yHCtnHgXpEEkbHFoC +p3eSX44fIQ/EIHBkJ6jvFyA61OKdjC0gsAj02XudRxsxq76JhRuRBETksNXiKo1k +txGlub+1WwXw3GYTDyjs23iROrf853eo1PTW2BocqDzdb6AFB8CkhQIM8lKkRJFe +Ud9XaZxwtPRYYuTWsJtwVM4GEj4CNvkOejnOgYU+YDJdHD8rTmdzTqQSwaPArCJj +kicLoihoJYPKvESIM+dRDHUXglXu0AWXSDZW7jhEcQaABvy+R6uR8NQoRwCnDWnW +9BuJ5yWg7tgdBHAcTw+zIT0yNPFPQ7yHxvcocbKDsAD2v5fA6rCKo04ExCwzGjvq +VPziGDSWQpMeyWZBl0bM8ImBRJ4NCkQLZGbWwqKCClyuTbIrl5vDQWa7RFLhz9sX +7UupGlRGTMLCeM14MqNak5fz19D/+5RGFM4HgBvzEteBpWetcsTRmDKh8dM2eCkF +q2H7nGtUT0YWjVcpkgPPJmcicdlBjkddEklWnmq9D6cnsaYNoZpNgd2vYsWUUuGC +OX1tPxXPrpLFmjWWv9S3YBktM3/bRdujZM5UsMrjh1IVZ1kIkM5NM0H0YVlE74ce +6+qAltkGjRI6dpaFA+9yuH3125i170IFrl13IiBVpBn0TX9ISHDm/IcTOvwZ6wrw ++Z7v/7ABM/hcfwOpdqUsmRl9OO7ZYHEVkzHf6lRJ4reYZ7PzXV1K95g5GWTttkBZ +oGsOAbke+u4OGduinSCSzl5voGmnEmgQ9Y+D7EEWDSS4D2B27QDHFVoJFIq+ftDe +leGgihAqC5W6p54JNbTrp1GmpIYTxgcgeVRzaNAPJ8brqHqyMSGtVIRZ59+wLNzR +GLResfaurHLA4yoUlWQwG8SQ/9m1x5Vvc6kW29v8l4MG/xAfKepI92NlD58wZAhb +iF38GP4nLgsMlWX4E6oF4fWEjoPEhMYC1fR0WCYhjQxdgKN1bHf1QfRICVqprKxS +jlP+XNEiN5RIGDKZZdbmfc7vyrfF83aWJU4joLW0m9+CMgqQIXgt6AhWfNWLVIJh +7oN/atW3Gk4rnvJTEa1NKo5e4GdAkjnd8sNku3c9tQrv7oLat7/6IzACnS7wPBr4 +kVbbEHMj+PmXbrkh/0sHfGHRwoweEGBK8lyXQfwoTzTxNDrSIUBz4+7ZsfkINpm9 +c6pI5Tv/jhvN3OC6CcZIcl1GYeKjsPKGBcmsxYNz7OKvvNz+0V6gCH5tXP+UonoM +jB/lYcsNyM2cqT/SwIlgWZguseIUmFR836ZLBqXkUVOX5vsDZryDrwZdW2qhHq6W +sqbaA0xn6pIZNo3ma6siY4TypA+UccgnQbIFxbAydrBt/ywzAhUFaCzTxv1JwG+S +MT8MoLI88wtpgGC+lbXNgS46D0Jy3uGZq6A5yBgLT5dwgYcP0M0HZjkThMozilEJ +xjRR80RUWZriVvU5QGBEd8/VgNnXdZuFHNF8HthIpgilAvF6kunsQMQe4yRGMO8u +FOp4ZXUQbuG00EM2vzEygce9HsiV6hIvpb+4M56JimSJgDP9ptsRuUI27VHqRVk4 +clLj3Vz78fgBb8TdKtkLn8mvcSgO8bWRFCBCnJ43AQry33aYGKs7KWUg3/eUrp0H +m8hey7U7tlD7nMmk9Dj2iMFv7nFOix5ISillo0soQXHWM1t2SAYSRYyichouZ7jR +ovIzBQ309elW0QQB7yQQLQ+XJ1EikMbvk7JLL+3ki5DHnerAGC0qZhfbYCoOZZ/+ +KLyQ0tsBmW6IyF2ey2NS/kMlp/5hub5DS+/SbamtpcxJnJ7Nr5VCISSSQzEtVAPI +MuJged9xjFdn0skx5Go2htScK3YatwWCbsK/lOQg5kZW2y+fObgmvLpSpdYKcE9o +jDrOIltzjsyW0Am2/mx9/90d+dehI5gKm/RqJrasmMTpmW5RIeXMutDy/HNAhNPv +lpEyQk5MFkL7x8+mtRQC2j8+p1JPzrJ0r7fJUb1muZQo866PI9Fe3L/48cruk2q4 +O7jAn2I/PFalXBGjFJVOt3MYb0GR/Qspdfqh1gCmMB4AbadW+702rfWcg6/uawog +InByisqiQi+Xrxl1XAqIOJn7SG1fOW3xGbIspRyODQuxY/+uPysZIacG7FrcYHzm +mTGm7bBoMMXdPjv1DZAkW2ZglGTWgjG0HXxfkHYoZb9ptYbeoEey6PrQR6eMSRe8 +ybn/GMG3r88pXpBK5h6hHA2+YScASRvBsEEUBL4J4OiseNY5JtjlRm2WEYCm7dSo +id+762nqI6ACttJpPIIVSFUYfDNpg0pAjEAcYkaBB1Zinxh4GS0yVIN8/4qjXbTX +PAQY+MkVoJDUoDVk1omrrZULwMs0DsSciSpczKBID950CnZSzlOISbSfEtDC9abX +P/SMOjA/DbIuD85OEKatfj4KsGnFbY6fNx6TE3eKVjdkH+K646mHzeE9vpmxrx5p +aHBcfsxn1C6w24vaLtCk2fZjIFpN9pMqYQE+BTlsGqTEzWOlqRd0rY+f5zltKtyF +Kxv5a9gnT3OgAfyEcofdRgkJvBAy0zi4A1pm6OHr7FctQShKq5NE9gnkGyy370et +X4xysoKnUb63dz5qHVbYiZOmDqnr4Xt8G/vhiUJlQTNnXPMz3juQrRKfPeJd63EZ +THahCZjcKdTCx1H7zKe4/FvEZsQda37M9sxU6IFiJY5cpt5qgSxJFh3ICwS+/ne/ +Iu14O4tQ2GbJ7mgaMYzGfCvuIgRw7Q2WpU9qTLDRwunZ63hD6p44PGnMVpJHNI5/ +/yR/yHinCR/vWA+W/hrQbu1Cqc4y7UxLLhxeefZevIflStb1fa0A9mzcFxEK7zes +vJRlE96crEI2V0nMOkRYiPEbgLEXqC805NbJjMIdVC0cC3epVKVFO+5gwzsmhjsW +ssKtEKDLvvdIYoOw0r/nXP+KKti5YmQyNvboR3A2fEUqnNmVe5OyUEDZIaWcv7e8 +PQv3RdCMTVNvluOJvG9selH/Hq529HdEbZ785AYjvsyq+tY3ymONM78uwprbnVW6 +U63pcADFtSXZSn7zWg61ziA08B7723CER2xhDSFYS+5xcmtnGTLZEHm+WHnsXKMB +4vBkyV3xLjETs6+I0wKHHcOPryjhLK+A0Pxt/TatVtWvTgoGg0JKhFwV60gsHqpt +Bv2VnchCPbxWjEm9oxXscgMtdZpd8EBc3qSxxB09Gbaf3sOczqq+MmJcT15GGvPo +16Otm32YxzzqBI0/V4HqBDztBvL1JHB0rmvB2G/9RRoSmeKms9d3pDy9+VbMXSX1 +r5/SQl9m2O9UgtZLBr5LmYJTHvkbq53bO6d8N1DDawV2ghF/MmzWG6uajMu5Rgor +8yAh1Qy/tVwtvH2HMS72NLRAs7Zts0qHzX8umxDV1Me7IW0tUA+VXalPh6GI+xfg ++FXEvK89laFrnXjbfDT47Z7fh2RcyOhRa8kcl+GvR3XeyCsaFGbIuyB5bfXMqCIa +SN9DRHk8xaoJj/Fw8fU6KEPtWXV8S6cPgk070FkIOHPM+IBOYeKgQjgvwocxCTka +dWv3n66qjLjYMGizvg3qIJ5+Wh9pYoPRdjawbX6gqwzrVxgOpJbMfZZy+hrEuE+W +RSTfsviAjKjBMvdHHPMzSwfJbuFBUzhwUL76GNQ7TQqeoBjilL/e7UpqEPXnAMIO +hIf6NqbZOo+hc0jkJc7H7kjrN8fG9hWehR/qr3AmdtT2QAB2eFy++TP5Y/8vUT3v +8CdXYU3vzRR842F9O4qEpp0QVYPJV4WLYUoj7Rln+4hcF8m3r+Cn5h+uVVC+67hq +d84x1PT+Y8klwk2EEJ0VXPTCwoAFiJ49Zf6nQ5/iojmUlT4huFlD+072Uh37fCzs +OBXGSQRVTRIeXRYCUNuWpclQF3ucc2due/MsOOgZB/jCsviZh9yztBhCjKDitH4v +/+E189WTtLhC0euW88xMHdI2sVOy99EgbklzlXkuSVfclhKD32C+VT73p/borAbz +E2G2oEsuRsN/VKRVRtUStQCPDlyrZjff4MndgdOsTONUwcTWVEQiyAVljs8xkHr4 +YoAVmlBUmCddw8YWmedfS8yAtNQ8hx7jyw5txM/6dCY3ggn3cblrA1xU0GxW9PVf +y/wGfUIE9/0M0OBtj/UvOK1R6ZLxahlctNdlR+7/KVN7S9O15NdD0ey2hYDPyrxH +BsPYzUm1AFJL8O5fhCKJWI3uVJjtPQRerrXGmVRzX52x6xaOGW/IkjetaIh91QDq +PRaz0afy/O84RtsoXEIn1VxxOInJ0wtOIOT7nbq7zE1usua9KG9wqHFb/Dlwz5pB +wpEkYN98cKg2VQcD2sc0MsBHtPkw2K9iZF5WtLbtYplElx3gGvkf7gjEJoxEyioj +i9S9uQuXy9yxTHBy+0nv6EQYcntasu+zJQ6so2bSUfRknjSdYknIt778lkycZ9B9 +n20iM1gHtSa9RNoekEsHbLzYaZx2GthK4vBLc6BMmp6L/hg3qlfeNULjUugI1QEO +M3Tp43ax6pV//6cYAwfNOVtnt9LRDtbMvRe72+GziXt516I0uhWba0M4gTcGWnEH +97pINk4TPzBX++2ukKHeFkayTdRMpiOPbjeSOJH93KwCR5hxY/ZAkBo4eOUx98lI +nlhS3MqdRzbd3eCPTXuDioQJddlkU95EPLXHxGKoJFhfFu3FSNQJWC9uRk02O9jH +cve4D5A2YfjhspJQg/v9IDiV8i9RK0oPt1x6M8z/JugROF0MRGIG2fRjS+6GM/xt +z/ILPxS7n8Q+ONg0NJmx4r1lXwAjtfTQi472EKloBzCM/U5wqLFR+ODHXniTqisM +OlEdHRSiVnX/kJPOf56LUmTS341cpWnHE0hcl5e+dtJoaz4jBnR+b2kA3OM+Quer +DFCVBxd2heZ60FyTFOp7SmnwtqMcA4n81KLjwluK2/2KHWPDDKMld5UWw8h0aaX5 +C/vmckob8m+tEUI4KvIJLvjLDlvkjVZxCTbw0Crzq+S3PA3uu74oaKOxXAOHLpSY +T/18dhYciR1FQC9tPRYRxSnxr1YBr3ZnY/II2PwcaoZc4d94fPPRWPL5x6WQp6fn +4dKL0rK/VBEQ4brinLAnYaE+OTsTFJpnzjQuaxohT6qFUoZjVEQuVWkGMrXTMI9N +Gw4jFRKK5B3+/UndWXPIc9gx8r6V8l93NippLEQ2tL5Ld+Rb83n7nSQKLxFQHaJV +Fg2Ramf6f1UUhIH98Z47a4iOjD5zfYsWiKkiQjIuLEo3VRGmgiixmfAOzfklurYQ +pA7QopglnZLJc8uQ1Q8VPP28QomPnEz522sW9irX186QJhgfEXGrif6JGI955SZw +Gzki2XZV9oNqAwB8K+Dr65Ae1weafkr1deROfiUHT7jX81s0mCOh1X3KmJaH7Vdq +qsGfj845Gq9aXJBy5I0vsZogtvafGUpF7r9QS8xS2UM/aUBZBEh2pwkD0OgEJjcH +rV1fTOLCw58ilXmj6dMxkvNqGZqyi/kMUmPtvTt8c5Z/TAdAkKfQnwMlgZoMr0zu +kOcvr70MdkDe7HiwMj3x3GPmcbRTfdu/lFwqCoo6DaXx6V6+ty6QoNALBtlEB0NL +y+1tSTuX3YMjZck/Wz4UB2XVH8iQ5iXFZH+rFGB2cKTeYMRfi7nN6dGvwQSyTTH6 +7slMZO5JQmqw0FKGOg4EqaRVd+NRQNRTTw2Oj8Pir4fuUkJMrJ/QSi7Sb7HD0jcM +Z2GMVsNZZy9MTbKACa1O0y9LF2pWKw1c0L86s6icApuLzr1CCM5PSY8TzuBLI5EB +/zPogXHR7yNeuKS5gtqbEUfOaZLXVQWX99+wmjD7dl6wqw5g8N3S+Jh5jWjyEVvE +D9AcBcu7XWtlzzSgBN1kQpi9zd3/2T8iuYA3globfEs2jkv+N0cINcpNQzspHLFV +bY2wTOk6detdQlkXR8TIh5CN1LaNkNpxrgVtq+n2MBkC3+Y53WjGeG7Shwt2gxtP +lv3mVCE6B0j8Zi8Qusd74JUl4sdwgG7IdxnOlbUh4JnmdlAXnmtj01LwVZTQCjJr +dl7JwlV9szhW7va8d9iBZwefCaZ6uJqu+Wu+6CWGam6xYy9DqnFB6ys2FKNjp8z+ +RBErmKvnAEEZc/r5/YBACuaVYGzr9ak0JtFigqI3EOXDgm6Q6kAFiT3DwILQKjB+ +XNOEDkUwv1qI1ozHH7FB2MCbKvXyBPselF57fTDfjsz1AftaUTyZ/67CrRnGks+z +GF/F9rsM5oSQUrRnHeowi2udmiW9D2B2vu3zBi/nkDRyQ517G3A55uA0Pgkqo6Vg +za/6c/4PWgn2GpMyFV5TU9kxQuZLfJrulnjBUxYlwWtdMr+cOVQ6sUJsY5GTdrj1 +qmitz5CI4xqj6+RIHPPIJo2RrxM+4hGHefEAdE/519YJuXRyvn7AwNDlbyR2023g +A5yAeHMVRIbyfSsUK+THe0judO9hHUxQJaXXpt/ROEKz4zS6kKb1DRIaeT/2BXkt +c8Z+hdCQTP+zwiihopr0U1dJYMaQwrBv7NqFjQ1snfPGDW3VFRDGfdQnTEsZVhyE +EPN5U9Kxt08C8moIxEodkxfl1I0pRZ6+SPngatBcfynJ2U9igp4Zg/rR0at/3WxJ +rZsFHAdDgEVkhOizM+4/6Vflyi2XQ7OtHTMkbc9Rb+ta7LPRtd/eSzm2r0ae6qHj +TyaTSB41QG4fpBpsfaEw1iy9B+KBNcgiU2S6tfKR+ZzaKgKOCgjCP6OChT1ZD63t +EJ08t5nPhPaBnGg6XJ0q4q4btfM+9PUOY8rYPx3a0RQm9s1VsFk1ldN2psrEiR+l +6l+W0he50lBg6Ov9CfAdOpwHJQnwbUEWqcbrULGO2TbUj25b3mghCWwyazzrHPi0 +yj8M4moWe0xJtSabkNcK/uHN+WAhblqSX06ldUij9+PxMiALfB4tvtGJe/6DJyio +E0sil9xIK/8tWcDVYIjYkFU19tlZGdDxJqo7MQjaDYOECiwX6DYRqbyKCszakypY +58i8Klxgojkwl2qkC1QL6ozvqwNHy6p5sUzScmACsk5qMD3He2SqGlsxKnWPtZOu +nLdQLvW0M0O8HrRamdjIOwgyj9ttDARrQkyLcHdWp0Rs2RsKrDYfMs+5gH8hVVlI +gkpfIWEuOdWM60nVvofgn36o16EN9iptow0tuEgTVcamTB5VZLxTAf1t+SW2TfAY +Vd5L1mbtNB2S491sN74jc8MqE7n55/lx7tXdP7KB/u6XA4FKsHm01YplT19YKE2i +//595NRPuurUdczfnnq2N0MvSOCCuOJZ1JVca1idZSEUQEc95nbAw/pioz6JP/mp +g45sO91YjcA5Hoxxrd7YYmaWdu0CdK7uPVdUkd4JATPFoV7Kbc2UGTaV1edC7GrP +d6bxGq9CO/17xu0T5UKS5HPZZ/EnvPD5l/GPA5n7scv6cfgKlMMQljooZfXMxnGV +o/PSoEFK/fhhy+85rkkPLaeP2az78T+alvfd9G4GOsPNlichIagz6aF0dP12LJuS +k5aKn+a3zqexr4Tcyv7I3QWXMh1irXfWznC7+APOdp/TTiHKtg11MT89Hti2r6rg +CviyLo9dvDvu/NhwFAT5lRT/5M9R67cMbx98Kk039bk+sStbKIWrYFxJdaVB7e0g +/b76mRqEUnsb8ixUtPzKCuQjkbnScc/tac1VN4emoVUVhJBwrUGcNv1VU7HRA9gq ++Z44uymsl957AhYc34bqrmbbAHDXmog8k5n93UlFwK83wDiweOOAxfGrzJU5h7Bl +uLRGtIc+SSNP7/xe1UijoYOSrIam/4P1RB58+0pUQtkzd5nqWXo2zEXrtn6qG8lu +r7om5uPdw92Y6W69P685KVav6U71t2NCtccSgF3NXCzRZ836YrufjoYzu+SFaYAE +SIX00EYlyn2UJuXzjOJmSQeFpDeGesFv5aaf5ecPGQlg63a+fAiJsz0uPf463K3Z +A/gA2MVuxTYhcRNYrq6221Y4uk2vDwATItHB2I/d7Rck2zGq+JnJTgs75bKNyIdx +ZKOoFddZQCwawdhoFGYPGw/1UBeCYlJd3UEXJv6/ZHL0I3rPFWSArSzYrrfoho0X +AxDgzkLgoKqIwsO+3pG4R9ntgWD18YBjnpTxrBDe1m44YsNwWvowGaX1lWvEfTPe +6wyFgyotpNFQu5iE9/n3UQ1S3niqHWgDXAYX9cAT409jK1CkwSjMh6GwnHXV+6ZP +SBoE0QMq20f66TNny3Mq7lbHjQIy2aLMdh1bF71Wi31tOtZd8ShwY7yF7WdwkbNR +rptvNdpypf6W7RYdI/bewh91pKDHQWRfF6rqDM+swkRAwXEMw3P1IF8uu4QBb1gl +hqR83c2ARzWF9DavjCMHENeDV05bA3PnkiqNFX0zJRZWlJLlc+eI4fiPTBv/ZE+D +9CaQ4h5CJzM+MlO7RvirC2q59AvJK9xH8YENv1eAe+PTJj6kwHJPKXvu4YRh6kc+ +5EPDmGGgElaAtZVda8HVVtgZF2vV2V/4LNFx5NKKG9PWLlVpHnqM1/kyBh8RT9Ww +WPkTpmln4xLraEp3dtIZJINvbxSXfo7tPRlRreTBQzZldFPC3nntD/SWEwH43SoY +QXi+8tnwyD5NQOst/RejpSW9+lxvuA4NeNmrjD+3NNn6IY3HgiMtO4jkAG+BjJO/ +0kcve+4eCjjoPID+Nkgi3MiABv6B+39tbBgWRYxYEJn8QHekr3X+Sn1y8GE1QjtX +VCrv27Wi7kcK91iiL42b1yH/U3q9DqW/vpB28DsUWUQBzrGGTBlQIwLyhxCrxjrv +dfsLom+y1ecpoxDy62iGGXNGqDylqBPDBDPYUmdcGFlXxzpLjqY7iBNSOtkdXoGl +LOXhBaBA/U7aThDUreSbrb0VFMGxFW+RNYy7IeOVdMru11xYPqJ2kTTQ49ezHM2r +B+K+2MBH5BsW1ho5TK365CS64BuAFqvoiojn0WTd954RynB+n46s+zq0niuY8UpY +NLjav5ZSmG+Evqx51lEXNVqALpU925chdx7bPBnmSSuX8d2XCeDWU7WmfUquLiZY +5IHKp3Ob2gC53V57IB/t4HOFhXyErIznwT8thhD92LFfDJDpMthmOcuCCuGbaiX0 +mC7K8Z2JexPu2dOs5fF471MPo3J6JC5zEungiQIeZ22PdJU7P/1qM7sOApQHBGVP +Q6okOaDrl86s6b85PJMLd/SMRhyRntp8ZxQ4Crrf48jx+Vm8myKRrlJdEIYIO7Zb +5udFlsnU5EX+Mb6ql7DasT2CP+zIVzQbmYajVwk6vp92ts/6mg8cElPSWmhFAFfP +OUWaSECIO7ar011Kd7ckwzT6y98Vw5Y+0V3bUJO0F076JA4AWUQdEo1t4TYfJfqn +yzlOsEkyCofnVVzSRh8DWHJzdjkAP2465/4alajYgGyUdmkKxcSIapXhKBuwcaDw +C8nCZocdvu2S8DMLXD/WeaSQWXmRO5S/so9cLarw486leQIUqacnfHcmhWUHXy0s +e6BLyFjpOuTDKG3St/gwePJ24ZL0CqeKCbV1E+i0ZCAQRm+G8N/0JpaZcb4P7ghr +Syprc0CcWUK3faCkzPm7oZEzIUtkKhWf8B7v2EAlOQqMF2tZLKSMxNYa2hmNVxYj +4hz2dw3NKjfIHBGKP/waPNlgt2RQMpznQWssL5CaoHo2B/dLgqH4KminZ1yzHkPa +XEEerrmCJpnFkA0h+olkjd6A9ZFxrcyFolp88sk95+eXH+hfjt6xdaw/AHaXtO+E +TWy6i+7AkO1EsOOEDQgPTvsL+GuKFBHcSz9TKX8jfZFlhtYdfWl2i/r+sBmbPiUo +7EqzuEMF0npkqb5BoLSMPthVz+QNYGhkfPnTKgX7e3rT9LiydzDdP94hQE9joLUp +cXND2mZulmenF3dSmBlEkjLTvxVKZXgWBxkjyJX+zgvZeg9L5rWxN7Fyqqy00JD6 +3bNgwu9A8yh5TD97Kg5QQ1Vt6/NcnKNHKYK16g6/PWGkIsAC5/AFVByhjO05YtyZ +TAOak0EMWMNQhKw8ootYfcDsDfkKQQOAW9ZcC+DGFkfrtbeTT3tidFxac3X9R4BW +KgSVJSO9BD6aYfMys906T2cQU7s/yVC3/4DZFqeq4sQWGs8Z4AsgEr4DNZLomqq6 +l512KarXXP6qrJZpbgu4Ht8+ysH+f3PfgHHz4lSYz0tsLYVa97MZ3aspn1hEHjE/ +Tk73oYtPquDuOqU+gCxluhfuQvdq0AI2uCl+RDrP/3IK33jv3mSxC6po8Gvds48/ +bSYE7bzQFKoYDx1RPZWiJK2WcmXGfSjLyP7D1sRpvlqdcm9SeUZmfrq1W7Moqwqp +6Lg3KPzr6jSQkW0hfvx1oQngzPlJtRuOeBX8HKzUTpvaySrXMVWn+kvC2hOh9XyA +Z/Pmp4mkJ4vV0FCOnMTQSnXYEbsB54LNls5FN9Ftunqmg5XlGtIokBlR5NkzA09r +nCFmCU1vYdQJAhOkMPVlqqyi+/IEsib7X5/6O2Qg9TO/I4psMZmfFYMAjGPUltXc +pmHHfdefTm0EhuTbTzQeSiENTrAa+/4G95XMz3B+BOPWg+BSWKth+5mgSLhHXHIv ++gwg/Omo0zP9saECTaELZpcoRQrA51R3zYCBCQIJKlg9Gi9DxeoOk87oUzlBaeqO +ljwYg9gcuaaaD2iyHNZIp32mHBiU6Krgx+aBKdiKrfDy8gm5LgNiLkwi7qzUyqdy +i8n03HaTLfSOOoK2Abygb70nzuQ8cHnJHWZNt12pGho1QRmOJH1ZcC0XQaCwNn0v +q6n+RO4h8QG+1HSMLYP7OGaxawED69gZktdDqdbDWtnbk/E4NVR5lB0OhWAtvCZ9 +zDEXZshScSU+6erzyukoXvVfWsKAKNTDQvngaNbkIO+r2J16R5MfyiTX3oUjzI8g +JC6byTRHwcBdJW2NzvzewKvFDnwrQzNE+DwOt43oiU13PVPLW3gAJ3xl4GiI5O1i +njVyIfP+ftzu4JMBgysK4g18M0sz3mWCxxMRQ7pqxlj5wUt4LHRG72oBjYG19xEK +mM9vgeB2oXaDxlFnBKoIJ3cdraczGyxqZajBI0SCcyTyXifdg1o6pM4FJjCSHBxT +7sgVqIIqwmvqOhOySu5Y8zswxttYxokcVOg6pegR0y+ZO2Z+/lHMFCbRjoIOtzuo +5PX2E94FrdjvCskaOZGwRnQRMosbBkrcFIxPMI3IqYTvPFEEY+VIg573vdr2Aic5 +QiONULjjFt2QFzkwOIFosxpHtoujpQqLNA2QMj1NObsfJnxVxtjdYxUhN1hBEAB/ +oTUTOXvASnjjX1zWZE10tnWrY7CQaAPlTnBdlZ60UfDaWC5317uoubV98IP7LsiO +bysdmfMylo6EUvGWKWs1uHMU6pKOWMGQGr7eKBkTd1GFRSvPcwCI/VBgNsFVKDON +5nuMYsgbvKEUw2ZU3JRlUuFkhbq3YZAKfw58zvrTrZqioV10frAE806FuoTsiKDK +8uKXUemT5nfY6ln1uGOUggdrHkFG0NMOc8LEju6dGg7lZGkb4DSDSsZ+qAejkYY8 +jnRt6FuaSceCLUq/J0ErevhmfHRD7XpUkkfH9Bt/7PrC/vJEYWXA+d5HyQBYiV92 +AREcRWxvrmzBJ6icmitCoiITq5uByRQR9Zon1hzcPUVf6yYlI9zpnYaQ89kMQpWp +AQwl9oCpeuXeX1h+2euhZdEYpxTeHEirTQSrgkO9hR+e4KGD5KirUrXWJXGcw01+ +F7RHFSk9OQtyRJJYRSN9wHa64oPfCOkr5SWu1ADPxaksYaRgw4DqBZbsv980Eyes +6wPqMmKMYfGVcW0VnMZEhg+aCN37Eai9gjR0ScKhbuhMUhgn41i3criLcBanbj8s +YIQGJaIUY7kXT3QmxdqierkW8f/STrHyfEMDVJieEWWSdeksbgg6D9WCLK0hLtVp +60YffjXUOW/UaZMcG0jWgoN251RNPRXQAmPHfEJBF52q3P7gyKez52R2jWIjtxpF +0VeyyzSnR+qwDYGroqgW0IsUZyUWwALNNVeajfbZDzA7EAXWrfYnOM8bbCnt2Er6 +EA0DboSOXPSSIOT+DPsBw7ef1+vRl7qf5CsKDEydUbX+kpAmEvksObiciTr2PlhV +VZtEwuVOpQcxS2kLUcDKixskft9THMzYxwUwp5Gg0TTQ5V+666bKXfmyMQukC9IT +MJklMKTNzuKMsp1SSqF9i+hJ82KRYnM7mps7HzDr8FbVhYWPnUUHYYESdI6m9bOt +TBbGmme/Cv0Xsz7Dek624Jyj6ATiA2r3dz8O2eSHBtnjtTzfVM5sEGm4y1b75jC6 +nGaN47Y/wq587xyXx/TO4eXWR3tFXKr0uiiYvgSyhEYTbjTO3s8WxWzV46eFYB/d ++tG4vSJ0otC47aEFqIb2EFjLg64SmAcyoZN8tDHN8DVTAhyaT/aUqp/N3ziYsQ/E +mRNfpYiSnkIpgJSnl6iIkYrtj4HczkNNvZu/ow2YHyJs/W00aYT4Ymo0l1Q0kmVj +hmIs6mJXDeCqM1EAzF2/6rvp2Et+h3yczObrS0spsGIb5bXdQJ8L1akQUx4keExs +OnYe+caH4SxaOOWKngYPUaRaGUydJ70Y8n/fNsZPpxQlr/X4U7B3rGD42RPz8POA +p/7NWH1Ipl7LAvV+VqUUrYHWh0osQOBU/rgS+M6d3YV1hlP+uYZ5NmMhVdhCTT4v +Yya3k3DXGKNwrDyBgF1xde+z3C6JkgXtKpKT9pt96mQEMRuC6hqM6IZ5DCVOZplq +u/Us0l+JYw/A6tSm8H8Vy8EaxdGwsqNz5UV/Hsj0oelhXJZFE4PGyR8kH+DEDFmr +9OJKmOtietVN+jwlG7GuedLvXjH6WOCSqPEIQJ+mAfeIHF32k5mU/L08yf0mVKcL +NES6kD1H+p4dK+KzdHPDoo/rJZWa78CwlWunn7Dhu9fpAYCjIwcLukhScmBeuQrR +aHMtc/OjgQAwjs9Q3bVfRjWvJaNJOjDzPrZEO4v0RR50onwKvN60BM5exRZpNu8W +ikNYAXsfS2cWvFqQC3CN3fblnWihYhYE8F0f5WexfttI13KRc+D6RllhYLTJI9l4 +RmrOBjF1d3+MzjHP3biUCFAR32w6NjSQq5KP07acF40YzaFD85A92nt+pTJ0RA5i +zOA+tOJbraGa9P/Soeu16riwpsx67LgX/RNt/kWlku857OK5FyuAlS62KYlxwwTW +K0WbZy4aReeoIdIty0EpAvL38wWm6PGSqj+w+J3fGNYQio8PmTljputWNRq8ho6l +PsEjqs3KQ718IY3/P+ae4rtWrBdW5NN1qVnQuZON1McXHNRbfVmLRtVyYSUxEERy +dy8ASUsTTzk97tgywQ5DZ5i8/vdaJiGZ1QnZinbQLaOd4q8dP8CGEIex2Gb+8OYk +fyXt6ef5Hsrd9LE/a1C4gyQDLcGoRlARVXNldzxCelfKeD5MZ9Ox5A5wNlbVkfi3 +rL/tS8KgW8gzLEr7xAKo4PVCn/98NeKmA/7enmlP9U5cAgTzu2w82YkGhldJKjT1 +tyeb6VyyL1TACTmMTppfiWzMKXsS7yxrXk+aHaqXzkDh1W7VnIUXsbGO+UDgUfkE +/SbEHCbPzMeE/JiojHTpgh6W03HiltnBWnjfi9PuBzpwO9pIKjzwWy3PEFbJemvt +Ritg1ludvlpE6sqAvDO6YVtSuhEtn2+vJRJzCPOHRjUhfcHu+sSUPOkBU4yPjRLd +6+7UyKAaVGfLLthO7r2xw8T0G2+/DU52YtZNzd4SFakMXGNVlyIhPA5zOuqxYGrP +FFIeche1YTgMCvFLmRjmURDgbT9dGE57FUrJnd/EQmoVoJN82i0r8zGLaPkgMbXt +gvoD3HgACf2FmOhV+05RWKxDspQCSgY98GtH0DCtRJyi51p4GbMRCilEMv/sCBHR +eyRYGrIX3Orm4yydHTeE20vCCich9ZoxQDu6ZKuWF0HN+rORbOKKgNgVRoEuRvnu +DdgTsYKLo4BMtDDHXE9J2xPDtXuro/+Jjd9/AnsJ/ZrbTVOlrdufRMPSer4o0Y0W +vwuqL7Xvm0fNBOc+BQ4aRzWajLBX5awYtF/riqkLgtNCuOiUQtipMVAQLewsmY64 +zGA5ICU1MaDUkDdRerGFX5VQP2l5kq7Z8zX3uLHlGieBXL9YOULzrEWmQf7m2zHa +p/Vp7BUhDLZrWjzC8hItRYTdaQdbQly7MzVBTvmeaKX2MmuB66q2cP4qSBmokzMG +U4ZMKU51YfWU0v+vSO9zvhIJMre2XeAPQWZPBtzK1QETVDNqvh0SAt08dLLT2YdI +Z7PbyBM6dmTMQdpb3xny72sE8c6fQ8UhFaVifwkHH28ELCYCC3DzNnlv5XdZGh2B +s72d2J5W12vZaqf3FZQJM0bZukC1fca3zJ8nU4svIr++JlNGTyqZxr6ATa5xeJ5S +fSrYYuVRo2+OZUPxm3s6tVdpcBLdQ9ydMOYNeACd4Ms5x628IDPW1DY3s/1CFgr4 +hhdTs7bGNIHAyK/1yNGvVfDQooHSH+8e80pVhg5fPmbXsmfK5S2Y5jCF9SQqPFFb +BSP/vihiws20UKgXYzEBBoGozzd3GF5qjmafkNeI/BMliHNBTSNgL87gF4rSjQbF +drM9uigPBsQxIhlDL6uPe0DKnX4yaoKfNqED20j/3qf6KLhUVO6TC5a19MtjsHfp +Y3JXXjucnYtw+78cFnvnU8QcKNxWK7OhHIxzCvULb3MRQ4F7677sznUaxFEyU8UL +HvJWJbP2pnXBZL6Pz+uHqbd5B5RESBggFMrXa9Sttvx+0IKKSsaP4UahRiBdeAsd +OmPFFSzjDzAkP13guDI2LuQJSow+k3rRGONQhGEK9yK9+tFEosTrCJmG26AAOTmK +0qwP8741XYaaZXRrmVx9sNVOBT1AHtdQP0nkxBIhmdj4rfhtLvgCSgBt1m8beHQd +6Qhlfyp0FCjRW08qtHYT7l/wT/f+HXqELEiX7I8qmJ7mV2ZekW/eqB84BTBFGLCF +kx4mJ0Vbjhc5kbGbWwy7TQNV6MQ7R8f0kce1UJ3ltLIdvbfMd6mgn8elpXlewJkk +Nj59s5pRwApEA3dV572R2u5zAG6r+G0uc1w3iISuYmPLpOUJ2FvLGOXOmmrLvIh9 +dVinZ8R9Vs2d6V+XJ0DNKANhpWIOv73kEDzQHCpHC0Dynm66dF+SqO7C78RZqnKA +wjZ1JtMKEuHOWcEFNfjkoRngQn2kVRgY/f2HN5iTGfAmoQbaG7Z0qjxwpqxBOg1+ +BbXloBg8X5SCJQC7q+u8TLfWFEyjeEvJvRr88g2OreWYqnTcMACWQ8O7KwFkykqD +Y9Dl/XC+viB2AjceAgy0GKraweQ74JOtPzbp8ibTYphvOWOvXlkwLReGRSzl0Ocu +VZw0bQ+b8di9tUoutn6wEdBP8vMvn4bFXxWP5g6HL5Vtr0NHjWNd2+/hFXJJ+XRm +7pt4T36/QK3u9qa3RyRfUHo+Xa1eMadFDgs4w9QiKNrR12ElgJ1s7m9kmWhUm+w3 +KA5E9vSb4B0iU5EBnuzgtHqjzrpM6Ii9IW3w1D0FMvKgXtsX5jriSR+7QHXJeuP/ +3bNV6ra6me5tqCbNbZzf8U6O2RXHQqq5sLFXXQ5pMo0oSmOPAenNz5iGRPNUBoMr +37kBw4taasAgE2JgYW1+gawHoQOI1pl3nO4bFvUsLtPWnLQziSN2z1zPo43xbX/5 +TRrm8THM6Wm0Vl1gzrHGgnoEDqvoQKANmVbP7A89lSFRPW543DuURkuFoNLWu5s+ +syHqT5oZaJf2fgIwxZCq6DxB8HWqlHwWLsdYOojgoBQy7vI9PKqtvgLm+zfKz0Br +Rbg7Tjfb1D9C6ecPPkrf+5UXWmNlumLHmG52o7c7vI8M7hmS0fQp9jPxrHI9TNe4 +w/b8XG1LlvHWCUEUSxCywmvy5ndiCNBWeA0IJ6JXnTTM1hr3gexfmOr3dKMJerBY +UfF5wuWaDA/RPagLfoq8EAT/Tb0xDgQhR8xql0zWDf/+suhChu+tRStBB/S+3A6k +Cbk394i2CiSDn6FmTFU41Khf+SPkdrWArHFSIfe3HG/WFwncQ08H0ga8ZbZst9LE +q7TKVLmMYI/o0EJruy+z6vkknp9NbkGhBDLWHTnssFs8pozVWoyoD4bOGVdQ2b9k +WhHF1i9e9q2sYvRZKzlJXEsVTjl/+Up9hVQwKVwDthPGs5idMpGyXS7lcC1tDj9N +2pimqHtAu5hZ7MWXPXgmmGITB7xjK0GP0BSbMwIKKgBDJrpI9lwK12HzqKGHzWGM +ShIh0+GMOsDszoUi0NmP0OFNL8hImk1GaRKXatPjFB0+7dSU6p6JcXpUOCHOcW1V +yI5UViNXRv++hRb9nGQs4kh3lnRSwVTs4KiMe0e3g3cl4LWLpl+an0M2Gka+hO6P +XdJoKZJ1mEUjX2uRJc+OWC1s9KvAjQNPpUdnuBZWe5bsfkf/fxyRzM1JxlxVz+3e +1DMajfNrAz3/4EPDKVM2gwF9TCL0CmP0xkCYrp83MbzwQzu6DRmCtag5z/nAApSK +19DRC5E/NcVh8cRQCxhxMMvUm2hCoL7KSp71ifejckQbpG0XaFSslGJvnN47HvVq +nofj0XnrBRzp7967WSSplkzrpgsneyYOY9D2BaGmNg1Uj/h8d3QR/WUx4k+Gvc6m +TKySdkCYCZ52LvFvsmZDUO892Bqqi8TKzVogwYgWHIIvTpgOp7NyCQOCDXf0QuV2 +s4+frVMOYb+N87RT3PqSvXec6R9rMFmksKUJd1UX/jVfnR6ifqUmwIyVp1Hb6/8c +zGLOyuMawHKFg1M10EpwUd4CRHkIRvEFrtWpQrjQQyIZBH58HYSiIrKefwHYCpZS +HH0as5Ex2BpOw2BWWrlPKm9IrBl1LLDrDrqJGKXZJ0UEBABXy7s9y9+dO1AVxHQH +EU35Y5r0cTFcbtw9UVwJHljs2iFkCRr/mE2j2Zw0hpFXI3T8ZaB1gua1KkJQEsMk +UM2Px4wDr9TL+CKAOO75jW/MIknB3xsCMFJ4wl/tSo36U0jn3aAmF5Me9/N8Gc63 +MAG6k/JP4YCZWksT979YpOlEIO5udEupzArkmEu5WWJJIPRYGMou9hSNx//eFLVp +0myXIgOvvUbuxycPwiAdFjhGu1F5EJBpwGlgtA8cuiL/7WGmgOLWrCKOXLD9WSZO +dDx7mSRHZYYyKtABNwzHqVN6B0dydwT3KR/EsaoR2GPOmzlWCXIhCBVx3YjxEA1S +wCT+siSMoLmfITEbSHi5Sg7ESUkK+Wk7cAciaWM2VTxmTLIyXO+WsIWoRwEdL2mZ +7VuzaHr02IPw3EhPYOhitOcKSvzQv/uT4Yit4/Q7AQeKVT1yt829FnBlPwvFB/W6 +HD/RqmTFPzxBZ5Anu4M4a+o+u/NkhU5LCE+VLffzmNL8GGS1eXyf12IJm1T62/W3 +XOX6127dnVAIIYqgEIf4M4XfPQAzMt++66W5EdQdkzI2T4wKTGm4iZP2Kp0Cbtr/ +4eKxdyAcdktYvBfgS7/70fc1lowbwCHu6R+k9UQgjidZPqdHSDbl7FIOR7ErxL8y +KEcFh+7P5GJBaegUH7n+ByK0BNYPQuZNQymZJxcVeTtqcs7ODPfePigwlShn8KJ0 +aEa/aV3CYabXEM9oCOlJQpfqeda020g+HhItAmYbM/ouCPAHBiq0GAU5rrC4fS/N +rT47gkRDoVE+6PurgBINQQJDSMi4FGLvar/Wvb37u2mb4iqUf0tIrIVsl58Qj/uj +XcCBuaHuuSeYFpcfQcIQjwGFZRfurZkbYUhNxtyM5VgMaQnaVD0W/4jVwSdwiEc8 +G+B+jGY6x9xMwEVwBo0ztuIvkLYDX9g5I6G/cobMEAAyanpZ7H1Tmp0FwqvjvPER +f6b67xTpGP4eycenzQJbHusj3HLu6GWx7cOAHlEWlj+OPeskODPDrsISZvazO/TK +yuUeI2t9DJKPz/5v6Qf0z2d9jnoUy5q1lgqa2o1sZxcpy/HOfFbIUkmo5A4QWqt0 +Q2J81LY+ZKrRz7vcwO9WWGuUA9Pg1xEPDny3PfFWsfgeK6lfIoGoehQBqvdc/7tK +AOQFl90rMlsZK4U5IV8Yo2lCKx6fTkEL3fEwKTXnfqa4ZP5n8o1lyidG7DCaDyqm +JWwWCP9Lv/AnMPnFJSOlEcFuEjfJBfXwO3TofseRSdQlpnD6yOw7J+yEQWKSucoV +1/mFTS/s+rzbtVDBcF8rk1EudFVXJw2eBvccP2E5EUFuTSmzcS/ERR46wu6YI04D +ZexQ9IUEBSqb6tCxyzYmKXfood5v+2RDsDIt90KQoXhtmiM3VPKUjRYyFy/daVrl +OjA/KiqUvvTK2o2lrapyS2BUobFqquD0onXM20gmXNTyozf7HSjf4Of3/6YdCMgK +8zoPx1qJjuxEddu7Qr429xo822nO11IUj3IdHfyLhAROfP31ATOcQlLaN1A9AdHy +QpFsNX7EDga6QNPA5AENETPD+rI/H4u86KkqSOQU8hHv7+KSJ5ltIBOJDKbH4YBd +DW35Z9d9Lhg9qbc13r/7rOit156t0XgSpb/r20fdUeC5xHcNeIJZSQ/SpfRDyJgs +mPQaIgwG64q14TUUdn3uE7vTh227l1jmG/idbiLm3ICGzavkg3OG1AZbkUA8YzDy +oVkK0TR8F+CUW/hJtpMeIFq6B3+1v3RgflydTspxyPQBOz02lUI5Z+aRn22k5fGM +HWFXFyK4FUHVMDVpBlgQ2aWAZm7dDUcPl3FSDksP88Vh0fIni27D8B0ZSwQbKBRt +Y502O4gVJxg38rTO1ArB9EGrggh1j0PHUWVZYyEAsXxtg6uslxOn1gOUx5YrDw73 +qytnzWedlLbXTRLL9brVYTeTGE3hS3zBtpFLpxt2MUzsPdFxV3plLZTAReGlDsEO +IyAA8WjJrMx7r/F/tMXqN/Q1cXm75lnN328MDXJBqRDnxUet0AGRQA5hyWm01Wfq +adIakStBmlqzO/idMwZO35p9AMexoSpWskDxIiSrnjOnkpC1RPCIDamUbIb//5zs +Gdcs8GuiiYas3pGHt/r7GYr4ZOdKVtEf18dtNa0NehyypOfyknuRR93d9dMEtyah +JY1LyXUR/RkODnDh2w1Dns6I8Dt6FFLBzWg3vNLtR9xdYYOOJjQGrmYMXR0eogd5 +h8MOALPchAaKr9GIuPWSgVMRvjVkd4+rTiktEp5MnPrQ5mGAgiDuKuUtBSoSXYj6 +LKapIdXUotfSq1ugB5tpOuEAVCYrN+oSbVOyhEH8sOLW0btFDMVb8Z2BaB2wWjHn +HHIzhJtluxrhP+IXLDgQEgVeU64iKyOieyaqJclU7VmhjZp4KWC5mnYRwzOcmwRO +ffpisHDU2xBZ+Af8ADb2Pf+HWw/doOmtdrTQ2QZqJOoWPBQkEaCvARG5IijPXLys +hra0Q7J62xQ3KHjHvOkla4EDdosQ8hSIsCD8O3N5BpPLZqs3HDeKglh0+8e24OIK +9H1BkAaPFILht84ON6lcdzWGEg3pKlZlXrGZXFJm8uSIR5nCGLbtT9ZBFESzOHRV +CAD7ZgCujlmjaMOb+5m6wp/sAtQXMKDMYk/9btdi8aq9GkWQFm8Tcw0pm1CqnlkI +n5+zrcOA6mJffNKns6/SXkLSvuXg4482TTbrEItw8QLsxFIfkTFypHGi7fAH2ndS +xi+VZOeWiY6oVm1UqOOI4+kEr4vbHYQaZGSGv+LAXqWEchGoSUQY0Cb5GH9g1o4F +F4tZVMUYN57qJcH54odhIenBU7PIIK6gpXy9VLnptpZ7yk2Mx9rrfYdzIZfJQz0Y +p8IFTegEaaILfuv0mZfghR76b4z38Ah8CH8spNENlCzB2DHHe2Q/fmPfJzfse89v +APEZgsmOpRK6/pNj1edKGm4kJGgtO+kW1Z3gysJlDvdsur04jwIStGBOir9HzoNA +HPq2ftJ/8mHQT1BR882Wfx5KE+D0cS99gRsLF+NKiBocyhNGm4TPq5qSEHMJTuoZ +1PWji5dB54aURQBdoFSAzZq4UMu3uyULGVm4czX9Ypc/QPF/dgQYO6pNKSDpAKCq +UIDmHFKJQf+xM19JR1yl0XgpF6429/XxvatcoDZF6Kuf0y46gslkzEexyF/AV2La +MElPLWVI1X9hbrEvQaFLt4nLczpMYT6r4r7gXm/q9IuIC2QgIbv2+Deol/iex8zm +VMn9+L3HphPe9vSJJKH/q6AuuPrFm3hK5AZD1MEb5vWEbxzcwgpSpgWUSd9L0q5+ +rJ/PoRXM3Cx+4/wjW5NBysgcMdHvH3jmTabJZjOgJC0pJDbYCdTV+FuRzriLPiLo +SK+UokJPpEIleWJQ+7ys6jP6eHiy91g+ih1I/It1ZlBZmQ2oPUluwhHVWGd6mMSM +K58F6reX0BNuimT4+RxqHhH+NQLxbCj+ETBmuwsZXvJJM/FZLR3OJSMYuvKiw+CM +mmUSpaqTrDh//gEqOKRdUojQa5npW10xmdv0WhXvVklISuO057bBFFA2W0k68ZRN +onF91GQNE72lqOjHkX2y04EDHAaA5cJtiKRtPUgttRAWyg5Ak4O/0GbBzrnhgNH1 +Dxuuagn26BUbBWYGdWP8f3URDHHCoZMwIyFkGL7SBk8hmUmwek8tkZ5TN/hnYL/d +7LPXnaaRL8VKZ9G9SYdCmFZgr70Pn9fzzKuR+oxICLc3RHJENnzOnVklmcihfauT +nzEie0F8pUzMXxX57aLEbowahrp+lyng+YEjTKZXO7t0o0SLIwnauS04SfE9oikV +R1wMuJHqWUK4kJbNC/HPGliFZDMtNn3k9UPkrVMI7YKC5H+71QmpYWZnpK6Yx8vc +ttnBlYi0myorMifNY7MlDQddBI9630zlXBXv8gpQffKLBIgH/UoFXY934BEi2vUj +62OdhyqoEHfrBRDM63IEPplui+Fmx4ppkogt4PQWTq3TJuFeA/AygXk58Dzpka34 +2hZQzjAjWKlPpXDpgNg0ag65fb95eZZh4bPj6O1pLSBMUm3nfXh9O4qPBejpP3iu +YCRpuw1Zfqx0cBDilL0X6nuXqlVBRBbqc7uN1VPzrGgdOKdxJ+y5ot/miBQwhclU +LcSIxYt+FEQdNBAo2C2tes8DTj+47lucdR5TQjoWqKd2scHmgnZgJcQDPMUz4VNf +nrFlt09vgEyarq8+Ys2+bwPBtxGg0KZwDzuKZqs4/p5m5vxL9axdUydqe2j5tC5K +nG1VTtPa8G5dDTd4jGvkAFBS94qbs7MHe5Sl+U/+7VMMQ4YLnqBv6xBZCA6vXBBu +9RgeRk67233dkVjpKgbO84SHH4vq7E0viu5mPXt4J3kQeOHr/9FtzjualbvIXiFs +Gi7cs4dcoTt8TB1egNJC8QBH50MnSVob+/yYQ8tgdZNkQxy96fdolGtrgWjdeVhG +uQuO+lTt8CjhCSkpzEF4YzhkDVZVUtwnvYzArsw/GEdB0/a7Wf3E9IHls8Xkvca3 +LHoVSlEceKJsiVce2kXW05Mep66x/2w2v3w4KCN73CPiYLxWDFcwSmT4Gex6EjDt +2oLHx8QlTtEIYi7yORRUsO4LXQTAVrjSMfaaebxOdKOJUoVbC7912OD65PtoRjiV +Mu3qoKJU5kiBCNfUdeiVx4LpdhyNnOWSk5uTl9p5JePp2Btl4Y65b2QvvgbfeI8r +g0UKEXPqsZusZhcxHCyFT5Y0uZV8YZA90EefA/JEACmdqlPeNMDS1KszLuAIR/ZV +Mt6ZtG0WH9ss2auBwAPKBf6t/xR9nma+ZmLP0kY03++uNomwvPtH877dzVlHTAvx +S/cFudDQG8t23C9gFhRNJ2iVe759ROQlMDub1bey7OXJNotEtYpdYpPgW8KojaYl +Dv8ayg2Vm9o4+UbhLJ89bOjPDyS31QjBgte4iV9hlbtHUm4E+KNH1lSiH93kUGQY +Zok2nG6rPRuNo1RvtB0rZmialRx+UtHxx9XaC5puUDOvxI35IVAT/EisMT1jAIpH +ShBFNI6DTNxlSiqZeDj3damW5U6SIDDphypK3+WC/BVHPU9KmvrwkSzPxmDL1ryw +bq5Fzbpr9yGLr5fv8BcCpJa+1NHcJ64ZqUNr70hZHd61qTJ8PrrGOh6sDmuE991p +nVlO/0+ImWlYqxC+arvBLdZPMxbSUNZdni9S29OrTR6EvCk+8iM3CVT+y9FpU0zZ +k0+ePG7ARx3I1cftYNDSzGbn2tMEoXszJqN540eJH6vpsRUF2iKDHrcLXn6gHAtQ +vL52ItOuhOq7IyPj9+IbQm3pud/DAxOJvWkUI3qC8Rs5LMfnRW1fRF4tQieW+r2K +hSOTyK6acUG6DUt/pcK/L6+NLjrg+86LdjgNr83RJ1ikJz3Wgu9UYFdAE6CwZIJu +9rReZmyPAKj0EH/ycPF0qZtp+VCMicme6LFl34VG7hRts1ZtnpDWqQ6aQhnAq4EG +eFz6t7p/+clQr+ADCjD5BBbhjMv+Kn4ySwdbmTWfdJb0U+zSorLZZlJF55E4simh +T3yjzjiFIMb858+wrbDYi4yKnkEeYntivYSLXqZffvik6hHBMiq7kUMme5gJFRUf +dM/s0e7gQBVR6cpLsnalO2L31TEVYKYq6WERxdBDeYk0AxrfQryqBRlCEhKgNfbR +yLtRGQU9+/X4EvvNJJ8qGloBzhPR2urWExO/DoW8aaxSWLMNJ5YiknLm7aN9vWMa +k6gKN7SFemG5IPoA+aHtL46eJJyR77UNxnipTMrccLyxV9cHdYCUPtKMArWRKvwU +0AjyvIUHgelShusC0ttYpGwPGaOTsJ+yC4hMU9gftnK3Y4QcHu7q5/Z1EN2a2fRK +w+lDHrYgvSKk5bHw3C3BEV/HRG89sThhYfIOFcCdtW3EWMZtCjoE/PZyaDHjvC56 +wZQC2MON6gvvk5In1v6TI7aoqloutrOBnEbbr07beBye38KW9MVcyuu2mdvbrsaU +btzVrE3KD5LOhOvkE6NJqahRWnXsedIxrtACYA9XdZfFeGJfz1tDFZuJfmvmC23d +0OqUsSR8TWb8jotNIU3Qm9U9XFNfnoonfOtze1HZyOKQCqWXO6WmbX4Aqz0UEcDT +LPzsb/FuKNIezJuUTt3mCitDOiQJa8wOhhcWnCDfDrXwm9DVMY0Mw8Kddg5pXhU4 +BPT0sPMa7OlEhAyKFqDaC7IM2XHFj+JGy4COMQtvKH6LQkNB6To9YF1PfZsXwqi3 +wkOlF6hopJOlDU76D4Iy8NyHqqfDY4ney6bZde60wt/KdVtaCVSnzXRFsToTKepe +UZ5BOLlz5aIsuJM8lI1+gGZkRBGRj+3IRXfGeIfQ6C8XyEs5jqV9BFNl9z7wOGXN +J5C+Zq+cNzhwHp7m63Yq2ytN5JunI13LuOdrG0l7EVW3a0TwcLXE3+Fq2AU9NmvY +DZbbMIziZ+wz+pMC/v4BwqShe4kYvosEzSOpDfbf1sLvbviBXe1OqHG6ZOwCANst +YHUsQlURFFd8HIy/rWBiM4mv895pQ93VUUWnYf9VMw09cDaLQ5V+6enp7aGrAHLI +jVYii7Mwsqwi8ofioW2jj9HuANh/dv6bvZA6rAbbgiHViiXIBrqAZ0Qx7tstOGW0 +W07DC9AoFqGKXM6wWBH2/roHH9KixHhlULTR1lRAUPun3FtKcorjJT2otrcS0P9/ +VRbZJ1KZR/z2869RbWX51vW116ZDYAg7DAnzDiSdAQF+dDpI9yXQ1Qz5PxyeGrYA +S9UGd5AZQ4Z2eLulLgj0Lp5LUR7N7YBu5tS2J+nePJk/32teGdowxaFb+ycjwllP +S4NeP8XYATQygxogte9l9iV+sHeeH3kbwY3hiXgaboNB/K7pnPh4f6kKA5TMeZ6b +67WGnA00Pc9t5JrFJfpj8sWfrlJbrR3pWoJu0H9MRbnYwRHMTXVHtOeAmBCkbuuF +0EJ3m3k25ruS4UEArp6HU7Fpm7yukhg9mDEqJ2s4nHX9W4WYrKG47Lq+8JmRuVai +Smlsdz3enuMlq4bwoJrvV+UQM7aVY3jzI7aK+2RxxWHERGmBJM1rMp0d9RPvWHwe +bZ87hzpQOfyzf+BrDn+MTvbwDsCFwibCjIuGpryTtWdXSkpXnd/BTCnDcsGZWuy6 +V7jHvPmjK4Cki2hIHBZT5fENzpAlhS1hxulpYnLj97rBoP8l1Iqs3mYw0JGAicRq +mnjv2FriCnEgxIphpXe38AT3U0Xx2zolDkjN2uQaF3UfzcWEalaApxicMKebXRNl +Q/tDa2LKWdiB9H6YqFEhhteej3ZzJqYFmkNtDL/BfHTT4k0ll6IveC/Y4jlT/lYl +AMKi1/w24+lPXWPW8j8m/mGhXfUtZN+XZOPzlCfDifMqQM8b9cFaCZo5/DYpCE3e +3soAtTlPeG4mIcsQZrUm6vp5Rk6Gyn/u1R+LR+5MiqB5SSiLcY4QSw0aGq3iP8S9 +CuAprbxsjMIFjfnhE2hYMIvkAzTHi/nEtmTswWeeuY1eCCoP+OZvGHdY3GywGGG+ +Rf6TTmFbvQjHAPJSk4MgjXVJ+9Fmij7kJa+hsXLq19fEHPdN3oD3FA3wBLi/1Ln5 +5707OW57H8FZ1lK8aKMFT9cfSEng2VAM6AAk+pKmWq5leACWh4CwPuy5VNOCQL5q +Q3Q7J2cEz0vSHrG/yZIcvH7Qfz+4TKrlCnLKD4OxWL+PYSFo9wu7aOw+JslVBMa3 +PSFZ32YRTUHc640KvDvn67g0sURA3UDeiRuM0UsICxitd9pfAsPJFavbeNtsG+5k +4CAEnJ4v40ZlAiriuDVCPc8jeaf30kYdwBtV1wFYqDWMKrYLM7d51PiVVGYyQxKf +adE/MwOIOJWjL2IG3tyY++jwUiElLAN/WW6dIiO6PtmbGHOTtKPicSVXsZ9nyfR0 +8eCLySc2N7Orzptd36YTP6Nwq/RvxsZCQXU9gjSYyVjD/2vu2i6rTHa7fD75+i4M +eDH4k5csQ7Sfd53ryouiHeBdHtEHbavD/ZMjm7h7ocgvgoSwISnORf7rYFsLDvbm +1+XoKYMGDZTFKfyOAyA2fzrj4fLkzvW/jTysYm69Yog6qPanGotfX681Ww7VTVI1 +I2BvdqiURa1qMAQ6/5iWDCx0VpvS3hCfzBs1VpisJxGHSt6XO1Rki4koq5pcsHEG +kQ/y2N0b5gTnjnN0D4CKJ+npX0uXpjs7apDBHNwsEZtKDSeSYWdqCGxOsZoHnCsA +lvoj/EoD6U86hh5mDfSMtiin6mBoIT0vg9omsSsyBXkl9hIB4SvnaUNZlS8gqQvn +ONaSw+V7j9UqnWI+DbTt4SRQT8kuiY60ZiRFzHtym6WchYkDUTM0aYVkxl2SKyeC +2PsBADMjYNbYl7GUEOe+pjNMSwWBIqErLl95ZTzEwjMxsg8pHeanSAo0B657CLjq +yxFe4kmSFzaZ34ebaXMm4F+2Eimxt5AOgaCbxyjG8NkfaLSZCK6tWamNzI2Nt7d3 +7OT7D03KQ5c3fKtQGQk11s7HOHEScZVZuoCNKKrChR/hl2xJFWoBCXRhTR2xXmQo +DwXbkUz5KR6fzRYCgzH0f6qKM8BwA7/N9hEK9+XxtyrUGrxLctPQv6iCHFByAdTL +hsGNcUBZZD157uCiBj73k9eQEgR3mCWRMZSTWU44q8om/r62TDJ1GjXmEuf5ybRW +TPjv5FZp5ZFnx9A7wSE9aifYg4GGhE0FI6TynyK0TCjHwTWW26mVYPwg/klsYe9t +rh3+Py4XU8uN5ACD9daSTNNTbBN8AriRUPrbTxhgGXWmUqGeoJ0Pebtj0tin5WGT +NvU4jpjJrigtxHWKZzPK7sKJK7BMtS1bokM+Rt1Z08pEK5M8pZjvOPTxlQq4L00Y +RTVl4OvlmNdcX4pwch3EQ626VfyAMjwNscxT9CoRcRTV+eAfuL7tK59dakITuYMf +RYV7NbHgFr7WlpRoM1aT0/0b5jR7pM6p/QBaEHDB59gFsN0jIA1Q6nj3DngrNZaE +Q1C5vrBxDpPpTs6BUg23PROT0fBkbvAAKt/lk9ES06hSZWezMudAA2YaYt22qVV5 +yqbyBhSgyLii5qCjnvG8Q+o0TiBZ/oTtX1gI1FDljM4skbKzBzL2DyhbMuBbx7j5 +GTjEmPQUeI7g6mQPPdvvC8kKWISsX0nGFdmr+5BUuA4891rFMo0m+T63YJQHmUUh +0hxYg4WQYxjXszRkranOYQgy7A1o8Xg8M7EBsyyeom+nc/lPE6eaR+R393OWKWDL +OdHUkrJGAgdpolFecAuHndW/rXGIfCWdvoBU4npwjz9N+2heuVY251erNjikzJG5 +zXIybYLOIjmhxtsDW+U6JekhFbMPrnZfQcA/JOw8A/EZChThnaX98R8Jg9Vqpx1g +S/5g6F3rB+OWIv7FzgxNwJ0W2EvQ2VBZVvkwLk9Upxyn47YJ0rk6mxuBTCqkhVXJ +Jhg9sXVWcke0+TvYQcT7lIQAJBmxGNUn8lqLDgduTynISiBzXMqTbN2epEDjzVLF +tyxx+rYBN5N9KAjqiT9l8IIpL2Lo59gedgU64KWJdpaeLg55OyetzlhDbWGBFk15 +EdRd++SoLD0UuHb9dYH8lORbxg84Rwn9gdFHstRSNT5ywic7y7iQHrL6dBSYwKDr +Mjf9PnhTbUcDKd/tF1fsLe5ZU1jtIDBfCgG2gQLdopeM0Euujp45ZyoHB9KdvE5n +Ow//d2VIg5YMyJFAFN7dKVKrDO/2xWcXBQCSFPjxJe3vQ+y34f1Jvz/q2gj/od45 +s3k7cV3GmXt4Rbzeqch0VAtLSkZ0e9NggDb9d/KQHlmtN1Nx1YKdvC4Bvoqo3h1c +DzgtLhMyC5vemhGnTAvGcxA46tFjSZBC0umJrnagPxuLNtUPqSFs4MX2HsdyHtDc +kLege0aPHf1BZXGvfilNaeLPWJx0/JPI5mvDB9Y/abY0EtPKs22LAoXuTawmPbky +O5XZtetolliZPNsx+8IqbjNvgn2oDJJ9qBBQ033fFok0POAxVC8MaUxej64fxFYd +i8zXmNJmpK5npBtPxkM37QlJD9AEtGGscFRfsQsm3VmdcE7VTANoWWM8QnewC3iz +44jZHf0t+bPsuieN6p/NL3hbeRKZ7XrQ0ajHBHWv76dpL5dxNsEZ57UY/9eTooeN +/E/uTGOFhhVm//SMXgscCHxtjf4fsF46I3M9RRXhYeNSZY5OxSgwqYdsv5rdYoP8 +ebu0Z4TJr3LsNVVZqdbpB83BmwwVXi2kUr20qB/1/IfxQDF6+JABN635e7jj2adj +6Vk1XnjYXBDUTQfqtpf8GUU7P8NqpYnG9Gk+U61Vq5JJKdZEZVV5d0DVaG1/sG3X +erSwQkkjuHto1L1Q7uvUhxYWsfvmx1CQ9q9nae+IfD/VYK9/nbcEOTgNWc2g33+c +Ej7UlOs23qisK+wPKiSY25zvt0+733YppBXmgjuQCuUgDL0Q4hK//+842xZY56bQ +OFHtOzU5xkwx+c2squqNs3HB2EXJDeJIPUjuqzJCM58cOv5GtHvhKafa7l/5wOCM +eJ86vu9bD4EvHiI7aWHw3Luwp5MCJaBtdAHdF3WOH3l6KSCfo7lU79yijNF+7nqo +ro9oN6zkWAulQ+UkAa52vjL1CtQsKa3kZ6aNOuFq2M4U3lWl/kGu+cwwrxEMLsFt +HviNcooX9Bd8GgMUIiUl0Mqae8pT60q+KHQI9DbC6Xcnk/1r0PBnn1hPtufA4Hi0 +tZpw+fgN9JxFe8O2OOnSImm0I5sq26j2OYWfdWT7o2mWi0HAce1YowCC/P4dyclW +zK7W54cLmNCrjpFc8VZIjxSVXxNEKcpVNrAAeUeP+w0kRvmn16YALcJRe+pVNfGL +M4nv7RSgrtnbCsb+mK51Vg4hW1PpkX3uvoLlJUHmBtlGRyPXiECppRnlEbuRWGxd +VYUcG81iAnZifnIMzJXrvQDvRgN1zIRC2KlzRKgBPX7nYL7i0nPevYkcGaiB4D/8 +ANdb59kTCT7BUlaYxJkm845k0CqhTjLAT+Hs8Uy6O6AghDHYNyFm7lWNB/a7NmGy +tLEV+K09H2lH98Jxn81xiDp9rx7JTzzOnTwJQamyipJZdHiHf3OaAoizt0gZITUf +5UUCJAR+RIAWx7dOkE9yPwA4PZ7W7pXGeslP2szGTnDk3FBRuzKewVWdpHkNS3s8 +sF/+OEs73dTsnmi7auLk6WgK0uJdMrZS1IL99Y5TsT8lk4VhEgtTXaXPDPDrHUGf +ifswzJeCdfoUUMbXLHpoNuzXyOStdKmUhfkcdpjGvc7KScNN2rGZw/j/G3fa7vel +CATHj0lO1FKSpRfaHzBD9bqUn9Sp4lRJ6YlWF6KPXGqkFj1r/J7GB2FI5ctLZUbR +rXeRh5kWZZvLshsZt/GMFJPr/TZASvLajBM1T9surQULTAjkwyyFRntkWl7WoAAK +GhQJq+MbmEggpqPyFRVZGausniYY3u5kyiZa15jj8Ga4tTXP77Yqakv0ePdLgxbx +XRnrl3FMzU4d+qJB+oRFg0+DF3S8f7IdWg0djTNDoxVmGDt9Aiowr2woFpld5J+R +HYjYXnqFZY5AA/vdREW1Iq0YjoiHBEgz2vtHcUs8zL3xYH159CR5QDyKcLCohV04 +9APC0U2rWLLIjsR0NNbrrC2BTXtsOGmo3l7FlUmOzpQBbMVUQPbC8OITpeprtKqe ++vgELZ5krH2cyOY4qwjo4XnMBBZX4seiJHxmaieMSS87PYyMAtsQXWpZINnEZfgo +b3X/qL/G4yo2dexZXd2WU040Mo1woKBGyIz02+MT63ehFQOiRtmz12BTkvNqmZpT +XuSVTTKTt11NSlUTsfthNzPLNGddTq2Z14z9OCCzIstrkJKWISPAKhdvNEG+tEB3 +IkUFc1cgoATGsra5aYYi28U+F2Bdz+OiyID/nRGZMOpBpBjPrHrqU45U6oSXTtEe +3L2AoC4MPuh9D1+ElFrWE0SRZG2HZr5XdGZqG1YPwZnYnCMWQYUJjxlBfk37dZgt +r5ExI1pGNSH9//Y/MGfi0YdGasyURchybzAFBqBPQncYoJJd59EuuFvDKe61vqnz +UwmT6hBjVltw3wo5ZO/zy2s7IrMTq0ZNJYlNgN8B8ZA1j7HuSq4/bthQuhm8gEZS +cEBEpVMB8POKzvB68i4w1+1P2TLDbdJsTG3HWvqKBmmgGhmAHGLDymLKh8UTu5ke +X3aA+skwxfifnzgVnv+xKdc9DEWimIE1fNU4LVR/4iiMSYDpQeQEEaHY/JbPxt9o +5ACEZkytoNFw9QqC2NrKI3kQ2q/kz2JsVFR/sPuBBCN5+JI6121bUy1O95B1JWjr +dbt6UQMAbXHqycQ86oOXPaqUJzqPRAcEGaK68OlhfxqUo1bgtLoiPkHNxAPQqKLi +W2Olki0g7Z9zVzaR5/cublzSgvh7JWA622Fj6WP5h9hj31H2rp+mkLwBBxDIWW6V +AUnm+fOWA/rYPabXn7kvoEj3h+tt4f6whrN3b+rLNBAgZN+YX+cGTJPTbfEo5RWv +DQvhAYU1uIOTF5KDtDjR/jOrRqV+eXmsgkhq5E4J93wKRY2XuMjSZPbLB0GeycY3 +bLh66SPgSabSAkWmBAGAZN1F7dY4MO9dw1pD0S6p9gGzYeoUpExc9r7mMDan26qm +LbNSMaUY0hoSQ961AiGdxsFbVyiBmdOBLBgcPnv6XknWUz0fKOs9wILctT0BX2k/ +kZf/9Rf1daeB/KsyaCiPYOPkX02a61xXAshEi42jlyaSAsul/47oYYso7HVVoqmw +mKmOBdbMjiJk40oj6GzQWrfPsnssygo9rIEMMRP2452xqWYBfEpaxxNlswnT/K/a +EUEnCk3Jhrifsq+nNy+5QfgAA8SY4uCoKAs29r71o4fEdsbemsnHMFcPvxx4SW7y +uTRODq+RN6LasiF4kuEaoVY3dpY2GZ66nLzfw4Qwil40dyiTymb//VVEVGmk05xo +Uk8NgeWE79/gaC/o8Qa/qu1KcTuCpe1hQoLWt2ynxTNqFr877AF8+r0teqM6dQKU +sMnZJyhRDWAK8UodSoddJO5EXv/lVPyA488s0BhIYieS/RsRjTg2PDCM3kFpWRiY +6Sgu3ZFqj8duLmBMTqJzlToqEpG7fEWwM7Fny6qnum/kpbgTTO/chlDhxrPC2zlm +JTIkg9TGQu9O0qUTDRoUnPzaeJDdeqDaoZyZBAw4k2BRxbFUaZo3tA7UQhfNuo2b +f3cV5sXXuzNfnp0ze9jMkbd/QlqcBoNB7hzLkHwhfYHIftcRCkBpb9QKJpZhEEdl +QT3oZFQTdOjruzXBgyP67mEfeyuQUgFkSn0w8KrtG9NRL6MbTGZPeNQQHQ+4jfCV +5+t9kr6D2ghD35b31kEGYayjMyb79CwVAlWly2D/RkLydSbvGuJ7/S2tUe+wbAA8 +48ZzwvsoEYAShvffELPQyQWUrej1Fbv9bApqnYdWhOwixsolF7sOQoW1SO/EzBdt +dbXRDBkjVAm5GvXvON5lPWYvSkdmaYfIPAQXRfuarloErf7TIklFTVEmKJovkiOg +mxBvBVgrAJZMATPlMz1Xdvf5CwIfPFm/PboaWS1Q7/mzlUSjBSIdPJQVZQ7S2BQw +qLGw9gKVLlwEiokuNvSL6AXYDlxd6nCSyOM+nb1QHyfmt7dMrFWor67PDTC0lwjU +9zcMAWrVQOFDeKWV3aa5LOzOvZBWml74NUoj3NLyWEarA0phv3WMltXyYBjNGB3f +TB1SgPqc6sfTPeiI9a1B4cve2J8zRA3KPoKO3KaXIrwOmDpgsC+2TJ2eEpmL032d +Yg6UJzltMqJ51MjVLlXXbr75yiwtL5CZ4o9OPMRCOdB4JERkq6rNpCcNHg6Qrmae +WxLl6ObOV53td0Axcqu7/1d/ywnObMzZwQueTEcDK+IoWkvyCFspoGQGJSTdrCln +9U/fwZ1Aw573Y8yV23mCoVz+46CizX1R0tt8RsiUUuJRedZuXpdgmloXHSwHqVir +4TeoeKbJ5TabI9wAUk5DudmB5BBA5WQUXbk863Vmp6ZrYuTLfrMjZIX9wugW7G99 +XjupmycimgGdDcwkPXsuhcn+y+kypAeSBT8BmORPoMB3GBQcBFCpksISgnzfj9Df +f88VaFEwPw6WYPsr5zD3qmYV2Wcsa1+AXMyVWEud3OibijB/ydovxfhoylxzubgq +c5dWawXZrm5RAj6OLUtonq8ExeCxZUVesAT41fPbsmxPMODfaNW5FbLVC3kqoKSR +/vBOG3e/0w29HIfCe3INg/hQVqRtqNawZuPB3U4eg6mkDZO0y9woSZUx+4YHiEnU +NTXJ5dCxVSwAc1bY/Ip6OLqp0SL7pbJLVLOZcdpgE5tqhkRt2TK3t44YBFUW+niA ++7vUO6hk9FiP9bQI/e7mVqrPotPqBtZ/BYUCVLnHL1JkdNsfhSH93PbRBOL30thr +a/CDhbsHwqYjqkrPHUZbNL6xs3s1Ebn/iXs+MoUC0UijkUhThusSGW3zplPE0G54 +0jWIUjvdB/4anXrEkP0+JFchB+2p29bDA6M6GqPIVL5rQWDi/hZj7Jo0GIXXkCmh +pvHuQ5Figaz8huMCbW3V2iIeCWQtEZCIlkqcyGu/srkMp8Qy6LofUqNL4sudqhPx +f4uyi9jp8NVnv5ItQ16FzQScH1btWx693lWnmb0+Z2LTNY3edWuP30Cn2zr10hQO +93mjE8j8xiqRmhLimsfa03ja3y1M5RFuYdaN/LBTd4fTOYAzlN0jlO+qU0fuEZpk +uQWrVWtrciib0QKfC1g20lTslFmwF9dosu8yjarIqZXr+RJVRJ+dXzaC9RXCMNZb +65UcvJNvzjdQOIPUdQcFIuSQwWUnMe5P8kikQsxEZuT+BErj9Pt17T+HPstvcsd4 +mLxzNtdOSZuENCu1k9eImFqEVVl2odtXcLBE6f8fS1rDtjNUupb+m5h+WR63QHid +eDln4z8ShnayiKhW6xp0jj2dUvWnOyhQwZWRP8m/EmfeFO7gYiIw1SxDD/ZqH364 +PzVEZruTbQ4jUKjpfHxf9WBgIVrEYTPTBjPjxaZbhfA= +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +gQ+VauIuH+g40FNOpVzoPSXPaSSXzZWh6rE+e4zt/Higof5lTVqndEO2y+vyS/HT +Uz3/xsHmLa5/hfJOzrQ2WAbWJcFOc0pzmbDqYnUgEw1W4IUS1qcjifpXTLdxvwfy +rSWd00QRecQN7v+pyLFb6xf5TELzzsB2PAr6/xlRVs03sGcC8jpFMP1gppLRrh+C +xnDjMIBVdGmu01tJ1gcEY/913addbws7HLgMcMDLft0U/4zTbjE/rrDoC7+eO+3k +z9ZPUNkRvEPxurfsVZfIuglJuZJSqyaB+Khmc5Q1nMDb9IswcttQUM3RtjEksR13 +Y4OcKLh/ejWsVorB6JLJeA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1312 ) +`pragma protect data_block +fo0JdXfIQsWgrENhFGo0RRW9s/IV4eGBK5upzSxFjRkxTj+wCit1QKkd15jJgDu4 +P06Rnw+P2/Cu/tkXRjH7RGfSCa1EZ08cwLiSykEmyb+qQo8wTkOBh8KIag5m0P1t +XTuNeK4lZP50EUwL/4wSSMPuRtdpIAF+0PAXjdoge2gwhduxtVQZpgPO12dwk0Wo +Qyfuxrm/7iyjiETt18QCBk/PXC9JLX6a9hmtr8ujb+7IKQJFj1S7F9WxCZ1yamDs +e1D+l34aYZ5r3sBbAysWrg65oN3fAAd6bhptfeU2+BDBA8oKIcTClBK2f3pBUPul +8YV5xUU0+FGat/Rjkm2ZmKKpm9JD+w7ufesbJ2fqRCCex08yynx+EuV6lNupQQk3 +UbxIK2+04eVmLtY7V87103cxyVnLFXqAQY3XaG0AWBpO2Ew1NwH6CU4yFpyUAC84 +Bjztc1mHKONeueopzONq61tRDqarI0ex6IhDy04D9/zAOhMyBrEHzeR0UozXtK6Y +TB/qqFBgJmagIMQWcL03s2FYWQgGUU3PRQ4JiB57ubJG6H64M9UJUMXI7VXW245F +S0oLuBSWchTwY4/6zvioNieoCZgdkxOTUqHNuV4Zf7Epcgh3IQIZRzjBSpah3skn +kQwLdkHYbh3EzBAN0L4lF8u4LE/8SqwLPpsl91D8Qck2jzgNTYnbsG+t2tsum6n8 +wYvw9H2G6SCXAimDrg2Qy66lpdDA8XQf+1Pu8sYKlEd3GH9lQyGX+l4gx3OLuOtR +fAlYbOhHnFRDXMNE9ZG/I8VKDFToJD1/SjoKUnrz4TdMcQZn3Asrj6LyXsw5CHgd +zhf60BREHK5nXIJRGkqTlV0OyCbaEe0yTgmpWapYbnUcpX4UNu07ijUdSbUBReil +f2PULQwchd1Nh+nj49FyRm0SU4twHeYIMoSC2sMtPiJkuqAZPugzpBpKZUPnKzDd +VmHxPV5Fl4haVbGLfQj4rfl6Mqpqk2DLOiPmwiXnf7CTAjpnwNQ07KsBw6SKxLAe +YS+1RZFe1JQTA73Dv+hAjOEby2uC1tz9V61abAakI4omdhXK1WBGS7AW7VIkOhsa +U2d43C1vqygKdJzTQVB3SVqswMzruIiClRGEypfl8F1L7BIegRA7y6KJYY2lQ69u +7eDX8XmDYmXDiWgXqtWRALbhHrDi8EwOCp5Tts6KK1q+HZNB6UjiGUrGZ2/EhU4H +rNhfbS8YD9wTQtEs/QCi40wIeLIYjIf429BBIRU8k3na6ZwzGLdfxJnqsRLJ6E7X +aCiJk8iag4Wfv0HsAb9J8vDUKzzLHS5OYlHmEss6CTswBAYs7u8/UF9rlfvXy8Mb +z5tfh7xCXqOQpY1gF85w0agvdFKLhhUzfB2Y/XiH+P9zw8608Q4B2irkUuj0fbhU +/VGCOg52ghhNNkaio6JDtzCj/4nMf3QJwdYnJNTiSWLmN/D4rgU8FE7RObm2foEA +5qemSiCt9nYnRGtaRQ0jFh1zieourorN3TI49Lfh/b++M/Hq8OUZh7Uxs5ni4scB +RqEGxATE+29gCCCJ1S3HVi7fcit9xh2mupZnT+m3qHM+Jt01sv59AUJ/UFx/cNYz +qo1oB/NkzOstxVDMlcp8bOO+elF1X4n4wKeC0g/eMM8C+ffQiVT7Rqh2mYLgXQA7 +BhBS+E0RB6UhkxYPnRFEgtk0VLL54VPEVDTINYlLs+L3ZsWwYJs39Gen6vvvepYy +bujDTnnouQqtvD9ok3pkbA== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +TpRHXtmr81JyoWaAtQOsoLu44jF5UvFDPdO5/CllOd3kdY7PwU2fkKx7bS6RlGe6 +282Wvc58pPBGh6uImNRfZkaAKTaspN+giuR1GHAo4nfIKi92dgY2DTW5JbEU67ml +1IGNiK4su606fm7n90PZ69MZadoZPNpUxZxzYbSs+I39eZWsgU+rtoUE2d35qjdW +UyorSD+O2F5Wv51CWlcWJyscNK886BFGFi72CtEY8IdYcolZ7hcONOhQT5jbhGWK +UFFTqjnMO6iVrEodujVvUgcUtFQSTl5/oHSkmacP7CSADA82+06uIHf+rByqHGTp +JNgtSAVN844IRP39n4T5EA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1200 ) +`pragma protect data_block +dW2N/rFxim9wkWiMqoV2KfFOb7ryaosiEjsKQ5d9XAY99bfh9dHXfxBwbIc/m/4e +C1jjMt+51lGF8ncrYuentPA6MwNEfk27Jwvqv9/Trdq+kOdiWuYmhbZxfJC2L3WJ +BzjhoC/o2ZNSFpgmDKLxln0/pf6iM8sUIldzujq1RDEv/fZvcQ9IXZ0c0cgbXEWf +SfOaD5E2qBGsljqkzqzIKjaiTPnGPsKJ6cZ41jLGbcm+AcbSk6th9Vdeim0hCA9t +HjX+E+Tq77j/ivdd5OuzAehdPAg3IiMJTQxdTNsI3km5GzvomnmxK+pG8L9aCaAh +o+hCsSXZD2QyVCRFZjVT4s0ltvRto5PgSDzzqm1N69eUDE/spFnroMx1TQCLbjBT +zS0w4mCeLkzFlxc0DJduqQlnRMlA8AnBFujD/Q2OAdVMSHQC7YscXbPzF31GPlqx +Eg2t/VyotaMLOGG0wG7ax43UokgdGbSuphzh14sCh3ZSbPueJQLw2MQwK5M2gcvg +/OCrpP6ZQDt10hFz8i/uLrgNIWA93ZzqujdUnYXBBCwUzRJEyHSLnlXX6Ko3rzE5 +ct8FuQPGV8vF+t6COL2nQ0qaq+23R5E5PuFtEMyRrDT+p8iXZasw8RECO0NyVnEE +YuX0T1i6imJS88oOkLq+ywGLgMFC+4O26DIlpPh4+UJ/fnt/pVOADhugk3UeF+QA +ZDR1sgxihCZe9rP7QzVpjm2tDiaPt+fklsKWPprWH2eAiuNaia9mSSHNYGF2x2lD +9h3FKeV/2LSUG5mOvvl3sgKhV2fY0MuldurIH+utuZSPbknY3sebf3BKCntClVOm +6zvNgcnFtvD2+A79A8sltui4gm5GYPS2b0YDfju51vT0iTsCH30p3LWNEG/zEtf2 +48bHsr15Z/CgHdw169NsY8B3V8RHxaJP+T6zbPLBjVmRFbuTftozxf/dv+m7Rgl2 +3kmwmDxauFLyklSGjQ352H678ASYS37eMG1wvn3akQjYEAsrQTdi1sxmk6SACmSb +Ko7v8gOZpn886AO3O4V3iIggxtfGIfRMtOXcoEIX6dRl5GdFkcASHigHwoV56yRO +tlfJEHrrKLKbmqhjLMjDz5jTptQZfwCjZGzki/PYImxPv0ay8+PTa/qXEaJEMsWZ +vWEGZGSO9zphfmPXEJI+qF22X0dYlKGn/U8rzBEsdcxIXyGWQwBJvbo+GhnPURiQ +i1MJHwfOEDztC3XemmsQeaMuSDWZFrnOKXuYkOBj7tD8ir7vJOor8isvwQUz9LGK +g5Vx+0HdaBgE32QEZ/NjYA1V6bM0iUHz9e9qzEVqN/kRww8HFXA6SnpD5lz6hyxy +jFVRtphwYQWmSzwLvFWa2AYQuI4xjU7tJKOCZRqxjD4hiIkjDK6/K/01Gk5QL/3K +12xoSmqSIZRHwxFGBoHiuBmy+wBhSdqqIOdJ/OsoBT+1OwzQ24l0CRjfAk+zBdVi +7A89GoA5JGSeX8OCJopZvuJ/kEWBUL+l+AU3S9Z4l0uVYybFXE7WXuTNCWRjCQFQ +DmofPA/+XPmyr1MT/3DpFQgnMN00C/jJ1eRmmSntrjCcYaPS0vX117igGa1YWfcD +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +TBCX5/gAT5S6xdVBuY05hYDsXmHLnm/0Yl4d4ayUlKrDe3IUWB3JcRtZJEwtIwhQ +wqO6qIYs21XvVt74eCxdt1SZXHRXXJiT196fD9q5vFrJxAQqeTDvH51bmshhKW+i +DwXpMTwZlLgBsT2BEP5C0RiiICy9chJTycHB7vHEh6lTXT6S/2H7bweTMlFCh6s6 +n5aHgBbfjk9BYIUSTuEvOxw9Yki0T44zjqGmjZ3qxkhk5Rae8iPLqCnjRTjNfqOE +zQtaoVQW+8NbATVUmZC4WlgxF/J03hq0TLeqLYfcuWR0uH9vLAWsUzHqlGMZvUSV +23zwmB8p0BqUeaj1cllyzw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1984 ) +`pragma protect data_block +2OvJlNYOCu/okutbEvWbuQI4X9C4wmVA84hW5XRuqc+R7lDXEYZ89g58fT3Wyd8M +ecpTY/f/5J++NaepFO9rZ71cRzxgXD7ZQypxrBwT8eXz6kwhomKLL8xgQuGMrD2h +002LEC5h770bZFbr2QDl94Kd8oWweGDIcwbbPgGtsgfsrwnZq107rvdgRLsvDJ6H +A9T68XpAsV83OJOA8hk5S1ytXOtMoD1vxUA9NgZ2d9BBiwxnfNC6r2DYa/TpgT+F +8Dlnu2u3Ch2T50E1FvIsU2NsOkKdsN8k6Nmhr7J+mWrK8q1RSElNbQt02yIshAzD +fz1m7maxuzNvKiofs7xTJYH5Zl3jsRgP4i3jUPcFIYQTdju0XGFuzz4tT0y3o98B +wJPQRdZzLdAIRwwOeqCGe94DNj6v4B0lCOW+L2I2xO/Zd85RIWk0KQ11TMBxIioX +lElgvMwoYdOobLmpseg4vchu9jvsSwd1ET14HpSefqoM8cHFSvGA3j0KpwHUHD6N +cAg2z8pkpvWyZBxPOnKrjjHml3gwE3q+X2mtD1ayi41L4xn6E8czI/znMUiRwwcz +u/UG8I65XcONtBswjX1cTAad9X9cP37rq7ly/mnCVaQ1fwdx50rBY6tOiF0jiVR5 +JjSBl4FkBYJu7kHqA7DcluE9ATZ1+D+BIfESxs4o+MIGiPbk2VMeafwTD7GkJFOt +pp85p5WDA/qQLIA+aQsaHfBRLInMjsajsBU1Nnr1Z2FuT4dNgRDU1JiEJoiGBh4S +RZzlhgVKqLQdDiC5KHU60BMuW3u1CxkP6BLofYO1/DTsIOzKRlb9s3+Bx2RBLO+X +LpI1kmPdmyjjLOe9xPxUuWAlk4Ona2bF7SOrCRKslzRwj5WK3kdfynnrqi6fyg/g +6RtRb5T19kv8xkX8Q0Nu2f6aIj9NFg8R8LJhXh6X45cptFvZzqgrDrKouB2qeqzv +r/ARvwCCrLhqU1Rwol3o14E8rmlZcjNTDxMVbtGHIC6f+FQD8Ge6dA7TLtOmbzhg +ADyiBfAGChDV8d6/1Hzt1ZCbp6C5hSA43mtpTQYEjZcGds4olsLWRMFlvn6SaE8U +/yc4f8I5aqNLijlkaO5yVtVndDXvrhyJK63yxQ2hv4wjwsq4K2PDQ4XYvUcmKPD/ +XlPlsS9Ze38WOmF18BNsWhFg/X1ZEsnJQZqQFknQ9z/lHiYTcq+HtWHD6JfZzOaM +E3UA8T88Db5hkBxdi+VdfTfF/tcJB9TVv94cA8SuyNnP6Q6AMPtj4AcaMmUbLwpN +6fOz+eRjs375gUjeGtSoPhbJZ6VvJjLK6xs1mDGS9ROACnxpeDCou3/Z35w98hvB ++vycfefBU/3Oz/FibzGZfGGRZxR88DoezSovO8xS1UTztbTV/E3Hf50BgcR927BL +NJGAapWYDd8JtV0BHG5wpaes7/XmU1ypZarztFE+5fUtgzp4AKZ9d8fLPqu7uHyy +VFSlknUG3lKAvV+aTv5kwTm6T24a0lpxxYWzaadSBxuqeJtU7FNijzCia9l+KD/j +MuWIX01bTZapbrnUlFm4fAAgbW5f3nA4jSdhRz4mKzYdZ4aMWDM8hBS+zHKdAxt+ +r3IOTmKOM53qQd6/AzPhoA0A+KC7CNCPEgYxWjHD9LvdybgmZ3XenDSbtLwQbD6Q +UwWAn1xKUS+VTfDL9VkVXP1CneqLQxZtc1Sc/vBPwSJ6+7jAYG5QfCsFKpYk6KVg +WWBjX/iaBk51jQZ/ISopM3fO5XEr5/3lYtazRsrg0f+S3e4Zzo8nxEOq9P5xVhSQ +O7JVUzPKxB+mq8b8+Trp0jpdlwATuoCmknWv7M7xGQxIxgYlBegfgpZNrb4ocJt1 +C2A5oMK874OASkTuFy/CZtTCSKDyyC2WSUJy/ybgFlZWnTyWBNaSIgYpaI2Gq/5N +W2sAGdn2IzwgLXJcE2TeXPkUP8I6D0EvyGS8UJ8WVt4jXlr/F3VEInfxr2Y6siXk +AHHFHgrTgDIGLtO8E808PqkxvLBmGkuPh75G6ryBOPonCZ0aT1e/GX3dbFPpEaEW +llXDZSgbk2fjRwniN+3OtnrHeVbQUlTC3iaVcpJd1hL8XMqXbPIDInH7Hno0Rp0/ +Voc9LaQvrTj/kEwf26rJMPkHP3A/gue3fawMlgP2mdiTeVrBYqtURRsKaMlxgKT3 +3O7Gyd/yxwB05GETZ6zA/3Z0q4ztIi5TZ5m+C2wW+NIXwkcYJdqHOodrO1fkRlTs +npvFlNq1Br3v3gImbnvFaouFkT+542lb5sOY50i4uwrifKPntqOl0n9+dE1pyipU +QURHoCbkL2QR65H1hYcDoLRvhJAfS/oEFf4DSf8HgiZITq5pSvnYcJn76jC0mNiX +9LRJqxBuOkHcdFIbmkvDuwIN0asrQmGQCAsYOOxVA6EpX0XWcJ8dVmRyWbGVZXNq +45wAMvGDj0F6Jm7b2sQ3quJFDXDWvD7hPWp8nLqRDN+P/s9tHqK5LMXPHFdcqMn4 +hKSmCVgEtnsVfWUGyjVJ0Yvh+jxdg3vECIO38UuFBuTGroD0egvsyd7iuwT3aOmn +5YaYW0vHuHERbtLy6AkO1sVVmg18jSH32tE036uQS+LCrj+G0cg6Mf5sU2CHJZA0 +9Jse9KsUSQdI7bnqvPdYIQ== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +eiP/26NloMbfJbEe1aU/cN+AkTVidxKZaNv824TVZXkpjf5L1zEVLf4buBzXwSr1 +MiO1FaB1qgL+ZgKHLwNzc4IiIP0d7qYOaGR46jDr8/k9N2BVxXC3V0wJJ6yhDom9 +O7B9d2Lcm+b0UifdEaFcX3luTwZzXAQW83Bggnm4eVP275Vqog3REHo5wgsstEU3 +AG6o+oVDnNjZTPDPyJ4uHq9bjFFyvY3ga+lOo2iVymecnhCiRtjy3AFtvWBJW0ek +uhj8QvNYf04TXkRXdhdRfq/HDLr3M6Qa7/Xn6vGE+drFyRTL1nmH9wkjBBbD3swn +58tiwvvx3ajgMOCJeXfrXQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1104 ) +`pragma protect data_block +z83CFN/6+XAqqlsaR10y0/0TRdqihm7Mln1SErDagYzHq/tf3472iVn71ufDnRwX +XjpfuAMiYkGYL+YySToA+S247ZqaWHze8oceixrYgRvhox5tY82fxq9Fl8kghDLv +SjC2MS3eD6cYQeQLFqzD1Mn0WKOQZFVCku3VAWFB2lduR5mhayfY/Fa3R/W72ABn +Z0d6Zn4ZBsgSyb/M70GpfeksPL4x3rnLEOyMOaWSU6+bpfwlHv6gwzh9HPzLZxVy +08g2U6/uxm0PBfE3o/LncY5k29GaWHkcOHv6VhXh/m8K01MJZqFeBphDIArYoxxq +PWDxAO8AUxxtI14Tgpa2V285dFMvK+4KnQioTwi0kMw0x+o+AprykzkXPkE/VVzK +KXd3WO23uskN1uRWHMVa+YBeVjuyFSDLn3GxfHH9tkFDow1kssYW0TqHWs0aqHah +qnNS7hoeJjqPZiowmyQrmDxNCJSTzH8quhzu6sXOHqjuy3hV/M2EY8gngXNAKKsb +WbOvs5QeFheEcLGYrod/Zfv9aZk0e3y0m11vKOyZVQVGFJQzc1uQ0fLjWrpSt7yG +qya4/JgJ8aoha2vBdN7gKSQ0jQBRSMhhOkv1iunq1iT+1ZETzOdrs32w7jLu65tq +rkZk2Z9PlyyFm4XlIu3ljYIH3Z1F+BdPGXiUKHiLhEHanApDED/zljh7BDGApCKl +t1zRJJjZMckJfWQclrLgdXSejbEhZFqHfgYNQe4ywo4o/SbWaqGvPgahhDBBVxZV +rvCFFNip8ka1YAIM4x0DqYw1pSFzn0sUmEm44Jl+Eo4D5chLPEJnYyAjsKm0nIFa +We3J6DKurh1q/PmPYqN51Vno2A5tlFLR8v6SH4m4qu3V3skZsRF0vR6BGx84VdVj +bN8BlLOwDEGmTO8UZpg5knVPN5bAfvf/kXvbSbr8KPR5NBZRqz3SXFeMxZYBPfbj +GI8S5ZZZeq5AvybyDwwt8BHWypNkKlsr+UxyAt+phMEA8F/U9gAt5r50llYjO4qu +5tLeotWmT7oFHBktGytHHC+gKwtWEMsJLm7+744JbDfnMvdHRr+AQgpYts9jdNY6 +guxuay2WoNBpjmE51Kq8M1xXeO6beJN3h1JAlESUfz7eFKkE8Vkr5Jg6ccn0KUsS +ZZmNyAaAta//k2mRELcX5bJmUCCHy7lAgQBjtv7XZBfyULC/eXy3RUO/ar8/VQKj +wwOLkv6PJN1DfDlpZ+oswIslScrN1ijU4t2buGKO8zI+cQCpYuC9FBN8V8chHOZw +//0ODvW7AEl6D/OUt8ZC6gUirNCSFRQjXz5x+MOrJPH54wUb0gmtQRPSsbnbcm8g +r+J90t6Fz+FSggPmyNbgv8Z+eWprb5Z3QuqJaQlTYxXGJYLXXwcTjZP3Sf58Vd4Q +9PV9zVG1BxTwV5hFTLJrTkIFGs6wyF+96e+3TnhJKuzZ4Qgf0XJPp9crAdiNtxfx +`pragma protect end_protected + +//pragma protect end + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch_define.vh b/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch_define.vh new file mode 100644 index 0000000..b794024 --- /dev/null +++ b/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch_define.vh @@ -0,0 +1,53 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.1.95 +// IP Version: 5.4 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam ARB_MODE = "ROUND_ROBIN_1"; +localparam S_PORTS = 1; +localparam DATA_WIDTH = 32; +localparam ADDR_WIDTH = 32; +localparam M_PORTS = 2; +localparam ID_WIDTH = 8; +localparam USER_WIDTH = 3; +localparam PROTOCOL = "AXI4_LITE"; diff --git a/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch_tmpl.v b/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch_tmpl.v new file mode 100644 index 0000000..1711a12 --- /dev/null +++ b/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch_tmpl.v @@ -0,0 +1,97 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.1.95 +// IP Version: 5.4 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +gTSE_1to2_switch u_gTSE_1to2_switch +( + .rst_n ( rst_n ), + .clk ( clk ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awlock ( s_axi_awlock ), + .s_axi_awready ( s_axi_awready ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arlock ( s_axi_arlock ), + .s_axi_arready ( s_axi_arready ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_wlast ( s_axi_wlast ), + .s_axi_wid ( s_axi_wid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_rready ( s_axi_rready ), + .s_axi_bid ( s_axi_bid ), + .s_axi_rid ( s_axi_rid ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rlast ( s_axi_rlast ), + .s_axi_wstrb ( s_axi_wstrb ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awready ( m_axi_awready ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arready ( m_axi_arready ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_bready ( m_axi_bready ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_rready ( m_axi_rready ), + .m_axi_bid ( m_axi_bid ), + .m_axi_rid ( m_axi_rid ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_rdata ( m_axi_rdata ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_wready ( m_axi_wready ), + .s_axi_wready ( s_axi_wready ) +); diff --git a/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch_tmpl.vhd b/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch_tmpl.vhd new file mode 100644 index 0000000..2c4910b --- /dev/null +++ b/fpga/ip/gTSE_1to2_switch/gTSE_1to2_switch_tmpl.vhd @@ -0,0 +1,149 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +component gTSE_1to2_switch is +port ( + rst_n : in std_logic; + clk : in std_logic; + s_axi_awvalid : in std_logic_vector(0 to 0); + s_axi_awaddr : in std_logic_vector(31 downto 0); + s_axi_awlock : in std_logic_vector(1 downto 0); + s_axi_awready : out std_logic_vector(0 to 0); + s_axi_arvalid : in std_logic_vector(0 to 0); + s_axi_araddr : in std_logic_vector(31 downto 0); + s_axi_arlock : in std_logic_vector(1 downto 0); + s_axi_arready : out std_logic_vector(0 to 0); + s_axi_wvalid : in std_logic_vector(0 to 0); + s_axi_wlast : in std_logic_vector(0 to 0); + s_axi_wid : in std_logic_vector(7 downto 0); + s_axi_bready : in std_logic_vector(0 to 0); + s_axi_bresp : out std_logic_vector(1 downto 0); + s_axi_rready : in std_logic_vector(0 to 0); + s_axi_bid : out std_logic_vector(7 downto 0); + s_axi_rid : out std_logic_vector(7 downto 0); + s_axi_wdata : in std_logic_vector(31 downto 0); + s_axi_rdata : out std_logic_vector(31 downto 0); + s_axi_rresp : out std_logic_vector(1 downto 0); + s_axi_bvalid : out std_logic_vector(0 to 0); + s_axi_rvalid : out std_logic_vector(0 to 0); + s_axi_rlast : out std_logic_vector(0 to 0); + s_axi_wstrb : in std_logic_vector(3 downto 0); + m_axi_awvalid : out std_logic_vector(1 downto 0); + m_axi_awaddr : out std_logic_vector(63 downto 0); + m_axi_awlock : out std_logic_vector(3 downto 0); + m_axi_awready : in std_logic_vector(1 downto 0); + m_axi_arvalid : out std_logic_vector(1 downto 0); + m_axi_araddr : out std_logic_vector(63 downto 0); + m_axi_arlock : out std_logic_vector(3 downto 0); + m_axi_arready : in std_logic_vector(1 downto 0); + m_axi_wvalid : out std_logic_vector(1 downto 0); + m_axi_wlast : out std_logic_vector(1 downto 0); + m_axi_bready : out std_logic_vector(1 downto 0); + m_axi_bresp : in std_logic_vector(3 downto 0); + m_axi_rready : out std_logic_vector(1 downto 0); + m_axi_bid : in std_logic_vector(15 downto 0); + m_axi_rid : in std_logic_vector(15 downto 0); + m_axi_wdata : out std_logic_vector(63 downto 0); + m_axi_rdata : in std_logic_vector(63 downto 0); + m_axi_rresp : in std_logic_vector(3 downto 0); + m_axi_bvalid : in std_logic_vector(1 downto 0); + m_axi_rvalid : in std_logic_vector(1 downto 0); + m_axi_rlast : in std_logic_vector(1 downto 0); + m_axi_wstrb : out std_logic_vector(7 downto 0); + m_axi_wready : in std_logic_vector(1 downto 0); + s_axi_wready : out std_logic_vector(0 to 0) +); +end component gTSE_1to2_switch; + +---------------------- End COMPONENT Declaration ------------ +------------- Begin Cut here for INSTANTIATION Template ----- +u_gTSE_1to2_switch : gTSE_1to2_switch +port map ( + rst_n => rst_n, + clk => clk, + s_axi_awvalid => s_axi_awvalid, + s_axi_awaddr => s_axi_awaddr, + s_axi_awlock => s_axi_awlock, + s_axi_awready => s_axi_awready, + s_axi_arvalid => s_axi_arvalid, + s_axi_araddr => s_axi_araddr, + s_axi_arlock => s_axi_arlock, + s_axi_arready => s_axi_arready, + s_axi_wvalid => s_axi_wvalid, + s_axi_wlast => s_axi_wlast, + s_axi_wid => s_axi_wid, + s_axi_bready => s_axi_bready, + s_axi_bresp => s_axi_bresp, + s_axi_rready => s_axi_rready, + s_axi_bid => s_axi_bid, + s_axi_rid => s_axi_rid, + s_axi_wdata => s_axi_wdata, + s_axi_rdata => s_axi_rdata, + s_axi_rresp => s_axi_rresp, + s_axi_bvalid => s_axi_bvalid, + s_axi_rvalid => s_axi_rvalid, + s_axi_rlast => s_axi_rlast, + s_axi_wstrb => s_axi_wstrb, + m_axi_awvalid => m_axi_awvalid, + m_axi_awaddr => m_axi_awaddr, + m_axi_awlock => m_axi_awlock, + m_axi_awready => m_axi_awready, + m_axi_arvalid => m_axi_arvalid, + m_axi_araddr => m_axi_araddr, + m_axi_arlock => m_axi_arlock, + m_axi_arready => m_axi_arready, + m_axi_wvalid => m_axi_wvalid, + m_axi_wlast => m_axi_wlast, + m_axi_bready => m_axi_bready, + m_axi_bresp => m_axi_bresp, + m_axi_rready => m_axi_rready, + m_axi_bid => m_axi_bid, + m_axi_rid => m_axi_rid, + m_axi_wdata => m_axi_wdata, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_rvalid => m_axi_rvalid, + m_axi_rlast => m_axi_rlast, + m_axi_wstrb => m_axi_wstrb, + m_axi_wready => m_axi_wready, + s_axi_wready => s_axi_wready +); + +------------------------ End INSTANTIATION Template --------- diff --git a/fpga/ip/gTSE_1to2_switch/ipm/component.pickle b/fpga/ip/gTSE_1to2_switch/ipm/component.pickle new file mode 100644 index 0000000..e262fd7 Binary files /dev/null and b/fpga/ip/gTSE_1to2_switch/ipm/component.pickle differ diff --git a/fpga/ip/gTSE_1to2_switch/ipm/graph.pickle b/fpga/ip/gTSE_1to2_switch/ipm/graph.pickle new file mode 100644 index 0000000..bc82c02 Binary files /dev/null and b/fpga/ip/gTSE_1to2_switch/ipm/graph.pickle differ diff --git a/fpga/ip/gTSE_1to2_switch/settings.json b/fpga/ip/gTSE_1to2_switch/settings.json new file mode 100644 index 0000000..cd4b201 --- /dev/null +++ b/fpga/ip/gTSE_1to2_switch/settings.json @@ -0,0 +1,96 @@ +{ + "args": [ + "-o", + "gTSE_1to2_switch", + "--base_path", + "/home/cslau/Desktop/Workspace/efinity/2025.1.95/project/Example_Ti/ip/EfxSapphireHpSoc_slb/Ti375C529_devkit/ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "axi_infra", + "name": "efx_axi_interconnect", + "version": "5.4" + } + ], + "conf": { + "ARB_MODE": "\"ROUND_ROBIN_1\"", + "S_PORTS": "1", + "TABLE0_AXI_S0__MIN": "32'd0", + "TABLE0_AXI_S1__MIN": "32'd512", + "TABLE0_AXI_S2__MIN": "32'd285212672", + "TABLE0_AXI_S3__MIN": "32'd286261248", + "TABLE0_AXI_S4__MIN": "32'd536870912", + "TABLE0_AXI_S5__MIN": "32'd805306368", + "TABLE0_AXI_S6__MIN": "32'd1073741824", + "TABLE0_AXI_S7__MIN": "32'd1090519040", + "TABLE0_AXI_S0__MAX": "32'd9", + "TABLE0_AXI_S1__MAX": "32'd8", + "TABLE0_AXI_S2__MAX": "32'd12", + "TABLE0_AXI_S3__MAX": "32'd20", + "TABLE0_AXI_S4__MAX": "32'd28", + "TABLE0_AXI_S5__MAX": "32'd28", + "TABLE0_AXI_S6__MAX": "32'd24", + "TABLE0_AXI_S7__MAX": "32'd20", + "DATA_WIDTH": "32", + "ADDR_WIDTH": "32", + "M_PORTS": "2", + "ID_WIDTH": "8", + "USER_WIDTH": "3", + "PROTOCOL": "\"AXI4_LITE\"" + }, + "output": { + "external_script_generator": [], + "external_source_source": [ + "gTSE_1to2_switch/gTSE_1to2_switch.v", + "gTSE_1to2_switch/gTSE_1to2_switch_tmpl.vhd", + "gTSE_1to2_switch/gTSE_1to2_switch_define.vh", + "gTSE_1to2_switch/gTSE_1to2_switch_tmpl.v" + ], + "external_example_example": [ + "gTSE_1to2_switch/Ti60F225_devkit/axi_interconnect_ed.xml", + "gTSE_1to2_switch/Ti60F225_devkit/constraints.sdc", + "gTSE_1to2_switch/Ti60F225_devkit/axi_interconnect_ed.peri.xml", + "gTSE_1to2_switch/Ti60F225_devkit/efx_crc32.v", + "gTSE_1to2_switch/Ti60F225_devkit/efx_custom_master_model.v", + "gTSE_1to2_switch/Ti60F225_devkit/efx_custom_slave_model.v", + "gTSE_1to2_switch/Ti60F225_devkit/top.v", + "gTSE_1to2_switch/Ti60F225_devkit/efx_fifo_top.v", + "gTSE_1to2_switch/Ti60F225_devkit/axi_interconnect.vh", + "gTSE_1to2_switch/Ti60F225_devkit/gTSE_1to2_switch.v", + "gTSE_1to2_switch/Ti60F225_devkit/gTSE_1to2_switch_define.vh" + ], + "external_testbench_synopsys": [ + "gTSE_1to2_switch/Testbench/synopsys/gTSE_1to2_switch.v" + ], + "external_testbench_modelsim": [ + "gTSE_1to2_switch/Testbench/modelsim/gTSE_1to2_switch.v" + ], + "external_testbench_ncsim": [ + "gTSE_1to2_switch/Testbench/ncsim/gTSE_1to2_switch.v" + ], + "external_testbench_aldec": [ + "gTSE_1to2_switch/Testbench/aldec/gTSE_1to2_switch.v" + ], + "external_testbench_testbench": [ + "gTSE_1to2_switch/Testbench/modelsim.do", + "gTSE_1to2_switch/Testbench/modelsim.sh", + "gTSE_1to2_switch/Testbench/xrun.sh", + "gTSE_1to2_switch/Testbench/axi_interconnect.vh", + "gTSE_1to2_switch/Testbench/tb.v", + "gTSE_1to2_switch/Testbench/top.v", + "gTSE_1to2_switch/Testbench/efx_custom_slave_model.v", + "gTSE_1to2_switch/Testbench/efx_crc32.v", + "gTSE_1to2_switch/Testbench/efx_custom_master_model.v", + "gTSE_1to2_switch/Testbench/efx_fifo_top.ncsim.v", + "gTSE_1to2_switch/Testbench/efx_fifo_top.vcs.v", + "gTSE_1to2_switch/Testbench/flist_ncsim", + "gTSE_1to2_switch/Testbench/flist_modelsim", + "gTSE_1to2_switch/Testbench/efx_fifo_top.modelsim.v", + "gTSE_1to2_switch/Testbench/gTSE_1to2_switch.v", + "gTSE_1to2_switch/Testbench/gTSE_1to2_switch_define.vh" + ] + }, + "ooc_synthesis": {}, + "sw_version": "2025.1.95", + "generated_date": "2025-04-14T02:17:58.052364+00:00" +} \ No newline at end of file diff --git a/fpga/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl.sv b/fpga/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl.sv new file mode 100644 index 0000000..1562fb2 --- /dev/null +++ b/fpga/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl.sv @@ -0,0 +1,1587 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 8.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _0340c286f12f4e3bb92b102aa178f77b +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module gTSE_core_fifo_ctrl +( + output full_o, + output empty_o, + input wr_clk_i, + input rd_clk_i, + input wr_en_i, + input rd_en_i, + input [15:0] wdata, + output rst_busy, + output [15:0] rdata, + input a_rst_i, + output [9:0] wr_datacount_o, + output [9:0] rd_datacount_o +); +`IP_MODULE_NAME(efx_fifo_top) +#( + .SYNC_CLK (0), + .SYNC_STAGE (2), + .DATA_WIDTH (16), + .MODE ("FWFT"), + .OUTPUT_REG (0), + .PROG_FULL_ASSERT (128), + .PROGRAMMABLE_FULL ("NONE"), + .PROG_FULL_NEGATE (128), + .PROGRAMMABLE_EMPTY ("NONE"), + .PROG_EMPTY_ASSERT (2), + .PROG_EMPTY_NEGATE (3), + .OPTIONAL_FLAGS (0), + .PIPELINE_REG (1), + .DEPTH (512), + .FAMILY ("TITANIUM"), + .ASYM_WIDTH_RATIO (4), + .BYPASS_RESET_SYNC (0), + .ENDIANESS (0), + .RAM_STYLE ("block_ram"), + .OVERFLOW_PROTECT (0), + .UNDERFLOW_PROTECT (0) +) +u_efx_fifo_top +( + .full_o ( full_o ), + .empty_o ( empty_o ), + .wr_clk_i ( wr_clk_i ), + .rd_clk_i ( rd_clk_i ), + .wr_en_i ( wr_en_i ), + .rd_en_i ( rd_en_i ), + .wdata ( wdata ), + .rst_busy ( rst_busy ), + .rdata ( rdata ), + .a_rst_i ( a_rst_i ), + .wr_datacount_o ( wr_datacount_o ), + .rd_datacount_o ( rd_datacount_o ) +); +endmodule + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian + parameter RAM_STYLE = "block_ram" +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + // NIC + //wr_ack <= wr_en_int & ~wr_overflow; + wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; + end + end + end + + if (OVERFLOW_PROTECT) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else begin + wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; + end + end + end + + if (UNDERFLOW_PROTECT) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else begin + rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + // NIC + else if (ASYM_WIDTH_RATIO == 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - raddr_int; + assign rd_datacount_int = waddr_int - raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + // NIC + //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_r <= 'h0; + end + else begin + waddr_cntr_r <= waddr_cntr; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + end + // NIC + //else if (rd_en_int) begin + else begin + //raddr_cntr <= raddr_cntr + 1'b1; + //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); + raddr_cntr <= ram_raddr; + end +end +// NIC +assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); + + +generate + if (SYNC_CLK) begin : sync_clk + if (MODE == "FWFT") begin + assign waddr_int = waddr_cntr_r; + assign raddr_int = raddr_cntr; + end + else begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr; + end + end + else begin : async_clk + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_resetsync) #( + parameter ASYNC_STAGE = 2, + parameter ACTIVE_LOW = 1 +) ( + input wire clk, + input wire reset, + output wire d_o +); + + +generate + if (ACTIVE_LOW == 1) begin: active_low + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (1), + .RST_VALUE (0) + ) efx_resetsync_active_low ( + .clk (clk), + .reset_n (reset), + .d_i (1'b1), + .d_o (d_o) + ); + end + else begin: active_high + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (0), + .RST_VALUE (1) + ) efx_resetsync_active_high ( + .clk (clk), + .reset_n (reset), + .d_i (1'b0), + .d_o (d_o) + ); + end +endgenerate + +endmodule + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_asyncreg) #( + parameter ASYNC_STAGE = 2, + parameter WIDTH = 4, + parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset + parameter RST_VALUE = 0, + parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance +) ( + input wire clk, + input wire reset_n, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + + + + + + + + + + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect author = "author-a" , author_info = "author-a-details" +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V +o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE +El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY +kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc +/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 +uYJaS5tuGEuFInBHa7oO8g== +`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 +fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa +rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq +PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL +DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w +K3OoKmk3zFeArSsql8B4/Q== +`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 ) +`pragma protect key_block +RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M +GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l +6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI= +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf +RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk +1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw +Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz +eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0 +2HflB1HYKxojQCcZU7qUgQ== +`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx +Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB +rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr +XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD +e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod +B2Zpo2FQ//YDRSAaEa9ksQ== +`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze +vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 +ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 +06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP +fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN +ZoPzFCMjGk5ZmMyIlytNCw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 ) +`pragma protect data_block +0d33xo/2RnBYy8BD6jq1J42m9u/75PA0owNvxlnr0TDOq7sF8XT6xouctVD1XQW2 +Ylwj0urY+dCJZku0aGRpcvb3H/nTlKVdEZOEl4QqB1gNGz/3mz75A3eudu5zgHEr +MaagjyQfDnoIqLWi1r5uTZrlS298IvNcGAJ+xXzpmkFmfG4Tk/5Jf2GPAPVtjREI +01kt8Go4CL1WNxBKcwm0xCiCchxvZ2oEtpERiC+7LUalgTJapIVoLFpvFv98229k +egvgF1KHNj0rAKedSG2Xo58TyA4iZXJJDdtgCxiKgu3Rimjno7l+ekApwmvx8n+p +yHkRGqetWfRhyE4A5q03RzOeSdA6NbCqijB3NPw/p58brAbA35rrjYpGIZXtZ4mU +De3As8VtD64nS2PRuf4/a2lIcDbwMjNTfMpN7iJfVBJ0/48tLHdetx592TLXenkF +GvAZ2yxoyBYzKctj4Keo+19Xp1UjVd3fr2MR3A7nmxLRKDA+upDxQ7ql8+pR7Moh +0b53/4Ri3Mkl+7EC1KXJNt2VbkZmcT7OAFIoPpibmcXS2R6DNVrhSKzfc2+TRM9r +mwRrJy9/R5RR+WGfw1S57Ho3wBPf4belj+Tfd7yhnwOVRXkTMq5M1BiigrGeeQ3q +z/hc1Kg8b/R+g7lnU0pqASnExPQW/DIMfH1RX75U68CAgaBAH22Vcbkoibp8sxyO +g18LefEh48UffnbpCKyv7SQ3LAdj+YO+KvvXHj1eW+CH7GA2lC5vt2be5Ah2/13H +bCeZ+srG6r7wmafy9MNNh8AgjUfZWwMnuJdCIcHTOfAncCd2B0T1Oza4VIkvnSl5 +60V34JXkfrGsNuHxwCF/sRSBbZUSpqig4ZGYHjOHldx2OANZQeUvLES3fwScYY5D +7SpR4ofVxIB/ev/+RXzvC3MNk1N0GT4F1XwokeeQIr/ilRETe/pFvEKttvviZ7uJ +uEVblS2v61DMXEgDavkbA0WdhMChPulwDvZtisWT4hCKRxfuBvNBtz0wH/WgRoX3 +aipWvPJG3G0xvO0u0EQVNdcxE+LZ7vyGF5HWEwKdQYDyhH+yVDeG+M/b08dU2aq4 +sG7dyygyVnzVbk2Lf0nCkGqKkUZUr05Zim0Wcflkhkqy348SOZ3xmEGuYAkzelLV +feQ+0ScsscFL5Cq4ETfFrN8GO8M5kkBN2ELs1MQecPRsgMCh0hcvd8IQrJTybQPW +aqwp9mgnFvS8AJ1ct+XgrAt8zgVnhaZGS9TKa6OWbr0U+SD5m+/pXjNsZA2dni6b +85/PmQeWeAarE/+EaJn/hlP6y3x3R3ItU8Itf6SB50LZ17LAhIRSIYsa7LBBNWOk +ngFHcGBCJnqTJv3hdVqa9cYipZ98XCa8dqrtAM5Rkxwd6H8KxXA+B+PWEz/cQWlb +szi9u5ufmyaJp6PWhklroQkPJEorUtF96X763itgtlAMHfkZglkElUD/gPlkXLtl +yquUmHqPK5D2pJDq0Q0jromE2yrr9fl3OI+eBehd2YBUivGKeaDFkPx7HbzWp9ok +9bT55H8VKYyF1awcjNND+WcXzm2WfvZHBDUJkRm7dnOQRvcX2RxlPRZSzAA3irVn +GFbHXD0RYn/dUR7Vy4kU68P5S5q4bUxD5vmUCN9vDoCivY7WCnlQCHQs3+iFblzP +A636C3dNQMSw0pjDisiZB63VczY8bivFh3cO82inNw5r2IZjvMB9XPhc4FHuIpfR +F7ptW0TUnO1MSDcZvCnjUfVSnHN22l2FM/P5oI1SbG3W+8YmxBvto8jwpES4ohOQ +YSECrvWkLklq68FVTzB7Tvg3JLdSy3TEKBuZE/ot0w/SXusFovOwd4aeiNDAmzwl +fQuCYHuJ0UKLaVNVAO4mw91PJODKCk2NYTr0ghOLovOXiMhUYtXZ+wFchXVkQKDI +B8BXjM7P+blhoOFA6AhRuCX4gZn0dP6m99qnyBJoxf1/FyfJXuklnPll93amUYUx +MzxNNTf7F08tnKQ8pTOk2mfFZnhA2MFn4XQ9FaGvtUrlJI8bvJTWiZFMF0eOJdIw +kzYOXEzKBjIdWW4rtTZmQJb7AOrznUpYdgTAPip/DQx6cg1+tZAVwhZPCjCsb5wa +em5hMtISQKDc92QrlU5O74OXe7641fzFRcKqy9AzwhZl+tmHk1uvpDkpsYiMa7Rk +YrbIjsKQV36PTqYPvxq1EiwYF8PMRf9FG8JZk85EZdM6QEGuehDHqFcZ+SlUb7/e +ji6GgjKxcZwaRREGKSOslcscHS6QNuGCF3iInqNCT4V2l7nboWOefMT2f1kmQOdE +szTFg563SQ8pu7ok3T3XNqUDi5ulvF+XGHDhcQ2hTkZ+xQ8dHFAWZdgzEGMXF2Lw +jU+ZRA2JULfjxOMIU2j9f+aGWmFx2PELMA5K5uOWYUQG2Fn04p1D6u8MEe7fIPeI +k7KH8j/Tumj+kG4t/lCrme6VM9u6A2NGddX1yH1NCejfophy3UWJg9wL/dNxzf6t +vXdm3rGPdZPWFgSIuGlmT03QZmWGPbs8qvkkUVAL37kMJP2r4L+PI00ZxbX8V5jp +GgYN1Rh+NSOwAcUEFCViRhFYC+Gi5eZ6AF6XDSU6qfjGsUKqJ9yrNx0Km6+SjpAK +7Zxblp7vweFVkJ7IESoFeB+vP8JNeoidbBPGEWo+2V08PgfGgjPEAA6pjj8uc0jC +SDFZ0sVrzvc66PZ5FxbI4g+VuXPJgyJsnQ/eHhPVTVTP3/oGMRVktNiJrkJYxAW7 +Sa/EJMjfXX+rMIWG5ssWLT6WfrojlHduEqJ9hJr24RZy514HHF8SMPRBLD6l1wd5 +07U/ChjFdy5qHn5Ce+lanjxnoxgvCsF3lMqoZ7e2bfzXakj7CxahwqRt6yeU0Q+/ +a8tvIJgHfdtOPw/r6HnSrzpdWzTx2e6/MEryHZqpMN63Lhakpjw1L7u3FD/rW40b +LGajigQ7Ql+cZmP7wYl+uSmTFIS6ZgXOc1ibb7yYxJwpeixPHL1iu5ltvriRiTZ6 +DMbbOjNpPuL7ie3AwgmwXwnpnTL6k/Rj2+ma3B7ImODBMkC4SLtTc0ynCcPAFZKA +Xh78wUAgt1T5Nm4XR555DBO7zPHX9rZzMLil4/j0RMDwn1gitmP2PSNFWsrXJG8p +C46kfpdqoM3Yf6HySlhsith6GW41sMF6imUXwahQQRw240HLW3N876LDe6bjTmgN +eIC7y/4NZk7OmpmP8udAEH+UsNfSGtKA8959AoJDr43XsWkOfccNWstu4sTXA5+w +pCALypmBMdholEsrW9DgsIgbgf2pcOAC9+mAjld+yyQ+UNdKRbmtRDHTztGmcVvw +Szip4YUuTM1tPzReucfm38gVFT7eo1qFQg/FJ4VgeYab7ku5OHuwZQmKyzng/t0U +A1lquVENVYQEIotBiOC7jQ1YTkTasGN4xoFgFTyKLFPyk8bl2/anzr1Fx0ieVGCx +2ipzG2JzIQf/FlHXaYrgkWiF817amty+KZp4/dCJtvDXxzOZKnBTVcjHXpqR1Ik+ +tdV+k+21tXZxP0rkG0yi4//2c5UiWGb0UegpemqutykLuT9tGjsqMuc5DaDH/8zk +wLTVfODT+HqN1/ZLqfq9VoAF5m/ujnPNt3wZcsjsAyBD153rW4Q2yVYMat0sFQN6 +XbNAeNBJZlO/aE1PfKBcSDFkJkPqRxlgdiE5B83/w1MP6Z4qwz7LJ8yTYM22xwRo +LIYpKq52yYMhJm42YeQxbBRTx0MyubCb+ompEVBF28Eh0vE98UAZj7t1szSweg99 +Wq6/4kxR2SQj8rFo2wrZe7ngsDmbIrMk2SinS6WmV4Mj+MBbPlmiuwB6NUV04Id1 +9enBBsJIfWt+PZJXyWkOoG/fOVBUxCY+CMCiab0qQ1EVdhggrdI30BgFqcLjfyD6 +/h5AqIzMGWrhWnap8WDEh1Ah6K9f2oCESSXO751sV5eK8jgl63FJMIVsnjVejxrl +Qa7PCXP3BO6Cnv896NBzAsddPq/AYBLHIC6eX3sTtOxTx52NsmJzoyUSJcAoA/QS +leHU1bLA2z+HGfMrkSzsuvXafmqr3B+PHfWdxrYzTxmVhMBPX/FvEU/gfxXGa6kj +niZYGue/Rk+zXL65ENgPwxiz0mm7QyQ6eMBMRovm6MGyIl/8obkOPygH+lhc+bgR +SNWLmxqjR2YABrKsUgCITQ6GK7VmVR3wOOwbZs+YW/0Yj2yzg7ESjaeqI40/OQFD +Ft2IHaURJPk6jl5vRrcCc0J0GCy7CK0BU14n+Nxfl2+CFRe4efoqZry/CmY2+S4M +p9OqgjUzHGSIbNRAXHf44nIAUjWYvijzzLSj9A7WY3TpYxgtqU8Wbf7SbWmw8RJV +pAYDHGmwHa8fL4Y9xEFF/WqmqWSL3g146i41MKWKY7lchvnWtc6yOgk+0geVFOpe +9BLs4TehFA/SueFC99S0Cxcxc0KMWXOKm0I3bI1CAlLje7wUcdI/pki33iqBLJlL +T2vz8ptPqfgAxDW0ZEvEYY/jfB+jCO0MKT7XK/LZNYSuEke3Y3CeuwZ/5IWkDcwy +7BArmDy7Hpw88le9ODL94mS1fUB8jsBaazeiXniZPNZjBkugt/ZAf4XYuoaGVPAM +DnRd8GW5eiDHFCEB42lpg9n7Ak8cXsSSlODCHeay2VtcQP1DEgwWdI5XdXE879gI +8lLU9bH2MfsxI2mNWCMv5immaioZJDorIVzyMGvIn3OcgqmhTU1owINUJf+Hm8Q7 +JfJq4m6t0J5eoKQH57uSGFkWRZ3dtp5QL3d5bBOMmorXUBzdrLt8wurvNke29bHD +UQdmANjayV8drYWAccZdPWyi9jNC/K31BTDI6RCpZdV3Wr5scOZdXWrl961jirm1 +g/2MGKxriuH2F4MRIh2vp3uS8PLbj4cHJv+5+LtLgs0lpdEMYAvJKDACRg68tDhY +XsF9lhHpcF5+tANOawRtnSvy/rlLn+A3wi7v8tnTZcLkocJ51c+nK5/Ij0YgUrA0 +eLrKNlJM78stswPWkvpBlAJ+G3D4Cw6P3XcJWrLyV3u79jf9PRJZmxMU/COGTmgQ +PJdXp90O3u2Pjdwhp4VdtBK2d/jTpk59j8xbQBavf5flZ+PzoLpd8NSt6GdPVJ5r +uVWvNy14pJXUsn+Tgxj+9Wp3vm5mofWtJAkEgr/Rfp7AVLLShJSd6vsbT7F2+TS/ +OMDv0XH92v1G4tqJ0rbxS1TnxX61+1sfjKlfIQdFR9gxLy71Tb705LQHBAw8vmSx +X6Uv+HbtPaEqRCF+pdvGsLNI2Seo6INA/mXqNpd6VPhfQHtp3bgV+Hxnlcc9lCiI +bCZq6KG4a6sVQHIZ3pZo7PQtoAo22niHvgZFoOVnBv+bu+blmvSV6gxCPoV8rwOe +/WD7YikHE7WVSq1SHtTIcbPv+K+1NKqZIiSCS2qDfJLgI7vH4zjIqibDhzGZTeKV +Km234SSlJ1OL4WQ5FtsxjednjUIAKqVe1auDiTzAKY28dwUkwGN/XXQ+EjrmxQuL +qIAT3WP49EeM+CQCp3D6Vxzm7Picq+RtwtbAXnnSQtvPcaSprODI089a0iR46Pp/ +4DLMUOLS+01HozXF1589YdqYep05No/Fp4eP2RdQxicYxK8d/OcvG7E8F1URVmAa +XdZxVa9caM3xYMWDZaiaOo6IZ+YM5VeZ4KxUblS1L1IlOnGOOZ3AiaLsHOh55ryc +Ei7EaFpheCmlTJyxUg8TdA== +`pragma protect end_protected + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/fpga/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_define.svh b/fpga/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_define.svh new file mode 100644 index 0000000..d6e5cb2 --- /dev/null +++ b/fpga/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_define.svh @@ -0,0 +1,66 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 8.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 2; +localparam DATA_WIDTH = 16; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 128; +localparam PROGRAMMABLE_FULL = "NONE"; +localparam PROG_FULL_NEGATE = 128; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 2; +localparam PROG_EMPTY_NEGATE = 3; +localparam OPTIONAL_FLAGS = 0; +localparam PIPELINE_REG = 1; +localparam DEPTH = 512; +localparam FAMILY = "TITANIUM"; +localparam ASYM_WIDTH_RATIO = 4; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; +localparam RAM_STYLE = "block_ram"; +localparam OVERFLOW_PROTECT = 0; +localparam UNDERFLOW_PROTECT = 0; diff --git a/fpga/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.sv b/fpga/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.sv new file mode 100644 index 0000000..a0f357f --- /dev/null +++ b/fpga/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.sv @@ -0,0 +1,60 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 8.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +gTSE_core_fifo_ctrl u_gTSE_core_fifo_ctrl +( + .full_o ( full_o ), + .empty_o ( empty_o ), + .wr_clk_i ( wr_clk_i ), + .rd_clk_i ( rd_clk_i ), + .wr_en_i ( wr_en_i ), + .rd_en_i ( rd_en_i ), + .wdata ( wdata ), + .rst_busy ( rst_busy ), + .rdata ( rdata ), + .a_rst_i ( a_rst_i ), + .wr_datacount_o ( wr_datacount_o ), + .rd_datacount_o ( rd_datacount_o ) +); diff --git a/fpga/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.vhd b/fpga/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.vhd new file mode 100644 index 0000000..470be78 --- /dev/null +++ b/fpga/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.vhd @@ -0,0 +1,75 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +component gTSE_core_fifo_ctrl is +port ( + full_o : out std_logic; + empty_o : out std_logic; + wr_clk_i : in std_logic; + rd_clk_i : in std_logic; + wr_en_i : in std_logic; + rd_en_i : in std_logic; + wdata : in std_logic_vector(15 downto 0); + rst_busy : out std_logic; + rdata : out std_logic_vector(15 downto 0); + a_rst_i : in std_logic; + wr_datacount_o : out std_logic_vector(9 downto 0); + rd_datacount_o : out std_logic_vector(9 downto 0) +); +end component gTSE_core_fifo_ctrl; + +---------------------- End COMPONENT Declaration ------------ +------------- Begin Cut here for INSTANTIATION Template ----- +u_gTSE_core_fifo_ctrl : gTSE_core_fifo_ctrl +port map ( + full_o => full_o, + empty_o => empty_o, + wr_clk_i => wr_clk_i, + rd_clk_i => rd_clk_i, + wr_en_i => wr_en_i, + rd_en_i => rd_en_i, + wdata => wdata, + rst_busy => rst_busy, + rdata => rdata, + a_rst_i => a_rst_i, + wr_datacount_o => wr_datacount_o, + rd_datacount_o => rd_datacount_o +); + +------------------------ End INSTANTIATION Template --------- diff --git a/fpga/ip/gTSE_core_fifo_ctrl/ipm/component.pickle b/fpga/ip/gTSE_core_fifo_ctrl/ipm/component.pickle new file mode 100644 index 0000000..61a1d4c Binary files /dev/null and b/fpga/ip/gTSE_core_fifo_ctrl/ipm/component.pickle differ diff --git a/fpga/ip/gTSE_core_fifo_ctrl/ipm/graph.pickle b/fpga/ip/gTSE_core_fifo_ctrl/ipm/graph.pickle new file mode 100644 index 0000000..6aaff8c Binary files /dev/null and b/fpga/ip/gTSE_core_fifo_ctrl/ipm/graph.pickle differ diff --git a/fpga/ip/gTSE_core_fifo_ctrl/settings.json b/fpga/ip/gTSE_core_fifo_ctrl/settings.json new file mode 100644 index 0000000..20c6360 --- /dev/null +++ b/fpga/ip/gTSE_core_fifo_ctrl/settings.json @@ -0,0 +1,75 @@ +{ + "args": [ + "-o", + "gTSE_core_fifo_ctrl", + "--base_path", + "/projects/SSE/llching/repo/efx_IP_master/efx_IP/efx_hard_soc/fpga/Ti375C529_devkit/ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "memory", + "name": "efx_fifo_top", + "version": "8.1" + } + ], + "conf": { + "SYNC_CLK": "0", + "SYNC_STAGE": "2", + "DEPTH_2": "9", + "DATA_WIDTH": "16", + "MODE": "\"FWFT\"", + "OUTPUT_REG": "0", + "PROG_FULL_ASSERT": "128", + "PROGRAMMABLE_FULL": "\"NONE\"", + "PFN_INTERNAL": "127", + "PEA_INTERNAL": "2", + "PEN_INTERNAL": "3", + "PROGRAMMABLE_EMPTY": "\"NONE\"", + "OPTIONAL_FLAGS": "0", + "PIPELINE_REG": "1", + "ASYM_WIDTH_RATIO": "4", + "BYPASS_RESET_SYNC": "0", + "ENDIANESS": "0", + "RAM_STYLE": "\"block_ram\"", + "OVERFLOW_PROTECT": "0", + "UNDERFLOW_PROTECT": "0" + }, + "output": { + "external_source_source": [ + "gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl.sv", + "gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_define.svh", + "gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.sv", + "gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.vhd" + ], + "external_example_example": [ + "gTSE_core_fifo_ctrl/T20F256_devkit/fifo_demo.peri.xml", + "gTSE_core_fifo_ctrl/T20F256_devkit/fifo_demo.xml", + "gTSE_core_fifo_ctrl/T20F256_devkit/fifo_demo_top.v", + "gTSE_core_fifo_ctrl/T20F256_devkit/fifo_demo_T20.sdc", + "gTSE_core_fifo_ctrl/T20F256_devkit/efx_symmetric_width_fifo_top.sv", + "gTSE_core_fifo_ctrl/T20F256_devkit/gTSE_core_fifo_ctrl.sv", + "gTSE_core_fifo_ctrl/T20F256_devkit/gTSE_core_fifo_ctrl_define.svh" + ], + "external_example_2": [ + "gTSE_core_fifo_ctrl/Ti60F225_devkit/fifo_demo.peri.xml", + "gTSE_core_fifo_ctrl/Ti60F225_devkit/fifo_demo.xml", + "gTSE_core_fifo_ctrl/Ti60F225_devkit/fifo_demo_top.v", + "gTSE_core_fifo_ctrl/Ti60F225_devkit/fifo_demo_Ti60.sdc", + "gTSE_core_fifo_ctrl/Ti60F225_devkit/efx_symmetric_width_fifo_top.sv", + "gTSE_core_fifo_ctrl/Ti60F225_devkit/gTSE_core_fifo_ctrl.sv", + "gTSE_core_fifo_ctrl/Ti60F225_devkit/gTSE_core_fifo_ctrl_define.svh" + ], + "external_testbench_testbench": [ + "gTSE_core_fifo_ctrl/Testbench/fifo_tb.sv", + "gTSE_core_fifo_ctrl/Testbench/xrun.sh", + "gTSE_core_fifo_ctrl/Testbench/msim.sh", + "gTSE_core_fifo_ctrl/Testbench/flist", + "gTSE_core_fifo_ctrl/Testbench/modelsim.do", + "gTSE_core_fifo_ctrl/Testbench/gTSE_core_fifo_ctrl.sv", + "gTSE_core_fifo_ctrl/Testbench/gTSE_core_fifo_ctrl_define.svh" + ] + }, + "ooc_synthesis": {}, + "sw_version": "2025.2.272", + "generated_date": "2025-10-16T09:35:38.547531+00:00" +} \ No newline at end of file diff --git a/fpga/ip/gTSE_core_fifo_data/gTSE_core_fifo_data.sv b/fpga/ip/gTSE_core_fifo_data/gTSE_core_fifo_data.sv new file mode 100644 index 0000000..79ebb98 --- /dev/null +++ b/fpga/ip/gTSE_core_fifo_data/gTSE_core_fifo_data.sv @@ -0,0 +1,1587 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 8.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _b22e1dac76b0412988d984e3bea79485 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module gTSE_core_fifo_data +( + output full_o, + output empty_o, + input wr_clk_i, + input rd_clk_i, + input wr_en_i, + input rd_en_i, + input [12:0] wdata, + output rst_busy, + output [12:0] rdata, + input a_rst_i, + output [12:0] wr_datacount_o, + output [12:0] rd_datacount_o +); +`IP_MODULE_NAME(efx_fifo_top) +#( + .SYNC_CLK (0), + .SYNC_STAGE (2), + .DATA_WIDTH (13), + .MODE ("STANDARD"), + .OUTPUT_REG (0), + .PROG_FULL_ASSERT (128), + .PROGRAMMABLE_FULL ("NONE"), + .PROG_FULL_NEGATE (128), + .PROGRAMMABLE_EMPTY ("NONE"), + .PROG_EMPTY_ASSERT (2), + .PROG_EMPTY_NEGATE (3), + .OPTIONAL_FLAGS (0), + .PIPELINE_REG (1), + .DEPTH (4096), + .FAMILY ("TITANIUM"), + .ASYM_WIDTH_RATIO (4), + .BYPASS_RESET_SYNC (0), + .ENDIANESS (0), + .RAM_STYLE ("block_ram"), + .OVERFLOW_PROTECT (0), + .UNDERFLOW_PROTECT (0) +) +u_efx_fifo_top +( + .full_o ( full_o ), + .empty_o ( empty_o ), + .wr_clk_i ( wr_clk_i ), + .rd_clk_i ( rd_clk_i ), + .wr_en_i ( wr_en_i ), + .rd_en_i ( rd_en_i ), + .wdata ( wdata ), + .rst_busy ( rst_busy ), + .rdata ( rdata ), + .a_rst_i ( a_rst_i ), + .wr_datacount_o ( wr_datacount_o ), + .rd_datacount_o ( rd_datacount_o ) +); +endmodule + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian + parameter RAM_STYLE = "block_ram" +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + // NIC + //wr_ack <= wr_en_int & ~wr_overflow; + wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; + end + end + end + + if (OVERFLOW_PROTECT) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else begin + wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; + end + end + end + + if (UNDERFLOW_PROTECT) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else begin + rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + // NIC + else if (ASYM_WIDTH_RATIO == 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - raddr_int; + assign rd_datacount_int = waddr_int - raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + // NIC + //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_r <= 'h0; + end + else begin + waddr_cntr_r <= waddr_cntr; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + end + // NIC + //else if (rd_en_int) begin + else begin + //raddr_cntr <= raddr_cntr + 1'b1; + //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); + raddr_cntr <= ram_raddr; + end +end +// NIC +assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); + + +generate + if (SYNC_CLK) begin : sync_clk + if (MODE == "FWFT") begin + assign waddr_int = waddr_cntr_r; + assign raddr_int = raddr_cntr; + end + else begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr; + end + end + else begin : async_clk + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_resetsync) #( + parameter ASYNC_STAGE = 2, + parameter ACTIVE_LOW = 1 +) ( + input wire clk, + input wire reset, + output wire d_o +); + + +generate + if (ACTIVE_LOW == 1) begin: active_low + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (1), + .RST_VALUE (0) + ) efx_resetsync_active_low ( + .clk (clk), + .reset_n (reset), + .d_i (1'b1), + .d_o (d_o) + ); + end + else begin: active_high + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (0), + .RST_VALUE (1) + ) efx_resetsync_active_high ( + .clk (clk), + .reset_n (reset), + .d_i (1'b0), + .d_o (d_o) + ); + end +endgenerate + +endmodule + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_asyncreg) #( + parameter ASYNC_STAGE = 2, + parameter WIDTH = 4, + parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset + parameter RST_VALUE = 0, + parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance +) ( + input wire clk, + input wire reset_n, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + + + + + + + + + + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect author = "author-a" , author_info = "author-a-details" +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V +o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE +El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY +kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc +/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 +uYJaS5tuGEuFInBHa7oO8g== +`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 +fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa +rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq +PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL +DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w +K3OoKmk3zFeArSsql8B4/Q== +`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 ) +`pragma protect key_block +RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M +GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l +6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI= +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf +RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk +1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw +Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz +eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0 +2HflB1HYKxojQCcZU7qUgQ== +`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx +Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB +rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr +XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD +e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod +B2Zpo2FQ//YDRSAaEa9ksQ== +`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze +vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 +ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 +06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP +fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN +ZoPzFCMjGk5ZmMyIlytNCw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 ) +`pragma protect data_block +0d33xo/2RnBYy8BD6jq1J42m9u/75PA0owNvxlnr0TDOq7sF8XT6xouctVD1XQW2 +Ylwj0urY+dCJZku0aGRpcvb3H/nTlKVdEZOEl4QqB1gNGz/3mz75A3eudu5zgHEr +MaagjyQfDnoIqLWi1r5uTZrlS298IvNcGAJ+xXzpmkFmfG4Tk/5Jf2GPAPVtjREI +01kt8Go4CL1WNxBKcwm0xCiCchxvZ2oEtpERiC+7LUalgTJapIVoLFpvFv98229k +egvgF1KHNj0rAKedSG2Xo58TyA4iZXJJDdtgCxiKgu3Rimjno7l+ekApwmvx8n+p +yHkRGqetWfRhyE4A5q03RzOeSdA6NbCqijB3NPw/p58brAbA35rrjYpGIZXtZ4mU +De3As8VtD64nS2PRuf4/a2lIcDbwMjNTfMpN7iJfVBJ0/48tLHdetx592TLXenkF +GvAZ2yxoyBYzKctj4Keo+19Xp1UjVd3fr2MR3A7nmxLRKDA+upDxQ7ql8+pR7Moh +0b53/4Ri3Mkl+7EC1KXJNt2VbkZmcT7OAFIoPpibmcXS2R6DNVrhSKzfc2+TRM9r +mwRrJy9/R5RR+WGfw1S57Ho3wBPf4belj+Tfd7yhnwOVRXkTMq5M1BiigrGeeQ3q +z/hc1Kg8b/R+g7lnU0pqASnExPQW/DIMfH1RX75U68CAgaBAH22Vcbkoibp8sxyO +g18LefEh48UffnbpCKyv7SQ3LAdj+YO+KvvXHj1eW+CH7GA2lC5vt2be5Ah2/13H +bCeZ+srG6r7wmafy9MNNh8AgjUfZWwMnuJdCIcHTOfAncCd2B0T1Oza4VIkvnSl5 +60V34JXkfrGsNuHxwCF/sRSBbZUSpqig4ZGYHjOHldx2OANZQeUvLES3fwScYY5D +7SpR4ofVxIB/ev/+RXzvC3MNk1N0GT4F1XwokeeQIr/ilRETe/pFvEKttvviZ7uJ +uEVblS2v61DMXEgDavkbA0WdhMChPulwDvZtisWT4hCKRxfuBvNBtz0wH/WgRoX3 +aipWvPJG3G0xvO0u0EQVNdcxE+LZ7vyGF5HWEwKdQYDyhH+yVDeG+M/b08dU2aq4 +sG7dyygyVnzVbk2Lf0nCkGqKkUZUr05Zim0Wcflkhkqy348SOZ3xmEGuYAkzelLV +feQ+0ScsscFL5Cq4ETfFrN8GO8M5kkBN2ELs1MQecPRsgMCh0hcvd8IQrJTybQPW +aqwp9mgnFvS8AJ1ct+XgrAt8zgVnhaZGS9TKa6OWbr0U+SD5m+/pXjNsZA2dni6b +85/PmQeWeAarE/+EaJn/hlP6y3x3R3ItU8Itf6SB50LZ17LAhIRSIYsa7LBBNWOk +ngFHcGBCJnqTJv3hdVqa9cYipZ98XCa8dqrtAM5Rkxwd6H8KxXA+B+PWEz/cQWlb +szi9u5ufmyaJp6PWhklroQkPJEorUtF96X763itgtlAMHfkZglkElUD/gPlkXLtl +yquUmHqPK5D2pJDq0Q0jromE2yrr9fl3OI+eBehd2YBUivGKeaDFkPx7HbzWp9ok +9bT55H8VKYyF1awcjNND+WcXzm2WfvZHBDUJkRm7dnOQRvcX2RxlPRZSzAA3irVn +GFbHXD0RYn/dUR7Vy4kU68P5S5q4bUxD5vmUCN9vDoCivY7WCnlQCHQs3+iFblzP +A636C3dNQMSw0pjDisiZB63VczY8bivFh3cO82inNw5r2IZjvMB9XPhc4FHuIpfR +F7ptW0TUnO1MSDcZvCnjUfVSnHN22l2FM/P5oI1SbG3W+8YmxBvto8jwpES4ohOQ +YSECrvWkLklq68FVTzB7Tvg3JLdSy3TEKBuZE/ot0w/SXusFovOwd4aeiNDAmzwl +fQuCYHuJ0UKLaVNVAO4mw91PJODKCk2NYTr0ghOLovOXiMhUYtXZ+wFchXVkQKDI +B8BXjM7P+blhoOFA6AhRuCX4gZn0dP6m99qnyBJoxf1/FyfJXuklnPll93amUYUx +MzxNNTf7F08tnKQ8pTOk2mfFZnhA2MFn4XQ9FaGvtUrlJI8bvJTWiZFMF0eOJdIw +kzYOXEzKBjIdWW4rtTZmQJb7AOrznUpYdgTAPip/DQx6cg1+tZAVwhZPCjCsb5wa +em5hMtISQKDc92QrlU5O74OXe7641fzFRcKqy9AzwhZl+tmHk1uvpDkpsYiMa7Rk +YrbIjsKQV36PTqYPvxq1EiwYF8PMRf9FG8JZk85EZdM6QEGuehDHqFcZ+SlUb7/e +ji6GgjKxcZwaRREGKSOslcscHS6QNuGCF3iInqNCT4V2l7nboWOefMT2f1kmQOdE +szTFg563SQ8pu7ok3T3XNqUDi5ulvF+XGHDhcQ2hTkZ+xQ8dHFAWZdgzEGMXF2Lw +jU+ZRA2JULfjxOMIU2j9f+aGWmFx2PELMA5K5uOWYUQG2Fn04p1D6u8MEe7fIPeI +k7KH8j/Tumj+kG4t/lCrme6VM9u6A2NGddX1yH1NCejfophy3UWJg9wL/dNxzf6t +vXdm3rGPdZPWFgSIuGlmT03QZmWGPbs8qvkkUVAL37kMJP2r4L+PI00ZxbX8V5jp +GgYN1Rh+NSOwAcUEFCViRhFYC+Gi5eZ6AF6XDSU6qfjGsUKqJ9yrNx0Km6+SjpAK +7Zxblp7vweFVkJ7IESoFeB+vP8JNeoidbBPGEWo+2V08PgfGgjPEAA6pjj8uc0jC +SDFZ0sVrzvc66PZ5FxbI4g+VuXPJgyJsnQ/eHhPVTVTP3/oGMRVktNiJrkJYxAW7 +Sa/EJMjfXX+rMIWG5ssWLT6WfrojlHduEqJ9hJr24RZy514HHF8SMPRBLD6l1wd5 +07U/ChjFdy5qHn5Ce+lanjxnoxgvCsF3lMqoZ7e2bfzXakj7CxahwqRt6yeU0Q+/ +a8tvIJgHfdtOPw/r6HnSrzpdWzTx2e6/MEryHZqpMN63Lhakpjw1L7u3FD/rW40b +LGajigQ7Ql+cZmP7wYl+uSmTFIS6ZgXOc1ibb7yYxJwpeixPHL1iu5ltvriRiTZ6 +DMbbOjNpPuL7ie3AwgmwXwnpnTL6k/Rj2+ma3B7ImODBMkC4SLtTc0ynCcPAFZKA +Xh78wUAgt1T5Nm4XR555DBO7zPHX9rZzMLil4/j0RMDwn1gitmP2PSNFWsrXJG8p +C46kfpdqoM3Yf6HySlhsith6GW41sMF6imUXwahQQRw240HLW3N876LDe6bjTmgN +eIC7y/4NZk7OmpmP8udAEH+UsNfSGtKA8959AoJDr43XsWkOfccNWstu4sTXA5+w +pCALypmBMdholEsrW9DgsIgbgf2pcOAC9+mAjld+yyQ+UNdKRbmtRDHTztGmcVvw +Szip4YUuTM1tPzReucfm38gVFT7eo1qFQg/FJ4VgeYab7ku5OHuwZQmKyzng/t0U +A1lquVENVYQEIotBiOC7jQ1YTkTasGN4xoFgFTyKLFPyk8bl2/anzr1Fx0ieVGCx +2ipzG2JzIQf/FlHXaYrgkWiF817amty+KZp4/dCJtvDXxzOZKnBTVcjHXpqR1Ik+ +tdV+k+21tXZxP0rkG0yi4//2c5UiWGb0UegpemqutykLuT9tGjsqMuc5DaDH/8zk +wLTVfODT+HqN1/ZLqfq9VoAF5m/ujnPNt3wZcsjsAyBD153rW4Q2yVYMat0sFQN6 +XbNAeNBJZlO/aE1PfKBcSDFkJkPqRxlgdiE5B83/w1MP6Z4qwz7LJ8yTYM22xwRo +LIYpKq52yYMhJm42YeQxbBRTx0MyubCb+ompEVBF28Eh0vE98UAZj7t1szSweg99 +Wq6/4kxR2SQj8rFo2wrZe7ngsDmbIrMk2SinS6WmV4Mj+MBbPlmiuwB6NUV04Id1 +9enBBsJIfWt+PZJXyWkOoG/fOVBUxCY+CMCiab0qQ1EVdhggrdI30BgFqcLjfyD6 +/h5AqIzMGWrhWnap8WDEh1Ah6K9f2oCESSXO751sV5eK8jgl63FJMIVsnjVejxrl +Qa7PCXP3BO6Cnv896NBzAsddPq/AYBLHIC6eX3sTtOxTx52NsmJzoyUSJcAoA/QS +leHU1bLA2z+HGfMrkSzsuvXafmqr3B+PHfWdxrYzTxmVhMBPX/FvEU/gfxXGa6kj +niZYGue/Rk+zXL65ENgPwxiz0mm7QyQ6eMBMRovm6MGyIl/8obkOPygH+lhc+bgR +SNWLmxqjR2YABrKsUgCITQ6GK7VmVR3wOOwbZs+YW/0Yj2yzg7ESjaeqI40/OQFD +Ft2IHaURJPk6jl5vRrcCc0J0GCy7CK0BU14n+Nxfl2+CFRe4efoqZry/CmY2+S4M +p9OqgjUzHGSIbNRAXHf44nIAUjWYvijzzLSj9A7WY3TpYxgtqU8Wbf7SbWmw8RJV +pAYDHGmwHa8fL4Y9xEFF/WqmqWSL3g146i41MKWKY7lchvnWtc6yOgk+0geVFOpe +9BLs4TehFA/SueFC99S0Cxcxc0KMWXOKm0I3bI1CAlLje7wUcdI/pki33iqBLJlL +T2vz8ptPqfgAxDW0ZEvEYY/jfB+jCO0MKT7XK/LZNYSuEke3Y3CeuwZ/5IWkDcwy +7BArmDy7Hpw88le9ODL94mS1fUB8jsBaazeiXniZPNZjBkugt/ZAf4XYuoaGVPAM +DnRd8GW5eiDHFCEB42lpg9n7Ak8cXsSSlODCHeay2VtcQP1DEgwWdI5XdXE879gI +8lLU9bH2MfsxI2mNWCMv5immaioZJDorIVzyMGvIn3OcgqmhTU1owINUJf+Hm8Q7 +JfJq4m6t0J5eoKQH57uSGFkWRZ3dtp5QL3d5bBOMmorXUBzdrLt8wurvNke29bHD +UQdmANjayV8drYWAccZdPWyi9jNC/K31BTDI6RCpZdV3Wr5scOZdXWrl961jirm1 +g/2MGKxriuH2F4MRIh2vp3uS8PLbj4cHJv+5+LtLgs0lpdEMYAvJKDACRg68tDhY +XsF9lhHpcF5+tANOawRtnSvy/rlLn+A3wi7v8tnTZcLkocJ51c+nK5/Ij0YgUrA0 +eLrKNlJM78stswPWkvpBlAJ+G3D4Cw6P3XcJWrLyV3u79jf9PRJZmxMU/COGTmgQ +PJdXp90O3u2Pjdwhp4VdtBK2d/jTpk59j8xbQBavf5flZ+PzoLpd8NSt6GdPVJ5r +uVWvNy14pJXUsn+Tgxj+9Wp3vm5mofWtJAkEgr/Rfp7AVLLShJSd6vsbT7F2+TS/ +OMDv0XH92v1G4tqJ0rbxS1TnxX61+1sfjKlfIQdFR9gxLy71Tb705LQHBAw8vmSx +X6Uv+HbtPaEqRCF+pdvGsLNI2Seo6INA/mXqNpd6VPhfQHtp3bgV+Hxnlcc9lCiI +bCZq6KG4a6sVQHIZ3pZo7PQtoAo22niHvgZFoOVnBv+bu+blmvSV6gxCPoV8rwOe +/WD7YikHE7WVSq1SHtTIcbPv+K+1NKqZIiSCS2qDfJLgI7vH4zjIqibDhzGZTeKV +Km234SSlJ1OL4WQ5FtsxjednjUIAKqVe1auDiTzAKY28dwUkwGN/XXQ+EjrmxQuL +qIAT3WP49EeM+CQCp3D6Vxzm7Picq+RtwtbAXnnSQtvPcaSprODI089a0iR46Pp/ +4DLMUOLS+01HozXF1589YdqYep05No/Fp4eP2RdQxicYxK8d/OcvG7E8F1URVmAa +XdZxVa9caM3xYMWDZaiaOo6IZ+YM5VeZ4KxUblS1L1IlOnGOOZ3AiaLsHOh55ryc +Ei7EaFpheCmlTJyxUg8TdA== +`pragma protect end_protected + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/fpga/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_define.svh b/fpga/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_define.svh new file mode 100644 index 0000000..90fdc68 --- /dev/null +++ b/fpga/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_define.svh @@ -0,0 +1,66 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 8.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 2; +localparam DATA_WIDTH = 13; +localparam MODE = "STANDARD"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 128; +localparam PROGRAMMABLE_FULL = "NONE"; +localparam PROG_FULL_NEGATE = 128; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 2; +localparam PROG_EMPTY_NEGATE = 3; +localparam OPTIONAL_FLAGS = 0; +localparam PIPELINE_REG = 1; +localparam DEPTH = 4096; +localparam FAMILY = "TITANIUM"; +localparam ASYM_WIDTH_RATIO = 4; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; +localparam RAM_STYLE = "block_ram"; +localparam OVERFLOW_PROTECT = 0; +localparam UNDERFLOW_PROTECT = 0; diff --git a/fpga/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.sv b/fpga/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.sv new file mode 100644 index 0000000..1305620 --- /dev/null +++ b/fpga/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.sv @@ -0,0 +1,60 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 8.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +gTSE_core_fifo_data u_gTSE_core_fifo_data +( + .full_o ( full_o ), + .empty_o ( empty_o ), + .wr_clk_i ( wr_clk_i ), + .rd_clk_i ( rd_clk_i ), + .wr_en_i ( wr_en_i ), + .rd_en_i ( rd_en_i ), + .wdata ( wdata ), + .rst_busy ( rst_busy ), + .rdata ( rdata ), + .a_rst_i ( a_rst_i ), + .wr_datacount_o ( wr_datacount_o ), + .rd_datacount_o ( rd_datacount_o ) +); diff --git a/fpga/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.vhd b/fpga/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.vhd new file mode 100644 index 0000000..513297d --- /dev/null +++ b/fpga/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.vhd @@ -0,0 +1,75 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +component gTSE_core_fifo_data is +port ( + full_o : out std_logic; + empty_o : out std_logic; + wr_clk_i : in std_logic; + rd_clk_i : in std_logic; + wr_en_i : in std_logic; + rd_en_i : in std_logic; + wdata : in std_logic_vector(12 downto 0); + rst_busy : out std_logic; + rdata : out std_logic_vector(12 downto 0); + a_rst_i : in std_logic; + wr_datacount_o : out std_logic_vector(12 downto 0); + rd_datacount_o : out std_logic_vector(12 downto 0) +); +end component gTSE_core_fifo_data; + +---------------------- End COMPONENT Declaration ------------ +------------- Begin Cut here for INSTANTIATION Template ----- +u_gTSE_core_fifo_data : gTSE_core_fifo_data +port map ( + full_o => full_o, + empty_o => empty_o, + wr_clk_i => wr_clk_i, + rd_clk_i => rd_clk_i, + wr_en_i => wr_en_i, + rd_en_i => rd_en_i, + wdata => wdata, + rst_busy => rst_busy, + rdata => rdata, + a_rst_i => a_rst_i, + wr_datacount_o => wr_datacount_o, + rd_datacount_o => rd_datacount_o +); + +------------------------ End INSTANTIATION Template --------- diff --git a/fpga/ip/gTSE_core_fifo_data/ipm/component.pickle b/fpga/ip/gTSE_core_fifo_data/ipm/component.pickle new file mode 100644 index 0000000..c2645c9 Binary files /dev/null and b/fpga/ip/gTSE_core_fifo_data/ipm/component.pickle differ diff --git a/fpga/ip/gTSE_core_fifo_data/ipm/graph.pickle b/fpga/ip/gTSE_core_fifo_data/ipm/graph.pickle new file mode 100644 index 0000000..c15a035 Binary files /dev/null and b/fpga/ip/gTSE_core_fifo_data/ipm/graph.pickle differ diff --git a/fpga/ip/gTSE_core_fifo_data/settings.json b/fpga/ip/gTSE_core_fifo_data/settings.json new file mode 100644 index 0000000..62ba683 --- /dev/null +++ b/fpga/ip/gTSE_core_fifo_data/settings.json @@ -0,0 +1,75 @@ +{ + "args": [ + "-o", + "gTSE_core_fifo_data", + "--base_path", + "/projects/SSE/llching/repo/efx_IP_master/efx_IP/efx_hard_soc/fpga/Ti375C529_devkit/ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "memory", + "name": "efx_fifo_top", + "version": "8.1" + } + ], + "conf": { + "SYNC_CLK": "0", + "SYNC_STAGE": "2", + "DEPTH_2": "12", + "DATA_WIDTH": "13", + "MODE": "\"STANDARD\"", + "OUTPUT_REG": "0", + "PROG_FULL_ASSERT": "128", + "PROGRAMMABLE_FULL": "\"NONE\"", + "PFN_INTERNAL": "127", + "PEA_INTERNAL": "2", + "PEN_INTERNAL": "3", + "PROGRAMMABLE_EMPTY": "\"NONE\"", + "OPTIONAL_FLAGS": "0", + "PIPELINE_REG": "1", + "ASYM_WIDTH_RATIO": "4", + "BYPASS_RESET_SYNC": "0", + "ENDIANESS": "0", + "RAM_STYLE": "\"block_ram\"", + "OVERFLOW_PROTECT": "0", + "UNDERFLOW_PROTECT": "0" + }, + "output": { + "external_source_source": [ + "gTSE_core_fifo_data/gTSE_core_fifo_data.sv", + "gTSE_core_fifo_data/gTSE_core_fifo_data_define.svh", + "gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.sv", + "gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.vhd" + ], + "external_example_example": [ + "gTSE_core_fifo_data/T20F256_devkit/fifo_demo.peri.xml", + "gTSE_core_fifo_data/T20F256_devkit/fifo_demo.xml", + "gTSE_core_fifo_data/T20F256_devkit/fifo_demo_top.v", + "gTSE_core_fifo_data/T20F256_devkit/fifo_demo_T20.sdc", + "gTSE_core_fifo_data/T20F256_devkit/efx_symmetric_width_fifo_top.sv", + "gTSE_core_fifo_data/T20F256_devkit/gTSE_core_fifo_data.sv", + "gTSE_core_fifo_data/T20F256_devkit/gTSE_core_fifo_data_define.svh" + ], + "external_example_2": [ + "gTSE_core_fifo_data/Ti60F225_devkit/fifo_demo.peri.xml", + "gTSE_core_fifo_data/Ti60F225_devkit/fifo_demo.xml", + "gTSE_core_fifo_data/Ti60F225_devkit/fifo_demo_top.v", + "gTSE_core_fifo_data/Ti60F225_devkit/fifo_demo_Ti60.sdc", + "gTSE_core_fifo_data/Ti60F225_devkit/efx_symmetric_width_fifo_top.sv", + "gTSE_core_fifo_data/Ti60F225_devkit/gTSE_core_fifo_data.sv", + "gTSE_core_fifo_data/Ti60F225_devkit/gTSE_core_fifo_data_define.svh" + ], + "external_testbench_testbench": [ + "gTSE_core_fifo_data/Testbench/fifo_tb.sv", + "gTSE_core_fifo_data/Testbench/xrun.sh", + "gTSE_core_fifo_data/Testbench/msim.sh", + "gTSE_core_fifo_data/Testbench/flist", + "gTSE_core_fifo_data/Testbench/modelsim.do", + "gTSE_core_fifo_data/Testbench/gTSE_core_fifo_data.sv", + "gTSE_core_fifo_data/Testbench/gTSE_core_fifo_data_define.svh" + ] + }, + "ooc_synthesis": {}, + "sw_version": "2025.2.272", + "generated_date": "2025-10-16T09:35:27.104449+00:00" +} \ No newline at end of file diff --git a/fpga/source/MacRxCheckSumChecker.v b/fpga/source/MacRxCheckSumChecker.v new file mode 100644 index 0000000..d13420d --- /dev/null +++ b/fpga/source/MacRxCheckSumChecker.v @@ -0,0 +1,460 @@ +`timescale 1ns/1ps +`define IP_MODULE_NAME(name) name +module `IP_MODULE_NAME(MacRxCheckSumChecker) ( + input wire io_input_valid, + output reg io_input_ready, + input wire io_input_payload_last, + input wire io_input_payload_fragment_error, + input wire [7:0] io_input_payload_fragment_data, + output reg io_output_valid, + input wire io_output_ready, + output reg io_output_payload_last, + output reg io_output_payload_fragment_error, + output reg [7:0] io_output_payload_fragment_data, + input wire clk, + input wire reset +); +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +hitigEdAF1oYulO+rzgvZGPZ/Fd2rMxle3YAk5YXRsXciII9biXM11yT9um6jJ8+ +3kzVSR81TQjw7cIj5GSOo/ZUXLyM5C31H4zOLXmkRszAL1LLpcHPwqj/0zmRQxsk +Crgj5D989eHlroC0Prpz3dn6NdNSKLXz0GqV6d9E9r24bdIdCEg7IOxSJrlw18oq +t6GUxKyKSqV8FcH3XaacJ6RYAf6AeAQgEC04VhojxONJQnPlp2dcTeMRl6NhnRqs +sxE1pShW8ERncX+VZUigeFks09GmTIJcmh3dk//EuICiBGVdKtEDU3w0bxIs8mkX +fv849ddnaoUeK2vjnaRMXg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 20032 ) +`pragma protect data_block +rCwwbt0+cyBbGJvD3UcIfPB8PO9JeIfGCIrZ80ZeBp71sOWySAsRKDi/6hP1ZYPG +EZhL/2cc6+0Zb3hMl6Z7/PADwMV7Kwbd0MTfq9LGUupuU5kHnYl240MwTwe3X3v+ +VbiK/mU/HKeVWh8IPvoGri6nCkEwQ3F5uMNdt+5hy4AI5PWbOTy+BpjJS7q2UMsk +rfGa7X/R6da9gXlEZiG/KYDnQP78Gg5nPwRAl7HNOP9dXfFoFjvIrJr02D+yIYhe +Q4SeOeFDoSDUOg8Y2XSYEQpT8Y+jS39V0vOS02OS6ay3Fs1qIsNoI/lb3YjzwCsZ +x7ShWL4wVoBa60xVXwgimM2yPNQrity/qzIuP2rzLvE82kh4abl2s86HdcP6En6B +86QzOBudvzzPytAESeQkv7pkd+n19y+sfbCUXUirdfGoEYa1h+0zBYiw6/YD5HdK +wkVPB/Hk022MocvKkKCVdDM9nAj0jy9VUMd/5N6Nn7/Qyt48R1QaG0gDl1LDEW9/ +1RFjf6SnnnKeC1KSWCVN7eXOh6+xQRF0R/X25UGNJnLaJZYsr9r+PFkhBQNq9jAu +9U/ytmbHjyQfbocmAHnjU13hR+U0LhgBrP/OcP0ea6Dm7vwoG/kQItM4qqRghMnZ +oV200CP3cLH3iKkOdtGNXoafaFEmwKY/fp3Yyjd50sjW7f1Kb1rWHBKdKJXm4ynk +83jsmQUCq98UnQFOMEC1h7FSiwnrh1pdC54DYK0mcYRpzlnBKmZhgf2qpKjOLnkB +C9TKTF5vnZzOz/5peD1an32c8EKqjcvkb0peNhnSdUgnQpw48yMYZhEkjXZf5Oq8 ++gAbvI5UyEN4fXhvf8oAPuqCeDlr25ij175KNawPnptj4Mnf9wOjTlt9As4ikC1w +AZu+S6mlMVATYdtsUQEhPLUe5W8KjdeO/PVf9UJ4V06a6bJwqyJfXnO0c7oOjNkB +VQtOJt4OTUT+Q8u8fDNqj0/jjKu62VkcowdVZP1eo3OgVajHvJnQlkjsPI/Uzvp/ +CmnqNy7+pklXeppCG4ty8N47kTsPkPR1qYUzZfQTVjZK7TH02RXXV9mZwm06LqtV +cQ7qkxLsf++Wkbu/paSRlSLIWB7JKREldmCGuhMLHhQCmda5mP1cYfjjJZLmkMI+ +ZUZ78Dil5JKpaZa+PAch8VbcHQfbYWJB93cuTfVt80ooFEt8SbSRj6S+MAhq0UjV +8kNRAHHHSAMYs0x1c6F0x32cR8EkKjXl/MZK/MmQazRpiOnQ/t6SamO6kUyx1g6l +DWMTRdy0/r7NpjrsYMmlHqgjLszqXOFfYWVUNtmLNOAtf0DXG8xHg8t3PSR5NgZP +FvgqD5oAErNyYycAal4SPDe9YqsscCPT/4yJQMOanqD6S75/JdjKw9CCRIyKufjx +CrosQxGmlJn3GKtBZqdo98wMRJEGXHDFdrOU25ncTVHPecH/k39nva88yWPSeYRw +JlR7fMyEsfWWOt24eSb53LbzMxLdRFsmAEOGWsyDBN04h+zSTxZQdmKPhSQCREad +Qo6JP0ejAcsac/7ayhw7eeGXcPVMVzvLxh9z665ZwWqjwNjCVVumbHAgI5/lBvUK +khaYWpqAR9wxgfwHB2Raa2SJLcxvJYTEEF39A9U07mmhBwqf2/LIJXfM06PQaVW9 +VdHk3PP9BaponhBdxz4ZHv3P36suPrZ48dCvkhf2QjwlwLJtUD5dcShiptHgbeAV +iQedne0ckbPOgdiBHctbVOK33s06SBlZv+hrfquxn1QnYTdTpcz5nHdc3xHQGjbo +PzM3Uqj0yHAdrsXz2NtI2qP5Oj0qlNAihukPqko9hvREL7oehlYC6l2s1QJPVQpB ++jf+YjpexmT1Mj7N1X6qWkcm3wvzklF81/U2dOwtp5+ZVKl5FEZ97wVCkXwaNrTF +kfmvB6RqQXUxBmAmViAkVtdrRHXylj0BF+G7VoE4h6SHZnIepMvulRp7VBrDDZ9p +/XgkhVFSBPQAze0/SskFn7IxOSYmTQfsEQX2D4N/2Pb9bm6NUCHfDfTY8MfyOSiS +4CK/n1ZNXhRWYdzzg4z64XcS9slfca7L2f4UkRNQWKRvuyQ7kvi04MbXl2zoZNwT +8Mc1961n0uBVxR2uCAntaqmXtDdXH4OfbpMjqYte3XoEqH9JMHC3HApWpS7yt33Y +MNN4aWcC5PnG3p+aReZ2PZcUWeatPQp7BEiU/E7zCRTiFNJGaOABaNbjtHNW6pN/ +qfwd23lGCY0exM63gmGfdbEIYfpHvUDVmsagMI6WSrGqS8LE45oii/vsf19mLpgq +KhC3vRXFGrsvAcdNLzFM4jd0BbQwoeVouZwc93rpuj2CTIPn+I7hUqTOWgdYBGS4 +TBMjv+o26um4eMi2pB/RCO6A4YlwM17DmIAUBNe/spZdWHhGKQ+vRVWAFkNtmNbg +YpEcmHOA3evpmTzIv3wmBATcghhAHgLMWT/A3OOWhfnggEZcfK9mO1qdxh9V0qNz +dX+VNzs68lgfo1XJHuNoLx1uaiODhBhqSK+bJ8XveTtaapNxCppX0R91y+HIuw2U +CsksgHpzfxO4cP1HTfEWf8DtxXhXkA7DwwsUdog3Q9bSjEn24UkUrjDyedAGYzQD +HYhmr3bUhDeCKPjV4lTuTi52b34kCaNyXW3zaS+PIHqR7kNLdHWg2Cc3DALQDEGd +90wzEMGa0e1HZQ+34W4ynJJrxEzzcDUZuY3lcM/B8nmAh5NgDBt2n/3n6cDou/T3 +hitn7dpoHgUnMfwrVJbukUmuVnaHhc7Mj/pf0gcYTsoLMSkswsoVT+m/N7Pdk7uW +2AF3xwKfGDWoxi1CtFQ8sFFj6ub7WA2ZMxHvimCS9BtOHOi6NcBOOr3zzmjyr3K9 +09Y6Jcb66imyGl2jORIjsnIp1YKx4WcOuZ/ZLtnRPabXxeKYCU3uEnNCdh+7PSlY ++sIIxEJivJrQ008AzCJhaFivpBLtxVKezPOlFp3zh1xwApLZWK3kw3fZjiEeiqvq +/KIQi5YaeeVInMgB/671juc3AmVN90yU7/hNUqcHlkzWJx1y0RbuyoIRO4WkI4hm +f/bP1XltseWPayIsb3J0Dad4Fb/sdps+U3GcwyVexO7hOG3UWnntkMX2U7o+6VWE +lTWy7dXXtLYZh3+6Y5V2kplxc97dMXbueRQ0oqSKqyK736wB7KoQkIlWFs58eZzM +J9wsGOgORJDk165BZWKC/Z30z+3XyhuS84xude5uzSCNNYexoJyncrHAzvIntp/O +7ghQFTnxNZlYKli0a6hyBscbx41L5tA7hatH4S0Rv0u42fqrMFybRrTescJmYgNs +eCPQ+GuGkAu1RoPhRlTANOZ9FSsELwpN2HkQf9EURUXTAPMlVHaenFb8Hyc3hDEE ++LC2r4HiQFLmJY/9KW0lTdDHcj4p9yuiPDHBaeB0Y25BkZmseFXTnY5jupnTKb14 +5ruKXr2/VVeOgvoRTWNalEWZFwgazN6cDbo1d0fVvkW7bD+CY6ro813HlX1pBVSk +TTqhqOmDK9wm9NADXL/ie037ppZ1VkGLAujos/9ZDeDJnlDKzNiO+GVwM0t7qF0Y +m3EWqWSVTEZ7hsEGSe5rU4YWcYLEw4/Fx97PtG4KvKiTw+Pe3Q7+hqQ86T7zZBGg +u1AND3wv/rapCd+BOCxQs1JiplkyR660WpLU3UNBmxGbyJx/q+v69RZCALaa3M16 +hYvri/mdmeUmpZ4wNZjcU2yDhsoldMyhfl/22nrfkdoApdDQWr/KZJqTBdhvYPPu +0Cq7LzOBQz3wX38jazEt1Pbt4T8dp0713UdHlFYWIDzUwk4wf37fRknWP2RD17sg +820x8RXzFs6bl7fSYZB3p4Xm9h1xRQJ3zndvfhU/qjd2lQesG4tSNyJu5l3fVjIh +zwsWTs8rBds8lL9qgrC1H4zmsxPN0wynWtG9pX3Svsl30jgggl1TUA3A117m5cyB +ZuSvX/v3+VaibK6Lyb70MFx1d3s5fKbWuYrBwG+2kDjyWoYR8Eqkf/AQXFzEu+jV +MCFBliPI51+xmd7FMp2m2z78m5H05fOyTW0Ci1hvYF/qnZA/BFziKCdTcL2f5qmy +Y68k98LjqWi/XZzdfa94exMPLsKcycCd6dP7T9UiVYXQwiaj7CF5wpLwNsDEKVLJ +EfqHN3nxCUGgcNwAnXaN7oQlyC8ly+T7jKUw9AYkYY+8LZ92AHVoDU3DnKkGGMBW +aT1jVe4DvEH3dXb5riRykb/SsYIzKztIlJp+FCh+CNuGbiQ56dxo/aDy1qE/cPzP +KW1t6T+GMnq0+NWuakfBb+mL30sVaJDHjFhrpZpwzua8I429VPuOTIo2D4J7+dye +fQx55pr9ARa6K4FocsgRkMNHUVZTTlnwX6X9icJ2RgSXnJrAef2GuE5LwhyvcH3H +fBWXQRFmV0Z0XpnitDzMCAAQ+6Yo8WBWrOKCruy1DkIVY20VKhgi3C5sdZfn+NCh +tWZsfhvEJOVBv/cobprvWYMXSp3h/qmRFj4Xa6TbX0CJJJjUsGW7Drt/jcjvyYVx +/0w/LvZPWEll5I3QNdh344B46ptJhdjmNZtMIusrqvb0rfzhwplvA9KrBMxR00Ui +wkbQgvCUcn/9sifoxuFp+9PITwGI+TX+4LSXebC7QyGU3pWl3TeBfBwsA035KXWR +lfRciU7v9GJkE+mtq7hTUR/bx6HInLEDwWTmXXX77RQWnv0smBMN/i1A0xDy1EeX +7kXpxsVfrSVWDASJCkawI1GGklnPPXRUEUajG9fYSJCq830IxBqUfgkVykhY9RA3 +dk85asUfyPGtbSZpTCvIllv3f/maMC166ewXPaozuk1n43JAa+M2tGZ2VTNLP+RK +YMy9fawljxZMvIFwOBXlqCBvzKWPdyKmav409tI3nOIzdi1pBdeEYTms/yLnfFZK +0zaYzuwoWRuRiPW763rPfHu4WKyy7UDfjsu1I90ZxeRtkw0F9P8hTcnb0Pt6ir66 +SsZyzOfEEOe6IIL2Abw36zQQla+2nikRXSiUWjizwqI2HX17NssczE4o85cBzob0 +XcJU7nXbkSakiFf3uyDD1FO53NPCXWNSq3iiSwsXxVVDV/81nrFsBcFdYLPowxXY +UWVa+5ZGm8cbOCujkKa5IRN9sBbqnixU6UslWBK97J5EVeTdq62zZicu6LssJOKF +ePGbZ7aO+Bji3mokDNfJcUdjq/MqjZpNVDvZ9Q0oe0Ijv6LidTY3U96GwrZzhjIA +PTFD4fO4gAOHG8tqoRVOkjPrAYdUQeYFFfCV83RK1yefJZ7xpYn2hP9H+UynUwyK +SmCn5nM5m5W1rRjbbhpjkmXvvLjvLMfgMs6wfsqjt+OdWxwQ/GN2urwNklDeh+Pf +TYU/q5ICTMjyaVkvz5OdoBUmMa7SsSvBCWuUzdZsBz1CNMP3HWSyiixacxlGzsqO +pXeNCxrMeVgm5GGuuDaIOFHl8F3E4q/8U0JvsHlLLZAONv+t1tpEMCNSxDqa9FBJ +AFEHUDMAlKY6PjbIeUErMT0JdleqmSz8tG8ZHZcQUIfSLbRO7zPkFNVnq7mLM4eX +zGRoASp1lYKQJiRN7s78chBmGEO4YEoWI6QfQi8pIeGGLVrUX/K8JMdj3arFd21l +c2s7gr75rAst+eXcvs3frVXa8w/glWiiT8d8N76RsrVwBuanHCIzHZ8qtLsLQ24g +x7WbQqeEil8VwdUAzAl9t2/LxEQl9h9JvirEFQbfhbuVCeGuTwfvsYTotpyU6mO7 +WKrrR0a0PCoknA+EF3pzyHW6R3KmnTDkQA3RCGbCDnr76zndZlEPS85QisNw/V9N +M7assfvj5I4Ezm1reMRlA2b8Y1Vi2OkPeRKF7tHsKDJ1m/dMaiOIpqMX5UFdtZz9 +aB0ojEk7JkXEzy+X7868Hln6KRPul3loaoo7NiwO51CvUrov6w6FzAeycPREN3Ve +rr2tTGw+p6sYIP1CDrljh/gFNHtsMtFJY6tyKHNLp6urFmk8hEmaQhOWBKXTnm/i +b2uY0sVbrAjmfqxG0XkCF+wQuyQYVaflZuT5UFK/JrknNLEtGIUJfopazbMAlrM9 +RqPUQYfrkpanfs8O7B2pK+D44Uv9dDtcuzD3p9kXmoX1kV1tanju6QfRvw8jlXBF +t9TPMQynPPuXAeocbwasgKXY3qadccLtji7mYuQL/4aVeQEsFt++qd9eujon+sC6 +ApeWqVFszLO7uEfjobCe7yqxIvbOJluqhrcH6d2g6I1mLcf/BuewEmjdZqd5C0lZ +N2nmrPyMBYMy594MCriMb6FCRwfD4DHDqQ5yP1wk2TRbjwf5sxbvi6o1ATMxBU8Z +RDRKwUheSyupkgiDTDtDa9ub2EhYWs4NWBzyfdBhDvg+fFljWSZXSL5iCPdIGZiJ +AvTtMJc9H9litgFBddEUH53upy087YEzzJRdBbLPrOaFuaCXqncJ6sG57njIizk2 +jCUxMbq0VPRTEt/N70Wzo6tOo/aHch9ncRgrvTBEu+eQ2FhePtjBODxKrqH4f22J +Ss/Zd3YbBWEY2BzXvDTZxPNzVTr1WJm+cP/1sqEOgHDVs7gdDVWL6kwOyvv1dlJX +UCZvznqmI4kMCmXUpWRWo3SS+bq0W2bO2FTwuD53YrlBMxU+fY8OXeyDn1kLDeZ7 +tanw9RHu5znypy3Ya2g1PvaZ7U8shQAKvVDkITw4RQoYrZb2Nv5Cb33Ky42wRG0V +1JDeRD6FJ0smfk8h1PuudUMxYiCW8naOepGG/4FzGZ2Z2+K4It8lr6F1H/wA4xcE +s+IkE4vX7KQR1LhFORFD08sje1TYu8QOLlKhvXlS5vmG+IXcGwJA8bEKjzK5SH7g +723PyfWCwk92xeZX1IrKS+yuBYiTZHVnlnrGEeHUk8MGGc8yzEFMRDoMjSdAyNal +ye71LK1H1TPhmWYrFrDi9u94jm+qkRyWRUwMBowSIGy2atU1nICcos/U3FAP9cdF +rJ///jwIQbWAhcSm4ZOr3WDlprmCuzMmp4P2DRjYMjIzxfYk61WlsW2OcH9lI+FW +MCqruOnFM6p110JoMQU31a/FjgPcVtHFZZKfajME20wCPqJ44OXpzVJmcVJ7uoOo +ZEcC1gc2O5IgFwTf+cq/MHf2XUQ6htlAs2mH37QWc4QL5Sh1FjvWh8yZKR4ABsHx +6AadEnMrkQ+4M1X5DPSDy2l5Y9OJVW97Zsjgc9S/KPQGlSy4tfnwlkmhb3f9n++o +aHPra/dIhbx+w8bs9mlceVdqr1U0PpiW/sYHw2KtxTZdcky9UhwV9ff3bqGT7tNw +K05HPPHUbc77I2odw2Qx/l0wZH3r0OOCEdNJF+EEcNI6Rdb/uIRfwsCthpjQkx1E +83wAyACLuDNmTPEGdxgwrVRLFr4s8D9dXnv+ZxFzw625pYzzzJQQBMCpCuRMTKF1 +g5B8VtPTDWmVWNXJFL+zvyRTnxptjbU8tDBzeh86in1m10qyzlJkMgfBDni0alXY +Gdnjq5o3ci6xtQH62LhuncU5glP46D79Ia68d/KeVq4x6tU8BYGtVipYJ2GjUkZT +iCCCSuygyO1cQ90dh0t4Ii8zUnyfBSLt4LxAKFmveX+bUzzgD81cA6UV8I+hgXjx +uMUwYfYFHqQ1tDeagTkVLh2t7pvZbh/R7mblcIFjuLba7wtYvO+6UD7qMe7U4nWj +MatBpFkxTs8purD54VIgU9jg4eyuo7iiMLn+j5I3wb+z8Z0zvRM8ATlSXC6JwOmw +abafCaj0LHHYUVc4GhcEccdZeeDypNURQ7+bL8jfOGR5jYhg8x2SnRwKNOR+ynFh +rxadOcuxU8Ds4MQeLpf9RD1AVgossAuCmgwpKBA8yAaHH9lqpftrBuUM0sEHbqMM +NU6rdQ3GEVQBeHTuRy43u/7BaDtf2Qa/kOBdKVQ3GJTjT1rzW0/27w7Ibdbmqreq +baOp6cMtoO14mjQkDv6UrgbVlaWduFWrMF4YxYWNQ4lXdm5hKXqQNjFQk6g+xX8L +cMdQuJa/StQi2bf4g4uZtn80dUMtkl4s4gbyWxkOzpuakQdzNd+zR8TCZUDwXkve +63wALzTlvhv2MocL9Kg/5BJydCBDz0uPn5/JDXo8AKYXglGYVzYhs2c8xNPmCmUq +K1gzL7QKXeWH/5EYUH9YwOL9vv3Um+PwTbXZxgitypGmzg28+NgC6GeN5Zziolis ++h5/gjjf5ScQZ4gUVX/TsbsClldrdu40XASJlWm4Ax0YO6QCmX+ReSPnSr2xF51B +QJTiNho6O3zZExWxQwRI6A3DxJkG7gEKqjKC6zGonPVp8y0sG2puLjIMVVc6atZs +4ImAxKr3VcCitDQHFj7RXEAHIMvgeoTf7HPfw9xpgzeESx1KY2J2UjZS/dSSkG9B +8Sn38w5yv1otDtg2Vf/XrtSWuookPozzV7s3XxoPUHxuunVra0mG3DnRKrTurfET +BNuPaHzXgow7FOTYph7iRQMgu6N26WySpLd1wjvwworzRh6DeyoaG55fqScH4ULA +/17FBxaG4yVcFlyAw5r+06Y3oP2z9yR8+UenST6NZAxr9jKiUItFf7jmlJfcTA7N +FvZKY4S5Q5SoAat4Owke4x4zvckk6yW9Whqqmipp3f+IwA5CqlVb0BEL0GB82KpE +yAqpUoOrnYU5Wqm2DZu6N0yNzumnzV/qKTI6DEhzfTrzv5tkqkPeMh2Oy39gBIXI +4qDC8/zWPNIC4RpPbjphusVI4zfzsGwhKLhoSMP+HfKwUdmMie2GkFiqwYCHJj8C +umt3ZTbML34yo/Sc1OCu5ShMWNLH7XqBF6r+3HpakzyXvll48kc0WEafgLPclxI3 +q0RXpu+ZXbRTphaXxS4DmoQvu7wQBpwL135S8DD40Ua/Lu3DbSpPzm/l2Jd/fcke +n7AKWX+m0gWkQNvi/rilLRCj1AmdVQWH7roiY77ApQv4JzjFXeD4b9bmXqKNbv7l +Fi2bQ/rVJk9s70vKnr4pyBNbT56QRwTeS2kKdu7ktJv/zIq2LvQqFgAuSXqC0j9Q +Uhg8/rdYldhCxdn9ooOGlYr6Qm7olC0O7t8UP2cCL55xOdCuo6laHR0+fbFhXl4Y +PAk3RdgfID4eYVIvhvkyeua8mtGTTl1XOe5vadNtnPpNUnRh8id98abfqGnYKI29 +ibQZhnYPhRxNNgSHNYw4NLOdiW1XFWWfewBJvj/ZEhx/viugb3gSE8tsGvae9BVC +xm7fnJHmXTeDo9tyzNSZsGDrJSL7fq2CLxNp0NyilrZAhdykarnm4aruGJInewWb +NH0FHjRylpxrVzAPdXz0pUwxXSZpuXuGHcXyYOgrfIINrmC3nlw2dnTODuelweGN +UpG1t8b7rBOYH5j0nKOQzYzPrS2DHgI8eA0pJgDkuvHcLiROPodyi4EjO+N2Hx6F +nDuu4sBYyiUnq61SV9KfIjxTXN3rSN0IduTqDtU2VB8XY/dla96AJmuqQnt+S4oE +x08NSWJ1FcyrIfA82sZ+CGnB/Df8yFbj1nRbVvHNf3ssPZ2y5h0sy5fPi4JF4nT9 +TPXQfgEITSEjaowB+FiSRHnphVQ7ppEB5Iuz/LyUkGRi6xxSVcFZkcRdMcjrR9dy +fnG2EEpWdjTx8qfa9YfEtcEoskOyQjNTCqKgSQxhbWL9OzwwHUmJKU1755YSH2Kb +Lb5VCVgTjyM1sOFK8kRjGAZhCXevnXC39oMothivNWeK6N1Pq4KmK95O/21MEyRc +PeAfANQXsqaR4Vf+1Q2H16OcT4pD7JIsHsKiXOuRbfJAmZ9UVSXbPuQ97PBdXA3R +QTdJDZceRIqdQsXUg9VoOMKlae8gvDza3CLoS0Ibjz6+29NOT2mwnlm0uR+7iF18 +6rmqFeRAHkk7gdGcAZT9sGdqajuLCQ42lqBKyFo5ospnvTauxnG2BKJTuqXN9736 +fENjtVs3wS4exrrTCmyWbrgY03jciwTYL8h4EFXvIXl30n+zJlR5CS2pa7x2IC8E +AJzDBkpor1qrUizoxljdzdTY0906/GJRGLlvxdYfaKXFsy9bxY3ixm1D9Ippg2bH +TuScRQs8pgOMdvrlA1ON3Yz8bUxAg4PEaLTTmAUbAMlpqPkRJfAy10ynypS2f53W +W/OuJnJJcbQJ7SApFvCo1D1IYTmJKSVLnhU4FLQD+JhRncBwHq1xk3s8dGrNL8QT +cQ5xpQnoY1tourHS+1AUyR/34Xkh0fPSxzj5A/7nNn3xqiMZNI1qL5s19QiNdKmr +6yOCfQbMQiN5GyY0u37hPj+xHczCVhr0bnfXD5UhqgaMzYPJqsYj8ARljauC28tL +z+H+U8BR5wppRdajU6/T+O8Xu8mtZwIlMVKYou4ncv1mh7EUPaBqCph3qllR6q7T +3egCZru+FKFZbOHsSbGswXCIS3ExUCoUoOKx4H7JzhjAG0XmABznyDQGL+GUXFAW +sDUCG92Dr7MHKMQ/lwCYFq17p3aC9QPQaVrUUoHPZdL1ocpa7gqIz8E24hNuTaXP +8TA6nZBfXUWyhRH1JCcSkUugKLnYT+12Ah6ViztdWb5BtghmJLJ74jw0C9dmgq/I +CZYvW1SeC2bKyCJvkxPGjdjOlEjl76penqUmAYLVbyoFgkqQoReqyjCYjn+Wirbo +m5TK6qxhWme9IsWhMrH2ZFkLs6EqewdjO6WLiQND2l3p70MBem0O1RR2cxV7tiWj +l0wgqThv5Hc+yCyejA1splBPLpnknXH8OWbgIAMq3FbyQDTX8Y7LV1eoKMyl5icg +t9V7EsXfQnzJatvN7oIXmwN2y9MgGmRUVES9+KZZWKqkkTr76iZUGA4/A50+oHpi +07Y73j9ihb7NKZvc+FP+rlLHD0K4VrAKFHeSopbjDauxxtybbMZbjfU7bV/deDaM +EtLnS/UOt8/QIJB+ChR+sxI2h2ACEE3O+XKENX9MdsLmGUJSONqudTOosaKVNFNu +tsG+v5MmNS0gMlav8vC6r/F4IFke4M+TyPu+SPHOKaootRr+1oEPWJIaXEkTek5G +n7zCEPWzOkJaLq0nMLZ989ohFDfqrHw6xsJuwhclSSrPl16coGHLdmnaQwlA9zLD +KgkBqyjFDYf5tc5ZN+KzoZ/9BoNwZlsx/K9xpgIhtrcZ8gYF5M94a/Of4cALa3sH +SNyCniseN8/S5gtC+Pokpx1G8bSzbZ+AubhzNtyri+WU2NWuwCkVrB4jXDUwdIeh +xjxtJ6NaOtDPtCTsdXx75mgRx3NLz9if2OVlXCrxbXiE8uY9T1+MPhYCqsSqIbsf +ipI6rrukDW3uMLrQHVu90EjNN5iSzeentUghWE7AZ3rOTL1PbFyBWHG3346PIu5m +jSxDTVkRWC5Yc+UIkLjhh7LxyBcPnFkDDasTmkT9Kn1Iw5YrH3vYfoeXxNU75Vln +uyIg4We4cwdxfINIC5r9SQ8u4bRVHaG7n4UGENa0nBI51mo236O0Gju4XUy/N28g +a6IdGuLh7X6JIg/+r69n/2DiLNCH/Wp/I5ajYB86M3V1HzTDjGn+AQBt+y05gW+m +SMunVfYgMKjzddzhLGMohL2tz8tRnmSpXp7gYOtFdZgS6SBr3Tw+CwNiM+qLsFg0 +Lyso2UEPQBxiIGOuC4a/nEvmH9s1/Z/mfUIIOjxG1aGuIuaEtDvdiQiFgfE1RyvZ +X06Xraaujs1pQlLdEwKjkl8+GY2GiVJVFEW35cJ8YDy9RPLFAcjLSkuq+LIRrWWf +D6HJr+7XqILKQBEJMXBzig4a+uKTPHCpL/u6IWFWTCvZwHS0iC6zeYxYFM5ufpLd +QG44zD1mlKXeuamgV8uhbbGaRkRrgqySDc6wX9GjW/fmcid4PRRklYYyGuMSfmWS +0IPSSUgVzG+Jaiu8DjK6/OwuHFAA8fHrsrbHAfdx/n8woCZhc48mUsVwSBF/FX7F +hJ+x41siKuob0IuJz6gTtx5xERBRyE2l7v00HO86/h8KV2wjcHROVH+oGA+tW5D4 +W7vZpFiEhxqRM1Lr7QrWYxFv/9FX20/tgTNbjuqQiNwFdBqm++qZ/JGaly0HUvGq +CVs+G6NY+VFXbkTaPa/HtGQzEJJjaEUitDDxOUEwhfu28YE6PeQxyB840vIjrISf +kgYslgKYiU8RU+qlGO3o9IdfWQu6nvlMwGiq0C64Vc1rDkLzfx54+Nz/Ybg3GYQo +R7mV9HPyFniZFA+tzsu/tJQWWsrXFZ1AvvmwBruimgrxON0ncaVSZ3MimrVCmXYO +/zfo3qKlD22PD9Cx325CyX/XenNJ9ARAKImgciCVfH93rA6V3uaun3/4hqCNsWJo +4VYnknaB2OLhozbP9iTajJz8K5CqBUlAZVSh3jrKv/lHmYiLa29+ZTgv2TicEXVv +7lyEY+3cn2IQU417cUyBsUR7hvFK61wqcxRqF6q3XoMb7Wxs3UeUyKpEP3kAcWkI +das3k1XCu8GFYe5R9lOa2x6bL/WtikpcFHkSWF1ZkAGNCaL+BixXHCh0PFJ+4OLN +9OprvwUXKY81cW88ktBOaUUHZtLJfM/2LCXzyjiOBrrt/J2yC0oM2mwRlPZaUHZb +oUSkISh0Y8nB2BiFQvCNE8MpUl/BrLRSpMwMlrMi5vcqIdz6qj8m+hWM85rHbidK +WtwGnjFXfKFUB0yw6QsCxWkZ915IT45seFx44ERdtnqMq73xmXdR2gadkmXEhpED +VEf1GsQW6BcHnmNiDtAQljYo6Y4oe5qX0hfXVMfzRvlLdDCS64e8JRdYpBOjOxF6 +1QO6BJ6Kiqsif5Gne7G7IPegjPO9AdDXQ/jw11WBGlMoII+lgpLwx+7yoK9B0RvF +EyY1rpWHJdeKq1qzIgQbomnQLmgi+FSZXZ3xfWYHpEbctGiBN0gg3nN6R3HPQHk3 +B2K39jGOvIPNirKI3uZPXeL6QvEu5VmRCKrDL6zZQlsBGsY3AKkjv8qYIPeY5kzi +cidAL0WF2Tf8eQMzU6GivMgly+Uej0RinDWkEcD7uIh+S+8NsBW8AaQEszIMZGPP +PKiMVNcqgRZeSvwXtXmjyER9cTIb0cUXR8cnZ7tc822WsfIDQBe9bpoY6AdzGGqr +BCrHkyfxf89xfB+avZtC8JV4P/RdQJGaBOcYXG/RMsXaZq13ry7nLtvkJRixT8MY +fW62SW1Sdl9xqebK0+DMZa7RU9bZ1lU+JZKNbNRmjxuP8ZS95vG6MO+Vww9wU7mF +G4QigpQc5Np8dgyFMxmKp7CeV+tD1tsCnZRwg/scH1dWQ1sAYsklNBD43GLWpr3D +UALcEX2KapidMfv1p3Cu0TL+mnscuFrbF1RQSNVo8Z3S0lIfqJGHed6Psau/+yyh +9valARn6ILNmOMhrbkGUC0UQzzlGHjeb7BU7gRHH4S5+t6TpfVATAkmz42W1Kpc5 +NqX/23/nTwe5Jg5QSZv3+6GrCAOemV79mlO1eavHWOhSv5hA5FjrM66CC2QKl0qf +r9w06/DXnX/LzWWY5UMoSkvjkhblWSsF7mA45B2mRbwX36+AIae4hGPSWZZBwevA +IvZXObO9AmnFHRgo6jsfFuhFksKlktFTmyQgml89Izl8oE7O0grR4728ZRLH3sIJ +KqE1+0x9xJfGSoL2zNL4j9+6jSxvjeq3/zbqnU+JCWjPaictsVhg22Mej7hAjuG4 +T6Hpqp0oKDVD1zNtll9PusFSP0hUeebYNxzSun9/pMNsqFmm2zuyA2SLEFWZlhhi +z1sKXu+lQ4iAbvVjz2qgzzWDqyl+Ri4DmAvR6042BEwUdxFGLEZqIIswAJW/vIDl +kbDKHAsXcNiOJ//eQxDzi0MMamCHwSOytxU4tX2rMlqQHgsVgBVWaoGPu3Tmk6EH +lTsY9MMNJI15kRAgyVtofcvtZ9DMli+QSNYyC5ZxTw1fnxmkXdvS1k/tdz9SyYbA +z8ZDGSfwvHSM5OK8BGeU9yUGjWHZYSnGu7L9c8e7uXGEyzMztBW00miW872oy49U +eFboWpLSUBzA6xZXAkd2Y6rOaRCQULgFLdJ8g4bOFOYIUIQspBNzBUukPOX3ZX/A +6p8cbv657H4ZVvSuapc/Lfmrjv/4vnPsknI6XblpuWXzTqh/zDxTXUIZ0EYCMEr+ +R4UQHyPuB+u8A2aDYiUcXbEJM+un+pDyivTo3nhVmT6pacQHa5xjjRNBJut7GR7u +InAKT/pROFRzgzSeqvTOdeLdOUr2VfwCq7fWird4xL0vLA7Fu3AOBbwT6UMWzfNW +RdXAI9/hsr7XLmNGDr33HWiItTsYQ/rRRA6nSunzedLt0ZmokL75Oys4A9J2y/6k +o3NDVyaViW2U3332P1Tx2Et/JyKPnyjuHhDGmSSONMDF3mFJYUF/cwRrxnvLyeEd +iSSQ/j2dMzJCBGgohkEe/xsvw8UNFHXjbw1h3D/SSM0UAWh+spLsc87krSZZLiX7 +jPlzNBKsuYLoNW9aXmrXPbNeCfm7Pwj8G69/6FD/Qkom8/iXz15wVuTv6j24Gze0 +C3bpR1sel6PzuPRbaOUfOWwGAn+Ne7UGvZhSTu2+O6ugboSzWr2xBHqh3+T0QskL +zXPFh75mFJf9QlpKm2/adgc/h4crp08pOCWzKnSYVK/wRKrXZ3nAF1aMqbO/+LDK +pL0RRs3K41zSDQ+6d1XvOj/BSD2CLLaMBfqvLK7zZ85T+LYALLBQtuMAyujgluwX +6i0qY9xAU+x8aSab64Gpr6cbSTArxkWTwRDjrAtrMhWsN7aGAAhWJbe/3uavocSF +QvbGz8UcAZ3kt+KWpAc9v30g2DviRQZbhPZlLyVNj8MpMeDnSA1zOwkNISrAlmIj +06UbUsdq0zKO3kBuPmGSsF3jZ/Ed02UU2JGN1neXtag04/rxofiF2BTo+g7xAsjx +EJHgZv9bODFAvyIji14T2F0km2rB1avzj0u8UcW+NRMa64cRtcLwP3SdjhUHr+6v +DvOjRDUz1/4ZtYp5Ghs/fyFQFsjY+nCwNzsZofMMexOJIKlweC2Su8ULpeCcueDz +njMNvPwrIxjfYjg05xagKXgM/T7UvwevCXjuS8a10bGVjcWqhnArY+6w0NII6C4F +wpvVQZlgUcownFP5/YyVhgIAd57SCN2SjYa8n0CytgfrzK0w1JF3krtR8vk+REcR +YsuIxGFCjmUH0CJFUwgc4vnqiTZMaK9thVMBe6qLwHJFhbcpxBDkZP00PjVo9nd8 +rEFWppvDgwuvGK7p79KrfPEgWPOxSR4rkVNMrUBPbbGByfYzbMwUv+afrunGV0MC +3JvQ6WqyMAKIK8ivhCqW3vx5BSMQTud6BS6LTxLwTDuFMUqQKaqRq8GnJPYLNyzx +BAg10NfaXH6662237GWupi5vl6J3FmyMOq8o6y9MKuMtHTvs9sxg48IjY0g+GjbB +KYNuHYXyIwjfOzZA8c22SwuS40VahX6dnr/BA/P2YpPvttO13bm6GvrPffdST6KI +bYkCV911um5dzkGjWWVw1JtAVJD0K4D9dZQpDLjIoC5xzfBCMk1mUc+HxHM+rWvX +2BAEMv6vcylPJECOnhJAD7bNiKzWlhTHIxEocxOozLE2XfbKL1SNiWtGxSfDhaJ+ +qmwWBcLvKZeHxyaY6k7ZpccmTznvZIXJ5zAROcFpQidwHOroykCvH5mWR4mBei/Z +uT5OlGf+S+cLjDjFPyi6ZZUWYGSmpDYqxps10UCqWaQgY5UcjxQ04AJJNOd4hs8M +giDbxsIrNVvydwgcMZczw+NVnH3kjr+1OxkUdIrF7NjCIcbTWKrjGBlZ82JeA9/u +63wvx/aQ+PN/aIftVBV1LKguwy+pyr6QV7ECWPTx9acwjURHJ58ueSMeqXAUi55F +EWAlQ0zUjqOvIRSeR6m3kQ0L+LLoWr/Dhu5agGF6c2mRL7gQ8+0uaPAm0rE7gJ++ +xDjJ4Wv3yoWdWlDwFccKvkTIPLuus5/lsxZ8Odl49hTMrR9h6C9yHcgaxmum3FVg +VyXdEVGAnmHucWvvw+GK5UYGp1oJyiJrXY4bD2q2Kf207Yuw7Kis0ZC72ddsmlHG +Xo6Q9s8hxYJ9UW4gmWmi44xwc2UB1bTIe+PDxDxEgjzw8O+/NxsznJ1gcUw1qAFM +PpHLuInBe92YBXwrGhOCMW/ngynVzONhTjVk+edHfDEuvigh3/SpjVqwGaI3AJ3X +62G+iqXddPx1ELE67iIOodxcA06Ahj0z8VpkXX9CqcRw/n3idtK9ISY5MYn9N33D +cnu3LI2HPDSLGs13emAfWsqDZPs4uUnoRfkP+RczvFdw7aVubCtqDZJrusya44Yx +qvkXsW3ZHR+B7LJ0D64kAL6yxRWo4ZmAwNJtIRkakWlKes5GymPpWcgIPRyyPANB +H+N+/brQZIFk9NwTj74OFaiNk5jJdrGHAYB0covo5jNV2D9oz0FL35tUF+RrQ6Q+ +8EEQQgk/+24MiAlWQkVPtA/0RN2/GDNC3mzUmxIgrlACklRjNrX1Jk3Z8TeBHGb5 +MCqeW6RmrIVH9FBM3tb7vu/54GFMrL4C9skLvfw/ET5yWozACpJedoZSe9vsuvnT +vYj1NhGoi8EKDh2YfUDOYGOJ8p0pvi0gN1Ny/zvjG7yTD6eA+3w2wJQGjV199oVA +cgzBbSMiK3LYmrcDcm4To+YEfLQFXv45hviELOla2HzlAV3qswldZPpJuI//3pZY +j+xPqdkPG+UbraJv6w8QzFLempTCYijyUCIQhEzOXDpSjauOg9o7edswZax+ni5L +zOHXJ4yfkjqXJDBwc5N+ZnD6XLzSCMzCJL4t+PKHrktx+seq+19uHDbAw7wWM7Cg +5nYMdGgeZFlIjWWVdeDBPg9mpxetWWGpse2ArhdhxX4NxdzRF8ksZ5nYKkecHX6a +XpR+wfvv5v7G33ExGUruy0MtlUa+g+bUF+HDiAeJ1BZ3SB8CgKNa87O+VYrBHZMd +YQDmijqHOpKTh3pQVzRvQpYsrPKPcYIm0rwq9EjOf8mGjGHuUYhpn4n++vZJ/Cr0 +Qua9UtsAATFx+D5BCgkDZHz/8hZ5M126hCHMo0iksFzKbS5aMoTDyu/1+RkU0b5w +2b/3dRd9Ex2AJyRmVB4aOsLQoRsB745oWDmZnxm1baSdNWdkgmWSOjFqeLh56ogN +xM4+6ogRts+Gs12xDQevVDKIe+bYtvoyJa8QhapUZqFJbF/hBvjDEs322u/JWDpw +pvrwCSWNby7Nc4OEDa3UCnmQX0hF/4v1/z5N2KQyXO/of6MrKO1iC5Xei46Ba+ax +lb7x4nG8p6Rq0UtBrznw/wlK7jkmcnGsK7E4iGSDfsPp32ag+xBagvy4VC9GoZ8g +r4EJibIWGR3xDQKpW1RBjG43RCaWWKaNVWyyxttnvWDEUFoDKhVQqUL0UuQYntwC +cj4nPWKISD6ESdTe8K+nd/1HWzUtLb0JMg0cet6f8NAbalNa5+o/JDzf0RWlsYyx +KG4M9h+5Ew+wAhlQkBviIh4CmIBC5IC+63XUliGo9ssUduLWepK8vG0UPi4gXjEn +Bt1hasZ/4X+hH1TZmKb5ZLjeNM1IpBd2+pa7v3DM7kyyCi45/nE1ZLfu6WfSQ7Yo +BhPxmUYcD7izP1IsdoCM401Us6L4akl9hACS3zz0PqbS8kFFSBC47W1F+/O6MKKt +1VwESsVYI4ipPbHBq5jerCz8xrPTVBLk3cyleqJFX1N3defLvvZA1MHiSBdoaEBv +V5q/1GWtSTnxFeGARmvT+hvVcZOtGKMe2LQ1Ip3jTluXC+nPaJiFZql4V058BAgV +G6zqu+rOSEuG7cEL04WOMujWqVEpbw+d9BKDicxMULqCR3jnqeENC7hnATOGAhA5 +i4goCGUD5saxPT60BA5fjCswCy5LqHon5s4tR5Sl/DSbh32XAYjnKe3rlY/LT5tS +v+6NsIFhBW7aSr0T8RXqDT7AwyE1I3cxO1wrqde5N/OPRa/S526c9gYHIbBaTDIy +t9udG7fff3rt2zJjS0izTcOpJt3L+BVOnFuf+QmKv7qQtgLsMQa4iHPOBxgrMUgS +40FOcRh2zSqRS6b7FWNSduvzRptglEqRRhhCLlppg6YBoMXr5+/IepGZwo9vVGGB +1S8FQLLA+eOpup9Mk6u7xmQJplpgOjysQjeydEOWnaAQd4YT/22dqvsWOIa9E9Zi +fMdHu0ELFeOA7b9u2qkZYYBucNbsoS2Jh1dmvFqw8kOBKvDWiRx3PnHywA2PJVZS +kgyZR5zJbHcEzbgqyCYEiwXtBDgzXono+UqW36S3AM4z6E2aOj8ZfjaP94Frzr1g +zJx/EPECgTReWwKQclXLy6SdWLSVbNn3xZE2eg+4HTwceD5+Yne3eAGrXAWo9SMh +iTttBlMxYTWptw+mcF5ZUwnNHW4Eh6ScSiL66OGP7Q4Iqke8rrovBqtcb38w3kFl +xIGjRbTcqvZKlGAgu93LU1jql6uY3zDdAkJrIf7kKVFlBLbXhXMlpYW21y+lvR20 +TWhEB1z0X428Brfyqf/WWO1K5VgLfldkULLYUy0ZfKZad2VCjtu9WUJ4WQyND+1x +eqvx2QtZJitU6uyNOJ7x5vqXUWesQKgHC7WyrM6bCq/y8B3QjMrVqUD4hKp1T/V8 +SsyEDORv2WEunaUYy8wASCnrGCqq6vsHdJAVBZggNbaPa6HPKecd71qouHM2gdyS +QvLkwblztMDqo+jW9n+SF8NZkcdSSoBKjyNbyYYSJxAq3cJtxJV+Hm8eRiUphwIa +phRM/ZsmMsSlPlN8wV875YubJ7ldmvFZWN06xpfHfd5YV9ZifVwMN3ZnPobp8jrX +DFi45SpmoBWM2Gd34TNa+jMVIlTJ5T4BDaO53pMr4gF+2qu2byPAdaUrs35or3AE +n7MUxwLT9/IdPP4Bj97CBIvIneHkYnO5ZcJ0b2ckur91gbaM/ymGbilwAIVV9L1L +yAZjCwSBbVQx0/pPJqEhI/gxmkx872F3YOk0v3tivATV0atJaL1vOiGbwXAcztjD +DbNBJ1AuKx/8fNo3DNPDQe4bRzAduZLBFewRjaXbArVRBw0botF8zDAlewU7uVuA +pfAV6W6xOXkz5Be7Z3lglIGUMo7GwiFh/vQtBk7uo2yG47FeSP6K+jJWhbn12b6R +eApp5bYU3Ug8efCby5XquHR5FMXonn40xtLQUMBcM1+MwTerVqq4hjYkHZX0RJQu +kg2nQR2tOmhCWiI734cdr8C5vjxBgNeJ6TKLLFuatf2JY4c8gBbjr0D0mHg0fEXZ +dqLpaTntNDabtviXO7BTwnCtrtpLd4x9q1ZAgD4QUuOijXtUE4wp/T67Y1paV6xO +2E9O1Qg1/C5BG1ZuJnT0th/QVP6rJrSevAi56FoGfEA9nxl/2a3M+ZEM2sX+RmTi +Txc6VtCSp8VCOSHhblLSA2FB24mi7HG09/J8w5QBvTFVq7bF4NtJk+iqYG900yFK +p6NNQY5iOgY8URI7LG+ZkC3xBA0zx0MuogL97ZmYgeEbd3WSjO80DoOAEpOA877i +TMg7o0dwEAkhZhQNg7Cu5E0JAR9ojxOc1uHUbev8XoiLky4DBSAY3eHO+1wub5o6 +IMf/i85dLwJSODDNP3it6VXv2U4JrVE68UVQjFWF2owGmMLH/65OiAl+y+ft1Ctr +vz11tqPNM3yEOjssghRzK6E9RenYEZ9bhD37DWWqidTh0IlywyDND5zo0OO1S+Db +7JcI3BL9XdPUolzIyu9z4sFydBLYIBUGTPs451pWb/O+bCpyJOsOF1J8uuRSstFM +WDlfAect0BXZ5NJeFmTD6hCT+BF+txHBaJPluV+vnSFW/Fz2snZ/jmYWPShrZ8+v +kupjmQSmg0Y+CBtOKyK8S1Sdd5+v2+ze3+ctwkz55Mu8JcGISOqyjct6v/jCjXrA +tRIYOHAvYzvO4bdky4dcSRr1V+A5zyRSSBnvxZrN/Qp7ewPdKzWoBAlXQ3sVJr+x +PpXhezIOC4n6WlrjCIKtphP1Off7D0+fGFS+LZOeMHs4hLao2cbMI66C1CyXRL9b +3sTX8mjDs/8oe7pUjJwfpijvVgpQE909m4xuDQhkrrn1Oclu8d6qkF62eOk+I9S1 +M9y0d5uTWXVoAvtyMg8aqkldje7zlBDYoyoWELXNWeWJl4FWNYgB0rcXSEWblCR+ +PSM7rvN7Uxk3zgyFSwM/gwizRGsXveARg/omLbpEhbe6UMOj5xhvKgaBnKUq/Df+ +NmT5vWcEvG6kZUOL9blH3K1SEcEt6fjK78kJXv9ZCRL2iiFU9id4geQo04LTULrj +Z5XUpsFY3ZL9fyzEHSdbuIhn+98WdGJQVrC6eKe7KjPtpXWSBmcefULaNEb4M/H/ +c3jvPoSiFaHpinPDjLUkcVKPnavj5gc8gcxMBUG52eTqQtrOvn5uZR2f5uT1zWNC +KYTa7xqWBzA9WDUK+sa9O5vZ0SMEiud7ipWcWFaCZwLUYer/db07pVlUBSHcOSnG +QZj/6tXW31m2VfjpXoKZ03sNiqtzPTj0+7UdpwOCBgyV2c1fo90HE4Yz9zRKwy1C +TnrflWuwuuP79lMuhz5tBzamrc0m8ECFuicx1faev4x7sjRo9mVjHuIrZq3GbgTk +r/09j+WzIL/WVTNjZ5nWCGI60gA3EmbLJ9nHoMGvPi9/v/60x/jedfB1uChVk+at +uDF9sLEPdHBLNWhTJx86uFmlHf7nLVn666BjBaCuzVrt+QSuKnsgBZluMxwfzrpD +xMPVglWkPuC2iR47SiHxLDD75zcIaRg+///oXcKEwgPwelbjY3qw/UyABPkrTapT +3dC+N8+0zIInc0xnFXfmtKr0+BMnJttH703ARSTcmuTCr6XdmDq9Oc80h4k79FIs +YWIFdJAXzXE1yNmTJO5HJegPilebEtsACxaiFeEVMyekmtlF/C/+2xA2ZmL9L8Um +1cOru8sjKg04JCzIVSjTzstZ0PDTt5lHZxnnSWRke94YKqciDYgo78fmlIFORnDH +kZ5yzRf/qPIVDAv0EAU6eM47LD1ovDI6npOUwfwGwmPDdFZDGDax0ecwNBE1FY/Y +WNmqh20XBE/7wvpP3IBjGrCO9S8v6z8J41gYhOxjXxYITn/+jbqhkZwqSpRx6QZ9 +u41P/4PupcIusDAcrjw/brqKPJ69MxzX4imuYEoY/yvVrBdz2Vi6Pl1YdyoL4XYv +tcU+u7RNAjo5Uj/4KBktUVvMpMEU2uD7ob4s1Hq7i9f3l7xT99oMvr9U9xUmt9TX +rcUhtICXeHqtbDXDBSc2irleLmggS70kxwJqZGQDEE9p8PMuNQRk6Th0P3mhAded +EbZOglquJlOv4zoDatYwycenqvHPxXaSb6QplwSeJSVK6wSthrBOXdWSlangZgEC +IY/jL9r6j3Spyx1WI9KwSkuhh5GDBUb5dY6jr7Cv3azmVPQmQFMpLfalhnqb0utN +mbhuCkBqvwz3EkEjzkYPhZCdccB7ApayS81SlS52dsefJPnLPUzv41nJUWZqzQdK +cSRUDfdjeL9dNidAz2ZFHo3loyJ+TnRQk4LTitJt2SzmfLPYIZpQ641qVQIxMSJQ +YVPsAIlWPEiooeb9cZnk/J0fuqAPOsEtLHOmvBjMKylSZvK99wLuehudvJzuB3Zj +olBp+pH0cRqBQtsLyWE1PX7EGYZOjqIoedZo0v52F/KhrCQKOZm5hJiMVWKfpWQW +Kq04nSYoYlVC8hWSiATMwahHeh6n4NGWyHNf/E8nonRuqSMxPTGeNM1+zhMfzi1y +ZA7VBuhuIIecJo/TjezU5d4Lgyuli1VDFpdv0sXplXApHtLE+GUimP8Xgf6TcXcj ++Oki+5f3MRZf6e8A8k/1sCjgl8RSp1oeYXY99AJC71tpnx3+3GCvsoZqBGwaN8wp +KKikdoAW6FacKdWNWZxYjf+3t1GAO/ZbyEwPupNpfWxNF6Q+W6hGCyndnBO70r06 +/blR5paVTlbT3eQrb4vqIDR0xiDXV6pafCI9nJoTT+pwG9lUFMassq8sI9A9i3cN +c+6no55MUDQ8Ig9T8nUIPuGJHmVq/N+T+Mh8lG7wIiNgxoRJoRe35hcM9jPyWtBO +uIyabOFJNB/bfqCTW8W9YPVmpEk++PWjtYQ3vJxsUjalILlp1KSmQiXyXmijZm1p +kY4Lt2pV1lcEwZpqL8Yv5fqIDix49pwMxpzxhhck4mJQmtCp3dS80os2GLppdy4U +MaGEG7eur53wmnDqakrJS0ehozo65r7A9DeEzPPez5IS/yPLa1G5G5d/TYbLbPEw +1P0AShJ6GA/DNeACt1NgRu8Yt8ZUvBwc4R07p7JBWi7NgWAr+BNrYAhCwqSfqCCZ +qFg/VMmn+xn5ZxNcsMYnQXxNkgpFlPfyTXq4RfXoR32yZAV7kUAiiPwoGSlAUUt1 +3RE1togMupUaJQfZGqUzDSTQpZFthhg8Tavq4hrKGfKIp9FYzUGsJywvJmj7KgJy +EbKJHwQuhPiT808IqsqJHDAk0FOAIQQyY6ClUT7IcTTY2+10ixS3rdmj4PQvFtch +z3tvoe6brf6T5AeZ3EKGlqxKLXqRx9cbG3iK2SMj0qPORlwcfQnmKZJ03TktuqO7 +5KXXtFnqaFRV/WJp6bb+C+NnU0w3J4cJ8GlUVlaNo+H92/6i0AAT2hPXyQLi4WJ0 +rIUcJqLagEA9muaabL2Gd5rAm/vpoW/JlF8VbBrdoGXZM/+uQ2952fF2t0zwvxDp +fNuhFvdDm8554go6nwfhBAyfustZl/MsrJkMOIWUBsCb5bnMi/pQoVLyA7HEUjK7 +p0QSZbGxf8VENpv80XGEKpvGN6oE+eAEbcYhE4x5IJNjDq03DJUCWvZFM8j3waZ1 +ISqGmPjLqOQCKgiK8AD0/11LOhoG+qwsuRgvF1ldO7L4AHwFC73DnXXGtm0yV7Px +VsiZOV3uXYZ84Id0dZ1WUEBFk+LcGlzhBFdhYAWgOe1spqfX30lb62e0e2ZzKpkp +Sus05QxXdbBfalhCrh2Xqgo9Ya8bslOndjCuNfMzLqFnrZ5zW7tOjwJ6ygEL7Mbz +l+zY0wX2xx233TJgTm2TaW+NEu5yVL46FzELo81eD40abl44yq4ibqYwNngPR6mw +4Yw7btAcsiwxg+sOfGkNX2Kdvs/nQ53KLB45/jhj19Kp5WQrBnUYZMr51Wm/zVRn +uNZQcaNSYr97B/G1SkGOlU6nFUwOJkKJyt/3G8emW9SKUVfn/5VPAtT1lyS6ZA5g +O7Jp7GEJSjrPTArNhDVEM3kfBjeUAV0TEla4rydV1+3pjKfuq+iOqp0xx4tbCLAg +DS+xFeBFCWPXN0g7ruICxtL0zijEVaK4Rj6BqsgzXrvrnEWLxmWSRXUt/QLFmwFe +vYvBVHH1npIzVQfs1G1jTUJUFjhs8GygREALCRfsYmCgFD99zvzs+yjvUsO55AuH +ZXXLP/hvaUTuGAtz+Wa5o9MNk6abkUwgpIMjwZmPW+h1jibFMuohXfwbMuBpMefq +6v/7Zp+DJP6w0EnOpJkSlTIOYaEIpt2q8cRYvRoSVvqVKJKyW9WrIPK02PNPy7iw +KZlZIJwXnOskzQuVVBI6tFcuF47YUJZdoDE65AbH8fI8GCrgiOl6AarvjcKIBG9H +CWcvuLCLsjVubO43MrTVQ2ToDVbcKvp299onK/wcSz1hJl9t6swfw0gPWSI5f6bV +5p/R9TKUt9Ln2rGEvVq8PB2iI+DYRQ9Ryy0CSJtGkcjrqz1qsGdtlwTeI/BqDCF0 +me5N0jHoaxRoJsylt9njfnD/faPnOi4b1QmnyglDZ3x9FErORWmH5HUMtb8heioS +4hkqHc8XS5crDhv/dzwcJ9qI6Re56f9u8aYTktN5dFep0nDS67Pa+7hmred2fUEs +c1aKci1Y9Df454tGcSjqk0I31+HVn4NoyF7zxWt13/8mv/9ff+QCrbFui4Z9w4zX +8uBRd9n+s2I9nDwP2xRXuNbCnrq1iBvZhgdWpEsq6E2hd1WvYG/u0W1GtbaVTk/S +0hqsZpQnwyojEU/HI+6oRS/Q7RRAvnqtA17wgwIY+hy5J/thbBp1uPp/1FAt1PpR +nfyKIS3lUeTiAoGCjjqfeOFDoDcaFQT1hrMEwXaHkMyzuVC6fcNJ7HmxXo0WCTs1 +VjuQ+16brspCpgYK/UQZsqjSNVkoNEre61WRE0s3Wk+1QFqPOmLO8p6CCb4z0jhA +yScsQXFn3E7dlq+keHOKgsRe637ec/r2uAWOpR1zTMnJ7p98YkbhtXn2f2rpXJqy +CGe+okpqrZBUaQIgOxzqrYDMtnfxEURmkzZfUT6+6ctCucmvvc1Hj10UTUzkXD3H +Et6AY+jUi1EMfNCkdBKC4kHEdaBxwryOfFNRfDqexBQpfF4Bn+PC75tC6lcBeORh +NeJ13Si4at5mUweU/Q1EJH9s1YTuHj3EhVVwC6hXWvUtCICa1s5nILU1C9YyPVdG +zo8fJCkKZFGT/N8lEpQGPhCKmUB7lLl42nrkFLuZNv3F3HCVAg9DsWF/pZKiRnEv +EM9NJVb7shic9+km1obDCllMU9nLhyGrMG5xxxAwbi/0MUaAjpuFZ3S6kZE7N/Ec +WyLLqyf1BtyeYR1EWB+6bhGJ5bkn8xWSmIQ4uxYfMUOq7JjHnCCJ0EyfQT5jlwJZ +AeXAK5/szcXntCFQrREdXX1VumeeSTxJMeaApZE2Qli5tDNDIrxZmAT6dGBaQJ3Z +QnWrlHTTUPbgoIWfo5mcTMImpNn3ace3bf9UGNEF8PQLptB827UwpWMG6leQ4Tf4 +glKzORAxYX5FcCDnxjikzYyaBWrQzSDx1knVBy2srtbk7G8Q3c+5Z/Q5fXcmhi/9 +JTkwp43j6gdrqm3+IeU0yr9KwzZI2gsGYj5mKBwZwbPtbK2H0kug7cqS5jFXne0Y +nu2fskAectEG7FmX3yzSc4+jVQc4CaKSDRVYcnmS5sNlAJAngC+qA4ILBTsODHpI +HI8VqPqvrGxHXMEXIrbGzVaok8dRkYjKo/qW7iXEudyyigp9uwnhgvQ31AQaaZSX +6EOQHs1ikcSTu+M6fkozMUTitLjM+J7qsEKYA01WFfK+ymPSrcPQsldcl6S2sVFa +prY4GQVuJif8qOcXMX4eE6xHClYOtBtStemgfVo3L9FTsG9x4LLSgvolIGjgID8b +xE2FAigQPHq8TWUmGDGmCGsdwiwQPSdYTp+AnbQvq6Pdx3pImDDgFQDZIk07Xj1i +291qLrpLnyxP7ZtwIUZ8qXUB1dkOE9knw5+5QjtoTYdWdln9SpLESShxRABgPFHf +N+VQpb7mH78gOrXu5AVAaRAULOG90rHg+s4LdAfGrDE0KGP2Zj9Fe0+5fg1T+6Dd +8wJbC+X7/TOO0tcXT2Nw7IWIg8yWfG//9qUHj9PnEqMtW/dkhQCi2NT6d0BSXAKF +8GeTC5JOkkqVZ+eqj8brYUNzQu7wk1gkxVaJ3Nj5fkyevmxfu5Lta/NunlpgOI3P +CO7yIPG/IAZ/oJthNmTY67/UEH1w8KN2O7LDc55Op3iBPcqnQyhopGvzLJoF1XaU +tHi2DwEoXURGkGR6MOu7qsVrW/V21cldJ3M95XdiSo3VvvnpGjnwFsS4Z0uVDcxQ +ei3DdH6LA/rbd18e5BreomZQ1ZmjKzisfEyrqxsmOc3IxZyiedXEhujBO+r+MaQP +FHMHF8ii8TRlRwJOoYFF0rE87YSJur5VWzRJ0Jx/1E2ebOIF+gHsJ2k2phY2aWO3 +F+jyfZwbTeskaLoZwlU8GIgddpTtEQHm6ZwpWusSlqXi+M8zNgqTHxfq25XQiKIJ +JVQDYJ8wy53EQGDdfV477LKfBLzNeHaEPTps7WyqWzKB5yMiT5oprYHkeckdiRey ++mSBBTsaLfuc9XVtETvoY5iifjFqx6ww6ZymnlWIREkNIuqgduvqkmLf3BvyvBp4 +nZ+c3f27zaQFxSGfRlnjoen7hWi7C0sPakUabWriQYkIbNpS8EAWjbUMNFcNXsis +ct/nrqP7dRcOHLzvs6EWj9WXRkeolb16yulMJZLfkPGtTtEmkoWZuaKnkA9HFalQ +inlvBlHEDsNQeB+abTX5b89FNh/gGvloDvLoqpxzlBdQPGsO3Lvb8HcDxTVMODVt +SiEK2IRf01BDldGZiR7PdONTXVDdYRqgig28qyIkxXNgg531lUbrSlfx4LCJ1L7r +sMqrfgbCIlKX6kFy1DdUGiRWgahmrNlU6/WeZqqlFUIliZPLbb3vYaLY0kLzpeev +IMHJp8oA1M2ve2ji4N26J/yhOA6p/P2m+eqHggDZOxdpBnZxEgzblsNpeCkf/DDI +gbMc+hmAmqeTFXzrW9qZzP/MRg4M/KXpCCEhojxV4kaCvmfm7E+HNrxcPbnjkCx0 +CR+cBTEv4f7VDkgNMOPrAFPLLha13wZ1S2tJwtT2Ub3wU2CWFIBNyk2IQz3Xzjjq +CAqv6/guzIMhv0ji5/42Ut70sAiYnSuLtjUswBKFIIQ/4lE0Lf4nXuFPkngnD9ZR +vQWiDPAr6jvPkEo2WPWnuTWrRC65yWWGTy4LVRVgRssVff8wF0DvjsGgPUEcjcM5 +rbgJO3OLJ7mDTuBU8T2FWf0PomDbDbWw0m4XwEYkuZmz/NrkAl/IAjKyXgcSiJTI +cXUoJH/6AqXMUDxei5HV3aeqYusmciLa+p3r4rHP6JMUP7H7EA7bQuRMohkOhzRc +o3zoREhPGeNDrc1jReZszqIvl3AqojeRytiieHj0avAMPHmX0a+/0rJPfxjg0GY7 +1HaTisqxJbDWbV49GlfnQg== +`pragma protect end_protected + +//pragma protect end + +`undef IP_MODULE_NAME diff --git a/fpga/source/MacTxLso.v b/fpga/source/MacTxLso.v new file mode 100644 index 0000000..8805316 --- /dev/null +++ b/fpga/source/MacTxLso.v @@ -0,0 +1,1744 @@ +`timescale 1ns/1ps +`define IP_MODULE_NAME(name) name +module `IP_MODULE_NAME(MacTxLso) ( + input wire io_input_valid, + output wire io_input_ready, + input wire io_input_payload_last, + input wire [7:0] io_input_payload_fragment_data, + output wire io_output_valid, + input wire io_output_ready, + output wire io_output_payload_last, + output wire [7:0] io_output_payload_fragment_data, + input wire clk, + input wire reset +); +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +EYAd3mbn/xhar3hlqQhHXmi9nJO/Sc1phUP+NTKHH/cySFdPR/c6LtYnfdaakOst +DZn8xJcYSAxgRQrxWTES7TEnvtmukjAiedXml9QEurP5HyD300CnuOA/HNrQFS72 +ijRe6hCva+3p6g+osbxssWNj43uf3H7A3z00f+6LU+gLjl/cLAQopvRSpv9Cq4Wf +GA3mmls9DUOQ96sxBgLufDQ2V6kAggNRmbMbb4iks2sRddHYw6khj4qpbBu601G3 +SfzSAZcejK7it73r7Ku/bv8a995UcODh5Ya0pEiQ1O0NHuROqzGo/+rFQrBwvMEv +oKFvKMZEUs4IM4MZeY9q3g== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 81776 ) +`pragma protect data_block +z1UmCVj+11HZ7zlYo7iy18wd2AOfYne44/6ibkZX0OpmFrVq3bktCzQeZRUzswBC +ssCXyhvFauDWI/0OE+6daQD382Ai8tpsfiBspyhm+S/hxToiuieswOtJrCjjRsda +/sWPZQnnSMxdzGhGpRyOhnp2ekWubm9nVIYjGu7wNauKwLj3dcphUqY0r3wNr0hi +w4wMhDDVsh6KfWBiyUQviANxNpVMTHd8fYUL9PfMMpM7JHgfr74xYU/59caF6Ung +CFgscfR6Z11/SbRAwVOu1ABzpjw4WU/SR3idkVgxVYtql2TLEf+7RshFulpba7+u +AP+35GDmFR4RdNoSDx1hUcejBMNy5dAdx9xc2uGwi42q6rhigpOJiQJibtfe8QTr +fx6t8i/xY78FfcFpS5SNECnr02mNDcpSsnMpzEt45y8I1K7vp32D3nL9g+sFcLa2 +gj8avZp4OK37hk/V7VhrwOgjBfzuxeUqec/UPZ2rRtqvIhSxAYYfm9rbHWl5a7Nm +hfw8Mg5j3jAIgxc4xRJhzcr7cB8BehG57Y1HZT2rjoxTQw8i4nPK8t85URaSB8kS +3lXSaAnK3YSUCwaR80EdgKRulXIUW0AO8YV8OEHDFiPeg0j3vrZvqjlHgoE1kaik +wZRCLNfeZBSocPsIoyz9hdEbj7TgruDDg/wSVvOnl+OOmjBzx1Yce+rSB6dEgchz +PwB6rkMjfszkwmOx31vcEnl8Tp2N6CggP66Am3IgDUYmL+vUaRCETkAg/sqSrqG9 +ZR5G/W9LwQHZYc2I8ZC8lN8TDhmIC1KLyQRUBY68iSpxGgALX+OYGxV85wQe9bRu +W/jo1Vt08Qa5uikGkR7/6j0jShDRhl/LNaHAcS9ofH+XjsrRvEsyKAnsQRyNxQHK +3fEduqWXbIPdrnzbry5tWfDGEUeYO8TOhkORFW4IxUnCa0hj3pdZlGdu4mrfCSz1 +HuoUGeni99t41Ygfy0DJWJFNcLXT4Vw/JXtJGSRHY/iaX0Ps5z0oS24k5WUe5FjJ +CfvFcSHqHZCl4uYXOdA9nwToTqHH1YDKNdf0/V/nakSPZBF3EUTNZ2839w2T+ZUx +UgjMNIGAvMUI8zlg7QBHJ3tSA4gRus1AQf22eD4d5rVfAFkx3DjlKA2FFZivLtDQ +2YU7hVz5ENxrZwPhAln7y/KveWN3k/O8Yy4Hh6x3xPEHQHAT7LX0IEegJfOt5x3A +AMBtbg5Vkvwq/Ji8etBC3fu940fHW2mfQY4ybt1jLKc19QC3zvyYl2VPEY2gcYuy +lnOR3hTIKDrsHMBtbSXcs23xZwSbceNzmKcP0ZK44kTKDwgdbitcySkgpo0u+gvm +KOJcMyu1Sj0elUoZw5afbuMK4FiYjFmMBsrnqNNWCIXyEmwvrnTLL+pZ0X64gtXB +dKIDCrCoEiMmXxvpNVQ3UaAiiDZ5Ny0nhRmTNph6V/m+7HlLI8+klz19jtPfUuuo +GaLdbotJyzXO1aH/uqKpx98OFg7WwPERBuQCJ5yvwBm1s3yXgLSRM3WEvh/Cc2QV +TuIpLidlU25au3u47rXAqqnsSyZCCrvs03HjCWpuqR0XANYKiKEVTZOODSL83Z2Z +60JIubXRFhXD/8/4uBwJroam/nkq3knVDXdUxQL4+08nne4i0pk2bqyjLV/YE/vm +CV3LGmxZvsVp44gDY3mbeOYQSsgHvOkMbWB+inkNfA+F7i4ktHUpWccvDQUjGPo8 +9XAzrh5iqwA19FJzY1g1JxG0YL4iSAlUy0ctjjacBM/OITGqiJ0WTcrw94/Qsbjn +jRAEAg9rhUaXSRsGaqS3pO8FxQmGkspiPVnoaHWZvYaM5IxKTywjvqpjTnU27lDh +QhKOUDF+PRj+ZrSGt4APPTQfNFIaUExF4CVEAUTZv7aY6OLXD1mr2W0d2JhQGL1U +a3rOosAx7wUYQFnNrjTwXFB8CGpwMewzBmciRxltVb9lAkSx9/l2TZ3OeNnqnI7J +GI3HvHrKaiippXvG9VL9QrJOc2kjsMFXzymuiJFZfjCsE8RaFwui1M7SjrDyg576 +L/2+fKscNpQNxRWgt2H3WJ9Xgkcw1KVA4qW1rQg2w+buSx1dRTByLrcXaWdhaDzj +70/FKauGGPHxGo/xgLlSy5cR16x5+ixLOcLO2uziX/5ukES7aYqdYTsdx7Kz770d +aiDdKUtxAmYh6/fbwsfvWhUtstowdLAbn7iQZSDOkaTQh1bW/1pWL3F5kPf+Do3D +H8ngvv04JDLW92BjUIFhthbjsKdcG5MSKEI04KzGXDaQq+C1jPe7ZX3bhBeS8uBT +1R4T/6gcb6/jR/GB5PmVoLHV7PDF9lCY+FTFNr2htllwh/PAvG/MJFDozCVt/r6j +QjZLdEDh8Ni3h2pZNQyPGlcaMsEhKlgXhngfG7D3MoLERxacof1kWgHlY5urI2cL +RxJudkT8NOSON9Oh0n3Q29fTiqiHmg828o3eaat+NKHSvvykeZQtJBiMqtdFHEgK +m4r6DSyrs6UaBhStEu9VvRvKiOWvBtcFS/DO+8kj7FpFMSiUl6ipsH6ULpimQmI1 +v6c7rJjNwhww4xqCjZ3YF22GnyDJ2B5LsphpBa/FaHAIyqtc5g+gd6ytjRg9Ze0o +UsuEFw6zaWo9Kdzw+EJ5GxG5QpvnStv417F1Fw9kb5DFk020WHRdpQwcRZOk+2My +wwszf8UgN7uZdw6zGAbclXfzQChZdCnnpXwpPGCbRhBFWsuo46PuAc9XTjP/nazs +q1g8VqWHyk+IfnBErID/Dw8RDhwTwaAs128ojDIihHBb9QWFPzdCKGWWgH4VoMNe +m7/c9hp9Pv6mK4HQmh5syYI3hzYpAw/qVDkc5b643wkX3x+BDjUmmLfwdDEhVTMP +YnE/e/gqxt6K6D9ojbFb57SqYVtQ1OLUssn/IIiflk8kmK6jVKL+LjOJdSwbYsvG +9CeDg4CVmNCKQHnA11J7MDXFxN569ILoiRLQ4ZDT1w1htMDFNlzDHTkVhv1BEXys +dXaKMuCYj5Uh9WolNoUIP0yZgUpfP6UG7Txpu5Hwd2oxKIqoffWk3FXIj+vRd9Dy +ERueyBE+wczkdvDoD3IJzEDvCaklpJNAAD6D7miPrAl3Ijl1AG5/kKWbt0KlvrU/ +6/L32Do8yCpbtbPQP55eslu+1LzcUzO0jvwXZLbBs6TOJvxG54+m1xq+4AIGLryR +Ol2Q9kmb/te55aSOZGz9U8F7hdn7yvVgu1waDoRwsCEf/t78ICEfmQ1jA0DPE8CL ++4NdESQ2wxo6G+q2iTUZTfxmrIBDaGJkf8YtQU37dK8tV2N35xTRsK76a58XuJd7 +d+1l+J+otzpySrFb+Po62DdPMkvt1Z1riDk4WknF8XupAJUg9PJTG65Xt9ICHkuy +ieZkMVx/orEud8Wphd5VGiVoVy9aQKSiJe4LxdPTp8y+4AjfnN1RvPQU9Uj4mY9X +TaUwEL4hSHxFWIKWiEeva7nlDxkzNmgVAVq1FQtNZAjDdcNgp9pcoOTe3HS27VA+ +7vJvkD8nbeNMcxGl704/RyhnpxgYiXSkqpNeodxg93HRMGKl6BdpnBDghZeS2Qhs +9leHrXfKBsPzDeVO+2Sjx0s8MKWAf6GOA7k2x8k/F//kdpJkjdne4TAwxTfQlKwg +KgoHr3/PMR3q0+yDLofnBdIkR8iVxz+WdVBRrstW+GIfWEbSFrSIkjr1pknqPO3y +EAMvt7zgpCWOIdGBqGGcjhsBbr3gXtjCB684M5srS5Pmy/IfbQJM0jW8V1tkkup9 ++96ANQBn6Du3GURuIq0Y0dIV1fCdiRugFS3P12qCimOEMh52NuA1z+RsNk6P+IDw +C170EcPOOTze3OkldQiA4ZXDrl5MAgPvzHgmt4ZgQ/RwVEqoWThnhOG7xMnslIbz +qw1JiwsQBfl9q4dqAPPyumWErHAfZJqvelkej6MJdk3syb7Gm3Yn8ABjp2lDzAWi +PDGC1vhEEGEa6CKxXJB7DAqAnD0UJCYKHOcmIisUCXCrhtwDTdT8TMeRk+MElW77 +5Sc+lnrxN0Mv7JUjTFoPU7EhOEjsC3wr7zHRAGBD/5SCTnU2qZxVoq/zWKQ8Kuyf +Sg34+IOTuXfW7XZnyNmoZChHaDV5Pra/mn2/62fDYszY8TsyoCL4KvHl1Tzyjham +GGheqn92oInE17thh8a87We9OLqYgMR4n3Vy/oCXk6MuzMclGpR1O3O2GqyxwiDN +aaUGxn1LhwQ9HnVxCT9Gb1T8z7fxPhvRMM+Fv0B6XeI/Vp1mVeWbFM+VGGh/+0xU +fP8UEhPaIfkWjc+r8Tq1ent8vt02HjDhJch5buRWmF4w7MAaP03FhKVGvOzyAM5F +DlFsIoz+/w7OoJORMNVpFB7l3D/sQKFbjiEV8P8aIezpzTE9w74BizowCGLqgxbl +n7n5NM++WKmmHwa76tvwylEx9AEnE8VtF233I09gxAlrOm3c6GC0uuLmx1EGKUAL +bh+DxPt2AwA9txmww6Vpjx+s2we+FVIuvZtTKTt8Gq8vETsyjcFq/YqzShB2KsF1 +U23zcJYm1AS9dskCwTWrOTgA9lOCG5vtzV/133629ThiS+7/1AWvhIglTumAHcCW +7ljD24WfhFTo+4fqYSkgxw+EZnEnz3Tj+3MakGFbzocTW+zzvG8lcUfP/NvRRCsi +1abtNaxdmeV4m/WuIx+T90baNTXlhm/FQktFYp/XZtyZsPMwehpnlMgy/tuXufYH +HrM679Zw2sbjnU/wvwuPAboi4TYD3IaxHfLkQeb2dFzLrk25AjSGT15rWFhR7WjN +yTkA1YgD8iNdBVRHX6STQEsZumJxmvz2WtSEE6SmJ5ZpwJh+mbBQwCJWlUdVl7VL +26WAR/yCqc8Oyu2b+/+xiXSTBUr3JCcZ3X8X7ju1Lf17Pa3UDr4eeHyMcqre0dHf +RZKBjbe5eWLVZeWx8K6fyNmuwb3GmWtbGPzETa7Yb75K9X6tF05vX4MBX0c5cDrZ +Aj8UZWZ5XTs12RTbDFqpDVwgRTlgOR6Bxg3PuGkPUX/JMOjqhjTlc4UjGE8jfVkl +n8uSXPXyEC7jGccM6WHWKFnFn2qTIaUYU4GJmASnHp+MeozxNmVWLDZ7LyyhaKXG +brq1Z1bvHfrwL16xtryQrpEo9CAAmEkwKY7c4cXAl5ftDFeKWTi0t26ISFOG5Q9W +PzBLaIMIbf4i0gkmbojQPqgTkS+cmmChUgnBOVhLo/Zh/w1BYGeiXTJYrLiECEY0 +2yigrACz/QXxX2JMtk4mCWmIAxc3jGSEF+xVHaaHsrK3727cB15d+LYOLzDMv2D9 +DRJ1A04vaQwS0vxUM/lFWgU15qlTArLxwwUTUPE9VGBaNbtOKUF5NnnhDMSONLJh +yKH6Zh8uZdW3SH6piR7fqSqsKNod793PxMoCttvOi0W0W/oYZf/eGrmjVGypTtC/ +NU8K4+Nzncq9V/SnCDbPMvY6BwFJdZSEd07eZz0pbK/awKufEWjgtGk9YotREZLu +Ipvt29a4tpbL9d5xnqDuGyprZPnGXvDtv3vvwUuJtIhCoSiz58HW/GdSE06VXqhn +9d0hFFxrUAx6AbC714E1L+3q+GIgHPwXUIzM1FL1GyxSDSEpdNx/jd/O+a+KloI/ +UF2WZ4isaQ+1Yur+UaYu8cGmPY0cn9x962ZfBQ9mNpA8+DyOCP4W8o6+tlIUU2Wr +hXmSDK6PUGLb72S69dmdNBwqySCJ0oEf3QmvWNZXjXztfBzWBP4U/kn1DGNvzqLg +oeNdY2pfwL+rM/xfu6b7GCHWyum5ULBervTrAn4XEGhucFVI1CXL3L0n4Ri3rhYL +fMNqRzLDRe7HbVb6slvWap43o1Guc/PDhD1bKX+zoz3b2N8axzmCZxyBNgaD43BW +X8QQziwhqYkczQHD2DrCe0nU5uzu4/D7wWF6mjuySHVOC1hqqJoDVZQljrHMCWzm +59zVW+eSwWxoaGTM+J8myzudDQZu4Gdv4wPwrn+uLe+gY0KKZ8Wy9oiMWVwM2j/l +tzhojKO8rvY5bhUs+5d+Dsf3ffLRJRbeONJBvjGzY1iAtTCSsdgdxmzIttaUYxt9 +hzGNL4vEvKO398YY7dykJJzIEU7dRf4+5EJApq2bUwJPvcCeFauDVb374a2gq7vm +5ejMBQEo1WrhjdhkQZN1Ki9jw3Tk5ZqGQMJf5ylhJOXtKm4Y1/8S7FW4CLswPck6 +nHaZdnizB2z3D65NAEMFJM+U1LZWbsIvCAJy/MnPNJaLgF9qC8g2dmyMDGAAFCkz +EsFVoLLhpe6+fLvZ8n2gH+ks09WxI6nUbx3pRxuhYQKhBcx0JjYEeSGyidkfUKiA +MKbUpp2R1EbqtHfbbVs2tCpHoHjviZwkBZMN6/cXJiLvqQIWFIxFBTi8QiVtlqp+ +18we1/6/VUTLpM6GBvP4uf2nXAJ5nQiI2epjwjtG85plUSRjHnDxr5gj+j9slMfM +WdJf6MJef9bJVAIEbod52aIF1fkdZaaI+6XQkeh6uWnZb6oSjSUIgz8YZ5mC4R00 +mdBvNTugdte7VRIslNxFDu8HDfAVKEQ/wJdQlkro0RmULU28QoVw4mVGsFv1qsYs +FHW5i+f2n99wr4M89cIR/KhYSvdpnRaWlW4upA7zG5NhAXK40GLPTmk+rMK6H1Dh +rU1ww31pu/RzRf92k2DhcGzmSN8srZo15DpgBhn9LmfITgHI/YAAAbgAorVJgChj +Fn6pkDfFcJ6EDwhfBMBK7KLpves0iwmEtW+ifeBie0JWsTLVt4Ux4eMzL3jHUW64 +7QwpEgIGVC1zDDb0wBWy96q1BLzvdVugzoGszVdFbleMxPsygpYmWdV/kzhKisW+ +RE6nbkWXVHtkve3BtNPniEMCBdu6URg7tNIms5E8yi4FlpFFtcBOXJ6W37jA/Phd +6n3syywLIHnye+WRPxgzvhcgCYzCHcJFysUVNv+VI4Rvf6lMb9y5adlZi9DwimV5 +R0YH0XmYvMSzAbfgHsvdMqDJH2V//l2BElxMPc9MiQbycWeb/J7u5DRt+cda3ma+ +Om6N6p3eyARqX6dYsWYguDo0n7ET0VTu96OanZlDfBW1G9Ygwpv6eWUu476sLjH5 +TbQW6OpRe97pYhrM62T9yuJTdX+qrTq0/0pfUX23cNNdrgs/z57odyJq+qwdQIjN +k1S+jzhVXdEz+mTwzQnFTfIrfzGkIsOZKX2H/cJUIwbUp5X2rAeVpkb7DGjRa393 +CrzV43ZE3tm52ydQdUQ/Kv1qjkKQ/I3BmDcYqw0HdtDV+cfQAzZSXd8aKbmhh+W/ +inYa3iBFFM4AnjfsmicMvVXXvu8YwdEDEhrILk44f+upp/CtG5EIKir2DOvTW8gA +AYaxeN8Mhf0iuOHzE/1HEL5M9qSqbyQN5L1M9sQblgBwzFukRomMF5XNic8TIr9q +A6iKrwyM3+T8uPHwrSRaCY+ngftSZXMVvsxhVq5gXFBqOXpOv6po+rszH4kvFBiC +yT5NY/kn8ILXfEjaT4zrQU2bogaaIyU86JPgArDw4nDAIK1RN4K/vrVXTP9V24yG +pfz6lkrwC6OSiN/v4G1bekosX4qQt5J3td47ZJWLYqWwBUmnPU6B01euHHHrjHMY +vDw0vPf/O2IMxDXcz4Ee2Dn/nrvXJGPMYAH8OIIEjedI+ZURUK3LH4vSToiGhZL6 +t+yJQQkwMPQH23KcHTcLAssgjJynTh1pI3R+Jq8bBnnOQ7qw7sWoG58PQNYH8y1B +GwzEAOBy5dDAiJ5+69IuEu5uXlwICVTq321mrRHO6OUIqQ6Zvcjgk9+TTT4oKkpS +ymQmXsDZhJHbfbOM9tnfvCisbw1SWKxo5vW/aVUfJeZfhZ/ivIx6SOYkwF4D+5By +ww0LudwHvtu4AXX3osvr6ZXZmIiIr9GhU06Up0/xJX+CzLsr0n4NUx2kYOT9uvLQ +QgD+cJj4Fb7f5KCZ5ZCzJBzJb/v2b7fZz2nT4ajfYTwJuLZWsP5ACwtX2wJen6nA +LItQkzkNCiU6WQ7fkt5xDEO3NTzKOmV2uYby+IMvHQyrVJyQ2nL1oAiFwwysP+Tc +yxJLDC05gwJPbdh+1pFhTISB9AoTto9vBTZVn5dpNYxTH/6wuzIqA3QL8eq7HFUO +nLRHqwde2nh9B7iyTsjB6a2ywbjW5HqqGyaS/iGM3DcnsWA6eWltQ0iWykbOHtDW +igtep0g1LWtKX/RgFSsgOoMVe3t1hFoIta0GwHS2Lhqy0JxNET3CFRwtqJTB1BzS +MV4mA6z5wPx5v5M7F3QrZlyK6DKH8fpPdaYATk3tXodYWxYilCglbdaTKBL35HH8 +hUkr2KWyygWZ24/djv9DgbDAi/jifdHJp79l+7cZ+IcD+3eHfqxu0vxsPpheS0VD +QAz3tLn9xQK515TV2Be6pJB7Aq9LsoCXj1RxgZZj0owi+kemVuIEmqRIw9iBiuKb +x0UWH4ElfUwpUKul4DHwMk6INh3Qavl47Fd8gPeRret+KaPbBdHG2j+x63+o1nOo +8TxQdO0hVwxbnCl1ZMLDG7XJdB3XQcWpy/pSRIge6Sj87pSjyf5wEECGjoF5ZJdD +sgQX+3z/Yq+yK5r4RmqM7g58RJ9lRvUaWprMhAiq4dFwoin+Im65hYDhAyLGRIEi +8lTRTteWGEqdDwb5dt7HmtyFIKAD5UoEJdX6OncfLp3bclCgTHSk3GThCXPqFpUf +yj+a/4ZqSi65zBm9n7FCo031NXWf083lDBes3pauTfO7wFnK9P+Iybk0gRMWicl6 +padEbIH8JojD9NHaD/MQNx+QqSLTO4maY511auIG9JrcsNFXPTi0oE2oMCdESvGW ++ZOXmTf9CJr4Lptu+dLqAKvexLsohuHh+qIb9lHHTIOjXKSokjOKfWvk7Im/VZF5 +ls1sXkXzdcOdSRBGGiFzt1E6wiYSJ3NPdGW7Zx1ATGlbPRoy/USZPbMHX1jgydW7 +sZ5VdFxF6qCJGPK/JfXPbQV0YI0k+nntc1CuubK2fdzdb/NDDW8n1f+fB7+xSrQQ +TsXkh5AM0x2GwM/+brDek+/i4/BKSjK5Gxv78nFfAzspPIPivA+a4r7khvwreEyV +clJ25qm0wMukXmXnKqcvUK1KVo7CEvM17NPd4va6UzkXEZGV8F7pfQy8h7LyJzup +1UPVqGaqVh1XO7gosI6BWy70E/shd2mRdGJNproyu1Yo2oFD/2nxSAirdKvc6iDF +8qKLTO7gT2Z1gTHYR2E8i6NTkPXc/l74fkgS+tHBrFRKU7ObYZMNWrZLScvbkvIR +2lq2R+jT3eedIA0UpxF0szsGYn4wFuhbEG1EJf2FV6+krVzF04ykfM34mxnDH+OQ +zgFOHv1LPVr4uY6xIQgDcCFnwQDwzzlgaMwPJik5TKiB4AZwNdrELQf25JEFlvbv +YOcvDxetAlHfcZ+ZgnEg/ZPzSj6gbIKMEqlewd5myKgSOF5ZyUHV5+LFy96yYi5g +xF3wuZDC6Qcd4NcLk+8l1ukL6YOrRvqhj/yxwA7E9mbZrgYU+w0ipl/Drcdsp4tr +wXXk4NOjtPXD/hSagYT+pyBtl3QysEKfse4sBjjvzH8oifajBc8Cpf1BzE5afxiA +gOto1aX+XEPjg1U8cPUdJ0Jm7mA0TkxZAH+PC0c09ec6+2GCxmi5yXA1eCQeHfnK +CGLliMJ5OgBeQ+kBHECfeEiZ08kvz0thozE5GbDwMA0KxVv+h8ZVkKWU2TlaNJac +aqQ1ijcRPlFhoSVXfKJZuDlxsBw+unUkRbgPnqWvIxZk74WC0bBfOSnkADTXraFG +whUtT3PNhvqlkLdmYrS4+fqbxBQk/Z7YTxwjJJ7bjM7o2SsEe0ZTXQ2J8W7IIwmz +jBUMd7Q+YME8lsMIyzhMxHDyHrE0kmEWcBZcv801/AYhyVaQqirsERSzf/UBWtIw +pIW71nPO/nl8J3Brdst3U9AGTWp9qNhYbmi5O5jTo6NqI0xwQmIBjEjrX10vFeNU +wH7CAPshS0DYPKgDVCICTi/XzDaRd3fIEFtMH8BSIekCBrzFnyMOWz2HrrOiiCgQ +DRr6krvsTDL/GvGc18Yd7uH7lxskC/Ui1Yo9d8P0RoYZScVwLXWlr8Ra4e6eSmoO +HdTp4h7fkpxq+g0kOT7Q7/Ttet09GvhHWNB7aaSQ6Zg6JzWPxtZty/ddRyF7bcKY +UuJKe2QsFUCZneIkrove0urUQu7Iku3VfsWonMFa96fwtTHjrMVqh7HpeduDFZhX +qtW2+XJ2XaLzh5YruWApfM5yx824RxcCJwEMrecfVWircYpM43zhgETrfoV3xi+9 +Rr7yadX1uDEPSKP41OBNgCVIBnoyKnfhnmvSCocQDmrdy3E7WYgqyV3z8tx9b/q5 +K7C+A2x12mu/rMauL6alcf1iKCKwwNJgKXFCG+tUAovCCyVClnlPXXwO4+cFQNDS +uX2QvC0J9CPCI1ZwtraECOYbRnQmC6IpoAWxnIFH3xc/Yq6VVFrP1OXbBIDh5TJq +KANpnTq7jZA806SVTLBVl0MYCL0RQGaAZai1ujPy9NM18RKNXDbfIemX/RQoQ/Oi +cdJjxx/87hOvzkc9nSURsqZh2YakRbrjb3EXXjuyG5xMPbz8WnMCWWqyUtXkSOZk +QtSUs90H0GavAYsmYlKttcEBS3ZD9LDqqC6fg+2O+lSy19S7F97XjzRfpURpmfuY +hGuDEshwtWvyaJjKoCQNYWkDbqpzBoQN6qwBalQuKD3Sh2Jr3+3LFjcacKJ1mjxt +e5xB++fpQsKZ4KjW0qsaZh7psxd/QnryeOEeSvbrKrXjtmjmI1bugar7Wf5Scakr ++rZmJZTQAlpwz6y1twN3aSVvBWOXmSNPPFoUu/t3vvnwNzF3zeDOfdLzElsj9hAC ++qnowcpIjnJM6q3rVBp+zrk7lkFfQ3x7Xp13tyxiaYWr8lLvPERwKfAslN+fGyzx +cfaU1Plk2cKgyPOiJv3xPiiy63+9wiNBSADknBjsqOeb9HVvq2/Eo07Dgt0yVAIa +AhZHwDhbdVR4bPL/M7lOlUQ+lV7sh3ZxvAPc0C9bfgMlnjfKUt6EGtMS3zKjNsOo +uLhi8bJmrewADontCMfSk+K1ZhNSddWy5efbACGTDS8MNlCibxrn0U2P42XlwwFL +lnClXIghvBiZiGRzPDErPnQFf8Fk4FU5ZwcYCCFeXrR23xup45aZ+d6vGnl0o4vw +4uWZccV54g2lz2pNK4OaDC/GyrMixhOy8BOhVp+AfcG1X5mTb5ovUyhQxqsPrjSL +TWg8ZKj7Yag+uJjbo8BYHFzvMlNrNbFDwrr6/qUgf9W2y9EWzfqKAdw5YsbbcY78 +Kh+NsYmQoL1+zR/wEye7h4rrSiVggRl5YevVs8nskCb2/VRbinMhit4z21LchgO1 +J3VgKxJ1pV6OfMiCR9u0AmoSNfpKr7VwCB+hQ+/On0rxnBGXYiMteyxpm9btTsrM +KH21fPvgAeY3lDvWzles06JeUq94igjV1v8Uqj4EwzBWhEcVyt7ICz8y79VK6m16 +KKC2hs+kSuXVbJWj6q/irfbETMnKxXStHNHgFRmJTqxrj13TfAdlRmtefX3syclL +QDDCeNY58ysUEazzISXtiq+R1eudsXb6FmBq9GRtcyh8kuzYIcEtoBmm0jWbuhII +G1MEOwIBSTRMzOk2QamVOf7MdOllJnqQ6p/YVGZgtU6zWCaeUijDeIFjIn2xt0RA +SQbkyayKPAaHz2IAjBMjGfcyB9/130gKss/vk2oj7kX3sxptzWBCmwtm6JZ6C56A +RyQwj73CdOysDo7bXUUHAWMTrE+nEybG+mwgZDxXjD26I8vXuV4FnGixjtKHslRj +nunBm7aJB9hJjpDO9K1CX+VObzHCRW45lpLIIa/KGHW77WB9VD41R7YrLEGZlm6Q +l4zyFX8WTo7HrXFleTLjfmf2QDlzeS3uod2swywJjJPqvnGT01STdxDAsjajqpDh +W2AfHVgGyrYyg7VzxOuZp7d3vqnIUPHgZCGS23sRwC8l8L0a6+9+KliD8jveZjH8 +gAtAc9jkVQHFXMAmDtKhA0sS7ou+8qSSCyXWmHNATtxSesEt6WBHNrRMIk5oa/VT +oh2DXaWBWlkjJAlVsuoI2ddsYszhrdR1KQA67wbl05XTk4OnORhil9zIpIi28o/B +r4IGoIBwpUx7dAD2NqO6t7JfJq9h4w9vIGlwBCeioQP5adxQiukZmqOuGYTlnrx3 +Vw6yavj1V5EdCICgxy6bGADwXCa0gKgxVKKM0YziaC6/Yyrou1E6n7lcd2Ad/hmR +epR4BiqV4oKge/J4HskyHc/4CyxAoPAVUBP2RDFZkDhhv1yKjiOIf0hkP8FIJ4Ot +pdxxTAaSxsLEvXTxxVdKX36IfHvpYcYDAdw/8/ATJbadB16j/TRGUMl6RO1NBDI0 +j8h3NFmZ7ln01KETPd4vJ9fWL6sADefuCZhhLW9cXGC0CaFO3/DYSFNYB7yYGOXh +0nUFun810u+N/rweKCvMFVitjpGdYbXL/RQBg2qavLQSa4nu/b4f4zaeFNhtvTQ6 +FEVraudcKwLhb7N66JhfeJQJwmm9PblOWNEIx4usNXwNArutZ38nropMtTwyRdjY +PO75D3PP2DIAPRBjPVX7ernW2igt4hdnCDnsvhLWdApHAqY2BDrN5z8F2srDncbb +2Rhw9kSsdyUwDIhDdW4HEjD8pioNWgzOh17xnhjsbvyWmpjlIVp/pmHnxTg/NWJ0 +wGZnwjqLeR2CV41wtrM7LHPOj2HupGMGFU1hYh8O3KDKxUKaQSbyFhls1rumukZZ +Cs2hNi2i0bNzv/X29PmuPjXumDl5u0xQiLyQAWZs4zSTH3su9Zx90QxexXSeDSlF +yEEpo9qjc/xAaPkGf13Wr7SvyMvWsjIGHL/aOaVLC3lCaGWQD/Kdy/jpd6NyTBGc +QUOVthWFBQc3tOO6wCEVdHpVu2JtWm+HKZIMfAp4T1iRR42s+1Vt3nvyfeTihet+ +L1fnIRtpKlNqNFkr+J5EuSSAIfHf5ihJLoPCexXAXwEnQtYmky3hddCavguQSGgM +Ni7EkYq31Rd/dj2+b1hyHuO/gVSamPnWKalU6zqAz4hqCumkKH4G9Nj5a5w1hgx9 +585iEgUH+aWGMfPjMy4E4xL9M8drKIlHWwJNbRB4I5ltqF+n4Lgk0YJtVyeju5jO +m2XckvOBGT4lFVlmyCkNFQ1uSibEhMogsDK4TY8nzuPUe6uyNgEK4w5wGf2QB5RT +rbghUmBt9HTFDsSRbldcHZLo3/wey1LfxpsP5rSdW84ZSCqwF74/BiOkS3VdAcuA +etGgHDdnbVMld1fX4tnUDdqxWomnxmhMPlqCDeO7D1lpZsT57X2X/TG3191bQbFc +JFgKvFe4/JaE2LvhRR9dap7P3PnNHgtx7ycOXZpJgByLKuUu3ZLfwwOrvtFCRELq +6w8g/dLKElaLyRVoP8brJg+qpUP7E7ckxeQjQuhl3FRhAn9SprqfWPKhOwWrZoZv +YP0JTir8ggA5/htH6U9U0yDlRM3JMnmYiEIQc+djE1vlvpLeedzys9A0Lzy8XR6I +vzVHv9HhftEHXWGGoeeoWd6TzFdUrX0m5UEaDdDTJXU0UqVShFbBT6ezISpPzZNq +Oaf48zWPeGe0dEM5UGZ/LhgdctmkWyM7trEDNSHj2TUuVOmGQjra9wzEtRJv6CiK +vKD5mcborZAOOtNxcsRid5XBhoGJ8EkFfgkuKnXPvNd5hNdiDzGlYV42dgvda2YB +AN1qukuncN6ExjnaFjAtbQ7gfmaBbBdv2IdmVHaHR+KWBt33AFlmRPBdlsgN5iYO +WkhR15mOQXia6KJ5KvYZdz5TjrJsosxwasQvSmp7VUAkVjqjli9CT/94I4gXweX1 +NZV5xWV7Spt9gZv1jpYjcW1x/LRiwAhxRdCsmoR7s7soZ/paun3+p8Jao4yT10nq +c0cumimdX19zvZ7NMZLDSeg0STtGsqPUcHgtDLJE8bUBAWIUKWhPv+JCeCwXsJ86 +w827tkbSTA8wDykmJhBb7QzRxjD4gR+sk/Gd5+gxXS96eamGDMQKiwhJDT6VbYSt +uUsdnksrcMQQiS2EHTLR4rtWcVDtIFbBWBmchjyhtZzRsOjjFmi0YFeEQ+p/4AZX +XupS48zHIYb2fwH5NxbTEUisfDj9vedJCR/EB4a/Ve4VGTiSd5UV4DJSlY7nLfOd +P0gdyWr2YBIJGZ/zeV3W7oMJHnS5GPENixiw11dmmNm28d4R6YqY42IiXsLZdWVS +rSXPgZFL9VgTBvI83oeLEevu6hmTZ1XFlmzr2xS9w0KyJfz6jor2JEfx9IMUbePZ +DMB2i1AOC9q78N+NbrtGMgwMUQU8JKW1D/j+H0aXUwv1J6fILbeOfhmeW4g1n/+O +680rpYbXbpLFAldGqY8EJvISEhej/XVSgJH+Od/gOsw2Oo6udf02OEVhVGqC4Wei +bYbkxkibFgImQ1YCdfCj01kKTi+v2lW9qnvw67pHmc0pM0+irgu4MaMIOSFVwZZx +NFrtOU+H7pQ0iKHV2AhO28YNg+9LAGfh5PsVskT31fXDlufQhPvU2ROMvP5nPCVO +SAjJoPp8SeW313UARWMCTYUsMUWnxrOmNfqWy2gL86y+4nNvQRNxj8G73AzZl7My +yXw07CLi2b2oTDYqrccqpq2UlALwdlzy4wGtm8/tdOauuGY2ydx6eSL4wQVYT1NS +xPvP8Ps0pkMj9dQKsqxZnQBUGk99sl0xOfdBYZj6mNsQBH/bB+AI1R/fKqUOKr8D +dmM6/PeOrhVgDR/e5uBb5bfLfl6TT7uQMJvALVqLYGbKkRqo+fakSKN7hoGCT+c8 +zxvledYNDCQwbgg5GoZTtcgYG/ApLbGL5vcFTR+vQFM5g5GRQa3i8WNinxL0nLpY +tGBeAOFaEZEMRwbJacE6JBTZBuhVIMCq+AZlQsfFuYhNEk6hl2DeJpS0IkJQJJbc +CfEoim9BpSJXgzk3on5xPjDsvf2AekK56Kz9I0gnWkTrVrT5xOLrtm4feotElcEB +k0rZkjcY3lC/ljaVugtVEwzlqz054s5tLo/k99rBt7fS3UhdDW7RnRsJoNGSTy8J +0xa1qJCQepG+zzd4EqyErPfQq9PuCzYUzuysp7yel1t7n3FyaIxijUMbPLMQrfWR +08Mlm+6mkBdPNQ4cC9gSEQWfISfA8hBs9vDubz87kdGlRg5X7oxQVXqXPCR8KB+y +rkLBafY5zCULOXKQUOTTm8ac71OQ8SyZ5qWENrgDgOiqvE7DIVLrEiUx/xtUGt80 +Y+0mmpUDtWKun+ErgFZakvQCsIcekealmy6oOCIURQusPiYvBaYKv4+8RLG10f4O +4YyDH73AMphbngut9H0XaYktuBZZlM+A9OAD8YcU0MWrH9ItnZwSXtzKynFMnkv7 +3ygwrRBLE/mISUa03NoXVwSxLu2r6yYjfHC6UY+XnXqnPqMRL53IE0UO5Kx+SGbq +L7JLoUM8f8DEYGMCsfy1DD8D/5HZRGXJEOxeAK5WMwwKyu9MGYG9BSFA0yAHJvms +0WNnvd2gcZ9eTDRr8V6AWbTpSlzhYJZ/ugfBgqSoWIj37XiUCAex983YQmAdIW5V +vdKxMx68X0ooB0tNkNHWJaY+IXx336WyP11dYHxFMAlpVX7B+DeahmTztg3sIZPj +VT+MQTlshW27B4ldo1Ze2vc8dtSfx+RL4ygv+a8D+9VSmCNyWB6lpQ+56GKNN3ix +PzjTi2k0OUOti/mv/o1hLKBzdcUuOdjY9UbsOJaBv4ebB5SiFmlamci6jqrudF74 +TC+HcC+qZrMGj8YYM6T1IyhrLHWbd2sVstyKjgg6HTOPKD5cARVsYnRO3AA1Dp6+ +otw34BMWE4UkwIblcAKdZJa0KPyYbs/2HtfKsQcPjGC5GTjB7CbXeXEfVjH8vgHb +CAc/HZslCO/TUfWncDfI8IDgxNPhZTUJRGF/U1VveMebG4gKs8uY1AOuUVNVHWwR +jcQ4gJzWebQqAehdbT7rXrKkzBsUKg6kwfcE/WUL0uNnhnoUYRYDw2xNADx6dcFJ +wH7emTdGOaNzR5WkGxJdeEOeIQ5QAIAeHHAsC/eIIU5nF2upHFdlPuV4tL1pSzTB +5pgrB3AJCB2vdQ/UQd2gyVNRh1z0wEIobJdpq6FWyshXEP7MBD8p9jYmXOQkkaQE +4ve3yaexA1iqKJZD2TI8ssOlQ2Np7F8HcR1xH/t6GjeiQiLBOEkpcnTsvtPW3Kzo +/1jxKthqzvNswX1R779PgfVo9KPElbauQvQf5CoS1XxwBYjEWvux5tEQFQ8pb35X +Je9/ZIFrU8X/OG2xqpE2aFzQ49gmMISflLYo7gV3AG92vtCxx9Js1HPi+BRvKM8J +dXNHHL++nu7NqH2I7SWPS2x9LTv0U3f1kzFw+KOFLx4QByDZ6/+I+sRsiy/M5jmJ +VOStjA58mKHPLPI6KdDbUnV9mLaoLHO/D9XQVAwrYs+TmCwSdNPMaSSCoWkDrQCo +ATmWUleutYGy0LnlqCVewppMakru+HuuYxLuKPZDNhngBEWdyfYjQQqyYQAcfCAo +wxam7eeedk+vACazsghDKnbb+mgPhJ+rit5V4qUe4+uTNBvoBeJU4Zj73/8NY7JP +jS5LqfjROyml16su5rDVE1DbhTQARkJE1vaYQXljBYWenw0U8JOpbrPAMhf22y5X +9DP4nXVeRlDDCfO3ZnSszsPTilZ7SWd0mG+PJdZeq0rAFig7kZjaFXQi0qlz2BPk +9VgQ9W+unLa4obZ4NV1S3gSfJ1cb1yj6UxLzfzOClaXRpO990IsvnmfxUzQoAYfB +MMiiumpk3xCheb9iBrtKKZV3jxcB1O4c4W6uGAiKFKx0NhmxIKFPdOfLm3ujfkDw +0N5I9SNeeeDDIax9T6EvaFX24CkJg/qObh0rL5OMuYPK3H0EETlAOqboGKvxRDSL +rF87IWKjFBjibXwmZHUSfAnJEIJ0o5waMcJLWoXWnIV3IfRpZW2wXb/21IXMCZ5b +syz9iAdwMNzcrC3Zsq1F8za9K6l2gLj5lyWjxdPsZw6orNfRhNehLNP/ooiozkgH +Fvq4/REhX7rk97zv5wkDcYBr8I+hxZ35j4i1jSFDgIvs3qsCbPA/0XAV6xtDfB9R +mPz8t2vZifgoWP6zBx+gOiiOBR1dB5BItwqQ2+Vhpo9B1Atb3Kn8XhyRcor/EFU/ +zYpFTB9WwQQK2BF/J6l0FWOwqY8TZTmu4/SN1GLTLFlFslsP7cdrU+O5sjOgKXBS +LSw6v1AD4CRDmJsevHlG55Sg2Ii/pwDMDj6zY9sM0k9MA92A1QO7pb7riiHXtQTl +we1wsHw/00uVAghZI6fjJ2Zrdb6pB8Yn59t+K70iSe9YZV/H66H9dYkyWSgESRuF +K9ro3lYeY/FVRF+JMGyip7a7uTRDWbIyHdJ+xir2f0Ci8SVPe0dNtfohabhVd4TW +EMeP2eDE5SEGkOw1+S0WJvSMAc3dNIG+JzLTmJu4WbPANQ5ThPhZR1KzmYXsNYgP +ePtBBng2JEzBpk39QvDV7Xxac+GvGI1ECsnATzpQby+Y0OuPC/2PFasD8m4UCdO8 +YdrwBnEvp6AijBngEb6If4gjQDucv4UAfxaTrtl6n3t/um9kqHbTEBjTl2zK5A6v +5FAq+ERiJ8AH+UPAi7aAhlNUVr8I610HktPfmyno+CyX88WMzr1SlRC5G+3rHx0i +S7Y+Pcf2BhAUARvjuDlAn+7WPTZ/9h53LPYMjYRx47dghDAfTC1TWsiqW/CyweYu +CYQ/UirLaTxIsZiOC+/nw/dPjeNaisRlWFS5Tt90GrnyF2zxGr/mdZxbbumiEJc2 +XeAVeuxAL0QFI+4i6qGo96do0br+NYaHLmd/tJP9o3N53wxJ5rZFOgtSptK13OMb +Hp/lm46LqzJh2o4/TbzqFDyM5O5vCOCsb64Vml+vmuWwML4aH5hQHOXnGS1KbFtL +9SVVpml8Gv6kcAmCyBOlAMcup0666A3F/Q8/8+kySM6SlZMubrpwHSGNILAmkR7o +DK+90/ozV7WHfq7hhKvp6NaG7dmvAQkJjf7+S+JPziplZyADiP0amC6tL/rb/BeZ +EUBQ3bu51+O8k8PyqOwkx8x1oNN3csUKR/TZR8sa6PBp3SgE4WtvyzoYeZ/OoM2M +RE98+Lc+Xh1mZpl5GggInxi75ygmmqFV1821oAUruc5lJXlUoUfby3dYvRxd7PRi +93mk1+0o55C2qwBYIeyfqpoBz7Ve69dDkucq4ChiPpK7DPSghYmBrU9zBI9MfbdV +rtor23/MOCA69MEJ+hmRAX347Qd4aKS769cfQ0zDYk1PZPN9iEo06wIX4bpbF21D +Li5x6UYEv4H7LyJIXZzS23x0ZGsRapEWxq2IyD/GrJszYCLCjQTI8XRrE5eXQ8m+ +kRD4LkOzxsa5XEXblebyczaRxhiBp4WGzvX3XD/mLgUdjUR2DH8yvthdKLJrATsm +D7QTBJY6w0BaM666ndYSMBmY1gZOTI51WYhUvZB3dLykjzGnpyzfSCChkxuqM9sP +WUm+sZq1A9ax244NZQkrmEzkUbK/RZEUVi9bCmqrkVa5SgSpcSChor2cEva459AO +SkFoD5qub7WpHnrGGXr3/U9LXhjh//5Yp5CzbOPOHDQRPi7BvTgd5deuKRkTdBL9 +OxNW3kSo7BSS4940XESmHmrSehrVzCk4YrY4sf1cVdJNbzcdReG4JfqnmKaTnlPj +7V/jTjJIPecInzXMfQiJksJw7sYeFqj2qYhP3kuQ3Nlj+GcjUvigiWM6FeesS+y+ +94wUQ+irGrG4RslFuUGSITZhuhS4oXXLFxyAkgClJOJh8c279rSApI2mpOeZUYuN +qwC9E44WXnSQIOIAXpQ7OzpElMj7zx3HHFA7IKy2adBzo2jnImJkdDAInTUlMi97 +aaAuz5ObPsO1xbezo3OQ1cooXYb1prz5vzL8RD1PJcudQVItciDM6Atei7g2jKXQ +0dCNeNW3k5KGHbyYncPdcvzaovXOp3WBDMSyxvAyKGcg/mPr3PwsD7KgFTgjnv8j +lcvSNXmBjYw2P/s8v9NkPKauORRJKsQTNqu+xUoL+Vlea91uGJtdEK7EdlO/0N25 +Cg5XuIlujb6f8j8/bEHth1EJnfa5e1oUbKtySpvjuFcSY556lCuvLDXiLkwvz+1c +IqR1fzRXnh6w6BghjcXG4u2B4mSLlvplgIkIkaepS1+fNnOmtxzSX3Mx09TJcaoD +jERMnokOHsi+rGXZ7cipn3h8JXGksRD4Fuc6Qe0KJL2raRWr0SP6OJJ2gJH3sra8 +cRq/dBmNK/v6kPMghCzRVS+0KoJandULAdyfHglmCbpx2I/1M5Vo0E42MYoq1+uL +Dleg3dv8xpc+Dtj02K7jTftc4DcJvaleIglZKkCXdcTZbDwahz52QLedtGGqDKbu +zUh//vfFDiELVtAm6GPyuiJ+/Pgkq+Hm91nT3Rpxxt65+sUr4lc4b0OtZVVgZkBO +2So4qcYf15MObc2TI3u5uS6WXk5eLZ2qEMk2C/lYfHo9fV8We8yAYX5wG8C8h8J6 +j0OWDyBwYjkCA02rq95slfOSFGGqFSad5HcRK1cSr/g0uhwtPn71OkgU7M5yHo9g +39beld0F6jKEs5V7M4xElN75OuxwWa8jM/8NaH8U8+mWWSttlefrPEFnIk31eJph +pPVWK5xrtnGxWWDQ1sO/UgbiUXoBttZ+/pOmY6B637nXN592LUphF70DzeUsyGEM +UizcLR2Oga3FB93QPSvDWeDFb9WyM5Qrqkigbzy5nVr/Ilaad3lHD+BiK0alTR7w +8r0S4JKVRdvz7DdH2xPpbymuhGXMfly2D6BS1tnusOzNLFaxzRWHZehDWrsW0o81 +R32OGvOuGTnL1Bzjp/UDJ4IfPIcLomwrYj5BXZ2cyD95QupB1dLd28e51TYDMEDn +reRHCzZZHmMwWEvmVhrNz2PGEWT4cD1T0SZUBU7DwRv5Fc7VJuW5qmwLsV11ULPY +fbookEsRKPGkvXHEtjdiTrv1adu1UfnbQ5iBhpC1Ca3Ayo9mGHDxnraKvxSv3ChK +RWC+hZFaqo1yBSInWYW1jGHHzRMymlons4NX5WbecYvNsdC1Ilt3gJ6ha/iO1ZJL +KtkoZafmHWGFXBU2h/2y/2nxlLq9wrzOF7A/9+Sm/Jj1n7NWCzQNZn/Ubrum6Ffg +FdxUquXrcqAG0qlf6mIduOCEtX3CyiFeGC1edBKt6X+Iz+G6uwqm6Fc4MJR+W/Gv +xbmZrNSQ3a50xf7uvhdXbElQdqALBhirBjwZa6lw5Ke43v7qTQmv476FeI0KwndP ++yRKMIgsQ2oy6se26PE4R0PTSNCz8az/z9fvrpFj0elPsRx43e7vqy0/NjslpmvR +cLwXNjeR8gXTkBkC1C+tw1tF1uez/vH3wph3nJ+S/W87kBtLhAp6vF/WHkwnZWNI +u4ycoItRLl6KjfshMpR70xGGKoQ+p8hIwSZXHOoQEScjhtmL2KKPsId/RrBcJ+VB +UyeoR+acDOxetKrWWThZrUHRe4Stn5Y7eiHDvJz21Q8027OZL+SH/YtYzeiIZSFf +LmRRS3RKsyb6mx70C12bK/kw2mB3tXPpk4GSgSA8I/MTfaAElegsPCvgVqIsy9RP +T7K+MbdURkIeO5lKEzwgf9Kbs5inPFNdE1i6Y+zY3j/kPjdLLc/tpGne7kwGq23N +4IArB2qDkwJrXNtCIHa5g0Eqs8AR/+7HD7W10SK3eHVofGDPgkZyN7YESNo268Vk +Mp3Mi0GQNQCCWWKrOpL1tGSdoCX+GSlYnZkiFDhhetEvd2e0FT8/NiqpcT1zQzNP +VENANpDhrXZ0WhwQp4/1Fo6KS1nkvCq1UusCQvtx4GBBWa7gbCcMSYiQ0501+SKP +SNp85OEp3+JprwbS8hNeSZ5QIbC08sbujh2mXNe9LK9JV3Zs7SCycCm4odOdqpmR +Sq4V43Yfujg/KHSuER7i0QafDKs3GoXmAF4ACmq/noieC3b1vTS9YkdddjayKXTM +0WDijWziW2djSlOdDTgxX4fbETKOouJIGL4h3+tCFUQEiD7h/FQPJ8XgIZJ0nXJy +o/lh+vm3bnchH3jMKGKKqf/73zyJLkkRaS/4/0gFIA/AsqT28Xusd5mWEsGGBcym +FgQDvFrhtjkdtDD0Rl12hh44qLjoloBjBZ7ZSmQ8l7/0Ri/ezXfR+V/FCk0Ie6t+ +ffRpnCpfF8/Z+Rc/CYhWUL9U7B8NaFtRYwQ2vo3VS6tYUEBBXnh2rAf9sj/c6wYH ++bF/Vqqx/sOivBY4Oo+nAYV3dfp9oXKNm/DL0f/fUigRhgugZEqBTJ3hX/dgtZdF +RGTtcGxVoS+Sf07PjhNNIWjNtcgDp5GpT6a0X0fwPiCbllu7ZLW69uTtdz2Ar6xP +C+zd5sGKMgMgQ7Bc1FZGouHf0Y6doAL6bJHkeRc7elbfQDF+u7P6w4JipLixLEAL +ggxQCfZlQhwPyUFUxklWJLDQBgOXaAoVF4Trap6im7afyoFKhhD2LybbwKUCFW1h +qPfDybZr1Q04JjPH1xEUjsM4mYrsC7GdzE3rt4nCHcnq1cQkDTAmT0Nwg5kOXCks +NTIGMNSa/e0AEhtdrqX/KHXWh/8VRbYNHMirGJUVQ/xQ/Hdu0WwA5C4SsEJSDK8f +eeCMdwNI1ULME9j/uPqjvztfYfRze/0D+CQDC04GryvvAMZLlKjmW6eDcMyeLsLT +cCsUT6r1gD4P76ot1iXHQgZ7UwdoXg2+4VMX5YRb6ZLVRZjxHlBI96pl00bCeZK0 +Furg5O9bxlTwGho59e8VhJCtJwfF+BXlUHN+gW8lrsFCPNo1gvfg5OiPlgwjRaDO +bV7lyACZAC+NPz5TF0GGxNgmY4ywLAkE7cBY8Rl3MmxLQDa2FHC7mjRLmrl90sB1 +ip+8PfKMlpKfTG0xoEDhY+HafpKXTsgFoFKmwQawFpTyr3F17W0mrfEiintCoeeI +Av+S5xmZ4/YcUGQb48SvDDMk0HuQv89lmmWemKwEcH/nLXrljcXUNLkN4qS/9aoT +IZjvtvrq+4hhx2Pm5KwmorvT/bc7HdDuqCkQPqhzMdYUyy3rFprWrQznYlkAQbR5 +DEFAwBiSQXvENkCj0fZr/yg5UrPCtVN76d4wnY07LYqP2MizhPfpr0X31dm0YLP5 +G1DlQRZYHxFO/QnvN3EkPVqMtVwc1KO642MmZASJThJYzc1RGnJXi2r2nntyNo8r +qQGKoIqvmQfQZzwNtZE/LKGbudQmLVH/PxXC0YpOBP1mdIM9bHVJs5RmF5sC/8Vd +9YT6a20f4Ey6tcxnlWLyJPEfcCuzZcI7Otuci7Ebys+9S65iyoMWFKN+B6YAbuCK +jwPf3fEKxONBoXWF6K1hJXDaOjh924BNdl1I9qF4/YZ68owH0+Z3ueM6HkEmuR5P +2Jjkgn9kR4Mdl4+euZvKRFDNA5cSVclxICjF8S8b/Q5asyOY1zdEYy4W+ZL5g0se +SL5EGuGsHy/dLaL28nfyup7UGAc7yqUMjQZsYbEB/ZQNXa1lrr7FUqej3JgYwpHq +8FRuaBSJa4wbEZGrwwZOmtqrlhFNvdJitEzRTRurqxG3Z5wdg/NC3vxMGgUIVIJn +ImKiFFB4pvqVxbCTKd4oopCv3j0bwcrnHkJ25/30Sq4K+16IFZk6ROIjCPYb0qvi +xIf0GJ4UOUx/jeA+JgDI+E2Az3YFYv6mtIy679UNlDF5BpWzuYHT238GFRs7Cvxb +H3IIAmi2OaDftYWDSQDS5qYFC4SzrNK5ITxneneGuiKkmZ/B8TWSulhCEJdnQZlk +WN1F8h+kX5tjJJXMO0AElZsNnB6PvVgAjS31sl1CuwpNtolcLxUo64nIA91IiPDo ++pNgFig7ejy8fADcXfJq6kPW8DJ23VKrXnsjjRUksKivW1ARexXPStujVaCe9qb5 +R74COc1yjv2dSxMm9Mh8LRNSwW5DEjeQTjOP5++SHpBhwYF7Oe2SJuZ74wvOkA0P +LhsoZxf3C5UaKuWNHqiQkddGEM4pVXHfOpju5eKtlriC/B1nW+Uuu1t6C7noa6qJ +1H7wuAkUbj8sD9nn6RC+9f70sAAm2LSF0C4+0XFjMhZP3b0beSuVphtlLNUqSD8N +QdYgPvDe4qLCbiWeFmlQo/C0NUWVQDvVWDc3lcrV3phvhF/xfz6IkL8fikhIXkVt +3Hr+i/OY2ePgbxe2J9jrsDuafJAU/9faUKnWdc5Kvn9i3OxVSjf6YmW8P4IJ0UNZ +th9lWoTbQV6IM9j/36m6pQeA4P/M7Z74E4dlZPe47wRWKBDwASogVY3sNolBV6Z1 +0nj9oYZygtDILJ55L9aJTZdg0cGvFfmn73jAnnBGicVhytrsfJyw/wMaFgDxpWIx +egstXAj0xRP4COc1WQau4TP/O4uxcfrKRBlpcgaZUPI//d8Xmk+Sr0NfxlEehHWT +UEoUFIX4RjD61hhWofmsPDSx2fCunv4n6lBeYiAysT/+f8oGKSRzU8lwLi1GjdQ+ +QQo42VGeyAcwGH6FktzjULMQ7whlpEQQk0jPvAa/iAW7obLgygTefIxKm2lxwPPD +26PpCzdBMONkkH6TkfDNoWhzcCVpqlnObE2r9V83hzif2xh2tfyUI2Gt1Zfzr59/ +tFnYeHqePstLvR9RdAVB5HaEAKKVAQVHsN67/+DkDKhcEs6oOZDStW/Y/yxRupgk +zkFqCxAc+I0DvciXsnOPP65eijgFRtKx6vLBF2aYBNSRTALSPK1ZiRfhnNEKDduv +j622+y/neRqcEOVqAqkab5/MTJYiXegC6DbJ2PiqPg1aIP0e08wKT8RDUwkSohD0 +ZxGxz8Tr/pMgJqJQyBmXDdfTlqtTnFE6NP3vY17XyS+sXLCYshTjP1eTkdHIk+Jv +MZYUt851sDtmoG3upoEBjOcr74X/8v7tmJe7zQCcP2DptjV1uVI7sovi6s4bqrIY +AdKP3g2AouEOihkdsABsG4P9B55vGk6+YmBHdjYlWHF/dwQw0tv0bb8eALynJzk1 +YDOsbqy242u19NUIIUymqPB8ZS5CZ1ZLYwkA56K87Laepniqp/nWkPzAkXN/PiaE +rwSGCifAXAI/roffp78Qv3MORISkrU71qSnvMGCUC0b5yGWCqW+/Vw9uorP3GO9p +2tDA3op5JJp6AhhxRWwdWEOUkcJqshj8xWgW/la1xAEmY9cbx0IAwyE89H1kzKjH +feUssttCHFUmazx1v1bAqfz0wAZqto63cptv8say5kVD4kWm8CnJLAtyXDxIpNlW +M84bkzC9a0ysohS+rVGGZRLPS6vI2tVzlwAr7HF/Lgcn3un7VJscg6Uqkp3aUwpe +4lAL3PiW/T5SZjOkJmSQ/YuPdxnGJAY2I3N0FcAYXQ0XcoYifv6xOQHBvintqoiv +mzzWoC/I0xBek+DX1ww1rmta+x9zdhUm4sW10hgq+j+DIP41qZ5te/o0ZOZu1KDz +0GEliDj9bO1SWniGTRl8muW9GxXI5J4CI9izjskZUQk4HrNnEltW2+uqNaw4AGw1 +mehjeTgDtLHeIX7P72fUiE/ThCXcu7p/gctdwF79mt3JwkyRVYFyfPwGs0DwYNFL +WfqYzeWB7HT3/wPzOpgHtrdH3MvVSfxODTErhH6/mwbntqPnofbsZDHumeqpVW2h +vd596tmtRkIrVks1cHHY8v8SbimIcZaoBeNSAUh0tWiqWX721jzISu2Pl6Nc+y8i +6nUMn5E9sBRFXWXt7pAeJ8xbPNBjLtovRBqVYZdhL0646blWeh96F4zrALZ5WjRg +oTaTPuODzbpCglVwv+h6FJfpACuxHYo7uevuKx3qFHHc3vuEQw89ik3SS3JDdqeg +V/y8U7s83Xqhf7jmdQjZTxFfvtirCifUoVyphFJo5rcACqAHsRgm5DdqsyQ9DXh1 +EJ4MQwjUKq27HKx7MQQ160dqTF1rl5D3bbfuVr51ykreYPq3XGbmibUWkFCgGS5d +sHl8ZzRMCkG6tQWUsdHnbIRPE2qbWs/r7kLutu1Opr7OHxFtClvCqBTyknGfWfnS +4dACzMjnf+caN74QaUxywk+grf41wtlVWSliRXG3pHWrvGVGurxAlNZu/xmYwgcJ +oGiP1wlq79UA43gu9sduKPxglrB1ulJTLfkoKQnYcagdJiTo13pZO5iZQD1Kzhij +s9h7rOz7sm6xWrcgMFR22V+QQx2vvImbZyK+snJfaBd7yByHMI3uQAWbKwl4hiGe +XyWXlgZXY9ajUC8vAxPh5lO0WHMoiKRvjxtO7fLMrGQFdvT6pJJ7UrBeOoMrUw+R +6urmLdCZz/J/dVhvH9lwWRXYwDCrSO6KeFsL7LFB6mFT3Q6reo9M9hSX+eLjxqmv +lWpKr1v6V5Ac8CWKr/3PCLpRGn0S4BeZnwsDeZ0GL6Nb3GZFwVRAkYIN/tKoBNlI +fGQzVpuUeNPqasfMCEzo0mPH7b8TzN2BN/K2/3kcRfQlRBHL2opBxHSbXBh94zuH +ZteTbF5hc1KodLDah5NTZcaQlsLTMJLo11HS5byz5GiRw8A6XEH4B2kY7NI2ZPW0 +XyisA2fGxnfv+IDqp/d1jYwaPpuIgNz/V6Z4oqsUOp0HIdq7Vbvk2Sh0qTUhxDvx +zGE3H7sW3Xy76xm/ucYjeEGswTkyOCeK9fO79v1MDyNNaChurm4+l4aGroXvEc4d +T4ITZoMU/Zwg+wkoARlK/5mbcvTntBDL9HFdyciWFUqONw8WF4oCu5C12NCUqG1i +mQhZTGHR6kUBnRmC+zqNMXS50nnC0Tzmb/DtFT7/JCEkQaCyxuGf5KYuQ80J7xwf +RiHkNrukgWxixdRPpAHYf3fC+EapE297F0mJb3+eNbyLSpfi4LdO+lC9lj8ydgxK +BLCrazK8CGSqmRqVkhxigtA7402t3zoaWsAJWEtcUeZpRcOeGMsKTlI+njH6uPtr +8WFKKzwy0W0QxDe64zg0Sw0GrBcY/zQpqLF/VLsrIR8TR7V9pYKn70R5gALBWYIG +Zq24peXnxhE7m2YBsN2OMAWsqFN8AXWNF63USoJWeoGcfXQXTfZ+HBCDSLn9NEYo +tpuRANcEIxO1fk3JgZmV2ibK6ASFf/4R/dNw4Itvws8DjpnQB9S5woOMkEWYkYsM +cz+W399lfkD5F6FZ/H35g70+yiVD9+tDDT1+JPqcRPoMiuIj4Kp/5L57Sq4b7g+0 +ZWNw6R5zbdd+hoQXoIOQetJfosj1g0VTTPpWmbqa38ncLNUN+KBTCWvtLkw2ocBt +DMci11UxDeq1jTThS1N6h0sFSEoJE4dXH0bx4JneLpUy+QvwANraz53lMhhDWzOB +We+ivr67UUH4/R8DsXEW6hEi2/wgq1U0REAuLyyiCWHDm7d+UdE2YAOGWFjVOGJj +jyIgMxCBdXe6PdWLEuoUOCxwjvwWcV/vEVnxgSYTQ4qWyLi1R2peMxR4+Fsk1XSh +n4rawRGB4Au1uqTX7XRlFpl2V1psD1q0hqm7DZlYr2wJXzLrAiAXvIrR1Ae0ejep +gBvgYCCfUPF10XzS4xm1fSGvV+aiG6TerX4obJuzZBdKT4KvFqKfx+T5+hnLilFq +/uMdYyNzPDmjeBugeViTfGMwsdT4inZtkJLFWbLlAH+XYxpq/ARQ+R+dzCELDXW3 +zcoPprDCAS6urqA6EuQ0EJGe2zvjcv7FddKB7NbIKIHic+pDIzxhiNOdNTWtEwUZ +6ijyEfufNpMvRr54lyRm160PFFrBUTUM2fzTtlHewHmdv6Bmt8AbY/nYd4LgFWgM +C8YRySRMVzieqi8dJLOibvPCvdlCQeY3KJqgPzOtpzA0Y2SHjRDpDwYMWbsj8BwZ +Bk5nqr0aF/cZrLzkMg6LH+e6fX9uzPDarUQBlWKGni6EyeYYK0rxSJWUc0sgm/X/ +PaPGuMJyTcbhXaBQO2gbTQDLbOErtXo9iXeOHzl2gQQWFtdpdgr0VoxB4QZ/AIqv +d76fzzdXG2eX2BphNhUNQn645Xbxi1KUqsB+9ZMo/BbyD66cMs6KlrNZJ9xFAXab +8AD8J7YjyunC6iBTbcEnJpo7kPA2TmVGb/Qys1lsJGUDbOWWILOtzSFCs+hg75s2 +YdkbMs5rh9p9nHELognf8QVfCfiA9wY/3ypRkW74bLkbnvohafK9FEyyp103AOjH +8NsnWcbDk/hAyXzLtx34qEQ9QW6tDGLU8ImiaekwyLJtQXb4KyC2Is4C6UKfQkRT +PmZAWHYiZELs7UR4mHIY8Y15ai5CiCi/khyTUa3Czz1nK31/jIOHPEp1er5bXAbK +TaLXh2FGIUc+ceA69HCfGeIc33Z+NLoRJ3GBmqtpHzLa9AFk6127Oig9A27g8H26 +UAkYBmYiwU9ycH1QX/IVQCwK866hhes7thiuvCu/1pHsPLjwF0xEKbHeKjOfQllE +WLhLkfNZyLFuLnibuKPY/vSicpxRpEMFJFD4STdxx9K/AT9lijXnCHlPFceQuLIg +JVJjK+8tZXB4UvqOdrKycYczPkinaSCUGRFEqrpYCTC7LNG/MO2Scvh744XJD+Lm +Abv2MqHnGFjU7XG1GZErtj2mN57luWTJ/Epn2GxVxXXZZsagr1RYz38poBqS0JLp +2g5l3SyqEcMmMU4YgYWhPTwrKLoJNc0/Z7FgTee8ZkKtHeE3o65HcVS0oHG1Th0E +8NCVX5k8IbiBXWGMPJjuLDeC/y0RH/QSRPVHNJLEF1ehFeK6SFTtWMQWU/dkZ21z +MeqQTVKYMCyvvxpR2y16D49n3xdIfd4A6cxpUwv3YSUjGVv++JSZUSjRJrD2KO4J +YVRlhPK2l90/seFEyZRoYmzNoXoxlc6TrKDyViTxhJVWtBuneNxnFhTl6QrC3w+q +uKDlRN/pMdqYWngh9Gi1MgyiNVMErsRJOiTjoMIH9vqeWMNcUjgUHQenqOwdHTah +NE/KWBP+Pj+hK1HptqJA0GWWoePhCiSzzPhPuctqG6B5lW2yQMf5n9Be0plN9iB0 +AJ+aqKn91/sW6JLVO+/COIXM2k9bZT87i0BKG1hog2H8Xl+ynLWGzh4oSzUsGfLW +XD/975fEx288E/F73nQD1HakZQ99SvSm5l8VNI9diUesMzFb6l+QmT5onqcClc0h +cmZyZDtT/3I58GrBS8qE77QSv0fD6ZAdRpDX9H/gmomju1dh3MCioT5L6NWnyiQJ +PfHAEnLk7uVnxly+jw61LC+a6YxQlC/R7oqEGo95GFhyDuk2nq6ocdMIodhE58fB +K8x1u3d+YIubxUZgq/TDgvfvfZJIB9zzu/enAbSH4Qu4LqmrU4QFLfzpkORQBLeJ +84FD5Y3B9G5sxck8wrzHPxnwO/QV4kDWahx//gOTz3M5OOIdZoUBAbOfJ8VwAwHI +jb1WymbVaUEtd3G4ju6eOe2FKnzGaftjXtD2/mi1mYcdZWcM14OxTGUAdEXOo54c +8XCaI9G2Tm9M1BQ4O23LpzQnvC43zdFLndwOjJr+MVXDUGhb2gQAJPN1KVk5IyPx +zv7NNBav0sOWy0TeEcehpe0wH3HS7zBuGrhOHwQlRsRrvxgxhFZLGsb8jvm8KpHg +WfohHH+fJoOcGDC8QYHGOWQVdmGSpcck0FqXfKBvncEjlspFsYU/nDMNjEy9vuu4 +UsqCINrpG5lLBP17PLmRB8em5KQtPp5T7mnzpAWbDYcfndZTbs+Wb9rMRLqP7qF2 +zdPRfp7NLkGCax5uQVqsCdeABH06tis15Xxrm2iAZPF2ig/h0oTx6MQ2NQgC6RiJ +fTFDXItNEOj9NMmhTc/9+UuonfyBN8uutzmSqDp8bm71DaPrvwlyHWvj9lVUctIW +Dh/daCd1zEmBbA5sXHCY4s7pu7GR+iu/bqCtqKmjK9WdyDfZUIE0tvc97B+CMrs1 +nSFDYFnveCmjVjqK4I8yjmjP3X8jR1V8ubOShFCCiER50MOMRvgn54VHJ1JIfAsB +SORLJtCuBHEe41FdAVRzH4pUup8HmwKBi02D27NthXSyED4lc4gDIvlkXTY530Xi +B6g2FWVwR2bUehAy6vFL2MN76ILPWM+5U/L9EevVqyOJpKSjePSjo3GPAuv8ZboY +dL5eJM1vBQ84N+zf8XXnnQhgoWz2zrS7JHbdhCK0f2Wl+HEgIRBo596Pkh8ZIND7 +bOqqb28X2VXcFo7QbvOSaNZcw30eFqTENTPkMPitfyyZt13H9aJ18tohbva2bq+g +Y6PZf+cEIUNEWjagixcbWwtxQpbtrcYXVqV47Y8PxpjXfy+qm2A6N9vWky2aUW+1 +wXM3pkOlBjll71rQ5jjU3jgo0S/2aCjZW+dOpIkMgLwfhistheEZQgCSEHVYEj5c +buN2KBE9v5X62clR9FmKBZExc5TUfkCezFHE/EKBvjpLZR3Y7cpnG4WyZJYtbJXe +Lh1zE/cD0f+FGDrsXaG5hbyk/zTgcEXhfTKP9I4oNFllxB+I3Cp1PKvNSF9f3svP +oZwNPqoiry4MfkI6FDklg+sch1CFXtShm0G8VWY/O1R3e6z87fbiWVhmAckhS3O5 +DUwRDJvxlukZMN+0kxYWISDmFChXtW9FGoM/OGelhbW0Os1/JLF/rY9VKGxr8tpu +LL7RcIF2pXVUkY5O6Z62P3rD9xHSWkLlFOkrZ3BL6G+NFf+vY5sGhEX5nuZKw/2W +yURC6AFRXCY0PTDbjang+ZZD3MSRjNUELgvEhtoDFyJSeIVQd7etwEP/11FdWz29 +OnxRaLpnBG2Dab+8Q+2DmVovV7/jLjqMNzeWgxMqb8HPGQcljEyOB/4LcGYY1tSO +RFSCXHYCkPqoGDNlW6xbkQErCcAPCVG5cLBuQhZR81wi/QIHYDM4kooXBGNaNmXZ +jehpZYqGLI8RP7dhFa7W9JQoG/h9N6ah+lUYnEYKfxEMB6lv8mjvDuFdazn3AzX2 +hdW/jEPBxeUujCdzd7nm+UOOULO8cYtVGOrPkCmEdslTeQYqCEHq/wfzCKsD06rx +qmIrPZmBqbrSwNyjAApRQ8cc3UXhlA5odYTiLLzDv8CgYsjasVhsjZaGCRk1YYaH +j7XF2K8uYF0qxNH1jsb1lye4i/T/rpvYkIf6S7jN3OSAiChPJJVZ/GskcBn45xfe +WIuZNTkZ+G3XD43umy9i87bzJlbni6x6j9ZdnRtkp8mblxPScfFBSAE3gWO251td +vZ7XmklzvyvH+okwxWk8JjTOSzktMERxlS+38fFk9sritjgLCKh3yY57sghSkj0w +T6olwxNx8Q8AoGF66D32wq8avRa6V6rxzlHtUPh+3vX9MvEDI5AP0zkfZSxYLYkm +5pbm7XMtYQfEfhx2P2CjGX1TMH7QTcKQxisP9HQSK6p66+ww3+P6l8Ob/0JJ8dhW +lcjOdWJnmPjkB/212MuKQHwTeIBYP/R0pV6UNcr0zqrrJwmx1c3ZrwdebRsCR7pV +dfP07vT7zqvRzL0tANmTcUOOYrZky/LtpWeU9CTwm3NJg9MaJyglbv0eV8ECsmd+ +apqrBLJPzKQlSMKpFs84GW878JiG9l+OMy+gM+DwV6JqOAcnbGu4GXGIJ+gcnjXH +0Xy7IfPL1p0F7T6b1gPKWCakBKNStXyAR/rkwaLyfx8p9udgzp80Qvti2S/aotZp +fkFY96/6jXx826l/O9o+YFLVhloAHCHjZcVrIi6DbmarfYeDZRxyul8OEpv/X/zS +u9FN0CszKAXkYYok4ePu4UoZgKuH65w9NwSLD1MrJ3/rSY2RKv3ckx2oebMsFDj6 +UJw8/EoreaK4Jd9vkOSMYwm8fYJPXN2dBPhm0sf9WvuClPxLk8tJwgU+rbArjDZp +Unbju+tqea1JCryFwrOZxq3XZ8LOtlz4NYr6bi7jMRG5+G0xCkwLHoutpoGwJ63q +xgC6Cj3rUC6tssmg5AZiiKTCAlfM/4kv8xRC4MlgP3wyuQNOpVRxITdB+e0HkMAh +lw6407M1GDsLIEUo2Me+qmEAtpMahzt1ciIZ/3Glrl198mPoZhYj6dp/m+XxSASB +1kabu2ml0MbO/RUB5x9m6MxW0/tPySipt/NmHQFPu4FsSV46nS8kuwvanqRjnliy +IMbKXam+vFYNYX+Jtutw346l+Sba/I//b5wEcTibvPHg4JVoaDoVFZyz795k8tSB +9gkK0MgkN1cVy3nH80NF3j84/MQRSKqfRieNxXOQRi9+QnCVYGgeDrYlrzA9Tt60 ++rY3X0wGDO9/5PNLc45DIPRQQN78flUS6t0y8zZBWK7NPrF2eLdFkCS85usA7Sle +r0gU1uipZm6aUeVFKd2Yp7VmsTMtAQrSbF2W4CkRueEAPmnVILJROTnNtLtdo5Mg +s5akeTlNtyv24O9rKZ6EKbgJM5ml3YGlX2pApZfOTTT2XhH9fFGILgyEHFpDrTsd +psm+PbNekao21I8ytcyNnKKaPa9OxYukjBaHcpCRpKa7nx5OqxvrXN4b/7vZwYm/ +8/Z1uhi8w90hauG5sybSIvpNb6fsjKBXfG8wjgLSHNMtR8TwsYfvJtij3qetq75t +PL60YdFlqwrbjS4MAoohrPlEFswTMGHu4Nk70zPaa3PgjJE4xJKtZyYzwOgi2jVf +0PFW9tg5+rqM68Xy0e37xQL9xmoezSgy9aXTO1nZPfRVWYOpw6oTblHm8lngRdt3 +P+gtjpb/TF2g9MyESoLqUA0mVNPGwqJ5x5aKo9/xC8pXzGLmdZnu6HaQs4pdxLDj +ifjC7qIpeS4TWRG3yQ4/Av3IuTJT2Y2SYn8w0SwkCbtw0xpOjHb/exrJ8ycWyRGo +85Bkrvi/zj2Nl0x7IPbvThYbLVtj2wiRRpfLpuZeX1sAay7m/4nG0eJGX7FKGvOf +5LK8Kjra73jMlEBym7GYHFX2uvEN52HNt8592EwrJMzboJh7IbUmS85MHGMSbIlh +6psmxs0t4/D7AflJTO4npK4QjGWA95XG9vCw2c3u81tbh1925VnMtz407FBhWLbY +r7A2hczwDhUnkFsLeplUwnu4sTND07M5JFkO4V+02lY3CWOyk0ptLbo0Mzfa7uyl +UvN3NQX3455hpzeFFuyRq/v4dOu6fC5vybDlBmyE4w1BgUfweZes1BoJwofos8YQ +srqX3FXX6dR8aeQUdH4OyOzMsrRNE3ZlvtxtujquBJ88h40QT+oG3OgYo+cRipnD +yzM1tEslGKAQvM1wBAC2Mlt1SXB53VE8OBTRKI66FY9yfw5DXVk7gUTO89onwSpW +UtF3JiR0sexAhRaRnnIpxpSP8gt7VhNxCFv7dglikcKLUSITymgW71gSqCbz3eUv +XOQuDxH4ecpOY8PtgdHY3X/Zm36nxt4bDnRC7H3HojX/Y0XkoyvkblKMZ/uN7pKY +HOkqMRYLiRfCDHwL5tk57K1MecY/PomaGzdcezXAtJS9Uqrw+HaO7XPV9dVvmm54 +vKRlVqREfgRdmS8e8ZH2AeywH/iHdjfvRwUw/H4kQSUSs3PiYKe+rfPC423+nW63 +YkOUn6S8iYslkfix/e5jiJpG2LJD0vmzUFK40EcbTTuCo5oVPhcPcjfEx9BUIgkO +W+f1HmbSdQHlEGzPCbYjILZbYscL6Fc/KxPNER60SyXT6oHpKf61jLYLQ39HiFs+ +8VufA3h3fiOCO+zfNkHflFJyDuHoa8K9kLAVcZ+WD4EO7Fp0FjRKjgXZ/Qs8VGnb +9vRJgmMgQqyM5Mn6t8E4wxqltxip/jU/oPVBPkoLE2zVjjnQ75MABuTYs83cgY8f +/X3vVxI3Nw9OfpZVEMOApJBrcMvETze1yUP4xGXGwDJsMjTzoZm78UFkOgKWN3XD +8tMMo2f9iGNLqSKOrFku2UteVryt+iEB4qJjLrxQNNfNO9+pIas84v1kDY353yQq +WWBLLUJd8HHOXlMG2jsZpwWJIKpYigNPE8sxYMazbVuDzCbhfwmlONP1kJyT2hU2 +g2uBS+V+wjgGA62yzM887dnCw1xWaZPWPkhhJvFBS0hMZgY088oqV8k24tU7FZLR +V9P0hHIuz10rTAL0v461rCPvCpqEKqXY3YiIq+GmNmfcj8XhQqM7hxWRajUBOaNg +z2Wmj3S9pcwu//3ur9JhqySUlZ5VLT6eDI0PmdCP0ff/hZUUDdEtJ+j3+VGDnpzi +ORjyDFx2uym7ILl9pJN/4bZsYKvUUVMN5r/PPoVW9GgW5Q9/gWcu6G0J7IakOYji +6jJ62GXItdkIXB8vR7Ed5UADbje3xhZDLnWB4SrB0uzoY6fWnJDeEzSuugMk6ZnP +fPirel8W/EomA5h8evJ+47W7zSBCIpAreVPXtkkA8quOk1wlj9spB+TZymnlb6k9 +FKsapSLQny6NpANmxRHeu90InjesxNvWQrgzi1NbtiFEb6U5xX3q1oD3yvSX0ntp +yh6ol/VPH418dhM1RNoE31E08lyvhu26pH1c+Qox8UDTZFqVPWwbHJt7DTbrHeRF +3/JNt4TOgDrwj1EnB0/JIj9rWg11cMyIYT13nyAywci092tamO7BEtVXHDV5Sn4V +ZBs3226tjpw5Gxcy/9+1hSPlLyaR9PooEWdYggPl2a+/srcYlWRnq8dXBLdDLwNx +dr89diadeMxDV/Ww4Q65JkGK4i6zt1MkIeOp669CvClMpcM0wGrZHNFZkBtrrqXF +UuJcL8N6JcPqkqbLgMmMJu4W3+/U4anUvLxTdySwxGFlCQTBitHr8K+/EY+4ydTL +VF5D2k+hVWOJXV0RSh75JRBXv9wUUE+FHcCAm8JafFKQWzS8y/yjP3qUhXCe5Goc +cJrpYE9WCg0N65sT3BcYGLmIqmfvmjVt4C+S3KVqrmcw6Qi7SJ0pt0tF0TBmnfKH +zCgyZeBQsiIFPjTwM6j3hpQogsrx/KZp/tr6piisea873dHoC23isHip5rDXupKA +MMkglS77ew/WE7BmfDc5VG2/DSC71nvfcnWQrC6slGWvtkhjU6FWUHOyYu96FnAB +IBm13/3GZ8KPWfnEGwZNeerfGgWXRhxBwVcrDRIWJmbIUJbmz1tktXts7tH4dpKC +w5Q0bcOKrxGS364ElExP2qE/gVzyQDwihd61vmyoiE+QGM0oj2xEWdlZuFq1giSW +aPuOUCBSxruayb7XOuh+Rw2AbfhwlFqxPPRirOR4LZJ90Q4BOg7rmuFpf+9M3hJk +t+rpVmPwy/WbMRx1fYgbLkEnrKx9R2DURnKloBU8wR0yPqdfufIjvbdJFMzi95xO +ncfdhi5otPyucClqGt8njj1bVA5mf+5eIYosSf+Led+wyDtqq/izyzt4hke9RXg/ +igjaujWgUqtA/fNAPf33PYQKhsrbLc85tJSJsHK59Zi3eXUP/4RMjoI0l0ppW/Vs +lfatjStx4lSjjRizw/S6PytoA4ZcE5YHDoa5lE8+a5lASqRYxA6c0vwyAO4RIKIy +TkwSt8TLOVfoveEYlEybQF5h6cizH9QeSWTTb7RKhkG6nnL5n4KIQ85HHAFGiQWH +sTspfd4Z8PpJWDoy5qjRDr9hXehHQ0uPzeNdI3rlAI7EbyMh/Xo1/lmIkle74aFp +7WWTB9LSHtxzkUODyaWBawdg/Kh6xeIqdNQKmJGD9FQLorR+3n6VaxUHedOpCwCC +0RV2B15CmVUwZk1wCGrj3WWC2b2Nfl0X3hc6NJpoKTnB6uR6KakB9Lui7gahegGn +2/O9FAb6RSinDmy8cKnNT0OxdjgG7DDZ/qNAB9IvRwCUEs1m25DahnZ69fy9oULD +BeCnROozLaNNHdiTYgrvd7iAPgW/hevLi3rygbLoLvxwTzsrlbwWlri65J/TKnmy +74FGY6GwDv+eXyM7iMTN0msQHS74fsZJT3zKMxXqbt/aByzV7QnDetIULQ+orux7 +OYueMr3vjWpnZyaUTBTXVmm7V1Tj3eq4IgyLOrSdaRITrl+IFi7ZEXKZ20xQKuLB +pWiS2IeNXLJxKk+KFHv+WY147Va4GkYj6wjgLBQfsHM++szSDVtpgyXVivINXfgc +uJrxLmZMUbjTf2WEBXtMMjXxTUOY/uGKRRn2mvH1+XmOTBs7FExoqLXSIh0vsSMe +CYdR4mAMzrdQtVvU0Dr6XH1iNuYy2knPmGpJhiqf/aPdKzvuJC7z9kFYUeJfLqkO +cd4AkO77zRYQEJJAeO5wxJhybQadNygGWE6DFschtSAII/5DbqYvaz2KkIV1LEr0 +vZsPCddbS/OIAVutYBYCjCo1LfcI1y+xP4FmcAMcSCyc96SGoFFg6qeTmPaessLk +yfEymhBm7igHF9bkOOdZ2qn4iN6ehXUffJJo8gCLEUsR24nleIi/lsN8Siz5EIzH +U7AQRDEIRZyy8LWg5Lvj+1ZO6FjqjNnDjg/feJQoIG1Cn1Z5IutUilxC7MgsUS6K +YnDHAzZ8HD3RBaUA8pVTzBciXMHATd2hRD52XWe4um2nsdvhJEbtMDL4jFlX35p8 ++/OHJNJckUy14MH3WZ1PmoXAQXvk3su2O0nYcd7c40F5ScDqIWce/x7OvQ0f5YHI +9cJFn6I78xsemAxDBY5l5pfgSFyRDNZgDoiLDc1ClgKOvJnMpg2B1kaX1fNhXYJN +qUudaSf9N8Df+gTugpvTtoIHExeY/ImrnLOcvPfj4olFqdw84r2v3xidSqV43AWs +EMsqmY22BP6BD5l33YNeIdhNvdpO4sQeKhFb+sEW0SLcchl/3fc++z3gI4U/+bbQ +sabJR0sZnOS/LItKUyu3nPQMRHUuYhFEyfLDRqcIYVPvQsKj0M6Xp7udBqANIsH8 +xBygtS+uQzxzaeHh5TDn8djKmSh7KnX8An1YxI6z6rQuHgB/zLKyXZ5S0TbSPfP/ +vIF4EwC4odivEpEmYPBadudQtw6ZpJ3xtXsSYAfAjkcPVGQWjwlc0fwlF+hErzfB +CUmBVe0Gqa6SVt9hAD1MwJbxagL9YY7pisllXxeB+GqNM83PApXx8DcTBgJyb2EA +gGasmcqxgTixKiY0wEcW+RnokxE91I8DCVsi5B4qkcpGSbLEVeBnYryUGqh8xDnh +gQq4oqU0n0agCEEWyVyxsOX3juKaSp6glcnnH7NGzMpUzY5hlyS3xEnz/kKEGiV8 +KiEORd9sY9t1r1VVCEanaLQNDZV/p+sMOvkTPzmCqpxgDDh3lMbMYQFFb8OaYtH1 +RSDGDSg9B0pDjeqQudma5n6sqGOK1bGoc0Jg+Ckk+vNCH2c+e4LSvcmHtSOQi3/x +fVYWz/+/4lDQ0eEw83O02+uZT1Pdy4U9Re4eqr8DLSfZ8MFZ3oAVtmO8YYnQ/ew/ +z3ocWAGS/CAdb/tcaJWep28HqK6ZHnolBqmtttYzKhOMkwBoJITmoYJeAMKXjUEN +PSkkKntvdmyMZubl8DHGOrkOAFKIDniAx9pDKrUojL+BERxVWp3g/zOO6Q61+dQS +oz0RPmZQejKfJnwzra/EOpKpKGJdBnLUyEt3ioHIXHRw42bjZHIVcZU8Czx6kG1o +l868HG0R6hbl2y8+YqBFRrtGnVjnzfWXIygLPEUuPBX31+o12RHn3QzuuZ9ZY0bY +MhMfo1Vq0dgvyV71191Zn9hcQA3SjZKSqejY88t6P0nO3EXGDiXe7vI2wk816Cv+ +NbOPiWpZkg586gkQIuFIIhcf48WlifGAGg1/8FSPyCfx0ZrPlsC2J37pkEfvRrV9 +n5EBhEZ/WAs0GPWXURL0tc7imw37bunQXyAVANwAk/ZpdJkv9kz3B0Jx1TiA5hpp +t04N/5Y8xnrgCD9aqYPcQFTg3ReDmuQP4m2sgSW6qKjvfGtCQ4tP0y6D3qvIgjQw +EsyoS1/IxY8PIcuJ8Z4hz0N7N/CXEeAUnn0dg2U+NH+HvSbRUAlnuiy77UuZkJQL +kXQpDx1151mH1uyPXsPY0YROi5/xQ6lOqhPujQMsVSPHqFVvrQ+eYY58DLppQb+t +6RDAJj8XWQcYrNcHYShRFxgxsF940Q7qZjq7jZ6EQDxEZK5v8ivyyb7N8AJKP8sh +O3YWFGk7GLF00/2Vc0IchdRYY9EsVuWZ/xbU2OvOeCXS7AZSg/SgZZCDexA+xJ/I +SQeS12x8/wTnydPoao3dFmO9ZaWDIt1pkQhszGgYfOwrynyiZYfB9/rxmpXCLtzi +eR99LOEJMNifdHVW0cEzPYi1id0QOQLhPaMO9HntBHqcdJbb15+938byCDVdv4am +b1XEKAk8G4uZZ3uyOXwsuCTcA7WJKJLjWHKTdlaP/iLoKpiYCJqdKXgYE6X+UlTd +rYpVRTg9CgyWGO0IZtXvc7ntzYgGYsYKpmrY6rv997nOiOGkPueTFE5A/lZCwsK4 +ZNlQWKoDWTd83EaAlQUySFoXkMWnhf6L5sCjevr+IiYhCjhMi6y79tN+VG8FOvK2 +FTqvAhj4x4c9b1h53pvMcLbP1+slbn09za0V5Y7JFUp6ZWtizM95pFDBzmVIy6va +/s/Sk73JIWOMla0zv0R+165k1jQ37UNAF8uLUusIAxLwh+b00axRdRI+an/akaN5 +ofgu9LKxytpy4p48lz2GLTxPAoDh5iM4HyXrqY9I4xKIdpeqwziOuyCoakHWJ2Tw +R8n7KyV1n1HpvKvkXVfy32TS2da3wovxwDwL+l5uZ6FLCBAVPx5hXm7Nv+vUK2S9 +J+wBmiO1kXvCU1CzNpYgZMXaZ2kiHX/N7g+HR5B5L+GotY0Tpo8Ki4rPvHddxMdH +xaC7AkqhegMGWB7fxkEoM4xCrLr28Z1TV3KF5DW/x+3K8bYrXeoydyhG5/KtcFFK +V4cSp+PtVy3Z72l7zqbk6HHpxVI1MlCvKaR2w2rDEtYUnvV9V2uIt1emWSqlyE2h +A4VC8Lj007ZVTkDidwMYgFKttolXxcCeA4R1zYmGyer9TF10x6kOQBEJocrsQqko +zvr7JDF3imw8LLR1lqrOY8kq7c79e1g+Oz59d7WNM4NS/XcZ2e7ULzycTWbA1UnM +WJ1/A9+8cviBYrmcMhkwhIhDNOlqWYcPneHEg1YpAk0MWtGVOnIz0wd78gKlUNTQ +VmR+3IzLWCh45+c2vlN9N7v3Ytp1sDb6rM76Z9T4/MfJOBIhPhI73skjH17VpbEh +ZlGIPmWgXzOOUtSZpNYJAe/lKr9vpIwaU+XbsgJHmbkvLHmARDhXQxt9oNmCouIQ +gBrksJ7rTqceBTh4BEOls4tUI4DHNPbtLnj1MSRwVDjO0W0miTUP90/ZzlH+PKSr +iaylqFbo7jGgC8S/Jhuo918Fz0uQ0YsP/lG+q4GQ3WvFof+QRgskEtQB07zZ5Cng +zJa17t34rgZROy6h93i0HNrdyqGsa/Cdz7T/C/ytzMBjnFLF9AellGeMZ4yU0i1/ +S3ijizpdOeB/ZzUNULthkiZkoO+5EdDMB7pQUIxzcT7+8VzNCBAdfs1poEIf0hPV +CLNRkku1+NoYcpI788hVpsXqH6uvTKK1k5lgqO3ZxMFsYE0MW3kiSs7wBDCHlXdI +l2y4uXpinRyqDfZefAkbAIJTEvi6OPRL0M1XJhIzfubirrhQWsU6zlxJqJMV604o +6I++57tU19UjsPevBb1MwxYcZPZk+9HYRFp57wwHoMVm3cjCK8PMuJ0BKxTssnT/ +kpMLQV4EhkHI3KVR/RwXYzV4RTPheoYqjw+XZ5m77ZOE9i0BLUK1fGj3jKcb8wR/ +txXe+WZFafWrG8ufvThVB2QLGyqjY+UX2R1pdHhmlEoZmEbn9SatEYtST66ZnlWl +wih9lncaT0jPawepoNBQv8Ep5DR2z02i/bisv8PBBgTVaqONbfSzS/wAWETveWCB +UprCY9Y0QP18LCdYNorbu80TNJJW5wp2smUaElHKar0JUV1o9ZUlRdlQJIYo3XS5 +m8E3Ab8mh2nwa86Y4FNO4ajrdPs0zp3FPHIk/BUHJ8tOf3prJ+KfYzb+qPmW1Xq3 +vAYVoqn1dGWfhfON5LjcY2cQzvAOqn+6pl7jpUgQaponeSrmVvxAov62Mk4ax2pI +f6CvXRm5pScgWOWN4ltEuk9dnaALmanjKO3WLR0ks6AnItVeBSPMQrrisKfx9DmG +OxMCQ2rNWLxmp0Qp0ztH5/QgRkXfahVTf6ubLkX05kq7cFgsG5acL5T0W67mU7q3 +xkB99xoFVWeyVyPNVpDgYXkS+7zRTtSUBn00XClROZp19IuyzCI7svtNywjgTb+5 +57xsSfNCE4lATNlFg8B1+QxJ5nxdM1SPEnDyIdOzzEyfG5FCtwile7BJfKodzSVD +firrlhAt0vmIKb9b9+Yw7ZLQCf5vs1wWmjPlXNjAE/esfWQXKtDDPMnzElY53Ztn +8UR3DwupdP+tZXOGBc6arrBowPqKXkavgTzGIMntaLOnS+5ekiDRBc/IeaDaxt4L +HYgnx+mgBA8pHQa5ArS9eZcOw/l1qTlF4IqgY2vSLlS3bh4kK1ddQJnnsfP/8sKR +rMHk6qyqCKfSgPLajWVNB0M0XBG1j6WIJv/TtFy2s132+EpY/qQV03Sr/5ITHQ+o +QzTF2uXQYr1PQtqR8htBv+rA+uVDTLZU4hSPZpHxplx0iDln+SR2Gq67PDcBK82m +qUCyCMtWtRMd5Uab8uiAZgIx3C6ZVCw2mmBoqnu6Vluc5xRibHzyOqCxpQcxTTEk +z09qxvKzQN/us4ryygz20OhofGN4Q57yTs6BRj7P+f4hup4McKQGV+ySWKUPlRHr +18HXD3zOyXhxWDefbSGjJ8tQBUBdfC1wspITef0AGeZhyNoStM/ObNLqzUG1DOyZ +rArSA8uSVDLEgWpeVP8SOEXJ3q472c4nkjuUPARVPG6Aeo/EGDbEAmeoPK/5Uj6q +IHAnB68HjjyzDNK0r5ExZZPjbMyogrVA2PBhDNw0Ch7r63sYXVcuhWDj96oS7spY +EZUmsf/YnJ6gWl4vt6w1h8S9fJXdpMIrRSj/aNfSRwiKex2MzF3XFGdGMg3dlYdT +jg/3ML2fwBzW9yNmTOJQ/hXDWPKOcF16V+scIigEtjotZy/cWWoMdHQOAjlyzlE+ +DNRvSQdlON9WI4hVxJSanNCXgVZ3EuaJzgiVgAGXH2MxrV1TFXquXWkPpX05uBrD +WgSjwIHGTNGyD7NHNPcNlC2lLmAqrJ6KERYvC3PNR2jV4QFm8CzXNoiyiUZQXHJl +ey0tsyP2PoZi+DcDBbSU2npTaeb2jRTFg03NiLAuXlu29HKnnga/A9RbQFb+X2ZZ +rchQWkWpAFdXwicIQUqJrGt7xDripCoCZTc/3o7dpJ9hE2d6qqru3iiXtGdjOZxh +0Mxt6DHzRM1ZfbHApXM5GnaffIhNHVLhwLCR5O72XMM1If4aHiy2F8av8zTXabCk +J/un6ReOKAT+EMTs7iXLK1suOX7w42XyAYqejco1hj0Uhhz7U2CNhmJfQpE9e8Im +Uj6ZM4UAHlxjzKP0tFomMQwP2tdgCFXNBdeZKM7+1wkN92qhKVWlIa1ZSe+ZRLNG +aqs81ASEuAkNXVGwGuYK/n4lfHfJQIfhDMpWowVhitUXAyOnZSydbThy6AVtH7BO +Wu9aC2lxYSWKa4RApclJouuw4/MaXneXIrkv9d/EcpLyVtaSuJgOR7wFjht3tD+x +ntTXwV2akWEoGZPmYR+nVx9HjbX+NDliCFTrquJFY8Jc9Sut0f6+GuELglldg//W +cdV9E87p8i5UFYl/XxyaZnuBKd30iD6YfQm8yH4b/nchmx9kAS7hSXttWziSitsd +Br6E8Fc9YEXBUgIoD5AWfSM4EdVjnPrGnvJlEzs0gYHvQCBUJkbHpgQ6O882ZnZR +JFLRaQ+U8Vnq6YaE2zmPWbYTfj5RD8vPkSFuyFAXSkOnG2m/FofKOInSX4wMVbBl +HOkKRvmnoZi2oDT4rRwO7/j7el7/RJRt5Imyqe/CcxJrdtAtw4emkfHycYSp/E+D +c5m7yZhJO7X1z7qIDJ2OA2EOXE6UmtvxQHA+XkgC8AMlnKi2GI2TeMbS0vdDJDB7 +tZYBNXgVfkFe5SNr6gVViQ854h2nYXgXGnucSy6NK74hstfEuL8IoShFQNRjZ2Ig +3rf70jn7MLzvWoX87G0AEpFDwLv+xugxoC9EFyuj6YI07WV+zhhvVdQGsR264luV +cTdTHifULYeFOwRXa2WPCQlRqE7Plt/bvbNWN4V+if/Sya6BPnir2d8uudQkdGH9 ++K86rZlOdlWON8jVskpikRZ7c9+qOYJA0UVUXIfeuMYNTgWBeFh4iyhMCM3G+yZr +wXeMY7nManBjKL9hSstwWcQ677c5bPW7F0tYlMlTCqoOv0zgm8kz0njf5LDbd9p/ +QkvqQjapojTE42C8CjGpIXMhePpe2yturYFSSmTyX1D7nUDYSbdYQs7QpmBgQ4x9 +4I+JEEBtzUJz+/TxEZIJInktCLKBRo+KOM7KaqdQJfrKK2uyeE/zhkBjLVnqoV/T +foteqMrnoFndDPCK/Rc3/8eSQlRg6ySPnsQ4fczFomNE54YYwB1dU/Q9e4zVXl5I +ad3PGLgjnOmJB3fjVewAeg521wiUUXgaG6yVXI5qO0q8ezzgHj+Mvsmf9QVRG+Pw +PERdxykpE6XQRrxWfGu0clzctj5EsntxBB6e9dltUMoQ6BUDY1NRXd+685cTSjuT +fyHQ4Nz5E8swI7pXgll0e3QqAyNCRiq7xDlr2YBNWVuWhAPSGHinXNdQc+EjanJv +TC1XwgGOETpRhPMJWbuixOBFW0R2lZbjyiqkgTI4OX+zn7kU5UgqaoPAeoWpOrV0 +5TINbpYH3QVSA0bp1yWKN6OJgqPJidenv1m+9R1gHsBgT2XcYAiPONQ28QN/szt3 +Jr4C30x5TBBbMYfLOk7M6AlV3MAz4sJSwXYZmEdeKms4iI9fn06TlSCEOdJseTwi +uJU67nVQQJq16M1kzM2e1PruA4cXeI+rfmpYDDuTFWfRCzJI3U1Q8m0OhXiOWukk +w4Rbc48LHwiip/JZMUDlmrDNCy9CRB2lHkRbYnkg19MNGx4y6Er/se5ugS6KdTPD +LxiIfHHil+QByuKFa9tVpg6cN2A84ERhBXtDUV/9pwPOaKJ49yOzAeiJS9J/L19g +fdIWd95U+Rq4Es0XjGoElxEbk+3HM8VZrql658VmUJ6QsbzS2HmIawmxyiTIG28l +SLmIeMl8JGWhsdcgV4jF//bECvk3n3il1V9tVTKLsv/13FM/uulMyEbpKVkq5Mw4 +ULlTSleXFJaqGAKkf0lHwr4zyIhP8q4N19I51+FuOxwyOVKAF/3kjXhVLdqdDVN/ +T7XBseopUrr1Ppxft+tCUeAfwT/dNTHuXT+9GT2SGLD/gdG1+/XIdfAI9KZk/gsp +ziK+tO2ocvbgILj6aeMmGQ7Ic8FmtAJuAG1T/sqwQSHaBfkF+OESlBPMkqRpCzkO +vz3GYPjF4KY87Xsn3aRtcFpJE0C4YuEwEvn9VkqJ0AOSoyPH4F+UzG29mh2sZdb1 +A/TDFdN2FwEf5FAi0LBTYzWEho3xwIZrZEMLS6bSVSxZJccr9YE+SA8PCrfBf6Ky +iGJtfdSNhz1aIbUAxg9flPmYuLGmRam6jfnJXcMKiv96DuTN3dJUqHL4tsr/+1dx +TH/VRDpeUp032sWkwYw+Df7LyQd1HU4IrkSXYM40WnlTtG+YjQRLUsz2goT/OivE +beEykR/eKoBb1MGIudP8NMPyXb9EnaM3z3B2DP4YHx/FwTWpXDClmAHFtgI0x0Y/ +3tKGdvH28k1zcLSAxr7PzBFxPPtDhs+a417B7wGxQk2ZYwDM11ol2M1XWIZoJcD8 +MaGiGXFxioyCXvWOhWghdi9hfLaEm/rFuBx8hzFhRpyLQTeFt2SnhjydUConDw9z +01eOPcVoWjbmm+hMESDKoP/2fuOO8Gwg6zOd6xGXeWNTWmmU/tEd0CG7XYrOk3zu +1x2WetHcwUmCuaBNd/o3NgmVoSQT1i6oqfL6kHeMy03oVYnS+KF/GG4OuzO+HeJE +uneyHjMd/5njIhs8YVBypAGfmepJBCE8X/YGNHbZSH7SjjB8WgzCxqLrlUjIEeaq +R1IVXK8TCk4CcfncD3S46b+pEUir52cAg56ACGdLCl7F6c85NN7caasxO4+jFlBs +laOtJ2HqZNuY9vurOU60VU6t1B5FzJ/Mfaw5DwjihmwQWCRXWC17IONzzsb/zfgv +EYej3t4HyTcOykadhx+URwO036rUiWCXBidpfUdysC1vquLH4RTQmaNT9xm2yOlY +x/zDtEWsaTA4DQj++HxEVM4j+kuJ7q99BRZgRVJlYJgRqufwbLTG2bZsp/na8CqK +UxUUVAQBef+2UjaQ3OF35zr0mKdjJPSqk6p1gE47AM/W1s3Lz+ld21rSjR+tzE3g +/RM1gRvM5NAEFmVQUxDLW1uU455sUjB+CcobbAg0jIMWr4QAGs6tnF3e1bLHCPxh +bpbiQRVesB9ufPxEgnZl1Gv0KF1qMg/+sAyTqRB8hNp6rkNXHu6laBUh9iZHrHCq +Tu7B8A9kElV8gLF5Lza1gTuZu4FZG+TwP4zFl/fnSX0qggIRq6IVI/LhWiz5Bkrj +8uzf01qD8xQXNzYRqkKdlELG9ic8WNDaZ51KBziVt2ps61ZK1COLeoo+YLPq7MxT +NXHlgLz8jx8JVvNRb9ov9+kL8WDVBSz9S3CDzpJkWV6pfWE11GpuHpbhT/zy98oC +4mPjXMx7yDIib1asYG/uOQzIQ+3nGwtXUFcULtBgTy3IOiThVNWiNP/jaZNRCvuU +c104ZvQ9sJIx5W+ptrLnpbZHmD+GJ0exIF6r5/YxXQh1sWpDH0j9eTNq5GjZkEJq +AfAAIxO3i48pGSEQ9Ql1lqVMNO7il+vGGI/GPT8iqflpVo7MNG4DLI1tT7fqVcRa +cCORWqhfNBBikFidCO+IgWZ2taSx6P4HBPX9rlg6ZKcZe+5ae4aSeuXmqTNE4hQI +rNOf1Onoeqj8XCASfVKrcOiGHpO9olKRXH2YPL9jEQSzpPzAjnK7kECm/OgOHIRa +Kf/mfNL8+yIovl+Z/Ijmcwq+sY8UaYv6UTeScL/DFzLtN10Kze3M0Bw/fgmBzBRc +PXUAvMVPciO4zxMGHXLG+OZ8h68fL3ccpfDvcu7O6XKBHIDXw63g+4ieZQFrrWwu +T0Ot7L0NRxEbccR6QOgwws5oah567+sCDhrBTrjE0Z+zBST518NT5QKw9PJKse3t +8RBoqk1KAYYOAOxqCxGR6SDEXuSBCPoZKs1wYvGTk/IR7Epv0kxIQh/iDXBswZAS +W9oY4OcaeQR2bS5Dwh1iZmZZkZqpEECvPOs24DwaznT+zRUREo7ZSDN9wkK4lV6e +DVLYcAmIzr6XKXb+xTbV6lCTbsuHiD4y0zI6I/5aUuh6dc7WcI01052xe5xe1Ov1 +2DUATPB4Dh6/l8CiwxlfS9O8fVk3IGCfAuILdUjkxE+El4FSXZjYuWhuocFTpar5 +CMPA1uUMCy8BrYr1ObdHcI7rJ6zRHNTNft4d4a6+tHvVE/bGs0uQf78kMPBdHW7S +4jsO9fhOnx0/p/noR9ha6+Bd5Y82Rq5RmrDpAX87owVnY+ckCfsITgxXB69awzS6 +BwsmURVYEalQUGPB44Dp5jBhMJ15ELC96pVssWRWSJHa8aQna+mda1cLyaWdDR0J +FNGqHwd4tuAmH/063OQzxqy3FS5lvLoxiFyUEP5HdUt9mGCo9kj1C3tuKTz9JbOs +l6TMJfeuK+/w3hh8LBL7pTG2a8d4jRW44k8mFk/639TlEaJ4tmU4OD5SgRqKQ0D6 +g2wYKS0ybjm0pmMGTRqMkyzhZSmna1YNn7uIigwb8hivEQw6b8hodSwlXzPTJWDQ +aG+hJepgVw4B9gE7q0m3isVMUSJZ8ePTOi10JW0/jkBUu15R1MALhUn0+a166+ZR +59hBTP/O8MsRvPUmYSFm41Rev35ORDtoqKSIFXq+u9XLX7tU8Nq3ibbU68rntlZs +O4R8/2Smsz5cOOwamvtEWf9W8fPsgoeqgc1RukvOqgKIaWJX7+t3GkziCUdM6rp2 +EWrvgBVpkaDUkSsEaLN2brSEqDHG8lKXlQb5r91VqCJnZYtmRu0azT4yl85orD0d +dFmjz2FCYX9Zs/NCrEX32Un6/9TO968Ckq73S2BPsaY8g270Wrh127Kpy58Q/7ln +JpAXlFxC0DFV6zUTBz3QKBa8hfH+TzlgU8WP+cNzlIXH0MUO6SitvfwWls5rH64a +NQ/FO3c+e1KCPK/gD6aot46eWknGBgDzp4YZAnpn0oKQeHl9/G3Ur6bUv5NCOWjP +v2GUXyJt3D69aVqfcRZo0h6FDD4Z65PHFbpkzoOsCU1UkHniyrOIQ0uENDOhs0Su +AsGION/mlR0pT7N8IS8Wps9hgqWV2kd2skKoOXPxtgky2NxgkoagCg+9CtgdktqQ +FD/n32mK8rdwv3eaDxjsdzLm/Aabb+MfKUC9AtkxErrwq8Y7JXVHWPeecTLdaOcY +b3BYSV9hNstMabpINWD2e9PrdOzRK0w7TibBRZMBDISkvuvtbXVwd8xK8/GQjaJ2 +6wShTgkfyKNihD+gx0QErQYQL04XJCiD5pc5cRVcGyrOKVXSjOfQEKMU1e5x+4Vl +iKhvdkmknjY2dvUBtn5iy9cjQNiMsRMzzLgs1cIdMOTeI1DGZvyEaO2+TZUQOXFT +9z/aLSvO0TgEyMmGVxnAbBCSij70LuIhBwhitcTlExTX+eGwu/Iz+bKjHeiJ+Vuq +8xFNJK2aOXJQpvdkB9hOGMa8WNAVCtRM2hmSPzFE2VckkIF3zVExpHQiDuopQvD8 +tqGuORehc57OSsgjfY8raAgY0287XUIfU2S52PSz71vhsbRJqcQNdWDH2f2+S3V2 +TeiwQIDfeZefM3RKbuB0N4dbUkN+Tr12Bm21YYQJDTzn8jQfLMeLGCJuf1F/MhN8 +Qmc+mSVjCzersmcXI+/DLB3DSe6Z+9Skpdre/Bs3QlCo9gw2pjeN6RgOJf8YyJci +ZlNneogkjApnU7jpu6zhrb2E8D7qlzptG08KrfHZAN+TvW9aQv8In6Th1+TMoAjM +7DaAk4qjgLRi9cQBSqQ4k9c/CQPXHnWYlkRuUvThbAX25TN4huYc06Faq6kjZ2MC +U8yrtP3/saMv7VKLUpUnBzlMadxWooyWpuZaM/+l6E63OixbkQg9SA7ZjYD1K0zi +51BFDubTud2EaLEKMwxnBDAFei40t0e2c7zj2rsoDKKJ9EBCI0vhX6/4CwMabi+9 +Fs8y2JLmWgBtoXZf7/IQqimtvIw1lDoy/vMbijJuVnR0vlqhZC+quG66ResekZt5 +vGDx3u4VP4zoiYiiT3cDgCI8xoJM0pc/xUlLAG1FdTnxZcKjTVLa25CnTzLr0+kt +K3doy0AXTu3XRGNsN0iy4CeYt6H37TxHwR7t9TLdquoJy20tDAxR/J0CB4wcOuAj +2SijJvNyeDgNaS3ldHJHptcr0LwW1o2fnbCP0Va9ddIbUXbOobDYQkmsgek2y+yb +v5Lb8KzCXuUanUtAAfy03pBdokiOPsp+i9NbNQs+gLP5HCBc1fJUIhw1a4ctLKkn +eFHgdeY7in3zOAOL0qAaUcmkrDj0AZw5q+Qg51FNW5IS6aOWu23QdP1Li12gFedF +/U7uFz2wWdMC+7QuwiTBChqMVhxr3v/L7/1kHdPZDnbpKtEmNnWtWDdNTeh/KaTm +0CBn3i6h4RpD2T1evN0CRrAgh1iHJmW4KujNy1dbctNObctWNfMNrf/Cg0Ip7FWU +PvOKPxXijp3Ca50tGulXDHMcrByw6GBWpcVT3cpNlSZYiHlem+PYwxVI/tQBAaCz +GbvMfLP1vEbne2wwhPLlRIbQiLZ3qawhk+hFQgnN6kFa+EqeZtoqUv0mTlhaoeam +/lj1ewIwwAZe7iqtVXKLGq4wcs1Xny1OP83u5AD2bRecv4XC3CH8YqQDFZ1s7Q/c +Lmzjl1IQf6FXUyREoWmxoEf6BtOfzwqBrIHqEgzYUJnQC+5bMgZEOaBbMxbn1gDD +of03hKILA7gb3MmJ/UT8zmRqhdzUrp05NL75bskBmATuxQUft8q9QrFSk9c8PPuC +CcBxv1Sc81+xx8xQ2SB6EgWppg6MP0KZczwOSKhOVtadus/rUS0IwjHsA16+HcCZ +Hzo4fMlXzm9QxZTjwDa0z5nRAeKOW/Waj3ykEo4mXXRdmTF8Y2P4Qg+7xUtUppik +jzh6aazYmImjQooiqsWLJj5vvRwFs9czD8FKuTsB/7xfbE5dyZ/FUXlcq9JPQPKA +09PVM3hbu49KSegAVWZeHvyXJUICUmsnZ+v67Sj1XdVubCtIGrsC6H8pllYD+73J +/Lbx3Heag8IHw0lZi0cqgayKhWiv6JclTlcb49Kwr3dVLpOvqG9CojSEkQlHf6rQ +Yx22Iad4mCK9zDIc5YiUaS025EpNE4NW8Mt6AwsZiW8Uuld7Tr9ErmfXKL4Jm38m +agHMmcIjtoUhlW2dwTzW1E6zYWqm+nwyRLwegfluUnMlBJREBhEeCwpo5Gj+So5v +QEh8xK6xlQZw6vZnFogimeKz7Lb0llEqy2rdeVRcmhnDtoqQyyCCQMyRGmLEMSaA +7kP5Qssra9i9EDz0KTdarO8U8ouPKUTY5Gb9RZccjoPvvA3eywp5uKWc9ttfpexJ +JaoDJDJI6f63fjnDC85wFEBd/+krluxWj4/F2+VQGt4DZqAlhHHiK/8DOUToN/ag +MpZriYBMa3tw2+nKNjKShcMZmkgIUhX4Z1Fjji518SrYGIIx/Cs9w7PXWpk27qj7 +v194hn36aEFmVfZeM8mDbmK4TzqwNc2+9NdkzEDuC0HRxuCIU/VnjVd8vDaxsgD+ +fHHaiEufrB0Nk3RLS3wwvVXRdTeGqbG49WBERwqGUNqx8/L0KHTYauhbuHLb4Wbl +aIOgZUbwyKi5eQmc5OqiZeIgEH23ImdllcIr2eLvUdBUGhcCFDqWC3/ir4hC0/Wi +yMJkudyMA9YbhMsvCWN7iQhtCFXjvS4fTw614NeyzSj//iHYuE/4QudBz7DzNiO4 +1vXCjTWjhgubPlR57A3chw+x3rLWh8O0RvZONblyfcKvJ5OsRtSD1ZpXRl8+gTyk +x/Th4Rfqq/2Jzn7tIVUqK84nHba7EJz6zL+af6le+gjev8g0deiPSwsGUQRrLbpo +zneHbNc/th/heD/f9p292HR73wjj9EPplbSMji9+BDLdNhjzKyZMcYJqhMAxkker +T4UqrhQORPmsCXPPSREhGLfJHLWMzIgt2VWiKJ/rCmawMNpKlf6r9yB5eDBhBOuh +43Hte/RJP0cfqscXQf0fluFbLqE7DKCwDC/WSZNbkNvK7wJo1b7lNGowqcdj2B9j +mWV2tvot2mCaK28pQnl68tQ1PLwQ6fHONSDAWzy+tkhS6//eExgwpsVzTfn8uSrN +2UTca34BaSaBoJEVYMLNlGfNNOFi1nNSgu9GUKQeLZztv/9p2kUEgTcyrFrNCTqG +XS1CGj19xy1P1KkXSjT1cqN4Q6111Xe/Y1sGMszeW766dlCB49v/a2lb+1IIhMcG +nph5VEihpQpVriwRfQUH2YhcOTYKc1/QlnthxkiCxlcoqHz+ajkDz3i8XPSHWqBc +VqPrXkNwyAlqaPEZadKy1EgKtzdSCcaVPYFnJBE2ys+BJ/3esA4QHMw4osYV+SbZ +wEmvB1YMqYkaC0xfDV+O8y2+sGDngZnbKHP/rcDr3snVAGJcrqi+VkDQmu1faXqT +izin7Rwj27A/64GwTqP9mvX0bLn/cpXQN66dTUwgXWrgrmGWswrOlrrMjCrKIKlG +X6gEum1NqXhu8tvDKzYew/+jvi2yGrMkaABE9H4aJ6VLWyuU4x9WMvIUT0UbdP0p +2lctp7CQmoYGD4MLdE0Fjga1MHuM+csUqegrjgaKjPEI4rfmkGQCCT8QrC1thAbp +x3it9OeI/6Z0HT3XNgbL6GIMs0Q+u0mwwUBf8WjR2lnXeJ1TmP9vuklIVUs2+fN9 +/yfGyWDpIoSikaRSz2Iqvd89ibanHLkQj1tHihQFFBL0c8uvMq/NRqWTxo6MBMsa +L5F7khDmfTGyT6IbCDvp9xI2tD6Qpmnl+k0OeGuPGt0HelHIK4o33mhkjC2280c1 +ztLB/IlSVFt5yP2gbqy5ap+zbQqF6okioK/xZqKjwR7jONffIAKipa1iOsB/On6w +enBWAniMbc6uJ3Nyvb6ACvaMTL+OfetRzzw9kwH5g/FgRnC8ScAFrVLjE/6604sl +A2Y0isH1+RGCV1CPANMKHtS3yAOcTNSxpf1kYSVJsrsWgnnGJW1sRARmmtUzkNIH +4ToPZCxPDvnZpQ3cj1A4UZJOKpl+7Nwbg4My2wf6drNvpAFlgqfDMKHjgZd6Oq4h +twwclt2TUBQSn1QBNFzR2YmqH79ZHm0b5JRYDIh5O+1ummz7zu2Ai3zET4OYu+1F +/nZ7Nwvf48rS1RTbv9l9ABecgsWHQeGBfdi1wUex/2LdMh5/nn29cWZMiPr2AC1I +fUUQqfQ2PJpsG+X22Fyzuba5Z4h2y4mRDKfO/bMiegcEM+sO3bJqQ26NhYDHqzi/ +MJLC3O72k/7TABN4ksvGFl99nVrFSHFdEOc0lzk+rGOyb5dyxs/bXD/icTWpeXes +wks865BYieZy6+aHY/vGmQ+PgGH8YspLMKM5Huue4BXY5xjxYjkVAudyaGmIu0+Q +p1xG8qxRopItZT0BiD9iU3Hg4Il1UXFZ8yjcIInas38lwEzUAuwBbyc+h2A99fAv +bxiye0qyMMleN5x+3mh1B3YhionjHnsRdHhdI4Gjr89ZJC4heNW4ArH/kgxcSa5Y +PqLJT7WbuPlAwJp5vMiA9dT3eCNU+FbqrcH5oTfZpUbW+ehcWMBLjzECteya6LpF +Sq6zIwDxoKtY3RkIbtC9316brDEW3BYoOwimchG4D5UGIxMmkZeBFzyHCP1Ddkp1 +0dLCrRqt2yoHWN+XFaPB7dt10N3k1u7wsK0e1lGYLwXvlEbCeTlI04Mzju7QKJA7 +oWZvulYo3TT2xTabIgldu2sdDdTq+zFmbr7ZY5r/MDlbdDCtuXm/Ogn+P4w3Be49 +CsaOdzBdEmr1ll+ZCNUc6jvzaBNT9x6XWG0mggima4Is3FCVu8SwOCFKbBeIHVIp +aaMU30nGrwv0YnI38Tr6eMy2OjtBOEnDP67PBdq1JM4uHJpVGYMi+rJdj1fxesWg +QKjtI0TjR+TtGZKodVRhVwWZH0uY/ZcnwD1RMTVRY9hxqj5Sj28MLD7Qz80wNBi6 +K8ELXGrwd/WPJgsxEZ5pxon49egtAXYj2zHFoly/8tGo6L73cmNSe4W6NKqUMj6r +CsM0WUkAkT/ySGWbWvJSclxBL7fo5mX15944TD/LGlw10sFkpWm76+pVJJ+U488U +m9V/uKq4uPiRugy4CQnCS7v3Uq5QMEpy/xb3az1LTX12zvKJ1c4JsfG3YXtZjC8/ +a/PkQU1LDKYiE9u0eszU/060C+lwAl/amlnO6n9cRuKby4vIHS1yxd7vpwzC/oUO +YeFUH1Jt4P+yvju3IlCVfwdZpnmrhWgVk/SgAVAlQ+nnMu7UpQJbao2RI6bCzTaG +cEXofuqT0KhTpMlUseZBVcCLU0afzBUeUM4a8Pu1c/MtTxbo6gvyZwnbQ5gsGoaT +eoS34eS5VTMcdgu2cFJwx4G7V1gq+ZR/w+psIiB2yFGpjIBRIdVDpdCud9H+qU/a +v4NGc4g/FyKA013BWMqTwN333m7XAhI2MpQFrwww9zeyDYgL3zorv2CaJoMz4aQq +D7a2lVvBF/IbDSkG+awtIoI1zN/6L+juSgHQUucVeWe4zLKPNh8KMNWj3y5e3rws +FuwjOmC6sZmBRJT254f92pVSNgJpQGmiNfBbgMCaY0WFpEnjhw9etV8Jsk3lwd9h +zX0/497/dUhfaliEBygPPVr641P1dKYe83oEv7bKUYqLy9f4D8p+gJnNNr37NYR1 +Cpbg6UGq2aDoSHod5HFBrCapGWZJ3bkw+a0RUeL+eRmPHbIBnAGXodXSJmZoukrW +siH6t5oLVTOZTIGW2UFZ8MZ7bCDBmO7C52o70gXuT00YpgFpElEMtShNhUxFDAue +LyfaV0qHHPSGh3Jp9wKmjH5pZ2onLs33soYrJbqMKqWkdvsCwGKQ8YPMoZOZdYR+ +GR8PldBUCw22z2eCwvmi4aPN2hxrJbfCjGlB1tlHOP359TEXpuuxALd9lOvFcR7U +IUY+iOhuNbaMyT+E8NssBh62NaVeHkXoj1cHsbAf/hiPjh+gXb/NRC/4ZJBbDQ8v +z0FIUHU4qoq6K2kFBf6VcKpR10/YyDw+sGYp7cU1ORDP/kfMpJN7aQYLpnZe8+H5 +kQmFJzQCxn+YEYWvLVCqrAUfl6JwETa0/KFMxxUlqzYYIRB1xx+cjc1IkwNExBIx +1HCqMYODLlX7pVxS9GVZ6QRorzPn0PscnXmCXlLr5kXn0d1cH4bHEZxypvecV8xg +gqIoknfSajxIWkjXP1qLuko3A4StUXq+MnxCuyJ3SIQ+/ejedjlhCDHBtNcZICPD +gEtlNbqsDhEas9/8cbR9te6+WVNHe/UoLLeDcR1AjIA3BqGTbYCfoDdEDO5E6Qeq +qZyhV/P3qxKS0F9j18e+Gb+ajtM/pDPf+EsSIT1Al9++i76l9MqLKPCN8gnKgdzi +z+uv5WMeuLQIaEo72qp646yAWQb3mSBI8Yj0ylXAvGCzzEOCcD47ohscosU8258J +7DMP9wNpzrjGwOoaB5awpWJar8rDutDxwjU+TnTczwh1mgiuEecHIqeAgEU1b8eZ +QLGV3aOJhzvsKP/SuvR+FBWSh/mS6um7deshJAJUlIAmDlnlCThWqw+IgnruCNhD +lFoyt8uf4vnN0QF/PRfHmtK0RyetWBxXK1aDoFLc6V2Z5Dm/9IFSmOXPl6cHQb1N +9lBb1PDuHWJCrjsWdtqUTK8QrY97W+GUsJpSS9X2CH6gvuSAT2ECvBC6Yk4gTerA +231xliqMVGIXl+qYHB9BmbXtVLakI/agN9uTQfFAPVzdVXZ/QlYbxNkJ8wwrboki +k5xa4a8iJnUemzl3s4PXTSOzvuvFaMBTiH71NcquqBlKWz05Pom8ipE4SWnRvxpX +BSykIhuYxutCfqZpKAQABkVIfDjDppGs29KL2/Fd1G16ndzpWebXOcR/Tu3gMyGZ +dmebZRwG5DNsLCAHuN7KrcodFWt6M3Bt6704Rk8oLLddGu7BcwKvgLqYzJt3weo+ +IHOZ7/yA5Zn5OUWyAUUiRAIpkgV1MkPaG7bN3DvusnUJ4RgSbbNBhBgPAxvGSoBR +LrvMxKrsq9iZfhZFV49cBgGqXBVh26s8uTXH51UbC7dy0HAkKW5Xx30vH54NoxeV +AQBmP6q2+TDNp20dalYnRDOwI/B7kJIORq2BL1ghgffJw/024ZHlfSrZzp63XnJu +wc47xf/njSlAXRqFOhtbC24x6JELATAImqDgBrck75/yHxvn5y/da+iXw9wIns7B +444bTF26n1rAbm6gwjK9JMrt66+MnLe8rKjrxMhATiFur46zB24Snji7Mu0JvfAS +PZJ7u28JttJZuXEHBN6wZMY8eElSkCpAvPC0in9OD9T9knstAfVJL3dSHFY9QygR +AtvxgGL+ICW3xnXFj12GMHgkpCtcJpz0dOHl4YYbP3Sxj47+nsT2Pbwn1tRKx+ud +mV1w6TAQWO/vAq0TPxPIMdd+y/+lPh+QZRXfyXBS7InTuHFGojMxjf5ZDMX5euLW +zhe2ALOSNTkxQZPjGNIJAVAG3SMinymrNbqi+wP82UR1DFwVjhtJxGY6D52bvwmv +k5ZvlKCRRVSQfLaPEATVA9X/1uXUpt8IXWn1ndUI8+VW4rZ3txGnxPZiyG+0M18N +jASAMcFmV1Stx6oz4sfLbussXYByLwIxEYGX48M/4rhnoxhNe2KfUsFbfDMcIDyK +2wpysnp4aYlZcGExLoulOA0C13DGcuK4Q3UVTNkppdo+fFGPKAPFSRS77TcvIA3L +MT5XPjCZ+SKaiUacpUzST5XPPqcDRHuGiA+H3pKdkczu76vnqbiOUygpLnkh7YaT +lXXcA1lKxBHKxTa4tYtxKTcC1eLXFkYKAKN0EYcTA5sY4dGmfeUO2CB8NSzDnSqE +RWSBtMusbH+YMIVkfwC/YolCCm/6T7iBjDu+KglEnGfqjEwjk16O/E2fSChIgtQH +mTWfKhWK1z4oGJeAC2lhijAUfHHJ1/Fk+ZDrosyRB9jQ/rNfBEVkDjtgkPRNDXV7 +8950pCu/0fhxld1AZz0JpTKqrIuDZEbC0mhf/ac/s/NXO17MT0JltBUSnnQylAUx +/ABEGy+LwREfBV+5UoE3ylg3EDYxf+bHLfwAYMbOHMF+p3Ak/aN80wnWkv22A2cW +NE5Lt4YPZY97s7v+PUu/gLl806c6UyrJ23ewXa+lSHaxyrciNEJ76/1GadW0GaXF +iizWN3dpUwCAzU1MVscbs12Z2UmImIQ8kL+s1iFeU8YBk2GnKu3WxCJae6EjNNo9 +s7gtj112PiVqC8tGFLUGGv7v8CSjpmSj/baq8S2j4mACqv+Y2Au8wSvFNeEqITM7 +hRzrMudNgYv2p012xINYUqv7Q8XSTidTbw2ljdmw6hqGBEcuqOkxhZ4Uy7BkxgzL +Ai0vr9y0xLHhqlH1AbLHv6kQzuhlokZoVm/zMHXZF2bDk4kDgvbUDrMkdIZzbGmI +i8hcY3WyCXnH6f0vcd8CYQ7c9OeJWKXEkmg3Oebxh61G6tZzDU2rAhpz2aMYymMJ +bDOcqV3JYAFrPNmfbLj9iJV9ndvreH/ULbs2z54jugwhP5HFA1EjuipiChY8BYHx +0aN3noy7T2Jnrgt6N3JI/VeelNREePbqRKt5YM90cw3vAO6t+SR3XgN2IyUmiQnq +sK4BLFOoFv4XNX80YmyRZzhLW2uI6gmWgvdIrC3WaihRyth81z0kQ+DbzImzxWsw +zaaknUWNRiqYUZ2p/iGfp/2SM3nLUXP9sFP7iWeXxxB3LC2lz/k3OpawUBiN+z75 +MvNxGZuYuBvt26Vx5ixx3PyyWoRGgJ8Oht9slW3Lm7wcSUKhQ5vr+LhPQyjKZUU9 +b7q66D9DhCxHXHkdt/+RF9fSIoTQtrQMjCEb8FpRId+TKwo7uK64JEo6geIyddzg +ddN3bRNq3WMOt5sZ95WLT68aYFIZSZXmyplxdmLYnfY0ma+6Ir3Pzn4yQbpltlDU +RNx6GFCbrdNfmjxIi6vXMZnpHKuKCs0xeZ05OwzYSgD+RNSdihvlPWn/Y5EEFHFq +EBSMuBobxPmiQYqukaz7CHxD8xqJmmgQ/w4xydCx7AOu7FS5xAH12ObmP33zzom3 +j5nuRjY1MHks6KQ90XfRelTwv4V+tfRc+2u0pUjpw9GJsO/gc6/HhieHZnxnGftr +4aXiAwOGW0yTqo17cvJh2cEqfpwfG3jCIaytY1N1Yo2kjTMdMR0pVwR1mbCqvP/u +4aZ8v0YdgBQ/NJJezIPIqfNUC3z/f5pITawPBa+Hp722zKfRR/blOAnEDCgSXfON +0N7dSb8EtPOyu3spnIMR8jLzeh5H0pY6oreR4LpvKO9+bl88Du+hG9U77ywfbUrJ +Fl/EzUSb8MAcScqVAZakfhB5P961AGvJCpUr/pdpFGFSNr0Dm8ZYvyoc4oCK7JDG +8dx3x7posUOVgUv2HM72WHdFjfehFq7hWF3kcNn16sOj+gMDbbSj7rlJgrLxssm8 +55BXv8D6yCJW/r/l4x7Eo3y9BA09tGJIiIPPfcY7q7stbkaZbnVYva+uymod5QyT +63TO5jUG1kRf/yDpKt6CHSPNwZxWjaxSiDX9Gj8L6c2IiqisZYi+qAwSsDWUV1gU +4pbLpfTDdjD5wd5HOBrp/9hzH9hjZcyPpYDMHtar1IQbXWsR6t+ZhLqAEPHAphIV +oxn6vNp+iqFOu0rv0zCYxUWO6Ne6rBfYEqGbMdOFp4zOT2xky+WiSo7v1wmU+8lg +i/OtWUuWYFAWLkjbc1ulY8rN2fFLwXfc/CUnnqmejJBHK5c0IwJa+j7HgFO8jcmj +Tb3XnlTwv2RPUud7rCB3yXskG4/VrwQntyQZCREUTsNH33Oy6MO3NP0Vr+cMvZ4m +Wx0+Iq1UAKQ8fkVA/0aExK2kWioqZPHyijC0TCIHFEnxvrF2o1scP6IAW4BuME8S +zymEVRakHZXBhV37+LthoC9ipHdAjNSco+BR/p089bD1jf6Tu1xzjq1jtbR8F3Ld +9zup6zJ9w7itC4oQ+62WXavF3IoYmJ7PRyUh0+6/ZhPeQqorKqUBKHKbXXPWJBl4 +zJaFt042hrpWrsVrUI7ZSyGJyh8sr92eoowgOWx0yLSOwIVEW1n1jQd03MTP4O7N +nGoqc1D1mRyJCzOsAkghtugAaakixysHL/kjTH75v9Ljv0Mi2WhXxWKbj+6zRi04 +VMVtYgA/wfrIJCDf1Wc9gF+rD3jQTnsTaLURN04ryGkwBErJ8YDRdkKIXoHqjo1+ +o0WIb3yl/EKGrm9NdVD5L3/knA6MYl/xM8sVH2aX1WuhOcmjwVElcUa3xx50OUNY +Bne0/DhyD7ZA4aXLHtGCmnO27ZaNOd9O45E6g/SEejVEk76YZVVi55TxBRUryHu6 +yKJkfZu8umQOcrPh8Zhj00xABa0b5G+w2frIz9dOPj4dK2vW0EPmDbJngGgBxN7y +eBe80+x4QkNKGoNAiNNj2uA8W9jm/UiAHvpxgCkTYC3Is0zzyFLKE7wEskKcA5xN +6LWrtwK9xKqymiQUAGieKwNyAz4DA9VxWNtyErIn1cf7/oNZgtRrroSZTi9Kn7ZM +U2VuAeSrrTaDfLwB9mskvtrQCx9froVlvq3rNcpzkBBLNhYVtVwvT0kySQc4BKQz +JWrh1wvJZtqf6uKwg2eM9gTuuQ2J5iFx6wf/rfghVxXmRd1fwA0RfSD171NsDXqJ +Q2OfhyHbNRxK7S5L6bRLH6OvSihhJDfqF9XUEO/uFWEc+cnsNsjiMrIn3LGy5BxM +sT+yjTn88JXrE3g5DRnZJxEc8u8ZlnLt3yTqeqllDmaZr46ZD6j9hYBdSPisBACY +nm3wwSLUEF2a3vOWJEv1zNGfs9TCO2L0kigek7SRCmGHJk0HaijGX3856utHrmgP +RHjEuadaXi4KKIszwYrULalKRLXsCzYkKXudE9z4w9804CQ5cZ8NKO3jOcodZ3oF +aeW8pR/iErIpYbfrinZYdwsiSRAgWMTQXbw61YlsPvXSpMI4Dcit6rkgOWl2Q/BK +FgwwtqPfE9EQ0aulYSmViM3H4Ak2Lw3qI+ZVzI2sLcEO0nGONzjWb/FFrSOGVZQs +LhVllJmq67YOEhHhUIJUr1XTpafKfEcvGR11qH4Fgbxb1up8A20GJhgOwkHw6/Hx +VPXuM1ZY16h2/8tYlQTClUoLM8Q9WmdmtPV7ag+BNqvVjQd2IVL2g9TwbpZiH5L+ +H9B7tdWw217lwceHE2tVxai5OKlX+4JTRpjFfnhG7/V74V81xkjQggoVg6a74diH +ARUdMC2IjC2qGchMFzb7qml21S0uqgSy/NTHAJNsoS1v6ZlwBvsNZT+FHIK5b2xz +uRpQtAm6E3m+mgJBT0bxuHlidZO8dQ1g6VpbREwwD8Vg8nF5tZBexwlGLIi6zuOc +6gDdSY+qFCSfTy3loI+BVl8BZYZffM2AwlSTyB+5jdvHAcPb+dyu4N3Q9yjdxRel +n4W+XzT834yITYPz4B2RgGtoIqTMlcdcfJprZUKAydLyDquXLdFBev4uhDkXQ0Y4 +3XkN/PyFdEm7Z55lSHboxeZpxbO3u+2J519DEVc5nPSOVpYukZ2WiRZqhvuh5msu +Bh3eHjAIj1USfjzifHhobK4MIlG36Jpu2bcXqMnacfAbj09nsvPLj4yZ3OP8YX54 +VDkVfr3AfzHYjYDuh1RcWfBmM/p3/KuOLZbOmfckm35VxGIyMUtQ5tjgcuFc91/q +NWcexg18p7IngnDA0SlHLOX6JRZmiwnJ6revhBb1rqrGBzFDAc0E9klBTtuWUEqU +Fg3y/KaktuGsVjkCH+HUeg4rDY/ffu2qOuW9e+mlvMMcNvKk934crZdwJBDLorzA +jrlrQ77jSmcawxPN/PfhujQ6Vpp8s00RHiqGnLh1eqANlOtxKyRNkx9a8QSxqH3w +J3f6o39zUgo2QXoMr0a/S8ETmH3GdNGN3X2CZSvDrO4RWlna5TVu5th6BW/ttPQY +z0tRyc7J2FDh3KTiJG4tvS8uwY+fQfxbUuChr+IPkqumSUq9RKd1b15lu7ZNG4y6 +AsgXUR/TYT/PuwAObl1hc+FDlCmn3O6kZ6KmJUL/QQ+y1ITgo2bEB84t9Hjxl7GS +2eRLDTibEcW0qY4MhCBl3UY8HpWWy+G7nT1+mPNL5Nh/36XHBh/XYKhCbyxoPAHH +4nqX5kx3r63nizXxzcr/Jp82vhijA9BIpZNH1nyyihXT5lYxu6QbwR4J1A1EJyF7 +SqhEee4W1CpTTuLQ257n41PAh0km2V6Fbf5EbG/zDJhIdpxAcTFkRWzroKZsLpsx +qBLvZJwVXX4VWdvF+R/udYdrKQhHfIbbSERl/v8SISyTUgrurkF6fRRxaKH9lRN0 +yk+RGbhluxteAHHpEDswZx2yNQnxOxnENoF4YszhX86bpmsuUY0jQ7M+vU480REX +YVKGPiUKCFDUMjIdOo3U6dFL0vCJvzcHhjQkdb0lZJ+oKUj753OSocDui2CS8O9V +SUKGovbvNYn+yVEUBXSQE/IuyZh8EbDegYKQ+VD9EiQwpR2gFifcJEEn2P0OzhB6 +6r2+SbyqPzeTiVGmZ9ZdK4+MRU48EQqNoCgjp8EUqRshUVbc4m97HcARKHl4EpiY +e5T1t8KoiezGkRoniY75IZwKhwpfpNjEqA2XALKDcBTjVI1CR22aeN4IM2NWQp2H +S/6VdnfMptilFppBteCeoRll+51E88LlOHG5X4lDWcd3RtPsWrfJQGJNohC0gEgQ +FkGtY4gN+cnyHyxYQWMykDpT8LLMHZSqbuKojjH2/0Dr3d7YxLejpjtbIIzl9kD2 ++OBDMxoT/yDQP4xBOEjLMj0Qi97DY6HEpc4d0DUFbodn/C5CPL2Mv+LSxwVxAYHJ +Qq/g9pt0ChzJOKbb3+ba20mje/zq2jZ/6a9nazulFV83uIQZVaWtAVJzsS/s+oWu +Srh9iE8lRuHhzMZnSogEIUG+IF8yZDTzU0nEsNEkp9r5tcBtegEvnVcZZDE/xEfl +pk3I7NSldCIb466AGMLwjSGx09Pj3SmhjViPrAseMklr1gT0LAE8NiN/zALyDuCa +NT3LIobWEF0IM+cc2mor22wEJiWaGdp+g39ZMhJaA0XYxTf4q35Vu1ibSomlhe4m +8aQtxfFT7fv86T/Ll7tgnPLzlzhd1yqrnAIBNjBlDeo6KKxXoG45i/g+ukKAG3Hn +/XdtEoxU3PFbDcEwZGUUm4pzAPdTHXqsBFtW4njU2PL6/zpIokAE/hsMPk2hYE8K +tiFs+9uJZv3r44Lgz7A5y8W4lYGi1peh8ZSvENzXDNevjYo8yB7ix/fxz+G78V10 +OYySFsqRV5MLYqvPsW5+Tmv5rgI8ky6Daot7KNvGPP9LqkyMaG48IhjmOHrZMCjq +46nh5M7aA8ThaanXvYdS17q3FIPYSYuUrl+PhYbxnQ+jX5zEQ/Jdp/Uig3sX4pgw ++MBDH2qwhokxInKJ3GQ0gAh8WNsm/dJvmfaa0qNdwoIH2pdNWLSwBBxjyO+G9l2r +rFHoKJnOpUbwHsT5TZrXi/PY1jlmdYRcRRd0ufRD/XVhsy+LKscblHiFWJ6tc/Lr +9oR2xinJodE+F3if20MJOiGz+NCCYmL8VvE4KNHkC0YzUDk+tqLx3uRD6OIMv3DR +Xy6GxEtpccVZStzxbKitCw8Z8ZCbzqdvOxN1ipO7LPQtw5NeBMtlRLIFzfNI78BS +IPVnZd5FyzpLf/xH0J7eL2gWJeMQCqApYa1DEqX8f1VO9INaHjqzUCTSYLJc/N43 +ckYdHWBA8CHIYitaX+eX2OVyTwPXy0z9IWx/FZW+tt3987Vb7Ufv1QJlzybj+Rym +LGLONyHq7TuYrN3ybYTVPb4rP9sGfuIth7WGpOZfhUT6miYG6yH7la19oSxFg7BW +9J/TCOiznpfJX25oMufcCp7CtLEFWXrqwfkYu3/jNxSJOp6+JsXiQ1iwu6LOvqmJ +Y0qQkzcwkXnFNmrBE3MntYnS4FKERhtcjDvZjF99KfRkp6COyjZmwAE/uMsB8RKT +vJry5hsW61BGbdkznjlekh6nIp/IlXsTH0NZNKj2GXVe5hd5Yr5t2zvl1ed/Vid8 +JOd1G8Impm8u0K2HG24nEOVUov7zqPZxowhdLSqRjvlWTgaYJQ9OAzuPAqMD/ZDA +WrfvfVHnD7yP8BF9FaWW923qb2VVjIj4Rth09uia1/SmqzHrCNxfamnyuvZTQKYd +Molr9VKwuCvJjcSkiEocx+RrZzszQeC3s3f8O1460JqS0xpcRjSrM4xWVhjb7iUm +aIY7i1NHuVSTtz/+NbaThcq7+BMa0c28uDnHByaQPC9eBDLm5OjcOXQAPYDMdg1P +kbpxdRb3z1bpN/2JhTXzS0sUsS7IJ2KvXiVTSBX6oCmxa+hbaEvynDuy1PWxq5ER +T9xy3zuIzcuhCBanLeJnAUq6CPjxgOpwZ67uayUpSZvXCO2TUHW9prEm0ijg7FAM +SRenwFAadeodcFBsBMHNXvs9EIjj1x9gK+q/70J14Ss1vHGb8q1KSXdoz38jilj8 +8+WcpfHrxXYML7bcVIM4R2ezTYGqeO5ZT8fPIh7txZd6yMosPbIOFtj8d8RFVa0c +0BS6E1B3FLULJjBSQb+W6IyLwidsTsTsJToyc/clbLX9Wa3iJ0cyVqCz4zjB8t+F +qB8fthhOMXionKwAdrRdZnd2fUTihoSm+kqEA89s2Pu5lLrtIMGu+o3r+SweEPd+ +U5kx7mxgNd5fMLAi5VWyPB5bNiWE85GPfqJfq3prqaYKa9vQWW6DdihALwJiK/Y5 +29J/EatICJvIIxsHSUIUw5u2CfExs9Q+sy48paoY2cW//yD5uWk0nWo2yY9QNvEd +5vY8vab9cUxd4KMIQ65cW4hsYTe4dAUUbD1tX2WID4fpS0fbyYY+cXaq5sMOC0bG +fcNWWZlZV/evKNWk0xEnbuLqTRe5l9vB779pIbBAYmT9Jev9qLdgHji9vON8or8y +VVn7r+g/T3Gfu+WjXfiiQvbcP+YqpCuXL64Y7P9xNEfVCcdY3VlFS/ApbCyIWZsX +pK5qPmMOE2tx0+scVMw/dmR7ipkdxX3WigltJUy+vRoGSbRKCQsRUhJUXCtRfj49 +pYYB9g29g4B0yP5Qt+Ix25aBx+5kEcB5iMo7R3l/EtDtvtwZeogxUFmbbGeHGEmg ++voC1Pzh/ZK0/bbavWo6YDcMxNm1KzPFvFTR8jPdCt0mGZ7RoVNRJaB527nJ7LN4 +092ebrg5K7d2HiRgf+DsRNYFlNHpDhzIDT4pVnjv2ZKwC+uWWUZ7sxP74zzQA7b/ +nsEhskEdk8VkkwXgNNBaXwJi3g3amwgZ0Eql0mS1rFtHc5s7o9hqEsbFaOAidyPo +3Atg9QiAuj7B+c0PY//xn92W4dYHoLYYI3iZrm+H+tjwZzJ3IDK+QMJv0q+Nc0O2 +3nLJGpJ3o2KfGZERj7J2souhJDd5fRRyqHTvB0KssYWqiyQ/hSdSig/ExdqKX5Y7 +E5GLIc5tPptRgtzsMcrBrlePKF0z9RU0uV0mbPjyCL3IMzjx1MZlZbbT7UIHeUso +OdhLx34wpCdKZeX9BxlXd1YTNRrTq6WdrEIV3L5GEffYrC00lCRwDUgCH4NXAK6F +ejsleeVhKnhcXWnWFoC/WjPC9PXzXn+Nqa+dvSSuhHxiUGpRwa/8jE4LlbJpneZM +qZMcX+e1mglbfD22j4wfyW2s1UV0rW7U645CbOM1HeGn8l/vgH9ICd3lA+LAd3d+ +e1SM6YKGOyI1KM7C4LZFojQfpQVnDSZCOKTpGMSrLG73EJDFn/NucSKqyBvb0/oo +CbOybEfQJCHtHnFbk/rRnAr+tD3e9qyeS2OXXlaveiiFYpNMju4TrcldgzYUTZ7j +FUpidgGLMcj8hvx7oeg/O5pK61adkW9osDUgwQTBxcNfzXhMxZKQT/veRhZ81cky +TEFc62CyByko+9RsW0t3PZEhX0w3r3n1iAeevaNpFyOkuPTx+h5LsY8dCLOFWbyQ +yGHqm5YL8A3kGaqMEq4DxLVx4Ka58BsfTz+JY0GyhURzI41ZUqXinBKb5hATiWsj +erkI/WGao3mMVxoQSZ3mTLwPIqFHzaeR3FizInMG9g6ghfRkRFKF9180j7qbQLxY +Q6a+l2R5q2bS5Y7pFM1H/ncyKH/bwop4pwifir7MUsCnC1T8zrc/Hi9S7mCfnqIa +f3ZMgB9fMw91XW3YYJfjag3Noz2TVQ/sDku3wRNq19n0Evizk8FXWw7GTxpRT+X1 +CsKvlsqEeTmgJk0wt5f7oY+gpni89I0qSsXKyVuiRKmu8nU791NoEmTrar1l7Nkn +GhW4GaZT132X+JbcnqfBruTJX/PGsHte1d4xpqOW0xh9prx6C1XssK1VIA2jv1rW +rUaAl9ifZ0XfmnB/77nEPh9p3LL2Zo9KpX/wOBtU9+xD+4TzTBNt/RjcDErq1Nx7 +Aw6/Kr7yD55O+wAlrfvzvrkWjUY4ndnM8PKEGo/Bv5FLVujqoHVeJbJMwYEnIB7A +twOzZ2dBHMrsHDTx96SsVF7o8Dp61Gw3HrG0AZtpK8ngz1DxQAXK3hmWdp4F3EZo +bCg00LHam/8ipPd5zqJGBRwvVEu26DRmHZ+Iz06QCIRUAsBA9f9XNi8Nw90jaKHs +Z0VssNuV9WhTc6c9iDvYQNKp/IVlaez+hXQoO6wsdKqFSqyL1DtgMrdZhQf6u/cA +Z3DnnF73EAuUD58NIKxsYmbsDAZb1bi54c3QzW/MEoaMYm57ZLU8VFVPYkJ0QztF +V+7ZKTkFwlyAkgVVBVEgE6HTu3AnGjt3zLz4qZw+hjzdGQ9hjAugCBOsBP5I+9fC +QhGNiTzPf2pjbWTUVpUdKxSCf2u2lNFiunI5Xij8AzJZnJbRt281MooQePbiDWao +QMwun6hyl//CWjWQVbpGme6F3q4hI7RmMghjZZWWl06OgLgGYZu+Zsfk25SGCHGW +h5Jz/0BUXgGZCa8ikM3kWoICiNFArSkWzfMxNoVlbV2K8AYwLSJPBb88KUsdGWHw +FnZdk10y2My6KyRujZgS9J8U8+9UBRkfjWi+Fd5ZZxTNhyvuDhr368oIUDjCINrh +6s76muMVUvfsSmrPsRFeeTPWXj6HPr9Kv3RcKetjUElA9xL0Vb1MnONw03eeZ1do +BRdVRzbEoDD5GYuPKGuR4tLhUjpsl3XVbBtBQMT9J3/Lz93wcojC/JUfJmU+zaHU +/8KTqXD/srpqqfekWbjB6zrMmUtnV1MJhQayaRdyag8ir6oUOMN9GofsvvXdG91/ +iSFWyZxS2qKxV2NFEJiA62VOep4X1tdWizJyonOk6bMuXzzecN7EsuvLBSQdRGz1 +ghMR0XJ2ZxIhA5Jc+oVwGAIZBdezTSvXTL9+X9quFqZRlZzCl2PmUYTt8JlqqoTQ +K0hJ3xbn1HBaiZTQYBZbJI7ST7UsGylyUKRlVQUy6cmeRZRZQSCTGOFQXU/i1VPs +X3TMhAqsnp86eLRhMB91pYk8KqTfKTr2Qkn1/jJultPSniQSsX+yYaoREodMh1Xl +tVM6eovupaTnXuzGmljQU/6609wQjj9/xUYVHI62W86HqYEeGq1Sj2z/nWMMe9KF +NaZv1cYhVd9bUlkMGPZ8ldnSFwWFJeCfc5bWScwxtzlrXaPZOWMf8Q72G0NSJnN7 +cRvQT3CF85FPjzGd0sKMMRVxfzhmLHklTRDT6yBKK8Gsf4SPTBktP5+D7/cXjU9y +WJnaiF7pYPP8LTd0OwwsX1/iS1NGvW7EsosYLVwWH62vZ1C0ivzGC1E2IGeJyiaZ +pjKtlNP5nF9NTdTARmgiGss27Ed6QeW9MypxXOdUsvw8tQIDRZq5UU45fmhTZmsq +eMNDlmWKA4YD0NIZrf+Bfm9LKjYvVlFBFSfpqwNF5f1euYEtOIgu48Rpd49LG9u5 +JS/8sT5/QksxzYmsn3bpdvr4djLah4HRQz3YXKvoi61QstHScjZ1w3pf8Zeopko6 +Xzwcd4YaYFKcn8/e6ukB1ukPGuFdKRAdFMhIqXYyL3jza64QxRuP1pfSUoUNXbAM +jzN2weSP6KZRoujfiitJezxbYrfGKulWvUiwzX6OEKUkbG6TX5S+IwcP9uaFhcAZ +xxLsCETrStksucqvjZdAad4CugRUrkF5qkzd+Q2qIynzdOATIMHh/PzgEZsRZyso +Mh6YQn1QWh0n58cuyvy5JR7rwaNM23Y+/UTeOdNEMxII4w/aLwGP89aBg7lFccA5 +juiOcwren58oxnwmDcIqw1G7VO2R9mR3sY6rQDu1DSDZ4gjWh98066OUsJl6H0yI +ArwbPjhNWs3jv52I5Dpb9SQ9dmeMr1Lxb4AUc42zx3y42AtP2DsvTZM6Q2ojhFsO +gA/fKa/usGtZ9RrlIbkWKlrmjCxo6DZrPzPRiFCIkcWojfZZ5f1VIRa+SqsewX7u +D+rVVuCu0bYnk4OphCKzNyhxdzHEdPJiyIv31uSmv6VX8qEPk3xtbD7UzwvdU+zo +P5Jj5+E8euKbHNaZj3CCR+o/cb5J8KoYlH81Xj3DvhaAV5wTrMmJFYWRWWflEJKl +Ubc4Ruuf51zG2++11zvIjI94BsSjxWa8dh2232JJ6o0GaRCp2bCfXQ70z//J8wkZ +vO7IKKegu/HVePSqEiAnZlGwb7sc9GjzbkpN1tC+SbY81DBeti2oIJFgE6EUGHgE +weg90psGaoo48f18bwWkAQT7DdqXn6WwX74ALWTk6o+MSQbrzd2vKDEzE9gVuLjG +uOsSAoHrt1tUA8ypoQh4H07SULhjrAmSqVP+zQaPYmF2mYyhtH1+CuJxfRCULtii +7Zpb1Sh4J2PSqpifpGk9JoWGB7QDKRHmb8Ua9oEFOj97pPEuQtiKRr9LA2TD/Hwr +t9xgN09LwfvJKccnxa+e3H3CRwxC5Zh3qL57uKwdRDeghZR6Q7alzEKhc5/2qifu +gm4m8y5FUkHypLKKItIkdtd68qlnaIiykOpwLTRb9nIBPAClxfeXeLsR42WDWTC2 +YF6zG3rwoOOnG067/P2EYs9Cl9YyBeu3rTFHewldZ1oxXnOu9+11uebO+kwihg2e +LbjDpA4MuEur3nqqGj/cPlXap5QqrUMBaMqP/r4O+OxPawhMoTg6ERURX/rmwmki +INP8mo8MiDA/js4c7RZimpDtBCqo5faGLKWPEvv/Xhx9/UrpMmcqjBVDO7ICUMm0 +Ayb9S0RSXvYnoOPcaQ4wTXIbYg192BNhHWvCzyGJd1ZCnmMqslUA/IcN7IDNgRao +RF4j3p6qBPSRs6FnFIT4GtLpjAi6Uzn8dS75oZ2QucejDVGDipK/xsEM/QA99eRl +tpSKIVJmpJzJXzRqH3RrL+jYhtAYlpDlhrbNbXmVR5CxGIO/BKDNk+Ccqk1ukWpD +REULNasYRoXi+Vg0jtvd9GO7tAN+rZVVmj+SQstSbWNvYGV7QePWIuHyI2BOjKEt +K587hBFiH4BBZbx4tYLLB+K4/gmyMllJ2ApsSNXPsNPW5TrvKteYO2vJDQ5bb1w4 +rWAKUjTYhxjAawGWTLhJp+gMrW1fF3aBM7Qrs4cNHQJcyBH4WGvPdatcfzUvL9VJ +Zv+OOR/F+krjyf0JE8rWwylvzPYT5K7b6Mu7ha05CSVpAxSVJ8HdIE3OlQyR2llP +j1pmXraXuFMH73drKPqAHvGfghpEFRm/VqhLRN4rO5rnyvaKkwIvoOmaHTpy1Bgd +G28tyoI7pLl0SFjnC1mC2BlF9iQXVivbr3S3Di9WrABQBhuSYeBa7JlcS/sFwpjb +JzWkDj3PFo8BgK30SmCiy1nesAqtAtRv8xh4xHCLLul40dgSn2MAlPcGQKMwzBpN +LFbGVSHR/WUHhbKiStl0yNoklIKvJZ2toQayIF/ZJV5PASnDWCBtCJAjV/1+pvaS +2bRfFwwSguYxI5ITWx10aUp8SO6X88GGhHo9UYM2SA+sF8DWohlRYAmNAanruICP +XmIDwqZeW/za/lbYCcZhZO5vdmYZ6bi9EbwZMtFJk+68dHhwCMTdSUS9YGVkupMy +VGTTMiqyfBN/dbcikXaHuw+JG7kE+xD8gsh5//RB7LvqXQWfYcyMNtLkT4a+SmrR +RcYNFSVexQphICb2E5MxTVUgOo6KlAoSJyoNVLv/KNtBgN0vSKOzzH4fxR/3sFHS +YbQt/1uIzKzzA3PtVc4XblvNgV31bJOF+Yk0/enBOVx/JPUq6iiyh8UwcC45V28N +qobSKe2lgkVNrh3eyL8cJgdQzM85Db/md+oqNTPhysjHQY6Ag9ZO4B+QXcUdqUjc +ZCtILI3yi+XNXkPiQPw4qcNLWM6FGHa+1hhmaKgaIcHekj1VXjxtrVqcZ0OxkxfE +fwIxsLQ7NHUL85EoIU1AQd2bGAJu8vuWa7bTAgYmVOsMQxdztEYWC7IIaE++6xP0 +yKYekYvYmf4h43XAI6O9gulsPHQkTRessYnuYw9M52Y117GZt+rOYuROzxpzFM2E +AdrMWkZX6j1nE2ql7FBIXCFQVqb9witCSzF4vAqg2x6C/lBi3zgiM2AVRqEUPj7c +MnFNvZK/f7L1ck55T1yaiYjoQuJpqlLjwLT0RDj06cHBDlvxwsifItdGwHdIyYmW +jkl0LdxDg5TgD9biJU9PFRgbjBj2Vd4TaIC93Hey64AO5nw3O8tJFwbsfzBNDL1y +jqEbQ6vqxcNj3WazPCDrTPRU5zDpjiL2Dz4dz8tibB7ZzJuF55Z42JdQPDwC2N46 +1BCFxv7gs6n9BEFSsEYNg9VvNIkc8kFlcyTr014Z8Iy2R2MscJPcTPoy8Qg2v/na +kSkmZqqj8m2hxGDuzStsGly2Rrc3TNWKr+Tc1dbL573IFr3ICmV9hmHPXAmRbdRy +/uz5O46gCskv1DLRBQKT9Fbsks0JT8wsJWhTiyDw9XXYLKdFbyEDcnYn4vp7KHBc +mdy0/ZlGVBjegQC8cInl4t6BkXnBDo7e0ibClyTd6zHq2tAmPJnKyypUYvpK5EmF +XxrzH59fFwNg2B3LCs6A69ch1Pw/iywkkMJFLpFjPzUam+1f6VyNhp4zmke6Fuz3 +rkkKybKZMcqfZP+kVJqDJ4V+gOid1o0ILsqm/RdghlImSBVCvP2wPFP0c83qenFb +qDAOBTt8F3cZTLJb+sC/XGXJUw+sCqSGBKRfkxfJATV5kHzO2eb5bJ7AeuiVLI2T +aN+m8gNCeoXbtZMacHGSA6qhfIEXI2sIGYgy7lwjD0MKM3ViWFngF6MbdEBWoEsj +0uo/h6q2ReMLR/Kk38TC6a8dedBIuPPAdsXCpexsz4sTLcJdAziLJekoDD0KhlPH +ILXaZl4dTQK51/EkQxGFvD6exoEqTkH8BNfLmSgQeZtzy+MpcB4VAMBQBSkZvZ4L +XHCmcVxKhFYlRp6RuEcMlWpILtDPZXUEBOHJefLyAElIY/KmFZT5atTlRGnZEFcW +x3mXB08e81nv+4kR3Zx/0hSc/qGFwwaHeI+qvmgh8cyJo1ocCtoVy/HZIeI0Yo5t +JEOVnT0sRbK8DURFyfacQGFH2wmji1wX/yQHmVu6tYO4t/dQQu4TvL2OAGfEBSTw +E2uuWbDmIBnnojyaGh2zADA8LkD74Zup3nUCTOS4j8e6q4hPHB6+vlGV3aWTpKD0 +SGFp20iv6pnJj7XdzE3zX+IAsUcJ3FBnuRZSBT3d+XXZv3e8ExvkkId8mLT2C34w +9vPx+inDBzUDoFWlSpXb1I8vuCHClKEN19dRY6MkS55R3XbUhS2yOnH8faP8eVVV +5//AK5qEuGm8tuVGHaPYcU4UVt4EAvKdmrXo8gGnqv/rMWDYk4xbwKAHqfj8lPQL +v2f2eiitkrhutZ3Lrc3ablfM3C31JX96qPaUXkis5rbfY/SttuQxUIM7hd2HM2Jb +IaCc2kDS5/EMWkQalvH6+YusuvIPGga+ebMLMmztiKyffVwZZwmc7TVIpYWR5DJw +L3p5DJOMQ9/x2kxDNVm0tZJfrH8+33laWbHZjIFXUe96x+fD2jCi3lntTP6Ggdv1 +lnwyNNM0xrKPxa2dhAbCKZtDdkDNILi4NgNBlx+GSfihU3uVSsA5vWBn+C5ZlvW7 +Bn7P6n3TQz20YGoIXS+Aggd1/rnNcaHS1KF6YAEyf9CFZGZ2frxCvApa7/ATkTcE +LLZ+NqcJbkwBacFSSqls4h7CWVMFXqYa7f0PDyXwhBiCG9ZO8BiDGlDS1PIyuGHl +A3X4ulXW6wiXD8F+x+pNjWvOgb2w9UxRC/v+Fb3OklZwuRVIT0B8F9lOGCQsDeTV +axHItc/eyIMXRgyPVjctnlWf9cn15Wghm5rLtsHNIbkGIHJ4Oi3zTWPlzb6NLrLy +PW2cNoZDjO6fxdBUVUh13DK+C3HgmDnemUHgVOiMHYIza3dSLM1me1OWOKoIaqL7 +01QKivjJvpZgVuDs4LuryXLePLRSpG2z6Cd+HsG7e7OT0C6Hg2vXakVhZijTq4dt +1rvZMSY7x15Yb/v5uVS2CjULq+bgt7TA3G8BO5c+jNjwG3LhRm5rxUMSu+xZzsN5 +TGD/Pg4eQaSftyseYyVKeOS1GJOx+xk/8TcotX2AN4viY7UNiDB5jbtozoTjX54c +pJvHsOngTvmRwLe+19VNdQUsVIguisBEZXdxdicyIQmnP5u6NB83JJXoR+dbvK4s +TqIEtXWwBDkXGhQAhmQBRhcTz0A8YnSBzNCqwVVWobFRvplUGWhig1h1Nhn1BCqn +SUskwL8PAdUaz1NRWiSVOxUiPooZkz5DtECHQxAuYTuoX1j3YD8ro9uNOAx8yXvI +P8WnVps7wgg75SFyOvVdPkqF45O4BP9F+WOh2j1x2In8u/an0pUyvE5iK0VzBqni +eWAXGf6hcQyqMgkiKvU8MDGMe1ZwRpM7eeBP2A8FhIrdh0TbUyM//0wdqnklt0pL +sGiic0u7OpATgrKpL/+JoY6d9OQ7rcu5KfxX/9Q18jMngLjW137yY66c8VnH5r/w +vsrpx+J/+JnybaR3Yd07/y/vx/kKuxOEu2DDN9ynGudl293EYPoWvgc7FB0VHmKl +2/oqjKw+PLYJL0vO2enrvFq5hyOyAneewRvJ6Ofe1ix3C0RPgqz1A0hKn/KEX6wt +/1mXCCAzHwCY/2hnNPrbhLpZ2aovUXa0yTiDBzz9riA+TuPDVjtQl619x5fKi0DK +0xuOCQ6ErvoOjM9hJfl/iSvYMQzbJCRVqdwTkSrpflMTtnLh0fNnMb70+8Y2F91j +hEz7L9mUXKQ0UfZOFT1K23UsyOLTx2qHN1oHKsfUFDfam1UUq+3Su3x+Mpr0fv74 +Gx6Gq3K9SbOzO1WW4XJb8kB9QkA+mc2ricjVlAF0VilYt+wDxJkXpM/G0BcGkG6L +GFK3vcn+gSVqkqxU1Dg8BH7/SLZa2mNZp1viN445byw+CxZGM7e0deALCgSo19E5 +XDmMxAoIMxihBIwMXwOvYYG0V4CG96PZbUr+Jv9wajysRPqnuTFUXGYTVtQ2nJ5Y +pjNOupwhCkIwTqPsyzlqC3vVZn3D160YfMzf8FqeYnz/hdlCE4Y4kJUosyMnp7hE +VUtDsH5uGr6ISSusu2czJLr0mOKBfNnPeUfJ02SZA3XsUTmIszZE+Z0VqcsAOgp+ +UDJPYAVFjnbUNoVuTC8hiGG/noqTBmXhgSSdFTYcg/YZk+vza4dO1KBHWZR1hA3K +jRGdTaPtEIs5swQ4U08EUIyDEl8zFZR+ZtJny+k6otPAT5d+3skmi4iaVs6qYy4f +NPTi3FA/jTystcYJmmBRkhjNNeRCauQWgFyl8xVTckS4gpKnvMuLqlWTgTblUnPt +Uj15d0bzEOEcWoX8U9rjRg/EuJLb8uaACz9Wu40PckRVv0Ce5TOLep4BHq7wS2Zp +ovGm2KRfms87ZVF+JKvOmYXk/tjd3HEcGKl86MgQU2eYmYtKVUa5Aa7/mMEj/1WF +YNpZUtqDfSYRaOFvfYPAwR/Mv8Ol1+ZHwdPj7Sx1+oIucuJTeqs9c+vC95+cczsa +TOVyhgrYM6V/XrhHy4L9ARnCBrCcJzqKAaEnqTzcRjmIbc/wSeLn2HEVR6bIPB2G +GyxkjKnFFSvMYAF8+K9ipDFN1hSpTLaCCKb2yHR51T97d9xDJaUiknGeDHsmx6r9 +sbzd9NSqKzIEoJ8QFbKupog9KTO1Yi5WDEFXG55654FQEMcB7YC6SdNvgoFKzBFj +NFE4nmkCHMIhGjQrwWZKEZ0kXIAkTDBkNVJptogC+RrQqYnNkg4BOQk4Qc3GgNTZ +oTjknVn1hVFc9mc2EckYxtY7cva7iBeL4hqmnmBrkPn18Cs5YiRYORgge6cPbBYT +0nPeLPwKrpa0cHvDbDC11KqzIDYOuacGNJIyVQSrvHdRtG4q/T7U7TpReNoRvG0R +87y16UTjHBjQKPwxYECSHysVqbHJYE6BHcHI+gqT2Xk1awokIzIIoYVWXQHPup7c +6YiqBc2KUymFvO+dDMuo50rucBVvnJsuOfR99cMFKLS3liSNt7+zzsB0S4r1EHS5 +wEVbQNSFEOT68YYLaFhTg+/PQNEkKKq8fvKT5BTspbEqxbCjYEhqME3hCpB/kWkk +9WUfh3Jclk+MbTZvYXPoK26cifuIK1RDl8E7XXNnuondUjoG3J0liGk+BFTy4RhZ +ktwACLdraB3Ebqg73KHncWo4YUy8v421c6Q3Gj4A343+Lh496NDnInfQyg5JIL4N +hc9G3aW4+bcU5C5oA0Ju3y1cjWobdm8MFhuKzJI8prtjvwNL/uyyexIULougj1Gc +HrjjG2bDflGIsbg17/0Ncq+tdhpJTAmjC/+42JXUGySAvgG8yJyIFKbXZClMpXK5 +Yd1h5tJ8CK1nK7nZm+VY+tzJIzl8zoHJDSXsNxKW6+i5nXBbBvV2jt78K86Crf6N +QiZBs6BiwIf8wUOpo7iAym+JqIsKB5F5hOFUuOXEOL0jM9TTDPvuRjyDO71L3tPt +2SyY3OIiDAEKm1depV0RaMbEj+IXdautDX/Ss4FdsmwHWqk0OOFdaGMkoYEANc4v +fYKiTgkAtaltydXoqYsa8on+wAuL157HDMm52Rby+XbjKwB6QZtXFmFci4OSkpao +KmQCDNaAHe6QEMSEdZsnlaVFuTCDqb+CTFpG//QeMHse77+L7oJRJFHtbeEh7XcP +OZu4olyn1M18zc7EF2UndJGcr80dwFgVBWjbAvOeBSFxlhlyK5KVt+JDPDg8DrKq +bDrASriCCY7r1J1t/BHFf8PktG8pCJWM1Asq87mI1URlly1JD13cFk3BwWNRs/YG +Ne19QjE0/1otiAQq4SQZWtb10EXGm6WRy3i6z8o7PNlJVm7iHVIdjgcJ+N8ybuAU +wBozu/HqcM58FE/rEwqqNh76htX2KCpKKhqRu+GBiezYEbRCRaTDGlcwtQqZxXRd +hnnDTEN/+2eL2oWPcUOpAABXCXaD0ML8RdCGQ8cce32UfBky4aM48CrOVvVL+YUp +O9Oo0P2hDhbzbvuEsm0FQ60e5T1nkqQeV4wZi/I+9d2b51iR19VVGZWuq3HdqT5W +kJdbypLvlp7NGOCLE+Fxc2r+2IazhT/rx0F0MtBofGWp6v3Kl8kwEUJ4OiiIh94R +q3jbpm4mD4ulE4FimUAFsW4wW/jpKY3jJODQ0KhZyFe8YfL+WulvdIN7v39mJGUy +Z1//KfqOnbegLEfRAy3XcNjsIC4wBIFEtuue70zTlsp8OKJpzqVmY2Re/zdQA4h0 +4ueGezqgKmL9G/G6wVX19mnk3Z5vKusKokbWDoFobTaoRFSuCMh9Pv2yWdJ4vFD9 +1li3AkMCr+T3FZGZ/Me7l2+0njEfywCaqVGcypXgy3p1JMWeXJgWo1IdalCFEfXU +MfE7a2HdmQlkxzHvMEfBobCmhtfdcRe30J6J/yfGlAZqifkTjq41+CmoNgtVINBD +g4EL21/DrjgPafzikXq9dseeZiOto/PF7zUs7olOeAAw/MQoPqfKadxqgdSrYQqb +n3ABYAuCX5oSp9LzFgdxZeVZVAsVLRTJT6orc8B7cxSQbtxuUfwhS77rRQ6sIO6g +TPDzsaVbaek3CxEs/Hop3zimiFD4pMcGNTnHygxArIHRKinkvbrLWzpkCbogA3as +SFy3EBsszjNmToJ+bCchN/YZaIEjBSi7+3YZvSqaj+iG6viGoJMHIRa9S2SLRvmO +/ckYoveOG/Jl4DxRVGiFqdn2PBz01t6Fbv9RzdtjHJ0+FnUSZRcqUJQS4kFuCs4F +IE9oR/YS9PrOBoi76ypQixK4sQT/aIiDB73duJ0D1YOGIIightPLq+UU/hXAmGli +Gf9HNaBjeDsh5p4eEMw9jQTX/VTmKAhu9Z5mmbIUrm0Vpd4l/lpY4GSm9wKXwEG9 +2Wlfk385t0xdM04olpi23MMiIVqmypLdOmFRReqCpmxG9UWSsjLbQn1OYw+xyrlp +RDwLyIAka7eGek3vcsJn7m84ibMZQFPnX4NRSIzfvg+BWY7gPXlbV3YaLkkTMqZn +2nWbvHXUPkVfBRWtvkOOloedaLNMpY0ump/sx3554B4P63WD6otfhgvjmNGwPvtW +MvJyE1wJTTyzaNTFruLx70VwowG1iqTiJdffQHTFyo+Ndgdrd3W7sGBQX/CfXh20 +rg7OnhCbqg3D5rgIdQ2I/p7SeKtxLfA4JtEleztIlKjmuBzJuIlzu3JUzla272lR +/hgsNGInjq74xj8W6DeCMlPf2sZFMgWaN2pic89ACPzDoquAtWi3LQUXx8LVwvd7 +WmENhFpJ0cPPKVzwf6m3icgpbcR71rw/7H4JmlI+00+tbcKAgZGgzUblTvgYD4w4 +2bEYn7PSmMXyZrerEymwe5t7eU/qm+7Q2Hyw2gBTzYKDe0H3+Rc/TfMN9iguy6fG +G9+hy0xGrJ2gtSI885v3C3lyVzDjWZ/wUxXS0jNjEUCyayzd0a6QYavDEeS5Mfvv +OyJRhi9lyfmYeX4FMckF7RrZ7+Lp5zv32MzsOHt6IBsuN12lYCJhH1VrPe21z5Qr +hW5DuqSsBpB3+xgeZkm+vWCvwMarLX/Zcae7Q7GqNYWGBAi2dMeGUXwsu5GsfE13 +D8fkR5VC8fVEmCfCBJ0la5W4HB1vhXhSn9dKnp5tvoz/el2IpVUDwxetqQRcwlID +d4SLGrxSzpF4ztEz1GFroPicHF4KazKJwahu3tu2h47xd/+20VpxdG31C2DmpLqO +davaZ7qrMY/IbOCXzRZcl2J3xNHYlBJK1CMJvHu5CCfKE4w0AD9uMbQT5ppswoPd +3b55NocyVFDKMmu253LMsFcjAICe/aS2kQu+q1b34biHR/lFrjjEEqx5YKymaoI9 +jqazJe498NYAJERgJ1wILqR52wAQBhfoDAC8+QShurghcz2jfNSCiuMJ8U7K4+fS +53BKQRF2H/qO42AlLojmZ6NG2GMJg17PaHDdr2OcsVqw6TJA/g7P7q7Lkk9c3gBk +qO/dDtby1lSj+Ik+4eG6nQVCPIc9pV9NTMrUXtGPya5btO0gE57dLjB7r0yTCu6K +E1VjNyQbKLgI2HkNA4LnUmIJTGjXUuWVG5HQx2H/KxZsEhNyZkwbbLK9RdE++z+W +NwDnI6c8OGOf3GcT2ZC/3LVlc+SKK4xPGA/DrQ7EflpIOo0jv1WuGSMaz2FexCxa +TPveQDpZm3ARp9KNmjBGmk1I7+hSwBr7BOGWJVayTs7GQfUhaU9dNtv4Kyvovfh0 +Fsb0pTH+4IktU1xLzqO8tx5oeXk7oWD5pjnv//diVHcGK3soCcH/5sa4Q3dQOsk1 +EAZ3yFTqz+1V7lAmDkruWpSZG801nMs1mlFOzo6ezKVnMFKk98g7334CMrwb8Bir +7XkkgkhBGaGsutW0u6S5Zxsfj2RJ9LNqmA7CbfOqYdJ0Agz2IKUxaekuywv4PQf9 +oEauY8rO5BFlYTgvDIpq17Xrv3Z2niXaxfXWQZij5xRkg9UaM3jLo9Jy+XgeyB5S +JCbUig14RmzfJsp9llDbG3vMz2XG1tqSRHNErkBuWb1axGVG6/Tb888BntlapXxr +eiTYP7paKylyyDLEltvGkLUKvd9q3J1A9Jcm5ngQHRBGeAkWZhWf7q/w9PRGMq6K +H2b/DQvR8giv5eW6aBFxhCx9uSBfy4pRuYE/BJBb1JGkAKgMTCS+VDfGhpxJ1XXD +JsRUextf/ZwpF6Duj427WHr5dUysE4y9DjIDDMlTcPOnsaglGSXkgIjuP1b+XUVp +HDzu+Z2PsosjKAsTuOfzfq6Czb57YguFt4v9+L1w41taymfVcaYXD+APugOHvOqr +p7xRhc/N4evGHXdXatCUYYMlPdV1+ULdkIOQQmZ3Igv1qRMARfgl+tWv7ucH9lYl +H62q4DqWxf2DhO3SPf3jfX4KWub+wpe8aq9r0UFSCufJ05n7Qwn/p5ld5OHIxV4C +0RGVvYdQjivElGEp4JucL/GAla2qKKfZrzWmQ0GZDBJoRY2f+JzsG/Onck+k7WV6 +EwqRldOY9hr6b2UbR9u5UB94xGugfYOriqEi4s7sQ0Avnti87dy3Ysx3W8v9AqMN +wymvSNgv9n91QRd0zkWXOZumYcBPy21ouuwoqv2DYSdhxRT3+L7zkM+NahNKnxrk +lu07jNxsYD10ydAZalzUP7DLMB2cRb+Hm9D4CEi0QSL1gn5d/cTBmfcpp+Oe28kg +NdHUq+xCN1KkLfII5C+uh1blh3Ryw2We5sghAoN0kf2n8bAEHyH/5IHbOl4kAEme +rW8iFRBVuQfEA+DhFZdM4w5nHin47J3F35Nuo17UAZAApp+bsvBKS5rjIlBrRkY/ +K2NVj+th2bVRRYv6ENot3TxB6byxgJ0NWZCqsZBjA3B2EeG84tPFO7ftpzRY9lJ2 +03lS16cGzrXuSvXquIoOdjL8PQus+EL4Rb4sS17Xv3xFXTkym9APfKnrrRYUYrha +vUJxqOpiiEreag7LbDtlXcDIy6phrKog4gcWyRo3YUUTxwb41rnLTuSqABGuGWjO +d05IqzL2gK/J5vs6Msa0zuognjgm5aC7eVlXJFE/fiz8h0K+OaKOeMONarZ9jk4Q +ynSUMphlSYFVFY/rhMes7nOfLxRix4RydHBTfAvWRyvtlK3KAS1QRMTjGjQZbNqb +T7mbGGZPyghzCZ2maRHZVxr2uN5xWl1teQNMaZaQLxLVPnocrLvktQacx0S/iASV +xCrQXAaJ6W9b9KPYa4v7/5BVgup7Xiy0yNvu6mQz4Gn8PtqA/RhbNikhFXH3JALW +rjfyxaElPSUFu9fsyGYQkowB/ECy1894yzKwSbU4BSmgjLoNaJBAEx9vJRUlDtfD +St3bxv3uyY2lX0rUD3CWXDqeYlSrNSCCVIbm+8nme9aKMv/t5us/phYmpTCjENob +6T6lfLfrupAz6uj+n5QjwqmU4Cm8fdfEvnVNfxlSDnS564Ysopht6k00I0KiBUzp +Q15lTDG8AG49AMVeyDhmiGV4w3JrMnDEFwhiXpTNlerQCyPkw+T8Oo1dhq0QB3j5 +K4CocQtxmyIhNuGyUPvzGExADSDa9ImrZ9eMgG6cc9HbxNvyAyqqafJe3R0pjRjy +9bOv5eJE6m4wtdkk7RerUukeUvOQSttzM+LeMGF3MJzDH8pWQYZZijkMTPphJm9w +cVC7KnTZikfsWzz+JADcfEb+mXyKY6ZJxfUzOp2fGw7YSNoH/I3HWdUVKyCBMPWs +WSGka+iumlx3fGl/G8VqeOL20BkZNKphqu5ZHdTi8ICFiVLblwbcKTkml70QX++4 +zuRGuXqzU/GiIZCP2whbT0Xosp4a6D0rWfl5FLaNS5p02JlxpuDzbk1GwMA2JLra +ricrzbpNZc+kyJhN0T15ZXoU3BqzmoZxZEefEJKUIkNPkcHoyzVFm47IeVR8hE+r +ITBHKOQCZOnUipb+NiqEzXWogREf1NgIYa9FRSV2QuWjZGMFnTliTsebkiN+UYpF +w73P1vXe94tSv5zheSqY8nQTV1yORSkliV8UCJVrYuhHjQa6zqsP0+tFfpyJwWOE +x62ZNGX56rjkgqr/5ErIDuKhLegngPUAweArbPBCzS7ypgO5UC5F8MPGFTWaYOpk +LjR+kOEJPniC0+FV9ToRNCEEuKpu2A/Mh9VA3QSj5gLlZx9Cmf23Ag+aM89YoFeG ++poQXas9WacqpF+0cD0vgicEhxg+xp7PGOcKyMmdu+X/5Tdk/A8s44A78k7Nbi9H +7dxYg+dY85zqCTrFt0Il4R2rNQKinqbq9FXsb0csodJSKLp0OOQuToQ9tsfSBRFC +ySXoVhfRVfYwWoqCKKBNYIzpt2HS8sMnDGD8YtOHJiZlreZtNbL/VmvgWLonK4nr +q9dyCWoOjdcfcgUwPRWJ9p2F3iBAXb7jDCb9etuQ59EittQHfmq/5aKKJIE54dt9 +z1oXeqBt7fRRGSRl5n8A+zQXMBASAqD+8Y11ufLVW+h6sAJjuziXLndFxCdU5uKo +36TiftdxMVasxjMLWClNERN6pqDFxRCb219Y/MbF6opLBPFoYUPjDr+sKqWj/xE6 +6Vt0mErAud8AMTTdlR6jkpmu/CocTKEHEzjO5Y+udvrroEqNrww+xUvrqKA7UA0G +cLSPdYEh9wAvvETNia5EuuhN0ynotrTXUKeNFR3lk6EMQhRQ29jclWbfVXgjPWEw +k9kzx5/OIVm1sYSIGSwNK8MugpG8KLBB/fqDy0V2tJsoaFKqrjmsLRDc5SojzT5v +NtTtRgOHhct/wSc4ZJx78tTOKWA9fqfcSLA7xPRN5YKBr6XGwLj0yGIefFcZndmY +ouXi7/+YZlfTg54BCiU6Yg7ZQE+oWyWLs9LbOzxRYE5+GwddSeiC5aEyDwZRkn/2 +jcWZ7mGfnoeY7kUv2+Df4wl9fhUCuC5urNpE97XSWeBMoRDACZstdbDmI3eLmMN+ +XRaX2tP/LtNA3dq4O6s21Y0CLo2R6SqmTST4wypaX+Dx+94ho/whtnUWY2nugWgP +nq5j9zeINhoVW3S76m4C5AHpUqhqHwnA583Z1tNolW1Mmay8nS+N7ytGwwwmL890 +FamLaG3KqReLsQ14p6YTd25hHMV2nnHg3asIZoZeBCDgg1Ai8GCGkLij+jNrieXM +/tDsLAw4MrBrfOcKaksnZ50CyXiH88rsS+LIi9wT87Ww2EKH7VlXCrPJ6mBbXwbe +l8MlESzST5M2WKY1jwmWBb8DAQmLUa6ddT2FTOhDavwe6Cqfysm9ROzhDD9fQfle +TkbT5Z1/zYlSUR4BAuBlTejbp0fsynQj+G6Qry4K1odYWYkqowkboUmLI5/kPKeZ +koNWT9YZy/ArPUDCYFTjsHLBhYQEm5Qz1RTlsdCxp6U/L9Ms2sH1fqBgR2dhdnTY +aSKdSsb6DUsiOyynAaPCjoAwrSYIIRcq+tiBU2AKu2WE73epgOEiLVlIPb8ZGnyI +74Mn/OwwkpmBkvS2oIH2hQDTTNS5nXIknQiTUYf8yrAwCYCsyHSIrRQirbaSt53s +z/3IFMYz6SUDm4nNHyLke7kIy7x8oyNV7xfRH6t6ryu1IdtWR9QkCa94/htzYvMV +xaPkspdiCqYjwKPNZxYr0DzYKk1GJjNWuM9UDRbhv+QBVImiEpCCX7bGLxM5HUCo +U8sRq+ha1wn3FhHNwNjsTcGMxaVnD2U1FA02Cxyt/RlooQOmpSimSKLiXUYEW43/ +/A7PMFTkQD4Wpwl0c/DJpM9mRGLqYSGLgpr/4BYZ5Pybhwh/1W7CPo21ZeTDQd0Z +hoWhtVQ0KdRiOv4WHE2rNQC+va8eE3LK1u2fHgYp+UWALLu4fJJU7axiGtBfteYA +n7EkLAE03W++OqfxzC6BKewRLJLAgqMBsTVYSNA+hkI2zdGwFLv0IzjXOQxddWZt +vsIny+jL41fi9t9JdOQiNOA/AxbAJJ2o3qoCyLeVI19EL8nnqC6DSkF+jOyTHScY +uAnjF0195gMIW1aL3GIOM7v4HORIRK5JcSOxV3/B284GDf5IY5ENB35xTR/M7DIf +EP8DVOXJKxEwX6FCjiFgfxoy8E0LSphmlzeXae3zY6OQEtnFB61abS5jAsmYoz1Q +iiKD6uJlEFEgbUX/YmfsuaGqTpVHIU0pqEjALE/KEqJ1Y80bKMgGZ2GaogFTnANr +KWbeMvrx4qWXWumipb/T6Doq93TeRN53s/fkRnXq2liYtsArCHQkkzO1cQdbpNgm +uIIvCSzLqkyexdPjKcGkwc+rV+3+7QsRfyDNsu3KyH0oKumdkb4XVWN+0Oieg18Y +eybpT4bR24lJ6v1IzI68HKZmqzf8bp3/oudFQb3Dosv3meOvwCsEx2jzoI8Xbn5H +roTIpI+YhpttYxNzBUi7IU6X4nu3WSzb6QHxxKPjcNj7e3HB2pSr8abVT48J57OA +vA3ZhFN9q5uWN93Pk+qzlJZ04jKIAd0yYbSaDPYVRmHTvkeWgPEtiaM3sQDqol4P +V5x3eKQJ8n5tkbj2epob78GmshZfdnASmNzAhRPW6PiQEqaGe5FdpnATejrkvlK6 +3eAGxwYgZ+AoHczld1GiVUjxG/8xCYd/q7AXeqXoazE4BqS0wLQjAFWjMEikkklQ +FndZdQG6pXCeRd4qyVeLIYBzH/RTwO/y+7skJCwB6afzz/cyHCdm3SGh+WpmlB6h +4zvpeh+lyaVdBJmbbT1+8DZzTdCIHhQnO8sSTAcEzlmbEI0SbIzydpkwAwp4qjpf +4dKrOyvdbMyASeuI8cm5Co6A0IlqcrAGjImQHlcve3XpgKuihUsMbbmE4Vl7nHc6 +amdWmjJ2URd4cmsPmlgwkJf5sW/lyC3AKKBwiP7P9M6pJO0NtdtoqDdGEfjKkbop +T86U6Gc1Aa1aK/ejIVwX/6swjdAVsUmXfV+BWkKqvkOKTRSA9EkmrE8+vuHS+HWC +pFmS8skhn2MH1P2NVYRaFWXMC9sxgX+Kqc5I6p9tMJjG8Sr1Dxs4Aad3q0w4Nhks +Tg4KiTT8l7hHpT3cCbP1WgX2wVFWrhqfQExfyIXWuM7n2XsLpMlXfoH4fhZmGkRe +8bAuZV4TsitySxApp7kjgYmnYls+Vooaxrg96B/mKjvm839Q2k5vfXKv2pJFhSpP +G19FCfTeUSps1YMmatm4rB3mgiUcIh/WqCSRnIMTJF6T0E/rlLDMkdAIatRQHOEx +Q/GL/MrMxVvBHqV6pJageST6c6CVFaBG7T1M0Qm0E+RteBuf9lcqSbfgpLhWK3lA +phpqDQ0ZjB+zbfZxx45nj5woRk9sANedrAYygV0/SWtp4+s9BE4Kvu+oCO1ZmAi3 +AAff1FDfpEsszxRQuxuYHZKWiTaUvgzI+mb/lJjF6hT1mrKj1dSPjkkRmTngWIz6 +LeRJi2ZRnnHQLO08flHzeHYvivvN9LyaSpPye1Xm8wu/gJSCTwAo0BIWG3cmjecw +t6NYF7pxZRDDuYIGB69NwcPvkBUCgA+Gqh/G3554WNUxSSyA8hBAL/cVlHXXhDU/ +2LbcUMhH5GunTivkcXyVPHzDIofuDFjGdA9Aw3/Ape5JCPCnnL0f+Uux/C0iOguM +d+AcXiv2A9eSQSwDU8zZsVlQxfIUSnYmTiLV/GzrSdP/BRuWECSzfQgGPEoWH4Ot +t9O7O1K/0Uq3t6SCSa7VezYdr6iKvNGrwl9rPxd+8dp2I/u5TCPT6oYuvLPPY9pj +5abY7+RIBnxzz/XiMXj1qKkIfAfgHTU/k/obEP+xO/tsQ/5AaVyhd4Tor2eZyncT +pdwtGbfjqHdLor0mdork2rfRF3Yd/dVIzSGFUQEWg9I+Fawj+7UffNAhha82Hogk +ZHP2XYGZdBlS9s4GMf1Tw639rXabO8/FcBmtoGyEFohfm2n4qUIEEX/IgxHw+DS4 +oZYxMopByElgvlmjOZV5WXooPHA3oLIJP7gWUZXVfGeBOsB4DLif8ge17jsdW+gw +003cWqTd+ndhv1mzQBCJqgiUSg8OqBuj9shuv5hYPqhpVlXHskjpSP3E7fV7amaI +/0MvLkUtfktL1+/dQUM5PAg2r9qWZYxsF4Un/HStwDMTbCPekKL9TP5V+R4pL3wG +Dm0VECqQZ9JEHtqm4GTzE5knW0WlhrQ/HSXYX4RvdiG9mvuUgPBdxhaICr6nnkE4 +LCHaWLHhCpIbOhJTR+ESNZwN4bb1PAY0+5Cy0ijBYZZTqwgmIRKgZ7EL0mpKOB2E +QuQLXgCEkFNj/XrFSsOHDXxOenUDLSiY5JbhGKYWfOJ7CHeCsutwiZNZYMwzhzFn +o0xfqEYjMiZYWzhJYdZIsDzN6k7JUGpBRivA/1KIen2Zlfe1uVM7QfVHXvBGLyQd +K/II2cnCTzuhtJToB1EK27dThi9FXntrlFAjwawWkIz8euGqSuAMQCPH0m8xzkPJ +lxMI+T8eHusALZZdEBRXLjnAZAY8U4heRni5lbnxiAxnB74D7j9E1kF/ATSgixo6 +hJU80tr630NLggto7KD+GJkfu//KXtIuwuWYw0KaH/aWkR/AScvW/jBM5yFnFYUt +8LgTcAIkpM7SVUXHfzZnpdKX1mPxL73os3OPP+2Jh44o+SXoEG9YMeaffphMNi7a +bO13SWR1NBz6M5TiRR/92XDj5CybdIUsrXBFGXFqiWQ3glnWcFS2n8pEjwsp41kM +DCUUF25Z4jqK/a4QprOLgn0EGLsU/cxAU0st3fcX6ln/8oZauMCWQlz0q1A3P2wK +HH6JiPSb+YyfmdNPPw2wjOH+h/AhF21YrXB113gmKrtoNB9rJMnJbODmEwWyHjym +xcF0/KC530EPrnypjvaNshy4sXbl8SRIp1lVX9DW0SvuBeUwqPLZXlJNnPEyt0iY +wHUJT/lffOH8aJ9UjbWbIvVmVSnJyzgsJ2NrHvNXkKQ2DrwNW50AGUwktSpQ4gUa +noc6fqRTdmlL0UUT3judR8vMQxnVnGGTl3QDV50BnrbaO8bT5J2k9NRUPFd0b9s4 +xi90vaj/LrhCjDakkRoi1MVcLygGrD/7eHwrv3TB38D3atxMA251UqoMo771bN/o +TgnroB6ufaWaa8t8LyyXPJHSOjmt9g9OnPiOdeviygOyH/TvGzKsCaIQGJFmPwUu +8lWH4aoG3p5qS8rNGruGIOgnE5EjbB7rUvi5JDrr5NZOSuWmHZnXXToRhaNJ0XwE +ca+MNI1QLOj6QdhGIwLXp82n4EB6geDgDhoeAUUM71fDuvn4b4h6ngS8xk8+rx82 +4FpvjjN129jhby+JvEUwJpNJmYYYqgtCbiZPiJC90NwkXAzWVP2gBY/NgXrK3Prk +7DlhMqUgGLtTIHYoqOkQjc+YIE6JwqSq8Aa10lQyIppq9lJ8H8DX0WQEW3+7/E1B +FuGjdG5J5Q7ai80kC+ASo5Z9xF1FGqE7/6NPfzHbWEpcJ6uf4iOCxVAHfpaMCFVN +6AnrdGpvzgluiR2e76SHTHjgDblxAwuJ7dLDMiVT1ImtKdkbRYBSA6c6pwgUAqij +qvtXmln45PuvIR0/p+Rrv/fOkxCPuKKUw/vFc+40Rz+UgZ60NRUQPX79HR6MFTy6 +Albur1mvdwik0FJt3zIXrTlqv/x2sMPKLB6UksBiZ7g+1eCbQgd1Ht4T6p3Q+8V+ +fnRXJOL+3ViXKqF5omJ7uERZHhmQEGW2s/1yCxY5G8S4shDdxOvorbeta056B2F6 +oKgBplmkX01fItz4lAvjUA7XdJH4iZHIivml17hp+RtlNVFZ5I/8CUUzARuBaDNQ +Bsp2f8a4Hu/N62sX3PZN7LQWas/DbrFptlTqchm3gNkobz+L+19JFUnUZwTwmWx7 +ersTko+zb9KHP20nOGBYSOMrMAAzyZp3mbMuhVquBXIhtGUsK2c5NgycdH5TFK0q +1ueBSfj4kfgVCGUEjZ7GwbD5578fOMyuvfPAbK/3c1QewADkYws5/RPSvlsORlRn +7Uf0EGrGQsZuAShY039LiZdEFS4U+TJaTuKiPTGeg+LCMwozqsWHGO2iQHltNQWp +n5vB5O0NM+qiQvVlai6ZM4k9enOFZ1tFMtl+RkGGQIolXkzZiC5EWRR+WFdpTGSv +miGtl5PqfxCV5ljItwBXHc7Tn+O3Y4DyaKFWYYKCP9f5MjZz2MvfVBOCJGa3MxbI +NNRbN54xDdZBN5ZPuVJnySv6YsHNfu0E73t/D+/XS33+Codig6SoDuq2yr2j0hkQ +zpVv78FgMaSA+TC4jtGVR8i4pJ28/BDOg+eBTN+7OLGxIrT5wReK8T/TTG98lUnW +FOz7AtZpcEYnxF/U9EcdPKr9UoY8IQa/ZARsnPn8hINxhdtAU20oZ805D4PPBmPM +Ox+/8Sr6IC+nsdUKdPdL77bEdCF38xMl83g/Fw7cW/QJA0B8yLnHwpaxPAo2gfaW +BNJgVeDyCJCs0c6qoZB6FysgtU1zgwrZ5mIydtUJYwlvEVsb0V50eRAIdQTylmFE +Wqh57obxEt8bqfk91DN5N+oPN4hr2ux1+MSBvXgIX4fhiuJuW3CFh9jyObNDg/HE +y43d9i3skUi6Uv284YOg7UIELnnE0HHLzUvpFfK/6ejyJXKEUK6Jm4FForQ5ZxgM +vHL9GQZaKAhxQRX2sYADiVg1VlFbBSqbJ6HQ5nsvkTj2YBYFq5ChKXq07est9SGK +kGbMj1Rjcn3H91ivJqqEuEVeSsMmN4jSTBcGrD9+90vLVmZ+SPDWG7cXuIPVF2Qq +Kjf5zHsKMU7Tl+qA8fsEzQaBz/C2e5Bt4V8PZ+LMV33eHN/WFVQ+1s5H6+v7OmZJ +Q8uhHGO0IHfexk7VbqpWWeM6ESxMuw+Pew0FRN/tBlYfj1/34i32OM+bpCzM9A4v +0PLhov+95MU7ou6KbOcJ6zPmDqWaXKMhS08TioUUqb1osDIgJbwmBRKWNqLYBczJ +6EFalqXLHRwAW+Rx9GfEk2QbdAMqPrE/BYs4280mKoWcppTA09/oKCVWrpBb1yVY +ITZ7AtkkT6HQjP46qjarK3Ngsi4HpD3XlLnLn0U1ac8gLe3rNi/QljOOKYO1aieN +FcX7ozz49moWmbrYUV70ND3YnkhDJ0CN77Ypvz5mrM/YQzC0J/aLD32tZKunu4Eb +FU0/ZuPORjxnJ3+Hk7aR9yIsevwFYf1f/qz+ta3iG/wUslS1cuZyPWSX7I1K2omm +Kx8RbHQ6gdbAU6VguJiv0hcXkjVAEX0cZv7dtM9k9dsQgZXHfo3PMhrrclRWABcf +l4FV33DRf5p712Xtn1LrvxAstV5z1fvDGw/BcnNxltubQFDMH7oyD+tkwOc9ymXo +itVtkG5C26J81k46RRYHORT5v3vIpzrgf288+F/0kTjea6NTe/HakZYJdKM3BkMH +wQKOx4qx0GG9+lBCCB1YdeCytLpAKBCQjA4anxcTxPXD5W0atFoP084F4Meb8pQY +EOHOAG2aId1+L1tVFlZilRz4JAkpasB1k4ecSa/pYDNsf+Zp1TVC297RX1Pmp/kR +CAbRuEbrBFyETStm+8qpi1bYbp9IlEn2pfdjCTeoXIVFZiL+xMmKWqvpXMlJO5IV +RlU+zZVMeRp2QIoNQ2X5HkS5e9Z+ZH9sqn8sLpQN6dMKQkqQVrZfhXg5TRZy/IMS +eGmiZRTZw7GdT0cfWjYw2R/FB67XKwPA8/ZvfQAWIxQVHcWED+MwzQf3YQKHD199 +dMMx++7YvPtXADc8A4WgEytZQYlH1bda2f18afo9ji0R5LL1VN4iIh2PZUQybhTT +zAa9zWiq/2/ec3BzFkAkAShAP+gfxqGhkiCZn4NwnqhSJJwseP8pf3/AkyqJ9Gfj +Q8vtpkRFWFzmiMkZ8hpsjqJa/mmpvSR1QF12fHicOLsi5S1eV/TmoJKPVQHPPXPj +YoASh0B475g6kwICM9PkUH5SGQEOGtyx3bwPEAqL+MxCB+4jkFwINIW7sGAf0efb ++5LlLx7+eBYVEtfwPMAMND0Q4PjXuJnsaFDAEkh+pOcOTVjzntcElmE9nSvdFDkF +85qeTMw3YnS4a3U7tqhCQZ+Ve14onrSL81HYgkFy07rTsKFf5zwi7AXIrKnP1qRB +8yys1wIFvFZv5LnoPPfBtoNZYPmBD9tsXV23wSaJkCjEnabZE+6s8iVCEbVsow4l +w50Al8t7vVmH5FZbevJJjhMcQCuyXtzu4/PG5n+TX2Q/JzrmAWI956+fF+/rqXyJ +PMKy5pTv9dTK7qQzr2dnBc5TO4pGpt3lUTLBUgDYH2mpcdGgnf+JHMPWmjHuxZaJ +afdpg6zQ5mF0RVILu3g8TQ+LRJ888ny8UPConSr0KxeAyKiIrQgv0nme+pcaNj0Q +oRjpLC3gyldkwzFCHQmqhoVfpfmlJtxRXUXMH7KoCK6Mx/5SGHkdGhFpkDV1g7GS +i5kDF1oh42zKznIp3sJMOCUI7QS+4qSdvQn+lROSjKVfTOolcQJ25LGYPilQ9iSx +Jk1sCQnB3X2QfngqQ/cAvbB5iAFihIQ2iBSmZ8PiaD+XK1FTzbhiKWRrEs6n3kVl +Hl0zj6IJ/cs4TGd9muoOqZCBzI/pMpieXVrgSVJRY0uJQ/m/Qe9Xd5ZT3WTVW9mt +1wuJwHwT3neFkUZjQQauKvbuTZ9coeEUWq4hkBHsW9lyvHssjwBrD3B2XadEfY4Q +nhxef82L9NTmIbsbyqGpiGeiRCFY32QkCfTtx7affPvnCuPUf9+6gVAJLi/7ljk+ +I+57Kv7NIqltzyRaDtVyhpfXaub0l+OfFZsC+Atv1v8hRsLE8w9jLLbXfQi7x86t +/ksC2YENeIuWdToTQRJaeOMAq7WXYrFu4Ch8mYZ+ZI611eslEzSFdWmCbbnccz9i +CbNCqvc8+JdgSUMnj/bjSFcnkbuc1/WUQ9gKJ8hlFG5S7c41rHEIogcIGQ8n09sC +imrOzAnHEncNW5EYbiwbuSyw9NFmLNhyQDQt9OKUMUYjZpRTxrzTn4fJJ02H90Yu +7uWnfscFqwV4ACalKKq5LCBFUO6VjL5RgQZY0CKtqysgKGBKu+aPKITFUkyqj8I6 +4/TN/OUd1tsXFjkI/lRyhKfhqa60G3nohLU0ro6woHvCMWEvmDQXc11eW/PFhmTE +QUW+sXfBrfFM0acgJmjqtgrRyv+r9dM1b4CVRE+9SIddSOZw/KfJ2eWxLeYbEIfj +ZT4LRa+fXl4ZURwUrAVcUSvgLkgYv1b2b5gzofNfVDEXd3KoabDwrqmAb2iyisJy +3jq2BlMqEiaH9M6TWfi8on+Ym/C1qpA+vm+Aqlrw66XjOm9VUZKcBt+4uQ86Uy4r +v+xwj28fP1UwdIvir02mZiHrODbl7C8HokgvrKjwj4YEn3ZGOEqs130QvmD855Xp +kB6fOyk0nH3aGRE0HNSh20971uMMUCe88rwEVU4IaZ/hCc53gCQ7go5CQda7yLY1 +NT9grAWwYo1C2L6+t/4ocEijX4etyjPEMkMakB4/yfzB0SfegdDQGwB8feZeOMYm +rOeeq292y6jOzWJDfXVgiM2T8XNID2XV0+q1wNI8OOlyQlQ67tu/oJyETXB8Yx5i +SstAcqoiXxol90YrBs7TR/4qX3381mvgoW6tFCiXjCmmQ1jMx+IFGQXvqWT5Bcud +QdLw118fYczTM5KDwM2XQWUkkD67J66+PljSpm1FgyUx51oG2DvnjnMQPpLVDO7T +7njyqklh4pYJJNt7wig/HCxgY97j4srYfPtQ4WSRkQ7ounTgWRCvR+78lXwiNkON +VH6i+ByUVTic0PargYsgW5vgKgPDK7mL+v2qTR5uJkUVr63ItrP0VHqgW698pGau +NFTKB9ghYIc3gpmB/g4Tx6YHdKs148ag729whiLHK6P9nT1u2/t4jhevX+3YmG5G +lBV/4PXiVVvGZ83FbZ/DGwHrW+ck8xujAIJQDxqcNpcuO3lRyCtyOWR/E4PpfiBB +y22u63iOPiFiFZ5U+irc6s9+/+Y8ZIobIWdiFgq9i5jypsdd4ocRPisjVHoD0F2U +pOdLoj4v9F+zAxmxEoJzQs1rjnpuN6/HB5EU3xftV/90pipR4zOZV3VMfyhBmAMp +qPPckomLFFpTp4IHOzMnxSdOBIF8zWTfiKlFCJ+4b7PSgqVdnNclqirIFXPI5Sy3 +HVPZFYbRvRCRMTPStQq3jiWqUK4bzcJKVNXaf14XchCLqhTCwtUZmoFJq6sJEh35 +xc75oEL4JG8WMp1Bh5Kh7IoCdYrqJJ3prPjPy7bIi4N9IcLF8lzPyp3mFhU653Yt +Z16YXV531KwBEMEOgYvp7Rz444HVnW6k0v3dgJMRgAOt+0mEo8kWd+K8Lxm/ng3t +13dBSnjQ20u7JKqJBamb8HpMsspHnznANLVcFO9oXJd53/T6+MV7mQjhulneZ8JC +5Hp9/ThupdBz9Z0IS6P8q5JXKfFODz6eFzshC1wxmyw3Kftign4zQTn8ERM2RiYp +XTyykCLmSXEaG2AbeuHx2sj4TDYQqf6zGG0NgbeUvSlC8PvFwXa2OrkqZdYnzRM2 +VqDbpZb647arSfok8JbnKQKvaqxppbVvClwXZRgChENzLnq1Vki2tgpb4cn97i/H +etGr50f8FLX1EfPi7OCj6CrJlMrT7OEituvmY/lFWJcvydzXQIzRpwzwALFQr3sK +EFq3tcKRv9ZX55oy00LfAT9w/a5SmvZgvxrAlHCEsGFjrSJ+tbQc0yLzdG2wKOG9 +oFS8FlceOIabBdO7volpq+rfKqFxdlHqXjlKlbqxMJf+NiVU5wOFbYgvaGi0y+8P +fTX0rvsvR+z3tZqR113JIXuaHMUQDkSveij05IxgALboxm7FQnhoGzrYo9Yr412M +vClndxHm02uAobhf2tnxYCeTeW/1RrwrsCOBMbONmeAgxV/mNQNVaT4Chq05M4Wk +6J+Omo7DgdUWeRG7ZP8NReoRJ7VZFL1gvrzEI5qVSzHQE4SlpDo54nwrmITerktA +mw0TEv1DZPkWd2FT0uZVWSv47vpbYKqpCAbwvaaZIIjIefxSd6qiOcZw+xqSG3ng +FKMT654nDFtezlY+wLzVVeXSRi5N8oYBaqw5jL+kdtsof67T3/am15YeFGqMWj+C +KU5SfL94QLJV/Eo6Q/U/k77ud6oz4wLSF8O0TK/Am+5756lH14Yc+j+EIzf/SagB +50kPXFAhxIBFUxWwrpicaNtfTNw8SQBrZkmjbsjcn+svR84U5XIDZyi6jfmddBe6 +o6SLmDKtJBXa0h42pThd5sACfTnvxiXERcvDsot4l8WkXrUSPW8Q21V9bVnfT0J6 +H1LAAx0UdlueNMpxOdkzdzsi3UCB53cHktcHC8r3NUiiRFV7CTsfOu9W2mT2AoVy +Uci9jeuQkR5ZoBDZbYDM/zAmG8j5Oh0qb2QP65FyFNAbIj9LM7/L3Kjo+6lzBiT6 +nQmMj8FSAVYJ7Zt6UwGYIiR/lf+jPMcG3KjxDpdtIU+ROe7cdmrZHyI1jlNl/eaN +CPxDMkHR++966cJSNOLbkirT4SzERAPJ9YThVpXqeD5821KsbbRWUgfvBM9ZMy2H +Wo83JDsZBtxH94kbgAYu6Zim5Ew7R202+DMzaE+ZNAtixALpjjRZau9K+kF3yRNO +7WkoQh/09NdASN/FSZNr2t/HCa/V9+5mxyubKHV11IItQd1NnWjDhy1Ledebd0Mm ++sy+zlJdh1cwj07Tv0ngGUcHtjhERaVOSrZYtWvFwnw4GiiUHHrgLTElY5TrUoBw +lEOx+wmamaaldED+HoR9tqz/Osax8RCyovnNPfPkqetbfwz0difxCGDL95tnC0eY +0p/mU5/LchyqNrXVAcAw0lLAsITgTcGb2/QGcKLIkOjDs+3Wg4PWuxhAWyd38PuW +cJRxoO/tEV0IiZRJIe3YDMTslmONqazs9zxapEHUXzC/EKQXr1KlCfp9O5k9O6D9 +vugHmxPSa9J1GAdAvGE1/3I4qMsI5OzNeX0Klkz6MIvlJRfXBoebdW7qKp2u9KcR +vWyEPYG8+8YemIYTPeY926tN91zHRSPaPCSEknVkP+9bcw+EFD2p4foFjR+MGZJO +SJQdj+aqNs5fCt3Cpv1wiYJlbMQGto2shfKycRcs0WIFclBAaL0D0N/SbldjXSQ4 +MNCs3xQMgk4+1jZW+JewFEclZXuiunRVoy62J1b3c2dtg/b6rdq+cyqMcASc6mEe +zCg7pEzY/aBVXXUN4HMGIuEqPkWk7vmLNQxoILhwaTK7IyhvPPYF+rulKrE2yAuB +vaNQUx1fONg4Qkm/IVvCv2qr+HAY1rtOUGk89tWX0MZF6or5nAXiva12/WGbtRtS +bD0o+gQBt+XKdIyrdkuv6ZsNmlLnW0i/wFkLz8/CCuLGq0JwfVTNZr7OeVNBWL/c +ZH8B4Tq/y5BV+3RKtXkQhWn7L0u7mhgl0yk1XpJ5L4KIIPbLLRRTg6nnMbzXIYy8 +E36w+cq//uoWKR5O78WpsQJkCTTfBrOaEIkz9gZHJ5QPrAM5B3rd74q2V18/VZET +yHZxizMvlibR0Dl7uNbSJcDDBo6SUOsiaJDvghmQo9mKCsTdB0dG5KA8deabwc/G +3s4HhzCTMtBuA346kcBxaY8Lt2/sUSGpAFUp2TNNFe3mlhlxg5a0lOedoZh5iiPM +xeL4qNqbi2O/H/VoK/ElmKtaigv6xU39gV6t+oze9yHD2yAtiPWNE1FCNBodFHsC +XALi0tsRHp8/PCaJ4fhtgxAmARxQh19RIXCBjEAaKagtQXcwaypiJdiAPr+BSDJq +MYVy8DeaMtPZx64ypD/ri4KAbX0WWp4vSgWatNOd7gx0Xwmxqu+T/9RExnURdYuO +pmJ97nIo53FOFHA57cQ8bIpIttdfSzf/+uMzTmPEjnqShHXZLhFr+45TAa4SYNGn +w5UkB6MOFZXRYIyxtzwNVLgR5JksNmh7ObyWC0jx2KGgy2H2AwddvK4Cdd2Go2NX +nXB4A4o8Xu3MKONp3OG6BGSREwPs2W6KLfbC3cc+B4MdLfSxf8O4SVYyggmV/Oc4 +3dctcLdXZudwKk7Uxzt/HBMQO6/BCoR+XqESzym+LAQsXCM4JJbGnddi0uFc+NrQ +JDuC360cQ9Yh8cDogThUf2KbZ3CbNv3VU+RkLXkiXyNkijgPFuiSmtO95yvnMkZR +FM8+raU7hq5Klh5rXF/7ackszZADxg2Ap7OUOl/4QuTpPehEbKOcGQRuVGJY2m2Y +Dp6qwGwhGOOk4lN/+uZYpTPcsZ28rLGZqEWAUu6jiWeO/UReutafNnnDTM3YncJh +eOV4inJoqLpvyyHPEoidaMVZIGBMRTbwPrBSKxYsSoI1f2Y5kfLi/xAnzvdnlTir +vtBJZpQaajLJPQvLVFc2/PpH4r5i00weO8oS2ImAly758h0XlEwveiPk8yh7e/Rl +oUt8jVfU/7TnTUIWhA9m08+zy6LdTjqpWnepQzqZ7KvAhussqRjFxZ89WuXJ4XxF ++xRlo2FTDWwe4N//KLbDaYUF69Hl8gchAgF2fr0c9QXE+bHz1BEa5CdgltLjWHpg +SM8yxzcfwf+pMmRQqLxYIOOACm98Ng9G+Rxsn0LZbZKkU8xY6e2SXKm1pJixIYQt +9Go7gPg/tH9PFj05MlHMbbJNvYk8LGi5xkVALcKcTDUzbtvxPVg3qDAbEKXO6LfV +ZGChVESUXhV8k259vihRlsN2j/k6aqtu6cXmCIQZQcQSeo4nROC3Nm2oybQJnwYK +MA301VgPHeDP6dfIGcR3YjQOwgRH7EzA8kOSXwTg8VMZztHIlMBqtKCxQhoOTnS8 +m7C99RAuUth7qUlP/JRv/5XcM37xy28RaXKNArWeMk13ABjudWiwto+UQBIXyZV5 +4+yjRK9vEMfV/wd6xL7+gAjQqGvMuOu8TCrxMD2lIx2qhLFgKFR9P3qCK3bV6XJp +l1uV91Bnp0oH/YuQFbmVHYyMazKxZSSjF783JESJ9oeumICbSzHSUPr+eSYiemOC +EKA7xElct7KMihCIsnUbLNAoT5arAO1dLgSfeaMKNFgCZPE6k3jP7G5LIbEib/K7 +TUp3hPveBzIs8TiCitWAGQhe7CK7eYNh6VN+fK92vKtXm+OHt1LakM/JqAMcSr5o +DMRI0SgE6fn6UusQI0km1LSCGv91C4u9nnj8TU4Hcr28V5FYsDgF4M22BuN7QXF7 +AmeFBI6hvz8gYv/P+qDYpsEC8dTAG4rp8SGD8X61mPJlW2nxqxR8zVDroRcg6H0m ++y5SjJ5oemUVBQ3eza61VB/CYEX1/KkW9L/PABTZvfOJ6m6WR6MhMu9OTu59wtz3 +vB71JhRhHJ3KYTugGf4UIJ6c6jxz4eaYDcUZ7KhyJkfqA94XaYpK1PbPiOZLs4c+ +y6D7OcoJ3U9E8f/eG01nxXW6nyD6azSTvY2B9ubX8vrFI6gndNJ2VSawk5mXDXNj +MOKNLBmIIF66BLzV+rQjgyZyFn3IgO9PUcIzSZjnEvAeLkrhvZvNKTpaM1sAJsYL +FHsA2OOZKNITVdlyP3TO/MWa17Mi3rqzI3cFTtrFr/9eQYHx8t8WyMLEu8ofmAyC +a8WaltN9gv2lvWUQD/ehK+WM+v5lTa2fH0XmjfiS0FRmEUmk7lltNRkko9MVoMkb +LFE2MbMETb7dJfH9ibAgH4ah/8JmMaIH8gtYKbcKKWmyH31nbxlBiUOtLePq/2IC +GPi7GaAxIFjbo70HaEmIgBlf+0R6EMRMG9ZEV5Md7hwgooHzpI2x+IeZeEbSUfdj +cL4OHvhZ/pDlqdlEbzTO1RxmI1Wa+/LipdMlU0dF9xkt/ogO+2BosEzlWL7PwqcA +hBwjgzpOrESDsPnq6gBcfYmDkMMIXVNH1nX3Qsb7xckPvKOXAbOWrDY+6HtfjxY3 +s1whuBBsql4DzImBZ8TlvcmYmnK/xmjfkztXMgMn/1FmVQxCHUfdqbRJLjo+oPXt +3eMMzJGWZmajiaTPUIztYe5DkSq1JtmodqYOJnfddIzRIZYRZDQj+7Ahy4590Z3X +Tw9OT81DMW+HR04Amr7s9Tc1Zz3ow5HN2lJ4zVp0184j9xj8UHXqNHeBziu8n5L4 +46t4V6p8n2RddE8IMbQuFia9Gqgn1m3SQaBhzKw16FqiERZJ4d7cWuidfntaCzuh +oyW3hjgGZHNNmYuwjIt7sCqHQWG3dWVZ62oapnyeNZL7SAU6Z02RvUxvYUxIgLVe +CFio9cazrsRKJxKwIZpzHNGSdZ8XZOoyUBAKQ1ZUdxVOp20DLWwczlk6NA/55HMJ +hhJAWgCxwJWQuOJauEVf9jpS+8CqS46JdAWcwg1Y5abNl5WXVrFLE0pacclvfC+s +alqd8WundLQd9yhlbg8pY58b/DLKwZTL2r0fHcJioyOc5tGAbQMpttxCgGHQf36x +5JwsHbDAWYP+XwgFLvINequFO92+vy1XEl2g9kW526x2VpNDp9sdHxyg9+eTX40p +w3yVBXkj0Xaxn9qoABll+i3uGemZR+9u1YdXhLLxesNjXCIdvM1LkNHVZJ1C9H51 +NBwP1wyJn1tvW4j2ME6UVNCbBc1xIfMhm5hSJT6RV0gtx9QBiinC6wzA/8vtx0/d +ThSEPU7FW06lqNJ3Ix2gQimbTZfL/7tGsIHjuzxA67eSxr4O8oVXCm76ycLPhNtz +R/vGj7CLBLkLgK6JoAncYnk0YMQ5Y9vpZc5gqKcgHT4EoE71c+aYZl8xiQfEN9eA +26zMZO4D3wVS9+iJqMcPGUgpnNziO7M7D8dzEwoFvA3I8o9BglniYzNqPqnVMkG/ +haMQHL0yZNeW6+GEefgZ11rtRXCzP37bX7Vb901ZcUA3ZiRgIvPkboYwl7hHW1Hz +h4e2dK9hBaQXVAQSrYMA9rvTcid9Y3LVJ3qOmsa/I2EJjgaZ47bH3jHDXNLkYojg +ngkJ1+BynlCHNaXCXEb4YgJmPjL6ozZ248oAcsoqMZP+WE1uTZPII71Acq4te9Ta +xpjqDTjd3GCdeAiM1yIThUPcCObnF56RlaAY/q3SKGTUPswh70LJd/7UMP41881q +k6o/d22jiAS3S/IJ3ElJSY+jgURKHgNRMKKwM+9q2f7SWgKOV9CIaSYqkAeGy0Cv +PgqYlx8TTzYD3w3cNsMqYqsETDGAyqsOkgj+N4qYARfZwxPJnGwH9pJ3JXA9BnvU +SYcI354HPZrPraVvONxs8KCYhvbC0GK4wZwc5Rcyp5qZw4ajvtmedhQjQLh+v7rc +XBLeRSD0RJV6ipR0cIvceCd3yWV0sH/r755zAuazoAJv7JESktz1+6SLJxJwtTJn +RrNHf76Ecz2Tn3E9hulLgb7AUVZgiorReTSRa1vxWrOiuI3SWPQTNeobDBJ+V/Sl +ZE3Uw9S10Go7pYHxBjgmXURSrQsEXZedu0z+/d0Z8+VoeqVzWZaXk6WnkGJ5Mh9P +d/EelTjKySOjNMmf3DVYF60E93wAVidtcqNErYmUu7KWJMzsz/9/kSbMzuU/agNI +nWEbNlUnU40/9iHCMsLN8LW13xTknxkJtNw4Sp2cXy409tEr4wClr25VY5vCtKWX +yGQ53oZkjUkSnzogB8mYBe8zk4Mb6LcDoM60Nl48SciUa0Q6+k2+D+OsfifXtQ3Y +M3QCuZYjr99hOg/vmLet/HC2WSKbge+VH7JFNxC/KfNoJdkydauWbIPGHJgoW3I5 +gFnFP167T6Gapnp+0Zq5im0+tN3xJEVT3Eal2O1L2k3KPcaKw6mFzJkfLQZJPI0q +UBfn3RPtz8CNb+v2HEpQVqbxt6Hyo3rh4/xMRP4gdvasVeDyh8l/WJHBIVbaX4WY +oHa57414vvLHXqD2jdwBiOWaOELrFIdRx5v3M8z99V3YjPAZzD3ujufu4J2I6+Xz +S+o6CEgo+hJ0m4qGKwhZrCcJmMmrvG+EZybFnLqLHStlLvS3fgapPZI43xSrzpAg +gKAtxN/vLbjWAJvtPxxzMZzB7sEMli0uSiDPlor8hoxz7zXHdK+/CefOy5DYhzjN +j9M+4oZrZIqZFPycEMtEnq758banKH2AZhRKpaAc0uqesmG9FWuxszenilzr1tf+ +zv6QhwZUhU+2xwGuKryyoWviaFu9H3hhUAxtJ9SV3sZ1/YwD28/5Um4XHTLcupCj +kKiRmFxox5GpM1vFHhyu00Ce13F3MfXU+j6vNC02XxKN5LoRvHCaovIEQzzPAcMH +ZgEdc8Wslk9cYg3cOqbZPSPSNl2i3aanYkB3VxT8wbLCkxJQidY3AcsEtakQBdEe +DXOuo//TJUCwJn8t/TzOyP0zDrnfdy9z54zHjLe80/MUDh/f8MQHNrYGDXCCJwuK +ZBVhcBdVMpDGP2aAzzc4XnsIJZlhj+Wy+TcKpvqtfOKMMWWRjows8PVjatUTPrq1 +sdAfwDvEAXBVbMXGpuTb2Lt1NBYVEgOh5D06T57C3+BFoudr+deDanYWVVWIxZed +EqH2uNht+Ekf7HKweghu+78mtxFQuinIfN549Tt89NYApOz0U2SrcFPm8CZoheBq +6a3yAozxk388yPfUoTbRlXwFslt94k18J7RbD0CIN5u87gHK04Xm+NO4d7YpfBoZ +Z5kUC8DvT8eysRSi6MGHp7ZS+MHO+vH5hgSLmOEllq3xD4o2F9WlMPLpCUbwrELg +4VxFDIHxqhaovTNmATBKYDepxO28XrX8oudUQVAZHVQDbiJZk4zKRE0DBt9QeT0A +6fQ/l5WiJdMBafy6jZlduBh9BYnQu7D+FX3l72mvCpqqk0T8SDl3k4F/IiqN9qw6 +CaPdSA1Xo4kRV+JHfywi1O9ph6rQwK42qDr5ZqMjQp4SsblyiHFDEmv7DKYBC69B +I0LHNse3sqgWKP3JlvK4Y1Lfa1+/I5r5+CETR1amesRmLgdAdmSrJKPt98j6Rk8z +rRNC/Fe+dGyKLBRJ0txy/R9U3Pix7o7KYk5LNwr1y1Xd/Qe3YIsTPvybk014e3KH +LTwWFpxtzgBtbZisOV/iMRYHUdzqdbPKNa4fSv3+kcfVK+AAeKvRlrBpZF4+S90k +nH44PdvRPPSLFz+LcC9Z+8/i97gwRw3mFz57fK5VRlnJuAb9IIurPJ7sfI6l0/cs +qo19gqCXWXIMUwX0L1uszTbIShkXLU1O/0Ef/3ZOBGNu55blzjcVFXZyshWcv4RM +KURwHMRMlemXu9QH3MqDXtiUTiUPK78RT8e+8fVIvm7vZ7zYXVLQmHA4vmsWbC7Y +kA0/sSB2DpGeTAZpnZL6dG9Gb1j/NNukeSuaoOp2Wo1C4BUckJ++Xm8UuQADEKIi +n55O4IHQ0B5RuJIE8/LPJJdSuhGqA5V3mK1OgdMW2gncshS56wMZfkn4iVVtRNec +3Nj0jK6TfPHjZisMn6me4MFh0zRzFGhTbaEjxoXfjzbjG/LymOcTiQxJKra6qTOj +ex1MaUHysSw8K1ElS25u5zKRxhc1+wKMdWKwoE+i+6QkBO0ed+vpybl5ccLNNL2v +EwBoXVk1PWyoKUCW6hLIBum/zH3HBVqaqy0uz0J5IRMdHySUuw3HBwaaPEqKTavj +c+f2NovY1wuFHlVMbUog5TH7s1wAMMjrHnuTOLvEZQpEKc73/iv1lw5tmJGPLAbb +TxY5Aw9bWRyGYTNRaNSVdNZKgMsUCNvivEu1gMCHQ6h9qBPJQU714IBqZ7lPGl7L +iQ/QqwnpQ6rl70doHqLiqgLP+7/Bt3UOJotRzEFr+h6VDLqCf5Scj6w9vIOB+JDW +8bYdXx4JEs81EGhrNCSsMZH69rVMTDRq/B0Klow/N5zB2Sd1OIjfyBv08ScIN+46 +aPddh1PKyOTtHYOn/DvjGG9646o8thHdgL2KXlUeDQVjuQR9MPjilt/XbzGPt8EK +C/gzET4maMODETtxsVhQJUIeSvnSdBJAF5wKudWJGROaLhw1+w4xUsrsW58OwYlz +SrtTLnrcAFHFS2s/DQmbHqikiG8JBhnzna4wmTlJs47l9yHS0nb2l5MdjuxqrRMM +958mGRFgjN2EjLJ7ZV7M9U4M+eEl0JvSPkrhvA6AgB6qEK0dv5UOuFNXmdQ5LMde +wpwTGtC/jNFdoSD23HFFBpLQWjSl8izUJ4z/5D3fCxDnEcsm6wtKE425QlvPpoxU +q8eKQ7fAGR1ZV2/AvvAhix23G3Y4mQudmrzjrfuuAe0EXACpt6CtZcKT1bPIw7gy +T/JM0PqvGgCLiZeMbmZDU/Eb9RYZ+1wf8K33m943aCxtDazqYrJJ+sXeQkPsCUav +miBeY9/PdZLKOjU1Bd3MPUV3ZwlZZET/bMMLViSpNWadNFKuNBgTbr76Q6P+Z2jV +0N+WqPL6n8bs+UZP2mfI5IHwYS3OUpiMuAaIolCZ8O5MyPwaCrIkcIZNcvYSux09 +e3Yp4NhQbGN/7rnZqrO+5m6Cx6gyXWeTwkLGHKrS0BqMlS/7EebxXtw9alJFoDeh +WUtHaD+QgZnGBEWZ4CS8wh1M/BxV3UuW7wm8HdDfNDMBQcaNVGiMCHI+QTqlSy4/ +RvDYHa5uF3pn0zuvuCeguVmbHxRTYZc3rt+tHCkKlg/BZVW9mTvu9GB0vbZz1L8L +2kroIOfptJ9O4zRbD8R+mwF31vCx9GecFBzeFTir/r658H5nG/GKuMXdWQ6jytKV +/f4XpPzt2RKSc20os6a8aSdUZ6xTrmQghgG8+/uc0UXoQnNhYtg70c/AeTlIYYdY +b6KOeyI/2Zj4R/VI1U/Yu5sCMSnGozwKhyc9hAvF0oVRy+UqOdvbRozBX6Vwi0Fb +a3sQhSB+jQdZzakAPNLXgSZO4DCfAOhsBOvkRVIhRDmbOF2qULArRJ/v3QToaHFj +s2YjqOK+kH+CzOAuhRc/EY4lYnx97l7A6z1Lj8B4LN/r+hFm+Z9EMzW+xazgUXnc +8NY5LQPoOTa4lyMUwBo0bCaubigkRMccQAn6TBIiTOb8uChVPQ9I3bMMIta86//A +GFymR5/uyBPJAE+vUNCAv1B18BZuT+u1ZJpoWcKCh9r6+PYdJHq9oKHgUfRyWVgt +iIxddlmjJoa2UQu290i5seScks3AyDYKcSYJyADEZGjdj84/4T5dZ0A4PzGlNFdk +DYnAJm6WScC/AIpkAi2jxuzMYM9+XDsqyTz8bjVXYNg9YXfYNEH4b0YR3kWXEbWU +LYiJqp9H/i3dVtZpWIn6czmeejMrxVVnvZQNuLIx3tWmRxOZnLTkfDzbsJdmsgo3 +WbjPv31LEagB8pE6nIov2saXXG9cjKrdKfJCCggM5DZZp613ZoM+idjGuG3BMlTO +E/nXUvi1qH9m8sod0yc7WX9UBrvB6BIwlafUu/ydsCTfwHKpl+70s9e6c6zkyHfJ +0IEEf7dIddobJwiHwpGO1LLkgFKjExliX7Ifd2w3xh6ijxlR+jTeAOnCLQ23aO6k +QUF7DBWU0fsJkWZs96Dy1PPz2+aQ1s4aSTrutWVzRacFtAdVFr87gKXfu5KmhbJp +SPTQg156KlOn9B6Uzj/tmirem/5hfDRwWpAh521DkO7sOst+tfl8e2J8xYI/jrZY +xtcfDPCg/SpX/3j7NENbwlzYun2svIocK0nYpnsc4SXrzWHbjyzkIfSMmUH3Bw0G +WVjEqWDBdSeuZuzUCBzIqMqcbM+sERVMeF4QHVoznFm14geWnBcwfVdGup3fGxMa +EDpSQvigND8N1AbDMh1WeFrny3XHZ9knmpwdof20K2o7PlPQZxQB/lX1pmVPpyal +TnhNohPC7WfdBKPsX1d/oekGkltYYkxn/jWey6Od7vqBhTvfLpaEtHv6d8F8LohT +Xofmj11MJKlWwpquAOs1V0fTCH5YD4BJ8Pr8fqQ/qdwMdWZxMRZ+BTw3MwOPwCrw +ZaHrdqJvsfscqVZK0nA4LCsNDeoyOG3r0ccbcmaG8unRVcfG3h8UMnk7omWNaNoG +JoXnEYIMho9RerSzHg9Lp0OL5k1xcfIOdbTzXdzilMhVJJuUp8vjzbkumiHg2wge +8+IlkBtiAPwMAuvDZNtaLiXzntzXht3OPr6nUNQluBcaN6BXdwXvR6Ipe88Q+CHm +IGxp2sVGWAm3mhwonfo95QZwqOAVSTz3QMAnJCqFmgftoppYZn6eE+8bfSxHGzRi +ukVZG47esYK1mQqji7Eryay6K8b9NS998xbPKOa93fmjyQgV2iHUaniaicUIz5PI +wlus+MTgrXtEdQGiYfilBKvBiLLkXrHw/xAE84tFBD9j0rlZ/D5z7BkQAfTpsVOW +LwVKW7jzBIOnYY0g/kUMugAlYkN7WQQdpiqw0DdshS9NVQ/XC7DWxqQZrz07jLI+ +ac/sIto7B/a6yqx0zGsl863o+62ejKfb8QHhlO4AOx2fDY1XwI4Z0ArrwLgqNpwi +efMAsfmdbtU6hUVr3kiGexEfixr7oIRmeB0+HrrB9nbxL2qjJeDfTzGgVkqJorKO +L7iHfx+1fyQ5uFB/9XONdfZIjIl8zBAsgTYqXmMoZ/tQ7s+U5o9yzMqbYsiAWpnM +1Sr1uPHa/Q5i9a1aDpQXc8T4aWJOvfsb5/juEKXuOVjQ5Rjw0Wq+1x6SIavStGe3 +24n1zkQedXBYHSFOL/anyAHf4AS0jZuyQf4tzsN96l8u/EmULNe8111QpwiacVh9 +latcP+27XrfiU0BXzuabC3CzdT3KGc51oRbWGIzsw7LekU4Tj6lEdUTHuhGlzO4x +GxZ5iWKqMiRHpP6NNgXT9E7054I8Kj8UPe5vjXoFn84CLKEnZSt+zAHykMzEvN3v +jgMdADc8pXgKUDqnJ1S5Xprh7E+hKLGujgEsk6n4TPt9ZfzDXqsJkrSDfGTNb7Pk +X3XK66BQLMHorxW3+HBB1/5qT4OiREtLmdGir+XLDIe/Ql0/YtBKf/+AMn/qp2og +1tfRDFeSki+2/o559EFJXV0YK8mt2Kpad2fXZNB8OrWmAVTxXh8xBNTE0ks0V+Ez +UXoWg2VD1vFgcPyekfDLtB96X2AJeZochvhbzVsxIxY6fpgLju73XvqL4l7Ac6qB +Cvo1ky37tuEy8wUo0gJ+fwEfSynVayKoEZY2+K28Nsm4gcfAwL1HYI7TumYe+Npx +D2sNFNYkR5umZritCzfRED36v4YRPLOw8LJVcjhsquxyW/YM+u9ComO+we5MBWdq +1UVUnuujP0O0HPzgemVVB9PLxzGjIdNsyVf2cbETrF9olqicdmuKoLs6JrNdKTJa +AfI0qfLUZEwQNmuQFoUZNnQzqiWJbK80FvsQba4SG4ebHmg7KsOrzVdLQPnGSaNI +GRlfd0f+jrRpsELV3awtWadOhAFY7g6PpML79olObb02r0JVuYHO4pkFRVNlrfwF +y5hSVSk6bVd1Ta4gUnipjwT7mq5tuKWgCyHo5ey4/5RTU5fyAXw19eGbkDvzYyel +35V8IYSvT2NZEqokAUUjGL/uyUQ/E1O3qWEaw9PrNEEnH4HmWIJaGkHk/n2eZUFq +FopgVXnLJ1bjDDf5obV+GuSUq8ih+Zek4XQ3UlMc/spByWMOFRtr8d+S6qLuwE8g +yDCTxYmJ0FWdnwT9m5Y609dTAltDFPfnH7v2Sv7DUir68GMFzRfpz+BtEVmLvirE +i5vpLcQP4bRxw3tvTnvGnIZVo6qRG6eq/5jJ2xUx5zZ73sGpByaJ6fqrtrVbYj7+ +xywyTFyX5XD8zuLOmCZEjMLXs7rGI9lFOCB0fHJObJpb2qZ8H/HyUCp1FiENIuC7 +mSY/zVd5YiUO5L3Hi98oGN9VZhlXK+LPa/dU23PyYJXHCF4ujfY+1n5kEWN4RDkB +VuXJ8+cAyZHau4+oR41QJIyxcO5slYsEbl0/bF3XtC1S9l6YLwEULo3z9F9888YC +WESGLFH1OYaBZ2YtwaEVrlvX/P7bI+rO0/q4oYYmarItlWoM2d0D7wgtj8faZe1K +5vjcidkoxqzieojZvoQTgTVtOEXbVAafNErwq2I119tDTJ+m6xLNaNBDUCOEf//u +Loh6LThSIDX4JKCKTLj/E+IVE6lL6LTNxKjocUA6fsuprOFNhzfG266Vtmt3ra6a +SEd0BdnOwQrQotqLrYzXHMvVPlI5TDyYiw2gC7aCvyl7IyDZr3HNYAdVwdJhCZW6 +Pr/3zhme8XvZfgnk5HlV3zQxOSEHIxglNEaUT3+kQvHPRjyMoxu+t0kcUL+Fj1yt +6uPmY4O3dKk0rCSsh61t9ViRnxtA6KEq6LA9SXLm2b3mWz+w1+eh5dCftF47Xcf2 +NjB6VVKN3m0+Z+fgTSXITfscVJW2rNP5xQNRqb2oxofpnOCXgmJUmiURF1+oh3yY +JO+zCydg5la4P3u3//5HMAOzoNEVQDLyfyRrRCAAyhcKOV372+zXLQdsTOs24Kqb +MR99H3y7v0Zv/zEuZfyFimqH4tEbniSfwk+ICK7+NzgjPO3G+Dibmzr3P4m0QGra +Gy2uP2vkgfCXoRKQMYMBjqJqEZWAxI8ak8o4iHzIZg2zGD/Ujt5bW0fpOwqCg05M +HnWrE76JtW395PYkzvtGsH5u9uNs9JYSZEJfzLyw1uoNbbRaNpacHZwe8M84I3Wi +iOzYTZ7RuLl48g3a9pAs5FKIx5DQm51Lee8IBfOIFiCdoBOeLmZwLuY6rLSv9brL +i6rpbI6ojlrL5JxgfTjzyH+kUfiOrn0S61TIKeS4Xdej2A9/Pf1K2imNKl1qFjH+ +H2gQ5Vdped1Rw+3J1xnHI+v57jisK5UKP4ld2yiyZfdUE6Sw2hQ7KNS7q9O5/xOn +b9sC+FBSe9S+MAp2q9Km9y3V1lnaFLBh5r1gEqfxGvurN5nsZYx64zPRiIp6kCD2 +bfRGI++PJMt6uSQZb3U1DPN+cGCUTvbRGqLgBASwdqeDNX9hGFlveCH69vsEVeJI +C1ghQJqSfXzlUftd17w/bsWoRqJ0/bcKlGxXzw4SRL62Vcgt6WABlJ7KR6SHcsKV +MILIN7AWgLYpH1swyZCDXtz3PynJyaPNeSJqOBoNDbp9wjoBJ3SKOgf37wf3SCDs +RAdekhe2ghPGlKmovGTZ3pEvwsv7DvqepUUxWzV296eiINhEK1qwx+kfIRuuO4hJ +Ar/h1zECB9h9kHdGhHBn9E2waaFW3EQIJO+iQSKAxQJWHjTCsKl4gIf9nf23e2Jm +FiDBKesVtNGr8KwUlhrljgEewvWogz6gaOoHx4nxW1F23erxAsaVolQO0otZWN2P +ATQBtHcytH42ajxyMeBzkUXTPWtWFhI0CeMH7rsMPkHeDIRsDt7bl5LxxRm4Hj4x +rgw4bpEqt/LEuZ8q6eOjC6NpEZXYMAQCHHJXbDmvyCvqQOjvB1pWnhilPMqxP2TQ +Ni8SYyLinIcMGuL7E9FwVF2neY0+wrYy9myJhpp2hg8Mb8O7zPdhZDp9cwlEreJL +G72Rge/pp7BWrmum1qBZDgIN3E0gglgWXHY9yO7gNQd9Z1VITwXIwpDNseICFvGf +YiLkjJeids/Qo7kKGHWpBC89hdIZQstzxIfPlqYZUEJteC8VQ++QLYU/o1tammay +IeRoP9q613VKq8RSY7TDJYNr/2GEZI2wQMIVmtoqr3yk1a8lSDAH78K6/2khMi8r +K/7iULjKNXWv26uyEyIxirZuzaaB1IK4YkiF9KC3pHE/hYqLUNNrMmr8IHMH0CJe +LNNT1NUY+u1gMFGgIDWmf/3B66qYxagGQb5TYykyAWvak7nS0NV3yxYyscWl9Aas +65kTd5OhjZFwbkhv53i62Zphh7VuSYF9S7gV028HB1v5cIbiZES6qMcNloiC8OGI +tRRrk6ClgO61NM1oUoImsX1O4UNOeJPKt/MfScMzTN+qKGP/iUw/3gFHheKXx2Uw +CmchT9WRZbFYKsMT6yLFrzxAz1liCTD9Xpo0Dn9tT4Nhx+rmPb1fd8uttLLRdToe +OHVlK7nlFdygyFeoKD04HWHxtQNGooT3s9tCuuS5ePdu0rukq204eCX1sLoVXJ5X +Zu8axTFfWX8krm8wR/Gq8CWp3JvrsnBH/eCP09bSeQNh0gcQg0JAwU5a9Fkqix3X +eQxOUeTcSUxPYhgFzK22cym2BH5JKZq4B/yWIk5+SUjnf5ZntNkQoBXI8wtUvWvW +RXItv42PUpkiAw+rc4scTh+YSAUKfZYbmtU6v9OzqKK5GNeij6YlS6qAHy8mDoWA +IU5/Tw05aYjO7gATrIs+lyufQMfgBdcBp0Tu6ofvAok6lOwiJ+BZSBT91UHhSAov +KapignMSqDd5FHrUFK1pONzi7zPxDbYgEQPEhtIQfcmf8b0s/p8zatPcNAq34PNr +o80oqZHIVURKpB/SFzy/gbigIlYo9cqpiRNUnC0Hu6nJgn9VAqYPJlcarrYoHzh+ +97GCDPAB1cxu5WW0LFsmpUVVntcv/YnoAKyWfBf9truqwjhkX/rQauH70EtBXRK+ +93xaIoCeW6vyXicsM5y/YCWiA2cqOPUgGBsPoliLiqUJSzhU7NhmVeaLNcjkQ8ar +2Mlw9fh+qqaRPeO1pUGYyhNWcaw0PcM29WH5rXkS0R2kn2vZd1t+2V8h2+FtuPSk ++gw4I0VD0yyn3M/DeHOHIIqV7J2TtHcDFCgRhdDVLjZtcQtCMp0oy2WiWDS/DGs1 +WCq1TcanVqbDhMr2rPSHtJJR7yFxu+gatAYdA26x3XK4JKTiuROSZlsbZxWj8l48 +/TPRwtVJkUHteEG9OrjGDrlhxQuUoIYhpZWEPUBrExQPLaoR4ywcm7J0PagM5ouz +PJl186+uk1pfhp4UQWa8u99DoROxDeWzppcz/DFom0Iz5dK4Hdu7W4PL+Xejugqa +nr3d4kossi+yDNmLktNCXPzPu1B0UcbUx060jnY9fzswWF6zpzne+ytAMAh215/7 +kNmRIUC8DJyt58hkk0rb96tBz+bVKwExkyfhctkcsU7ye3dEdUgV5fsKEBx9PMbR +NYwzBiU37R8yT21GoMw+tcUl4tDOJRD2u6H9QrY8MVDnEbJE3WTGooilyxkMNJac +qCamyz1edRjhD2WOHxwg7I1SWI4mKzNUcUW4s5KMeZN5pzYvdk36WHzabMebj9bv +jMxHvtg2Km7h60O3UPClJdOOfuFiPNBw1hs6W+2z22PrevToTf+G40sRfIG77QbE +1OlxkjRRm5YFB2uc6XjAtPGRDr62Qf2yWctG6Rtn8eQJJbK2eO/eIut87QXI5TrX +7JzCMVcqRzjWuAIDS+3q6+lqpSxi9rEDXtze5eks8nK9PNkGYaKmJxLXYgZYUY2j +NgXwBz0kGZgUgb0bqnJ+HAv2hmDC84gIPQmZpBOL9oaIQWqWzdzOVJgVLx0s+7ed +OKhXnsc4AYOHG9JBrhKnhsaakW+gXxp4SN49iDtmgJjWLiqdijEcVbI9O23AEK8G +CmszSoZwhxfdOkmVwk3IaHm+7Za2o8WVU005cg1ZiM1u4cxUJE954Qhk/hUOPNUR +s8lDqjws2MVesf0b6qtuD/9T9SZNP3xJf0ogRY87H6jABJxCJF9IA2QYI3ZP0Ai3 +D6rVPVT1YSlTLpJRhfHR8u01XYhqbGksFhRRgmi3ymKFcWh0n7PHmmVT6X/p8fLD +teQfeZpIZNQb8AhyX6f4PISbsYI7s65Aeb7FL+egkYt1uBPgtYFrub3xkTr3tTOl +CnYkbxOjacohQfzs9Xri3sLY/lvJ/ItSB0mZOtVdZuCvlgcPCAu4p5UfvbPPsPdX +aXS6hUU8QJ/C5Ld6c644UgaRo6HeySkzU894MDzv8rkxPFDaiRXVc2ZRTGSOXpHO +JEfb2jtvKLhMDZORVqhAsqKqQI98s7awCGX69Ko4dqla9FtQAd4sV27ns9U7HVRL +u+QROif/8xu3wNGULajA06Wzkk+45dyB+K8Mnjy3ch1Hfmso7mYEeGwAQ3eEo0S0 +w9q/MzjbN999siLZENwkGnIHXMbltjVz98+X/vedU/jgt/0EBb8JAvD2Hrw3Q4ZN +XHbcmsL1mocRvq3sUtNtznqIfRUwUqXvqxa2a9xwj7VzrnFoUDFNUzPKx9W3jmvi +9g7nvBGWJ7DLgll17GhrWFPbn8BcqHk3ub/EfF/xuX5fML4zXuLhDRB31BSKirJ7 +ZDxa7zxdHRjPp3ivGM8kEqDRpJOMFgx3SwdD4MnKEE2kr+kq8kUC8h6EkfJ/4HtS +j7HnSM4jmWcwbSotyZLYHj5mZ/PS7584g+84cLozcXZcfDP/oWDrkZPhDBpbqp0L +OkTfiNS2TlOEWfbF+7rvTc84cgQW8LYQxEki7E6AbH3QtZtQaXQVOrt+ACD5nZyp +jnAwKEITWWIAqrAKkl4tkr7dGlT0UPZn+7ewfKnIg3EITIA6Y1IT4qagBO3SfSIh +D+0Qp6ZVrrLNXmfAXWcCZzcVbJiM/hvIqc5wsLdp2i3G/yElgbs5qFCFd65eWyKi +tpwqWsPWbugxeB9RkquBhKz66qWwflueN4SCMD1lw3TF3clEBZ0Akqmpuriz6Neo +12FkLiKg3OyCya1bX/i1GCUwC/fb/h3/cf2QY2hJijmtUxU7U4HVkbyquvC9quFk +P4nKypfps5Awl11wDDaB1k1iqkOWXzsq+KjgtNtMx6pEhqaCNjqiBQE75jOWl61C +wBSJ46kz/uo2uDt/747cbcPKRlxtK8lB5SNYA+PFAfonOUx5kAR1+gQG2VsXM8EN +1/TBrkL5CYU61TAHhNM4pfx4jDnbEVByXBnRCiljhry2HC5GJ0D++GNAvq0CQ8xJ +X9SVUY2HFSUUwOR8QOA+wMm+sL4zswsNsuWZ/U0vVVE7i0FgWgYBmH6/fp0FJ/I6 +9r+n3r4YZvJB/9apgX9CB2/T+X3eHEtUNWn0r/v2vGZXUqUaArPfdDCq90OfsT7S +UXgAPbVa8rAYrSZJjfdilev+LUhe0VRESHEHMy59evHsXPfT1uU/dq3lsyfn8XVH ++Q93/LdN7bf4DWEKLhf6N32xQBI/PT1DMGP4hTMoNhd3UwCJDQvTUbL1eXtY/X79 +DInrx6W0ySKqoVXadwzdanMfhQMUFc0CGmPttfBWeDTnYe6+QlqpxQHXHC1kn8xl +NOeNRCai6OEwVBQkFhaoQRP+uU83Lju4XyP20LhsYfKDItl7UiMRZABCO5yU4XyJ +MhEprqAMUhxJLZESgu2/B6bvZjJfSN7H9KljWJsxQHdzuIHsHvKM/AMIgm2s3JhQ +uUOHL6QpMXTlwfVxOZMpQHG3hWY1XG9HYepSMP8jDlcweSIn/c91HJjmsxAN/taN +yQP/C2/jtw9wn6XOWZHz/9h5Sxz9RSO+zfWwJQ1pxX3jOYdjZ4YOOfsmzzBd05Qk +VbMIdmbWvBTKlO8K0GCwP5OLgdEsuISfSG5hWsBFctVdz5EJjmnNPKzBJhIw9/WI +Vcym7Wj8gXSvz//aTRWkl8mY0cSITsvETuqxsOiqujKvlnUD4uku85UZ7VGpO3Y2 +qvULy5Imr38JCsZ0q5awnRr6ZxXeD9hcDEDrnI+46E41LAYRfIceJcq75GUFGzu3 +N/kDqC9TQUKkC1RXNjXdBomf6xeRAXOEe8hhKQHNAzFYUlTF0iIK8Z9w7XMRhoNq +09ZKaG4Lj4f1Yk9SL86gSg1OXSIE/xdl/9kFaEDowDhvp9Xwg3BqjHleXoBue2rH +bcZwsV8X8f/Vl/c0S+YwOXSx4g7FkcmaIGhnTkYf8+TsqEmTtG/5zawgaIOrnvpF +GP2CSSaBKt7cmlME8ReoUDi2pODB3mALeu7FU0prnFP4GgOnUx67wU5rN0vS7LyL +i/fHeTb23klpugmRQe8OjpjAgXb+FaCSjGQPg/YG/1FTpXsY9LjZwOUH6ckzDzGj +qwcV8CS55Jn8u5yM4uzg+Aqn8SvKCCqGtMbkcz29H+xUI5HCU/Eya97NWvuECcC0 +haDqgNsuzsM5rvOTtNJSzvQqEA/RNvIWx6yfk+B80EgzkxvSWkIIz+4m/qbHCzy6 +g5TR5ZmWOCm6qIj9pp92n06VkkHxi/klxuygoOQIs3tnXyJUQwZZWXR4SQlpoAzK +IOtYZhduvi6fFBDrGld6zuCcGWa518U4ZeMSnNihNBuHaqjlJZbWFNNdx2lw54Dl +GMmNbOExk9bm3hbbTGRsypPdNLj2tGgombiH1CqWHfbw7QCCayqCsh0rNqP2HL/U +gX44R/c3IVh2viskCz90O4UM4lON18/dN87J+zjkdA0KquEveMUzIJwfMwx7PYSU +uUEEnc0vmY7N8XFY/nnhFsscQNZLmdHXRn16kvfYVaylww+4IXKGt24/oil2v8Bb +edcouQWESr0X4qKeeiFevP1n63uqdD9OeRFRjm/aRTdAQjZlMWemP/j/chaI9xp/ +1I2fXm42GAOtTsTOTq7uklw+Uc//L15/rNCHpiG+Qhuk6tQDF9kXT758mAL+4DhB +cVWtg+aS89NLQr3cmKY17j93YXb5/r18fxfihAkf2dhGGuIGvBzSMalTWZchxLsD +2OqkTYaOnOeJ+OYQknuVkGn6EUIrMlHxBSp0fA4kcA5MbRnPQ0LNcHF2SbmVMR+A +bmYHxhSbcPokIfesh5cWKOorLT6BrMvNwpbjt1Gc3qS5s13ThvpVqYjX9Q2YA75T +vW4/1nGlJ3k+h8HFSHPFp6wwM9eDlyMj+Q7YwZ40nGzoZNIPLOnNnb85AKOpvreM +N4BZa6LZtjNv5FUZdOUQYkcnCGJwvDBwWwcCLWiFlRXcfYK19NNl0OBzuw1qQWdw +5CCjDbkL6xB0sLcR2GaA9EQnHvCKVni7x59HmaCUU13yvuthHm5JgLOkTaaK+mrh +VPwPTmdFs9Fsuwghd1uz1R1UZ+KMnhe/JDMb3jj/bUo2xfQ6VUivAqrSFkwzmFMM +w7OM5v0rLli0bUpc9yg9yU42O6Y/S6n5VpCum0NHTI2QKcwqBQOiFjTdR7cTadgZ +5XUPzYPssu1+0J47Y/gJuehRFnwyFCwzBowSh0+0v70mMSwhcac3F6ZSlooK9ynW +Q3qKaA51MGUK6IY3ZrzyUGJ4J2fIXEi9V33nUNMCsaFS8VOenEgVlkT5RVhDc+X9 +Zw4ckc4jbSwgp004K7qc5sedO+iU0kPaya0VJkUCx0bvqRx24FEUOvKaZ0esxHAr +7CGqcaOi7wRPMl4PFfd2Vr0NcQATl8mzRTJqubE7Tv36KMJ0bU8Q31guepbT7U/z +pMkQdnlumVcjGpjhaxHRszDy8ueb/n/JGNXeoGA2kTVhfYMpBV26xcbyvU6/dW7B +8IGQlqCL01ArKfxh/TIfeGIr8LR1rGEurIZlgEz2lkI+uMQ7agokILCScZxtSm7j +NpmtVWVlK8GLxA+95TNJeBKviB75VNO4ets9am9Tx++l+XmaPqyqAyYv64R6Baba +32AsBqAW7sgLtnrQ1n7uuwceVanzcANH1nxXQN3iWNawetG80t/eUcGK02Ct5Qpv +BruLiAnE/CzUq6hh7Wd8FUdrvzVN4S5xUq5RIBUb4udsqI8VBggEs12/E01IAzQG +egSPHsy91Yvnl7ysqD0DAMcNhaqFFOfUMpnNxTqv8gHMFaWZgp+zl3CjsLcoJzLw +bd7sdUDgJalhnJI7ODiKoVhz1tiRhqQH9FtfvDWKhA3fLFrvxNOsepMPX9KADVJl +2ex4oh1qKRY/ZktFIFL1BdvJo8++u8zlrWtZkyx/p0f7mYwthz62JgVRld0qwjQq +1wIrmqbkbkyroJuvePx5VcWlNtqp1Mt58iMlYoBmIS1UAh89idOoONI4oeFAmA1o +Jpz2WYXb6e9uhico6wNJSuBC4QRzdsajhtahiD2NiGzyq0FEMTqEVzakvIF/YXfL +AXUi32XBhWkAd+y0yBMjCBg5FjZzSWYYXWqGdhtcUDXXhI6JeYZwTRgbt0/2g+27 +OQL4A1farvCM59fSJ89ipmNQFcVduiPxnOKsApAYLWiIRB9tmZfYOgf+gTdklEhQ +0N3De4fDjkALEnKnVl6m/aLCcDSDgpFDeQzGLo8W0Sspy2a8O+QgzPjhDoBzkTN9 +SFx+or8NIhUpprJnbefZct3xgim/WLknuJuq9B/QTXR7RFwC7Lz5CQP1zpGWKsdH +NRehD2/iZW/9ij8kM+sZLVI4lOh1DqnR9NV/keq3829T6lgyCPutFbgwwj5IwzlP ++grhFsmTjefX1c2WvyM9Cpb+TFmHHFe3rcGM+difMfH08qS2DSFEaMzp0jMsvPyR ++gsqX3AWEFIVNcgQGj2QF4ityW3kqU7m0odjGqA7+KagvQY6Ky1e1cG0D60SSfZq +xxBgf39gxd/PGGryVikqmwDq9RcjAvy5Av2xLytXB85AF4KXV1yq3LUMSCJhlpVY +SWGQtyfEvff1j29E3vhHeFyueMcivfjQVdX3Ti/3vY700kmRL8DLQ80qQoXLRKBg +VUkdC/eOy9iWO6TS7ZLfd+ko2ngF6LIF7/95npGcwnx0+EPz9Mc9UJm/gaehyjXi +l6KWkN6SsHPEzyN7qNsx0sXYJKemRuXNzY3/4NeLrwqPtGdbn2kSC5x4a6Zzb/3p +SQk/hLSjRUX64bTVd+lF1SQOvjkMyjgrI77D+2e0ArmV9UmpCGPg4Cj2vZdzEamm +ofJyUEbxqLpPSlH/hcrwxsMrf2/7JjgTl6EqKznSzxmfoT3N/Ws0arMQjpwUKRjZ +jc4Yvs1fcUPpp7bvyKQlTJCXTzSYQYGlJoHH9s/UWMpXhHYoVH7s8GsAB2dJuoqW +YTGD+j5cxc8dUn0pqrPOH2Fui601P+W1Ed3IR/NwQm88kCK763xt01dajqqPwF2r +2P6J0dfUy9LmtiCeAEGC6eGggspWGMC8HJdQ4JwYYCvMVslHDu4itwvOOFmxQ3LR +HKVku8KWdm5osVBxCSBHmq8dPp7a0a+zxStmE62abh49Wxk0s3yNNueE0F6aPr9A +y69Zn1sYdxZQYEre3zSfkUBeuPONocb/83tLdVWpGEHhb64FohCZot9DGRjFGVZj +kmY22hVUwBJajgKiV+jxhEXsyoGf3NPEDHkLiAVTYgWj65nVREUSTfuWW+5xCOsg +WPxhLA3E4+uHm31ov2DTScC4O//WPdrfHcS8VOhyoBmnhOXcsDgcQvP41p0EutRr +75hoiKr9GsBRmASKLKQZ/koubLv//3ZpHRAqHONXuOq9oDa8hzhKImfAKuPL9a4C +Rr29Y89ZnDxsxv6m5sR+fZtu/TelBxLoq2hu5FKTMm6ehy95+QnrXaFf8SZayS30 +LdH1plTYQc1LCVDBKScAIoGHfdW224Rld5p0gH1idrKv4wCV4yKPBCxKk7MIIEk9 +7/zchWdCXBJnLKLxpwk7sug81oEIAhhvZg9rdsn5VoWzdnm9EB66wO5KQqqh18Kq +3KTN9nWK50dvGUBC9kSiUO1VEfeWnEwR4fmIbI2UT3lJRVGiX/nxN0/abl2HFnax +FNAKiJj7pmU2bQq21Izxd9wUXo8g7ZyZ2mhIT4R//F4RoQiFBpTiwi0LZgftLgA1 +vmzZZ92reMjkaDtTuniLIce0wXlssAhIZ/iPnfyFDfW6GENXOvuX7pRZauBPQQah +g0ebUesF3UtiRMO59ZSI3DbQiBcqRDznErWRSEci/3ge+qNAJxZlgfggiZ580wN5 +o6p8hBJVxzbtLRcktBGM2p1vXwCj125dPg3cPl2WYNplCTEgIv6gacQLeW3HVW5h +LEpJ18jMx7yyJmeaPV/H47V+JIoj+rx6zP0/5B7YF/+mnesVi4sK22JAmRc5T0SO +zsjkQrMFGM9qR7jO8VYkR4xWelpgP+BI5XXtbq8IVJim4TpYoMVtatzJIOIYy2tn +DwaaaMVX48mj/dubrwbPuXNNCW6uGPn4nyv/bKDZPnSs1gkXMEptb4XrS6LRN7lh +n3Lmu/QD4BlU1UQDlL+Ru4kP5QWyFqgTvfKU6NdNyVDmHSFH/iCNWza6ujq7Rj1i +22yrafFNvltycSu4EbeTzC6u5HEptBjmSNIAjPxE/s/YxC0CgFKw4tpJSEpSXbTq +uby6nh1mmktmDCmWRfY492QqUoZm4PPMQFoJwigrylMSqXwVoVVF7deguH0vh059 ++z/hE1tvZuM4Q6l92FDdVo/BlIuYuqIcMBPOBGZZVOJNh4yeoQZMToXdohIu+H3o +rhNO4WCmL0XGkE766UFoQ3iVn2NoOoFh2B/PeBOt8i1usbubq1Bh5nPtMnEgXXIb +cnNVwVhA8IME/Tm08z6rx0aUCKALTas4uNggLRXvqDzDCwLIKjWz57CB7u0PFEYz +IjX4qwqKLzLOhrdbO4kjRITG8ubJ5CiQADHwltMmAKVUm9snR1cGvMm1rS8i9/E6 +1bMJsXMK2ZzNKSB2v/jTVAyrhgBEmPKJAzaQHx1Gyi1hl8hwU+XUBVS1L+DfwzCc +XX9ZRl8rgp5KzwmSNA1V+Bjl9svoEK0RZoM2sZovDoXWOtZWrq3f36E40JUzhkc+ +Y/9L851fPDqjHFTLNb5BnrHxzp9zujxd42kmu4iLszIcVfacqsO6NmW3SChGAWcg +dDbfSwi0obvQOjiMq9Jr3Gtf/+KNzNZm4JVBEeW0KZsvYMkTbr/qFuAEPo3u15PP +RXkD0FBW5WscXwm65H0zxme3MW3tzVdIJpYssfBJNVqpyJpKciPPyBwQrDrP8O8n +hlOXdepnSo6JVN4ZzflYK5UIX4zD5X+dVDva6NWJisvn2CEgPYJFe79Phi1tNopE +E4SLlSOmCIJ2J1vkO3oBkswAJwALPalgpZJkS/aWjsG6g9kvSeTLB70YCfkdoYEi +aICjJt8eKaGl15PG7YiVlnRGLB1tn2GJCLOoHwVmDlMXqWDUGQLK5wkqmKkfPhOY +WRtJp0QGKXO6r4tp8fVlNkoIgX7KA+rWAgGXkrQn+IDYAnvKnaed6rJfEnLXgGCD +01C9d74CY7mAd3Kg3YY858coKwiDhDwiT1IUCz0ceuY= +`pragma protect end_protected + +//pragma protect end + +`undef IP_MODULE_NAME diff --git a/fpga/source/design_modules.v b/fpga/source/design_modules.v new file mode 100644 index 0000000..d99ad61 --- /dev/null +++ b/fpga/source/design_modules.v @@ -0,0 +1,1494 @@ +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// / / \ +// / / .. / design_modules.v +// / / .' / +// __/ /.' / Description: +// __ \ / Modules for SapphireSoC example design +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// *********************************************************************** +// Revisions: +// 1.0 Initial rev +// 1.1 Added Custom ALU +// 1.2 Fixed AXI4 slave read first issue +// 1.3 Added axi full-duplex to half-duplex converter +// *********************************************************************** +`timescale 1ns/1ps + +module apb3_slave #( + // user parameter starts here + // + parameter ADDR_WIDTH = 16, + parameter DATA_WIDTH = 32, + parameter NUM_REG = 4 +) ( + // user logic starts here + input clk, + input resetn, + input [ADDR_WIDTH-1:0] PADDR, + input PSEL, + input PENABLE, + output PREADY, + input PWRITE, + input [DATA_WIDTH-1:0] PWDATA, + output [DATA_WIDTH-1:0] PRDATA, + output PSLVERROR + +); + + +/////////////////////////////////////////////////////////////////////////////// + +localparam [1:0] IDLE = 2'b00, + SETUP = 2'b01, + ACCESS = 2'b10; + +integer byteIndex; +reg [DATA_WIDTH-1:0] slaveReg [0:NUM_REG-1]; +reg [DATA_WIDTH-1:0] slaveRegOut; +reg [1:0] busState, + busNext; +reg slaveReady; +wire actWrite, + actRead; +reg [31:0] lfsr; +wire lfsr_stop; + + +/////////////////////////////////////////////////////////////////////////////// + + always@(posedge clk or negedge resetn) + begin + if(!resetn) + busState <= IDLE; + else + busState <= busNext; + end + + always@(*) + begin + busNext = busState; + + case(busState) + IDLE: + begin + if(PSEL && !PENABLE) + busNext = SETUP; + else + busNext = IDLE; + end + SETUP: + begin + if(PSEL && PENABLE) + busNext = ACCESS; + else + busNext = IDLE; + end + ACCESS: + begin + if(PREADY) + busNext = IDLE; + else + busNext = ACCESS; + end + default: + begin + busNext = IDLE; + end + endcase + end + + + assign actWrite = PWRITE & (busState == ACCESS); + assign actRead = !PWRITE & (busState == ACCESS); + assign PSLVERROR = 1'b0; + assign PRDATA = slaveRegOut; + assign PREADY = slaveReady & & (busState !== IDLE); + + always@ (posedge clk) + begin + slaveReady <= actWrite | actRead; + end + + always@ (posedge clk or negedge resetn) + begin + if(!resetn) + for(byteIndex = 0; byteIndex < NUM_REG; byteIndex = byteIndex + 1) + slaveReg[byteIndex] <= {DATA_WIDTH{1'b0}}; + else + begin + if(actWrite) + begin + for(byteIndex = 0; byteIndex < NUM_REG; byteIndex = byteIndex + 1) + if (PADDR[3:0] == (byteIndex*4)) + slaveReg[byteIndex] <= PWDATA; + end + else + begin + slaveReg[0] <= lfsr; + for(byteIndex = 1; byteIndex < NUM_REG; byteIndex = byteIndex + 1) + slaveReg[byteIndex] <= slaveReg[byteIndex]; + end + end + end + + always@ (posedge clk or negedge resetn) + begin + if(!resetn) + slaveRegOut <= {DATA_WIDTH{1'b0}}; + else begin + if(actRead) + slaveRegOut <= slaveReg[PADDR[7:2]]; + else + slaveRegOut <= slaveRegOut; + + end + + end + + assign lfsr_stop = slaveReg[1][0]; +//custom logics + + always@(posedge clk or negedge resetn) + begin + if (!resetn) + lfsr <= 'd1; + else + begin + if(!lfsr_stop) + begin + lfsr[31] <= lfsr[0]; + lfsr[30] <= lfsr[31]; + lfsr[29] <= lfsr[30]; + lfsr[28] <= lfsr[29]; + lfsr[27] <= lfsr[28]; + lfsr[26] <= lfsr[27]; + lfsr[25] <= lfsr[26]; + lfsr[24] <= lfsr[25]; + lfsr[23] <= lfsr[24]; + lfsr[22] <= lfsr[23]; + lfsr[21] <= lfsr[22]; + lfsr[20] <= lfsr[21]; + lfsr[19] <= lfsr[20]; + lfsr[18] <= lfsr[19]; + lfsr[17] <= lfsr[18]; + lfsr[16] <= lfsr[17]; + lfsr[15] <= lfsr[16]; + lfsr[14] <= lfsr[15]; + lfsr[13] <= lfsr[14]; + lfsr[12] <= lfsr[13]; + lfsr[11] <= lfsr[12]; + lfsr[10] <= lfsr[11]; + lfsr[9 ] <= lfsr[10]; + lfsr[8 ] <= lfsr[9 ]; + lfsr[7 ] <= lfsr[8 ]; + lfsr[6 ] <= lfsr[7 ]; + lfsr[5 ] <= lfsr[6 ]; + lfsr[4 ] <= lfsr[5 ]; + lfsr[3 ] <= lfsr[4 ] ^ lfsr[0]; + lfsr[2 ] <= lfsr[3 ]; + lfsr[1 ] <= lfsr[2 ]; + lfsr[0 ] <= lfsr[1 ] ^ lfsr[0]; + end + else + begin + lfsr <= lfsr; + end + end + end + +endmodule + +// *********************************************************************** + +module axi4_slave #( + parameter ADDR_WIDTH = 32, + parameter DATA_WIDTH = 32 +) ( + //custom logic starts here + output axi_interrupt, + // + input axi_aclk, + input axi_resetn, + //AW + input [7:0] axi_awid, + input [ADDR_WIDTH-1:0] axi_awaddr, + input [7:0] axi_awlen, + input [2:0] axi_awsize, + input [1:0] axi_awburst, + input axi_awlock, + input [3:0] axi_awcache, + input [2:0] axi_awprot, + input [3:0] axi_awqos, + input [3:0] axi_awregion, + input axi_awvalid, + output axi_awready, + //W + input [DATA_WIDTH-1:0] axi_wdata, + input [(DATA_WIDTH/8)-1:0] + axi_wstrb, + input axi_wlast, + input axi_wvalid, + output axi_wready, + //B + output [7:0] axi_bid, + output [1:0] axi_bresp, + output axi_bvalid, + input axi_bready, + //AR + input [7:0] axi_arid, + input [ADDR_WIDTH-1:0] axi_araddr, + input [7:0] axi_arlen, + input [2:0] axi_arsize, + input [1:0] axi_arburst, + input axi_arlock, + input [3:0] axi_arcache, + input [2:0] axi_arprot, + input [3:0] axi_arqos, + input [3:0] axi_arregion, + input axi_arvalid, + output axi_arready, + //R + output [7:0] axi_rid, + output [DATA_WIDTH-1:0] axi_rdata, + output [1:0] axi_rresp, + output axi_rlast, + output axi_rvalid, + input axi_rready +); + +/////////////////////////////////////////////////////////////////////////////// +localparam RAM_SIZE = 2048; +localparam RAMW = $clog2(RAM_SIZE); + +localparam [2:0] IDLE = 3'h0, + PRE_WR = 3'h1, + WR = 3'h2, + WR_RESP = 3'h3, + PRE_RD = 3'h4, + RD = 3'h5; + +reg [2:0] busState, + busNext; +wire busReady, + busPreWrite, + busWrite, + busWriteResp, + busPreRead, + busRead; +wire awWrap, + arWrap; +reg [7:0] awidReg; +reg [ADDR_WIDTH-1:0] awaddrReg; +reg [7:0] awlenReg; +reg [2:0] awsizeReg; +reg [1:0] awburstReg, + awlockReg; +reg [3:0] awcacheReg; +reg [2:0] awprotReg; +reg [3:0] awqosReg; +reg [3:0] awregionReg; + +reg [7:0] aridReg; +reg [ADDR_WIDTH-1:0] araddrReg; +reg [7:0] arlenReg; +reg [2:0] arsizeReg; +reg [1:0] arburstReg, + arlockReg; +reg [3:0] arcacheReg; +reg [2:0] arprotReg; +reg [3:0] arqosReg; +reg [3:0] arregionReg; + +reg [31:0] awaddr_base; +wire [31:0] awWrapSize; +reg [7:0] decodeAwsize; + +wire [31:0] araddr_wrap; +reg [7:0] decodeArsize; + +reg [31:0] araddr_base; +wire [31:0] arWrapSize; +reg [7:0] ridReg; +reg [1:0] rrespReg; +reg [1:0] rlastReg; + +wire pWr_done; +wire pRd_done; +wire awaddr_ext; +wire araddr_ext; +wire [(DATA_WIDTH/8)-1:0] + rlast; +wire [(DATA_WIDTH/8)-1:0] + rvalid; +//custom logic +wire [9:0] wdata [0:3]; +wire wEnable[0:3]; +wire [9:0] rdata [0:3]; +wire [31:0] data_o; +wire rEnable; +reg r_axi_interrupt; + +/////////////////////////////////////////////////////////////////////////////// + + + always@ (posedge axi_aclk or negedge axi_resetn) + begin + if(!axi_resetn) + busState <= IDLE; + else + busState <= busNext; + + end + + always@ (*) + begin + busNext = busState; + + case(busState) + IDLE: + begin + if(axi_awvalid) + busNext = PRE_WR; + else if(axi_arvalid) + busNext = PRE_RD; + else + busNext = IDLE; + end + PRE_WR: + begin + if(pWr_done) + busNext = WR; + else + busNext = PRE_WR; + end + WR: + begin + if(axi_wlast) + busNext = WR_RESP; + else + busNext = WR; + end + WR_RESP: + begin + if(axi_bready) + busNext = IDLE; + else + busNext = WR_RESP; + end + PRE_RD: + begin + if(pRd_done) + busNext = RD; + else + busNext = PRE_RD; + end + RD: + begin + if(axi_rlast && axi_rready) + busNext = IDLE; + else + busNext = RD; + end + default: + busNext = IDLE; + endcase + end + + assign busReady = (busState == IDLE); + assign busPreWrite = (busState == PRE_WR); + assign busWrite = (busState == WR); + assign busWriteResp = (busState == WR_RESP); + assign busPreRead = (busState == PRE_RD); + assign busRead = (busState == RD); + + //PRE_WRITE + assign pWr_done = (awburstReg == 2'b10)? awaddr_ext : 1'b1; + //AW Control + + assign axi_awready = busReady; + + //Wrap Control + always@ (posedge axi_aclk or negedge axi_resetn) + begin + if (!axi_resetn) + awaddr_base <= 'h0; + else begin + if(busReady) + awaddr_base <= 'h0; + else if(busPreWrite && !awaddr_ext) + awaddr_base <= awaddr_base + awWrapSize; + else + awaddr_base <= awaddr_base; + end + end + + assign awaddr_ext = busPreWrite ? (awaddr_base[RAMW:0] > awaddrReg[RAMW:0]) : 1'b0; + assign awWrap = busWrite && (axi_awburst == 2'b10) ? (awaddrReg[RAMW:0] == awaddr_base - 4) : 1'b0; + assign awWrapSize = (DATA_WIDTH/8) * awlenReg; + + //AW Info + always@ (posedge axi_aclk) + begin + if(axi_awvalid) begin + awidReg <= axi_awid; + awlenReg <= axi_awlen + 1'b1; + awsizeReg <= axi_awsize; + awburstReg <= axi_awburst; + awlockReg <= axi_awlock; + awcacheReg <= axi_awcache; + awprotReg <= axi_awprot; + awqosReg <= axi_awqos; + awregionReg <= axi_awregion; + end + else begin + awidReg <= awidReg; + awlenReg <= awlenReg; + awsizeReg <= awsizeReg; + awburstReg <= awburstReg; + awlockReg <= awlockReg; + awcacheReg <= awcacheReg; + awprotReg <= awprotReg; + awqosReg <= awqosReg; + awregionReg <= awregionReg; + end + end + + always@ (awsizeReg) + begin + case(awsizeReg) + 3'h0:decodeAwsize <= 8'd1; + 3'h1:decodeAwsize <= 8'd2; + 3'h2:decodeAwsize <= 8'd4; + 3'h3:decodeAwsize <= 8'd8; + 3'h4:decodeAwsize <= 8'd16; + 3'h5:decodeAwsize <= 8'd32; + 3'h6:decodeAwsize <= 8'd64; + 3'h7:decodeAwsize <= 8'd128; + default:decodeAwsize <= 8'd1; + endcase + end + + always@ (posedge axi_aclk) + begin + if(axi_awvalid) + awaddrReg <= axi_awaddr; + else if (busWrite) begin + case(awburstReg) + 2'b00://fixed burst + awaddrReg <= awaddrReg; + 2'b01://incremental burst + awaddrReg <= awaddrReg + decodeAwsize; + 2'b10://wrap burst + begin + if(awWrap) + awaddrReg <= awaddrReg - awWrapSize; + else + awaddrReg <= awaddrReg + decodeAwsize; + end + default: + awaddrReg <= awaddrReg; + endcase + end + end + //W operation + assign axi_wready = busWrite; + + //B Response + assign axi_bid = awidReg; + assign axi_bresp = 2'b00; + assign axi_bvalid = busWriteResp; + + //PRE_READ + assign pRd_done = (arburstReg == 2'b10)? araddr_ext : 1'b1; + + //AR Control + assign axi_arready = busReady; + + //Wrap Control + always@ (posedge axi_aclk or negedge axi_resetn) + begin + if (!axi_resetn) + araddr_base <= 'h0; + else begin + if(busReady) + araddr_base <= 'h0; + else if(busPreRead && !araddr_ext) + araddr_base <= araddr_base + arWrapSize; + else + araddr_base <= araddr_base; + end + end + + assign araddr_ext = busPreRead ? (araddr_base[RAMW:0] > araddrReg[RAMW:0]) : 1'b0; + assign arWrap = (busRead && axi_arburst == 2'b10) ? (araddrReg[RAMW:0] == araddr_base - 4) : 1'b0; + assign arWrapSize = (DATA_WIDTH/8) * arlenReg; + + //AR Info + always@ (posedge axi_aclk) + begin + if(axi_arvalid) begin + aridReg <= axi_arid; + arlenReg <= axi_arlen + 1'b1; + arsizeReg <= axi_arsize; + arburstReg <= axi_arburst; + arlockReg <= axi_arlock; + arcacheReg <= axi_arcache; + arprotReg <= axi_arprot; + arqosReg <= axi_arqos; + arregionReg <= axi_arregion; + end + else begin + aridReg <= aridReg; + arlenReg <= arlenReg; + arsizeReg <= arsizeReg; + arburstReg <= arburstReg; + arlockReg <= arlockReg; + arcacheReg <= arcacheReg; + arprotReg <= arprotReg; + arqosReg <= arqosReg; + arregionReg <= arregionReg; + end + end + + always@ (arsizeReg) + begin + case(arsizeReg) + 3'h0:decodeArsize <= 8'd1; + 3'h1:decodeArsize <= 8'd2; + 3'h2:decodeArsize <= 8'd4; + 3'h3:decodeArsize <= 8'd8; + 3'h4:decodeArsize <= 8'd16; + 3'h5:decodeArsize <= 8'd32; + 3'h6:decodeArsize <= 8'd64; + 3'h7:decodeArsize <= 8'd128; + default:decodeArsize <= 8'd1; + endcase + end + + always@ (posedge axi_aclk) + begin + if(axi_arvalid) + araddrReg <= axi_araddr; + else if (rEnable && axi_rready) begin + case(arburstReg) + 2'b00://fixed burst + araddrReg <= araddrReg; + 2'b01://incremental burst + araddrReg <= araddrReg + decodeArsize; + 2'b10://wrap burst + begin + if(arWrap) + araddrReg <= araddrReg - arWrapSize; + else + araddrReg <= araddrReg + decodeArsize; + end + default: + araddrReg <= araddrReg; + endcase + end + end + + // R Operation + assign axi_rdata = data_o; + + // R Response + assign axi_rvalid = busRead? |rvalid : 1'b0 ; + assign axi_rlast = busRead? |rlast : 1'b0 ; + + assign axi_rresp = 2'b00; + assign axi_rid = aridReg; + + //custom logic starts here + assign axi_interrupt = r_axi_interrupt; + assign rEnable = (axi_arburst == 2'b10)? busRead : busPreRead; + + always@ (posedge axi_aclk) + begin + if (!axi_resetn) + begin + r_axi_interrupt <= 1'b0; + end + else + begin + if((axi_wvalid) && (axi_wdata == 16'hABCD)) + r_axi_interrupt <= 1'b1; + else + r_axi_interrupt <= 1'b0; + end + end + + genvar i; + generate + for(i=0;i < (DATA_WIDTH/8); i = i + 1) begin + + assign rvalid[i] = (arlenReg != 'h1)? rdata[i][8] : 1'b1; + assign rlast[i] = (arlenReg != 'h1)? rdata[i][9] : 1'b1; + assign wdata[i] = {axi_wlast, axi_wvalid, axi_wdata[(i*8+7) -: 8]} ; + assign data_o[(i*8+7) -: 8] = rdata[i]; + assign wEnable[i] = axi_wready & axi_wvalid & axi_wstrb[i]; + + ext_mem #( + .DATA_WIDTH (10), + .ADDR_WIDTH (RAMW-2), + .OUTPUT_REG ("TRUE") + + ) user_ram ( + .wdata (wdata[i]), + .waddr (awaddrReg[RAMW-1:2]), + .raddr (araddrReg[RAMW-1:2]), + .we (wEnable[i]), + .wclk (axi_aclk), + .re (rEnable), + .rclk (axi_aclk), + .rdata (rdata[i]) + ); + end + endgenerate + +endmodule + +// *********************************************************************** + +module memory_checker #( + parameter WIDTH = 32, + parameter ALEN = 23, + parameter START_ADDR = 32'h00000000, + parameter STOP_ADDR = 32'h00100000, + parameter ADDR_OFFSET = (ALEN + 1)*(WIDTH/8) +) ( +input axi_clk, +input rstn, +input start, +output [7:0] aid, +output reg [31:0] aaddr, +output reg [7:0] alen, +output reg [2:0] asize, +output reg [1:0] aburst, +output reg [1:0] alock, +output reg avalid, +input aready, +output reg atype, + +output [7:0] wid, +output reg [WIDTH-1:0] wdata, +output [WIDTH/8-1:0] wstrb, +output reg wlast, +output reg wvalid, +input wready, + +input [3:0] rid, +input [WIDTH-1:0] rdata, +input rlast, +input rvalid, +output reg rready, +input [1:0] rresp, + +input [7:0] bid, +input bvalid, +output reg bready, +output pass + +); + +/////////////////////////////////////////////////////////////////////////////// +localparam ASIZE = (WIDTH == 512)? 6 : + (WIDTH == 256)? 5 : + (WIDTH == 128)? 4 : + (WIDTH == 64)? 3 : 2; + +//Main states +localparam COMPARE_WIDTH = WIDTH; +localparam IDLE = 4'b0000, + WRITE_ADDR = 4'b0001, + PRE_WRITE = 4'b0010, + WRITE = 4'b0011, + POST_WRITE = 4'b0100, + READ_ADDR = 4'b0101, + PRE_READ = 4'b0110, + READ_COMPARE = 4'b0111, + POST_READ = 4'b1000, + DONE = 4'b1001; + +//reg [3:0] states, nstates; +reg fail; +reg done; +reg [3:0] states; +reg [3:0] nstates; +reg bvalid_done; +reg [1:0] start_sync; +reg [8:0] write_cnt, read_cnt; +reg [WIDTH-1:0] rdata_store; +reg wburst_done, + rburst_done, + write_done, + read_done; + +/////////////////////////////////////////////////////////////////////////////// + assign aid = 8'h00; + assign wstrb = {WIDTH/8{1'b1}}; + assign wid = 8'h00; + assign pass = done & ~fail; + + always @(posedge axi_clk or negedge rstn) + begin + if (!rstn) begin + start_sync <= 2'b00; + end else begin + start_sync[0] <= start; + start_sync[1] <= start_sync[0]; + end + end + + always @(posedge axi_clk or negedge rstn) + begin + if (!rstn) begin + states <= IDLE; + end else begin + states <= nstates; + end + end + + always @(states or start_sync[1] or write_cnt or rburst_done or write_done or read_done or bvalid_done or aready) + begin + case(states) + IDLE : + if (start_sync[1]) + nstates = WRITE_ADDR; + else + nstates = IDLE; + WRITE_ADDR : + if (aready) + nstates = PRE_WRITE; + else + nstates = WRITE_ADDR; + PRE_WRITE : + nstates = WRITE; + WRITE : + if (write_cnt == 9'd0) + nstates = POST_WRITE; + else + nstates = WRITE; + POST_WRITE : + if (write_done & bvalid_done) + nstates = READ_ADDR; + else if (bvalid_done) + nstates = WRITE_ADDR; + else + nstates = POST_WRITE; + READ_ADDR : + if (aready) + nstates = PRE_READ; + else + nstates = READ_ADDR; + PRE_READ : + nstates = READ_COMPARE; + READ_COMPARE : + if (rburst_done) + nstates = POST_READ; + else + nstates = READ_COMPARE; + POST_READ : + if (read_done) + nstates = DONE; + else + nstates = READ_ADDR; + DONE : + nstates = DONE; + default : + nstates = IDLE; + endcase + end + + always @(posedge axi_clk or negedge rstn) + begin + if (!rstn) begin + aaddr <= START_ADDR; + avalid <= 1'b0; + atype <= 1'b0; + aburst <= 2'b00; + asize <= 3'b000; + alen <= 8'd0; + alock <= 2'b00; + wvalid <= 1'b0; + write_cnt <= ALEN + 1; + write_done <= 1'b0; + wdata <= {WIDTH{1'b0}}; + wburst_done <= 1'b0; + wlast <= 1'b0; + bready <= 1'b0; + fail <= 1'b0; + done <= 1'b0; + rready <= 1'b0; + bvalid_done <=1'b0; + end + else + begin + if (states == IDLE) + begin + aaddr <= START_ADDR; + avalid <= 1'b0; + atype <= 1'b0; + aburst <= 2'b00; + asize <= 3'b000; + alen <= 8'd0; + alock <= 2'b00; + wvalid <= 1'b0; + write_cnt <= ALEN + 1; + wdata <= {WIDTH{1'b0}}; + wburst_done <= 1'b0; + wlast <= 1'b0; + bready <= 1'b0; + rready <= 1'b0; + bvalid_done <= 1'b0; + fail <= 1'b0; + done <= 1'b0; + end + if (states == WRITE_ADDR) + begin + avalid <= 1'b1; + atype <= 1'b1; + asize <= ASIZE; + alen <= ALEN; + aburst <= 2'b01; + alock <= 2'b00; + wvalid <= 1'b0; + write_cnt <= ALEN + 1; + wburst_done <= 1'b0; + bvalid_done <= 1'b0; + bready <= 1'b0; + rready <= 1'b0; + done <= 1'b0; + fail <= 1'b0; + end + if (states == PRE_WRITE) + begin + avalid <= 1'b0; + atype <= 1'b0; + wvalid <= 1'b1; + wdata <= {{WIDTH/32{~aaddr[7:0]}},{WIDTH/32{~write_cnt[7:0]}},{WIDTH/32{aaddr[7:0]}},{WIDTH/32{write_cnt[7:0]}}}; + bready <= 1'b1; + write_cnt <= write_cnt - 1; + if(alen == 'd0) + begin + wlast <= 1'b1; + end + end + if (states == WRITE) + begin + if (wready == 1'b1) + begin + wdata <= {{WIDTH/32{~aaddr[7:0]}},{WIDTH/32{~write_cnt[7:0]}},{WIDTH/32{aaddr[7:0]}},{WIDTH/32{write_cnt[7:0]}}}; + if (write_cnt == 9'd0) + begin + wburst_done <= 1'b1; + wlast <= 1'b0; + wvalid <= 1'b0; + if (aaddr >= STOP_ADDR) + begin + write_done <= 1'b1; + end else + begin + write_done <= 1'b0; + end + end if (write_cnt == 9'd1) + begin + wlast <= 1'b1; + write_cnt <= write_cnt - 1; + end + else + begin + write_cnt <= write_cnt - 1; + end + end + end + if (states == POST_WRITE) + begin + if (write_done) + begin + aaddr <= START_ADDR; + end + else + begin + if (bvalid) begin + aaddr <= aaddr + ADDR_OFFSET; + end + end + if (wready == 1'b1) + begin + wlast <= 1'b0; + wvalid <= 1'b0; + end + if (bvalid) + begin + bvalid_done <= 1'b1; + bready <= 1'b0; + end + end + if (states == READ_ADDR) + begin + avalid <= 1'b1; + read_cnt <= ALEN + 1; + + end + if (states == PRE_READ) + begin + avalid <= 1'b0; + rburst_done <= 1'b0; + rdata_store <= {{WIDTH/32{~aaddr[7:0]}},{WIDTH/32{~read_cnt[7:0]}},{WIDTH/32{aaddr[7:0]}},{WIDTH/32{read_cnt[7:0]}}}; + read_cnt <= read_cnt - 1'b1; + end + if (states == READ_COMPARE) + begin + rready <= 1'b1; + if (read_cnt != 9'd0) + begin + if (rvalid == 1'b1) + begin + rdata_store <= {{WIDTH/32{~aaddr[7:0]}},{WIDTH/32{~read_cnt[7:0]}},{WIDTH/32{aaddr[7:0]}},{WIDTH/32{read_cnt[7:0]}}}; + read_cnt <= read_cnt - 1'b1; + if (rdata[COMPARE_WIDTH-1:0] != rdata_store[COMPARE_WIDTH-1:0]) + fail <= 1'b1; + else + fail <= 1'b0; + end + + end + end + if (read_cnt == 9'd0) + begin + if (rvalid == 1'b1) + begin + if (rdata[COMPARE_WIDTH-1:0] != rdata_store[COMPARE_WIDTH-1:0]) + begin + fail <= 1'b1; + end + else + begin + fail <= 1'b0; + end + if (aaddr >= STOP_ADDR) + begin + read_done <= 1'b1; + end + else + begin + read_done <= 1'b0; + end + rburst_done <= 1'b1; + end + end + if (states == POST_READ) + begin + aaddr <= aaddr + ADDR_OFFSET; + rready <= 1'b1; + end + if (states == DONE) + begin + done <= 1'b1; + end + end + end +endmodule + +// *********************************************************************** +module timer_start #( + parameter MHZ = 50, + parameter SECOND = 3, + parameter PULSE = 0 +) ( + input clk, + input rst_n, + output start +); + +reg [35:0] delay_cnt; +wire second_tick; +reg [4:0] second_cnt; +reg [3:0] pulse_reg; +wire start_reg; + +/////////////////////////////////////////////////////////////////////////////// + +`ifndef EFX_SIM +localparam tick_cnt = (MHZ * 1000000) >> 1; +`else +localparam tick_cnt = MHZ * 200; +`endif + + always@(posedge clk or negedge rst_n) + begin + if(!rst_n) + delay_cnt <= 'd0; + else + begin + if(delay_cnt == tick_cnt || start_reg == 1'b1) + delay_cnt <= 'd0; + else + delay_cnt <= delay_cnt + 1'b1; + end + end + + assign second_tick = ((delay_cnt) == (tick_cnt - 1)); + + always@(posedge clk or negedge rst_n) + begin + if(!rst_n) + second_cnt <= 'd0; + else + begin + if(second_tick) + second_cnt <= second_cnt + 1'b1; + else + second_cnt <= second_cnt; + end + end + + assign start_reg = (second_cnt == SECOND); + + always@(posedge clk) + begin + pulse_reg <= {pulse_reg[2:0],start_reg}; + end + +generate +if(PULSE == 1) + assign start = ~pulse_reg[3] & start_reg; +else + assign start = start_reg; +endgenerate + +endmodule + +// *********************************************************************** +module ext_mem #( + parameter DATA_WIDTH = 8, + parameter ADDR_WIDTH = 9, + parameter OUTPUT_REG = "TRUE", + parameter RAM_INIT_FILE = "" +) ( + input [DATA_WIDTH-1:0] wdata, + input [ADDR_WIDTH-1:0] waddr, + input [ADDR_WIDTH-1:0] raddr, + input we, + input wclk, + input re, + input rclk, + output [DATA_WIDTH-1:0] rdata +); + +///////////////////////////////////////////////////////////////////////////// + + localparam MEMORY_DEPTH = 2**ADDR_WIDTH; + localparam MAX_DATA = (1<=0.1.30 +cocotbext-eth>=0.1.24 +pytest +fpga-sim>=0.5.4 +build_fpga +git+https://github.com/arnavsacheti/PeakRDL-BusDecoder.git +peakrdl-python-regmap>=0.0.5 +taxi-peakrdl-extensions diff --git a/sim/sources.list b/sim/sources.list new file mode 100644 index 0000000..047d32a --- /dev/null +++ b/sim/sources.list @@ -0,0 +1,24 @@ +verilator.vlt +verilog6502_wrapper_tb.sv + +../src/regs/verilog6502_io_regs_pkg.sv +../src/regs/verilog6502_io_regs.sv + +../src/verilog6502_addr_decoder.sv +../src/verilog6502_internal_memory.sv +../src/verilog6502_apb_adapter.sv +../src/verilog6502_wrapper.sv + + +../sub/verilog-6502/ALU.v +../sub/verilog-6502/cpu_65c02.v + +../sub/taxi/src/apb/rtl/taxi_apb_if.sv +../sub/taxi/src/axi/rtl/taxi_axi_if.sv +../sub/taxi/src/axi/rtl/taxi_axi_ram_if_rd.sv +../sub/taxi/src/axi/rtl/taxi_axi_ram_if_wr.sv +../sub/taxi/src/axi/rtl/taxi_axi_ram_if_rdwr.sv +../sub/taxi/src/apb/rtl/taxi_apb_interconnect.sv +../sub/taxi/src/apb/rtl/taxi_apb_tie.sv +../sub/taxi/src/prim/rtl/taxi_arbiter.sv +../sub/taxi/src/prim/rtl/taxi_penc.sv \ No newline at end of file diff --git a/sim/verilator.vlt b/sim/verilator.vlt new file mode 100644 index 0000000..6ea35fc --- /dev/null +++ b/sim/verilator.vlt @@ -0,0 +1,7 @@ +`verilator_config + +lint_off -file "**/ALU.v" +lint_off -file "**/cpu_65c02.v" +lint_off -rule MULTIDRIVEN -file "**/verilog6502_io_regs.sv" +lint_off -rule UNOPTFLAT +lint_off -rule TIMESCALEMOD \ No newline at end of file diff --git a/sim/verilog6502_wrapper.yaml b/sim/verilog6502_wrapper.yaml new file mode 100644 index 0000000..549c201 --- /dev/null +++ b/sim/verilog6502_wrapper.yaml @@ -0,0 +1,9 @@ +tests: + - name: "verilog6502_wrapper" + toplevel: "verilog6502_wrapper_tb" + modules: + - "verilog6502_wrapper_test" + sources: "sources.list" + waves: True + defines: + SIM: "hi" \ No newline at end of file diff --git a/sim/verilog6502_wrapper_tb.sv b/sim/verilog6502_wrapper_tb.sv new file mode 100644 index 0000000..176a718 --- /dev/null +++ b/sim/verilog6502_wrapper_tb.sv @@ -0,0 +1,28 @@ +module verilog6502_wrapper_tb(); + +`define SIM + +taxi_apb_if s_apb(); +taxi_axi_if m_axi(); +taxi_axi_if s_axi(); + +logic clk; +logic rst; + +logic o_irq_ext; +logic i_irq_ext; + + +verilog6502_wrapper u_dut( + .clk(clk), + .rst(rst), + .s_apb(s_apb), + .m_axi_rd(m_axi), + .m_axi_wr(m_axi), + .s_axi_rd(s_axi), + .s_axi_wr(s_axi), + .o_irq_ext(o_irq_ext), + .i_irq_ext(i_irq_ext) +); + +endmodule \ No newline at end of file diff --git a/sim/verilog6502_wrapper_test.py b/sim/verilog6502_wrapper_test.py new file mode 100644 index 0000000..28c4ca0 --- /dev/null +++ b/sim/verilog6502_wrapper_test.py @@ -0,0 +1,40 @@ +import cocotb +from cocotb.handle import Immediate + +from cocotb.clock import Clock +from cocotb.triggers import Timer, RisingEdge + +from cocotbext.axi.apb import ApbMaster, ApbBus +from cocotbext.axi import AxiMaster, AxiBus + + + +CLK_PERIOD = 5 + + +@cocotb.test +async def test_sanity(dut): + print("Hello world") + cocotb.start_soon(Clock(dut.clk, CLK_PERIOD, unit="ns").start()) + + s_apb = ApbMaster(ApbBus.from_prefix(dut.s_apb, ""), dut.clk, dut.rst) + + s_axi = AxiMaster(AxiBus.from_prefix(dut.s_axi, ""), dut.clk, dut.rst) + + + dut.rst.value = Immediate(1) + for _ in range(10): + await RisingEdge(dut.clk) + dut.rst.value = 0 + for _ in range(10): + await RisingEdge(dut.clk) + + await s_axi.write(0x0, [0x4c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00]) + + cocotb.start_soon(s_axi.read(0x0, 8)) + + await Timer(10, "us") + + await s_apb.write_dword(0x0, 0) + + await Timer(10, "us") \ No newline at end of file diff --git a/src/fpga6502.sv b/src/fpga6502.sv new file mode 100644 index 0000000..996362e --- /dev/null +++ b/src/fpga6502.sv @@ -0,0 +1,387 @@ +module fpga6502 ( + output jtagCtrl_tdi, + input jtagCtrl_tdo, + output jtagCtrl_enable, + output jtagCtrl_capture, + output jtagCtrl_shift, + output jtagCtrl_update, + output jtagCtrl_reset, + input ut_jtagCtrl_tdi, + output ut_jtagCtrl_tdo, + input ut_jtagCtrl_enable, + input ut_jtagCtrl_capture, + input ut_jtagCtrl_shift, + input ut_jtagCtrl_update, + input ut_jtagCtrl_reset, + input io_cfuClk, + input io_cfuReset, + input cpu0_customInstruction_cmd_valid, + output cpu0_customInstruction_cmd_ready, + input [9:0] cpu0_customInstruction_function_id, + input [31:0] cpu0_customInstruction_inputs_0, + input [31:0] cpu0_customInstruction_inputs_1, + output cpu0_customInstruction_rsp_valid, + input cpu0_customInstruction_rsp_ready, + output [31:0] cpu0_customInstruction_outputs_0, + input cpu1_customInstruction_cmd_valid, + output cpu1_customInstruction_cmd_ready, + input [9:0] cpu1_customInstruction_function_id, + input [31:0] cpu1_customInstruction_inputs_0, + input [31:0] cpu1_customInstruction_inputs_1, + output cpu1_customInstruction_rsp_valid, + input cpu1_customInstruction_rsp_ready, + output [31:0] cpu1_customInstruction_outputs_0, + input cpu2_customInstruction_cmd_valid, + output cpu2_customInstruction_cmd_ready, + input [9:0] cpu2_customInstruction_function_id, + input [31:0] cpu2_customInstruction_inputs_0, + input [31:0] cpu2_customInstruction_inputs_1, + output cpu2_customInstruction_rsp_valid, + input cpu2_customInstruction_rsp_ready, + output [31:0] cpu2_customInstruction_outputs_0, + input cpu3_customInstruction_cmd_valid, + output cpu3_customInstruction_cmd_ready, + input [9:0] cpu3_customInstruction_function_id, + input [31:0] cpu3_customInstruction_inputs_0, + input [31:0] cpu3_customInstruction_inputs_1, + output cpu3_customInstruction_rsp_valid, + input cpu3_customInstruction_rsp_ready, + output [31:0] cpu3_customInstruction_outputs_0, + output io_ddrMasters_0_aw_valid, + input io_ddrMasters_0_aw_ready, + output [31:0] io_ddrMasters_0_aw_payload_addr, + output [3:0] io_ddrMasters_0_aw_payload_id, + output [3:0] io_ddrMasters_0_aw_payload_region, + output [7:0] io_ddrMasters_0_aw_payload_len, + output [2:0] io_ddrMasters_0_aw_payload_size, + output [1:0] io_ddrMasters_0_aw_payload_burst, + output io_ddrMasters_0_aw_payload_lock, + output [3:0] io_ddrMasters_0_aw_payload_cache, + output [3:0] io_ddrMasters_0_aw_payload_qos, + output [2:0] io_ddrMasters_0_aw_payload_prot, + output io_ddrMasters_0_aw_payload_allStrb, + output io_ddrMasters_0_w_valid, + input io_ddrMasters_0_w_ready, + output [127:0] io_ddrMasters_0_w_payload_data, + output [15:0] io_ddrMasters_0_w_payload_strb, + output io_ddrMasters_0_w_payload_last, + input io_ddrMasters_0_b_valid, + output io_ddrMasters_0_b_ready, + input [3:0] io_ddrMasters_0_b_payload_id, + input [1:0] io_ddrMasters_0_b_payload_resp, + output io_ddrMasters_0_ar_valid, + input io_ddrMasters_0_ar_ready, + output [31:0] io_ddrMasters_0_ar_payload_addr, + output [3:0] io_ddrMasters_0_ar_payload_id, + output [3:0] io_ddrMasters_0_ar_payload_region, + output [7:0] io_ddrMasters_0_ar_payload_len, + output [2:0] io_ddrMasters_0_ar_payload_size, + output [1:0] io_ddrMasters_0_ar_payload_burst, + output io_ddrMasters_0_ar_payload_lock, + output [3:0] io_ddrMasters_0_ar_payload_cache, + output [3:0] io_ddrMasters_0_ar_payload_qos, + output [2:0] io_ddrMasters_0_ar_payload_prot, + input io_ddrMasters_0_r_valid, + output io_ddrMasters_0_r_ready, + input [127:0] io_ddrMasters_0_r_payload_data, + input [3:0] io_ddrMasters_0_r_payload_id, + input [1:0] io_ddrMasters_0_r_payload_resp, + input io_ddrMasters_0_r_payload_last, + input io_ddrMasters_0_clk, + input io_ddrMasters_0_reset, + output io_ddrMasters_memCheck_pass, + output userInterruptA, + output userInterruptB, + output userInterruptC, + output userInterruptD, + output userInterruptE, + output userInterruptF, + output userInterruptH, + output userInterruptG, + output userInterruptI, + input [3:0] system_gpio_0_io_read, + output [3:0] system_gpio_0_io_write, + output [3:0] system_gpio_0_io_writeEnable, + output system_uart_0_io_txd, + input system_uart_0_io_rxd, + output system_spi_0_io_sclk_write, + output system_spi_0_io_data_0_writeEnable, + input system_spi_0_io_data_0_read, + output system_spi_0_io_data_0_write, + output system_spi_0_io_data_1_writeEnable, + input system_spi_0_io_data_1_read, + output system_spi_0_io_data_1_write, + output system_spi_0_io_data_2_writeEnable, + input system_spi_0_io_data_2_read, + output system_spi_0_io_data_2_write, + output system_spi_0_io_data_3_writeEnable, + input system_spi_0_io_data_3_read, + output system_spi_0_io_data_3_write, + output [3:0] system_spi_0_io_ss, + output system_i2c_0_io_sda_writeEnable, + output system_i2c_0_io_sda_write, + input system_i2c_0_io_sda_read, + output system_i2c_0_io_scl_writeEnable, + output system_i2c_0_io_scl_write, + input system_i2c_0_io_scl_read, + input [31:0] axiA_awaddr, + input [7:0] axiA_awlen, + input [2:0] axiA_awsize, + input [1:0] axiA_awburst, + input axiA_awlock, + input [3:0] axiA_awcache, + input [2:0] axiA_awprot, + input [3:0] axiA_awqos, + input [3:0] axiA_awregion, + input axiA_awvalid, + output axiA_awready, + input [31:0] axiA_wdata, + input [3:0] axiA_wstrb, + input axiA_wvalid, + input axiA_wlast, + output axiA_wready, + output [1:0] axiA_bresp, + output axiA_bvalid, + input axiA_bready, + input [31:0] axiA_araddr, + input [7:0] axiA_arlen, + input [2:0] axiA_arsize, + input [1:0] axiA_arburst, + input axiA_arlock, + input [3:0] axiA_arcache, + input [2:0] axiA_arprot, + input [3:0] axiA_arqos, + input [3:0] axiA_arregion, + input axiA_arvalid, + output axiA_arready, + output [31:0] axiA_rdata, + output [1:0] axiA_rresp, + output axiA_rlast, + output axiA_rvalid, + input axiA_rready, + output axiAInterrupt, + input cfg_done, + output cfg_start, + output cfg_sel, + output cfg_reset, + input io_peripheralClk, + input io_peripheralReset, + output io_asyncReset, + input io_gpio_sw_n, + input pll_peripheral_locked, + input pll_system_locked, + input pll_tse_locked, + // SDHC + input sd_base_clk, + output sd_clk_hi, + output sd_clk_lo, + input sd_cmd_i, + output sd_cmd_o, + output sd_cmd_oe, + input [3:0] sd_dat_i, + output [3:0] sd_dat_o, + output [3:0] sd_dat_oe, + input sd_cd_n, + input sd_wp, + // TSEMAC + input io_tseClk, + // MAC + output [3:0] rgmii_txd_HI, + output [3:0] rgmii_txd_LO, + output rgmii_tx_ctl_HI, + output rgmii_tx_ctl_LO, + output rgmii_txc_HI, + output rgmii_txc_LO, + input [3:0] rgmii_rxd_HI, + input [3:0] rgmii_rxd_LO, + input rgmii_rx_ctl_HI, + input rgmii_rx_ctl_LO, + input mux_clk, + output [1:0] mux_clk_sw, + // PHY + output phy_rst, + input phy_mdi, + output phy_mdo, + output phy_mdo_en, + output phy_mdc, + input rgmii_rxc, + input rgmii_rxc_slow +); + + + +top_soc u_top_soc ( + .jtagCtrl_tdi (jtagCtrl_tdi), + .jtagCtrl_tdo (jtagCtrl_tdo), + .jtagCtrl_enable (jtagCtrl_enable), + .jtagCtrl_capture (jtagCtrl_capture), + .jtagCtrl_shift (jtagCtrl_shift), + .jtagCtrl_update (jtagCtrl_update), + .jtagCtrl_reset (jtagCtrl_reset), + .ut_jtagCtrl_tdi (ut_jtagCtrl_tdi), + .ut_jtagCtrl_tdo (ut_jtagCtrl_tdo), + .ut_jtagCtrl_enable (ut_jtagCtrl_enable), + .ut_jtagCtrl_capture (ut_jtagCtrl_capture), + .ut_jtagCtrl_shift (ut_jtagCtrl_shift), + .ut_jtagCtrl_update (ut_jtagCtrl_update), + .ut_jtagCtrl_reset (ut_jtagCtrl_reset), + .io_cfuClk (io_cfuClk), + .io_cfuReset (io_cfuReset), + .io_ddrMasters_0_aw_valid (io_ddrMasters_0_aw_valid), + .io_ddrMasters_0_aw_ready (io_ddrMasters_0_aw_ready), + .io_ddrMasters_0_aw_payload_addr (io_ddrMasters_0_aw_payload_addr), + .io_ddrMasters_0_aw_payload_id (io_ddrMasters_0_aw_payload_id), + .io_ddrMasters_0_aw_payload_region (io_ddrMasters_0_aw_payload_region), + .io_ddrMasters_0_aw_payload_len (io_ddrMasters_0_aw_payload_len), + .io_ddrMasters_0_aw_payload_size (io_ddrMasters_0_aw_payload_size), + .io_ddrMasters_0_aw_payload_burst (io_ddrMasters_0_aw_payload_burst), + .io_ddrMasters_0_aw_payload_lock (io_ddrMasters_0_aw_payload_lock), + .io_ddrMasters_0_aw_payload_cache (io_ddrMasters_0_aw_payload_cache), + .io_ddrMasters_0_aw_payload_qos (io_ddrMasters_0_aw_payload_qos), + .io_ddrMasters_0_aw_payload_prot (io_ddrMasters_0_aw_payload_prot), + .io_ddrMasters_0_aw_payload_allStrb (io_ddrMasters_0_aw_payload_allStrb), + .io_ddrMasters_0_w_valid (io_ddrMasters_0_w_valid), + .io_ddrMasters_0_w_ready (io_ddrMasters_0_w_ready), + .io_ddrMasters_0_w_payload_data (io_ddrMasters_0_w_payload_data), + .io_ddrMasters_0_w_payload_strb (io_ddrMasters_0_w_payload_strb), + .io_ddrMasters_0_w_payload_last (io_ddrMasters_0_w_payload_last), + .io_ddrMasters_0_b_valid (io_ddrMasters_0_b_valid), + .io_ddrMasters_0_b_ready (io_ddrMasters_0_b_ready), + .io_ddrMasters_0_b_payload_id (io_ddrMasters_0_b_payload_id), + .io_ddrMasters_0_b_payload_resp (io_ddrMasters_0_b_payload_resp), + .io_ddrMasters_0_ar_valid (io_ddrMasters_0_ar_valid), + .io_ddrMasters_0_ar_ready (io_ddrMasters_0_ar_ready), + .io_ddrMasters_0_ar_payload_addr (io_ddrMasters_0_ar_payload_addr), + .io_ddrMasters_0_ar_payload_id (io_ddrMasters_0_ar_payload_id), + .io_ddrMasters_0_ar_payload_region (io_ddrMasters_0_ar_payload_region), + .io_ddrMasters_0_ar_payload_len (io_ddrMasters_0_ar_payload_len), + .io_ddrMasters_0_ar_payload_size (io_ddrMasters_0_ar_payload_size), + .io_ddrMasters_0_ar_payload_burst (io_ddrMasters_0_ar_payload_burst), + .io_ddrMasters_0_ar_payload_lock (io_ddrMasters_0_ar_payload_lock), + .io_ddrMasters_0_ar_payload_cache (io_ddrMasters_0_ar_payload_cache), + .io_ddrMasters_0_ar_payload_qos (io_ddrMasters_0_ar_payload_qos), + .io_ddrMasters_0_ar_payload_prot (io_ddrMasters_0_ar_payload_prot), + .io_ddrMasters_0_r_valid (io_ddrMasters_0_r_valid), + .io_ddrMasters_0_r_ready (io_ddrMasters_0_r_ready), + .io_ddrMasters_0_r_payload_data (io_ddrMasters_0_r_payload_data), + .io_ddrMasters_0_r_payload_id (io_ddrMasters_0_r_payload_id), + .io_ddrMasters_0_r_payload_resp (io_ddrMasters_0_r_payload_resp), + .io_ddrMasters_0_r_payload_last (io_ddrMasters_0_r_payload_last), + .io_ddrMasters_0_clk (io_ddrMasters_0_clk), + .io_ddrMasters_0_reset (io_ddrMasters_0_reset), + .io_ddrMasters_memCheck_pass (io_ddrMasters_memCheck_pass), + .userInterruptA (userInterruptA), + .userInterruptB (userInterruptB), + .userInterruptC (userInterruptC), + .userInterruptD (userInterruptD), + .userInterruptE (userInterruptE), + .userInterruptF (userInterruptF), + .userInterruptH (userInterruptH), + .userInterruptG (userInterruptG), + .userInterruptI (userInterruptI), + .system_gpio_0_io_read (system_gpio_0_io_read), + .system_gpio_0_io_write (system_gpio_0_io_write), + .system_gpio_0_io_writeEnable (system_gpio_0_io_writeEnable), + .system_uart_0_io_txd (system_uart_0_io_txd), + .system_uart_0_io_rxd (system_uart_0_io_rxd), + .system_spi_0_io_sclk_write (system_spi_0_io_sclk_write), + .system_spi_0_io_data_0_writeEnable (system_spi_0_io_data_0_writeEnable), + .system_spi_0_io_data_0_read (system_spi_0_io_data_0_read), + .system_spi_0_io_data_0_write (system_spi_0_io_data_0_write), + .system_spi_0_io_data_1_writeEnable (system_spi_0_io_data_1_writeEnable), + .system_spi_0_io_data_1_read (system_spi_0_io_data_1_read), + .system_spi_0_io_data_1_write (system_spi_0_io_data_1_write), + .system_spi_0_io_data_2_writeEnable (system_spi_0_io_data_2_writeEnable), + .system_spi_0_io_data_2_read (system_spi_0_io_data_2_read), + .system_spi_0_io_data_2_write (system_spi_0_io_data_2_write), + .system_spi_0_io_data_3_writeEnable (system_spi_0_io_data_3_writeEnable), + .system_spi_0_io_data_3_read (system_spi_0_io_data_3_read), + .system_spi_0_io_data_3_write (system_spi_0_io_data_3_write), + .system_spi_0_io_ss (system_spi_0_io_ss), + .system_i2c_0_io_sda_writeEnable (system_i2c_0_io_sda_writeEnable), + .system_i2c_0_io_sda_write (system_i2c_0_io_sda_write), + .system_i2c_0_io_sda_read (system_i2c_0_io_sda_read), + .system_i2c_0_io_scl_writeEnable (system_i2c_0_io_scl_writeEnable), + .system_i2c_0_io_scl_write (system_i2c_0_io_scl_write), + .system_i2c_0_io_scl_read (system_i2c_0_io_scl_read), + .axiA_awaddr (axiA_awaddr), + .axiA_awlen (axiA_awlen), + .axiA_awsize (axiA_awsize), + .axiA_awburst (axiA_awburst), + .axiA_awlock (axiA_awlock), + .axiA_awcache (axiA_awcache), + .axiA_awprot (axiA_awprot), + .axiA_awqos (axiA_awqos), + .axiA_awregion (axiA_awregion), + .axiA_awvalid (axiA_awvalid), + .axiA_awready (axiA_awready), + .axiA_wdata (axiA_wdata), + .axiA_wstrb (axiA_wstrb), + .axiA_wvalid (axiA_wvalid), + .axiA_wlast (axiA_wlast), + .axiA_wready (axiA_wready), + .axiA_bresp (axiA_bresp), + .axiA_bvalid (axiA_bvalid), + .axiA_bready (axiA_bready), + .axiA_araddr (axiA_araddr), + .axiA_arlen (axiA_arlen), + .axiA_arsize (axiA_arsize), + .axiA_arburst (axiA_arburst), + .axiA_arlock (axiA_arlock), + .axiA_arcache (axiA_arcache), + .axiA_arprot (axiA_arprot), + .axiA_arqos (axiA_arqos), + .axiA_arregion (axiA_arregion), + .axiA_arvalid (axiA_arvalid), + .axiA_arready (axiA_arready), + .axiA_rdata (axiA_rdata), + .axiA_rresp (axiA_rresp), + .axiA_rlast (axiA_rlast), + .axiA_rvalid (axiA_rvalid), + .axiA_rready (axiA_rready), + .axiAInterrupt (axiAInterrupt), + .cfg_done (cfg_done), + .cfg_start (cfg_start), + .cfg_sel (cfg_sel), + .cfg_reset (cfg_reset), + .io_peripheralClk (io_peripheralClk), + .io_peripheralReset (io_peripheralReset), + .io_asyncReset (io_asyncReset), + .io_gpio_sw_n (io_gpio_sw_n), + .pll_peripheral_locked (pll_peripheral_locked), + .pll_system_locked (pll_system_locked), + .pll_tse_locked (pll_tse_locked), + .sd_base_clk (sd_base_clk), + .sd_clk_hi (sd_clk_hi), + .sd_clk_lo (sd_clk_lo), + .sd_cmd_i (sd_cmd_i), + .sd_cmd_o (sd_cmd_o), + .sd_cmd_oe (sd_cmd_oe), + .sd_dat_i (sd_dat_i), + .sd_dat_o (sd_dat_o), + .sd_dat_oe (sd_dat_oe), + .sd_cd_n (sd_cd_n), + .sd_wp (sd_wp), + .io_tseClk (io_tseClk), + .rgmii_txd_HI (rgmii_txd_HI), + .rgmii_txd_LO (rgmii_txd_LO), + .rgmii_tx_ctl_HI (rgmii_tx_ctl_HI), + .rgmii_tx_ctl_LO (rgmii_tx_ctl_LO), + .rgmii_txc_HI (rgmii_txc_HI), + .rgmii_txc_LO (rgmii_txc_LO), + .rgmii_rxd_HI (rgmii_rxd_HI), + .rgmii_rxd_LO (rgmii_rxd_LO), + .rgmii_rx_ctl_HI (rgmii_rx_ctl_HI), + .rgmii_rx_ctl_LO (rgmii_rx_ctl_LO), + .mux_clk (mux_clk), + .mux_clk_sw (mux_clk_sw), + .phy_rst (phy_rst), + .phy_mdi (phy_mdi), + .phy_mdo (phy_mdo), + .phy_mdo_en (phy_mdo_en), + .phy_mdc (phy_mdc), + .rgmii_rxc (rgmii_rxc), + .rgmii_rxc_slow (rgmii_rxc_slow) +); + +endmodule \ No newline at end of file diff --git a/src/regs/gen_regs.sh b/src/regs/gen_regs.sh new file mode 100755 index 0000000..b8a12a2 --- /dev/null +++ b/src/regs/gen_regs.sh @@ -0,0 +1 @@ +peakrdl regblock -o . --cpuif taxi-apb verilog6502_io_regs.rdl \ No newline at end of file diff --git a/src/regs/verilog6502_io_regs.rdl b/src/regs/verilog6502_io_regs.rdl new file mode 100644 index 0000000..a8301ec --- /dev/null +++ b/src/regs/verilog6502_io_regs.rdl @@ -0,0 +1,37 @@ +addrmap verilog6502_io_regs { + name = ""; + desc = ""; + + reg { + name = "Core Control"; + desc = ""; + + field { + name = "reset"; + desc = ""; + hw = r; + sw = rw; + } reset[0:0] = 0x1; + + } core_ctrl @ 0x0; + + + reg { + name = "reset_brq"; + desc = ""; + + field { + name = "reset"; + desc = ""; + hw = r; + sw = rw; + } reset[15:0] = 0x200; + + field { + name = "brq"; + desc = ""; + hw = r; + sw = rw; + } brk[31:16] = 0x200; + } reset_brq @ 0xffc; +}; \ No newline at end of file diff --git a/src/regs/verilog6502_io_regs.sv b/src/regs/verilog6502_io_regs.sv new file mode 100644 index 0000000..3f5e267 --- /dev/null +++ b/src/regs/verilog6502_io_regs.sv @@ -0,0 +1,262 @@ +// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator +// https://github.com/SystemRDL/PeakRDL-regblock + +module verilog6502_io_regs ( + input wire clk, + input wire rst, + + taxi_apb_if.slv s_apb, + + output verilog6502_io_regs_pkg::verilog6502_io_regs__out_t hwif_out + ); + + //-------------------------------------------------------------------------- + // CPU Bus interface logic + //-------------------------------------------------------------------------- + logic cpuif_req; + logic cpuif_req_is_wr; + logic [11:0] cpuif_addr; + logic [31:0] cpuif_wr_data; + logic [31:0] cpuif_wr_biten; + logic cpuif_req_stall_wr; + logic cpuif_req_stall_rd; + + logic cpuif_rd_ack; + logic cpuif_rd_err; + logic [31:0] cpuif_rd_data; + + logic cpuif_wr_ack; + logic cpuif_wr_err; + + `ifndef SYNTHESIS + initial begin + assert_bad_addr_width: assert($bits(s_apb.paddr) >= verilog6502_io_regs_pkg::VERILOG6502_IO_REGS_MIN_ADDR_WIDTH) + else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits(s_apb.paddr), verilog6502_io_regs_pkg::VERILOG6502_IO_REGS_MIN_ADDR_WIDTH); + assert_bad_data_width: assert($bits(s_apb.pwdata) == verilog6502_io_regs_pkg::VERILOG6502_IO_REGS_DATA_WIDTH) + else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits(s_apb.pwdata), verilog6502_io_regs_pkg::VERILOG6502_IO_REGS_DATA_WIDTH); + end + `endif + + // Request + logic is_active; + always_ff @(posedge clk) begin + if(rst) begin + is_active <= '0; + cpuif_req <= '0; + cpuif_req_is_wr <= '0; + cpuif_addr <= '0; + cpuif_wr_data <= '0; + cpuif_wr_biten <= '0; + end else begin + if(~is_active) begin + if(s_apb.psel) begin + is_active <= '1; + cpuif_req <= '1; + cpuif_req_is_wr <= s_apb.pwrite; + cpuif_addr <= {s_apb.paddr[11:2], 2'b0}; + cpuif_wr_data <= s_apb.pwdata; + for(int i=0; i<4; i++) begin + cpuif_wr_biten[i*8 +: 8] <= {8{s_apb.pstrb[i]}}; + end + end + end else begin + cpuif_req <= '0; + if(cpuif_rd_ack || cpuif_wr_ack) begin + is_active <= '0; + end + end + end + end + + // Response + assign s_apb.pready = cpuif_rd_ack | cpuif_wr_ack; + assign s_apb.prdata = cpuif_rd_data; + assign s_apb.pslverr = cpuif_rd_err | cpuif_wr_err; + + logic cpuif_req_masked; + + // Read & write latencies are balanced. Stalls not required + assign cpuif_req_stall_rd = '0; + assign cpuif_req_stall_wr = '0; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); + + //-------------------------------------------------------------------------- + // Address Decode + //-------------------------------------------------------------------------- + typedef struct { + logic core_ctrl; + logic reset_brq; + } decoded_reg_strb_t; + decoded_reg_strb_t decoded_reg_strb; + logic decoded_err; + logic [11:0] decoded_addr; + logic decoded_req; + logic decoded_req_is_wr; + logic [31:0] decoded_wr_data; + logic [31:0] decoded_wr_biten; + + always_comb begin + automatic logic is_valid_addr; + automatic logic is_valid_rw; + is_valid_addr = '1; // No valid address check + is_valid_rw = '1; // No valid RW check + decoded_reg_strb.core_ctrl = cpuif_req_masked & (cpuif_addr == 12'h0); + decoded_reg_strb.reset_brq = cpuif_req_masked & (cpuif_addr == 12'hffc); + decoded_err = '0; + end + + // Pass down signals to next stage + assign decoded_addr = cpuif_addr; + assign decoded_req = cpuif_req_masked; + assign decoded_req_is_wr = cpuif_req_is_wr; + assign decoded_wr_data = cpuif_wr_data; + assign decoded_wr_biten = cpuif_wr_biten; + + //-------------------------------------------------------------------------- + // Field logic + //-------------------------------------------------------------------------- + typedef struct { + struct { + struct { + logic next; + logic load_next; + } reset; + } core_ctrl; + struct { + struct { + logic [15:0] next; + logic load_next; + } reset; + struct { + logic [15:0] next; + logic load_next; + } brk; + } reset_brq; + } field_combo_t; + field_combo_t field_combo; + + typedef struct { + struct { + struct { + logic value; + } reset; + } core_ctrl; + struct { + struct { + logic [15:0] value; + } reset; + struct { + logic [15:0] value; + } brk; + } reset_brq; + } field_storage_t; + field_storage_t field_storage; + + // Field: verilog6502_io_regs.core_ctrl.reset + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.core_ctrl.reset.value; + load_next_c = '0; + if(decoded_reg_strb.core_ctrl && decoded_req_is_wr) begin // SW write + next_c = (field_storage.core_ctrl.reset.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); + load_next_c = '1; + end + field_combo.core_ctrl.reset.next = next_c; + field_combo.core_ctrl.reset.load_next = load_next_c; + end + always_ff @(posedge clk) begin + if(rst) begin + field_storage.core_ctrl.reset.value <= 1'h1; + end else begin + if(field_combo.core_ctrl.reset.load_next) begin + field_storage.core_ctrl.reset.value <= field_combo.core_ctrl.reset.next; + end + end + end + assign hwif_out.core_ctrl.reset.value = field_storage.core_ctrl.reset.value; + // Field: verilog6502_io_regs.reset_brq.reset + always_comb begin + automatic logic [15:0] next_c; + automatic logic load_next_c; + next_c = field_storage.reset_brq.reset.value; + load_next_c = '0; + if(decoded_reg_strb.reset_brq && decoded_req_is_wr) begin // SW write + next_c = (field_storage.reset_brq.reset.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]); + load_next_c = '1; + end + field_combo.reset_brq.reset.next = next_c; + field_combo.reset_brq.reset.load_next = load_next_c; + end + always_ff @(posedge clk) begin + if(rst) begin + field_storage.reset_brq.reset.value <= 16'h200; + end else begin + if(field_combo.reset_brq.reset.load_next) begin + field_storage.reset_brq.reset.value <= field_combo.reset_brq.reset.next; + end + end + end + assign hwif_out.reset_brq.reset.value = field_storage.reset_brq.reset.value; + // Field: verilog6502_io_regs.reset_brq.brk + always_comb begin + automatic logic [15:0] next_c; + automatic logic load_next_c; + next_c = field_storage.reset_brq.brk.value; + load_next_c = '0; + if(decoded_reg_strb.reset_brq && decoded_req_is_wr) begin // SW write + next_c = (field_storage.reset_brq.brk.value & ~decoded_wr_biten[31:16]) | (decoded_wr_data[31:16] & decoded_wr_biten[31:16]); + load_next_c = '1; + end + field_combo.reset_brq.brk.next = next_c; + field_combo.reset_brq.brk.load_next = load_next_c; + end + always_ff @(posedge clk) begin + if(rst) begin + field_storage.reset_brq.brk.value <= 16'h200; + end else begin + if(field_combo.reset_brq.brk.load_next) begin + field_storage.reset_brq.brk.value <= field_combo.reset_brq.brk.next; + end + end + end + assign hwif_out.reset_brq.brk.value = field_storage.reset_brq.brk.value; + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + assign cpuif_wr_ack = decoded_req & decoded_req_is_wr; + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + + //-------------------------------------------------------------------------- + // Readback + //-------------------------------------------------------------------------- + + logic [11:0] rd_mux_addr; + assign rd_mux_addr = decoded_addr; + + logic readback_err; + logic readback_done; + logic [31:0] readback_data; + always_comb begin + automatic logic [31:0] readback_data_var; + readback_data_var = '0; + if(rd_mux_addr == 12'h0) begin + readback_data_var[0] = field_storage.core_ctrl.reset.value; + end + if(rd_mux_addr == 12'hffc) begin + readback_data_var[15:0] = field_storage.reset_brq.reset.value; + readback_data_var[31:16] = field_storage.reset_brq.brk.value; + end + readback_data = readback_data_var; + readback_done = decoded_req & ~decoded_req_is_wr; + readback_err = '0; + end + + assign cpuif_rd_ack = readback_done; + assign cpuif_rd_data = readback_data; + assign cpuif_rd_err = readback_err; +endmodule diff --git a/src/regs/verilog6502_io_regs_pkg.sv b/src/regs/verilog6502_io_regs_pkg.sv new file mode 100644 index 0000000..3750542 --- /dev/null +++ b/src/regs/verilog6502_io_regs_pkg.sv @@ -0,0 +1,35 @@ +// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator +// https://github.com/SystemRDL/PeakRDL-regblock + +package verilog6502_io_regs_pkg; + + localparam VERILOG6502_IO_REGS_DATA_WIDTH = 32; + localparam VERILOG6502_IO_REGS_MIN_ADDR_WIDTH = 12; + localparam VERILOG6502_IO_REGS_SIZE = 'h1000; + + typedef struct { + logic value; + } verilog6502_io_regs__core_ctrl__reset__out_t; + + typedef struct { + verilog6502_io_regs__core_ctrl__reset__out_t reset; + } verilog6502_io_regs__core_ctrl__out_t; + + typedef struct { + logic [15:0] value; + } verilog6502_io_regs__reset_brq__reset__out_t; + + typedef struct { + logic [15:0] value; + } verilog6502_io_regs__reset_brq__brk__out_t; + + typedef struct { + verilog6502_io_regs__reset_brq__reset__out_t reset; + verilog6502_io_regs__reset_brq__brk__out_t brk; + } verilog6502_io_regs__reset_brq__out_t; + + typedef struct { + verilog6502_io_regs__core_ctrl__out_t core_ctrl; + verilog6502_io_regs__reset_brq__out_t reset_brq; + } verilog6502_io_regs__out_t; +endpackage diff --git a/src/verilog6502_addr_decoder.sv b/src/verilog6502_addr_decoder.sv new file mode 100644 index 0000000..7ef3b38 --- /dev/null +++ b/src/verilog6502_addr_decoder.sv @@ -0,0 +1,130 @@ +module verilog6502_addr_decoder( + input i_clk, + input i_rst, + + input logic [15:0] i_cpu_addr, + input logic [7:0] i_cpu_data, + output logic [7:0] o_cpu_data, + input logic i_cpu_we, + /* verilator lint_off UNOPTFLAT */ + output logic o_cpu_rdy, + /* verilator lint_on UNOPTFLAT */ + + + output logic [15:0] o_mem_addr, + output logic [7:0] o_mem_data, + input logic [7:0] i_mem_data, + output logic o_mem_rd, + output logic o_mem_we, + input logic i_mem_rdy, + + output logic [15:0] o_external_addr, + output logic [7:0] o_external_data, + input logic [7:0] i_external_data, + output logic o_external_rd, + output logic o_external_we, + input logic i_external_rdy, + + output logic [15:0] o_io_addr, + output logic [7:0] o_io_data, + input logic [7:0] i_io_data, + output logic o_io_rd, + output logic o_io_we, + input logic i_io_rdy +); + +enum logic [1:0] {NONE, MEM, EXT, IO} prev_addr, prev_addr_next; + +always_ff @(posedge i_clk) begin + if (i_rst) begin + prev_addr <= NONE; + end else begin + prev_addr <= prev_addr_next; + end +end + +always_comb begin + prev_addr_next = prev_addr; + + o_mem_addr = '0; + o_mem_data = '0; + o_mem_rd = '0; + o_mem_we = '0; + + o_external_addr = '0; + o_external_data = '0; + o_external_rd = '0; + o_external_we = '0; + + o_io_addr = '0; + o_io_data = '0; + o_io_rd = '0; + o_io_we = '0; + + case (prev_addr) + NONE: begin + o_cpu_rdy = '1; + o_cpu_data = '0; + end + + MEM: begin + o_cpu_rdy = i_mem_rdy; + o_cpu_data = i_mem_data; + end + + EXT: begin + o_cpu_rdy = i_external_rdy; + o_cpu_data = i_external_data; + end + + IO: begin + o_cpu_rdy = i_io_rdy; + o_cpu_data = i_io_data; + end + + default: begin + o_cpu_rdy = '1; + o_cpu_data = '0; + end + endcase + + if (o_cpu_rdy) begin + if (i_cpu_addr < 16'hE000) begin + o_mem_addr = i_cpu_addr; + o_mem_data = i_cpu_data; + o_mem_we = i_cpu_we & o_cpu_rdy; + o_mem_rd = ~i_cpu_we & o_cpu_rdy; + prev_addr_next = MEM; + // o_cpu_rdy = i_mem_rdy; + // o_cpu_data = i_mem_data; + end else if (i_cpu_addr < 16'hF000) begin + o_external_addr = {4'b0, i_cpu_addr[11:0]}; + o_external_data = i_cpu_data; + o_external_we = i_cpu_we & o_cpu_rdy; + o_external_rd = ~i_cpu_we & o_cpu_rdy; + prev_addr_next = EXT; + // o_cpu_rdy = i_external_rdy; + // o_cpu_data = i_external_data; + end else begin + o_io_addr = {4'b0, i_cpu_addr[11:0]}; + o_io_data = i_cpu_data; + o_io_we = i_cpu_we & o_cpu_rdy; + o_io_rd = ~i_cpu_we & o_cpu_rdy; + prev_addr_next = IO; + // o_cpu_rdy = i_io_rdy; + // o_cpu_data = i_io_data; + end + end + + if (i_rst) begin + o_mem_rd = 0; + o_mem_we = 0; + o_external_rd = 0; + o_external_we = 0; + o_io_rd = 0; + o_io_we = 0; + end + +end + +endmodule \ No newline at end of file diff --git a/src/verilog6502_apb_adapter.sv b/src/verilog6502_apb_adapter.sv new file mode 100644 index 0000000..6d1bb36 --- /dev/null +++ b/src/verilog6502_apb_adapter.sv @@ -0,0 +1,116 @@ +module verilog6502_apb_adapter( + input i_clk, + input i_rst, + + input logic [15:0] i_addr, + input logic [7:0] i_data, + output logic [7:0] o_data, + input logic i_rd, + input logic i_we, + output logic o_rdy, + + taxi_apb_if.mst m_apb +); + +enum logic {IDLE, ENABLE} state, state_next; + +logic [15:0] latched_addr, latched_addr_next; +logic [15:0] second_addr, second_addr_next; +logic second_we, second_rd, second_we_next, second_rd_next; +logic [7:0] latched_data, latched_data_next; +logic [7:0] second_data, second_data_next; +logic latched_pwrite, latched_pwrite_next; + +always_ff @(posedge i_clk) begin + if (i_rst) begin + state <= IDLE; + latched_addr <= '0; + second_addr <= '0; + second_we <= '0; + second_rd <= '0; + latched_data <= '0; + latched_pwrite <= '0; + second_data <= '0; + end else begin + state <= state_next; + latched_addr <= latched_addr_next; + second_addr <= second_addr_next; + second_we <= second_we_next; + second_rd <= second_rd_next; + latched_data <= latched_data_next; + latched_pwrite <= latched_pwrite_next; + second_data <= second_data_next; + end +end + + +always_comb begin + + + case (state) + IDLE: begin + if (i_rd | i_we) begin + m_apb.pprot = '0; + m_apb.paddr = {16'b0, i_addr} & 32'hfffc; // 32 bit address + m_apb.psel = '1; + m_apb.pwrite = i_we; + m_apb.pstrb = 4'h1 << i_addr[1:0]; // shift based on lower 2 bits + m_apb.pwdata = {24'b0, i_data} << i_addr[1:0]; + o_rdy = '0; + + m_apb.penable = '0; + state_next = ENABLE; + latched_addr_next = i_addr; + latched_data_next = i_data; + latched_pwrite_next = i_we; + end else if (second_rd | second_we) begin + m_apb.pprot = '0; + m_apb.paddr = {16'b0, second_addr} & 32'hfffc; // 32 bit address + m_apb.psel = '1; + m_apb.pwrite = second_we; + m_apb.pstrb = 4'h1 << second_addr[1:0]; // shift based on lower 2 bits + m_apb.pwdata = {24'b0, second_data} << second_addr[1:0]; + o_rdy = '0; + + m_apb.penable = '0; + state_next = ENABLE; + latched_addr_next = second_addr; + latched_data_next = second_data; + latched_pwrite_next = second_we; + end else begin + m_apb.pprot = '0; + m_apb.paddr = '0; + m_apb.psel = '0; + m_apb.pwrite = '0; + m_apb.pstrb = '0; + m_apb.pwdata = '0; + o_rdy = '0; + end + end + + ENABLE: begin + m_apb.penable = '1; + + second_we_next = i_we; + second_rd_next = i_rd; + second_addr_next = i_addr; + second_data_next = i_data; + + m_apb.pprot = '0; + m_apb.paddr = {16'b0, latched_addr} & 32'hfffc; // 32 bit address + m_apb.psel = '1; + m_apb.pwrite = latched_pwrite; + m_apb.pstrb = 4'h1 << latched_addr[1:0]; // shift based on lower 2 bits + m_apb.pwdata = {24'b0, latched_data} << latched_addr[1:0]; + + if (m_apb.pready) begin + state_next = IDLE; + o_data = m_apb.prdata[8 * latched_addr[1:0] +: 8]; + o_rdy = '1; + end + end + + endcase +end + +endmodule \ No newline at end of file diff --git a/src/verilog6502_internal_memory.sv b/src/verilog6502_internal_memory.sv new file mode 100644 index 0000000..4ac6d92 --- /dev/null +++ b/src/verilog6502_internal_memory.sv @@ -0,0 +1,163 @@ +module verilog6502_internal_memory( + input i_clk, + input i_rst, + + taxi_axi_if.rd_slv s_axi_rd, + taxi_axi_if.wr_slv s_axi_wr, + + input logic [15:0] i_addr, + input logic [7:0] i_data, + output logic [7:0] o_data, + input logic i_rd, + input logic i_we, + output logic o_rdy +); + +localparam ID_W = 8; +localparam ADDR_W = 32; +localparam AUSER_W = 1; +localparam RUSER_W = 1; +localparam WUSER_W = 1; +localparam DATA_W = 32; +localparam STRB_W = 4; + +logic [ID_W-1:0] ram_cmd_id; +logic [ADDR_W-1:0] ram_cmd_addr; +logic [DATA_W-1:0] ram_cmd_wr_data; +logic [STRB_W-1:0] ram_cmd_wr_strb; +logic ram_cmd_wr_en; +logic ram_cmd_rd_en; +logic ram_cmd_last; +logic ram_cmd_ready; +logic [DATA_W-1:0] ram_rd_resp_data; +logic ram_rd_resp_last; +logic ram_rd_resp_valid; +logic ram_rd_resp_ready; + +taxi_axi_ram_if_rdwr #( + .DATA_W(DATA_W), + .ADDR_W(ADDR_W), + .STRB_W(STRB_W), + .ID_W(ID_W), + .AUSER_W(AUSER_W), + .WUSER_W(WUSER_W), + .RUSER_W(RUSER_W) +) axi_ram_if_rdwr ( + .clk (i_clk), + .rst (i_rst), + + .s_axi_wr (s_axi_wr), + .s_axi_rd (s_axi_rd), + + .ram_cmd_id (ram_cmd_id), + .ram_cmd_addr (ram_cmd_addr), + .ram_cmd_lock (), + .ram_cmd_cache (), + .ram_cmd_prot (), + .ram_cmd_qos (), + .ram_cmd_region (), + .ram_cmd_auser (), + .ram_cmd_wr_data (ram_cmd_wr_data), + .ram_cmd_wr_strb (ram_cmd_wr_strb), + .ram_cmd_wr_user (), + .ram_cmd_wr_en (ram_cmd_wr_en), + .ram_cmd_rd_en (ram_cmd_rd_en), + .ram_cmd_last (ram_cmd_last), + .ram_cmd_ready (ram_cmd_ready), + .ram_rd_resp_id (), + .ram_rd_resp_data (ram_rd_resp_data), + .ram_rd_resp_last (ram_rd_resp_last), + .ram_rd_resp_user (), + .ram_rd_resp_valid (ram_rd_resp_valid), + .ram_rd_resp_ready (ram_rd_resp_ready) +); + + +logic [7:0] mem [4][14*1024]; + + +enum logic {CPU, EXT} sel, sel_next; + +logic [15:0] ram_addr; +logic [31:0] ram_wdata; +logic [3:0] ram_wstrb; +logic ram_we; + +logic ram_re; +logic [31:0] ram_rdata; +logic ram_rdata_valid; + + +always_ff @(posedge i_clk) begin + if (i_rst) begin + sel <= CPU; + end else begin + sel <= sel_next; + + ram_rdata_valid <= '0; + ram_rd_resp_last <= '0; + + if (ram_we) begin + for (int i = 0; i < 4; i++) begin + if (ram_wstrb[i]) begin + mem[i][ram_addr[15:2]] <= ram_wdata[8*i +: 8]; + end + end + end + + if (ram_re) begin + for (int i = 0; i < 4; i++) begin + ram_rdata[8*i +: 8] <= mem[i][ram_addr[15:2]]; + end + ram_rdata_valid <= '1; + ram_rd_resp_last <= ram_cmd_last; + end + end +end + +always_comb begin + sel_next = sel; + + ram_cmd_ready = '0; + + ram_addr = '0; + ram_we = '0; + ram_wdata = '0; + ram_we = '0; + ram_re = '0; + + ram_rd_resp_valid = '0; + ram_rd_resp_data = '0; + + case (sel) + CPU: begin + // if there was no CPU op, then give external bus a chance + if (~(i_rd | i_we)) begin + sel_next = EXT; + end + end + + EXT: begin + ram_cmd_ready = '1; + + if (ram_cmd_wr_en) begin + ram_addr = ram_cmd_addr[15:0]; + ram_wdata = ram_cmd_wr_data; + ram_wstrb = ram_cmd_wr_strb; + ram_we = '1; + end else if (ram_cmd_rd_en) begin + ram_addr = ram_cmd_addr[15:0]; + ram_re = '1; + + end else begin + sel_next = CPU; + end + + ram_rd_resp_valid = ram_rdata_valid; + ram_rd_resp_data = ram_rdata; + end + endcase +end + + +endmodule \ No newline at end of file diff --git a/src/verilog6502_wrapper.sv b/src/verilog6502_wrapper.sv new file mode 100644 index 0000000..e5ee5af --- /dev/null +++ b/src/verilog6502_wrapper.sv @@ -0,0 +1,176 @@ +// Wrapper around verilog-6502 + +// memory map: +// 0x0000-0x00FF Zero Page (Hard coded) +// 0x0100-0x01FF Stack (Hard coded) +// 0x0200-0xCFFF Internal Memory +// 0xE000-0xEFFF External AXI +// 0xF000-0xFFFF Processor IO + +module verilog6502_wrapper( + input clk, + input rst, + + taxi_apb_if.slv s_apb, + + taxi_axi_if.rd_mst m_axi_rd, + taxi_axi_if.wr_mst m_axi_wr, + taxi_axi_if.rd_slv s_axi_rd, + taxi_axi_if.wr_slv s_axi_wr, + + output logic o_irq_ext, + input logic i_irq_ext +); + +taxi_apb_if internal_apb(); + +taxi_apb_if s_apb_mux[2](); +taxi_apb_if m_apb_mux[1](); +taxi_apb_if m_apb(); + +taxi_apb_tie u_external_apb_tie( + .s_apb(s_apb), + .m_apb(s_apb_mux[0]) +); + +taxi_apb_tie u_internal_apb_tie( + .s_apb(internal_apb), + .m_apb(s_apb_mux[1]) +); + +taxi_apb_tie u_master_apb_tie( + .s_apb(m_apb_mux[0]), + .m_apb(m_apb) +); + +taxi_apb_interconnect #( + .S_CNT(2), + .M_CNT(1), + .ADDR_W(32) +) u_apb_interconnect ( + .clk (clk), + .rst (rst), + + .s_apb (s_apb_mux), + .m_apb (m_apb_mux) +); + + +logic cpu_clk; +logic cpu_reset; +logic [15:0] cpu_addr; +logic [7:0] cpu_data_in; +logic [7:0] cpu_data_out; + +logic cpu_we; +logic cpu_irq; +logic cpu_nmi; +logic cpu_rdy; +logic cpu_sync; + +assign cpu_clk = clk; +assign cpu_reset = hwif_out.core_ctrl.reset.value; + +assign cpu_rdy = '1; + +logic [15:0] mem_addr; +logic [7:0] mem_data_in; +logic [7:0] mem_data_out; +logic mem_rd; +logic mem_we; +logic mem_rdy; + +logic [15:0] io_addr; +logic [7:0] io_data_in; +logic [7:0] io_data_out; +logic io_rd; +logic io_we; +logic io_rdy; + +verilog6502_io_regs_pkg::verilog6502_io_regs__out_t hwif_out; + +cpu_65c02 u_cpu_6502( + .clk (cpu_clk), + .reset (cpu_reset), + + .AB (cpu_addr), + .DI (cpu_data_in), + .DO (cpu_data_out), + .WE (cpu_we), + .IRQ (cpu_irq), + .NMI (cpu_nmi), + .RDY (cpu_rdy), + .SYNC (cpu_sync) +); + +verilog6502_addr_decoder u_addr_decoder( + .i_clk (cpu_clk), + .i_rst (cpu_reset), + + .i_cpu_addr (cpu_addr), + .i_cpu_data (cpu_data_out), + .o_cpu_data (cpu_data_in), + .i_cpu_we (cpu_we), + .o_cpu_rdy (cpu_rdy), + + .o_mem_addr (mem_addr), + .o_mem_data (mem_data_in), + .i_mem_data (mem_data_out), + .o_mem_rd (mem_rd), + .o_mem_we (mem_we), + .i_mem_rdy (mem_rdy), + + .o_external_addr (), + .o_external_data (), + .i_external_data ('0), + .o_external_rd (), + .o_external_we (), + .i_external_rdy ('1), + + .o_io_addr (io_addr), + .o_io_data (io_data_in), + .i_io_data (io_data_out), + .o_io_rd (io_rd), + .o_io_we (io_we), + .i_io_rdy (io_rdy) +); + +verilog6502_internal_memory u_internal_memory( + .i_clk (cpu_clk), + .i_rst (rst), + + .s_axi_rd (s_axi_rd), + .s_axi_wr (s_axi_wr), + + .i_addr (mem_addr), + .i_data (mem_data_in), + .o_data (mem_data_out), + .i_rd (mem_rd), + .i_we (mem_we), + .o_rdy (mem_rdy) +); + +verilog6502_apb_adapter u_io_apb_adapter( + .i_clk (cpu_clk), + .i_rst (rst), + + .i_addr (io_addr), + .i_data (io_data_in), + .o_data (io_data_out), + .i_rd (io_rd), + .i_we (io_we), + .o_rdy (io_rdy), + + .m_apb (internal_apb) +); + + +verilog6502_io_regs u_io_regs ( + .clk (cpu_clk), + .rst (rst), + .s_apb (m_apb), + + .hwif_out (hwif_out) +); + +endmodule \ No newline at end of file diff --git a/sub/taxi b/sub/taxi new file mode 160000 index 0000000..1fe508a --- /dev/null +++ b/sub/taxi @@ -0,0 +1 @@ +Subproject commit 1fe508a6bf17edbb29bce9a8477be615b1012789 diff --git a/sub/verilog-6502 b/sub/verilog-6502 new file mode 160000 index 0000000..ef2cc5a --- /dev/null +++ b/sub/verilog-6502 @@ -0,0 +1 @@ +Subproject commit ef2cc5ab453b0c35e8c9f459b52eb72be70b71d7