// ============================================================================= // Generated by efx_ipmgr // Version: 2025.2.288.2.10 // IP Version: 7.1 // ============================================================================= //////////////////////////////////////////////////////////////////////////////// // Copyright (C) 2013-2025 Efinix Inc. All rights reserved. // // This document contains proprietary information which is // protected by copyright. All rights are reserved. This notice // refers to original work by Efinix, Inc. which may be derivitive // of other work distributed under license of the authors. In the // case of derivative work, nothing in this notice overrides the // original author's license agreement. Where applicable, the // original license agreement is included in it's original // unmodified form immediately below this header. // // WARRANTY DISCLAIMER. // THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND // EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH // RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, // INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF // MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR // PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED // WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. // // LIMITATION OF LIABILITY. // NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY // INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT // MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY // OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, // SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY // CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF // GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR // MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN // THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER // (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE // BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO // NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR // CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT // APPLY TO LICENSEE. // //////////////////////////////////////////////////////////////////////////////// `define IP_UUID _4c19f37180ff465ca20760e199a0613f `define IP_NAME_CONCAT(a,b) a``b `define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) module gTSE ( input mac_reset, input proto_reset, output rx_mac_aclk, input tx_mac_aclk, output [2:0] eth_speed, input rx_axis_clk, output rx_axis_mac_tuser, output rx_axis_mac_tlast, output rx_axis_mac_tvalid, input rx_axis_mac_tready, input tx_axis_clk, input tx_axis_mac_tvalid, input tx_axis_mac_tlast, input tx_axis_mac_tuser, output tx_axis_mac_tready, output [3:0] rgmii_txd_HI, output [3:0] rgmii_txd_LO, output rgmii_tx_ctl_HI, output rgmii_tx_ctl_LO, output rgmii_txc_HI, output rgmii_txc_LO, input [3:0] rgmii_rxd_HI, input [3:0] rgmii_rxd_LO, input rgmii_rx_ctl_HI, input rgmii_rx_ctl_LO, input rgmii_rxc, input s_axi_aclk, output [7:0] rx_axis_mac_tdata, input [7:0] tx_axis_mac_tdata, input [0:0] tx_axis_mac_tstrb, output [0:0] rx_axis_mac_tstrb, output MdoEn, output Mdo, input Mdi, output Mdc, input [9:0] s_axi_araddr, output s_axi_arready, input s_axi_arvalid, input [9:0] s_axi_awaddr, output s_axi_awready, input s_axi_awvalid, input s_axi_bready, output [1:0] s_axi_bresp, output s_axi_bvalid, output [31:0] s_axi_rdata, input s_axi_rready, output [1:0] s_axi_rresp, output s_axi_rvalid, input [31:0] s_axi_wdata, output s_axi_wready, input s_axi_wvalid ); `IP_MODULE_NAME(efx_mac1gbe) #( .VERSION (16), .TXFIFO_EN (1'b1), .RXFIFO_EN (1'b1), .TXFIFO_DTH (4096), .RXFIFO_DTH (4096), .PHY_INTF_MODE (0), .AXIS_DW (8), .RGMII_RXC_EDGE (1'b1), .RGMII_TXC_DLY (1'b1), .INTER_PACKET_GAP (6'd12), .MTU_FRAME_LENGTH (16'd1518), .MAC_SOURCE_ADDRESS (48'd0), .ENABLE_BROADCAST_FILTERING (1'b1), .LOOPBACK_EN (1'b1), .APBIF (1'b0), .FAMILY ("TITANIUM") ) u_efx_mac1gbe ( .mac_reset ( mac_reset ), .proto_reset ( proto_reset ), .rx_mac_aclk ( rx_mac_aclk ), .tx_mac_aclk ( tx_mac_aclk ), .eth_speed ( eth_speed ), .rx_axis_clk ( rx_axis_clk ), .rx_axis_mac_tuser ( rx_axis_mac_tuser ), .rx_axis_mac_tlast ( rx_axis_mac_tlast ), .rx_axis_mac_tvalid ( rx_axis_mac_tvalid ), .rx_axis_mac_tready ( rx_axis_mac_tready ), .tx_axis_clk ( tx_axis_clk ), .tx_axis_mac_tvalid ( tx_axis_mac_tvalid ), .tx_axis_mac_tlast ( tx_axis_mac_tlast ), .tx_axis_mac_tuser ( tx_axis_mac_tuser ), .tx_axis_mac_tready ( tx_axis_mac_tready ), .rgmii_txd_HI ( rgmii_txd_HI ), .rgmii_txd_LO ( rgmii_txd_LO ), .rgmii_tx_ctl_HI ( rgmii_tx_ctl_HI ), .rgmii_tx_ctl_LO ( rgmii_tx_ctl_LO ), .rgmii_txc_HI ( rgmii_txc_HI ), .rgmii_txc_LO ( rgmii_txc_LO ), .rgmii_rxd_HI ( rgmii_rxd_HI ), .rgmii_rxd_LO ( rgmii_rxd_LO ), .rgmii_rx_ctl_HI ( rgmii_rx_ctl_HI ), .rgmii_rx_ctl_LO ( rgmii_rx_ctl_LO ), .rgmii_rxc ( rgmii_rxc ), .s_axi_aclk ( s_axi_aclk ), .rx_axis_mac_tdata ( rx_axis_mac_tdata ), .tx_axis_mac_tdata ( tx_axis_mac_tdata ), .tx_axis_mac_tstrb ( tx_axis_mac_tstrb ), .rx_axis_mac_tstrb ( rx_axis_mac_tstrb ), .MdoEn ( MdoEn ), .Mdo ( Mdo ), .Mdi ( Mdi ), .Mdc ( Mdc ), .s_axi_araddr ( s_axi_araddr ), .s_axi_arready ( s_axi_arready ), .s_axi_arvalid ( s_axi_arvalid ), .s_axi_awaddr ( s_axi_awaddr ), .s_axi_awready ( s_axi_awready ), .s_axi_awvalid ( s_axi_awvalid ), .s_axi_bready ( s_axi_bready ), .s_axi_bresp ( s_axi_bresp ), .s_axi_bvalid ( s_axi_bvalid ), .s_axi_rdata ( s_axi_rdata ), .s_axi_rready ( s_axi_rready ), .s_axi_rresp ( s_axi_rresp ), .s_axi_rvalid ( s_axi_rvalid ), .s_axi_wdata ( s_axi_wdata ), .s_axi_wready ( s_axi_wready ), .s_axi_wvalid ( s_axi_wvalid ) ); endmodule ///////////////////////////////////////////////////////////////////////////// // _____ // / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. // / / \ // / / .. / simple_dual_port_ram_fifo.v // / / .' / // __/ /.' / Description: // __ \ / EFX FIFO // /_/ /\ \_____/ / // ____/ \_______/ // // ******************************* // Revisions: // // ******************************* module `IP_MODULE_NAME(efx_fifo_top) # ( parameter FAMILY = "TRION", // New Param parameter SYNC_CLK = 0, parameter BYPASS_RESET_SYNC = 0, // New Param parameter SYNC_STAGE = 2, // New Param parameter MODE = "STANDARD", parameter DEPTH = 512, // Reverted (Equivalent to WDATA_DEPTH) parameter DATA_WIDTH = 32, // Reverted (Equivalent to WDATA_WIDTH) parameter PIPELINE_REG = 1, // Reverted (By default is ON) parameter OPTIONAL_FLAGS = 1, // Reverted parameter OUTPUT_REG = 0, parameter PROGRAMMABLE_FULL = "STATIC_DUAL", // Set to "NONE" if not require this feature parameter PROG_FULL_ASSERT = 27, parameter PROG_FULL_NEGATE = 23, parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature parameter PROG_EMPTY_ASSERT = 5, parameter PROG_EMPTY_NEGATE = 7, parameter ALMOST_FLAG = OPTIONAL_FLAGS, parameter HANDSHAKE_FLAG = OPTIONAL_FLAGS, parameter ASYM_WIDTH_RATIO = 4, parameter WADDR_WIDTH = depth2width(DEPTH), parameter RDATA_WIDTH = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH), parameter RD_DEPTH = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH), parameter RADDR_WIDTH = depth2width(RD_DEPTH), parameter ENDIANESS = 0, parameter OVERFLOW_PROTECT = 1, parameter UNDERFLOW_PROTECT = 1, parameter RAM_STYLE = "block_ram" )( input wire a_rst_i, input wire a_wr_rst_i, input wire a_rd_rst_i, input wire clk_i, input wire wr_clk_i, input wire rd_clk_i, input wire wr_en_i, input wire rd_en_i, input wire [DATA_WIDTH-1:0] wdata, output wire almost_full_o, output wire prog_full_o, output wire full_o, output wire overflow_o, output wire wr_ack_o, output wire [WADDR_WIDTH :0] datacount_o, output wire [WADDR_WIDTH :0] wr_datacount_o, output wire empty_o, output wire almost_empty_o, output wire prog_empty_o, output wire underflow_o, output wire rd_valid_o, output wire [RDATA_WIDTH-1:0] rdata, output wire [RADDR_WIDTH :0] rd_datacount_o, output wire rst_busy ); localparam WR_DEPTH = DEPTH; localparam WDATA_WIDTH = DATA_WIDTH; localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 : (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 : (RDATA_WIDTH <= WDATA_WIDTH/8) ? 8 : (RDATA_WIDTH <= WDATA_WIDTH/4) ? 4 : (RDATA_WIDTH <= WDATA_WIDTH/2) ? 2 : (RDATA_WIDTH <= WDATA_WIDTH) ? 1 : (RDATA_WIDTH <= WDATA_WIDTH*2) ? 2 : (RDATA_WIDTH <= WDATA_WIDTH*4) ? 4 : (RDATA_WIDTH <= WDATA_WIDTH*8) ? 8 : (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32; wire wr_rst_int; wire rd_rst_int; wire wr_en_int; wire rd_en_int; wire [WADDR_WIDTH-1:0] waddr; wire [RADDR_WIDTH-1:0] raddr; wire wr_clk_int; wire rd_clk_int; wire [WADDR_WIDTH :0] wr_datacount_int; wire [RADDR_WIDTH :0] rd_datacount_int; generate if (ASYM_WIDTH_RATIO == 4) begin if (SYNC_CLK) begin assign wr_clk_int = clk_i; assign rd_clk_int = clk_i; assign datacount_o = wr_datacount_int; assign wr_datacount_o = {(WADDR_WIDTH+1){1'b0}}; assign rd_datacount_o = {(RADDR_WIDTH+1){1'b0}}; end else begin assign wr_clk_int = wr_clk_i; assign rd_clk_int = rd_clk_i; assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; assign wr_datacount_o = wr_datacount_int; assign rd_datacount_o = rd_datacount_int; end end else begin assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; assign wr_datacount_o = wr_datacount_int; assign rd_datacount_o = rd_datacount_int; if (SYNC_CLK) begin assign wr_clk_int = clk_i; assign rd_clk_int = clk_i; end else begin assign wr_clk_int = wr_clk_i; assign rd_clk_int = rd_clk_i; end end if (!SYNC_CLK) begin //(* async_reg = "true" *) reg [1:0] wr_rst; //(* async_reg = "true" *) reg [1:0] rd_rst; // //always @ (posedge wr_clk_int or posedge a_rst_i) begin // if (a_rst_i) // wr_rst <= 2'b11; // else // wr_rst <= {wr_rst[0],1'b0}; //end // //always @ (posedge rd_clk_int or posedge a_rst_i) begin // if (a_rst_i) // rd_rst <= 2'b11; // else // rd_rst <= {rd_rst[0],1'b0}; //end if (BYPASS_RESET_SYNC) begin assign wr_rst_int = a_wr_rst_i; assign rd_rst_int = a_rd_rst_i; assign rst_busy = 1'b0; end else begin `IP_MODULE_NAME(efx_resetsync) #( .ACTIVE_LOW (0) ) efx_resetsync_wr_rst ( .clk (wr_clk_int), .reset (a_rst_i), .d_o (wr_rst_int) ); `IP_MODULE_NAME(efx_resetsync) #( .ACTIVE_LOW (0) ) efx_resetsync_rd_rst ( .clk (rd_clk_int), .reset (a_rst_i), .d_o (rd_rst_int) ); assign rst_busy = wr_rst_int | rd_rst_int; end end else begin //(* async_reg = "true" *) reg [1:0] a_rst; // //always @ (posedge clk_i or posedge a_rst_i) begin // if (a_rst_i) // a_rst <= 2'b11; // else // a_rst <= {a_rst[0],1'b0}; //end wire a_rst; `IP_MODULE_NAME(efx_resetsync) #( .ACTIVE_LOW (0) ) efx_resetsync_a_rst ( .clk (clk_i), .reset (a_rst_i), .d_o (a_rst) ); if (BYPASS_RESET_SYNC) begin assign wr_rst_int = a_rst_i; assign rd_rst_int = a_rst_i; assign rst_busy = 1'b0; end else begin assign wr_rst_int = a_rst; assign rd_rst_int = a_rst; assign rst_busy = wr_rst_int | rd_rst_int; end end endgenerate `IP_MODULE_NAME(efx_fifo_ram) # ( .FAMILY (FAMILY), .WR_DEPTH (WR_DEPTH), .RD_DEPTH (RD_DEPTH), .WDATA_WIDTH (WDATA_WIDTH), .RDATA_WIDTH (RDATA_WIDTH), .WADDR_WIDTH (WADDR_WIDTH), .RADDR_WIDTH (RADDR_WIDTH), .OUTPUT_REG (OUTPUT_REG), .RAM_MUX_RATIO (RAM_MUX_RATIO), .ENDIANESS (ENDIANESS), .RAM_STYLE (RAM_STYLE) ) xefx_fifo_ram ( .wdata (wdata), .waddr (waddr), .raddr (raddr), .we (wr_en_int), .re (rd_en_int), .wclk (wr_clk_int), .rclk (rd_clk_int), .rdata (rdata) ); `IP_MODULE_NAME(efx_fifo_ctl) # ( .SYNC_CLK (SYNC_CLK), .SYNC_STAGE (SYNC_STAGE), .MODE (MODE), .WR_DEPTH (WR_DEPTH), .WADDR_WIDTH (WADDR_WIDTH), .RADDR_WIDTH (RADDR_WIDTH), .ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), .RAM_MUX_RATIO (RAM_MUX_RATIO), .PIPELINE_REG (PIPELINE_REG), .ALMOST_FLAG (ALMOST_FLAG), .PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), .PROG_FULL_ASSERT (PROG_FULL_ASSERT), .PROG_FULL_NEGATE (PROG_FULL_NEGATE), .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), .PROG_EMPTY_ASSERT (PROG_EMPTY_ASSERT), .PROG_EMPTY_NEGATE (PROG_EMPTY_NEGATE), .OUTPUT_REG (OUTPUT_REG), .HANDSHAKE_FLAG (HANDSHAKE_FLAG), .OVERFLOW_PROTECT (OVERFLOW_PROTECT), .UNDERFLOW_PROTECT (UNDERFLOW_PROTECT) ) xefx_fifo_ctl ( .wr_rst (wr_rst_int), .rd_rst (rd_rst_int), .wclk (wr_clk_int), .rclk (rd_clk_int), .we (wr_en_i), .re (rd_en_i), .wr_full (full_o), .wr_ack (wr_ack_o), .rd_empty (empty_o), .wr_almost_full (almost_full_o), .rd_almost_empty (almost_empty_o), .wr_prog_full (prog_full_o), .rd_prog_empty (prog_empty_o), .wr_en_int (wr_en_int), .rd_en_int (rd_en_int), .waddr (waddr), .raddr (raddr), .wr_datacount (wr_datacount_int), .rd_datacount (rd_datacount_int), .rd_vld (rd_valid_o), .wr_overflow (overflow_o), .rd_underflow (underflow_o) ); function integer depth2width; input [31:0] depth; begin : fnDepth2Width if (depth > 1) begin depth = depth - 1; for (depth2width=0; depth>0; depth2width = depth2width + 1) depth = depth>>1; end else depth2width = 0; end endfunction function integer width2depth; input [31:0] width; begin : fnWidth2Depth width2depth = width**2; end endfunction function integer rdwidthcompute; input [31:0] asym_option; input [31:0] wr_width; begin : RdWidthCompute rdwidthcompute = (asym_option==0)? wr_width/16 : (asym_option==1)? wr_width/8 : (asym_option==2)? wr_width/4 : (asym_option==3)? wr_width/2 : (asym_option==4)? wr_width/1 : (asym_option==5)? wr_width*2 : (asym_option==6)? wr_width*4 : (asym_option==7)? wr_width*8 : (asym_option==8)? wr_width*16 : wr_width/1; end endfunction function integer rddepthcompute; input [31:0] wr_depth; input [31:0] wr_width; input [31:0] rd_width; begin : RdDepthCompute rddepthcompute = (wr_depth * wr_width) / rd_width; end endfunction endmodule ///////////////////////////////////////////////////////////////////////////// // _____ // / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. // / / \ // / / .. / simple_dual_port_ram_fifo.v // / / .' / // __/ /.' / Description: // __ \ / EFX FIFO // /_/ /\ \_____/ / // ____/ \_______/ // // ******************************* // Revisions: // // ******************************* module `IP_MODULE_NAME(efx_fifo_ram) #( parameter FAMILY = "TRION", parameter WR_DEPTH = 512, parameter RD_DEPTH = 512, parameter WDATA_WIDTH = 8, parameter RDATA_WIDTH = 8, parameter WADDR_WIDTH = 9, parameter RADDR_WIDTH = 9, parameter OUTPUT_REG = 1, parameter RAM_MUX_RATIO = 4, parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian parameter RAM_STYLE = "block_ram" ) ( input wire wclk, input wire rclk, input wire we, input wire re, input wire [(WDATA_WIDTH-1):0] wdata, input wire [(WADDR_WIDTH-1):0] waddr, input wire [(RADDR_WIDTH-1):0] raddr, output wire [(RDATA_WIDTH-1):0] rdata ); localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; (* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; reg [RDATA_WIDTH-1:0] r_rdata_1P; reg [RDATA_WIDTH-1:0] r_rdata_2P; wire re_int; generate if (FAMILY == "TRION") begin if (RDATA_WDATA_RATIO == "ONE") begin always @ (posedge wclk) begin if (we) ram[waddr] <= wdata; end always @ (posedge rclk) begin if (re_int) begin r_rdata_1P <= ram[raddr]; end r_rdata_2P <= r_rdata_1P; end end else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin if (ENDIANESS == 0) begin integer i; always @ (posedge wclk) begin for (i=0; i 1) begin wire [1:0] bin_1; assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; if (WIDTH == 2) begin assign bin_o = bin_1; end else begin assign bin_o[WIDTH-1] = bin_1[1]; `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); end end else /* if (WIDTH == 1) */ assign bin_o = gray_i; endgenerate endmodule //////////////////////////////////////////////////////////////////////////////// // Copyright (C) 2013-2020 Efinix Inc. All rights reserved. // // This document contains proprietary information which is // protected by copyright. All rights are reserved. This notice // refers to original work by Efinix, Inc. which may be derivitive // of other work distributed under license of the authors. In the // case of derivative work, nothing in this notice overrides the // original author's license agreement. Where applicable, the // original license agreement is included in it's original // unmodified form immediately below this header. // // WARRANTY DISCLAIMER. // THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND // EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH // RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, // INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF // MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR // PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED // WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. // // LIMITATION OF LIABILITY. // NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY // INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT // MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY // OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, // SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY // CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF // GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR // MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN // THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER // (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE // BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO // NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR // CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT // APPLY TO LICENSEE. // //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////// // _____ // / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. // / / \ // / / .. / pipe_reg.v // / / .' / // __/ /.' / Description: // __ \ / Parallel Pipelining Shift Register // /_/ /\ \_____/ / // ____/ \_______/ // // ******************************* // Revisions: // 1.0 Initial rev // // ******************************* module `IP_MODULE_NAME(efx_fifo_datasync) #( parameter STAGE = 32, parameter WIDTH = 4 ) ( input wire clk_i, input wire [WIDTH-1:0] d_i, output wire [WIDTH-1:0] d_o ); (* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; integer i; always @(posedge clk_i) begin for (i=STAGE-1; i>0; i = i - 1) begin pipe_reg[i] <= pipe_reg[i-1]; end pipe_reg[0] <= d_i; end assign d_o = pipe_reg[STAGE-1]; endmodule //////////////////////////////////////////////////////////////////////////////// // Copyright (C) 2013-2020 Efinix Inc. All rights reserved. // // This document contains proprietary information which is // protected by copyright. All rights are reserved. This notice // refers to original work by Efinix, Inc. which may be derivitive // of other work distributed under license of the authors. In the // case of derivative work, nothing in this notice overrides the // original author's license agreement. Where applicable, the // original license agreement is included in it's original // unmodified form immediately below this header. // // WARRANTY DISCLAIMER. // THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND // EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH // RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, // INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF // MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR // PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED // WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. // // LIMITATION OF LIABILITY. // NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY // INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT // MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY // OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, // SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY // CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF // GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR // MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN // THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER // (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE // BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO // NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR // CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT // APPLY TO LICENSEE. // //////////////////////////////////////////////////////////////////////////////// // synopsys translate_off `timescale 1 ns / 1 ps // synopsys translate_on module `IP_MODULE_NAME(efx_resetsync) #( parameter ASYNC_STAGE = 2, parameter ACTIVE_LOW = 1 ) ( input wire clk, input wire reset, output wire d_o ); generate if (ACTIVE_LOW == 1) begin: active_low `IP_MODULE_NAME(efx_asyncreg) #( .WIDTH (1), .ACTIVE_LOW (1), .RST_VALUE (0) ) efx_resetsync_active_low ( .clk (clk), .reset_n (reset), .d_i (1'b1), .d_o (d_o) ); end else begin: active_high `IP_MODULE_NAME(efx_asyncreg) #( .WIDTH (1), .ACTIVE_LOW (0), .RST_VALUE (1) ) efx_resetsync_active_high ( .clk (clk), .reset_n (reset), .d_i (1'b0), .d_o (d_o) ); end endgenerate endmodule // synopsys translate_off `timescale 1 ns / 1 ps // synopsys translate_on module `IP_MODULE_NAME(efx_asyncreg) #( parameter ASYNC_STAGE = 2, parameter WIDTH = 4, parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset parameter RST_VALUE = 0, parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance ) ( input wire clk, input wire reset_n, input wire [WIDTH-1:0] d_i, output wire [WIDTH-1:0] d_o ); `pragma protect begin_protected `pragma protect version = 1 `pragma protect author = "author-a" , author_info = "author-a-details" `pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" `pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" `pragma protect key_method = "rsa" `pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) `pragma protect key_block IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc /5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 uYJaS5tuGEuFInBHa7oO8g== `pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" `pragma protect key_method = "rsa" `pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) `pragma protect key_block ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w K3OoKmk3zFeArSsql8B4/Q== `pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2" `pragma protect key_method = "rsa" `pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 ) `pragma protect key_block RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l 6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI= `pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" `pragma protect key_method = "rsa" `pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) `pragma protect key_block YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk 1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0 2HflB1HYKxojQCcZU7qUgQ== `pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2" `pragma protect key_method = "rsa" `pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) `pragma protect key_block fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod B2Zpo2FQ//YDRSAaEa9ksQ== `pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2" `pragma protect key_method = "rsa" `pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) `pragma protect key_block TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN ZoPzFCMjGk5ZmMyIlytNCw== `pragma protect data_method = "aes256-cbc" `pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 ) `pragma protect data_block 0d33xo/2RnBYy8BD6jq1J42m9u/75PA0owNvxlnr0TDOq7sF8XT6xouctVD1XQW2 Ylwj0urY+dCJZku0aGRpcvb3H/nTlKVdEZOEl4QqB1gNGz/3mz75A3eudu5zgHEr MaagjyQfDnoIqLWi1r5uTZrlS298IvNcGAJ+xXzpmkFmfG4Tk/5Jf2GPAPVtjREI 01kt8Go4CL1WNxBKcwm0xCiCchxvZ2oEtpERiC+7LUalgTJapIVoLFpvFv98229k egvgF1KHNj0rAKedSG2Xo58TyA4iZXJJDdtgCxiKgu3Rimjno7l+ekApwmvx8n+p yHkRGqetWfRhyE4A5q03RzOeSdA6NbCqijB3NPw/p58brAbA35rrjYpGIZXtZ4mU De3As8VtD64nS2PRuf4/a2lIcDbwMjNTfMpN7iJfVBJ0/48tLHdetx592TLXenkF GvAZ2yxoyBYzKctj4Keo+19Xp1UjVd3fr2MR3A7nmxLRKDA+upDxQ7ql8+pR7Moh 0b53/4Ri3Mkl+7EC1KXJNt2VbkZmcT7OAFIoPpibmcXS2R6DNVrhSKzfc2+TRM9r mwRrJy9/R5RR+WGfw1S57Ho3wBPf4belj+Tfd7yhnwOVRXkTMq5M1BiigrGeeQ3q z/hc1Kg8b/R+g7lnU0pqASnExPQW/DIMfH1RX75U68CAgaBAH22Vcbkoibp8sxyO g18LefEh48UffnbpCKyv7SQ3LAdj+YO+KvvXHj1eW+CH7GA2lC5vt2be5Ah2/13H bCeZ+srG6r7wmafy9MNNh8AgjUfZWwMnuJdCIcHTOfAncCd2B0T1Oza4VIkvnSl5 60V34JXkfrGsNuHxwCF/sRSBbZUSpqig4ZGYHjOHldx2OANZQeUvLES3fwScYY5D 7SpR4ofVxIB/ev/+RXzvC3MNk1N0GT4F1XwokeeQIr/ilRETe/pFvEKttvviZ7uJ uEVblS2v61DMXEgDavkbA0WdhMChPulwDvZtisWT4hCKRxfuBvNBtz0wH/WgRoX3 aipWvPJG3G0xvO0u0EQVNdcxE+LZ7vyGF5HWEwKdQYDyhH+yVDeG+M/b08dU2aq4 sG7dyygyVnzVbk2Lf0nCkGqKkUZUr05Zim0Wcflkhkqy348SOZ3xmEGuYAkzelLV feQ+0ScsscFL5Cq4ETfFrN8GO8M5kkBN2ELs1MQecPRsgMCh0hcvd8IQrJTybQPW aqwp9mgnFvS8AJ1ct+XgrAt8zgVnhaZGS9TKa6OWbr0U+SD5m+/pXjNsZA2dni6b 85/PmQeWeAarE/+EaJn/hlP6y3x3R3ItU8Itf6SB50LZ17LAhIRSIYsa7LBBNWOk ngFHcGBCJnqTJv3hdVqa9cYipZ98XCa8dqrtAM5Rkxwd6H8KxXA+B+PWEz/cQWlb szi9u5ufmyaJp6PWhklroQkPJEorUtF96X763itgtlAMHfkZglkElUD/gPlkXLtl yquUmHqPK5D2pJDq0Q0jromE2yrr9fl3OI+eBehd2YBUivGKeaDFkPx7HbzWp9ok 9bT55H8VKYyF1awcjNND+WcXzm2WfvZHBDUJkRm7dnOQRvcX2RxlPRZSzAA3irVn GFbHXD0RYn/dUR7Vy4kU68P5S5q4bUxD5vmUCN9vDoCivY7WCnlQCHQs3+iFblzP A636C3dNQMSw0pjDisiZB63VczY8bivFh3cO82inNw5r2IZjvMB9XPhc4FHuIpfR F7ptW0TUnO1MSDcZvCnjUfVSnHN22l2FM/P5oI1SbG3W+8YmxBvto8jwpES4ohOQ YSECrvWkLklq68FVTzB7Tvg3JLdSy3TEKBuZE/ot0w/SXusFovOwd4aeiNDAmzwl fQuCYHuJ0UKLaVNVAO4mw91PJODKCk2NYTr0ghOLovOXiMhUYtXZ+wFchXVkQKDI B8BXjM7P+blhoOFA6AhRuCX4gZn0dP6m99qnyBJoxf1/FyfJXuklnPll93amUYUx MzxNNTf7F08tnKQ8pTOk2mfFZnhA2MFn4XQ9FaGvtUrlJI8bvJTWiZFMF0eOJdIw kzYOXEzKBjIdWW4rtTZmQJb7AOrznUpYdgTAPip/DQx6cg1+tZAVwhZPCjCsb5wa em5hMtISQKDc92QrlU5O74OXe7641fzFRcKqy9AzwhZl+tmHk1uvpDkpsYiMa7Rk YrbIjsKQV36PTqYPvxq1EiwYF8PMRf9FG8JZk85EZdM6QEGuehDHqFcZ+SlUb7/e ji6GgjKxcZwaRREGKSOslcscHS6QNuGCF3iInqNCT4V2l7nboWOefMT2f1kmQOdE szTFg563SQ8pu7ok3T3XNqUDi5ulvF+XGHDhcQ2hTkZ+xQ8dHFAWZdgzEGMXF2Lw jU+ZRA2JULfjxOMIU2j9f+aGWmFx2PELMA5K5uOWYUQG2Fn04p1D6u8MEe7fIPeI k7KH8j/Tumj+kG4t/lCrme6VM9u6A2NGddX1yH1NCejfophy3UWJg9wL/dNxzf6t vXdm3rGPdZPWFgSIuGlmT03QZmWGPbs8qvkkUVAL37kMJP2r4L+PI00ZxbX8V5jp GgYN1Rh+NSOwAcUEFCViRhFYC+Gi5eZ6AF6XDSU6qfjGsUKqJ9yrNx0Km6+SjpAK 7Zxblp7vweFVkJ7IESoFeB+vP8JNeoidbBPGEWo+2V08PgfGgjPEAA6pjj8uc0jC SDFZ0sVrzvc66PZ5FxbI4g+VuXPJgyJsnQ/eHhPVTVTP3/oGMRVktNiJrkJYxAW7 Sa/EJMjfXX+rMIWG5ssWLT6WfrojlHduEqJ9hJr24RZy514HHF8SMPRBLD6l1wd5 07U/ChjFdy5qHn5Ce+lanjxnoxgvCsF3lMqoZ7e2bfzXakj7CxahwqRt6yeU0Q+/ a8tvIJgHfdtOPw/r6HnSrzpdWzTx2e6/MEryHZqpMN63Lhakpjw1L7u3FD/rW40b LGajigQ7Ql+cZmP7wYl+uSmTFIS6ZgXOc1ibb7yYxJwpeixPHL1iu5ltvriRiTZ6 DMbbOjNpPuL7ie3AwgmwXwnpnTL6k/Rj2+ma3B7ImODBMkC4SLtTc0ynCcPAFZKA Xh78wUAgt1T5Nm4XR555DBO7zPHX9rZzMLil4/j0RMDwn1gitmP2PSNFWsrXJG8p C46kfpdqoM3Yf6HySlhsith6GW41sMF6imUXwahQQRw240HLW3N876LDe6bjTmgN eIC7y/4NZk7OmpmP8udAEH+UsNfSGtKA8959AoJDr43XsWkOfccNWstu4sTXA5+w pCALypmBMdholEsrW9DgsIgbgf2pcOAC9+mAjld+yyQ+UNdKRbmtRDHTztGmcVvw Szip4YUuTM1tPzReucfm38gVFT7eo1qFQg/FJ4VgeYab7ku5OHuwZQmKyzng/t0U A1lquVENVYQEIotBiOC7jQ1YTkTasGN4xoFgFTyKLFPyk8bl2/anzr1Fx0ieVGCx 2ipzG2JzIQf/FlHXaYrgkWiF817amty+KZp4/dCJtvDXxzOZKnBTVcjHXpqR1Ik+ tdV+k+21tXZxP0rkG0yi4//2c5UiWGb0UegpemqutykLuT9tGjsqMuc5DaDH/8zk wLTVfODT+HqN1/ZLqfq9VoAF5m/ujnPNt3wZcsjsAyBD153rW4Q2yVYMat0sFQN6 XbNAeNBJZlO/aE1PfKBcSDFkJkPqRxlgdiE5B83/w1MP6Z4qwz7LJ8yTYM22xwRo LIYpKq52yYMhJm42YeQxbBRTx0MyubCb+ompEVBF28Eh0vE98UAZj7t1szSweg99 Wq6/4kxR2SQj8rFo2wrZe7ngsDmbIrMk2SinS6WmV4Mj+MBbPlmiuwB6NUV04Id1 9enBBsJIfWt+PZJXyWkOoG/fOVBUxCY+CMCiab0qQ1EVdhggrdI30BgFqcLjfyD6 /h5AqIzMGWrhWnap8WDEh1Ah6K9f2oCESSXO751sV5eK8jgl63FJMIVsnjVejxrl Qa7PCXP3BO6Cnv896NBzAsddPq/AYBLHIC6eX3sTtOxTx52NsmJzoyUSJcAoA/QS leHU1bLA2z+HGfMrkSzsuvXafmqr3B+PHfWdxrYzTxmVhMBPX/FvEU/gfxXGa6kj niZYGue/Rk+zXL65ENgPwxiz0mm7QyQ6eMBMRovm6MGyIl/8obkOPygH+lhc+bgR SNWLmxqjR2YABrKsUgCITQ6GK7VmVR3wOOwbZs+YW/0Yj2yzg7ESjaeqI40/OQFD Ft2IHaURJPk6jl5vRrcCc0J0GCy7CK0BU14n+Nxfl2+CFRe4efoqZry/CmY2+S4M p9OqgjUzHGSIbNRAXHf44nIAUjWYvijzzLSj9A7WY3TpYxgtqU8Wbf7SbWmw8RJV pAYDHGmwHa8fL4Y9xEFF/WqmqWSL3g146i41MKWKY7lchvnWtc6yOgk+0geVFOpe 9BLs4TehFA/SueFC99S0Cxcxc0KMWXOKm0I3bI1CAlLje7wUcdI/pki33iqBLJlL T2vz8ptPqfgAxDW0ZEvEYY/jfB+jCO0MKT7XK/LZNYSuEke3Y3CeuwZ/5IWkDcwy 7BArmDy7Hpw88le9ODL94mS1fUB8jsBaazeiXniZPNZjBkugt/ZAf4XYuoaGVPAM DnRd8GW5eiDHFCEB42lpg9n7Ak8cXsSSlODCHeay2VtcQP1DEgwWdI5XdXE879gI 8lLU9bH2MfsxI2mNWCMv5immaioZJDorIVzyMGvIn3OcgqmhTU1owINUJf+Hm8Q7 JfJq4m6t0J5eoKQH57uSGFkWRZ3dtp5QL3d5bBOMmorXUBzdrLt8wurvNke29bHD UQdmANjayV8drYWAccZdPWyi9jNC/K31BTDI6RCpZdV3Wr5scOZdXWrl961jirm1 g/2MGKxriuH2F4MRIh2vp3uS8PLbj4cHJv+5+LtLgs0lpdEMYAvJKDACRg68tDhY XsF9lhHpcF5+tANOawRtnSvy/rlLn+A3wi7v8tnTZcLkocJ51c+nK5/Ij0YgUrA0 eLrKNlJM78stswPWkvpBlAJ+G3D4Cw6P3XcJWrLyV3u79jf9PRJZmxMU/COGTmgQ PJdXp90O3u2Pjdwhp4VdtBK2d/jTpk59j8xbQBavf5flZ+PzoLpd8NSt6GdPVJ5r uVWvNy14pJXUsn+Tgxj+9Wp3vm5mofWtJAkEgr/Rfp7AVLLShJSd6vsbT7F2+TS/ OMDv0XH92v1G4tqJ0rbxS1TnxX61+1sfjKlfIQdFR9gxLy71Tb705LQHBAw8vmSx X6Uv+HbtPaEqRCF+pdvGsLNI2Seo6INA/mXqNpd6VPhfQHtp3bgV+Hxnlcc9lCiI bCZq6KG4a6sVQHIZ3pZo7PQtoAo22niHvgZFoOVnBv+bu+blmvSV6gxCPoV8rwOe /WD7YikHE7WVSq1SHtTIcbPv+K+1NKqZIiSCS2qDfJLgI7vH4zjIqibDhzGZTeKV Km234SSlJ1OL4WQ5FtsxjednjUIAKqVe1auDiTzAKY28dwUkwGN/XXQ+EjrmxQuL qIAT3WP49EeM+CQCp3D6Vxzm7Picq+RtwtbAXnnSQtvPcaSprODI089a0iR46Pp/ 4DLMUOLS+01HozXF1589YdqYep05No/Fp4eP2RdQxicYxK8d/OcvG7E8F1URVmAa XdZxVa9caM3xYMWDZaiaOo6IZ+YM5VeZ4KxUblS1L1IlOnGOOZ3AiaLsHOh55ryc Ei7EaFpheCmlTJyxUg8TdA== `pragma protect end_protected ///////////////////////////////////////////////////////////////////////////// // _____ // / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. // / / \ // / / .. / simple_dual_port_ram_fifo.v // / / .' / // __/ /.' / Description: // __ \ / EFX FIFO // /_/ /\ \_____/ / // ____/ \_______/ // // ******************************* // Revisions: // // ******************************* module `IP_MODULE_NAME(efx_fifo_ctl) # ( parameter SYNC_CLK = 1, parameter SYNC_STAGE = 2, parameter MODE = "STANDARD", parameter WR_DEPTH = 512, parameter WADDR_WIDTH = 9, parameter RADDR_WIDTH = 9, parameter ASYM_WIDTH_RATIO = 4, parameter RAM_MUX_RATIO = 1, parameter PIPELINE_REG = 1, parameter ALMOST_FLAG = 1, parameter PROGRAMMABLE_FULL = "NONE", parameter PROG_FULL_ASSERT = 0, parameter PROG_FULL_NEGATE = 0, parameter PROGRAMMABLE_EMPTY = "NONE", parameter PROG_EMPTY_ASSERT = 0, parameter PROG_EMPTY_NEGATE = 0, parameter OUTPUT_REG = 0, parameter HANDSHAKE_FLAG = 1, parameter OVERFLOW_PROTECT = 0, parameter UNDERFLOW_PROTECT = 0 )( input wire wr_rst, input wire rd_rst, input wire wclk, input wire rclk, input wire we, input wire re, output wire wr_full, output reg wr_ack, output wire wr_almost_full, output wire rd_empty, output wire rd_almost_empty, output wire wr_prog_full, output wire rd_prog_empty, output wire wr_en_int, output wire rd_en_int, output wire [WADDR_WIDTH-1:0] waddr, output wire [RADDR_WIDTH-1:0] raddr, output wire [WADDR_WIDTH:0] wr_datacount, output wire [RADDR_WIDTH:0] rd_datacount, output wire rd_vld, output reg wr_overflow, output reg rd_underflow ); reg [WADDR_WIDTH:0] waddr_cntr; reg [WADDR_WIDTH:0] waddr_cntr_r; reg [RADDR_WIDTH:0] raddr_cntr; reg rd_valid; wire [WADDR_WIDTH:0] waddr_int; wire [RADDR_WIDTH:0] raddr_int; wire rd_empty_int; wire [WADDR_WIDTH:0] wr_datacount_int; wire [RADDR_WIDTH:0] rd_datacount_int; assign waddr = waddr_cntr[WADDR_WIDTH-1:0]; // NIC wire [RADDR_WIDTH:0] ram_raddr; assign raddr = (MODE == "FWFT") ? ram_raddr[RADDR_WIDTH-1:0] : raddr_cntr[RADDR_WIDTH-1:0]; //assign raddr = raddr_cntr[RADDR_WIDTH-1:0]; //assign wr_en_int = we & ~wr_full; assign wr_en_int = OVERFLOW_PROTECT ? we & ~wr_full : we; assign wr_datacount = wr_datacount_int; assign rd_datacount = ASYM_WIDTH_RATIO == 4 && SYNC_CLK ? wr_datacount_int : rd_datacount_int; generate if (MODE == "FWFT") begin // NIC //assign rd_en_int = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int); //assign rd_empty = rd_empty_fwft; assign rd_en_int = 1'b1; //assign rd_empty = rd_empty_int; //always @ (posedge rclk or posedge rd_rst) begin // if (rd_rst) begin // init_set <= 1'b1; // end // else if (~init_set & rd_empty) begin // init_set <= 1'b1; // end // else if (~rd_empty_int) begin // init_set <= 1'b0; // end // else if (rd_empty) begin // init_set <= 1'b1; // end //end // NIC //always @ (posedge rclk or posedge rd_rst) begin // if (rd_rst) begin // rd_empty_fwft <= 1'b1; // end // else if (rd_en_int) begin // rd_empty_fwft <= 1'b0; // end // else if (re) begin // rd_empty_fwft <= 1'b1; // end //end //if (FAMILY == "TRION") begin if (OUTPUT_REG) begin always @ (posedge rclk or posedge rd_rst) begin if (rd_rst) begin rd_valid <= 1'b0; end else begin rd_valid <= ~rd_empty; end end assign rd_vld = rd_valid; end else begin assign rd_vld = ~rd_empty; end assign rd_empty = rd_empty_int; end else begin assign rd_en_int = UNDERFLOW_PROTECT ? re & ~rd_empty_int : re; assign rd_empty = rd_empty_int; if (OUTPUT_REG) begin reg rd_valid_r; always @ (posedge rclk or posedge rd_rst) begin if (rd_rst) begin rd_valid_r <= 'h0; rd_valid <= 'h0; end else begin {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int}; end end assign rd_vld = rd_valid; end else begin always @ (posedge rclk or posedge rd_rst) begin if (rd_rst) begin rd_valid <= 'h0; end else begin rd_valid <= rd_en_int; end end assign rd_vld = rd_valid; end end if (ALMOST_FLAG) begin assign wr_almost_full = wr_datacount >= WR_DEPTH-1; assign rd_almost_empty = rd_datacount <= 'd1; end else begin assign wr_almost_full = 1'b0; assign rd_almost_empty = 1'b0; end if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin reg wr_prog_full_int; assign wr_prog_full = wr_datacount >= PROG_FULL_ASSERT; always @ (posedge wclk or posedge wr_rst) begin if (wr_rst) begin wr_prog_full_int <= 1'b0; end else begin wr_prog_full_int <= wr_prog_full; end end end else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin reg wr_prog_full_int; assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; always @ (posedge wclk or posedge wr_rst) begin if (wr_rst) begin wr_prog_full_int <= 1'b0; end else begin wr_prog_full_int <= wr_prog_full; end end end else begin assign wr_prog_full = 1'b0; end if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin reg rd_prog_empty_int; assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; always @ (posedge rclk or posedge rd_rst) begin if (rd_rst) begin rd_prog_empty_int <= 1'b1; end else begin rd_prog_empty_int <= rd_prog_empty; end end end else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin reg rd_prog_empty_int; assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); always @ (posedge rclk or posedge rd_rst) begin if (rd_rst) begin rd_prog_empty_int <= 1'b1; end else begin rd_prog_empty_int <= rd_prog_empty; end end end else begin assign rd_prog_empty = 1'b0; end if (HANDSHAKE_FLAG) begin always @ (posedge wclk or posedge wr_rst) begin if (wr_rst) begin wr_ack <= 1'b0; end else begin // NIC //wr_ack <= wr_en_int & ~wr_overflow; wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; end end end if (OVERFLOW_PROTECT) begin always @ (posedge wclk or posedge wr_rst) begin if (wr_rst) begin wr_overflow <= 1'b0; end else if (we && wr_full) begin wr_overflow <= 1'b1; end else begin wr_overflow <= 1'b0; end end end else if (HANDSHAKE_FLAG) begin always @ (posedge wclk or posedge wr_rst) begin if (wr_rst) begin wr_overflow <= 1'b0; end else begin wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; end end end if (UNDERFLOW_PROTECT) begin always @ (posedge rclk or posedge rd_rst) begin if (rd_rst) begin rd_underflow <= 1'b0; end else if (re && rd_empty) begin rd_underflow <= 1'b1; end else begin rd_underflow <= 1'b0; end end end else if (HANDSHAKE_FLAG) begin always @ (posedge rclk or posedge rd_rst) begin if (rd_rst) begin rd_underflow <= 1'b0; end else begin rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; end end end localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; if (ASYM_WIDTH_RATIO < 4) begin assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; end // NIC else if (ASYM_WIDTH_RATIO == 4) begin assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; assign wr_datacount_int = waddr_cntr - raddr_int; assign rd_datacount_int = waddr_int - raddr_cntr; end else begin assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); // NIC //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; end endgenerate always @ (posedge wclk or posedge wr_rst) begin if (wr_rst) begin waddr_cntr <= 'h0; end else if (wr_en_int) begin waddr_cntr <= waddr_cntr + 1'b1; end end always @ (posedge wclk or posedge wr_rst) begin if (wr_rst) begin waddr_cntr_r <= 'h0; end else begin waddr_cntr_r <= waddr_cntr; end end always @ (posedge rclk or posedge rd_rst) begin if (rd_rst) begin raddr_cntr <= 'h0; end // NIC //else if (rd_en_int) begin else begin //raddr_cntr <= raddr_cntr + 1'b1; //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); raddr_cntr <= ram_raddr; end end // NIC assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); generate if (SYNC_CLK) begin : sync_clk if (MODE == "FWFT") begin assign waddr_int = waddr_cntr_r; assign raddr_int = raddr_cntr; end else begin assign waddr_int = waddr_cntr; assign raddr_int = raddr_cntr; end end else begin : async_clk reg [RADDR_WIDTH:0] raddr_cntr_gry_r; reg [WADDR_WIDTH:0] waddr_cntr_gry_r; wire [RADDR_WIDTH:0] raddr_cntr_gry; wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; wire [WADDR_WIDTH:0] waddr_cntr_gry; wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; if (PIPELINE_REG) begin reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; assign waddr_int = waddr_cntr_sync_g2b_r; assign raddr_int = raddr_cntr_sync_g2b_r; always @ (posedge wclk or posedge wr_rst) begin if (wr_rst) begin raddr_cntr_sync_g2b_r <= 'h0; end else begin raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; end end always @ (posedge rclk or posedge rd_rst) begin if (rd_rst) begin waddr_cntr_sync_g2b_r <= 'h0; end else begin waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; end end end else begin assign waddr_int = waddr_cntr_sync_g2b; assign raddr_int = raddr_cntr_sync_g2b; end always @ (posedge rclk or posedge rd_rst) begin if (rd_rst) begin raddr_cntr_gry_r <= 'h0; end else begin raddr_cntr_gry_r <= raddr_cntr_gry; end end `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); always @ (posedge wclk or posedge wr_rst) begin if (wr_rst) begin waddr_cntr_gry_r <= 'h0; end else begin waddr_cntr_gry_r <= waddr_cntr_gry; end end `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); end endgenerate endmodule //////////////////////////////////////////////////////////////////////////// // _____ // / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. // / / \ // / / .. / bin2gray.v // / / .' / // __/ /.' / Description: // __ \ / Binary to Gray Encoding Convertor // /_/ /\ \_____/ / // ____/ \_______/ // // ******************************* // Revisions: // 1.0 Initial rev // // ******************************* `resetall `timescale 1ns/1ps module `IP_MODULE_NAME(efx_fifo_bin2gray) #(parameter WIDTH=5) (// outputs output wire [WIDTH-1:0] gray_o, // input input [WIDTH-1:0] bin_i ); //--------------------------------------------------------------------- // Function : bit_xor // Description: reduction xor function bit_xor ( input [31:0] nex_bit, input [31:0] curr_bit, input [WIDTH-1:0] xor_in); begin : fn_bit_xor bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; end endfunction // Convert Binary to Gray, bit by bit generate begin genvar bit_idx; for(bit_idx=0; bit_idx