// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
//  https://github.com/SystemRDL/PeakRDL-regblock

package verilog6502_io_regs_pkg;

    localparam VERILOG6502_IO_REGS_DATA_WIDTH = 32;
    localparam VERILOG6502_IO_REGS_MIN_ADDR_WIDTH = 12;
    localparam VERILOG6502_IO_REGS_SIZE = 'h1000;

    typedef struct {
        logic value;
    } verilog6502_io_regs__core_ctrl__reset__out_t;

    typedef struct {
        verilog6502_io_regs__core_ctrl__reset__out_t reset;
    } verilog6502_io_regs__core_ctrl__out_t;

    typedef struct {
        logic [15:0] value;
    } verilog6502_io_regs__reset_brq__reset__out_t;

    typedef struct {
        logic [15:0] value;
    } verilog6502_io_regs__reset_brq__brk__out_t;

    typedef struct {
        verilog6502_io_regs__reset_brq__reset__out_t reset;
        verilog6502_io_regs__reset_brq__brk__out_t brk;
    } verilog6502_io_regs__reset_brq__out_t;

    typedef struct {
        verilog6502_io_regs__core_ctrl__out_t core_ctrl;
        verilog6502_io_regs__reset_brq__out_t reset_brq;
    } verilog6502_io_regs__out_t;
endpackage