{
    "name": "EfxDMA",
    "efinix_ddr": false,
    "with_sg_bus": false,
    "with_ddr_write_queue": false,
    "with_ddr_read_queue": false,
    "ctrl": {
        "asynchronous": true
    },
    "buffer": {
        "bank_count": 2,
        "bank_width": 64,
        "bank_words": 512
    },
    "read": {
        "address_width": 32,
        "data_width_external": 128,
        "data_width_internal": 128
    },
    "write": {
        "address_width": 32,
        "data_width_external": 128,
        "data_width_internal": 128
    },
    "channels": {
        "c0": {
            "progress_probe": true,
            "direct_ctrl_capable": true,
            "linked_list_capable": true,
            "memory_to_memory": false,
            "inputs": [
                "dat0_i"
            ],
            "half_completion_interrupt": false,
            "self_restart_capable": false,
            "bytes_per_burst": 1024,
            "buffer_address": 0,
            "buffer_size": 4096
        },
        "c1": {
            "progress_probe": true,
            "direct_ctrl_capable": true,
            "linked_list_capable": true,
            "memory_to_memory": false,
            "outputs": [
                "dat1_o"
            ],
            "half_completion_interrupt": false,
            "self_restart_capable": false,
            "bytes_per_burst": 1024,
            "buffer_address": 4096,
            "buffer_size": 4096
        }
    },
    "inputs": {
        "dat0_i": {
            "data_width": 8,
            "tid_width": 0,
            "tdest_width": 4,
            "asynchronous": true
        }
    },
    "outputs": {
        "dat1_o": {
            "data_width": 8,
            "tid_width": 0,
            "tdest_width": 4,
            "asynchronous": true
        }
    }
}