From c9269b2fb853e4db9cbd4aa62c9817b0d7cf603d Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Mon, 11 Apr 2022 16:13:38 -0500
Subject: [PATCH] Fix some warnings
Adds some missing cases, length specifiers.
---
hw/fpga/sd_controller.sv | 13 ++++++++++---
hw/fpga/super6502.sv | 2 +-
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/hw/fpga/sd_controller.sv b/hw/fpga/sd_controller.sv
index b166f18..b8f864f 100644
--- a/hw/fpga/sd_controller.sv
+++ b/hw/fpga/sd_controller.sv
@@ -84,12 +84,12 @@ always_ff @(posedge clk) begin
if (addr < 4'h4) begin
arg[8 * addr +: 8] <= data;
end else if (addr == 4'h4) begin
- cmd <= data;
+ cmd <= data[6:0];
end
end
if (cs & addr == 4'h5 && sd_clk) begin
- data_count <= data_count + 1;
+ data_count <= data_count + 9'b1;
end
if (state.macro == RXCMD) begin
@@ -183,7 +183,7 @@ always_comb begin
if (state.d_bit_count == 8'h0) begin
next_state.count = state.count + 9'b1;
end
- next_state.d_bit_count = state.d_bit_count - 8'h1;
+ next_state.d_bit_count = state.d_bit_count - 3'h1;
end else begin
next_data_flag = '1;
next_state.macro = RXDCRC;
@@ -199,6 +199,11 @@ always_comb begin
next_state.count = '0;
end
end
+
+ default: begin
+ next_state.macro = IDLE;
+ next_state.count = '0;
+ end
endcase
end
@@ -220,6 +225,8 @@ always_comb begin
end
RXCMD:;
+
+ default:;
endcase
end
diff --git a/hw/fpga/super6502.sv b/hw/fpga/super6502.sv
index 54bbdfe..6cb2502 100644
--- a/hw/fpga/super6502.sv
+++ b/hw/fpga/super6502.sv
@@ -29,7 +29,7 @@ module super6502(
input [7:0] SW,
output logic [7:0] LED,
- inout logic [15: 0] ARDUINO_IO,
+ inout logic [15: 2] ARDUINO_IO,
///////// SDRAM /////////
output DRAM_CLK,
--
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