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Updated date
Remove fpga RAM
!9
· created
Mar 21, 2022
by
Byron Lathi
Merged
updated
Mar 21, 2022
Add board-io, replace sevenseg in sw
!8
· created
Mar 18, 2022
by
Byron Lathi
Merged
updated
Mar 18, 2022
Add SDRAM controller (controller)
!7
· created
Mar 17, 2022
by
Byron Lathi
Merged
updated
Mar 17, 2022
Add conio
!6
· created
Mar 15, 2022
by
Byron Lathi
Merged
updated
Mar 15, 2022
Add UART Receive logic
!5
· created
Mar 14, 2022
by
Byron Lathi
Merged
updated
Mar 14, 2022
Add interrupt status register
!4
· created
Mar 14, 2022
by
Byron Lathi
Merged
updated
Mar 14, 2022
Add UART TX Module
!3
· created
Mar 14, 2022
by
Byron Lathi
Merged
updated
Mar 14, 2022
Add full seven segment display driver
!2
· created
Mar 13, 2022
by
Byron Lathi
Merged
updated
Mar 13, 2022
Get the FPGA part working
!1
· created
Mar 13, 2022
by
Byron Lathi
Merged
updated
Mar 13, 2022
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