diff --git a/.gitmodules b/.gitmodules
index 591c898..0a0a7e3 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +1,6 @@
 [submodule "sw/cc65"]
 	path = sw/cc65
-	url = https://git.byronlathi.com/bslathi19/cc65
\ No newline at end of file
+	url = https://git.byronlathi.com/bslathi19/cc65
+[submodule "hw/efinix_fpga/simulation/src/verilog-6502"]
+	path = hw/efinix_fpga/simulation/src/verilog-6502
+	url = https://git.byronlathi.com/bslathi19/verilog-6502
diff --git a/hw/efinix_fpga/simulation/src/verilog-6502 b/hw/efinix_fpga/simulation/src/verilog-6502
new file mode 160000
index 0000000..a5f605d
--- /dev/null
+++ b/hw/efinix_fpga/simulation/src/verilog-6502
@@ -0,0 +1 @@
+Subproject commit a5f605d00d22095532cc32aa7a481465b1bdca17