From 00173f4e890ced956711ccc7991a2a3df55a0d7f Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sat, 23 Sep 2023 09:59:39 -0700 Subject: [PATCH] Add submodule back --- .gitmodules | 5 ++++- hw/efinix_fpga/simulation/src/verilog-6502 | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) create mode 160000 hw/efinix_fpga/simulation/src/verilog-6502 diff --git a/.gitmodules b/.gitmodules index 591c898..0a0a7e3 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,6 @@ [submodule "sw/cc65"] path = sw/cc65 - url = https://git.byronlathi.com/bslathi19/cc65 \ No newline at end of file + url = https://git.byronlathi.com/bslathi19/cc65 +[submodule "hw/efinix_fpga/simulation/src/verilog-6502"] + path = hw/efinix_fpga/simulation/src/verilog-6502 + url = https://git.byronlathi.com/bslathi19/verilog-6502 diff --git a/hw/efinix_fpga/simulation/src/verilog-6502 b/hw/efinix_fpga/simulation/src/verilog-6502 new file mode 160000 index 0000000..a5f605d --- /dev/null +++ b/hw/efinix_fpga/simulation/src/verilog-6502 @@ -0,0 +1 @@ +Subproject commit a5f605d00d22095532cc32aa7a481465b1bdca17