From 00e4c551c15cf74ac33d46eb532e807dd7c0d216 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Sat, 18 Nov 2023 21:11:35 -0800
Subject: [PATCH] Make full sim manual

---
 .gitlab-ci.yml                           | 31 +-----------------------
 hw/efinix_fpga/simulation/src/sim_top.sv |  2 +-
 2 files changed, 2 insertions(+), 31 deletions(-)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 8b8c641..c8b39e5 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -47,22 +47,6 @@ build fpga:       # This job runs in the build stage, which runs first.
     - cd hw/efinix_fpga
     - make
 
-build sim:
-  tags:
-   - iverilog
-   - linux
-  stage: build
-  artifacts:
-    paths:
-      - hw/efinix_fpga/simulation/sim_top
-      - hw/efinix_fpga/simulation/init_hex.mem
-  script:  
-    - source init_env.sh
-    - cd hw/efinix_fpga/simulation
-    - make sim_top
-  dependencies:
-    - build toolchain
-
 build bios:
   tags:
     - linux
@@ -85,22 +69,9 @@ build kernel:
   dependencies:
     - build toolchain
 
-run sim:
-  tags:
-    - linux
-    - iverilog
-  stage: simulate
-  artifacts:
-    paths:
-      - hw/efinix_fpga/simulation/sim_top.vcd
-  script:
-    - source init_env.sh
-    - cd hw/efinix_fpga/simulation
-    - make sim
-  dependencies:
-    - build toolchain
 
 full sim:
+  when: manual
   tags:
     - linux
     - iverilog
diff --git a/hw/efinix_fpga/simulation/src/sim_top.sv b/hw/efinix_fpga/simulation/src/sim_top.sv
index 5433cc6..855ac03 100644
--- a/hw/efinix_fpga/simulation/src/sim_top.sv
+++ b/hw/efinix_fpga/simulation/src/sim_top.sv
@@ -53,7 +53,7 @@ initial begin
     button_reset <= '0;
     repeat(10) @(r_clk_cpu);
     button_reset <= '1;
-    repeat(1250000) @(posedge r_clk_cpu);
+    repeat(1500000) @(posedge r_clk_cpu);
     $finish();
 end