Add basic sim

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Byron Lathi

2024-03-03 17:06:10 -08:00

parent ab9da189d1

commit 01b1ecbcac

9 changed files with 152 additions and 1 deletions

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hw/super6502_fpga/src/sim/sub/verilog-6502 Submodule

Submodule hw/super6502_fpga/src/sim/sub/verilog-6502 added at aaf4c084ef