From 02ac7d5213a6563b5b0107e1748a53a6995a5fcc Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Thu, 7 Sep 2023 23:41:17 -0700 Subject: [PATCH] Add diagram, throw some code together --- doc/top.drawio | 107 ++++++++++++++++++++++++++++ hw/efinix_fpga/addr_decode.sv | 22 +++--- hw/efinix_fpga/control_registers.sv | 19 +++++ hw/efinix_fpga/super6502.sv | 54 ++++++++------ hw/efinix_fpga/super6502.xml | 2 +- 5 files changed, 171 insertions(+), 33 deletions(-) create mode 100644 doc/top.drawio create mode 100644 hw/efinix_fpga/control_registers.sv diff --git a/doc/top.drawio b/doc/top.drawio new file mode 100644 index 0000000..24e3027 --- /dev/null +++ b/doc/top.drawio @@ -0,0 +1,107 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hw/efinix_fpga/addr_decode.sv b/hw/efinix_fpga/addr_decode.sv index ce48f8c..2d7ed54 100644 --- a/hw/efinix_fpga/addr_decode.sv +++ b/hw/efinix_fpga/addr_decode.sv @@ -1,6 +1,8 @@ module addr_decode ( - input [15:0] i_addr, + input [24:0] i_addr, + + input config_reg_sel, output o_rom_cs, output o_leds_cs, @@ -9,18 +11,16 @@ module addr_decode output o_divider_cs, output o_uart_cs, output o_spi_cs, - output o_mapper_cs, output o_sdram_cs ); -assign o_rom_cs = i_addr >= 16'hf000 && i_addr <= 16'hffff; -assign o_timer_cs = i_addr >= 16'heff8 && i_addr <= 16'heffb; -assign o_multiplier_cs = i_addr >= 16'heff0 && i_addr <= 16'heff7; -assign o_divider_cs = i_addr >= 16'hefe8 && i_addr <= 16'hefef; -assign o_uart_cs = i_addr >= 16'hefe6 && i_addr <= 16'hefe7; -assign o_spi_cs = i_addr >= 16'hefd8 && i_addr <= 16'hefdb; -assign o_mapper_cs = i_addr >= 16'hefb7 && i_addr <= 16'hefd7; -assign o_leds_cs = i_addr == 16'hefff; -assign o_sdram_cs = i_addr < 16'he000; +assign o_rom_cs = (i_addr >= 25'hf000 && i_addr <= 25'hffff) && ~config_reg_sel; +assign o_timer_cs = (i_addr >= 25'heff8 && i_addr <= 25'heffb) && ~config_reg_sel; +assign o_multiplier_cs = (i_addr >= 25'heff0 && i_addr <= 25'heff7) && ~config_reg_sel; +assign o_divider_cs = (i_addr >= 25'hefe8 && i_addr <= 25'hefef) && ~config_reg_sel; +assign o_uart_cs = (i_addr >= 25'hefe6 && i_addr <= 25'hefe7) && ~config_reg_sel; +assign o_spi_cs = (i_addr >= 25'hefd8 && i_addr <= 25'hefdb) && ~config_reg_sel; +assign o_leds_cs = (i_addr == 25'hefff) && ~config_reg_sel; +assign o_sdram_cs = (i_addr < 25'he000 || i_addr >= 25'h10000) && ~config_reg_sel; endmodule \ No newline at end of file diff --git a/hw/efinix_fpga/control_registers.sv b/hw/efinix_fpga/control_registers.sv new file mode 100644 index 0000000..b5aaf2f --- /dev/null +++ b/hw/efinix_fpga/control_registers.sv @@ -0,0 +1,19 @@ +module control_registers #( + parameter START = 16'h0a00, + parameter SIZE = 16'h0600 +)( + input i_clk, + input i_rst, + + input logic o_selected, + input i_rwb, + input [15:0] i_addr, + input [7:0] i_data, + output logic [7:0] o_data +); + +logic [7:0] regs [SIZE]; + +assign o_selected = (addr >= START && addr > START + SIZE); + +endmodule diff --git a/hw/efinix_fpga/super6502.sv b/hw/efinix_fpga/super6502.sv index c00146f..6fa9b79 100644 --- a/hw/efinix_fpga/super6502.sv +++ b/hw/efinix_fpga/super6502.sv @@ -1,4 +1,8 @@ module super6502 +#( + parameter CONTROL_REG_START = 16'h0a00, + parameter CONTROL_REG_SIZE = 16'h0600 +) ( input logic i_sysclk, // Controller Clock (100MHz) input logic i_sdrclk, // t_su and t_wd clock (200MHz) @@ -71,6 +75,14 @@ always @(posedge clk_2) begin end end +logic w_control_reg_cs; + + +// 0a00 - 0xffff +assign w_control_reg_cs = (cpu_addr >= CONTROL_REG_START && cpu_addr < CONTROL_REG_START + CONTROL_REG_SIZE); + +// The w_control_reg_cs is redundant but whatever +assign o_mapper_cs = (cpu_addr >= 16'h0a00 && cpu_addr <= 25'h0a20) && w_control_reg_cs; logic w_rom_cs; logic w_leds_cs; @@ -83,7 +95,8 @@ logic w_mapper_cs; logic w_spi_cs; addr_decode u_addr_decode( - .i_addr(cpu_addr), + .i_addr(w_sdram_addr), + .config_reg_sel(w_control_reg_cs), .o_rom_cs(w_rom_cs), .o_leds_cs(w_leds_cs), .o_timer_cs(w_timer_cs), @@ -91,7 +104,6 @@ addr_decode u_addr_decode( .o_divider_cs(w_divider_cs), .o_uart_cs(w_uart_cs), .o_spi_cs(w_spi_cs), - .o_mapper_cs(w_mapper_cs), .o_sdram_cs(w_sdram_cs) ); @@ -128,8 +140,21 @@ always_comb begin cpu_data_out = 'x; end +logic [24:0] w_sdram_addr; + +mapper u_mapper( + .clk(clk_2), + .rst(~cpu_resb), + .cpu_addr(cpu_addr), + .sdram_addr(w_sdram_addr), + .cs(w_mapper_cs), + .rwb(cpu_rwb), + .i_data(cpu_data_in), + .o_data(w_mapper_data_out) +); + rom #(.DATA_WIDTH(8), .ADDR_WIDTH(12)) u_rom( - .addr(cpu_addr[11:0]), + .addr(w_sdram_addr[11:0]), .clk(clk_2), .data(w_rom_data_out) ); @@ -152,7 +177,7 @@ timer u_timer( .o_data(w_timer_data_out), .cs(w_timer_cs), .rwb(cpu_rwb), - .addr(cpu_addr[1:0]), + .addr(w_sdram_addr[1:0]), .irqb(w_timer_irqb) ); @@ -163,7 +188,7 @@ multiplier u_multiplier( .o_data(w_multiplier_data_out), .cs(w_multiplier_cs), .rwb(cpu_rwb), - .addr(cpu_addr[2:0]) + .addr(w_sdram_addr[2:0]) ); divider_wrapper u_divider( @@ -174,7 +199,7 @@ divider_wrapper u_divider( .o_data(w_divider_data_out), .cs(w_divider_cs), .rwb(cpu_rwb), - .addr(cpu_addr[2:0]) + .addr(w_sdram_addr[2:0]) ); logic w_uart_irqb; @@ -187,7 +212,7 @@ uart_wrapper u_uart( .o_data(w_uart_data_out), .cs(w_uart_cs), .rwb(cpu_rwb), - .addr(cpu_addr[0]), + .addr(w_sdram_addr[0]), .rx_i(uart_rx), .tx_o(uart_tx), .irqb(w_uart_irqb) @@ -198,7 +223,7 @@ spi_controller spi_controller( .i_rst(~cpu_resb), .i_cs(w_spi_cs), .i_rwb(cpu_rwb), - .i_addr(cpu_addr[1:0]), + .i_addr(w_sdram_addr[1:0]), .i_data(cpu_data_in), .o_data(w_spi_data_out), @@ -208,19 +233,6 @@ spi_controller spi_controller( .i_spi_miso(spi_miso) ); -logic [24:0] w_sdram_addr; - -mapper u_mapper( - .clk(clk_2), - .rst(~cpu_resb), - .cpu_addr(cpu_addr), - .sdram_addr(w_sdram_addr), - .cs(w_mapper_cs), - .rwb(cpu_rwb), - .i_data(cpu_data_in), - .o_data(w_mapper_data_out) -); - sdram_adapter u_sdram_adapter( .i_cpuclk(clk_2), diff --git a/hw/efinix_fpga/super6502.xml b/hw/efinix_fpga/super6502.xml index 5df8475..665473d 100644 --- a/hw/efinix_fpga/super6502.xml +++ b/hw/efinix_fpga/super6502.xml @@ -1,5 +1,5 @@ - +