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Add basic project with cpu, ram and rom

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This commit is contained in:
Byron Lathi
2024-03-02 22:46:48 -08:00
parent 0a0394ae33
commit 0752220b0e
15 changed files with 1019 additions and 0 deletions
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hw/super6502_fpga/sources.list Normal file
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src/rtl/super_6502_fpga.sv
src/sub/axi_crossbar/src/rtl/axi_crossbar.sv
src/sub/axi_crossbar/src/rtl/axi_master.sv
src/sub/axi_crossbar/src/rtl/axi_slave.sv
src/sub/axi_crossbar/src/rtl/rr_scheduler.sv
src/sub/axi_crossbar/src/rtl/slave_addr_decoder.sv
src/sub/cpu_wrapper/cpu_wrapper.sv
src/sub/rtl-common/src/rtl/async_fifo.sv
src/sub/rtl-common/src/rtl/axi4_lite_ram.sv
src/sub/rtl-common/src/rtl/axi4_lite_rom.sv
src/sub/rtl-common/src/rtl/ff_cdc.sv
src/sub/rtl-common/src/rtl/shallow_async_fifo.sv
src/sub/rtl-common/src/rtl/sync_fifo.sv