Add sd card cs

hw/fpga/addr_decode.sv

@@ -6,8 +6,9 @@ module addr_decode(
     output logic uart_cs,
     output logic irq_cs,
     output logic board_io_cs,
-	output logic mm_cs1,
-	output logic mm_cs2
+    output logic mm_cs1,
+    output logic mm_cs2,
+    output logic sd_cs
 );
 
 assign rom_cs = addr >= 24'h008000 && addr < 24'h010000;
@@ -17,6 +18,7 @@ assign hex_cs = addr >= 24'h007ff0 && addr < 24'h007ff4;
 assign uart_cs = addr >= 24'h007ff4 && addr < 24'h007ff6;
 assign board_io_cs = addr == 24'h007ff6;
 assign mm_cs2 = addr == 24'h007ff7;
+assign sd_cs = addr >= 24'h007ff8 && addr < 24'h007ffd;
 assign irq_cs  = addr == 24'h007fff;
 
 endmodule

hw/fpga/hvl/cs_testbench.sv

@@ -13,8 +13,9 @@ logic uart_cs;
 logic irq_cs;
 logic mm_cs2;
 logic mm_cs1;
+logic sd_cs;
 
-int cs_count = sdram_cs + rom_cs + hex_cs + uart_cs + board_io_cs + mm_cs2 + mm_cs1;
+int cs_count = sdram_cs + rom_cs + hex_cs + uart_cs + board_io_cs + mm_cs2 + mm_cs1 + sd_cs;
 
 addr_decode dut(.*);
 
@@ -56,6 +57,11 @@ initial begin : TEST_VECTORS
             else
                 $error("Bad CS! addr=%4x should have mm_cs1!", addr);
         end
+        if (i >= 24'h007ff8 && i < 24'h007ffd) begin
+            assert(sd_cs == '1)
+            else
+            $error("Bad CS! addr=%4x should have sd_cs!", addr);
+        end
         if (i == 16'h7fff) begin
             assert(irq_cs == '1)
             else