diff --git a/hw/efinix_fpga/.lock b/hw/efinix_fpga/.lock
new file mode 100644
index 0000000..00f90ec
--- /dev/null
+++ b/hw/efinix_fpga/.lock
@@ -0,0 +1 @@
+18538
diff --git a/hw/efinix_fpga/HexDriver.sv b/hw/efinix_fpga/HexDriver.sv
deleted file mode 100644
index 0cce9d4..0000000
--- a/hw/efinix_fpga/HexDriver.sv
+++ /dev/null
@@ -1,27 +0,0 @@
-module HexDriver (input  [3:0]  In0,
-                  output logic [6:0]  Out0);
-	
-	always_comb
-	begin
-		unique case (In0)
-	 	   4'b0000   : Out0 = 7'b1000000; // '0'
-	 	   4'b0001   : Out0 = 7'b1111001; // '1'
-		   4'b0010   : Out0 = 7'b0100100; // '2'
-	 	   4'b0011   : Out0 = 7'b0110000; // '3'
-	 	   4'b0100   : Out0 = 7'b0011001; // '4'
-		   4'b0101   : Out0 = 7'b0010010; // '5'
-	 	   4'b0110   : Out0 = 7'b0000010; // '6'
-	 	   4'b0111   : Out0 = 7'b1111000; // '7'
-	 	   4'b1000   : Out0 = 7'b0000000; // '8'
-		   4'b1001   : Out0 = 7'b0010000; // '9'
-	 	   4'b1010   : Out0 = 7'b0001000; // 'A'
-	 	   4'b1011   : Out0 = 7'b0000011; // 'b'
-	 	   4'b1100   : Out0 = 7'b1000110; // 'C'
-		   4'b1101   : Out0 = 7'b0100001; // 'd'
-	 	   4'b1110   : Out0 = 7'b0000110; // 'E'
-	 	   4'b1111   : Out0 = 7'b0001110; // 'F'
-	 	   default   : Out0 = 7'bX;
-	  	 endcase
-	end
-
-endmodule
diff --git a/hw/efinix_fpga/SevenSeg.sv b/hw/efinix_fpga/SevenSeg.sv
deleted file mode 100644
index ff2179e..0000000
--- a/hw/efinix_fpga/SevenSeg.sv
+++ /dev/null
@@ -1,42 +0,0 @@
-module SevenSeg(
-    input clk,
-    input rst,
-    
-    input rw,
-
-    input [7:0] data,
-    input cs,
-    input [1:0] addr,
-    
-    output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5
-);
-
-logic [7:0] _data [3:0];
-
-always_ff @(posedge clk) begin
-    if (rst)
-        _data = '{default:'0};
-    if (~rw & cs)
-        _data[addr] <= data;
-end
-
-
-logic [3:0] hex_4[5:0];
-
-assign {hex_4[5], hex_4[4]} = _data[2];
-assign {hex_4[3], hex_4[2]} = _data[1];
-assign {hex_4[1], hex_4[0]} = _data[0];
-
-logic [6:0] _HEX0, _HEX1, _HEX2, _HEX3, _HEX4, _HEX5;
-
-HexDriver hex_drivers[5:0] (hex_4, {_HEX5, _HEX4, _HEX3, _HEX2, _HEX1, _HEX0});
-
-assign HEX0 = _HEX0 | {7{~_data[3][0]}};
-assign HEX1 = _HEX1 | {7{~_data[3][1]}};
-assign HEX2 = _HEX2 | {7{~_data[3][2]}};
-assign HEX3 = _HEX3 | {7{~_data[3][3]}};
-assign HEX4 = _HEX4 | {7{~_data[3][4]}};
-assign HEX5 = _HEX5 | {7{~_data[3][5]}};
-
-
-endmodule
diff --git a/hw/efinix_fpga/addr_decode.sv b/hw/efinix_fpga/addr_decode.sv
deleted file mode 100644
index bcfde85..0000000
--- a/hw/efinix_fpga/addr_decode.sv
+++ /dev/null
@@ -1,24 +0,0 @@
-module addr_decode(
-    input logic [23:0] addr,
-    output logic sdram_cs,
-    output logic rom_cs,
-    output logic hex_cs,
-    output logic uart_cs,
-    output logic irq_cs,
-    output logic board_io_cs,
-    output logic mm_cs1,
-    output logic mm_cs2,
-    output logic sd_cs
-);
-
-assign rom_cs = addr >= 24'h008000 && addr < 24'h010000;
-assign sdram_cs = addr < 24'h007fe0 || addr >= 24'h010000;
-assign mm_cs1 = addr >= 24'h007fe0 && addr < 24'h007ff0;
-assign hex_cs = addr >= 24'h007ff0 && addr < 24'h007ff4;
-assign uart_cs = addr >= 24'h007ff4 && addr < 24'h007ff6;
-assign board_io_cs = addr == 24'h007ff6;
-assign mm_cs2 = addr == 24'h007ff7;
-assign sd_cs = addr >= 24'h007ff8 && addr < 24'h007ffe;
-assign irq_cs  = addr == 24'h007fff;
-
-endmodule
diff --git a/hw/efinix_fpga/board_io.sv b/hw/efinix_fpga/board_io.sv
deleted file mode 100644
index d83d1b3..0000000
--- a/hw/efinix_fpga/board_io.sv
+++ /dev/null
@@ -1,27 +0,0 @@
-module board_io(
-    input clk,
-    input rst,
-    
-    input rw,
-
-    input [7:0] data_in,
-    input cs,
-    input [1:0] addr,
-    
-    output logic [7:0] data_out,
-
-    output logic [7:0] led,
-    input [7:0] sw
-);
-
-assign data_out = sw;
-
-
-always_ff @(posedge clk) begin
-    if (rst)
-        led = '0;
-    if (~rw & cs)
-        led <= data_in;
-end
-
-endmodule
diff --git a/hw/efinix_fpga/crc7.sv b/hw/efinix_fpga/crc7.sv
deleted file mode 100644
index e009826..0000000
--- a/hw/efinix_fpga/crc7.sv
+++ /dev/null
@@ -1,106 +0,0 @@
-module crc7 #(parameter POLYNOMIAL = 8'h89)
-(
-    input clk,
-    input rst,
-
-    input load,
-    input [39:0] data_in,
-
-    output logic [6:0] crc_out,
-    output logic valid
-);
-
-logic [46:0] data;
-logic [46:0] next_data;
-logic [46:0] polyshift;
-
-typedef enum bit [1:0] {IDLE, WORKING, VALID} macro_t;
-struct packed {
-    macro_t macro;
-    logic [5:0] count;
-} state, next_state;
-
-always_ff @(posedge clk) begin
-    if (rst) begin
-        polyshift <= {POLYNOMIAL, 39'b0};    //start all the way at the left
-        data <= '0;
-        state.macro <= IDLE;
-        state.count <= '0;
-    end else begin
-        if (load) begin
-            data <= {data_in, 7'b0};
-        end else begin
-            data <= next_data;
-        end
-        state <= next_state;
-
-        if (state.macro == WORKING) begin
-            polyshift <= polyshift >> 1;
-        end
-
-        if (state.macro == VALID) begin
-            polyshift <= {POLYNOMIAL, 39'b0};
-        end
-    end
-end
-
-always_comb begin
-    next_state = state;
-
-    case (state.macro)
-        IDLE: begin
-            if (load) begin
-                next_state.macro = WORKING;
-                next_state.count = '0;
-            end
-        end
-
-        WORKING: begin
-            if (state.count < 39) begin
-                next_state.count = state.count + 6'b1;
-            end else begin
-                next_state.macro = VALID;
-                next_state.count = '0;
-            end
-        end
-
-        VALID: begin            // Same as IDLE, but IDLE is just for reset.
-            if (load) begin
-                next_state.macro = WORKING;
-                next_state.count = '0;
-            end
-        end
-
-        default:;
-    endcase
-end
-
-always_comb begin
-    valid = 0;
-    next_data = '0;
-    crc_out = '0;
-
-    case (state.macro)
-        IDLE: begin
-            valid = 0;
-        end
-
-        WORKING: begin
-            if (data[6'd46 - state.count]) begin
-                next_data = data ^ polyshift;
-            end else begin
-                next_data = data;
-            end
-        end
-
-        VALID: begin
-            valid =  ~load;
-            next_data = data;
-            crc_out = data[6:0];
-        end
-
-        default:;
-    endcase
-end
-
-endmodule
diff --git a/hw/efinix_fpga/debug_profile.wizard.json b/hw/efinix_fpga/debug_profile.wizard.json
new file mode 100644
index 0000000..e09d118
--- /dev/null
+++ b/hw/efinix_fpga/debug_profile.wizard.json
@@ -0,0 +1,297 @@
+{
+    "debug_cores": [
+        {
+            "name": "la0",
+            "type": "la",
+            "uuid": "d64eaf74d37c4eb79fa6271eeceeb4bc",
+            "trigin_en": false,
+            "trigout_en": false,
+            "auto_inserted": true,
+            "capture_control": false,
+            "data_depth": 32,
+            "input_pipeline": 1,
+            "probes": [
+                {
+                    "name": "cpu_resb",
+                    "width": 1,
+                    "probe_type": 1
+                },
+                {
+                    "name": "cpu_addr",
+                    "width": 16,
+                    "probe_type": 1
+                },
+                {
+                    "name": "button_reset",
+                    "width": 1,
+                    "probe_type": 1
+                }
+            ]
+        }
+    ],
+    "connections": [
+        {
+            "command": "add_ports",
+            "id": 1,
+            "args": {
+                "netlist": "super6502",
+                "ports": [
+                    {
+                        "name": "jtag_inst1_CAPTURE",
+                        "dir": "in",
+                        "width": 1
+                    },
+                    {
+                        "name": "jtag_inst1_DRCK",
+                        "dir": "in",
+                        "width": 1
+                    },
+                    {
+                        "name": "jtag_inst1_RESET",
+                        "dir": "in",
+                        "width": 1
+                    },
+                    {
+                        "name": "jtag_inst1_RUNTEST",
+                        "dir": "in",
+                        "width": 1
+                    },
+                    {
+                        "name": "jtag_inst1_SEL",
+                        "dir": "in",
+                        "width": 1
+                    },
+                    {
+                        "name": "jtag_inst1_SHIFT",
+                        "dir": "in",
+                        "width": 1
+                    },
+                    {
+                        "name": "jtag_inst1_TCK",
+                        "dir": "in",
+                        "width": 1
+                    },
+                    {
+                        "name": "jtag_inst1_TDI",
+                        "dir": "in",
+                        "width": 1
+                    },
+                    {
+                        "name": "jtag_inst1_TMS",
+                        "dir": "in",
+                        "width": 1
+                    },
+                    {
+                        "name": "jtag_inst1_UPDATE",
+                        "dir": "in",
+                        "width": 1
+                    },
+                    {
+                        "name": "jtag_inst1_TDO",
+                        "dir": "out",
+                        "width": 1
+                    }
+                ]
+            }
+        },
+        {
+            "command": "instantiate",
+            "netlist": "edb_top",
+            "id": 2,
+            "instance": "edb_top_inst"
+        },
+        {
+            "command": "connect",
+            "id": 3,
+            "args": {
+                "instance": "edb_top_inst",
+                "ports": [
+                    {
+                        "name": "bscan_CAPTURE",
+                        "net": "jtag_inst1_CAPTURE"
+                    },
+                    {
+                        "name": "bscan_DRCK",
+                        "net": "jtag_inst1_DRCK"
+                    },
+                    {
+                        "name": "bscan_RESET",
+                        "net": "jtag_inst1_RESET"
+                    },
+                    {
+                        "name": "bscan_RUNTEST",
+                        "net": "jtag_inst1_RUNTEST"
+                    },
+                    {
+                        "name": "bscan_SEL",
+                        "net": "jtag_inst1_SEL"
+                    },
+                    {
+                        "name": "bscan_SHIFT",
+                        "net": "jtag_inst1_SHIFT"
+                    },
+                    {
+                        "name": "bscan_TCK",
+                        "net": "jtag_inst1_TCK"
+                    },
+                    {
+                        "name": "bscan_TDI",
+                        "net": "jtag_inst1_TDI"
+                    },
+                    {
+                        "name": "bscan_TMS",
+                        "net": "jtag_inst1_TMS"
+                    },
+                    {
+                        "name": "bscan_UPDATE",
+                        "net": "jtag_inst1_UPDATE"
+                    },
+                    {
+                        "name": "bscan_TDO",
+                        "net": "jtag_inst1_TDO"
+                    },
+                    {
+                        "name": "la0_clk",
+                        "net": "clk_2",
+                        "path": []
+                    },
+                    {
+                        "name": "la0_probe0",
+                        "net": "cpu_resb",
+                        "path": []
+                    },
+                    {
+                        "name": "la0_probe1[0]",
+                        "net": "cpu_addr[0]",
+                        "path": []
+                    },
+                    {
+                        "name": "la0_probe1[1]",
+                        "net": "cpu_addr[1]",
+                        "path": []
+                    },
+                    {
+                        "name": "la0_probe1[2]",
+                        "net": "cpu_addr[2]",
+                        "path": []
+                    },
+                    {
+                        "name": "la0_probe1[3]",
+                        "net": "cpu_addr[3]",
+                        "path": []
+                    },
+                    {
+                        "name": "la0_probe1[4]",
+                        "net": "cpu_addr[4]",
+                        "path": []
+                    },
+                    {
+                        "name": "la0_probe1[5]",
+                        "net": "cpu_addr[5]",
+                        "path": []
+                    },
+                    {
+                        "name": "la0_probe1[6]",
+                        "net": "cpu_addr[6]",
+                        "path": []
+                    },
+                    {
+                        "name": "la0_probe1[7]",
+                        "net": "cpu_addr[7]",
+                        "path": []
+                    },
+                    {
+                        "name": "la0_probe1[8]",
+                        "net": "cpu_addr[8]",
+                        "path": []
+                    },
+                    {
+                        "name": "la0_probe1[9]",
+                        "net": "cpu_addr[9]",
+                        "path": []
+                    },
+                    {
+                        "name": "la0_probe1[10]",
+                        "net": "cpu_addr[10]",
+                        "path": []
+                    },
+                    {
+                        "name": "la0_probe1[11]",
+                        "net": "cpu_addr[11]",
+                        "path": []
+                    },
+                    {
+                        "name": "la0_probe1[12]",
+                        "net": "cpu_addr[12]",
+                        "path": []
+                    },
+                    {
+                        "name": "la0_probe1[13]",
+                        "net": "cpu_addr[13]",
+                        "path": []
+                    },
+                    {
+                        "name": "la0_probe1[14]",
+                        "net": "cpu_addr[14]",
+                        "path": []
+                    },
+                    {
+                        "name": "la0_probe1[15]",
+                        "net": "cpu_addr[15]",
+                        "path": []
+                    },
+                    {
+                        "name": "la0_probe2",
+                        "net": "button_reset",
+                        "path": []
+                    }
+                ]
+            }
+        }
+    ],
+    "vdbs": [
+        {
+            "file": "debug_top.post.vdb",
+            "instance": "edb_top_inst"
+        }
+    ],
+    "session": {
+        "wizard": {
+            "data_depth": 32,
+            "capture_control": false,
+            "selected_nets": [
+                {
+                    "name": "cpu_resb",
+                    "width": 1,
+                    "clk_domain": "clk_2",
+                    "selected_probe_type": "DATA AND TRIGGER",
+                    "child": [],
+                    "path": []
+                },
+                {
+                    "name": "cpu_addr",
+                    "width": 16,
+                    "clk_domain": "clk_2",
+                    "selected_probe_type": "DATA AND TRIGGER",
+                    "child": [],
+                    "path": [],
+                    "net_idx_left": 15,
+                    "net_idx_right": 0
+                },
+                {
+                    "name": "button_reset",
+                    "width": 1,
+                    "clk_domain": "clk_2",
+                    "selected_probe_type": "DATA AND TRIGGER",
+                    "child": [],
+                    "path": []
+                }
+            ],
+            "top_module": "super6502",
+            "db_checksum": "ba5fce12098a2c03e7bae2e9a172d1842464edfca8e284870b3519e987537970",
+            "src": "elaborate",
+            "jtag_user": "USER1",
+            "input_pipeline": 1
+        }
+    }
+}
\ No newline at end of file
diff --git a/hw/efinix_fpga/ip/sdram/sdram.v b/hw/efinix_fpga/ip/sdram/sdram.v
deleted file mode 100644
index 57af1cf..0000000
--- a/hw/efinix_fpga/ip/sdram/sdram.v
+++ /dev/null
@@ -1,4236 +0,0 @@
-// =============================================================================
-// Generated by efx_ipmgr
-// Version: 2021.2.323
-// IP Version: 1.5
-// =============================================================================
-
-////////////////////////////////////////////////////////////////////////////////
-// Copyright (C) 2013-2021 Efinix Inc. All rights reserved.              
-//
-// This   document  contains  proprietary information  which   is        
-// protected by  copyright. All rights  are reserved.  This notice       
-// refers to original work by Efinix, Inc. which may be derivitive       
-// of other work distributed under license of the authors.  In the       
-// case of derivative work, nothing in this notice overrides the         
-// original author's license agreement.  Where applicable, the           
-// original license agreement is included in it's original               
-// unmodified form immediately below this header.                        
-//                                                                       
-// WARRANTY DISCLAIMER.                                                  
-//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
-//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
-//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
-//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
-//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
-//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
-//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
-//                                                                       
-// LIMITATION OF LIABILITY.                                              
-//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
-//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
-//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
-//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
-//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
-//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
-//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
-//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
-//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
-//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
-//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
-//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
-//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
-//     APPLY TO LICENSEE.                                                
-//
-////////////////////////////////////////////////////////////////////////////////
-
-`define IP_UUID _2fa8b2362acf42f5841c22a03034c8fb
-`define IP_NAME_CONCAT(a,b) a``b
-`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID)
-module sdram (
-input i_we,
-input i_sysclk,
-input i_arst,
-input i_sdrclk,
-input i_tACclk,
-input i_pll_locked,
-input i_re,
-input i_last,
-output o_dbg_tRTW_done,
-output o_dbg_ref_req,
-output o_dbg_wr_ack,
-output o_dbg_rd_ack,
-output [1:0] o_dbg_n_CS,
-output [1:0] o_dbg_n_RAS,
-output [1:0] o_dbg_n_CAS,
-output [1:0] o_dbg_n_WE,
-output [3:0] o_dbg_BA,
-output [25:0] o_dbg_ADDR,
-output [31:0] o_dbg_DATA_out,
-output [31:0] o_dbg_DATA_in,
-input [23:0] i_addr,
-input [31:0] i_din,
-output [31:0] o_dout,
-output [3:0] o_sdr_state,
-output o_sdr_init_done,
-output o_wr_ack,
-output o_rd_ack,
-output o_ref_req,
-output o_rd_valid,
-output [1:0] o_sdr_CKE,
-output [1:0] o_sdr_n_CS,
-output [1:0] o_sdr_n_RAS,
-output [1:0] o_sdr_n_CAS,
-output [1:0] o_sdr_n_WE,
-output [3:0] o_sdr_BA,
-output [25:0] o_sdr_ADDR,
-output [31:0] o_sdr_DATA,
-output [31:0] o_sdr_DATA_oe,
-input [31:0] i_sdr_DATA,
-output [3:0] o_sdr_DQM,
-output [5:0] o_dbg_dly_cnt_b,
-output o_dbg_tRCD_done
-);
-`IP_MODULE_NAME(efx_sdram_controller) #(
-.fSYS_MHz (100),
-.fCK_MHz  (200),
-.tIORT_u (2),
-.BL (1),
-.DDIO_TYPE ("SOFT"),
-.DQ_WIDTH  (8),
-.DQ_GROUP (2),
-.BA_WIDTH  (2),
-.ROW_WIDTH  (13),
-.COL_WIDTH  (9),
-.tPWRUP  (200000),
-.tRAS  (44),
-.tRC  (66),
-.tRCD (20),
-.tREF  (64000000),
-.tWR (2),
-.tMRD (2),
-.tRFC  (66),
-.tRAS_MAX (120000),
-.DATA_RATE (2),
-.AXI_ARADDR_WIDTH (24),
-.SDRAM_MODE ("Native"),
-.AXI_BUSER_WIDTH (2),
-.AXI_BID_WIDTH (4),
-.AXI_AWUSER_WIDTH (2),
-.AXI_AWID_WIDTH (4),
-.AXI_AWADDR_WIDTH (24),
-.AXI_RDATA_WIDTH (32),
-.AXI_WUSER_WIDTH (2),
-.AXI_WDATA_WIDTH (32),
-.AXI_RUSER_WIDTH (3),
-.AXI_ARUSER_WIDTH (3),
-.AXI_ARID_WIDTH (4),
-.tRP (20),
-.CL (3)
-) u_efx_sdram_controller(
-.i_we ( i_we ),
-.i_sysclk ( i_sysclk ),
-.i_arst ( i_arst ),
-.i_sdrclk ( i_sdrclk ),
-.i_tACclk ( i_tACclk ),
-.i_pll_locked ( i_pll_locked ),
-.i_re ( i_re ),
-.i_last ( i_last ),
-.o_dbg_tRTW_done ( o_dbg_tRTW_done ),
-.o_dbg_ref_req ( o_dbg_ref_req ),
-.o_dbg_wr_ack ( o_dbg_wr_ack ),
-.o_dbg_rd_ack ( o_dbg_rd_ack ),
-.o_dbg_n_CS ( o_dbg_n_CS ),
-.o_dbg_n_RAS ( o_dbg_n_RAS ),
-.o_dbg_n_CAS ( o_dbg_n_CAS ),
-.o_dbg_n_WE ( o_dbg_n_WE ),
-.o_dbg_BA ( o_dbg_BA ),
-.o_dbg_ADDR ( o_dbg_ADDR ),
-.o_dbg_DATA_out ( o_dbg_DATA_out ),
-.o_dbg_DATA_in ( o_dbg_DATA_in ),
-.i_addr ( i_addr ),
-.i_din ( i_din ),
-.o_dout ( o_dout ),
-.o_sdr_state ( o_sdr_state ),
-.o_sdr_init_done ( o_sdr_init_done ),
-.o_wr_ack ( o_wr_ack ),
-.o_rd_ack ( o_rd_ack ),
-.o_ref_req ( o_ref_req ),
-.o_rd_valid ( o_rd_valid ),
-.o_sdr_CKE ( o_sdr_CKE ),
-.o_sdr_n_CS ( o_sdr_n_CS ),
-.o_sdr_n_RAS ( o_sdr_n_RAS ),
-.o_sdr_n_CAS ( o_sdr_n_CAS ),
-.o_sdr_n_WE ( o_sdr_n_WE ),
-.o_sdr_BA ( o_sdr_BA ),
-.o_sdr_ADDR ( o_sdr_ADDR ),
-.o_sdr_DATA ( o_sdr_DATA ),
-.o_sdr_DATA_oe ( o_sdr_DATA_oe ),
-.i_sdr_DATA ( i_sdr_DATA ),
-.o_sdr_DQM ( o_sdr_DQM ),
-.o_dbg_dly_cnt_b ( o_dbg_dly_cnt_b ),
-.o_dbg_tRCD_done ( o_dbg_tRCD_done )
-);
-
-endmodule
-
-/////////////////////////////////////////////////////////////////////////////
-//           _____       
-//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
-//         / /       \   
-//        / /  ..    /   `IP_MODULE_NAME(axi4_sdram_controller).v
-//       / / .'     /    
-//    __/ /.'      /     Description:
-//   __   \       /      sdram contronller top with AXI4 interface
-//  /_/ /\ \_____/ /     
-// ____/  \_______/     
-//
-// *******************************
-// Revisions:
-// 1.0 Initial rev
-//  Support ONLY AXI 32-bit data to SDRAM total DQ x16 half rate
-//
-// *******************************
-/////////////////////////////////////////////////////////////////////////////
-// AxSIZE
-`define	BYTES_TX_1		3'b000
-`define	BYTES_TX_2		3'b001
-`define	BYTES_TX_4		3'b010
-`define	BYTES_TX_8		3'b011
-`define	BYTES_TX_16		3'b100
-`define	BYTES_TX_32		3'b101
-`define	BYTES_TX_64		3'b110
-`define	BYTES_TX_128	3'b111
-`define	OKAY	2'b00
-
-module `IP_MODULE_NAME(axi4_sdram_controller)
-#(
-	parameter	AXI_AWADDR_WIDTH	= 32,
-	parameter	AXI_WDATA_WIDTH		= 32,
-	parameter	AXI_ARADDR_WIDTH	= 32,
-	parameter	AXI_RDATA_WIDTH		= 32,
-                                    
-	parameter	fSYS_MHz		= 100,
-	parameter	fCK_MHz			= 100,
-	parameter	DDIO_TYPE		= "SOFT",
-	parameter	tPWRUP			= 100,			// 100 us
-	parameter	tRAS			= 44,			// 44 ns
-	parameter	tRAS_MAX		= 120,		// 120 us
-	parameter	tRC			    = 66,			// 66 ns
-	parameter	tRCD			= 20,			// 20 ns
-	parameter	tREF			= 64,			// 64 ms
-	parameter	tRFC			= 66,			// 66 ns
-	parameter	tRP			    = 20,			// 20 ns
-	parameter	tWR			    = 2,			// 1 CK+7.5 ns
-	parameter	tMRD			= 2,			// 2 CK
-	parameter	CL			    = 3,			// 3 CK
-	parameter	BL			    = 1,
-    parameter   DATA_RATE       = 1,
-    parameter   tIORT_u		    = 2,
-	parameter	BA_WIDTH		= 2,
-	parameter	ROW_WIDTH		= 10,
-	parameter	COL_WIDTH		= 10,
-	parameter	DQ_WIDTH		= 8,	// x4, x8
-	parameter	DQ_GROUP		= 8,
-	//			x4	x8	x16	x32
-	// DQ_WIDTH	4	8	8	8
-	// DQ_GROUP	1	1	2	4
-	// AXI not support DQ_WIDTH = 4 DQ_GROUP = 1
-	
-	//----- parameter not configurable by user----
-	parameter	AXI_AWID_WIDTH		= 4,
-	parameter	AXI_AWUSER_WIDTH	= 2,
-	parameter	AXI_WUSER_WIDTH		= 2,
-	parameter	AXI_BID_WIDTH		= 4,
-	parameter	AXI_BUSER_WIDTH		= 2,
-	parameter	AXI_ARID_WIDTH		= 4,
-	parameter	AXI_ARUSER_WIDTH	= 2,
-	parameter	AXI_RUSER_WIDTH		= 2
-)
-(
-	input	i_aresetn,
-	input	i_sysclk,
-	input	i_sdrclk,
-	input	i_tACclk,
-	input	i_pll_locked,
-	output	o_pll_reset,
-	
-	// Compulsory
-	output	o_AXI4_AWREADY,
-	input	[AXI_AWADDR_WIDTH-1:0]i_AXI4_AWADDR,
-	input	[2:0]i_AXI4_AWPROT,	// Dummy
-	input	i_AXI4_AWVALID,
-	
-	output	o_AXI4_WREADY,
-	input	[AXI_WDATA_WIDTH-1:0]i_AXI4_WDATA,
-	input	i_AXI4_WLAST,
-	input	i_AXI4_WVALID,
-	
-	output	o_AXI4_BVALID,
-	input	i_AXI4_BREADY,
-	
-	output	o_AXI4_ARREADY,
-	input	[AXI_ARADDR_WIDTH-1:0]i_AXI4_ARADDR,
-	input	[2:0]i_AXI4_ARPROT,		// Dummy
-	input	i_AXI4_ARVALID,
-	
-	input	i_AXI4_RREADY,
-	output	[AXI_RDATA_WIDTH-1:0]o_AXI4_RDATA,
-	output	o_AXI4_RLAST,
-	output	o_AXI4_RVALID,
-	
-	// Optional
-	input	[AXI_AWID_WIDTH-1:0]i_AXI4_AWID,
-	input	[3:0]i_AXI4_AWREGION,					// Dummy
-	input	[7:0]i_AXI4_AWLEN,						// Dummy
-	input	[2:0]i_AXI4_AWSIZE,
-	input	[1:0]i_AXI4_AWBURST,					// Dummy
-	input	i_AXI4_AWLOCK,							// Dummy
-	input	[3:0]i_AXI4_AWCACHE,					// Dummy
-	input	[3:0]i_AXI4_AWQOS,						// Dummy
-	input	[AXI_AWUSER_WIDTH-1:0]i_AXI4_AWUSER,	// Dummy
-	
-	input	[AXI_WDATA_WIDTH/8-1:0]i_AXI4_WSTRB,	// Dummy
-	input	[AXI_WUSER_WIDTH-1:0]i_AXI4_WUSER,		// Dummy
-	
-	output	[AXI_BID_WIDTH-1:0]o_AXI4_BID,
-	output	[1:0]o_AXI4_BRESP,						// Dummy
-	output	[AXI_BUSER_WIDTH-1:0]o_AXI4_BUSER,		// Dummy
-	
-	input	[AXI_ARID_WIDTH-1:0]i_AXI4_ARID,
-	input	[3:0]i_AXI4_ARREGION,					// Dummy
-	input	[7:0]i_AXI4_ARLEN,
-	input	[2:0]i_AXI4_ARSIZE,
-	input	[1:0]i_AXI4_ARBURST,					// Dummy
-	input	i_AXI4_ARLOCK,							// Dummy
-	input	[3:0]i_AXI4_ARCACHE,					// Dummy
-	input	[3:0]i_AXI4_ARQOS,						// Dummy
-	input	[AXI_ARUSER_WIDTH-1:0]i_AXI4_ARUSER,	// Dummy
-	
-	output	[AXI_ARID_WIDTH-1:0]o_AXI4_RID,
-	output	[1:0]o_AXI4_RRESP,						// Dummy
-	output	[AXI_RUSER_WIDTH-1:0]o_AXI4_RUSER,		// Dummy
-	
-	output	[DATA_RATE							-1:0]	o_sdr_CKE,
-	output	[DATA_RATE							-1:0]	o_sdr_n_CS,
-	output	[DATA_RATE							-1:0]	o_sdr_n_RAS,
-	output	[DATA_RATE							-1:0]	o_sdr_n_CAS,
-	output	[DATA_RATE							-1:0]	o_sdr_n_WE,
-	output	[DATA_RATE	*BA_WIDTH				-1:0]	o_sdr_BA,
-	output	[DATA_RATE	*ROW_WIDTH				-1:0]	o_sdr_ADDR,
-	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_sdr_DATA,
-	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_sdr_DATA_oe,
-	input	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	i_sdr_DATA,
-	output	[DATA_RATE	*DQ_GROUP				-1:0]	o_sdr_DQM,
-	
-	// Debug port
-	output	[3:0]o_sdr_state,
-	output	o_dbg_we,
-	output	o_dbg_re,
-	output	o_dbg_last,
-	output	[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:0]o_dbg_addr,
-	output	[AXI_WDATA_WIDTH-1:0]o_dbg_din,
-	output	o_dbg_wr_ack,
-	output	o_dbg_rd_ack,
-	output	o_sdr_rd_valid,
-	output	o_dbg_ref_req,
-	output	[DATA_RATE*DQ_GROUP*DQ_WIDTH+AXI_ARID_WIDTH:0]o_sdr_dout,
-	output	[1:0]o_axi4_wrstate,
-	output	o_dbg_axi4_wlast,
-	output	[1:0]o_axi4_rastate,
-	output	[1:0]o_axi4_rdstate,
-	output	o_axi4_nwr,
-	output	o_re_lock,
-	output	[6:0]o_shift_cnt,
-	output	[7:0]o_axi4_arlen,
-	output	o_fifo_wr,
-	output	o_fifo_full,
-	output	o_fifo_empty,
-	output	o_dbg_fifo_we,
-	output	[7:0]o_dbg_fifo_waddr,
-	output	o_dbg_fifo_re,
-	output	[7:0]o_dbg_fifo_raddr,
-	
-	output	[DATA_RATE							-1:0]	o_dbg_n_CS,
-	output	[DATA_RATE							-1:0]	o_dbg_n_RAS,
-	output	[DATA_RATE							-1:0]	o_dbg_n_CAS,
-	output	[DATA_RATE							-1:0]	o_dbg_n_WE,
-	output	[DATA_RATE	*BA_WIDTH				-1:0]	o_dbg_BA,
-	output	[DATA_RATE	*ROW_WIDTH				-1:0]	o_dbg_ADDR,
-	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_dbg_DATA_out,
-	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_dbg_DATA_in
-);
-
-function integer log2;
-	input	integer	val;
-	integer	i;
-	begin
-		log2 = 0;
-		for (i=0; 2**i<val; i=i+1)
-			log2 = i+1;
-	end
-endfunction
-
-initial
-begin
-	$display("DQ_GROUP: %d\n", DQ_GROUP);
-	$display("DQ_WIDTH: %d\n", DQ_WIDTH);
-end
-
-`ifdef RTL_SIM
-        localparam   tIORT		    = (DATA_RATE == 2 && CL == 2) ? 1 : 0;
-`else
-        localparam   tIORT		    = tIORT_u;
-`endif
-
-localparam	s_INIT		= 2'b00;
-localparam	s_IDLE		= 2'b01;
-localparam	s_WR_SHIFT	= 2'b10;
-localparam	s_WR_RESP	= 2'b11;
-localparam	s_RD_ADDR	= 2'b10;
-localparam	s_RD_INIT	= 2'b10;
-localparam	s_RD_SHIFT	= 2'b11;
-localparam	SDR_DWIDTH	= DQ_GROUP*DQ_WIDTH;
-localparam	SDR_BWIDTH	= DATA_RATE*SDR_DWIDTH;
-localparam	DIN_WIDTH	= AXI_WDATA_WIDTH;
-localparam	DOUT_WIDTH	= AXI_RDATA_WIDTH;
-
-wire    r_AXI4_WREADY_c;
-
-reg		[1:0]r_axi4_wrstate_1P;
-reg		[1:0]r_axi4_rastate_1P;
-reg		[1:0]r_axi4_rdstate_1P;
-reg		r_axi4_nwr_1P;
-reg		r_AXI4_AWREADY_1P;
-reg		r_AXI4_AWLEN_1P;
-//reg		r_AXI4_WREADY_c;
-reg		r_AXI4_WLAST_1P;
-reg		r_AXI4_BVALID_1P;
-reg		r_AXI4_ARREADY_1P;
-reg		[7:0]r_AXI4_ARLEN_1P;
-reg		r_AXI4_RVALID_1P;
-reg		[AXI_BID_WIDTH-1:0]r_AXI4_BID_1P;
-reg		[AXI_ARID_WIDTH-1:0]r_AXI4_RID_1P;
-
-reg		r_we_1P;
-reg		r_re_1P;
-reg		r_last_1P;
-reg		[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:0]r_addr_1P;
-reg		[DIN_WIDTH-1:0]r_din_1P;
-reg		[6:0]r_size_1P;
-reg		[6:0]r_shift_cnt_1P;
-reg		[6:0]r_addr_cnt_1P;
-reg		[7:0]r_arlen_cnt_1P;
-
-reg		r_wr_ack_1P;
-reg		r_AXI4_WREADY_2P;
-reg		r_re_lock_1P;
-
-reg		[AXI_ARID_WIDTH-1:0]r_AXI4_RID[0:CL+tIORT+1];
-reg		[DOUT_WIDTH+AXI_ARID_WIDTH:0]r_dout_1P;
-reg		r_fifo_wr_1P;
-reg		r_fifo_rd_1P;
-
-wire	[SDR_BWIDTH-1:0]w_dout;
-wire	w_sdr_init_done;
-wire	w_wr_ack;
-wire	w_rd_ack;
-wire	w_ref_req;
-wire	w_rd_valid;
-
-wire	[AXI_RDATA_WIDTH+AXI_ARID_WIDTH:0]w_fifo_dout;
-wire	w_afull;
-wire	w_empty;
-
-wire	[1:0]c_addr_increment;
-assign	c_addr_increment	= DATA_RATE;
-assign	o_pll_reset			= i_aresetn;
-
-`IP_MODULE_NAME(sdram_controller)
-#(
-	.fSYS_MHz			(fSYS_MHz),
-	.fCK_MHz			(fCK_MHz),
-	.REF_LATENCY		(4),
-	.tIORT_u		    (tIORT_u),
-	.DDIO_TYPE			(DDIO_TYPE),
-	.tPWRUP				(tPWRUP),	// 100 us
-	.tRAS				(tRAS),		// 44 ns
-	.tRAS_MAX			(tRAS_MAX),	// 120 us
-	.tRC				(tRC),		// 66 ns
-	.tRCD				(tRCD),		// 20 ns
-	.tREF				(tREF),		// 64 ms
-	.tRFC				(tRFC),		// 66 ns
-	.tRP				(tRP),		// 20 ns
-	.tWR				(tWR),		// 1 CK+7.5 ns
-	.tMRD				(tMRD),		// 2 CK
-	.CL					(CL),		// 3 CK
-	.BL					(BL),
-	.BA_WIDTH			(BA_WIDTH),
-	.ROW_WIDTH			(ROW_WIDTH),
-	.COL_WIDTH			(COL_WIDTH),
-    .DATA_RATE          (DATA_RATE),
-	.DQ_WIDTH			(DQ_WIDTH),	// x4, x8
-	.DQ_GROUP			(DQ_GROUP)
-	//			x4	x8	x16	x32
-	// DQ_WIDTH	4	8	8	8
-	// DQ_GROUP	1	1	2	4
-)
-inst_sdram_controller
-(
-	.i_arst			(~i_aresetn),
-	.i_sysclk		(i_sysclk),
-	.i_sdrclk		(i_sdrclk),
-	.i_tACclk		(i_tACclk),
-	.i_pll_locked	(i_pll_locked),
-	
-	.i_we			(r_we_1P),
-	.i_re			(r_re_1P),
-	.i_last			(r_last_1P),
-	.i_addr			(r_addr_1P),
-	.i_din			(r_din_1P[SDR_BWIDTH-1:0]),
-	.o_dout			(w_dout),
-	.o_sdr_state	(o_sdr_state),	// debug use
-	.o_sdr_init_done(w_sdr_init_done),
-	.o_wr_ack		(w_wr_ack),
-	.o_rd_ack		(w_rd_ack),
-	.o_ref_req		(w_ref_req),
-	.o_rd_valid		(w_rd_valid),
-	
-	.o_sdr_CKE		(o_sdr_CKE),
-	.o_sdr_n_CS		(o_sdr_n_CS),
-	.o_sdr_n_RAS	(o_sdr_n_RAS),
-	.o_sdr_n_CAS	(o_sdr_n_CAS),
-	.o_sdr_n_WE		(o_sdr_n_WE),
-	.o_sdr_BA		(o_sdr_BA),
-	.o_sdr_ADDR		(o_sdr_ADDR),
-	.o_sdr_DATA		(o_sdr_DATA),
-	.o_sdr_DATA_oe	(o_sdr_DATA_oe),
-	.i_sdr_DATA		(i_sdr_DATA),
-	.o_sdr_DQM		(o_sdr_DQM),
-	
-	.o_dbg_ref_req	(o_dbg_ref_req),
-	.o_dbg_n_CS		(o_dbg_n_CS),
-	.o_dbg_n_RAS	(o_dbg_n_RAS),
-	.o_dbg_n_CAS	(o_dbg_n_CAS),
-	.o_dbg_n_WE		(o_dbg_n_WE),
-	.o_dbg_BA		(o_dbg_BA),
-	.o_dbg_ADDR		(o_dbg_ADDR),
-	.o_dbg_DATA_out	(o_dbg_DATA_out),
-	.o_dbg_DATA_in	(o_dbg_DATA_in),
-	.o_dbg_wr_ack	(o_dbg_wr_ack),
-	.o_dbg_rd_ack	(o_dbg_rd_ack)
-);
-
-`IP_MODULE_NAME(dual_clock_fifo_wrapper)
-#(
-	.DATA_WIDTH(AXI_RDATA_WIDTH+AXI_ARID_WIDTH+1),
-	.ADDR_WIDTH(8),
-	.LATENCY(2),
-	.FIFO_MODE("STD_FIFO"),
-	.RAM_INIT_FILE(""),
-	.COMPATIBILITY("E"),
-	.OUTPUT_REG("FALSE"),
-	.CHECK_FULL("TRUE"),
-	.CHECK_EMPTY("TRUE"),
-	.AFULL_THRESHOLD(2**8-1),
-	.AEMPTY_THRESHOLD(1)
-)
-inst_dual_clock_fifo_wrapper
-(
-	.i_arst(~i_aresetn),
-	
-	.i_wclk(i_sysclk),
-	.i_we(r_fifo_wr_1P),
-	.i_wdata(r_dout_1P),
-	
-	.i_rclk(i_sysclk),
-	.i_re(r_fifo_rd_1P || (r_AXI4_RVALID_1P && i_AXI4_RREADY)),
-	
-	.o_full(w_afull),
-	.o_empty(w_empty),
-	.o_rdata(w_fifo_dout),
-
-	.o_afull(),
-	.o_wcnt(),
-	.o_aempty(),
-	.o_rcnt(),
-	
-	.o_dbg_we(o_dbg_fifo_we),
-	.o_dbg_waddr(o_dbg_fifo_waddr),
-	.o_dbg_re(o_dbg_fifo_re),
-	.o_dbg_raddr(o_dbg_fifo_raddr)
-);
-
-always@(negedge i_aresetn or posedge i_sysclk)
-begin
-	if (~i_aresetn)
-	begin
-		r_axi4_wrstate_1P	<= s_INIT;
-		r_axi4_rastate_1P	<= s_INIT;
-		r_axi4_rdstate_1P	<= s_INIT;
-		r_axi4_nwr_1P		<= 1'b0;
-		
-		r_AXI4_AWREADY_1P	<= 1'b0;
-		r_AXI4_AWLEN_1P		<= 1'b0;
-		//r_AXI4_WREADY_c	<= 1'b0;
-		r_AXI4_WLAST_1P		<= 1'b0;
-		r_AXI4_BVALID_1P	<= 1'b0;
-		r_AXI4_ARREADY_1P	<= 1'b0;
-		r_AXI4_ARLEN_1P		<= {8{1'b0}};
-		r_AXI4_RVALID_1P	<= 1'b0;
-		r_AXI4_BID_1P		<= {AXI_BID_WIDTH{1'b0}};
-		r_AXI4_RID_1P		<= {AXI_ARID_WIDTH{1'b0}};
-		
-		r_we_1P				<= 1'b0;
-		r_re_1P				<= 1'b0;
-		r_last_1P			<= 1'b0;
-		r_addr_1P			<= {BA_WIDTH+ROW_WIDTH+COL_WIDTH{1'b0}};
-		r_din_1P			<= {DIN_WIDTH{1'b0}};
-		r_size_1P			<= {7{1'b0}};
-		r_shift_cnt_1P		<= {7{1'b0}};
-		r_addr_cnt_1P		<= {7{1'b0}};
-		r_arlen_cnt_1P		<= {8{1'b0}};
-		
-		r_wr_ack_1P			<= 1'b0;
-		r_AXI4_WREADY_2P	<= 1'b0;
-		r_re_lock_1P		<= 1'b0;
-		
-		r_AXI4_RID[0]		<= {AXI_ARID_WIDTH{1'b0}};
-		r_dout_1P			<= {DOUT_WIDTH+AXI_ARID_WIDTH+1{1'b0}};
-		r_fifo_wr_1P		<= 1'b0;
-		r_fifo_rd_1P		<= 1'b0;
-	end
-	else if (i_pll_locked)
-	begin
-		r_axi4_nwr_1P		<= ~r_axi4_nwr_1P;
-		r_AXI4_AWREADY_1P	<= 1'b0;
-		//r_AXI4_WREADY_c	<= 1'b0;
-		r_AXI4_ARREADY_1P	<= 1'b0;
-		
-		r_wr_ack_1P			<= w_wr_ack;
-		r_AXI4_WREADY_2P	<= r_AXI4_WREADY_c;
-		
-		r_AXI4_RID[0]		<= r_AXI4_RID_1P;
-		r_fifo_wr_1P		<= 1'b0;
-		r_fifo_rd_1P		<= 1'b0;
-		
-		case (r_axi4_wrstate_1P)
-			s_INIT:
-			begin
-				if (w_sdr_init_done)
-					r_axi4_wrstate_1P	<= s_IDLE;
-			end
-			
-			s_IDLE:
-			begin
-				if (i_AXI4_AWVALID && i_AXI4_WVALID &&
-					~r_axi4_nwr_1P && ~r_re_lock_1P)
-				begin
-					r_axi4_wrstate_1P	<= s_WR_SHIFT;
-					r_AXI4_AWREADY_1P	<= 1'b1;
-					if (i_AXI4_AWLEN != {8{1'b0}})
-						r_AXI4_AWLEN_1P	<= 1'b1;
-					else
-						r_AXI4_AWLEN_1P	<= 1'b0;
-					r_AXI4_WLAST_1P		<= i_AXI4_WLAST;
-					if (AXI_AWID_WIDTH >= AXI_BID_WIDTH)
-						r_AXI4_BID_1P	<= i_AXI4_AWID[AXI_BID_WIDTH-1:0];
-					else
-						r_AXI4_BID_1P	<= {{AXI_BID_WIDTH-AXI_AWID_WIDTH{1'b0}}, i_AXI4_AWID};
-					
-					r_we_1P			<= 1'b1;
-					// TODO AXI different width support
-					if (SDR_BWIDTH > AXI_WDATA_WIDTH)
-					begin
-						r_addr_1P[0+:BA_WIDTH+ROW_WIDTH+COL_WIDTH-(0-SDR_BWIDTH/AXI_WDATA_WIDTH+1)]	<= i_AXI4_AWADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:0-SDR_BWIDTH/AXI_WDATA_WIDTH+1];
-						$display("foo_gt\n");
-					end
-					else if (SDR_BWIDTH == AXI_WDATA_WIDTH)
-					begin
-						//r_addr_1P	<= {i_AXI4_AWADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:COL_WIDTH], {(DATA_RATE-1){1'b0}}, i_AXI4_AWADDR[COL_WIDTH-1:DATA_RATE-1]};
-						r_addr_1P <= i_AXI4_AWADDR;
-						$display("foo_eq\n");
-					end
-					
-					if (SDR_BWIDTH > AXI_WDATA_WIDTH)
-					begin
-						//r_AXI4_WREADY_c				<= 1'b1;
-						r_size_1P						<= SDR_BWIDTH/AXI_WDATA_WIDTH-1'b1;
-						r_shift_cnt_1P					<= SDR_BWIDTH/AXI_WDATA_WIDTH-1'b1;
-						$display("SDR_BWIDTH %d > AXI_WDATA_WIDTH %d\n", SDR_BWIDTH, AXI_WDATA_WIDTH);
-					end
-					else if (SDR_BWIDTH == AXI_WDATA_WIDTH)
-					begin
-						if (i_AXI4_WLAST)
-						begin
-							r_din_1P			<= i_AXI4_WDATA;
-							r_last_1P			<= 1'b1;
-						end
-						r_size_1P			<= SDR_BWIDTH/AXI_WDATA_WIDTH-1'b1;
-						r_shift_cnt_1P		<= {7{1'b0}};
-						$display("SDR_BWIDTH %d = AXI_WDATA_WIDTH %d\n", SDR_BWIDTH, AXI_WDATA_WIDTH);
-					end
-					else
-					begin
-						//r_AXI4_WREADY_c	<= 1'b1;
-						r_size_1P			<= AXI_WDATA_WIDTH/SDR_BWIDTH-1'b1;
-						r_shift_cnt_1P		<= AXI_WDATA_WIDTH/SDR_BWIDTH-1'b1;
-						$display("SDR_BWIDTH %d < AXI_WDATA_WIDTH %d\n", SDR_BWIDTH, AXI_WDATA_WIDTH);
-					end
-				end
-			end
-			
-			s_WR_SHIFT:
-			begin
-				if (SDR_BWIDTH > AXI_WDATA_WIDTH)
-				begin
-					if (r_shift_cnt_1P != 7'd0)
-					begin
-						if (r_AXI4_WREADY_c)
-							r_shift_cnt_1P		<= r_shift_cnt_1P-1'b1;
-					end
-					else
-					begin
-						r_shift_cnt_1P		<= r_size_1P;
-					end
-				end		
-				else if (SDR_BWIDTH == AXI_WDATA_WIDTH)
-				begin
-					if (r_AXI4_WREADY_2P)
-						r_addr_1P	<= r_addr_1P+c_addr_increment;
-					
-					if (r_AXI4_WREADY_c)
-						r_din_1P	<= i_AXI4_WDATA;
-					
-					if (~r_AXI4_WREADY_c & r_AXI4_WREADY_2P & i_AXI4_WLAST)
-					begin
-						r_din_1P	<= i_AXI4_WDATA;
-					end
-				end
-				
-				if (w_wr_ack)
-				begin
-					/*if (SDR_BWIDTH < AXI_WDATA_WIDTH)
-					begin
-						if (r_size_1P != `BYTES_TX_1)
-							r_addr_1P	<= r_addr_1P+c_addr_increment;
-						else if (~r_wr_ack_1P)
-							r_addr_1P	<= r_addr_1P+c_addr_increment;
-						else if (r_AXI4_WREADY_2P)
-							r_addr_1P	<= r_addr_1P+c_addr_increment;
-						
-						r_shift_cnt_1P	<= r_shift_cnt_1P-1'b1;
-						if (r_AXI4_WLAST_1P && r_shift_cnt_1P == 7'd1)
-							r_last_1P	<= 1'b1;
-					end
-					else if (SDR_BWIDTH == AXI_WDATA_WIDTH)
-					begin
-						r_AXI4_WREADY_c	<= 1'b1;
-					end
-					else
-					begin
-						r_AXI4_WREADY_c	<= 1'b1;
-						
-						if (r_AXI4_WREADY_c)
-							r_addr_1P	<= r_addr_1P+1'b1;
-						
-						if (r_shift_cnt_1P == 7'd1)
-						begin
-							if (i_AXI4_WLAST || r_AXI4_WLAST_1P)
-							begin
-								r_axi4_wrstate_1P	<= s_WR_RESP;
-								r_AXI4_WREADY_c	<= 1'b0;
-								r_AXI4_WLAST_1P		<= 1'b0;
-								r_AXI4_BVALID_1P	<= 1'b1;
-								
-								r_last_1P			<= 1'b1;
-							end
-						end
-					end*/
-					
-					if (r_shift_cnt_1P == 7'd0)
-					begin	
-						//r_AXI4_WREADY_c	<= 1'b1;
-						
-						r_AXI4_WLAST_1P	<= i_AXI4_WLAST;
-						r_shift_cnt_1P	<= r_size_1P;
-						
-						if (i_AXI4_WLAST && r_size_1P == {7{1'b0}} && r_AXI4_AWLEN_1P)
-						begin
-							r_axi4_wrstate_1P	<= s_WR_RESP;
-							//r_AXI4_WREADY_c	<= ~r_AXI4_WREADY_c;
-							r_AXI4_WLAST_1P		<= 1'b0;
-							r_AXI4_BVALID_1P	<= 1'b1;
-							
-							r_we_1P				<= 1'b1;
-							r_last_1P			<= 1'b1;
-						end
-						else if (r_AXI4_WLAST_1P)
-						begin
-							r_axi4_wrstate_1P	<= s_WR_RESP;
-							//r_AXI4_WREADY_c	<= ~r_AXI4_WREADY_c;
-							r_AXI4_WLAST_1P		<= 1'b0;
-							r_AXI4_BVALID_1P	<= 1'b1;
-							
-							r_we_1P				<= 1'b0;
-							r_last_1P			<= 1'b0;
-						end
-					end
-				end
-			end
-			
-			s_WR_RESP:
-			begin
-				r_we_1P		<= 1'b0;
-				r_last_1P	<= 1'b0;
-				
-				if (i_AXI4_BREADY)
-				begin
-					r_axi4_wrstate_1P	<= s_IDLE;
-					r_AXI4_BVALID_1P	<= 1'b0;
-				end
-			end
-		endcase
-		
-		case (r_axi4_rastate_1P)
-			s_INIT:
-			begin
-				if (w_sdr_init_done)
-					r_axi4_rastate_1P	<= s_IDLE;
-			end
-			
-			s_IDLE:
-			begin
-				if (i_AXI4_ARVALID && r_axi4_nwr_1P
-					&& ~r_we_1P && ~w_afull && ~r_AXI4_RVALID_1P)
-				begin
-					r_axi4_rastate_1P	<= s_RD_ADDR;
-					r_AXI4_ARREADY_1P	<= 1'b1;
-					r_AXI4_RID_1P		<= i_AXI4_ARID;
-					
-					r_re_1P				<= 1'b1;
-					r_re_lock_1P		<= 1'b1;
-					if (i_AXI4_ARLEN == 8'd0 && (SDR_BWIDTH == AXI_RDATA_WIDTH))
-						r_last_1P		<= 1'b1;
-					
-					// TODO AXI different width support
-					if (SDR_BWIDTH > AXI_RDATA_WIDTH)
-					begin
-						r_addr_1P[0+:BA_WIDTH+ROW_WIDTH+COL_WIDTH-(0-SDR_BWIDTH/AXI_RDATA_WIDTH+1)]	<= i_AXI4_ARADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:0-SDR_BWIDTH/AXI_RDATA_WIDTH+1];
-					end
-					else if (SDR_BWIDTH == AXI_RDATA_WIDTH)
-					begin
-						//r_addr_1P	<= {i_AXI4_ARADDR[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:COL_WIDTH], {(DATA_RATE-1){1'b0}}, i_AXI4_ARADDR[COL_WIDTH-1:DATA_RATE-1]};
-						r_addr_1P	<= i_AXI4_ARADDR;
-					end
-					
-					if (SDR_BWIDTH > AXI_WDATA_WIDTH)
-					begin
-						r_size_1P		<= SDR_BWIDTH/AXI_RDATA_WIDTH-1'b1;
-						r_shift_cnt_1P	<= SDR_BWIDTH/AXI_RDATA_WIDTH-1'b1;
-						r_addr_cnt_1P	<= SDR_BWIDTH/AXI_RDATA_WIDTH-1'b1;
-					end
-					else if (SDR_BWIDTH == AXI_WDATA_WIDTH)
-					begin
-						r_AXI4_ARLEN_1P	<= i_AXI4_ARLEN;
-						r_size_1P		<= 7'd0;
-						r_shift_cnt_1P	<= 7'd0;
-						r_addr_cnt_1P	<= 7'd0;
-						r_arlen_cnt_1P	<= i_AXI4_ARLEN;
-					end
-					else
-					begin
-						r_AXI4_ARLEN_1P	<= i_AXI4_ARLEN;
-						r_size_1P		<= AXI_RDATA_WIDTH/SDR_BWIDTH-1'b1;
-						r_shift_cnt_1P	<= AXI_RDATA_WIDTH/SDR_BWIDTH-1'b1;
-						r_addr_cnt_1P	<= AXI_RDATA_WIDTH/SDR_BWIDTH-1'b1;
-						r_arlen_cnt_1P	<= i_AXI4_ARLEN;
-					end
-				end
-			end
-			
-			s_RD_ADDR:
-			begin
-				if (~w_afull)
-					r_re_1P	<= 1'b1;
-				
-				if (w_rd_ack)
-				begin
-					if (w_afull)
-						r_re_1P	<= 1'b0;
-					if (SDR_BWIDTH < AXI_WDATA_WIDTH)
-						r_addr_1P		<= r_addr_1P+c_addr_increment;
-					else if (SDR_BWIDTH == AXI_WDATA_WIDTH)
-						r_addr_1P		<= r_addr_1P+c_addr_increment;
-					else
-						r_addr_1P		<= r_addr_1P+1'b1;
-					
-					r_addr_cnt_1P	<= r_addr_cnt_1P-1'b1;
-					if (r_addr_cnt_1P == 7'd0)
-					begin
-						r_addr_cnt_1P	<= r_size_1P;
-						r_arlen_cnt_1P	<= r_arlen_cnt_1P-1'b1;
-					end
-					
-					if (r_arlen_cnt_1P == 8'd1 && (SDR_BWIDTH == AXI_RDATA_WIDTH))
-						r_last_1P	<= 1'b1;
-					
-					if (r_arlen_cnt_1P == 8'd0)
-					begin
-						if (r_addr_cnt_1P == 8'd1)
-							r_last_1P	<= 1'b1;
-						
-						if (r_addr_cnt_1P == 8'd0)
-						begin
-							r_axi4_rastate_1P	<= s_IDLE;
-							
-							r_re_1P			<= 1'b0;
-							r_last_1P		<= 1'b0;
-							r_re_lock_1P	<= 1'b0;
-						end
-					end
-				end
-			end
-		endcase
-		
-		if (w_rd_valid)
-		begin
-			if (SDR_BWIDTH >= AXI_RDATA_WIDTH)
-			begin
-				r_dout_1P[DOUT_WIDTH-1:0]	<= w_dout;
-			end
-			
-			r_dout_1P[DOUT_WIDTH+AXI_ARID_WIDTH-1:DOUT_WIDTH]	<= r_AXI4_RID[CL+tIORT+1];
-			
-			r_shift_cnt_1P	<= r_shift_cnt_1P-1'b1;
-			
-			if (r_shift_cnt_1P == 7'd0)
-			begin
-				r_fifo_wr_1P	<= 1'b1;
-				if (r_AXI4_ARLEN_1P == 7'd0)
-					r_dout_1P[DOUT_WIDTH+AXI_ARID_WIDTH]	<= 1'b1;
-				else
-					r_AXI4_ARLEN_1P	<= r_AXI4_ARLEN_1P-1'b1;
-				r_shift_cnt_1P	<= r_size_1P;
-			end
-		end
-		
-		case (r_axi4_rdstate_1P)
-			s_INIT:
-			begin
-				if (w_sdr_init_done)
-					r_axi4_rdstate_1P	<= s_IDLE;
-			end
-			
-			s_IDLE:
-			begin
-				if (~w_empty & r_dout_1P[DOUT_WIDTH+AXI_ARID_WIDTH])
-				begin
-					r_axi4_rdstate_1P	<= s_RD_SHIFT;
-					r_fifo_rd_1P		<= 1'b1;
-					r_dout_1P[DOUT_WIDTH+AXI_ARID_WIDTH]	<= 1'b0;
-				end
-			end
-			
-			s_RD_SHIFT:
-			begin
-				r_AXI4_RVALID_1P	<= 1'b1;
-				
-				if (i_AXI4_RREADY)
-				begin
-					if (w_empty)
-					begin
-						r_axi4_rdstate_1P	<= s_IDLE;
-						r_AXI4_RVALID_1P	<= 1'b0;
-					end
-				
-					if (w_fifo_dout[AXI_RDATA_WIDTH+AXI_ARID_WIDTH])
-					begin
-						r_axi4_rdstate_1P	<= s_IDLE;
-						r_AXI4_RVALID_1P	<= 1'b0;
-					end
-				end
-			end
-		endcase
-	end
-end
-
-genvar i;
-generate
-	for (i=0; i<CL+tIORT+1; i=i+1)
-	begin: pipe
-		always@(negedge i_aresetn or posedge i_sysclk)
-		begin
-			if (~i_aresetn)
-				r_AXI4_RID[i+1]	<= {AXI_ARID_WIDTH{1'b0}};
-			else
-				r_AXI4_RID[i+1]	<= r_AXI4_RID[i];
-		end
-	end
-endgenerate
-
-assign r_AXI4_WREADY_c = w_wr_ack;
-
-assign	o_AXI4_AWREADY	= r_AXI4_AWREADY_1P;
-assign	o_AXI4_WREADY	= r_AXI4_WREADY_c;
-assign	o_AXI4_BVALID	= r_AXI4_BVALID_1P;
-assign	o_AXI4_ARREADY	= r_AXI4_ARREADY_1P;
-assign	o_AXI4_RVALID	= r_AXI4_RVALID_1P;
-assign	o_AXI4_RDATA	= w_fifo_dout[AXI_RDATA_WIDTH-1:0];
-assign	o_AXI4_RLAST	= w_fifo_dout[AXI_RDATA_WIDTH+AXI_ARID_WIDTH];
-assign	o_AXI4_BID		= r_AXI4_BID_1P;
-assign	o_AXI4_RID		= w_fifo_dout[AXI_RDATA_WIDTH+AXI_ARID_WIDTH-1:AXI_RDATA_WIDTH];
-assign	o_AXI4_BRESP	= `OKAY;
-assign	o_AXI4_BUSER	= {AXI_BUSER_WIDTH{1'b0}};
-assign	o_AXI4_RRESP	= `OKAY;
-assign	o_AXI4_RUSER	= {AXI_RUSER_WIDTH{1'b0}};
-
-assign	o_dbg_we			= r_we_1P;
-assign	o_dbg_re			= r_re_1P;
-assign	o_dbg_last			= r_last_1P;
-assign	o_dbg_addr			= r_addr_1P;
-assign	o_dbg_din			= r_din_1P;
-assign	o_sdr_rd_valid		= w_rd_valid;
-assign	o_sdr_dout			= r_dout_1P;
-assign	o_axi4_wrstate		= r_axi4_wrstate_1P;
-assign	o_dbg_axi4_wlast	= r_AXI4_WLAST_1P;
-assign	o_axi4_rastate		= r_axi4_rastate_1P;
-assign	o_axi4_rdstate		= r_axi4_rdstate_1P;
-assign	o_axi4_nwr			= r_axi4_nwr_1P;
-assign	o_re_lock			= r_re_lock_1P;
-assign	o_shift_cnt			= r_shift_cnt_1P;
-assign	o_axi4_arlen		= r_AXI4_ARLEN_1P;
-assign	o_fifo_wr			= r_fifo_wr_1P;
-assign	o_fifo_full			= w_afull;
-assign	o_fifo_empty		= w_empty;
-
-endmodule
-
-//////////////////////////////////////////////////////////////////////////////
-// Copyright (C) 2013-2019 Efinix Inc. All rights reserved.
-//
-// This   document  contains  proprietary information  which   is
-// protected by  copyright. All rights  are reserved.  This notice
-// refers to original work by Efinix, Inc. which may be derivitive
-// of other work distributed under license of the authors.  In the
-// case of derivative work, nothing in this notice overrides the
-// original author's license agreement.  Where applicable, the 
-// original license agreement is included in it's original 
-// unmodified form immediately below this header.
-//
-// WARRANTY DISCLAIMER.  
-//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
-//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
-//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
-//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
-//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
-//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
-//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
-//
-// LIMITATION OF LIABILITY.  
-//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
-//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
-//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
-//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
-//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
-//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
-//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
-//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
-//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
-//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
-//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
-//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
-//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
-//     APPLY TO LICENSEE.
-//
-//////////////////////////////////////////////////////////////////////////////projects/SWIP/hxlai/workplace/test/20201008_184659/testbench_random
-
-/////////////////////////////////////////////////////////////////////////////
-//           _____       
-//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
-//         / /       \   
-//        / /  ..    /   axi4.vh
-//       / / .'     /    
-//    __/ /.'      /     Description:
-//   __   \       /      axi4 header file
-//  /_/ /\ \_____/ /     
-// ____/  \_______/      
-//
-// *******************************
-// Revisions:
-// 1.0 Initial rev
-//
-// *******************************
-/////////////////////////////////////////////////////////////////////////////
-
-// AxSIZE
-`define	BYTES_TX_1		3'b000
-`define	BYTES_TX_2		3'b001
-`define	BYTES_TX_4		3'b010
-`define	BYTES_TX_8		3'b011
-`define	BYTES_TX_16		3'b100
-`define	BYTES_TX_32		3'b101
-`define	BYTES_TX_64		3'b110
-`define	BYTES_TX_128	3'b111
-
-// AxBURST
-`define	FIXED		2'b00
-`define	INCR		2'b01
-`define	WRAP		2'b10
-`define	RESERVED	2'b11
-
-// xRESP
-`define	OKAY	2'b00
-`define	EXOKAY	2'b01
-`define	SLVERR	2'b10
-`define	DECERR	2'b11
-
-// AxCACHE
-`define	B_BIT	0
-`define	M_BIT	1
-`define	OA_BIT	2
-`define	A_BIT	3
-
-// AxPROT
-`define	PRIVILEGED	0
-`define	SECURE		1
-`define	DATA_INSTR	2
-
-// AxLOCK
-`define	NORMAL		1'b0
-`define	EXCLUSIVE	1'b1
-
-
-/////////////////////////////////////////////////////////////////////////////
-//           _____       
-//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
-//         / /       \   
-//        / /  ..    /   `IP_MODULE_NAME(dual_clock_fifo_wrapper).v
-//       / / .'     /    
-//    __/ /.'      /     Description:
-//   __   \       /      wraps around dual clock fifo
-//  /_/ /\ \_____/ /     
-// ____/  \_______/      
-//
-// *******************************
-// Revisions:
-// 1.0 Initial rev
-//
-// *******************************
-
-module `IP_MODULE_NAME(dual_clock_fifo_wrapper)
-#(
-	parameter	DATA_WIDTH		= 8,
-	parameter	ADDR_WIDTH		= 8,
-	parameter	LATENCY			= 1,
-	parameter	FIFO_MODE		= "STD_FIFO",
-	parameter	RAM_INIT_FILE	= "",
-	/////////////////////////////////////////////////////////////////////////////////////
-	// compatibility	output_reg			check_full_overflow		check_empty_underflow
-	/////////////////////////////////////////////////////////////////////////////////////
-	// E				user configurable	user configurable		user configurable
-	// X				user configurable	always on				always on
-	// A				always off			user configurable		user configurable
-	parameter	COMPATIBILITY	= "E",
-	parameter	OUTPUT_REG		= "TRUE",
-	parameter	CHECK_FULL		= "TRUE",
-	parameter	CHECK_EMPTY		= "TRUE",
-	parameter	AFULL_THRESHOLD	= 2**ADDR_WIDTH-1,
-	parameter	AEMPTY_THRESHOLD= 1
-)
-(
-	input						i_arst,
-	
-	input						i_wclk,
-	input						i_we,
-	input	[DATA_WIDTH-1:0]	i_wdata,
-	
-	input						i_rclk,
-	input						i_re,
-	
-	output						o_full,
-	output						o_empty,
-	output	[DATA_WIDTH-1:0]	o_rdata,
-	
-	output						o_afull,
-	output	[ADDR_WIDTH-1:0]	o_wcnt,
-	output						o_aempty,
-	output	[ADDR_WIDTH-1:0]	o_rcnt,
-	
-	output						o_dbg_we,
-	output	[ADDR_WIDTH-1:0]	o_dbg_waddr,
-	output						o_dbg_re,
-	output	[ADDR_WIDTH-1:0]	o_dbg_raddr
-);
-
-generate
-	if (COMPATIBILITY == "X")
-	begin
-		if (FIFO_MODE == "BYPASS")
-		begin
-			`IP_MODULE_NAME(dual_clock_fifo)
-			#(
-				.DATA_WIDTH			(DATA_WIDTH),
-				.ADDR_WIDTH			(ADDR_WIDTH),
-				.LATENCY			(LATENCY+4),
-				.FIFO_MODE			(FIFO_MODE),
-				.RAM_INIT_FILE		(RAM_INIT_FILE),
-				.COMPATIBILITY		(COMPATIBILITY),
-				.OUTPUT_REG			("FALSE"),
-				.CHECK_FULL			("TRUE"),
-				.CHECK_EMPTY		("TRUE"),
-				.AFULL_THRESHOLD	(AFULL_THRESHOLD),
-				.AEMPTY_THRESHOLD	(AEMPTY_THRESHOLD)
-			)
-			inst_dual_clock_fifo
-			(
-				.i_arst		(i_arst),
-				.i_wclk		(i_wclk),
-				.i_we		(i_we),
-				.i_wdata	(i_wdata),
-				.i_rclk		(i_rclk),
-				.i_re		(i_re),
-				.o_full		(o_full),
-				.o_empty	(o_empty),
-				.o_rdata	(o_rdata),
-				
-				.o_afull	(o_afull),
-				.o_wcnt		(o_wcnt),
-				.o_aempty	(o_aempty),
-				.o_rcnt		(o_rcnt),
-				
-				.o_dbg_we	(o_dbg_we),
-				.o_dbg_waddr(o_dbg_waddr),
-				.o_dbg_re	(o_dbg_re),
-				.o_dbg_raddr(o_dbg_raddr)
-			);
-		end
-		else
-		begin
-			`IP_MODULE_NAME(dual_clock_fifo)
-			#(
-				.DATA_WIDTH			(DATA_WIDTH),
-				.ADDR_WIDTH			(ADDR_WIDTH),
-				.LATENCY			(LATENCY+2),
-				.FIFO_MODE			(FIFO_MODE),
-				.RAM_INIT_FILE		(RAM_INIT_FILE),
-				.COMPATIBILITY		(COMPATIBILITY),
-				.OUTPUT_REG			(OUTPUT_REG),
-				.CHECK_FULL			("TRUE"),
-				.CHECK_EMPTY		("TRUE"),
-				.AFULL_THRESHOLD	(AFULL_THRESHOLD),
-				.AEMPTY_THRESHOLD	(AEMPTY_THRESHOLD)
-			)
-			inst_dual_clock_fifo
-			(
-				.i_arst		(i_arst),
-				.i_wclk		(i_wclk),
-				.i_we		(i_we),
-				.i_wdata	(i_wdata),
-				.i_rclk		(i_rclk),
-				.i_re		(i_re),
-				.o_full		(o_full),
-				.o_empty	(o_empty),
-				.o_rdata	(o_rdata),
-				
-				.o_afull	(o_afull),
-				.o_wcnt		(o_wcnt),
-				.o_aempty	(o_aempty),
-				.o_rcnt		(o_rcnt),
-				
-				.o_dbg_we	(o_dbg_we),
-				.o_dbg_waddr(o_dbg_waddr),
-				.o_dbg_re	(o_dbg_re),
-				.o_dbg_raddr(o_dbg_raddr)
-			);
-		end
-	end
-	else if (COMPATIBILITY == "A")
-	begin
-		`IP_MODULE_NAME(dual_clock_fifo)
-		#(
-			.DATA_WIDTH			(DATA_WIDTH),
-			.ADDR_WIDTH			(ADDR_WIDTH),
-			.LATENCY			(LATENCY),
-			.FIFO_MODE			(FIFO_MODE),
-			.RAM_INIT_FILE		(RAM_INIT_FILE),
-			.COMPATIBILITY		(COMPATIBILITY),
-			.OUTPUT_REG			("FALSE"),
-			.CHECK_FULL			(CHECK_FULL),
-			.CHECK_EMPTY		(CHECK_EMPTY),
-			.AFULL_THRESHOLD	(AFULL_THRESHOLD),
-			.AEMPTY_THRESHOLD	(AEMPTY_THRESHOLD)
-		)
-		inst_dual_clock_fifo
-		(
-			.i_arst		(i_arst),
-			.i_wclk		(i_wclk),
-			.i_we		(i_we),
-			.i_wdata	(i_wdata),
-			.i_rclk		(i_rclk),
-			.i_re		(i_re),
-			.o_full		(o_full),
-			.o_empty	(o_empty),
-			.o_rdata	(o_rdata),
-			
-			.o_afull	(o_afull),
-			.o_wcnt		(o_wcnt),
-			.o_aempty	(o_aempty),
-			.o_rcnt		(o_rcnt),
-			
-			.o_dbg_we	(o_dbg_we),
-			.o_dbg_waddr(o_dbg_waddr),
-			.o_dbg_re	(o_dbg_re),
-			.o_dbg_raddr(o_dbg_raddr)
-		);
-	end
-	else
-	begin
-		`IP_MODULE_NAME(dual_clock_fifo)
-		#(
-			.DATA_WIDTH			(DATA_WIDTH),
-			.ADDR_WIDTH			(ADDR_WIDTH),
-			.LATENCY			(LATENCY),
-			.FIFO_MODE			(FIFO_MODE),
-			.RAM_INIT_FILE		(RAM_INIT_FILE),
-			.COMPATIBILITY		(COMPATIBILITY),
-			.OUTPUT_REG			(OUTPUT_REG),
-			.CHECK_FULL			(CHECK_FULL),
-			.CHECK_EMPTY		(CHECK_EMPTY),
-			.AFULL_THRESHOLD	(AFULL_THRESHOLD),
-			.AEMPTY_THRESHOLD	(AEMPTY_THRESHOLD)
-		)
-		inst_dual_clock_fifo
-		(
-			.i_arst		(i_arst),
-			.i_wclk		(i_wclk),
-			.i_we		(i_we),
-			.i_wdata	(i_wdata),
-			.i_rclk		(i_rclk),
-			.i_re		(i_re),
-			.o_full		(o_full),
-			.o_empty	(o_empty),
-			.o_rdata	(o_rdata),
-			
-			.o_afull	(o_afull),
-			.o_wcnt		(o_wcnt),
-			.o_aempty	(o_aempty),
-			.o_rcnt		(o_rcnt),
-			
-			.o_dbg_we	(o_dbg_we),
-			.o_dbg_waddr(o_dbg_waddr),
-			.o_dbg_re	(o_dbg_re),
-			.o_dbg_raddr(o_dbg_raddr)
-		);
-	end
-endgenerate
-
-endmodule
-
-//////////////////////////////////////////////////////////////////////////////
-// Copyright (C) 2013-2019 Efinix Inc. All rights reserved.
-//
-// This   document  contains  proprietary information  which   is
-// protected by  copyright. All rights  are reserved.  This notice
-// refers to original work by Efinix, Inc. which may be derivitive
-// of other work distributed under license of the authors.  In the
-// case of derivative work, nothing in this notice overrides the
-// original author's license agreement.  Where applicable, the 
-// original license agreement is included in it's original 
-// unmodified form immediately below this header.
-//
-// WARRANTY DISCLAIMER.  
-//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
-//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
-//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
-//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
-//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
-//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
-//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
-//
-// LIMITATION OF LIABILITY.  
-//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
-//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
-//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
-//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
-//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
-//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
-//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
-//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
-//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
-//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
-//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
-//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
-//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
-//     APPLY TO LICENSEE.
-//
-/////////////////////////////////////////////////////////////////////////////
-
-/////////////////////////////////////////////////////////////////////////////
-//           _____       
-//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
-//         / /       \   
-//        / /  ..    /   `IP_MODULE_NAME(dual_clock_fifo).v
-//       / / .'     /    
-//    __/ /.'      /     Description:
-//   __   \       /      dual clock fifo
-//  /_/ /\ \_____/ /     
-// ____/  \_______/     
-//
-// *******************************
-// Revisions:
-// 1.0 Initial rev
-//
-// *******************************
-/////////////////////////////////////////////////////////////////////////////
-
-module `IP_MODULE_NAME(dual_clock_fifo)
-#(
-	parameter	DATA_WIDTH		= 8,
-	parameter	ADDR_WIDTH		= 8,
-	parameter	LATENCY			= 1,
-	parameter	FIFO_MODE		= "STD_FIFO",
-	parameter	RAM_INIT_FILE	= "",
-	parameter	COMPATIBILITY	= "E",
-	parameter	OUTPUT_REG		= "FALSE",
-	parameter	CHECK_FULL		= "TRUE",
-	parameter	CHECK_EMPTY		= "TRUE",
-	parameter	AFULL_THRESHOLD	= 2**ADDR_WIDTH-1,
-	parameter	AEMPTY_THRESHOLD= 1
-)
-(
-	input						i_arst,
-	
-	input						i_wclk,
-	input						i_we,
-	input	[DATA_WIDTH-1:0]	i_wdata,
-	
-	input						i_rclk,
-	input						i_re,
-	
-	output						o_full,
-	output						o_empty,
-	output	[DATA_WIDTH-1:0]	o_rdata,
-	
-	output						o_afull,
-	output	[ADDR_WIDTH-1:0]	o_wcnt,
-	output						o_aempty,
-	output	[ADDR_WIDTH-1:0]	o_rcnt,
-	
-	output						o_dbg_we,
-	output	[ADDR_WIDTH-1:0]	o_dbg_waddr,
-	output						o_dbg_re,
-	output	[ADDR_WIDTH-1:0]	o_dbg_raddr
-);
-
-reg		[ADDR_WIDTH:0]	r_waddrb_1P;
-reg						r_wflag_1P;
-reg		[ADDR_WIDTH-1:0]r_waddrg_1P;
-reg		[ADDR_WIDTH-1:0]r_waddrg_2P;
-
-reg		[ADDR_WIDTH:0]r_raddrb_wclk_1P;
-reg		[ADDR_WIDTH:0]r_raddrb_wclk_neg;
-reg		[ADDR_WIDTH:0]wr_cnt;
-
-reg		[ADDR_WIDTH:0]r_waddrb_rclk_1P;
-reg		[ADDR_WIDTH:0]r_waddrb_rclk_neg;
-reg		[ADDR_WIDTH:0]rd_cnt;
-
-reg						r_we_1P;
-reg						r_re_1P;
-reg		[ADDR_WIDTH:0]	r_raddrb_1P;
-reg						r_rflag_1P;
-reg		[ADDR_WIDTH-1:0]r_raddrg_1P;
-reg						r_rflag_2P;
-reg		[ADDR_WIDTH-1:0]r_raddrg_2P;
-
-reg		[LATENCY-1:0]	r_empty;
-reg		[LATENCY:0]		r_full;
-
-wire	[ADDR_WIDTH:0]	w_waddrb_1P;
-wire					w_wflag_1P;
-wire	[ADDR_WIDTH-1:0]w_waddrg_1P;
-
-wire	[ADDR_WIDTH:0]	w_raddrb_1P;
-wire					w_rflag_1P;
-wire	[ADDR_WIDTH-1:0]w_raddrg_1P;
-
-wire	w_empty;
-wire	w_full;
-
-wire	w_empty_P;
-wire	w_full_P;
-
-wire					w_we;
-wire					w_re;
-wire	[ADDR_WIDTH-1:0]w_raddr;
-
-assign	w_waddrb_1P					=	r_waddrb_1P + 1'b1;
-assign	w_wflag_1P					=	w_waddrb_1P[ADDR_WIDTH];
-assign	w_waddrg_1P[ADDR_WIDTH-1]	=	w_waddrb_1P[ADDR_WIDTH-1] ^ 1'b0;
-assign	w_waddrg_1P[ADDR_WIDTH-2:0]	=	w_waddrb_1P[ADDR_WIDTH-2:0] ^ w_waddrb_1P[ADDR_WIDTH-1:1];
-
-assign	w_full	=	((r_waddrg_1P == r_raddrg_1P) &
-					(r_wflag_1P != r_rflag_1P))?
-						1'b1:
-					(i_we &
-					((w_waddrg_1P == r_raddrg_2P) &
-					(w_wflag_1P != r_rflag_2P)))?
-						1'b1:
-						1'b0;
-
-always@(posedge i_arst or posedge i_wclk)
-begin
-	if (i_arst) begin
-		r_raddrb_wclk_1P	<= {ADDR_WIDTH+1{1'b0}};
-	end
-	else begin
-		r_raddrb_wclk_1P	<= r_raddrb_1P;
-	end
-end
-
-always@(posedge i_arst or posedge i_wclk)
-begin
-	if (i_arst) begin
-		r_raddrb_wclk_neg	<= {ADDR_WIDTH+1{1'b0}};
-	end
-	else begin
-		r_raddrb_wclk_neg	<= ~r_raddrb_wclk_1P + 1'b1;
-	end
-end
-
-always@(posedge i_arst or posedge i_wclk)
-begin
-	if (i_arst) begin
-		wr_cnt			<= {ADDR_WIDTH+1{1'b0}};
-	end
-	else begin
-		wr_cnt			<= r_waddrb_1P + r_raddrb_wclk_neg;
-	end
-end
-
-always@(posedge i_arst or posedge i_rclk)
-begin
-	if (i_arst) begin
-		r_waddrb_rclk_1P	<= {ADDR_WIDTH+1{1'b0}};
-	end
-	else begin
-		r_waddrb_rclk_1P	<= r_waddrb_1P;
-	end
-end
-
-always@(posedge i_arst or posedge i_rclk)
-begin
-	if (i_arst) begin
-		r_waddrb_rclk_neg	<= {ADDR_WIDTH+1{1'b0}};
-	end
-	else begin
-		r_waddrb_rclk_neg	<= ~r_waddrb_rclk_1P;
-	end
-end
-
-always@(posedge i_arst or posedge i_rclk)
-begin
-	if (i_arst) begin
-		rd_cnt			<= {ADDR_WIDTH+1{1'b0}};
-	end
-	else begin
-		rd_cnt			<= r_raddrb_1P + r_waddrb_rclk_neg;
-	end
-end
-
-always@(posedge i_arst or posedge i_wclk)
-begin
-	if (i_arst)
-	begin
-		r_we_1P			<= 1'b0;
-		r_waddrb_1P		<= {ADDR_WIDTH{1'b0}};
-		r_wflag_1P		<= 1'b0;
-		r_waddrg_1P		<= {ADDR_WIDTH{1'b0}};
-		r_waddrg_2P		<= {ADDR_WIDTH{1'b0}};
-		
-		r_full[0]		<= 1'b0;
-	end
-	else
-	begin
-		r_we_1P	<= 1'b0;
-
-		if (CHECK_FULL == "TRUE")
-		begin
-			if (i_we & ~w_full_P)
-			begin
-				r_we_1P			<= 1'b1;
-				r_waddrb_1P		<= w_waddrb_1P;
-				r_wflag_1P		<= w_wflag_1P;
-				r_waddrg_1P		<= w_waddrg_1P;
-			end
-		end
-		else
-		begin
-			if (i_we)
-			begin
-				r_we_1P			<= 1'b1;
-				r_waddrb_1P		<= w_waddrb_1P;
-				r_wflag_1P		<= w_wflag_1P;
-				r_waddrg_1P		<= w_waddrg_1P;
-			end
-		end
-		
-		if (r_we_1P)
-			r_waddrg_2P		<= r_waddrg_1P;
-		
-		r_full[0]		<= w_full;
-	end
-end
-
-assign	w_raddrb_1P					=	r_raddrb_1P + 1'b1;
-assign	w_rflag_1P					=	w_raddrb_1P[ADDR_WIDTH];
-assign	w_raddrg_1P[ADDR_WIDTH-1]	=	w_raddrb_1P[ADDR_WIDTH-1] ^ 1'b0;
-assign	w_raddrg_1P[ADDR_WIDTH-2:0]	=	w_raddrb_1P[ADDR_WIDTH-2:0] ^ w_raddrb_1P[ADDR_WIDTH-1:1];
-
-assign	w_empty	=	((r_waddrg_2P == r_raddrg_1P) &
-					(r_wflag_1P == r_rflag_2P))?
-						1'b1:
-					(i_re &
-					((r_waddrg_1P == r_raddrg_1P) &
-					(r_wflag_1P == r_rflag_1P)))?
-						1'b1:
-						1'b0;
-
-always@(posedge i_arst or posedge i_rclk)
-begin
-	if (i_arst)
-	begin
-		r_re_1P			<= 1'b0;
-		r_raddrb_1P		<= {ADDR_WIDTH{1'b0}};
-		r_rflag_1P		<= 1'b0;
-		r_raddrg_1P		<= {ADDR_WIDTH{1'b0}};
-		r_rflag_2P		<= 1'b0;
-		r_raddrg_2P		<= {ADDR_WIDTH{1'b0}};
-		
-		r_empty[0]		<= 1'b1;
-	end
-	else
-	begin
-		r_re_1P	<= 1'b0;
-		
-		if (CHECK_FULL == "TRUE")
-		begin
-			if (i_re & ~w_empty_P)
-			begin
-				r_re_1P			<= 1'b1;
-				r_raddrb_1P		<= w_raddrb_1P;
-				r_rflag_1P		<= w_rflag_1P;
-				r_raddrg_1P		<= w_raddrg_1P;
-			end
-		end
-		else
-		begin
-			if (i_re)
-			begin
-				r_re_1P			<= 1'b1;
-				r_raddrb_1P		<= w_raddrb_1P;
-				r_rflag_1P		<= w_rflag_1P;
-				r_raddrg_1P		<= w_raddrg_1P;
-			end
-		end
-		
-		if (r_re_1P)
-		begin
-			r_raddrg_2P		<= r_raddrg_1P;
-			r_rflag_2P		<= r_rflag_1P;
-		end
-		
-		r_empty[0]		<= w_empty;
-	end
-end
-
-genvar i, j;
-generate
-	for (i=1; i<LATENCY; i=i+1)
-	begin: pipe_empty
-		always@(posedge i_arst or posedge i_rclk)
-		begin
-			if (i_arst)
-				r_empty[i]	<= 1'b1;
-			else
-				r_empty[i]	<= r_empty[i-1];
-		end
-	end
-	
-	assign	w_empty_P	= w_empty | r_empty[LATENCY-1];
-	
-	for (j=1; j<LATENCY+1; j=j+1)
-	begin: pipe_full
-		always@(posedge i_arst or posedge i_wclk)
-		begin
-			if (i_arst)
-				r_full[j]	<= 1'b0;
-			else
-				r_full[j]	<= r_full[j-1];
-		end
-	end
-	
-	if (COMPATIBILITY == "X")
-		if (FIFO_MODE == "BYPASS")
-			assign	w_full_P	= r_full[0] | r_full[LATENCY-2];
-		else
-			assign	w_full_P	= r_full[0]	| r_full[LATENCY];
-	else
-		assign	w_full_P	= r_full[0] | r_full[LATENCY-1];
-	
-	if (CHECK_FULL == "TRUE")
-		assign	w_we	= i_we & ~w_full_P;
-	else
-		assign	w_we	= i_we;
-	
-	if (FIFO_MODE == "BYPASS")
-	begin
-		assign	w_re	= 1'b1;
-		if (CHECK_EMPTY == "TRUE")
-			assign	w_raddr	= (i_re & ~w_empty_P)?
-								w_raddrg_1P[ADDR_WIDTH-1:0]:
-								r_raddrg_1P[ADDR_WIDTH-1:0];
-		else
-			assign	w_raddr	= (i_re)?
-								w_raddrg_1P[ADDR_WIDTH-1:0]:
-								r_raddrg_1P[ADDR_WIDTH-1:0];
-	end
-	else
-	begin
-		if (CHECK_EMPTY == "TRUE")
-			assign	w_re	= i_re & ~w_empty_P;
-		else
-			assign	w_re	= i_re;
-		assign	w_raddr	= r_raddrg_1P[ADDR_WIDTH-1:0];
-	end
-
-	`IP_MODULE_NAME(sdram_simple_dual_port_ram)
-	#(
-		.DATA_WIDTH(DATA_WIDTH),
-		.ADDR_WIDTH(ADDR_WIDTH),
-		.OUTPUT_REG(OUTPUT_REG),
-		.RAM_INIT_FILE(RAM_INIT_FILE)
-	)
-	inst_simple_dual_port_ram
-	(
-		.wdata(i_wdata),
-		.waddr(r_waddrg_1P[ADDR_WIDTH-1:0]),
-		.raddr(w_raddr),
-		.we(w_we),
-		.wclk(i_wclk),
-		.re(w_re),
-		.rclk(i_rclk),
-		.rdata(o_rdata)
-	);
-endgenerate
-
-assign	o_empty	= w_empty_P;
-assign	o_full	= w_full_P;
-
-assign	o_aempty= w_empty_P | (rd_cnt[ADDR_WIDTH-1] & rd_cnt[ADDR_WIDTH-2] & rd_cnt[ADDR_WIDTH-3]);
-assign	o_wcnt	= wr_cnt[ADDR_WIDTH] ? {ADDR_WIDTH{1'b1}} : wr_cnt[ADDR_WIDTH-1:0];
-assign	o_afull	= w_full_P | wr_cnt[ADDR_WIDTH] | (wr_cnt[ADDR_WIDTH-1] & wr_cnt[ADDR_WIDTH-2] & wr_cnt[ADDR_WIDTH-3]);
-assign	o_rcnt	= w_full_P ? {ADDR_WIDTH{1'b0}} : rd_cnt[ADDR_WIDTH-1:0];
-
-assign	o_dbg_we	= w_we;
-assign	o_dbg_waddr	= r_waddrg_1P[ADDR_WIDTH-1:0];
-assign	o_dbg_re	= w_re;
-assign	o_dbg_raddr	= w_raddr;
-
-endmodule
-
-//////////////////////////////////////////////////////////////////////////////
-// Copyright (C) 2013-2019 Efinix Inc. All rights reserved.
-//
-// This   document  contains  proprietary information  which   is
-// protected by  copyright. All rights  are reserved.  This notice
-// refers to original work by Efinix, Inc. which may be derivitive
-// of other work distributed under license of the authors.  In the
-// case of derivative work, nothing in this notice overrides the
-// original author's license agreement.  Where applicable, the 
-// original license agreement is included in it's original 
-// unmodified form immediately below this header.
-//
-// WARRANTY DISCLAIMER.  
-//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
-//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
-//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
-//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
-//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
-//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
-//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
-//
-// LIMITATION OF LIABILITY.  
-//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
-//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
-//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
-//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
-//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
-//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
-//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
-//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
-//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
-//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
-//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
-//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
-//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
-//     APPLY TO LICENSEE.
-//
-/////////////////////////////////////////////////////////////////////////////
-
-
-/////////////////////////////////////////////////////////////////////////////
-//           _____       
-//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
-//         / /       \   
-//        / /  ..    /   `IP_MODULE_NAME(efx_sdram_controller).v
-//       / / .'     /    
-//    __/ /.'      /     Description:
-//   __   \       /      SDRAM controller top module
-//  /_/ /\ \_____/ /     
-// ____/  \_______/      
-//
-// *******************************
-// Revisions:
-// 1.0 Initial rev
-//
-// *******************************
-
-module `IP_MODULE_NAME(efx_sdram_controller)
-(
-	i_aresetn,
-	i_arst,
-	i_sysclk,
-	i_sdrclk,
-	i_tACclk,
-	i_pll_locked,
-	o_pll_reset,
-	i_we,
-	i_re,
-	i_last,
-	i_addr,
-	i_din,
-	o_dout,
-	o_sdr_init_done,
-	o_wr_ack,
-	o_rd_ack,
-	o_ref_req,
-	o_rd_valid,
-	o_AXI4_AWREADY,
-	i_AXI4_AWADDR,
-	i_AXI4_AWPROT,
-	i_AXI4_AWVALID,
-	o_AXI4_WREADY,
-	i_AXI4_WDATA,
-	i_AXI4_WLAST,
-	i_AXI4_WVALID,
-	o_AXI4_BVALID,
-	i_AXI4_BREADY,
-	o_AXI4_ARREADY,
-	i_AXI4_ARADDR,
-	i_AXI4_ARPROT,
-    i_AXI4_ARVALID,
-	i_AXI4_RREADY,
-	o_AXI4_RDATA,
-	o_AXI4_RLAST,
-	o_AXI4_RVALID,
-	i_AXI4_AWID,
-	i_AXI4_AWREGION,
-	i_AXI4_AWLEN,
-	i_AXI4_AWSIZE,
-	i_AXI4_AWBURST,
-	i_AXI4_AWLOCK,
-	i_AXI4_AWCACHE,
-	i_AXI4_AWQOS,
-	i_AXI4_AWUSER,
-	i_AXI4_WSTRB,
-	i_AXI4_WUSER,
-	o_AXI4_BID,
-	o_AXI4_BRESP,					
-	o_AXI4_BUSER,	
-	i_AXI4_ARID,
-	i_AXI4_ARREGION,				
-	i_AXI4_ARLEN,
-	i_AXI4_ARSIZE,
-	i_AXI4_ARBURST,					
-	i_AXI4_ARLOCK,							
-	i_AXI4_ARCACHE,				
-	i_AXI4_ARQOS,					
-	i_AXI4_ARUSER,	
-	o_AXI4_RID,
-	o_AXI4_RRESP,						
-	o_AXI4_RUSER,
-	o_sdr_CKE,
-	o_sdr_n_CS,
-	o_sdr_n_RAS,
-	o_sdr_n_CAS,
-	o_sdr_n_WE,
-	o_sdr_BA,
-	o_sdr_ADDR,
-	o_sdr_DATA,
-	o_sdr_DATA_oe,
-	i_sdr_DATA,
-	o_sdr_DQM,
-	o_dbg_dly_cnt_b,
-	o_dbg_tRCD_done,
-	o_dbg_tRTW_done,
-	o_dbg_ref_req,
-	o_dbg_wr_ack,
-	o_dbg_rd_ack,
-	o_sdr_state,
-	o_dbg_we,
-	o_dbg_re,
-	o_dbg_last,
-	o_dbg_addr,
-	o_dbg_din,
-	o_sdr_rd_valid,
-	o_sdr_dout,
-	o_axi4_wrstate,
-	o_dbg_axi4_wlast,
-	o_axi4_rastate,
-	o_axi4_rdstate,
-	o_axi4_nwr,
-	o_re_lock,
-	o_shift_cnt,
-	o_axi4_arlen,
-	o_fifo_wr,
-	o_fifo_full,
-	o_fifo_empty,
-	o_dbg_fifo_we,
-	o_dbg_fifo_waddr,
-	o_dbg_fifo_re,
-	o_dbg_fifo_raddr,
-    o_dbg_n_CS,
-    o_dbg_n_RAS,
-    o_dbg_n_CAS,
-    o_dbg_n_WE,
-    o_dbg_BA,
-    o_dbg_ADDR,
-    o_dbg_DATA_out,
-    o_dbg_DATA_in
-);
-
-	parameter	AXI_AWADDR_WIDTH	= 32;
-	parameter	AXI_WDATA_WIDTH		= 32;
-	parameter	AXI_ARADDR_WIDTH	= 32;
-	parameter	AXI_RDATA_WIDTH		= 32;
-                                    
-	parameter	fSYS_MHz		= 100;
-	parameter	fCK_MHz			= 100;
-	parameter   DATA_RATE       = 1;
-	parameter	DDIO_TYPE		= "SOFT";
-	parameter	tPWRUP			= 100;			// 100 us
-	parameter	tRAS			= 44;			// 44 ns
-	parameter	tRAS_MAX		= 120;		// 120 us
-	parameter	tRC			    = 66;			// 66 ns
-	parameter	tRCD			= 20;			// 20 ns
-	parameter	tREF			= 64;			// 64 ms
-	parameter	tRFC			= 66;			// 66 ns
-	parameter	tRP			    = 20;			// 20 ns
-	parameter	tWR			    = 2;			// 1 CK+7.5 ns
-	parameter	tMRD			= 2;			// 2 CK
-	parameter	CL			    = 3;			// 3 CK
-	parameter	BL			    = 1;
-    parameter   tIORT_u		    = 2;
-	parameter	BA_WIDTH		= 2;
-	parameter	ROW_WIDTH		= 10;
-	parameter	COL_WIDTH		= 10;
-	parameter	DQ_WIDTH		= 8;	// x4; x8
-	parameter	DQ_GROUP		= 8;
-	parameter   SDRAM_MODE      = "AXI4";
-	
-	//----- parameter not configurable by user----
-	parameter	AXI_AWID_WIDTH		= 4;
-	parameter	AXI_AWUSER_WIDTH	= 2;
-	parameter	AXI_WUSER_WIDTH		= 2;
-	parameter	AXI_BID_WIDTH		= 4;
-	parameter	AXI_BUSER_WIDTH		= 2;
-	parameter	AXI_ARID_WIDTH		= 4;
-	parameter	AXI_ARUSER_WIDTH	= 2;
-	parameter	AXI_RUSER_WIDTH		= 2;
-	
-	//Common
-	input i_aresetn;
-	input i_arst;
-	input i_sysclk;
-	input i_sdrclk;
-	input i_tACclk;
-	input i_pll_locked;
-	output	o_pll_reset;
-	
-	//Native 
-	input	i_we;
-	input	i_re;
-	input	i_last;
-	input	[(BA_WIDTH+ROW_WIDTH+COL_WIDTH)	-1:0]				i_addr;
-	input	[DATA_RATE	*DQ_GROUP		*DQ_WIDTH		-1:0]	i_din;
-	output	[DATA_RATE	*DQ_GROUP		*DQ_WIDTH		-1:0]	o_dout;
-	output	o_sdr_init_done;
-	output	o_wr_ack;
-	output	o_rd_ack;
-	output	o_ref_req;
-	output	o_rd_valid;
-	
-	//AXI4
-	output wire o_AXI4_AWREADY;
-	input  	[AXI_AWADDR_WIDTH-1:0] i_AXI4_AWADDR;
-	input  	[2:0] i_AXI4_AWPROT;
-	input  	i_AXI4_AWVALID;
-	
-	output 	o_AXI4_WREADY;
-	input  	[AXI_WDATA_WIDTH-1:0] i_AXI4_WDATA;
-	input  	i_AXI4_WLAST;
-	input  	i_AXI4_WVALID;
-	
-	output 	o_AXI4_BVALID;
-	input 	i_AXI4_BREADY;
-	
-	output 	o_AXI4_ARREADY;
-	input 	[AXI_ARADDR_WIDTH-1:0] i_AXI4_ARADDR;
-	input 	[2:0] i_AXI4_ARPROT;
-    input 	i_AXI4_ARVALID;
-	
-	input 	i_AXI4_RREADY;
-	output	[AXI_RDATA_WIDTH-1:0] o_AXI4_RDATA;
-	output 	o_AXI4_RLAST;
-	output  o_AXI4_RVALID;
-	
-	input	[AXI_AWID_WIDTH-1:0] i_AXI4_AWID;
-	input	[3:0] i_AXI4_AWREGION;
-	input	[7:0] i_AXI4_AWLEN;
-	input	[2:0] i_AXI4_AWSIZE;
-	input	[1:0] i_AXI4_AWBURST;
-	input  	i_AXI4_AWLOCK;
-	input	[3:0] i_AXI4_AWCACHE;
-	input	[3:0] i_AXI4_AWQOS;
-	input	[AXI_AWUSER_WIDTH-1:0] i_AXI4_AWUSER;
-	input	[AXI_WDATA_WIDTH/8-1:0] i_AXI4_WSTRB;
-	input	[AXI_WUSER_WIDTH-1:0] i_AXI4_WUSER;
-	
-	output	[AXI_BID_WIDTH-1:0] o_AXI4_BID;
-	output	[1:0] o_AXI4_BRESP;					
-	output	[AXI_BUSER_WIDTH-1:0] o_AXI4_BUSER;	
-	
-	input	[AXI_ARID_WIDTH-1:0] i_AXI4_ARID;
-	input	[3:0] i_AXI4_ARREGION;				
-	input	[7:0] i_AXI4_ARLEN;
-	input	[2:0] i_AXI4_ARSIZE;
-	input	[1:0] i_AXI4_ARBURST;					
-	input	i_AXI4_ARLOCK;							
-	input	[3:0] i_AXI4_ARCACHE;				
-	input	[3:0] i_AXI4_ARQOS;					
-	input	[AXI_ARUSER_WIDTH-1:0] i_AXI4_ARUSER;	
-	
-	output	[AXI_ARID_WIDTH-1:0] o_AXI4_RID;
-	output	[1:0] o_AXI4_RRESP;						
-	output	[AXI_RUSER_WIDTH-1:0] o_AXI4_RUSER;
-	
-	output	[DATA_RATE							-1:0]	o_sdr_CKE;
-	output	[DATA_RATE							-1:0]	o_sdr_n_CS;
-	output	[DATA_RATE							-1:0]	o_sdr_n_RAS;
-	output	[DATA_RATE							-1:0]	o_sdr_n_CAS;
-	output	[DATA_RATE							-1:0]	o_sdr_n_WE;
-	output	[DATA_RATE	*BA_WIDTH				-1:0]	o_sdr_BA;
-	output	[DATA_RATE	*ROW_WIDTH				-1:0]	o_sdr_ADDR;
-	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_sdr_DATA;
-	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_sdr_DATA_oe;
-	input	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	i_sdr_DATA;
-	output	[DATA_RATE	*DQ_GROUP				-1:0]	o_sdr_DQM;
-	
-	// Debug port
-	output	[5:0] o_dbg_dly_cnt_b;
-	output	o_dbg_tRCD_done;
-	output	o_dbg_tRTW_done;
-	output	o_dbg_ref_req;
-	output	o_dbg_wr_ack;
-	output	o_dbg_rd_ack;
-	output	[3:0] o_sdr_state;
-	output	o_dbg_we;
-	output	o_dbg_re;
-	output	o_dbg_last;
-	output	[BA_WIDTH+ROW_WIDTH+COL_WIDTH-1:0] o_dbg_addr;
-	output	[AXI_WDATA_WIDTH-1:0] o_dbg_din;
-	output	o_sdr_rd_valid;
-	output	[DATA_RATE*DQ_GROUP*DQ_WIDTH+AXI_ARID_WIDTH:0] o_sdr_dout;
-	output	[1:0] o_axi4_wrstate;
-	output	o_dbg_axi4_wlast;
-	output	[1:0] o_axi4_rastate;
-	output	[1:0] o_axi4_rdstate;
-	output	o_axi4_nwr;
-	output	o_re_lock;
-	output	[6:0] o_shift_cnt;
-	output	[7:0] o_axi4_arlen;
-	output	o_fifo_wr;
-	output	o_fifo_full;
-	output	o_fifo_empty;
-	output	o_dbg_fifo_we;
-	output	[7:0] o_dbg_fifo_waddr;
-	output	o_dbg_fifo_re;
-	output	[7:0] o_dbg_fifo_raddr;
-	
-	output	[DATA_RATE							-1:0]	o_dbg_n_CS;
-	output	[DATA_RATE							-1:0]	o_dbg_n_RAS;
-	output	[DATA_RATE							-1:0]	o_dbg_n_CAS;
-	output	[DATA_RATE							-1:0]	o_dbg_n_WE;
-	output	[DATA_RATE	*BA_WIDTH				-1:0]	o_dbg_BA;
-	output	[DATA_RATE	*ROW_WIDTH				-1:0]	o_dbg_ADDR;
-	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_dbg_DATA_out;
-	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_dbg_DATA_in;
-	
-generate
-   if (SDRAM_MODE == "AXI4") begin
-   `IP_MODULE_NAME(axi4_sdram_controller)
-   #(
-	.AXI_AWADDR_WIDTH	(AXI_AWADDR_WIDTH),
-	.AXI_WDATA_WIDTH	(AXI_WDATA_WIDTH),
-	.AXI_ARADDR_WIDTH	(AXI_ARADDR_WIDTH),
-	.AXI_RDATA_WIDTH	(AXI_RDATA_WIDTH),
-	.fSYS_MHz			(fSYS_MHz),
-	.fCK_MHz			(fCK_MHz),
-	.DDIO_TYPE	        (DDIO_TYPE),
-	.tPWRUP		        (tPWRUP),
-	.tRAS		        (tRAS),
-	.tRAS_MAX	        (tRAS_MAX),
-	.tRC		        (tRC),
-	.tRCD		        (tRCD),
-	.tREF		        (tREF),
-	.tRFC		        (tRFC),
-	.tRP		        (tRP),
-	.tWR		        (tWR),
-	.tMRD		        (tMRD),
-	.CL			        (CL),
-	.BL			        (BL),
-	.DATA_RATE          (DATA_RATE),
-	.tIORT_u		    (tIORT_u),
-	.BA_WIDTH	        (BA_WIDTH),
-	.ROW_WIDTH	        (ROW_WIDTH),
-	.COL_WIDTH	        (COL_WIDTH),
-	.DQ_WIDTH	        (DQ_WIDTH),
-	.DQ_GROUP	        (DQ_GROUP),
-    .AXI_AWID_WIDTH	    (AXI_AWID_WIDTH	     ),
-    .AXI_AWUSER_WIDTH   (AXI_AWUSER_WIDTH    ),
-    .AXI_WUSER_WIDTH	(AXI_WUSER_WIDTH	 ),
-    .AXI_BID_WIDTH	    (AXI_BID_WIDTH	     ),
-    .AXI_BUSER_WIDTH	(AXI_BUSER_WIDTH	 ),
-    .AXI_ARID_WIDTH	    (AXI_ARID_WIDTH	     ),
-    .AXI_ARUSER_WIDTH   (AXI_ARUSER_WIDTH    ),
-    .AXI_RUSER_WIDTH	(AXI_RUSER_WIDTH	 )
-	)
-	inst_axi4_sdram_controller
-	(
-	.i_aresetn			(i_aresetn),
-	.i_sysclk			(i_sysclk),
-	.i_sdrclk			(i_sdrclk),
-	.i_tACclk			(i_tACclk),
-	.i_pll_locked		(i_pll_locked),
-	
-	.o_AXI4_AWREADY		(o_AXI4_AWREADY),
-	.i_AXI4_AWADDR		(i_AXI4_AWADDR),
-	.i_AXI4_AWPROT		(i_AXI4_AWPROT),
-	.i_AXI4_AWVALID		(i_AXI4_AWVALID),
-	
-	.o_AXI4_WREADY		(o_AXI4_WREADY),
-	.i_AXI4_WDATA		(i_AXI4_WDATA),
-	.i_AXI4_WLAST		(i_AXI4_WLAST),
-	.i_AXI4_WVALID		(i_AXI4_WVALID),
-	
-	.o_AXI4_BVALID		(o_AXI4_BVALID),
-	.i_AXI4_BREADY		(i_AXI4_BREADY),
-	
-	.o_AXI4_ARREADY		(o_AXI4_ARREADY),
-	.i_AXI4_ARADDR		(i_AXI4_ARADDR),
-	.i_AXI4_ARPROT		(i_AXI4_ARPROT),
-	.i_AXI4_ARVALID		(i_AXI4_ARVALID),
-	
-	.i_AXI4_RREADY		(i_AXI4_RREADY),
-	.o_AXI4_RDATA		(o_AXI4_RDATA),
-	.o_AXI4_RLAST		(o_AXI4_RLAST),
-	.o_AXI4_RVALID		(o_AXI4_RVALID),
-	
-	.i_AXI4_AWID		(i_AXI4_AWID),
-	.i_AXI4_AWREGION	(i_AXI4_AWREGION),
-	.i_AXI4_AWLEN		(i_AXI4_AWLEN),
-	.i_AXI4_AWSIZE		(i_AXI4_AWSIZE),
-	.i_AXI4_AWBURST		(i_AXI4_AWBURST),
-	.i_AXI4_AWLOCK		(i_AXI4_AWLOCK),
-	.i_AXI4_AWCACHE		(i_AXI4_AWCACHE),
-	.i_AXI4_AWQOS		(i_AXI4_AWQOS),
-	.i_AXI4_AWUSER		(i_AXI4_AWUSER),
-	
-	.i_AXI4_WSTRB		(i_AXI4_WSTRB),
-	.i_AXI4_WUSER		(i_AXI4_WUSER),
-	
-	.o_AXI4_BID			(o_AXI4_BID),
-	.o_AXI4_BRESP		(o_AXI4_BRESP),
-	.o_AXI4_BUSER		(o_AXI4_BUSER),
-	
-	.i_AXI4_ARID		(i_AXI4_ARID),
-	.i_AXI4_ARREGION	(i_AXI4_ARREGION),
-	.i_AXI4_ARLEN		(i_AXI4_ARLEN),
-	.i_AXI4_ARSIZE		(i_AXI4_ARSIZE),
-	.i_AXI4_ARBURST		(i_AXI4_ARBURST),
-	.i_AXI4_ARLOCK		(i_AXI4_ARLOCK),
-	.i_AXI4_ARCACHE		(i_AXI4_ARCACHE),
-	.i_AXI4_ARQOS		(i_AXI4_ARQOS),
-	.i_AXI4_ARUSER		(i_AXI4_ARUSER),
-	
-	.o_AXI4_RID			(o_AXI4_RID),
-	.o_AXI4_RRESP		(o_AXI4_RRESP),
-	.o_AXI4_RUSER		(o_AXI4_RUSER),
-	
-	.o_sdr_CKE			(o_sdr_CKE),
-	.o_sdr_n_CS			(o_sdr_n_CS),
-	.o_sdr_n_RAS		(o_sdr_n_RAS),
-	.o_sdr_n_CAS		(o_sdr_n_CAS),
-	.o_sdr_n_WE			(o_sdr_n_WE),
-	.o_sdr_BA			(o_sdr_BA),
-	.o_sdr_ADDR			(o_sdr_ADDR),
-	.o_sdr_DATA			(o_sdr_DATA),
-	.o_sdr_DATA_oe		(o_sdr_DATA_oe),
-	.i_sdr_DATA			(i_sdr_DATA),
-	.o_sdr_DQM			(o_sdr_DQM),
-	
-	.o_sdr_state		(o_sdr_state),
-	.o_dbg_we			(o_dbg_we),
-	.o_dbg_re			(o_dbg_re),
-	.o_dbg_last			(o_dbg_last),
-	.o_dbg_addr			(o_dbg_addr),
-	.o_dbg_din			(o_dbg_din),
-	.o_dbg_wr_ack		(o_dbg_wr_ack),
-	.o_dbg_rd_ack		(o_dbg_rd_ack),
-	.o_sdr_rd_valid		(o_sdr_rd_valid),
-	.o_dbg_ref_req		(o_dbg_ref_req),
-	.o_sdr_dout			(o_sdr_dout),
-	.o_axi4_wrstate		(o_axi4_wrstate),
-	.o_dbg_axi4_wlast	(o_dbg_axi4_wlast),
-	.o_axi4_rastate		(o_axi4_rastate),
-	.o_axi4_rdstate		(o_axi4_rdstate),
-	.o_axi4_nwr			(o_axi4_nwr),
-	.o_re_lock			(o_re_lock),
-	.o_shift_cnt		(o_shift_cnt),
-	.o_axi4_arlen		(o_axi4_arlen),
-	.o_fifo_wr			(o_fifo_wr),
-	.o_fifo_full		(o_fifo_full),
-	.o_fifo_empty		(o_fifo_empty),
-	.o_dbg_fifo_we		(o_dbg_fifo_we),
-	.o_dbg_fifo_waddr	(o_dbg_fifo_waddr),
-	.o_dbg_fifo_re		(o_dbg_fifo_re),
-	.o_dbg_fifo_raddr	(o_dbg_fifo_raddr),
-	
-	.o_dbg_n_CS			(o_dbg_n_CS),
-	.o_dbg_n_RAS		(o_dbg_n_RAS),
-	.o_dbg_n_CAS		(o_dbg_n_CAS),
-	.o_dbg_n_WE			(o_dbg_n_WE),
-	.o_dbg_BA			(o_dbg_BA),
-	.o_dbg_ADDR			(o_dbg_ADDR),
-	.o_dbg_DATA_out		(o_dbg_DATA_out),
-	.o_dbg_DATA_in		(o_dbg_DATA_in)
-);
-end
-else begin
-`IP_MODULE_NAME(sdram_controller)
-#(
-	.fSYS_MHz			(fSYS_MHz),
-	.fCK_MHz			(fCK_MHz),
-	.REF_LATENCY		(2),
-	.tIORT_u	        (tIORT_u),
-	.DDIO_TYPE			(DDIO_TYPE),	
-	.tPWRUP				(tPWRUP),
-	.tRAS				(tRAS),
-	.tRAS_MAX			(tRAS_MAX),
-	.tRC				(tRC),
-	.tRCD				(tRCD),
-	.tREF				(tREF),
-	.tRFC				(tRFC),
-	.tRP				(tRP),
-	.tWR				(tWR),
-	.tMRD				(tMRD),
-	.CL					(CL),
-	.BL					(BL),
-	.BA_WIDTH			(BA_WIDTH),
-	.ROW_WIDTH			(ROW_WIDTH),
-	.COL_WIDTH			(COL_WIDTH),
-    .DATA_RATE          (DATA_RATE),
-	.DQ_WIDTH			(DQ_WIDTH),
-	.DQ_GROUP			(DQ_GROUP)
-)
-inst_sdram_controller
-(
-	.i_arst				(i_arst),
-	.i_sysclk			(i_sysclk),
-	.i_sdrclk			(i_sdrclk),
-	.i_tACclk			(i_tACclk),
-	.i_pll_locked		(i_pll_locked),
-	
-	.i_we				(i_we),
-	.i_re				(i_re),
-	.i_last				(i_last),
-	.i_addr				(i_addr),
-	.i_din				(i_din),
-	.o_dout				(o_dout),
-	.o_sdr_state		(o_sdr_state),
-	.o_sdr_init_done	(o_sdr_init_done),
-	.o_wr_ack			(o_wr_ack),
-	.o_rd_ack			(o_rd_ack),
-	.o_ref_req			(o_ref_req),
-	.o_rd_valid			(o_rd_valid),
-	
-	.o_sdr_CKE			(o_sdr_CKE),
-	.o_sdr_n_CS			(o_sdr_n_CS),
-	.o_sdr_n_RAS		(o_sdr_n_RAS),
-	.o_sdr_n_CAS		(o_sdr_n_CAS),
-	.o_sdr_n_WE			(o_sdr_n_WE),
-	.o_sdr_BA			(o_sdr_BA),
-	.o_sdr_ADDR			(o_sdr_ADDR),
-	.o_sdr_DATA			(o_sdr_DATA),
-	.o_sdr_DATA_oe		(o_sdr_DATA_oe),
-	.i_sdr_DATA			(i_sdr_DATA),
-	.o_sdr_DQM			(o_sdr_DQM),
-	
-	.o_dbg_dly_cnt_b	(o_dbg_dly_cnt_b),
-	.o_dbg_tRCD_done	(o_dbg_tRCD_done),
-	.o_dbg_tRTW_done	(o_dbg_tRTW_done),
-	.o_dbg_ref_req		(o_dbg_ref_req),
-	.o_dbg_wr_ack		(o_dbg_wr_ack),
-	.o_dbg_rd_ack		(o_dbg_rd_ack),
-	.o_dbg_n_CS			(o_dbg_n_CS),
-	.o_dbg_n_RAS		(o_dbg_n_RAS),
-	.o_dbg_n_CAS		(o_dbg_n_CAS),
-	.o_dbg_n_WE			(o_dbg_n_WE),
-	.o_dbg_BA			(o_dbg_BA),
-	.o_dbg_ADDR			(o_dbg_ADDR),
-	.o_dbg_DATA_out		(o_dbg_DATA_out),
-	.o_dbg_DATA_in		(o_dbg_DATA_in)
-);
-end
-endgenerate
-
-endmodule
-
-/////////////////////////////////////////////////////////////////////////////
-//           _____       
-//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
-//         / /       \   
-//        / /  ..    /   `IP_MODULE_NAME(sdram_controller).v
-//       / / .'     /    
-//    __/ /.'      /     Description:
-//   __   \       /      sdram controller top with native interface
-//  /_/ /\ \_____/ /     
-// ____/  \_______/      
-//
-// *******************************
-// Revisions:
-//
-// 1.0 Initial rev
-// *******************************
-////////////////////////////////////////////////////////////////
-
-module `IP_MODULE_NAME(sdram_controller)
-#(
-	parameter	fSYS_MHz		= 100,
-	parameter	fCK_MHz			= 100,
-	parameter	REF_LATENCY		= 2,			// 2 for Native interface, 4 for AXI interface
-	parameter	DDIO_TYPE		= "SOFT",		// SOFT, RTL
-												// HARD, Interface Designer
-	//sdram parameters
-	parameter	tPWRUP			= 100,			// 100 us
-	parameter	tRAS			= 44,			// 44 ns
-	parameter	tRAS_MAX		= 120,			// 120 us
-	parameter	tRC				= 66,		// 66 ns
-	parameter	tRCD			= 20,			// 20 ns
-	parameter	tREF			= 64,			// 64 ms
-	parameter	tRFC			= 66,			// 66 ns
-	parameter	tRP				= 20,		// 20 ns
-	parameter	tWR				= 2,		// 1 CK+7.5 ns
-	parameter	tMRD			= 2,			// 2 CK
-	parameter	CL				= 3,		// 3 CK
-	parameter	BL				= 1,
-	parameter	BA_WIDTH		= 2,
-	parameter	ROW_WIDTH		= 13,
-	parameter	COL_WIDTH		= 10,
-	parameter	DATA_RATE		= 1,	// 1, 2
-    parameter   tIORT_u		    = 2,
-	parameter	DQ_WIDTH		= 8,	// x4, x8
-	parameter	DQ_GROUP		= 8
-	//			x4	x8	x16	x32
-	// DQ_WIDTH	4	8	8	8
-	// DQ_GROUP	1	1	2	4
-)
-(
-	input	i_arst,
-	input	i_sysclk,
-	input	i_sdrclk,	// x2 i_sysclk
-	input	i_tACclk,	// x2 i_sysclk
-	input	i_pll_locked,
-	
-	input	i_we,
-	input	i_re,
-	input	i_last,
-	input	[			(BA_WIDTH+ROW_WIDTH+COL_WIDTH)	-1:0]	i_addr,
-	input	[DATA_RATE	*DQ_GROUP		*DQ_WIDTH		-1:0]	i_din,
-	output	[DATA_RATE	*DQ_GROUP		*DQ_WIDTH		-1:0]	o_dout,
-	output	[3:0]o_sdr_state,
-	output	o_sdr_init_done,
-	output	o_wr_ack,
-	output	o_rd_ack,
-	output	o_ref_req,
-	output	o_rd_valid,
-	
-	output	[DATA_RATE							-1:0]	o_sdr_CKE,
-	output	[DATA_RATE							-1:0]	o_sdr_n_CS,
-	output	[DATA_RATE							-1:0]	o_sdr_n_RAS,
-	output	[DATA_RATE							-1:0]	o_sdr_n_CAS,
-	output	[DATA_RATE							-1:0]	o_sdr_n_WE,
-	output	[DATA_RATE	*BA_WIDTH				-1:0]	o_sdr_BA,
-	output	[DATA_RATE	*ROW_WIDTH				-1:0]	o_sdr_ADDR,
-	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_sdr_DATA,
-	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_sdr_DATA_oe,
-	input	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	i_sdr_DATA,
-	output	[DATA_RATE	*DQ_GROUP				-1:0]	o_sdr_DQM,
-	
-	// Debug port
-	output	[5:0]o_dbg_dly_cnt_b,
-	output	o_dbg_tRCD_done,
-	output	o_dbg_tRTW_done,
-	output	o_dbg_ref_req,
-	output	o_dbg_wr_ack,
-	output	o_dbg_rd_ack,
-	output	[DATA_RATE							-1:0]	o_dbg_n_CS,
-	output	[DATA_RATE							-1:0]	o_dbg_n_RAS,
-	output	[DATA_RATE							-1:0]	o_dbg_n_CAS,
-	output	[DATA_RATE							-1:0]	o_dbg_n_WE,
-	output	[DATA_RATE	*BA_WIDTH				-1:0]	o_dbg_BA,
-	output	[DATA_RATE	*ROW_WIDTH				-1:0]	o_dbg_ADDR,
-	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_dbg_DATA_out,
-	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_dbg_DATA_in
-);
-`ifdef RTL_SIM
-    localparam   tIORT		    = (DATA_RATE == 2 && CL == 2) ? 1 : 0;
-`else
-    localparam   tIORT		    = tIORT_u;
-`endif
-localparam  PARTIAL_FEATURES = (fCK_MHz == 166 && fSYS_MHz == 166) ? 1 : 0;  //partial features only applicable to 166Mhz fullrate
-localparam  DLY_CNT_A_WIDTH	= (PARTIAL_FEATURES == 1) ? 4 : 6;
-localparam  DLY_CNT_B_WIDTH	= (PARTIAL_FEATURES == 1) ? 4 : 6;
-localparam  CHECK_ACT_BA	= (PARTIAL_FEATURES == 1) ? 1 : 4;
-localparam	BA_MSB	= BA_WIDTH+	ROW_WIDTH+	COL_WIDTH-	1;
-localparam	BA_LSB	= 			ROW_WIDTH+	COL_WIDTH;
-localparam	ROW_MSB	= 			ROW_WIDTH+	COL_WIDTH-	1;
-localparam	ROW_LSB	= 						COL_WIDTH;
-localparam	COL_MSB	=						COL_WIDTH-	1;
-localparam	COL_LSB	= 0;
-
-localparam	CYC_A	= 0;
-localparam	CYC_B	= 1;
-localparam	CYC_C	= 2;
-localparam	CYC_D	= 3;
-
-wire	[DATA_RATE							-1:0]w_sdr_CKE;
-wire	[DATA_RATE							-1:0]w_sdr_n_CS;
-wire	[DATA_RATE							-1:0]w_sdr_n_RAS;
-wire	[DATA_RATE							-1:0]w_sdr_n_CAS;
-wire	[DATA_RATE							-1:0]w_sdr_n_WE;
-wire	[DATA_RATE	*BA_WIDTH				-1:0]w_sdr_BA;
-wire	[DATA_RATE	*ROW_WIDTH				-1:0]w_sdr_ADDR;
-wire	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]w_sdr_DATA_out;
-wire	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]w_sdr_DATA_oe;
-wire	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]w_sdr_DATA_in;
-wire	[DATA_RATE	*DQ_GROUP				-1:0]w_sdr_DQM;
-
-`IP_MODULE_NAME(sdram_fsm)
-#(
-	.fSYS_MHz			(fSYS_MHz),
-	.fCK_MHz			(fCK_MHz),
-	.DLY_CNT_A_WIDTH	(DLY_CNT_A_WIDTH),
-	.DLY_CNT_B_WIDTH	(DLY_CNT_B_WIDTH),
-	.CHECK_ACT_BA		(CHECK_ACT_BA),
-	.REF_LATENCY		(REF_LATENCY),
-    .DATA_RATE	        (DATA_RATE),
-	.tPWRUP				(tPWRUP),
-	.tRAS				(tRAS),
-	.tRAS_MAX			(tRAS_MAX),
-	.tRC				(tRC),
-	.tRCD				(tRCD),
-	.tREF				(tREF),
-	.tRFC				(tRFC),
-	.tRP				(tRP),
-	.tWR				(tWR),
-	.tMRD				(tMRD),
-	.CL					(CL),
-	.BL					(BL),
-	.tIORT				(tIORT),
-	.DDIO_TYPE          (DDIO_TYPE),
-	.BA_WIDTH			(BA_WIDTH),
-	.ROW_WIDTH			(ROW_WIDTH),
-	.COL_WIDTH			(COL_WIDTH),
-	.DQ_WIDTH			(DQ_WIDTH),
-	.DQ_GROUP			(DQ_GROUP)
-)
-inst_sdram_fsm
-(
-	.i_arst				(i_arst),
-	.i_sysclk			(i_sysclk),
-	.i_pll_locked		(i_pll_locked),
-	
-	.i_we				(i_we),
-	.i_re				(i_re),
-	.i_last				(i_last),
-	.i_addr				(i_addr),
-	.i_din				(i_din),
-	.o_dout				(o_dout),
-	.o_sdr_state		(o_sdr_state),
-	.o_sdr_init_done	(o_sdr_init_done),
-	.o_wr_ack			(o_wr_ack),
-	.o_rd_ack			(o_rd_ack),
-	.o_ref_req			(o_ref_req),
-	.o_rd_valid			(o_rd_valid),
-	
-	.o_sdr_CKE			(w_sdr_CKE),
-	.o_sdr_n_CS			(w_sdr_n_CS),
-	.o_sdr_n_RAS		(w_sdr_n_RAS),
-	.o_sdr_n_CAS		(w_sdr_n_CAS),
-	.o_sdr_n_WE			(w_sdr_n_WE),
-	.o_sdr_BA			(w_sdr_BA),
-	.o_sdr_ADDR			(w_sdr_ADDR),
-	.o_sdr_DATA			(w_sdr_DATA_out),
-	.o_sdr_DATA_oe		(w_sdr_DATA_oe),
-	.i_sdr_DATA			(w_sdr_DATA_in),
-	.o_sdr_DQM			(w_sdr_DQM),
-	
-	.o_dbg_dly_cnt_b	(o_dbg_dly_cnt_b),
-	.o_dbg_tRCD_done	(o_dbg_tRCD_done),
-	.o_dbg_tRTW_done	(o_dbg_tRTW_done),
-	.o_dbg_ref_req		(o_dbg_ref_req),
-	.o_dbg_wr_ack		(o_dbg_wr_ack),
-	.o_dbg_rd_ack		(o_dbg_rd_ack),
-	.o_dbg_n_CS			(o_dbg_n_CS),
-	.o_dbg_n_RAS		(o_dbg_n_RAS),
-	.o_dbg_n_CAS		(o_dbg_n_CAS),
-	.o_dbg_n_WE			(o_dbg_n_WE),
-	.o_dbg_BA			(o_dbg_BA),
-	.o_dbg_ADDR			(o_dbg_ADDR)
-);
-
-generate if (DDIO_TYPE == "SOFT" && DATA_RATE > 1) begin
-    `IP_MODULE_NAME(sdram_io_block)
-    #(
-    	.DATA_RATE	(DATA_RATE),
-    	.BA_WIDTH	(BA_WIDTH),
-    	.ROW_WIDTH	(ROW_WIDTH),
-    	.COL_WIDTH	(COL_WIDTH),
-    	.DQ_WIDTH	(DQ_WIDTH),
-    	.DQ_GROUP	(DQ_GROUP)
-    )
-    inst_sdram_io_block
-    (
-    	.i_arst				(i_arst),
-    	.i_sysclk			(i_sysclk),
-    	.i_sdrclk			(i_sdrclk),
-    	.i_tACclk			(i_tACclk),
-    	.i_pll_locked		(i_pll_locked),
-    	
-    	.i_sdr_CKE_core		(w_sdr_CKE),
-    	.i_sdr_n_CS_core	(w_sdr_n_CS),
-    	.i_sdr_n_RAS_core	(w_sdr_n_RAS),
-    	.i_sdr_n_CAS_core	(w_sdr_n_CAS),
-    	.i_sdr_n_WE_core	(w_sdr_n_WE),
-    	.i_sdr_BA_core		(w_sdr_BA),
-    	.i_sdr_ADDR_core	(w_sdr_ADDR),
-    	.i_sdr_DATA_core	(w_sdr_DATA_out),
-    	.i_sdr_DATA_oe_core	(w_sdr_DATA_oe),
-    	.o_sdr_DATA_core	(w_sdr_DATA_in),
-    	.i_sdr_DQM_core		(w_sdr_DQM),
-    	
-    	.o_sdr_CKE_pad		(o_sdr_CKE),
-    	.o_sdr_n_CS_pad		(o_sdr_n_CS),
-    	.o_sdr_n_RAS_pad	(o_sdr_n_RAS),
-    	.o_sdr_n_CAS_pad	(o_sdr_n_CAS),
-    	.o_sdr_n_WE_pad		(o_sdr_n_WE),
-    	.o_sdr_BA_pad		(o_sdr_BA),
-    	.o_sdr_ADDR_pad		(o_sdr_ADDR),
-    	.o_sdr_DATA_pad		(o_sdr_DATA),
-    	.o_sdr_DATA_oe_pad	(o_sdr_DATA_oe),
-    	.i_sdr_DATA_pad		(i_sdr_DATA),
-    	.o_sdr_DQM_pad		(o_sdr_DQM)
-    );
-end
-else begin
-    reg		[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]r_sdr_DATA_in_tACclk_1P;
-    
-    always@(posedge i_arst or posedge i_tACclk)
-    begin
-    	if (i_arst)
-    		r_sdr_DATA_in_tACclk_1P	<= {DATA_RATE*DQ_GROUP*DQ_WIDTH{1'b0}};
-    	else
-    		r_sdr_DATA_in_tACclk_1P	<= i_sdr_DATA;
-    end
-    
-    assign	w_sdr_DATA_in	= r_sdr_DATA_in_tACclk_1P;
-    assign	o_sdr_CKE		= w_sdr_CKE;
-    assign	o_sdr_n_CS		= w_sdr_n_CS;
-    assign	o_sdr_n_RAS		= w_sdr_n_RAS;
-    assign	o_sdr_n_CAS		= w_sdr_n_CAS;
-    assign	o_sdr_n_WE		= w_sdr_n_WE;
-    assign	o_sdr_BA		= w_sdr_BA;
-    assign	o_sdr_ADDR		= w_sdr_ADDR;
-    assign	o_sdr_DATA		= w_sdr_DATA_out;
-    assign	o_sdr_DATA_oe	= w_sdr_DATA_oe;
-    assign	o_sdr_DQM		= w_sdr_DQM;     
-end
-endgenerate
-
-assign	o_dbg_DATA_out	= w_sdr_DATA_out;
-assign	o_dbg_DATA_in	= w_sdr_DATA_in;
-
-endmodule
-
-//////////////////////////////////////////////////////////////////////////////
-// Copyright (C) 2013-2019 Efinix Inc. All rights reserved.
-//
-// This   document  contains  proprietary information  which   is
-// protected by  copyright. All rights  are reserved.  This notice
-// refers to original work by Efinix, Inc. which may be derivitive
-// of other work distributed under license of the authors.  In the
-// case of derivative work, nothing in this notice overrides the
-// original author's license agreement.  Where applicable, the 
-// original license agreement is included in it's original 
-// unmodified form immediately below this header.
-//
-// WARRANTY DISCLAIMER.  
-//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
-//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
-//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
-//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
-//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
-//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
-//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
-//
-// LIMITATION OF LIABILITY.  
-//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
-//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
-//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
-//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
-//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
-//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
-//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
-//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
-//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
-//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
-//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
-//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
-//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
-//     APPLY TO LICENSEE.
-//
-/////////////////////////////////////////////////////////////////////////////
-
-/////////////////////////////////////////////////////////////////////////////
-//           _____       
-//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
-//         / /       \   
-//        / /  ..    /   `IP_MODULE_NAME(sdram_fsm).v
-//       / / .'     /    
-//    __/ /.'      /     Description:
-//   __   \       /      sdram controller state machine
-//  /_/ /\ \_____/ /     
-// ____/  \_______/      
-//
-// *******************************
-// Revisions:
-// 1.0 Initial rev
-//
-// *******************************
-
-module `IP_MODULE_NAME(sdram_fsm)
-#(
-	parameter	fSYS_MHz		= 100,
-	parameter	fCK_MHz			= 200,				// MHz
-	parameter	DLY_CNT_A_WIDTH	= 6,
-	parameter	DLY_CNT_B_WIDTH	= 6,
-	parameter	CHECK_ACT_BA	= 4,
-	parameter	REF_LATENCY		= 2,				// 
-	
-	parameter	tPWRUP			= 200,				// 100 us
-	parameter	tRAS			= 44,				// 44 ns
-	parameter	tRAS_MAX		= 120000,			// 120 us
-	parameter	tRC				= 66,				// 66 ns
-	parameter	tRCD			= 20,				// 20 ns
-	parameter	tREF			= 64,				// 64 ms
-	parameter	tRFC			= 66,				// 66 ns
-	parameter	tRP				= 20,				// 20 ns
-	parameter	tWR				= 2,				// 1 CK+7.5 ns
-	parameter	tMRD			= 2,				// 2 CK
-	parameter	CL				= 3,				// 3 CK
-	parameter	BL				= 1,
-	parameter	tIORT			= 2,
-	parameter   DDIO_TYPE       = "SOFT",
-	parameter	DATA_RATE		= 2,	
-	parameter	BA_WIDTH		= 2,
-	parameter	ROW_WIDTH		= 13,
-	parameter	COL_WIDTH		= 10,
-	parameter	DQ_WIDTH		= 8,	// x4, x8
-	parameter	DQ_GROUP		= 4
-	//			x4	x8	x16	x32
-	// DQ_WIDTH	4	8	8	8
-	// DQ_GROUP	1	1	2	4
-)
-(
-	input	i_arst,
-	input	i_sysclk,
-	input	i_pll_locked,
-	
-	input	i_we,
-	input	i_re,
-	input	i_last,
-	input	[			(BA_WIDTH+ROW_WIDTH+COL_WIDTH)	-1:0]	i_addr,
-	input	[DATA_RATE	*DQ_GROUP		*DQ_WIDTH		-1:0]	i_din,
-	output	[DATA_RATE	*DQ_GROUP		*DQ_WIDTH		-1:0]	o_dout,
-	output	[3:0]o_sdr_state,
-	output	o_sdr_init_done,
-	output	o_wr_ack,
-	output	o_rd_ack,
-	output	o_ref_req,
-	output	o_rd_valid,
-	
-	output	[DATA_RATE							-1:0]	o_sdr_CKE,
-	output	[DATA_RATE							-1:0]	o_sdr_n_CS,
-	output	[DATA_RATE							-1:0]	o_sdr_n_RAS,
-	output	[DATA_RATE							-1:0]	o_sdr_n_CAS,
-	output	[DATA_RATE							-1:0]	o_sdr_n_WE,
-	output	[DATA_RATE	*BA_WIDTH				-1:0]	o_sdr_BA,
-	output	[DATA_RATE	*ROW_WIDTH				-1:0]	o_sdr_ADDR,
-	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_sdr_DATA,
-	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_sdr_DATA_oe,
-	input	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	i_sdr_DATA,
-	output	[DATA_RATE	*DQ_GROUP				-1:0]	o_sdr_DQM,
-	
-	output	[5:0]o_dbg_dly_cnt_b,
-	output	o_dbg_tRCD_done,
-	output	o_dbg_tRTW_done,
-	output	o_dbg_ref_req,
-	output	o_dbg_wr_ack,
-	output	o_dbg_rd_ack,
-	output	[DATA_RATE							-1:0]	o_dbg_n_CS,
-	output	[DATA_RATE							-1:0]	o_dbg_n_RAS,
-	output	[DATA_RATE							-1:0]	o_dbg_n_CAS,
-	output	[DATA_RATE							-1:0]	o_dbg_n_WE,
-	output	[DATA_RATE	*BA_WIDTH				-1:0]	o_dbg_BA,
-	output	[DATA_RATE	*ROW_WIDTH				-1:0]	o_dbg_ADDR
-);
-
-function integer log2;
-	input	integer	val;
-	integer	i;
-	begin
-		log2 = 0;
-		for (i=0; 2**i<val; i=i+1)
-			log2 = i+1;
-	end
-endfunction
-
-localparam	DLY_CNT_C_WIDTH	= 16;  // counter for tPWRUP & tRAS_MAX
-localparam	DLY_CNT_D_WIDTH	= 17;  // counter for tREF
-	
-//localparam	tCK		= (1000/fCK_MHz);
-//+1 for parameter with minimum value, -1 for parameter wth maximum value
-localparam	nPWRUP	= tPWRUP/(1000/fSYS_MHz) + 1;
-localparam	nRAS	= tRAS/(1000/fSYS_MHz) + 1;
-localparam	nRAS_MAX= tRAS_MAX/(1000/fSYS_MHz);
-localparam	nRC		= tRC/(1000/fSYS_MHz) + 1;
-localparam	nRCD	= tRCD/(1000/fSYS_MHz) + 1;
-localparam	nREF	= (tREF/(2**ROW_WIDTH)/100)/(1000/fSYS_MHz);
-localparam	nRFC	= tRFC/(1000/fSYS_MHz) + 1;
-localparam	nRP		= tRP/(1000/fSYS_MHz) + 1;
-localparam	nRTP	= CL-1'b1;
-localparam	nRTW	= CL+tIORT;
-
-//						 CRCW
-//						  AA
-//						 SSSE
-localparam	c_NOP	= 4'b1111;
-localparam	c_ACT	= 4'b0011;
-localparam	c_RD	= 4'b0101;
-localparam	c_WR	= 4'b0100;
-localparam	c_BT	= 4'b0110;
-localparam	c_PRE	= 4'b0010;
-localparam	c_REF	= 4'b0001;
-localparam	c_MRS	= 4'b0000;
-
-localparam	BA_MSB	= BA_WIDTH+	ROW_WIDTH+	COL_WIDTH-	1;
-localparam	BA_LSB	= 			ROW_WIDTH+	COL_WIDTH;
-localparam	ROW_MSB	= 			ROW_WIDTH+	COL_WIDTH-	1;
-localparam	ROW_LSB	= 						COL_WIDTH;
-localparam	COL_MSB	=						COL_WIDTH-	1;
-localparam	COL_LSB	= 0;
-
-// M2-M0
-localparam	BL1	= 3'b000;
-localparam	BL2	= 3'b001;
-localparam	BL4	= 3'b010;
-localparam	BL8	= 3'b011;
-localparam	BLP	= 3'b111;
-// M3
-localparam	SEQ	= 1'b0;
-localparam	INT	= 1'b1;
-// M6-M4
-localparam	CL1	= 3'b001;
-localparam	CL2	= 3'b010;
-localparam	CL3	= 3'b011;
-// M8-M7
-localparam	STD	= 2'b00;
-// M9
-localparam	PBL	= 1'b0;
-localparam	SLA	= 1'b1;
-
-localparam	BURST_LENGTH	= (BL == 1)? BL1 :
-								(BL == 2)? BL2 :
-								  (BL == 4)? BL4 :	
-								    (BL == 8)? BL8 : BL1;	
-localparam	BURST_TYPE		= SEQ;
-localparam	CAS_LATENCY		= CL;
-localparam	OP_MODE			= PBL;
-
-localparam	s_POWER_UP	= 4'b0000;
-localparam	s_INIT_CKE	= 4'b0001;
-localparam	s_INIT_PRE	= 4'b0010;
-localparam	s_INIT_REF0	= 4'b0011;
-localparam	s_INIT_REF1	= 4'b0100;
-localparam	s_INIT_MRS	= 4'b0101;
-localparam	s_IDLE		= 4'b0110;
-localparam	s_ACT		= 4'b0111;
-localparam	s_PRE		= 4'b1000;
-localparam	s_REF		= 4'b1001;
-reg		[3:0]r_sdr_state_1P;
-
-localparam	PRE_ALL		= 1'b1;
-localparam	PRE_SINGLE	= 1'b0;
-
-localparam	CYC_A	= 0;
-localparam	CYC_B	= 1;
-localparam	CYC_C	= 2;
-localparam	CYC_D	= 3;
-
-`ifdef RTL_SIM
-    localparam	RD_PIPE	= (DATA_RATE == 1 && DDIO_TYPE == "HARD") ? CL+tIORT+2 :	
-	                    (DATA_RATE == 1 && DDIO_TYPE == "SOFT") ? CL+tIORT+2 : CL+tIORT+3;
-`else
-    localparam	RD_PIPE	= (DATA_RATE == 1 && DDIO_TYPE == "HARD") ? CL+tIORT+2 :	
-	                    CL+tIORT+3;
-`endif	                    
-	                    
-(* syn_preserve = "TRUE" *)reg		[DLY_CNT_A_WIDTH-1:0]r_dly_cnt_a_1P;
-(* syn_preserve = "TRUE" *)reg		[DLY_CNT_B_WIDTH-1:0]r_dly_cnt_b_1P;
-(* syn_preserve = "TRUE" *)reg		[DLY_CNT_C_WIDTH-1:0]r_dly_cnt_c_1P;
-(* syn_preserve = "TRUE" *)reg		[DLY_CNT_D_WIDTH-1:0]r_dly_cnt_d_1P;
-reg		r_sdr_init_done_1P;
-reg		r_tRAS_done_1P;
-reg		[REF_LATENCY-1:0]r_tRAS_MAX_done_1P;
-reg		r_tRCD_done_1P;
-reg		r_tRTP_done_1P;
-reg		r_tRTW_done_1P;
-reg		r_tWR_done_1P;
-reg		r_tRC_done_1P;
-
-reg		r_wr_ack_1P;
-reg		[RD_PIPE:0]r_rd_ack_P;
-
-reg		[ROW_WIDTH:0]r_act_row_1P[0:3];
-reg		[BA_WIDTH+ROW_WIDTH-1:0]r_act_addr_1P;
-
-reg		r_tRAS_MAX_1P;
-reg		r_tRAS_MAX_2P;
-
-reg     r_pre_allbank;
-
-reg		r_oscclk_1P;
-reg		[REF_LATENCY-1:0]r_ref_req_1P;
-reg	    [6:0]	         r_sysclk_cnt_100_1P;
-reg		[DATA_RATE							-1:0]	r_sdr_cke_1P;
-reg		[DATA_RATE	*4						-1:0]	r_sdr_cmd_1P;
-reg		[DATA_RATE	*BA_WIDTH				-1:0]	r_sdr_ba_1P;
-reg		[DATA_RATE	*ROW_WIDTH				-1:0]	r_sdr_addr_1P;
-reg		[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	r_sdr_dq_1P;
-reg		[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	r_sdr_dqoe_1P;
-reg		[DATA_RATE	*DQ_GROUP				-1:0]	r_sdr_dm_1P;
-
-reg		[DATA_RATE	*4						-1:0]	r_sdr_cmd_2P;
-reg		[DATA_RATE	*BA_WIDTH				-1:0]	r_sdr_ba_2P;
-reg		[DATA_RATE	*ROW_WIDTH				-1:0]	r_sdr_addr_2P;
-reg		[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	r_sdr_dqoe_2P;
-reg		[DATA_RATE	*DQ_GROUP				-1:0]	r_sdr_dm_2P;
-
-reg		[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	r_sdr_dqin_1P;
-
-integer	c, b;
-
-wire	w_oscclk;
-wire	w_tRAS_MAX;
-wire	[BA_WIDTH-1:0]w_BA;
-wire	[ROW_WIDTH-1:0]w_ROW;
-wire	w_AFLAG;
-wire	[ROW_WIDTH-1:0]w_AROW;
-wire	w_pre_req;
-
-assign	w_BA	= i_addr[BA_MSB:BA_LSB];
-assign	w_ROW	= i_addr[ROW_MSB:ROW_LSB];
-assign	w_AFLAG	= r_act_row_1P[w_BA][ROW_WIDTH];
-assign	w_AROW	= r_act_row_1P[w_BA][ROW_WIDTH-1:0];
-
-initial
-begin
-	$display("RD_PIPE = %d\n", RD_PIPE);
-	$display("nPWRUP = %d\n", nPWRUP);
-	$display("nRAS = %d\n", nRAS);
-	$display("nRC = %d\n", nRC);
-	$display("nREF = %d\n", nREF);
-	$display("nRCD = %d\n", nRCD);
-	$display("nRFC = %d\n", nRFC);
-	$display("nRP = %d\n", nRP);
-end
-
-genvar k;
-generate
-
-    always@(posedge i_arst or posedge i_sysclk)
-    begin
-    	if (i_arst)
-    		r_sysclk_cnt_100_1P	<= {7{1'b0}};
-    	else
-    	begin
-    		if (r_sysclk_cnt_100_1P == 7'd98) begin
-    		    r_sysclk_cnt_100_1P	<= {7{1'b0}};
-    		end
-    		else if (r_dly_cnt_d_1P == nREF-1) begin
-    		    r_sysclk_cnt_100_1P	<= r_sysclk_cnt_100_1P+7'd1;
-    		end
-    		
-    	end
-    end
-	
-	if (CHECK_ACT_BA == 4)
-		assign	w_pre_req	= (~w_AFLAG) || (w_AROW != w_ROW);
-	else
-		assign	w_pre_req	= r_act_addr_1P != {w_BA, w_ROW};
-	
-	for (k=0; k<REF_LATENCY-1; k=k+1)
-	begin: REF_LATENCY_MAP
-		always@(posedge i_arst or posedge i_sysclk)
-		begin
-			if (i_arst)
-			begin
-				r_ref_req_1P[k+1]	<= 1'b0;
-			end
-			else if (r_sdr_state_1P == s_REF && r_dly_cnt_a_1P == nRFC)
-			begin
-				r_ref_req_1P[k+1]	<= 1'b0;
-			end
-			else
-			begin
-				r_ref_req_1P[k+1]	<= r_ref_req_1P[k];
-			end
-		end
-		
-		always@(posedge i_arst or posedge i_sysclk)
-		begin
-			if (i_arst)
-			begin
-				r_tRAS_MAX_done_1P[k+1]	<= 1'b0;
-			end
-			else
-			begin
-				r_tRAS_MAX_done_1P[k+1]	<= r_tRAS_MAX_done_1P[k];
-			end
-		end
-	end
-endgenerate
-
-always@(posedge i_arst or posedge i_sysclk)
-begin
-	if (i_arst)
-	begin
-		r_sdr_state_1P		<= s_POWER_UP;
-		
-		r_sdr_cke_1P		<= {DATA_RATE							{1'b0}};
-		r_sdr_cmd_1P		<= {DATA_RATE							{c_NOP}};
-		r_sdr_ba_1P			<= {DATA_RATE	*BA_WIDTH				{1'b0}};
-		r_sdr_addr_1P		<= {DATA_RATE	*ROW_WIDTH				{1'b0}};
-		r_sdr_dq_1P			<= {DATA_RATE	*DQ_GROUP	*DQ_WIDTH	{1'b0}};
-		r_sdr_dqoe_1P		<= {DATA_RATE	*DQ_GROUP	*DQ_WIDTH	{1'b0}};
-		r_sdr_dm_1P			<= {DATA_RATE	*DQ_GROUP				{1'b1}};
-		r_act_row_1P[0]		<= {ROW_WIDTH+1{1'b0}};
-		r_act_row_1P[1]		<= {ROW_WIDTH+1{1'b0}};
-		r_act_row_1P[2]		<= {ROW_WIDTH+1{1'b0}};
-		r_act_row_1P[3]		<= {ROW_WIDTH+1{1'b0}};
-		r_act_addr_1P		<= {BA_WIDTH+ROW_WIDTH{1'b0}};
-		
-		r_sdr_cmd_2P		<= {DATA_RATE							{c_NOP}};
-		r_sdr_ba_2P			<= {DATA_RATE	*BA_WIDTH				{1'b0}};
-		r_sdr_addr_2P		<= {DATA_RATE	*ROW_WIDTH				{1'b0}};
-		r_sdr_dqoe_2P		<= {DATA_RATE	*DQ_GROUP	*DQ_WIDTH	{1'b0}};
-		r_sdr_dm_2P			<= {DATA_RATE	*DQ_GROUP				{1'b1}};
-		
-		r_dly_cnt_a_1P		<= {DLY_CNT_A_WIDTH{1'b0}};
-		r_dly_cnt_b_1P		<= {DLY_CNT_B_WIDTH{1'b0}};
-		r_dly_cnt_c_1P		<= {DLY_CNT_C_WIDTH{1'b0}};
-		r_dly_cnt_d_1P      <= {DLY_CNT_D_WIDTH{1'b0}};
-		r_sdr_init_done_1P	<= 1'b0;
-		r_wr_ack_1P			<= 1'b0;
-		r_rd_ack_P[0]		<= 1'b0;
-
-		r_oscclk_1P			<= 1'b0;
-		r_ref_req_1P[0]		<= 1'b0;
-		r_tRAS_done_1P		<= 1'b0;
-		r_tRAS_MAX_done_1P[0]	<= 1'b0;
-		r_tRCD_done_1P		<= 1'b0;
-		r_tRTP_done_1P		<= 1'b0;
-		r_tRTW_done_1P		<= 1'b0;
-		r_tWR_done_1P		<= 1'b0;
-		r_tRC_done_1P		<= 1'b0;
-		
-		r_sdr_dqin_1P		<= {DQ_GROUP*DQ_WIDTH{1'b0}};
-		r_pre_allbank       <= 1'b0;
-	end
-	else if (i_pll_locked)
-	begin
-		r_sdr_cmd_1P		<= {DATA_RATE							{c_NOP}};
-		r_sdr_ba_1P			<= {DATA_RATE	*BA_WIDTH				{1'b0}};
-		r_sdr_addr_1P		<= {DATA_RATE	*ROW_WIDTH				{1'b0}};
-		r_sdr_dq_1P			<= {DATA_RATE	*DQ_GROUP	*DQ_WIDTH	{1'b0}};
-		r_sdr_dqoe_1P		<= {DATA_RATE	*DQ_GROUP	*DQ_WIDTH	{1'b0}};
-		
-		r_sdr_cmd_2P		<= r_sdr_cmd_1P;
-		r_sdr_ba_2P			<= r_sdr_ba_1P;
-		r_sdr_addr_2P		<= r_sdr_addr_1P;
-		r_sdr_dqoe_2P		<= r_sdr_dqoe_1P;
-		
-		r_wr_ack_1P			<= 1'b0;
-		r_rd_ack_P[0]		<= 1'b0;
-		
-		r_sdr_dqin_1P		<= i_sdr_DATA;
-		
-		r_dly_cnt_a_1P		<= r_dly_cnt_a_1P+1'b1;
-		r_dly_cnt_b_1P		<= r_dly_cnt_b_1P+1'b1;
-		r_dly_cnt_c_1P		<= r_dly_cnt_c_1P+1'b1;
-		
-		if (r_dly_cnt_d_1P == nREF-1)
-		    r_dly_cnt_d_1P      <= {DLY_CNT_D_WIDTH{1'b0}};
-		else if (r_sdr_state_1P != s_POWER_UP)
-		    r_dly_cnt_d_1P      <= r_dly_cnt_d_1P+1'b1;
-
-		if (r_dly_cnt_b_1P == nRAS-1'b1)
-			r_tRAS_done_1P	<= 1'b1;
-
-		if (r_sysclk_cnt_100_1P == 7'd98)
-			r_ref_req_1P[0]	<= 1'b1; 
-			
-		if (r_dly_cnt_b_1P == nRCD-1)
-			r_tRCD_done_1P	<= 1'b1;
-		
-		if (r_dly_cnt_b_1P == nRTP-1)
-			r_tRTP_done_1P	<= 1'b1;
-		
-		if (r_dly_cnt_b_1P == nRTW-1)
-			r_tRTW_done_1P	<= 1'b1;
-		
-		if (r_dly_cnt_b_1P == tWR-1)
-			r_tWR_done_1P	<= 1'b1;
-		
-		if (r_dly_cnt_b_1P == nRC-1)
-			r_tRC_done_1P	<= 1'b1;
-			
-        if (r_dly_cnt_c_1P == nRAS_MAX && r_sdr_state_1P != s_POWER_UP) 
-            r_tRAS_MAX_done_1P[0]  <= 1'b1;
-		
-		case (r_sdr_state_1P)
-			s_POWER_UP:
-			begin
-				if (r_dly_cnt_c_1P == nPWRUP)  // count power up sequence
-				begin
-					r_sdr_state_1P	<= s_INIT_CKE;
-					
-					r_sdr_cke_1P	<= {DATA_RATE{1'b1}};
-					r_dly_cnt_c_1P	<= {DLY_CNT_C_WIDTH{1'b0}};
-				end
-			end
-			
-			s_INIT_CKE:
-			begin
-				r_sdr_state_1P			<= s_INIT_PRE;
-				
-				r_sdr_cmd_1P[CYC_A+:4]	<= c_PRE;
-				r_sdr_addr_1P[CYC_A+10]	<= PRE_ALL;
-				
-				r_dly_cnt_a_1P			<= {DLY_CNT_A_WIDTH{1'b0}};
-			end
-			
-			s_INIT_PRE:
-			begin
-				if (r_dly_cnt_a_1P == nRP)
-				begin
-					r_sdr_state_1P			<= s_INIT_REF0;
-					
-					r_sdr_cmd_1P[CYC_A+:4]	<= c_REF;
-					
-					r_dly_cnt_a_1P			<= {DLY_CNT_A_WIDTH{1'b0}};
-				end
-			end
-			
-			s_INIT_REF0:
-			begin
-				if (r_dly_cnt_a_1P == nRFC)
-				begin
-					r_sdr_state_1P			<= s_INIT_REF1;
-					
-					r_sdr_cmd_1P[CYC_A+:4]	<= c_REF;
-					
-					r_dly_cnt_a_1P			<= {DLY_CNT_A_WIDTH{1'b0}};
-				end
-			end
-			
-			s_INIT_REF1:
-			begin
-				if (r_dly_cnt_a_1P == nRFC)
-				begin
-					r_sdr_state_1P					<= s_INIT_MRS;
-					
-					r_sdr_cmd_1P[CYC_A+:4]			<= c_MRS;
-					r_sdr_addr_1P[CYC_A+:ROW_WIDTH]	<= {{ROW_WIDTH-10{1'b0}},
-														OP_MODE, CAS_LATENCY,
-														BURST_TYPE, BURST_LENGTH};
-					
-					r_dly_cnt_a_1P					<= {DLY_CNT_A_WIDTH{1'b0}};
-				end
-			end
-			
-			s_INIT_MRS:
-			begin
-				if (r_dly_cnt_a_1P == tMRD-1'b1)
-				begin
-					r_sdr_state_1P		<= s_IDLE;
-					
-					r_sdr_dm_1P			<= {DATA_RATE*DQ_GROUP{1'b0}};
-					r_sdr_dm_2P			<= {DATA_RATE*DQ_GROUP{1'b0}};
-
-					r_sdr_init_done_1P	<= 1'b1;
-					r_tRCD_done_1P		<= 1'b0;
-					r_tRTP_done_1P		<= 1'b0;
-					r_tWR_done_1P		<= 1'b0;
-					r_tRC_done_1P		<= 1'b0;
-				end
-			end
-			
-			s_IDLE:
-			begin
-				if (r_ref_req_1P[REF_LATENCY-1])
-				begin
-					if (CHECK_ACT_BA == 4 && (
-						r_act_row_1P[0][ROW_WIDTH] || r_act_row_1P[1][ROW_WIDTH] ||
-						r_act_row_1P[2][ROW_WIDTH] || r_act_row_1P[3][ROW_WIDTH ]))
-					begin
-						r_sdr_state_1P				<= s_PRE;
-						
-						r_sdr_cmd_1P[CYC_A+:4]		<= c_PRE;
-						r_sdr_addr_1P[CYC_A+10]		<= PRE_ALL;
-						r_act_row_1P[0][ROW_WIDTH]	<= 1'b0;
-						r_act_row_1P[1][ROW_WIDTH]	<= 1'b0;
-						r_act_row_1P[2][ROW_WIDTH]	<= 1'b0;
-						r_act_row_1P[3][ROW_WIDTH]	<= 1'b0;
-						
-						r_dly_cnt_a_1P				<= {DLY_CNT_A_WIDTH{1'b0}};
-					end
-					else
-					begin
-						r_sdr_state_1P			<= s_REF;
-						
-						r_sdr_cmd_1P[CYC_A+:4]	<= c_REF;
-						
-						r_dly_cnt_a_1P			<= {DLY_CNT_A_WIDTH{1'b0}};
-					end
-				end
-				else if (i_we || i_re)
-				begin
-					r_sdr_state_1P		<= s_ACT;
-					
-					r_sdr_cmd_1P[CYC_A+:4]			<= c_ACT;
-					r_sdr_ba_1P[CYC_A+:BA_WIDTH]	<= i_addr[BA_MSB:BA_LSB];
-					r_sdr_addr_1P[CYC_A+:ROW_WIDTH]	<= i_addr[ROW_MSB:ROW_LSB];
-					
-					if (CHECK_ACT_BA == 4)
-						r_act_row_1P[w_BA]	<= {1'b1, w_ROW};
-					r_act_addr_1P		<= {w_BA, w_ROW};
-
-					r_dly_cnt_b_1P		  <= {DLY_CNT_B_WIDTH{1'b0}};
-					r_dly_cnt_c_1P        <= {DLY_CNT_C_WIDTH{1'b0}};
-					r_tRAS_done_1P		  <= 1'b0;
-					r_tRCD_done_1P		  <= 1'b0;
-					r_tRC_done_1P		  <= 1'b0;
-					r_tRAS_MAX_done_1P[0] <= 1'b0;
-				end
-			end
-			
-			s_ACT:
-			begin
-				if (r_ref_req_1P[REF_LATENCY-1] || r_tRAS_MAX_done_1P[REF_LATENCY-1])
-				begin
-					if (r_tRAS_done_1P && r_tWR_done_1P && r_tRTP_done_1P)
-					begin
-						r_sdr_state_1P				<= s_PRE;
-						
-						r_sdr_cmd_1P[CYC_A+:4]		<= c_PRE;
-						r_sdr_addr_1P[CYC_A+10]		<= PRE_ALL;
-						r_sdr_ba_2P                 <= r_sdr_ba_2P;
-						r_sdr_addr_2P               <= r_sdr_addr_2P;  // do not assign r_sdr_addr_1P to r_sdr_addr_2P because r_sdr_addr_1P was zero in previous clock
-						r_pre_allbank               <= 1'b1;
-						if (CHECK_ACT_BA == 4)
-						begin
-							r_act_row_1P[0][ROW_WIDTH]	<= 1'b0;
-							r_act_row_1P[1][ROW_WIDTH]	<= 1'b0;
-							r_act_row_1P[2][ROW_WIDTH]	<= 1'b0;
-							r_act_row_1P[3][ROW_WIDTH]	<= 1'b0;
-						end
-						
-						r_dly_cnt_a_1P		<= {DLY_CNT_A_WIDTH{1'b0}};
-					end
-				end
-				else if (i_we || i_re)
-				begin
-					if (w_pre_req)
-					begin
-						if (r_tRC_done_1P && r_tRAS_done_1P &&
-							r_tWR_done_1P && r_tRTP_done_1P)
-						begin
-							r_sdr_state_1P					<= s_PRE;
-							
-							r_sdr_cmd_1P[CYC_A+:4]			<= c_PRE;
-							r_sdr_ba_1P[CYC_A+:BA_WIDTH]	<= i_addr[BA_MSB:BA_LSB];
-							r_sdr_addr_1P[CYC_A+10]			<= PRE_SINGLE;
-							if (CHECK_ACT_BA == 4)
-								r_act_row_1P[w_BA][ROW_WIDTH]	<= 1'b0;
-							
-							r_dly_cnt_a_1P					<= {DLY_CNT_A_WIDTH{1'b0}};
-						end
-					end
-					else if (r_tRCD_done_1P)
-					begin
-						if (i_we && r_tRTW_done_1P)
-						begin
-							if (DATA_RATE == 1)
-							begin
-								r_sdr_cmd_1P[CYC_A+:4]			<= c_WR;
-								r_sdr_ba_2P[CYC_A+:BA_WIDTH]	<= i_addr[BA_MSB:BA_LSB];
-								r_sdr_addr_2P[CYC_A+:COL_WIDTH]	<= i_addr[COL_MSB:COL_LSB];
-							end
-							else
-							begin
-								for (c=0; c<DATA_RATE; c=c+1)
-								begin
-									r_sdr_cmd_1P[c*4+:4]				<= c_WR;
-									r_sdr_ba_2P[c*BA_WIDTH+:BA_WIDTH]	<= i_addr[BA_MSB:BA_LSB];
-									r_sdr_addr_2P[c*ROW_WIDTH+log2(DATA_RATE)+:COL_WIDTH-log2(DATA_RATE)]	<= i_addr[COL_MSB:COL_LSB+log2(DATA_RATE)];
-									for (b=0; b<log2(DATA_RATE); b=b+1)
-									begin
-										r_sdr_addr_2P[c*ROW_WIDTH+b]	<= (c & 32'hFFFFFFFF) >> b;
-									end
-								end
-							end
-							
-							r_sdr_dq_1P		<= i_din;
-							r_sdr_dqoe_1P	<= {DATA_RATE*DQ_GROUP*DQ_WIDTH{1'b1}};
-							
-							r_dly_cnt_b_1P	<= {DLY_CNT_B_WIDTH{1'b0}};
-							r_tWR_done_1P	<= 1'b0;
-							
-							r_wr_ack_1P		<= ~r_ref_req_1P[0];
-							
-							if (REF_LATENCY > 2) begin
-							    if (r_ref_req_1P[REF_LATENCY-2] || r_tRAS_MAX_done_1P[REF_LATENCY-2] || (i_last))
-							    begin
-							    		r_sdr_cmd_1P			<= {DATA_RATE{c_NOP}};
-							    		r_sdr_dqoe_1P			<= {DATA_RATE*DQ_GROUP*DQ_WIDTH{1'b0}};
-							    		r_wr_ack_1P				<= 1'b0;
-							    end
-							end
-							else begin
-							    if (r_ref_req_1P[REF_LATENCY-2] || r_tRAS_MAX_done_1P[REF_LATENCY-2] || (i_last & r_wr_ack_1P))
-							    begin
-							    		r_sdr_cmd_1P			<= {DATA_RATE{c_NOP}};
-							    		r_sdr_dqoe_1P			<= {DATA_RATE*DQ_GROUP*DQ_WIDTH{1'b0}};
-							    		r_wr_ack_1P				<= 1'b0;
-							    end
-							end
-						
-						end
-						else if (~i_we && i_re)
-						begin
-							if (DATA_RATE == 1)
-							begin
-								r_sdr_cmd_1P	<= c_RD;
-								r_sdr_ba_2P		<= i_addr[BA_MSB:BA_LSB];
-								r_sdr_addr_2P	<= i_addr[COL_MSB:COL_LSB];
-							end
-							else
-							begin
-								for (c=0; c<DATA_RATE; c=c+1)
-								begin
-									r_sdr_cmd_1P[c*4+:4]				<= c_RD;
-									r_sdr_ba_2P[c*BA_WIDTH+:BA_WIDTH]	<= i_addr[BA_MSB:BA_LSB];
-									r_sdr_addr_2P[c*ROW_WIDTH+log2(DATA_RATE)+:COL_WIDTH-log2(DATA_RATE)]	<= i_addr[COL_MSB:COL_LSB+log2(DATA_RATE)];
-									for (b=0; b<log2(DATA_RATE); b=b+1)
-									begin
-										r_sdr_addr_2P[c*ROW_WIDTH+b]	<= (c & 32'hFFFFFFFF) >> b;
-									end
-								end
-							end
-							
-							r_dly_cnt_b_1P	<= {DLY_CNT_B_WIDTH{1'b0}};
-							r_tRTW_done_1P	<= 1'b0;
-							r_tRC_done_1P	<= 1'b0;
-							
-							r_rd_ack_P[0]	<= ~r_ref_req_1P[0];
-							
-							if (REF_LATENCY > 2) begin
-							    if (r_ref_req_1P[REF_LATENCY-2] || r_tRAS_MAX_done_1P[REF_LATENCY-2] || (i_last))
-							    begin
-							    	if (r_rd_ack_P[0])
-							    	begin
-							    		r_sdr_cmd_1P			<= {DATA_RATE{c_NOP}};
-							    		r_sdr_dqoe_1P			<= {DATA_RATE*DQ_GROUP*DQ_WIDTH{1'b0}};
-							    		r_rd_ack_P[0]			<= 1'b0;
-							    	end
-							    end
-							end
-							else begin
-							    if (r_ref_req_1P[REF_LATENCY-2] || r_tRAS_MAX_done_1P[REF_LATENCY-2] || (i_last & r_rd_ack_P[0]))
-							    begin
-							    	if (r_rd_ack_P[0])
-							    	begin
-							    		r_sdr_cmd_1P			<= {DATA_RATE{c_NOP}};
-							    		r_sdr_dqoe_1P			<= {DATA_RATE*DQ_GROUP*DQ_WIDTH{1'b0}};
-							    		r_rd_ack_P[0]			<= 1'b0;
-							    	end
-							    end
-							end
-						end
-					end
-				end
-			end
-			
-			s_PRE:
-			begin
-				if (r_dly_cnt_a_1P == nRP-1'b1)
-				begin
-					if (r_ref_req_1P[REF_LATENCY-1])
-					begin
-						if (r_pre_allbank)  // check if the previous PRE is ALL_BANK or SINGLE_BANK
-						begin                   
-						    r_sdr_state_1P			<= s_REF;
-						    r_sdr_cmd_1P[CYC_A+:4]	<= c_REF;
-						    r_pre_allbank           <= 1'b0;
-						    r_dly_cnt_a_1P			<= {DLY_CNT_A_WIDTH{1'b0}};
-						end
-						else 
-						begin // if the previous PRE is SINGLE_BANK, issue PRE to ALL_BANK before trigger AUTO-refresh
-						    r_sdr_state_1P			<= s_PRE;
-						    r_sdr_cmd_1P[CYC_A+:4]	<= c_PRE;
-						    r_sdr_addr_1P[CYC_A+10] <= PRE_ALL;
-						    r_pre_allbank           <= 1'b1;
-						    if (CHECK_ACT_BA == 4)
-						    begin
-						    	r_act_row_1P[0][ROW_WIDTH]	<= 1'b0;
-						    	r_act_row_1P[1][ROW_WIDTH]	<= 1'b0;
-						    	r_act_row_1P[2][ROW_WIDTH]	<= 1'b0;
-						    	r_act_row_1P[3][ROW_WIDTH]	<= 1'b0;
-						    end
-						    r_dly_cnt_a_1P			<= {DLY_CNT_A_WIDTH{1'b0}};
-						end
-					end
-					else
-					begin
-						r_sdr_state_1P	<= s_IDLE;
-					end
-				end
-			end
-			
-			s_REF:
-			begin
-				if (r_dly_cnt_a_1P == nRFC)
-				begin
-					r_sdr_state_1P	<= s_IDLE;
-					r_ref_req_1P[0]	<= 1'b0;
-		            r_dly_cnt_d_1P  <= {DLY_CNT_D_WIDTH{1'b0}};
-				end
-			end
-		endcase
-	end
-end
-
-assign	o_sdr_state		= r_sdr_state_1P;
-assign	o_sdr_init_done	= r_sdr_init_done_1P;
-assign	o_wr_ack		= r_wr_ack_1P;
-genvar i;
-generate
-	for (i=1; i<=RD_PIPE; i=i+1)
-	begin: readback
-		always@(posedge i_arst or posedge i_sysclk)
-		begin
-			if (i_arst)
-				r_rd_ack_P[i]	<= 1'b0;
-			else
-				r_rd_ack_P[i]	<= r_rd_ack_P[i-1];
-		end
-	end
-endgenerate
-assign	o_rd_ack		= r_rd_ack_P[0];
-assign	o_ref_req		= r_ref_req_1P[0];
-assign	o_rd_valid		= r_rd_ack_P[RD_PIPE];
-assign	o_dout			= r_sdr_dqin_1P;
-
-assign	o_sdr_CKE		= r_sdr_cke_1P;
-genvar j;
-generate
-	for (j=0; j<DATA_RATE; j=j+1)
-	begin: cycle_mapping
-		assign	o_sdr_n_CS[j]	= r_sdr_cmd_2P[j*4+3];
-		assign	o_sdr_n_RAS[j]	= r_sdr_cmd_2P[j*4+2];
-		assign	o_sdr_n_CAS[j]	= r_sdr_cmd_2P[j*4+1];
-		assign	o_sdr_n_WE[j]	= r_sdr_cmd_2P[j*4+0];
-		
-		assign	o_dbg_n_CS[j]	= r_sdr_cmd_2P[j*4+3];
-		assign	o_dbg_n_RAS[j]	= r_sdr_cmd_2P[j*4+2];
-		assign	o_dbg_n_CAS[j]	= r_sdr_cmd_2P[j*4+1];
-		assign	o_dbg_n_WE[j]	= r_sdr_cmd_2P[j*4+0];
-	end
-endgenerate
-assign	o_sdr_BA		= r_sdr_ba_2P;
-assign	o_sdr_ADDR		= r_sdr_addr_2P;
-assign	o_sdr_DATA		= r_sdr_dq_1P;
-assign	o_sdr_DATA_oe	= r_sdr_dqoe_2P;
-assign	o_sdr_DQM		= r_sdr_dm_2P;
-
-assign	o_dbg_dly_cnt_b	= (DLY_CNT_B_WIDTH == 4) ? {2'b00, r_dly_cnt_b_1P} : r_dly_cnt_b_1P;
-assign	o_dbg_tRCD_done	= r_tRCD_done_1P;
-assign	o_dbg_tRTW_done	= r_tRTW_done_1P;
-assign	o_dbg_ref_req	= r_ref_req_1P[REF_LATENCY-2];
-assign	o_dbg_wr_ack	= r_wr_ack_1P;
-assign	o_dbg_rd_ack	= r_rd_ack_P[0];
-
-assign	o_dbg_BA		= r_sdr_ba_2P;
-assign	o_dbg_ADDR		= r_sdr_addr_2P;
-
-endmodule
-
-//////////////////////////////////////////////////////////////////////////////
-// Copyright (C) 2013-2019 Efinix Inc. All rights reserved.
-//
-// This   document  contains  proprietary information  which   is
-// protected by  copyright. All rights  are reserved.  This notice
-// refers to original work by Efinix, Inc. which may be derivitive
-// of other work distributed under license of the authors.  In the
-// case of derivative work, nothing in this notice overrides the
-// original author's license agreement.  Where applicable, the 
-// original license agreement is included in it's original 
-// unmodified form immediately below this header.
-//
-// WARRANTY DISCLAIMER.  
-//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
-//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
-//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
-//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
-//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
-//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
-//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
-//
-// LIMITATION OF LIABILITY.  
-//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
-//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
-//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
-//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
-//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
-//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
-//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
-//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
-//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
-//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
-//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
-//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
-//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
-//     APPLY TO LICENSEE.
-//
-/////////////////////////////////////////////////////////////////////////////
-
-/////////////////////////////////////////////////////////////////////////////
-//           _____       
-//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
-//         / /       \   
-//        / /  ..    /   `IP_MODULE_NAME(sdram_io_block).v
-//       / / .'     /    
-//    __/ /.'      /     Description:
-//   __   \       /      sdram controller I/O alignment
-//  /_/ /\ \_____/ /     
-// ____/  \_______/      
-//
-// *******************************
-// Revisions:
-// 1.0 Initial rev
-//
-// *******************************
-/////////////////////////////////////////////////////////////////////////////
-
-module `IP_MODULE_NAME(sdram_io_block)
-#(
-	parameter	DATA_RATE		= 2,		// Do not over write
-	parameter	BA_WIDTH		= 2,
-	parameter	ROW_WIDTH		= 13,
-	parameter	COL_WIDTH		= 10,
-	parameter	DQ_WIDTH		= 8,	// x4, x8
-	parameter	DQ_GROUP		= 2
-)
-(
-	input	i_arst,
-	input	i_sysclk,
-	input	i_sdrclk,
-	input	i_tACclk,
-	input	i_pll_locked,
-	
-	input	[DATA_RATE							-1:0]	i_sdr_CKE_core,
-	input	[DATA_RATE							-1:0]	i_sdr_n_CS_core,
-	input	[DATA_RATE							-1:0]	i_sdr_n_RAS_core,
-	input	[DATA_RATE							-1:0]	i_sdr_n_CAS_core,
-	input	[DATA_RATE							-1:0]	i_sdr_n_WE_core,
-	input	[DATA_RATE	*BA_WIDTH				-1:0]	i_sdr_BA_core,
-	input	[DATA_RATE	*ROW_WIDTH				-1:0]	i_sdr_ADDR_core,
-	input	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	i_sdr_DATA_core,
-	input	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	i_sdr_DATA_oe_core,
-	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_sdr_DATA_core,
-	input	[DATA_RATE	*DQ_GROUP				-1:0]	i_sdr_DQM_core,
-	
-	output	[DATA_RATE							-1:0]	o_sdr_CKE_pad,
-	output	[DATA_RATE							-1:0]	o_sdr_n_CS_pad,
-	output	[DATA_RATE							-1:0]	o_sdr_n_RAS_pad,
-	output	[DATA_RATE							-1:0]	o_sdr_n_CAS_pad,
-	output	[DATA_RATE							-1:0]	o_sdr_n_WE_pad,
-	output	[DATA_RATE	*BA_WIDTH				-1:0]	o_sdr_BA_pad,
-	output	[DATA_RATE	*ROW_WIDTH				-1:0]	o_sdr_ADDR_pad,
-	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_sdr_DATA_pad,
-	output	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	o_sdr_DATA_oe_pad,
-	input	[DATA_RATE	*DQ_GROUP	*DQ_WIDTH	-1:0]	i_sdr_DATA_pad,
-	output	[DATA_RATE	*DQ_GROUP				-1:0]	o_sdr_DQM_pad
-);
-
-localparam	BA_MSB	= BA_WIDTH+	ROW_WIDTH+	COL_WIDTH-	1;
-localparam	BA_LSB	= 			ROW_WIDTH+	COL_WIDTH;
-localparam	ROW_MSB	= 			ROW_WIDTH+	COL_WIDTH-	1;
-localparam	ROW_LSB	= 						COL_WIDTH;
-localparam	COL_MSB	=						COL_WIDTH-	1;
-localparam	COL_LSB	= 0;
-
-localparam	CYC_A	= 0;
-localparam	CYC_B	= 1;
-localparam	CYC_C	= 2;
-localparam	CYC_D	= 3;
-
-wire	[DATA_RATE*DQ_GROUP*DQ_WIDTH-1:0]w_sdr_DATA_core;
-reg		[DQ_GROUP*DQ_WIDTH-1:0]r_sdr_DATA_core_1P;
-reg		r_pll_locked_1P;
-
-genvar rate;
-
-initial
-begin
-	$display("Data Rate = %d\n", DATA_RATE);
-`ifdef RTL_SIM
-	$display("RTL_SIM\n");
-`endif
-end
-
-always@(posedge i_arst or posedge i_sysclk)
-begin
-	if (i_arst)
-	begin
-		r_pll_locked_1P	<= 1'b0;
-	end
-	else
-	begin
-		r_pll_locked_1P	<= i_pll_locked;
-	end
-end
-
-    `IP_MODULE_NAME(sync_ddio_group_out)
-    #(
-    	.DW(1),
-    	.INIT(1'b0),
-    	.SYNC("RISING")
-    )
-    inst_CKE
-    (
-    	.arst(i_arst),
-    	.d0(i_sdr_CKE_core[CYC_A]),
-    	.d1(i_sdr_CKE_core[CYC_B]),
-    	.c_x1(i_sysclk),
-    	.c_x2(i_sdrclk),
-    	.lock(r_pll_locked_1P),
-    	.c(),
-    	.q(o_sdr_CKE_pad[CYC_A])
-    );
-    
-    `IP_MODULE_NAME(sync_ddio_group_out)
-    #(
-    	.DW(1),
-    	.INIT(1'b0),
-    	.SYNC("RISING")
-    )
-    inst_CS
-    (
-    	.arst(i_arst),
-    	.d0(i_sdr_n_CS_core[CYC_A]),
-    	.d1(i_sdr_n_CS_core[CYC_B]),
-    	.c_x1(i_sysclk),
-    	.c_x2(i_sdrclk),
-    	.lock(r_pll_locked_1P),
-    	.c(),
-    	.q(o_sdr_n_CS_pad[CYC_A])
-    );
-    
-    `IP_MODULE_NAME(sync_ddio_group_out)
-    #(
-    	.DW(1),
-    	.INIT(1'b0),
-    	.SYNC("RISING")
-    )
-    inst_RAS
-    (
-    	.arst(i_arst),
-    	.d0(i_sdr_n_RAS_core[CYC_A]),
-    	.d1(i_sdr_n_RAS_core[CYC_B]),
-    	.c_x1(i_sysclk),
-    	.c_x2(i_sdrclk),
-    	.lock(r_pll_locked_1P),
-    	.c(),
-    	.q(o_sdr_n_RAS_pad[CYC_A])
-    );
-    
-    `IP_MODULE_NAME(sync_ddio_group_out)
-    #(
-    	.DW(1),
-    	.INIT(1'b0),
-    	.SYNC("RISING")
-    )
-    inst_CAS
-    (
-    	.arst(i_arst),
-    	.d0(i_sdr_n_CAS_core[CYC_A]),
-    	.d1(i_sdr_n_CAS_core[CYC_B]),
-    	.c_x1(i_sysclk),
-    	.c_x2(i_sdrclk),
-    	.lock(r_pll_locked_1P),
-    	.c(),
-    	.q(o_sdr_n_CAS_pad[CYC_A])
-    );
-    
-    `IP_MODULE_NAME(sync_ddio_group_out)
-    #(
-    	.DW(1),
-    	.INIT(1'b0),
-    	.SYNC("RISING")
-    )
-    inst_WE
-    (
-    	.arst(i_arst),
-    	.d0(i_sdr_n_WE_core[CYC_A]),
-    	.d1(i_sdr_n_WE_core[CYC_B]),
-    	.c_x1(i_sysclk),
-    	.c_x2(i_sdrclk),
-    	.lock(r_pll_locked_1P),
-    	.c(),
-    	.q(o_sdr_n_WE_pad[CYC_A])
-    );
-    
-    `IP_MODULE_NAME(sync_ddio_group_out)
-    #(
-    	.DW(BA_WIDTH),
-    	.INIT(1'b0),
-    	.SYNC("RISING")
-    )
-    inst_BA
-    (
-    	.arst(i_arst),
-    	.d0(i_sdr_BA_core[CYC_A*BA_WIDTH+:BA_WIDTH]),
-    	.d1(i_sdr_BA_core[CYC_B*BA_WIDTH+:BA_WIDTH]),
-    	.c_x1(i_sysclk),
-    	.c_x2(i_sdrclk),
-    	.lock(r_pll_locked_1P),
-    	.c(),
-    	.q(o_sdr_BA_pad[BA_WIDTH-1:0])
-    );
-    
-    `IP_MODULE_NAME(sync_ddio_group_out)
-    #(
-    	.DW(ROW_WIDTH),
-    	.INIT(1'b0),
-    	.SYNC("RISING")
-    )
-    inst_ADDR
-    (
-    	.arst(i_arst),
-    	.d0(i_sdr_ADDR_core[CYC_A*ROW_WIDTH+:ROW_WIDTH]), 
-    	.d1(i_sdr_ADDR_core[CYC_B*ROW_WIDTH+:ROW_WIDTH]),
-    	.c_x1(i_sysclk),
-    	.c_x2(i_sdrclk),
-    	.lock(r_pll_locked_1P),
-    	.c(),
-    	.q(o_sdr_ADDR_pad[ROW_WIDTH-1:0])
-    );
-    
-    `IP_MODULE_NAME(sync_ddio_group_out)
-    #(
-    	.DW(DQ_GROUP*DQ_WIDTH),
-    	.INIT(1'b0),
-    	.SYNC("RISING")
-    )
-    inst_DQ_OUT
-    (
-    	.arst(i_arst),
-    	.d0(i_sdr_DATA_core[CYC_A*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH]),   
-    	.d1(i_sdr_DATA_core[CYC_B*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH]),
-    	.c_x1(i_sysclk),
-    	.c_x2(i_sdrclk),
-    	.lock(r_pll_locked_1P),
-    	.c(),
-    	.q(o_sdr_DATA_pad[DQ_GROUP*DQ_WIDTH-1:0])
-    );
-    
-    `IP_MODULE_NAME(sync_ddio_group_out)
-    #(
-    	.DW(DQ_GROUP*DQ_WIDTH),
-    	.INIT(1'b0),
-    	.SYNC("RISING")
-    )
-    inst_DQ_oe
-    (
-    	.arst(i_arst),
-    	.d0(i_sdr_DATA_oe_core[CYC_A*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH]),
-    	.d1(i_sdr_DATA_oe_core[CYC_B*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH]),
-    	.c_x1(i_sysclk),
-    	.c_x2(i_sdrclk),
-    	.lock(r_pll_locked_1P),
-    	.c(),
-    	.q(o_sdr_DATA_oe_pad[DQ_GROUP*DQ_WIDTH-1:0])
-    );
-    
-    `IP_MODULE_NAME(sync_ddio_group_in)
-    #(
-    	.DW		(DQ_GROUP*DQ_WIDTH),
-    	.SYNC	("RISING")   
-    )
-    inst_DQ_IN
-    (
-    	.arst	(i_arst),
-    	.c_x1	(i_sysclk),
-    	.c_x2	(i_tACclk),
-    	.d		(i_sdr_DATA_pad[DQ_GROUP*DQ_WIDTH-1:0]),
-`ifdef RTL_SIM
-        .q0		(o_sdr_DATA_core[CYC_A*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH]),	// simulation
-        .q1		(o_sdr_DATA_core[CYC_B*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH])	// simulation
-`else
-        .q0		(w_sdr_DATA_core[CYC_A*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH]),
-        .q1		(w_sdr_DATA_core[CYC_B*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH])
-`endif
-    );
-    
-    `IP_MODULE_NAME(sync_ddio_group_out)
-    #(
-    	.DW(DQ_GROUP),
-    	.INIT(1'b0),
-    	.SYNC("RISING")
-    )
-    inst_DQM
-    (
-    	.arst(i_arst),
-    	.d0(i_sdr_DQM_core[CYC_A*DQ_GROUP+:DQ_GROUP]),
-    	.d1(i_sdr_DQM_core[CYC_B*DQ_GROUP+:DQ_GROUP]),
-    	.c_x1(i_sysclk),
-    	.c_x2(i_sdrclk),
-    	.lock(r_pll_locked_1P),
-    	.c(),
-    	.q(o_sdr_DQM_pad[DQ_GROUP-1:0])
-    );
-			
-`ifndef RTL_SIM
-    // on board
-    always@(posedge i_arst or posedge i_sysclk)
-    begin
-    	if (i_arst)
-    		r_sdr_DATA_core_1P	<= {DQ_GROUP*DQ_WIDTH{1'b0}};
-    	else
-    		r_sdr_DATA_core_1P	<= w_sdr_DATA_core[CYC_B*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH];
-    end
-    assign	o_sdr_DATA_core	= {	w_sdr_DATA_core[CYC_A*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH],
-    							r_sdr_DATA_core_1P};
-`endif
-	generate
-	    for (rate=1; rate<DATA_RATE; rate=rate+1)
-	    begin: cycle_mapping
-	    	assign	o_sdr_CKE_pad[rate]		= 1'b0;
-	    	assign	o_sdr_n_CS_pad[rate]	= 1'b0;
-	    	assign	o_sdr_n_RAS_pad[rate]	= 1'b0;
-	    	assign	o_sdr_n_CAS_pad[rate]	= 1'b0;
-	    	assign	o_sdr_n_WE_pad[rate]	= 1'b0;
-	    	assign	o_sdr_BA_pad[rate*BA_WIDTH+:BA_WIDTH]		= {BA_WIDTH{1'b0}};
-	    	assign	o_sdr_ADDR_pad[rate*ROW_WIDTH+:ROW_WIDTH]	= {ROW_WIDTH{1'b0}};
-	    	assign	o_sdr_DATA_pad[rate*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH]		= {DQ_GROUP*DQ_WIDTH{1'b0}};
-	    	assign	o_sdr_DATA_oe_pad[rate*DQ_GROUP*DQ_WIDTH+:DQ_GROUP*DQ_WIDTH]	= {DQ_GROUP*DQ_WIDTH{1'b0}};
-	    	assign	o_sdr_DQM_pad[rate*DQ_GROUP+:DQ_GROUP]		= {DQ_GROUP{1'b0}};
-	    end
-    endgenerate
-endmodule
-
-//////////////////////////////////////////////////////////////////////////////
-// Copyright (C) 2013-2019 Efinix Inc. All rights reserved.
-//
-// This   document  contains  proprietary information  which   is
-// protected by  copyright. All rights  are reserved.  This notice
-// refers to original work by Efinix, Inc. which may be derivitive
-// of other work distributed under license of the authors.  In the
-// case of derivative work, nothing in this notice overrides the
-// original author's license agreement.  Where applicable, the 
-// original license agreement is included in it's original 
-// unmodified form immediately below this header.
-//
-// WARRANTY DISCLAIMER.  
-//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
-//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
-//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
-//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
-//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
-//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
-//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
-//
-// LIMITATION OF LIABILITY.  
-//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
-//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
-//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
-//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
-//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
-//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
-//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
-//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
-//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
-//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
-//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
-//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
-//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
-//     APPLY TO LICENSEE.
-//
-/////////////////////////////////////////////////////////////////////////////
-
-	`define CLK_200    	
-
-	`define SYS_CLK_100     	
-
-	`define tPWRUP     	      200000
-
-	`define tRAS       	          44
-
-	`define tRAS_MAX   	      120000
-
-	`define tRC        	          66
-
-	`define tRCD       	          20
-
-	`define tREF       	    64000000
-
-	`define tRFC       	          66
-
-	`define tRP        	          20
-
-	`define tWR        	           2
-
-	`define tMRD       	           2
-
-	`define ba_width   	           2
-
-	`define row_width  	          13
-
-	`define col_width  	          10
-
-	`define dq_width   	           8
-
-	`define dq_group   	           2
-
-	`define fsys_mhz   	         100
-
-	`define fck_mhz    	         200
-
-	`define cl         	           3
-
-	`define bl         	           1
-
-	`define ddio_type  	 "SOFT"
-	
-	`define tIORT                  2
-	
-	`define SDRAM_MODE		"AXI4" //"Native"
-
-
-
-
-
-/////////////////////////////////////////////////////////////////////////////
-//           _____       
-//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
-//         / /       \   
-//        / /  ..    /   simple_dual_port_ram.v
-//       / / .'     /    
-//    __/ /.'      /     Description:
-//   __   \       /      simple dual port ram macro
-//  /_/ /\ \_____/ /     
-// ____/  \_______/      
-//
-// *******************************
-// Revisions:
-// 1.0 Initial rev
-//
-// *******************************
-
-module `IP_MODULE_NAME(sdram_simple_dual_port_ram)
-#(
-	parameter DATA_WIDTH	= 8,
-	parameter ADDR_WIDTH	= 9,
-	parameter OUTPUT_REG	= "TRUE",
-	parameter RAM_INIT_FILE	= ""
-)
-(
-	input [(DATA_WIDTH-1):0] wdata,
-	input [(ADDR_WIDTH-1):0] waddr, raddr,
-	input we, wclk, re, rclk,
-	output [(DATA_WIDTH-1):0] rdata
-);
-
-	localparam MEMORY_DEPTH = 2**ADDR_WIDTH;
-	localparam MAX_DATA = (1<<ADDR_WIDTH)-1;
-	
-	reg [DATA_WIDTH-1:0] ram[MEMORY_DEPTH-1:0];
-	reg [DATA_WIDTH-1:0] r_rdata_1P;
-	reg [DATA_WIDTH-1:0] r_rdata_2P;
-	
-	reg [DATA_WIDTH-1:0] i;
-	initial
-	begin
-	// By default the Efinix memory will initialize to 0
-		if (RAM_INIT_FILE != "")
-		begin
-			$readmemh(RAM_INIT_FILE, ram);
-		end
-		else
-		begin
-			for (i=0;i<=MEMORY_DEPTH-1;i=i+1)
-                ram[i] = i[DATA_WIDTH-1:0];
-		end
-	end
-	
-	always @ (posedge wclk)
-		if (we)
-		ram[waddr] <= wdata;
-	
-	always @ (posedge rclk)
-	begin
-		if (re)
-			r_rdata_1P <= ram[raddr];
-		r_rdata_2P <= r_rdata_1P;
-	end
-	
-	generate
-		if (OUTPUT_REG == "TRUE")
-			assign	rdata = r_rdata_2P;
-		else
-			assign	rdata = r_rdata_1P;
-	endgenerate
-
-endmodule
-
-//////////////////////////////////////////////////////////////////////////////
-// Copyright (C) 2013-2019 Efinix Inc. All rights reserved.
-//
-// This   document  contains  proprietary information  which   is
-// protected by  copyright. All rights  are reserved.  This notice
-// refers to original work by Efinix, Inc. which may be derivitive
-// of other work distributed under license of the authors.  In the
-// case of derivative work, nothing in this notice overrides the
-// original author's license agreement.  Where applicable, the 
-// original license agreement is included in it's original 
-// unmodified form immediately below this header.
-//
-// WARRANTY DISCLAIMER.  
-//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
-//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
-//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
-//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
-//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
-//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
-//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
-//
-// LIMITATION OF LIABILITY.  
-//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
-//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
-//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
-//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
-//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
-//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
-//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
-//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
-//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
-//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
-//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
-//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
-//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
-//     APPLY TO LICENSEE.
-//
-/////////////////////////////////////////////////////////////////////////////
-
-/////////////////////////////////////////////////////////////////////////////
-//           _____       
-//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
-//         / /       \   
-//        / /  ..    /   `IP_MODULE_NAME(sync_ddio_group_in).v
-//       / / .'     /    
-//    __/ /.'      /     Description:
-//   __   \       /      soft DDIO input
-//  /_/ /\ \_____/ /     
-// ____/  \_______/      
-//
-// *******************************
-// Revisions:
-// 1.0 Initial rev
-//
-// *******************************
-/////////////////////////////////////////////////////////////////////////////
-
-module `IP_MODULE_NAME(sync_ddio_group_in)
-#(
-	parameter	DW		= 1,
-	parameter	SYNC	= "RISING"
-)
-(
-	input	arst,
-	input	c_x1,
-	input	c_x2,
-	input	[DW-1:0]d,
-	output	[DW-1:0]q0,
-	output	[DW-1:0]q1
-);
-
-reg		[DW-1:0]r_d_x2_1P;
-reg		[DW-1:0]r_d_x2_2P;
-
-reg		[DW-1:0]r_d0_x1_2P;
-reg		[DW-1:0]r_d1_x1_2P;
-
-always@(posedge arst or posedge c_x2)
-begin
-	if (arst)
-	begin
-		r_d_x2_1P	<= {DW{1'b0}};
-		r_d_x2_2P	<= {DW{1'b0}};
-	end
-	else
-	begin
-		r_d_x2_1P	<= d;
-		r_d_x2_2P	<= r_d_x2_1P;
-	end
-end
-
-    always@(posedge arst or posedge c_x1)
-    begin
-    	if (arst)
-    	begin
-    		r_d0_x1_2P	<= {DW{1'b0}};
-    		r_d1_x1_2P	<= {DW{1'b0}};
-    	end
-    	else
-    	begin
-    		if (SYNC == "FALLING")
-    		begin
-    			r_d0_x1_2P	<= r_d_x2_1P;
-    			r_d1_x1_2P	<= r_d_x2_2P;
-    		end
-    		else
-    		begin
-    			r_d0_x1_2P	<= r_d_x2_2P;
-    			r_d1_x1_2P	<= r_d_x2_1P;
-    		end
-    	end
-    end
-
-assign	q0	= r_d0_x1_2P;
-assign	q1	= r_d1_x1_2P;
-
-endmodule
-
-//////////////////////////////////////////////////////////////////////////////
-// Copyright (C) 2013-2019 Efinix Inc. All rights reserved.
-//
-// This   document  contains  proprietary information  which   is
-// protected by  copyright. All rights  are reserved.  This notice
-// refers to original work by Efinix, Inc. which may be derivitive
-// of other work distributed under license of the authors.  In the
-// case of derivative work, nothing in this notice overrides the
-// original author's license agreement.  Where applicable, the 
-// original license agreement is included in it's original 
-// unmodified form immediately below this header.
-//
-// WARRANTY DISCLAIMER.  
-//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
-//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
-//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
-//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
-//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
-//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
-//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
-//
-// LIMITATION OF LIABILITY.  
-//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
-//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
-//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
-//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
-//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
-//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
-//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
-//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
-//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
-//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
-//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
-//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
-//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
-//     APPLY TO LICENSEE.
-//
-/////////////////////////////////////////////////////////////////////////////
-
-/////////////////////////////////////////////////////////////////////////////
-//           _____       
-//          / _______    Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
-//         / /       \   
-//        / /  ..    /   `IP_MODULE_NAME(sync_ddio_group_out).v
-//       / / .'     /    
-//    __/ /.'      /     Description:
-//   __   \       /      soft DDIO output
-//  /_/ /\ \_____/ /     
-// ____/  \_______/      
-//
-// *******************************
-// Revisions:
-// 1.0 Initial rev
-//
-// *******************************
-/////////////////////////////////////////////////////////////////////////////
-
-module `IP_MODULE_NAME(sync_ddio_group_out)
-#(
-	parameter	DW		= 1,
-	parameter	INIT	= 1'b0,
-	parameter	SYNC	= "RISING"
-)
-(
-	input	arst,
-	input	[DW-1:0]d0,
-	input	[DW-1:0]d1,
-	input	c_x1,
-	input	c_x2,
-	input	lock,
-	output	c,
-	output	[DW-1:0]q
-);
-
-reg		[DW-1:0]r_d0_x1_1P;
-reg		[DW-1:0]r_d1_x1_1P;
-
-reg		r_c_x2_1P;
-reg		r_s_x2_1P;
-reg		[DW-1:0]r_d_x2_2P;
-
-wire	w_c_rst;
-
-generate
-	if (SYNC == "FALLING")
-		assign	w_c_rst	= 1'b1;
-	else
-		assign	w_c_rst	= 1'b0;
-endgenerate
-
-always@(posedge arst or posedge c_x1)
-begin
-	if (arst)
-	begin
-		r_d0_x1_1P	<= {DW{INIT}};
-		r_d1_x1_1P	<= {DW{INIT}};
-	end
-	else if (lock)
-	begin
-		r_d0_x1_1P	<= d0;
-		r_d1_x1_1P	<= d1;
-	end
-end
-
-always@(posedge arst or posedge c_x2)
-begin
-	if (arst)
-	begin
-		r_c_x2_1P	<= w_c_rst;
-		r_s_x2_1P	<= 1'b0;
-		r_d_x2_2P	<= {DW{INIT}};
-	end
-	else if (lock)
-	begin
-		r_c_x2_1P	<= ~r_c_x2_1P;
-		r_s_x2_1P	<= ~r_s_x2_1P;
-		if (r_s_x2_1P)
-			r_d_x2_2P	<= r_d1_x1_1P;
-		else
-			r_d_x2_2P	<= r_d0_x1_1P;
-	end
-end
-
-assign	c	= r_c_x2_1P;
-assign	q	= r_d_x2_2P;
-
-endmodule
-
-//////////////////////////////////////////////////////////////////////////////
-// Copyright (C) 2013-2019 Efinix Inc. All rights reserved.
-//
-// This   document  contains  proprietary information  which   is
-// protected by  copyright. All rights  are reserved.  This notice
-// refers to original work by Efinix, Inc. which may be derivitive
-// of other work distributed under license of the authors.  In the
-// case of derivative work, nothing in this notice overrides the
-// original author's license agreement.  Where applicable, the 
-// original license agreement is included in it's original 
-// unmodified form immediately below this header.
-//
-// WARRANTY DISCLAIMER.  
-//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND 
-//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH 
-//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, 
-//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF 
-//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR 
-//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED 
-//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
-//
-// LIMITATION OF LIABILITY.  
-//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY 
-//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT 
-//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY 
-//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, 
-//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY 
-//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF 
-//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR 
-//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN 
-//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER 
-//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
-//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
-//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR 
-//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT 
-//     APPLY TO LICENSEE.
-//
-/////////////////////////////////////////////////////////////////////////////
-`undef IP_UUID
-`undef IP_NAME_CONCAT
-`undef IP_MODULE_NAME
diff --git a/hw/efinix_fpga/ip/sdram/sdram_define.vh b/hw/efinix_fpga/ip/sdram/sdram_define.vh
deleted file mode 100644
index feb3c53..0000000
--- a/hw/efinix_fpga/ip/sdram/sdram_define.vh
+++ /dev/null
@@ -1,80 +0,0 @@
-// =============================================================================
-// Generated by efx_ipmgr
-// Version: 2021.2.323
-// IP Version: 1.5
-// =============================================================================
-
-////////////////////////////////////////////////////////////////////////////////
-// Copyright (C) 2013-2021 Efinix Inc. All rights reserved.              
-//
-// This   document  contains  proprietary information  which   is        
-// protected by  copyright. All rights  are reserved.  This notice       
-// refers to original work by Efinix, Inc. which may be derivitive       
-// of other work distributed under license of the authors.  In the       
-// case of derivative work, nothing in this notice overrides the         
-// original author's license agreement.  Where applicable, the           
-// original license agreement is included in it's original               
-// unmodified form immediately below this header.                        
-//                                                                       
-// WARRANTY DISCLAIMER.                                                  
-//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
-//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
-//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
-//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
-//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
-//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
-//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
-//                                                                       
-// LIMITATION OF LIABILITY.                                              
-//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
-//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
-//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
-//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
-//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
-//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
-//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
-//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
-//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
-//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
-//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
-//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
-//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
-//     APPLY TO LICENSEE.                                                
-//
-////////////////////////////////////////////////////////////////////////////////
-
-localparam fSYS_MHz = 100;
-localparam fCK_MHz  = 200;
-localparam tIORT_u = 2;
-localparam BL = 1;
-localparam DDIO_TYPE = "SOFT";
-localparam DQ_WIDTH  = 8;
-localparam DQ_GROUP = 2;
-localparam BA_WIDTH  = 2;
-localparam ROW_WIDTH  = 13;
-localparam COL_WIDTH  = 9;
-localparam tPWRUP  = 200000;
-localparam tRAS  = 44;
-localparam tRC  = 66;
-localparam tRCD = 20;
-localparam tREF  = 64000000;
-localparam tWR = 2;
-localparam tMRD = 2;
-localparam tRFC  = 66;
-localparam tRAS_MAX = 120000;
-localparam DATA_RATE = 2;
-localparam AXI_ARADDR_WIDTH = 24;
-localparam SDRAM_MODE = "Native";
-localparam AXI_BUSER_WIDTH = 2;
-localparam AXI_BID_WIDTH = 4;
-localparam AXI_AWUSER_WIDTH = 2;
-localparam AXI_AWID_WIDTH = 4;
-localparam AXI_AWADDR_WIDTH = 24;
-localparam AXI_RDATA_WIDTH = 32;
-localparam AXI_WUSER_WIDTH = 2;
-localparam AXI_WDATA_WIDTH = 32;
-localparam AXI_RUSER_WIDTH = 3;
-localparam AXI_ARUSER_WIDTH = 3;
-localparam AXI_ARID_WIDTH = 4;
-localparam tRP = 20;
-localparam CL = 3;
diff --git a/hw/efinix_fpga/ip/sdram/sdram_tmpl.v b/hw/efinix_fpga/ip/sdram/sdram_tmpl.v
deleted file mode 100644
index 5e85ae6..0000000
--- a/hw/efinix_fpga/ip/sdram/sdram_tmpl.v
+++ /dev/null
@@ -1,83 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-// Copyright (C) 2013-2021 Efinix Inc. All rights reserved.              
-//
-// This   document  contains  proprietary information  which   is        
-// protected by  copyright. All rights  are reserved.  This notice       
-// refers to original work by Efinix, Inc. which may be derivitive       
-// of other work distributed under license of the authors.  In the       
-// case of derivative work, nothing in this notice overrides the         
-// original author's license agreement.  Where applicable, the           
-// original license agreement is included in it's original               
-// unmodified form immediately below this header.                        
-//                                                                       
-// WARRANTY DISCLAIMER.                                                  
-//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
-//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
-//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
-//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
-//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
-//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
-//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
-//                                                                       
-// LIMITATION OF LIABILITY.                                              
-//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
-//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
-//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
-//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
-//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
-//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
-//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
-//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
-//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
-//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
-//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
-//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
-//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
-//     APPLY TO LICENSEE.                                                
-//
-////////////////////////////////////////////////////////////////////////////////
-
-sdram u_sdram(
-.i_we ( i_we ),
-.i_sysclk ( i_sysclk ),
-.i_arst ( i_arst ),
-.i_sdrclk ( i_sdrclk ),
-.i_tACclk ( i_tACclk ),
-.i_pll_locked ( i_pll_locked ),
-.i_re ( i_re ),
-.i_last ( i_last ),
-.o_dbg_tRTW_done ( o_dbg_tRTW_done ),
-.o_dbg_ref_req ( o_dbg_ref_req ),
-.o_dbg_wr_ack ( o_dbg_wr_ack ),
-.o_dbg_rd_ack ( o_dbg_rd_ack ),
-.o_dbg_n_CS ( o_dbg_n_CS ),
-.o_dbg_n_RAS ( o_dbg_n_RAS ),
-.o_dbg_n_CAS ( o_dbg_n_CAS ),
-.o_dbg_n_WE ( o_dbg_n_WE ),
-.o_dbg_BA ( o_dbg_BA ),
-.o_dbg_ADDR ( o_dbg_ADDR ),
-.o_dbg_DATA_out ( o_dbg_DATA_out ),
-.o_dbg_DATA_in ( o_dbg_DATA_in ),
-.i_addr ( i_addr ),
-.i_din ( i_din ),
-.o_dout ( o_dout ),
-.o_sdr_state ( o_sdr_state ),
-.o_sdr_init_done ( o_sdr_init_done ),
-.o_wr_ack ( o_wr_ack ),
-.o_rd_ack ( o_rd_ack ),
-.o_ref_req ( o_ref_req ),
-.o_rd_valid ( o_rd_valid ),
-.o_sdr_CKE ( o_sdr_CKE ),
-.o_sdr_n_CS ( o_sdr_n_CS ),
-.o_sdr_n_RAS ( o_sdr_n_RAS ),
-.o_sdr_n_CAS ( o_sdr_n_CAS ),
-.o_sdr_n_WE ( o_sdr_n_WE ),
-.o_sdr_BA ( o_sdr_BA ),
-.o_sdr_ADDR ( o_sdr_ADDR ),
-.o_sdr_DATA ( o_sdr_DATA ),
-.o_sdr_DATA_oe ( o_sdr_DATA_oe ),
-.i_sdr_DATA ( i_sdr_DATA ),
-.o_sdr_DQM ( o_sdr_DQM ),
-.o_dbg_dly_cnt_b ( o_dbg_dly_cnt_b ),
-.o_dbg_tRCD_done ( o_dbg_tRCD_done )
-);
diff --git a/hw/efinix_fpga/ip/sdram/sdram_tmpl.vhd b/hw/efinix_fpga/ip/sdram/sdram_tmpl.vhd
deleted file mode 100644
index 1fbac17..0000000
--- a/hw/efinix_fpga/ip/sdram/sdram_tmpl.vhd
+++ /dev/null
@@ -1,132 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-// Copyright (C) 2013-2021 Efinix Inc. All rights reserved.              
-//
-// This   document  contains  proprietary information  which   is        
-// protected by  copyright. All rights  are reserved.  This notice       
-// refers to original work by Efinix, Inc. which may be derivitive       
-// of other work distributed under license of the authors.  In the       
-// case of derivative work, nothing in this notice overrides the         
-// original author's license agreement.  Where applicable, the           
-// original license agreement is included in it's original               
-// unmodified form immediately below this header.                        
-//                                                                       
-// WARRANTY DISCLAIMER.                                                  
-//     THE  DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND        
-//     EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH               
-//     RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,  
-//     INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF          
-//     MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR    
-//     PURPOSE.  SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED       
-//     WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.           
-//                                                                       
-// LIMITATION OF LIABILITY.                                              
-//     NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY       
-//     INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT    
-//     MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY   
-//     OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,      
-//     SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY    
-//     CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF      
-//     GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR   
-//     MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN    
-//     THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER    
-//     (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE 
-//     BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES.  SOME STATES DO 
-//     NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR            
-//     CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT   
-//     APPLY TO LICENSEE.                                                
-//
-////////////////////////////////////////////////////////////////////////////////
-------------- Begin Cut here for COMPONENT Declaration ------
-COMPONENT sdram is
-PORT (
-i_we : in std_logic;
-i_sysclk : in std_logic;
-i_arst : in std_logic;
-i_sdrclk : in std_logic;
-i_tACclk : in std_logic;
-i_pll_locked : in std_logic;
-i_re : in std_logic;
-i_last : in std_logic;
-o_dbg_tRTW_done : out std_logic;
-o_dbg_ref_req : out std_logic;
-o_dbg_wr_ack : out std_logic;
-o_dbg_rd_ack : out std_logic;
-o_dbg_n_CS : out std_logic_vector(1 downto 0);
-o_dbg_n_RAS : out std_logic_vector(1 downto 0);
-o_dbg_n_CAS : out std_logic_vector(1 downto 0);
-o_dbg_n_WE : out std_logic_vector(1 downto 0);
-o_dbg_BA : out std_logic_vector(3 downto 0);
-o_dbg_ADDR : out std_logic_vector(25 downto 0);
-o_dbg_DATA_out : out std_logic_vector(31 downto 0);
-o_dbg_DATA_in : out std_logic_vector(31 downto 0);
-i_addr : in std_logic_vector(23 downto 0);
-i_din : in std_logic_vector(31 downto 0);
-o_dout : out std_logic_vector(31 downto 0);
-o_sdr_state : out std_logic_vector(3 downto 0);
-o_sdr_init_done : out std_logic;
-o_wr_ack : out std_logic;
-o_rd_ack : out std_logic;
-o_ref_req : out std_logic;
-o_rd_valid : out std_logic;
-o_sdr_CKE : out std_logic_vector(1 downto 0);
-o_sdr_n_CS : out std_logic_vector(1 downto 0);
-o_sdr_n_RAS : out std_logic_vector(1 downto 0);
-o_sdr_n_CAS : out std_logic_vector(1 downto 0);
-o_sdr_n_WE : out std_logic_vector(1 downto 0);
-o_sdr_BA : out std_logic_vector(3 downto 0);
-o_sdr_ADDR : out std_logic_vector(25 downto 0);
-o_sdr_DATA : out std_logic_vector(31 downto 0);
-o_sdr_DATA_oe : out std_logic_vector(31 downto 0);
-i_sdr_DATA : in std_logic_vector(31 downto 0);
-o_sdr_DQM : out std_logic_vector(3 downto 0);
-o_dbg_dly_cnt_b : out std_logic_vector(5 downto 0);
-o_dbg_tRCD_done : out std_logic);
-END COMPONENT;
----------------------- End COMPONENT Declaration ------------
-
-------------- Begin Cut here for INSTANTIATION Template -----
-u_sdram : sdram
-PORT MAP (
-i_we => i_we,
-i_sysclk => i_sysclk,
-i_arst => i_arst,
-i_sdrclk => i_sdrclk,
-i_tACclk => i_tACclk,
-i_pll_locked => i_pll_locked,
-i_re => i_re,
-i_last => i_last,
-o_dbg_tRTW_done => o_dbg_tRTW_done,
-o_dbg_ref_req => o_dbg_ref_req,
-o_dbg_wr_ack => o_dbg_wr_ack,
-o_dbg_rd_ack => o_dbg_rd_ack,
-o_dbg_n_CS => o_dbg_n_CS,
-o_dbg_n_RAS => o_dbg_n_RAS,
-o_dbg_n_CAS => o_dbg_n_CAS,
-o_dbg_n_WE => o_dbg_n_WE,
-o_dbg_BA => o_dbg_BA,
-o_dbg_ADDR => o_dbg_ADDR,
-o_dbg_DATA_out => o_dbg_DATA_out,
-o_dbg_DATA_in => o_dbg_DATA_in,
-i_addr => i_addr,
-i_din => i_din,
-o_dout => o_dout,
-o_sdr_state => o_sdr_state,
-o_sdr_init_done => o_sdr_init_done,
-o_wr_ack => o_wr_ack,
-o_rd_ack => o_rd_ack,
-o_ref_req => o_ref_req,
-o_rd_valid => o_rd_valid,
-o_sdr_CKE => o_sdr_CKE,
-o_sdr_n_CS => o_sdr_n_CS,
-o_sdr_n_RAS => o_sdr_n_RAS,
-o_sdr_n_CAS => o_sdr_n_CAS,
-o_sdr_n_WE => o_sdr_n_WE,
-o_sdr_BA => o_sdr_BA,
-o_sdr_ADDR => o_sdr_ADDR,
-o_sdr_DATA => o_sdr_DATA,
-o_sdr_DATA_oe => o_sdr_DATA_oe,
-i_sdr_DATA => i_sdr_DATA,
-o_sdr_DQM => o_sdr_DQM,
-o_dbg_dly_cnt_b => o_dbg_dly_cnt_b,
-o_dbg_tRCD_done => o_dbg_tRCD_done);
------------------------- End INSTANTIATION Template ---------
diff --git a/hw/efinix_fpga/ip/sdram/settings.json b/hw/efinix_fpga/ip/sdram/settings.json
deleted file mode 100644
index b869f62..0000000
--- a/hw/efinix_fpga/ip/sdram/settings.json
+++ /dev/null
@@ -1,44 +0,0 @@
-{
-    "args": [
-        "-o",
-        "sdram",
-        "--base_path",
-        "/home/byron/Projects/super6502/hw/efinix_fpga/ip",
-        "--vlnv",
-        {
-            "vendor": "efinixinc.com",
-            "library": "memory_controller",
-            "name": "efx_sdram_controller",
-            "version": "1.5"
-        }
-    ],
-    "conf": {
-        "fCK_MHz": "200",
-        "tIORT_u": "2",
-        "CL": "3",
-        "DDIO_TYPE": "0",
-        "DQ_GROUP": "2",
-        "ROW_WIDTH": "13",
-        "COL_WIDTH": "9",
-        "tPWRUP": "200000",
-        "tRAS": "44",
-        "tRAS_MAX": "120000",
-        "tRC": "66",
-        "tRCD": "20",
-        "tREF": "64000000",
-        "tRFC ": "66",
-        "tRP": "20",
-        "SDRAM_MODE": "0",
-        "DATA_RATE": "2"
-    },
-    "output": {
-        "external_source": [
-            "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v",
-            "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram_define.vh",
-            "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram_tmpl.vhd",
-            "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram_tmpl.v"
-        ]
-    },
-    "sw_version": "2021.2.323",
-    "generated_date": "2022-06-12T00:16:17.036312"
-}
\ No newline at end of file
diff --git a/hw/efinix_fpga/memory_mapper.sv b/hw/efinix_fpga/memory_mapper.sv
deleted file mode 100644
index 00858d7..0000000
--- a/hw/efinix_fpga/memory_mapper.sv
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- *	This is based off of the 74LS610, but is not identical.
-	Some of the inputs are flipped so that they are all active high,
-	and some outputs are reordered.
-	Notably, when MM is low, MA is present on MO0-MO4, not 8 to 11.
- */
-
-module memory_mapper(
-	input clk,
-	input rst,
-
-	input rw,
-	input cs,
-
-	input MM_cs,
-
-	input [3:0] RS,
-
-	input [3:0] MA,
-
-	input logic [11:0] data_in,
-	output logic [11:0] data_out,
-
-	output logic [11:0] MO
-);
-
-logic [11:0] RAM [16];
-
-logic MM;
-
-
-always_ff @(posedge clk) begin
-    if (rst) begin
-        MM <= '0;
-    end else begin
-        if (MM_cs & ~rw) begin					// can't read MM but do you really need too?
-            MM = |data_in;
-        end
-
-        if (cs & ~rw) begin					// write to registers
-            RAM[RS] <= data_in;
-        end else if (cs & rw) begin			// read registers
-            data_out <= RAM[RS];
-        end
-    end
-end
-
-
-always_comb begin
-	if (MM) begin						// normal mode
-		MO = RAM[MA];
-	end else begin						// passthrough mode
-		MO = {8'b0, MA};
-	end
-end
-
-endmodule
-
diff --git a/hw/efinix_fpga/outflow/super6502.err.log b/hw/efinix_fpga/outflow/super6502.err.log
deleted file mode 100644
index d9c4ab7..0000000
--- a/hw/efinix_fpga/outflow/super6502.err.log
+++ /dev/null
@@ -1,159 +0,0 @@
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 09, 2022 21:36:12
-///////////////////////////////////
-
-[EFX-0010 VERI-ERROR] instantiating unknown module 'cpu_clk' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:92)
-[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 09, 2022 21:36:40
-///////////////////////////////////
-
-[EFX-0010 VERI-ERROR] instantiating unknown module 'memory_mapper' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:118)
-[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 09, 2022 21:42:28
-///////////////////////////////////
-
-[EFX-0010 VERI-ERROR] instantiating unknown module 'sdram_platform' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram.sv:85)
-[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 11, 2022 12:05:39
-///////////////////////////////////
-
-[EFX-0010 VERI-ERROR] instantiating unknown module 'sdram_platform' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram.sv:85)
-[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 11, 2022 19:19:40
-///////////////////////////////////
-
-[EFX-0010 VERI-ERROR] overwriting previous definition of module 'sdram' (VERI-1206) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:174)
-[EFX-0010 VERI-ERROR] module 'axi4_sdram_controller_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:1006)
-[EFX-0010 VERI-ERROR] module 'dual_clock_fifo_wrapper_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:1327)
-[EFX-0010 VERI-ERROR] module 'dual_clock_fifo_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:1740)
-[EFX-0010 VERI-ERROR] module 'efx_sdram_controller_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:2308)
-[EFX-0010 VERI-ERROR] module 'sdram_controller_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:2585)
-[EFX-0010 VERI-ERROR] module 'sdram_fsm_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:3419)
-[EFX-0010 VERI-ERROR] module 'sdram_io_block_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:3784)
-[EFX-0010 VERI-ERROR] module 'sdram_simple_dual_port_ram_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:3948)
-[EFX-0010 VERI-ERROR] module 'sync_ddio_group_in_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:4066)
-[EFX-0010 VERI-ERROR] module 'sync_ddio_group_out_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:4194)
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 11, 2022 19:20:04
-///////////////////////////////////
-
-[EFX-0010 VERI-ERROR] cannot find port 'rst' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:155)
-[EFX-0010 VERI-ERROR] cannot find port 'clk_50' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:156)
-[EFX-0010 VERI-ERROR] cannot find port 'cpu_clk' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:157)
-[EFX-0010 VERI-ERROR] cannot find port 'addr' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:158)
-[EFX-0010 VERI-ERROR] cannot find port 'sdram_cs' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:159)
-[EFX-0010 VERI-ERROR] cannot find port 'rwb' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:160)
-[EFX-0010 VERI-ERROR] cannot find port 'data_in' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:161)
-[EFX-0010 VERI-ERROR] cannot find port 'data_out' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:162)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CLK' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:165)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_ADDR' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:166)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_BA' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:167)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:168)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CKE' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:169)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:170)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_DQ' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:171)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_UDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:172)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_LDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:173)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_RAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:174)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_WE_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:175)
-[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 11, 2022 19:20:55
-///////////////////////////////////
-
-[EFX-0010 VERI-ERROR] cannot find port 'rst' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:155)
-[EFX-0010 VERI-ERROR] cannot find port 'clk_50' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:156)
-[EFX-0010 VERI-ERROR] cannot find port 'cpu_clk' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:157)
-[EFX-0010 VERI-ERROR] cannot find port 'addr' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:158)
-[EFX-0010 VERI-ERROR] cannot find port 'sdram_cs' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:159)
-[EFX-0010 VERI-ERROR] cannot find port 'rwb' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:160)
-[EFX-0010 VERI-ERROR] cannot find port 'data_in' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:161)
-[EFX-0010 VERI-ERROR] cannot find port 'data_out' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:162)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CLK' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:165)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_ADDR' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:166)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_BA' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:167)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:168)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CKE' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:169)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:170)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_DQ' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:171)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_UDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:172)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_LDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:173)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_RAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:174)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_WE_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:175)
-[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 11, 2022 19:21:29
-///////////////////////////////////
-
-[EFX-0010 VERI-ERROR] instantiating unknown module 'sdram_platform' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:85)
-[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 11, 2022 19:21:33
-///////////////////////////////////
-
-[EFX-0010 VERI-ERROR] instantiating unknown module 'sdram_platform' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:85)
-[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 13, 2022 19:05:46
-///////////////////////////////////
-
-[EFX-0010 VERI-ERROR] 'DQ_GROUP' is not a constant (VERI-1188) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:49)
-[EFX-0010 VERI-ERROR] module 'sdram_adapter' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:68)
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 13, 2022 19:08:09
-///////////////////////////////////
-
-[EFX-0010 VERI-ERROR] 'DQ_GROUP' is not a constant (VERI-1188) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:49)
-[EFX-0010 VERI-ERROR] module 'sdram_adapter' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:68)
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 13, 2022 19:08:21
-///////////////////////////////////
-
-[EFX-0010 VERI-ERROR] cannot find port 'rst' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:155)
-[EFX-0010 VERI-ERROR] cannot find port 'clk_50' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:156)
-[EFX-0010 VERI-ERROR] cannot find port 'cpu_clk' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:157)
-[EFX-0010 VERI-ERROR] cannot find port 'addr' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:158)
-[EFX-0010 VERI-ERROR] cannot find port 'sdram_cs' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:159)
-[EFX-0010 VERI-ERROR] cannot find port 'rwb' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:160)
-[EFX-0010 VERI-ERROR] cannot find port 'data_in' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:161)
-[EFX-0010 VERI-ERROR] cannot find port 'data_out' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:162)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CLK' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:165)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_ADDR' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:166)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_BA' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:167)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:168)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CKE' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:169)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:170)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_DQ' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:171)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_UDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:172)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_LDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:173)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_RAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:174)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_WE_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:175)
-[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
diff --git a/hw/efinix_fpga/outflow/super6502.info.log b/hw/efinix_fpga/outflow/super6502.info.log
deleted file mode 100644
index 05dc356..0000000
--- a/hw/efinix_fpga/outflow/super6502.info.log
+++ /dev/null
@@ -1,397 +0,0 @@
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 09, 2022 21:36:12
-///////////////////////////////////
-
-[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504) 
-[EFX-0012 VERI-INFO] compiling module 'super6502' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
-[EFX-0010 VERI-ERROR] instantiating unknown module 'cpu_clk' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:92)
-[EFX-0012 VERI-INFO] module 'super6502' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
-[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 09, 2022 21:36:40
-///////////////////////////////////
-
-[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504) 
-[EFX-0012 VERI-INFO] compiling module 'super6502' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
-[EFX-0010 VERI-ERROR] instantiating unknown module 'memory_mapper' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:118)
-[EFX-0012 VERI-INFO] module 'super6502' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
-[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 09, 2022 21:42:28
-///////////////////////////////////
-
-[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504) 
-[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
-[EFX-0012 VERI-INFO] compiling module 'super6502' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
-[EFX-0012 VERI-INFO] compiling module 'memory_mapper' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:8)
-[EFX-0012 VERI-INFO] extracting RAM for identifier 'RAM' (VERI-2571) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:27)
-[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
-[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)
-[EFX-0012 VERI-INFO] compiling module 'addr_decode' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/addr_decode.sv:1)
-[EFX-0012 VERI-INFO] compiling module 'sdram' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram.sv:1)
-[EFX-0010 VERI-ERROR] instantiating unknown module 'sdram_platform' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram.sv:85)
-[EFX-0012 VERI-INFO] module 'sdram' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram.sv:1)
-[EFX-0012 VERI-INFO] module 'super6502' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
-[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 11, 2022 12:05:39
-///////////////////////////////////
-
-[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504) 
-[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
-[EFX-0012 VERI-INFO] compiling module 'super6502' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
-[EFX-0012 VERI-INFO] compiling module 'memory_mapper' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:8)
-[EFX-0012 VERI-INFO] extracting RAM for identifier 'RAM' (VERI-2571) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:27)
-[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
-[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)
-[EFX-0012 VERI-INFO] compiling module 'addr_decode' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/addr_decode.sv:1)
-[EFX-0012 VERI-INFO] compiling module 'sdram' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram.sv:1)
-[EFX-0010 VERI-ERROR] instantiating unknown module 'sdram_platform' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram.sv:85)
-[EFX-0012 VERI-INFO] module 'sdram' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram.sv:1)
-[EFX-0012 VERI-INFO] module 'super6502' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
-[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 11, 2022 19:19:40
-///////////////////////////////////
-
-[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504) 
-[EFX-0010 VERI-ERROR] overwriting previous definition of module 'sdram' (VERI-1206) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:174)
-[EFX-0012 VERI-INFO] previous definition of design element 'sdram' is here (VERI-2142) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:87)
-[EFX-0010 VERI-ERROR] module 'axi4_sdram_controller_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:1006)
-[EFX-0010 VERI-ERROR] module 'dual_clock_fifo_wrapper_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:1327)
-[EFX-0010 VERI-ERROR] module 'dual_clock_fifo_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:1740)
-[EFX-0010 VERI-ERROR] module 'efx_sdram_controller_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:2308)
-[EFX-0010 VERI-ERROR] module 'sdram_controller_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:2585)
-[EFX-0010 VERI-ERROR] module 'sdram_fsm_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:3419)
-[EFX-0010 VERI-ERROR] module 'sdram_io_block_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:3784)
-[EFX-0010 VERI-ERROR] module 'sdram_simple_dual_port_ram_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:3948)
-[EFX-0010 VERI-ERROR] module 'sync_ddio_group_in_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:4066)
-[EFX-0010 VERI-ERROR] module 'sync_ddio_group_out_2fa8b2362acf42f5841c22a03034c8fb' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:4194)
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 11, 2022 19:20:04
-///////////////////////////////////
-
-[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504) 
-[EFX-0010 VERI-ERROR] cannot find port 'rst' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:155)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'clk_50' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:156)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'cpu_clk' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:157)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'addr' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:158)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'sdram_cs' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:159)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'rwb' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:160)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'data_in' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:161)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'data_out' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:162)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CLK' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:165)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_ADDR' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:166)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_BA' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:167)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:168)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CKE' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:169)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:170)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_DQ' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:171)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_UDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:172)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_LDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:173)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_RAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:174)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_WE_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:175)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0011 VERI-WARNING] port 'i_we' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
-[EFX-0011 VERI-WARNING] port 'o_dbg_tRTW_done' remains unconnected for this instance (VERI-1927) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
-[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
-[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 11, 2022 19:20:55
-///////////////////////////////////
-
-[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504) 
-[EFX-0010 VERI-ERROR] cannot find port 'rst' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:155)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'clk_50' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:156)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'cpu_clk' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:157)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'addr' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:158)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'sdram_cs' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:159)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'rwb' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:160)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'data_in' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:161)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'data_out' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:162)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CLK' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:165)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_ADDR' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:166)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_BA' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:167)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:168)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CKE' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:169)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:170)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_DQ' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:171)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_UDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:172)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_LDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:173)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_RAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:174)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_WE_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:175)
-[EFX-0012 VERI-INFO] 'sdram' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v:49)
-[EFX-0011 VERI-WARNING] port 'i_we' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
-[EFX-0011 VERI-WARNING] port 'o_dbg_tRTW_done' remains unconnected for this instance (VERI-1927) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
-[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
-[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 11, 2022 19:21:29
-///////////////////////////////////
-
-[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504) 
-[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
-[EFX-0012 VERI-INFO] compiling module 'super6502' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
-[EFX-0012 VERI-INFO] compiling module 'memory_mapper' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:8)
-[EFX-0012 VERI-INFO] extracting RAM for identifier 'RAM' (VERI-2571) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:27)
-[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
-[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)
-[EFX-0012 VERI-INFO] compiling module 'addr_decode' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/addr_decode.sv:1)
-[EFX-0012 VERI-INFO] compiling module 'sdram_adapter' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
-[EFX-0010 VERI-ERROR] instantiating unknown module 'sdram_platform' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:85)
-[EFX-0012 VERI-INFO] module 'sdram_adapter' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
-[EFX-0012 VERI-INFO] module 'super6502' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
-[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 11, 2022 19:21:33
-///////////////////////////////////
-
-[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504) 
-[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
-[EFX-0012 VERI-INFO] compiling module 'super6502' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
-[EFX-0012 VERI-INFO] compiling module 'memory_mapper' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:8)
-[EFX-0012 VERI-INFO] extracting RAM for identifier 'RAM' (VERI-2571) (/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv:27)
-[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
-[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)
-[EFX-0012 VERI-INFO] compiling module 'addr_decode' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/addr_decode.sv:1)
-[EFX-0012 VERI-INFO] compiling module 'sdram_adapter' (VERI-1018) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
-[EFX-0010 VERI-ERROR] instantiating unknown module 'sdram_platform' (VERI-1063) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:85)
-[EFX-0012 VERI-INFO] module 'sdram_adapter' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
-[EFX-0012 VERI-INFO] module 'super6502' remains a black box due to errors in its contents (VERI-1073) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:2)
-[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 13, 2022 19:05:46
-///////////////////////////////////
-
-[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504) 
-[EFX-0012 VERI-INFO] undeclared symbol 'w_areset', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:21)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sysclk', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:22)
-[EFX-0012 VERI-INFO] undeclared symbol 'r_we_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:27)
-[EFX-0012 VERI-INFO] undeclared symbol 'r_re_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:28)
-[EFX-0012 VERI-INFO] undeclared symbol 'r_last_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:29)
-[EFX-0012 VERI-INFO] undeclared symbol 'r_addr_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:30)
-[EFX-0012 VERI-INFO] undeclared symbol 'r_din_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:31)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dout', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:32)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_state', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:33)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_init_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:34)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_wr_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:35)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_rd_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:36)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_rd_valid', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:38)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_CKE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:40)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_CS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:41)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_RAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:42)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_CAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:43)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_WE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:44)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_BA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:45)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_ADDR', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:46)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DATA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:47)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DATA_oe', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:48)
-[EFX-0012 VERI-INFO] undeclared symbol 'DQ_GROUP', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:49)
-[EFX-0012 VERI-INFO] undeclared symbol 'DQ_WIDTH', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:49)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DQM', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:50)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_dly_cnt_b', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:52)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_tRCD_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:53)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_tRTW_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:54)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_ref_req', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:55)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_wr_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:56)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_rd_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:57)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_CS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:58)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_RAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:59)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_CAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:60)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_WE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:61)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_BA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:62)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_ADDR', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:63)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_DATA_out', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:64)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_DATA_in', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:65)
-[EFX-0010 VERI-ERROR] 'DQ_GROUP' is not a constant (VERI-1188) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:49)
-[EFX-0010 VERI-ERROR] module 'sdram_adapter' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:68)
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 13, 2022 19:08:09
-///////////////////////////////////
-
-[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504) 
-[EFX-0012 VERI-INFO] undeclared symbol 'w_areset', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:21)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sysclk', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:22)
-[EFX-0012 VERI-INFO] undeclared symbol 'r_we_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:27)
-[EFX-0012 VERI-INFO] undeclared symbol 'r_re_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:28)
-[EFX-0012 VERI-INFO] undeclared symbol 'r_last_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:29)
-[EFX-0012 VERI-INFO] undeclared symbol 'r_addr_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:30)
-[EFX-0012 VERI-INFO] undeclared symbol 'r_din_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:31)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dout', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:32)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_state', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:33)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_init_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:34)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_wr_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:35)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_rd_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:36)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_rd_valid', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:38)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_CKE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:40)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_CS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:41)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_RAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:42)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_CAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:43)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_WE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:44)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_BA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:45)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_ADDR', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:46)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DATA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:47)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DATA_oe', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:48)
-[EFX-0012 VERI-INFO] undeclared symbol 'DQ_GROUP', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:49)
-[EFX-0012 VERI-INFO] undeclared symbol 'DQ_WIDTH', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:49)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DQM', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:50)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_dly_cnt_b', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:52)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_tRCD_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:53)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_tRTW_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:54)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_ref_req', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:55)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_wr_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:56)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_rd_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:57)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_CS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:58)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_RAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:59)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_CAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:60)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_WE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:61)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_BA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:62)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_ADDR', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:63)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_DATA_out', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:64)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_DATA_in', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:65)
-[EFX-0010 VERI-ERROR] 'DQ_GROUP' is not a constant (VERI-1188) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:49)
-[EFX-0010 VERI-ERROR] module 'sdram_adapter' is ignored due to previous errors (VERI-1072) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:68)
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 13, 2022 19:08:21
-///////////////////////////////////
-
-[EFX-0012 VERI-INFO] default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504) 
-[EFX-0012 VERI-INFO] undeclared symbol 'w_areset', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:21)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sysclk', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:22)
-[EFX-0012 VERI-INFO] undeclared symbol 'r_we_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:27)
-[EFX-0012 VERI-INFO] undeclared symbol 'r_re_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:28)
-[EFX-0012 VERI-INFO] undeclared symbol 'r_last_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:29)
-[EFX-0012 VERI-INFO] undeclared symbol 'r_addr_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:30)
-[EFX-0012 VERI-INFO] undeclared symbol 'r_din_1P', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:31)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dout', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:32)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_state', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:33)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_init_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:34)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_wr_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:35)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_rd_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:36)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_rd_valid', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:38)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_CKE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:40)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_CS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:41)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_RAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:42)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_CAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:43)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_n_WE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:44)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_BA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:45)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_ADDR', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:46)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DATA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:47)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DATA_oe', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:48)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_sdr_DQM', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:50)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_dly_cnt_b', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:52)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_tRCD_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:53)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_tRTW_done', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:54)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_ref_req', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:55)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_wr_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:56)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_rd_ack', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:57)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_CS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:58)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_RAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:59)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_CAS', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:60)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_n_WE', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:61)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_BA', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:62)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_ADDR', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:63)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_DATA_out', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:64)
-[EFX-0012 VERI-INFO] undeclared symbol 'w_dbg_DATA_in', assumed default net type 'wire' (VERI-2561) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:65)
-[EFX-0010 VERI-ERROR] cannot find port 'rst' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:155)
-[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
-[EFX-0010 VERI-ERROR] cannot find port 'clk_50' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:156)
-[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
-[EFX-0010 VERI-ERROR] cannot find port 'cpu_clk' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:157)
-[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
-[EFX-0010 VERI-ERROR] cannot find port 'addr' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:158)
-[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
-[EFX-0010 VERI-ERROR] cannot find port 'sdram_cs' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:159)
-[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
-[EFX-0010 VERI-ERROR] cannot find port 'rwb' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:160)
-[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
-[EFX-0010 VERI-ERROR] cannot find port 'data_in' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:161)
-[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
-[EFX-0010 VERI-ERROR] cannot find port 'data_out' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:162)
-[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CLK' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:165)
-[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_ADDR' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:166)
-[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_BA' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:167)
-[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:168)
-[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CKE' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:169)
-[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_CS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:170)
-[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_DQ' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:171)
-[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_UDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:172)
-[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_LDQM' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:173)
-[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_RAS_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:174)
-[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
-[EFX-0010 VERI-ERROR] cannot find port 'DRAM_WE_N' on this module (VERI-1010) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:175)
-[EFX-0012 VERI-INFO] 'sdram_adapter' is declared here (VERI-1310) (/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv:1)
-[EFX-0011 VERI-WARNING] port 'i_sysclk' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
-[EFX-0011 VERI-WARNING] port 'o_pll_reset' remains unconnected for this instance (VERI-1927) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
-[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
-[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
diff --git a/hw/efinix_fpga/outflow/super6502.map.out b/hw/efinix_fpga/outflow/super6502.map.out
deleted file mode 100644
index 515046e..0000000
--- a/hw/efinix_fpga/outflow/super6502.map.out
+++ /dev/null
@@ -1,113 +0,0 @@
-[EFX-0000 INFO] Efinix FPGA Synthesis.
-[EFX-0000 INFO] Version: 2021.2.323.4.6
-[EFX-0000 INFO] Compiled: May 12 2022.
-[EFX-0000 INFO] 
-[EFX-0000 INFO] Copyright (C) 2013 - 2021 Efinix Inc. All rights reserved.
-
-INFO: Read project database "/home/byron/Projects/super6502/hw/efinix_fpga/super6502.xml"
-INFO: ***** Beginning Analysis ... *****
-INFO: default VHDL library search path is now "/home/byron/Software/efinity/2021.2/sim_models/vhdl/packages/vhdl_2008" (VHDL-1504)
--- Analyzing Verilog file '/home/byron/Software/efinity/2021.2/sim_models/maplib/efinix_maplib.v' (VERI-1482)
--- Analyzing Verilog file '/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv' (VERI-1482)
--- Analyzing Verilog file '/home/byron/Projects/super6502/hw/efinix_fpga/crc7.sv' (VERI-1482)
--- Analyzing Verilog file '/home/byron/Projects/super6502/hw/efinix_fpga/memory_mapper.sv' (VERI-1482)
--- Analyzing Verilog file '/home/byron/Projects/super6502/hw/efinix_fpga/uart.sv' (VERI-1482)
--- Analyzing Verilog file '/home/byron/Projects/super6502/hw/efinix_fpga/HexDriver.sv' (VERI-1482)
--- Analyzing Verilog file '/home/byron/Projects/super6502/hw/efinix_fpga/addr_decode.sv' (VERI-1482)
--- Analyzing Verilog file '/home/byron/Projects/super6502/hw/efinix_fpga/board_io.sv' (VERI-1482)
--- Analyzing Verilog file '/home/byron/Projects/super6502/hw/efinix_fpga/SevenSeg.sv' (VERI-1482)
--- Analyzing Verilog file '/home/byron/Projects/super6502/hw/efinix_fpga/sd_controller.sv' (VERI-1482)
--- Analyzing Verilog file '/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv' (VERI-1482)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(21): INFO: undeclared symbol 'w_areset', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(22): INFO: undeclared symbol 'w_sysclk', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(27): INFO: undeclared symbol 'r_we_1P', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(28): INFO: undeclared symbol 'r_re_1P', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(29): INFO: undeclared symbol 'r_last_1P', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(30): INFO: undeclared symbol 'r_addr_1P', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(31): INFO: undeclared symbol 'r_din_1P', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(32): INFO: undeclared symbol 'w_dout', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(33): INFO: undeclared symbol 'w_sdr_state', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(34): INFO: undeclared symbol 'w_sdr_init_done', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(35): INFO: undeclared symbol 'w_wr_ack', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(36): INFO: undeclared symbol 'w_rd_ack', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(38): INFO: undeclared symbol 'w_rd_valid', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(40): INFO: undeclared symbol 'w_sdr_CKE', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(41): INFO: undeclared symbol 'w_sdr_n_CS', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(42): INFO: undeclared symbol 'w_sdr_n_RAS', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(43): INFO: undeclared symbol 'w_sdr_n_CAS', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(44): INFO: undeclared symbol 'w_sdr_n_WE', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(45): INFO: undeclared symbol 'w_sdr_BA', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(46): INFO: undeclared symbol 'w_sdr_ADDR', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(47): INFO: undeclared symbol 'w_sdr_DATA', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(48): INFO: undeclared symbol 'w_sdr_DATA_oe', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(50): INFO: undeclared symbol 'w_sdr_DQM', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(52): INFO: undeclared symbol 'w_dbg_dly_cnt_b', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(53): INFO: undeclared symbol 'w_dbg_tRCD_done', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(54): INFO: undeclared symbol 'w_dbg_tRTW_done', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(55): INFO: undeclared symbol 'w_dbg_ref_req', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(56): INFO: undeclared symbol 'w_dbg_wr_ack', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(57): INFO: undeclared symbol 'w_dbg_rd_ack', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(58): INFO: undeclared symbol 'w_dbg_n_CS', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(59): INFO: undeclared symbol 'w_dbg_n_RAS', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(60): INFO: undeclared symbol 'w_dbg_n_CAS', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(61): INFO: undeclared symbol 'w_dbg_n_WE', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(62): INFO: undeclared symbol 'w_dbg_BA', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(63): INFO: undeclared symbol 'w_dbg_ADDR', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(64): INFO: undeclared symbol 'w_dbg_DATA_out', assumed default net type 'wire' (VERI-2561)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(65): INFO: undeclared symbol 'w_dbg_DATA_in', assumed default net type 'wire' (VERI-2561)
--- Analyzing Verilog file '/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram/sdram.v' (VERI-1482)
-/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(155): ERROR: cannot find port 'rst' on this module (VERI-1010)
-/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(156): ERROR: cannot find port 'clk_50' on this module (VERI-1010)
-/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(157): ERROR: cannot find port 'cpu_clk' on this module (VERI-1010)
-/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(158): ERROR: cannot find port 'addr' on this module (VERI-1010)
-/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(159): ERROR: cannot find port 'sdram_cs' on this module (VERI-1010)
-/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(160): ERROR: cannot find port 'rwb' on this module (VERI-1010)
-/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(161): ERROR: cannot find port 'data_in' on this module (VERI-1010)
-/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(162): ERROR: cannot find port 'data_out' on this module (VERI-1010)
-/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(165): ERROR: cannot find port 'DRAM_CLK' on this module (VERI-1010)
-/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(166): ERROR: cannot find port 'DRAM_ADDR' on this module (VERI-1010)
-/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(167): ERROR: cannot find port 'DRAM_BA' on this module (VERI-1010)
-/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(168): ERROR: cannot find port 'DRAM_CAS_N' on this module (VERI-1010)
-/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(169): ERROR: cannot find port 'DRAM_CKE' on this module (VERI-1010)
-/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(170): ERROR: cannot find port 'DRAM_CS_N' on this module (VERI-1010)
-/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(171): ERROR: cannot find port 'DRAM_DQ' on this module (VERI-1010)
-/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(172): ERROR: cannot find port 'DRAM_UDQM' on this module (VERI-1010)
-/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(173): ERROR: cannot find port 'DRAM_LDQM' on this module (VERI-1010)
-/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(174): ERROR: cannot find port 'DRAM_RAS_N' on this module (VERI-1010)
-/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(175): ERROR: cannot find port 'DRAM_WE_N' on this module (VERI-1010)
-[EFX-0021 ERROR] Verific elaboration of module 'super6502' failed.
-INFO: Analysis took 0.0226114 seconds.
-INFO: 	Analysis took 0.02 seconds (approximately) in total CPU time.
-INFO: Analysis virtual memory usage: begin = 186.592 MB, end = 187.592 MB, delta = 1 MB
-INFO: Analysis resident set memory usage: begin = 73.968 MB, end = 77.944 MB, delta = 3.976 MB
-INFO: 	Analysis peak resident set memory usage = 634.104 MB
-INFO: ***** Ending Analysis ... *****
-INFO: ***** Beginning Elaboration ... *****
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
-/home/byron/Projects/super6502/hw/efinix_fpga/sdram_adapter.sv(1): INFO: 'sdram_adapter' is declared here (VERI-1310)
-/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(176): WARNING: port 'i_sysclk' is not connected on this instance (VERI-2435)
-/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(176): WARNING: port 'o_pll_reset' remains unconnected for this instance (VERI-1927)
-/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv(204): WARNING: port 'addr' is not connected on this instance (VERI-2435)
-INFO: Elaboration took 0.00132981 seconds.
-INFO: 	Elaboration took 0 seconds (approximately) in total CPU time.
-INFO: Elaboration virtual memory usage: begin = 187.592 MB, end = 187.592 MB, delta = 0 MB
-INFO: Elaboration resident set memory usage: begin = 77.944 MB, end = 77.944 MB, delta = 0 MB
-INFO: 	Elaboration peak resident set memory usage = 634.104 MB
-INFO: ***** Ending Elaboration ... *****
diff --git a/hw/efinix_fpga/outflow/super6502.warn.log b/hw/efinix_fpga/outflow/super6502.warn.log
deleted file mode 100644
index b8458e9..0000000
--- a/hw/efinix_fpga/outflow/super6502.warn.log
+++ /dev/null
@@ -1,93 +0,0 @@
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 09, 2022 21:36:12
-///////////////////////////////////
-
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 09, 2022 21:36:40
-///////////////////////////////////
-
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 09, 2022 21:42:28
-///////////////////////////////////
-
-[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
-[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
-[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 11, 2022 12:05:39
-///////////////////////////////////
-
-[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
-[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
-[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 11, 2022 19:19:40
-///////////////////////////////////
-
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 11, 2022 19:20:04
-///////////////////////////////////
-
-[EFX-0011 VERI-WARNING] port 'i_we' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
-[EFX-0011 VERI-WARNING] port 'o_dbg_tRTW_done' remains unconnected for this instance (VERI-1927) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
-[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 11, 2022 19:20:55
-///////////////////////////////////
-
-[EFX-0011 VERI-WARNING] port 'i_we' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
-[EFX-0011 VERI-WARNING] port 'o_dbg_tRTW_done' remains unconnected for this instance (VERI-1927) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
-[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 11, 2022 19:21:29
-///////////////////////////////////
-
-[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
-[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
-[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 11, 2022 19:21:33
-///////////////////////////////////
-
-[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
-[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_in' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:115)
-[EFX-0011 VERI-WARNING] actual bit length 8 differs from formal bit length 12 for port 'data_out' (VERI-1330) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:116)
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 13, 2022 19:05:46
-///////////////////////////////////
-
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 13, 2022 19:08:09
-///////////////////////////////////
-
-
-///////////////////////////////////
-// Efinity Synthesis Started 
-// Jun 13, 2022 19:08:21
-///////////////////////////////////
-
-[EFX-0011 VERI-WARNING] port 'i_sysclk' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
-[EFX-0011 VERI-WARNING] port 'o_pll_reset' remains unconnected for this instance (VERI-1927) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:176)
-[EFX-0011 VERI-WARNING] port 'addr' is not connected on this instance (VERI-2435) (/home/byron/Projects/super6502/hw/efinix_fpga/super6502.sv:204)
diff --git a/hw/efinix_fpga/sd_controller.sv b/hw/efinix_fpga/sd_controller.sv
deleted file mode 100644
index 54b7001..0000000
--- a/hw/efinix_fpga/sd_controller.sv
+++ /dev/null
@@ -1,235 +0,0 @@
-module sd_controller(
-    input clk,
-    input sd_clk,
-    input rst,
-
-    input [2:0] addr,
-    input [7:0] data,
-    input cs,
-    input rw,
-
-    input i_sd_cmd,
-    output logic o_sd_cmd,
-
-    input i_sd_data,
-    output logic o_sd_data,
-
-    output logic [7:0] data_out
-);
-
-logic [31:0] arg;
-logic [5:0] cmd;
-
-logic [47:0] rxcmd_buf;
-logic [31:0] rx_val;
-
-logic [7:0] rxdata_buf [512];
-logic [8:0] data_count;
-
-logic [15:0] data_crc;
-
-
-assign rx_val = rxcmd_buf[39:8];
-
-always_comb begin
-    data_out = 'x;
-
-    if (addr < 4'h4) begin
-        data_out = rx_val[8 * addr +: 8];
-    end else if (addr == 4'h4) begin
-        data_out = {data_flag, read_flag};
-    end else if (addr == 4'h5) begin
-        data_out = rxdata_buf[data_count];
-    end
-end
-
-logic read_flag, next_read_flag;
-logic data_flag, next_data_flag;
-
-typedef enum bit [2:0] {IDLE, LOAD, CRC, TXCMD, RXCMD, TXDATA, RXDATA, RXDCRC} macro_t;
-struct packed {
-    macro_t macro;
-    logic [8:0] count;
-    logic [2:0] d_bit_count;
-} state, next_state;
-
-always_ff @(posedge clk) begin
-    if (rst) begin
-        state.macro <= IDLE;
-        state.count <= '0;
-        state.d_bit_count <= '1;
-        read_flag <= '0;
-        data_flag <= '0;
-        data_count <= '0;
-    end else begin
-        if (state.macro == TXCMD || state.macro == CRC) begin
-            if (sd_clk) begin
-                state <= next_state;
-            end
-        end else if (state.macro == RXCMD || state.macro == RXDATA || state.macro == RXDCRC) begin
-            if (~sd_clk) begin
-                state <= next_state;
-            end
-        end else begin
-            state <= next_state;
-        end
-    end
-
-    if (sd_clk) begin
-        read_flag <= next_read_flag;
-        data_flag <= next_data_flag;
-    end
-
-    if (cs & ~rw) begin
-        if (addr < 4'h4) begin
-            arg[8 * addr +: 8] <= data;
-        end else if (addr == 4'h4) begin
-            cmd <= data[6:0];
-        end
-    end
-
-    if (cs & addr == 4'h5 && sd_clk) begin
-        data_count <= data_count + 8'b1;
-    end
-
-    if (state.macro == RXCMD) begin
-        rxcmd_buf[6'd46-state.count] <= i_sd_cmd;   //we probabily missed bit 47
-    end
-
-    if (state.macro == RXDATA && ~sd_clk) begin
-        rxdata_buf[state.count][state.d_bit_count] <= i_sd_data;
-    end
-
-    if (state.macro == RXDCRC && ~sd_clk) begin
-        data_crc[4'd15-state.count] <= i_sd_data;
-        data_count <= '0;
-    end
-
-end
-
-logic [6:0] crc;
-logic load_crc;
-logic crc_valid;
-logic [39:0] _packet;
-assign _packet = {1'b0, 1'b1, cmd, arg};
-logic [47:0] packet_crc;
-assign packet_crc = {_packet, crc, 1'b1};
-
-crc7 u_crc7(
-    .clk(clk),
-    .rst(rst),
-    .load(load_crc),
-    .data_in(_packet),
-    .crc_out(crc),
-    .valid(crc_valid)
-);
-
-always_comb begin
-    next_state = state;
-    next_read_flag = read_flag;
-    next_data_flag = data_flag;
-
-    case (state.macro)
-        IDLE: begin
-            if (~i_sd_cmd) begin        // receive data if sd pulls cmd low
-                next_state.macro = RXCMD;
-            end
-
-            if (~i_sd_data) begin
-                next_state.d_bit_count = '1;
-                next_state.macro = RXDATA;
-            end
-
-            if (addr == 4'h4 & cs & ~rw) begin     // transmit if cpu writes to cmd
-                next_state.macro = LOAD;
-            end
-
-            if (addr == 4'h4 & cs & rw) begin
-                next_read_flag = '0;
-            end
-
-            if (addr == 4'h5 & cs) begin
-                next_data_flag = '0;
-            end
-        end
-
-        LOAD: begin
-            next_state.macro = CRC;
-        end
-
-        CRC: begin
-            next_state.macro = TXCMD;
-        end
-
-        TXCMD: begin
-            if (state.count < 47) begin
-                next_state.count = state.count + 6'b1;
-            end else begin
-                next_state.macro = IDLE;
-                next_state.count = '0;
-            end
-        end
-
-        RXCMD: begin
-            if (state.count < 47) begin
-                next_state.count = state.count + 6'b1;
-            end else begin
-                next_read_flag = '1;
-                next_state.macro = IDLE;
-                next_state.count = '0;
-            end
-        end
-
-        RXDATA: begin
-            if (state.count < 511 || (state.count == 511 && state.d_bit_count > 0)) begin
-                if (state.d_bit_count == 8'h0) begin
-                    next_state.count = state.count + 9'b1;
-                end
-                next_state.d_bit_count = state.d_bit_count - 3'h1;
-            end else begin
-                next_data_flag = '1;
-                next_state.macro = RXDCRC;
-                next_state.count = '0;
-            end
-        end
-
-        RXDCRC: begin
-            if (state.count < 16) begin
-                next_state.count = state.count + 9'b1;
-            end else begin
-                next_state.macro = IDLE;
-                next_state.count = '0;
-            end
-        end
-
-        default: begin
-                next_state.macro = IDLE;
-                next_state.count = '0;
-        end
-    endcase
-end
-
-always_comb begin
-    o_sd_cmd = '1;  //default to 1
-    o_sd_data = '1;
-
-    load_crc = '0;
-
-    case (state.macro)
-        IDLE:;
-
-        CRC: begin
-            load_crc = '1;
-        end
-
-        TXCMD: begin
-            o_sd_cmd = packet_crc[6'd47 - state.count];
-        end
-
-        RXCMD:;
-
-        default:;
-    endcase
-end
-
-endmodule
diff --git a/hw/efinix_fpga/sdram_adapter.sv b/hw/efinix_fpga/sdram_adapter.sv
deleted file mode 100644
index ace4eba..0000000
--- a/hw/efinix_fpga/sdram_adapter.sv
+++ /dev/null
@@ -1,68 +0,0 @@
-module sdram_adapter(
-    input   i_sysclk,
-    input   i_sdrclk,
-    input   i_tACclk,
-    input   i_pll_locked,
-    output  o_pll_reset,
-    output  o_sdr_CKE,
-    output  o_sdr_n_CS,
-    output  o_sdr_n_WE,
-    output  o_sdr_n_RAS,
-    output  o_sdr_n_CAS,
-    output  [1:0]o_sdr_BA,
-    output  [12:0]o_sdr_ADDR,
-    input   [15:0]i_sdr_DATA,
-    output  [15:0]o_sdr_DATA,
-    output  [15:0]o_sdr_DATA_oe,
-    output  [1:0]o_sdr_DQM
-);
-
-sdram u_sdram (
-    .i_arst             (w_areset),
-    .i_sysclk           (w_sysclk),
-    .i_sdrclk           (i_sdrclk),
-    .i_tACclk           (i_tACclk),
-    .i_pll_locked       (1'b1),
-
-    .i_we               (r_we_1P),
-    .i_re               (r_re_1P),
-    .i_last             (r_last_1P),
-    .i_addr             (r_addr_1P),
-    .i_din              (r_din_1P),
-    .o_dout             (w_dout),
-    .o_sdr_state        (w_sdr_state),
-    .o_sdr_init_done    (w_sdr_init_done),
-    .o_wr_ack           (w_wr_ack),
-    .o_rd_ack           (w_rd_ack),
-    .o_ref_req          (),
-    .o_rd_valid         (w_rd_valid),
-
-    .o_sdr_CKE          (w_sdr_CKE),
-    .o_sdr_n_CS         (w_sdr_n_CS),
-    .o_sdr_n_RAS        (w_sdr_n_RAS),
-    .o_sdr_n_CAS        (w_sdr_n_CAS),
-    .o_sdr_n_WE         (w_sdr_n_WE),
-    .o_sdr_BA           (w_sdr_BA),
-    .o_sdr_ADDR         (w_sdr_ADDR),
-    .o_sdr_DATA         (w_sdr_DATA),
-    .o_sdr_DATA_oe      (w_sdr_DATA_oe),
-    .i_sdr_DATA         ({{16{1'b0}}, i_sdr_DATA}),
-    .o_sdr_DQM          (w_sdr_DQM),
-
-    .o_dbg_dly_cnt_b    (w_dbg_dly_cnt_b),
-    .o_dbg_tRCD_done    (w_dbg_tRCD_done),
-    .o_dbg_tRTW_done    (w_dbg_tRTW_done),
-    .o_dbg_ref_req      (w_dbg_ref_req),
-    .o_dbg_wr_ack       (w_dbg_wr_ack),
-    .o_dbg_rd_ack       (w_dbg_rd_ack),
-    .o_dbg_n_CS         (w_dbg_n_CS),
-    .o_dbg_n_RAS        (w_dbg_n_RAS),
-    .o_dbg_n_CAS        (w_dbg_n_CAS),
-    .o_dbg_n_WE         (w_dbg_n_WE),
-    .o_dbg_BA           (w_dbg_BA),
-    .o_dbg_ADDR         (w_dbg_ADDR),
-    .o_dbg_DATA_out     (w_dbg_DATA_out),
-    .o_dbg_DATA_in      (w_dbg_DATA_in)
-);
-
-endmodule
diff --git a/hw/efinix_fpga/super6502.peri.pre_import.xml b/hw/efinix_fpga/super6502.peri.pre_import.xml
deleted file mode 100644
index 8a7e173..0000000
--- a/hw/efinix_fpga/super6502.peri.pre_import.xml
+++ /dev/null
@@ -1,275 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2021.2.323.4.6" db_version="20212999" last_change_date="Sat Jun 11 18:46:25 2022" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
-    <efxpt:device_info>
-        <efxpt:iobank_info>
-            <efxpt:iobank name="1A" iostd="3.3 V LVTTL / LVCMOS"/>
-            <efxpt:iobank name="1B_1C" iostd="3.3 V LVTTL / LVCMOS"/>
-            <efxpt:iobank name="1D_1E" iostd="3.3 V LVTTL / LVCMOS"/>
-            <efxpt:iobank name="3A_3B_3C" iostd="3.3 V LVTTL / LVCMOS"/>
-            <efxpt:iobank name="3D_3E" iostd="3.3 V LVTTL / LVCMOS"/>
-            <efxpt:iobank name="4A" iostd="3.3 V LVTTL / LVCMOS"/>
-            <efxpt:iobank name="4B" iostd="3.3 V LVTTL / LVCMOS"/>
-            <efxpt:iobank name="BR" iostd="1.2 V"/>
-            <efxpt:iobank name="TL" iostd="1.2 V"/>
-            <efxpt:iobank name="TR" iostd="1.2 V"/>
-        </efxpt:iobank_info>
-        <efxpt:ctrl_info>
-            <efxpt:ctrl name="cfg" ctrl_def="CONFIG_CTRL0" clock_name="" is_clk_invert="false" cbsel_bus_name="cfg_CBSEL" config_ctrl_name="cfg_CONFIG" ena_capture_name="cfg_ENA" error_status_name="cfg_ERROR" um_signal_status_name="cfg_USR_STATUS" is_remote_update_enable="false" is_user_mode_enable="false"/>
-        </efxpt:ctrl_info>
-    </efxpt:device_info>
-    <efxpt:gpio_info device_def="T20F256">
-        <efxpt:gpio name="i_BRPLL_clkin" gpio_def="GPIOR_157" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_BRPLL_clkin" name_ddio_lo="" conn_type="pll_clkin" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="i_sw2" gpio_def="GPIOL_02" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sw2" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="i_sw3" gpio_def="GPIOL_04" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sw3" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[0]" gpio_def="GPIOR_92" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[0]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[0]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[10]" gpio_def="GPIOR_116" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[10]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[10]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[10]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[11]" gpio_def="GPIOR_108" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[11]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[11]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[11]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[12]" gpio_def="GPIOR_112" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[12]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[12]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[12]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[13]" gpio_def="GPIOR_106" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[13]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[13]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[13]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[14]" gpio_def="GPIOR_98" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[14]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[14]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[14]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[15]" gpio_def="GPIOR_94" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[15]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[15]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[15]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[1]" gpio_def="GPIOR_90" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[1]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[1]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[2]" gpio_def="GPIOR_97" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[2]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[2]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[2]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[3]" gpio_def="GPIOR_95" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[3]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[3]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[3]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[4]" gpio_def="GPIOR_93" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[4]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[4]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[4]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[5]" gpio_def="GPIOR_83" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[5]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[5]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[5]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[6]" gpio_def="GPIOR_84" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[6]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[6]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[6]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[7]" gpio_def="GPIOR_82" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[7]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[7]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[7]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[8]" gpio_def="GPIOR_136" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[8]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[8]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[8]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[9]" gpio_def="GPIOR_119" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[9]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[9]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[9]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_dbg[0]" gpio_def="GPIOL_11" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_dbg[0]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_dbg[10]" gpio_def="GPIOL_16" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_dbg[10]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_dbg[11]" gpio_def="GPIOL_37" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_dbg[11]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_dbg[12]" gpio_def="GPIOL_18" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_dbg[12]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_dbg[13]" gpio_def="GPIOL_36" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_dbg[13]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_dbg[14]" gpio_def="GPIOL_19" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_dbg[14]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_dbg[15]" gpio_def="GPIOL_35" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_dbg[15]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_dbg[1]" gpio_def="GPIOL_43" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_dbg[1]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_dbg[2]" gpio_def="GPIOL_12" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_dbg[2]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_dbg[3]" gpio_def="GPIOL_42" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_dbg[3]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_dbg[4]" gpio_def="GPIOL_13" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_dbg[4]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_dbg[5]" gpio_def="GPIOL_41" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_dbg[5]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_dbg[6]" gpio_def="GPIOL_14" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_dbg[6]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_dbg[7]" gpio_def="GPIOL_40" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_dbg[7]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_dbg[8]" gpio_def="GPIOL_15" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_dbg[8]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_dbg[9]" gpio_def="GPIOL_39" mode="output" bus_name="o_dbg" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_dbg[9]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_dbg_sdr_CK" gpio_def="GPIOR_76" mode="clkout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="" name_ddio_lo="" register_option="none" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_dbg_sdr_CKn" gpio_def="GPIOR_78" mode="clkout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="" name_ddio_lo="" register_option="none" clock_name="i_sdrclk" is_clock_inverted="true" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_led[0]" gpio_def="GPIOR_104" mode="output" bus_name="o_led" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_led[0]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_led[1]" gpio_def="GPIOR_105" mode="output" bus_name="o_led" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_led[1]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_led[2]" gpio_def="GPIOR_117" mode="output" bus_name="o_led" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_led[2]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_led[3]" gpio_def="GPIOR_118" mode="output" bus_name="o_led" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_led[3]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_led[4]" gpio_def="GPIOR_153" mode="output" bus_name="o_led" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_led[4]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_led[5]" gpio_def="GPIOR_154" mode="output" bus_name="o_led" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_led[5]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_led[6]" gpio_def="GPIOR_155" mode="output" bus_name="o_led" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_led[6]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_led[7]" gpio_def="GPIOR_156" mode="output" bus_name="o_led" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_led[7]" name_ddio_lo="" register_option="register" clock_name="i_sysclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[0]" gpio_def="GPIOR_85" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[10]" gpio_def="GPIOR_89" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[10]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[11]" gpio_def="GPIOR_143" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[11]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[12]" gpio_def="GPIOR_144" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[12]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[1]" gpio_def="GPIOR_87" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[2]" gpio_def="GPIOR_86" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[2]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[3]" gpio_def="GPIOR_88" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[3]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[4]" gpio_def="GPIOR_133" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[4]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[5]" gpio_def="GPIOR_135" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[5]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[6]" gpio_def="GPIOR_131" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[6]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[7]" gpio_def="GPIOR_148" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[7]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[8]" gpio_def="GPIOR_138" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[8]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[9]" gpio_def="GPIOR_147" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[9]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_BA[0]" gpio_def="GPIOR_102" mode="output" bus_name="o_sdr_BA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_BA[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_BA[1]" gpio_def="GPIOR_99" mode="output" bus_name="o_sdr_BA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_BA[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_CK" gpio_def="GPIOR_146" mode="clkout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="" name_ddio_lo="" register_option="none" clock_name="i_sdrclk" is_clock_inverted="true" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_CKE" gpio_def="GPIOR_145" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_CKE" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_DQM[0]" gpio_def="GPIOR_80" mode="output" bus_name="o_sdr_DQM" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_DQM[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_DQM[1]" gpio_def="GPIOR_132" mode="output" bus_name="o_sdr_DQM" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_DQM[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_n_CAS" gpio_def="GPIOR_139" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_n_CAS" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="2"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_n_CS" gpio_def="GPIOR_103" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_n_CS" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_n_RAS" gpio_def="GPIOR_91" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_n_RAS" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_n_WE" gpio_def="GPIOR_141" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_n_WE" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:global_unused_config state="input with weak pullup"/>
-        <efxpt:bus name="io_sdr_DATA" mode="inout" msb="15" lsb="0"/>
-        <efxpt:bus name="o_dbg" mode="output" msb="15" lsb="0"/>
-        <efxpt:bus name="o_led" mode="output" msb="7" lsb="0"/>
-        <efxpt:bus name="o_sdr_ADDR" mode="output" msb="12" lsb="0"/>
-        <efxpt:bus name="o_sdr_BA" mode="output" msb="1" lsb="0"/>
-        <efxpt:bus name="o_sdr_DQM" mode="output" msb="1" lsb="0"/>
-    </efxpt:gpio_info>
-    <efxpt:pll_info>
-        <efxpt:pll name="pll_inst1" pll_def="PLL_BR0" ref_clock_name="" ref_clock_freq="50.00" multiplier="8" pre_divider="4" post_divider="2" reset_name="o_pll_reset" locked_name="i_pll_locked" is_ipfrz="false" is_bypass_lock="true">
-            <efxpt:output_clock name="i_sdrclk" number="0" out_divider="2" adv_out_phase_shift="0"/>
-            <efxpt:output_clock name="i_tACclk" number="1" out_divider="2" adv_out_phase_shift="0"/>
-            <efxpt:output_clock name="i_sysclk" number="2" out_divider="4" adv_out_phase_shift="0"/>
-            <efxpt:adv_prop ref_clock_mode="external" ref_clock1_name="" ext_ref_clock_id="2" clksel_name="" feedback_clock_name="i_sysclk" feedback_mode="core"/>
-        </efxpt:pll>
-    </efxpt:pll_info>
-    <efxpt:lvds_info/>
-    <efxpt:jtag_info/>
-</efxpt:design_db>
diff --git a/hw/efinix_fpga/super6502.peri.xml b/hw/efinix_fpga/super6502.peri.xml
index 105f9ed..b6916c0 100644
--- a/hw/efinix_fpga/super6502.peri.xml
+++ b/hw/efinix_fpga/super6502.peri.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2021.2.323.4.6" db_version="20212999" last_change_date="Sat Jun 11 19:20:20 2022" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
+<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2021.2.323.4.6" db_version="20212999" last_change_date="Tue Nov  1 18:31:26 2022" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
     <efxpt:device_info>
         <efxpt:iobank_info>
             <efxpt:iobank name="1A" iostd="3.3 V LVTTL / LVCMOS"/>
@@ -18,177 +18,130 @@
         </efxpt:ctrl_info>
     </efxpt:device_info>
     <efxpt:gpio_info device_def="T20F256">
-        <efxpt:gpio name="gpio_inst41" gpio_def="" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="gpio_inst41" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+        <efxpt:gpio name="button_reset" gpio_def="GPIOL_02" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="button_reset" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
         </efxpt:gpio>
-        <efxpt:gpio name="i_BRPLL_clkin" gpio_def="GPIOR_157" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_BRPLL_clkin" name_ddio_lo="" conn_type="pll_clkin" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+        <efxpt:gpio name="cpu_addr[0]" gpio_def="GPIOL_65" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="cpu_addr[0]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
         </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[0]" gpio_def="GPIOR_92" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[0]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[0]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        <efxpt:gpio name="cpu_addr[10]" gpio_def="GPIOL_46" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="cpu_addr[10]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
         </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[10]" gpio_def="GPIOR_116" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[10]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[10]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[10]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        <efxpt:gpio name="cpu_addr[11]" gpio_def="GPIOL_44" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="cpu_addr[11]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
         </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[11]" gpio_def="GPIOR_108" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[11]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[11]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[11]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        <efxpt:gpio name="cpu_addr[12]" gpio_def="GPIOL_45" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="cpu_addr[12]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
         </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[12]" gpio_def="GPIOR_112" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[12]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[12]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[12]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        <efxpt:gpio name="cpu_addr[13]" gpio_def="GPIOL_47" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="cpu_addr[13]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
         </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[13]" gpio_def="GPIOR_106" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[13]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[13]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[13]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        <efxpt:gpio name="cpu_addr[14]" gpio_def="GPIOL_49" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="cpu_addr[14]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
         </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[14]" gpio_def="GPIOR_98" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[14]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[14]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[14]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        <efxpt:gpio name="cpu_addr[15]" gpio_def="GPIOL_51" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="cpu_addr[15]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
         </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[15]" gpio_def="GPIOR_94" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[15]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[15]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[15]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        <efxpt:gpio name="cpu_addr[1]" gpio_def="GPIOL_63" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="cpu_addr[1]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
         </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[1]" gpio_def="GPIOR_90" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[1]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[1]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        <efxpt:gpio name="cpu_addr[2]" gpio_def="GPIOL_62" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="cpu_addr[2]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
         </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[2]" gpio_def="GPIOR_97" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[2]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[2]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[2]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        <efxpt:gpio name="cpu_addr[3]" gpio_def="GPIOL_60" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="cpu_addr[3]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
         </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[3]" gpio_def="GPIOR_95" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[3]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[3]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[3]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        <efxpt:gpio name="cpu_addr[4]" gpio_def="GPIOL_58" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="cpu_addr[4]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
         </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[4]" gpio_def="GPIOR_93" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[4]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[4]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[4]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        <efxpt:gpio name="cpu_addr[5]" gpio_def="GPIOL_56" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="cpu_addr[5]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
         </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[5]" gpio_def="GPIOR_83" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[5]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[5]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[5]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        <efxpt:gpio name="cpu_addr[6]" gpio_def="GPIOL_54" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="cpu_addr[6]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
         </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[6]" gpio_def="GPIOR_84" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[6]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[6]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[6]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        <efxpt:gpio name="cpu_addr[7]" gpio_def="GPIOL_52" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="cpu_addr[7]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
         </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[7]" gpio_def="GPIOR_82" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[7]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[7]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[7]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        <efxpt:gpio name="cpu_addr[8]" gpio_def="GPIOL_50" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="cpu_addr[8]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
         </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[8]" gpio_def="GPIOR_136" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[8]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[8]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[8]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        <efxpt:gpio name="cpu_addr[9]" gpio_def="GPIOL_48" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="cpu_addr[9]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
         </efxpt:gpio>
-        <efxpt:gpio name="io_sdr_DATA[9]" gpio_def="GPIOR_119" mode="inout" bus_name="io_sdr_DATA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:input_config name="i_sdr_DATA[9]" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
-            <efxpt:output_config name="o_sdr_DATA[9]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-            <efxpt:output_enable_config name="o_sdr_DATA_oe[9]" is_register="true" clock_name="i_sdrclk" is_clock_inverted="false"/>
+        <efxpt:gpio name="cpu_clk" gpio_def="GPIOL_71" mode="clkout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="" name_ddio_lo="" register_option="none" clock_name="clk_2" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
         </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[0]" gpio_def="GPIOR_85" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        <efxpt:gpio name="cpu_data[0]" gpio_def="GPIOL_68" mode="inout" bus_name="cpu_data" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="cpu_data_in[0]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="cpu_data_out[0]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="cpu_data_oe[0]" is_register="false" clock_name="" is_clock_inverted="false"/>
         </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[10]" gpio_def="GPIOR_89" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[10]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        <efxpt:gpio name="cpu_data[1]" gpio_def="GPIOL_66" mode="inout" bus_name="cpu_data" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="cpu_data_in[1]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="cpu_data_out[1]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="cpu_data_oe[1]" is_register="false" clock_name="" is_clock_inverted="false"/>
         </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[11]" gpio_def="GPIOR_143" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[11]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        <efxpt:gpio name="cpu_data[2]" gpio_def="GPIOL_64" mode="inout" bus_name="cpu_data" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="cpu_data_in[2]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="cpu_data_out[2]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="cpu_data_oe[2]" is_register="false" clock_name="" is_clock_inverted="false"/>
         </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[12]" gpio_def="GPIOR_144" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[12]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        <efxpt:gpio name="cpu_data[3]" gpio_def="GPIOL_61" mode="inout" bus_name="cpu_data" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="cpu_data_in[3]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="cpu_data_out[3]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="cpu_data_oe[3]" is_register="false" clock_name="" is_clock_inverted="false"/>
         </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[1]" gpio_def="GPIOR_87" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        <efxpt:gpio name="cpu_data[4]" gpio_def="GPIOL_59" mode="inout" bus_name="cpu_data" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="cpu_data_in[4]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="cpu_data_out[4]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="cpu_data_oe[4]" is_register="false" clock_name="" is_clock_inverted="false"/>
         </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[2]" gpio_def="GPIOR_86" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[2]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        <efxpt:gpio name="cpu_data[5]" gpio_def="GPIOL_57" mode="inout" bus_name="cpu_data" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="cpu_data_in[5]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="cpu_data_out[5]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="cpu_data_oe[5]" is_register="false" clock_name="" is_clock_inverted="false"/>
         </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[3]" gpio_def="GPIOR_88" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[3]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        <efxpt:gpio name="cpu_data[6]" gpio_def="GPIOL_55" mode="inout" bus_name="cpu_data" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="cpu_data_in[6]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="cpu_data_out[6]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="cpu_data_oe[6]" is_register="false" clock_name="" is_clock_inverted="false"/>
         </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[4]" gpio_def="GPIOR_133" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[4]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        <efxpt:gpio name="cpu_data[7]" gpio_def="GPIOL_53" mode="inout" bus_name="cpu_data" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="cpu_data_in[7]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
+            <efxpt:output_config name="cpu_data_out[7]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+            <efxpt:output_enable_config name="cpu_data_oe[7]" is_register="false" clock_name="" is_clock_inverted="false"/>
         </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[5]" gpio_def="GPIOR_135" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[5]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        <efxpt:gpio name="cpu_irqb" gpio_def="GPIOL_72" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="cpu_irqb" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
         </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[6]" gpio_def="GPIOR_131" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[6]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        <efxpt:gpio name="cpu_nmib" gpio_def="GPIOL_69" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="cpu_nmib" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
         </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[7]" gpio_def="GPIOR_148" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[7]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        <efxpt:gpio name="cpu_rdy" gpio_def="GPIOL_74" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="cpu_rdy" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
         </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[8]" gpio_def="GPIOR_138" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[8]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        <efxpt:gpio name="cpu_resb" gpio_def="GPIOL_73" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:output_config name="cpu_resb" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
         </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_ADDR[9]" gpio_def="GPIOR_147" mode="output" bus_name="o_sdr_ADDR" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_ADDR[9]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        <efxpt:gpio name="cpu_rwb" gpio_def="GPIOL_70" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="cpu_rwb" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
         </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_BA[0]" gpio_def="GPIOR_102" mode="output" bus_name="o_sdr_BA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_BA[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        <efxpt:gpio name="cpu_sync" gpio_def="GPIOL_67" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="cpu_sync" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
         </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_BA[1]" gpio_def="GPIOR_99" mode="output" bus_name="o_sdr_BA" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_BA[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_CK" gpio_def="GPIOR_146" mode="clkout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="" name_ddio_lo="" register_option="none" clock_name="i_sdrclk" is_clock_inverted="true" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_CKE" gpio_def="GPIOR_145" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_CKE" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_DQM[0]" gpio_def="GPIOR_80" mode="output" bus_name="o_sdr_DQM" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_DQM[0]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_DQM[1]" gpio_def="GPIOR_132" mode="output" bus_name="o_sdr_DQM" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_DQM[1]" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_n_CAS" gpio_def="GPIOR_139" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_n_CAS" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="2"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_n_CS" gpio_def="GPIOR_103" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_n_CS" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_n_RAS" gpio_def="GPIOR_91" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_n_RAS" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
-        </efxpt:gpio>
-        <efxpt:gpio name="o_sdr_n_WE" gpio_def="GPIOR_141" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
-            <efxpt:output_config name="o_sdr_n_WE" name_ddio_lo="" register_option="register" clock_name="i_sdrclk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
+        <efxpt:gpio name="pll_in" gpio_def="GPIOR_157" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
+            <efxpt:input_config name="pll_in" name_ddio_lo="" conn_type="pll_clkin" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
         </efxpt:gpio>
         <efxpt:global_unused_config state="input with weak pullup"/>
-        <efxpt:bus name="io_sdr_DATA" mode="inout" msb="15" lsb="0"/>
-        <efxpt:bus name="o_sdr_ADDR" mode="output" msb="12" lsb="0"/>
-        <efxpt:bus name="o_sdr_BA" mode="output" msb="1" lsb="0"/>
-        <efxpt:bus name="o_sdr_DQM" mode="output" msb="1" lsb="0"/>
+        <efxpt:bus name="cpu_data" mode="inout" msb="7" lsb="0"/>
+        <efxpt:bus name="cpu_addr" mode="output" msb="15" lsb="0"/>
     </efxpt:gpio_info>
     <efxpt:pll_info>
-        <efxpt:pll name="sdram_pll" pll_def="PLL_BR0" ref_clock_name="" ref_clock_freq="50.00" multiplier="2" pre_divider="1" post_divider="8" reset_name="o_pll_reset" locked_name="i_pll_locked" is_ipfrz="false" is_bypass_lock="true">
-            <efxpt:output_clock name="i_sdrclk" number="0" out_divider="1" adv_out_phase_shift="0"/>
-            <efxpt:output_clock name="i_tACclk" number="1" out_divider="1" adv_out_phase_shift="0"/>
-            <efxpt:output_clock name="i_sysclk" number="2" out_divider="2" adv_out_phase_shift="0"/>
-            <efxpt:adv_prop ref_clock_mode="external" ref_clock1_name="" ext_ref_clock_id="3" clksel_name="" feedback_clock_name="i_sysclk" feedback_mode="core"/>
-        </efxpt:pll>
-        <efxpt:pll name="cpu_clk_pll" pll_def="PLL_TL0" ref_clock_name="i_BRPLL_clkin" ref_clock_freq="100.00" multiplier="32" pre_divider="2" post_divider="8" reset_name="" locked_name="" is_ipfrz="false" is_bypass_lock="true">
-            <efxpt:output_clock name="cpu_clk_pll_CLKOUT0" number="0" out_divider="25" adv_out_phase_shift="0"/>
-            <efxpt:adv_prop ref_clock_mode="core" ref_clock1_name="" ext_ref_clock_id="3" clksel_name="" feedback_clock_name="" feedback_mode="internal"/>
+        <efxpt:pll name="pll_cpu_clk" pll_def="PLL_BR0" ref_clock_name="" ref_clock_freq="50.00" multiplier="16" pre_divider="1" post_divider="8" reset_name="pll_cpu_reset" locked_name="pll_cpu_locked" is_ipfrz="false" is_bypass_lock="true">
+            <efxpt:output_clock name="clk_50" number="0" out_divider="2" adv_out_phase_shift="0"/>
+            <efxpt:output_clock name="clk_2" number="1" out_divider="50" adv_out_phase_shift="0"/>
+            <efxpt:adv_prop ref_clock_mode="external" ref_clock1_name="" ext_ref_clock_id="3" clksel_name="" feedback_clock_name="" feedback_mode="internal"/>
         </efxpt:pll>
     </efxpt:pll_info>
     <efxpt:lvds_info/>
diff --git a/hw/efinix_fpga/super6502.pt.sdc b/hw/efinix_fpga/super6502.pt.sdc
new file mode 100644
index 0000000..d27a80e
--- /dev/null
+++ b/hw/efinix_fpga/super6502.pt.sdc
@@ -0,0 +1,114 @@
+
+# Efinity Interface Designer SDC
+# Version: 2021.2.323.4.6
+# Date: 2022-11-01 18:17
+
+# Copyright (C) 2017 - 2021 Efinix Inc. All rights reserved.
+
+# Device: T20F256
+# Project: super6502
+# Timing Model: C4 (final)
+
+# PLL Constraints
+#################
+create_clock -period 20.00 clk_50
+create_clock -period 500.00 clk_2
+
+# GPIO Constraints
+####################
+# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {button_reset}]
+# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {button_reset}]
+# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_sync}]
+# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_sync}]
+# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {pll_in}]
+# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {pll_in}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[0]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[0]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[1]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[1]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[2]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[2]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[3]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[3]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[4]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[4]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[5]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[5]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[6]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[6]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[7]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[7]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[8]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[8]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[9]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[9]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[10]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[10]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[11]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[11]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[12]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[12]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[13]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[13]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[14]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[14]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[15]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[15]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_irqb}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_irqb}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_nmib}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_nmib}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_rdy}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_rdy}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_resb}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_resb}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_rwb}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_rwb}]
+# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[0]}]
+# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[0]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[0]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[0]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[0]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[0]}]
+# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[1]}]
+# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[1]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[1]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[1]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[1]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[1]}]
+# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[2]}]
+# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[2]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[2]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[2]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[2]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[2]}]
+# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[3]}]
+# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[3]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[3]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[3]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[3]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[3]}]
+# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[4]}]
+# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[4]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[4]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[4]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[4]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[4]}]
+# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[5]}]
+# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[5]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[5]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[5]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[5]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[5]}]
+# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[6]}]
+# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[6]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[6]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[6]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[6]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[6]}]
+# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[7]}]
+# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[7]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[7]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[7]}]
+# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[7]}]
+# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[7]}]
diff --git a/hw/efinix_fpga/super6502.sv b/hw/efinix_fpga/super6502.sv
index 89f3a74..3293d66 100644
--- a/hw/efinix_fpga/super6502.sv
+++ b/hw/efinix_fpga/super6502.sv
@@ -1,256 +1,39 @@
+module super6502
+(
+  input [7:0] cpu_data_in,
+  input cpu_sync,
+  input pll_in,
+  input button_reset,
+  input pll_cpu_locked,
+  input clk_50,
+  input clk_2,
+  output logic [15:0] cpu_addr,
+  output logic [7:0] cpu_data_out,
+  output logic [7:0] cpu_data_oe,
+  output logic cpu_irqb,
+  output logic cpu_nmib,
+  output logic cpu_rdy,
+  output logic cpu_resb,
+  output logic cpu_rwb,
+  output logic pll_cpu_reset
+);
 
-module super6502(
-    input                   clk_50,
-    input                   pll_inst1_CLKOUT0,
-    input   logic           rst_n,
-    input   logic           button_1,
-
-    input   logic [15:0]    cpu_addr,
-    inout   logic [7:0]     cpu_data,
-
-    input   logic           cpu_vpb,
-    input   logic           cpu_mlb,
-    input   logic           cpu_rwb,
-    input   logic           cpu_sync,
-
-    output  logic           cpu_led,
-    output  logic           cpu_resb,
-    output  logic           cpu_rdy,
-    output  logic           cpu_sob,
-    output  logic           cpu_irqb,
-    output  logic           cpu_phi2,
-    output  logic           cpu_be,
-    output  logic           cpu_nmib,
-
-    output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5,
-
-    input   logic           UART_RXD,
-    output  logic           UART_TXD,
-
-    input                   [7:0] SW,
-    output  logic           [7:0] LED,
-
-    inout   logic [15: 2]   ARDUINO_IO,
-
-    ///////// SDRAM /////////
-    output             DRAM_CLK,
-    output             DRAM_CKE,
-    output   [12: 0]   DRAM_ADDR,
-    output   [ 1: 0]   DRAM_BA,
-    inout    [15: 0]   DRAM_DQ,
-    output             DRAM_LDQM,
-    output             DRAM_UDQM,
-    output             DRAM_CS_N,
-    output             DRAM_WE_N,
-    output             DRAM_CAS_N,
-    output             DRAM_RAS_N
-  );
-
-logic rst;
-assign rst = ~rst_n;
-
-logic clk;
-
-logic [7:0] cpu_data_in;
-assign cpu_data_in = cpu_data;
-
-logic [7:0] cpu_data_out;
-assign cpu_data = cpu_rwb ? cpu_data_out : 'z;
-
-logic o_sd_cmd, i_sd_cmd;
-logic o_sd_data, i_sd_data;
-
-assign ARDUINO_IO[11] = o_sd_cmd ? 1'bz : 1'b0;
-assign ARDUINO_IO[12] = o_sd_data ? 1'bz : 1'b0;
-assign ARDUINO_IO[13] = cpu_phi2;
-assign ARDUINO_IO[6] = 1'b1;
-
-assign i_sd_cmd = ARDUINO_IO[11];
-assign i_sd_data = ARDUINO_IO[12];
-
-logic [7:0] rom_data_out;
-logic [7:0] sdram_data_out;
-logic [7:0] uart_data_out;
-logic [7:0] irq_data_out;
-logic [7:0] board_io_data_out;
-logic [7:0] mm_data_out;
-logic [7:0] sd_data_out;
-
-logic sdram_cs;
-logic rom_cs;
-logic hex_cs;
-logic uart_cs;
-logic irq_cs;
-logic board_io_cs;
-logic mm_cs1;
-logic mm_cs2;
-logic sd_cs;
-
-assign clk = pll_inst1_CLKOUT0;
-
-always @(posedge clk) begin
-    cpu_phi2 <= ~cpu_phi2;
-end
+assign pll_cpu_reset = '1;
 
+assign cpu_data_oe = '0;
 assign cpu_rdy = '1;
-assign cpu_sob = '0;
-assign cpu_resb = rst_n;
-assign cpu_be = '1;
+assign cpu_irqb = '1;
 assign cpu_nmib = '1;
-assign cpu_irqb = irq_data_out == 0;
-
-logic [11:0] mm_MO;
-
-logic [23:0] mm_addr;
-assign mm_addr = {mm_MO, cpu_addr[11:0]};
-
-memory_mapper memory_mapper(
-    .clk(clk),
-    .rst(rst),
-    .rw(cpu_rwb),
-    .cs(mm_cs1),
-    .MM_cs(mm_cs2),
-    .RS(cpu_addr[3:0]),
-    .MA(cpu_addr[15:12]),
-    .data_in(cpu_data_in),
-    .data_out(mm_data_out),
-    .MO(mm_MO)
-);
-
-addr_decode decode(
-    .addr(mm_addr),
-    .sdram_cs(sdram_cs),
-    .rom_cs(rom_cs),
-    .hex_cs(hex_cs),
-    .uart_cs(uart_cs),
-    .irq_cs(irq_cs),
-    .board_io_cs(board_io_cs),
-    .mm_cs1(mm_cs1),
-    .mm_cs2(mm_cs2),
-    .sd_cs(sd_cs)
-);
-
-
-always_comb begin
-    if (sdram_cs)
-        cpu_data_out = sdram_data_out;
-    else if (rom_cs)
-        cpu_data_out = rom_data_out;
-    else if (uart_cs)
-        cpu_data_out = uart_data_out;
-    else if (irq_cs)
-        cpu_data_out = irq_data_out;
-    else if (board_io_cs)
-        cpu_data_out = board_io_data_out;
-    else if (mm_cs1)
-        cpu_data_out = mm_data_out;
-    else if (sd_cs)
-        cpu_data_out = sd_data_out;
-    else
-        cpu_data_out = 'x;
-end
-
-
-sdram_adapter u_sdram_adapter(
-    .rst(rst),
-    .clk_50(clk_50),
-    .cpu_clk(cpu_phi2),
-    .addr(mm_addr),
-    .sdram_cs(sdram_cs),
-    .rwb(cpu_rwb),
-    .data_in(cpu_data_in),
-    .data_out(sdram_data_out),
-
-    //SDRAM
-    .DRAM_CLK(DRAM_CLK),                           //clk_sdram.clk
-    .DRAM_ADDR(DRAM_ADDR),                         //sdram_wire.addr
-    .DRAM_BA(DRAM_BA),                             //.ba
-    .DRAM_CAS_N(DRAM_CAS_N),                       //.cas_n
-    .DRAM_CKE(DRAM_CKE),                           //.cke
-    .DRAM_CS_N(DRAM_CS_N),                         //.cs_n
-    .DRAM_DQ(DRAM_DQ),                             //.dq
-    .DRAM_UDQM(DRAM_UDQM),                         //.dqm
-    .DRAM_LDQM(DRAM_LDQM),
-    .DRAM_RAS_N(DRAM_RAS_N),                       //.ras_n
-    .DRAM_WE_N(DRAM_WE_N)                          //.we_n
-);
-
-
-rom boot_rom(
-    .address(cpu_addr[14:0]),
-    .clock(clk),
-    .q(rom_data_out)
-);
-
-SevenSeg segs(
-    .clk(clk),
-    .rst(rst),
-    .rw(cpu_rwb),
-    .data(cpu_data_in),
-    .cs(hex_cs),
-    .addr(cpu_addr[1:0]),
-    .HEX0(HEX0), .HEX1(HEX1), .HEX2(HEX2), .HEX3(HEX3), .HEX4(HEX4), .HEX5(HEX5)
-);
-
-board_io board_io(
-    .clk(clk),
-    .rst(rst),
-    .rw(cpu_rwb),
-    .data_in(cpu_data_in),
-    .data_out(board_io_data_out),
-    .cs(board_io_cs),
-    .led(LED),
-    .sw(SW)
-);
-
-logic uart_irq;
-
-uart uart(
-    .clk_50(clk_50),
-    .clk(clk),
-    .rst(rst),
-    .rw(cpu_rwb),
-    .data_in(cpu_data_in),
-    .cs(uart_cs),
-    .addr(cpu_addr[1:0]),
-    .RXD(UART_RXD),
-    .TXD(UART_TXD),
-    .irq(uart_irq),
-    .data_out(uart_data_out)
-);
-
-sd_controller sd_controller(
-    .clk(clk),
-    .sd_clk(cpu_phi2),
-    .rst(rst),
-    .addr(cpu_addr[2:0]),
-    .data(cpu_data_in),
-    .cs(sd_cs),
-    .rw(cpu_rwb),
-
-    .i_sd_cmd(i_sd_cmd),
-    .o_sd_cmd(o_sd_cmd),
-
-    .i_sd_data(i_sd_data),
-    .o_sd_data(o_sd_data),
-
-    .data_out(sd_data_out)
-);
-
-always_ff @(posedge clk_50) begin
-    if (rst)
-        irq_data_out <= '0;
-    else if (irq_cs && ~cpu_rwb)
-        irq_data_out <= irq_data_out & cpu_data_in;
 
+always @(posedge clk_2) begin
+    if (button_reset == '0) begin
+        cpu_resb <= '0;
+    end 
     else begin
-        if (~button_1)
-            irq_data_out[0] <= '1;
-        if (uart_irq)
-            irq_data_out[1] <= '1;
+        if (cpu_resb == '0) begin
+            cpu_resb <= '1;
+        end
     end
-
 end
 
 endmodule
-
diff --git a/hw/efinix_fpga/super6502.xml b/hw/efinix_fpga/super6502.xml
index d4bea2a..e70987a 100644
--- a/hw/efinix_fpga/super6502.xml
+++ b/hw/efinix_fpga/super6502.xml
@@ -1,35 +1,22 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<efx:project name="super6502" description="" last_change_date="Wed August 17 2022 12:17:48" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2021.2.323.4.6" last_run_state="fail" last_run_tool="efx_map" last_run_flow="syn" config_result_in_sync="true" design_ood="" place_ood="" route_ood="" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
+<efx:project name="super6502" description="" last_change_date="Tue November 1 2022 18:28:14" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2021.2.323.4.6" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
     <efx:device_info>
         <efx:family name="Trion"/>
         <efx:device name="T20F256"/>
-        <efx:timing_model name="C3"/>
+        <efx:timing_model name="C4"/>
     </efx:device_info>
     <efx:design_info def_veri_version="sv_09" def_vhdl_version="vhdl_2008">
-        <efx:top_module name="super6502"/>
+        <efx:top_module name=""/>
         <efx:design_file name="super6502.sv" version="default" library="default"/>
-        <efx:design_file name="crc7.sv" version="default" library="default"/>
-        <efx:design_file name="memory_mapper.sv" version="default" library="default"/>
-        <efx:design_file name="uart.sv" version="default" library="default"/>
-        <efx:design_file name="HexDriver.sv" version="default" library="default"/>
-        <efx:design_file name="addr_decode.sv" version="default" library="default"/>
-        <efx:design_file name="board_io.sv" version="default" library="default"/>
-        <efx:design_file name="SevenSeg.sv" version="default" library="default"/>
-        <efx:design_file name="sd_controller.sv" version="default" library="default"/>
-        <efx:design_file name="sdram_adapter.sv" version="default" library="default"/>
         <efx:top_vhdl_arch name=""/>
     </efx:design_info>
     <efx:constraint_info>
-        <efx:sdc_file name=""/>
+        <efx:sdc_file name="super6502.pt.sdc"/>
         <efx:inter_file name=""/>
     </efx:constraint_info>
     <efx:sim_info/>
     <efx:misc_info/>
-    <efx:ip_info>
-        <efx:ip instance_name="sdram" path="ip/sdram/settings.json">
-            <efx:ip_src_file name="sdram.v"/>
-        </efx:ip>
-    </efx:ip_info>
+    <efx:ip_info/>
     <efx:synthesis tool_name="efx_map">
         <efx:param name="work_dir" value="work_syn" value_type="e_string"/>
         <efx:param name="write_efx_verilog" value="on" value_type="e_bool"/>
@@ -47,7 +34,6 @@
         <efx:param name="optimize-adder-tree" value="0" value_type="e_option"/>
         <efx:param name="mult_input_regs_packing" value="1" value_type="e_option"/>
         <efx:param name="mult_output_regs_packing" value="1" value_type="e_option"/>
-        <efx:param name="include" value="ip/sdram" value_type="e_string"/>
     </efx:synthesis>
     <efx:place_and_route tool_name="efx_pnr">
         <efx:param name="work_dir" value="work_pnr" value_type="e_string"/>
@@ -77,7 +63,7 @@
     </efx:bitstream_generation>
     <efx:debugger>
         <efx:param name="work_dir" value="work_dbg" value_type="e_string"/>
-        <efx:param name="auto_instantiation" value="off" value_type="e_bool"/>
-        <efx:param name="profile" value="NONE" value_type="e_string"/>
+        <efx:param name="auto_instantiation" value="on" value_type="e_bool"/>
+        <efx:param name="profile" value="debug_profile.wizard.json" value_type="e_string"/>
     </efx:debugger>
 </efx:project>
diff --git a/hw/efinix_fpga/uart.sv b/hw/efinix_fpga/uart.sv
deleted file mode 100644
index e0a3922..0000000
--- a/hw/efinix_fpga/uart.sv
+++ /dev/null
@@ -1,228 +0,0 @@
-module uart(
-    input clk_50,
-    input clk,
-    input rst,
-    
-    input cs,
-    input rw,
-    input [7:0] data_in,
-    input [1:0] addr,
-    
-    input RXD,
-    
-    output logic TXD,
-    
-    output logic irq,
-    output logic [7:0] data_out
-);
-
-//Handle reading and writing registers
-
-logic [7:0] tx_buf;
-logic [7:0] rx_buf;
-logic [7:0] status;
-
-logic tx_flag;
-logic rx_flag;
-
-logic tx_flag_set;
-logic tx_flag_clear;
-logic rx_flag_set;
-logic rx_flag_clear;
-
-assign status[0] = tx_flag | tx_flag_clear;
-assign status[1] = rx_flag | rx_flag_set;
-
-assign irq = status[1];
-
-always_ff @(posedge clk) begin
-    if (rst) begin
-        tx_flag_set <= '0;
-        rx_flag_clear <= '0;
-        tx_buf <= '0;
-        status[7:2] <= '0;
-    end
-
-    if (cs) begin
-        if (~rw) begin
-            if (addr == 0)
-                tx_buf <= data_in;
-        end else begin
-            if (addr == 0)
-                data_out <= rx_buf;
-            if (addr == 1)
-                data_out <= status;
-        end
-    end
-
-    if (~rw & cs && addr == 0)
-        tx_flag_set <= '1;
-    else
-        tx_flag_set <= '0;
-
-    if (rw & cs && addr == 0)
-        rx_flag_clear <= '1;
-    else
-        rx_flag_clear <= '0;
-end
-
-// tx state controller
-typedef enum bit [2:0] {START, DATA, PARITY, STOP, IDLE} macro_t;
-struct packed {
-    macro_t macro;
-    logic [3:0] count;
-} tx_state, tx_next_state, rx_state, rx_next_state;
-localparam logic [3:0] maxcount = 4'h7;
-
-// baud rate: 9600
-localparam baud = 9600;
-localparam count = (50000000/baud)-1;
-logic [14:0] tx_clkdiv;
-
-always_ff @(posedge clk_50) begin
-    if (rst) begin
-        tx_clkdiv <= 0;
-        tx_state.macro <= IDLE;
-        tx_state.count <= 3'b0;
-        tx_flag <= '0;
-    end else begin
-        if (tx_flag_set)
-            tx_flag <= '1;
-        else if (tx_flag_clear)
-            tx_flag <= '0;
-
-        if (tx_clkdiv == count) begin
-            tx_clkdiv <= 0;
-            tx_state <= tx_next_state;
-        end else begin
-            tx_clkdiv <= tx_clkdiv + 15'b1;
-        end
-    end
-end
-
-always_comb begin
-    tx_next_state = tx_state;
-
-    unique case (tx_state.macro)
-        START: begin
-            tx_next_state.macro = DATA;
-            tx_next_state.count = 3'b0;
-        end
-        DATA: begin
-            if (tx_state.count == maxcount) begin
-                tx_next_state.macro = STOP;    // or PARITY
-                tx_next_state.count = 3'b0;
-            end else begin
-                tx_next_state.count = tx_state.count + 3'b1;
-                tx_next_state.macro = DATA;
-            end
-        end
-        PARITY: begin
-        end
-        STOP: begin
-            tx_next_state.macro = IDLE;
-            tx_next_state.count = '0;
-        end
-        IDLE: begin
-            if (tx_flag)
-                tx_next_state.macro = START;
-            else
-                tx_next_state.macro = IDLE;
-        end
-    
-        default:;
-    endcase
-end
-
-always_comb begin
-    TXD = '1;
-    tx_flag_clear = '0;
-
-    unique case (tx_state.macro)
-        START: begin
-            TXD = '0;
-        end
-        DATA: begin
-            TXD = tx_buf[tx_state.count];
-        end 
-        PARITY: begin
-
-        end
-        STOP: begin
-            tx_flag_clear = '1;
-            TXD = '1;
-        end
-        IDLE: begin
-            TXD = '1;
-        end
-
-        default:;
-    endcase
-end
-
-//basically in idle state we need to sample RXD very fast,
-//then as soon as we detect that RXD is low, we start clkdiv
-//going and then go into the start state.
-
-logic [14:0] rx_clkdiv;
-
-always_ff @(posedge clk_50) begin
-    if (rst) begin
-        rx_buf <= '0;
-        rx_clkdiv <= 0;
-        rx_state.macro <= IDLE;
-        rx_state.count <= 3'b0;
-    end else begin
-        if (rx_flag_set)
-            rx_flag <= '1;
-        else if (rx_flag_clear)
-            rx_flag <= '0;
-
-        if (rx_state.macro == IDLE) begin           // Sample constantly in idle state
-            rx_state <= rx_next_state;
-            rx_clkdiv <= count/15'h2;                   // offset rx clock by 1/2 phase
-        end else begin              
-            if (rx_clkdiv == count) begin           // other states are as usual
-                rx_clkdiv <= 0;
-                rx_state <= rx_next_state;
-                if (rx_state.macro == DATA)
-                    rx_buf[rx_state.count] = RXD;
-            end else begin
-                rx_clkdiv <= rx_clkdiv + 15'b1;
-            end
-        end
-    end
-end
-
-always_comb begin
-    rx_next_state = rx_state;
-    rx_flag_set = '0;
-
-    unique case (rx_state.macro)
-        IDLE: begin
-            if (~RXD)
-                rx_next_state.macro = START;
-        end
-        START: begin
-            rx_next_state.macro = DATA;
-            rx_next_state.count = 3'b0;
-        end
-        DATA: begin
-            if (rx_state.count == maxcount) begin
-                rx_next_state.macro = STOP;
-                rx_next_state.count = 3'b0;
-            end else begin
-                rx_next_state.count = rx_state.count + 3'b1;
-                rx_next_state.macro = DATA;
-            end
-        end
-        PARITY: begin
-        end
-        STOP: begin
-            rx_flag_set = '1;
-            rx_next_state.macro = IDLE;
-        end
-    endcase
-end
-
-endmodule
diff --git a/hw/efinix_fpga/work_pt/peri_load.bak b/hw/efinix_fpga/work_pt/peri_load.bak
deleted file mode 100644
index b65d11b..0000000
--- a/hw/efinix_fpga/work_pt/peri_load.bak
+++ /dev/null
@@ -1,31 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2021.2.323.4.6" db_version="20212999" last_change_date="Thu Jun  9 21:34:24 2022" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
-    <efxpt:device_info>
-        <efxpt:iobank_info>
-            <efxpt:iobank name="1A" iostd="3.3 V LVTTL / LVCMOS"/>
-            <efxpt:iobank name="1B_1C" iostd="3.3 V LVTTL / LVCMOS"/>
-            <efxpt:iobank name="1D_1E" iostd="3.3 V LVTTL / LVCMOS"/>
-            <efxpt:iobank name="3A_3B_3C" iostd="3.3 V LVTTL / LVCMOS"/>
-            <efxpt:iobank name="3D_3E" iostd="3.3 V LVTTL / LVCMOS"/>
-            <efxpt:iobank name="4A" iostd="3.3 V LVTTL / LVCMOS"/>
-            <efxpt:iobank name="4B" iostd="3.3 V LVTTL / LVCMOS"/>
-            <efxpt:iobank name="BR" iostd="1.2 V"/>
-            <efxpt:iobank name="TL" iostd="1.2 V"/>
-            <efxpt:iobank name="TR" iostd="1.2 V"/>
-        </efxpt:iobank_info>
-        <efxpt:ctrl_info>
-            <efxpt:ctrl name="cfg" ctrl_def="CONFIG_CTRL0" clock_name="" is_clk_invert="false" cbsel_bus_name="cfg_CBSEL" config_ctrl_name="cfg_CONFIG" ena_capture_name="cfg_ENA" error_status_name="cfg_ERROR" um_signal_status_name="cfg_USR_STATUS" is_remote_update_enable="false" is_user_mode_enable="false"/>
-        </efxpt:ctrl_info>
-    </efxpt:device_info>
-    <efxpt:gpio_info device_def="T20F256">
-        <efxpt:global_unused_config state="input with weak pullup"/>
-    </efxpt:gpio_info>
-    <efxpt:pll_info>
-        <efxpt:pll name="pll_inst1" pll_def="PLL_BR0" ref_clock_name="" ref_clock_freq="50.00" multiplier="32" pre_divider="1" post_divider="8" reset_name="" locked_name="" is_ipfrz="false" is_bypass_lock="true">
-            <efxpt:output_clock name="pll_inst1_CLKOUT0" number="0" out_divider="200" adv_out_phase_shift="0"/>
-            <efxpt:adv_prop ref_clock_mode="external" ref_clock1_name="" ext_ref_clock_id="3" clksel_name="" feedback_clock_name="" feedback_mode="internal"/>
-        </efxpt:pll>
-    </efxpt:pll_info>
-    <efxpt:lvds_info/>
-    <efxpt:jtag_info/>
-</efxpt:design_db>
diff --git a/hw/efinix_fpga/work_pt/peri_res.json b/hw/efinix_fpga/work_pt/peri_res.json
deleted file mode 100644
index da6bd0e..0000000
--- a/hw/efinix_fpga/work_pt/peri_res.json
+++ /dev/null
@@ -1,3 +0,0 @@
-{
-    "migration_launch_pt": "normal"
-}
\ No newline at end of file
diff --git a/hw/efinix_fpga/work_syn/run_efx_map.sh b/hw/efinix_fpga/work_syn/run_efx_map.sh
deleted file mode 100755
index ac2d51b..0000000
--- a/hw/efinix_fpga/work_syn/run_efx_map.sh
+++ /dev/null
@@ -1 +0,0 @@
-"/home/byron/Software/efinity/2021.2/bin/efx_map" --project "super6502" --root "super6502" --write-efx-verilog "/home/byron/Projects/super6502/hw/efinix_fpga/outflow/super6502.map.v" --write-premap-module "/home/byron/Projects/super6502/hw/efinix_fpga/outflow/super6502.elab.vdb" --binary-db "/home/byron/Projects/super6502/hw/efinix_fpga/super6502.vdb" --device "T20F256" --family "Trion" --mode "speed" --max_ram "-1" --max_mult "-1" --infer-clk-enable "3" --infer-sync-set-reset "1" --fanout-limit "0" --bram_output_regs_packing "1" --retiming "1" --seq_opt "1" --blast_const_operand_adders "1" --operator-sharing "0" --optimize-adder-tree "0" --mult_input_regs_packing "1" --mult_output_regs_packing "1" --veri_option "verilog_mode=sv_09,vhdl_mode=vhdl_2008" --work-dir "/home/byron/Projects/super6502/hw/efinix_fpga/work_syn" --output-dir "/home/byron/Projects/super6502/hw/efinix_fpga/outflow" --project-xml "/home/byron/Projects/super6502/hw/efinix_fpga/super6502.xml" --I "/home/byron/Projects/super6502/hw/efinix_fpga" --I "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram"
\ No newline at end of file
diff --git a/hw/efinix_shield/#auto_saved_files# b/hw/efinix_shield/#auto_saved_files#
new file mode 100644
index 0000000..905b1e5
--- /dev/null
+++ b/hw/efinix_shield/#auto_saved_files#
@@ -0,0 +1 @@
+/home/byron/Projects/super6502/hw/efinix_shield/_autosave-efinix_shield.kicad_sch
diff --git a/hw/efinix_shield/efinix_shield.kicad_sch b/hw/efinix_shield/efinix_shield.kicad_sch
index 63925eb..b543d09 100644
--- a/hw/efinix_shield/efinix_shield.kicad_sch
+++ b/hw/efinix_shield/efinix_shield.kicad_sch
@@ -211,130 +211,6 @@
         )
       )
     )
-    (symbol "Connector:Micro_SD_Card" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
-      (property "Reference" "J" (id 0) (at -16.51 15.24 0)
-        (effects (font (size 1.27 1.27)))
-      )
-      (property "Value" "Micro_SD_Card" (id 1) (at 16.51 15.24 0)
-        (effects (font (size 1.27 1.27)) (justify right))
-      )
-      (property "Footprint" "" (id 2) (at 29.21 7.62 0)
-        (effects (font (size 1.27 1.27)) hide)
-      )
-      (property "Datasheet" "http://katalog.we-online.de/em/datasheet/693072010801.pdf" (id 3) (at 0 0 0)
-        (effects (font (size 1.27 1.27)) hide)
-      )
-      (property "ki_keywords" "connector SD microsd" (id 4) (at 0 0 0)
-        (effects (font (size 1.27 1.27)) hide)
-      )
-      (property "ki_description" "Micro SD Card Socket" (id 5) (at 0 0 0)
-        (effects (font (size 1.27 1.27)) hide)
-      )
-      (property "ki_fp_filters" "microSD*" (id 6) (at 0 0 0)
-        (effects (font (size 1.27 1.27)) hide)
-      )
-      (symbol "Micro_SD_Card_0_1"
-        (rectangle (start -7.62 -9.525) (end -5.08 -10.795)
-          (stroke (width 0) (type default) (color 0 0 0 0))
-          (fill (type outline))
-        )
-        (rectangle (start -7.62 -6.985) (end -5.08 -8.255)
-          (stroke (width 0) (type default) (color 0 0 0 0))
-          (fill (type outline))
-        )
-        (rectangle (start -7.62 -4.445) (end -5.08 -5.715)
-          (stroke (width 0) (type default) (color 0 0 0 0))
-          (fill (type outline))
-        )
-        (rectangle (start -7.62 -1.905) (end -5.08 -3.175)
-          (stroke (width 0) (type default) (color 0 0 0 0))
-          (fill (type outline))
-        )
-        (rectangle (start -7.62 0.635) (end -5.08 -0.635)
-          (stroke (width 0) (type default) (color 0 0 0 0))
-          (fill (type outline))
-        )
-        (rectangle (start -7.62 3.175) (end -5.08 1.905)
-          (stroke (width 0) (type default) (color 0 0 0 0))
-          (fill (type outline))
-        )
-        (rectangle (start -7.62 5.715) (end -5.08 4.445)
-          (stroke (width 0) (type default) (color 0 0 0 0))
-          (fill (type outline))
-        )
-        (rectangle (start -7.62 8.255) (end -5.08 6.985)
-          (stroke (width 0) (type default) (color 0 0 0 0))
-          (fill (type outline))
-        )
-        (polyline
-          (pts
-            (xy 16.51 12.7)
-            (xy 16.51 13.97)
-            (xy -19.05 13.97)
-            (xy -19.05 -16.51)
-            (xy 16.51 -16.51)
-            (xy 16.51 -11.43)
-          )
-          (stroke (width 0.254) (type default) (color 0 0 0 0))
-          (fill (type none))
-        )
-        (polyline
-          (pts
-            (xy -8.89 -11.43)
-            (xy -8.89 8.89)
-            (xy -1.27 8.89)
-            (xy 2.54 12.7)
-            (xy 3.81 12.7)
-            (xy 3.81 11.43)
-            (xy 6.35 11.43)
-            (xy 7.62 12.7)
-            (xy 20.32 12.7)
-            (xy 20.32 -11.43)
-            (xy -8.89 -11.43)
-          )
-          (stroke (width 0.254) (type default) (color 0 0 0 0))
-          (fill (type background))
-        )
-      )
-      (symbol "Micro_SD_Card_1_1"
-        (pin bidirectional line (at -22.86 7.62 0) (length 3.81)
-          (name "DAT2" (effects (font (size 1.27 1.27))))
-          (number "1" (effects (font (size 1.27 1.27))))
-        )
-        (pin bidirectional line (at -22.86 5.08 0) (length 3.81)
-          (name "DAT3/CD" (effects (font (size 1.27 1.27))))
-          (number "2" (effects (font (size 1.27 1.27))))
-        )
-        (pin input line (at -22.86 2.54 0) (length 3.81)
-          (name "CMD" (effects (font (size 1.27 1.27))))
-          (number "3" (effects (font (size 1.27 1.27))))
-        )
-        (pin power_in line (at -22.86 0 0) (length 3.81)
-          (name "VDD" (effects (font (size 1.27 1.27))))
-          (number "4" (effects (font (size 1.27 1.27))))
-        )
-        (pin input line (at -22.86 -2.54 0) (length 3.81)
-          (name "CLK" (effects (font (size 1.27 1.27))))
-          (number "5" (effects (font (size 1.27 1.27))))
-        )
-        (pin power_in line (at -22.86 -5.08 0) (length 3.81)
-          (name "VSS" (effects (font (size 1.27 1.27))))
-          (number "6" (effects (font (size 1.27 1.27))))
-        )
-        (pin bidirectional line (at -22.86 -7.62 0) (length 3.81)
-          (name "DAT0" (effects (font (size 1.27 1.27))))
-          (number "7" (effects (font (size 1.27 1.27))))
-        )
-        (pin bidirectional line (at -22.86 -10.16 0) (length 3.81)
-          (name "DAT1" (effects (font (size 1.27 1.27))))
-          (number "8" (effects (font (size 1.27 1.27))))
-        )
-        (pin passive line (at 20.32 -15.24 180) (length 3.81)
-          (name "SHIELD" (effects (font (size 1.27 1.27))))
-          (number "9" (effects (font (size 1.27 1.27))))
-        )
-      )
-    )
     (symbol "Connector:SD_Card" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
       (property "Reference" "J" (id 0) (at -16.51 13.97 0)
         (effects (font (size 1.27 1.27)))
@@ -1407,36 +1283,24 @@
   (junction (at 41.275 122.555) (diameter 0) (color 0 0 0 0)
     (uuid 079c2b89-f21c-4c54-9833-db78eff9d236)
   )
-  (junction (at 93.98 109.855) (diameter 0) (color 0 0 0 0)
-    (uuid 189ebf88-6c92-4b4a-8cb1-05fa1d4dc389)
-  )
   (junction (at 212.09 151.765) (diameter 0) (color 0 0 0 0)
     (uuid 1e03c892-5996-4232-8760-3677b3a5cf3b)
   )
   (junction (at 127.635 51.435) (diameter 0) (color 0 0 0 0)
     (uuid 22515598-dc6b-47f8-b925-2e18c597dfb8)
   )
-  (junction (at 97.79 153.67) (diameter 0) (color 0 0 0 0)
-    (uuid 23b8e691-b24a-4b0c-a50a-2e54e51cdc1c)
-  )
-  (junction (at 103.505 125.095) (diameter 0) (color 0 0 0 0)
-    (uuid 34a57385-bf89-4616-9804-059e7c23e1b9)
-  )
   (junction (at 127.635 31.75) (diameter 0) (color 0 0 0 0)
     (uuid 36a23d3d-de9c-4c14-a013-52497e3a1bce)
   )
-  (junction (at 99.695 117.475) (diameter 0) (color 0 0 0 0)
-    (uuid 3e03c087-1b99-4b8b-818f-f00f7d326cb2)
-  )
-  (junction (at 95.885 112.395) (diameter 0) (color 0 0 0 0)
-    (uuid 47531917-622e-4913-9e93-ac0487100ced)
-  )
   (junction (at 69.215 53.975) (diameter 0) (color 0 0 0 0)
     (uuid 4c3e4baa-4402-4cad-bd03-f8ffdfd75fa2)
   )
   (junction (at 91.44 59.055) (diameter 0) (color 0 0 0 0)
     (uuid 5051b0d0-55d6-4776-af5d-2555a6e6a474)
   )
+  (junction (at 97.79 122.555) (diameter 0) (color 0 0 0 0)
+    (uuid 5eafca30-e2a4-43d4-8767-b2685c98cb72)
+  )
   (junction (at 91.44 70.485) (diameter 0) (color 0 0 0 0)
     (uuid 674c3857-e844-4a30-827e-7ad49fdaa008)
   )
@@ -1446,18 +1310,12 @@
   (junction (at 141.605 26.67) (diameter 0) (color 0 0 0 0)
     (uuid 88b06290-d27c-4960-90b4-582d358567b8)
   )
-  (junction (at 92.075 107.315) (diameter 0) (color 0 0 0 0)
-    (uuid 94c03e17-bbe3-4267-bd6b-323ed1cfb8ab)
-  )
   (junction (at 127.635 29.21) (diameter 0) (color 0 0 0 0)
     (uuid 984ad38a-d465-4cdb-b286-74838135b88a)
   )
   (junction (at 92.075 46.355) (diameter 0) (color 0 0 0 0)
     (uuid a27e9172-4518-4af6-a98c-ca010eb97b43)
   )
-  (junction (at 105.41 127.635) (diameter 0) (color 0 0 0 0)
-    (uuid b499f07e-2238-4225-9723-00b20de2df6a)
-  )
   (junction (at 92.075 26.67) (diameter 0) (color 0 0 0 0)
     (uuid b8bfbf39-d34d-4ea1-a7ec-2bdf630a7e61)
   )
@@ -1470,18 +1328,12 @@
   (junction (at 92.075 35.56) (diameter 0) (color 0 0 0 0)
     (uuid d5ffad96-ce10-43d6-b626-e6505a20666c)
   )
-  (junction (at 101.6 120.015) (diameter 0) (color 0 0 0 0)
-    (uuid daaaa5b3-e505-4b77-b00f-a11d98ca2569)
-  )
   (junction (at 69.215 48.895) (diameter 0) (color 0 0 0 0)
     (uuid ea77c522-14ed-40a1-bd82-bac6c09d9e14)
   )
   (junction (at 69.215 64.135) (diameter 0) (color 0 0 0 0)
     (uuid ee2ac0af-f262-4303-971b-8be27cfeba17)
   )
-  (junction (at 97.79 122.555) (diameter 0) (color 0 0 0 0)
-    (uuid f0a007ad-d7eb-48d2-bc47-8d6c3db1834e)
-  )
   (junction (at 91.44 61.595) (diameter 0) (color 0 0 0 0)
     (uuid f1a6b0f7-1cac-4cbf-a8ca-30ee448bffac)
   )
@@ -1524,10 +1376,6 @@
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 08273950-c760-4346-9d11-e1409a39dbc5)
   )
-  (wire (pts (xy 88.265 125.095) (xy 103.505 125.095))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid 09e81e97-1a13-4ec3-8cbc-a38bcec7f4b3)
-  )
   (wire (pts (xy 67.945 53.975) (xy 69.215 53.975))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 0b48931a-e247-4800-a176-ce58d2f072fa)
@@ -1552,10 +1400,6 @@
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 1a703f1b-4a68-4313-90e2-5b9e0f21712e)
   )
-  (wire (pts (xy 95.885 112.395) (xy 95.885 146.05))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid 1a7599a4-9eba-46a3-82c2-008833567f52)
-  )
   (wire (pts (xy 48.895 61.595) (xy 52.705 61.595))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 1db0a9d3-56cd-4441-81f1-89507023da30)
@@ -1564,14 +1408,6 @@
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 1e4ac7d6-50ee-4115-baae-d40a697c8d87)
   )
-  (wire (pts (xy 92.075 107.315) (xy 88.265 107.315))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid 26a69da8-a9fd-4ff9-aad1-b7e87a616a27)
-  )
-  (wire (pts (xy 103.505 125.095) (xy 103.505 156.21))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid 2917bdbe-b740-414c-9408-d86a931ab964)
-  )
   (wire (pts (xy 30.48 61.595) (xy 41.275 61.595))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 2c0420d0-ed86-40a7-8f60-15f37b663044)
@@ -1580,31 +1416,19 @@
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 2d395d5a-8118-4e37-9c8d-7de1c37a55e9)
   )
-  (wire (pts (xy 95.885 146.05) (xy 89.535 146.05))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid 2efac688-e086-4c7b-8eb0-f8f991147690)
-  )
   (wire (pts (xy 144.145 51.435) (xy 127.635 51.435))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 2fda2626-f62c-42de-98bc-6c4dc2d86213)
   )
-  (wire (pts (xy 99.695 117.475) (xy 99.695 148.59))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid 318e0e6f-5647-4b12-a7a2-ae7c34976c32)
-  )
   (wire (pts (xy 106.045 35.56) (xy 123.19 35.56))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 33d7f8fa-7630-47cf-a834-3a28ca71fdf4)
   )
-  (wire (pts (xy 99.695 148.59) (xy 89.535 148.59))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid 38ab1345-dfc2-4e5d-b56d-09ea1abbf127)
-  )
   (wire (pts (xy 67.945 51.435) (xy 127.635 51.435))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 3930f87b-49c5-4f14-b6d2-5a3339257d67)
   )
-  (wire (pts (xy 88.265 109.855) (xy 93.98 109.855))
+  (wire (pts (xy 88.265 109.855) (xy 125.73 109.855))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 3e0c38b3-468c-42df-b6bc-16baba65669c)
   )
@@ -1664,10 +1488,6 @@
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 546926fc-5dbc-4551-a2ae-43bdd8e6ba79)
   )
-  (wire (pts (xy 105.41 158.75) (xy 89.535 158.75))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid 54956b15-1adc-48b7-9c20-2cad1351995c)
-  )
   (wire (pts (xy 69.215 53.975) (xy 69.215 64.135))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 5aa03f53-a324-4df2-8387-09568def94e4)
@@ -1688,10 +1508,6 @@
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 669ddbbd-9ea9-41e4-940d-ede17d667c24)
   )
-  (wire (pts (xy 93.98 109.855) (xy 125.73 109.855))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid 671855cf-5d08-4d62-8ced-276dacf5076a)
-  )
   (wire (pts (xy 93.345 73.025) (xy 93.345 75.565))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 68db1b2a-94ec-4d09-b927-2fbdba55513b)
@@ -1700,14 +1516,10 @@
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 6b54885e-b3ff-486e-8b86-d606564b57c9)
   )
-  (wire (pts (xy 101.6 120.015) (xy 125.73 120.015))
+  (wire (pts (xy 88.265 120.015) (xy 125.73 120.015))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 6d54d31a-a490-4941-9ba3-b57eefbf935b)
   )
-  (wire (pts (xy 101.6 120.015) (xy 101.6 151.13))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid 6da41431-6db0-4bc7-8219-1eeceaedaae9)
-  )
   (wire (pts (xy 48.895 56.515) (xy 52.705 56.515))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 6df1330d-975f-460d-9f4a-cee05c4fcc48)
@@ -1728,10 +1540,6 @@
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 73f4cecb-233f-4608-82f5-7992140a9853)
   )
-  (wire (pts (xy 101.6 151.13) (xy 89.535 151.13))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid 76c211d2-9a1a-4a53-8d21-936e67a3d405)
-  )
   (wire (pts (xy 92.075 26.67) (xy 95.885 26.67))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 7ac238c0-16d6-45d6-8821-46b2aedb8938)
@@ -1756,10 +1564,6 @@
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 800c6e86-869c-4db6-b59c-f4c8cb4b1f3d)
   )
-  (wire (pts (xy 45.085 165.1) (xy 45.085 163.83))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid 808f3245-4871-4492-86ed-3704e905028c)
-  )
   (wire (pts (xy 95.25 73.025) (xy 93.345 73.025))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 8249468a-2289-4584-aa79-d32d2e8a9781)
@@ -1784,10 +1588,6 @@
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 8abbac3f-8207-47f0-b2ae-a35f866dc348)
   )
-  (wire (pts (xy 89.535 143.51) (xy 93.98 143.51))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid 8b4865ee-777f-4d44-b6cb-4ec1a5a42cb3)
-  )
   (wire (pts (xy 127.635 29.21) (xy 127.635 26.67))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 8c9da1e3-e36d-4ad2-9a6e-14ef00a499ee)
@@ -1816,10 +1616,6 @@
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 9725ce3b-c118-4415-a5f3-04867a541c6a)
   )
-  (wire (pts (xy 92.075 140.97) (xy 92.075 107.315))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid 9a41703a-41b5-4977-97c5-ec49b59ac4b4)
-  )
   (wire (pts (xy 105.41 73.025) (xy 122.555 73.025))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 9aeb2237-b192-401b-b72e-3f365f735484)
@@ -1828,29 +1624,17 @@
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 9b74c741-d20e-4a51-ada8-e23d00ccdcd0)
   )
-  (wire (pts (xy 89.535 140.97) (xy 92.075 140.97))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid 9e085cd5-50e1-448c-a1d7-a0bc9635b00a)
-  )
   (wire (pts (xy 60.325 74.295) (xy 60.325 76.2))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 9e29af0d-5676-43a8-9776-26c78b0e9337)
   )
-  (wire (pts (xy 97.79 122.555) (xy 97.79 153.67))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid 9eeb282b-40e4-45be-aae3-2395c1ebfc39)
-  )
   (wire (pts (xy 93.98 38.1) (xy 93.98 40.64))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid 9f35b7da-aca2-4234-9f23-9c80ea326afa)
   )
-  (wire (pts (xy 88.265 112.395) (xy 95.885 112.395))
+  (wire (pts (xy 97.79 122.555) (xy 97.79 133.35))
     (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid a3e890ab-e878-4aeb-a33c-cfeacae46ba0)
-  )
-  (wire (pts (xy 97.79 153.67) (xy 89.535 153.67))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid a76ee62e-cafe-4ca0-a1c2-0ce9b56e3b68)
+    (uuid a12cf9a6-2ed1-4796-9aa1-cba4163d41a1)
   )
   (wire (pts (xy 93.345 75.565) (xy 95.25 75.565))
     (stroke (width 0) (type default) (color 0 0 0 0))
@@ -1872,10 +1656,6 @@
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid ad98a920-1a5c-437d-83f0-164aa0ac89a0)
   )
-  (wire (pts (xy 88.265 127.635) (xy 105.41 127.635))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid aec2641d-5e8a-4b4f-b03e-f80351ff62b4)
-  )
   (wire (pts (xy 141.605 43.18) (xy 158.75 43.18))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid b1ce4493-1749-45b1-ad49-ee175fe290c8)
@@ -1884,15 +1664,11 @@
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid b50fcac6-0329-49d7-bae2-85c6248e1dfd)
   )
-  (wire (pts (xy 88.265 120.015) (xy 101.6 120.015))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid b6dabeea-afc2-4243-b088-5854fa23c121)
-  )
   (wire (pts (xy 106.045 26.67) (xy 123.19 26.67))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid b9f490a2-452a-4739-8cc7-2015ec09826c)
   )
-  (wire (pts (xy 92.075 107.315) (xy 125.73 107.315))
+  (wire (pts (xy 88.265 107.315) (xy 125.73 107.315))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid bb12b01c-3492-44c1-9b91-11254fa8a091)
   )
@@ -1920,14 +1696,6 @@
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid c6e0e520-7e6b-478a-8a59-96c5ec9ae784)
   )
-  (wire (pts (xy 105.41 127.635) (xy 105.41 158.75))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid c8ae0e9d-dd3e-451b-bef6-3496715c68bd)
-  )
-  (wire (pts (xy 97.79 153.67) (xy 97.79 160.655))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid c90e1468-8833-46ea-b54a-ba8076050a19)
-  )
   (wire (pts (xy 212.09 151.765) (xy 208.915 151.765))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid ccde4358-398b-4976-ac94-5e168addf502)
@@ -1952,11 +1720,7 @@
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid d4133f18-fe64-48d6-bae0-b72c976b59f3)
   )
-  (wire (pts (xy 45.085 163.83) (xy 46.355 163.83))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid d644a905-1db9-493a-9fa0-1dba78728e3e)
-  )
-  (wire (pts (xy 95.885 112.395) (xy 125.73 112.395))
+  (wire (pts (xy 88.265 112.395) (xy 125.73 112.395))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid dba9bda2-50f0-490c-8937-f0fd74c92d59)
   )
@@ -1968,15 +1732,11 @@
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid dfd27567-8814-4ff1-a1cf-73f360ecfde4)
   )
-  (wire (pts (xy 93.98 143.51) (xy 93.98 109.855))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid e13d5bda-d426-4880-a58c-d6cc2b22eb83)
-  )
   (wire (pts (xy 187.325 104.14) (xy 187.325 108.585))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid e3da055e-6541-40be-ba08-630738ea62f1)
   )
-  (wire (pts (xy 105.41 127.635) (xy 125.73 127.635))
+  (wire (pts (xy 88.265 127.635) (xy 125.73 127.635))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid e49ff074-572e-4895-9a3f-e89189544a89)
   )
@@ -2000,15 +1760,11 @@
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid ed4036cf-4846-4486-8514-df9f91f1e889)
   )
-  (wire (pts (xy 103.505 156.21) (xy 89.535 156.21))
-    (stroke (width 0) (type default) (color 0 0 0 0))
-    (uuid f60e6da7-8a1d-43b0-9327-ba9eed2d675e)
-  )
   (wire (pts (xy 131.445 43.18) (xy 129.54 43.18))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid f67fe448-b673-4550-8d27-b84a9a1f2d8b)
   )
-  (wire (pts (xy 103.505 125.095) (xy 125.73 125.095))
+  (wire (pts (xy 88.265 125.095) (xy 125.73 125.095))
     (stroke (width 0) (type default) (color 0 0 0 0))
     (uuid fa612f50-99f1-49d7-89e1-4476a1540727)
   )
@@ -2239,22 +1995,6 @@
     (pin "9" (uuid 585df365-6fdb-463c-90ce-8d22413405ee))
   )
 
-  (symbol (lib_id "power:GND") (at 45.085 165.1 0) (unit 1)
-    (in_bom yes) (on_board yes) (fields_autoplaced)
-    (uuid 1aef78cc-e482-481e-969e-f90dfdada4c6)
-    (property "Reference" "#PWR010" (id 0) (at 45.085 171.45 0)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (property "Value" "GND" (id 1) (at 45.085 169.545 0))
-    (property "Footprint" "" (id 2) (at 45.085 165.1 0)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (property "Datasheet" "" (id 3) (at 45.085 165.1 0)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (pin "1" (uuid 3cd09298-9e24-418f-ab50-1d197f571adc))
-  )
-
   (symbol (lib_id "power:GND") (at 60.325 76.2 0) (unit 1)
     (in_bom yes) (on_board yes) (fields_autoplaced)
     (uuid 1c2f8c4a-74e9-4a84-acc6-31d4acc7d4be)
@@ -2369,28 +2109,6 @@
     (pin "1" (uuid 3a86e1c4-f043-455d-bea3-3fc0f431afdb))
   )
 
-  (symbol (lib_id "Connector:Micro_SD_Card") (at 66.675 148.59 0) (mirror y) (unit 1)
-    (in_bom yes) (on_board yes) (fields_autoplaced)
-    (uuid 4d4fdeae-39f1-45cd-bcac-32ad09d03d85)
-    (property "Reference" "J4" (id 0) (at 66.04 128.905 0))
-    (property "Value" "Micro_SD_Card" (id 1) (at 66.04 131.445 0))
-    (property "Footprint" "" (id 2) (at 37.465 140.97 0)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (property "Datasheet" "http://katalog.we-online.de/em/datasheet/693072010801.pdf" (id 3) (at 66.675 148.59 0)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (pin "1" (uuid 905da886-f2c9-4c7f-9278-474a876f287b))
-    (pin "2" (uuid 907c5fd3-1680-4d3c-b556-37751f0fa26f))
-    (pin "3" (uuid 27c1ed4a-f33b-43be-845e-1cd817a25735))
-    (pin "4" (uuid 91c369d2-6142-42c7-ba2c-088d134abd52))
-    (pin "5" (uuid 5171ede7-f408-44ac-9fa1-77ce0d16f788))
-    (pin "6" (uuid 3d10c864-54d8-4232-86f8-2512eeb89e3b))
-    (pin "7" (uuid 6b4bd29d-1c5a-4f7a-9391-4429bfc9a1f9))
-    (pin "8" (uuid c74c1bd8-55e7-4c48-9310-e03f1800df70))
-    (pin "9" (uuid 579209ac-4137-4c53-84fc-d20b6ca7a9c6))
-  )
-
   (symbol (lib_id "Device:R_Pack04") (at 100.965 40.64 270) (unit 1)
     (in_bom yes) (on_board yes)
     (uuid 5b552e45-456d-4ee8-a0c6-334e4f0099fe)
@@ -2488,11 +2206,17 @@
     (in_bom yes) (on_board yes) (fields_autoplaced)
     (uuid 97e40c45-0497-47e2-9b07-32e14687d031)
     (property "Reference" "J1" (id 0) (at 60.325 33.655 0))
-    (property "Value" "DB15_Female_HighDensity_MountingHoles" (id 1) (at 60.325 36.195 0))
-    (property "Footprint" "Connector_Dsub:DSUB-15-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm" (id 2) (at 84.455 46.355 0)
+    (property "Value" "VGA" (id 1) (at 60.325 36.195 0))
+    (property "Footprint" "Connector_Dsub:ICD15S13E4GX00LF" (id 2) (at 84.455 46.355 0)
       (effects (font (size 1.27 1.27)) hide)
     )
-    (property "Datasheet" " ~" (id 3) (at 84.455 46.355 0)
+    (property "Datasheet" "https://cdn.amphenol-cs.com/media/wysiwyg/files/drawing/c-cd-0011.pdf" (id 3) (at 84.455 46.355 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Link" "https://www.digikey.com/en/products/detail/amphenol-cs-fci/ICD15S13E4GX00LF/1536501" (id 4) (at 60.325 56.515 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Part Name" "ICD15S13E4GX00LF" (id 5) (at 60.325 56.515 0)
       (effects (font (size 1.27 1.27)) hide)
     )
     (pin "0" (uuid 1dfedb6a-a203-46f4-aeb0-2dede99df55b))
@@ -2534,22 +2258,6 @@
     (pin "8" (uuid a5a41fc1-046b-474b-bbec-76368cb593ea))
   )
 
-  (symbol (lib_id "power:GND") (at 97.79 160.655 0) (unit 1)
-    (in_bom yes) (on_board yes) (fields_autoplaced)
-    (uuid a64f7ffb-f2dc-41d9-9682-c9dd7598c314)
-    (property "Reference" "#PWR09" (id 0) (at 97.79 167.005 0)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (property "Value" "GND" (id 1) (at 97.79 165.735 0))
-    (property "Footprint" "" (id 2) (at 97.79 160.655 0)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (property "Datasheet" "" (id 3) (at 97.79 160.655 0)
-      (effects (font (size 1.27 1.27)) hide)
-    )
-    (pin "1" (uuid 0ff3be93-a6ad-4da8-bbf7-0a5cd1f871c5))
-  )
-
   (symbol (lib_id "Device:R_Pack04") (at 136.525 45.72 270) (unit 1)
     (in_bom yes) (on_board yes)
     (uuid b72068bd-7a88-466e-a624-4d3225534c3d)
@@ -2603,6 +2311,22 @@
     (pin "1" (uuid d6a40aa4-70a3-4177-86fc-57092af70a4a))
   )
 
+  (symbol (lib_id "power:GND") (at 97.79 133.35 0) (unit 1)
+    (in_bom yes) (on_board yes) (fields_autoplaced)
+    (uuid ddf2789c-0d5f-4db2-9a10-7fae6f878787)
+    (property "Reference" "#PWR0101" (id 0) (at 97.79 139.7 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Value" "GND" (id 1) (at 97.79 138.43 0))
+    (property "Footprint" "" (id 2) (at 97.79 133.35 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (property "Datasheet" "" (id 3) (at 97.79 133.35 0)
+      (effects (font (size 1.27 1.27)) hide)
+    )
+    (pin "1" (uuid 437f2c76-c977-446e-9581-8cd8637691fe))
+  )
+
   (symbol (lib_id "power:GND") (at 41.275 123.825 0) (unit 1)
     (in_bom yes) (on_board yes) (fields_autoplaced)
     (uuid ddfea861-1c19-4655-b7a9-8f6d15ca16b7)
@@ -2664,14 +2388,11 @@
     (path "/ce17878b-9c9d-4250-9c53-bd2dca5488f9"
       (reference "#PWR08") (unit 1) (value "GND") (footprint "")
     )
-    (path "/a64f7ffb-f2dc-41d9-9682-c9dd7598c314"
-      (reference "#PWR09") (unit 1) (value "GND") (footprint "")
-    )
-    (path "/1aef78cc-e482-481e-969e-f90dfdada4c6"
-      (reference "#PWR010") (unit 1) (value "GND") (footprint "")
+    (path "/ddf2789c-0d5f-4db2-9a10-7fae6f878787"
+      (reference "#PWR0101") (unit 1) (value "GND") (footprint "")
     )
     (path "/97e40c45-0497-47e2-9b07-32e14687d031"
-      (reference "J1") (unit 1) (value "DB15_Female_HighDensity_MountingHoles") (footprint "Connector_Dsub:DSUB-15-HD_Male_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm")
+      (reference "J1") (unit 1) (value "VGA") (footprint "Connector_Dsub:ICD15S13E4GX00LF")
     )
     (path "/087238f6-faa3-48bd-b901-1fe7b8104345"
       (reference "J2") (unit 1) (value "SD_Card") (footprint "")
@@ -2679,9 +2400,6 @@
     (path "/027d4054-2c1b-407b-8023-47ec3d9f5eae"
       (reference "J3") (unit 1) (value "Conn_02x18_Odd_Even") (footprint "Connector_PinSocket_2.54mm:PinSocket_2x18_P2.54mm_Vertical")
     )
-    (path "/4d4fdeae-39f1-45cd-bcac-32ad09d03d85"
-      (reference "J4") (unit 1) (value "Micro_SD_Card") (footprint "")
-    )
     (path "/723cc3f8-c18f-493c-a2e9-9687f0beecc2"
       (reference "R1") (unit 1) (value "120") (footprint "Resistor_SMD:R_0603_1608Metric_Pad0.98x0.95mm_HandSolder")
     )