diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 453baae..2ded9e8 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -116,3 +116,32 @@ full sim:
dependencies:
- build toolchain
+mapper sim:
+ tags:
+ - linux
+ - iverilog
+ stage: simulate
+ artifacts:
+ paths:
+ - hw/efinix_fpga/simulation/mapper_tb.vcd
+ script:
+ - source init_env.sh
+ - cd hw/efinix_fpga/simulation
+ - make clean
+ - make mapper_tb
+ - ./mapper_tb
+
+mapper_code sim:
+ tags:
+ - linux
+ - iverilog
+ stage: simulate
+ artifacts:
+ paths:
+ - hw/efinix_fpga/simulation/mapper_code_tb.vcd
+ script:
+ - source init_env.sh
+ - cd hw/efinix_fpga/simulation
+ - make clean
+ - TEST_PROGRAM_NAME=mapper_test make mapper_code_tb
+ - ./mapper_code_tb
\ No newline at end of file
diff --git a/doc/memory_mapper.drawio b/doc/memory_mapper.drawio
new file mode 100644
index 0000000..296e767
--- /dev/null
+++ b/doc/memory_mapper.drawio
@@ -0,0 +1,293 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/doc/top.drawio b/doc/top.drawio
new file mode 100644
index 0000000..24e3027
--- /dev/null
+++ b/doc/top.drawio
@@ -0,0 +1,107 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/hw/efinix_fpga/init_hex.mem b/hw/efinix_fpga/init_hex.mem
index 65dd39a..2b05a54 100644
--- a/hw/efinix_fpga/init_hex.mem
+++ b/hw/efinix_fpga/init_hex.mem
@@ -1,9 +1,9 @@
@00000000
00 80 4C 00 00 8D 13 92 8E 14 92 8D 1A 92 8E 1B
92 88 B9 FF FF 8D 24 92 88 B9 FF FF 8D 23 92 8C
-26 92 20 FF FF A0 FF D0 E8 60 00 00 4B FD 00 00
-00 00 A2 FF 9A D8 A9 00 85 04 A9 DF 85 05 20 C3
-FD 20 38 FA 20 52 F0 58 20 69 F2 6C FC FF 20 2C
+26 92 20 FF FF A0 FF D0 E8 60 00 00 4C FD 00 00
+00 00 A2 FF 9A D8 A9 00 85 04 A9 DF 85 05 20 C4
+FD 20 39 FA 20 52 F0 58 20 69 F2 6C FC FF 20 2D
FA 00 A0 00 F0 07 A9 52 A2 F0 4C 05 92 60 AD FF
EF A2 00 60 8D FF EF 60 20 4F F2 C9 0A D0 05 A9
0D 20 4F F2 60 DA 5A A8 B2 04 AA A9 1B 20 4F F2
@@ -13,19 +13,19 @@ A9 63 20 4F F2 68 60 40 DA BA 48 E8 E8 BD 00 01
29 10 D0 06 68 FA 20 68 F2 40 68 FA 7C BF F0 C5
F0 C9 F0 CA F0 20 9A F0 40 40 20 68 F0 40 48 A0
04 B1 04 09 40 20 3F F2 88 B1 04 20 3F F2 88 10
-F8 68 09 01 20 3F F2 20 28 FB 60 A2 08 A9 FF 20
+F8 68 09 01 20 3F F2 20 29 FB 60 A2 08 A9 FF 20
3F F2 C9 FF D0 03 CA D0 F4 60 85 0C 86 0D 20 EB
-F0 92 0C A9 FF 20 3F F2 A0 01 91 0C 20 15 FB 60
-AA 20 9F FC A9 FF 20 3F F2 92 0C E6 0C D0 02 E6
+F0 92 0C A9 FF 20 3F F2 A0 01 91 0C 20 16 FB 60
+AA 20 A0 FC A9 FF 20 3F F2 92 0C E6 0C D0 02 E6
0D CA D0 F0 60 85 0C 86 0D 20 EB F0 C9 02 B0 12
-E6 0C D0 02 E6 0C A5 0C A6 0D 20 CC FC A9 04 20
+E6 0C D0 02 E6 0C A5 0C A6 0D 20 CD FC A9 04 20
10 F1 60 48 A9 FF 20 3F F2 A9 00 20 33 F2 A9 FF
20 3F F2 68 20 CE F0 20 EB F0 A8 A9 FF 20 3F F2
A9 00 20 39 F2 A9 FF 20 3F F2 98 A2 00 60 A9 00
20 39 F2 20 8B F1 A9 FF 20 3F F2 A9 00 20 39 F2
A2 50 A9 FF 20 3F F2 CA D0 F8 60 A2 01 A9 C8 3A
-D0 FD CA D0 F8 60 85 0E 86 0F A9 FF 92 0E 20 9F
-FC A5 04 85 10 A5 05 85 11 20 D0 FA A0 00 B1 10
+D0 FD CA D0 F8 60 85 0E 86 0F A9 FF 92 0E 20 A0
+FC A5 04 85 10 A5 05 85 11 20 D1 FA A0 00 B1 10
91 04 C8 B1 10 91 04 C8 B1 10 91 04 C8 B1 10 91
04 A9 FF 20 3F F2 A9 00 20 33 F2 A9 FF 20 3F F2
A9 11 A0 04 91 04 A9 00 20 CE F0 20 EB F0 C9 FF
@@ -37,91 +37,91 @@ EB A9 FF 20 3F F2 A9 FF 20 3F F2 A5 15 92 0E A5
F2 68 60 A9 01 8D DB EF 60 9C DB EF 60 A9 00 8D
DA EF AD DB EF 30 FB AD D9 EF 60 8D E6 EF 60 48
8D E6 EF AD E7 EF 89 02 D0 F9 68 60 AD E6 EF A2
-00 60 AD E7 EF A2 00 60 60 20 F3 FA A2 00 86 06
-86 07 A9 00 20 8A FB 20 D9 FA A9 05 A2 FE 20 99
-FA 20 3A F3 C9 00 20 37 FC D0 03 4C 98 F2 A9 FE
-A2 FD 20 99 FA 4C 2E F3 A9 F5 A2 FD 20 99 FA A0
-05 20 46 FB 20 8A FB AD 00 92 AE 01 92 20 CC FC
-A9 0C 20 57 FB 20 96 F1 A0 07 91 04 A0 07 A2 00
-B1 04 C9 00 20 3D FC D0 03 4C DC F2 A0 06 A2 00
-B1 04 C9 FE 20 3D FC F0 03 4C E5 F2 A2 00 A9 00
+00 60 AD E7 EF A2 00 60 60 20 F4 FA A2 00 86 06
+86 07 A9 00 20 8B FB 20 DA FA A9 06 A2 FE 20 9A
+FA 20 3A F3 C9 00 20 38 FC D0 03 4C 98 F2 A9 FF
+A2 FD 20 9A FA 4C 2E F3 A9 F6 A2 FD 20 9A FA A0
+05 20 47 FB 20 8B FB AD 00 92 AE 01 92 20 CD FC
+A9 0C 20 58 FB 20 96 F1 A0 07 91 04 A0 07 A2 00
+B1 04 C9 00 20 3E FC D0 03 4C DC F2 A0 06 A2 00
+B1 04 C9 FE 20 3E FC F0 03 4C E5 F2 A2 00 A9 00
D0 03 4C E9 F2 A2 00 A9 01 D0 03 4C FA F2 AD 00
92 AE 01 92 20 BB F5 4C 2B F3 A0 06 A2 00 B1 04
-A2 00 29 F0 20 1E FA D0 03 4C 16 F3 A9 FE A2 FD
-20 99 FA 4C 2B F3 A9 E6 A2 FD 20 CC FC A0 08 A2
-00 B1 04 20 CC FC A0 04 20 65 FA 6C 00 92 4C 31
-F3 4C 31 F3 A0 0C 20 04 FA 60 20 00 FB A9 00 20
-B6 FC 20 6E F1 4C 71 F3 A0 00 A2 00 18 A9 01 71
-04 91 04 A0 00 A2 00 B1 04 C9 FF 20 3D FC D0 03
-4C 71 F3 A9 24 A2 FE 20 99 FA A2 00 A9 01 4C 27
-F4 20 2B F4 A0 01 91 04 C9 01 20 37 FC D0 C9 A9
-01 20 57 FB 20 48 F4 A0 01 A2 00 B1 04 C9 01 20
-37 FC D0 03 4C A5 F3 A9 1B A2 FE 20 99 FA A2 00
-A9 01 4C 27 F4 A0 05 A2 00 B1 04 C9 AA 20 37 FC
+A2 00 29 F0 20 1F FA D0 03 4C 16 F3 A9 FF A2 FD
+20 9A FA 4C 2B F3 A9 E7 A2 FD 20 CD FC A0 08 A2
+00 B1 04 20 CD FC A0 04 20 66 FA 6C 00 92 4C 31
+F3 4C 31 F3 A0 0C 20 05 FA 60 20 01 FB A9 00 20
+B7 FC 20 6E F1 4C 71 F3 A0 00 A2 00 18 A9 01 71
+04 91 04 A0 00 A2 00 B1 04 C9 FF 20 3E FC D0 03
+4C 71 F3 A9 25 A2 FE 20 9A FA A2 00 A9 01 4C 27
+F4 20 2B F4 A0 01 91 04 C9 01 20 38 FC D0 C9 A9
+01 20 58 FB 20 48 F4 A0 01 A2 00 B1 04 C9 01 20
+38 FC D0 03 4C A5 F3 A9 1C A2 FE 20 9A FA A2 00
+A9 01 4C 27 F4 A0 05 A2 00 B1 04 C9 AA 20 38 FC
D0 03 4C BC F3 A2 00 A9 01 4C 27 F4 A2 00 A9 00
-A0 00 91 04 A0 00 A2 00 B1 04 C9 FF 20 3D FC D0
-03 4C E2 F3 A9 0C A2 FE 20 99 FA A2 00 A9 01 4C
+A0 00 91 04 A0 00 A2 00 B1 04 C9 FF 20 3E FC D0
+03 4C E2 F3 A9 0D A2 FE 20 9A FA A2 00 A9 01 4C
27 F4 20 6A F5 A0 01 91 04 A0 01 A2 00 B1 04 C9
-02 20 56 FC D0 03 4C 00 F4 20 87 F5 A0 01 91 04
+02 20 57 FC D0 03 4C 00 F4 20 87 F5 A0 01 91 04
A0 00 A2 00 18 A9 01 71 04 91 04 A0 01 A2 00 B1
-04 C9 00 20 37 FC D0 AC A9 01 20 57 FB 20 F0 F4
-A2 00 A9 00 4C 27 F4 20 2D FB 60 A2 00 A9 00 20
-B6 FC A2 00 86 06 86 07 A9 00 20 8A FB A2 00 A9
-94 20 43 F1 4C 47 F4 60 20 CC FC A2 00 A9 FF 20
+04 C9 00 20 38 FC D0 AC A9 01 20 58 FB 20 F0 F4
+A2 00 A9 00 4C 27 F4 20 2E FB 60 A2 00 A9 00 20
+B7 FC A2 00 86 06 86 07 A9 00 20 8B FB A2 00 A9
+94 20 43 F1 4C 47 F4 60 20 CD FC A2 00 A9 FF 20
3F F2 A2 00 A9 00 20 33 F2 A2 00 A9 FF 20 3F F2
-A2 00 A9 08 20 B6 FC A2 01 A9 00 85 06 A9 00 85
-07 A9 AA 20 8A FB A2 00 A9 86 20 CE F0 A0 01 20
-3D FB 20 25 F1 A2 00 A9 FF 20 3F F2 A2 00 A9 00
-20 39 F2 A2 00 A9 FF 20 3F F2 20 15 FB 60 20 CC
+A2 00 A9 08 20 B7 FC A2 01 A9 00 85 06 A9 00 85
+07 A9 AA 20 8B FB A2 00 A9 86 20 CE F0 A0 01 20
+3E FB 20 25 F1 A2 00 A9 FF 20 3F F2 A2 00 A9 00
+20 39 F2 A2 00 A9 FF 20 3F F2 20 16 FB 60 20 CD
FC A2 00 A9 FF 20 3F F2 A2 00 A9 00 20 33 F2 A2
-00 A9 FF 20 3F F2 A2 00 A9 0D 20 B6 FC A2 00 86
-06 86 07 A9 00 20 8A FB A2 00 A9 00 20 CE F0 A0
-01 20 3D FB 20 FA F0 A2 00 A9 FF 20 3F F2 A2 00
-A9 00 20 39 F2 A2 00 A9 FF 20 3F F2 20 15 FB 60
-20 CC FC 20 D0 FA A2 00 A9 FF 20 3F F2 A2 00 A9
+00 A9 FF 20 3F F2 A2 00 A9 0D 20 B7 FC A2 00 86
+06 86 07 A9 00 20 8B FB A2 00 A9 00 20 CE F0 A0
+01 20 3E FB 20 FA F0 A2 00 A9 FF 20 3F F2 A2 00
+A9 00 20 39 F2 A2 00 A9 FF 20 3F F2 20 16 FB 60
+20 CD FC 20 D1 FA A2 00 A9 FF 20 3F F2 A2 00 A9
00 20 33 F2 A2 00 A9 FF 20 3F F2 A0 00 91 04 A0
-00 A2 00 B1 04 C9 FF 20 37 FC D0 03 4C 30 F5 4C
-22 F5 A2 00 A9 FF 20 3F F2 C9 FF 20 37 FC D0 F2
-A2 00 A9 3A 20 B6 FC A2 00 86 06 86 07 A9 00 20
-8A FB A2 00 A9 00 20 CE F0 A0 02 20 3D FB 20 25
+00 A2 00 B1 04 C9 FF 20 38 FC D0 03 4C 30 F5 4C
+22 F5 A2 00 A9 FF 20 3F F2 C9 FF 20 38 FC D0 F2
+A2 00 A9 3A 20 B7 FC A2 00 86 06 86 07 A9 00 20
+8B FB A2 00 A9 00 20 CE F0 A0 02 20 3E FB 20 25
F1 A2 00 A9 FF 20 3F F2 A2 00 A9 00 20 39 F2 A2
-00 A9 FF 20 3F F2 20 23 FB 60 A2 00 A9 37 20 B6
-FC A2 00 86 06 86 07 A9 00 20 8A FB A2 00 A9 00
-20 43 F1 4C 86 F5 60 A2 00 A9 29 20 B6 FC A2 00
-86 06 A9 40 85 07 A9 00 20 8A FB A2 00 A9 00 20
-43 F1 4C A5 F5 60 20 CC FC 20 F3 FA A0 03 A2 00
-B1 04 4C B5 F5 A0 0E 20 04 FA 60 20 CC FC A9 00
-20 B6 FC 20 D9 FA A2 00 A9 00 A0 00 20 E4 FC A0
-01 20 3D FB E0 02 20 56 FC F0 03 4C E1 F5 4C 43
-F6 A9 2D A2 FE 20 CC FC A0 06 20 3D FB A0 00 20
-32 FB 20 CC FC A0 07 A2 00 A9 01 20 F4 F9 A0 04
-20 65 FA A0 02 A2 00 B1 04 C9 1F 20 3D FC D0 03
-4C 25 F6 A9 31 A2 FE 20 99 FA A2 00 A9 00 A0 02
+00 A9 FF 20 3F F2 20 24 FB 60 A2 00 A9 37 20 B7
+FC A2 00 86 06 86 07 A9 00 20 8B FB A2 00 A9 00
+20 43 F1 4C 86 F5 60 A2 00 A9 29 20 B7 FC A2 00
+86 06 A9 40 85 07 A9 00 20 8B FB A2 00 A9 00 20
+43 F1 4C A5 F5 60 20 CD FC 20 F4 FA A0 03 A2 00
+B1 04 4C B5 F5 A0 0E 20 05 FA 60 20 CD FC A9 00
+20 B7 FC 20 DA FA A2 00 A9 00 A0 00 20 E5 FC A0
+01 20 3E FB E0 02 20 57 FC F0 03 4C E1 F5 4C 43
+F6 A9 2E A2 FE 20 CD FC A0 06 20 3E FB A0 00 20
+33 FB 20 CD FC A0 07 A2 00 A9 01 20 F5 F9 A0 04
+20 66 FA A0 02 A2 00 B1 04 C9 1F 20 3E FC D0 03
+4C 25 F6 A9 32 A2 FE 20 9A FA A2 00 A9 00 A0 02
91 04 4C 37 F6 A2 00 A9 20 20 68 F0 A0 02 A2 00
-18 A9 01 71 04 91 04 A0 00 A2 00 A9 01 20 F4 F9
-4C CF F5 A9 31 A2 FE 20 99 FA 20 28 FB 60 A0 00
+18 A9 01 71 04 91 04 A0 00 A2 00 A9 01 20 F5 F9
+4C CF F5 A9 32 A2 FE 20 9A FA 20 29 FB 60 A0 00
B1 1A E6 1A D0 02 E6 1B 60 AD 4A 92 8D 45 92 20
-FA F6 A9 45 A2 92 20 CC FC 20 AD FC 4C 02 92 A5
+FA F6 A9 45 A2 92 20 CD FC 20 AE FC 4C 02 92 A5
18 38 E9 02 85 18 B0 02 C6 19 60 AD 4F 92 D0 11
-20 98 F6 4C 17 FA AD 4F 92 D0 06 20 98 F6 4C 11
+20 98 F6 4C 18 FA AD 4F 92 D0 06 20 98 F6 4C 12
FA 20 98 F6 85 06 86 07 20 6F F6 A0 01 B1 18 AA
88 B1 18 60 A0 00 84 0C 84 0D B1 1A 38 E9 30 90
2C C9 0A B0 28 20 52 F6 48 A5 0C A6 0D 06 0C 26
0D 06 0C 26 0D 65 0C 85 0C 8A 65 0D 85 0D 06 0C
26 0D 68 65 0C 85 0C 90 D1 E6 0D B0 CD A5 0C A6
0D 60 AC 51 92 EE 51 92 99 52 92 60 A9 52 A2 92
-18 6D 51 92 90 01 E8 4C CC FC A5 1C A6 1D 4C CC
+18 6D 51 92 90 01 E8 4C CD FC A5 1C A6 1D 4C CD
FC 20 59 F6 EE 4B 92 D0 F8 EE 4C 92 D0 F3 60 20
-FA F6 AD 66 92 AE 67 92 20 CC FC AD 68 92 AE 69
-92 20 CC FC 4C 02 92 84 0C 20 8A FB 20 EC F6 A5
-0C 4C BA FB 84 0C 20 8A FB 20 EC F6 A5 0C 4C FB
+FA F6 AD 66 92 AE 67 92 20 CD FC AD 68 92 AE 69
+92 20 CD FC 4C 02 92 84 0C 20 8B FB 20 EC F6 A5
+0C 4C BB FB 84 0C 20 8B FB 20 EC F6 A5 0C 4C FC
FB 48 A0 05 B9 18 00 99 3F 92 88 10 F7 68 85 18
-86 19 20 0D FB 85 1A 86 1B 20 0D FB 85 1C 86 1D
+86 19 20 0E FB 85 1A 86 1B 20 0E FB 85 1C 86 1D
A9 00 A8 91 1C C8 91 1C C8 B1 1C 8D 03 92 C8 B1
1C 8D 04 92 A5 1A 85 0C A5 1B 85 0D A0 00 B1 1A
F0 0B C9 25 F0 07 C8 D0 F5 E6 1B D0 F1 98 18 65
1A 85 1A 90 02 E6 1B 38 E5 0C 85 0E A5 1B E5 0D
-85 0F 05 0E F0 25 20 F3 FA A0 05 A5 1D 91 04 88
+85 0F 05 0E F0 25 20 F4 FA A0 05 A5 1D 91 04 88
A5 1C 91 04 88 A5 0D 91 04 88 A5 0C 91 04 88 A5
0F 91 04 88 A5 0E 91 04 20 02 92 20 4E F6 AA D0
0B A2 05 BD 3F 92 95 18 CA 10 F8 60 C9 25 D0 09
@@ -137,102 +137,102 @@ C9 2E D0 1B 20 52 F6 B1 1A C9 2A D0 09 20 52 F6
1A C9 7A F0 19 C9 68 F0 15 C9 74 F0 11 C9 6A F0
08 C9 4C F0 04 C9 6C D0 0B A9 FF 8D 4F 92 20 52
F6 4C 6F F8 8C 51 92 A2 52 8E 66 92 A2 92 8E 67
-92 20 52 F6 C9 63 D0 0D 20 98 F6 8D 52 92 A2 00
-A9 01 4C 9B F9 C9 64 F0 04 C9 69 D0 2D A2 00 AD
-48 92 F0 02 A2 20 AD 47 92 F0 02 A2 2B 8E 50 92
-20 86 F6 A4 07 30 0B AC 50 92 F0 06 8C 52 92 EE
-51 92 A0 0A 20 27 F7 4C 92 F9 C9 6E D0 15 20 98
-F6 85 0C 86 0D A0 00 B1 1C 91 0C C8 B1 1C 91 0C
-4C 74 F7 C9 6F D0 27 20 86 F6 AC 49 92 F0 17 48
-86 14 05 14 05 06 05 07 0D 4D 92 0D 4E 92 F0 06
-A9 30 20 E2 F6 68 A0 08 20 27 F7 4C 92 F9 C9 70
-D0 0D A2 00 8E 4F 92 E8 8E 49 92 A9 78 D0 27 C9
-73 D0 0C 20 98 F6 8D 66 92 8E 67 92 4C 92 F9 C9
-75 D0 0B 20 7B F6 A0 0A 20 34 F7 4C 92 F9 C9 78
-F0 04 C9 58 D0 29 48 AD 49 92 F0 0A A9 30 20 E2
-F6 A9 58 20 E2 F6 20 7B F6 A0 10 20 34 F7 68 C9
-78 D0 09 AD 66 92 AE 67 92 20 24 FD 4C 92 F9 4C
-74 F7 AD 66 92 AE 67 92 20 0E FD 8D 68 92 8E 69
-92 AD 4D 92 0D 4E 92 F0 15 AE 4D 92 EC 68 92 AD
-4E 92 A8 ED 69 92 B0 06 8E 68 92 8C 69 92 38 AD
-4B 92 ED 68 92 AA AD 4C 92 ED 69 92 B0 03 A9 00
-AA 49 FF 8D 4C 92 8A 49 FF 8D 4B 92 AD 46 92 D0
-03 20 04 F7 20 0F F7 AD 46 92 F0 03 20 04 F7 4C
-74 F7 A0 00 18 71 04 91 04 48 C8 8A 71 04 91 04
-AA 68 60 C8 48 18 98 65 04 85 04 90 02 E6 05 68
-60 A0 FF E0 80 B0 02 A0 00 84 06 84 07 60 E0 00
-D0 06 AA D0 03 A9 01 60 A2 00 8A 60 A0 00 F0 07
-A9 52 A2 F0 4C 05 92 60 A9 00 85 0C A9 F0 85 0D
-A9 00 85 0E A9 92 85 0F A2 CD A9 FF 85 14 A0 00
-E8 F0 0D B1 0C 91 0E C8 D0 F6 E6 0D E6 0F D0 F0
-E6 14 D0 EF 60 8C 6A 92 88 88 98 18 65 04 85 0C
-A6 05 90 01 E8 86 0D A0 01 B1 0C AA 88 B1 0C 20
-CC FC A5 0C A6 0D 20 93 FD AC 6A 92 4C 04 FA 85
-0C 86 0D 20 75 F0 4C 9D FA 85 0C 86 0D A0 00 B1
-0C F0 0E C8 84 14 20 68 F0 A4 14 D0 F2 E6 0D D0
-EE 60 E0 00 D0 15 4A AA BD 5A FE 90 05 4A 4A 4A
-4A 18 29 0F AA BD 4F FE A2 00 60 38 A9 00 AA 60
-A4 04 D0 02 C6 05 C6 04 60 A5 04 38 E9 02 85 04
-90 01 60 C6 05 60 A5 04 38 E9 04 85 04 90 01 60
-C6 05 60 A5 04 38 E9 06 85 04 90 01 60 C6 05 60
-A5 04 38 E9 07 85 04 90 01 60 C6 05 60 A0 01 B1
-04 AA 88 B1 04 E6 04 F0 05 E6 04 F0 03 60 E6 04
-E6 05 60 A0 03 4C 04 FA A0 05 4C 04 FA A0 08 4C
-04 FA 85 0C 86 0D A2 00 B1 0C 60 A0 01 B1 04 AA
-88 B1 04 60 A0 03 B1 04 85 07 88 B1 04 85 06 88
-B1 04 AA 88 B1 04 60 A2 00 18 65 04 48 8A 65 05
-AA 68 60 18 49 FF 69 01 48 8A 49 FF 69 00 AA A5
-06 49 FF 69 00 85 06 A5 07 49 FF 69 00 85 07 68
-60 A9 00 AA A0 00 84 06 84 07 48 20 E6 FA A0 03
-A5 07 91 04 88 A5 06 91 04 88 8A 91 04 68 88 91
-04 60 85 14 20 0D FB 85 0E 86 0F 85 10 86 11 20
-9F FC 20 0D FB 85 06 86 07 60 20 A2 FB A6 07 A4
-14 C0 0A D0 39 A5 06 05 0D 05 0C D0 11 E0 80 D0
-0D A0 0B B9 43 FE 91 0E 88 10 F8 4C 32 FC 8A 10
-1D A9 2D A0 00 91 0E E6 0E D0 02 E6 0F A5 0C A6
-0D 20 63 FB 85 0C 86 0D 4C FE FB 20 A2 FB A9 00
-48 A0 20 A9 00 06 0C 26 0D 26 06 26 07 2A C5 14
-90 04 E5 14 E6 0C 88 D0 EC A8 B9 33 FE 48 A5 0C
-05 0D 05 06 05 07 D0 D9 A0 00 68 91 0E F0 03 C8
-D0 F8 A5 10 A6 11 60 D0 06 A2 00 8A 60 D0 FA A2
-00 A9 01 60 F0 F9 30 F7 A2 00 8A 60 F0 02 10 EF
-A2 00 8A 60 F0 E9 90 E7 A2 00 8A 60 F0 DB A2 00
-8A 2A 60 20 8C FC A6 11 F0 13 B1 0C 91 0E C8 B1
-0C 91 0E C8 D0 F4 E6 0D E6 0F CA D0 ED A6 10 F0
-08 B1 0C 91 0E C8 CA D0 F8 4C 0D FB 85 10 86 11
-20 9F FC C8 B1 04 AA 86 0F 88 B1 04 85 0E 60 A0
-01 B1 04 85 0D 88 B1 04 85 0C 4C 15 FB A9 01 4C
-CA FC A0 00 B1 04 A4 04 F0 07 C6 04 A0 00 91 04
-60 C6 05 C6 04 91 04 60 A9 00 A2 00 48 A5 04 38
-E9 02 85 04 B0 02 C6 05 A0 01 8A 91 04 68 88 91
-04 60 A0 00 91 04 C8 48 8A 91 04 68 60 85 0E 86
-0F 20 9F FC B1 0C D1 0E D0 0C AA F0 10 C8 D0 F4
-E6 0D E6 0F D0 EE B0 03 A2 FF 60 A2 01 60 85 0E
-86 0F A2 00 A0 00 B1 0E F0 08 C8 D0 F9 E6 0F E8
-D0 F4 98 60 85 0C 86 0D 85 0E 86 0F A0 00 B1 0C
-F0 14 20 B6 FA 29 02 F0 06 B1 0C 69 20 91 0C C8
-D0 EC E6 0D D0 E8 A5 0E A6 0F 60 20 0D FB 85 0E
-86 0F E8 8E 31 92 AA E8 8E 30 92 20 9F FC 20 0D
-FB 85 10 86 11 A0 00 84 14 B1 10 18 65 0E 91 10
-C8 B1 10 65 0F 91 10 CE 30 92 F0 11 A4 14 B1 0C
-C8 D0 02 E6 0D 84 14 20 68 F0 4C 77 FD CE 31 92
-D0 EA 60 85 0C 86 0D A9 00 8D 2A 92 8D 2B 92 A0
-01 B1 04 AA 88 B1 04 20 CC FC A0 02 A9 2A 91 04
-C8 A9 92 91 04 A5 0C A6 0D 20 41 F7 AD 2A 92 AE
-2B 92 60 A9 32 85 0C A9 92 85 0D A9 00 A8 A2 00
-F0 0A 91 0C C8 D0 FB E6 0D CA D0 F6 C0 39 F0 05
-91 0C C8 D0 F7 60 62 61 64 20 74 6F 6B 65 6E 3A
-20 25 78 0A 00 53 75 63 63 65 73 73 0A 00 45 72
-72 6F 72 0A 00 53 74 61 72 74 0A 00 6F 70 5F 63
-6F 6E 64 20 65 72 72 6F 72 0A 00 49 46 20 43 6F
-6E 64 0A 00 47 6F 20 49 44 4C 45 0A 00 25 32 78
-00 0A 00 30 31 32 33 34 35 36 37 38 39 41 42 43
-44 45 46 2D 32 31 34 37 34 38 33 36 34 38 00 00
-01 02 0C 09 0A 10 40 50 A0 D0 66 66 66 66 A6 88
-88 66 66 66 66 66 66 66 66 66 09 00 00 00 00 00
-00 00 33 33 33 33 33 00 00 00 50 55 55 25 22 22
-22 22 22 22 22 22 22 02 00 00 40 44 44 14 11 11
-11 11 11 11 11 11 11 01 00 70 00 00 00 00 00 00
+92 20 52 F6 C9 63 D0 0E 20 98 F6 8D 52 92 A9 00
+8D 53 92 4C 93 F9 C9 64 F0 04 C9 69 D0 2D A2 00
+AD 48 92 F0 02 A2 20 AD 47 92 F0 02 A2 2B 8E 50
+92 20 86 F6 A4 07 30 0B AC 50 92 F0 06 8C 52 92
+EE 51 92 A0 0A 20 27 F7 4C 93 F9 C9 6E D0 15 20
+98 F6 85 0C 86 0D A0 00 B1 1C 91 0C C8 B1 1C 91
+0C 4C 74 F7 C9 6F D0 27 20 86 F6 AC 49 92 F0 17
+48 86 14 05 14 05 06 05 07 0D 4D 92 0D 4E 92 F0
+06 A9 30 20 E2 F6 68 A0 08 20 27 F7 4C 93 F9 C9
+70 D0 0D A2 00 8E 4F 92 E8 8E 49 92 A9 78 D0 27
+C9 73 D0 0C 20 98 F6 8D 66 92 8E 67 92 4C 93 F9
+C9 75 D0 0B 20 7B F6 A0 0A 20 34 F7 4C 93 F9 C9
+78 F0 04 C9 58 D0 29 48 AD 49 92 F0 0A A9 30 20
+E2 F6 A9 58 20 E2 F6 20 7B F6 A0 10 20 34 F7 68
+C9 78 D0 09 AD 66 92 AE 67 92 20 25 FD 4C 93 F9
+4C 74 F7 AD 66 92 AE 67 92 20 0F FD 8D 68 92 8E
+69 92 AD 4D 92 0D 4E 92 F0 15 AE 4D 92 EC 68 92
+AD 4E 92 A8 ED 69 92 B0 06 8E 68 92 8C 69 92 38
+AD 4B 92 ED 68 92 AA AD 4C 92 ED 69 92 B0 03 A9
+00 AA 49 FF 8D 4C 92 8A 49 FF 8D 4B 92 AD 46 92
+D0 03 20 04 F7 20 0F F7 AD 46 92 F0 03 20 04 F7
+4C 74 F7 A0 00 18 71 04 91 04 48 C8 8A 71 04 91
+04 AA 68 60 C8 48 18 98 65 04 85 04 90 02 E6 05
+68 60 A0 FF E0 80 B0 02 A0 00 84 06 84 07 60 E0
+00 D0 06 AA D0 03 A9 01 60 A2 00 8A 60 A0 00 F0
+07 A9 52 A2 F0 4C 05 92 60 A9 00 85 0C A9 F0 85
+0D A9 00 85 0E A9 92 85 0F A2 CD A9 FF 85 14 A0
+00 E8 F0 0D B1 0C 91 0E C8 D0 F6 E6 0D E6 0F D0
+F0 E6 14 D0 EF 60 8C 6A 92 88 88 98 18 65 04 85
+0C A6 05 90 01 E8 86 0D A0 01 B1 0C AA 88 B1 0C
+20 CD FC A5 0C A6 0D 20 94 FD AC 6A 92 4C 05 FA
+85 0C 86 0D 20 75 F0 4C 9E FA 85 0C 86 0D A0 00
+B1 0C F0 0E C8 84 14 20 68 F0 A4 14 D0 F2 E6 0D
+D0 EE 60 E0 00 D0 15 4A AA BD 5B FE 90 05 4A 4A
+4A 4A 18 29 0F AA BD 50 FE A2 00 60 38 A9 00 AA
+60 A4 04 D0 02 C6 05 C6 04 60 A5 04 38 E9 02 85
+04 90 01 60 C6 05 60 A5 04 38 E9 04 85 04 90 01
+60 C6 05 60 A5 04 38 E9 06 85 04 90 01 60 C6 05
+60 A5 04 38 E9 07 85 04 90 01 60 C6 05 60 A0 01
+B1 04 AA 88 B1 04 E6 04 F0 05 E6 04 F0 03 60 E6
+04 E6 05 60 A0 03 4C 05 FA A0 05 4C 05 FA A0 08
+4C 05 FA 85 0C 86 0D A2 00 B1 0C 60 A0 01 B1 04
+AA 88 B1 04 60 A0 03 B1 04 85 07 88 B1 04 85 06
+88 B1 04 AA 88 B1 04 60 A2 00 18 65 04 48 8A 65
+05 AA 68 60 18 49 FF 69 01 48 8A 49 FF 69 00 AA
+A5 06 49 FF 69 00 85 06 A5 07 49 FF 69 00 85 07
+68 60 A9 00 AA A0 00 84 06 84 07 48 20 E7 FA A0
+03 A5 07 91 04 88 A5 06 91 04 88 8A 91 04 68 88
+91 04 60 85 14 20 0E FB 85 0E 86 0F 85 10 86 11
+20 A0 FC 20 0E FB 85 06 86 07 60 20 A3 FB A6 07
+A4 14 C0 0A D0 39 A5 06 05 0D 05 0C D0 11 E0 80
+D0 0D A0 0B B9 44 FE 91 0E 88 10 F8 4C 33 FC 8A
+10 1D A9 2D A0 00 91 0E E6 0E D0 02 E6 0F A5 0C
+A6 0D 20 64 FB 85 0C 86 0D 4C FF FB 20 A3 FB A9
+00 48 A0 20 A9 00 06 0C 26 0D 26 06 26 07 2A C5
+14 90 04 E5 14 E6 0C 88 D0 EC A8 B9 34 FE 48 A5
+0C 05 0D 05 06 05 07 D0 D9 A0 00 68 91 0E F0 03
+C8 D0 F8 A5 10 A6 11 60 D0 06 A2 00 8A 60 D0 FA
+A2 00 A9 01 60 F0 F9 30 F7 A2 00 8A 60 F0 02 10
+EF A2 00 8A 60 F0 E9 90 E7 A2 00 8A 60 F0 DB A2
+00 8A 2A 60 20 8D FC A6 11 F0 13 B1 0C 91 0E C8
+B1 0C 91 0E C8 D0 F4 E6 0D E6 0F CA D0 ED A6 10
+F0 08 B1 0C 91 0E C8 CA D0 F8 4C 0E FB 85 10 86
+11 20 A0 FC C8 B1 04 AA 86 0F 88 B1 04 85 0E 60
+A0 01 B1 04 85 0D 88 B1 04 85 0C 4C 16 FB A9 01
+4C CB FC A0 00 B1 04 A4 04 F0 07 C6 04 A0 00 91
+04 60 C6 05 C6 04 91 04 60 A9 00 A2 00 48 A5 04
+38 E9 02 85 04 B0 02 C6 05 A0 01 8A 91 04 68 88
+91 04 60 A0 00 91 04 C8 48 8A 91 04 68 60 85 0E
+86 0F 20 A0 FC B1 0C D1 0E D0 0C AA F0 10 C8 D0
+F4 E6 0D E6 0F D0 EE B0 03 A2 FF 60 A2 01 60 85
+0E 86 0F A2 00 A0 00 B1 0E F0 08 C8 D0 F9 E6 0F
+E8 D0 F4 98 60 85 0C 86 0D 85 0E 86 0F A0 00 B1
+0C F0 14 20 B7 FA 29 02 F0 06 B1 0C 69 20 91 0C
+C8 D0 EC E6 0D D0 E8 A5 0E A6 0F 60 20 0E FB 85
+0E 86 0F E8 8E 31 92 AA E8 8E 30 92 20 A0 FC 20
+0E FB 85 10 86 11 A0 00 84 14 B1 10 18 65 0E 91
+10 C8 B1 10 65 0F 91 10 CE 30 92 F0 11 A4 14 B1
+0C C8 D0 02 E6 0D 84 14 20 68 F0 4C 78 FD CE 31
+92 D0 EA 60 85 0C 86 0D A9 00 8D 2A 92 8D 2B 92
+A0 01 B1 04 AA 88 B1 04 20 CD FC A0 02 A9 2A 91
+04 C8 A9 92 91 04 A5 0C A6 0D 20 41 F7 AD 2A 92
+AE 2B 92 60 A9 32 85 0C A9 92 85 0D A9 00 A8 A2
+00 F0 0A 91 0C C8 D0 FB E6 0D CA D0 F6 C0 39 F0
+05 91 0C C8 D0 F7 60 62 61 64 20 74 6F 6B 65 6E
+3A 20 25 78 0A 00 53 75 63 63 65 73 73 0A 00 45
+72 72 6F 72 0A 00 53 74 61 72 74 0A 00 6F 70 5F
+63 6F 6E 64 20 65 72 72 6F 72 0A 00 49 46 20 43
+6F 6E 64 0A 00 47 6F 20 49 44 4C 45 0A 00 25 32
+78 00 0A 00 30 31 32 33 34 35 36 37 38 39 41 42
+43 44 45 46 2D 32 31 34 37 34 38 33 36 34 38 00
+00 01 02 0C 09 0A 10 40 50 A0 D0 66 66 66 66 A6
+88 88 66 66 66 66 66 66 66 66 66 09 00 00 00 00
+00 00 00 33 33 33 33 33 00 00 00 50 55 55 25 22
+22 22 22 22 22 22 22 22 02 00 00 40 44 44 14 11
+11 11 11 11 11 11 11 11 01 00 70 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/hw/efinix_fpga/simulation/Makefile b/hw/efinix_fpga/simulation/Makefile
index e59b38c..a59949e 100644
--- a/hw/efinix_fpga/simulation/Makefile
+++ b/hw/efinix_fpga/simulation/Makefile
@@ -1,4 +1,5 @@
SRCS=$(shell find src/ -type f -name "*.*v")
+TBS=$(shell find tbs/ -type f -name "*.*v")
SRCS+=$(shell find ../ip/ -type f -name "*.*v" -not \( -name "*tmpl*" \))
SRCS+=$(shell find ../src/ -type f -name "*.*v")
@@ -28,6 +29,12 @@ sim: $(TARGET)
full_sim: $(TARGET) $(SD_IMAGE)
vvp $(TARGET) -fst
+mapper_tb: $(SRCS) $(TBS)
+ iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INC) $(SRCS) $(TBS)
+
+mapper_code_tb: $(SRCS) $(TBS) $(INIT_MEM)
+ iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INC) $(SRCS) $(TBS)
+
$(TARGET): $(INIT_MEM) $(SRCS)
iverilog -g2005-sv $(FLAGS) -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)
@@ -46,3 +53,5 @@ clean:
rm -rf $(TARGET)
rm -rf $(INIT_MEM)
rm -rf $(SD_IMAGE)
+ rm -rf mapper_tb
+ rm -rf mapper_tb.vcd
diff --git a/hw/efinix_fpga/simulation/tbs/mapper_code_tb.sv b/hw/efinix_fpga/simulation/tbs/mapper_code_tb.sv
new file mode 100644
index 0000000..e18fac2
--- /dev/null
+++ b/hw/efinix_fpga/simulation/tbs/mapper_code_tb.sv
@@ -0,0 +1,23 @@
+`timescale 1ns/1ps
+
+module mapper_code_tb();
+
+sim_top u_sim_top();
+
+always begin
+ if (
+ u_sim_top.w_cpu_addr == 16'h0 &&
+ u_sim_top.w_cpu_we == '1
+ ) begin
+ if (u_sim_top.w_cpu_data_from_cpu == 8'h6d) begin
+ $display("Good finish!");
+ $finish();
+ end else begin
+ $display("Bad finish!");
+ $finish_and_return(-1);
+ end
+ end
+ # 1;
+end
+
+endmodule
\ No newline at end of file
diff --git a/hw/efinix_fpga/simulation/tbs/mapper_tb.sv b/hw/efinix_fpga/simulation/tbs/mapper_tb.sv
new file mode 100644
index 0000000..f413529
--- /dev/null
+++ b/hw/efinix_fpga/simulation/tbs/mapper_tb.sv
@@ -0,0 +1,125 @@
+`timescale 1ns/1ps
+
+module mapper_tb();
+
+logic r_clk_cpu;
+
+// clk_cpu
+initial begin
+ r_clk_cpu <= '1;
+ forever begin
+ #125 r_clk_cpu <= ~r_clk_cpu;
+ end
+end
+
+logic reset;
+logic [15:0] addr;
+logic [24:0] map_addr;
+logic [7:0] i_data;
+logic [7:0] o_data;
+logic cs;
+logic rwb;
+
+mapper u_mapper(
+ .i_reset(reset),
+ .i_clk(r_clk_cpu),
+ .i_cs(cs),
+ .i_we(~rwb),
+ .i_data(i_data),
+ .o_data(o_data),
+ .i_cpu_addr(addr),
+ .o_mapped_addr(map_addr)
+);
+
+
+/* These could be made better probably */
+task write_reg(input logic [4:0] _addr, input logic [7:0] _data);
+ @(negedge r_clk_cpu);
+ cs <= '1;
+ addr <= _addr;
+ rwb <= '0;
+ i_data <= '1;
+ @(posedge r_clk_cpu);
+ i_data <= _data;
+ @(negedge r_clk_cpu);
+ cs <= '0;
+ rwb <= '1;
+endtask
+
+task read_reg(input logic [2:0] _addr, output logic [7:0] _data);
+ @(negedge r_clk_cpu);
+ cs <= '1;
+ addr <= _addr;
+ rwb <= '1;
+ i_data <= '1;
+ @(posedge r_clk_cpu);
+ _data <= o_data;
+ @(negedge r_clk_cpu);
+ cs <= '0;
+ rwb <= '1;
+endtask
+
+int errors;
+
+int rnd_values [16];
+
+int rnd_addr;
+
+initial begin
+ for (int i = 0; i < 16; i++) begin
+ rnd_values[i] = $urandom();
+ end
+
+
+ errors = 0;
+ repeat (5) @(posedge r_clk_cpu);
+ reset = 1;
+ cs = 0;
+ rwb = 1;
+ addr = '0;
+ i_data = '0;
+ repeat (5) @(posedge r_clk_cpu);
+ reset = 0;
+ repeat (5) @(posedge r_clk_cpu);
+
+
+ for (int i = 0; i < 16; i++) begin
+ write_reg(2*i, rnd_values[i][7:0]);
+ write_reg(2*i + 1, rnd_values[i][15:8]);
+ end
+
+ repeat (5) @(posedge r_clk_cpu);
+
+ for (int i = 0; i < 16; i++) begin
+ assert (u_mapper.mm[i] == rnd_values[i][15:0]) else begin
+ $error("mm[%d] expected 0x%x got 0x%x", i, rnd_values[i][15:0], u_mapper.mm[i]);
+ errors += 1;
+ end
+ end
+
+ for (int i = 0; i < 16; i++) begin
+ rnd_addr = $urandom();
+ addr = i << 12 | rnd_addr[11:0];
+ #1 // Neccesary for this assertion to work
+ assert (map_addr == {rnd_values[i][12:0], rnd_addr[11:0]}) else begin
+ $error("Expected %x got %x", {rnd_values[i][12:0], rnd_addr[11:0]}, map_addr);
+ end
+
+ @(posedge r_clk_cpu);
+ end
+
+ if (errors != 0) begin
+ $finish_and_return(-1);
+ end else begin
+ $finish();
+ end
+end
+
+initial
+begin
+ $dumpfile("mapper_tb.vcd");
+ $dumpvars(0,mapper_tb);
+ for (int i = 0; i < 16; i++) $dumpvars(0, u_mapper.mm[i]);
+end
+
+endmodule
diff --git a/hw/efinix_fpga/src/mapper.sv b/hw/efinix_fpga/src/mapper.sv
new file mode 100644
index 0000000..1e79e17
--- /dev/null
+++ b/hw/efinix_fpga/src/mapper.sv
@@ -0,0 +1,57 @@
+module mapper(
+ input i_reset,
+ input i_clk,
+ input i_cs,
+ input i_we,
+ input [7:0] i_data,
+ output logic [7:0] o_data,
+ input [15:0] i_cpu_addr,
+ output logic [24:0] o_mapped_addr
+);
+
+logic [15:0] mm [16];
+logic [15:0] mm_next [16];
+
+logic [31:0] we;
+
+
+// TODO These have basically the same name.
+logic [15:0] mm_sel;
+
+logic [15:0] selected_mm;
+
+always_comb begin
+ we = ((i_we & i_cs) << i_cpu_addr[4:0]);
+
+ mm_sel = (1 << i_cpu_addr[4:1]);
+ o_data = mm_sel[8*i_cpu_addr[0] +: 8];
+
+ selected_mm = mm[i_cpu_addr[15:12]];
+ o_mapped_addr = {selected_mm[12:0], i_cpu_addr[11:0]};
+
+ for (int i = 0; i < 16; i++) begin
+ mm_next[i] = mm[i];
+ end
+
+ for (int i = 0; i < 32; i++) begin
+ if (we[i]) begin
+ mm_next[i/2][(i%2)*8 +: 8] = i_data;
+ end
+ end
+end
+
+always_ff @(negedge i_clk or posedge i_reset) begin
+ if (i_reset) begin
+ for (int i = 0; i < 16; i++) begin
+ mm[i] <= i;
+ end
+ end else begin
+ for (int i = 0; i < 16; i++) begin
+ mm[i] <= mm_next[i];
+ end
+ end
+
+
+end
+
+endmodule
diff --git a/hw/efinix_fpga/src/super6502.sv b/hw/efinix_fpga/src/super6502.sv
index 5cdc894..66fd0fd 100644
--- a/hw/efinix_fpga/src/super6502.sv
+++ b/hw/efinix_fpga/src/super6502.sv
@@ -72,6 +72,8 @@ always @(posedge clk_cpu) begin
end
+logic w_mapper_cs;
+
logic w_rom_cs;
logic w_leds_cs;
logic w_sdram_cs;
@@ -91,19 +93,34 @@ logic [7:0] w_uart_data_out;
logic [7:0] w_spi_data_out;
logic [7:0] w_sdram_data_out;
+logic [24:0] w_mapped_addr;
+
always_comb begin
- w_rom_cs = cpu_addr >= 16'hf000 && cpu_addr <= 16'hffff;
- w_timer_cs = cpu_addr >= 16'heff8 && cpu_addr <= 16'heffb;
- w_multiplier_cs = cpu_addr >= 16'heff0 && cpu_addr <= 16'heff7;
- w_divider_cs = cpu_addr >= 16'hefe8 && cpu_addr <= 16'hefef;
- w_uart_cs = cpu_addr >= 16'hefe6 && cpu_addr <= 16'hefe7;
- w_spi_cs = cpu_addr >= 16'hefd8 && cpu_addr <= 16'hefdb;
- w_leds_cs = cpu_addr == 16'hefff;
- w_sdram_cs = cpu_addr < 16'he000;
+ w_mapper_cs = cpu_addr >= 16'h200 && cpu_addr <= 16'h21f;
+
+ w_rom_cs = w_mapped_addr >= 16'hf000 && w_mapped_addr <= 16'hffff;
+ w_timer_cs = w_mapped_addr >= 16'heff8 && w_mapped_addr <= 16'heffb;
+ w_multiplier_cs = w_mapped_addr >= 16'heff0 && w_mapped_addr <= 16'heff7;
+ w_divider_cs = w_mapped_addr >= 16'hefe8 && w_mapped_addr <= 16'hefef;
+ w_uart_cs = w_mapped_addr >= 16'hefe6 && w_mapped_addr <= 16'hefe7;
+ w_spi_cs = w_mapped_addr >= 16'hefd8 && w_mapped_addr <= 16'hefdb;
+ w_leds_cs = w_mapped_addr == 16'hefff;
+
+ w_sdram_cs = ~(
+ w_rom_cs |
+ w_timer_cs |
+ w_multiplier_cs |
+ w_divider_cs |
+ w_uart_cs |
+ w_spi_cs |
+ w_leds_cs
+ );
if (w_rom_cs)
cpu_data_out = w_rom_data_out;
+ else if (w_mapper_cs)
+ cpu_data_out = w_mapper_data_out;
else if (w_leds_cs)
cpu_data_out = w_leds_data_out;
else if (w_timer_cs)
@@ -123,7 +140,7 @@ always_comb begin
end
rom #(.DATA_WIDTH(8), .ADDR_WIDTH(12)) u_rom(
- .addr(cpu_addr[11:0]),
+ .addr(w_mapped_addr[11:0]),
.clk(clk_cpu),
.data(w_rom_data_out)
);
@@ -146,10 +163,21 @@ timer u_timer(
.o_data(w_timer_data_out),
.cs(w_timer_cs),
.rwb(cpu_rwb),
- .addr(cpu_addr[1:0]),
+ .addr(w_mapped_addr[1:0]),
.irqb(w_timer_irqb)
);
+mapper u_mapper(
+ .i_reset(~cpu_resb),
+ .i_clk(clk_cpu),
+ .i_cs(w_mapper_cs),
+ .i_we(~cpu_rwb),
+ .i_data(cpu_data_in),
+ .o_data(w_mapper_data_out),
+ .i_cpu_addr(cpu_addr),
+ .o_mapped_addr(w_mapped_addr)
+);
+
multiplier u_multiplier(
.clk(clk_cpu),
.reset(~cpu_resb),
@@ -157,7 +185,7 @@ multiplier u_multiplier(
.o_data(w_multiplier_data_out),
.cs(w_multiplier_cs),
.rwb(cpu_rwb),
- .addr(cpu_addr[2:0])
+ .addr(w_mapped_addr[2:0])
);
divider_wrapper u_divider(
@@ -168,7 +196,7 @@ divider_wrapper u_divider(
.o_data(w_divider_data_out),
.cs(w_divider_cs),
.rwb(cpu_rwb),
- .addr(cpu_addr[2:0])
+ .addr(w_mapped_addr[2:0])
);
logic w_uart_irqb;
@@ -181,7 +209,7 @@ uart_wrapper u_uart(
.o_data(w_uart_data_out),
.cs(w_uart_cs),
.rwb(cpu_rwb),
- .addr(cpu_addr[0]),
+ .addr(w_mapped_addr[0]),
.rx_i(uart_rx),
.tx_o(uart_tx),
.irqb(w_uart_irqb)
@@ -192,7 +220,7 @@ spi_controller spi_controller(
.i_rst(~cpu_resb),
.i_cs(w_spi_cs),
.i_rwb(cpu_rwb),
- .i_addr(cpu_addr[1:0]),
+ .i_addr(w_mapped_addr[1:0]),
.i_data(cpu_data_in),
.o_data(w_spi_data_out),
@@ -213,7 +241,7 @@ sdram_adapter u_sdram_adapter(
.i_cs(w_sdram_cs),
.i_rwb(cpu_rwb),
- .i_addr(cpu_addr),
+ .i_addr(w_mapped_addr),
.i_data(cpu_data_in),
.o_data(w_sdram_data_out),
diff --git a/hw/efinix_fpga/super6502.xml b/hw/efinix_fpga/super6502.xml
index 9496adf..013bb59 100644
--- a/hw/efinix_fpga/super6502.xml
+++ b/hw/efinix_fpga/super6502.xml
@@ -1,104 +1,106 @@
-
+
+
-
-
-
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
+
+
-
-
+
+
-
+
-
+
-
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
-
-
-
-
-
+
+
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
-
+
+
+
-
\ No newline at end of file
+
diff --git a/sw/test_code/mapper_test/Makefile b/sw/test_code/mapper_test/Makefile
new file mode 100644
index 0000000..52fe60f
--- /dev/null
+++ b/sw/test_code/mapper_test/Makefile
@@ -0,0 +1,39 @@
+CC=../../cc65/bin/cl65
+LD=../../cc65/bin/cl65
+CFLAGS=-T -t none -I. --cpu "65C02"
+LDFLAGS=-C link.ld -m $(NAME).map
+
+NAME=mapper_test
+
+BIN=$(NAME).bin
+HEX=$(NAME).hex
+
+LISTS=lists
+
+SRCS=$(wildcard *.s) $(wildcard *.c)
+SRCS+=$(wildcard **/*.s) $(wildcard **/*.c)
+OBJS+=$(patsubst %.s,%.o,$(filter %s,$(SRCS)))
+OBJS+=$(patsubst %.c,%.o,$(filter %c,$(SRCS)))
+
+# Make sure the kernel linked to correct address, no relocation!
+all: $(HEX)
+
+$(HEX): $(BIN)
+ objcopy --input-target=binary --output-target=verilog $(BIN) $(HEX)
+
+$(BIN): $(OBJS)
+ $(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@
+
+%.o: %.c $(LISTS)
+ $(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
+
+%.o: %.s $(LISTS)
+ $(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
+
+$(LISTS):
+ mkdir -p $(addprefix $(LISTS)/,$(sort $(dir $(SRCS))))
+
+.PHONY: clean
+clean:
+ rm -rf $(OBJS) $(BIN) $(HEX) $(LISTS) $(NAME).map
+
diff --git a/sw/test_code/mapper_test/link.ld b/sw/test_code/mapper_test/link.ld
new file mode 100644
index 0000000..66a42fe
--- /dev/null
+++ b/sw/test_code/mapper_test/link.ld
@@ -0,0 +1,35 @@
+MEMORY
+{
+ ZP: start = $0, size = $100, type = rw, define = yes;
+ SDRAM: start = $9200, size = $4d00, type = rw, define = yes;
+ ROM: start = $F000, size = $1000, file = %O;
+}
+
+SEGMENTS {
+ ZEROPAGE: load = ZP, type = zp, define = yes;
+ DATA: load = ROM, type = rw, define = yes, run = SDRAM;
+ BSS: load = SDRAM, type = bss, define = yes;
+ HEAP: load = SDRAM, type = bss, optional = yes;
+ STARTUP: load = ROM, type = ro;
+ ONCE: load = ROM, type = ro, optional = yes;
+ CODE: load = ROM, type = ro;
+ RODATA: load = ROM, type = ro;
+ VECTORS: load = ROM, type = ro, start = $FFFA;
+}
+
+FEATURES {
+ CONDES: segment = STARTUP,
+ type = constructor,
+ label = __CONSTRUCTOR_TABLE__,
+ count = __CONSTRUCTOR_COUNT__;
+ CONDES: segment = STARTUP,
+ type = destructor,
+ label = __DESTRUCTOR_TABLE__,
+ count = __DESTRUCTOR_COUNT__;
+}
+
+SYMBOLS {
+ # Define the stack size for the application
+ __STACKSIZE__: value = $0200, type = weak;
+ __STACKSTART__: type = weak, value = $0800; # 2k stack
+}
diff --git a/sw/test_code/mapper_test/main.s b/sw/test_code/mapper_test/main.s
new file mode 100644
index 0000000..14e3b24
--- /dev/null
+++ b/sw/test_code/mapper_test/main.s
@@ -0,0 +1,64 @@
+.export _init, _nmi_int, _irq_int
+
+.code
+
+_nmi_int:
+_irq_int:
+
+MAPPER_BASE = $200
+
+_init:
+ ldx #$ff
+ txs
+
+ lda #$10
+ sta MAPPER_BASE + 2
+
+ ; This should store 0x55aa to memory $010000, instead of $001000
+
+ lda #$aa
+ sta $1000
+ lda #$55
+ sta $1001
+
+ lda #$01
+ sta MAPPER_BASE + 2
+
+ ; This should store 0xddcc to memory $001000
+
+ lda #$cc
+ sta $1000
+ lda #$dd
+ sta $1001
+
+ lda #$10
+ sta MAPPER_BASE + 2
+
+ lda $1000
+ cmp #$aa
+ bne @bad
+ lda $1001
+ cmp #$55
+ bne @bad
+
+ lda #$01
+ sta MAPPER_BASE + 2
+
+ lda $1000
+ cmp #$cc
+ bne @bad
+ lda $1001
+ cmp #$dd
+ bne @bad
+
+@end:
+ lda #$6d
+ sta $00
+ bra @end
+
+
+@bad:
+ lda #$bd
+ sta $00
+ bra @bad
+
diff --git a/sw/test_code/mapper_test/vectors.s b/sw/test_code/mapper_test/vectors.s
new file mode 100644
index 0000000..81ae6e0
--- /dev/null
+++ b/sw/test_code/mapper_test/vectors.s
@@ -0,0 +1,14 @@
+; ---------------------------------------------------------------------------
+; vectors.s
+; ---------------------------------------------------------------------------
+;
+; Defines the interrupt vector table.
+
+.import _init
+.import _nmi_int, _irq_int
+
+.segment "VECTORS"
+
+.addr _nmi_int ; NMI vector
+.addr _init ; Reset vector
+.addr _irq_int ; IRQ/BRK vector
\ No newline at end of file