From 18140b32a0ea05ef51476fbb1726965a25212168 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Wed, 6 Sep 2023 19:48:51 -0700 Subject: [PATCH 1/7] Add null mapper --- hw/efinix_fpga/addr_decode.sv | 2 + hw/efinix_fpga/debug_profile.wizard.json | 146 ++++++++++++++++++++++- hw/efinix_fpga/mapper.sv | 38 ++++++ hw/efinix_fpga/super6502.sv | 20 +++- hw/efinix_fpga/super6502.xml | 3 +- 5 files changed, 204 insertions(+), 5 deletions(-) create mode 100644 hw/efinix_fpga/mapper.sv diff --git a/hw/efinix_fpga/addr_decode.sv b/hw/efinix_fpga/addr_decode.sv index b137400..ce48f8c 100644 --- a/hw/efinix_fpga/addr_decode.sv +++ b/hw/efinix_fpga/addr_decode.sv @@ -9,6 +9,7 @@ module addr_decode output o_divider_cs, output o_uart_cs, output o_spi_cs, + output o_mapper_cs, output o_sdram_cs ); @@ -18,6 +19,7 @@ assign o_multiplier_cs = i_addr >= 16'heff0 && i_addr <= 16'heff7; assign o_divider_cs = i_addr >= 16'hefe8 && i_addr <= 16'hefef; assign o_uart_cs = i_addr >= 16'hefe6 && i_addr <= 16'hefe7; assign o_spi_cs = i_addr >= 16'hefd8 && i_addr <= 16'hefdb; +assign o_mapper_cs = i_addr >= 16'hefb7 && i_addr <= 16'hefd7; assign o_leds_cs = i_addr == 16'hefff; assign o_sdram_cs = i_addr < 16'he000; diff --git a/hw/efinix_fpga/debug_profile.wizard.json b/hw/efinix_fpga/debug_profile.wizard.json index 19ea65c..045a87c 100644 --- a/hw/efinix_fpga/debug_profile.wizard.json +++ b/hw/efinix_fpga/debug_profile.wizard.json @@ -3,12 +3,12 @@ { "name": "la0", "type": "la", - "uuid": "d9fdd9521e234ab2a085f0e0ef437289", + "uuid": "2d64f403f73d428c8b583d71d6829ed4", "trigin_en": false, "trigout_en": false, "auto_inserted": true, "capture_control": false, - "data_depth": 16384, + "data_depth": 8192, "input_pipeline": 1, "probes": [ { @@ -35,6 +35,11 @@ "name": "cpu_rdy", "width": 1, "probe_type": 1 + }, + { + "name": "w_sdram_addr", + "width": 25, + "probe_type": 1 } ] } @@ -299,6 +304,131 @@ "name": "la0_probe4", "net": "cpu_rdy", "path": [] + }, + { + "name": "la0_probe5[0]", + "net": "w_sdram_addr[0]", + "path": [] + }, + { + "name": "la0_probe5[1]", + "net": "w_sdram_addr[1]", + "path": [] + }, + { + "name": "la0_probe5[2]", + "net": "w_sdram_addr[2]", + "path": [] + }, + { + "name": "la0_probe5[3]", + "net": "w_sdram_addr[3]", + "path": [] + }, + { + "name": "la0_probe5[4]", + "net": "w_sdram_addr[4]", + "path": [] + }, + { + "name": "la0_probe5[5]", + "net": "w_sdram_addr[5]", + "path": [] + }, + { + "name": "la0_probe5[6]", + "net": "w_sdram_addr[6]", + "path": [] + }, + { + "name": "la0_probe5[7]", + "net": "w_sdram_addr[7]", + "path": [] + }, + { + "name": "la0_probe5[8]", + "net": "w_sdram_addr[8]", + "path": [] + }, + { + "name": "la0_probe5[9]", + "net": "w_sdram_addr[9]", + "path": [] + }, + { + "name": "la0_probe5[10]", + "net": "w_sdram_addr[10]", + "path": [] + }, + { + "name": "la0_probe5[11]", + "net": "w_sdram_addr[11]", + "path": [] + }, + { + "name": "la0_probe5[12]", + "net": "w_sdram_addr[12]", + "path": [] + }, + { + "name": "la0_probe5[13]", + "net": "w_sdram_addr[13]", + "path": [] + }, + { + "name": "la0_probe5[14]", + "net": "w_sdram_addr[14]", + "path": [] + }, + { + "name": "la0_probe5[15]", + "net": "w_sdram_addr[15]", + "path": [] + }, + { + "name": "la0_probe5[16]", + "net": "w_sdram_addr[16]", + "path": [] + }, + { + "name": "la0_probe5[17]", + "net": "w_sdram_addr[17]", + "path": [] + }, + { + "name": "la0_probe5[18]", + "net": "w_sdram_addr[18]", + "path": [] + }, + { + "name": "la0_probe5[19]", + "net": "w_sdram_addr[19]", + "path": [] + }, + { + "name": "la0_probe5[20]", + "net": "w_sdram_addr[20]", + "path": [] + }, + { + "name": "la0_probe5[21]", + "net": "w_sdram_addr[21]", + "path": [] + }, + { + "name": "la0_probe5[22]", + "net": "w_sdram_addr[22]", + "path": [] + }, + { + "name": "la0_probe5[23]", + "net": "w_sdram_addr[23]", + "path": [] + }, + { + "name": "la0_probe5[24]", + "net": "w_sdram_addr[24]", + "path": [] } ] } @@ -312,7 +442,7 @@ ], "session": { "wizard": { - "data_depth": 16384, + "data_depth": 8192, "capture_control": false, "selected_nets": [ { @@ -358,6 +488,16 @@ "selected_probe_type": "DATA AND TRIGGER", "child": [], "path": [] + }, + { + "name": "w_sdram_addr", + "width": 25, + "clk_domain": "clk_2", + "selected_probe_type": "DATA AND TRIGGER", + "child": [], + "path": [], + "net_idx_left": 24, + "net_idx_right": 0 } ], "top_module": "super6502", diff --git a/hw/efinix_fpga/mapper.sv b/hw/efinix_fpga/mapper.sv new file mode 100644 index 0000000..4bf88fb --- /dev/null +++ b/hw/efinix_fpga/mapper.sv @@ -0,0 +1,38 @@ +module mapper( + input clk, + input rst, + + input [15:0] cpu_addr, + output logic [24:0] sdram_addr, + + input cs, + input rw, + + input [7:0] i_data, + output logic [7:0] o_data +); + +logic [12:0] map [16]; + +logic [15:0] base_addr; + +assign base_addr = cpu_addr - 16'hefb7; + +logic en; + +always_comb begin + if (!en) begin + sdram_addr = {9'b0, cpu_addr}; + end +end + +always_ff @(posedge clk) begin + if (rst) begin + en <= '0; + end +end + +// each each entry is 4k and total address space is 64M, +// so we need 2^14 possible entries + +endmodule diff --git a/hw/efinix_fpga/super6502.sv b/hw/efinix_fpga/super6502.sv index abe90d8..1ac44d8 100644 --- a/hw/efinix_fpga/super6502.sv +++ b/hw/efinix_fpga/super6502.sv @@ -79,6 +79,7 @@ logic w_timer_cs; logic w_multiplier_cs; logic w_divider_cs; logic w_uart_cs; +logic w_mapper_cs; logic w_spi_cs; addr_decode u_addr_decode( @@ -90,6 +91,7 @@ addr_decode u_addr_decode( .o_divider_cs(w_divider_cs), .o_uart_cs(w_uart_cs), .o_spi_cs(w_spi_cs), + .o_mapper_cs(w_mapper_cs), .o_sdram_cs(w_sdram_cs) ); @@ -100,6 +102,7 @@ logic [7:0] w_multiplier_data_out; logic [7:0] w_divider_data_out; logic [7:0] w_uart_data_out; logic [7:0] w_spi_data_out; +logic [7:0] w_mapper_data_out; logic [7:0] w_sdram_data_out; always_comb begin @@ -119,6 +122,8 @@ always_comb begin cpu_data_out = w_spi_data_out; else if (w_sdram_cs) cpu_data_out = w_sdram_data_out; + else if (w_mapper_cs) + cpu_data_out = w_mapper_data_out; else cpu_data_out = 'x; end @@ -203,6 +208,19 @@ spi_controller spi_controller( .i_spi_miso(spi_miso) ); +logic [24:0] w_sdram_addr; + +mapper u_mapper( + .clk(clk_2), + .rst(~cpu_resb), + .cpu_addr(cpu_addr), + .sdram_addr(w_sdram_addr), + .cs(w_mapper_cs), + .rw(cpu_rwb), + .i_data(cpu_data_in), + .o_data(w_mapper_data_out) +); + sdram_adapter u_sdram_adapter( .i_cpuclk(clk_2), @@ -214,7 +232,7 @@ sdram_adapter u_sdram_adapter( .i_cs(w_sdram_cs), .i_rwb(cpu_rwb), - .i_addr(cpu_addr), + .i_addr(w_sdram_addr), .i_data(cpu_data_in), .o_data(w_sdram_data_out), diff --git a/hw/efinix_fpga/super6502.xml b/hw/efinix_fpga/super6502.xml index 5f9b3c7..aaabab3 100644 --- a/hw/efinix_fpga/super6502.xml +++ b/hw/efinix_fpga/super6502.xml @@ -1,5 +1,5 @@ - + @@ -20,6 +20,7 @@ + From 5fc71567f2db0fbcd0729597a677a3ff3938e8ba Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Wed, 6 Sep 2023 20:18:36 -0700 Subject: [PATCH 2/7] Add basic mapping --- hw/efinix_fpga/mapper.sv | 19 ++++++++++++++++++- hw/efinix_fpga/super6502.sv | 2 +- hw/efinix_fpga/super6502.xml | 2 +- 3 files changed, 20 insertions(+), 3 deletions(-) diff --git a/hw/efinix_fpga/mapper.sv b/hw/efinix_fpga/mapper.sv index 4bf88fb..0c75cf9 100644 --- a/hw/efinix_fpga/mapper.sv +++ b/hw/efinix_fpga/mapper.sv @@ -6,7 +6,7 @@ module mapper( output logic [24:0] sdram_addr, input cs, - input rw, + input rwb, input [7:0] i_data, output logic [7:0] o_data @@ -23,12 +23,29 @@ logic en; always_comb begin if (!en) begin sdram_addr = {9'b0, cpu_addr}; + end else begin + sdram_addr = {map[cpu_addr[15:12]], cpu_addr[11:0]}; end end always_ff @(posedge clk) begin if (rst) begin en <= '0; + for (bit [13:0] a = 14'b0; a < 14'h10; a++) begin + map[a] = a; + end + end else begin + if (~rwb & cs) begin + if (base_addr == 16'h32) begin + en <= i_data[0]; + end else begin + if (!base_addr[0]) begin + map[base_addr[3:1]] <= {i_data[5:0], map[base_addr[3:1]][7:0]}; + end else begin + map[base_addr[3:1]] <= {map[base_addr[3:1]][12:8], i_data}; + end + end + end end end diff --git a/hw/efinix_fpga/super6502.sv b/hw/efinix_fpga/super6502.sv index 1ac44d8..c00146f 100644 --- a/hw/efinix_fpga/super6502.sv +++ b/hw/efinix_fpga/super6502.sv @@ -216,7 +216,7 @@ mapper u_mapper( .cpu_addr(cpu_addr), .sdram_addr(w_sdram_addr), .cs(w_mapper_cs), - .rw(cpu_rwb), + .rwb(cpu_rwb), .i_data(cpu_data_in), .o_data(w_mapper_data_out) ); diff --git a/hw/efinix_fpga/super6502.xml b/hw/efinix_fpga/super6502.xml index aaabab3..5df8475 100644 --- a/hw/efinix_fpga/super6502.xml +++ b/hw/efinix_fpga/super6502.xml @@ -1,5 +1,5 @@ - + From 02ac7d5213a6563b5b0107e1748a53a6995a5fcc Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Thu, 7 Sep 2023 23:41:17 -0700 Subject: [PATCH 3/7] Add diagram, throw some code together --- doc/top.drawio | 107 ++++++++++++++++++++++++++++ hw/efinix_fpga/addr_decode.sv | 22 +++--- hw/efinix_fpga/control_registers.sv | 19 +++++ hw/efinix_fpga/super6502.sv | 54 ++++++++------ hw/efinix_fpga/super6502.xml | 2 +- 5 files changed, 171 insertions(+), 33 deletions(-) create mode 100644 doc/top.drawio create mode 100644 hw/efinix_fpga/control_registers.sv diff --git a/doc/top.drawio b/doc/top.drawio new file mode 100644 index 0000000..24e3027 --- /dev/null +++ b/doc/top.drawio @@ -0,0 +1,107 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hw/efinix_fpga/addr_decode.sv b/hw/efinix_fpga/addr_decode.sv index ce48f8c..2d7ed54 100644 --- a/hw/efinix_fpga/addr_decode.sv +++ b/hw/efinix_fpga/addr_decode.sv @@ -1,6 +1,8 @@ module addr_decode ( - input [15:0] i_addr, + input [24:0] i_addr, + + input config_reg_sel, output o_rom_cs, output o_leds_cs, @@ -9,18 +11,16 @@ module addr_decode output o_divider_cs, output o_uart_cs, output o_spi_cs, - output o_mapper_cs, output o_sdram_cs ); -assign o_rom_cs = i_addr >= 16'hf000 && i_addr <= 16'hffff; -assign o_timer_cs = i_addr >= 16'heff8 && i_addr <= 16'heffb; -assign o_multiplier_cs = i_addr >= 16'heff0 && i_addr <= 16'heff7; -assign o_divider_cs = i_addr >= 16'hefe8 && i_addr <= 16'hefef; -assign o_uart_cs = i_addr >= 16'hefe6 && i_addr <= 16'hefe7; -assign o_spi_cs = i_addr >= 16'hefd8 && i_addr <= 16'hefdb; -assign o_mapper_cs = i_addr >= 16'hefb7 && i_addr <= 16'hefd7; -assign o_leds_cs = i_addr == 16'hefff; -assign o_sdram_cs = i_addr < 16'he000; +assign o_rom_cs = (i_addr >= 25'hf000 && i_addr <= 25'hffff) && ~config_reg_sel; +assign o_timer_cs = (i_addr >= 25'heff8 && i_addr <= 25'heffb) && ~config_reg_sel; +assign o_multiplier_cs = (i_addr >= 25'heff0 && i_addr <= 25'heff7) && ~config_reg_sel; +assign o_divider_cs = (i_addr >= 25'hefe8 && i_addr <= 25'hefef) && ~config_reg_sel; +assign o_uart_cs = (i_addr >= 25'hefe6 && i_addr <= 25'hefe7) && ~config_reg_sel; +assign o_spi_cs = (i_addr >= 25'hefd8 && i_addr <= 25'hefdb) && ~config_reg_sel; +assign o_leds_cs = (i_addr == 25'hefff) && ~config_reg_sel; +assign o_sdram_cs = (i_addr < 25'he000 || i_addr >= 25'h10000) && ~config_reg_sel; endmodule \ No newline at end of file diff --git a/hw/efinix_fpga/control_registers.sv b/hw/efinix_fpga/control_registers.sv new file mode 100644 index 0000000..b5aaf2f --- /dev/null +++ b/hw/efinix_fpga/control_registers.sv @@ -0,0 +1,19 @@ +module control_registers #( + parameter START = 16'h0a00, + parameter SIZE = 16'h0600 +)( + input i_clk, + input i_rst, + + input logic o_selected, + input i_rwb, + input [15:0] i_addr, + input [7:0] i_data, + output logic [7:0] o_data +); + +logic [7:0] regs [SIZE]; + +assign o_selected = (addr >= START && addr > START + SIZE); + +endmodule diff --git a/hw/efinix_fpga/super6502.sv b/hw/efinix_fpga/super6502.sv index c00146f..6fa9b79 100644 --- a/hw/efinix_fpga/super6502.sv +++ b/hw/efinix_fpga/super6502.sv @@ -1,4 +1,8 @@ module super6502 +#( + parameter CONTROL_REG_START = 16'h0a00, + parameter CONTROL_REG_SIZE = 16'h0600 +) ( input logic i_sysclk, // Controller Clock (100MHz) input logic i_sdrclk, // t_su and t_wd clock (200MHz) @@ -71,6 +75,14 @@ always @(posedge clk_2) begin end end +logic w_control_reg_cs; + + +// 0a00 - 0xffff +assign w_control_reg_cs = (cpu_addr >= CONTROL_REG_START && cpu_addr < CONTROL_REG_START + CONTROL_REG_SIZE); + +// The w_control_reg_cs is redundant but whatever +assign o_mapper_cs = (cpu_addr >= 16'h0a00 && cpu_addr <= 25'h0a20) && w_control_reg_cs; logic w_rom_cs; logic w_leds_cs; @@ -83,7 +95,8 @@ logic w_mapper_cs; logic w_spi_cs; addr_decode u_addr_decode( - .i_addr(cpu_addr), + .i_addr(w_sdram_addr), + .config_reg_sel(w_control_reg_cs), .o_rom_cs(w_rom_cs), .o_leds_cs(w_leds_cs), .o_timer_cs(w_timer_cs), @@ -91,7 +104,6 @@ addr_decode u_addr_decode( .o_divider_cs(w_divider_cs), .o_uart_cs(w_uart_cs), .o_spi_cs(w_spi_cs), - .o_mapper_cs(w_mapper_cs), .o_sdram_cs(w_sdram_cs) ); @@ -128,8 +140,21 @@ always_comb begin cpu_data_out = 'x; end +logic [24:0] w_sdram_addr; + +mapper u_mapper( + .clk(clk_2), + .rst(~cpu_resb), + .cpu_addr(cpu_addr), + .sdram_addr(w_sdram_addr), + .cs(w_mapper_cs), + .rwb(cpu_rwb), + .i_data(cpu_data_in), + .o_data(w_mapper_data_out) +); + rom #(.DATA_WIDTH(8), .ADDR_WIDTH(12)) u_rom( - .addr(cpu_addr[11:0]), + .addr(w_sdram_addr[11:0]), .clk(clk_2), .data(w_rom_data_out) ); @@ -152,7 +177,7 @@ timer u_timer( .o_data(w_timer_data_out), .cs(w_timer_cs), .rwb(cpu_rwb), - .addr(cpu_addr[1:0]), + .addr(w_sdram_addr[1:0]), .irqb(w_timer_irqb) ); @@ -163,7 +188,7 @@ multiplier u_multiplier( .o_data(w_multiplier_data_out), .cs(w_multiplier_cs), .rwb(cpu_rwb), - .addr(cpu_addr[2:0]) + .addr(w_sdram_addr[2:0]) ); divider_wrapper u_divider( @@ -174,7 +199,7 @@ divider_wrapper u_divider( .o_data(w_divider_data_out), .cs(w_divider_cs), .rwb(cpu_rwb), - .addr(cpu_addr[2:0]) + .addr(w_sdram_addr[2:0]) ); logic w_uart_irqb; @@ -187,7 +212,7 @@ uart_wrapper u_uart( .o_data(w_uart_data_out), .cs(w_uart_cs), .rwb(cpu_rwb), - .addr(cpu_addr[0]), + .addr(w_sdram_addr[0]), .rx_i(uart_rx), .tx_o(uart_tx), .irqb(w_uart_irqb) @@ -198,7 +223,7 @@ spi_controller spi_controller( .i_rst(~cpu_resb), .i_cs(w_spi_cs), .i_rwb(cpu_rwb), - .i_addr(cpu_addr[1:0]), + .i_addr(w_sdram_addr[1:0]), .i_data(cpu_data_in), .o_data(w_spi_data_out), @@ -208,19 +233,6 @@ spi_controller spi_controller( .i_spi_miso(spi_miso) ); -logic [24:0] w_sdram_addr; - -mapper u_mapper( - .clk(clk_2), - .rst(~cpu_resb), - .cpu_addr(cpu_addr), - .sdram_addr(w_sdram_addr), - .cs(w_mapper_cs), - .rwb(cpu_rwb), - .i_data(cpu_data_in), - .o_data(w_mapper_data_out) -); - sdram_adapter u_sdram_adapter( .i_cpuclk(clk_2), diff --git a/hw/efinix_fpga/super6502.xml b/hw/efinix_fpga/super6502.xml index 5df8475..665473d 100644 --- a/hw/efinix_fpga/super6502.xml +++ b/hw/efinix_fpga/super6502.xml @@ -1,5 +1,5 @@ - + From 76aea3180ab8f82e1f0064cb2545349e80f0de35 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Mon, 18 Sep 2023 23:00:27 -0700 Subject: [PATCH 4/7] Move mapper into src folder --- hw/efinix_fpga/src/mapper.sv | 55 ++++++++++++++++++++++++++++++++++++ hw/efinix_fpga/super6502.xml | 3 +- 2 files changed, 57 insertions(+), 1 deletion(-) create mode 100644 hw/efinix_fpga/src/mapper.sv diff --git a/hw/efinix_fpga/src/mapper.sv b/hw/efinix_fpga/src/mapper.sv new file mode 100644 index 0000000..0c75cf9 --- /dev/null +++ b/hw/efinix_fpga/src/mapper.sv @@ -0,0 +1,55 @@ +module mapper( + input clk, + input rst, + + input [15:0] cpu_addr, + output logic [24:0] sdram_addr, + + input cs, + input rwb, + + input [7:0] i_data, + output logic [7:0] o_data +); + +logic [12:0] map [16]; + +logic [15:0] base_addr; + +assign base_addr = cpu_addr - 16'hefb7; + +logic en; + +always_comb begin + if (!en) begin + sdram_addr = {9'b0, cpu_addr}; + end else begin + sdram_addr = {map[cpu_addr[15:12]], cpu_addr[11:0]}; + end +end + +always_ff @(posedge clk) begin + if (rst) begin + en <= '0; + for (bit [13:0] a = 14'b0; a < 14'h10; a++) begin + map[a] = a; + end + end else begin + if (~rwb & cs) begin + if (base_addr == 16'h32) begin + en <= i_data[0]; + end else begin + if (!base_addr[0]) begin + map[base_addr[3:1]] <= {i_data[5:0], map[base_addr[3:1]][7:0]}; + end else begin + map[base_addr[3:1]] <= {map[base_addr[3:1]][12:8], i_data}; + end + end + end + end +end + +// each each entry is 4k and total address space is 64M, +// so we need 2^14 possible entries + +endmodule diff --git a/hw/efinix_fpga/super6502.xml b/hw/efinix_fpga/super6502.xml index 674cb88..d2ecbe3 100644 --- a/hw/efinix_fpga/super6502.xml +++ b/hw/efinix_fpga/super6502.xml @@ -1,4 +1,4 @@ - + @@ -19,6 +19,7 @@ + From dc2154e2c2845b6bcd0e8d152eaf28d01f9b2eaf Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sun, 15 Oct 2023 21:07:15 -0700 Subject: [PATCH 5/7] Fix fpga project config --- hw/efinix_fpga/super6502.peri.xml | 4 ++-- hw/efinix_fpga/super6502.xml | 3 +-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/efinix_fpga/super6502.peri.xml b/hw/efinix_fpga/super6502.peri.xml index d32a564..16b6309 100644 --- a/hw/efinix_fpga/super6502.peri.xml +++ b/hw/efinix_fpga/super6502.peri.xml @@ -1,5 +1,5 @@ - + @@ -336,7 +336,7 @@ - + diff --git a/hw/efinix_fpga/super6502.xml b/hw/efinix_fpga/super6502.xml index 55c88b1..4016eca 100644 --- a/hw/efinix_fpga/super6502.xml +++ b/hw/efinix_fpga/super6502.xml @@ -1,5 +1,5 @@ - + @@ -9,7 +9,6 @@ - From a7b7f4fe3518ad4d1146ced5af9b40fc7fd61410 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sun, 15 Oct 2023 21:27:11 -0700 Subject: [PATCH 6/7] Update build --- hw/efinix_fpga/control_registers.sv | 19 ---- hw/efinix_fpga/mapper.sv | 55 ---------- hw/efinix_fpga/src/mapper.sv | 55 ---------- hw/efinix_fpga/src/super6502.sv | 10 -- hw/efinix_fpga/super6502.xml | 165 ++++++++++++++-------------- 5 files changed, 82 insertions(+), 222 deletions(-) delete mode 100644 hw/efinix_fpga/control_registers.sv delete mode 100644 hw/efinix_fpga/mapper.sv delete mode 100644 hw/efinix_fpga/src/mapper.sv diff --git a/hw/efinix_fpga/control_registers.sv b/hw/efinix_fpga/control_registers.sv deleted file mode 100644 index b5aaf2f..0000000 --- a/hw/efinix_fpga/control_registers.sv +++ /dev/null @@ -1,19 +0,0 @@ -module control_registers #( - parameter START = 16'h0a00, - parameter SIZE = 16'h0600 -)( - input i_clk, - input i_rst, - - input logic o_selected, - input i_rwb, - input [15:0] i_addr, - input [7:0] i_data, - output logic [7:0] o_data -); - -logic [7:0] regs [SIZE]; - -assign o_selected = (addr >= START && addr > START + SIZE); - -endmodule diff --git a/hw/efinix_fpga/mapper.sv b/hw/efinix_fpga/mapper.sv deleted file mode 100644 index 0c75cf9..0000000 --- a/hw/efinix_fpga/mapper.sv +++ /dev/null @@ -1,55 +0,0 @@ -module mapper( - input clk, - input rst, - - input [15:0] cpu_addr, - output logic [24:0] sdram_addr, - - input cs, - input rwb, - - input [7:0] i_data, - output logic [7:0] o_data -); - -logic [12:0] map [16]; - -logic [15:0] base_addr; - -assign base_addr = cpu_addr - 16'hefb7; - -logic en; - -always_comb begin - if (!en) begin - sdram_addr = {9'b0, cpu_addr}; - end else begin - sdram_addr = {map[cpu_addr[15:12]], cpu_addr[11:0]}; - end -end - -always_ff @(posedge clk) begin - if (rst) begin - en <= '0; - for (bit [13:0] a = 14'b0; a < 14'h10; a++) begin - map[a] = a; - end - end else begin - if (~rwb & cs) begin - if (base_addr == 16'h32) begin - en <= i_data[0]; - end else begin - if (!base_addr[0]) begin - map[base_addr[3:1]] <= {i_data[5:0], map[base_addr[3:1]][7:0]}; - end else begin - map[base_addr[3:1]] <= {map[base_addr[3:1]][12:8], i_data}; - end - end - end - end -end - -// each each entry is 4k and total address space is 64M, -// so we need 2^14 possible entries - -endmodule diff --git a/hw/efinix_fpga/src/mapper.sv b/hw/efinix_fpga/src/mapper.sv deleted file mode 100644 index 0c75cf9..0000000 --- a/hw/efinix_fpga/src/mapper.sv +++ /dev/null @@ -1,55 +0,0 @@ -module mapper( - input clk, - input rst, - - input [15:0] cpu_addr, - output logic [24:0] sdram_addr, - - input cs, - input rwb, - - input [7:0] i_data, - output logic [7:0] o_data -); - -logic [12:0] map [16]; - -logic [15:0] base_addr; - -assign base_addr = cpu_addr - 16'hefb7; - -logic en; - -always_comb begin - if (!en) begin - sdram_addr = {9'b0, cpu_addr}; - end else begin - sdram_addr = {map[cpu_addr[15:12]], cpu_addr[11:0]}; - end -end - -always_ff @(posedge clk) begin - if (rst) begin - en <= '0; - for (bit [13:0] a = 14'b0; a < 14'h10; a++) begin - map[a] = a; - end - end else begin - if (~rwb & cs) begin - if (base_addr == 16'h32) begin - en <= i_data[0]; - end else begin - if (!base_addr[0]) begin - map[base_addr[3:1]] <= {i_data[5:0], map[base_addr[3:1]][7:0]}; - end else begin - map[base_addr[3:1]] <= {map[base_addr[3:1]][12:8], i_data}; - end - end - end - end -end - -// each each entry is 4k and total address space is 64M, -// so we need 2^14 possible entries - -endmodule diff --git a/hw/efinix_fpga/src/super6502.sv b/hw/efinix_fpga/src/super6502.sv index bd76451..2969a08 100644 --- a/hw/efinix_fpga/src/super6502.sv +++ b/hw/efinix_fpga/src/super6502.sv @@ -140,16 +140,6 @@ end logic [24:0] w_sdram_addr; -mapper u_mapper( - .clk(clk_2), - .rst(~cpu_resb), - .cpu_addr(cpu_addr), - .sdram_addr(w_sdram_addr), - .cs(w_mapper_cs), - .rwb(cpu_rwb), - .i_data(cpu_data_in), - .o_data(w_mapper_data_out) -); rom #(.DATA_WIDTH(8), .ADDR_WIDTH(12)) u_rom( .addr(cpu_addr[11:0]), diff --git a/hw/efinix_fpga/super6502.xml b/hw/efinix_fpga/super6502.xml index 4016eca..9496adf 100644 --- a/hw/efinix_fpga/super6502.xml +++ b/hw/efinix_fpga/super6502.xml @@ -1,105 +1,104 @@ - - + - - - + + + - - - - - - - - - - - - - - + + + + + + + + + + + + + + - - + + - - + + - + - + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - + + + + + + + - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + - - - + + + - + \ No newline at end of file From b179997da8c78dea3fec93aa2a963c920575551a Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sun, 15 Oct 2023 21:28:02 -0700 Subject: [PATCH 7/7] Remove docs (not for this merge) --- doc/top.drawio | 107 ------------------------------------------------- 1 file changed, 107 deletions(-) delete mode 100644 doc/top.drawio diff --git a/doc/top.drawio b/doc/top.drawio deleted file mode 100644 index 24e3027..0000000 --- a/doc/top.drawio +++ /dev/null @@ -1,107 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -