From 12fb6283ccfabbfb8f76cea85b3740c910c4980a Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Tue, 20 Dec 2022 17:26:59 -0500
Subject: [PATCH] Get block rom working

---
 hw/efinix_fpga/debug_profile.wizard.json | 6 +++---
 hw/efinix_fpga/super6502.sv              | 6 ++----
 hw/efinix_fpga/super6502.xml             | 2 +-
 3 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/hw/efinix_fpga/debug_profile.wizard.json b/hw/efinix_fpga/debug_profile.wizard.json
index 421efc5..e605521 100644
--- a/hw/efinix_fpga/debug_profile.wizard.json
+++ b/hw/efinix_fpga/debug_profile.wizard.json
@@ -3,12 +3,12 @@
         {
             "name": "la0",
             "type": "la",
-            "uuid": "2ec8ec3d274747939b82c28997a2ef1d",
+            "uuid": "244dbd2d34ea40fba571b257d0a2bb75",
             "trigin_en": false,
             "trigout_en": false,
             "auto_inserted": true,
             "capture_control": false,
-            "data_depth": 128,
+            "data_depth": 1024,
             "input_pipeline": 1,
             "probes": [
                 {
@@ -422,7 +422,7 @@
     ],
     "session": {
         "wizard": {
-            "data_depth": 128,
+            "data_depth": 1024,
             "capture_control": false,
             "selected_nets": [
                 {
diff --git a/hw/efinix_fpga/super6502.sv b/hw/efinix_fpga/super6502.sv
index 6cccb0a..f169f88 100644
--- a/hw/efinix_fpga/super6502.sv
+++ b/hw/efinix_fpga/super6502.sv
@@ -16,7 +16,7 @@ module super6502
   output logic cpu_rdy,
   output logic cpu_resb,
   output logic pll_cpu_reset,
-  output logic cpu_phi2
+  output logic cpu_phi2,
 );
 
 assign pll_cpu_reset = '1;
@@ -26,9 +26,7 @@ assign cpu_rdy = '1;
 assign cpu_irqb = '1;
 assign cpu_nmib = '1;
 
-always @(posedge clk_2) begin
-    cpu_phi2 <= ~cpu_phi2;
-end
+assign cpu_phi2 = clk_2;
 
 always @(posedge clk_2) begin
     if (button_reset == '0) begin
diff --git a/hw/efinix_fpga/super6502.xml b/hw/efinix_fpga/super6502.xml
index 82a8b09..11a500f 100644
--- a/hw/efinix_fpga/super6502.xml
+++ b/hw/efinix_fpga/super6502.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<efx:project name="super6502" description="" last_change_date="Tue December 20 2022 15:37:23" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.1.226" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
+<efx:project name="super6502" description="" last_change_date="Tue December 20 2022 17:26:24" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.1.226" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="change" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
     <efx:device_info>
         <efx:family name="Trion"/>
         <efx:device name="T20F256"/>