Add SDRAM controller (controller)

Turns out there are some issues with holding the chip select for the
SDRAM controller high for too long, so there is a simple 2-state fsm
which ensures that the chip select is only held for 1 clock cycle for
writes and for as long as it takes to read the data from sdram for
reads.

hw/fpga/addr_decode.sv

@@ -1,14 +1,16 @@
 module addr_decode(
     input logic [15:0] addr,
     output logic ram_cs,
+    output logic sdram_cs,
     output logic rom_cs,
     output logic hex_cs,
     output logic uart_cs,
     output logic irq_cs
 );
 
-assign rom_cs = addr[15];
-assign ram_cs = ~addr[15] && addr < 16'h7ff0;
+assign rom_cs = addr >= 16'h8000;
+assign ram_cs = addr < 16'h4000;
+assign sdram_cs = addr >= 16'h4000 && addr < 16'h7ff0;
 assign hex_cs = addr >= 16'h7ff0 && addr < 16'h7ff4;
 assign uart_cs = addr >= 16'h7ff4 && addr < 16'h7ff6;
 assign irq_cs  = addr == 16'h7fff;