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Add SDRAM controller (controller)

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Turns out there are some issues with holding the chip select for the
SDRAM controller high for too long, so there is a simple 2-state fsm
which ensures that the chip select is only held for 1 clock cycle for
writes and for as long as it takes to read the data from sdram for
reads.
This commit is contained in:
Byron Lathi
2022-03-17 13:31:56 -05:00
parent aa337c61d5
commit 15e3ae9688
5 changed files with 191 additions and 21 deletions
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71
hw/fpga/super6502.sv
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@@ -24,7 +24,20 @@ module super6502(
output logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5,
input logic UART_RXD,
output logic UART_TXD
output logic UART_TXD,
///////// SDRAM /////////
output DRAM_CLK,
output DRAM_CKE,
output [12: 0] DRAM_ADDR,
output [ 1: 0] DRAM_BA,
inout [15: 0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_UDQM,
output DRAM_CS_N,
output DRAM_WE_N,
output DRAM_CAS_N,
output DRAM_RAS_N
);
logic rst;
@@ -41,10 +54,12 @@ assign cpu_data = cpu_rwb ? cpu_data_out : 'z;
logic [7:0] rom_data_out;
logic [7:0] ram_data_out;
logic [7:0] sdram_data_out;
logic [7:0] uart_data_out;
logic [7:0] irq_data_out;
logic ram_cs;
logic sdram_cs;
logic rom_cs;
logic hex_cs;
logic uart_cs;
@@ -69,6 +84,7 @@ assign cpu_irqb = irq_data_out == 0;
addr_decode decode(
.addr(cpu_addr),
.ram_cs(ram_cs),
.sdram_cs(sdram_cs),
.rom_cs(rom_cs),
.hex_cs(hex_cs),
.uart_cs(uart_cs),
@@ -79,6 +95,8 @@ addr_decode decode(
always_comb begin
if (ram_cs)
cpu_data_out = ram_data_out;
else if (sdram_cs)
cpu_data_out = sdram_data_out;
else if (rom_cs)
cpu_data_out = rom_data_out;
else if (uart_cs)
@@ -89,7 +107,58 @@ always_comb begin
cpu_data_out = 'x;
end
enum logic {S_0, S_1 } teststate, next_teststate;
logic ack;
logic write;
logic _sdram_cs;
always @(posedge clk_50) begin
if (rst)
teststate <= S_0;
else
teststate <= next_teststate;
end
always_comb begin
next_teststate = teststate;
write = '0;
_sdram_cs = '0;
case (teststate)
S_0: begin
write = sdram_cs & ~cpu_rwb & cpu_phi2;
_sdram_cs = sdram_cs & cpu_phi2;
if (sdram_cs & ~cpu_rwb & ack)
next_teststate = S_1;
end
S_1: begin
if (~(sdram_cs & ~cpu_rwb))
next_teststate = S_0;
end
endcase
end
sdram_platform u0 (
.clk_clk (clk_50), // clk.clk
.reset_reset_n (1'b1), // reset.reset_n
.ext_bus_address (cpu_addr), // ext_bus.address
.ext_bus_byte_enable (1'b1), // .byte_enable
.ext_bus_read (_sdram_cs & cpu_rwb), // .read
.ext_bus_write (write), // .write
.ext_bus_write_data (cpu_data_in), // .write_data
.ext_bus_acknowledge (ack), // .acknowledge
.ext_bus_read_data (sdram_data_out), // .read_data
//SDRAM
.sdram_clk_clk(DRAM_CLK), //clk_sdram.clk
.sdram_wire_addr(DRAM_ADDR), //sdram_wire.addr
.sdram_wire_ba(DRAM_BA), //.ba
.sdram_wire_cas_n(DRAM_CAS_N), //.cas_n
.sdram_wire_cke(DRAM_CKE), //.cke
.sdram_wire_cs_n(DRAM_CS_N), //.cs_n
.sdram_wire_dq(DRAM_DQ), //.dq
.sdram_wire_dqm({DRAM_UDQM,DRAM_LDQM}), //.dqm
.sdram_wire_ras_n(DRAM_RAS_N), //.ras_n
.sdram_wire_we_n(DRAM_WE_N) //.we_n
);
ram main_memory(