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Register signals explicitly

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These were previously inferred latches, but now that they are not, we
need to register them explicitly, otherwise they will be 0
This commit is contained in:
Byron Lathi
2024-10-13 20:21:53 -07:00
parent 6bf7fee64b
commit 16858bbb9d
2 changed files with 16 additions and 3 deletions
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18
hw/super6502_fpga/src/sub/network_processor/src/tcp_packet_generator.sv
View File

@@ -67,6 +67,9 @@ logic data_checksum_clear;
logic [31:0] data_checksum_data; logic [31:0] data_checksum_data;
logic [15:0] data_checksum_final; logic [15:0] data_checksum_final;
logic [31:0] src_ip, dst_ip_next;
logic [31:0] dst_ip, src_ip_next;
checksum_calc u_header_checksum_calc( checksum_calc u_header_checksum_calc(
.i_rst (i_rst), .i_rst (i_rst),
.i_clk (i_clk), .i_clk (i_clk),
@@ -83,11 +86,15 @@ always_ff @(posedge i_clk) begin
checksum_counter <= '0; checksum_counter <= '0;
state <= IDLE; state <= IDLE;
data_expand <= '0; data_expand <= '0;
src_ip <= '0;
dst_ip <= '0;
end else begin end else begin
counter <= counter_next; counter <= counter_next;
checksum_counter <= checksum_counter_next; checksum_counter <= checksum_counter_next;
state <= state_next; state <= state_next;
data_expand <= data_expand_next; data_expand <= data_expand_next;
src_ip <= src_ip_next;
dst_ip <= dst_ip_next;
end end
end end
@@ -125,6 +132,8 @@ always_comb begin
data_expand_next = data_expand; data_expand_next = data_expand;
src_ip_next = src_ip;
dst_ip_next = dst_ip;
case (state) case (state)
IDLE: begin IDLE: begin
@@ -142,6 +151,9 @@ always_comb begin
m_ip.ip_source_ip = i_src_ip; m_ip.ip_source_ip = i_src_ip;
m_ip.ip_dest_ip = i_dst_ip; m_ip.ip_dest_ip = i_dst_ip;
src_ip_next = i_src_ip;
dst_ip_next = i_dst_ip;
if (m_ip.ip_hdr_ready) begin if (m_ip.ip_hdr_ready) begin
if (i_no_data) begin if (i_no_data) begin
state_next = HEADER; state_next = HEADER;
@@ -181,9 +193,9 @@ always_comb begin
end end
case (checksum_counter) case (checksum_counter)
0: checksum_data = m_ip.ip_source_ip; 0: checksum_data = src_ip;
1: checksum_data = m_ip.ip_dest_ip; 1: checksum_data = dst_ip;
2: checksum_data = {8'b0, m_ip.ip_protocol, (i_ip_len - 16'd20)}; // tcp length, not IP length 2: checksum_data = {8'b0, 8'h6, (i_ip_len - 16'd20)}; // tcp length, not IP length
3: checksum_data = {i_source_port, i_dest_port}; 3: checksum_data = {i_source_port, i_dest_port};
4: checksum_data = i_seq_number; 4: checksum_data = i_seq_number;
5: checksum_data = i_ack_number; 5: checksum_data = i_ack_number;

1
hw/super6502_fpga/src/sub/network_processor/src/tcp_parser.sv
View File

@@ -110,6 +110,7 @@ always_comb begin
end end
PAYLOAD: begin PAYLOAD: begin
s_ip.ip_payload_axis_tready = '1;
if (s_ip.ip_payload_axis_tlast) begin if (s_ip.ip_payload_axis_tlast) begin
counter_next = '0; counter_next = '0;
state_next = HEADER; state_next = HEADER;