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add uart interrupt

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This commit is contained in:
Byron Lathi
2023-11-21 18:47:16 -08:00
parent 4392a01de8
commit 1714a1e6da
5 changed files with 272 additions and 254 deletions
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2
hw/efinix_fpga/simulation/Makefile
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@@ -9,7 +9,7 @@ TEST_PROGRAM_NAME?=loop_test
TEST_FOLDER?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)
TEST_PROGRAM?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)/$(TEST_PROGRAM_NAME).hex
STANDALONE_TB= interrupt_controller_tb mapper_tb rtc_tb
STANDALONE_TB= interrupt_controller_tb mapper_tb rtc_tb uart_irq_tb
CODE_TB= interrupt_controller_code_tb mapper_code_tb rtc_code_tb \
devices_setup_code_tb

15
hw/efinix_fpga/simulation/tbs/uart_irq_tb.sv Normal file
View File

@@ -0,0 +1,15 @@
`timescale 1ns/1ps
module uart_irq_tb();
sim_top u_sim_top();
initial begin
u_sim_top.u_sim_uart.tx_en = 1;
@(posedge u_sim_top.r_clk_cpu);
u_sim_top.u_sim_uart.tx_data = 8'hAA;
repeat (100) @(posedge u_sim_top.r_clk_cpu);
$finish();
end
endmodule