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add uart interrupt

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This commit is contained in:
Byron Lathi
2023-11-21 18:47:16 -08:00
parent 4392a01de8
commit 1714a1e6da
5 changed files with 272 additions and 254 deletions
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42
hw/efinix_fpga/src/super6502.sv
View File

@@ -159,6 +159,24 @@ rom #(.DATA_WIDTH(8), .ADDR_WIDTH(12)) u_rom(
.data(w_rom_data_out)
);
logic w_irq;
assign cpu_irqb = ~w_irq;
logic [127:0] w_int_in;
assign w_int_in[127:2] = 0;
interrupt_controller u_interrupt_controller(
.clk(clk_cpu),
.reset(~cpu_resb),
.i_data(cpu_data_in),
.o_data(w_irq_data_out),
.addr(w_mapped_addr[0]),
.cs(w_irq_cs),
.rwb(cpu_rwb),
.int_in(w_int_in),
.int_out(w_irq)
);
leds u_leds(
.clk(clk_cpu),
.i_data(cpu_data_in),
@@ -213,7 +231,7 @@ divider_wrapper u_divider(
.addr(w_mapped_addr[2:0])
);
logic w_uart_irqb;
logic w_uart_irq;
uart_wrapper u_uart(
.clk(clk_cpu),
@@ -226,9 +244,11 @@ uart_wrapper u_uart(
.addr(w_mapped_addr[0]),
.rx_i(uart_rx),
.tx_o(uart_tx),
.irqb(w_uart_irqb)
.irq(w_uart_irq)
);
assign w_int_in[1] = w_uart_irq;
spi_controller spi_controller(
.i_clk(clk_cpu),
.i_rst(~cpu_resb),
@@ -275,24 +295,6 @@ sdram_adapter u_sdram_adapter(
.o_sdr_DQM(o_sdr_DQM)
);
logic w_irq;
assign cpu_irqb = ~w_irq;
logic [255:0] w_int_in;
assign w_int_in[255:1] = 0;
interrupt_controller u_interrupt_controller(
.clk(clk_cpu),
.reset(~cpu_resb),
.i_data(cpu_data_in),
.o_data(w_irq_data_out),
.addr(w_mapped_addr[0]),
.cs(w_irq_cs),
.rwb(cpu_rwb),
.int_in(w_int_in),
.int_out(w_irq)
);
rtc u_rtc(
.clk(clk_cpu),
.reset(~cpu_resb),

5
hw/efinix_fpga/src/uart_wrapper.sv
View File

@@ -11,7 +11,7 @@ module uart_wrapper(
input rx_i,
output tx_o,
output logic irqb
output logic irq
);
logic [7:0] status, control;
@@ -21,6 +21,8 @@ logic tx_busy, rx_busy;
logic rx_data_valid, rx_error, rx_parity_error;
logic baud_x16_ce;
assign irq = rx_data_valid;
logic tx_en;
logic [7:0] tx_data, rx_data;
@@ -47,7 +49,6 @@ enum bit [1:0] {READY, WAIT, TRANSMIT} state, next_state;
always_ff @(posedge clk_50) begin
if (reset) begin
state <= READY;
irqb <= '1;
end else begin
state <= next_state;
end