Add dumb multiplier code test

.gitlab-ci.yml

@@ -140,6 +140,24 @@ mapper_code sim:
     - TEST_PROGRAM_NAME=mapper_test make mapper_code_tb
     - ./mapper_code_tb
 
+multiplier_code sim:
+  tags:
+    - linux
+    - iverilog
+  stage: simulate
+  needs:
+    - job: build toolchain
+      artifacts: true
+  artifacts:
+    paths:
+      - hw/efinix_fpga/simulation/mapper_code_tb.vcd
+  script:
+    - source init_env.sh
+    - cd hw/efinix_fpga/simulation
+    - make clean
+    - TEST_PROGRAM_NAME=multiplier_test make mapper_code_tb
+    - ./mapper_code_tb
+
 interrupt_controller sim:
   tags:
     - linux

sw/test_code/multiplier_test/Makefile

@@ -0,0 +1,39 @@
+CC=../../cc65/bin/cl65
+LD=../../cc65/bin/cl65
+CFLAGS=-T -t none -I. --cpu "65C02"
+LDFLAGS=-C link.ld -m $(NAME).map
+
+NAME=multiplier_test
+
+BIN=$(NAME).bin
+HEX=$(NAME).hex
+
+LISTS=lists
+
+SRCS=$(wildcard *.s) $(wildcard *.c)
+SRCS+=$(wildcard **/*.s) $(wildcard **/*.c)
+OBJS+=$(patsubst %.s,%.o,$(filter %s,$(SRCS)))
+OBJS+=$(patsubst %.c,%.o,$(filter %c,$(SRCS)))
+
+# Make sure the kernel linked to correct address, no relocation!
+all: $(HEX)
+
+$(HEX): $(BIN)
+	objcopy --input-target=binary --output-target=verilog $(BIN) $(HEX)
+
+$(BIN): $(OBJS)
+	$(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@
+
+%.o: %.c $(LISTS)
+	$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
+
+%.o: %.s $(LISTS)
+	$(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@
+
+$(LISTS):
+	mkdir -p $(addprefix $(LISTS)/,$(sort $(dir $(SRCS))))
+
+.PHONY: clean
+clean:
+	rm -rf $(OBJS) $(BIN) $(HEX) $(LISTS) $(NAME).map
+

sw/test_code/multiplier_test/link.ld

@@ -0,0 +1,35 @@
+MEMORY
+{
+  ZP:  start = $0,    size = $100,  type = rw, define = yes;
+  SDRAM: start = $9200, size = $4d00, type = rw, define = yes;
+  ROM: start = $F000, size = $1000, file = %O;
+}
+
+SEGMENTS {
+    ZEROPAGE: load = ZP,  type = zp,  define   = yes;
+    DATA:     load = ROM, type = rw,  define   = yes, run = SDRAM;
+    BSS:      load = SDRAM, type = bss, define   = yes;
+    HEAP:     load = SDRAM, type = bss, optional = yes;
+    STARTUP:  load = ROM, type = ro;
+    ONCE:     load = ROM, type = ro,  optional = yes;
+    CODE:     load = ROM, type = ro;
+    RODATA:   load = ROM, type = ro;
+    VECTORS:  load = ROM, type = ro,  start    = $FFFA;
+}
+
+FEATURES {
+    CONDES:    segment = STARTUP,
+               type    = constructor,
+               label   = __CONSTRUCTOR_TABLE__,
+               count   = __CONSTRUCTOR_COUNT__;
+    CONDES:    segment = STARTUP,
+               type    = destructor,
+               label   = __DESTRUCTOR_TABLE__,
+               count   = __DESTRUCTOR_COUNT__;
+}
+
+SYMBOLS {
+    # Define the stack size for the application
+    __STACKSIZE__:  value = $0200, type = weak;
+    __STACKSTART__: type = weak, value = $0800; # 2k stack
+}

sw/test_code/multiplier_test/main.s

@@ -0,0 +1,73 @@
+.MACPACK generic
+
+.export _init, _nmi_int, _irq_int
+
+MULTIPLIER_BASE = $eff0
+
+MULTIPLIER_AL = MULTIPLIER_BASE + 0
+MULTIPLIER_AH = MULTIPLIER_BASE + 1
+MULTIPLIER_BL = MULTIPLIER_BASE + 2
+MULTIPLIER_BH = MULTIPLIER_BASE + 3
+
+MULTIPLIER_OLL = MULTIPLIER_BASE + 4
+MULTIPLIER_OLH = MULTIPLIER_BASE + 5
+MULTIPLIER_OHL = MULTIPLIER_BASE + 6
+MULTIPLIER_OHH = MULTIPLIER_BASE + 7
+
+GOLDEN_OUTPUT_0 = $03
+GOLDEN_OUTPUT_1 = $0a
+GOLDEN_OUTPUT_2 = $08
+GOLDEN_OUTPUT_3 = $00
+
+.zeropage
+finish: .res 1
+
+.data
+
+output: .res 4
+
+.code
+
+_nmi_int:
+_irq_int:
+
+_init:
+    ldx #$ff
+    txs
+
+    lda #$01
+    sta MULTIPLIER_AL
+    lda #$02
+    sta MULTIPLIER_AH
+
+    lda #$03
+    sta MULTIPLIER_BL
+    lda #$04
+    sta MULTIPLIER_BH
+
+    ldx #$00
+L1: lda MULTIPLIER_OLL,x
+    sta output,x
+    inx
+    cpx #$4
+    bne L1
+
+    lda output
+    cmp #GOLDEN_OUTPUT_0
+    bne fail
+    lda output+1
+    cmp #GOLDEN_OUTPUT_1
+    bne fail
+    lda output+2
+    cmp #GOLDEN_OUTPUT_2
+    bne fail
+    lda output+3
+    cmp #GOLDEN_OUTPUT_3
+    bne fail
+
+    lda #$6d
+    sta finish    
+
+fail:
+    lda #$bd
+    sta finish

sw/test_code/multiplier_test/vectors.s

@@ -0,0 +1,14 @@
+; ---------------------------------------------------------------------------
+; vectors.s
+; ---------------------------------------------------------------------------
+;
+; Defines the interrupt vector table.
+
+.import    _init
+.import    _nmi_int, _irq_int
+
+.segment  "VECTORS"
+
+.addr      _nmi_int    ; NMI vector
+.addr      _init       ; Reset vector
+.addr      _irq_int    ; IRQ/BRK vector