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Merge branch 'master' into 48-reduce-sim-time-for-full-sim

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Byron Lathi
2023-11-18 17:42:59 -08:00
parent da2675a3fe d8199a6438
commit 19461536a2
9 changed files with 239 additions and 9 deletions
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4
hw/efinix_fpga/simulation/src/sim_top.sv
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@@ -61,6 +61,7 @@ logic w_cpu_reset;
logic [15:0] w_cpu_addr;
logic [7:0] w_cpu_data_from_cpu, w_cpu_data_from_dut;
logic w_cpu_rdy;
logic w_cpu_irqb;
logic w_cpu_we;
logic w_cpu_phi2;
@@ -70,7 +71,7 @@ cpu_65c02 u_cpu(
.reset(~w_cpu_reset),
.AB(w_cpu_addr),
.RDY(w_cpu_rdy),
.IRQ('0),
.IRQ(~w_cpu_irqb),
.NMI('0),
.DI_s1(w_cpu_data_from_dut),
.DO(w_cpu_data_from_cpu),
@@ -114,6 +115,7 @@ super6502 u_dut(
.cpu_rwb(~w_cpu_we),
.cpu_rdy(w_cpu_rdy),
.cpu_phi2(w_cpu_phi2),
.cpu_irqb(w_cpu_irqb),
.uart_rx(w_dut_uart_rx),
.uart_tx(w_dut_uart_tx),