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RWB and ADDR are inputs, not outputs!

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This commit is contained in:
Byron Lathi
2022-12-19 23:43:45 -05:00
parent 507d783a0c
commit 19b13164e9
4 changed files with 144 additions and 44 deletions
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97
hw/efinix_fpga/debug_profile.wizard.json
View File

@@ -3,12 +3,12 @@
{
"name": "la0",
"type": "la",
"uuid": "d64eaf74d37c4eb79fa6271eeceeb4bc",
"uuid": "d0d972d74e3f4c45a9c473ba07318a8e",
"trigin_en": false,
"trigout_en": false,
"auto_inserted": true,
"capture_control": false,
"data_depth": 32,
"data_depth": 2048,
"input_pipeline": 1,
"probes": [
{
@@ -25,6 +25,21 @@
"name": "button_reset",
"width": 1,
"probe_type": 1
},
{
"name": "cpu_data_in",
"width": 8,
"probe_type": 1
},
{
"name": "cpu_rwb",
"width": 1,
"probe_type": 1
},
{
"name": "cpu_sync",
"width": 1,
"probe_type": 1
}
]
}
@@ -244,6 +259,56 @@
"name": "la0_probe2",
"net": "button_reset",
"path": []
},
{
"name": "la0_probe3[0]",
"net": "cpu_data_in[0]",
"path": []
},
{
"name": "la0_probe3[1]",
"net": "cpu_data_in[1]",
"path": []
},
{
"name": "la0_probe3[2]",
"net": "cpu_data_in[2]",
"path": []
},
{
"name": "la0_probe3[3]",
"net": "cpu_data_in[3]",
"path": []
},
{
"name": "la0_probe3[4]",
"net": "cpu_data_in[4]",
"path": []
},
{
"name": "la0_probe3[5]",
"net": "cpu_data_in[5]",
"path": []
},
{
"name": "la0_probe3[6]",
"net": "cpu_data_in[6]",
"path": []
},
{
"name": "la0_probe3[7]",
"net": "cpu_data_in[7]",
"path": []
},
{
"name": "la0_probe4",
"net": "cpu_rwb",
"path": []
},
{
"name": "la0_probe5",
"net": "cpu_sync",
"path": []
}
]
}
@@ -257,7 +322,7 @@
],
"session": {
"wizard": {
"data_depth": 32,
"data_depth": 2048,
"capture_control": false,
"selected_nets": [
{
@@ -285,6 +350,32 @@
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": []
},
{
"name": "cpu_data_in",
"width": 8,
"clk_domain": "clk_2",
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": [],
"net_idx_left": 7,
"net_idx_right": 0
},
{
"name": "cpu_rwb",
"width": 1,
"clk_domain": "clk_2",
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": []
},
{
"name": "cpu_sync",
"width": 1,
"clk_domain": "clk_2",
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": []
}
],
"top_module": "super6502",

70
hw/efinix_fpga/super6502.peri.xml
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2021.2.323.4.6" db_version="20212999" last_change_date="Tue Nov 1 18:31:26 2022" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2022.1.226" db_version="20221999" last_change_date="Mon Dec 19 23:36:04 2022" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:device_info>
<efxpt:iobank_info>
<efxpt:iobank name="1A" iostd="3.3 V LVTTL / LVCMOS"/>
@@ -21,53 +21,53 @@
<efxpt:gpio name="button_reset" gpio_def="GPIOL_02" mode="input" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="button_reset" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="cpu_addr[0]" gpio_def="GPIOL_65" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="cpu_addr[0]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:gpio name="cpu_addr[0]" gpio_def="GPIOL_65" mode="input" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="cpu_addr[0]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="cpu_addr[10]" gpio_def="GPIOL_46" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="cpu_addr[10]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:gpio name="cpu_addr[10]" gpio_def="GPIOL_46" mode="input" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="cpu_addr[10]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="cpu_addr[11]" gpio_def="GPIOL_44" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="cpu_addr[11]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:gpio name="cpu_addr[11]" gpio_def="GPIOL_44" mode="input" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="cpu_addr[11]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="cpu_addr[12]" gpio_def="GPIOL_45" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="cpu_addr[12]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:gpio name="cpu_addr[12]" gpio_def="GPIOL_45" mode="input" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="cpu_addr[12]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="cpu_addr[13]" gpio_def="GPIOL_47" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="cpu_addr[13]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:gpio name="cpu_addr[13]" gpio_def="GPIOL_47" mode="input" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="cpu_addr[13]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="cpu_addr[14]" gpio_def="GPIOL_49" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="cpu_addr[14]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:gpio name="cpu_addr[14]" gpio_def="GPIOL_49" mode="input" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="cpu_addr[14]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="cpu_addr[15]" gpio_def="GPIOL_51" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="cpu_addr[15]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:gpio name="cpu_addr[15]" gpio_def="GPIOL_51" mode="input" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="cpu_addr[15]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="cpu_addr[1]" gpio_def="GPIOL_63" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="cpu_addr[1]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:gpio name="cpu_addr[1]" gpio_def="GPIOL_63" mode="input" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="cpu_addr[1]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="cpu_addr[2]" gpio_def="GPIOL_62" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="cpu_addr[2]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:gpio name="cpu_addr[2]" gpio_def="GPIOL_62" mode="input" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="cpu_addr[2]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="cpu_addr[3]" gpio_def="GPIOL_60" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="cpu_addr[3]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:gpio name="cpu_addr[3]" gpio_def="GPIOL_60" mode="input" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="cpu_addr[3]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="cpu_addr[4]" gpio_def="GPIOL_58" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="cpu_addr[4]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:gpio name="cpu_addr[4]" gpio_def="GPIOL_58" mode="input" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="cpu_addr[4]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="cpu_addr[5]" gpio_def="GPIOL_56" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="cpu_addr[5]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:gpio name="cpu_addr[5]" gpio_def="GPIOL_56" mode="input" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="cpu_addr[5]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="cpu_addr[6]" gpio_def="GPIOL_54" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="cpu_addr[6]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:gpio name="cpu_addr[6]" gpio_def="GPIOL_54" mode="input" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="cpu_addr[6]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="cpu_addr[7]" gpio_def="GPIOL_52" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="cpu_addr[7]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:gpio name="cpu_addr[7]" gpio_def="GPIOL_52" mode="input" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="cpu_addr[7]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="cpu_addr[8]" gpio_def="GPIOL_50" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="cpu_addr[8]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:gpio name="cpu_addr[8]" gpio_def="GPIOL_50" mode="input" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="cpu_addr[8]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="cpu_addr[9]" gpio_def="GPIOL_48" mode="output" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="cpu_addr[9]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="3"/>
<efxpt:gpio name="cpu_addr[9]" gpio_def="GPIOL_48" mode="input" bus_name="cpu_addr" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:input_config name="cpu_addr[9]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="cpu_clk" gpio_def="GPIOL_71" mode="clkout" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="" name_ddio_lo="" register_option="none" clock_name="clk_2" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
@@ -135,10 +135,10 @@
</efxpt:gpio>
<efxpt:global_unused_config state="input with weak pullup"/>
<efxpt:bus name="cpu_data" mode="inout" msb="7" lsb="0"/>
<efxpt:bus name="cpu_addr" mode="output" msb="15" lsb="0"/>
<efxpt:bus name="cpu_addr" mode="input" msb="15" lsb="0"/>
</efxpt:gpio_info>
<efxpt:pll_info>
<efxpt:pll name="pll_cpu_clk" pll_def="PLL_BR0" ref_clock_name="" ref_clock_freq="50.00" multiplier="16" pre_divider="1" post_divider="8" reset_name="pll_cpu_reset" locked_name="pll_cpu_locked" is_ipfrz="false" is_bypass_lock="true">
<efxpt:pll name="pll_cpu_clk" pll_def="PLL_BR0" ref_clock_name="" ref_clock_freq="50.0000" multiplier="16" pre_divider="1" post_divider="8" reset_name="pll_cpu_reset" locked_name="pll_cpu_locked" is_ipfrz="false" is_bypass_lock="true">
<efxpt:output_clock name="clk_50" number="0" out_divider="2" adv_out_phase_shift="0"/>
<efxpt:output_clock name="clk_2" number="1" out_divider="50" adv_out_phase_shift="0"/>
<efxpt:adv_prop ref_clock_mode="external" ref_clock1_name="" ext_ref_clock_id="3" clksel_name="" feedback_clock_name="" feedback_mode="internal"/>

4
hw/efinix_fpga/super6502.sv
View File

@@ -2,19 +2,19 @@ module super6502
(
input [7:0] cpu_data_in,
input cpu_sync,
input cpu_rwb,
input pll_in,
input button_reset,
input pll_cpu_locked,
input clk_50,
input clk_2,
output logic [15:0] cpu_addr,
input logic [15:0] cpu_addr,
output logic [7:0] cpu_data_out,
output logic [7:0] cpu_data_oe,
output logic cpu_irqb,
output logic cpu_nmib,
output logic cpu_rdy,
output logic cpu_resb,
output logic cpu_rwb,
output logic pll_cpu_reset
);

17
hw/efinix_fpga/super6502.xml
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502" description="" last_change_date="Tue November 1 2022 18:28:14" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2021.2.323.4.6" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project name="super6502" description="" last_change_date="Mon December 19 2022 23:36:57" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.1.226" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion"/>
<efx:device name="T20F256"/>
@@ -34,6 +34,12 @@
<efx:param name="optimize-adder-tree" value="0" value_type="e_option"/>
<efx:param name="mult_input_regs_packing" value="1" value_type="e_option"/>
<efx:param name="mult_output_regs_packing" value="1" value_type="e_option"/>
<efx:param name="min-sr-fanout" value="0" value_type="e_option"/>
<efx:param name="seq-opt-sync-only" value="0" value_type="e_option"/>
<efx:param name="blackbox-error" value="1" value_type="e_option"/>
<efx:param name="allow-const-ram-index" value="0" value_type="e_option"/>
<efx:param name="hdl-compile-unit" value="1" value_type="e_option"/>
<efx:param name="create-onehot-fsms" value="0" value_type="e_option"/>
</efx:synthesis>
<efx:place_and_route tool_name="efx_pnr">
<efx:param name="work_dir" value="work_pnr" value_type="e_string"/>
@@ -41,15 +47,17 @@
<efx:param name="load_delaym" value="on" value_type="e_bool"/>
<efx:param name="optimization_level" value="NULL" value_type="e_option"/>
<efx:param name="seed" value="1" value_type="e_integer"/>
<efx:param name="placer_effort_level" value="2" value_type="e_option"/>
<efx:param name="max_threads" value="-1" value_type="e_integer"/>
</efx:place_and_route>
<efx:bitstream_generation tool_name="efx_pgm">
<efx:param name="mode" value="active" value_type="e_string"/>
<efx:param name="width" value="1" value_type="e_string"/>
<efx:param name="mode" value="active" value_type="e_option"/>
<efx:param name="width" value="1" value_type="e_option"/>
<efx:param name="enable_roms" value="smart" value_type="e_option"/>
<efx:param name="spi_low_power_mode" value="on" value_type="e_bool"/>
<efx:param name="io_weak_pullup" value="on" value_type="e_bool"/>
<efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option"/>
<efx:param name="bitstream_compression" value="on" value_type="e_bool"/>
<efx:param name="bitstream_compression" value="off" value_type="e_bool"/>
<efx:param name="enable_external_master_clock" value="off" value_type="e_bool"/>
<efx:param name="active_capture_clk_edge" value="posedge" value_type="e_option"/>
<efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string"/>
@@ -60,6 +68,7 @@
<efx:param name="generate_bitbin" value="off" value_type="e_bool"/>
<efx:param name="generate_hex" value="on" value_type="e_bool"/>
<efx:param name="generate_hexbin" value="off" value_type="e_bool"/>
<efx:param name="four_byte_addressing" value="off" value_type="e_bool"/>
</efx:bitstream_generation>
<efx:debugger>
<efx:param name="work_dir" value="work_dbg" value_type="e_string"/>