From 19e4344374b1c62b5792cd557cfb7bcf729ccecb Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Sun, 22 Sep 2024 23:49:36 -0700
Subject: [PATCH] Make synthesis optional

---
 .gitlab-ci.yml                       | 2 ++
 hw/super6502_fpga/super6502_fpga.xml | 5 +++++
 2 files changed, 7 insertions(+)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 92d0221..742f640 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -7,6 +7,7 @@ stages:
 
 build:
   stage: build
+  when: manual
   tags:
     - efinity
     - linux
@@ -18,6 +19,7 @@ build:
 
 sim:
   stage: sim
+  needs: []
   tags:
     - linux
     - efinity
diff --git a/hw/super6502_fpga/super6502_fpga.xml b/hw/super6502_fpga/super6502_fpga.xml
index 9c54f5a..25a33b8 100644
--- a/hw/super6502_fpga/super6502_fpga.xml
+++ b/hw/super6502_fpga/super6502_fpga.xml
@@ -204,6 +204,11 @@
         <efx:design_file name="src/sub/interfaces/axis_intf.sv" version="default" library="default" />
         <efx:design_file name="src/sub/interfaces/ip_intf.sv" version="default" library="default" />
         <efx:design_file name="src/sub/interfaces/eth_intf.sv" version="default" library="default" />
+        <efx:design_file name="src/sub/my-fifos/src/axis_saf.sv" version="default" library="default"/>
+        <efx:design_file name="src/sub/my-fifos/src/dpram.sv" version="default" library="default"/>
+        <efx:design_file name="src/sub/my-fifos/src/fifo_fwft.sv" version="default" library="default"/>
+        <efx:design_file name="src/sub/my-fifos/src/fifo.sv" version="default" library="default"/>
+        <efx:design_file name="src/sub/my-fifos/src/fwft_adapter.sv" version="default" library="default"/>
         <efx:top_vhdl_arch name="" />
     </efx:design_info>
     <efx:constraint_info>