From 1b78f51933a1d9d2dabf6cd26061c894db5a0b35 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Sat, 18 Nov 2023 15:00:44 -0800
Subject: [PATCH] Check all edge interrupts

---
 hw/efinix_fpga/simulation/Makefile            |  1 +
 .../tbs/interrupt_controller_code_tb.sv       | 10 ++-
 sw/test_code/irq_test/main.s                  | 67 ++++++++++++++++---
 3 files changed, 65 insertions(+), 13 deletions(-)

diff --git a/hw/efinix_fpga/simulation/Makefile b/hw/efinix_fpga/simulation/Makefile
index d22cccd..cdccb0f 100644
--- a/hw/efinix_fpga/simulation/Makefile
+++ b/hw/efinix_fpga/simulation/Makefile
@@ -42,6 +42,7 @@ $(CODE_TB): $(SRCS) $(TBS) $(INIT_MEM)
 $(TARGET): $(INIT_MEM) $(SRCS)
 	iverilog -g2005-sv $(FLAGS) -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)
 
+.PHONY: $(INIT_MEM)
 $(INIT_MEM):
 # Make kernel
 	$(MAKE) -C $(REPO_TOP)/sw/kernel
diff --git a/hw/efinix_fpga/simulation/tbs/interrupt_controller_code_tb.sv b/hw/efinix_fpga/simulation/tbs/interrupt_controller_code_tb.sv
index 3924f69..337a17b 100644
--- a/hw/efinix_fpga/simulation/tbs/interrupt_controller_code_tb.sv
+++ b/hw/efinix_fpga/simulation/tbs/interrupt_controller_code_tb.sv
@@ -22,12 +22,16 @@ end
 
 initial begin
     u_sim_top.u_dut.int_in = 0;
-    repeat (1000) @(posedge u_sim_top.r_clk_cpu);
-    u_sim_top.u_dut.int_in = 1;
+    repeat (2400) @(posedge u_sim_top.r_clk_cpu);
+    for (int i = 0; i < 256; i++) begin
+        repeat (100) @(posedge u_sim_top.r_clk_cpu);
+        u_sim_top.u_dut.int_in = 1 << i;
+        $display("Activiating interrupt %d", i);
+    end
 end
 
 initial begin
-    repeat (2000) @(posedge u_sim_top.r_clk_cpu);
+    repeat (40000) @(posedge u_sim_top.r_clk_cpu);
     $display("Timed out");
     $finish_and_return(-1);
 end
diff --git a/sw/test_code/irq_test/main.s b/sw/test_code/irq_test/main.s
index 6363b0a..5b1a211 100644
--- a/sw/test_code/irq_test/main.s
+++ b/sw/test_code/irq_test/main.s
@@ -1,23 +1,70 @@
+.MACPACK generic
+
 .export _init, _nmi_int, _irq_int
 
+.import tmp1
+
 CMD = $effc
 DAT = $effd
 
+.zeropage
+finish: .res 1
+curr_irq: .res 1
+
 .code
 
 _nmi_int:
 _irq_int:
+    ; We should have triggered interrupt 1
+    stz CMD
+    lda DAT
+    cmp curr_irq
+    bne @bad
+
+    lda #$ff
+    sta CMD
+    lda #$1
+    sta DAT
+
+    inc curr_irq
+    beq @good
+    cli
+    rti
+
+@good:
     lda #$6d
-    sta $00
+    sta finish
+
+@bad:
+    lda #$bd
+    sta finish
 
 _init:
-    lda #$20
-    sta CMD
-    lda #$ff
-    sta DAT
-    lda #$40
-    sta CMD
-    lda #$ff
-    sta DAT
+    ldx #$ff
+    txs
+    ldx #$20    ; enable
+    ldy #$ff
+    jsr cmd_all
+    ldx #$40    ; edge type
+    ldy #$00
+    jsr cmd_all
+    stz curr_irq
     cli
-@end:   bra @end
\ No newline at end of file
+    jmp wait
+
+cmd_all:
+    txa
+    add #$20
+    sta tmp1
+loop:
+    txa
+    sta CMD
+    tya
+    sta DAT
+    inx
+    cpx tmp1
+    blt loop
+    rts
+
+wait:
+    bra wait
\ No newline at end of file