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Check all edge interrupts

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This commit is contained in:
Byron Lathi
2023-11-18 15:00:44 -08:00
parent dea6227958
commit 1b78f51933
3 changed files with 65 additions and 13 deletions
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1
hw/efinix_fpga/simulation/Makefile
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@@ -42,6 +42,7 @@ $(CODE_TB): $(SRCS) $(TBS) $(INIT_MEM)
$(TARGET): $(INIT_MEM) $(SRCS)
iverilog -g2005-sv $(FLAGS) -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)
.PHONY: $(INIT_MEM)
$(INIT_MEM):
# Make kernel
$(MAKE) -C $(REPO_TOP)/sw/kernel

10
hw/efinix_fpga/simulation/tbs/interrupt_controller_code_tb.sv
View File

@@ -22,12 +22,16 @@ end
initial begin
u_sim_top.u_dut.int_in = 0;
repeat (1000) @(posedge u_sim_top.r_clk_cpu);
u_sim_top.u_dut.int_in = 1;
repeat (2400) @(posedge u_sim_top.r_clk_cpu);
for (int i = 0; i < 256; i++) begin
repeat (100) @(posedge u_sim_top.r_clk_cpu);
u_sim_top.u_dut.int_in = 1 << i;
$display("Activiating interrupt %d", i);
end
end
initial begin
repeat (2000) @(posedge u_sim_top.r_clk_cpu);
repeat (40000) @(posedge u_sim_top.r_clk_cpu);
$display("Timed out");
$finish_and_return(-1);
end