diff --git a/hw/super6502_fpga/src/sub/network_processor/sim/cocotb/tests/sanity.py b/hw/super6502_fpga/src/sub/network_processor/sim/cocotb/tests/sanity.py
index a2cb400..955c6f3 100644
--- a/hw/super6502_fpga/src/sub/network_processor/sim/cocotb/tests/sanity.py
+++ b/hw/super6502_fpga/src/sub/network_processor/sim/cocotb/tests/sanity.py
@@ -39,6 +39,18 @@ async def test_simple(dut):
 
     await tb.cycle_reset()
 
-    await tb.axil_master.write_dword(0, 0xffff)
+    test_data = bytearray([x % 256 for x in range(256)])
+
+    tb.axil_ram.write(0x1000, test_data)
+    tb.axil_ram.write(0x2000, test_data)
+
+    tb.axil_ram.write_dword(0x00000400, 0x00001000)
+    tb.axil_ram.write_dword(0x00000404, 64)
+    tb.axil_ram.write_dword(0x00000408, 0)
+    tb.axil_ram.write_dword(0x0000040c, 0x000000400)
+
+    await tb.axil_master.write_dword(0x22c, 0x000)
+    await tb.axil_master.write_dword(0x220, 0x400)
+    await tb.axil_master.write_dword(0x224, 0x400)
 
     await Timer(Decimal(CLK_PERIOD_NS * 400), units='ns')
\ No newline at end of file
diff --git a/hw/super6502_fpga/src/sub/network_processor/src/tcp.sv b/hw/super6502_fpga/src/sub/network_processor/src/tcp.sv
index 3d0ca7f..5015370 100644
--- a/hw/super6502_fpga/src/sub/network_processor/src/tcp.sv
+++ b/hw/super6502_fpga/src/sub/network_processor/src/tcp.sv
@@ -7,7 +7,7 @@ module tcp #(
 
     input  wire                         s_cpuif_req,
     input  wire                         s_cpuif_req_is_wr,
-    input  wire [4:0]                   s_cpuif_addr,
+    input  wire [8:0]                   s_cpuif_addr,
     input  wire [31:0]                  s_cpuif_wr_data,
     input  wire [31:0]                  s_cpuif_wr_biten,
     output wire                         s_cpuif_req_stall_wr,
@@ -193,7 +193,19 @@ ip_arb_mux_wrapper #(
 
 generate
 
-    for (genvar i = 0; i < NUM_TCP; i++) begin
+    for (genvar i = 0; i < NUM_TCP; i++) begin : TCP_STREAMS
+        logic req;
+        logic req_is_wr;
+        logic [5:0] addr;
+        logic [31:0] wr_data;
+        logic [31:0] wr_biten;
+
+        assign req = tcp_hwif_out.tcp_streams[i].req;
+        assign req_is_wr = tcp_hwif_out.tcp_streams[i].req_is_wr;
+        assign addr = tcp_hwif_out.tcp_streams[i].addr;
+        assign wr_data = tcp_hwif_out.tcp_streams[i].wr_data;
+        assign wr_biten = tcp_hwif_out.tcp_streams[i].wr_biten;
+
         tcp_stream u_tcp_stream (
             .clk                        (i_clk),
             .rst                        (i_rst),
diff --git a/hw/super6502_fpga/src/sub/network_processor/src/tcp_stream.sv b/hw/super6502_fpga/src/sub/network_processor/src/tcp_stream.sv
index bb8614c..eec2b59 100644
--- a/hw/super6502_fpga/src/sub/network_processor/src/tcp_stream.sv
+++ b/hw/super6502_fpga/src/sub/network_processor/src/tcp_stream.sv
@@ -9,7 +9,7 @@ module tcp_stream #(
 
     input wire s_cpuif_req,
     input wire s_cpuif_req_is_wr,
-    input wire [4:0] s_cpuif_addr,
+    input wire [5:0] s_cpuif_addr,
     input wire [31:0] s_cpuif_wr_data,
     input wire [31:0] s_cpuif_wr_biten,
     output wire s_cpuif_req_stall_wr,
@@ -30,6 +30,8 @@ module tcp_stream #(
 axis_intf m2s_axis();
 axis_intf s2m_axis();
 
+axis_intf m2s_post_saf_axis();
+
 // regs
 tcp_stream_regs_pkg::tcp_stream_regs__in_t hwif_in;
 tcp_stream_regs_pkg::tcp_stream_regs__out_t hwif_out;
@@ -59,8 +61,8 @@ tcp_stream_regs u_tcp_stream_regs (
 m2s_dma #(
     .AXIS_DATA_WIDTH(DATA_WIDTH)
 ) u_m2s_dma (
-    .i_clk                      (i_clk),
-    .i_rst                      (i_rst),
+    .i_clk                      (clk),
+    .i_rst                      (rst),
 
     .s_cpuif_req                (hwif_out.m2s_dma_regs.req),
     .s_cpuif_req_is_wr          (hwif_out.m2s_dma_regs.req_is_wr),
@@ -79,6 +81,44 @@ m2s_dma #(
     .m_axis                     (m2s_axis)
 );
 
+// SAF
+axis_fifo #(
+    .DEPTH(4096),
+    .DATA_WIDTH(DATA_WIDTH),
+    .FRAME_FIFO(1)
+) m2s_saf_fifo (
+    .clk                        (clk),
+    .rst                        (rst),
+
+    .s_axis_tdata               (m2s_axis.tdata),
+    .s_axis_tkeep               (m2s_axis.tkeep),
+    .s_axis_tvalid              (m2s_axis.tvalid),
+    .s_axis_tready              (m2s_axis.tready),
+    .s_axis_tlast               (m2s_axis.tlast),
+    .s_axis_tid                 (m2s_axis.tid),
+    .s_axis_tdest               (m2s_axis.tdest),
+    .s_axis_tuser               (m2s_axis.tuser),
+
+    .m_axis_tdata               (m2s_post_saf_axis.tdata),
+    .m_axis_tkeep               (m2s_post_saf_axis.tkeep),
+    .m_axis_tvalid              (m2s_post_saf_axis.tvalid),
+    .m_axis_tready              (m2s_post_saf_axis.tready),
+    .m_axis_tlast               (m2s_post_saf_axis.tlast),
+    .m_axis_tid                 (m2s_post_saf_axis.tid),
+    .m_axis_tdest               (m2s_post_saf_axis.tdest),
+    .m_axis_tuser               (m2s_post_saf_axis.tuser),
+
+    .pause_req                  ('0),
+    .pause_ack                  (),
+
+    .status_depth               (),
+    .status_depth_commit        (),
+    .status_overflow            (),
+    .status_bad_frame           (),
+    .status_good_frame          ()
+);
+
+
 // tcp state manager
 
 // tx buffer
diff --git a/hw/super6502_fpga/src/sub/stream_dmas b/hw/super6502_fpga/src/sub/stream_dmas
index 84b9e38..92ef12a 160000
--- a/hw/super6502_fpga/src/sub/stream_dmas
+++ b/hw/super6502_fpga/src/sub/stream_dmas
@@ -1 +1 @@
-Subproject commit 84b9e384ed1ae8224a127fb8d0fa4a0107ab006b
+Subproject commit 92ef12aed9a11bb4418fe20646eb819d4ce0aacf