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update sim environment

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This commit is contained in:
Byron Lathi
2023-09-21 20:35:52 -07:00
parent e50203dd3e
commit 1f503b2d80
13 changed files with 2831 additions and 274 deletions
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23
hw/efinix_fpga/simulation/Makefile
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@@ -1,20 +1,17 @@
TARGETS= timer interrupt_controller spi_controller
TB=$(patsubst %, %_tb.sv, $(TARGETS))
SRCS=$(shell find src/ -type f -name "*.*v")
SRCS+=$(shell find ../ip/ -type f -name "*.*v" -not \( -name "*tmpl*" \))
SRCS+=$(shell find ../src/ -type f -name "*.*v")
all: $(TARGETS)
INC=$(shell find include/ -type f)
timer: timer_tb.sv
iverilog -g2005-sv -s sim -o $@ $@_tb.sv ../$@.sv
#TODO implement something like sources.list
spi_controller: spi_controller_tb.sv ../spi_controller.sv
iverilog -g2005-sv -s sim -o $@ $@_tb.sv ../$@.sv
TOP_MODULE=sim_top
TARGET=sim_top
interrupt_controller: interrupt_controller_tb.sv
iverilog -g2005-sv -s sim -o $@ $@_tb.sv ../$@.sv
all:
iverilog -g2005-sv -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)
.PHONY: clean
clean:
rm -f $(TARGETS)
rm -f *.vcd
rm -f *.vvp
rm -rf $(TARGET)