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update sim environment

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This commit is contained in:
Byron Lathi
2023-09-21 20:35:52 -07:00
parent e50203dd3e
commit 1f503b2d80
13 changed files with 2831 additions and 274 deletions
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5
hw/efinix_fpga/src/sdram_adapter.sv
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@@ -245,10 +245,11 @@ logic [3:0] o_dbg_BA;
logic [25:0] o_dbg_ADDR;
logic [31:0] o_dbg_DATA_out;
logic [31:0] o_dbg_DATA_in;
logic o_sdr_init_done;
logic sdr_init_done;
logic [3:0] o_sdr_state;
assign o_ref_req = o_dbg_ref_req;
assign o_sdr_init_done = sdr_init_done;
sdram_controller u_sdram_controller(
@@ -265,7 +266,7 @@ sdram_controller u_sdram_controller(
.i_din(r_write_data), //Data to write to SDRAM. Twice normal width when running at half speed (hence the even addresses)
.i_dm(r_dm), //dm (r_dm)
.o_dout(w_data_o), //Data read from SDRAM, doubled as above.
.o_sdr_init_done(o_sdr_init_done), //Indicates that the SDRAM initialization is done.
.o_sdr_init_done(sdr_init_done), //Indicates that the SDRAM initialization is done.
.o_wr_ack(w_wr_ack), //Write acknowledge, handshake with we
.o_rd_ack(w_rd_ack), //Read acknowledge, handshake with re
.o_rd_valid(w_rd_valid),//Read valid. The data on o_dout is valid