diff --git a/hw/efinix_fpga/debug_profile.wizard.json b/hw/efinix_fpga/debug_profile.wizard.json index 209e41f..e3e4271 100644 --- a/hw/efinix_fpga/debug_profile.wizard.json +++ b/hw/efinix_fpga/debug_profile.wizard.json @@ -3,51 +3,156 @@ { "name": "la0", "type": "la", - "uuid": "0b8b4dbc24484e29a3931c7539b99820", + "uuid": "839a8cb8163a4829a5cc15adcbae907b", "trigin_en": false, "trigout_en": false, "auto_inserted": true, "capture_control": false, - "data_depth": 1024, + "data_depth": 4096, "input_pipeline": 1, "probes": [ { - "name": "sd_cmd_IN", + "name": "cpu_data_in", + "width": 8, + "probe_type": 1 + }, + { + "name": "cpu_rwb", "width": 1, "probe_type": 1 }, { - "name": "sd_cmd_OE", + "name": "cpu_sync", "width": 1, "probe_type": 1 }, { - "name": "sd_cmd_OUT", + "name": "cpu_resb", "width": 1, "probe_type": 1 }, { - "name": "sd_data_IN", + "name": "cpu_addr", + "width": 16, + "probe_type": 1 + }, + { + "name": "cpu_nmib", "width": 1, "probe_type": 1 }, { - "name": "sd_data_OE", + "name": "cpu_irqb", "width": 1, "probe_type": 1 }, { - "name": "sd_data_OUT", + "name": "cpu_data_out", + "width": 8, + "probe_type": 1 + }, + { + "name": "cpu_phi2", "width": 1, "probe_type": 1 }, { - "name": "w_sdcard_cs", + "name": "u_sdram_adapter/o_dbg_wr_ack", "width": 1, "probe_type": 1 }, { - "name": "sd_clk", + "name": "u_sdram_adapter/next_counter", + "width": 2, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/o_data", + "width": 8, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/next_state", + "width": 2, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/w_data_i", + "width": 32, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/i_rwb", + "width": 1, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/w_addr", + "width": 24, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/w_data_o", + "width": 32, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/i_cs", + "width": 1, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/counter", + "width": 2, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/state", + "width": 2, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/w_last", + "width": 1, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/w_data_valid", + "width": 1, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/w_wr_ack", + "width": 1, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/w_read", + "width": 1, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/w_write", + "width": 1, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/w_rd_ack", + "width": 1, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/w_rd_valid", + "width": 1, + "probe_type": 1 + }, + { + "name": "u_sdram_adapter/o_dbg_ref_req", + "width": 1, + "probe_type": 1 + }, + { + "name": "cpu_rdy", "width": 1, "probe_type": 1 } @@ -177,47 +282,1007 @@ }, { "name": "la0_clk", - "net": "clk_2", + "net": "i_sysclk", "path": [] }, { - "name": "la0_probe0", - "net": "sd_cmd_IN", + "name": "la0_probe0[0]", + "net": "cpu_data_in[0]", + "path": [] + }, + { + "name": "la0_probe0[1]", + "net": "cpu_data_in[1]", + "path": [] + }, + { + "name": "la0_probe0[2]", + "net": "cpu_data_in[2]", + "path": [] + }, + { + "name": "la0_probe0[3]", + "net": "cpu_data_in[3]", + "path": [] + }, + { + "name": "la0_probe0[4]", + "net": "cpu_data_in[4]", + "path": [] + }, + { + "name": "la0_probe0[5]", + "net": "cpu_data_in[5]", + "path": [] + }, + { + "name": "la0_probe0[6]", + "net": "cpu_data_in[6]", + "path": [] + }, + { + "name": "la0_probe0[7]", + "net": "cpu_data_in[7]", "path": [] }, { "name": "la0_probe1", - "net": "sd_cmd_OE", + "net": "cpu_rwb", "path": [] }, { "name": "la0_probe2", - "net": "sd_cmd_OUT", + "net": "cpu_sync", "path": [] }, { "name": "la0_probe3", - "net": "sd_data_IN", + "net": "cpu_resb", "path": [] }, { - "name": "la0_probe4", - "net": "sd_data_OE", + "name": "la0_probe4[0]", + "net": "cpu_addr[0]", + "path": [] + }, + { + "name": "la0_probe4[1]", + "net": "cpu_addr[1]", + "path": [] + }, + { + "name": "la0_probe4[2]", + "net": "cpu_addr[2]", + "path": [] + }, + { + "name": "la0_probe4[3]", + "net": "cpu_addr[3]", + "path": [] + }, + { + "name": "la0_probe4[4]", + "net": "cpu_addr[4]", + "path": [] + }, + { + "name": "la0_probe4[5]", + "net": "cpu_addr[5]", + "path": [] + }, + { + "name": "la0_probe4[6]", + "net": "cpu_addr[6]", + "path": [] + }, + { + "name": "la0_probe4[7]", + "net": "cpu_addr[7]", + "path": [] + }, + { + "name": "la0_probe4[8]", + "net": "cpu_addr[8]", + "path": [] + }, + { + "name": "la0_probe4[9]", + "net": "cpu_addr[9]", + "path": [] + }, + { + "name": "la0_probe4[10]", + "net": "cpu_addr[10]", + "path": [] + }, + { + "name": "la0_probe4[11]", + "net": "cpu_addr[11]", + "path": [] + }, + { + "name": "la0_probe4[12]", + "net": "cpu_addr[12]", + "path": [] + }, + { + "name": "la0_probe4[13]", + "net": "cpu_addr[13]", + "path": [] + }, + { + "name": "la0_probe4[14]", + "net": "cpu_addr[14]", + "path": [] + }, + { + "name": "la0_probe4[15]", + "net": "cpu_addr[15]", "path": [] }, { "name": "la0_probe5", - "net": "sd_data_OUT", + "net": "cpu_nmib", "path": [] }, { "name": "la0_probe6", - "net": "w_sdcard_cs", + "net": "cpu_irqb", "path": [] }, { - "name": "la0_probe7", - "net": "sd_clk", + "name": "la0_probe7[0]", + "net": "cpu_data_out[0]", + "path": [] + }, + { + "name": "la0_probe7[1]", + "net": "cpu_data_out[1]", + "path": [] + }, + { + "name": "la0_probe7[2]", + "net": "cpu_data_out[2]", + "path": [] + }, + { + "name": "la0_probe7[3]", + "net": "cpu_data_out[3]", + "path": [] + }, + { + "name": "la0_probe7[4]", + "net": "cpu_data_out[4]", + "path": [] + }, + { + "name": "la0_probe7[5]", + "net": "cpu_data_out[5]", + "path": [] + }, + { + "name": "la0_probe7[6]", + "net": "cpu_data_out[6]", + "path": [] + }, + { + "name": "la0_probe7[7]", + "net": "cpu_data_out[7]", + "path": [] + }, + { + "name": "la0_probe8", + "net": "cpu_phi2", + "path": [] + }, + { + "name": "la0_probe9", + "net": "o_dbg_wr_ack", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe10[0]", + "net": "next_counter[0]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe10[1]", + "net": "next_counter[1]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe11[0]", + "net": "o_data[0]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe11[1]", + "net": "o_data[1]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe11[2]", + "net": "o_data[2]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe11[3]", + "net": "o_data[3]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe11[4]", + "net": "o_data[4]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe11[5]", + "net": "o_data[5]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe11[6]", + "net": "o_data[6]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe11[7]", + "net": "o_data[7]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe12[0]", + "net": "next_state[0]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe12[1]", + "net": "next_state[1]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[0]", + "net": "w_data_i[0]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[1]", + "net": "w_data_i[1]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[2]", + "net": "w_data_i[2]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[3]", + "net": "w_data_i[3]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[4]", + "net": "w_data_i[4]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[5]", + "net": "w_data_i[5]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[6]", + "net": "w_data_i[6]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[7]", + "net": "w_data_i[7]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[8]", + "net": "w_data_i[8]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[9]", + "net": "w_data_i[9]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[10]", + "net": "w_data_i[10]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[11]", + "net": "w_data_i[11]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[12]", + "net": "w_data_i[12]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[13]", + "net": "w_data_i[13]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[14]", + "net": "w_data_i[14]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[15]", + "net": "w_data_i[15]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[16]", + "net": "w_data_i[16]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[17]", + "net": "w_data_i[17]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[18]", + "net": "w_data_i[18]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[19]", + "net": "w_data_i[19]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[20]", + "net": "w_data_i[20]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[21]", + "net": "w_data_i[21]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[22]", + "net": "w_data_i[22]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[23]", + "net": "w_data_i[23]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[24]", + "net": "w_data_i[24]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[25]", + "net": "w_data_i[25]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[26]", + "net": "w_data_i[26]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[27]", + "net": "w_data_i[27]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[28]", + "net": "w_data_i[28]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[29]", + "net": "w_data_i[29]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[30]", + "net": "w_data_i[30]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe13[31]", + "net": "w_data_i[31]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe14", + "net": "i_rwb", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[0]", + "net": "w_addr[0]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[1]", + "net": "w_addr[1]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[2]", + "net": "w_addr[2]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[3]", + "net": "w_addr[3]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[4]", + "net": "w_addr[4]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[5]", + "net": "w_addr[5]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[6]", + "net": "w_addr[6]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[7]", + "net": "w_addr[7]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[8]", + "net": "w_addr[8]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[9]", + "net": "w_addr[9]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[10]", + "net": "w_addr[10]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[11]", + "net": "w_addr[11]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[12]", + "net": "w_addr[12]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[13]", + "net": "w_addr[13]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[14]", + "net": "w_addr[14]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[15]", + "net": "w_addr[15]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[16]", + "net": "w_addr[16]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[17]", + "net": "w_addr[17]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[18]", + "net": "w_addr[18]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[19]", + "net": "w_addr[19]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[20]", + "net": "w_addr[20]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[21]", + "net": "w_addr[21]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[22]", + "net": "w_addr[22]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe15[23]", + "net": "w_addr[23]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[0]", + "net": "w_data_o[0]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[1]", + "net": "w_data_o[1]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[2]", + "net": "w_data_o[2]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[3]", + "net": "w_data_o[3]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[4]", + "net": "w_data_o[4]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[5]", + "net": "w_data_o[5]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[6]", + "net": "w_data_o[6]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[7]", + "net": "w_data_o[7]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[8]", + "net": "w_data_o[8]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[9]", + "net": "w_data_o[9]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[10]", + "net": "w_data_o[10]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[11]", + "net": "w_data_o[11]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[12]", + "net": "w_data_o[12]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[13]", + "net": "w_data_o[13]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[14]", + "net": "w_data_o[14]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[15]", + "net": "w_data_o[15]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[16]", + "net": "w_data_o[16]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[17]", + "net": "w_data_o[17]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[18]", + "net": "w_data_o[18]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[19]", + "net": "w_data_o[19]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[20]", + "net": "w_data_o[20]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[21]", + "net": "w_data_o[21]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[22]", + "net": "w_data_o[22]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[23]", + "net": "w_data_o[23]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[24]", + "net": "w_data_o[24]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[25]", + "net": "w_data_o[25]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[26]", + "net": "w_data_o[26]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[27]", + "net": "w_data_o[27]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[28]", + "net": "w_data_o[28]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[29]", + "net": "w_data_o[29]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[30]", + "net": "w_data_o[30]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe16[31]", + "net": "w_data_o[31]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe17", + "net": "i_cs", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe18[0]", + "net": "counter[0]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe18[1]", + "net": "counter[1]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe19[0]", + "net": "state[0]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe19[1]", + "net": "state[1]", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe20", + "net": "w_last", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe21", + "net": "w_data_valid", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe22", + "net": "w_wr_ack", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe23", + "net": "w_read", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe24", + "net": "w_write", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe25", + "net": "w_rd_ack", + "path": [ + "u_sdram_adapter" + ] + }, + { + "name": "la0_probe26", + "net": "w_rd_valid", + "path": [ + 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86 03 60 20 A1 F9 A6 03 A4 10 +C0 0A D0 39 A5 02 05 09 05 08 D0 11 E0 80 D0 0D +A0 0B B9 4D FC 91 0A 88 10 F8 4C 31 FA 8A 10 1D +A9 2D A0 00 91 0A E6 0A D0 02 E6 0B A5 08 A6 09 +20 4D F9 85 08 86 09 4C FD F9 20 A1 F9 A9 00 48 +A0 20 A9 00 06 08 26 09 26 02 26 03 2A C5 10 90 +04 E5 10 E6 08 88 D0 EC A8 B9 3D FC 48 A5 08 05 +09 05 02 05 03 D0 D9 A0 00 68 91 0A F0 03 C8 D0 +F8 A5 0C A6 0D 60 D0 06 A2 00 8A 60 D0 FA A2 00 +A9 01 60 F0 F9 30 F7 A2 00 8A 60 F0 02 10 EF A2 +00 8A 60 F0 E9 90 E7 A2 00 8A 60 F0 DB A2 00 8A +2A 60 A0 01 B1 00 85 09 88 B1 00 85 08 4C CC F8 +A9 01 4C 77 FA A9 00 A2 00 48 A5 00 38 E9 02 85 +00 B0 02 C6 01 A0 01 8A 91 00 68 88 91 00 60 48 +84 10 A0 01 B1 00 85 09 88 B1 00 85 08 A4 10 68 +91 08 4C CC F8 A0 00 91 00 C8 48 8A 91 00 68 60 +A0 00 91 00 C8 48 8A 91 00 C8 A5 02 91 00 C8 A5 +03 91 00 68 60 85 0A 86 0B A2 00 A0 00 B1 0A F0 +08 C8 D0 F9 E6 0B E8 D0 F4 98 60 85 08 86 09 85 +0A 86 0B A0 00 B1 08 F0 14 20 83 F8 29 02 F0 06 +B1 08 69 20 91 08 C8 D0 EC E6 09 D0 E8 A5 0A A6 +0B 60 20 C4 F8 85 0A 86 0B E8 8E 2F 02 AA E8 8E +2E 02 20 62 FA 20 C4 F8 85 0C 86 0D A0 00 84 10 +B1 0C 18 65 0A 91 0C C8 B1 0C 65 0B 91 0C CE 2E +02 F0 11 A4 10 B1 08 C8 D0 02 E6 09 84 10 20 66 +F0 4C 2E FB CE 2F 02 D0 EA 60 85 08 86 09 A9 00 +8D 28 02 8D 29 02 A0 01 B1 00 AA 88 B1 00 20 79 +FA A0 02 A9 28 91 00 C8 A9 02 91 00 A5 08 A6 09 +20 FF F4 AD 28 02 AE 29 02 60 A9 30 85 08 A9 02 +85 09 A9 00 A8 A2 02 F0 0A 91 08 C8 D0 FB E6 09 +CA D0 F6 C0 2C F0 05 91 08 C8 D0 F7 60 41 6E 64 +20 74 65 73 74 69 6E 67 20 63 70 72 69 6E 74 66 +0A 00 52 65 73 65 74 20 76 65 63 74 6F 72 3A 20 +25 78 0A 00 53 74 61 72 74 69 6E 67 20 73 64 5F +69 6E 69 74 0A 00 66 69 6E 69 73 68 20 73 64 5F +69 6E 69 74 0A 00 72 63 61 3A 20 25 78 0A 00 44 +6F 6E 65 21 0A 00 53 44 20 54 69 6D 65 64 20 6F +75 74 00 43 4D 44 34 31 3A 20 25 6C 78 0A 00 53 +65 6E 74 20 52 65 73 65 74 0A 00 49 6E 20 73 64 +5F 69 6E 69 74 0A 00 43 4D 44 32 3A 20 25 6C 78 +0A 00 43 4D 44 38 3A 20 25 6C 78 0A 00 30 31 32 +33 34 35 36 37 38 39 41 42 43 44 45 46 2D 32 31 +34 37 34 38 33 36 34 38 00 00 01 02 0C 09 0A 10 +40 50 A0 D0 66 66 66 66 A6 88 88 66 66 66 66 66 +66 66 66 66 09 00 00 00 00 00 00 00 33 33 33 33 +33 00 00 00 50 55 55 25 22 22 22 22 22 22 22 22 +22 02 00 00 40 44 44 14 11 11 11 11 11 11 11 11 +11 01 00 70 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 A5 F0 30 F0 A6 F0 diff --git a/hw/efinix_fpga/ip/divider/divider.v b/hw/efinix_fpga/ip/divider/divider.v index f221cb3..e9413c7 100644 --- a/hw/efinix_fpga/ip/divider/divider.v +++ b/hw/efinix_fpga/ip/divider/divider.v @@ -1,11 +1,11 @@ // ============================================================================= // Generated by efx_ipmgr -// Version: 2022.2.322 -// IP Version: 2.2 +// Version: 2023.1.150 +// IP Version: 5.0 // ============================================================================= //////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. // // This document contains proprietary information which is // protected by copyright. All rights are reserved. This notice @@ -43,7 +43,7 @@ // //////////////////////////////////////////////////////////////////////////////// -`define IP_UUID _e54826097db04c8995c0c56653e54765 +`define IP_UUID _80fa5e3b79ce4c76a6cd48724ad5bdd2 `define IP_NAME_CONCAT(a,b) a``b `define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) module divider ( @@ -61,7 +61,7 @@ output rfd .WIDTHN (16), .WIDTHD (16), .DREPRESENTATION ("UNSIGNED"), -.PIPELINE (0), +.PIPELINE (1'b0), .LATENCY (16) ) u_divider( .numer ( numer ), diff --git a/hw/efinix_fpga/ip/divider/divider_define.vh b/hw/efinix_fpga/ip/divider/divider_define.vh index 66c6b56..4538851 100644 --- a/hw/efinix_fpga/ip/divider/divider_define.vh +++ b/hw/efinix_fpga/ip/divider/divider_define.vh @@ -1,11 +1,11 @@ // ============================================================================= // Generated by efx_ipmgr -// Version: 2022.2.322 -// IP Version: 2.2 +// Version: 2023.1.150 +// IP Version: 5.0 // ============================================================================= //////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. // // This document contains proprietary information which is // protected by copyright. All rights are reserved. This notice @@ -47,5 +47,5 @@ localparam NREPRESENTATION = "UNSIGNED"; localparam WIDTHN = 16; localparam WIDTHD = 16; localparam DREPRESENTATION = "UNSIGNED"; -localparam PIPELINE = 0; +localparam PIPELINE = 1'b0; localparam LATENCY = 16; diff --git a/hw/efinix_fpga/ip/divider/divider_tmpl.v b/hw/efinix_fpga/ip/divider/divider_tmpl.v index bf3b514..aee9952 100644 --- a/hw/efinix_fpga/ip/divider/divider_tmpl.v +++ b/hw/efinix_fpga/ip/divider/divider_tmpl.v @@ -1,5 +1,5 @@ //////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. // // This document contains proprietary information which is // protected by copyright. All rights are reserved. This notice diff --git a/hw/efinix_fpga/ip/divider/divider_tmpl.vhd b/hw/efinix_fpga/ip/divider/divider_tmpl.vhd index 6f56c61..e8ef5d1 100644 --- a/hw/efinix_fpga/ip/divider/divider_tmpl.vhd +++ b/hw/efinix_fpga/ip/divider/divider_tmpl.vhd @@ -1,41 +1,41 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- ------------- Begin Cut here for COMPONENT Declaration ------ COMPONENT divider is PORT ( diff --git a/hw/efinix_fpga/ip/divider/ipm/component.pickle b/hw/efinix_fpga/ip/divider/ipm/component.pickle new file mode 100644 index 0000000..8dc2354 Binary files /dev/null and b/hw/efinix_fpga/ip/divider/ipm/component.pickle differ diff --git a/hw/efinix_fpga/ip/divider/ipm/graph.pickle b/hw/efinix_fpga/ip/divider/ipm/graph.pickle new file mode 100644 index 0000000..a26f853 Binary files /dev/null and b/hw/efinix_fpga/ip/divider/ipm/graph.pickle differ diff --git a/hw/efinix_fpga/ip/divider/settings.json b/hw/efinix_fpga/ip/divider/settings.json index 8bce4db..a0dafab 100644 --- a/hw/efinix_fpga/ip/divider/settings.json +++ b/hw/efinix_fpga/ip/divider/settings.json @@ -3,31 +3,31 @@ "-o", "divider", "--base_path", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip", + "/tmp/tmpeltk99q_/ip", "--vlnv", { "vendor": "efinixinc.com", "library": "arithmetic", "name": "efx_divider", - "version": "2.2" + "version": "5.0" } ], "conf": { - "NREPRESENTATION": "0", + "NREPRESENTATION": "\"UNSIGNED\"", "WIDTHN": "16", "WIDTHD": "16", - "DREPRESENTATION": "0", - "PIPELINE": "0", + "DREPRESENTATION": "\"UNSIGNED\"", + "PIPELINE": "1'b0", "LATENCY": "16" }, "output": { "external_source_source": [ - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/divider/divider.v", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/divider/divider_define.vh", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/divider/divider_tmpl.vhd", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/divider/divider_tmpl.v" + "/tmp/tmpeltk99q_/ip/divider/divider_tmpl.vhd", + "/tmp/tmpeltk99q_/ip/divider/divider_define.vh", + "/tmp/tmpeltk99q_/ip/divider/divider_tmpl.v", + "/tmp/tmpeltk99q_/ip/divider/divider.v" ] }, - "sw_version": "2022.2.322", - "generated_date": "2023-01-05T23:44:10.084005" + "sw_version": "2023.1.150", + "generated_date": "2023-07-16T16:45:12.554696" } \ No newline at end of file diff --git a/hw/efinix_fpga/ip/sdram_controller/ipm/component.pickle b/hw/efinix_fpga/ip/sdram_controller/ipm/component.pickle new file mode 100644 index 0000000..6a81c1d Binary files /dev/null and b/hw/efinix_fpga/ip/sdram_controller/ipm/component.pickle differ diff --git a/hw/efinix_fpga/ip/sdram_controller/ipm/graph.pickle b/hw/efinix_fpga/ip/sdram_controller/ipm/graph.pickle new file mode 100644 index 0000000..6dbdba1 Binary files /dev/null and b/hw/efinix_fpga/ip/sdram_controller/ipm/graph.pickle differ diff --git a/hw/efinix_fpga/ip/sdram_controller/sdram_controller.v b/hw/efinix_fpga/ip/sdram_controller/sdram_controller.v index 4ece735..b27c38b 100644 --- a/hw/efinix_fpga/ip/sdram_controller/sdram_controller.v +++ b/hw/efinix_fpga/ip/sdram_controller/sdram_controller.v @@ -1,11 +1,11 @@ // ============================================================================= // Generated by efx_ipmgr -// Version: 2022.2.322 -// IP Version: 1.6 +// Version: 2023.1.150 +// IP Version: 5.0 // ============================================================================= //////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. // // This document contains proprietary information which is // protected by copyright. All rights are reserved. This notice @@ -43,7 +43,7 @@ // //////////////////////////////////////////////////////////////////////////////// -`define IP_UUID _08775b1d2de94ebcb82f5350820af2e3 +`define IP_UUID _8fa1502251ff4c338cc5b2fd6c7f050a `define IP_NAME_CONCAT(a,b) a``b `define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) module sdram_controller ( diff --git a/hw/efinix_fpga/ip/sdram_controller/sdram_controller_define.vh b/hw/efinix_fpga/ip/sdram_controller/sdram_controller_define.vh index 9c5f846..3bbfa9a 100644 --- a/hw/efinix_fpga/ip/sdram_controller/sdram_controller_define.vh +++ b/hw/efinix_fpga/ip/sdram_controller/sdram_controller_define.vh @@ -1,11 +1,11 @@ // ============================================================================= // Generated by efx_ipmgr -// Version: 2022.2.322 -// IP Version: 1.6 +// Version: 2023.1.150 +// IP Version: 5.0 // ============================================================================= //////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. // // This document contains proprietary information which is // protected by copyright. All rights are reserved. This notice diff --git a/hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.v b/hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.v index 1ff37b5..8933d02 100644 --- a/hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.v +++ b/hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.v @@ -1,5 +1,5 @@ //////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. // // This document contains proprietary information which is // protected by copyright. All rights are reserved. This notice diff --git a/hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.vhd b/hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.vhd index 4bc9010..8120655 100644 --- a/hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.vhd +++ b/hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.vhd @@ -1,41 +1,41 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- ------------- Begin Cut here for COMPONENT Declaration ------ COMPONENT sdram_controller is PORT ( diff --git a/hw/efinix_fpga/ip/sdram_controller/settings.json b/hw/efinix_fpga/ip/sdram_controller/settings.json index 42643e4..dd440c4 100644 --- a/hw/efinix_fpga/ip/sdram_controller/settings.json +++ b/hw/efinix_fpga/ip/sdram_controller/settings.json @@ -3,20 +3,20 @@ "-o", "sdram_controller", "--base_path", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip", + "/tmp/tmpc6xveluy/ip", "--vlnv", { "vendor": "efinixinc.com", "library": "memory_controller", "name": "efx_sdram_controller", - "version": "1.6" + "version": "5.0" } ], "conf": { "fCK_MHz": "200", "tIORT_u": "2", "CL": "3", - "DDIO_TYPE": "0", + "DDIO_TYPE": "\"SOFT\"", "DQ_GROUP": "2", "ROW_WIDTH": "13", "COL_WIDTH": "9", @@ -28,17 +28,17 @@ "tREF": "64000000", "tRFC": "66", "tRP": "20", - "SDRAM_MODE": "0", + "SDRAM_MODE": "\"Native\"", "DATA_RATE": "2" }, "output": { "external_source_source": [ - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller_define.vh", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.vhd", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.v", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/sdram_controller/sdram_controller.v" + "/tmp/tmpc6xveluy/ip/sdram_controller/sdram_controller_tmpl.vhd", + "/tmp/tmpc6xveluy/ip/sdram_controller/sdram_controller_define.vh", + "/tmp/tmpc6xveluy/ip/sdram_controller/sdram_controller_tmpl.v", + "/tmp/tmpc6xveluy/ip/sdram_controller/sdram_controller.v" ] }, - "sw_version": "2022.2.322", - "generated_date": "2023-01-06T15:14:53.619359" + "sw_version": "2023.1.150", + "generated_date": "2023-07-16T16:45:19.021917" } \ No newline at end of file diff --git a/hw/efinix_fpga/ip/uart/ipm/component.pickle b/hw/efinix_fpga/ip/uart/ipm/component.pickle new file mode 100644 index 0000000..812cad0 Binary files /dev/null and b/hw/efinix_fpga/ip/uart/ipm/component.pickle differ diff --git a/hw/efinix_fpga/ip/uart/ipm/graph.pickle b/hw/efinix_fpga/ip/uart/ipm/graph.pickle new file mode 100644 index 0000000..2213ce4 Binary files /dev/null and b/hw/efinix_fpga/ip/uart/ipm/graph.pickle differ diff --git a/hw/efinix_fpga/ip/uart/settings.json b/hw/efinix_fpga/ip/uart/settings.json index c1e284a..182d6fc 100644 --- a/hw/efinix_fpga/ip/uart/settings.json +++ b/hw/efinix_fpga/ip/uart/settings.json @@ -9,26 +9,41 @@ "vendor": "efinixinc.com", "library": "serial_interface", "name": "efx_uart", - "version": "2.0" + "version": "5.0" } ], "conf": { "BYTE": "1", "CLOCK_FREQ": "50000000", "BAUD": "115200", - "ENABLE_PARITY": "0", - "FIX_BAUDRATE": "1", - "PARITY_MODE": "0", - "BOOTUP_CHECK": "0" + "ENABLE_PARITY": "1'b0", + "FIX_BAUDRATE": "1'b1", + "PARITY_MODE": "1'b0", + "BOOTUP_CHECK": "1'b1" }, "output": { "external_source_source": [ - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart.v", "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_define.vh", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_tmpl.vhd", - "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_tmpl.v" + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_tmpl.v", + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart.v", + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_tmpl.vhd" + ], + "external_example_example": [ + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/command_state.v", + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/decoder.v", + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/encoder.v", + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/led_ctl.v", + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/resets.v", + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_defines.v", + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_demo_top.v", + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/user_register.v", + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_demo.peri.xml", + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_demo.xml", + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_timing_T20.sdc", + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart.v", + "/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/T20F256_devkit/uart_define.vh" ] }, - "sw_version": "2022.2.322", - "generated_date": "2023-01-12T01:01:22.177819" + "sw_version": "2023.1.150", + "generated_date": "2023-07-16T20:20:12.259229" } \ No newline at end of file diff --git a/hw/efinix_fpga/ip/uart/uart.v b/hw/efinix_fpga/ip/uart/uart.v index df28590..f80fc6d 100644 --- a/hw/efinix_fpga/ip/uart/uart.v +++ b/hw/efinix_fpga/ip/uart/uart.v @@ -1,11 +1,11 @@ // ============================================================================= // Generated by efx_ipmgr -// Version: 2022.2.322 -// IP Version: 2.0 +// Version: 2023.1.150 +// IP Version: 5.0 // ============================================================================= //////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. // // This document contains proprietary information which is // protected by copyright. All rights are reserved. This notice @@ -43,7 +43,7 @@ // //////////////////////////////////////////////////////////////////////////////// -`define IP_UUID _5423258f8d324e3e81f7da25952c84a2 +`define IP_UUID _d1961caf8b8d4ca092806671a99095c2 `define IP_NAME_CONCAT(a,b) a``b `define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) module uart ( @@ -58,18 +58,18 @@ output rx_busy, output baud_x16_ce, input clk, input reset, -input [7:0] tx_data, input [2:0] baud_rate, -input tx_en +input tx_en, +input [7:0] tx_data ); `IP_MODULE_NAME(top_uart) #( .BYTE (1), .CLOCK_FREQ (50000000), .BAUD (115200), -.ENABLE_PARITY (0), -.FIX_BAUDRATE (1), -.PARITY_MODE (0), -.BOOTUP_CHECK (0) +.ENABLE_PARITY (1'b0), +.FIX_BAUDRATE (1'b1), +.PARITY_MODE (1'b0), +.BOOTUP_CHECK (1'b1) ) u_top_uart( .tx_o ( tx_o ), .rx_i ( rx_i ), @@ -82,9 +82,9 @@ input tx_en .baud_x16_ce ( baud_x16_ce ), .clk ( clk ), .reset ( reset ), -.tx_data ( tx_data ), .baud_rate ( baud_rate ), -.tx_en ( tx_en ) +.tx_en ( tx_en ), +.tx_data ( tx_data ) ); endmodule diff --git a/hw/efinix_fpga/ip/uart/uart_define.vh b/hw/efinix_fpga/ip/uart/uart_define.vh index 4f0f893..40752e0 100644 --- a/hw/efinix_fpga/ip/uart/uart_define.vh +++ b/hw/efinix_fpga/ip/uart/uart_define.vh @@ -1,11 +1,11 @@ // ============================================================================= // Generated by efx_ipmgr -// Version: 2022.2.322 -// IP Version: 2.0 +// Version: 2023.1.150 +// IP Version: 5.0 // ============================================================================= //////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. // // This document contains proprietary information which is // protected by copyright. All rights are reserved. This notice @@ -46,7 +46,7 @@ localparam BYTE = 1; localparam CLOCK_FREQ = 50000000; localparam BAUD = 115200; -localparam ENABLE_PARITY = 0; -localparam FIX_BAUDRATE = 1; -localparam PARITY_MODE = 0; -localparam BOOTUP_CHECK = 0; +localparam ENABLE_PARITY = 1'b0; +localparam FIX_BAUDRATE = 1'b1; +localparam PARITY_MODE = 1'b0; +localparam BOOTUP_CHECK = 1'b1; diff --git a/hw/efinix_fpga/ip/uart/uart_tmpl.v b/hw/efinix_fpga/ip/uart/uart_tmpl.v index 45a2939..a84a9a3 100644 --- a/hw/efinix_fpga/ip/uart/uart_tmpl.v +++ b/hw/efinix_fpga/ip/uart/uart_tmpl.v @@ -1,5 +1,5 @@ //////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// Copyright (C) 2013-2023 Efinix Inc. All rights reserved. // // This document contains proprietary information which is // protected by copyright. All rights are reserved. This notice @@ -49,7 +49,7 @@ uart u_uart( .baud_x16_ce ( baud_x16_ce ), .clk ( clk ), .reset ( reset ), -.tx_data ( tx_data ), .baud_rate ( baud_rate ), -.tx_en ( tx_en ) +.tx_en ( tx_en ), +.tx_data ( tx_data ) ); diff --git a/hw/efinix_fpga/ip/uart/uart_tmpl.vhd b/hw/efinix_fpga/ip/uart/uart_tmpl.vhd index 422f662..2ae5367 100644 --- a/hw/efinix_fpga/ip/uart/uart_tmpl.vhd +++ b/hw/efinix_fpga/ip/uart/uart_tmpl.vhd @@ -1,41 +1,41 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2013-2022 Efinix Inc. All rights reserved. -// -// This document contains proprietary information which is -// protected by copyright. All rights are reserved. This notice -// refers to original work by Efinix, Inc. which may be derivitive -// of other work distributed under license of the authors. In the -// case of derivative work, nothing in this notice overrides the -// original author's license agreement. Where applicable, the -// original license agreement is included in it's original -// unmodified form immediately below this header. -// -// WARRANTY DISCLAIMER. -// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND -// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH -// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, -// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR -// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED -// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. -// -// LIMITATION OF LIABILITY. -// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY -// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT -// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY -// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, -// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY -// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF -// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR -// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN -// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER -// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE -// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO -// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR -// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT -// APPLY TO LICENSEE. -// -//////////////////////////////////////////////////////////////////////////////// +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2023 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- ------------- Begin Cut here for COMPONENT Declaration ------ COMPONENT uart is PORT ( @@ -50,9 +50,9 @@ rx_busy : out std_logic; baud_x16_ce : out std_logic; clk : in std_logic; reset : in std_logic; -tx_data : in std_logic_vector(7 downto 0); baud_rate : in std_logic_vector(2 downto 0); -tx_en : in std_logic); +tx_en : in std_logic; +tx_data : in std_logic_vector(7 downto 0)); END COMPONENT; ---------------------- End COMPONENT Declaration ------------ @@ -70,7 +70,7 @@ rx_busy => rx_busy, baud_x16_ce => baud_x16_ce, clk => clk, reset => reset, -tx_data => tx_data, baud_rate => baud_rate, -tx_en => tx_en); +tx_en => tx_en, +tx_data => tx_data); ------------------------ End INSTANTIATION Template --------- diff --git a/hw/efinix_fpga/super6502.peri.xml b/hw/efinix_fpga/super6502.peri.xml index 96b3283..c44660e 100644 --- a/hw/efinix_fpga/super6502.peri.xml +++ b/hw/efinix_fpga/super6502.peri.xml @@ -1,5 +1,5 @@ - + @@ -326,7 +326,7 @@ - + diff --git a/hw/efinix_fpga/super6502.sv b/hw/efinix_fpga/super6502.sv index fc82502..c0d8457 100644 --- a/hw/efinix_fpga/super6502.sv +++ b/hw/efinix_fpga/super6502.sv @@ -69,9 +69,11 @@ assign pll_cpu_reset = '1; assign o_pll_reset = '1; assign cpu_data_oe = {8{cpu_rwb}}; -assign cpu_rdy = '1; assign cpu_nmib = '1; +logic w_wait; +assign cpu_rdy = ~w_wait; + assign cpu_phi2 = clk_2; logic w_sdr_init_done; @@ -244,6 +246,7 @@ sdram_adapter u_sdram_adapter( .o_data(w_sdram_data_out), .o_sdr_init_done(w_sdr_init_done), + .o_wait(w_wait), .o_sdr_CKE(o_sdr_CKE), .o_sdr_n_CS(o_sdr_n_CS), diff --git a/hw/efinix_fpga/super6502.xml b/hw/efinix_fpga/super6502.xml index f3a3f61..3843189 100644 --- a/hw/efinix_fpga/super6502.xml +++ b/hw/efinix_fpga/super6502.xml @@ -1,5 +1,5 @@ - + @@ -8,11 +8,6 @@ - - - - - @@ -23,6 +18,7 @@ + @@ -69,6 +65,8 @@ + +