bslathi19/super6502
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This commit is contained in:
Byron Lathi
2023-07-19 21:06:20 -07:00
parent 2f11808f11
commit 21e3a477c1
26 changed files with 1804 additions and 4334 deletions
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4
hw/efinix_fpga/super6502.peri.xml
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@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2022.2.322" db_version="20222999" last_change_date="Thu Jan 12 16:23:51 2023" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:design_db name="super6502" device_def="T20F256" location="/home/byron/Projects/super6502/hw/efinix_fpga" version="2023.1.150" db_version="20231999" last_change_date="Sun Jul 16 13:10:02 2023" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:device_info>
<efxpt:iobank_info>
<efxpt:iobank name="1A" iostd="3.3 V LVTTL / LVCMOS"/>
@@ -326,7 +326,7 @@
<efxpt:input_config name="uart_rx" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none"/>
</efxpt:gpio>
<efxpt:gpio name="uart_tx" gpio_def="GPIOL_12" mode="output" bus_name="" is_lvds_gpio="false" io_standard="3.3 V LVTTL / LVCMOS">
<efxpt:output_config name="uart_tx" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="1"/>
<efxpt:output_config name="uart_tx" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" drive_strength="4"/>
</efxpt:gpio>
<efxpt:global_unused_config state="input with weak pullup"/>
<efxpt:bus name="cpu_data" mode="inout" msb="7" lsb="0"/>