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This commit is contained in:
Byron Lathi
2024-10-14 23:48:16 -07:00
parent bc9b04853c
commit 21efb8ace8
11 changed files with 198 additions and 3 deletions
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2
hw/super6502_fpga/src/sim/Makefile
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@@ -23,7 +23,7 @@ all: waves
waves: $(TB_NAME)
# ./$(TB_NAME) -fst
./obj_dir/Vsim_top
./obj_dir/Vsim_top | tee run.log
$(TB_NAME): $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) $(COPY_FILES) $(SD_IMAGE)
# $(IVERILOG) -g2005-sv $(FLAGS) -s $@ -o $@ $(INCLUDE) $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) -I ../../

6
hw/super6502_fpga/src/sim/hvl/sim_top.sv
View File

@@ -197,8 +197,12 @@ initial begin
button_resetn <= '0;
repeat(10) @(clk_cpu);
button_resetn <= '1;
repeat(20000) @(posedge clk_cpu);
repeat(2000) @(posedge clk_cpu);
$finish();
end
always @(posedge w_cpu0_sync) begin
$display("[%t] CPU Executed %x:%x", $time(), w_cpu0_addr, w_cpu0_data_from_dut);
end
endmodule