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Synthesize sd card dma

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This commit is contained in:
Byron Lathi
2024-03-17 22:26:42 -07:00
parent 9b50dab855
commit 25f51deaa7
6 changed files with 148 additions and 108 deletions
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56
hw/super6502_fpga/src/rtl/super_6502_fpga.sv
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@@ -236,29 +236,29 @@ cpu_wrapper u_cpu_wrapper_0(
axi_crossbar #(
.N_INITIATORS(1),
.N_INITIATORS(2),
.N_TARGETS(4)
) u_crossbar (
.clk(i_sysclk),
.rst(~master_reset),
.ini_araddr ({cpu0_ARADDR }),
.ini_arvalid ({cpu0_ARVALID }),
.ini_arready ({cpu0_ARREADY }),
.ini_rdata ({cpu0_RDATA }),
.ini_rresp ({cpu0_RRESP }),
.ini_rvalid ({cpu0_RVALID }),
.ini_rready ({cpu0_RREADY }),
.ini_awaddr ({cpu0_AWADDR }),
.ini_awready ({cpu0_AWREADY }),
.ini_awvalid ({cpu0_AWVALID }),
.ini_wvalid ({cpu0_WVALID }),
.ini_wready ({cpu0_WREADY }),
.ini_wdata ({cpu0_WDATA }),
.ini_wstrb ({cpu0_WSTRB }),
.ini_bresp ({cpu0_BRESP }),
.ini_bvalid ({cpu0_BVALID }),
.ini_bready ({cpu0_BREADY }),
.ini_araddr ({cpu0_ARADDR, sd_controller_dma_ARADDR }),
.ini_arvalid ({cpu0_ARVALID, sd_controller_dma_ARVALID }),
.ini_arready ({cpu0_ARREADY, sd_controller_dma_ARREADY }),
.ini_rdata ({cpu0_RDATA, sd_controller_dma_RDATA }),
.ini_rresp ({cpu0_RRESP, sd_controller_dma_RRESP }),
.ini_rvalid ({cpu0_RVALID, sd_controller_dma_RVALID }),
.ini_rready ({cpu0_RREADY, sd_controller_dma_RREADY }),
.ini_awaddr ({cpu0_AWADDR, sd_controller_dma_AWADDR }),
.ini_awready ({cpu0_AWREADY, sd_controller_dma_AWREADY }),
.ini_awvalid ({cpu0_AWVALID, sd_controller_dma_AWVALID }),
.ini_wvalid ({cpu0_WVALID, sd_controller_dma_WVALID }),
.ini_wready ({cpu0_WREADY, sd_controller_dma_WREADY }),
.ini_wdata ({cpu0_WDATA, sd_controller_dma_WDATA }),
.ini_wstrb ({cpu0_WSTRB, sd_controller_dma_WSTRB }),
.ini_bresp ({cpu0_BRESP, sd_controller_dma_BRESP }),
.ini_bvalid ({cpu0_BVALID, sd_controller_dma_BVALID }),
.ini_bready ({cpu0_BREADY, sd_controller_dma_BREADY }),
.tgt_araddr ({ram_araddr, rom_araddr, sdram_ARADDR, sd_controller_csr_ARADDR }),
.tgt_arvalid ({ram_arvalid, rom_arvalid, sdram_ARVALID, sd_controller_csr_ARVALID }),
.tgt_arready ({ram_arready, rom_arready, sdram_ARREADY, sd_controller_csr_ARREADY }),
@@ -479,6 +479,26 @@ sd_controller_top u_sd_controller (
.s_apb_prdata(sd_controller_apb_prdata),
.s_apb_pslverr(sd_controller_apb_pslverr),
.o_AWVALID (sd_controller_dma_AWVALID),
.i_AWREADY (sd_controller_dma_AWREADY),
.o_AWADDR (sd_controller_dma_AWADDR),
.o_WVALID (sd_controller_dma_WVALID),
.i_WREADY (sd_controller_dma_WREADY),
.o_WDATA (sd_controller_dma_WDATA),
.o_WSTRB (sd_controller_dma_WSTRB),
.i_BVALID (sd_controller_dma_BVALID),
.o_BREADY (sd_controller_dma_BREADY),
.i_BRESP (sd_controller_dma_BRESP),
.o_ARVALID (sd_controller_dma_ARVALID),
.i_ARREADY (sd_controller_dma_ARREADY),
.o_ARADDR (sd_controller_dma_ARADDR),
.i_RVALID (sd_controller_dma_RVALID),
.o_RREADY (sd_controller_dma_RREADY),
.i_RDATA (sd_controller_dma_RDATA),
.i_RRESP (sd_controller_dma_RRESP),
.i_sd_cmd(i_sd_cmd),
.o_sd_cmd(o_sd_cmd),
.o_sd_cmd_oe(o_sd_cmd_oe),

2
hw/super6502_fpga/src/sub/rtl-common

Submodule hw/super6502_fpga/src/sub/rtl-common updated: bdf655b77b...401042bb0f

2
hw/super6502_fpga/src/sub/sd_controller

Submodule hw/super6502_fpga/src/sub/sd_controller updated: 52665b1b89...a16ffb427c