diff --git a/hw/fpga/hvl/mm_testbench.sv b/hw/fpga/hvl/mm_testbench.sv
new file mode 100644
index 0000000..777552c
--- /dev/null
+++ b/hw/fpga/hvl/mm_testbench.sv
@@ -0,0 +1,80 @@
+module testbench();
+
+timeunit 10ns;
+
+timeprecision 1ns;
+
+logic clk_50, clk, cs;
+logic rw, MM_cs;
+logic [3:0] RS, MA;
+logic [7:0] data_in;
+logic [7:0] data_out;
+
+logic [11:0] MO;
+
+logic [11:0] _data_in;
+assign _data_in = {4'h0, data_in};
+
+logic [11:0] _data_out;
+assign data_out = _data_out[7:0];
+
+logic [15:0] cpu_addr;
+logic [23:0] mm_address;
+assign MA = cpu_addr[15:12];
+assign mm_address = {MO, cpu_addr[11:0]};
+
+memory_mapper dut(
+	.data_in(_data_in),
+	.data_out(_data_out),
+	.*
+);
+
+always #1 clk_50 = clk_50 === 1'b0;
+always #100 clk = clk === 1'b0;
+
+task write_reg(logic [3:0] addr, logic [7:0] data);
+	@(negedge clk);
+	cs <= '1;
+	RS <= addr;
+	data_in <= data;
+	rw <= '0;
+	@(posedge clk);
+	cs <= '0;
+	rw <= '1;
+	@(negedge clk);
+endtask
+
+task enable(logic [7:0] data);
+	@(negedge clk);
+	MM_cs <= '1;
+	rw <= '0;
+	data_in <= data;
+	@(posedge clk);
+	rw <= '1;
+	MM_cs <= '0;
+	@(negedge clk);
+endtask
+
+initial begin
+	cpu_addr <= 16'h0abc;
+	write_reg(4'h0, 8'hcc);
+	$display("Address: %x", mm_address);
+	assert(mm_address == 24'h000abc) else begin
+		$error("Bad address before enable!");
+	end
+
+	enable(1);
+	$display("Address: %x", mm_address);
+	assert(mm_address == 24'h0ccabc) else begin
+		$error("Bad address after enable!");
+	end
+
+	enable(0);
+	$display("Address: %x", mm_address);
+	assert(mm_address == 24'h000abc) else begin
+		$error("Bad address after enable!");
+	end
+	$finish();
+end
+
+endmodule
diff --git a/hw/fpga/simulation/modelsim/mm_testbench.do b/hw/fpga/simulation/modelsim/mm_testbench.do
new file mode 100644
index 0000000..6627a55
--- /dev/null
+++ b/hw/fpga/simulation/modelsim/mm_testbench.do
@@ -0,0 +1,17 @@
+transcript on
+if {[file exists rtl_work]} {
+	vdel -lib rtl_work -all
+}
+vlib rtl_work
+vmap work rtl_work
+
+vlog -sv -work work  {../../memory_mapper.sv}
+vlog -sv -work work  {../../hvl/mm_testbench.sv}
+
+vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L stratixv_ver -L stratixv_hssi_ver -L stratixv_pcie_hip_ver -L rtl_work -L work -voptargs="+acc"  testbench
+
+add wave -group {dut} -radix hexadecimal sim:/testbench/dut/*
+
+onfinish stop
+run -all
+