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Test interrupt priority

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This commit is contained in:
Byron Lathi
2023-11-16 18:54:25 -08:00
parent b259d7f084
commit 27066a7ace
2 changed files with 49 additions and 11 deletions
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12
hw/efinix_fpga/src/interrupt_controller.sv
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@@ -82,19 +82,19 @@ always_comb begin
if (addr == '1) begin
unique casez (cmd)
8'h0?: begin
$display("Case 0 not handled");
8'b000?????: begin
o_data = irq_val;
end
8'h1?: begin
8'b001?????: begin
w_enable_write = we;
w_byte_sel = cmd[3:0];
w_byte_sel = cmd[4:0];
o_data = w_enable_data;
end
8'h2?: begin
8'b010?????: begin
w_type_write = we;
w_byte_sel = cmd[3:0];
w_byte_sel = cmd[4:0];
o_data = w_type_data;
end