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Add skeleton of interrupt controller

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This commit is contained in:
Byron Lathi
2023-11-15 08:27:29 -08:00
parent 0fe57c6ad5
commit 2b248db94f
4 changed files with 158 additions and 6 deletions
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4
hw/efinix_fpga/simulation/Makefile
View File

@@ -9,6 +9,8 @@ TEST_PROGRAM_NAME?=loop_test
TEST_FOLDER?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)
TEST_PROGRAM?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)/$(TEST_PROGRAM_NAME).hex
STANDALONE_TB= interrupt_controller_tb mapper_code_tb
#TODO implement something like sources.list
TOP_MODULE=sim_top
@@ -29,7 +31,7 @@ sim: $(TARGET)
full_sim: $(TARGET) $(SD_IMAGE)
vvp -i $(TARGET) -fst
mapper_tb: $(SRCS) $(TBS)
$(STANDALONE_TB): $(SRCS) $(TBS)
iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INC) $(SRCS) $(TBS)
mapper_code_tb: $(SRCS) $(TBS) $(INIT_MEM)

93
hw/efinix_fpga/simulation/tbs/interrupt_controller_tb.sv Normal file
View File

@@ -0,0 +1,93 @@
`timescale 1ns/1ps
module interrupt_controller_tb();
logic r_clk_cpu;
// clk_cpu
initial begin
r_clk_cpu <= '1;
forever begin
#125 r_clk_cpu <= ~r_clk_cpu;
end
end
logic reset;
logic addr;
logic [7:0] i_data;
logic [7:0] o_data;
logic cs;
logic rwb;
logic [255:0] int_in;
logic int_out;
interrupt_controller u_interrupt_controller(
.clk(r_clk_cpu),
.reset(reset),
.i_data(i_data),
.o_data(o_data),
.addr(addr),
.cs(cs),
.rwb(rwb),
.int_in(int_in),
.int_out(int_out2)
);
/* These should be shared */
task write_reg(input logic [4:0] _addr, input logic [7:0] _data);
@(negedge r_clk_cpu);
cs <= '1;
addr <= _addr;
rwb <= '0;
i_data <= '1;
@(posedge r_clk_cpu);
i_data <= _data;
@(negedge r_clk_cpu);
cs <= '0;
rwb <= '1;
endtask
task read_reg(input logic [2:0] _addr, output logic [7:0] _data);
@(negedge r_clk_cpu);
cs <= '1;
addr <= _addr;
rwb <= '1;
i_data <= '1;
@(posedge r_clk_cpu);
_data <= o_data;
@(negedge r_clk_cpu);
cs <= '0;
rwb <= '1;
endtask
initial begin
repeat (5) @(posedge r_clk_cpu);
reset = 1;
cs = 0;
rwb = 1;
addr = '0;
i_data = '0;
int_in = '0;
repeat (5) @(posedge r_clk_cpu);
reset = 0;
repeat (5) @(posedge r_clk_cpu);
write_reg(0, 8'h10);
write_reg(1, 8'hff);
write_reg(0, 8'h20);
write_reg(1, 8'hff);
repeat (5) @(posedge r_clk_cpu);
int_in = 1;
@(posedge r_clk_cpu)
int_in = 0;
repeat (5) @(posedge r_clk_cpu);
$finish();
end
initial
begin
$dumpfile("interrupt_controller_tb.vcd");
$dumpvars(0,interrupt_controller_tb);
end
endmodule