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Add skeleton of interrupt controller

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Byron Lathi
2023-11-15 08:27:29 -08:00
parent 0fe57c6ad5
commit 2b248db94f
4 changed files with 158 additions and 6 deletions
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12
hw/efinix_fpga/src/byte_sel_register.sv
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@@ -4,6 +4,7 @@ module byte_sel_register
parameter ADDR_WIDTH = 32
)(
input i_clk,
input i_reset,
input i_write,
input [$clog2(ADDR_WIDTH)-1:0] i_byte_sel,
input [DATA_WIDTH-1:0] i_data,
@@ -14,11 +15,16 @@ module byte_sel_register
logic [DATA_WIDTH*ADDR_WIDTH-1:0] r_data;
assign o_data = r_data[DATA_WIDTH*i_byte_sel +: DATA_WIDTH];
assign o_full_data = r_data;
always_ff @(posedge i_clk) begin
r_data <= r_data;
if (i_write) begin
r_data[DATA_WIDTH*i_byte_sel +: DATA_WIDTH] <= i_data;
if (i_reset) begin
r_data <= '0;
end else begin
r_data <= r_data;
if (i_write) begin
r_data[DATA_WIDTH*i_byte_sel +: DATA_WIDTH] <= i_data;
end
end
end