From 96e014567dbf54b6a09d0ba0897fea5f02f6411c Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Mon, 4 Mar 2024 00:05:18 -0800 Subject: [PATCH 01/21] Add sd controller submodule --- .gitmodules | 3 +++ hw/super6502_fpga/src/sub/sd_controller | 1 + 2 files changed, 4 insertions(+) create mode 160000 hw/super6502_fpga/src/sub/sd_controller diff --git a/.gitmodules b/.gitmodules index 90e702c..0f542ca 100644 --- a/.gitmodules +++ b/.gitmodules @@ -10,3 +10,6 @@ [submodule "hw/super6502_fpga/src/sim/sub/verilog-6502"] path = hw/super6502_fpga/src/sim/sub/verilog-6502 url = ../verilog-6502.git +[submodule "hw/super6502_fpga/src/sub/sd_controller"] + path = hw/super6502_fpga/src/sub/sd_controller + url = ../sd_controller.git diff --git a/hw/super6502_fpga/src/sub/sd_controller b/hw/super6502_fpga/src/sub/sd_controller new file mode 160000 index 0000000..361219f --- /dev/null +++ b/hw/super6502_fpga/src/sub/sd_controller @@ -0,0 +1 @@ +Subproject commit 361219ff1a2b2f2c7dfc6c1dbeb7390c656823af From 81382925f83d781252bd0b6f32567bc4d658f131 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sun, 10 Mar 2024 10:24:50 -0700 Subject: [PATCH 02/21] Update rtl common and sd controller submodules --- hw/super6502_fpga/src/sub/rtl-common | 2 +- hw/super6502_fpga/src/sub/sd_controller | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/super6502_fpga/src/sub/rtl-common b/hw/super6502_fpga/src/sub/rtl-common index 170285d..c884b49 160000 --- a/hw/super6502_fpga/src/sub/rtl-common +++ b/hw/super6502_fpga/src/sub/rtl-common @@ -1 +1 @@ -Subproject commit 170285d7abf968dbe9cb6f3d919039bc117eef60 +Subproject commit c884b490c76c60094b461aabe664a76e25df2ca8 diff --git a/hw/super6502_fpga/src/sub/sd_controller b/hw/super6502_fpga/src/sub/sd_controller index 361219f..c7f90a3 160000 --- a/hw/super6502_fpga/src/sub/sd_controller +++ b/hw/super6502_fpga/src/sub/sd_controller @@ -1 +1 @@ -Subproject commit 361219ff1a2b2f2c7dfc6c1dbeb7390c656823af +Subproject commit c7f90a361b0121d8e983f4df084b48f7328fa137 From da41e60ee7d827dd803882d5951dbb2530d2f9a8 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sun, 10 Mar 2024 11:31:07 -0700 Subject: [PATCH 03/21] integrate sd controller and super simple tb --- Makefile | 2 +- hw/super6502_fpga/addr_map.mem | 4 +- hw/super6502_fpga/sources.list | 8 + hw/super6502_fpga/src/rtl/super_6502_fpga.sv | 145 ++++++++++++++++--- hw/super6502_fpga/src/sub/rtl-common | 2 +- sw/test_code/sd_controller_test/Makefile | 39 +++++ sw/test_code/sd_controller_test/link.ld | 30 ++++ sw/test_code/sd_controller_test/main.s | 21 +++ 8 files changed, 228 insertions(+), 23 deletions(-) create mode 100644 sw/test_code/sd_controller_test/Makefile create mode 100644 sw/test_code/sd_controller_test/link.ld create mode 100644 sw/test_code/sd_controller_test/main.s diff --git a/Makefile b/Makefile index f13bfba..8c9523e 100644 --- a/Makefile +++ b/Makefile @@ -1,4 +1,4 @@ -ROM_TARGET=test_code/loop_test +ROM_TARGET=test_code/sd_controller_test INIT_HEX=hw/super6502_fpga/init_hex.mem HEX=sw/$(ROM_TARGET)/$(notdir $(ROM_TARGET)).bin diff --git a/hw/super6502_fpga/addr_map.mem b/hw/super6502_fpga/addr_map.mem index 7a02cdc..d10710d 100644 --- a/hw/super6502_fpga/addr_map.mem +++ b/hw/super6502_fpga/addr_map.mem @@ -4,4 +4,6 @@ 0000ff00 0000ffff 00000200 -0000efff \ No newline at end of file +0000dfff +0000e000 +0000e03f \ No newline at end of file diff --git a/hw/super6502_fpga/sources.list b/hw/super6502_fpga/sources.list index b9113d1..2cf8304 100644 --- a/hw/super6502_fpga/sources.list +++ b/hw/super6502_fpga/sources.list @@ -11,4 +11,12 @@ src/sub/rtl-common/src/rtl/axi4_lite_rom.sv src/sub/rtl-common/src/rtl/ff_cdc.sv src/sub/rtl-common/src/rtl/shallow_async_fifo.sv src/sub/rtl-common/src/rtl/sync_fifo.sv +src/sub/rtl-common/src/rtl/axi4_lite_to_apb4.sv ip/sdram_controller/sdram_controller.v +src/sub/sd_controller/src/regs/sd_controller_regs_pkg.sv +src/sub/sd_controller/src/regs/sd_controller_regs.sv +src/sub/sd_controller/src/crc7.sv +src/sub/sd_controller/src/crc16.sv +src/sub/sd_controller/src/sd_command.sv +src/sub/sd_controller/src/sd_control.sv +src/sub/sd_controller/src/sd_controller_top.sv \ No newline at end of file diff --git a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv index 84cdee6..3c92268 100644 --- a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv +++ b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv @@ -35,7 +35,10 @@ module super6502_fpga( output logic o_cpu0_nmib, output logic o_cpu0_rdy, output logic o_cpu0_reset, - output logic o_clk_phi2 + output logic o_clk_phi2, + + input i_sd_cmd, + output o_sd_cmd ); @@ -141,6 +144,45 @@ logic [DATA_WIDTH-1:0] sdram_RDATA; logic [1:0] sdram_RRESP; +// These are for the control/status registers +logic sd_controller_csr_AWVALID; +logic sd_controller_csr_AWREADY; +logic [ADDR_WIDTH-1:0] sd_controller_csr_AWADDR; +logic sd_controller_csr_WVALID; +logic sd_controller_csr_WREADY; +logic [DATA_WIDTH-1:0] sd_controller_csr_WDATA; +logic [DATA_WIDTH/8-1:0] sd_controller_csr_WSTRB; +logic sd_controller_csr_BVALID; +logic sd_controller_csr_BREADY; +logic [1:0] sd_controller_csr_BRESP; +logic sd_controller_csr_ARVALID; +logic sd_controller_csr_ARREADY; +logic [ADDR_WIDTH-1:0] sd_controller_csr_ARADDR; +logic sd_controller_csr_RVALID; +logic sd_controller_csr_RREADY; +logic [DATA_WIDTH-1:0] sd_controller_csr_RDATA; +logic [1:0] sd_controller_csr_RRESP; + +// these are for the dma master. +logic sd_controller_dma_AWVALID; +logic sd_controller_dma_AWREADY; +logic [ADDR_WIDTH-1:0] sd_controller_dma_AWADDR; +logic sd_controller_dma_WVALID; +logic sd_controller_dma_WREADY; +logic [DATA_WIDTH-1:0] sd_controller_dma_WDATA; +logic [DATA_WIDTH/8-1:0] sd_controller_dma_WSTRB; +logic sd_controller_dma_BVALID; +logic sd_controller_dma_BREADY; +logic [1:0] sd_controller_dma_BRESP; +logic sd_controller_dma_ARVALID; +logic sd_controller_dma_ARREADY; +logic [ADDR_WIDTH-1:0] sd_controller_dma_ARADDR; +logic sd_controller_dma_RVALID; +logic sd_controller_dma_RREADY; +logic [DATA_WIDTH-1:0] sd_controller_dma_RDATA; +logic [1:0] sd_controller_dma_RRESP; + + cpu_wrapper u_cpu_wrapper_0( .i_clk_cpu (clk_cpu), .i_clk_100 (i_sysclk), @@ -187,7 +229,7 @@ cpu_wrapper u_cpu_wrapper_0( axi_crossbar #( .N_INITIATORS(1), - .N_TARGETS(3) + .N_TARGETS(4) ) u_crossbar ( .clk(i_sysclk), .rst(~master_reset), @@ -209,24 +251,23 @@ axi_crossbar #( .ini_bresp ({cpu0_BRESP }), .ini_bvalid ({cpu0_BVALID }), .ini_bready ({cpu0_BREADY }), - - .tgt_araddr ({ram_araddr, rom_araddr, sdram_ARADDR }), - .tgt_arvalid ({ram_arvalid, rom_arvalid, sdram_ARVALID }), - .tgt_arready ({ram_arready, rom_arready, sdram_ARREADY }), - .tgt_rdata ({ram_rdata, rom_rdata, sdram_RDATA }), - .tgt_rresp ({ram_rresp, rom_rresp, sdram_RRESP }), - .tgt_rvalid ({ram_rvalid, rom_rvalid, sdram_RVALID }), - .tgt_rready ({ram_rready, rom_rready, sdram_RREADY }), - .tgt_awaddr ({ram_awaddr, rom_awaddr, sdram_AWADDR }), - .tgt_awvalid ({ram_awvalid, rom_awvalid, sdram_AWVALID }), - .tgt_awready ({ram_awready, rom_awready, sdram_AWREADY }), - .tgt_wdata ({ram_wdata, rom_wdata, sdram_WDATA }), - .tgt_wvalid ({ram_wvalid, rom_wvalid, sdram_WVALID }), - .tgt_wready ({ram_wready, rom_wready, sdram_WREADY }), - .tgt_wstrb ({ram_wstrb, rom_wstrb, sdram_WSTRB }), - .tgt_bresp ({ram_bresp, rom_bresp, sdram_BRESP }), - .tgt_bvalid ({ram_bvalid, rom_bvalid, sdram_BVALID }), - .tgt_bready ({ram_bready, rom_bready, sdram_BREADY }) + .tgt_araddr ({ram_araddr, rom_araddr, sdram_ARADDR, sd_controller_csr_ARADDR }), + .tgt_arvalid ({ram_arvalid, rom_arvalid, sdram_ARVALID, sd_controller_csr_ARVALID }), + .tgt_arready ({ram_arready, rom_arready, sdram_ARREADY, sd_controller_csr_ARREADY }), + .tgt_rdata ({ram_rdata, rom_rdata, sdram_RDATA, sd_controller_csr_RDATA }), + .tgt_rresp ({ram_rresp, rom_rresp, sdram_RRESP, sd_controller_csr_RRESP }), + .tgt_rvalid ({ram_rvalid, rom_rvalid, sdram_RVALID, sd_controller_csr_RVALID }), + .tgt_rready ({ram_rready, rom_rready, sdram_RREADY, sd_controller_csr_RREADY }), + .tgt_awaddr ({ram_awaddr, rom_awaddr, sdram_AWADDR, sd_controller_csr_AWADDR }), + .tgt_awvalid ({ram_awvalid, rom_awvalid, sdram_AWVALID, sd_controller_csr_AWVALID }), + .tgt_awready ({ram_awready, rom_awready, sdram_AWREADY, sd_controller_csr_AWREADY }), + .tgt_wdata ({ram_wdata, rom_wdata, sdram_WDATA, sd_controller_csr_WDATA }), + .tgt_wvalid ({ram_wvalid, rom_wvalid, sdram_WVALID, sd_controller_csr_WVALID }), + .tgt_wready ({ram_wready, rom_wready, sdram_WREADY, sd_controller_csr_WREADY }), + .tgt_wstrb ({ram_wstrb, rom_wstrb, sdram_WSTRB, sd_controller_csr_WSTRB }), + .tgt_bresp ({ram_bresp, rom_bresp, sdram_BRESP, sd_controller_csr_BRESP }), + .tgt_bvalid ({ram_bvalid, rom_bvalid, sdram_BVALID, sd_controller_csr_BVALID }), + .tgt_bready ({ram_bready, rom_bready, sdram_BREADY, sd_controller_csr_BREADY }) ); @@ -368,6 +409,70 @@ sdram_controller u_sdram_controller( .o_sdr_DQM (w_sdr_DQM) ); +logic sd_controller_apb_psel; +logic sd_controller_apb_penable; +logic sd_controller_apb_pwrite; +logic [2:0] sd_controller_apb_pprot; +logic [ADDR_WIDTH-1:0] sd_controller_apb_paddr; +logic [DATA_WIDTH-1:0] sd_controller_apb_pwdata; +logic [DATA_WIDTH/8-1:0] sd_controller_apb_pstrb; +logic sd_controller_apb_pready; +logic [DATA_WIDTH-1:0] sd_controller_apb_prdata; +logic sd_controller_apb_pslverr; +axi4_lite_to_apb4 u_sd_axi_apb_converter ( + .i_clk(i_sysclk), + .i_rst(~master_reset), + + .i_AWVALID(sd_controller_csr_AWVALID), + .o_AWREADY(sd_controller_csr_AWREADY), + .i_AWADDR(sd_controller_csr_AWADDR), + .i_WVALID(sd_controller_csr_AWVALID), + .o_WREADY(sd_controller_csr_WREADY), + .i_WDATA(sd_controller_csr_WDATA), + .i_WSTRB(sd_controller_csr_WSTRB), + .o_BVALID(sd_controller_csr_BVALID), + .i_BREADY(sd_controller_csr_BREADY), + .o_BRESP(sd_controller_csr_BRESP), + .i_ARVALID(sd_controller_csr_ARVALID), + .o_ARREADY(sd_controller_csr_ARREADY), + .i_ARADDR(sd_controller_csr_ARADDR), + .i_ARPROT('0), + .o_RVALID(sd_controller_csr_RVALID), + .i_RREADY(sd_controller_csr_RREADY), + .o_RDATA(sd_controller_csr_RDATA), + .o_RRESP(sd_controller_csr_RRESP), + + .m_apb_psel(sd_controller_apb_psel), + .m_apb_penable(sd_controller_apb_penable), + .m_apb_pwrite(sd_controller_apb_pwrite), + .m_apb_pprot(sd_controller_apb_pprot), + .m_apb_paddr(sd_controller_apb_paddr), + .m_apb_pwdata(sd_controller_apb_pwdata), + .m_apb_pstrb(sd_controller_apb_pstrb), + .m_apb_pready(sd_controller_apb_pready), + .m_apb_prdata(sd_controller_apb_prdata), + .m_apb_pslverr(sd_controller_apb_pslverr) +); + +sd_controller_top u_sd_controller ( + .clk(i_sysclk), + .rst(~master_reset), + + .s_apb_psel(sd_controller_apb_psel), + .s_apb_penable(sd_controller_apb_penable), + .s_apb_pwrite(sd_controller_apb_pwrite), + .s_apb_pprot(sd_controller_apb_pprot), + .s_apb_paddr(sd_controller_apb_paddr[5:0]), + .s_apb_pwdata(sd_controller_apb_pwdata), + .s_apb_pstrb(sd_controller_apb_pstrb), + .s_apb_pready(sd_controller_apb_pready), + .s_apb_prdata(sd_controller_apb_prdata), + .s_apb_pslverr(sd_controller_apb_pslverr), + + .i_sd_cmd(i_sd_cmd), + .o_sd_cmd(o_sd_cmd) +); + endmodule \ No newline at end of file diff --git a/hw/super6502_fpga/src/sub/rtl-common b/hw/super6502_fpga/src/sub/rtl-common index c884b49..8c16b92 160000 --- a/hw/super6502_fpga/src/sub/rtl-common +++ b/hw/super6502_fpga/src/sub/rtl-common @@ -1 +1 @@ -Subproject commit c884b490c76c60094b461aabe664a76e25df2ca8 +Subproject commit 8c16b92a51558ce200156a0d2e4f2b9279f73342 diff --git a/sw/test_code/sd_controller_test/Makefile b/sw/test_code/sd_controller_test/Makefile new file mode 100644 index 0000000..ebdce77 --- /dev/null +++ b/sw/test_code/sd_controller_test/Makefile @@ -0,0 +1,39 @@ +CC=../../toolchain/cc65/bin/cl65 +LD=../../toolchain/cc65/bin/cl65 +CFLAGS=-T -t none -I. --cpu "65C02" +LDFLAGS=-C link.ld -m $(NAME).map + +NAME=sd_controller_test + +BIN=$(NAME).bin +HEX=$(NAME).hex + +LISTS=lists + +SRCS=$(wildcard *.s) $(wildcard *.c) +SRCS+=$(wildcard **/*.s) $(wildcard **/*.c) +OBJS+=$(patsubst %.s,%.o,$(filter %s,$(SRCS))) +OBJS+=$(patsubst %.c,%.o,$(filter %c,$(SRCS))) + +# Make sure the kernel linked to correct address, no relocation! +all: $(HEX) + +$(HEX): $(BIN) + objcopy --input-target=binary --output-target=verilog $(BIN) $(HEX) + +$(BIN): $(OBJS) + $(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@ + +%.o: %.c $(LISTS) + $(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@ + +%.o: %.s $(LISTS) + $(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@ + +$(LISTS): + mkdir -p $(addprefix $(LISTS)/,$(sort $(dir $(SRCS)))) + +.PHONY: clean +clean: + rm -rf $(OBJS) $(BIN) $(HEX) $(LISTS) $(NAME).map + diff --git a/sw/test_code/sd_controller_test/link.ld b/sw/test_code/sd_controller_test/link.ld new file mode 100644 index 0000000..44fc445 --- /dev/null +++ b/sw/test_code/sd_controller_test/link.ld @@ -0,0 +1,30 @@ +MEMORY +{ + RAM: start = $0000, size = $200; + ROM: start = $FF00, size = $100, file = %O; +} + +SEGMENTS { + ZEROPAGE: load = RAM, type = zp, define = yes; + DATA: load = ROM, type = rw, define = yes; + CODE: load = ROM, type = ro; + RODATA: load = ROM, type = ro; + VECTORS: load = ROM, type = ro, start = $FFFA; +} + +FEATURES { + CONDES: segment = STARTUP, + type = constructor, + label = __CONSTRUCTOR_TABLE__, + count = __CONSTRUCTOR_COUNT__; + CONDES: segment = STARTUP, + type = destructor, + label = __DESTRUCTOR_TABLE__, + count = __DESTRUCTOR_COUNT__; +} + +SYMBOLS { + # Define the stack size for the application + __STACKSIZE__: value = $0200, type = weak; + __STACKSTART__: type = weak, value = $0800; # 2k stack +} diff --git a/sw/test_code/sd_controller_test/main.s b/sw/test_code/sd_controller_test/main.s new file mode 100644 index 0000000..ac93719 --- /dev/null +++ b/sw/test_code/sd_controller_test/main.s @@ -0,0 +1,21 @@ +.export _init, _nmi_int, _irq_int + +.segment "VECTORS" + +.addr _nmi_int ; NMI vector +.addr _init ; Reset vector +.addr _irq_int ; IRQ/BRK vector + +SD_CONTROLLER = $e000 +CLK_DIV = $20 + +.code + +_nmi_int: +_irq_int: + +_init: + lda #$08 + sta SD_CONTROLLER + +@end: bra @end \ No newline at end of file From cb426670cd2462b2c5649a10a5dbd25c5641f8aa Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sun, 10 Mar 2024 12:29:08 -0700 Subject: [PATCH 04/21] Do synthesis with sd controller --- hw/super6502_fpga/src/sub/rtl-common | 2 +- hw/super6502_fpga/src/sub/sd_controller | 2 +- hw/super6502_fpga/super6502_fpga.xml | 160 +++++++++++++----------- 3 files changed, 89 insertions(+), 75 deletions(-) diff --git a/hw/super6502_fpga/src/sub/rtl-common b/hw/super6502_fpga/src/sub/rtl-common index 8c16b92..a780aab 160000 --- a/hw/super6502_fpga/src/sub/rtl-common +++ b/hw/super6502_fpga/src/sub/rtl-common @@ -1 +1 @@ -Subproject commit 8c16b92a51558ce200156a0d2e4f2b9279f73342 +Subproject commit a780aab98b217c6d4750a6b7278902e8a7d070e2 diff --git a/hw/super6502_fpga/src/sub/sd_controller b/hw/super6502_fpga/src/sub/sd_controller index c7f90a3..cb68857 160000 --- a/hw/super6502_fpga/src/sub/sd_controller +++ b/hw/super6502_fpga/src/sub/sd_controller @@ -1 +1 @@ -Subproject commit c7f90a361b0121d8e983f4df084b48f7328fa137 +Subproject commit cb68857a7c40822c412f287729972755246f3283 diff --git a/hw/super6502_fpga/super6502_fpga.xml b/hw/super6502_fpga/super6502_fpga.xml index 1dcda00..f683a03 100644 --- a/hw/super6502_fpga/super6502_fpga.xml +++ b/hw/super6502_fpga/super6502_fpga.xml @@ -1,89 +1,103 @@ - + + - - - + + + - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + - - + + - - + + - + - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - + + + + + + + - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + - \ No newline at end of file + + + + + + From 8f6d0742552f8d8ca0900cf1eaf9ff63b59ce428 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sun, 10 Mar 2024 12:55:38 -0700 Subject: [PATCH 05/21] Re-order init script to fix python import issue in synthesis --- init_env.sh | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/init_env.sh b/init_env.sh index 5832a54..5cda461 100644 --- a/init_env.sh +++ b/init_env.sh @@ -8,14 +8,14 @@ export KICAD7_SYMBOL_DIR=$REPO_TOP/hw/kicad_library/symbols export KICAD7_3DMODEL_DIR=$REPO_TOP/hw/kicad_library/3dmodels export KICAD7_FOOTPRINT_DIR=$REPO_TOP/hw/kicad_library/footprints + +python3 -m venv .user_venv +. .user_venv/bin/activate + if [ -n "$EFX_SETUP" ]; then source $EFX_SETUP else echo "EFX_SETUP not defined!" fi - -python3 -m venv .user_venv -. .user_venv/bin/activate - # pip install -r requirements.txt From d3914b3a51474e410082a46a17ae566e666af0b8 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sun, 10 Mar 2024 16:09:12 -0700 Subject: [PATCH 06/21] Add sd io pins --- hw/super6502_fpga/src/rtl/super_6502_fpga.sv | 14 +- hw/super6502_fpga/src/sim/hvl/sim_top.sv | 27 ++- hw/super6502_fpga/src/sub/sd_controller | 2 +- hw/super6502_fpga/super6502_fpga.peri.xml | 17 +- hw/super6502_fpga/super6502_fpga.xml | 169 +++++++++---------- 5 files changed, 138 insertions(+), 91 deletions(-) diff --git a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv index 3c92268..8fa4b8d 100644 --- a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv +++ b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv @@ -38,7 +38,13 @@ module super6502_fpga( output logic o_clk_phi2, input i_sd_cmd, - output o_sd_cmd + output o_sd_cmd, + output o_sd_cmd_oe, + input i_sd_dat, + output o_sd_dat, + output o_sd_dat_oe, + output o_sd_clk, + output o_sd_cs ); @@ -69,6 +75,8 @@ assign sdram_ready = |w_sdr_state; assign master_reset = pre_reset & sdram_ready; +assign o_sd_cs = '1; + logic cpu0_AWVALID; logic cpu0_AWREADY; @@ -472,7 +480,9 @@ sd_controller_top u_sd_controller ( .s_apb_pslverr(sd_controller_apb_pslverr), .i_sd_cmd(i_sd_cmd), - .o_sd_cmd(o_sd_cmd) + .o_sd_cmd(o_sd_cmd), + .o_sd_cmd_oe(o_sd_cmd_oe), + .o_sd_clk(o_sd_clk) ); endmodule \ No newline at end of file diff --git a/hw/super6502_fpga/src/sim/hvl/sim_top.sv b/hw/super6502_fpga/src/sim/hvl/sim_top.sv index c4c29c8..94a10bb 100644 --- a/hw/super6502_fpga/src/sim/hvl/sim_top.sv +++ b/hw/super6502_fpga/src/sim/hvl/sim_top.sv @@ -59,9 +59,10 @@ logic w_cpu0_rdy; logic w_cpu0_irqb; logic w_cpu0_we; logic w_cpu0_sync; +logic w_clk_phi2; cpu_65c02 u_cpu0 ( - .phi2 (clk_cpu), + .phi2 (w_clk_phi2), .reset (~w_cpu0_reset), .AB (w_cpu0_addr), .RDY (w_cpu0_rdy), @@ -111,6 +112,18 @@ generate end endgenerate + +// potential sd card sim here? + +logic i_sd_cmd; +logic o_sd_cmd; +logic o_sd_cmd_oe; +logic i_sd_dat; +logic o_sd_dat; +logic i_sd_dat_oe; +logic o_sd_clk; +logic o_sd_cs; + super6502_fpga u_dut ( .i_sysclk (clk_100), .i_sdrclk (clk_200), @@ -127,6 +140,7 @@ super6502_fpga u_dut ( .o_cpu0_irqb (w_cpu0_irqb), .i_cpu0_rwb (~w_cpu0_we), .i_cpu0_sync (w_cpu0_sync), + .o_clk_phi2 (w_clk_phi2), .o_sdr_CKE (w_sdr_CKE), .o_sdr_n_CS (w_sdr_n_CS), @@ -138,7 +152,16 @@ super6502_fpga u_dut ( .i_sdr_DATA (w_sdr_DQ), .o_sdr_DATA (w_sdr_DATA), .o_sdr_DATA_oe (w_sdr_DATA_oe), - .o_sdr_DQM (w_sdr_DQM) + .o_sdr_DQM (w_sdr_DQM), + + .i_sd_cmd (i_sd_cmd), + .o_sd_cmd (o_sd_cmd), + .o_sd_cmd_oe (o_sd_cmd_oe), + .i_sd_dat (i_sd_dat), + .o_sd_dat (o_sd_dat), + .o_sd_dat_oe (o_sd_dat_oe), + .o_sd_clk (o_sd_clk), + .o_sd_cs (o_sd_cs) ); diff --git a/hw/super6502_fpga/src/sub/sd_controller b/hw/super6502_fpga/src/sub/sd_controller index cb68857..fc2813b 160000 --- a/hw/super6502_fpga/src/sub/sd_controller +++ b/hw/super6502_fpga/src/sub/sd_controller @@ -1 +1 @@ -Subproject commit cb68857a7c40822c412f287729972755246f3283 +Subproject commit fc2813b809e2fd25e0ce55e73aad9ce05cb603fb diff --git a/hw/super6502_fpga/super6502_fpga.peri.xml b/hw/super6502_fpga/super6502_fpga.peri.xml index 2141ac8..b9051f9 100644 --- a/hw/super6502_fpga/super6502_fpga.peri.xml +++ b/hw/super6502_fpga/super6502_fpga.peri.xml @@ -282,7 +282,22 @@ - + + + + + + + + + + + + + + + + diff --git a/hw/super6502_fpga/super6502_fpga.xml b/hw/super6502_fpga/super6502_fpga.xml index f683a03..0b88aab 100644 --- a/hw/super6502_fpga/super6502_fpga.xml +++ b/hw/super6502_fpga/super6502_fpga.xml @@ -1,103 +1,102 @@ - - + - - - + + + - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + - - + + - - + + - + - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - + + + + + + + - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + - - - + + + - + \ No newline at end of file From 142759ff5993ac80d56fc9455285a38cc42560fe Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sun, 10 Mar 2024 16:42:21 -0700 Subject: [PATCH 07/21] Require python3.11 --- init_env.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/init_env.sh b/init_env.sh index 5cda461..0bac1ed 100644 --- a/init_env.sh +++ b/init_env.sh @@ -9,7 +9,7 @@ export KICAD7_3DMODEL_DIR=$REPO_TOP/hw/kicad_library/3dmodels export KICAD7_FOOTPRINT_DIR=$REPO_TOP/hw/kicad_library/footprints -python3 -m venv .user_venv +python3.11 -m venv .user_venv . .user_venv/bin/activate if [ -n "$EFX_SETUP" ]; then From 3c0bf9740c43498c3c92c73738635b3ec085a5e5 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sun, 10 Mar 2024 21:56:48 -0700 Subject: [PATCH 08/21] Delete init hex on clean --- hw/super6502_fpga/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/super6502_fpga/Makefile b/hw/super6502_fpga/Makefile index 8b16685..d6fcf1b 100644 --- a/hw/super6502_fpga/Makefile +++ b/hw/super6502_fpga/Makefile @@ -12,4 +12,5 @@ $(SUPER6502_FPGA_BITSTREAM): $(SUPER6502_FPGA_SOURCES) $(SUPER6502_FPGA_PROJECT) .PHONY: clean clean: rm -rf work_* - rm -rf outflow \ No newline at end of file + rm -rf outflow + rm -rf init_hex.mem \ No newline at end of file From 61f6e53327802db2981b363f4ad08aabd8045b6a Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sun, 10 Mar 2024 21:57:22 -0700 Subject: [PATCH 09/21] Updates based on fpga test 1. in SD mode, CMD0 does not have a response, so we specifically ignore it. 2. The penable signal was messed up, although it looks like this doesn't matter anyway 3. The SD clock should be out of phase from the data signal by 180 degrees, so that we get max hold time --- hw/super6502_fpga/src/sub/rtl-common | 2 +- hw/super6502_fpga/src/sub/sd_controller | 2 +- sw/test_code/sd_controller_test/main.s | 11 +++++++++++ 3 files changed, 13 insertions(+), 2 deletions(-) diff --git a/hw/super6502_fpga/src/sub/rtl-common b/hw/super6502_fpga/src/sub/rtl-common index a780aab..bb214bc 160000 --- a/hw/super6502_fpga/src/sub/rtl-common +++ b/hw/super6502_fpga/src/sub/rtl-common @@ -1 +1 @@ -Subproject commit a780aab98b217c6d4750a6b7278902e8a7d070e2 +Subproject commit bb214bc79ee665325adb423472a13dbeec4431ed diff --git a/hw/super6502_fpga/src/sub/sd_controller b/hw/super6502_fpga/src/sub/sd_controller index fc2813b..091984c 160000 --- a/hw/super6502_fpga/src/sub/sd_controller +++ b/hw/super6502_fpga/src/sub/sd_controller @@ -1 +1 @@ -Subproject commit fc2813b809e2fd25e0ce55e73aad9ce05cb603fb +Subproject commit 091984c3342f13cfbf50c63f1fead7febc49158e diff --git a/sw/test_code/sd_controller_test/main.s b/sw/test_code/sd_controller_test/main.s index ac93719..b497f15 100644 --- a/sw/test_code/sd_controller_test/main.s +++ b/sw/test_code/sd_controller_test/main.s @@ -7,6 +7,7 @@ .addr _irq_int ; IRQ/BRK vector SD_CONTROLLER = $e000 +SD_ARG = SD_CONTROLLER + $4 CLK_DIV = $20 .code @@ -15,6 +16,16 @@ _nmi_int: _irq_int: _init: + lda #$00 + sta SD_CONTROLLER + + lda #$aa + sta SD_ARG + lda #$01 + sta SD_ARG+1 + lda #$00 + sta SD_ARG+2 + sta SD_ARG+3 lda #$08 sta SD_CONTROLLER From f7580f719f71c7176aee45f282e00cf3e4b81cd4 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sun, 10 Mar 2024 22:25:29 -0700 Subject: [PATCH 10/21] Add program target to makefiles --- Makefile | 3 +++ hw/super6502_fpga/Makefile | 5 ++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 8c9523e..a56ae02 100644 --- a/Makefile +++ b/Makefile @@ -14,6 +14,9 @@ fpga_image: $(INIT_HEX) sim: $(INIT_HEX) $(MAKE) -C hw/super6502_fpga/src/sim +pgm: + $(MAKE) -C hw/super6502_fpga pgm + waves: sim gtkwave hw/super6502_fpga/src/sim/sim_top.vcd diff --git a/hw/super6502_fpga/Makefile b/hw/super6502_fpga/Makefile index d6fcf1b..bf0d84c 100644 --- a/hw/super6502_fpga/Makefile +++ b/hw/super6502_fpga/Makefile @@ -9,8 +9,11 @@ all: $(SUPER6502_FPGA_BITSTREAM) $(SUPER6502_FPGA_BITSTREAM): $(SUPER6502_FPGA_SOURCES) $(SUPER6502_FPGA_PROJECT) efx_run.py $(SUPER6502_FPGA_PROJECT) +pgm: + efx_run.py $(SUPER6502_FPGA_PROJECT) --flow program --pgm_opts mode=jtag + .PHONY: clean clean: rm -rf work_* rm -rf outflow - rm -rf init_hex.mem \ No newline at end of file + rm -rf init_hex.mem From 455814ec14b0e4f06601891578bedd5e828c2829 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Tue, 12 Mar 2024 18:20:51 -0700 Subject: [PATCH 11/21] Update sd controller and test code --- Makefile | 6 +- hw/super6502_fpga/src/sub/sd_controller | 2 +- sw/test_code/sd_controller_test/main.s | 106 ++++++++++++++++++++++++ 3 files changed, 110 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index a56ae02..96f4ed7 100644 --- a/Makefile +++ b/Makefile @@ -3,6 +3,7 @@ ROM_TARGET=test_code/sd_controller_test INIT_HEX=hw/super6502_fpga/init_hex.mem HEX=sw/$(ROM_TARGET)/$(notdir $(ROM_TARGET)).bin +CC65=sw/toolchain/cc65/bin all: fpga_image @@ -21,11 +22,10 @@ waves: sim gtkwave hw/super6502_fpga/src/sim/sim_top.vcd # SW -.PHONY: toolchain -toolchain: +$(CC65): $(MAKE) -C sw/toolchain/cc65 -j $(shell nproc) -$(INIT_HEX): toolchain script/generate_rom_image.py $(HEX) +$(INIT_HEX): $(CC65) script/generate_rom_image.py $(HEX) python script/generate_rom_image.py -i $(HEX) -o $@ $(HEX): diff --git a/hw/super6502_fpga/src/sub/sd_controller b/hw/super6502_fpga/src/sub/sd_controller index 091984c..91168dc 160000 --- a/hw/super6502_fpga/src/sub/sd_controller +++ b/hw/super6502_fpga/src/sub/sd_controller @@ -1 +1 @@ -Subproject commit 091984c3342f13cfbf50c63f1fead7febc49158e +Subproject commit 91168dcccad424c51217d3679111e51be1127e46 diff --git a/sw/test_code/sd_controller_test/main.s b/sw/test_code/sd_controller_test/main.s index b497f15..7b26964 100644 --- a/sw/test_code/sd_controller_test/main.s +++ b/sw/test_code/sd_controller_test/main.s @@ -8,8 +8,12 @@ SD_CONTROLLER = $e000 SD_ARG = SD_CONTROLLER + $4 +SD_RESP = SD_CONTROLLER + $10 CLK_DIV = $20 +.zeropage +rca: .res 4 + .code _nmi_int: @@ -28,5 +32,107 @@ _init: sta SD_ARG+3 lda #$08 sta SD_CONTROLLER + nop + nop + nop + + lda #55 + sta SD_CONTROLLER + lda #41 + sta SD_CONTROLLER + nop + nop + nop + +@acmd41: + lda #55 + sta SD_CONTROLLER + lda #$80 + sta SD_ARG+1 + lda #$ff + sta SD_ARG+2 + lda #$40 + sta SD_ARG+3 + lda #41 + sta SD_CONTROLLER + + nop + nop + nop + nop + nop + + lda SD_RESP+3 + bmi card_ready + + + ldx #$10 +@loop: dex + bne @loop + + bra @acmd41 + +card_ready: + lda #2 + sta SD_CONTROLLER + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + + lda #3 + sta SD_CONTROLLER + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + + lda SD_RESP + sta rca + lda SD_RESP+1 + sta rca+1 + lda SD_RESP+2 + sta rca+2 + lda SD_RESP+3 + sta rca+3 + + lda rca + sta SD_ARG + lda rca+1 + sta SD_ARG+1 + lda rca+2 + sta SD_ARG+2 + lda rca+3 + sta SD_ARG+3 + lda #7 + sta SD_CONTROLLER + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + + lda #17 + sta SD_CONTROLLER @end: bra @end \ No newline at end of file From 02097ff3b8b612d95bf3786c34237d5d6bbfeae3 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Tue, 12 Mar 2024 20:23:41 -0700 Subject: [PATCH 12/21] Update sd controller with data host --- hw/super6502_fpga/src/rtl/super_6502_fpga.sv | 6 +- hw/super6502_fpga/src/sub/sd_controller | 2 +- hw/super6502_fpga/super6502_fpga.xml | 171 ++++++++++--------- 3 files changed, 93 insertions(+), 86 deletions(-) diff --git a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv index 8fa4b8d..93ed8e4 100644 --- a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv +++ b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv @@ -482,7 +482,11 @@ sd_controller_top u_sd_controller ( .i_sd_cmd(i_sd_cmd), .o_sd_cmd(o_sd_cmd), .o_sd_cmd_oe(o_sd_cmd_oe), - .o_sd_clk(o_sd_clk) + .o_sd_clk(o_sd_clk), + + .i_sd_dat(i_sd_dat), + .o_sd_dat(o_sd_dat), + .o_sd_dat_oe(o_sd_dat_oe) ); endmodule \ No newline at end of file diff --git a/hw/super6502_fpga/src/sub/sd_controller b/hw/super6502_fpga/src/sub/sd_controller index 91168dc..b4212ba 160000 --- a/hw/super6502_fpga/src/sub/sd_controller +++ b/hw/super6502_fpga/src/sub/sd_controller @@ -1 +1 @@ -Subproject commit 91168dcccad424c51217d3679111e51be1127e46 +Subproject commit b4212ba107ea3b251918ba356c339a64897ae085 diff --git a/hw/super6502_fpga/super6502_fpga.xml b/hw/super6502_fpga/super6502_fpga.xml index 0b88aab..88d787d 100644 --- a/hw/super6502_fpga/super6502_fpga.xml +++ b/hw/super6502_fpga/super6502_fpga.xml @@ -1,102 +1,105 @@ - + + - - - + + + - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + - - + + - - + + - + - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - + + + + + + + - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + - - - + + + - \ No newline at end of file + From 14cf303c9f1e381cdfcbd86b54010d7673cd9e15 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Tue, 12 Mar 2024 21:51:55 -0700 Subject: [PATCH 13/21] Update sd controller for sim --- hw/super6502_fpga/sources.list | 3 ++- hw/super6502_fpga/src/sub/sd_controller | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/super6502_fpga/sources.list b/hw/super6502_fpga/sources.list index 2cf8304..7c75831 100644 --- a/hw/super6502_fpga/sources.list +++ b/hw/super6502_fpga/sources.list @@ -19,4 +19,5 @@ src/sub/sd_controller/src/crc7.sv src/sub/sd_controller/src/crc16.sv src/sub/sd_controller/src/sd_command.sv src/sub/sd_controller/src/sd_control.sv -src/sub/sd_controller/src/sd_controller_top.sv \ No newline at end of file +src/sub/sd_controller/src/sd_controller_top.sv +src/sub/sd_controller/src/sd_data.sv \ No newline at end of file diff --git a/hw/super6502_fpga/src/sub/sd_controller b/hw/super6502_fpga/src/sub/sd_controller index b4212ba..52665b1 160000 --- a/hw/super6502_fpga/src/sub/sd_controller +++ b/hw/super6502_fpga/src/sub/sd_controller @@ -1 +1 @@ -Subproject commit b4212ba107ea3b251918ba356c339a64897ae085 +Subproject commit 52665b1b897ef77b79caf687c9dbfda4f62110a5 From 262c4cfd8311c138c33f8082ef1da6295f585059 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Tue, 12 Mar 2024 22:14:02 -0700 Subject: [PATCH 14/21] Add sd emulator (need to add sd mode) --- .gitmodules | 3 +++ hw/super6502_fpga/src/sim/sub/verilog-sd-emulator | 1 + 2 files changed, 4 insertions(+) create mode 160000 hw/super6502_fpga/src/sim/sub/verilog-sd-emulator diff --git a/.gitmodules b/.gitmodules index 0f542ca..4ac190d 100644 --- a/.gitmodules +++ b/.gitmodules @@ -13,3 +13,6 @@ [submodule "hw/super6502_fpga/src/sub/sd_controller"] path = hw/super6502_fpga/src/sub/sd_controller url = ../sd_controller.git +[submodule "hw/super6502_fpga/src/sim/sub/verilog-sd-emulator"] + path = hw/super6502_fpga/src/sim/sub/verilog-sd-emulator + url = ../verilog-sd-emulator.git diff --git a/hw/super6502_fpga/src/sim/sub/verilog-sd-emulator b/hw/super6502_fpga/src/sim/sub/verilog-sd-emulator new file mode 160000 index 0000000..72a7868 --- /dev/null +++ b/hw/super6502_fpga/src/sim/sub/verilog-sd-emulator @@ -0,0 +1 @@ +Subproject commit 72a7868fa926a8bdc612dddbcd1921aa75abe7c6 From 24a7001aee9560a82e0ab97db722f0660e594b49 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Wed, 13 Mar 2024 00:01:39 -0700 Subject: [PATCH 15/21] Add sd mode sd card emulator --- hw/super6502_fpga/src/sim/hvl/sim_top.sv | 6 ++++++ hw/super6502_fpga/src/sim/sources.list | 4 +++- hw/super6502_fpga/src/sim/sub/verilog-sd-emulator | 2 +- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/hw/super6502_fpga/src/sim/hvl/sim_top.sv b/hw/super6502_fpga/src/sim/hvl/sim_top.sv index 94a10bb..1eca534 100644 --- a/hw/super6502_fpga/src/sim/hvl/sim_top.sv +++ b/hw/super6502_fpga/src/sim/hvl/sim_top.sv @@ -162,7 +162,13 @@ super6502_fpga u_dut ( .o_sd_dat_oe (o_sd_dat_oe), .o_sd_clk (o_sd_clk), .o_sd_cs (o_sd_cs) +); +sd_card_emu u_sd_card_emu( + .clk(o_sd_clk), + .rst(~button_reset), + .i_cmd(o_sd_cmd), + .o_cmd(i_sd_cmd) ); initial begin diff --git a/hw/super6502_fpga/src/sim/sources.list b/hw/super6502_fpga/src/sim/sources.list index fd86d41..916dd74 100644 --- a/hw/super6502_fpga/src/sim/sources.list +++ b/hw/super6502_fpga/src/sim/sources.list @@ -1,4 +1,6 @@ hvl/sim_top.sv sub/verilog-6502/ALU.v sub/verilog-6502/cpu_65c02.v -sub/sim_sdram/generic_sdr.v \ No newline at end of file +sub/sim_sdram/generic_sdr.v +sub/verilog-sd-emulator/src/sd_card_command.sv +sub/verilog-sd-emulator/src/sd_card_emu.sv \ No newline at end of file diff --git a/hw/super6502_fpga/src/sim/sub/verilog-sd-emulator b/hw/super6502_fpga/src/sim/sub/verilog-sd-emulator index 72a7868..35c74ed 160000 --- a/hw/super6502_fpga/src/sim/sub/verilog-sd-emulator +++ b/hw/super6502_fpga/src/sim/sub/verilog-sd-emulator @@ -1 +1 @@ -Subproject commit 72a7868fa926a8bdc612dddbcd1921aa75abe7c6 +Subproject commit 35c74ed8d78d9378dcf6634507ce958064b4c8e2 From 335f877d66704064278c86366064486da0623677 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Thu, 14 Mar 2024 08:17:05 -0700 Subject: [PATCH 16/21] Run simulation with verilog sd emulator This also slowed the cpu clock down, we should speed it up again --- hw/super6502_fpga/src/sim/hvl/sim_top.sv | 2 +- hw/super6502_fpga/src/sim/sources.list | 3 +- .../src/sim/sub/verilog-sd-emulator | 2 +- .../src/sub/cpu_wrapper/cpu_wrapper.sv | 2 +- hw/super6502_fpga/src/sub/rtl-common | 2 +- sw/test_code/sd_controller_test/main.s | 66 +++++++------------ 6 files changed, 30 insertions(+), 47 deletions(-) diff --git a/hw/super6502_fpga/src/sim/hvl/sim_top.sv b/hw/super6502_fpga/src/sim/hvl/sim_top.sv index 1eca534..e5da831 100644 --- a/hw/super6502_fpga/src/sim/hvl/sim_top.sv +++ b/hw/super6502_fpga/src/sim/hvl/sim_top.sv @@ -39,7 +39,7 @@ initial begin clk_cpu <= '1; forever begin // #62.5 clk_cpu <= ~clk_cpu; - #250 clk_cpu <= ~clk_cpu; + #500 clk_cpu <= ~clk_cpu; end end diff --git a/hw/super6502_fpga/src/sim/sources.list b/hw/super6502_fpga/src/sim/sources.list index 916dd74..ecb3cfb 100644 --- a/hw/super6502_fpga/src/sim/sources.list +++ b/hw/super6502_fpga/src/sim/sources.list @@ -3,4 +3,5 @@ sub/verilog-6502/ALU.v sub/verilog-6502/cpu_65c02.v sub/sim_sdram/generic_sdr.v sub/verilog-sd-emulator/src/sd_card_command.sv -sub/verilog-sd-emulator/src/sd_card_emu.sv \ No newline at end of file +sub/verilog-sd-emulator/src/sd_card_emu.sv +sub/verilog-sd-emulator/src/sd_card_state_controller.sv \ No newline at end of file diff --git a/hw/super6502_fpga/src/sim/sub/verilog-sd-emulator b/hw/super6502_fpga/src/sim/sub/verilog-sd-emulator index 35c74ed..5413066 160000 --- a/hw/super6502_fpga/src/sim/sub/verilog-sd-emulator +++ b/hw/super6502_fpga/src/sim/sub/verilog-sd-emulator @@ -1 +1 @@ -Subproject commit 35c74ed8d78d9378dcf6634507ce958064b4c8e2 +Subproject commit 5413066bbbcba0ddaf8428898f35efb516f7673e diff --git a/hw/super6502_fpga/src/sub/cpu_wrapper/cpu_wrapper.sv b/hw/super6502_fpga/src/sub/cpu_wrapper/cpu_wrapper.sv index b0a20fd..51958e5 100644 --- a/hw/super6502_fpga/src/sub/cpu_wrapper/cpu_wrapper.sv +++ b/hw/super6502_fpga/src/sub/cpu_wrapper/cpu_wrapper.sv @@ -207,7 +207,7 @@ always @(posedge i_clk_100 or posedge i_rst) begin end end -localparam MAX_DELAY = 4; +localparam MAX_DELAY = 8; logic [7:0] cycle_counter; logic too_late; diff --git a/hw/super6502_fpga/src/sub/rtl-common b/hw/super6502_fpga/src/sub/rtl-common index bb214bc..28da839 160000 --- a/hw/super6502_fpga/src/sub/rtl-common +++ b/hw/super6502_fpga/src/sub/rtl-common @@ -1 +1 @@ -Subproject commit bb214bc79ee665325adb423472a13dbeec4431ed +Subproject commit 28da839bf6ef4c642f23678143bb8607e93407df diff --git a/sw/test_code/sd_controller_test/main.s b/sw/test_code/sd_controller_test/main.s index 7b26964..786df0c 100644 --- a/sw/test_code/sd_controller_test/main.s +++ b/sw/test_code/sd_controller_test/main.s @@ -20,6 +20,9 @@ _nmi_int: _irq_int: _init: + ldx #$ff + txs + lda #$00 sta SD_CONTROLLER @@ -32,21 +35,21 @@ _init: sta SD_ARG+3 lda #$08 sta SD_CONTROLLER - nop - nop - nop + jsr delay lda #55 sta SD_CONTROLLER + jsr delay lda #41 sta SD_CONTROLLER - nop - nop - nop + jsr delay @acmd41: lda #55 sta SD_CONTROLLER + + jsr delay + lda #$80 sta SD_ARG+1 lda #$ff @@ -56,11 +59,7 @@ _init: lda #41 sta SD_CONTROLLER - nop - nop - nop - nop - nop + jsr delay lda SD_RESP+3 bmi card_ready @@ -76,30 +75,12 @@ card_ready: lda #2 sta SD_CONTROLLER - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop + jsr delay lda #3 sta SD_CONTROLLER - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop + jsr delay lda SD_RESP sta rca @@ -121,18 +102,19 @@ card_ready: lda #7 sta SD_CONTROLLER - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop + jsr delay lda #17 sta SD_CONTROLLER -@end: bra @end \ No newline at end of file +@end: bra @end + +delay: + nop + nop + nop + nop + nop + nop + nop + rts \ No newline at end of file From 4028c2a36e889f7d62dca9f0914862c54c49b837 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Thu, 14 Mar 2024 17:14:38 -0700 Subject: [PATCH 17/21] Update rtl common since I commited to the wrong branch --- hw/super6502_fpga/src/sub/rtl-common | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/super6502_fpga/src/sub/rtl-common b/hw/super6502_fpga/src/sub/rtl-common index 28da839..d3fbb06 160000 --- a/hw/super6502_fpga/src/sub/rtl-common +++ b/hw/super6502_fpga/src/sub/rtl-common @@ -1 +1 @@ -Subproject commit 28da839bf6ef4c642f23678143bb8607e93407df +Subproject commit d3fbb06ee05abae119ceb39ed9a058f214ca06ad From 0f9e470d134436479274eaccfd61580bbd4e9b25 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Thu, 14 Mar 2024 19:20:08 -0700 Subject: [PATCH 18/21] Update rtl common since I commited to the wrong branch (again) --- hw/super6502_fpga/src/sub/rtl-common | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/super6502_fpga/src/sub/rtl-common b/hw/super6502_fpga/src/sub/rtl-common index d3fbb06..1417722 160000 --- a/hw/super6502_fpga/src/sub/rtl-common +++ b/hw/super6502_fpga/src/sub/rtl-common @@ -1 +1 @@ -Subproject commit d3fbb06ee05abae119ceb39ed9a058f214ca06ad +Subproject commit 14177224f6726b67ff5743a3ae54d190be607826 From eb5c3b0b02f04a7cee6f6463a36ea42841a2e62f Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Thu, 14 Mar 2024 19:34:04 -0700 Subject: [PATCH 19/21] Update verilog sd to get up to cmd7 --- hw/super6502_fpga/src/sim/sub/verilog-sd-emulator | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/super6502_fpga/src/sim/sub/verilog-sd-emulator b/hw/super6502_fpga/src/sim/sub/verilog-sd-emulator index 5413066..c64eff4 160000 --- a/hw/super6502_fpga/src/sim/sub/verilog-sd-emulator +++ b/hw/super6502_fpga/src/sim/sub/verilog-sd-emulator @@ -1 +1 @@ -Subproject commit 5413066bbbcba0ddaf8428898f35efb516f7673e +Subproject commit c64eff4f3658ed1545c6f6942979c83c4c42493b From 9b50dab855bc4e265c91003cb57f51bc1c551f8e Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Fri, 15 Mar 2024 21:02:53 -0700 Subject: [PATCH 20/21] Update submodules, update sources --- hw/super6502_fpga/src/sim/hvl/sim_top.sv | 4 +++- hw/super6502_fpga/src/sim/sources.list | 3 ++- hw/super6502_fpga/src/sim/sub/verilog-sd-emulator | 2 +- hw/super6502_fpga/src/sub/rtl-common | 2 +- 4 files changed, 7 insertions(+), 4 deletions(-) diff --git a/hw/super6502_fpga/src/sim/hvl/sim_top.sv b/hw/super6502_fpga/src/sim/hvl/sim_top.sv index e5da831..c8ba47e 100644 --- a/hw/super6502_fpga/src/sim/hvl/sim_top.sv +++ b/hw/super6502_fpga/src/sim/hvl/sim_top.sv @@ -168,7 +168,9 @@ sd_card_emu u_sd_card_emu( .clk(o_sd_clk), .rst(~button_reset), .i_cmd(o_sd_cmd), - .o_cmd(i_sd_cmd) + .o_cmd(i_sd_cmd), + .i_dat(o_sd_dat), + .o_dat(i_sd_dat) ); initial begin diff --git a/hw/super6502_fpga/src/sim/sources.list b/hw/super6502_fpga/src/sim/sources.list index ecb3cfb..76909da 100644 --- a/hw/super6502_fpga/src/sim/sources.list +++ b/hw/super6502_fpga/src/sim/sources.list @@ -4,4 +4,5 @@ sub/verilog-6502/cpu_65c02.v sub/sim_sdram/generic_sdr.v sub/verilog-sd-emulator/src/sd_card_command.sv sub/verilog-sd-emulator/src/sd_card_emu.sv -sub/verilog-sd-emulator/src/sd_card_state_controller.sv \ No newline at end of file +sub/verilog-sd-emulator/src/sd_card_state_controller.sv +sub/verilog-sd-emulator/src/sd_card_data.sv \ No newline at end of file diff --git a/hw/super6502_fpga/src/sim/sub/verilog-sd-emulator b/hw/super6502_fpga/src/sim/sub/verilog-sd-emulator index c64eff4..265c636 160000 --- a/hw/super6502_fpga/src/sim/sub/verilog-sd-emulator +++ b/hw/super6502_fpga/src/sim/sub/verilog-sd-emulator @@ -1 +1 @@ -Subproject commit c64eff4f3658ed1545c6f6942979c83c4c42493b +Subproject commit 265c636c86076662e1b6405dd47a71a6077d51d0 diff --git a/hw/super6502_fpga/src/sub/rtl-common b/hw/super6502_fpga/src/sub/rtl-common index 1417722..bdf655b 160000 --- a/hw/super6502_fpga/src/sub/rtl-common +++ b/hw/super6502_fpga/src/sub/rtl-common @@ -1 +1 @@ -Subproject commit 14177224f6726b67ff5743a3ae54d190be607826 +Subproject commit bdf655b77bfaddc832b1bdf748cb516b91446a48 From 25f51deaa7382326481af6eb99bdf5721933e11f Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sun, 17 Mar 2024 22:26:42 -0700 Subject: [PATCH 21/21] Synthesize sd card dma --- hw/super6502_fpga/sources.list | 3 +- hw/super6502_fpga/src/rtl/super_6502_fpga.sv | 56 ++++-- hw/super6502_fpga/src/sub/rtl-common | 2 +- hw/super6502_fpga/src/sub/sd_controller | 2 +- hw/super6502_fpga/super6502_fpga.xml | 174 +++++++++---------- sw/test_code/sd_controller_test/main.s | 19 ++ 6 files changed, 148 insertions(+), 108 deletions(-) diff --git a/hw/super6502_fpga/sources.list b/hw/super6502_fpga/sources.list index 7c75831..0ef340c 100644 --- a/hw/super6502_fpga/sources.list +++ b/hw/super6502_fpga/sources.list @@ -20,4 +20,5 @@ src/sub/sd_controller/src/crc16.sv src/sub/sd_controller/src/sd_command.sv src/sub/sd_controller/src/sd_control.sv src/sub/sd_controller/src/sd_controller_top.sv -src/sub/sd_controller/src/sd_data.sv \ No newline at end of file +src/sub/sd_controller/src/sd_data.sv +src/sub/sd_controller/src/sd_dma.sv \ No newline at end of file diff --git a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv index 93ed8e4..a1fae5c 100644 --- a/hw/super6502_fpga/src/rtl/super_6502_fpga.sv +++ b/hw/super6502_fpga/src/rtl/super_6502_fpga.sv @@ -236,29 +236,29 @@ cpu_wrapper u_cpu_wrapper_0( axi_crossbar #( - .N_INITIATORS(1), + .N_INITIATORS(2), .N_TARGETS(4) ) u_crossbar ( .clk(i_sysclk), .rst(~master_reset), - .ini_araddr ({cpu0_ARADDR }), - .ini_arvalid ({cpu0_ARVALID }), - .ini_arready ({cpu0_ARREADY }), - .ini_rdata ({cpu0_RDATA }), - .ini_rresp ({cpu0_RRESP }), - .ini_rvalid ({cpu0_RVALID }), - .ini_rready ({cpu0_RREADY }), - .ini_awaddr ({cpu0_AWADDR }), - .ini_awready ({cpu0_AWREADY }), - .ini_awvalid ({cpu0_AWVALID }), - .ini_wvalid ({cpu0_WVALID }), - .ini_wready ({cpu0_WREADY }), - .ini_wdata ({cpu0_WDATA }), - .ini_wstrb ({cpu0_WSTRB }), - .ini_bresp ({cpu0_BRESP }), - .ini_bvalid ({cpu0_BVALID }), - .ini_bready ({cpu0_BREADY }), + .ini_araddr ({cpu0_ARADDR, sd_controller_dma_ARADDR }), + .ini_arvalid ({cpu0_ARVALID, sd_controller_dma_ARVALID }), + .ini_arready ({cpu0_ARREADY, sd_controller_dma_ARREADY }), + .ini_rdata ({cpu0_RDATA, sd_controller_dma_RDATA }), + .ini_rresp ({cpu0_RRESP, sd_controller_dma_RRESP }), + .ini_rvalid ({cpu0_RVALID, sd_controller_dma_RVALID }), + .ini_rready ({cpu0_RREADY, sd_controller_dma_RREADY }), + .ini_awaddr ({cpu0_AWADDR, sd_controller_dma_AWADDR }), + .ini_awready ({cpu0_AWREADY, sd_controller_dma_AWREADY }), + .ini_awvalid ({cpu0_AWVALID, sd_controller_dma_AWVALID }), + .ini_wvalid ({cpu0_WVALID, sd_controller_dma_WVALID }), + .ini_wready ({cpu0_WREADY, sd_controller_dma_WREADY }), + .ini_wdata ({cpu0_WDATA, sd_controller_dma_WDATA }), + .ini_wstrb ({cpu0_WSTRB, sd_controller_dma_WSTRB }), + .ini_bresp ({cpu0_BRESP, sd_controller_dma_BRESP }), + .ini_bvalid ({cpu0_BVALID, sd_controller_dma_BVALID }), + .ini_bready ({cpu0_BREADY, sd_controller_dma_BREADY }), .tgt_araddr ({ram_araddr, rom_araddr, sdram_ARADDR, sd_controller_csr_ARADDR }), .tgt_arvalid ({ram_arvalid, rom_arvalid, sdram_ARVALID, sd_controller_csr_ARVALID }), .tgt_arready ({ram_arready, rom_arready, sdram_ARREADY, sd_controller_csr_ARREADY }), @@ -479,6 +479,26 @@ sd_controller_top u_sd_controller ( .s_apb_prdata(sd_controller_apb_prdata), .s_apb_pslverr(sd_controller_apb_pslverr), + .o_AWVALID (sd_controller_dma_AWVALID), + .i_AWREADY (sd_controller_dma_AWREADY), + .o_AWADDR (sd_controller_dma_AWADDR), + .o_WVALID (sd_controller_dma_WVALID), + .i_WREADY (sd_controller_dma_WREADY), + .o_WDATA (sd_controller_dma_WDATA), + .o_WSTRB (sd_controller_dma_WSTRB), + .i_BVALID (sd_controller_dma_BVALID), + .o_BREADY (sd_controller_dma_BREADY), + .i_BRESP (sd_controller_dma_BRESP), + .o_ARVALID (sd_controller_dma_ARVALID), + .i_ARREADY (sd_controller_dma_ARREADY), + .o_ARADDR (sd_controller_dma_ARADDR), + .i_RVALID (sd_controller_dma_RVALID), + .o_RREADY (sd_controller_dma_RREADY), + .i_RDATA (sd_controller_dma_RDATA), + .i_RRESP (sd_controller_dma_RRESP), + + + .i_sd_cmd(i_sd_cmd), .o_sd_cmd(o_sd_cmd), .o_sd_cmd_oe(o_sd_cmd_oe), diff --git a/hw/super6502_fpga/src/sub/rtl-common b/hw/super6502_fpga/src/sub/rtl-common index bdf655b..401042b 160000 --- a/hw/super6502_fpga/src/sub/rtl-common +++ b/hw/super6502_fpga/src/sub/rtl-common @@ -1 +1 @@ -Subproject commit bdf655b77bfaddc832b1bdf748cb516b91446a48 +Subproject commit 401042bb0ff9db0f44dab9cb6e08c71058a1bcb1 diff --git a/hw/super6502_fpga/src/sub/sd_controller b/hw/super6502_fpga/src/sub/sd_controller index 52665b1..a16ffb4 160000 --- a/hw/super6502_fpga/src/sub/sd_controller +++ b/hw/super6502_fpga/src/sub/sd_controller @@ -1 +1 @@ -Subproject commit 52665b1b897ef77b79caf687c9dbfda4f62110a5 +Subproject commit a16ffb427c6ac8857fd14b6fb9fe1614399b3cbc diff --git a/hw/super6502_fpga/super6502_fpga.xml b/hw/super6502_fpga/super6502_fpga.xml index 88d787d..cb3545b 100644 --- a/hw/super6502_fpga/super6502_fpga.xml +++ b/hw/super6502_fpga/super6502_fpga.xml @@ -1,105 +1,105 @@ - - + - - - + + + - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + - - + + - - + + - + - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - + + + + + + + - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + - - - + + + - + \ No newline at end of file diff --git a/sw/test_code/sd_controller_test/main.s b/sw/test_code/sd_controller_test/main.s index 786df0c..8576a2a 100644 --- a/sw/test_code/sd_controller_test/main.s +++ b/sw/test_code/sd_controller_test/main.s @@ -11,6 +11,9 @@ SD_ARG = SD_CONTROLLER + $4 SD_RESP = SD_CONTROLLER + $10 CLK_DIV = $20 +SD_DMA_BASE = SD_CONTROLLER + $28 +SD_DMA_STAT_CTRL = SD_CONTROLLER + $2C + .zeropage rca: .res 4 @@ -107,6 +110,22 @@ card_ready: lda #17 sta SD_CONTROLLER + lda #$10 + sta SD_DMA_BASE + 1 + lda #1 + sta SD_DMA_STAT_CTRL + +@poll: lda SD_DMA_STAT_CTRL+2 + cmp #$1 + bne @poll + stz SD_DMA_STAT_CTRL + + lda $1000 + lda $1001 + lda $1002 + lda $1003 + + @end: bra @end delay: