diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index eee110b..e34f157 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -162,4 +162,16 @@ rtc_code sim:
     - cd hw/efinix_fpga/simulation
     - make clean
     - TEST_PROGRAM_NAME=rtc_test make rtc_code_tb
-    - ./rtc_code_tb
\ No newline at end of file
+    - ./rtc_code_tb
+
+devices_setup_code sim:
+  tags:
+    - linux
+    - iverilog
+  stage: simulate
+  script:
+    - source init_env.sh
+    - cd hw/efinix_fpga/simulation
+    - make clean
+    - TEST_PROGRAM_NAME=devices_setup_test make devices_setup_code_tb  
+    - ./devices_setup_code_tb
\ No newline at end of file
diff --git a/hw/efinix_fpga/simulation/tbs/devices_setup_code_tb.sv b/hw/efinix_fpga/simulation/tbs/devices_setup_code_tb.sv
index da7306f..bceafe1 100644
--- a/hw/efinix_fpga/simulation/tbs/devices_setup_code_tb.sv
+++ b/hw/efinix_fpga/simulation/tbs/devices_setup_code_tb.sv
@@ -20,4 +20,8 @@ always begin
     # 1;
 end
 
+always @(u_sim_top.u_dut.u_rtc.r_output) begin
+    $display("counter: %d", u_sim_top.u_dut.u_rtc.r_output);
+end
+
 endmodule
\ No newline at end of file
diff --git a/sw/test_code/devices_setup_test/main.s b/sw/test_code/devices_setup_test/main.s
index 60528df..a380d19 100644
--- a/sw/test_code/devices_setup_test/main.s
+++ b/sw/test_code/devices_setup_test/main.s
@@ -34,4 +34,6 @@ _init:
     lda #$0
     jsr _enable_irq
 
+    cli
+
 @end:   bra @end
\ No newline at end of file