From 335f877d66704064278c86366064486da0623677 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Thu, 14 Mar 2024 08:17:05 -0700 Subject: [PATCH] Run simulation with verilog sd emulator This also slowed the cpu clock down, we should speed it up again --- hw/super6502_fpga/src/sim/hvl/sim_top.sv | 2 +- hw/super6502_fpga/src/sim/sources.list | 3 +- .../src/sim/sub/verilog-sd-emulator | 2 +- .../src/sub/cpu_wrapper/cpu_wrapper.sv | 2 +- hw/super6502_fpga/src/sub/rtl-common | 2 +- sw/test_code/sd_controller_test/main.s | 66 +++++++------------ 6 files changed, 30 insertions(+), 47 deletions(-) diff --git a/hw/super6502_fpga/src/sim/hvl/sim_top.sv b/hw/super6502_fpga/src/sim/hvl/sim_top.sv index 1eca534..e5da831 100644 --- a/hw/super6502_fpga/src/sim/hvl/sim_top.sv +++ b/hw/super6502_fpga/src/sim/hvl/sim_top.sv @@ -39,7 +39,7 @@ initial begin clk_cpu <= '1; forever begin // #62.5 clk_cpu <= ~clk_cpu; - #250 clk_cpu <= ~clk_cpu; + #500 clk_cpu <= ~clk_cpu; end end diff --git a/hw/super6502_fpga/src/sim/sources.list b/hw/super6502_fpga/src/sim/sources.list index 916dd74..ecb3cfb 100644 --- a/hw/super6502_fpga/src/sim/sources.list +++ b/hw/super6502_fpga/src/sim/sources.list @@ -3,4 +3,5 @@ sub/verilog-6502/ALU.v sub/verilog-6502/cpu_65c02.v sub/sim_sdram/generic_sdr.v sub/verilog-sd-emulator/src/sd_card_command.sv -sub/verilog-sd-emulator/src/sd_card_emu.sv \ No newline at end of file +sub/verilog-sd-emulator/src/sd_card_emu.sv +sub/verilog-sd-emulator/src/sd_card_state_controller.sv \ No newline at end of file diff --git a/hw/super6502_fpga/src/sim/sub/verilog-sd-emulator b/hw/super6502_fpga/src/sim/sub/verilog-sd-emulator index 35c74ed..5413066 160000 --- a/hw/super6502_fpga/src/sim/sub/verilog-sd-emulator +++ b/hw/super6502_fpga/src/sim/sub/verilog-sd-emulator @@ -1 +1 @@ -Subproject commit 35c74ed8d78d9378dcf6634507ce958064b4c8e2 +Subproject commit 5413066bbbcba0ddaf8428898f35efb516f7673e diff --git a/hw/super6502_fpga/src/sub/cpu_wrapper/cpu_wrapper.sv b/hw/super6502_fpga/src/sub/cpu_wrapper/cpu_wrapper.sv index b0a20fd..51958e5 100644 --- a/hw/super6502_fpga/src/sub/cpu_wrapper/cpu_wrapper.sv +++ b/hw/super6502_fpga/src/sub/cpu_wrapper/cpu_wrapper.sv @@ -207,7 +207,7 @@ always @(posedge i_clk_100 or posedge i_rst) begin end end -localparam MAX_DELAY = 4; +localparam MAX_DELAY = 8; logic [7:0] cycle_counter; logic too_late; diff --git a/hw/super6502_fpga/src/sub/rtl-common b/hw/super6502_fpga/src/sub/rtl-common index bb214bc..28da839 160000 --- a/hw/super6502_fpga/src/sub/rtl-common +++ b/hw/super6502_fpga/src/sub/rtl-common @@ -1 +1 @@ -Subproject commit bb214bc79ee665325adb423472a13dbeec4431ed +Subproject commit 28da839bf6ef4c642f23678143bb8607e93407df diff --git a/sw/test_code/sd_controller_test/main.s b/sw/test_code/sd_controller_test/main.s index 7b26964..786df0c 100644 --- a/sw/test_code/sd_controller_test/main.s +++ b/sw/test_code/sd_controller_test/main.s @@ -20,6 +20,9 @@ _nmi_int: _irq_int: _init: + ldx #$ff + txs + lda #$00 sta SD_CONTROLLER @@ -32,21 +35,21 @@ _init: sta SD_ARG+3 lda #$08 sta SD_CONTROLLER - nop - nop - nop + jsr delay lda #55 sta SD_CONTROLLER + jsr delay lda #41 sta SD_CONTROLLER - nop - nop - nop + jsr delay @acmd41: lda #55 sta SD_CONTROLLER + + jsr delay + lda #$80 sta SD_ARG+1 lda #$ff @@ -56,11 +59,7 @@ _init: lda #41 sta SD_CONTROLLER - nop - nop - nop - nop - nop + jsr delay lda SD_RESP+3 bmi card_ready @@ -76,30 +75,12 @@ card_ready: lda #2 sta SD_CONTROLLER - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop + jsr delay lda #3 sta SD_CONTROLLER - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop + jsr delay lda SD_RESP sta rca @@ -121,18 +102,19 @@ card_ready: lda #7 sta SD_CONTROLLER - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop + jsr delay lda #17 sta SD_CONTROLLER -@end: bra @end \ No newline at end of file +@end: bra @end + +delay: + nop + nop + nop + nop + nop + nop + nop + rts \ No newline at end of file