Run simulation with verilog sd emulator

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This also slowed the cpu clock down, we should speed it up again

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Byron Lathi

2024-03-14 08:17:05 -07:00

parent 24a7001aee

commit 335f877d66

6 changed files with 30 additions and 47 deletions

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hw/super6502_fpga/src/sim/sub/verilog-sd-emulator

Submodule hw/super6502_fpga/src/sim/sub/verilog-sd-emulator updated: 35c74ed8d7...5413066bbb