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Fix synthesis issue

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This commit is contained in:
Byron Lathi
2023-10-15 13:52:55 -07:00
parent e0e20d7fb4
commit 362c9f140f
2 changed files with 93 additions and 86 deletions
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10
hw/efinix_fpga/src/sdram_adapter.sv
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@@ -86,6 +86,7 @@ logic [31:0] r_write_data;
logic [1:0] counter, next_counter;
logic [7:0] o_data_next;
logic r_wait;
logic _r_wait;
@@ -123,8 +124,7 @@ always @(posedge i_sysclk or posedge i_arst) begin
r_dm <= w_dm;
end
if (w_data_valid)
o_data <= _data;
o_data <= o_data_next;
end
//because of timing issues, We really need to trigger
@@ -168,6 +168,12 @@ always_comb begin
w_data_valid = '0;
_data = 0;
if (w_data_valid) begin
o_data_next = _data;
end else begin
o_data_next = o_data;
end
unique case (state)
WAIT: begin
if (i_cs & i_cpuclk)

3
hw/efinix_fpga/super6502.xml
View File

@@ -1,4 +1,5 @@
<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502" description="" last_change_date="Thu Sep 28 2023 09:38:33 PM" location="/home/byron/ServerProjects/super6502/hw/efinix_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502" description="" last_change_date="Sun October 15 2023 13:52:14" location="/home/byron/ServerProjects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion"/>
<efx:device name="T20F256"/>