From 366c6c9b6e99e53aae1a0fd72e8e84b21a628013 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Tue, 20 Dec 2022 17:29:15 -0500
Subject: [PATCH] Remove gitlab ci

---
 .gitlab-ci.yml | 107 -------------------------------------------------
 1 file changed, 107 deletions(-)
 delete mode 100644 .gitlab-ci.yml

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
deleted file mode 100644
index 0fec3bb..0000000
--- a/.gitlab-ci.yml
+++ /dev/null
@@ -1,107 +0,0 @@
-default:
-  tags:
-    - docker
-
-variables:
-  GIT_SUBMODULE_STRATEGY: recursive
-
-stages:
-  - build_toolchain
-  - build_sw
-  - build_hw
-  - test
-
-build-cc65:
-  stage: build_toolchain
-  image: gcc
-  script:
-   - cd sw
-   - make toolchain
-  artifacts:
-    paths:
-      - sw/cc65/bin
-      - sw/cc65/lib
-
-build-kernel:
-  stage: build_sw
-  image: gcc
-  script:
-    - cd sw/kernel
-    - make
-
-build-bootloader:
-  stage: build_sw
-  image: gcc
-  script:
-    - cd sw/bootloader
-    - make
-  artifacts:
-    paths:
-      - sw/bootloader/bootloader.hex
-    expire_in: 1 week
-
-
-
-build-fpga:
-  rules:
-    - when: manual
-  stage: build_hw
-  dependencies:
-    - build-bootloader
-  image: bslathi19/modelsim_18.1:lite
-  script:
-    - cd hw/fpga/
-    - qsys-generate /builds/bslathi19/super6502/hw/fpga/sdram_platform.qsys --synthesis=VERILOG --output-directory=/builds/bslathi19/super6502/hw/fpga/sdram_platform --family="MAX 10" --part=10M50DAF484C7G
-    - quartus_map super6502 -c super6502
-
-test_addr_decode:
-    stage: test
-    rules:
-    - when: manual
-    image: bslathi19/modelsim_18.1:lite
-    script:
-      - cd hw/fpga/simulation/modelsim/
-      - vsim -do "do cs_testbench.do"
-
-test_bb_spi:
-    stage: test
-    rules:
-    - when: manual
-    image: bslathi19/modelsim_18.1:lite
-    script:
-      - cd hw/fpga/simulation/modelsim/
-      - vsim -do "do bb_spi_testbench.do"
-
-test-sw:
-  stage: test
-  image: gcc
-  script:
-    - cd sw/kernel
-    - make test
-
-test_mm:
-    stage: test
-    rules:
-    - when: manual
-    image: bslathi19/modelsim_18.1:lite
-    script:
-      - cd hw/fpga/simulation/modelsim/
-      - vsim -do "do mm_testbench.do"
-
-test_crc7:
-    stage: test
-    rules:
-    - when: manual
-    image: bslathi19/modelsim_18.1:lite
-    script:
-      - cd hw/fpga/simulation/modelsim/
-      - vsim -do "do crc7_testbench.do"
-
-test_sd_cmd:
-    stage: test
-    rules:
-    - when: manual
-    image: bslathi19/modelsim_18.1:lite
-    script:
-      - cd hw/fpga/simulation/modelsim/
-      - vsim -do "sd_cmd_testbench.do"