diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index f66e279..c9d0041 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -59,7 +59,7 @@ build sim:
   script:  
     - source init_env.sh
     - cd hw/efinix_fpga/simulation
-    - make
+    - make sim_top
   dependencies:
     - build toolchain
 
@@ -93,6 +93,6 @@ run sim:
   script:
     - source init_env.sh
     - cd hw/efinix_fpga/simulation
-    - vvp sim_top
+    - make sim
   dependencies:
     - build sim
diff --git a/hw/efinix_fpga/init_hex.mem b/hw/efinix_fpga/init_hex.mem
index 296024a..2b05a54 100644
--- a/hw/efinix_fpga/init_hex.mem
+++ b/hw/efinix_fpga/init_hex.mem
@@ -1,9 +1,9 @@
 @00000000
 00 80 4C 00 00 8D 13 92 8E 14 92 8D 1A 92 8E 1B
 92 88 B9 FF FF 8D 24 92 88 B9 FF FF 8D 23 92 8C
-26 92 20 FF FF A0 FF D0 E8 60 00 00 CC FD 00 00
-00 00 A2 FF 9A D8 A9 00 85 04 A9 DF 85 05 20 44
-FE 20 B9 FA 20 52 F0 58 20 69 F2 6C FC FF 20 AD
+26 92 20 FF FF A0 FF D0 E8 60 00 00 4C FD 00 00
+00 00 A2 FF 9A D8 A9 00 85 04 A9 DF 85 05 20 C4
+FD 20 39 FA 20 52 F0 58 20 69 F2 6C FC FF 20 2D
 FA 00 A0 00 F0 07 A9 52 A2 F0 4C 05 92 60 AD FF
 EF A2 00 60 8D FF EF 60 20 4F F2 C9 0A D0 05 A9
 0D 20 4F F2 60 DA 5A A8 B2 04 AA A9 1B 20 4F F2
@@ -13,19 +13,19 @@ A9 63 20 4F F2 68 60 40 DA BA 48 E8 E8 BD 00 01
 29 10 D0 06 68 FA 20 68 F2 40 68 FA 7C BF F0 C5
 F0 C9 F0 CA F0 20 9A F0 40 40 20 68 F0 40 48 A0
 04 B1 04 09 40 20 3F F2 88 B1 04 20 3F F2 88 10
-F8 68 09 01 20 3F F2 20 A9 FB 60 A2 08 A9 FF 20
+F8 68 09 01 20 3F F2 20 29 FB 60 A2 08 A9 FF 20
 3F F2 C9 FF D0 03 CA D0 F4 60 85 0C 86 0D 20 EB
-F0 92 0C A9 FF 20 3F F2 A0 01 91 0C 20 96 FB 60
-AA 20 20 FD A9 FF 20 3F F2 92 0C E6 0C D0 02 E6
+F0 92 0C A9 FF 20 3F F2 A0 01 91 0C 20 16 FB 60
+AA 20 A0 FC A9 FF 20 3F F2 92 0C E6 0C D0 02 E6
 0D CA D0 F0 60 85 0C 86 0D 20 EB F0 C9 02 B0 12
-E6 0C D0 02 E6 0C A5 0C A6 0D 20 4D FD A9 04 20
+E6 0C D0 02 E6 0C A5 0C A6 0D 20 CD FC A9 04 20
 10 F1 60 48 A9 FF 20 3F F2 A9 00 20 33 F2 A9 FF
 20 3F F2 68 20 CE F0 20 EB F0 A8 A9 FF 20 3F F2
 A9 00 20 39 F2 A9 FF 20 3F F2 98 A2 00 60 A9 00
 20 39 F2 20 8B F1 A9 FF 20 3F F2 A9 00 20 39 F2
 A2 50 A9 FF 20 3F F2 CA D0 F8 60 A2 01 A9 C8 3A
-D0 FD CA D0 F8 60 85 0E 86 0F A9 FF 92 0E 20 20
-FD A5 04 85 10 A5 05 85 11 20 51 FB A0 00 B1 10
+D0 FD CA D0 F8 60 85 0E 86 0F A9 FF 92 0E 20 A0
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 91 04 C8 B1 10 91 04 C8 B1 10 91 04 C8 B1 10 91
 04 A9 FF 20 3F F2 A9 00 20 33 F2 A9 FF 20 3F F2
 A9 11 A0 04 91 04 A9 00 20 CE F0 20 EB F0 C9 FF
@@ -37,136 +37,128 @@ EB A9 FF 20 3F F2 A9 FF 20 3F F2 A5 15 92 0E A5
 F2 68 60 A9 01 8D DB EF 60 9C DB EF 60 A9 00 8D
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-B1 04 C9 FE 20 BE FC F0 03 4C E5 F2 A2 00 A9 00
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 00 D0 06 AA D0 03 A9 01 60 A2 00 8A 60 A0 00 F0
@@ -175,58 +167,58 @@ D0 03 20 85 F7 20 90 F7 AD 46 92 F0 03 20 85 F7
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+4A 4A 18 29 0F AA BD 50 FE A2 00 60 38 A9 00 AA
 60 A4 04 D0 02 C6 05 C6 04 60 A5 04 38 E9 02 85
 04 90 01 60 C6 05 60 A5 04 38 E9 04 85 04 90 01
 60 C6 05 60 A5 04 38 E9 06 85 04 90 01 60 C6 05
 60 A5 04 38 E9 07 85 04 90 01 60 C6 05 60 A0 01
 B1 04 AA 88 B1 04 E6 04 F0 05 E6 04 F0 03 60 E6
-04 E6 05 60 A0 03 4C 85 FA A0 05 4C 85 FA A0 08
-4C 85 FA 85 0C 86 0D A2 00 B1 0C 60 A0 01 B1 04
+04 E6 05 60 A0 03 4C 05 FA A0 05 4C 05 FA A0 08
+4C 05 FA 85 0C 86 0D A2 00 B1 0C 60 A0 01 B1 04
 AA 88 B1 04 60 A0 03 B1 04 85 07 88 B1 04 85 06
 88 B1 04 AA 88 B1 04 60 A2 00 18 65 04 48 8A 65
 05 AA 68 60 18 49 FF 69 01 48 8A 49 FF 69 00 AA
 A5 06 49 FF 69 00 85 06 A5 07 49 FF 69 00 85 07
-68 60 A9 00 AA A0 00 84 06 84 07 48 20 67 FB A0
+68 60 A9 00 AA A0 00 84 06 84 07 48 20 E7 FA A0
 03 A5 07 91 04 88 A5 06 91 04 88 8A 91 04 68 88
-91 04 60 85 14 20 8E FB 85 0E 86 0F 85 10 86 11
-20 20 FD 20 8E FB 85 06 86 07 60 20 23 FC A6 07
+91 04 60 85 14 20 0E FB 85 0E 86 0F 85 10 86 11
+20 A0 FC 20 0E FB 85 06 86 07 60 20 A3 FB A6 07
 A4 14 C0 0A D0 39 A5 06 05 0D 05 0C D0 11 E0 80
-D0 0D A0 0B B9 C4 FE 91 0E 88 10 F8 4C B3 FC 8A
+D0 0D A0 0B B9 44 FE 91 0E 88 10 F8 4C 33 FC 8A
 10 1D A9 2D A0 00 91 0E E6 0E D0 02 E6 0F A5 0C
-A6 0D 20 E4 FB 85 0C 86 0D 4C 7F FC 20 23 FC A9
+A6 0D 20 64 FB 85 0C 86 0D 4C FF FB 20 A3 FB A9
 00 48 A0 20 A9 00 06 0C 26 0D 26 06 26 07 2A C5
-14 90 04 E5 14 E6 0C 88 D0 EC A8 B9 B4 FE 48 A5
+14 90 04 E5 14 E6 0C 88 D0 EC A8 B9 34 FE 48 A5
 0C 05 0D 05 06 05 07 D0 D9 A0 00 68 91 0E F0 03
 C8 D0 F8 A5 10 A6 11 60 D0 06 A2 00 8A 60 D0 FA
 A2 00 A9 01 60 F0 F9 30 F7 A2 00 8A 60 F0 02 10
 EF A2 00 8A 60 F0 E9 90 E7 A2 00 8A 60 F0 DB A2
-00 8A 2A 60 20 0D FD A6 11 F0 13 B1 0C 91 0E C8
+00 8A 2A 60 20 8D FC A6 11 F0 13 B1 0C 91 0E C8
 B1 0C 91 0E C8 D0 F4 E6 0D E6 0F CA D0 ED A6 10
-F0 08 B1 0C 91 0E C8 CA D0 F8 4C 8E FB 85 10 86
-11 20 20 FD C8 B1 04 AA 86 0F 88 B1 04 85 0E 60
-A0 01 B1 04 85 0D 88 B1 04 85 0C 4C 96 FB A9 01
-4C 4B FD A0 00 B1 04 A4 04 F0 07 C6 04 A0 00 91
+F0 08 B1 0C 91 0E C8 CA D0 F8 4C 0E FB 85 10 86
+11 20 A0 FC C8 B1 04 AA 86 0F 88 B1 04 85 0E 60
+A0 01 B1 04 85 0D 88 B1 04 85 0C 4C 16 FB A9 01
+4C CB FC A0 00 B1 04 A4 04 F0 07 C6 04 A0 00 91
 04 60 C6 05 C6 04 91 04 60 A9 00 A2 00 48 A5 04
 38 E9 02 85 04 B0 02 C6 05 A0 01 8A 91 04 68 88
 91 04 60 A0 00 91 04 C8 48 8A 91 04 68 60 85 0E
-86 0F 20 20 FD B1 0C D1 0E D0 0C AA F0 10 C8 D0
+86 0F 20 A0 FC B1 0C D1 0E D0 0C AA F0 10 C8 D0
 F4 E6 0D E6 0F D0 EE B0 03 A2 FF 60 A2 01 60 85
 0E 86 0F A2 00 A0 00 B1 0E F0 08 C8 D0 F9 E6 0F
 E8 D0 F4 98 60 85 0C 86 0D 85 0E 86 0F A0 00 B1
-0C F0 14 20 37 FB 29 02 F0 06 B1 0C 69 20 91 0C
-C8 D0 EC E6 0D D0 E8 A5 0E A6 0F 60 20 8E FB 85
-0E 86 0F E8 8E 31 92 AA E8 8E 30 92 20 20 FD 20
-8E FB 85 10 86 11 A0 00 84 14 B1 10 18 65 0E 91
+0C F0 14 20 B7 FA 29 02 F0 06 B1 0C 69 20 91 0C
+C8 D0 EC E6 0D D0 E8 A5 0E A6 0F 60 20 0E FB 85
+0E 86 0F E8 8E 31 92 AA E8 8E 30 92 20 A0 FC 20
+0E FB 85 10 86 11 A0 00 84 14 B1 10 18 65 0E 91
 10 C8 B1 10 65 0F 91 10 CE 30 92 F0 11 A4 14 B1
-0C C8 D0 02 E6 0D 84 14 20 68 F0 4C F8 FD CE 31
+0C C8 D0 02 E6 0D 84 14 20 68 F0 4C 78 FD CE 31
 92 D0 EA 60 85 0C 86 0D A9 00 8D 2A 92 8D 2B 92
-A0 01 B1 04 AA 88 B1 04 20 4D FD A0 02 A9 2A 91
-04 C8 A9 92 91 04 A5 0C A6 0D 20 C2 F7 AD 2A 92
+A0 01 B1 04 AA 88 B1 04 20 CD FC A0 02 A9 2A 91
+04 C8 A9 92 91 04 A5 0C A6 0D 20 41 F7 AD 2A 92
 AE 2B 92 60 A9 32 85 0C A9 92 85 0D A9 00 A8 A2
 00 F0 0A 91 0C C8 D0 FB E6 0D CA D0 F6 C0 39 F0
 05 91 0C C8 D0 F7 60 62 61 64 20 74 6F 6B 65 6E
@@ -254,4 +246,12 @@ AE 2B 92 60 A9 32 85 0C A9 92 85 0D A9 00 A8 A2
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 A7 F0 32 F0 A8 F0
diff --git a/hw/efinix_fpga/simulation/Makefile b/hw/efinix_fpga/simulation/Makefile
index ee67cae..e59b38c 100644
--- a/hw/efinix_fpga/simulation/Makefile
+++ b/hw/efinix_fpga/simulation/Makefile
@@ -8,22 +8,41 @@ TEST_PROGRAM_NAME?=loop_test
 TEST_FOLDER?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)
 TEST_PROGRAM?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)/$(TEST_PROGRAM_NAME).hex
 
+SD_IMAGE_PATH?=$(REPO_TOP)/sw/script/fs.fat.hex
 
 #TODO implement something like sources.list
 
 TOP_MODULE=sim_top
 TARGET=sim_top
 INIT_MEM=init_hex.mem
+SD_IMAGE=sd_image.mem
 FLAGS=-DSIM -DRTL_SIM
 
-all: $(INIT_MEM)
+all: sim
+
+.PHONY: sim
+sim: $(TARGET)
+	vvp $(TARGET) -fst
+
+.PHONY: full_sim
+full_sim: $(TARGET) $(SD_IMAGE)
+	vvp $(TARGET) -fst
+
+
+$(TARGET): $(INIT_MEM) $(SRCS)
 	iverilog -g2005-sv $(FLAGS) -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)
 
 $(INIT_MEM):
 	$(MAKE) -C $(TEST_FOLDER)
 	cp $(TEST_PROGRAM) ./init_hex.mem
 
+# The script that makes this file uses relative paths
+$(SD_IMAGE):
+	sh $(REPO_TOP)/sw/script/create_verilog_image.sh
+	cp $(SD_IMAGE_PATH) $(SD_IMAGE)
+
 .PHONY: clean
 clean:
 	rm -rf $(TARGET)
 	rm -rf $(INIT_MEM)
+	rm -rf $(SD_IMAGE)
diff --git a/hw/efinix_fpga/simulation/src/sim_top.sv b/hw/efinix_fpga/simulation/src/sim_top.sv
index 227ae42..4d18031 100644
--- a/hw/efinix_fpga/simulation/src/sim_top.sv
+++ b/hw/efinix_fpga/simulation/src/sim_top.sv
@@ -49,7 +49,7 @@ initial begin
     button_reset <= '0;
     repeat(10) @(r_clk_2);
     button_reset <= '1;
-    repeat(20000) @(r_clk_2);
+    repeat(1000000) @(r_clk_2);
     $finish();
 end
 
@@ -82,6 +82,19 @@ sim_uart u_sim_uart(
     .tx_o(w_dut_uart_rx)
 );
 
+logic w_sd_cs;
+logic w_spi_clk;
+logic w_spi_mosi;
+logic w_spi_miso;
+
+sd_card_emu u_sd_card_emu(
+    .rst(~w_cpu_reset),
+    .clk(w_spi_clk),
+    .cs(w_sd_cs),
+    .mosi(w_spi_mosi),
+    .miso(w_spi_miso)
+);
+
 
 super6502 u_dut(
     .i_sysclk(r_sysclk),
@@ -101,6 +114,11 @@ super6502 u_dut(
     .uart_rx(w_dut_uart_rx),
     .uart_tx(w_dut_uart_tx),
 
+    .sd_cs(w_sd_cs),
+    .spi_clk(w_spi_clk),
+    .spi_mosi(w_spi_mosi),
+    .spi_miso(w_spi_miso),
+
     .o_sdr_CKE(w_sdr_CKE),
     .o_sdr_n_CS(w_sdr_n_CS),
     .o_sdr_n_WE(w_sdr_n_WE),
@@ -152,4 +170,4 @@ generate
     end
 endgenerate
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/hw/efinix_fpga/simulation/src/verilog-sd-emulator b/hw/efinix_fpga/simulation/src/verilog-sd-emulator
index 7fb88c9..390b722 160000
--- a/hw/efinix_fpga/simulation/src/verilog-sd-emulator
+++ b/hw/efinix_fpga/simulation/src/verilog-sd-emulator
@@ -1 +1 @@
-Subproject commit 7fb88c9ee1ca65dd5bfd10b2e0f6331e958abdd7
+Subproject commit 390b7221dbcd176d3875d95f78ef84ccbd2ada1f
diff --git a/sw/.gitignore b/sw/.gitignore
index ec73f2b..5e3b75b 100644
--- a/sw/.gitignore
+++ b/sw/.gitignore
@@ -53,3 +53,6 @@ modules.order
 Module.symvers
 Mkfile.old
 dkms.conf
+
+# Filesystem Images
+*.fat
diff --git a/sw/bios/Makefile b/sw/bios/Makefile
index 3d489a2..f35b1a5 100644
--- a/sw/bios/Makefile
+++ b/sw/bios/Makefile
@@ -1,5 +1,5 @@
 CC=../cc65/bin/cl65
-CFLAGS=-T -t none -I. --cpu "65C02"
+CFLAGS=-T -t none -I. --cpu "65C02" -DRTL_SIM
 LDFLAGS=-C link.ld -m $(NAME).map
 
 NAME=bios
diff --git a/sw/bios/devices/sd_card.c b/sw/bios/devices/sd_card.c
index d1c5b47..6be2cc3 100644
--- a/sw/bios/devices/sd_card.c
+++ b/sw/bios/devices/sd_card.c
@@ -25,7 +25,9 @@ uint8_t SD_init()
         }
     }
 
+#ifndef RTL_SIM
     for (i = 0; i < 1000; i++);
+#endif
 
     SD_sendIfCond(res);
     if(res[0] != SD_IN_IDLE_STATE)
@@ -54,13 +56,17 @@ uint8_t SD_init()
             res[0] = SD_sendOpCond();
         }
 
+#ifndef RTL_SIM
         for (i = 0; i < 1000; i++);
+#endif
 
         cmdAttempts++;
     }
     while(res[0] != SD_READY);
 
+#ifndef RTL_SIM
     for (i = 0; i < 1000; i++);
+#endif
 
     SD_readOCR(res);
 
diff --git a/sw/script/create_verilog_image.sh b/sw/script/create_verilog_image.sh
new file mode 100644
index 0000000..83ac7cf
--- /dev/null
+++ b/sw/script/create_verilog_image.sh
@@ -0,0 +1,42 @@
+
+#!/bin/bash
+
+BOOTLOADER=$REPO_TOP/sw/bios/bootloader.bin
+FILE=fs.fat
+
+TMPMOUNT=/tmp/lo
+FSDIR=$REPO_TOP/sw/fsdir
+
+V=-v
+
+# Smallest number of blocks where mkfs doesn't complain
+BLOCKS=33296
+
+rm $FILE
+
+echo "$(tput bold setaf 11)Creating Filesystem$(tput sgr 0)"
+mkfs.vfat $V -I -F32 -C $FILE -n SUPER6502 $BLOCKS
+echo
+
+echo "$(tput bold setaf 11)Modifying Boot Sector$(tput sgr 0)"
+dd if=$BOOTLOADER of=$FILE bs=1 conv=notrunc count=11 $STATUS
+dd if=$BOOTLOADER of=$FILE bs=1 conv=notrunc count=380 seek=71 skip=71 $STATUS
+
+echo "$(tput bold setaf 11)Mounting Device$(tput sgr 0)"
+mkdir $V -p $TMPMOUNT
+sudo mount $FILE $TMPMOUNT
+echo
+
+echo "$(tput bold setaf 11)Copying Files$(tput sgr 0)"
+sudo cp $V -r $FSDIR/* $TMPMOUNT
+echo
+
+echo "$(tput bold setaf 11)Unmounting Device$(tput sgr 0)"
+sudo umount $V $FILE
+rmdir $V $TMPMOUNT
+echo
+
+# Really I want the data width to be 512 bytes long, not 16...
+echo "$(tput bold setaf 11)Converting Image to Verilog$(tput sgr 0)"
+objcopy --input-target=binary --output-target=verilog --verilog-data-width=1 $FILE $FILE.hex
+echo "$(tput bold setaf 10)Done!$(tput sgr 0)"
diff --git a/sw/script/format_disk.sh b/sw/script/format_disk.sh
index af66e59..8c77237 100644
--- a/sw/script/format_disk.sh
+++ b/sw/script/format_disk.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 
-BOOTLOADER=../bios/bootloader.bin
+BOOTLOADER=$REPO_TOP/sw/bios/bootloader.bin
 DEVICE=/dev/mmcblk0
 TMPBOOTSECT=/tmp/bootsect
 TMPMOUNT=/tmp/sd