Don't have sd wait in simulation

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need to figure out how to set that RTL_SIM flag only when we are
compiling code for the sim

also bro the sim is like 8000x slower than irl.

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Byron Lathi

2023-09-30 17:40:01 -07:00

parent cc32430f2a

commit 3a211faed7

4 changed files with 215 additions and 213 deletions

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hw/efinix_fpga/simulation/src/verilog-sd-emulator

Submodule hw/efinix_fpga/simulation/src/verilog-sd-emulator updated: a37857045c...2fc0f0737c