From 3a59de2947dc7d275fb8c3ea01065d6a38c5933a Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Thu, 14 Apr 2022 11:19:08 -0500
Subject: [PATCH] Change data count to have proper width (9)

This was probably an off-by-one mistage, with the width set to 10
instead of 9. The width should be 9 since the buffer is 512 bytes.
---
 hw/fpga/sd_controller.sv | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/fpga/sd_controller.sv b/hw/fpga/sd_controller.sv
index b8f864f..c606a31 100644
--- a/hw/fpga/sd_controller.sv
+++ b/hw/fpga/sd_controller.sv
@@ -24,7 +24,7 @@ logic [47:0] rxcmd_buf;
 logic [31:0] rx_val;
 
 logic [7:0] rxdata_buf [512];
-logic [9:0] data_count;
+logic [8:0] data_count;
 
 logic [15:0] data_crc;
 
@@ -89,7 +89,7 @@ always_ff @(posedge clk) begin
     end
 
     if (cs & addr == 4'h5 && sd_clk) begin
-        data_count <= data_count + 9'b1;
+        data_count <= data_count + 8'b1;
     end
 
     if (state.macro == RXCMD) begin
@@ -102,6 +102,7 @@ always_ff @(posedge clk) begin
 
     if (state.macro == RXDCRC && ~sd_clk) begin
         data_crc[4'd15-state.count] <= i_sd_data;
+        data_count <= '0;
     end
 
 end