diff --git a/.gitignore b/.gitignore index f6b5816..ba5b18b 100644 --- a/.gitignore +++ b/.gitignore @@ -1,2 +1,22 @@ .vscode .~lock* + +.user_venv/ + + +# Software build files +*.map +*.list +*.bin +*.o + + +# Efinix Debugger +*.log* +*.vcd +*.gtkw +*debug_profile* + + +*.mem + diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 6a5628b..5a43b0d 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -4,12 +4,12 @@ variables: stages: - build -build hw: +build: stage: build tags: - efinity - linux script: - source init_env.sh - - make hw + - make diff --git a/.gitmodules b/.gitmodules index 07a7976..d5d9d2b 100644 --- a/.gitmodules +++ b/.gitmodules @@ -4,3 +4,6 @@ [submodule "hw/super6502_fpga/src/sub/axi_crossbar"] path = hw/super6502_fpga/src/sub/axi_crossbar url = ../axi_crossbar.git +[submodule "sw/toolchain/cc65"] + path = sw/toolchain/cc65 + url = ../cc65.git diff --git a/Makefile b/Makefile index 7b9cb5d..24d1d56 100644 --- a/Makefile +++ b/Makefile @@ -1,9 +1,33 @@ -all: hw +ROM_TARGET=test_code/loop_test -.PHONY: hw -hw: - $(MAKE) -C hw +INIT_HEX=hw/super6502_fpga/init_hex.mem +HEX=sw/$(ROM_TARGET)/$(notdir $(ROM_TARGET)).bin + + +all: fpga_image + +# FPGA +.PHONY: fpga_image +fpga_image: $(INIT_HEX) + $(MAKE) -C hw/super6502_fpga + + +# SW +.PHONY: toolchain +toolchain: + $(MAKE) -C sw/toolchain/cc65 -j $(shell nproc) + +$(INIT_HEX): toolchain script/generate_rom_image.py $(HEX) + python script/generate_rom_image.py -i $(HEX) -o $@ + +$(HEX): + $(MAKE) -C sw/$(ROM_TARGET) $(notdir $@) .PHONY: clean clean: - $(MAKE) -C hw $@ \ No newline at end of file + $(MAKE) -C hw/super6502_fpga $@ + $(MAKE) -C sw/$(ROM_TARGET) clean + +.PHONY: distclean +distclean: clean + $(MAKE) -C sw/toolchain/cc65 clean diff --git a/doc/hw/super6502.md b/doc/hw/super6502.md new file mode 100644 index 0000000..e69de29 diff --git a/hw/Makefile b/hw/Makefile deleted file mode 100644 index cacf66e..0000000 --- a/hw/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -all: - $(MAKE) -C super6502_fpga - -.PHONY: clean -clean: - $(MAKE) -C super6502_fpga $@ \ No newline at end of file diff --git a/hw/super6502_fpga/init_hex.mem b/hw/super6502_fpga/init_hex.mem deleted file mode 100644 index b6697d2..0000000 --- a/hw/super6502_fpga/init_hex.mem +++ /dev/null @@ -1,65 +0,0 @@ -@00000000 -8d00a9 -200cd02 -801a03d0 -fe80f5 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -ff000000 -ff00ff00 diff --git a/hw/super6502_fpga/super6502_fpga.xml b/hw/super6502_fpga/super6502_fpga.xml index 71190d7..d4cd497 100644 --- a/hw/super6502_fpga/super6502_fpga.xml +++ b/hw/super6502_fpga/super6502_fpga.xml @@ -1,4 +1,4 @@ - + @@ -81,9 +81,4 @@ - - - - - \ No newline at end of file diff --git a/init_env.sh b/init_env.sh index 5870004..5832a54 100644 --- a/init_env.sh +++ b/init_env.sh @@ -8,23 +8,6 @@ export KICAD7_SYMBOL_DIR=$REPO_TOP/hw/kicad_library/symbols export KICAD7_3DMODEL_DIR=$REPO_TOP/hw/kicad_library/3dmodels export KICAD7_FOOTPRINT_DIR=$REPO_TOP/hw/kicad_library/footprints - -# if [ ! -d "$ENV" ]; then -# mkdir -p "$ENV" -# fi - -# if [ ! -f "$ENV/efinity-2023.1.150-rhe-x64.tar.bz2" ]; then -# scp 192.168.50.101:/export/scratch/efinity-2023.1.150-rhe-x64.tar.bz2 "$ENV" -# fi - -# if [ ! -d "$ENV/efinity" ]; then -# pv "$ENV/efinity-2023.1.150-rhe-x64.tar.bz2" | tar xj --directory "$ENV" -# scp 192.168.50.101:/export/scratch/libffi.so.6 "$ENV/efinity/2023.1/lib/" -# fi - -# source "$ENV/efinity/2023.1/bin/setup.sh" -# export PATH=$PATH:"$EFXPT_HOME/bin" - if [ -n "$EFX_SETUP" ]; then source $EFX_SETUP else @@ -32,7 +15,7 @@ else fi -# python -m venv .user_venv --system-site-packages -# . .user_venv/bin/activate +python3 -m venv .user_venv +. .user_venv/bin/activate # pip install -r requirements.txt diff --git a/script/generate_rom_image.py b/script/generate_rom_image.py new file mode 100644 index 0000000..b07c8d4 --- /dev/null +++ b/script/generate_rom_image.py @@ -0,0 +1,40 @@ +import getopt +import sys + +# ROM size in bytes +ROM_SIZE = 2**16 +DATA_WIDTH = 32 + +NUM_ENTRIES = ROM_SIZE // (DATA_WIDTH//8) + +def main(argv): + inputfile = '' + outputfile = '' + opts, args = getopt.getopt(argv,"hi:o:",["ifile=","ofile="]) + for opt, arg in opts: + if opt == '-h': + print ('test.py -i -o ') + sys.exit() + elif opt in ("-i", "--ifile"): + inputfile = arg + elif opt in ("-o", "--ofile"): + outputfile = arg + + with open(outputfile, "w") as init_file, open(inputfile, "rb") as hex_file: + init_file.write("@00000000\n") + + while True: + hex_bytes = hex_file.read(4) + if len(hex_bytes) == 0: + break + + val = int.from_bytes(hex_bytes, byteorder="little") + init_file.write(f"{val:x}\n") + + if len(hex_bytes) < 4: + break + + print("Done!") + +if __name__ == "__main__": + main(sys.argv[1:]) \ No newline at end of file diff --git a/sw/test_code/loop_test/Makefile b/sw/test_code/loop_test/Makefile new file mode 100644 index 0000000..295cadb --- /dev/null +++ b/sw/test_code/loop_test/Makefile @@ -0,0 +1,39 @@ +CC=../../toolchain/cc65/bin/cl65 +LD=../../toolchain/cc65/bin/cl65 +CFLAGS=-T -t none -I. --cpu "65C02" +LDFLAGS=-C link.ld -m $(NAME).map + +NAME=loop_test + +BIN=$(NAME).bin +HEX=$(NAME).hex + +LISTS=lists + +SRCS=$(wildcard *.s) $(wildcard *.c) +SRCS+=$(wildcard **/*.s) $(wildcard **/*.c) +OBJS+=$(patsubst %.s,%.o,$(filter %s,$(SRCS))) +OBJS+=$(patsubst %.c,%.o,$(filter %c,$(SRCS))) + +# Make sure the kernel linked to correct address, no relocation! +all: $(HEX) + +$(HEX): $(BIN) + objcopy --input-target=binary --output-target=verilog $(BIN) $(HEX) + +$(BIN): $(OBJS) + $(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $@ + +%.o: %.c $(LISTS) + $(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@ + +%.o: %.s $(LISTS) + $(CC) $(CFLAGS) -l $(LISTS)/$<.list -c $< -o $@ + +$(LISTS): + mkdir -p $(addprefix $(LISTS)/,$(sort $(dir $(SRCS)))) + +.PHONY: clean +clean: + rm -rf $(OBJS) $(BIN) $(HEX) $(LISTS) $(NAME).map + diff --git a/sw/test_code/loop_test/link.ld b/sw/test_code/loop_test/link.ld new file mode 100644 index 0000000..44fc445 --- /dev/null +++ b/sw/test_code/loop_test/link.ld @@ -0,0 +1,30 @@ +MEMORY +{ + RAM: start = $0000, size = $200; + ROM: start = $FF00, size = $100, file = %O; +} + +SEGMENTS { + ZEROPAGE: load = RAM, type = zp, define = yes; + DATA: load = ROM, type = rw, define = yes; + CODE: load = ROM, type = ro; + RODATA: load = ROM, type = ro; + VECTORS: load = ROM, type = ro, start = $FFFA; +} + +FEATURES { + CONDES: segment = STARTUP, + type = constructor, + label = __CONSTRUCTOR_TABLE__, + count = __CONSTRUCTOR_COUNT__; + CONDES: segment = STARTUP, + type = destructor, + label = __DESTRUCTOR_TABLE__, + count = __DESTRUCTOR_COUNT__; +} + +SYMBOLS { + # Define the stack size for the application + __STACKSIZE__: value = $0200, type = weak; + __STACKSTART__: type = weak, value = $0800; # 2k stack +} diff --git a/sw/test_code/loop_test/main.s b/sw/test_code/loop_test/main.s new file mode 100644 index 0000000..60aebb7 --- /dev/null +++ b/sw/test_code/loop_test/main.s @@ -0,0 +1,26 @@ +.export _init, _nmi_int, _irq_int + +.segment "VECTORS" + +.addr _nmi_int ; NMI vector +.addr _init ; Reset vector +.addr _irq_int ; IRQ/BRK vector + +.zeropage +tmp: .res 1 + +.code + +_nmi_int: +_irq_int: + +_init: + lda #$00 +@start: + sta tmp + cmp tmp + bne @end + ina + bra @start + +@end: bra @end \ No newline at end of file diff --git a/sw/toolchain/cc65 b/sw/toolchain/cc65 new file mode 160000 index 0000000..71b58f7 --- /dev/null +++ b/sw/toolchain/cc65 @@ -0,0 +1 @@ +Subproject commit 71b58f79678db2b0e826bd14ba5b7ff6ee67d70d