Get the FPGA part working

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This changes some of the clocks, fixes a bug in the seven segment stuff.

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This commit is contained in:

Byron Lathi

2022-03-11 22:55:26 -06:00

parent cdf3da9b13

commit 3d9d340520

11 changed files with 64714 additions and 11632 deletions

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hw/fpga/output_files/firsttry.vcd Normal file

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